target-ppc/op_helper.c

   1 /*
   2  *  PPC emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2003 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <math.h>
  21 #include "exec.h"
  22
  23 #define MEMSUFFIX _raw
  24 #include "op_helper_mem.h"
  25 #if !defined(CONFIG_USER_ONLY)
  26 #define MEMSUFFIX _user
  27 #include "op_helper_mem.h"
  28 #define MEMSUFFIX _kernel
  29 #include "op_helper_mem.h"
  30 #endif
  31
  32 /*****************************************************************************/
  33 /* Exceptions processing helpers */
  34 void cpu_loop_exit(void)
  35 {
  36     longjmp(env->jmp_env, 1);
  37 }
  38
  39 void do_raise_exception_err (uint32_t exception, int error_code)
  40 {
  41 #if 0
  42     printf("Raise exception %3x code : %d\n", exception, error_code);
  43 #endif
  44     switch (exception) {
  45     case EXCP_EXTERNAL:
  46     case EXCP_DECR:
  47         printf("DECREMENTER & EXTERNAL exceptions should be hard interrupts !\n");
  48         if (msr_ee == 0)
  49             return;
  50         break;
  51     case EXCP_PROGRAM:
  52         if (error_code == EXCP_FP && msr_fe0 == 0 && msr_fe1 == 0)
  53             return;
  54         break;
  55     default:
  56         break;
  57 }
  58     env->exception_index = exception;
  59     env->error_code = error_code;
  60         cpu_loop_exit();
  61     }
  62
  63 void do_raise_exception (uint32_t exception)
  64 {
  65     do_raise_exception_err(exception, 0);
  66 }
  67
  68 /*****************************************************************************/
  69 /* Helpers for "fat" micro operations */
  70 /* Special registers load and store */
  71 void do_load_cr (void)
  72 {
  73     T0 = (env->crf[0] << 28) |
  74         (env->crf[1] << 24) |
  75         (env->crf[2] << 20) |
  76         (env->crf[3] << 16) |
  77         (env->crf[4] << 12) |
  78         (env->crf[5] << 8) |
  79         (env->crf[6] << 4) |
  80         (env->crf[7] << 0);
  81 }
  82
  83 void do_store_cr (uint32_t mask)
  84 {
  85     int i, sh;
  86
  87     for (i = 0, sh = 7; i < 8; i++, sh --) {
  88         if (mask & (1 << sh))
  89             env->crf[i] = (T0 >> (sh * 4)) & 0xF;
  90     }
  91 }
  92
  93 void do_load_xer (void)
  94 {
  95     T0 = (xer_so << XER_SO) |
  96         (xer_ov << XER_OV) |
  97         (xer_ca << XER_CA) |
  98         (xer_bc << XER_BC);
  99 }
 100
 101 void do_store_xer (void)
 102 {
 103     xer_so = (T0 >> XER_SO) & 0x01;
 104     xer_ov = (T0 >> XER_OV) & 0x01;
 105     xer_ca = (T0 >> XER_CA) & 0x01;
 106     xer_bc = (T0 >> XER_BC) & 0x1f;
 107 }
 108
 109 void do_load_msr (void)
 110 {
 111     T0 = (msr_pow << MSR_POW) |
 112         (msr_ile << MSR_ILE) |
 113         (msr_ee << MSR_EE) |
 114         (msr_pr << MSR_PR) |
 115         (msr_fp << MSR_FP) |
 116         (msr_me << MSR_ME) |
 117         (msr_fe0 << MSR_FE0) |
 118         (msr_se << MSR_SE) |
 119         (msr_be << MSR_BE) |
 120         (msr_fe1 << MSR_FE1) |
 121         (msr_ip << MSR_IP) |
 122         (msr_ir << MSR_IR) |
 123         (msr_dr << MSR_DR) |
 124         (msr_ri << MSR_RI) |
 125         (msr_le << MSR_LE);
 126 }
 127
 128 void do_store_msr (void)
 129 {
 130     if (((T0 >> MSR_IR) & 0x01) != msr_ir ||
 131         ((T0 >> MSR_DR) & 0x01) != msr_dr) {
 132         /* Flush all tlb when changing translation mode or privilege level */
 133         do_tlbia();
 134     }
 135     msr_pow = (T0 >> MSR_POW) & 0x03;
 136     msr_ile = (T0 >> MSR_ILE) & 0x01;
 137     msr_ee = (T0 >> MSR_EE) & 0x01;
 138     msr_pr = (T0 >> MSR_PR) & 0x01;
 139     msr_fp = (T0 >> MSR_FP) & 0x01;
 140     msr_me = (T0 >> MSR_ME) & 0x01;
 141     msr_fe0 = (T0 >> MSR_FE0) & 0x01;
 142     msr_se = (T0 >> MSR_SE) & 0x01;
 143     msr_be = (T0 >> MSR_BE) & 0x01;
 144     msr_fe1 = (T0 >> MSR_FE1) & 0x01;
 145     msr_ip = (T0 >> MSR_IP) & 0x01;
 146     msr_ir = (T0 >> MSR_IR) & 0x01;
 147     msr_dr = (T0 >> MSR_DR) & 0x01;
 148     msr_ri = (T0 >> MSR_RI) & 0x01;
 149     msr_le = (T0 >> MSR_LE) & 0x01;
 150 }
 151
 152 /* shift right arithmetic helper */
 153 void do_sraw (void)
 154 {
 155     int32_t ret;
 156
 157     xer_ca = 0;
 158     if (T1 & 0x20) {
 159         ret = (-1) * (T0 >> 31);
 160         if (ret < 0)
 161             xer_ca = 1;
 162     } else {
 163         ret = (int32_t)T0 >> (T1 & 0x1f);
 164         if (ret < 0 && ((int32_t)T0 & ((1 << T1) - 1)) != 0)
 165             xer_ca = 1;
 166     }
 167     (int32_t)T0 = ret;
 168 }
 169
 170 /* Floating point operations helpers */
 171 void do_load_fpscr (void)
 172 {
 173     /* The 32 MSB of the target fpr are undefined.
 174      * They'll be zero...
 175      */
 176     union {
 177         double d;
 178         struct {
 179             uint32_t u[2];
 180         } s;
 181     } u;
 182     int i;
 183
 184     u.s.u[0] = 0;
 185     u.s.u[1] = 0;
 186     for (i = 0; i < 8; i++)
 187         u.s.u[1] |= env->fpscr[i] << (4 * i);
 188     FT0 = u.d;
 189 }
 190
 191 void do_store_fpscr (uint32_t mask)
 192 {
 193     /*
 194      * We use only the 32 LSB of the incoming fpr
 195      */
 196     union {
 197         double d;
 198         struct {
 199             uint32_t u[2];
 200         } s;
 201     } u;
 202     int i;
 203
 204     u.d = FT0;
 205     if (mask & 0x80)
 206         env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[1] >> 28) & ~0x9);
 207     for (i = 1; i < 7; i++) {
 208         if (mask & (1 << (7 - i)))
 209             env->fpscr[i] = (u.s.u[1] >> (4 * (7 - i))) & 0xF;
 210     }
 211     /* TODO: update FEX & VX */
 212     /* Set rounding mode */
 213     switch (env->fpscr[0] & 0x3) {
 214     case 0:
 215         /* Best approximation (round to nearest) */
 216         fesetround(FE_TONEAREST);
 217         break;
 218     case 1:
 219         /* Smaller magnitude (round toward zero) */
 220         fesetround(FE_TOWARDZERO);
 221         break;
 222     case 2:
 223         /* Round toward +infinite */
 224         fesetround(FE_UPWARD);
 225         break;
 226     case 3:
 227         /* Round toward -infinite */
 228         fesetround(FE_DOWNWARD);
 229         break;
 230     }
 231 }
 232
 233 void do_fctiw (void)
 234 {
 235     union {
 236         double d;
 237         uint64_t i;
 238     } *p = (void *)&FT1;
 239
 240     if (FT0 > (double)0x7FFFFFFF)
 241         p->i = 0x7FFFFFFFULL << 32;
 242     else if (FT0 < -(double)0x80000000)
 243         p->i = 0x80000000ULL << 32;
 244     else
 245         p->i = 0;
 246     p->i |= (uint32_t)FT0;
 247     FT0 = p->d;
 248 }
 249
 250 void do_fctiwz (void)
 251 {
 252     union {
 253         double d;
 254         uint64_t i;
 255     } *p = (void *)&FT1;
 256     int cround = fegetround();
 257
 258     fesetround(FE_TOWARDZERO);
 259     if (FT0 > (double)0x7FFFFFFF)
 260         p->i = 0x7FFFFFFFULL << 32;
 261     else if (FT0 < -(double)0x80000000)
 262         p->i = 0x80000000ULL << 32;
 263     else
 264         p->i = 0;
 265     p->i |= (uint32_t)FT0;
 266     FT0 = p->d;
 267     fesetround(cround);
 268 }
 269
 270 void do_fnmadds (void)
 271 {
 272     FTS0 = -((FTS0 * FTS1) + FTS2);
 273 }
 274
 275 void do_fnmsubs (void)
 276 {
 277     FTS0 = -((FTS0 * FTS1) - FTS2);
 278 }
 279
 280 void do_fsqrt (void)
 281 {
 282     FT0 = sqrt(FT0);
 283 }
 284
 285 void do_fsqrts (void)
 286 {
 287     FT0 = (float)sqrt((float)FT0);
 288 }
 289
 290 void do_fres (void)
 291 {
 292     FT0 = 1.0 / FT0;
 293 }
 294
 295 void do_fsqrte (void)
 296 {
 297     FT0 = 1.0 / sqrt(FT0);
 298 }
 299
 300 void do_fsel (void)
 301 {
 302     if (FT0 >= 0)
 303         FT0 = FT2;
 304     else
 305         FT0 = FT1;
 306 }
 307
 308 void do_fcmpu (void)
 309 {
 310     env->fpscr[4] &= ~0x1;
 311     if (isnan(FT0) || isnan(FT1)) {
 312         T0 = 0x01;
 313         env->fpscr[4] |= 0x1;
 314         env->fpscr[6] |= 0x1;
 315     } else if (FT0 < FT1) {
 316         T0 = 0x08;
 317     } else if (FT0 > FT1) {
 318         T0 = 0x04;
 319     } else {
 320         T0 = 0x02;
 321     }
 322     env->fpscr[3] |= T0;
 323 }
 324
 325 void do_fcmpo (void)
 326 {
 327     env->fpscr[4] &= ~0x1;
 328     if (isnan(FT0) || isnan(FT1)) {
 329         T0 = 0x01;
 330         env->fpscr[4] |= 0x1;
 331         /* I don't know how to test "quiet" nan... */
 332         if (0 /* || ! quiet_nan(...) */) {
 333             env->fpscr[6] |= 0x1;
 334             if (!(env->fpscr[1] & 0x8))
 335                 env->fpscr[4] |= 0x8;
 336         } else {
 337             env->fpscr[4] |= 0x8;
 338         }
 339     } else if (FT0 < FT1) {
 340         T0 = 0x08;
 341     } else if (FT0 > FT1) {
 342         T0 = 0x04;
 343     } else {
 344         T0 = 0x02;
 345     }
 346     env->fpscr[3] |= T0;
 347 }
 348
 349 void do_fabs (void)
 350 {
 351     FT0 = fabsl(FT0);
 352 }
 353
 354 void do_fnabs (void)
 355 {
 356     FT0 = -fabsl(FT0);
 357 }
 358
 359 /* Instruction cache invalidation helper */
 360 #define ICACHE_LINE_SIZE 32
 361
 362 void do_icbi (void)
 363 {
 364     /* Invalidate one cache line */
 365     T0 &= ~(ICACHE_LINE_SIZE - 1);
 366     tb_invalidate_page_range(T0, T0 + ICACHE_LINE_SIZE);
 367 }
 368
 369 /* TLB invalidation helpers */
 370 void do_tlbia (void)
 371 {
 372     tlb_flush(env, 1);
 373 }
 374
 375 void do_tlbie (void)
 376 {
 377     tlb_flush_page(env, T0);
 378 }
 379
 380 /*****************************************************************************/
 381 /* Special helpers for debug */
 382 extern FILE *stdout;
 383
 384 void dump_state (void)
 385 {
 386     cpu_ppc_dump_state(env, stdout, 0);
 387 }
 388
 389 void dump_rfi (void)
 390 {
 391 #if 0
 392     printf("Return from interrupt %d => 0x%08x\n", pos, env->nip);
 393     //    cpu_ppc_dump_state(env, stdout, 0);
 394 #endif
 395 }
 396
 397 void dump_store_sr (int srnum)
 398 {
 399 #if 0
 400     printf("%s: reg=%d 0x%08x\n", __func__, srnum, T0);
 401 #endif
 402 }
 403
 404 static void _dump_store_bat (char ID, int ul, int nr)
 405 {
 406     printf("Set %cBAT%d%c to 0x%08x (0x%08x)\n",
 407            ID, nr, ul == 0 ? 'u' : 'l', T0, env->nip);
 408 }
 409
 410 void dump_store_ibat (int ul, int nr)
 411 {
 412     _dump_store_bat('I', ul, nr);
 413 }
 414
 415 void dump_store_dbat (int ul, int nr)
 416 {
 417     _dump_store_bat('D', ul, nr);
 418 }
 419
 420 void dump_store_tb (int ul)
 421 {
 422     printf("Set TB%c to 0x%08x\n", ul == 0 ? 'L' : 'U', T0);
 423 }
 424
 425 void dump_update_tb(uint32_t param)
 426 {
 427 #if 0
 428     printf("Update TB: 0x%08x + %d => 0x%08x\n", T1, param, T0);
 429 #endif
 430 }
 431