target-ppc/op_helper.c

   1 /*
   2  *  PowerPC emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "exec.h"
  21
  22 #include "op_helper.h"
  23
  24 #define MEMSUFFIX _raw
  25 #include "op_helper.h"
  26 #include "op_helper_mem.h"
  27 #if !defined(CONFIG_USER_ONLY)
  28 #define MEMSUFFIX _user
  29 #include "op_helper.h"
  30 #include "op_helper_mem.h"
  31 #define MEMSUFFIX _kernel
  32 #include "op_helper.h"
  33 #include "op_helper_mem.h"
  34 #endif
  35
  36 //#define DEBUG_OP
  37 //#define DEBUG_EXCEPTIONS
  38 //#define DEBUG_SOFTWARE_TLB
  39 //#define FLUSH_ALL_TLBS
  40
  41 /*****************************************************************************/
  42 /* Exceptions processing helpers */
  43
  44 void do_raise_exception_err (uint32_t exception, int error_code)
  45 {
  46 #if 0
  47     printf("Raise exception %3x code : %d\n", exception, error_code);
  48 #endif
  49     switch (exception) {
  50     case EXCP_PROGRAM:
  51         if (error_code == EXCP_FP && msr_fe0 == 0 && msr_fe1 == 0)
  52             return;
  53         break;
  54     default:
  55         break;
  56     }
  57     env->exception_index = exception;
  58     env->error_code = error_code;
  59     cpu_loop_exit();
  60 }
  61
  62 void do_raise_exception (uint32_t exception)
  63 {
  64     do_raise_exception_err(exception, 0);
  65 }
  66
  67 void cpu_dump_EA (target_ulong EA);
  68 void do_print_mem_EA (target_ulong EA)
  69 {
  70     cpu_dump_EA(EA);
  71 }
  72
  73 /*****************************************************************************/
  74 /* Registers load and stores */
  75 void do_load_cr (void)
  76 {
  77     T0 = (env->crf[0] << 28) |
  78         (env->crf[1] << 24) |
  79         (env->crf[2] << 20) |
  80         (env->crf[3] << 16) |
  81         (env->crf[4] << 12) |
  82         (env->crf[5] << 8) |
  83         (env->crf[6] << 4) |
  84         (env->crf[7] << 0);
  85 }
  86
  87 void do_store_cr (uint32_t mask)
  88 {
  89     int i, sh;
  90
  91     for (i = 0, sh = 7; i < 8; i++, sh --) {
  92         if (mask & (1 << sh))
  93             env->crf[i] = (T0 >> (sh * 4)) & 0xFUL;
  94     }
  95 }
  96
  97 void do_load_xer (void)
  98 {
  99     T0 = (xer_so << XER_SO) |
 100         (xer_ov << XER_OV) |
 101         (xer_ca << XER_CA) |
 102         (xer_bc << XER_BC) |
 103         (xer_cmp << XER_CMP);
 104 }
 105
 106 void do_store_xer (void)
 107 {
 108     xer_so = (T0 >> XER_SO) & 0x01;
 109     xer_ov = (T0 >> XER_OV) & 0x01;
 110     xer_ca = (T0 >> XER_CA) & 0x01;
 111     xer_cmp = (T0 >> XER_CMP) & 0xFF;
 112     xer_bc = (T0 >> XER_BC) & 0x7F;
 113 }
 114
 115 void do_load_fpscr (void)
 116 {
 117     /* The 32 MSB of the target fpr are undefined.
 118      * They'll be zero...
 119      */
 120     union {
 121         float64 d;
 122         struct {
 123             uint32_t u[2];
 124         } s;
 125     } u;
 126     int i;
 127
 128 #if defined(WORDS_BIGENDIAN)
 129 #define WORD0 0
 130 #define WORD1 1
 131 #else
 132 #define WORD0 1
 133 #define WORD1 0
 134 #endif
 135     u.s.u[WORD0] = 0;
 136     u.s.u[WORD1] = 0;
 137     for (i = 0; i < 8; i++)
 138         u.s.u[WORD1] |= env->fpscr[i] << (4 * i);
 139     FT0 = u.d;
 140 }
 141
 142 void do_store_fpscr (uint32_t mask)
 143 {
 144     /*
 145      * We use only the 32 LSB of the incoming fpr
 146      */
 147     union {
 148         double d;
 149         struct {
 150             uint32_t u[2];
 151         } s;
 152     } u;
 153     int i, rnd_type;
 154
 155     u.d = FT0;
 156     if (mask & 0x80)
 157         env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[WORD1] >> 28) & ~0x9);
 158     for (i = 1; i < 7; i++) {
 159         if (mask & (1 << (7 - i)))
 160             env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF;
 161     }
 162     /* TODO: update FEX & VX */
 163     /* Set rounding mode */
 164     switch (env->fpscr[0] & 0x3) {
 165     case 0:
 166         /* Best approximation (round to nearest) */
 167         rnd_type = float_round_nearest_even;
 168         break;
 169     case 1:
 170         /* Smaller magnitude (round toward zero) */
 171         rnd_type = float_round_to_zero;
 172         break;
 173     case 2:
 174         /* Round toward +infinite */
 175         rnd_type = float_round_up;
 176         break;
 177     default:
 178     case 3:
 179         /* Round toward -infinite */
 180         rnd_type = float_round_down;
 181         break;
 182     }
 183     set_float_rounding_mode(rnd_type, &env->fp_status);
 184 }
 185
 186 target_ulong ppc_load_dump_spr (int sprn)
 187 {
 188     if (loglevel != 0) {
 189         fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
 190                 sprn, sprn, env->spr[sprn]);
 191     }
 192
 193     return env->spr[sprn];
 194 }
 195
 196 void ppc_store_dump_spr (int sprn, target_ulong val)
 197 {
 198     if (loglevel != 0) {
 199         fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n",
 200                 sprn, sprn, env->spr[sprn], val);
 201     }
 202     env->spr[sprn] = val;
 203 }
 204
 205 /*****************************************************************************/
 206 /* Fixed point operations helpers */
 207 #if defined(TARGET_PPC64)
 208 static void add128 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
 209 {
 210     *plow += a;
 211     /* carry test */
 212     if (*plow < a)
 213         (*phigh)++;
 214     *phigh += b;
 215 }
 216
 217 static void neg128 (uint64_t *plow, uint64_t *phigh)
 218 {
 219     *plow = ~ *plow;
 220     *phigh = ~ *phigh;
 221     add128(plow, phigh, 1, 0);
 222 }
 223
 224 static void mul64 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
 225 {
 226     uint32_t a0, a1, b0, b1;
 227     uint64_t v;
 228
 229     a0 = a;
 230     a1 = a >> 32;
 231
 232     b0 = b;
 233     b1 = b >> 32;
 234
 235     v = (uint64_t)a0 * (uint64_t)b0;
 236     *plow = v;
 237     *phigh = 0;
 238
 239     v = (uint64_t)a0 * (uint64_t)b1;
 240     add128(plow, phigh, v << 32, v >> 32);
 241
 242     v = (uint64_t)a1 * (uint64_t)b0;
 243     add128(plow, phigh, v << 32, v >> 32);
 244
 245     v = (uint64_t)a1 * (uint64_t)b1;
 246     *phigh += v;
 247 #if defined(DEBUG_MULDIV)
 248     printf("mul: 0x%016llx * 0x%016llx = 0x%016llx%016llx\n",
 249            a, b, *phigh, *plow);
 250 #endif
 251 }
 252
 253 void do_mul64 (uint64_t *plow, uint64_t *phigh)
 254 {
 255     mul64(plow, phigh, T0, T1);
 256 }
 257
 258 static void imul64 (uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b)
 259 {
 260     int sa, sb;
 261     sa = (a < 0);
 262     if (sa)
 263         a = -a;
 264     sb = (b < 0);
 265     if (sb)
 266         b = -b;
 267     mul64(plow, phigh, a, b);
 268     if (sa ^ sb) {
 269         neg128(plow, phigh);
 270     }
 271 }
 272
 273 void do_imul64 (uint64_t *plow, uint64_t *phigh)
 274 {
 275     imul64(plow, phigh, T0, T1);
 276 }
 277 #endif
 278
 279 void do_adde (void)
 280 {
 281     T2 = T0;
 282     T0 += T1 + xer_ca;
 283     if (likely(!((uint32_t)T0 < (uint32_t)T2 ||
 284                  (xer_ca == 1 && (uint32_t)T0 == (uint32_t)T2)))) {
 285         xer_ca = 0;
 286     } else {
 287         xer_ca = 1;
 288     }
 289 }
 290
 291 #if defined(TARGET_PPC64)
 292 void do_adde_64 (void)
 293 {
 294     T2 = T0;
 295     T0 += T1 + xer_ca;
 296     if (likely(!((uint64_t)T0 < (uint64_t)T2 ||
 297                  (xer_ca == 1 && (uint64_t)T0 == (uint64_t)T2)))) {
 298         xer_ca = 0;
 299     } else {
 300         xer_ca = 1;
 301     }
 302 }
 303 #endif
 304
 305 void do_addmeo (void)
 306 {
 307     T1 = T0;
 308     T0 += xer_ca + (-1);
 309     if (likely(!((uint32_t)T1 &
 310                  ((uint32_t)T1 ^ (uint32_t)T0) & (1UL << 31)))) {
 311         xer_ov = 0;
 312     } else {
 313         xer_so = 1;
 314         xer_ov = 1;
 315     }
 316     if (likely(T1 != 0))
 317         xer_ca = 1;
 318 }
 319
 320 #if defined(TARGET_PPC64)
 321 void do_addmeo_64 (void)
 322 {
 323     T1 = T0;
 324     T0 += xer_ca + (-1);
 325     if (likely(!((uint64_t)T1 &
 326                  ((uint64_t)T1 ^ (uint64_t)T0) & (1ULL << 63)))) {
 327         xer_ov = 0;
 328     } else {
 329         xer_so = 1;
 330         xer_ov = 1;
 331     }
 332     if (likely(T1 != 0))
 333         xer_ca = 1;
 334 }
 335 #endif
 336
 337 void do_divwo (void)
 338 {
 339     if (likely(!(((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) ||
 340                  (int32_t)T1 == 0))) {
 341         xer_ov = 0;
 342         T0 = (int32_t)T0 / (int32_t)T1;
 343     } else {
 344         xer_so = 1;
 345         xer_ov = 1;
 346         T0 = (-1) * ((uint32_t)T0 >> 31);
 347     }
 348 }
 349
 350 #if defined(TARGET_PPC64)
 351 void do_divdo (void)
 352 {
 353     if (likely(!(((int64_t)T0 == INT64_MIN && (int64_t)T1 == -1ULL) ||
 354                  (int64_t)T1 == 0))) {
 355         xer_ov = 0;
 356         T0 = (int64_t)T0 / (int64_t)T1;
 357     } else {
 358         xer_so = 1;
 359         xer_ov = 1;
 360         T0 = (-1ULL) * ((uint64_t)T0 >> 63);
 361     }
 362 }
 363 #endif
 364
 365 void do_divwuo (void)
 366 {
 367     if (likely((uint32_t)T1 != 0)) {
 368         xer_ov = 0;
 369         T0 = (uint32_t)T0 / (uint32_t)T1;
 370     } else {
 371         xer_so = 1;
 372         xer_ov = 1;
 373         T0 = 0;
 374     }
 375 }
 376
 377 #if defined(TARGET_PPC64)
 378 void do_divduo (void)
 379 {
 380     if (likely((uint64_t)T1 != 0)) {
 381         xer_ov = 0;
 382         T0 = (uint64_t)T0 / (uint64_t)T1;
 383     } else {
 384         xer_so = 1;
 385         xer_ov = 1;
 386         T0 = 0;
 387     }
 388 }
 389 #endif
 390
 391 void do_mullwo (void)
 392 {
 393     int64_t res = (int64_t)T0 * (int64_t)T1;
 394
 395     if (likely((int32_t)res == res)) {
 396         xer_ov = 0;
 397     } else {
 398         xer_ov = 1;
 399         xer_so = 1;
 400     }
 401     T0 = (int32_t)res;
 402 }
 403
 404 #if defined(TARGET_PPC64)
 405 void do_mulldo (void)
 406 {
 407     int64_t th;
 408     uint64_t tl;
 409
 410     do_imul64(&tl, &th);
 411     if (likely(th == 0)) {
 412         xer_ov = 0;
 413     } else {
 414         xer_ov = 1;
 415         xer_so = 1;
 416     }
 417     T0 = (int64_t)tl;
 418 }
 419 #endif
 420
 421 void do_nego (void)
 422 {
 423     if (likely((int32_t)T0 != INT32_MIN)) {
 424         xer_ov = 0;
 425         T0 = -(int32_t)T0;
 426     } else {
 427         xer_ov = 1;
 428         xer_so = 1;
 429     }
 430 }
 431
 432 #if defined(TARGET_PPC64)
 433 void do_nego_64 (void)
 434 {
 435     if (likely((int64_t)T0 != INT64_MIN)) {
 436         xer_ov = 0;
 437         T0 = -(int64_t)T0;
 438     } else {
 439         xer_ov = 1;
 440         xer_so = 1;
 441     }
 442 }
 443 #endif
 444
 445 void do_subfe (void)
 446 {
 447     T0 = T1 + ~T0 + xer_ca;
 448     if (likely((uint32_t)T0 >= (uint32_t)T1 &&
 449                (xer_ca == 0 || (uint32_t)T0 != (uint32_t)T1))) {
 450         xer_ca = 0;
 451     } else {
 452         xer_ca = 1;
 453     }
 454 }
 455
 456 #if defined(TARGET_PPC64)
 457 void do_subfe_64 (void)
 458 {
 459     T0 = T1 + ~T0 + xer_ca;
 460     if (likely((uint64_t)T0 >= (uint64_t)T1 &&
 461                (xer_ca == 0 || (uint64_t)T0 != (uint64_t)T1))) {
 462         xer_ca = 0;
 463     } else {
 464         xer_ca = 1;
 465     }
 466 }
 467 #endif
 468
 469 void do_subfmeo (void)
 470 {
 471     T1 = T0;
 472     T0 = ~T0 + xer_ca - 1;
 473     if (likely(!((uint32_t)~T1 & ((uint32_t)~T1 ^ (uint32_t)T0) &
 474                  (1UL << 31)))) {
 475         xer_ov = 0;
 476     } else {
 477         xer_so = 1;
 478         xer_ov = 1;
 479     }
 480     if (likely((uint32_t)T1 != UINT32_MAX))
 481         xer_ca = 1;
 482 }
 483
 484 #if defined(TARGET_PPC64)
 485 void do_subfmeo_64 (void)
 486 {
 487     T1 = T0;
 488     T0 = ~T0 + xer_ca - 1;
 489     if (likely(!((uint64_t)~T1 & ((uint64_t)~T1 ^ (uint64_t)T0) &
 490                  (1ULL << 63)))) {
 491         xer_ov = 0;
 492     } else {
 493         xer_so = 1;
 494         xer_ov = 1;
 495     }
 496     if (likely((uint64_t)T1 != UINT64_MAX))
 497         xer_ca = 1;
 498 }
 499 #endif
 500
 501 void do_subfzeo (void)
 502 {
 503     T1 = T0;
 504     T0 = ~T0 + xer_ca;
 505     if (likely(!(((uint32_t)~T1 ^ UINT32_MAX) &
 506                  ((uint32_t)(~T1) ^ (uint32_t)T0) & (1UL << 31)))) {
 507         xer_ov = 0;
 508     } else {
 509         xer_ov = 1;
 510         xer_so = 1;
 511     }
 512     if (likely((uint32_t)T0 >= (uint32_t)~T1)) {
 513         xer_ca = 0;
 514     } else {
 515         xer_ca = 1;
 516     }
 517 }
 518
 519 #if defined(TARGET_PPC64)
 520 void do_subfzeo_64 (void)
 521 {
 522     T1 = T0;
 523     T0 = ~T0 + xer_ca;
 524     if (likely(!(((uint64_t)~T1 ^ UINT64_MAX) &
 525                  ((uint64_t)(~T1) ^ (uint64_t)T0) & (1ULL << 63)))) {
 526         xer_ov = 0;
 527     } else {
 528         xer_ov = 1;
 529         xer_so = 1;
 530     }
 531     if (likely((uint64_t)T0 >= (uint64_t)~T1)) {
 532         xer_ca = 0;
 533     } else {
 534         xer_ca = 1;
 535     }
 536 }
 537 #endif
 538
 539 /* shift right arithmetic helper */
 540 void do_sraw (void)
 541 {
 542     int32_t ret;
 543
 544     if (likely(!(T1 & 0x20UL))) {
 545         if (likely((uint32_t)T1 != 0)) {
 546             ret = (int32_t)T0 >> (T1 & 0x1fUL);
 547             if (likely(ret >= 0 || ((int32_t)T0 & ((1 << T1) - 1)) == 0)) {
 548                 xer_ca = 0;
 549             } else {
 550                 xer_ca = 1;
 551             }
 552         } else {
 553             ret = T0;
 554             xer_ca = 0;
 555         }
 556     } else {
 557         ret = (-1) * ((uint32_t)T0 >> 31);
 558         if (likely(ret >= 0 || ((uint32_t)T0 & ~0x80000000UL) == 0)) {
 559             xer_ca = 0;
 560         } else {
 561             xer_ca = 1;
 562         }
 563     }
 564     T0 = ret;
 565 }
 566
 567 #if defined(TARGET_PPC64)
 568 void do_srad (void)
 569 {
 570     int64_t ret;
 571
 572     if (likely(!(T1 & 0x40UL))) {
 573         if (likely((uint64_t)T1 != 0)) {
 574             ret = (int64_t)T0 >> (T1 & 0x3FUL);
 575             if (likely(ret >= 0 || ((int64_t)T0 & ((1 << T1) - 1)) == 0)) {
 576                 xer_ca = 0;
 577             } else {
 578                 xer_ca = 1;
 579             }
 580         } else {
 581             ret = T0;
 582             xer_ca = 0;
 583         }
 584     } else {
 585         ret = (-1) * ((uint64_t)T0 >> 63);
 586         if (likely(ret >= 0 || ((uint64_t)T0 & ~0x8000000000000000ULL) == 0)) {
 587             xer_ca = 0;
 588         } else {
 589             xer_ca = 1;
 590         }
 591     }
 592     T0 = ret;
 593 }
 594 #endif
 595
 596 static inline int popcnt (uint32_t val)
 597 {
 598     int i;
 599
 600     for (i = 0; val != 0;)
 601         val = val ^ (val - 1);
 602
 603     return i;
 604 }
 605
 606 void do_popcntb (void)
 607 {
 608     uint32_t ret;
 609     int i;
 610
 611     ret = 0;
 612     for (i = 0; i < 32; i += 8)
 613         ret |= popcnt((T0 >> i) & 0xFF) << i;
 614     T0 = ret;
 615 }
 616
 617 #if defined(TARGET_PPC64)
 618 void do_popcntb_64 (void)
 619 {
 620     uint64_t ret;
 621     int i;
 622
 623     ret = 0;
 624     for (i = 0; i < 64; i += 8)
 625         ret |= popcnt((T0 >> i) & 0xFF) << i;
 626     T0 = ret;
 627 }
 628 #endif
 629
 630 /*****************************************************************************/
 631 /* Floating point operations helpers */
 632 void do_fctiw (void)
 633 {
 634     union {
 635         double d;
 636         uint64_t i;
 637     } p;
 638
 639     p.i = float64_to_int32(FT0, &env->fp_status);
 640 #if USE_PRECISE_EMULATION
 641     /* XXX: higher bits are not supposed to be significant.
 642      *     to make tests easier, return the same as a real PowerPC 750 (aka G3)
 643      */
 644     p.i |= 0xFFF80000ULL << 32;
 645 #endif
 646     FT0 = p.d;
 647 }
 648
 649 void do_fctiwz (void)
 650 {
 651     union {
 652         double d;
 653         uint64_t i;
 654     } p;
 655
 656     p.i = float64_to_int32_round_to_zero(FT0, &env->fp_status);
 657 #if USE_PRECISE_EMULATION
 658     /* XXX: higher bits are not supposed to be significant.
 659      *     to make tests easier, return the same as a real PowerPC 750 (aka G3)
 660      */
 661     p.i |= 0xFFF80000ULL << 32;
 662 #endif
 663     FT0 = p.d;
 664 }
 665
 666 #if defined(TARGET_PPC64)
 667 void do_fcfid (void)
 668 {
 669     union {
 670         double d;
 671         uint64_t i;
 672     } p;
 673
 674     p.d = FT0;
 675     FT0 = int64_to_float64(p.i, &env->fp_status);
 676 }
 677
 678 void do_fctid (void)
 679 {
 680     union {
 681         double d;
 682         uint64_t i;
 683     } p;
 684
 685     p.i = float64_to_int64(FT0, &env->fp_status);
 686     FT0 = p.d;
 687 }
 688
 689 void do_fctidz (void)
 690 {
 691     union {
 692         double d;
 693         uint64_t i;
 694     } p;
 695
 696     p.i = float64_to_int64_round_to_zero(FT0, &env->fp_status);
 697     FT0 = p.d;
 698 }
 699
 700 #endif
 701
 702 #if USE_PRECISE_EMULATION
 703 void do_fmadd (void)
 704 {
 705 #ifdef FLOAT128
 706     float128 ft0_128, ft1_128;
 707
 708     ft0_128 = float64_to_float128(FT0, &env->fp_status);
 709     ft1_128 = float64_to_float128(FT1, &env->fp_status);
 710     ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 711     ft1_128 = float64_to_float128(FT2, &env->fp_status);
 712     ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
 713     FT0 = float128_to_float64(ft0_128, &env->fp_status);
 714 #else
 715     /* This is OK on x86 hosts */
 716     FT0 = (FT0 * FT1) + FT2;
 717 #endif
 718 }
 719
 720 void do_fmsub (void)
 721 {
 722 #ifdef FLOAT128
 723     float128 ft0_128, ft1_128;
 724
 725     ft0_128 = float64_to_float128(FT0, &env->fp_status);
 726     ft1_128 = float64_to_float128(FT1, &env->fp_status);
 727     ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 728     ft1_128 = float64_to_float128(FT2, &env->fp_status);
 729     ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
 730     FT0 = float128_to_float64(ft0_128, &env->fp_status);
 731 #else
 732     /* This is OK on x86 hosts */
 733     FT0 = (FT0 * FT1) - FT2;
 734 #endif
 735 }
 736 #endif /* USE_PRECISE_EMULATION */
 737
 738 void do_fnmadd (void)
 739 {
 740 #if USE_PRECISE_EMULATION
 741 #ifdef FLOAT128
 742     float128 ft0_128, ft1_128;
 743
 744     ft0_128 = float64_to_float128(FT0, &env->fp_status);
 745     ft1_128 = float64_to_float128(FT1, &env->fp_status);
 746     ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 747     ft1_128 = float64_to_float128(FT2, &env->fp_status);
 748     ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
 749     FT0 = float128_to_float64(ft0_128, &env->fp_status);
 750 #else
 751     /* This is OK on x86 hosts */
 752     FT0 = (FT0 * FT1) + FT2;
 753 #endif
 754 #else
 755     FT0 = float64_mul(FT0, FT1, &env->fp_status);
 756     FT0 = float64_add(FT0, FT2, &env->fp_status);
 757 #endif
 758     if (likely(!isnan(FT0)))
 759         FT0 = float64_chs(FT0);
 760 }
 761
 762 void do_fnmsub (void)
 763 {
 764 #if USE_PRECISE_EMULATION
 765 #ifdef FLOAT128
 766     float128 ft0_128, ft1_128;
 767
 768     ft0_128 = float64_to_float128(FT0, &env->fp_status);
 769     ft1_128 = float64_to_float128(FT1, &env->fp_status);
 770     ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 771     ft1_128 = float64_to_float128(FT2, &env->fp_status);
 772     ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
 773     FT0 = float128_to_float64(ft0_128, &env->fp_status);
 774 #else
 775     /* This is OK on x86 hosts */
 776     FT0 = (FT0 * FT1) - FT2;
 777 #endif
 778 #else
 779     FT0 = float64_mul(FT0, FT1, &env->fp_status);
 780     FT0 = float64_sub(FT0, FT2, &env->fp_status);
 781 #endif
 782     if (likely(!isnan(FT0)))
 783         FT0 = float64_chs(FT0);
 784 }
 785
 786 void do_fsqrt (void)
 787 {
 788     FT0 = float64_sqrt(FT0, &env->fp_status);
 789 }
 790
 791 void do_fres (void)
 792 {
 793     union {
 794         double d;
 795         uint64_t i;
 796     } p;
 797
 798     if (likely(isnormal(FT0))) {
 799 #if USE_PRECISE_EMULATION
 800         FT0 = float64_div(1.0, FT0, &env->fp_status);
 801         FT0 = float64_to_float32(FT0, &env->fp_status);
 802 #else
 803         FT0 = float32_div(1.0, FT0, &env->fp_status);
 804 #endif
 805     } else {
 806         p.d = FT0;
 807         if (p.i == 0x8000000000000000ULL) {
 808             p.i = 0xFFF0000000000000ULL;
 809         } else if (p.i == 0x0000000000000000ULL) {
 810             p.i = 0x7FF0000000000000ULL;
 811         } else if (isnan(FT0)) {
 812             p.i = 0x7FF8000000000000ULL;
 813         } else if (FT0 < 0.0) {
 814             p.i = 0x8000000000000000ULL;
 815         } else {
 816             p.i = 0x0000000000000000ULL;
 817         }
 818         FT0 = p.d;
 819     }
 820 }
 821
 822 void do_frsqrte (void)
 823 {
 824     union {
 825         double d;
 826         uint64_t i;
 827     } p;
 828
 829     if (likely(isnormal(FT0) && FT0 > 0.0)) {
 830         FT0 = float64_sqrt(FT0, &env->fp_status);
 831         FT0 = float32_div(1.0, FT0, &env->fp_status);
 832     } else {
 833         p.d = FT0;
 834         if (p.i == 0x8000000000000000ULL) {
 835             p.i = 0xFFF0000000000000ULL;
 836         } else if (p.i == 0x0000000000000000ULL) {
 837             p.i = 0x7FF0000000000000ULL;
 838         } else if (isnan(FT0)) {
 839             if (!(p.i & 0x0008000000000000ULL))
 840                 p.i |= 0x000FFFFFFFFFFFFFULL;
 841         } else if (FT0 < 0) {
 842             p.i = 0x7FF8000000000000ULL;
 843         } else {
 844             p.i = 0x0000000000000000ULL;
 845         }
 846         FT0 = p.d;
 847     }
 848 }
 849
 850 void do_fsel (void)
 851 {
 852     if (FT0 >= 0)
 853         FT0 = FT1;
 854     else
 855         FT0 = FT2;
 856 }
 857
 858 void do_fcmpu (void)
 859 {
 860     if (likely(!isnan(FT0) && !isnan(FT1))) {
 861         if (float64_lt(FT0, FT1, &env->fp_status)) {
 862             T0 = 0x08UL;
 863         } else if (!float64_le(FT0, FT1, &env->fp_status)) {
 864             T0 = 0x04UL;
 865         } else {
 866             T0 = 0x02UL;
 867         }
 868     } else {
 869         T0 = 0x01UL;
 870         env->fpscr[4] |= 0x1;
 871         env->fpscr[6] |= 0x1;
 872     }
 873     env->fpscr[3] = T0;
 874 }
 875
 876 void do_fcmpo (void)
 877 {
 878     env->fpscr[4] &= ~0x1;
 879     if (likely(!isnan(FT0) && !isnan(FT1))) {
 880         if (float64_lt(FT0, FT1, &env->fp_status)) {
 881             T0 = 0x08UL;
 882         } else if (!float64_le(FT0, FT1, &env->fp_status)) {
 883             T0 = 0x04UL;
 884         } else {
 885             T0 = 0x02UL;
 886         }
 887     } else {
 888         T0 = 0x01UL;
 889         env->fpscr[4] |= 0x1;
 890         if (!float64_is_signaling_nan(FT0) || !float64_is_signaling_nan(FT1)) {
 891             /* Quiet NaN case */
 892             env->fpscr[6] |= 0x1;
 893             if (!(env->fpscr[1] & 0x8))
 894                 env->fpscr[4] |= 0x8;
 895         } else {
 896             env->fpscr[4] |= 0x8;
 897         }
 898     }
 899     env->fpscr[3] = T0;
 900 }
 901
 902 #if !defined (CONFIG_USER_ONLY)
 903 void cpu_dump_rfi (target_ulong RA, target_ulong msr);
 904 void do_rfi (void)
 905 {
 906 #if defined(TARGET_PPC64)
 907     if (env->spr[SPR_SRR1] & (1ULL << MSR_SF)) {
 908         env->nip = (uint64_t)(env->spr[SPR_SRR0] & ~0x00000003);
 909         do_store_msr(env, (uint64_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
 910     } else {
 911         env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003);
 912         ppc_store_msr_32(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
 913     }
 914 #else
 915     env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003);
 916     do_store_msr(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
 917 #endif
 918 #if defined (DEBUG_OP)
 919     cpu_dump_rfi(env->nip, do_load_msr(env));
 920 #endif
 921     env->interrupt_request |= CPU_INTERRUPT_EXITTB;
 922 }
 923
 924 #if defined(TARGET_PPC64)
 925 void do_rfid (void)
 926 {
 927     if (env->spr[SPR_SRR1] & (1ULL << MSR_SF)) {
 928         env->nip = (uint64_t)(env->spr[SPR_SRR0] & ~0x00000003);
 929         do_store_msr(env, (uint64_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
 930     } else {
 931         env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003);
 932         do_store_msr(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
 933     }
 934 #if defined (DEBUG_OP)
 935     cpu_dump_rfi(env->nip, do_load_msr(env));
 936 #endif
 937     env->interrupt_request |= CPU_INTERRUPT_EXITTB;
 938 }
 939 #endif
 940 #endif
 941
 942 void do_tw (int flags)
 943 {
 944     if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) ||
 945                   ((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) ||
 946                   ((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) ||
 947                   ((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) ||
 948                   ((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) {
 949         do_raise_exception_err(EXCP_PROGRAM, EXCP_TRAP);
 950     }
 951 }
 952
 953 #if defined(TARGET_PPC64)
 954 void do_td (int flags)
 955 {
 956     if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) ||
 957                   ((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) ||
 958                   ((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) ||
 959                   ((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) ||
 960                   ((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01)))))
 961         do_raise_exception_err(EXCP_PROGRAM, EXCP_TRAP);
 962 }
 963 #endif
 964
 965 /*****************************************************************************/
 966 /* PowerPC 601 specific instructions (POWER bridge) */
 967 void do_POWER_abso (void)
 968 {
 969     if ((uint32_t)T0 == INT32_MIN) {
 970         T0 = INT32_MAX;
 971         xer_ov = 1;
 972         xer_so = 1;
 973     } else {
 974         T0 = -T0;
 975         xer_ov = 0;
 976     }
 977 }
 978
 979 void do_POWER_clcs (void)
 980 {
 981     switch (T0) {
 982     case 0x0CUL:
 983         /* Instruction cache line size */
 984         T0 = ICACHE_LINE_SIZE;
 985         break;
 986     case 0x0DUL:
 987         /* Data cache line size */
 988         T0 = DCACHE_LINE_SIZE;
 989         break;
 990     case 0x0EUL:
 991         /* Minimum cache line size */
 992         T0 = ICACHE_LINE_SIZE < DCACHE_LINE_SIZE ?
 993             ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
 994         break;
 995     case 0x0FUL:
 996         /* Maximum cache line size */
 997         T0 = ICACHE_LINE_SIZE > DCACHE_LINE_SIZE ?
 998             ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
 999         break;
1000     default:
1001         /* Undefined */
1002         break;
1003     }
1004 }
1005
1006 void do_POWER_div (void)
1007 {
1008     uint64_t tmp;
1009
1010     if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
1011         T0 = (long)((-1) * (T0 >> 31));
1012         env->spr[SPR_MQ] = 0;
1013     } else {
1014         tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1015         env->spr[SPR_MQ] = tmp % T1;
1016         T0 = tmp / (int32_t)T1;
1017     }
1018 }
1019
1020 void do_POWER_divo (void)
1021 {
1022     int64_t tmp;
1023
1024     if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
1025         T0 = (long)((-1) * (T0 >> 31));
1026         env->spr[SPR_MQ] = 0;
1027         xer_ov = 1;
1028         xer_so = 1;
1029     } else {
1030         tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1031         env->spr[SPR_MQ] = tmp % T1;
1032         tmp /= (int32_t)T1;
1033         if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
1034             xer_ov = 1;
1035             xer_so = 1;
1036         } else {
1037             xer_ov = 0;
1038         }
1039         T0 = tmp;
1040     }
1041 }
1042
1043 void do_POWER_divs (void)
1044 {
1045     if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
1046         T0 = (long)((-1) * (T0 >> 31));
1047         env->spr[SPR_MQ] = 0;
1048     } else {
1049         env->spr[SPR_MQ] = T0 % T1;
1050         T0 = (int32_t)T0 / (int32_t)T1;
1051     }
1052 }
1053
1054 void do_POWER_divso (void)
1055 {
1056     if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
1057         T0 = (long)((-1) * (T0 >> 31));
1058         env->spr[SPR_MQ] = 0;
1059         xer_ov = 1;
1060         xer_so = 1;
1061     } else {
1062         T0 = (int32_t)T0 / (int32_t)T1;
1063         env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
1064         xer_ov = 0;
1065     }
1066 }
1067
1068 void do_POWER_dozo (void)
1069 {
1070     if ((int32_t)T1 > (int32_t)T0) {
1071         T2 = T0;
1072         T0 = T1 - T0;
1073         if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
1074             ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
1075             xer_so = 1;
1076             xer_ov = 1;
1077         } else {
1078             xer_ov = 0;
1079         }
1080     } else {
1081         T0 = 0;
1082         xer_ov = 0;
1083     }
1084 }
1085
1086 void do_POWER_maskg (void)
1087 {
1088     uint32_t ret;
1089
1090     if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
1091         ret = -1;
1092     } else {
1093         ret = (((uint32_t)(-1)) >> ((uint32_t)T0)) ^
1094             (((uint32_t)(-1) >> ((uint32_t)T1)) >> 1);
1095         if ((uint32_t)T0 > (uint32_t)T1)
1096             ret = ~ret;
1097     }
1098     T0 = ret;
1099 }
1100
1101 void do_POWER_mulo (void)
1102 {
1103     uint64_t tmp;
1104
1105     tmp = (uint64_t)T0 * (uint64_t)T1;
1106     env->spr[SPR_MQ] = tmp >> 32;
1107     T0 = tmp;
1108     if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
1109         xer_ov = 1;
1110         xer_so = 1;
1111     } else {
1112         xer_ov = 0;
1113     }
1114 }
1115
1116 #if !defined (CONFIG_USER_ONLY)
1117 void do_POWER_rac (void)
1118 {
1119 #if 0
1120     mmu_ctx_t ctx;
1121
1122     /* We don't have to generate many instances of this instruction,
1123      * as rac is supervisor only.
1124      */
1125     if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT, 1) == 0)
1126         T0 = ctx.raddr;
1127 #endif
1128 }
1129
1130 void do_POWER_rfsvc (void)
1131 {
1132     env->nip = env->lr & ~0x00000003UL;
1133     T0 = env->ctr & 0x0000FFFFUL;
1134     do_store_msr(env, T0);
1135 #if defined (DEBUG_OP)
1136     cpu_dump_rfi(env->nip, do_load_msr(env));
1137 #endif
1138     env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1139 }
1140
1141 /* PowerPC 601 BAT management helper */
1142 void do_store_601_batu (int nr)
1143 {
1144     do_store_ibatu(env, nr, (uint32_t)T0);
1145     env->DBAT[0][nr] = env->IBAT[0][nr];
1146     env->DBAT[1][nr] = env->IBAT[1][nr];
1147 }
1148 #endif
1149
1150 /*****************************************************************************/
1151 /* 602 specific instructions */
1152 /* mfrom is the most crazy instruction ever seen, imho ! */
1153 /* Real implementation uses a ROM table. Do the same */
1154 #define USE_MFROM_ROM_TABLE
1155 void do_op_602_mfrom (void)
1156 {
1157     if (likely(T0 < 602)) {
1158 #if defined(USE_MFROM_ROM_TABLE)
1159 #include "mfrom_table.c"
1160         T0 = mfrom_ROM_table[T0];
1161 #else
1162         double d;
1163         /* Extremly decomposed:
1164          *                    -T0 / 256
1165          * T0 = 256 * log10(10          + 1.0) + 0.5
1166          */
1167         d = T0;
1168         d = float64_div(d, 256, &env->fp_status);
1169         d = float64_chs(d);
1170         d = exp10(d); // XXX: use float emulation function
1171         d = float64_add(d, 1.0, &env->fp_status);
1172         d = log10(d); // XXX: use float emulation function
1173         d = float64_mul(d, 256, &env->fp_status);
1174         d = float64_add(d, 0.5, &env->fp_status);
1175         T0 = float64_round_to_int(d, &env->fp_status);
1176 #endif
1177     } else {
1178         T0 = 0;
1179     }
1180 }
1181
1182 /*****************************************************************************/
1183 /* Embedded PowerPC specific helpers */
1184 void do_405_check_ov (void)
1185 {
1186     if (likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
1187                !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
1188         xer_ov = 0;
1189     } else {
1190         xer_ov = 1;
1191         xer_so = 1;
1192     }
1193 }
1194
1195 void do_405_check_sat (void)
1196 {
1197     if (!likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
1198                 !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
1199         /* Saturate result */
1200         if (T2 >> 31) {
1201             T0 = INT32_MIN;
1202         } else {
1203             T0 = INT32_MAX;
1204         }
1205     }
1206 }
1207
1208 #if !defined(CONFIG_USER_ONLY)
1209 void do_40x_rfci (void)
1210 {
1211     env->nip = env->spr[SPR_40x_SRR2];
1212     do_store_msr(env, env->spr[SPR_40x_SRR3] & ~0xFFFF0000);
1213 #if defined (DEBUG_OP)
1214     cpu_dump_rfi(env->nip, do_load_msr(env));
1215 #endif
1216     env->interrupt_request = CPU_INTERRUPT_EXITTB;
1217 }
1218
1219 void do_rfci (void)
1220 {
1221 #if defined(TARGET_PPC64)
1222     if (env->spr[SPR_BOOKE_CSRR1] & (1 << MSR_CM)) {
1223         env->nip = (uint64_t)env->spr[SPR_BOOKE_CSRR0];
1224     } else
1225 #endif
1226     {
1227         env->nip = (uint32_t)env->spr[SPR_BOOKE_CSRR0];
1228     }
1229     do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_CSRR1] & ~0x3FFF0000);
1230 #if defined (DEBUG_OP)
1231     cpu_dump_rfi(env->nip, do_load_msr(env));
1232 #endif
1233     env->interrupt_request = CPU_INTERRUPT_EXITTB;
1234 }
1235
1236 void do_rfdi (void)
1237 {
1238 #if defined(TARGET_PPC64)
1239     if (env->spr[SPR_BOOKE_DSRR1] & (1 << MSR_CM)) {
1240         env->nip = (uint64_t)env->spr[SPR_BOOKE_DSRR0];
1241     } else
1242 #endif
1243     {
1244         env->nip = (uint32_t)env->spr[SPR_BOOKE_DSRR0];
1245     }
1246     do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_DSRR1] & ~0x3FFF0000);
1247 #if defined (DEBUG_OP)
1248     cpu_dump_rfi(env->nip, do_load_msr(env));
1249 #endif
1250     env->interrupt_request = CPU_INTERRUPT_EXITTB;
1251 }
1252
1253 void do_rfmci (void)
1254 {
1255 #if defined(TARGET_PPC64)
1256     if (env->spr[SPR_BOOKE_MCSRR1] & (1 << MSR_CM)) {
1257         env->nip = (uint64_t)env->spr[SPR_BOOKE_MCSRR0];
1258     } else
1259 #endif
1260     {
1261         env->nip = (uint32_t)env->spr[SPR_BOOKE_MCSRR0];
1262     }
1263     do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_MCSRR1] & ~0x3FFF0000);
1264 #if defined (DEBUG_OP)
1265     cpu_dump_rfi(env->nip, do_load_msr(env));
1266 #endif
1267     env->interrupt_request = CPU_INTERRUPT_EXITTB;
1268 }
1269
1270 void do_load_dcr (void)
1271 {
1272     target_ulong val;
1273
1274     if (unlikely(env->dcr_env == NULL)) {
1275         if (loglevel != 0) {
1276             fprintf(logfile, "No DCR environment\n");
1277         }
1278         do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL);
1279     } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
1280         if (loglevel != 0) {
1281             fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
1282         }
1283         do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG);
1284     } else {
1285         T0 = val;
1286     }
1287 }
1288
1289 void do_store_dcr (void)
1290 {
1291     if (unlikely(env->dcr_env == NULL)) {
1292         if (loglevel != 0) {
1293             fprintf(logfile, "No DCR environment\n");
1294         }
1295         do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL);
1296     } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
1297         if (loglevel != 0) {
1298             fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
1299         }
1300         do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG);
1301     }
1302 }
1303
1304 void do_load_403_pb (int num)
1305 {
1306     T0 = env->pb[num];
1307 }
1308
1309 void do_store_403_pb (int num)
1310 {
1311     if (likely(env->pb[num] != T0)) {
1312         env->pb[num] = T0;
1313         /* Should be optimized */
1314         tlb_flush(env, 1);
1315     }
1316 }
1317 #endif
1318
1319 /* 440 specific */
1320 void do_440_dlmzb (void)
1321 {
1322     target_ulong mask;
1323     int i;
1324
1325     i = 1;
1326     for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1327         if ((T0 & mask) == 0)
1328             goto done;
1329         i++;
1330     }
1331     for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1332         if ((T1 & mask) == 0)
1333             break;
1334         i++;
1335     }
1336  done:
1337     T0 = i;
1338 }
1339
1340 #if defined(TARGET_PPCEMB)
1341 /* SPE extension helpers */
1342 /* Use a table to make this quicker */
1343 static uint8_t hbrev[16] = {
1344     0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1345     0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1346 };
1347
1348 static inline uint8_t byte_reverse (uint8_t val)
1349 {
1350     return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
1351 }
1352
1353 static inline uint32_t word_reverse (uint32_t val)
1354 {
1355     return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
1356         (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
1357 }
1358
1359 #define MASKBITS 16 // Random value - to be fixed
1360 void do_brinc (void)
1361 {
1362     uint32_t a, b, d, mask;
1363
1364     mask = (uint32_t)(-1UL) >> MASKBITS;
1365     b = T1_64 & mask;
1366     a = T0_64 & mask;
1367     d = word_reverse(1 + word_reverse(a | ~mask));
1368     T0_64 = (T0_64 & ~mask) | (d & mask);
1369 }
1370
1371 #define DO_SPE_OP2(name)                                                      \
1372 void do_ev##name (void)                                                       \
1373 {                                                                             \
1374     T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) |         \
1375         (uint64_t)_do_e##name(T0_64, T1_64);                                  \
1376 }
1377
1378 #define DO_SPE_OP1(name)                                                      \
1379 void do_ev##name (void)                                                       \
1380 {                                                                             \
1381     T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) |                      \
1382         (uint64_t)_do_e##name(T0_64);                                         \
1383 }
1384
1385 /* Fixed-point vector arithmetic */
1386 static inline uint32_t _do_eabs (uint32_t val)
1387 {
1388     if (val != 0x80000000)
1389         val &= ~0x80000000;
1390
1391     return val;
1392 }
1393
1394 static inline uint32_t _do_eaddw (uint32_t op1, uint32_t op2)
1395 {
1396     return op1 + op2;
1397 }
1398
1399 static inline int _do_ecntlsw (uint32_t val)
1400 {
1401     if (val & 0x80000000)
1402         return _do_cntlzw(~val);
1403     else
1404         return _do_cntlzw(val);
1405 }
1406
1407 static inline int _do_ecntlzw (uint32_t val)
1408 {
1409     return _do_cntlzw(val);
1410 }
1411
1412 static inline uint32_t _do_eneg (uint32_t val)
1413 {
1414     if (val != 0x80000000)
1415         val ^= 0x80000000;
1416
1417     return val;
1418 }
1419
1420 static inline uint32_t _do_erlw (uint32_t op1, uint32_t op2)
1421 {
1422     return rotl32(op1, op2);
1423 }
1424
1425 static inline uint32_t _do_erndw (uint32_t val)
1426 {
1427     return (val + 0x000080000000) & 0xFFFF0000;
1428 }
1429
1430 static inline uint32_t _do_eslw (uint32_t op1, uint32_t op2)
1431 {
1432     /* No error here: 6 bits are used */
1433     return op1 << (op2 & 0x3F);
1434 }
1435
1436 static inline int32_t _do_esrws (int32_t op1, uint32_t op2)
1437 {
1438     /* No error here: 6 bits are used */
1439     return op1 >> (op2 & 0x3F);
1440 }
1441
1442 static inline uint32_t _do_esrwu (uint32_t op1, uint32_t op2)
1443 {
1444     /* No error here: 6 bits are used */
1445     return op1 >> (op2 & 0x3F);
1446 }
1447
1448 static inline uint32_t _do_esubfw (uint32_t op1, uint32_t op2)
1449 {
1450     return op2 - op1;
1451 }
1452
1453 /* evabs */
1454 DO_SPE_OP1(abs);
1455 /* evaddw */
1456 DO_SPE_OP2(addw);
1457 /* evcntlsw */
1458 DO_SPE_OP1(cntlsw);
1459 /* evcntlzw */
1460 DO_SPE_OP1(cntlzw);
1461 /* evneg */
1462 DO_SPE_OP1(neg);
1463 /* evrlw */
1464 DO_SPE_OP2(rlw);
1465 /* evrnd */
1466 DO_SPE_OP1(rndw);
1467 /* evslw */
1468 DO_SPE_OP2(slw);
1469 /* evsrws */
1470 DO_SPE_OP2(srws);
1471 /* evsrwu */
1472 DO_SPE_OP2(srwu);
1473 /* evsubfw */
1474 DO_SPE_OP2(subfw);
1475
1476 /* evsel is a little bit more complicated... */
1477 static inline uint32_t _do_esel (uint32_t op1, uint32_t op2, int n)
1478 {
1479     if (n)
1480         return op1;
1481     else
1482         return op2;
1483 }
1484
1485 void do_evsel (void)
1486 {
1487     T0_64 = ((uint64_t)_do_esel(T0_64 >> 32, T1_64 >> 32, T0 >> 3) << 32) |
1488         (uint64_t)_do_esel(T0_64, T1_64, (T0 >> 2) & 1);
1489 }
1490
1491 /* Fixed-point vector comparisons */
1492 #define DO_SPE_CMP(name)                                                      \
1493 void do_ev##name (void)                                                       \
1494 {                                                                             \
1495     T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32,                   \
1496                                                T1_64 >> 32) << 32,            \
1497                          _do_e##name(T0_64, T1_64));                          \
1498 }
1499
1500 static inline uint32_t _do_evcmp_merge (int t0, int t1)
1501 {
1502     return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1503 }
1504 static inline int _do_ecmpeq (uint32_t op1, uint32_t op2)
1505 {
1506     return op1 == op2 ? 1 : 0;
1507 }
1508
1509 static inline int _do_ecmpgts (int32_t op1, int32_t op2)
1510 {
1511     return op1 > op2 ? 1 : 0;
1512 }
1513
1514 static inline int _do_ecmpgtu (uint32_t op1, uint32_t op2)
1515 {
1516     return op1 > op2 ? 1 : 0;
1517 }
1518
1519 static inline int _do_ecmplts (int32_t op1, int32_t op2)
1520 {
1521     return op1 < op2 ? 1 : 0;
1522 }
1523
1524 static inline int _do_ecmpltu (uint32_t op1, uint32_t op2)
1525 {
1526     return op1 < op2 ? 1 : 0;
1527 }
1528
1529 /* evcmpeq */
1530 DO_SPE_CMP(cmpeq);
1531 /* evcmpgts */
1532 DO_SPE_CMP(cmpgts);
1533 /* evcmpgtu */
1534 DO_SPE_CMP(cmpgtu);
1535 /* evcmplts */
1536 DO_SPE_CMP(cmplts);
1537 /* evcmpltu */
1538 DO_SPE_CMP(cmpltu);
1539
1540 /* Single precision floating-point conversions from/to integer */
1541 static inline uint32_t _do_efscfsi (int32_t val)
1542 {
1543     union {
1544         uint32_t u;
1545         float32 f;
1546     } u;
1547
1548     u.f = int32_to_float32(val, &env->spe_status);
1549
1550     return u.u;
1551 }
1552
1553 static inline uint32_t _do_efscfui (uint32_t val)
1554 {
1555     union {
1556         uint32_t u;
1557         float32 f;
1558     } u;
1559
1560     u.f = uint32_to_float32(val, &env->spe_status);
1561
1562     return u.u;
1563 }
1564
1565 static inline int32_t _do_efsctsi (uint32_t val)
1566 {
1567     union {
1568         int32_t u;
1569         float32 f;
1570     } u;
1571
1572     u.u = val;
1573     /* NaN are not treated the same way IEEE 754 does */
1574     if (unlikely(isnan(u.f)))
1575         return 0;
1576
1577     return float32_to_int32(u.f, &env->spe_status);
1578 }
1579
1580 static inline uint32_t _do_efsctui (uint32_t val)
1581 {
1582     union {
1583         int32_t u;
1584         float32 f;
1585     } u;
1586
1587     u.u = val;
1588     /* NaN are not treated the same way IEEE 754 does */
1589     if (unlikely(isnan(u.f)))
1590         return 0;
1591
1592     return float32_to_uint32(u.f, &env->spe_status);
1593 }
1594
1595 static inline int32_t _do_efsctsiz (uint32_t val)
1596 {
1597     union {
1598         int32_t u;
1599         float32 f;
1600     } u;
1601
1602     u.u = val;
1603     /* NaN are not treated the same way IEEE 754 does */
1604     if (unlikely(isnan(u.f)))
1605         return 0;
1606
1607     return float32_to_int32_round_to_zero(u.f, &env->spe_status);
1608 }
1609
1610 static inline uint32_t _do_efsctuiz (uint32_t val)
1611 {
1612     union {
1613         int32_t u;
1614         float32 f;
1615     } u;
1616
1617     u.u = val;
1618     /* NaN are not treated the same way IEEE 754 does */
1619     if (unlikely(isnan(u.f)))
1620         return 0;
1621
1622     return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
1623 }
1624
1625 void do_efscfsi (void)
1626 {
1627     T0_64 = _do_efscfsi(T0_64);
1628 }
1629
1630 void do_efscfui (void)
1631 {
1632     T0_64 = _do_efscfui(T0_64);
1633 }
1634
1635 void do_efsctsi (void)
1636 {
1637     T0_64 = _do_efsctsi(T0_64);
1638 }
1639
1640 void do_efsctui (void)
1641 {
1642     T0_64 = _do_efsctui(T0_64);
1643 }
1644
1645 void do_efsctsiz (void)
1646 {
1647     T0_64 = _do_efsctsiz(T0_64);
1648 }
1649
1650 void do_efsctuiz (void)
1651 {
1652     T0_64 = _do_efsctuiz(T0_64);
1653 }
1654
1655 /* Single precision floating-point conversion to/from fractional */
1656 static inline uint32_t _do_efscfsf (uint32_t val)
1657 {
1658     union {
1659         uint32_t u;
1660         float32 f;
1661     } u;
1662     float32 tmp;
1663
1664     u.f = int32_to_float32(val, &env->spe_status);
1665     tmp = int64_to_float32(1ULL << 32, &env->spe_status);
1666     u.f = float32_div(u.f, tmp, &env->spe_status);
1667
1668     return u.u;
1669 }
1670
1671 static inline uint32_t _do_efscfuf (uint32_t val)
1672 {
1673     union {
1674         uint32_t u;
1675         float32 f;
1676     } u;
1677     float32 tmp;
1678
1679     u.f = uint32_to_float32(val, &env->spe_status);
1680     tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1681     u.f = float32_div(u.f, tmp, &env->spe_status);
1682
1683     return u.u;
1684 }
1685
1686 static inline int32_t _do_efsctsf (uint32_t val)
1687 {
1688     union {
1689         int32_t u;
1690         float32 f;
1691     } u;
1692     float32 tmp;
1693
1694     u.u = val;
1695     /* NaN are not treated the same way IEEE 754 does */
1696     if (unlikely(isnan(u.f)))
1697         return 0;
1698     tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1699     u.f = float32_mul(u.f, tmp, &env->spe_status);
1700
1701     return float32_to_int32(u.f, &env->spe_status);
1702 }
1703
1704 static inline uint32_t _do_efsctuf (uint32_t val)
1705 {
1706     union {
1707         int32_t u;
1708         float32 f;
1709     } u;
1710     float32 tmp;
1711
1712     u.u = val;
1713     /* NaN are not treated the same way IEEE 754 does */
1714     if (unlikely(isnan(u.f)))
1715         return 0;
1716     tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1717     u.f = float32_mul(u.f, tmp, &env->spe_status);
1718
1719     return float32_to_uint32(u.f, &env->spe_status);
1720 }
1721
1722 static inline int32_t _do_efsctsfz (uint32_t val)
1723 {
1724     union {
1725         int32_t u;
1726         float32 f;
1727     } u;
1728     float32 tmp;
1729
1730     u.u = val;
1731     /* NaN are not treated the same way IEEE 754 does */
1732     if (unlikely(isnan(u.f)))
1733         return 0;
1734     tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1735     u.f = float32_mul(u.f, tmp, &env->spe_status);
1736
1737     return float32_to_int32_round_to_zero(u.f, &env->spe_status);
1738 }
1739
1740 static inline uint32_t _do_efsctufz (uint32_t val)
1741 {
1742     union {
1743         int32_t u;
1744         float32 f;
1745     } u;
1746     float32 tmp;
1747
1748     u.u = val;
1749     /* NaN are not treated the same way IEEE 754 does */
1750     if (unlikely(isnan(u.f)))
1751         return 0;
1752     tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1753     u.f = float32_mul(u.f, tmp, &env->spe_status);
1754
1755     return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
1756 }
1757
1758 void do_efscfsf (void)
1759 {
1760     T0_64 = _do_efscfsf(T0_64);
1761 }
1762
1763 void do_efscfuf (void)
1764 {
1765     T0_64 = _do_efscfuf(T0_64);
1766 }
1767
1768 void do_efsctsf (void)
1769 {
1770     T0_64 = _do_efsctsf(T0_64);
1771 }
1772
1773 void do_efsctuf (void)
1774 {
1775     T0_64 = _do_efsctuf(T0_64);
1776 }
1777
1778 void do_efsctsfz (void)
1779 {
1780     T0_64 = _do_efsctsfz(T0_64);
1781 }
1782
1783 void do_efsctufz (void)
1784 {
1785     T0_64 = _do_efsctufz(T0_64);
1786 }
1787
1788 /* Double precision floating point helpers */
1789 static inline int _do_efdcmplt (uint64_t op1, uint64_t op2)
1790 {
1791     /* XXX: TODO: test special values (NaN, infinites, ...) */
1792     return _do_efdtstlt(op1, op2);
1793 }
1794
1795 static inline int _do_efdcmpgt (uint64_t op1, uint64_t op2)
1796 {
1797     /* XXX: TODO: test special values (NaN, infinites, ...) */
1798     return _do_efdtstgt(op1, op2);
1799 }
1800
1801 static inline int _do_efdcmpeq (uint64_t op1, uint64_t op2)
1802 {
1803     /* XXX: TODO: test special values (NaN, infinites, ...) */
1804     return _do_efdtsteq(op1, op2);
1805 }
1806
1807 void do_efdcmplt (void)
1808 {
1809     T0 = _do_efdcmplt(T0_64, T1_64);
1810 }
1811
1812 void do_efdcmpgt (void)
1813 {
1814     T0 = _do_efdcmpgt(T0_64, T1_64);
1815 }
1816
1817 void do_efdcmpeq (void)
1818 {
1819     T0 = _do_efdcmpeq(T0_64, T1_64);
1820 }
1821
1822 /* Double precision floating-point conversion to/from integer */
1823 static inline uint64_t _do_efdcfsi (int64_t val)
1824 {
1825     union {
1826         uint64_t u;
1827         float64 f;
1828     } u;
1829
1830     u.f = int64_to_float64(val, &env->spe_status);
1831
1832     return u.u;
1833 }
1834
1835 static inline uint64_t _do_efdcfui (uint64_t val)
1836 {
1837     union {
1838         uint64_t u;
1839         float64 f;
1840     } u;
1841
1842     u.f = uint64_to_float64(val, &env->spe_status);
1843
1844     return u.u;
1845 }
1846
1847 static inline int64_t _do_efdctsi (uint64_t val)
1848 {
1849     union {
1850         int64_t u;
1851         float64 f;
1852     } u;
1853
1854     u.u = val;
1855     /* NaN are not treated the same way IEEE 754 does */
1856     if (unlikely(isnan(u.f)))
1857         return 0;
1858
1859     return float64_to_int64(u.f, &env->spe_status);
1860 }
1861
1862 static inline uint64_t _do_efdctui (uint64_t val)
1863 {
1864     union {
1865         int64_t u;
1866         float64 f;
1867     } u;
1868
1869     u.u = val;
1870     /* NaN are not treated the same way IEEE 754 does */
1871     if (unlikely(isnan(u.f)))
1872         return 0;
1873
1874     return float64_to_uint64(u.f, &env->spe_status);
1875 }
1876
1877 static inline int64_t _do_efdctsiz (uint64_t val)
1878 {
1879     union {
1880         int64_t u;
1881         float64 f;
1882     } u;
1883
1884     u.u = val;
1885     /* NaN are not treated the same way IEEE 754 does */
1886     if (unlikely(isnan(u.f)))
1887         return 0;
1888
1889     return float64_to_int64_round_to_zero(u.f, &env->spe_status);
1890 }
1891
1892 static inline uint64_t _do_efdctuiz (uint64_t val)
1893 {
1894     union {
1895         int64_t u;
1896         float64 f;
1897     } u;
1898
1899     u.u = val;
1900     /* NaN are not treated the same way IEEE 754 does */
1901     if (unlikely(isnan(u.f)))
1902         return 0;
1903
1904     return float64_to_uint64_round_to_zero(u.f, &env->spe_status);
1905 }
1906
1907 void do_efdcfsi (void)
1908 {
1909     T0_64 = _do_efdcfsi(T0_64);
1910 }
1911
1912 void do_efdcfui (void)
1913 {
1914     T0_64 = _do_efdcfui(T0_64);
1915 }
1916
1917 void do_efdctsi (void)
1918 {
1919     T0_64 = _do_efdctsi(T0_64);
1920 }
1921
1922 void do_efdctui (void)
1923 {
1924     T0_64 = _do_efdctui(T0_64);
1925 }
1926
1927 void do_efdctsiz (void)
1928 {
1929     T0_64 = _do_efdctsiz(T0_64);
1930 }
1931
1932 void do_efdctuiz (void)
1933 {
1934     T0_64 = _do_efdctuiz(T0_64);
1935 }
1936
1937 /* Double precision floating-point conversion to/from fractional */
1938 static inline uint64_t _do_efdcfsf (int64_t val)
1939 {
1940     union {
1941         uint64_t u;
1942         float64 f;
1943     } u;
1944     float64 tmp;
1945
1946     u.f = int32_to_float64(val, &env->spe_status);
1947     tmp = int64_to_float64(1ULL << 32, &env->spe_status);
1948     u.f = float64_div(u.f, tmp, &env->spe_status);
1949
1950     return u.u;
1951 }
1952
1953 static inline uint64_t _do_efdcfuf (uint64_t val)
1954 {
1955     union {
1956         uint64_t u;
1957         float64 f;
1958     } u;
1959     float64 tmp;
1960
1961     u.f = uint32_to_float64(val, &env->spe_status);
1962     tmp = int64_to_float64(1ULL << 32, &env->spe_status);
1963     u.f = float64_div(u.f, tmp, &env->spe_status);
1964
1965     return u.u;
1966 }
1967
1968 static inline int64_t _do_efdctsf (uint64_t val)
1969 {
1970     union {
1971         int64_t u;
1972         float64 f;
1973     } u;
1974     float64 tmp;
1975
1976     u.u = val;
1977     /* NaN are not treated the same way IEEE 754 does */
1978     if (unlikely(isnan(u.f)))
1979         return 0;
1980     tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
1981     u.f = float64_mul(u.f, tmp, &env->spe_status);
1982
1983     return float64_to_int32(u.f, &env->spe_status);
1984 }
1985
1986 static inline uint64_t _do_efdctuf (uint64_t val)
1987 {
1988     union {
1989         int64_t u;
1990         float64 f;
1991     } u;
1992     float64 tmp;
1993
1994     u.u = val;
1995     /* NaN are not treated the same way IEEE 754 does */
1996     if (unlikely(isnan(u.f)))
1997         return 0;
1998     tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
1999     u.f = float64_mul(u.f, tmp, &env->spe_status);
2000
2001     return float64_to_uint32(u.f, &env->spe_status);
2002 }
2003
2004 static inline int64_t _do_efdctsfz (uint64_t val)
2005 {
2006     union {
2007         int64_t u;
2008         float64 f;
2009     } u;
2010     float64 tmp;
2011
2012     u.u = val;
2013     /* NaN are not treated the same way IEEE 754 does */
2014     if (unlikely(isnan(u.f)))
2015         return 0;
2016     tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2017     u.f = float64_mul(u.f, tmp, &env->spe_status);
2018
2019     return float64_to_int32_round_to_zero(u.f, &env->spe_status);
2020 }
2021
2022 static inline uint64_t _do_efdctufz (uint64_t val)
2023 {
2024     union {
2025         int64_t u;
2026         float64 f;
2027     } u;
2028     float64 tmp;
2029
2030     u.u = val;
2031     /* NaN are not treated the same way IEEE 754 does */
2032     if (unlikely(isnan(u.f)))
2033         return 0;
2034     tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2035     u.f = float64_mul(u.f, tmp, &env->spe_status);
2036
2037     return float64_to_uint32_round_to_zero(u.f, &env->spe_status);
2038 }
2039
2040 void do_efdcfsf (void)
2041 {
2042     T0_64 = _do_efdcfsf(T0_64);
2043 }
2044
2045 void do_efdcfuf (void)
2046 {
2047     T0_64 = _do_efdcfuf(T0_64);
2048 }
2049
2050 void do_efdctsf (void)
2051 {
2052     T0_64 = _do_efdctsf(T0_64);
2053 }
2054
2055 void do_efdctuf (void)
2056 {
2057     T0_64 = _do_efdctuf(T0_64);
2058 }
2059
2060 void do_efdctsfz (void)
2061 {
2062     T0_64 = _do_efdctsfz(T0_64);
2063 }
2064
2065 void do_efdctufz (void)
2066 {
2067     T0_64 = _do_efdctufz(T0_64);
2068 }
2069
2070 /* Floating point conversion between single and double precision */
2071 static inline uint32_t _do_efscfd (uint64_t val)
2072 {
2073     union {
2074         uint64_t u;
2075         float64 f;
2076     } u1;
2077     union {
2078         uint32_t u;
2079         float32 f;
2080     } u2;
2081
2082     u1.u = val;
2083     u2.f = float64_to_float32(u1.f, &env->spe_status);
2084
2085     return u2.u;
2086 }
2087
2088 static inline uint64_t _do_efdcfs (uint32_t val)
2089 {
2090     union {
2091         uint64_t u;
2092         float64 f;
2093     } u2;
2094     union {
2095         uint32_t u;
2096         float32 f;
2097     } u1;
2098
2099     u1.u = val;
2100     u2.f = float32_to_float64(u1.f, &env->spe_status);
2101
2102     return u2.u;
2103 }
2104
2105 void do_efscfd (void)
2106 {
2107     T0_64 = _do_efscfd(T0_64);
2108 }
2109
2110 void do_efdcfs (void)
2111 {
2112     T0_64 = _do_efdcfs(T0_64);
2113 }
2114
2115 /* Single precision fixed-point vector arithmetic */
2116 /* evfsabs */
2117 DO_SPE_OP1(fsabs);
2118 /* evfsnabs */
2119 DO_SPE_OP1(fsnabs);
2120 /* evfsneg */
2121 DO_SPE_OP1(fsneg);
2122 /* evfsadd */
2123 DO_SPE_OP2(fsadd);
2124 /* evfssub */
2125 DO_SPE_OP2(fssub);
2126 /* evfsmul */
2127 DO_SPE_OP2(fsmul);
2128 /* evfsdiv */
2129 DO_SPE_OP2(fsdiv);
2130
2131 /* Single-precision floating-point comparisons */
2132 static inline int _do_efscmplt (uint32_t op1, uint32_t op2)
2133 {
2134     /* XXX: TODO: test special values (NaN, infinites, ...) */
2135     return _do_efststlt(op1, op2);
2136 }
2137
2138 static inline int _do_efscmpgt (uint32_t op1, uint32_t op2)
2139 {
2140     /* XXX: TODO: test special values (NaN, infinites, ...) */
2141     return _do_efststgt(op1, op2);
2142 }
2143
2144 static inline int _do_efscmpeq (uint32_t op1, uint32_t op2)
2145 {
2146     /* XXX: TODO: test special values (NaN, infinites, ...) */
2147     return _do_efststeq(op1, op2);
2148 }
2149
2150 void do_efscmplt (void)
2151 {
2152     T0 = _do_efscmplt(T0_64, T1_64);
2153 }
2154
2155 void do_efscmpgt (void)
2156 {
2157     T0 = _do_efscmpgt(T0_64, T1_64);
2158 }
2159
2160 void do_efscmpeq (void)
2161 {
2162     T0 = _do_efscmpeq(T0_64, T1_64);
2163 }
2164
2165 /* Single-precision floating-point vector comparisons */
2166 /* evfscmplt */
2167 DO_SPE_CMP(fscmplt);
2168 /* evfscmpgt */
2169 DO_SPE_CMP(fscmpgt);
2170 /* evfscmpeq */
2171 DO_SPE_CMP(fscmpeq);
2172 /* evfststlt */
2173 DO_SPE_CMP(fststlt);
2174 /* evfststgt */
2175 DO_SPE_CMP(fststgt);
2176 /* evfststeq */
2177 DO_SPE_CMP(fststeq);
2178
2179 /* Single-precision floating-point vector conversions */
2180 /* evfscfsi */
2181 DO_SPE_OP1(fscfsi);
2182 /* evfscfui */
2183 DO_SPE_OP1(fscfui);
2184 /* evfscfuf */
2185 DO_SPE_OP1(fscfuf);
2186 /* evfscfsf */
2187 DO_SPE_OP1(fscfsf);
2188 /* evfsctsi */
2189 DO_SPE_OP1(fsctsi);
2190 /* evfsctui */
2191 DO_SPE_OP1(fsctui);
2192 /* evfsctsiz */
2193 DO_SPE_OP1(fsctsiz);
2194 /* evfsctuiz */
2195 DO_SPE_OP1(fsctuiz);
2196 /* evfsctsf */
2197 DO_SPE_OP1(fsctsf);
2198 /* evfsctuf */
2199 DO_SPE_OP1(fsctuf);
2200 #endif /* defined(TARGET_PPCEMB) */
2201
2202 /*****************************************************************************/
2203 /* Softmmu support */
2204 #if !defined (CONFIG_USER_ONLY)
2205
2206 #define MMUSUFFIX _mmu
2207 #define GETPC() (__builtin_return_address(0))
2208
2209 #define SHIFT 0
2210 #include "softmmu_template.h"
2211
2212 #define SHIFT 1
2213 #include "softmmu_template.h"
2214
2215 #define SHIFT 2
2216 #include "softmmu_template.h"
2217
2218 #define SHIFT 3
2219 #include "softmmu_template.h"
2220
2221 /* try to fill the TLB and return an exception if error. If retaddr is
2222    NULL, it means that the function was called in C code (i.e. not
2223    from generated code or from helper.c) */
2224 /* XXX: fix it to restore all registers */
2225 void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
2226 {
2227     TranslationBlock *tb;
2228     CPUState *saved_env;
2229     target_phys_addr_t pc;
2230     int ret;
2231
2232     /* XXX: hack to restore env in all cases, even if not called from
2233        generated code */
2234     saved_env = env;
2235     env = cpu_single_env;
2236     ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
2237     if (unlikely(ret != 0)) {
2238         if (likely(retaddr)) {
2239             /* now we have a real cpu fault */
2240             pc = (target_phys_addr_t)retaddr;
2241             tb = tb_find_pc(pc);
2242             if (likely(tb)) {
2243                 /* the PC is inside the translated code. It means that we have
2244                    a virtual CPU fault */
2245                 cpu_restore_state(tb, env, pc, NULL);
2246             }
2247         }
2248         do_raise_exception_err(env->exception_index, env->error_code);
2249     }
2250     env = saved_env;
2251 }
2252
2253 /* TLB invalidation helpers */
2254 void do_tlbia (void)
2255 {
2256     ppc_tlb_invalidate_all(env);
2257 }
2258
2259 void do_tlbie (void)
2260 {
2261     T0 = (uint32_t)T0;
2262 #if !defined(FLUSH_ALL_TLBS)
2263     if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
2264         ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 0);
2265         if (env->id_tlbs == 1)
2266             ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 1);
2267     } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
2268         /* XXX: TODO */
2269 #if 0
2270         ppcbooke_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK,
2271                                      env->spr[SPR_BOOKE_PID]);
2272 #endif
2273     } else {
2274         /* tlbie invalidate TLBs for all segments */
2275         T0 &= TARGET_PAGE_MASK;
2276         T0 &= ~((target_ulong)-1 << 28);
2277         /* XXX: this case should be optimized,
2278          * giving a mask to tlb_flush_page
2279          */
2280         tlb_flush_page(env, T0 | (0x0 << 28));
2281         tlb_flush_page(env, T0 | (0x1 << 28));
2282         tlb_flush_page(env, T0 | (0x2 << 28));
2283         tlb_flush_page(env, T0 | (0x3 << 28));
2284         tlb_flush_page(env, T0 | (0x4 << 28));
2285         tlb_flush_page(env, T0 | (0x5 << 28));
2286         tlb_flush_page(env, T0 | (0x6 << 28));
2287         tlb_flush_page(env, T0 | (0x7 << 28));
2288         tlb_flush_page(env, T0 | (0x8 << 28));
2289         tlb_flush_page(env, T0 | (0x9 << 28));
2290         tlb_flush_page(env, T0 | (0xA << 28));
2291         tlb_flush_page(env, T0 | (0xB << 28));
2292         tlb_flush_page(env, T0 | (0xC << 28));
2293         tlb_flush_page(env, T0 | (0xD << 28));
2294         tlb_flush_page(env, T0 | (0xE << 28));
2295         tlb_flush_page(env, T0 | (0xF << 28));
2296     }
2297 #else
2298     do_tlbia();
2299 #endif
2300 }
2301
2302 #if defined(TARGET_PPC64)
2303 void do_tlbie_64 (void)
2304 {
2305     T0 = (uint64_t)T0;
2306 #if !defined(FLUSH_ALL_TLBS)
2307     if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
2308         ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 0);
2309         if (env->id_tlbs == 1)
2310             ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 1);
2311     } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
2312         /* XXX: TODO */
2313 #if 0
2314         ppcbooke_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK,
2315                                      env->spr[SPR_BOOKE_PID]);
2316 #endif
2317     } else {
2318         /* tlbie invalidate TLBs for all segments
2319          * As we have 2^36 segments, invalidate all qemu TLBs
2320          */
2321 #if 0
2322         T0 &= TARGET_PAGE_MASK;
2323         T0 &= ~((target_ulong)-1 << 28);
2324         /* XXX: this case should be optimized,
2325          * giving a mask to tlb_flush_page
2326          */
2327         tlb_flush_page(env, T0 | (0x0 << 28));
2328         tlb_flush_page(env, T0 | (0x1 << 28));
2329         tlb_flush_page(env, T0 | (0x2 << 28));
2330         tlb_flush_page(env, T0 | (0x3 << 28));
2331         tlb_flush_page(env, T0 | (0x4 << 28));
2332         tlb_flush_page(env, T0 | (0x5 << 28));
2333         tlb_flush_page(env, T0 | (0x6 << 28));
2334         tlb_flush_page(env, T0 | (0x7 << 28));
2335         tlb_flush_page(env, T0 | (0x8 << 28));
2336         tlb_flush_page(env, T0 | (0x9 << 28));
2337         tlb_flush_page(env, T0 | (0xA << 28));
2338         tlb_flush_page(env, T0 | (0xB << 28));
2339         tlb_flush_page(env, T0 | (0xC << 28));
2340         tlb_flush_page(env, T0 | (0xD << 28));
2341         tlb_flush_page(env, T0 | (0xE << 28));
2342         tlb_flush_page(env, T0 | (0xF << 28));
2343 #else
2344         tlb_flush(env, 1);
2345 #endif
2346     }
2347 #else
2348     do_tlbia();
2349 #endif
2350 }
2351 #endif
2352
2353 #if defined(TARGET_PPC64)
2354 void do_slbia (void)
2355 {
2356     /* XXX: TODO */
2357     tlb_flush(env, 1);
2358 }
2359
2360 void do_slbie (void)
2361 {
2362     /* XXX: TODO */
2363     tlb_flush(env, 1);
2364 }
2365 #endif
2366
2367 /* Software driven TLBs management */
2368 /* PowerPC 602/603 software TLB load instructions helpers */
2369 void do_load_6xx_tlb (int is_code)
2370 {
2371     target_ulong RPN, CMP, EPN;
2372     int way;
2373
2374     RPN = env->spr[SPR_RPA];
2375     if (is_code) {
2376         CMP = env->spr[SPR_ICMP];
2377         EPN = env->spr[SPR_IMISS];
2378     } else {
2379         CMP = env->spr[SPR_DCMP];
2380         EPN = env->spr[SPR_DMISS];
2381     }
2382     way = (env->spr[SPR_SRR1] >> 17) & 1;
2383 #if defined (DEBUG_SOFTWARE_TLB)
2384     if (loglevel != 0) {
2385         fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
2386                 __func__, (unsigned long)T0, (unsigned long)EPN,
2387                 (unsigned long)CMP, (unsigned long)RPN, way);
2388     }
2389 #endif
2390     /* Store this TLB */
2391     ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2392                      way, is_code, CMP, RPN);
2393 }
2394
2395 static target_ulong booke_tlb_to_page_size (int size)
2396 {
2397     return 1024 << (2 * size);
2398 }
2399
2400 static int booke_page_size_to_tlb (target_ulong page_size)
2401 {
2402     int size;
2403
2404     switch (page_size) {
2405     case 0x00000400UL:
2406         size = 0x0;
2407         break;
2408     case 0x00001000UL:
2409         size = 0x1;
2410         break;
2411     case 0x00004000UL:
2412         size = 0x2;
2413         break;
2414     case 0x00010000UL:
2415         size = 0x3;
2416         break;
2417     case 0x00040000UL:
2418         size = 0x4;
2419         break;
2420     case 0x00100000UL:
2421         size = 0x5;
2422         break;
2423     case 0x00400000UL:
2424         size = 0x6;
2425         break;
2426     case 0x01000000UL:
2427         size = 0x7;
2428         break;
2429     case 0x04000000UL:
2430         size = 0x8;
2431         break;
2432     case 0x10000000UL:
2433         size = 0x9;
2434         break;
2435     case 0x40000000UL:
2436         size = 0xA;
2437         break;
2438 #if defined (TARGET_PPC64)
2439     case 0x000100000000ULL:
2440         size = 0xB;
2441         break;
2442     case 0x000400000000ULL:
2443         size = 0xC;
2444         break;
2445     case 0x001000000000ULL:
2446         size = 0xD;
2447         break;
2448     case 0x004000000000ULL:
2449         size = 0xE;
2450         break;
2451     case 0x010000000000ULL:
2452         size = 0xF;
2453         break;
2454 #endif
2455     default:
2456         size = -1;
2457         break;
2458     }
2459
2460     return size;
2461 }
2462
2463 /* Helpers for 4xx TLB management */
2464 void do_4xx_tlbre_lo (void)
2465 {
2466     ppcemb_tlb_t *tlb;
2467     int size;
2468
2469     T0 &= 0x3F;
2470     tlb = &env->tlb[T0].tlbe;
2471     T0 = tlb->EPN;
2472     if (tlb->prot & PAGE_VALID)
2473         T0 |= 0x400;
2474     size = booke_page_size_to_tlb(tlb->size);
2475     if (size < 0 || size > 0x7)
2476         size = 1;
2477     T0 |= size << 7;
2478     env->spr[SPR_40x_PID] = tlb->PID;
2479 }
2480
2481 void do_4xx_tlbre_hi (void)
2482 {
2483     ppcemb_tlb_t *tlb;
2484
2485     T0 &= 0x3F;
2486     tlb = &env->tlb[T0].tlbe;
2487     T0 = tlb->RPN;
2488     if (tlb->prot & PAGE_EXEC)
2489         T0 |= 0x200;
2490     if (tlb->prot & PAGE_WRITE)
2491         T0 |= 0x100;
2492 }
2493
2494 void do_4xx_tlbsx (void)
2495 {
2496     T0 = ppcemb_tlb_search(env, T0);
2497 }
2498
2499 void do_4xx_tlbsx_ (void)
2500 {
2501     int tmp = xer_ov;
2502
2503     T0 = ppcemb_tlb_search(env, T0);
2504     if (T0 != -1)
2505         tmp |= 0x02;
2506     env->crf[0] = tmp;
2507 }
2508
2509 void do_4xx_tlbwe_hi (void)
2510 {
2511     ppcemb_tlb_t *tlb;
2512     target_ulong page, end;
2513
2514 #if defined (DEBUG_SOFTWARE_TLB)
2515     if (loglevel != 0) {
2516         fprintf(logfile, "%s T0 " REGX " T1 " REGX "\n", __func__, T0, T1);
2517     }
2518 #endif
2519     T0 &= 0x3F;
2520     tlb = &env->tlb[T0].tlbe;
2521     /* Invalidate previous TLB (if it's valid) */
2522     if (tlb->prot & PAGE_VALID) {
2523         end = tlb->EPN + tlb->size;
2524 #if defined (DEBUG_SOFTWARE_TLB)
2525         if (loglevel != 0) {
2526             fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2527                     " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2528         }
2529 #endif
2530         for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2531             tlb_flush_page(env, page);
2532     }
2533     tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7);
2534     /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2535      * If this ever occurs, one should use the ppcemb target instead
2536      * of the ppc or ppc64 one
2537      */
2538     if ((T1 & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
2539         cpu_abort(env, "TLB size %u < %u are not supported (%d)\n",
2540                   tlb->size, TARGET_PAGE_SIZE, (int)((T1 >> 7) & 0x7));
2541     }
2542     tlb->EPN = (T1 & 0xFFFFFC00) & ~(tlb->size - 1);
2543     if (T1 & 0x40)
2544         tlb->prot |= PAGE_VALID;
2545     else
2546         tlb->prot &= ~PAGE_VALID;
2547     if (T1 & 0x20) {
2548         /* XXX: TO BE FIXED */
2549         cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2550     }
2551     tlb->PID = env->spr[SPR_40x_PID]; /* PID */
2552     tlb->attr = T1 & 0xFF;
2553 #if defined (DEBUG_SOFTWARE_TLB)
2554     if (loglevel != 0) {
2555         fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2556                 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2557                 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2558                 tlb->prot & PAGE_READ ? 'r' : '-',
2559                 tlb->prot & PAGE_WRITE ? 'w' : '-',
2560                 tlb->prot & PAGE_EXEC ? 'x' : '-',
2561                 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2562     }
2563 #endif
2564     /* Invalidate new TLB (if valid) */
2565     if (tlb->prot & PAGE_VALID) {
2566         end = tlb->EPN + tlb->size;
2567 #if defined (DEBUG_SOFTWARE_TLB)
2568         if (loglevel != 0) {
2569             fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2570                     " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2571         }
2572 #endif
2573         for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2574             tlb_flush_page(env, page);
2575     }
2576 }
2577
2578 void do_4xx_tlbwe_lo (void)
2579 {
2580     ppcemb_tlb_t *tlb;
2581
2582 #if defined (DEBUG_SOFTWARE_TLB)
2583     if (loglevel != 0) {
2584         fprintf(logfile, "%s T0 " REGX " T1 " REGX "\n", __func__, T0, T1);
2585     }
2586 #endif
2587     T0 &= 0x3F;
2588     tlb = &env->tlb[T0].tlbe;
2589     tlb->RPN = T1 & 0xFFFFFC00;
2590     tlb->prot = PAGE_READ;
2591     if (T1 & 0x200)
2592         tlb->prot |= PAGE_EXEC;
2593     if (T1 & 0x100)
2594         tlb->prot |= PAGE_WRITE;
2595 #if defined (DEBUG_SOFTWARE_TLB)
2596     if (loglevel != 0) {
2597         fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2598                 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2599                 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2600                 tlb->prot & PAGE_READ ? 'r' : '-',
2601                 tlb->prot & PAGE_WRITE ? 'w' : '-',
2602                 tlb->prot & PAGE_EXEC ? 'x' : '-',
2603                 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2604     }
2605 #endif
2606 }
2607 #endif /* !CONFIG_USER_ONLY */