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[mirror_qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91 tcg_ctx.tcg_env = cpu_env;
92
93 p = cpu_reg_names;
94 cpu_reg_names_size = sizeof(cpu_reg_names);
95
96 for (i = 0; i < 8; i++) {
97 snprintf(p, cpu_reg_names_size, "crf%d", i);
98 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
99 offsetof(CPUPPCState, crf[i]), p);
100 p += 5;
101 cpu_reg_names_size -= 5;
102 }
103
104 for (i = 0; i < 32; i++) {
105 snprintf(p, cpu_reg_names_size, "r%d", i);
106 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gpr[i]), p);
108 p += (i < 10) ? 3 : 4;
109 cpu_reg_names_size -= (i < 10) ? 3 : 4;
110 snprintf(p, cpu_reg_names_size, "r%dH", i);
111 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
112 offsetof(CPUPPCState, gprh[i]), p);
113 p += (i < 10) ? 4 : 5;
114 cpu_reg_names_size -= (i < 10) ? 4 : 5;
115
116 snprintf(p, cpu_reg_names_size, "fp%d", i);
117 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
118 offsetof(CPUPPCState, fpr[i]), p);
119 p += (i < 10) ? 4 : 5;
120 cpu_reg_names_size -= (i < 10) ? 4 : 5;
121
122 snprintf(p, cpu_reg_names_size, "avr%dH", i);
123 #ifdef HOST_WORDS_BIGENDIAN
124 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
125 offsetof(CPUPPCState, avr[i].u64[0]), p);
126 #else
127 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
128 offsetof(CPUPPCState, avr[i].u64[1]), p);
129 #endif
130 p += (i < 10) ? 6 : 7;
131 cpu_reg_names_size -= (i < 10) ? 6 : 7;
132
133 snprintf(p, cpu_reg_names_size, "avr%dL", i);
134 #ifdef HOST_WORDS_BIGENDIAN
135 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
136 offsetof(CPUPPCState, avr[i].u64[1]), p);
137 #else
138 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
139 offsetof(CPUPPCState, avr[i].u64[0]), p);
140 #endif
141 p += (i < 10) ? 6 : 7;
142 cpu_reg_names_size -= (i < 10) ? 6 : 7;
143 snprintf(p, cpu_reg_names_size, "vsr%d", i);
144 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
145 offsetof(CPUPPCState, vsr[i]), p);
146 p += (i < 10) ? 5 : 6;
147 cpu_reg_names_size -= (i < 10) ? 5 : 6;
148 }
149
150 cpu_nip = tcg_global_mem_new(cpu_env,
151 offsetof(CPUPPCState, nip), "nip");
152
153 cpu_msr = tcg_global_mem_new(cpu_env,
154 offsetof(CPUPPCState, msr), "msr");
155
156 cpu_ctr = tcg_global_mem_new(cpu_env,
157 offsetof(CPUPPCState, ctr), "ctr");
158
159 cpu_lr = tcg_global_mem_new(cpu_env,
160 offsetof(CPUPPCState, lr), "lr");
161
162 #if defined(TARGET_PPC64)
163 cpu_cfar = tcg_global_mem_new(cpu_env,
164 offsetof(CPUPPCState, cfar), "cfar");
165 #endif
166
167 cpu_xer = tcg_global_mem_new(cpu_env,
168 offsetof(CPUPPCState, xer), "xer");
169 cpu_so = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, so), "SO");
171 cpu_ov = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, ov), "OV");
173 cpu_ca = tcg_global_mem_new(cpu_env,
174 offsetof(CPUPPCState, ca), "CA");
175
176 cpu_reserve = tcg_global_mem_new(cpu_env,
177 offsetof(CPUPPCState, reserve_addr),
178 "reserve_addr");
179
180 cpu_fpscr = tcg_global_mem_new(cpu_env,
181 offsetof(CPUPPCState, fpscr), "fpscr");
182
183 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
184 offsetof(CPUPPCState, access_type), "access_type");
185
186 done_init = 1;
187 }
188
189 /* internal defines */
190 struct DisasContext {
191 struct TranslationBlock *tb;
192 target_ulong nip;
193 uint32_t opcode;
194 uint32_t exception;
195 /* Routine used to access memory */
196 bool pr, hv, dr, le_mode;
197 bool lazy_tlb_flush;
198 int mem_idx;
199 int access_type;
200 /* Translation flags */
201 TCGMemOp default_tcg_memop_mask;
202 #if defined(TARGET_PPC64)
203 bool sf_mode;
204 bool has_cfar;
205 #endif
206 bool fpu_enabled;
207 bool altivec_enabled;
208 bool vsx_enabled;
209 bool spe_enabled;
210 bool tm_enabled;
211 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
212 int singlestep_enabled;
213 uint64_t insns_flags;
214 uint64_t insns_flags2;
215 };
216
217 /* Return true iff byteswap is needed in a scalar memop */
218 static inline bool need_byteswap(const DisasContext *ctx)
219 {
220 #if defined(TARGET_WORDS_BIGENDIAN)
221 return ctx->le_mode;
222 #else
223 return !ctx->le_mode;
224 #endif
225 }
226
227 /* True when active word size < size of target_long. */
228 #ifdef TARGET_PPC64
229 # define NARROW_MODE(C) (!(C)->sf_mode)
230 #else
231 # define NARROW_MODE(C) 0
232 #endif
233
234 struct opc_handler_t {
235 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
236 uint32_t inval1;
237 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
238 uint32_t inval2;
239 /* instruction type */
240 uint64_t type;
241 /* extended instruction type */
242 uint64_t type2;
243 /* handler */
244 void (*handler)(DisasContext *ctx);
245 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
246 const char *oname;
247 #endif
248 #if defined(DO_PPC_STATISTICS)
249 uint64_t count;
250 #endif
251 };
252
253 static inline void gen_reset_fpstatus(void)
254 {
255 gen_helper_reset_fpstatus(cpu_env);
256 }
257
258 static inline void gen_compute_fprf(TCGv_i64 arg)
259 {
260 gen_helper_compute_fprf(cpu_env, arg);
261 gen_helper_float_check_status(cpu_env);
262 }
263
264 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
265 {
266 if (ctx->access_type != access_type) {
267 tcg_gen_movi_i32(cpu_access_type, access_type);
268 ctx->access_type = access_type;
269 }
270 }
271
272 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
273 {
274 if (NARROW_MODE(ctx)) {
275 nip = (uint32_t)nip;
276 }
277 tcg_gen_movi_tl(cpu_nip, nip);
278 }
279
280 void gen_update_current_nip(void *opaque)
281 {
282 DisasContext *ctx = opaque;
283
284 tcg_gen_movi_tl(cpu_nip, ctx->nip);
285 }
286
287 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
288 {
289 TCGv_i32 t0, t1;
290 if (ctx->exception == POWERPC_EXCP_NONE) {
291 gen_update_nip(ctx, ctx->nip);
292 }
293 t0 = tcg_const_i32(excp);
294 t1 = tcg_const_i32(error);
295 gen_helper_raise_exception_err(cpu_env, t0, t1);
296 tcg_temp_free_i32(t0);
297 tcg_temp_free_i32(t1);
298 ctx->exception = (excp);
299 }
300
301 static void gen_exception(DisasContext *ctx, uint32_t excp)
302 {
303 TCGv_i32 t0;
304 if (ctx->exception == POWERPC_EXCP_NONE) {
305 gen_update_nip(ctx, ctx->nip);
306 }
307 t0 = tcg_const_i32(excp);
308 gen_helper_raise_exception(cpu_env, t0);
309 tcg_temp_free_i32(t0);
310 ctx->exception = (excp);
311 }
312
313 static void gen_debug_exception(DisasContext *ctx)
314 {
315 TCGv_i32 t0;
316
317 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
318 (ctx->exception != POWERPC_EXCP_SYNC)) {
319 gen_update_nip(ctx, ctx->nip);
320 }
321 t0 = tcg_const_i32(EXCP_DEBUG);
322 gen_helper_raise_exception(cpu_env, t0);
323 tcg_temp_free_i32(t0);
324 }
325
326 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
327 {
328 /* Will be converted to program check if needed */
329 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
330 }
331
332 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
333 {
334 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
335 }
336
337 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
338 {
339 /* Will be converted to program check if needed */
340 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
341 }
342
343 /* Stop translation */
344 static inline void gen_stop_exception(DisasContext *ctx)
345 {
346 gen_update_nip(ctx, ctx->nip);
347 ctx->exception = POWERPC_EXCP_STOP;
348 }
349
350 #ifndef CONFIG_USER_ONLY
351 /* No need to update nip here, as execution flow will change */
352 static inline void gen_sync_exception(DisasContext *ctx)
353 {
354 ctx->exception = POWERPC_EXCP_SYNC;
355 }
356 #endif
357
358 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
359 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
360
361 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
362 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
363
364 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
365 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
366
367 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
368 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
369
370 typedef struct opcode_t {
371 unsigned char opc1, opc2, opc3;
372 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
373 unsigned char pad[5];
374 #else
375 unsigned char pad[1];
376 #endif
377 opc_handler_t handler;
378 const char *oname;
379 } opcode_t;
380
381 /* Helpers for priv. check */
382 #define GEN_PRIV \
383 do { \
384 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
385 } while (0)
386
387 #if defined(CONFIG_USER_ONLY)
388 #define CHK_HV GEN_PRIV
389 #define CHK_SV GEN_PRIV
390 #define CHK_HVRM GEN_PRIV
391 #else
392 #define CHK_HV \
393 do { \
394 if (unlikely(ctx->pr || !ctx->hv)) { \
395 GEN_PRIV; \
396 } \
397 } while (0)
398 #define CHK_SV \
399 do { \
400 if (unlikely(ctx->pr)) { \
401 GEN_PRIV; \
402 } \
403 } while (0)
404 #define CHK_HVRM \
405 do { \
406 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
407 GEN_PRIV; \
408 } \
409 } while (0)
410 #endif
411
412 #define CHK_NONE
413
414
415 /*****************************************************************************/
416 /*** Instruction decoding ***/
417 #define EXTRACT_HELPER(name, shift, nb) \
418 static inline uint32_t name(uint32_t opcode) \
419 { \
420 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
421 }
422
423 #define EXTRACT_SHELPER(name, shift, nb) \
424 static inline int32_t name(uint32_t opcode) \
425 { \
426 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
427 }
428
429 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
430 static inline uint32_t name(uint32_t opcode) \
431 { \
432 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
433 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
434 }
435
436 #define EXTRACT_HELPER_DXFORM(name, \
437 d0_bits, shift_op_d0, shift_d0, \
438 d1_bits, shift_op_d1, shift_d1, \
439 d2_bits, shift_op_d2, shift_d2) \
440 static inline int16_t name(uint32_t opcode) \
441 { \
442 return \
443 (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
444 (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
445 (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2)); \
446 }
447
448
449 /* Opcode part 1 */
450 EXTRACT_HELPER(opc1, 26, 6);
451 /* Opcode part 2 */
452 EXTRACT_HELPER(opc2, 1, 5);
453 /* Opcode part 3 */
454 EXTRACT_HELPER(opc3, 6, 5);
455 /* Update Cr0 flags */
456 EXTRACT_HELPER(Rc, 0, 1);
457 /* Update Cr6 flags (Altivec) */
458 EXTRACT_HELPER(Rc21, 10, 1);
459 /* Destination */
460 EXTRACT_HELPER(rD, 21, 5);
461 /* Source */
462 EXTRACT_HELPER(rS, 21, 5);
463 /* First operand */
464 EXTRACT_HELPER(rA, 16, 5);
465 /* Second operand */
466 EXTRACT_HELPER(rB, 11, 5);
467 /* Third operand */
468 EXTRACT_HELPER(rC, 6, 5);
469 /*** Get CRn ***/
470 EXTRACT_HELPER(crfD, 23, 3);
471 EXTRACT_HELPER(crfS, 18, 3);
472 EXTRACT_HELPER(crbD, 21, 5);
473 EXTRACT_HELPER(crbA, 16, 5);
474 EXTRACT_HELPER(crbB, 11, 5);
475 /* SPR / TBL */
476 EXTRACT_HELPER(_SPR, 11, 10);
477 static inline uint32_t SPR(uint32_t opcode)
478 {
479 uint32_t sprn = _SPR(opcode);
480
481 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
482 }
483 /*** Get constants ***/
484 /* 16 bits signed immediate value */
485 EXTRACT_SHELPER(SIMM, 0, 16);
486 /* 16 bits unsigned immediate value */
487 EXTRACT_HELPER(UIMM, 0, 16);
488 /* 5 bits signed immediate value */
489 EXTRACT_HELPER(SIMM5, 16, 5);
490 /* 5 bits signed immediate value */
491 EXTRACT_HELPER(UIMM5, 16, 5);
492 /* Bit count */
493 EXTRACT_HELPER(NB, 11, 5);
494 /* Shift count */
495 EXTRACT_HELPER(SH, 11, 5);
496 /* Vector shift count */
497 EXTRACT_HELPER(VSH, 6, 4);
498 /* Mask start */
499 EXTRACT_HELPER(MB, 6, 5);
500 /* Mask end */
501 EXTRACT_HELPER(ME, 1, 5);
502 /* Trap operand */
503 EXTRACT_HELPER(TO, 21, 5);
504
505 EXTRACT_HELPER(CRM, 12, 8);
506
507 #ifndef CONFIG_USER_ONLY
508 EXTRACT_HELPER(SR, 16, 4);
509 #endif
510
511 /* mtfsf/mtfsfi */
512 EXTRACT_HELPER(FPBF, 23, 3);
513 EXTRACT_HELPER(FPIMM, 12, 4);
514 EXTRACT_HELPER(FPL, 25, 1);
515 EXTRACT_HELPER(FPFLM, 17, 8);
516 EXTRACT_HELPER(FPW, 16, 1);
517
518 /* addpcis */
519 EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
520
521 /*** Jump target decoding ***/
522 /* Immediate address */
523 static inline target_ulong LI(uint32_t opcode)
524 {
525 return (opcode >> 0) & 0x03FFFFFC;
526 }
527
528 static inline uint32_t BD(uint32_t opcode)
529 {
530 return (opcode >> 0) & 0xFFFC;
531 }
532
533 EXTRACT_HELPER(BO, 21, 5);
534 EXTRACT_HELPER(BI, 16, 5);
535 /* Absolute/relative address */
536 EXTRACT_HELPER(AA, 1, 1);
537 /* Link */
538 EXTRACT_HELPER(LK, 0, 1);
539
540 /* DFP Z22-form */
541 EXTRACT_HELPER(DCM, 10, 6)
542
543 /* DFP Z23-form */
544 EXTRACT_HELPER(RMC, 9, 2)
545
546 /* Create a mask between <start> and <end> bits */
547 static inline target_ulong MASK(uint32_t start, uint32_t end)
548 {
549 target_ulong ret;
550
551 #if defined(TARGET_PPC64)
552 if (likely(start == 0)) {
553 ret = UINT64_MAX << (63 - end);
554 } else if (likely(end == 63)) {
555 ret = UINT64_MAX >> start;
556 }
557 #else
558 if (likely(start == 0)) {
559 ret = UINT32_MAX << (31 - end);
560 } else if (likely(end == 31)) {
561 ret = UINT32_MAX >> start;
562 }
563 #endif
564 else {
565 ret = (((target_ulong)(-1ULL)) >> (start)) ^
566 (((target_ulong)(-1ULL) >> (end)) >> 1);
567 if (unlikely(start > end))
568 return ~ret;
569 }
570
571 return ret;
572 }
573
574 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
575 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
576 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
577 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
578 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
579 EXTRACT_HELPER(DM, 8, 2);
580 EXTRACT_HELPER(UIM, 16, 2);
581 EXTRACT_HELPER(SHW, 8, 2);
582 EXTRACT_HELPER(SP, 19, 2);
583 /*****************************************************************************/
584 /* PowerPC instructions table */
585
586 #if defined(DO_PPC_STATISTICS)
587 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
588 { \
589 .opc1 = op1, \
590 .opc2 = op2, \
591 .opc3 = op3, \
592 .pad = { 0, }, \
593 .handler = { \
594 .inval1 = invl, \
595 .type = _typ, \
596 .type2 = _typ2, \
597 .handler = &gen_##name, \
598 .oname = stringify(name), \
599 }, \
600 .oname = stringify(name), \
601 }
602 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
603 { \
604 .opc1 = op1, \
605 .opc2 = op2, \
606 .opc3 = op3, \
607 .pad = { 0, }, \
608 .handler = { \
609 .inval1 = invl1, \
610 .inval2 = invl2, \
611 .type = _typ, \
612 .type2 = _typ2, \
613 .handler = &gen_##name, \
614 .oname = stringify(name), \
615 }, \
616 .oname = stringify(name), \
617 }
618 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
619 { \
620 .opc1 = op1, \
621 .opc2 = op2, \
622 .opc3 = op3, \
623 .pad = { 0, }, \
624 .handler = { \
625 .inval1 = invl, \
626 .type = _typ, \
627 .type2 = _typ2, \
628 .handler = &gen_##name, \
629 .oname = onam, \
630 }, \
631 .oname = onam, \
632 }
633 #else
634 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
635 { \
636 .opc1 = op1, \
637 .opc2 = op2, \
638 .opc3 = op3, \
639 .pad = { 0, }, \
640 .handler = { \
641 .inval1 = invl, \
642 .type = _typ, \
643 .type2 = _typ2, \
644 .handler = &gen_##name, \
645 }, \
646 .oname = stringify(name), \
647 }
648 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
649 { \
650 .opc1 = op1, \
651 .opc2 = op2, \
652 .opc3 = op3, \
653 .pad = { 0, }, \
654 .handler = { \
655 .inval1 = invl1, \
656 .inval2 = invl2, \
657 .type = _typ, \
658 .type2 = _typ2, \
659 .handler = &gen_##name, \
660 }, \
661 .oname = stringify(name), \
662 }
663 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
664 { \
665 .opc1 = op1, \
666 .opc2 = op2, \
667 .opc3 = op3, \
668 .pad = { 0, }, \
669 .handler = { \
670 .inval1 = invl, \
671 .type = _typ, \
672 .type2 = _typ2, \
673 .handler = &gen_##name, \
674 }, \
675 .oname = onam, \
676 }
677 #endif
678
679 /* SPR load/store helpers */
680 static inline void gen_load_spr(TCGv t, int reg)
681 {
682 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
683 }
684
685 static inline void gen_store_spr(int reg, TCGv t)
686 {
687 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
688 }
689
690 /* Invalid instruction */
691 static void gen_invalid(DisasContext *ctx)
692 {
693 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
694 }
695
696 static opc_handler_t invalid_handler = {
697 .inval1 = 0xFFFFFFFF,
698 .inval2 = 0xFFFFFFFF,
699 .type = PPC_NONE,
700 .type2 = PPC_NONE,
701 .handler = gen_invalid,
702 };
703
704 /*** Integer comparison ***/
705
706 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
707 {
708 TCGv t0 = tcg_temp_new();
709 TCGv_i32 t1 = tcg_temp_new_i32();
710
711 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
712
713 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
714 tcg_gen_trunc_tl_i32(t1, t0);
715 tcg_gen_shli_i32(t1, t1, CRF_LT);
716 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
717
718 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
719 tcg_gen_trunc_tl_i32(t1, t0);
720 tcg_gen_shli_i32(t1, t1, CRF_GT);
721 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
722
723 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
724 tcg_gen_trunc_tl_i32(t1, t0);
725 tcg_gen_shli_i32(t1, t1, CRF_EQ);
726 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
727
728 tcg_temp_free(t0);
729 tcg_temp_free_i32(t1);
730 }
731
732 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
733 {
734 TCGv t0 = tcg_const_tl(arg1);
735 gen_op_cmp(arg0, t0, s, crf);
736 tcg_temp_free(t0);
737 }
738
739 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
740 {
741 TCGv t0, t1;
742 t0 = tcg_temp_new();
743 t1 = tcg_temp_new();
744 if (s) {
745 tcg_gen_ext32s_tl(t0, arg0);
746 tcg_gen_ext32s_tl(t1, arg1);
747 } else {
748 tcg_gen_ext32u_tl(t0, arg0);
749 tcg_gen_ext32u_tl(t1, arg1);
750 }
751 gen_op_cmp(t0, t1, s, crf);
752 tcg_temp_free(t1);
753 tcg_temp_free(t0);
754 }
755
756 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
757 {
758 TCGv t0 = tcg_const_tl(arg1);
759 gen_op_cmp32(arg0, t0, s, crf);
760 tcg_temp_free(t0);
761 }
762
763 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
764 {
765 if (NARROW_MODE(ctx)) {
766 gen_op_cmpi32(reg, 0, 1, 0);
767 } else {
768 gen_op_cmpi(reg, 0, 1, 0);
769 }
770 }
771
772 /* cmp */
773 static void gen_cmp(DisasContext *ctx)
774 {
775 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
776 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
777 1, crfD(ctx->opcode));
778 } else {
779 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
780 1, crfD(ctx->opcode));
781 }
782 }
783
784 /* cmpi */
785 static void gen_cmpi(DisasContext *ctx)
786 {
787 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
788 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
789 1, crfD(ctx->opcode));
790 } else {
791 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
792 1, crfD(ctx->opcode));
793 }
794 }
795
796 /* cmpl */
797 static void gen_cmpl(DisasContext *ctx)
798 {
799 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
800 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
801 0, crfD(ctx->opcode));
802 } else {
803 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
804 0, crfD(ctx->opcode));
805 }
806 }
807
808 /* cmpli */
809 static void gen_cmpli(DisasContext *ctx)
810 {
811 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
812 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
813 0, crfD(ctx->opcode));
814 } else {
815 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
816 0, crfD(ctx->opcode));
817 }
818 }
819
820 /* cmprb - range comparison: isupper, isaplha, islower*/
821 static void gen_cmprb(DisasContext *ctx)
822 {
823 TCGv_i32 src1 = tcg_temp_new_i32();
824 TCGv_i32 src2 = tcg_temp_new_i32();
825 TCGv_i32 src2lo = tcg_temp_new_i32();
826 TCGv_i32 src2hi = tcg_temp_new_i32();
827 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
828
829 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
830 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
831
832 tcg_gen_andi_i32(src1, src1, 0xFF);
833 tcg_gen_ext8u_i32(src2lo, src2);
834 tcg_gen_shri_i32(src2, src2, 8);
835 tcg_gen_ext8u_i32(src2hi, src2);
836
837 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
838 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
839 tcg_gen_and_i32(crf, src2lo, src2hi);
840
841 if (ctx->opcode & 0x00200000) {
842 tcg_gen_shri_i32(src2, src2, 8);
843 tcg_gen_ext8u_i32(src2lo, src2);
844 tcg_gen_shri_i32(src2, src2, 8);
845 tcg_gen_ext8u_i32(src2hi, src2);
846 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
847 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
848 tcg_gen_and_i32(src2lo, src2lo, src2hi);
849 tcg_gen_or_i32(crf, crf, src2lo);
850 }
851 tcg_gen_shli_i32(crf, crf, CRF_GT);
852 tcg_temp_free_i32(src1);
853 tcg_temp_free_i32(src2);
854 tcg_temp_free_i32(src2lo);
855 tcg_temp_free_i32(src2hi);
856 }
857
858 #if defined(TARGET_PPC64)
859 /* cmpeqb */
860 static void gen_cmpeqb(DisasContext *ctx)
861 {
862 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
863 cpu_gpr[rB(ctx->opcode)]);
864 }
865 #endif
866
867 /* isel (PowerPC 2.03 specification) */
868 static void gen_isel(DisasContext *ctx)
869 {
870 uint32_t bi = rC(ctx->opcode);
871 uint32_t mask = 0x08 >> (bi & 0x03);
872 TCGv t0 = tcg_temp_new();
873 TCGv zr;
874
875 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
876 tcg_gen_andi_tl(t0, t0, mask);
877
878 zr = tcg_const_tl(0);
879 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
880 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
881 cpu_gpr[rB(ctx->opcode)]);
882 tcg_temp_free(zr);
883 tcg_temp_free(t0);
884 }
885
886 /* cmpb: PowerPC 2.05 specification */
887 static void gen_cmpb(DisasContext *ctx)
888 {
889 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
890 cpu_gpr[rB(ctx->opcode)]);
891 }
892
893 /*** Integer arithmetic ***/
894
895 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
896 TCGv arg1, TCGv arg2, int sub)
897 {
898 TCGv t0 = tcg_temp_new();
899
900 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
901 tcg_gen_xor_tl(t0, arg1, arg2);
902 if (sub) {
903 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
904 } else {
905 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
906 }
907 tcg_temp_free(t0);
908 if (NARROW_MODE(ctx)) {
909 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
910 }
911 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
912 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
913 }
914
915 /* Common add function */
916 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
917 TCGv arg2, bool add_ca, bool compute_ca,
918 bool compute_ov, bool compute_rc0)
919 {
920 TCGv t0 = ret;
921
922 if (compute_ca || compute_ov) {
923 t0 = tcg_temp_new();
924 }
925
926 if (compute_ca) {
927 if (NARROW_MODE(ctx)) {
928 /* Caution: a non-obvious corner case of the spec is that we
929 must produce the *entire* 64-bit addition, but produce the
930 carry into bit 32. */
931 TCGv t1 = tcg_temp_new();
932 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
933 tcg_gen_add_tl(t0, arg1, arg2);
934 if (add_ca) {
935 tcg_gen_add_tl(t0, t0, cpu_ca);
936 }
937 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
938 tcg_temp_free(t1);
939 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
940 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
941 } else {
942 TCGv zero = tcg_const_tl(0);
943 if (add_ca) {
944 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
945 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
946 } else {
947 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
948 }
949 tcg_temp_free(zero);
950 }
951 } else {
952 tcg_gen_add_tl(t0, arg1, arg2);
953 if (add_ca) {
954 tcg_gen_add_tl(t0, t0, cpu_ca);
955 }
956 }
957
958 if (compute_ov) {
959 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
960 }
961 if (unlikely(compute_rc0)) {
962 gen_set_Rc0(ctx, t0);
963 }
964
965 if (!TCGV_EQUAL(t0, ret)) {
966 tcg_gen_mov_tl(ret, t0);
967 tcg_temp_free(t0);
968 }
969 }
970 /* Add functions with two operands */
971 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
972 static void glue(gen_, name)(DisasContext *ctx) \
973 { \
974 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
975 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
976 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
977 }
978 /* Add functions with one operand and one immediate */
979 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
980 add_ca, compute_ca, compute_ov) \
981 static void glue(gen_, name)(DisasContext *ctx) \
982 { \
983 TCGv t0 = tcg_const_tl(const_val); \
984 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
985 cpu_gpr[rA(ctx->opcode)], t0, \
986 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
987 tcg_temp_free(t0); \
988 }
989
990 /* add add. addo addo. */
991 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
992 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
993 /* addc addc. addco addco. */
994 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
995 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
996 /* adde adde. addeo addeo. */
997 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
998 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
999 /* addme addme. addmeo addmeo. */
1000 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1001 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1002 /* addze addze. addzeo addzeo.*/
1003 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1004 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1005 /* addi */
1006 static void gen_addi(DisasContext *ctx)
1007 {
1008 target_long simm = SIMM(ctx->opcode);
1009
1010 if (rA(ctx->opcode) == 0) {
1011 /* li case */
1012 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1013 } else {
1014 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1015 cpu_gpr[rA(ctx->opcode)], simm);
1016 }
1017 }
1018 /* addic addic.*/
1019 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
1020 {
1021 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1022 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1023 c, 0, 1, 0, compute_rc0);
1024 tcg_temp_free(c);
1025 }
1026
1027 static void gen_addic(DisasContext *ctx)
1028 {
1029 gen_op_addic(ctx, 0);
1030 }
1031
1032 static void gen_addic_(DisasContext *ctx)
1033 {
1034 gen_op_addic(ctx, 1);
1035 }
1036
1037 /* addis */
1038 static void gen_addis(DisasContext *ctx)
1039 {
1040 target_long simm = SIMM(ctx->opcode);
1041
1042 if (rA(ctx->opcode) == 0) {
1043 /* lis case */
1044 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1045 } else {
1046 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1047 cpu_gpr[rA(ctx->opcode)], simm << 16);
1048 }
1049 }
1050
1051 /* addpcis */
1052 static void gen_addpcis(DisasContext *ctx)
1053 {
1054 target_long d = DX(ctx->opcode);
1055
1056 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));
1057 }
1058
1059 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1060 TCGv arg2, int sign, int compute_ov)
1061 {
1062 TCGLabel *l1 = gen_new_label();
1063 TCGLabel *l2 = gen_new_label();
1064 TCGv_i32 t0 = tcg_temp_local_new_i32();
1065 TCGv_i32 t1 = tcg_temp_local_new_i32();
1066
1067 tcg_gen_trunc_tl_i32(t0, arg1);
1068 tcg_gen_trunc_tl_i32(t1, arg2);
1069 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1070 if (sign) {
1071 TCGLabel *l3 = gen_new_label();
1072 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1073 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1074 gen_set_label(l3);
1075 tcg_gen_div_i32(t0, t0, t1);
1076 } else {
1077 tcg_gen_divu_i32(t0, t0, t1);
1078 }
1079 if (compute_ov) {
1080 tcg_gen_movi_tl(cpu_ov, 0);
1081 }
1082 tcg_gen_br(l2);
1083 gen_set_label(l1);
1084 if (sign) {
1085 tcg_gen_sari_i32(t0, t0, 31);
1086 } else {
1087 tcg_gen_movi_i32(t0, 0);
1088 }
1089 if (compute_ov) {
1090 tcg_gen_movi_tl(cpu_ov, 1);
1091 tcg_gen_movi_tl(cpu_so, 1);
1092 }
1093 gen_set_label(l2);
1094 tcg_gen_extu_i32_tl(ret, t0);
1095 tcg_temp_free_i32(t0);
1096 tcg_temp_free_i32(t1);
1097 if (unlikely(Rc(ctx->opcode) != 0))
1098 gen_set_Rc0(ctx, ret);
1099 }
1100 /* Div functions */
1101 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1102 static void glue(gen_, name)(DisasContext *ctx) \
1103 { \
1104 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1105 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1106 sign, compute_ov); \
1107 }
1108 /* divwu divwu. divwuo divwuo. */
1109 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1110 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1111 /* divw divw. divwo divwo. */
1112 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1113 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1114
1115 /* div[wd]eu[o][.] */
1116 #define GEN_DIVE(name, hlpr, compute_ov) \
1117 static void gen_##name(DisasContext *ctx) \
1118 { \
1119 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1120 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1121 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1122 tcg_temp_free_i32(t0); \
1123 if (unlikely(Rc(ctx->opcode) != 0)) { \
1124 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1125 } \
1126 }
1127
1128 GEN_DIVE(divweu, divweu, 0);
1129 GEN_DIVE(divweuo, divweu, 1);
1130 GEN_DIVE(divwe, divwe, 0);
1131 GEN_DIVE(divweo, divwe, 1);
1132
1133 #if defined(TARGET_PPC64)
1134 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1135 TCGv arg2, int sign, int compute_ov)
1136 {
1137 TCGLabel *l1 = gen_new_label();
1138 TCGLabel *l2 = gen_new_label();
1139
1140 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1141 if (sign) {
1142 TCGLabel *l3 = gen_new_label();
1143 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1144 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1145 gen_set_label(l3);
1146 tcg_gen_div_i64(ret, arg1, arg2);
1147 } else {
1148 tcg_gen_divu_i64(ret, arg1, arg2);
1149 }
1150 if (compute_ov) {
1151 tcg_gen_movi_tl(cpu_ov, 0);
1152 }
1153 tcg_gen_br(l2);
1154 gen_set_label(l1);
1155 if (sign) {
1156 tcg_gen_sari_i64(ret, arg1, 63);
1157 } else {
1158 tcg_gen_movi_i64(ret, 0);
1159 }
1160 if (compute_ov) {
1161 tcg_gen_movi_tl(cpu_ov, 1);
1162 tcg_gen_movi_tl(cpu_so, 1);
1163 }
1164 gen_set_label(l2);
1165 if (unlikely(Rc(ctx->opcode) != 0))
1166 gen_set_Rc0(ctx, ret);
1167 }
1168 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1169 static void glue(gen_, name)(DisasContext *ctx) \
1170 { \
1171 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1172 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1173 sign, compute_ov); \
1174 }
1175 /* divwu divwu. divwuo divwuo. */
1176 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1177 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1178 /* divw divw. divwo divwo. */
1179 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1180 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1181
1182 GEN_DIVE(divdeu, divdeu, 0);
1183 GEN_DIVE(divdeuo, divdeu, 1);
1184 GEN_DIVE(divde, divde, 0);
1185 GEN_DIVE(divdeo, divde, 1);
1186 #endif
1187
1188 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1189 TCGv arg2, int sign)
1190 {
1191 TCGv_i32 t0 = tcg_temp_new_i32();
1192 TCGv_i32 t1 = tcg_temp_new_i32();
1193
1194 tcg_gen_trunc_tl_i32(t0, arg1);
1195 tcg_gen_trunc_tl_i32(t1, arg2);
1196 if (sign) {
1197 TCGv_i32 t2 = tcg_temp_new_i32();
1198 TCGv_i32 t3 = tcg_temp_new_i32();
1199 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1200 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1201 tcg_gen_and_i32(t2, t2, t3);
1202 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1203 tcg_gen_or_i32(t2, t2, t3);
1204 tcg_gen_movi_i32(t3, 0);
1205 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1206 tcg_gen_rem_i32(t3, t0, t1);
1207 tcg_gen_ext_i32_tl(ret, t3);
1208 tcg_temp_free_i32(t2);
1209 tcg_temp_free_i32(t3);
1210 } else {
1211 TCGv_i32 t2 = tcg_const_i32(1);
1212 TCGv_i32 t3 = tcg_const_i32(0);
1213 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1214 tcg_gen_remu_i32(t3, t0, t1);
1215 tcg_gen_extu_i32_tl(ret, t3);
1216 tcg_temp_free_i32(t2);
1217 tcg_temp_free_i32(t3);
1218 }
1219 tcg_temp_free_i32(t0);
1220 tcg_temp_free_i32(t1);
1221 }
1222
1223 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1224 static void glue(gen_, name)(DisasContext *ctx) \
1225 { \
1226 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1227 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1228 sign); \
1229 }
1230
1231 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1232 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1233
1234 #if defined(TARGET_PPC64)
1235 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1236 TCGv arg2, int sign)
1237 {
1238 TCGv_i64 t0 = tcg_temp_new_i64();
1239 TCGv_i64 t1 = tcg_temp_new_i64();
1240
1241 tcg_gen_mov_i64(t0, arg1);
1242 tcg_gen_mov_i64(t1, arg2);
1243 if (sign) {
1244 TCGv_i64 t2 = tcg_temp_new_i64();
1245 TCGv_i64 t3 = tcg_temp_new_i64();
1246 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1247 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1248 tcg_gen_and_i64(t2, t2, t3);
1249 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1250 tcg_gen_or_i64(t2, t2, t3);
1251 tcg_gen_movi_i64(t3, 0);
1252 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1253 tcg_gen_rem_i64(ret, t0, t1);
1254 tcg_temp_free_i64(t2);
1255 tcg_temp_free_i64(t3);
1256 } else {
1257 TCGv_i64 t2 = tcg_const_i64(1);
1258 TCGv_i64 t3 = tcg_const_i64(0);
1259 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1260 tcg_gen_remu_i64(ret, t0, t1);
1261 tcg_temp_free_i64(t2);
1262 tcg_temp_free_i64(t3);
1263 }
1264 tcg_temp_free_i64(t0);
1265 tcg_temp_free_i64(t1);
1266 }
1267
1268 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1269 static void glue(gen_, name)(DisasContext *ctx) \
1270 { \
1271 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1272 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1273 sign); \
1274 }
1275
1276 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1277 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1278 #endif
1279
1280 /* mulhw mulhw. */
1281 static void gen_mulhw(DisasContext *ctx)
1282 {
1283 TCGv_i32 t0 = tcg_temp_new_i32();
1284 TCGv_i32 t1 = tcg_temp_new_i32();
1285
1286 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1287 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1288 tcg_gen_muls2_i32(t0, t1, t0, t1);
1289 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1290 tcg_temp_free_i32(t0);
1291 tcg_temp_free_i32(t1);
1292 if (unlikely(Rc(ctx->opcode) != 0))
1293 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1294 }
1295
1296 /* mulhwu mulhwu. */
1297 static void gen_mulhwu(DisasContext *ctx)
1298 {
1299 TCGv_i32 t0 = tcg_temp_new_i32();
1300 TCGv_i32 t1 = tcg_temp_new_i32();
1301
1302 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1303 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1304 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1305 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1306 tcg_temp_free_i32(t0);
1307 tcg_temp_free_i32(t1);
1308 if (unlikely(Rc(ctx->opcode) != 0))
1309 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1310 }
1311
1312 /* mullw mullw. */
1313 static void gen_mullw(DisasContext *ctx)
1314 {
1315 #if defined(TARGET_PPC64)
1316 TCGv_i64 t0, t1;
1317 t0 = tcg_temp_new_i64();
1318 t1 = tcg_temp_new_i64();
1319 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1320 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1321 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1322 tcg_temp_free(t0);
1323 tcg_temp_free(t1);
1324 #else
1325 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1326 cpu_gpr[rB(ctx->opcode)]);
1327 #endif
1328 if (unlikely(Rc(ctx->opcode) != 0))
1329 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1330 }
1331
1332 /* mullwo mullwo. */
1333 static void gen_mullwo(DisasContext *ctx)
1334 {
1335 TCGv_i32 t0 = tcg_temp_new_i32();
1336 TCGv_i32 t1 = tcg_temp_new_i32();
1337
1338 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1339 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1340 tcg_gen_muls2_i32(t0, t1, t0, t1);
1341 #if defined(TARGET_PPC64)
1342 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1343 #else
1344 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1345 #endif
1346
1347 tcg_gen_sari_i32(t0, t0, 31);
1348 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1349 tcg_gen_extu_i32_tl(cpu_ov, t0);
1350 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1351
1352 tcg_temp_free_i32(t0);
1353 tcg_temp_free_i32(t1);
1354 if (unlikely(Rc(ctx->opcode) != 0))
1355 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1356 }
1357
1358 /* mulli */
1359 static void gen_mulli(DisasContext *ctx)
1360 {
1361 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1362 SIMM(ctx->opcode));
1363 }
1364
1365 #if defined(TARGET_PPC64)
1366 /* mulhd mulhd. */
1367 static void gen_mulhd(DisasContext *ctx)
1368 {
1369 TCGv lo = tcg_temp_new();
1370 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1371 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1372 tcg_temp_free(lo);
1373 if (unlikely(Rc(ctx->opcode) != 0)) {
1374 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1375 }
1376 }
1377
1378 /* mulhdu mulhdu. */
1379 static void gen_mulhdu(DisasContext *ctx)
1380 {
1381 TCGv lo = tcg_temp_new();
1382 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1383 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1384 tcg_temp_free(lo);
1385 if (unlikely(Rc(ctx->opcode) != 0)) {
1386 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1387 }
1388 }
1389
1390 /* mulld mulld. */
1391 static void gen_mulld(DisasContext *ctx)
1392 {
1393 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1394 cpu_gpr[rB(ctx->opcode)]);
1395 if (unlikely(Rc(ctx->opcode) != 0))
1396 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1397 }
1398
1399 /* mulldo mulldo. */
1400 static void gen_mulldo(DisasContext *ctx)
1401 {
1402 TCGv_i64 t0 = tcg_temp_new_i64();
1403 TCGv_i64 t1 = tcg_temp_new_i64();
1404
1405 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1406 cpu_gpr[rB(ctx->opcode)]);
1407 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1408
1409 tcg_gen_sari_i64(t0, t0, 63);
1410 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1411 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1412
1413 tcg_temp_free_i64(t0);
1414 tcg_temp_free_i64(t1);
1415
1416 if (unlikely(Rc(ctx->opcode) != 0)) {
1417 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1418 }
1419 }
1420 #endif
1421
1422 /* Common subf function */
1423 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1424 TCGv arg2, bool add_ca, bool compute_ca,
1425 bool compute_ov, bool compute_rc0)
1426 {
1427 TCGv t0 = ret;
1428
1429 if (compute_ca || compute_ov) {
1430 t0 = tcg_temp_new();
1431 }
1432
1433 if (compute_ca) {
1434 /* dest = ~arg1 + arg2 [+ ca]. */
1435 if (NARROW_MODE(ctx)) {
1436 /* Caution: a non-obvious corner case of the spec is that we
1437 must produce the *entire* 64-bit addition, but produce the
1438 carry into bit 32. */
1439 TCGv inv1 = tcg_temp_new();
1440 TCGv t1 = tcg_temp_new();
1441 tcg_gen_not_tl(inv1, arg1);
1442 if (add_ca) {
1443 tcg_gen_add_tl(t0, arg2, cpu_ca);
1444 } else {
1445 tcg_gen_addi_tl(t0, arg2, 1);
1446 }
1447 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1448 tcg_gen_add_tl(t0, t0, inv1);
1449 tcg_temp_free(inv1);
1450 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1451 tcg_temp_free(t1);
1452 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1453 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1454 } else if (add_ca) {
1455 TCGv zero, inv1 = tcg_temp_new();
1456 tcg_gen_not_tl(inv1, arg1);
1457 zero = tcg_const_tl(0);
1458 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1459 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1460 tcg_temp_free(zero);
1461 tcg_temp_free(inv1);
1462 } else {
1463 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1464 tcg_gen_sub_tl(t0, arg2, arg1);
1465 }
1466 } else if (add_ca) {
1467 /* Since we're ignoring carry-out, we can simplify the
1468 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1469 tcg_gen_sub_tl(t0, arg2, arg1);
1470 tcg_gen_add_tl(t0, t0, cpu_ca);
1471 tcg_gen_subi_tl(t0, t0, 1);
1472 } else {
1473 tcg_gen_sub_tl(t0, arg2, arg1);
1474 }
1475
1476 if (compute_ov) {
1477 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1478 }
1479 if (unlikely(compute_rc0)) {
1480 gen_set_Rc0(ctx, t0);
1481 }
1482
1483 if (!TCGV_EQUAL(t0, ret)) {
1484 tcg_gen_mov_tl(ret, t0);
1485 tcg_temp_free(t0);
1486 }
1487 }
1488 /* Sub functions with Two operands functions */
1489 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1490 static void glue(gen_, name)(DisasContext *ctx) \
1491 { \
1492 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1493 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1494 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1495 }
1496 /* Sub functions with one operand and one immediate */
1497 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1498 add_ca, compute_ca, compute_ov) \
1499 static void glue(gen_, name)(DisasContext *ctx) \
1500 { \
1501 TCGv t0 = tcg_const_tl(const_val); \
1502 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1503 cpu_gpr[rA(ctx->opcode)], t0, \
1504 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1505 tcg_temp_free(t0); \
1506 }
1507 /* subf subf. subfo subfo. */
1508 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1509 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1510 /* subfc subfc. subfco subfco. */
1511 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1512 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1513 /* subfe subfe. subfeo subfo. */
1514 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1515 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1516 /* subfme subfme. subfmeo subfmeo. */
1517 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1518 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1519 /* subfze subfze. subfzeo subfzeo.*/
1520 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1521 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1522
1523 /* subfic */
1524 static void gen_subfic(DisasContext *ctx)
1525 {
1526 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1527 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1528 c, 0, 1, 0, 0);
1529 tcg_temp_free(c);
1530 }
1531
1532 /* neg neg. nego nego. */
1533 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1534 {
1535 TCGv zero = tcg_const_tl(0);
1536 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1537 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1538 tcg_temp_free(zero);
1539 }
1540
1541 static void gen_neg(DisasContext *ctx)
1542 {
1543 gen_op_arith_neg(ctx, 0);
1544 }
1545
1546 static void gen_nego(DisasContext *ctx)
1547 {
1548 gen_op_arith_neg(ctx, 1);
1549 }
1550
1551 /*** Integer logical ***/
1552 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1553 static void glue(gen_, name)(DisasContext *ctx) \
1554 { \
1555 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1556 cpu_gpr[rB(ctx->opcode)]); \
1557 if (unlikely(Rc(ctx->opcode) != 0)) \
1558 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1559 }
1560
1561 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1562 static void glue(gen_, name)(DisasContext *ctx) \
1563 { \
1564 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1565 if (unlikely(Rc(ctx->opcode) != 0)) \
1566 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1567 }
1568
1569 /* and & and. */
1570 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1571 /* andc & andc. */
1572 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1573
1574 /* andi. */
1575 static void gen_andi_(DisasContext *ctx)
1576 {
1577 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1578 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1579 }
1580
1581 /* andis. */
1582 static void gen_andis_(DisasContext *ctx)
1583 {
1584 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1585 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1586 }
1587
1588 /* cntlzw */
1589 static void gen_cntlzw(DisasContext *ctx)
1590 {
1591 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1592 if (unlikely(Rc(ctx->opcode) != 0))
1593 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1594 }
1595
1596 /* cnttzw */
1597 static void gen_cnttzw(DisasContext *ctx)
1598 {
1599 gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1600 if (unlikely(Rc(ctx->opcode) != 0)) {
1601 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1602 }
1603 }
1604
1605 /* eqv & eqv. */
1606 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1607 /* extsb & extsb. */
1608 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1609 /* extsh & extsh. */
1610 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1611 /* nand & nand. */
1612 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1613 /* nor & nor. */
1614 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1615
1616 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1617 static void gen_pause(DisasContext *ctx)
1618 {
1619 TCGv_i32 t0 = tcg_const_i32(0);
1620 tcg_gen_st_i32(t0, cpu_env,
1621 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1622 tcg_temp_free_i32(t0);
1623
1624 /* Stop translation, this gives other CPUs a chance to run */
1625 gen_exception_err(ctx, EXCP_HLT, 1);
1626 }
1627 #endif /* defined(TARGET_PPC64) */
1628
1629 /* or & or. */
1630 static void gen_or(DisasContext *ctx)
1631 {
1632 int rs, ra, rb;
1633
1634 rs = rS(ctx->opcode);
1635 ra = rA(ctx->opcode);
1636 rb = rB(ctx->opcode);
1637 /* Optimisation for mr. ri case */
1638 if (rs != ra || rs != rb) {
1639 if (rs != rb)
1640 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1641 else
1642 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1643 if (unlikely(Rc(ctx->opcode) != 0))
1644 gen_set_Rc0(ctx, cpu_gpr[ra]);
1645 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1646 gen_set_Rc0(ctx, cpu_gpr[rs]);
1647 #if defined(TARGET_PPC64)
1648 } else if (rs != 0) { /* 0 is nop */
1649 int prio = 0;
1650
1651 switch (rs) {
1652 case 1:
1653 /* Set process priority to low */
1654 prio = 2;
1655 break;
1656 case 6:
1657 /* Set process priority to medium-low */
1658 prio = 3;
1659 break;
1660 case 2:
1661 /* Set process priority to normal */
1662 prio = 4;
1663 break;
1664 #if !defined(CONFIG_USER_ONLY)
1665 case 31:
1666 if (!ctx->pr) {
1667 /* Set process priority to very low */
1668 prio = 1;
1669 }
1670 break;
1671 case 5:
1672 if (!ctx->pr) {
1673 /* Set process priority to medium-hight */
1674 prio = 5;
1675 }
1676 break;
1677 case 3:
1678 if (!ctx->pr) {
1679 /* Set process priority to high */
1680 prio = 6;
1681 }
1682 break;
1683 case 7:
1684 if (ctx->hv && !ctx->pr) {
1685 /* Set process priority to very high */
1686 prio = 7;
1687 }
1688 break;
1689 #endif
1690 default:
1691 break;
1692 }
1693 if (prio) {
1694 TCGv t0 = tcg_temp_new();
1695 gen_load_spr(t0, SPR_PPR);
1696 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1697 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1698 gen_store_spr(SPR_PPR, t0);
1699 tcg_temp_free(t0);
1700 }
1701 #if !defined(CONFIG_USER_ONLY)
1702 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1703 * CPU and the kernel hangs. This applies to all encodings other
1704 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1705 * and all currently undefined.
1706 */
1707 gen_pause(ctx);
1708 #endif
1709 #endif
1710 }
1711 }
1712 /* orc & orc. */
1713 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1714
1715 /* xor & xor. */
1716 static void gen_xor(DisasContext *ctx)
1717 {
1718 /* Optimisation for "set to zero" case */
1719 if (rS(ctx->opcode) != rB(ctx->opcode))
1720 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1721 else
1722 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1723 if (unlikely(Rc(ctx->opcode) != 0))
1724 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1725 }
1726
1727 /* ori */
1728 static void gen_ori(DisasContext *ctx)
1729 {
1730 target_ulong uimm = UIMM(ctx->opcode);
1731
1732 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1733 return;
1734 }
1735 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1736 }
1737
1738 /* oris */
1739 static void gen_oris(DisasContext *ctx)
1740 {
1741 target_ulong uimm = UIMM(ctx->opcode);
1742
1743 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1744 /* NOP */
1745 return;
1746 }
1747 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1748 }
1749
1750 /* xori */
1751 static void gen_xori(DisasContext *ctx)
1752 {
1753 target_ulong uimm = UIMM(ctx->opcode);
1754
1755 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1756 /* NOP */
1757 return;
1758 }
1759 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1760 }
1761
1762 /* xoris */
1763 static void gen_xoris(DisasContext *ctx)
1764 {
1765 target_ulong uimm = UIMM(ctx->opcode);
1766
1767 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1768 /* NOP */
1769 return;
1770 }
1771 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1772 }
1773
1774 /* popcntb : PowerPC 2.03 specification */
1775 static void gen_popcntb(DisasContext *ctx)
1776 {
1777 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1778 }
1779
1780 static void gen_popcntw(DisasContext *ctx)
1781 {
1782 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1783 }
1784
1785 #if defined(TARGET_PPC64)
1786 /* popcntd: PowerPC 2.06 specification */
1787 static void gen_popcntd(DisasContext *ctx)
1788 {
1789 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1790 }
1791 #endif
1792
1793 /* prtyw: PowerPC 2.05 specification */
1794 static void gen_prtyw(DisasContext *ctx)
1795 {
1796 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1797 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1798 TCGv t0 = tcg_temp_new();
1799 tcg_gen_shri_tl(t0, rs, 16);
1800 tcg_gen_xor_tl(ra, rs, t0);
1801 tcg_gen_shri_tl(t0, ra, 8);
1802 tcg_gen_xor_tl(ra, ra, t0);
1803 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1804 tcg_temp_free(t0);
1805 }
1806
1807 #if defined(TARGET_PPC64)
1808 /* prtyd: PowerPC 2.05 specification */
1809 static void gen_prtyd(DisasContext *ctx)
1810 {
1811 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1812 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1813 TCGv t0 = tcg_temp_new();
1814 tcg_gen_shri_tl(t0, rs, 32);
1815 tcg_gen_xor_tl(ra, rs, t0);
1816 tcg_gen_shri_tl(t0, ra, 16);
1817 tcg_gen_xor_tl(ra, ra, t0);
1818 tcg_gen_shri_tl(t0, ra, 8);
1819 tcg_gen_xor_tl(ra, ra, t0);
1820 tcg_gen_andi_tl(ra, ra, 1);
1821 tcg_temp_free(t0);
1822 }
1823 #endif
1824
1825 #if defined(TARGET_PPC64)
1826 /* bpermd */
1827 static void gen_bpermd(DisasContext *ctx)
1828 {
1829 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1830 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1831 }
1832 #endif
1833
1834 #if defined(TARGET_PPC64)
1835 /* extsw & extsw. */
1836 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1837
1838 /* cntlzd */
1839 static void gen_cntlzd(DisasContext *ctx)
1840 {
1841 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1842 if (unlikely(Rc(ctx->opcode) != 0))
1843 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1844 }
1845
1846 /* cnttzd */
1847 static void gen_cnttzd(DisasContext *ctx)
1848 {
1849 gen_helper_cnttzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1850 if (unlikely(Rc(ctx->opcode) != 0)) {
1851 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1852 }
1853 }
1854 #endif
1855
1856 /*** Integer rotate ***/
1857
1858 /* rlwimi & rlwimi. */
1859 static void gen_rlwimi(DisasContext *ctx)
1860 {
1861 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1862 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1863 uint32_t sh = SH(ctx->opcode);
1864 uint32_t mb = MB(ctx->opcode);
1865 uint32_t me = ME(ctx->opcode);
1866
1867 if (sh == (31-me) && mb <= me) {
1868 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1869 } else {
1870 target_ulong mask;
1871 TCGv t1;
1872
1873 #if defined(TARGET_PPC64)
1874 mb += 32;
1875 me += 32;
1876 #endif
1877 mask = MASK(mb, me);
1878
1879 t1 = tcg_temp_new();
1880 if (mask <= 0xffffffffu) {
1881 TCGv_i32 t0 = tcg_temp_new_i32();
1882 tcg_gen_trunc_tl_i32(t0, t_rs);
1883 tcg_gen_rotli_i32(t0, t0, sh);
1884 tcg_gen_extu_i32_tl(t1, t0);
1885 tcg_temp_free_i32(t0);
1886 } else {
1887 #if defined(TARGET_PPC64)
1888 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1889 tcg_gen_rotli_i64(t1, t1, sh);
1890 #else
1891 g_assert_not_reached();
1892 #endif
1893 }
1894
1895 tcg_gen_andi_tl(t1, t1, mask);
1896 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1897 tcg_gen_or_tl(t_ra, t_ra, t1);
1898 tcg_temp_free(t1);
1899 }
1900 if (unlikely(Rc(ctx->opcode) != 0)) {
1901 gen_set_Rc0(ctx, t_ra);
1902 }
1903 }
1904
1905 /* rlwinm & rlwinm. */
1906 static void gen_rlwinm(DisasContext *ctx)
1907 {
1908 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1909 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1910 uint32_t sh = SH(ctx->opcode);
1911 uint32_t mb = MB(ctx->opcode);
1912 uint32_t me = ME(ctx->opcode);
1913
1914 if (mb == 0 && me == (31 - sh)) {
1915 tcg_gen_shli_tl(t_ra, t_rs, sh);
1916 tcg_gen_ext32u_tl(t_ra, t_ra);
1917 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1918 tcg_gen_ext32u_tl(t_ra, t_rs);
1919 tcg_gen_shri_tl(t_ra, t_ra, mb);
1920 } else {
1921 target_ulong mask;
1922 #if defined(TARGET_PPC64)
1923 mb += 32;
1924 me += 32;
1925 #endif
1926 mask = MASK(mb, me);
1927
1928 if (mask <= 0xffffffffu) {
1929 TCGv_i32 t0 = tcg_temp_new_i32();
1930 tcg_gen_trunc_tl_i32(t0, t_rs);
1931 tcg_gen_rotli_i32(t0, t0, sh);
1932 tcg_gen_andi_i32(t0, t0, mask);
1933 tcg_gen_extu_i32_tl(t_ra, t0);
1934 tcg_temp_free_i32(t0);
1935 } else {
1936 #if defined(TARGET_PPC64)
1937 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1938 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1939 tcg_gen_andi_i64(t_ra, t_ra, mask);
1940 #else
1941 g_assert_not_reached();
1942 #endif
1943 }
1944 }
1945 if (unlikely(Rc(ctx->opcode) != 0)) {
1946 gen_set_Rc0(ctx, t_ra);
1947 }
1948 }
1949
1950 /* rlwnm & rlwnm. */
1951 static void gen_rlwnm(DisasContext *ctx)
1952 {
1953 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1954 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1955 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1956 uint32_t mb = MB(ctx->opcode);
1957 uint32_t me = ME(ctx->opcode);
1958 target_ulong mask;
1959
1960 #if defined(TARGET_PPC64)
1961 mb += 32;
1962 me += 32;
1963 #endif
1964 mask = MASK(mb, me);
1965
1966 if (mask <= 0xffffffffu) {
1967 TCGv_i32 t0 = tcg_temp_new_i32();
1968 TCGv_i32 t1 = tcg_temp_new_i32();
1969 tcg_gen_trunc_tl_i32(t0, t_rb);
1970 tcg_gen_trunc_tl_i32(t1, t_rs);
1971 tcg_gen_andi_i32(t0, t0, 0x1f);
1972 tcg_gen_rotl_i32(t1, t1, t0);
1973 tcg_gen_extu_i32_tl(t_ra, t1);
1974 tcg_temp_free_i32(t0);
1975 tcg_temp_free_i32(t1);
1976 } else {
1977 #if defined(TARGET_PPC64)
1978 TCGv_i64 t0 = tcg_temp_new_i64();
1979 tcg_gen_andi_i64(t0, t_rb, 0x1f);
1980 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1981 tcg_gen_rotl_i64(t_ra, t_ra, t0);
1982 tcg_temp_free_i64(t0);
1983 #else
1984 g_assert_not_reached();
1985 #endif
1986 }
1987
1988 tcg_gen_andi_tl(t_ra, t_ra, mask);
1989
1990 if (unlikely(Rc(ctx->opcode) != 0)) {
1991 gen_set_Rc0(ctx, t_ra);
1992 }
1993 }
1994
1995 #if defined(TARGET_PPC64)
1996 #define GEN_PPC64_R2(name, opc1, opc2) \
1997 static void glue(gen_, name##0)(DisasContext *ctx) \
1998 { \
1999 gen_##name(ctx, 0); \
2000 } \
2001 \
2002 static void glue(gen_, name##1)(DisasContext *ctx) \
2003 { \
2004 gen_##name(ctx, 1); \
2005 }
2006 #define GEN_PPC64_R4(name, opc1, opc2) \
2007 static void glue(gen_, name##0)(DisasContext *ctx) \
2008 { \
2009 gen_##name(ctx, 0, 0); \
2010 } \
2011 \
2012 static void glue(gen_, name##1)(DisasContext *ctx) \
2013 { \
2014 gen_##name(ctx, 0, 1); \
2015 } \
2016 \
2017 static void glue(gen_, name##2)(DisasContext *ctx) \
2018 { \
2019 gen_##name(ctx, 1, 0); \
2020 } \
2021 \
2022 static void glue(gen_, name##3)(DisasContext *ctx) \
2023 { \
2024 gen_##name(ctx, 1, 1); \
2025 }
2026
2027 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2028 {
2029 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2030 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2031
2032 if (sh != 0 && mb == 0 && me == (63 - sh)) {
2033 tcg_gen_shli_tl(t_ra, t_rs, sh);
2034 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
2035 tcg_gen_shri_tl(t_ra, t_rs, mb);
2036 } else {
2037 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2038 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2039 }
2040 if (unlikely(Rc(ctx->opcode) != 0)) {
2041 gen_set_Rc0(ctx, t_ra);
2042 }
2043 }
2044
2045 /* rldicl - rldicl. */
2046 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2047 {
2048 uint32_t sh, mb;
2049
2050 sh = SH(ctx->opcode) | (shn << 5);
2051 mb = MB(ctx->opcode) | (mbn << 5);
2052 gen_rldinm(ctx, mb, 63, sh);
2053 }
2054 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2055
2056 /* rldicr - rldicr. */
2057 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2058 {
2059 uint32_t sh, me;
2060
2061 sh = SH(ctx->opcode) | (shn << 5);
2062 me = MB(ctx->opcode) | (men << 5);
2063 gen_rldinm(ctx, 0, me, sh);
2064 }
2065 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2066
2067 /* rldic - rldic. */
2068 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2069 {
2070 uint32_t sh, mb;
2071
2072 sh = SH(ctx->opcode) | (shn << 5);
2073 mb = MB(ctx->opcode) | (mbn << 5);
2074 gen_rldinm(ctx, mb, 63 - sh, sh);
2075 }
2076 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2077
2078 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2079 {
2080 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2081 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2082 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2083 TCGv t0;
2084
2085 t0 = tcg_temp_new();
2086 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2087 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2088 tcg_temp_free(t0);
2089
2090 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2091 if (unlikely(Rc(ctx->opcode) != 0)) {
2092 gen_set_Rc0(ctx, t_ra);
2093 }
2094 }
2095
2096 /* rldcl - rldcl. */
2097 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2098 {
2099 uint32_t mb;
2100
2101 mb = MB(ctx->opcode) | (mbn << 5);
2102 gen_rldnm(ctx, mb, 63);
2103 }
2104 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2105
2106 /* rldcr - rldcr. */
2107 static inline void gen_rldcr(DisasContext *ctx, int men)
2108 {
2109 uint32_t me;
2110
2111 me = MB(ctx->opcode) | (men << 5);
2112 gen_rldnm(ctx, 0, me);
2113 }
2114 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2115
2116 /* rldimi - rldimi. */
2117 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2118 {
2119 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2120 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2121 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2122 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2123 uint32_t me = 63 - sh;
2124
2125 if (mb <= me) {
2126 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2127 } else {
2128 target_ulong mask = MASK(mb, me);
2129 TCGv t1 = tcg_temp_new();
2130
2131 tcg_gen_rotli_tl(t1, t_rs, sh);
2132 tcg_gen_andi_tl(t1, t1, mask);
2133 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2134 tcg_gen_or_tl(t_ra, t_ra, t1);
2135 tcg_temp_free(t1);
2136 }
2137 if (unlikely(Rc(ctx->opcode) != 0)) {
2138 gen_set_Rc0(ctx, t_ra);
2139 }
2140 }
2141 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2142 #endif
2143
2144 /*** Integer shift ***/
2145
2146 /* slw & slw. */
2147 static void gen_slw(DisasContext *ctx)
2148 {
2149 TCGv t0, t1;
2150
2151 t0 = tcg_temp_new();
2152 /* AND rS with a mask that is 0 when rB >= 0x20 */
2153 #if defined(TARGET_PPC64)
2154 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2155 tcg_gen_sari_tl(t0, t0, 0x3f);
2156 #else
2157 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2158 tcg_gen_sari_tl(t0, t0, 0x1f);
2159 #endif
2160 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2161 t1 = tcg_temp_new();
2162 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2163 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2164 tcg_temp_free(t1);
2165 tcg_temp_free(t0);
2166 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2167 if (unlikely(Rc(ctx->opcode) != 0))
2168 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2169 }
2170
2171 /* sraw & sraw. */
2172 static void gen_sraw(DisasContext *ctx)
2173 {
2174 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2175 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2176 if (unlikely(Rc(ctx->opcode) != 0))
2177 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2178 }
2179
2180 /* srawi & srawi. */
2181 static void gen_srawi(DisasContext *ctx)
2182 {
2183 int sh = SH(ctx->opcode);
2184 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2185 TCGv src = cpu_gpr[rS(ctx->opcode)];
2186 if (sh == 0) {
2187 tcg_gen_ext32s_tl(dst, src);
2188 tcg_gen_movi_tl(cpu_ca, 0);
2189 } else {
2190 TCGv t0;
2191 tcg_gen_ext32s_tl(dst, src);
2192 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2193 t0 = tcg_temp_new();
2194 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2195 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2196 tcg_temp_free(t0);
2197 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2198 tcg_gen_sari_tl(dst, dst, sh);
2199 }
2200 if (unlikely(Rc(ctx->opcode) != 0)) {
2201 gen_set_Rc0(ctx, dst);
2202 }
2203 }
2204
2205 /* srw & srw. */
2206 static void gen_srw(DisasContext *ctx)
2207 {
2208 TCGv t0, t1;
2209
2210 t0 = tcg_temp_new();
2211 /* AND rS with a mask that is 0 when rB >= 0x20 */
2212 #if defined(TARGET_PPC64)
2213 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2214 tcg_gen_sari_tl(t0, t0, 0x3f);
2215 #else
2216 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2217 tcg_gen_sari_tl(t0, t0, 0x1f);
2218 #endif
2219 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2220 tcg_gen_ext32u_tl(t0, t0);
2221 t1 = tcg_temp_new();
2222 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2223 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2224 tcg_temp_free(t1);
2225 tcg_temp_free(t0);
2226 if (unlikely(Rc(ctx->opcode) != 0))
2227 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2228 }
2229
2230 #if defined(TARGET_PPC64)
2231 /* sld & sld. */
2232 static void gen_sld(DisasContext *ctx)
2233 {
2234 TCGv t0, t1;
2235
2236 t0 = tcg_temp_new();
2237 /* AND rS with a mask that is 0 when rB >= 0x40 */
2238 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2239 tcg_gen_sari_tl(t0, t0, 0x3f);
2240 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2241 t1 = tcg_temp_new();
2242 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2243 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2244 tcg_temp_free(t1);
2245 tcg_temp_free(t0);
2246 if (unlikely(Rc(ctx->opcode) != 0))
2247 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2248 }
2249
2250 /* srad & srad. */
2251 static void gen_srad(DisasContext *ctx)
2252 {
2253 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2254 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2255 if (unlikely(Rc(ctx->opcode) != 0))
2256 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2257 }
2258 /* sradi & sradi. */
2259 static inline void gen_sradi(DisasContext *ctx, int n)
2260 {
2261 int sh = SH(ctx->opcode) + (n << 5);
2262 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2263 TCGv src = cpu_gpr[rS(ctx->opcode)];
2264 if (sh == 0) {
2265 tcg_gen_mov_tl(dst, src);
2266 tcg_gen_movi_tl(cpu_ca, 0);
2267 } else {
2268 TCGv t0;
2269 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2270 t0 = tcg_temp_new();
2271 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2272 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2273 tcg_temp_free(t0);
2274 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2275 tcg_gen_sari_tl(dst, src, sh);
2276 }
2277 if (unlikely(Rc(ctx->opcode) != 0)) {
2278 gen_set_Rc0(ctx, dst);
2279 }
2280 }
2281
2282 static void gen_sradi0(DisasContext *ctx)
2283 {
2284 gen_sradi(ctx, 0);
2285 }
2286
2287 static void gen_sradi1(DisasContext *ctx)
2288 {
2289 gen_sradi(ctx, 1);
2290 }
2291
2292 /* srd & srd. */
2293 static void gen_srd(DisasContext *ctx)
2294 {
2295 TCGv t0, t1;
2296
2297 t0 = tcg_temp_new();
2298 /* AND rS with a mask that is 0 when rB >= 0x40 */
2299 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2300 tcg_gen_sari_tl(t0, t0, 0x3f);
2301 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2302 t1 = tcg_temp_new();
2303 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2304 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2305 tcg_temp_free(t1);
2306 tcg_temp_free(t0);
2307 if (unlikely(Rc(ctx->opcode) != 0))
2308 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2309 }
2310 #endif
2311
2312 #if defined(TARGET_PPC64)
2313 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2314 {
2315 TCGv_i32 tmp = tcg_temp_new_i32();
2316 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2317 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2318 tcg_temp_free_i32(tmp);
2319 }
2320 #else
2321 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2322 {
2323 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2324 }
2325 #endif
2326
2327 /*** Floating-Point arithmetic ***/
2328 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2329 static void gen_f##name(DisasContext *ctx) \
2330 { \
2331 if (unlikely(!ctx->fpu_enabled)) { \
2332 gen_exception(ctx, POWERPC_EXCP_FPU); \
2333 return; \
2334 } \
2335 /* NIP cannot be restored if the memory exception comes from an helper */ \
2336 gen_update_nip(ctx, ctx->nip - 4); \
2337 gen_reset_fpstatus(); \
2338 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2339 cpu_fpr[rA(ctx->opcode)], \
2340 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2341 if (isfloat) { \
2342 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2343 cpu_fpr[rD(ctx->opcode)]); \
2344 } \
2345 if (set_fprf) { \
2346 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2347 } \
2348 if (unlikely(Rc(ctx->opcode) != 0)) { \
2349 gen_set_cr1_from_fpscr(ctx); \
2350 } \
2351 }
2352
2353 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2354 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2355 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2356
2357 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2358 static void gen_f##name(DisasContext *ctx) \
2359 { \
2360 if (unlikely(!ctx->fpu_enabled)) { \
2361 gen_exception(ctx, POWERPC_EXCP_FPU); \
2362 return; \
2363 } \
2364 /* NIP cannot be restored if the memory exception comes from an helper */ \
2365 gen_update_nip(ctx, ctx->nip - 4); \
2366 gen_reset_fpstatus(); \
2367 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2368 cpu_fpr[rA(ctx->opcode)], \
2369 cpu_fpr[rB(ctx->opcode)]); \
2370 if (isfloat) { \
2371 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2372 cpu_fpr[rD(ctx->opcode)]); \
2373 } \
2374 if (set_fprf) { \
2375 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2376 } \
2377 if (unlikely(Rc(ctx->opcode) != 0)) { \
2378 gen_set_cr1_from_fpscr(ctx); \
2379 } \
2380 }
2381 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2382 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2383 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2384
2385 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2386 static void gen_f##name(DisasContext *ctx) \
2387 { \
2388 if (unlikely(!ctx->fpu_enabled)) { \
2389 gen_exception(ctx, POWERPC_EXCP_FPU); \
2390 return; \
2391 } \
2392 /* NIP cannot be restored if the memory exception comes from an helper */ \
2393 gen_update_nip(ctx, ctx->nip - 4); \
2394 gen_reset_fpstatus(); \
2395 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2396 cpu_fpr[rA(ctx->opcode)], \
2397 cpu_fpr[rC(ctx->opcode)]); \
2398 if (isfloat) { \
2399 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2400 cpu_fpr[rD(ctx->opcode)]); \
2401 } \
2402 if (set_fprf) { \
2403 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2404 } \
2405 if (unlikely(Rc(ctx->opcode) != 0)) { \
2406 gen_set_cr1_from_fpscr(ctx); \
2407 } \
2408 }
2409 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2410 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2411 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2412
2413 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2414 static void gen_f##name(DisasContext *ctx) \
2415 { \
2416 if (unlikely(!ctx->fpu_enabled)) { \
2417 gen_exception(ctx, POWERPC_EXCP_FPU); \
2418 return; \
2419 } \
2420 /* NIP cannot be restored if the memory exception comes from an helper */ \
2421 gen_update_nip(ctx, ctx->nip - 4); \
2422 gen_reset_fpstatus(); \
2423 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2424 cpu_fpr[rB(ctx->opcode)]); \
2425 if (set_fprf) { \
2426 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2427 } \
2428 if (unlikely(Rc(ctx->opcode) != 0)) { \
2429 gen_set_cr1_from_fpscr(ctx); \
2430 } \
2431 }
2432
2433 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2434 static void gen_f##name(DisasContext *ctx) \
2435 { \
2436 if (unlikely(!ctx->fpu_enabled)) { \
2437 gen_exception(ctx, POWERPC_EXCP_FPU); \
2438 return; \
2439 } \
2440 /* NIP cannot be restored if the memory exception comes from an helper */ \
2441 gen_update_nip(ctx, ctx->nip - 4); \
2442 gen_reset_fpstatus(); \
2443 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2444 cpu_fpr[rB(ctx->opcode)]); \
2445 if (set_fprf) { \
2446 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2447 } \
2448 if (unlikely(Rc(ctx->opcode) != 0)) { \
2449 gen_set_cr1_from_fpscr(ctx); \
2450 } \
2451 }
2452
2453 /* fadd - fadds */
2454 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2455 /* fdiv - fdivs */
2456 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2457 /* fmul - fmuls */
2458 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2459
2460 /* fre */
2461 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2462
2463 /* fres */
2464 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2465
2466 /* frsqrte */
2467 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2468
2469 /* frsqrtes */
2470 static void gen_frsqrtes(DisasContext *ctx)
2471 {
2472 if (unlikely(!ctx->fpu_enabled)) {
2473 gen_exception(ctx, POWERPC_EXCP_FPU);
2474 return;
2475 }
2476 /* NIP cannot be restored if the memory exception comes from an helper */
2477 gen_update_nip(ctx, ctx->nip - 4);
2478 gen_reset_fpstatus();
2479 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2480 cpu_fpr[rB(ctx->opcode)]);
2481 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2482 cpu_fpr[rD(ctx->opcode)]);
2483 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2484 if (unlikely(Rc(ctx->opcode) != 0)) {
2485 gen_set_cr1_from_fpscr(ctx);
2486 }
2487 }
2488
2489 /* fsel */
2490 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2491 /* fsub - fsubs */
2492 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2493 /* Optional: */
2494
2495 /* fsqrt */
2496 static void gen_fsqrt(DisasContext *ctx)
2497 {
2498 if (unlikely(!ctx->fpu_enabled)) {
2499 gen_exception(ctx, POWERPC_EXCP_FPU);
2500 return;
2501 }
2502 /* NIP cannot be restored if the memory exception comes from an helper */
2503 gen_update_nip(ctx, ctx->nip - 4);
2504 gen_reset_fpstatus();
2505 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2506 cpu_fpr[rB(ctx->opcode)]);
2507 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2508 if (unlikely(Rc(ctx->opcode) != 0)) {
2509 gen_set_cr1_from_fpscr(ctx);
2510 }
2511 }
2512
2513 static void gen_fsqrts(DisasContext *ctx)
2514 {
2515 if (unlikely(!ctx->fpu_enabled)) {
2516 gen_exception(ctx, POWERPC_EXCP_FPU);
2517 return;
2518 }
2519 /* NIP cannot be restored if the memory exception comes from an helper */
2520 gen_update_nip(ctx, ctx->nip - 4);
2521 gen_reset_fpstatus();
2522 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2523 cpu_fpr[rB(ctx->opcode)]);
2524 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2525 cpu_fpr[rD(ctx->opcode)]);
2526 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2527 if (unlikely(Rc(ctx->opcode) != 0)) {
2528 gen_set_cr1_from_fpscr(ctx);
2529 }
2530 }
2531
2532 /*** Floating-Point multiply-and-add ***/
2533 /* fmadd - fmadds */
2534 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2535 /* fmsub - fmsubs */
2536 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2537 /* fnmadd - fnmadds */
2538 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2539 /* fnmsub - fnmsubs */
2540 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2541
2542 /*** Floating-Point round & convert ***/
2543 /* fctiw */
2544 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2545 /* fctiwu */
2546 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2547 /* fctiwz */
2548 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2549 /* fctiwuz */
2550 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2551 /* frsp */
2552 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2553 /* fcfid */
2554 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
2555 /* fcfids */
2556 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2557 /* fcfidu */
2558 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2559 /* fcfidus */
2560 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2561 /* fctid */
2562 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
2563 /* fctidu */
2564 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2565 /* fctidz */
2566 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
2567 /* fctidu */
2568 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2569
2570 /* frin */
2571 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2572 /* friz */
2573 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2574 /* frip */
2575 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2576 /* frim */
2577 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2578
2579 static void gen_ftdiv(DisasContext *ctx)
2580 {
2581 if (unlikely(!ctx->fpu_enabled)) {
2582 gen_exception(ctx, POWERPC_EXCP_FPU);
2583 return;
2584 }
2585 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2586 cpu_fpr[rB(ctx->opcode)]);
2587 }
2588
2589 static void gen_ftsqrt(DisasContext *ctx)
2590 {
2591 if (unlikely(!ctx->fpu_enabled)) {
2592 gen_exception(ctx, POWERPC_EXCP_FPU);
2593 return;
2594 }
2595 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2596 }
2597
2598
2599
2600 /*** Floating-Point compare ***/
2601
2602 /* fcmpo */
2603 static void gen_fcmpo(DisasContext *ctx)
2604 {
2605 TCGv_i32 crf;
2606 if (unlikely(!ctx->fpu_enabled)) {
2607 gen_exception(ctx, POWERPC_EXCP_FPU);
2608 return;
2609 }
2610 /* NIP cannot be restored if the memory exception comes from an helper */
2611 gen_update_nip(ctx, ctx->nip - 4);
2612 gen_reset_fpstatus();
2613 crf = tcg_const_i32(crfD(ctx->opcode));
2614 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2615 cpu_fpr[rB(ctx->opcode)], crf);
2616 tcg_temp_free_i32(crf);
2617 gen_helper_float_check_status(cpu_env);
2618 }
2619
2620 /* fcmpu */
2621 static void gen_fcmpu(DisasContext *ctx)
2622 {
2623 TCGv_i32 crf;
2624 if (unlikely(!ctx->fpu_enabled)) {
2625 gen_exception(ctx, POWERPC_EXCP_FPU);
2626 return;
2627 }
2628 /* NIP cannot be restored if the memory exception comes from an helper */
2629 gen_update_nip(ctx, ctx->nip - 4);
2630 gen_reset_fpstatus();
2631 crf = tcg_const_i32(crfD(ctx->opcode));
2632 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2633 cpu_fpr[rB(ctx->opcode)], crf);
2634 tcg_temp_free_i32(crf);
2635 gen_helper_float_check_status(cpu_env);
2636 }
2637
2638 /*** Floating-point move ***/
2639 /* fabs */
2640 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2641 static void gen_fabs(DisasContext *ctx)
2642 {
2643 if (unlikely(!ctx->fpu_enabled)) {
2644 gen_exception(ctx, POWERPC_EXCP_FPU);
2645 return;
2646 }
2647 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2648 ~(1ULL << 63));
2649 if (unlikely(Rc(ctx->opcode))) {
2650 gen_set_cr1_from_fpscr(ctx);
2651 }
2652 }
2653
2654 /* fmr - fmr. */
2655 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2656 static void gen_fmr(DisasContext *ctx)
2657 {
2658 if (unlikely(!ctx->fpu_enabled)) {
2659 gen_exception(ctx, POWERPC_EXCP_FPU);
2660 return;
2661 }
2662 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2663 if (unlikely(Rc(ctx->opcode))) {
2664 gen_set_cr1_from_fpscr(ctx);
2665 }
2666 }
2667
2668 /* fnabs */
2669 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2670 static void gen_fnabs(DisasContext *ctx)
2671 {
2672 if (unlikely(!ctx->fpu_enabled)) {
2673 gen_exception(ctx, POWERPC_EXCP_FPU);
2674 return;
2675 }
2676 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2677 1ULL << 63);
2678 if (unlikely(Rc(ctx->opcode))) {
2679 gen_set_cr1_from_fpscr(ctx);
2680 }
2681 }
2682
2683 /* fneg */
2684 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2685 static void gen_fneg(DisasContext *ctx)
2686 {
2687 if (unlikely(!ctx->fpu_enabled)) {
2688 gen_exception(ctx, POWERPC_EXCP_FPU);
2689 return;
2690 }
2691 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2692 1ULL << 63);
2693 if (unlikely(Rc(ctx->opcode))) {
2694 gen_set_cr1_from_fpscr(ctx);
2695 }
2696 }
2697
2698 /* fcpsgn: PowerPC 2.05 specification */
2699 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2700 static void gen_fcpsgn(DisasContext *ctx)
2701 {
2702 if (unlikely(!ctx->fpu_enabled)) {
2703 gen_exception(ctx, POWERPC_EXCP_FPU);
2704 return;
2705 }
2706 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2707 cpu_fpr[rB(ctx->opcode)], 0, 63);
2708 if (unlikely(Rc(ctx->opcode))) {
2709 gen_set_cr1_from_fpscr(ctx);
2710 }
2711 }
2712
2713 static void gen_fmrgew(DisasContext *ctx)
2714 {
2715 TCGv_i64 b0;
2716 if (unlikely(!ctx->fpu_enabled)) {
2717 gen_exception(ctx, POWERPC_EXCP_FPU);
2718 return;
2719 }
2720 b0 = tcg_temp_new_i64();
2721 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2722 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2723 b0, 0, 32);
2724 tcg_temp_free_i64(b0);
2725 }
2726
2727 static void gen_fmrgow(DisasContext *ctx)
2728 {
2729 if (unlikely(!ctx->fpu_enabled)) {
2730 gen_exception(ctx, POWERPC_EXCP_FPU);
2731 return;
2732 }
2733 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2734 cpu_fpr[rB(ctx->opcode)],
2735 cpu_fpr[rA(ctx->opcode)],
2736 32, 32);
2737 }
2738
2739 /*** Floating-Point status & ctrl register ***/
2740
2741 /* mcrfs */
2742 static void gen_mcrfs(DisasContext *ctx)
2743 {
2744 TCGv tmp = tcg_temp_new();
2745 TCGv_i32 tmask;
2746 TCGv_i64 tnew_fpscr = tcg_temp_new_i64();
2747 int bfa;
2748 int nibble;
2749 int shift;
2750
2751 if (unlikely(!ctx->fpu_enabled)) {
2752 gen_exception(ctx, POWERPC_EXCP_FPU);
2753 return;
2754 }
2755 bfa = crfS(ctx->opcode);
2756 nibble = 7 - bfa;
2757 shift = 4 * nibble;
2758 tcg_gen_shri_tl(tmp, cpu_fpscr, shift);
2759 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2760 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2761 tcg_temp_free(tmp);
2762 tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
2763 /* Only the exception bits (including FX) should be cleared if read */
2764 tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, ~((0xF << shift) & FP_EX_CLEAR_BITS));
2765 /* FEX and VX need to be updated, so don't set fpscr directly */
2766 tmask = tcg_const_i32(1 << nibble);
2767 gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
2768 tcg_temp_free_i32(tmask);
2769 tcg_temp_free_i64(tnew_fpscr);
2770 }
2771
2772 /* mffs */
2773 static void gen_mffs(DisasContext *ctx)
2774 {
2775 if (unlikely(!ctx->fpu_enabled)) {
2776 gen_exception(ctx, POWERPC_EXCP_FPU);
2777 return;
2778 }
2779 gen_reset_fpstatus();
2780 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2781 if (unlikely(Rc(ctx->opcode))) {
2782 gen_set_cr1_from_fpscr(ctx);
2783 }
2784 }
2785
2786 /* mtfsb0 */
2787 static void gen_mtfsb0(DisasContext *ctx)
2788 {
2789 uint8_t crb;
2790
2791 if (unlikely(!ctx->fpu_enabled)) {
2792 gen_exception(ctx, POWERPC_EXCP_FPU);
2793 return;
2794 }
2795 crb = 31 - crbD(ctx->opcode);
2796 gen_reset_fpstatus();
2797 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2798 TCGv_i32 t0;
2799 /* NIP cannot be restored if the memory exception comes from an helper */
2800 gen_update_nip(ctx, ctx->nip - 4);
2801 t0 = tcg_const_i32(crb);
2802 gen_helper_fpscr_clrbit(cpu_env, t0);
2803 tcg_temp_free_i32(t0);
2804 }
2805 if (unlikely(Rc(ctx->opcode) != 0)) {
2806 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2807 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2808 }
2809 }
2810
2811 /* mtfsb1 */
2812 static void gen_mtfsb1(DisasContext *ctx)
2813 {
2814 uint8_t crb;
2815
2816 if (unlikely(!ctx->fpu_enabled)) {
2817 gen_exception(ctx, POWERPC_EXCP_FPU);
2818 return;
2819 }
2820 crb = 31 - crbD(ctx->opcode);
2821 gen_reset_fpstatus();
2822 /* XXX: we pretend we can only do IEEE floating-point computations */
2823 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2824 TCGv_i32 t0;
2825 /* NIP cannot be restored if the memory exception comes from an helper */
2826 gen_update_nip(ctx, ctx->nip - 4);
2827 t0 = tcg_const_i32(crb);
2828 gen_helper_fpscr_setbit(cpu_env, t0);
2829 tcg_temp_free_i32(t0);
2830 }
2831 if (unlikely(Rc(ctx->opcode) != 0)) {
2832 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2833 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2834 }
2835 /* We can raise a differed exception */
2836 gen_helper_float_check_status(cpu_env);
2837 }
2838
2839 /* mtfsf */
2840 static void gen_mtfsf(DisasContext *ctx)
2841 {
2842 TCGv_i32 t0;
2843 int flm, l, w;
2844
2845 if (unlikely(!ctx->fpu_enabled)) {
2846 gen_exception(ctx, POWERPC_EXCP_FPU);
2847 return;
2848 }
2849 flm = FPFLM(ctx->opcode);
2850 l = FPL(ctx->opcode);
2851 w = FPW(ctx->opcode);
2852 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2853 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2854 return;
2855 }
2856 /* NIP cannot be restored if the memory exception comes from an helper */
2857 gen_update_nip(ctx, ctx->nip - 4);
2858 gen_reset_fpstatus();
2859 if (l) {
2860 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2861 } else {
2862 t0 = tcg_const_i32(flm << (w * 8));
2863 }
2864 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2865 tcg_temp_free_i32(t0);
2866 if (unlikely(Rc(ctx->opcode) != 0)) {
2867 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2868 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2869 }
2870 /* We can raise a differed exception */
2871 gen_helper_float_check_status(cpu_env);
2872 }
2873
2874 /* mtfsfi */
2875 static void gen_mtfsfi(DisasContext *ctx)
2876 {
2877 int bf, sh, w;
2878 TCGv_i64 t0;
2879 TCGv_i32 t1;
2880
2881 if (unlikely(!ctx->fpu_enabled)) {
2882 gen_exception(ctx, POWERPC_EXCP_FPU);
2883 return;
2884 }
2885 w = FPW(ctx->opcode);
2886 bf = FPBF(ctx->opcode);
2887 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2888 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2889 return;
2890 }
2891 sh = (8 * w) + 7 - bf;
2892 /* NIP cannot be restored if the memory exception comes from an helper */
2893 gen_update_nip(ctx, ctx->nip - 4);
2894 gen_reset_fpstatus();
2895 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2896 t1 = tcg_const_i32(1 << sh);
2897 gen_helper_store_fpscr(cpu_env, t0, t1);
2898 tcg_temp_free_i64(t0);
2899 tcg_temp_free_i32(t1);
2900 if (unlikely(Rc(ctx->opcode) != 0)) {
2901 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2902 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2903 }
2904 /* We can raise a differed exception */
2905 gen_helper_float_check_status(cpu_env);
2906 }
2907
2908 /*** Addressing modes ***/
2909 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2910 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2911 target_long maskl)
2912 {
2913 target_long simm = SIMM(ctx->opcode);
2914
2915 simm &= ~maskl;
2916 if (rA(ctx->opcode) == 0) {
2917 if (NARROW_MODE(ctx)) {
2918 simm = (uint32_t)simm;
2919 }
2920 tcg_gen_movi_tl(EA, simm);
2921 } else if (likely(simm != 0)) {
2922 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2923 if (NARROW_MODE(ctx)) {
2924 tcg_gen_ext32u_tl(EA, EA);
2925 }
2926 } else {
2927 if (NARROW_MODE(ctx)) {
2928 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2929 } else {
2930 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2931 }
2932 }
2933 }
2934
2935 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2936 {
2937 if (rA(ctx->opcode) == 0) {
2938 if (NARROW_MODE(ctx)) {
2939 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2940 } else {
2941 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2942 }
2943 } else {
2944 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2945 if (NARROW_MODE(ctx)) {
2946 tcg_gen_ext32u_tl(EA, EA);
2947 }
2948 }
2949 }
2950
2951 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2952 {
2953 if (rA(ctx->opcode) == 0) {
2954 tcg_gen_movi_tl(EA, 0);
2955 } else if (NARROW_MODE(ctx)) {
2956 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2957 } else {
2958 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2959 }
2960 }
2961
2962 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2963 target_long val)
2964 {
2965 tcg_gen_addi_tl(ret, arg1, val);
2966 if (NARROW_MODE(ctx)) {
2967 tcg_gen_ext32u_tl(ret, ret);
2968 }
2969 }
2970
2971 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2972 {
2973 TCGLabel *l1 = gen_new_label();
2974 TCGv t0 = tcg_temp_new();
2975 TCGv_i32 t1, t2;
2976 /* NIP cannot be restored if the memory exception comes from an helper */
2977 gen_update_nip(ctx, ctx->nip - 4);
2978 tcg_gen_andi_tl(t0, EA, mask);
2979 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2980 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2981 t2 = tcg_const_i32(0);
2982 gen_helper_raise_exception_err(cpu_env, t1, t2);
2983 tcg_temp_free_i32(t1);
2984 tcg_temp_free_i32(t2);
2985 gen_set_label(l1);
2986 tcg_temp_free(t0);
2987 }
2988
2989 /*** Integer load ***/
2990 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2991 {
2992 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2993 }
2994
2995 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2996 {
2997 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2998 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2999 }
3000
3001 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
3002 {
3003 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
3004 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3005 }
3006
3007 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
3008 {
3009 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
3010 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3011 }
3012
3013 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
3014 {
3015 TCGv tmp = tcg_temp_new();
3016 gen_qemu_ld32u(ctx, tmp, addr);
3017 tcg_gen_extu_tl_i64(val, tmp);
3018 tcg_temp_free(tmp);
3019 }
3020
3021 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
3022 {
3023 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
3024 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3025 }
3026
3027 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
3028 {
3029 TCGv tmp = tcg_temp_new();
3030 gen_qemu_ld32s(ctx, tmp, addr);
3031 tcg_gen_ext_tl_i64(val, tmp);
3032 tcg_temp_free(tmp);
3033 }
3034
3035 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3036 {
3037 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
3038 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3039 }
3040
3041 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
3042 {
3043 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
3044 }
3045
3046 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
3047 {
3048 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
3049 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3050 }
3051
3052 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
3053 {
3054 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
3055 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3056 }
3057
3058 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
3059 {
3060 TCGv tmp = tcg_temp_new();
3061 tcg_gen_trunc_i64_tl(tmp, val);
3062 gen_qemu_st32(ctx, tmp, addr);
3063 tcg_temp_free(tmp);
3064 }
3065
3066 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3067 {
3068 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
3069 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3070 }
3071
3072 #define GEN_LD(name, ldop, opc, type) \
3073 static void glue(gen_, name)(DisasContext *ctx) \
3074 { \
3075 TCGv EA; \
3076 gen_set_access_type(ctx, ACCESS_INT); \
3077 EA = tcg_temp_new(); \
3078 gen_addr_imm_index(ctx, EA, 0); \
3079 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
3080 tcg_temp_free(EA); \
3081 }
3082
3083 #define GEN_LDU(name, ldop, opc, type) \
3084 static void glue(gen_, name##u)(DisasContext *ctx) \
3085 { \
3086 TCGv EA; \
3087 if (unlikely(rA(ctx->opcode) == 0 || \
3088 rA(ctx->opcode) == rD(ctx->opcode))) { \
3089 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3090 return; \
3091 } \
3092 gen_set_access_type(ctx, ACCESS_INT); \
3093 EA = tcg_temp_new(); \
3094 if (type == PPC_64B) \
3095 gen_addr_imm_index(ctx, EA, 0x03); \
3096 else \
3097 gen_addr_imm_index(ctx, EA, 0); \
3098 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
3099 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3100 tcg_temp_free(EA); \
3101 }
3102
3103 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
3104 static void glue(gen_, name##ux)(DisasContext *ctx) \
3105 { \
3106 TCGv EA; \
3107 if (unlikely(rA(ctx->opcode) == 0 || \
3108 rA(ctx->opcode) == rD(ctx->opcode))) { \
3109 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3110 return; \
3111 } \
3112 gen_set_access_type(ctx, ACCESS_INT); \
3113 EA = tcg_temp_new(); \
3114 gen_addr_reg_index(ctx, EA); \
3115 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
3116 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3117 tcg_temp_free(EA); \
3118 }
3119
3120 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
3121 static void glue(gen_, name##x)(DisasContext *ctx) \
3122 { \
3123 TCGv EA; \
3124 chk; \
3125 gen_set_access_type(ctx, ACCESS_INT); \
3126 EA = tcg_temp_new(); \
3127 gen_addr_reg_index(ctx, EA); \
3128 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
3129 tcg_temp_free(EA); \
3130 }
3131
3132 #define GEN_LDX(name, ldop, opc2, opc3, type) \
3133 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3134
3135 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
3136 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
3137
3138 #define GEN_LDS(name, ldop, op, type) \
3139 GEN_LD(name, ldop, op | 0x20, type); \
3140 GEN_LDU(name, ldop, op | 0x21, type); \
3141 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
3142 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
3143
3144 /* lbz lbzu lbzux lbzx */
3145 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
3146 /* lha lhau lhaux lhax */
3147 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
3148 /* lhz lhzu lhzux lhzx */
3149 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
3150 /* lwz lwzu lwzux lwzx */
3151 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
3152 #if defined(TARGET_PPC64)
3153 /* lwaux */
3154 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
3155 /* lwax */
3156 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
3157 /* ldux */
3158 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
3159 /* ldx */
3160 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
3161
3162 /* CI load/store variants */
3163 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
3164 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
3165 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
3166 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
3167
3168 static void gen_ld(DisasContext *ctx)
3169 {
3170 TCGv EA;
3171 if (Rc(ctx->opcode)) {
3172 if (unlikely(rA(ctx->opcode) == 0 ||
3173 rA(ctx->opcode) == rD(ctx->opcode))) {
3174 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3175 return;
3176 }
3177 }
3178 gen_set_access_type(ctx, ACCESS_INT);
3179 EA = tcg_temp_new();
3180 gen_addr_imm_index(ctx, EA, 0x03);
3181 if (ctx->opcode & 0x02) {
3182 /* lwa (lwau is undefined) */
3183 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
3184 } else {
3185 /* ld - ldu */
3186 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
3187 }
3188 if (Rc(ctx->opcode))
3189 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3190 tcg_temp_free(EA);
3191 }
3192
3193 /* lq */
3194 static void gen_lq(DisasContext *ctx)
3195 {
3196 int ra, rd;
3197 TCGv EA;
3198
3199 /* lq is a legal user mode instruction starting in ISA 2.07 */
3200 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3201 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3202
3203 if (!legal_in_user_mode && ctx->pr) {
3204 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3205 return;
3206 }
3207
3208 if (!le_is_supported && ctx->le_mode) {
3209 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3210 return;
3211 }
3212
3213 ra = rA(ctx->opcode);
3214 rd = rD(ctx->opcode);
3215 if (unlikely((rd & 1) || rd == ra)) {
3216 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3217 return;
3218 }
3219
3220 gen_set_access_type(ctx, ACCESS_INT);
3221 EA = tcg_temp_new();
3222 gen_addr_imm_index(ctx, EA, 0x0F);
3223
3224 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3225 64-bit byteswap already. */
3226 if (unlikely(ctx->le_mode)) {
3227 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
3228 gen_addr_add(ctx, EA, EA, 8);
3229 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
3230 } else {
3231 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
3232 gen_addr_add(ctx, EA, EA, 8);
3233 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
3234 }
3235 tcg_temp_free(EA);
3236 }
3237 #endif
3238
3239 /*** Integer store ***/
3240 #define GEN_ST(name, stop, opc, type) \
3241 static void glue(gen_, name)(DisasContext *ctx) \
3242 { \
3243 TCGv EA; \
3244 gen_set_access_type(ctx, ACCESS_INT); \
3245 EA = tcg_temp_new(); \
3246 gen_addr_imm_index(ctx, EA, 0); \
3247 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3248 tcg_temp_free(EA); \
3249 }
3250
3251 #define GEN_STU(name, stop, opc, type) \
3252 static void glue(gen_, stop##u)(DisasContext *ctx) \
3253 { \
3254 TCGv EA; \
3255 if (unlikely(rA(ctx->opcode) == 0)) { \
3256 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3257 return; \
3258 } \
3259 gen_set_access_type(ctx, ACCESS_INT); \
3260 EA = tcg_temp_new(); \
3261 if (type == PPC_64B) \
3262 gen_addr_imm_index(ctx, EA, 0x03); \
3263 else \
3264 gen_addr_imm_index(ctx, EA, 0); \
3265 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3266 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3267 tcg_temp_free(EA); \
3268 }
3269
3270 #define GEN_STUX(name, stop, opc2, opc3, type) \
3271 static void glue(gen_, name##ux)(DisasContext *ctx) \
3272 { \
3273 TCGv EA; \
3274 if (unlikely(rA(ctx->opcode) == 0)) { \
3275 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3276 return; \
3277 } \
3278 gen_set_access_type(ctx, ACCESS_INT); \
3279 EA = tcg_temp_new(); \
3280 gen_addr_reg_index(ctx, EA); \
3281 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3282 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3283 tcg_temp_free(EA); \
3284 }
3285
3286 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
3287 static void glue(gen_, name##x)(DisasContext *ctx) \
3288 { \
3289 TCGv EA; \
3290 chk; \
3291 gen_set_access_type(ctx, ACCESS_INT); \
3292 EA = tcg_temp_new(); \
3293 gen_addr_reg_index(ctx, EA); \
3294 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3295 tcg_temp_free(EA); \
3296 }
3297 #define GEN_STX(name, stop, opc2, opc3, type) \
3298 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3299
3300 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
3301 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
3302
3303 #define GEN_STS(name, stop, op, type) \
3304 GEN_ST(name, stop, op | 0x20, type); \
3305 GEN_STU(name, stop, op | 0x21, type); \
3306 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3307 GEN_STX(name, stop, 0x17, op | 0x00, type)
3308
3309 /* stb stbu stbux stbx */
3310 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3311 /* sth sthu sthux sthx */
3312 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3313 /* stw stwu stwux stwx */
3314 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3315 #if defined(TARGET_PPC64)
3316 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3317 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
3318 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
3319 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
3320 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
3321 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
3322
3323 static void gen_std(DisasContext *ctx)
3324 {
3325 int rs;
3326 TCGv EA;
3327
3328 rs = rS(ctx->opcode);
3329 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3330 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3331 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3332
3333 if (!(ctx->insns_flags & PPC_64BX)) {
3334 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3335 }
3336
3337 if (!legal_in_user_mode && ctx->pr) {
3338 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3339 return;
3340 }
3341
3342 if (!le_is_supported && ctx->le_mode) {
3343 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3344 return;
3345 }
3346
3347 if (unlikely(rs & 1)) {
3348 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3349 return;
3350 }
3351 gen_set_access_type(ctx, ACCESS_INT);
3352 EA = tcg_temp_new();
3353 gen_addr_imm_index(ctx, EA, 0x03);
3354
3355 /* We only need to swap high and low halves. gen_qemu_st64 does
3356 necessary 64-bit byteswap already. */
3357 if (unlikely(ctx->le_mode)) {
3358 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3359 gen_addr_add(ctx, EA, EA, 8);
3360 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3361 } else {
3362 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3363 gen_addr_add(ctx, EA, EA, 8);
3364 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3365 }
3366 tcg_temp_free(EA);
3367 } else {
3368 /* std / stdu*/
3369 if (Rc(ctx->opcode)) {
3370 if (unlikely(rA(ctx->opcode) == 0)) {
3371 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3372 return;
3373 }
3374 }
3375 gen_set_access_type(ctx, ACCESS_INT);
3376 EA = tcg_temp_new();
3377 gen_addr_imm_index(ctx, EA, 0x03);
3378 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3379 if (Rc(ctx->opcode))
3380 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3381 tcg_temp_free(EA);
3382 }
3383 }
3384 #endif
3385 /*** Integer load and store with byte reverse ***/
3386
3387 /* lhbrx */
3388 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3389 {
3390 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3391 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3392 }
3393 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3394
3395 /* lwbrx */
3396 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3397 {
3398 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3399 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3400 }
3401 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3402
3403 #if defined(TARGET_PPC64)
3404 /* ldbrx */
3405 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3406 {
3407 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3408 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3409 }
3410 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
3411 #endif /* TARGET_PPC64 */
3412
3413 /* sthbrx */
3414 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3415 {
3416 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3417 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3418 }
3419 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3420
3421 /* stwbrx */
3422 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3423 {
3424 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3425 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3426 }
3427 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3428
3429 #if defined(TARGET_PPC64)
3430 /* stdbrx */
3431 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3432 {
3433 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3434 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3435 }
3436 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
3437 #endif /* TARGET_PPC64 */
3438
3439 /*** Integer load and store multiple ***/
3440
3441 /* lmw */
3442 static void gen_lmw(DisasContext *ctx)
3443 {
3444 TCGv t0;
3445 TCGv_i32 t1;
3446 gen_set_access_type(ctx, ACCESS_INT);
3447 /* NIP cannot be restored if the memory exception comes from an helper */
3448 gen_update_nip(ctx, ctx->nip - 4);
3449 t0 = tcg_temp_new();
3450 t1 = tcg_const_i32(rD(ctx->opcode));
3451 gen_addr_imm_index(ctx, t0, 0);
3452 gen_helper_lmw(cpu_env, t0, t1);
3453 tcg_temp_free(t0);
3454 tcg_temp_free_i32(t1);
3455 }
3456
3457 /* stmw */
3458 static void gen_stmw(DisasContext *ctx)
3459 {
3460 TCGv t0;
3461 TCGv_i32 t1;
3462 gen_set_access_type(ctx, ACCESS_INT);
3463 /* NIP cannot be restored if the memory exception comes from an helper */
3464 gen_update_nip(ctx, ctx->nip - 4);
3465 t0 = tcg_temp_new();
3466 t1 = tcg_const_i32(rS(ctx->opcode));
3467 gen_addr_imm_index(ctx, t0, 0);
3468 gen_helper_stmw(cpu_env, t0, t1);
3469 tcg_temp_free(t0);
3470 tcg_temp_free_i32(t1);
3471 }
3472
3473 /*** Integer load and store strings ***/
3474
3475 /* lswi */
3476 /* PowerPC32 specification says we must generate an exception if
3477 * rA is in the range of registers to be loaded.
3478 * In an other hand, IBM says this is valid, but rA won't be loaded.
3479 * For now, I'll follow the spec...
3480 */
3481 static void gen_lswi(DisasContext *ctx)
3482 {
3483 TCGv t0;
3484 TCGv_i32 t1, t2;
3485 int nb = NB(ctx->opcode);
3486 int start = rD(ctx->opcode);
3487 int ra = rA(ctx->opcode);
3488 int nr;
3489
3490 if (nb == 0)
3491 nb = 32;
3492 nr = (nb + 3) / 4;
3493 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
3494 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3495 return;
3496 }
3497 gen_set_access_type(ctx, ACCESS_INT);
3498 /* NIP cannot be restored if the memory exception comes from an helper */
3499 gen_update_nip(ctx, ctx->nip - 4);
3500 t0 = tcg_temp_new();
3501 gen_addr_register(ctx, t0);
3502 t1 = tcg_const_i32(nb);
3503 t2 = tcg_const_i32(start);
3504 gen_helper_lsw(cpu_env, t0, t1, t2);
3505 tcg_temp_free(t0);
3506 tcg_temp_free_i32(t1);
3507 tcg_temp_free_i32(t2);
3508 }
3509
3510 /* lswx */
3511 static void gen_lswx(DisasContext *ctx)
3512 {
3513 TCGv t0;
3514 TCGv_i32 t1, t2, t3;
3515 gen_set_access_type(ctx, ACCESS_INT);
3516 /* NIP cannot be restored if the memory exception comes from an helper */
3517 gen_update_nip(ctx, ctx->nip - 4);
3518 t0 = tcg_temp_new();
3519 gen_addr_reg_index(ctx, t0);
3520 t1 = tcg_const_i32(rD(ctx->opcode));
3521 t2 = tcg_const_i32(rA(ctx->opcode));
3522 t3 = tcg_const_i32(rB(ctx->opcode));
3523 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3524 tcg_temp_free(t0);
3525 tcg_temp_free_i32(t1);
3526 tcg_temp_free_i32(t2);
3527 tcg_temp_free_i32(t3);
3528 }
3529
3530 /* stswi */
3531 static void gen_stswi(DisasContext *ctx)
3532 {
3533 TCGv t0;
3534 TCGv_i32 t1, t2;
3535 int nb = NB(ctx->opcode);
3536 gen_set_access_type(ctx, ACCESS_INT);
3537 /* NIP cannot be restored if the memory exception comes from an helper */
3538 gen_update_nip(ctx, ctx->nip - 4);
3539 t0 = tcg_temp_new();
3540 gen_addr_register(ctx, t0);
3541 if (nb == 0)
3542 nb = 32;
3543 t1 = tcg_const_i32(nb);
3544 t2 = tcg_const_i32(rS(ctx->opcode));
3545 gen_helper_stsw(cpu_env, t0, t1, t2);
3546 tcg_temp_free(t0);
3547 tcg_temp_free_i32(t1);
3548 tcg_temp_free_i32(t2);
3549 }
3550
3551 /* stswx */
3552 static void gen_stswx(DisasContext *ctx)
3553 {
3554 TCGv t0;
3555 TCGv_i32 t1, t2;
3556 gen_set_access_type(ctx, ACCESS_INT);
3557 /* NIP cannot be restored if the memory exception comes from an helper */
3558 gen_update_nip(ctx, ctx->nip - 4);
3559 t0 = tcg_temp_new();
3560 gen_addr_reg_index(ctx, t0);
3561 t1 = tcg_temp_new_i32();
3562 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3563 tcg_gen_andi_i32(t1, t1, 0x7F);
3564 t2 = tcg_const_i32(rS(ctx->opcode));
3565 gen_helper_stsw(cpu_env, t0, t1, t2);
3566 tcg_temp_free(t0);
3567 tcg_temp_free_i32(t1);
3568 tcg_temp_free_i32(t2);
3569 }
3570
3571 /*** Memory synchronisation ***/
3572 /* eieio */
3573 static void gen_eieio(DisasContext *ctx)
3574 {
3575 }
3576
3577 #if !defined(CONFIG_USER_ONLY)
3578 static inline void gen_check_tlb_flush(DisasContext *ctx)
3579 {
3580 TCGv_i32 t;
3581 TCGLabel *l;
3582
3583 if (!ctx->lazy_tlb_flush) {
3584 return;
3585 }
3586 l = gen_new_label();
3587 t = tcg_temp_new_i32();
3588 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3589 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3590 gen_helper_check_tlb_flush(cpu_env);
3591 gen_set_label(l);
3592 tcg_temp_free_i32(t);
3593 }
3594 #else
3595 static inline void gen_check_tlb_flush(DisasContext *ctx) { }
3596 #endif
3597
3598 /* isync */
3599 static void gen_isync(DisasContext *ctx)
3600 {
3601 /*
3602 * We need to check for a pending TLB flush. This can only happen in
3603 * kernel mode however so check MSR_PR
3604 */
3605 if (!ctx->pr) {
3606 gen_check_tlb_flush(ctx);
3607 }
3608 gen_stop_exception(ctx);
3609 }
3610
3611 #define LARX(name, len, loadop) \
3612 static void gen_##name(DisasContext *ctx) \
3613 { \
3614 TCGv t0; \
3615 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3616 gen_set_access_type(ctx, ACCESS_RES); \
3617 t0 = tcg_temp_local_new(); \
3618 gen_addr_reg_index(ctx, t0); \
3619 if ((len) > 1) { \
3620 gen_check_align(ctx, t0, (len)-1); \
3621 } \
3622 gen_qemu_##loadop(ctx, gpr, t0); \
3623 tcg_gen_mov_tl(cpu_reserve, t0); \
3624 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3625 tcg_temp_free(t0); \
3626 }
3627
3628 /* lwarx */
3629 LARX(lbarx, 1, ld8u);
3630 LARX(lharx, 2, ld16u);
3631 LARX(lwarx, 4, ld32u);
3632
3633
3634 #if defined(CONFIG_USER_ONLY)
3635 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3636 int reg, int size)
3637 {
3638 TCGv t0 = tcg_temp_new();
3639 uint32_t save_exception = ctx->exception;
3640
3641 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3642 tcg_gen_movi_tl(t0, (size << 5) | reg);
3643 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3644 tcg_temp_free(t0);
3645 gen_update_nip(ctx, ctx->nip-4);
3646 ctx->exception = POWERPC_EXCP_BRANCH;
3647 gen_exception(ctx, POWERPC_EXCP_STCX);
3648 ctx->exception = save_exception;
3649 }
3650 #else
3651 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3652 int reg, int size)
3653 {
3654 TCGLabel *l1;
3655
3656 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3657 l1 = gen_new_label();
3658 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3659 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3660 #if defined(TARGET_PPC64)
3661 if (size == 8) {
3662 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3663 } else
3664 #endif
3665 if (size == 4) {
3666 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3667 } else if (size == 2) {
3668 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3669 #if defined(TARGET_PPC64)
3670 } else if (size == 16) {
3671 TCGv gpr1, gpr2 , EA8;
3672 if (unlikely(ctx->le_mode)) {
3673 gpr1 = cpu_gpr[reg+1];
3674 gpr2 = cpu_gpr[reg];
3675 } else {
3676 gpr1 = cpu_gpr[reg];
3677 gpr2 = cpu_gpr[reg+1];
3678 }
3679 gen_qemu_st64(ctx, gpr1, EA);
3680 EA8 = tcg_temp_local_new();
3681 gen_addr_add(ctx, EA8, EA, 8);
3682 gen_qemu_st64(ctx, gpr2, EA8);
3683 tcg_temp_free(EA8);
3684 #endif
3685 } else {
3686 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3687 }
3688 gen_set_label(l1);
3689 tcg_gen_movi_tl(cpu_reserve, -1);
3690 }
3691 #endif
3692
3693 #define STCX(name, len) \
3694 static void gen_##name(DisasContext *ctx) \
3695 { \
3696 TCGv t0; \
3697 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3698 gen_inval_exception(ctx, \
3699 POWERPC_EXCP_INVAL_INVAL); \
3700 return; \
3701 } \
3702 gen_set_access_type(ctx, ACCESS_RES); \
3703 t0 = tcg_temp_local_new(); \
3704 gen_addr_reg_index(ctx, t0); \
3705 if (len > 1) { \
3706 gen_check_align(ctx, t0, (len)-1); \
3707 } \
3708 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3709 tcg_temp_free(t0); \
3710 }
3711
3712 STCX(stbcx_, 1);
3713 STCX(sthcx_, 2);
3714 STCX(stwcx_, 4);
3715
3716 #if defined(TARGET_PPC64)
3717 /* ldarx */
3718 LARX(ldarx, 8, ld64);
3719
3720 /* lqarx */
3721 static void gen_lqarx(DisasContext *ctx)
3722 {
3723 TCGv EA;
3724 int rd = rD(ctx->opcode);
3725 TCGv gpr1, gpr2;
3726
3727 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3728 (rd == rB(ctx->opcode)))) {
3729 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3730 return;
3731 }
3732
3733 gen_set_access_type(ctx, ACCESS_RES);
3734 EA = tcg_temp_local_new();
3735 gen_addr_reg_index(ctx, EA);
3736 gen_check_align(ctx, EA, 15);
3737 if (unlikely(ctx->le_mode)) {
3738 gpr1 = cpu_gpr[rd+1];
3739 gpr2 = cpu_gpr[rd];
3740 } else {
3741 gpr1 = cpu_gpr[rd];
3742 gpr2 = cpu_gpr[rd+1];
3743 }
3744 gen_qemu_ld64(ctx, gpr1, EA);
3745 tcg_gen_mov_tl(cpu_reserve, EA);
3746
3747 gen_addr_add(ctx, EA, EA, 8);
3748 gen_qemu_ld64(ctx, gpr2, EA);
3749
3750 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3751 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3752
3753 tcg_temp_free(EA);
3754 }
3755
3756 /* stdcx. */
3757 STCX(stdcx_, 8);
3758 STCX(stqcx_, 16);
3759 #endif /* defined(TARGET_PPC64) */
3760
3761 /* sync */
3762 static void gen_sync(DisasContext *ctx)
3763 {
3764 uint32_t l = (ctx->opcode >> 21) & 3;
3765
3766 /*
3767 * We may need to check for a pending TLB flush.
3768 *
3769 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3770 *
3771 * Additionally, this can only happen in kernel mode however so
3772 * check MSR_PR as well.
3773 */
3774 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3775 gen_check_tlb_flush(ctx);
3776 }
3777 }
3778
3779 /* wait */
3780 static void gen_wait(DisasContext *ctx)
3781 {
3782 TCGv_i32 t0 = tcg_const_i32(1);
3783 tcg_gen_st_i32(t0, cpu_env,
3784 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3785 tcg_temp_free_i32(t0);
3786 /* Stop translation, as the CPU is supposed to sleep from now */
3787 gen_exception_err(ctx, EXCP_HLT, 1);
3788 }
3789
3790 #if defined(TARGET_PPC64)
3791 static void gen_doze(DisasContext *ctx)
3792 {
3793 #if defined(CONFIG_USER_ONLY)
3794 GEN_PRIV;
3795 #else
3796 TCGv_i32 t;
3797
3798 CHK_HV;
3799 t = tcg_const_i32(PPC_PM_DOZE);
3800 gen_helper_pminsn(cpu_env, t);
3801 tcg_temp_free_i32(t);
3802 gen_stop_exception(ctx);
3803 #endif /* defined(CONFIG_USER_ONLY) */
3804 }
3805
3806 static void gen_nap(DisasContext *ctx)
3807 {
3808 #if defined(CONFIG_USER_ONLY)
3809 GEN_PRIV;
3810 #else
3811 TCGv_i32 t;
3812
3813 CHK_HV;
3814 t = tcg_const_i32(PPC_PM_NAP);
3815 gen_helper_pminsn(cpu_env, t);
3816 tcg_temp_free_i32(t);
3817 gen_stop_exception(ctx);
3818 #endif /* defined(CONFIG_USER_ONLY) */
3819 }
3820
3821 static void gen_sleep(DisasContext *ctx)
3822 {
3823 #if defined(CONFIG_USER_ONLY)
3824 GEN_PRIV;
3825 #else
3826 TCGv_i32 t;
3827
3828 CHK_HV;
3829 t = tcg_const_i32(PPC_PM_SLEEP);
3830 gen_helper_pminsn(cpu_env, t);
3831 tcg_temp_free_i32(t);
3832 gen_stop_exception(ctx);
3833 #endif /* defined(CONFIG_USER_ONLY) */
3834 }
3835
3836 static void gen_rvwinkle(DisasContext *ctx)
3837 {
3838 #if defined(CONFIG_USER_ONLY)
3839 GEN_PRIV;
3840 #else
3841 TCGv_i32 t;
3842
3843 CHK_HV;
3844 t = tcg_const_i32(PPC_PM_RVWINKLE);
3845 gen_helper_pminsn(cpu_env, t);
3846 tcg_temp_free_i32(t);
3847 gen_stop_exception(ctx);
3848 #endif /* defined(CONFIG_USER_ONLY) */
3849 }
3850 #endif /* #if defined(TARGET_PPC64) */
3851
3852 /*** Floating-point load ***/
3853 #define GEN_LDF(name, ldop, opc, type) \
3854 static void glue(gen_, name)(DisasContext *ctx) \
3855 { \
3856 TCGv EA; \
3857 if (unlikely(!ctx->fpu_enabled)) { \
3858 gen_exception(ctx, POWERPC_EXCP_FPU); \
3859 return; \
3860 } \
3861 gen_set_access_type(ctx, ACCESS_FLOAT); \
3862 EA = tcg_temp_new(); \
3863 gen_addr_imm_index(ctx, EA, 0); \
3864 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3865 tcg_temp_free(EA); \
3866 }
3867
3868 #define GEN_LDUF(name, ldop, opc, type) \
3869 static void glue(gen_, name##u)(DisasContext *ctx) \
3870 { \
3871 TCGv EA; \
3872 if (unlikely(!ctx->fpu_enabled)) { \
3873 gen_exception(ctx, POWERPC_EXCP_FPU); \
3874 return; \
3875 } \
3876 if (unlikely(rA(ctx->opcode) == 0)) { \
3877 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3878 return; \
3879 } \
3880 gen_set_access_type(ctx, ACCESS_FLOAT); \
3881 EA = tcg_temp_new(); \
3882 gen_addr_imm_index(ctx, EA, 0); \
3883 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3884 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3885 tcg_temp_free(EA); \
3886 }
3887
3888 #define GEN_LDUXF(name, ldop, opc, type) \
3889 static void glue(gen_, name##ux)(DisasContext *ctx) \
3890 { \
3891 TCGv EA; \
3892 if (unlikely(!ctx->fpu_enabled)) { \
3893 gen_exception(ctx, POWERPC_EXCP_FPU); \
3894 return; \
3895 } \
3896 if (unlikely(rA(ctx->opcode) == 0)) { \
3897 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3898 return; \
3899 } \
3900 gen_set_access_type(ctx, ACCESS_FLOAT); \
3901 EA = tcg_temp_new(); \
3902 gen_addr_reg_index(ctx, EA); \
3903 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3904 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3905 tcg_temp_free(EA); \
3906 }
3907
3908 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3909 static void glue(gen_, name##x)(DisasContext *ctx) \
3910 { \
3911 TCGv EA; \
3912 if (unlikely(!ctx->fpu_enabled)) { \
3913 gen_exception(ctx, POWERPC_EXCP_FPU); \
3914 return; \
3915 } \
3916 gen_set_access_type(ctx, ACCESS_FLOAT); \
3917 EA = tcg_temp_new(); \
3918 gen_addr_reg_index(ctx, EA); \
3919 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3920 tcg_temp_free(EA); \
3921 }
3922
3923 #define GEN_LDFS(name, ldop, op, type) \
3924 GEN_LDF(name, ldop, op | 0x20, type); \
3925 GEN_LDUF(name, ldop, op | 0x21, type); \
3926 GEN_LDUXF(name, ldop, op | 0x01, type); \
3927 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3928
3929 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3930 {
3931 TCGv t0 = tcg_temp_new();
3932 TCGv_i32 t1 = tcg_temp_new_i32();
3933 gen_qemu_ld32u(ctx, t0, arg2);
3934 tcg_gen_trunc_tl_i32(t1, t0);
3935 tcg_temp_free(t0);
3936 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3937 tcg_temp_free_i32(t1);
3938 }
3939
3940 /* lfd lfdu lfdux lfdx */
3941 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3942 /* lfs lfsu lfsux lfsx */
3943 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3944
3945 /* lfdp */
3946 static void gen_lfdp(DisasContext *ctx)
3947 {
3948 TCGv EA;
3949 if (unlikely(!ctx->fpu_enabled)) {
3950 gen_exception(ctx, POWERPC_EXCP_FPU);
3951 return;
3952 }
3953 gen_set_access_type(ctx, ACCESS_FLOAT);
3954 EA = tcg_temp_new();
3955 gen_addr_imm_index(ctx, EA, 0);
3956 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3957 64-bit byteswap already. */
3958 if (unlikely(ctx->le_mode)) {
3959 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3960 tcg_gen_addi_tl(EA, EA, 8);
3961 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3962 } else {
3963 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3964 tcg_gen_addi_tl(EA, EA, 8);
3965 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3966 }
3967 tcg_temp_free(EA);
3968 }
3969
3970 /* lfdpx */
3971 static void gen_lfdpx(DisasContext *ctx)
3972 {
3973 TCGv EA;
3974 if (unlikely(!ctx->fpu_enabled)) {
3975 gen_exception(ctx, POWERPC_EXCP_FPU);
3976 return;
3977 }
3978 gen_set_access_type(ctx, ACCESS_FLOAT);
3979 EA = tcg_temp_new();
3980 gen_addr_reg_index(ctx, EA);
3981 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3982 64-bit byteswap already. */
3983 if (unlikely(ctx->le_mode)) {
3984 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3985 tcg_gen_addi_tl(EA, EA, 8);
3986 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3987 } else {
3988 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3989 tcg_gen_addi_tl(EA, EA, 8);
3990 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3991 }
3992 tcg_temp_free(EA);
3993 }
3994
3995 /* lfiwax */
3996 static void gen_lfiwax(DisasContext *ctx)
3997 {
3998 TCGv EA;
3999 TCGv t0;
4000 if (unlikely(!ctx->fpu_enabled)) {
4001 gen_exception(ctx, POWERPC_EXCP_FPU);
4002 return;
4003 }
4004 gen_set_access_type(ctx, ACCESS_FLOAT);
4005 EA = tcg_temp_new();
4006 t0 = tcg_temp_new();
4007 gen_addr_reg_index(ctx, EA);
4008 gen_qemu_ld32s(ctx, t0, EA);
4009 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
4010 tcg_temp_free(EA);
4011 tcg_temp_free(t0);
4012 }
4013
4014 /* lfiwzx */
4015 static void gen_lfiwzx(DisasContext *ctx)
4016 {
4017 TCGv EA;
4018 if (unlikely(!ctx->fpu_enabled)) {
4019 gen_exception(ctx, POWERPC_EXCP_FPU);
4020 return;
4021 }
4022 gen_set_access_type(ctx, ACCESS_FLOAT);
4023 EA = tcg_temp_new();
4024 gen_addr_reg_index(ctx, EA);
4025 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
4026 tcg_temp_free(EA);
4027 }
4028 /*** Floating-point store ***/
4029 #define GEN_STF(name, stop, opc, type) \
4030 static void glue(gen_, name)(DisasContext *ctx) \
4031 { \
4032 TCGv EA; \
4033 if (unlikely(!ctx->fpu_enabled)) { \
4034 gen_exception(ctx, POWERPC_EXCP_FPU); \
4035 return; \
4036 } \
4037 gen_set_access_type(ctx, ACCESS_FLOAT); \
4038 EA = tcg_temp_new(); \
4039 gen_addr_imm_index(ctx, EA, 0); \
4040 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
4041 tcg_temp_free(EA); \
4042 }
4043
4044 #define GEN_STUF(name, stop, opc, type) \
4045 static void glue(gen_, name##u)(DisasContext *ctx) \
4046 { \
4047 TCGv EA; \
4048 if (unlikely(!ctx->fpu_enabled)) { \
4049 gen_exception(ctx, POWERPC_EXCP_FPU); \
4050 return; \
4051 } \
4052 if (unlikely(rA(ctx->opcode) == 0)) { \
4053 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
4054 return; \
4055 } \
4056 gen_set_access_type(ctx, ACCESS_FLOAT); \
4057 EA = tcg_temp_new(); \
4058 gen_addr_imm_index(ctx, EA, 0); \
4059 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
4060 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
4061 tcg_temp_free(EA); \
4062 }
4063
4064 #define GEN_STUXF(name, stop, opc, type) \
4065 static void glue(gen_, name##ux)(DisasContext *ctx) \
4066 { \
4067 TCGv EA; \
4068 if (unlikely(!ctx->fpu_enabled)) { \
4069 gen_exception(ctx, POWERPC_EXCP_FPU); \
4070 return; \
4071 } \
4072 if (unlikely(rA(ctx->opcode) == 0)) { \
4073 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
4074 return; \
4075 } \
4076 gen_set_access_type(ctx, ACCESS_FLOAT); \
4077 EA = tcg_temp_new(); \
4078 gen_addr_reg_index(ctx, EA); \
4079 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
4080 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
4081 tcg_temp_free(EA); \
4082 }
4083
4084 #define GEN_STXF(name, stop, opc2, opc3, type) \
4085 static void glue(gen_, name##x)(DisasContext *ctx) \
4086 { \
4087 TCGv EA; \
4088 if (unlikely(!ctx->fpu_enabled)) { \
4089 gen_exception(ctx, POWERPC_EXCP_FPU); \
4090 return; \
4091 } \
4092 gen_set_access_type(ctx, ACCESS_FLOAT); \
4093 EA = tcg_temp_new(); \
4094 gen_addr_reg_index(ctx, EA); \
4095 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
4096 tcg_temp_free(EA); \
4097 }
4098
4099 #define GEN_STFS(name, stop, op, type) \
4100 GEN_STF(name, stop, op | 0x20, type); \
4101 GEN_STUF(name, stop, op | 0x21, type); \
4102 GEN_STUXF(name, stop, op | 0x01, type); \
4103 GEN_STXF(name, stop, 0x17, op | 0x00, type)
4104
4105 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
4106 {
4107 TCGv_i32 t0 = tcg_temp_new_i32();
4108 TCGv t1 = tcg_temp_new();
4109 gen_helper_float64_to_float32(t0, cpu_env, arg1);
4110 tcg_gen_extu_i32_tl(t1, t0);
4111 tcg_temp_free_i32(t0);
4112 gen_qemu_st32(ctx, t1, arg2);
4113 tcg_temp_free(t1);
4114 }
4115
4116 /* stfd stfdu stfdux stfdx */
4117 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
4118 /* stfs stfsu stfsux stfsx */
4119 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
4120
4121 /* stfdp */
4122 static void gen_stfdp(DisasContext *ctx)
4123 {
4124 TCGv EA;
4125 if (unlikely(!ctx->fpu_enabled)) {
4126 gen_exception(ctx, POWERPC_EXCP_FPU);
4127 return;
4128 }
4129 gen_set_access_type(ctx, ACCESS_FLOAT);
4130 EA = tcg_temp_new();
4131 gen_addr_imm_index(ctx, EA, 0);
4132 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
4133 64-bit byteswap already. */
4134 if (unlikely(ctx->le_mode)) {
4135 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
4136 tcg_gen_addi_tl(EA, EA, 8);
4137 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
4138 } else {
4139 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
4140 tcg_gen_addi_tl(EA, EA, 8);
4141 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
4142 }
4143 tcg_temp_free(EA);
4144 }
4145
4146 /* stfdpx */
4147 static void gen_stfdpx(DisasContext *ctx)
4148 {
4149 TCGv EA;
4150 if (unlikely(!ctx->fpu_enabled)) {
4151 gen_exception(ctx, POWERPC_EXCP_FPU);
4152 return;
4153 }
4154 gen_set_access_type(ctx, ACCESS_FLOAT);
4155 EA = tcg_temp_new();
4156 gen_addr_reg_index(ctx, EA);
4157 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
4158 64-bit byteswap already. */
4159 if (unlikely(ctx->le_mode)) {
4160 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
4161 tcg_gen_addi_tl(EA, EA, 8);
4162 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
4163 } else {
4164 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
4165 tcg_gen_addi_tl(EA, EA, 8);
4166 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
4167 }
4168 tcg_temp_free(EA);
4169 }
4170
4171 /* Optional: */
4172 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
4173 {
4174 TCGv t0 = tcg_temp_new();
4175 tcg_gen_trunc_i64_tl(t0, arg1),
4176 gen_qemu_st32(ctx, t0, arg2);
4177 tcg_temp_free(t0);
4178 }
4179 /* stfiwx */
4180 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
4181
4182 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
4183 {
4184 #if defined(TARGET_PPC64)
4185 if (ctx->has_cfar)
4186 tcg_gen_movi_tl(cpu_cfar, nip);
4187 #endif
4188 }
4189
4190 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
4191 {
4192 if (unlikely(ctx->singlestep_enabled)) {
4193 return false;
4194 }
4195
4196 #ifndef CONFIG_USER_ONLY
4197 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
4198 #else
4199 return true;
4200 #endif
4201 }
4202
4203 /*** Branch ***/
4204 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
4205 {
4206 if (NARROW_MODE(ctx)) {
4207 dest = (uint32_t) dest;
4208 }
4209 if (use_goto_tb(ctx, dest)) {
4210 tcg_gen_goto_tb(n);
4211 tcg_gen_movi_tl(cpu_nip, dest & ~3);
4212 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
4213 } else {
4214 tcg_gen_movi_tl(cpu_nip, dest & ~3);
4215 if (unlikely(ctx->singlestep_enabled)) {
4216 if ((ctx->singlestep_enabled &
4217 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
4218 (ctx->exception == POWERPC_EXCP_BRANCH ||
4219 ctx->exception == POWERPC_EXCP_TRACE)) {
4220 target_ulong tmp = ctx->nip;
4221 ctx->nip = dest;
4222 gen_exception(ctx, POWERPC_EXCP_TRACE);
4223 ctx->nip = tmp;
4224 }
4225 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
4226 gen_debug_exception(ctx);
4227 }
4228 }
4229 tcg_gen_exit_tb(0);
4230 }
4231 }
4232
4233 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
4234 {
4235 if (NARROW_MODE(ctx)) {
4236 nip = (uint32_t)nip;
4237 }
4238 tcg_gen_movi_tl(cpu_lr, nip);
4239 }
4240
4241 /* b ba bl bla */
4242 static void gen_b(DisasContext *ctx)
4243 {
4244 target_ulong li, target;
4245
4246 ctx->exception = POWERPC_EXCP_BRANCH;
4247 /* sign extend LI */
4248 li = LI(ctx->opcode);
4249 li = (li ^ 0x02000000) - 0x02000000;
4250 if (likely(AA(ctx->opcode) == 0)) {
4251 target = ctx->nip + li - 4;
4252 } else {
4253 target = li;
4254 }
4255 if (LK(ctx->opcode)) {
4256 gen_setlr(ctx, ctx->nip);
4257 }
4258 gen_update_cfar(ctx, ctx->nip);
4259 gen_goto_tb(ctx, 0, target);
4260 }
4261
4262 #define BCOND_IM 0
4263 #define BCOND_LR 1
4264 #define BCOND_CTR 2
4265 #define BCOND_TAR 3
4266
4267 static inline void gen_bcond(DisasContext *ctx, int type)
4268 {
4269 uint32_t bo = BO(ctx->opcode);
4270 TCGLabel *l1;
4271 TCGv target;
4272
4273 ctx->exception = POWERPC_EXCP_BRANCH;
4274 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
4275 target = tcg_temp_local_new();
4276 if (type == BCOND_CTR)
4277 tcg_gen_mov_tl(target, cpu_ctr);
4278 else if (type == BCOND_TAR)
4279 gen_load_spr(target, SPR_TAR);
4280 else
4281 tcg_gen_mov_tl(target, cpu_lr);
4282 } else {
4283 TCGV_UNUSED(target);
4284 }
4285 if (LK(ctx->opcode))
4286 gen_setlr(ctx, ctx->nip);
4287 l1 = gen_new_label();
4288 if ((bo & 0x4) == 0) {
4289 /* Decrement and test CTR */
4290 TCGv temp = tcg_temp_new();
4291 if (unlikely(type == BCOND_CTR)) {
4292 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4293 return;
4294 }
4295 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
4296 if (NARROW_MODE(ctx)) {
4297 tcg_gen_ext32u_tl(temp, cpu_ctr);
4298 } else {
4299 tcg_gen_mov_tl(temp, cpu_ctr);
4300 }
4301 if (bo & 0x2) {
4302 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
4303 } else {
4304 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
4305 }
4306 tcg_temp_free(temp);
4307 }
4308 if ((bo & 0x10) == 0) {
4309 /* Test CR */
4310 uint32_t bi = BI(ctx->opcode);
4311 uint32_t mask = 0x08 >> (bi & 0x03);
4312 TCGv_i32 temp = tcg_temp_new_i32();
4313
4314 if (bo & 0x8) {
4315 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4316 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
4317 } else {
4318 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4319 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
4320 }
4321 tcg_temp_free_i32(temp);
4322 }
4323 gen_update_cfar(ctx, ctx->nip);
4324 if (type == BCOND_IM) {
4325 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
4326 if (likely(AA(ctx->opcode) == 0)) {
4327 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
4328 } else {
4329 gen_goto_tb(ctx, 0, li);
4330 }
4331 gen_set_label(l1);
4332 gen_goto_tb(ctx, 1, ctx->nip);
4333 } else {
4334 if (NARROW_MODE(ctx)) {
4335 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
4336 } else {
4337 tcg_gen_andi_tl(cpu_nip, target, ~3);
4338 }
4339 tcg_gen_exit_tb(0);
4340 gen_set_label(l1);
4341 gen_update_nip(ctx, ctx->nip);
4342 tcg_gen_exit_tb(0);
4343 }
4344 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
4345 tcg_temp_free(target);
4346 }
4347 }
4348
4349 static void gen_bc(DisasContext *ctx)
4350 {
4351 gen_bcond(ctx, BCOND_IM);
4352 }
4353
4354 static void gen_bcctr(DisasContext *ctx)
4355 {
4356 gen_bcond(ctx, BCOND_CTR);
4357 }
4358
4359 static void gen_bclr(DisasContext *ctx)
4360 {
4361 gen_bcond(ctx, BCOND_LR);
4362 }
4363
4364 static void gen_bctar(DisasContext *ctx)
4365 {
4366 gen_bcond(ctx, BCOND_TAR);
4367 }
4368
4369 /*** Condition register logical ***/
4370 #define GEN_CRLOGIC(name, tcg_op, opc) \
4371 static void glue(gen_, name)(DisasContext *ctx) \
4372 { \
4373 uint8_t bitmask; \
4374 int sh; \
4375 TCGv_i32 t0, t1; \
4376 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
4377 t0 = tcg_temp_new_i32(); \
4378 if (sh > 0) \
4379 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
4380 else if (sh < 0) \
4381 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
4382 else \
4383 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
4384 t1 = tcg_temp_new_i32(); \
4385 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4386 if (sh > 0) \
4387 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4388 else if (sh < 0) \
4389 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4390 else \
4391 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4392 tcg_op(t0, t0, t1); \
4393 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4394 tcg_gen_andi_i32(t0, t0, bitmask); \
4395 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4396 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4397 tcg_temp_free_i32(t0); \
4398 tcg_temp_free_i32(t1); \
4399 }
4400
4401 /* crand */
4402 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4403 /* crandc */
4404 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4405 /* creqv */
4406 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4407 /* crnand */
4408 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4409 /* crnor */
4410 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
4411 /* cror */
4412 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
4413 /* crorc */
4414 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
4415 /* crxor */
4416 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
4417
4418 /* mcrf */
4419 static void gen_mcrf(DisasContext *ctx)
4420 {
4421 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4422 }
4423
4424 /*** System linkage ***/
4425
4426 /* rfi (supervisor only) */
4427 static void gen_rfi(DisasContext *ctx)
4428 {
4429 #if defined(CONFIG_USER_ONLY)
4430 GEN_PRIV;
4431 #else
4432 /* FIXME: This instruction doesn't exist anymore on 64-bit server
4433 * processors compliant with arch 2.x, we should remove it there,
4434 * but we need to fix OpenBIOS not to use it on 970 first
4435 */
4436 /* Restore CPU state */
4437 CHK_SV;
4438 gen_update_cfar(ctx, ctx->nip);
4439 gen_helper_rfi(cpu_env);
4440 gen_sync_exception(ctx);
4441 #endif
4442 }
4443
4444 #if defined(TARGET_PPC64)
4445 static void gen_rfid(DisasContext *ctx)
4446 {
4447 #if defined(CONFIG_USER_ONLY)
4448 GEN_PRIV;
4449 #else
4450 /* Restore CPU state */
4451 CHK_SV;
4452 gen_update_cfar(ctx, ctx->nip);
4453 gen_helper_rfid(cpu_env);
4454 gen_sync_exception(ctx);
4455 #endif
4456 }
4457
4458 static void gen_hrfid(DisasContext *ctx)
4459 {
4460 #if defined(CONFIG_USER_ONLY)
4461 GEN_PRIV;
4462 #else
4463 /* Restore CPU state */
4464 CHK_HV;
4465 gen_helper_hrfid(cpu_env);
4466 gen_sync_exception(ctx);
4467 #endif
4468 }
4469 #endif
4470
4471 /* sc */
4472 #if defined(CONFIG_USER_ONLY)
4473 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4474 #else
4475 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4476 #endif
4477 static void gen_sc(DisasContext *ctx)
4478 {
4479 uint32_t lev;
4480
4481 lev = (ctx->opcode >> 5) & 0x7F;
4482 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4483 }
4484
4485 /*** Trap ***/
4486
4487 /* tw */
4488 static void gen_tw(DisasContext *ctx)
4489 {
4490 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4491 /* Update the nip since this might generate a trap exception */
4492 gen_update_nip(ctx, ctx->nip);
4493 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4494 t0);
4495 tcg_temp_free_i32(t0);
4496 }
4497
4498 /* twi */
4499 static void gen_twi(DisasContext *ctx)
4500 {
4501 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4502 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4503 /* Update the nip since this might generate a trap exception */
4504 gen_update_nip(ctx, ctx->nip);
4505 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4506 tcg_temp_free(t0);
4507 tcg_temp_free_i32(t1);
4508 }
4509
4510 #if defined(TARGET_PPC64)
4511 /* td */
4512 static void gen_td(DisasContext *ctx)
4513 {
4514 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4515 /* Update the nip since this might generate a trap exception */
4516 gen_update_nip(ctx, ctx->nip);
4517 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4518 t0);
4519 tcg_temp_free_i32(t0);
4520 }
4521
4522 /* tdi */
4523 static void gen_tdi(DisasContext *ctx)
4524 {
4525 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4526 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4527 /* Update the nip since this might generate a trap exception */
4528 gen_update_nip(ctx, ctx->nip);
4529 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4530 tcg_temp_free(t0);
4531 tcg_temp_free_i32(t1);
4532 }
4533 #endif
4534
4535 /*** Processor control ***/
4536
4537 static void gen_read_xer(TCGv dst)
4538 {
4539 TCGv t0 = tcg_temp_new();
4540 TCGv t1 = tcg_temp_new();
4541 TCGv t2 = tcg_temp_new();
4542 tcg_gen_mov_tl(dst, cpu_xer);
4543 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4544 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4545 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4546 tcg_gen_or_tl(t0, t0, t1);
4547 tcg_gen_or_tl(dst, dst, t2);
4548 tcg_gen_or_tl(dst, dst, t0);
4549 tcg_temp_free(t0);
4550 tcg_temp_free(t1);
4551 tcg_temp_free(t2);
4552 }
4553
4554 static void gen_write_xer(TCGv src)
4555 {
4556 tcg_gen_andi_tl(cpu_xer, src,
4557 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4558 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4559 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4560 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4561 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4562 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4563 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4564 }
4565
4566 /* mcrxr */
4567 static void gen_mcrxr(DisasContext *ctx)
4568 {
4569 TCGv_i32 t0 = tcg_temp_new_i32();
4570 TCGv_i32 t1 = tcg_temp_new_i32();
4571 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4572
4573 tcg_gen_trunc_tl_i32(t0, cpu_so);
4574 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4575 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4576 tcg_gen_shli_i32(t0, t0, 3);
4577 tcg_gen_shli_i32(t1, t1, 2);
4578 tcg_gen_shli_i32(dst, dst, 1);
4579 tcg_gen_or_i32(dst, dst, t0);
4580 tcg_gen_or_i32(dst, dst, t1);
4581 tcg_temp_free_i32(t0);
4582 tcg_temp_free_i32(t1);
4583
4584 tcg_gen_movi_tl(cpu_so, 0);
4585 tcg_gen_movi_tl(cpu_ov, 0);
4586 tcg_gen_movi_tl(cpu_ca, 0);
4587 }
4588
4589 /* mfcr mfocrf */
4590 static void gen_mfcr(DisasContext *ctx)
4591 {
4592 uint32_t crm, crn;
4593
4594 if (likely(ctx->opcode & 0x00100000)) {
4595 crm = CRM(ctx->opcode);
4596 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4597 crn = ctz32 (crm);
4598 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4599 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4600 cpu_gpr[rD(ctx->opcode)], crn * 4);
4601 }
4602 } else {
4603 TCGv_i32 t0 = tcg_temp_new_i32();
4604 tcg_gen_mov_i32(t0, cpu_crf[0]);
4605 tcg_gen_shli_i32(t0, t0, 4);
4606 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4607 tcg_gen_shli_i32(t0, t0, 4);
4608 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4609 tcg_gen_shli_i32(t0, t0, 4);
4610 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4611 tcg_gen_shli_i32(t0, t0, 4);
4612 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4613 tcg_gen_shli_i32(t0, t0, 4);
4614 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4615 tcg_gen_shli_i32(t0, t0, 4);
4616 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4617 tcg_gen_shli_i32(t0, t0, 4);
4618 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4619 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4620 tcg_temp_free_i32(t0);
4621 }
4622 }
4623
4624 /* mfmsr */
4625 static void gen_mfmsr(DisasContext *ctx)
4626 {
4627 CHK_SV;
4628 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4629 }
4630
4631 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
4632 {
4633 #if 0
4634 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4635 printf("ERROR: try to access SPR %d !\n", sprn);
4636 #endif
4637 }
4638 #define SPR_NOACCESS (&spr_noaccess)
4639
4640 /* mfspr */
4641 static inline void gen_op_mfspr(DisasContext *ctx)
4642 {
4643 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4644 uint32_t sprn = SPR(ctx->opcode);
4645
4646 #if defined(CONFIG_USER_ONLY)
4647 read_cb = ctx->spr_cb[sprn].uea_read;
4648 #else
4649 if (ctx->pr) {
4650 read_cb = ctx->spr_cb[sprn].uea_read;
4651 } else if (ctx->hv) {
4652 read_cb = ctx->spr_cb[sprn].hea_read;
4653 } else {
4654 read_cb = ctx->spr_cb[sprn].oea_read;
4655 }
4656 #endif
4657 if (likely(read_cb != NULL)) {
4658 if (likely(read_cb != SPR_NOACCESS)) {
4659 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4660 } else {
4661 /* Privilege exception */
4662 /* This is a hack to avoid warnings when running Linux:
4663 * this OS breaks the PowerPC virtualisation model,
4664 * allowing userland application to read the PVR
4665 */
4666 if (sprn != SPR_PVR) {
4667 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
4668 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4669 if (qemu_log_separate()) {
4670 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4671 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4672 }
4673 }
4674 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4675 }
4676 } else {
4677 /* ISA 2.07 defines these as no-ops */
4678 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4679 (sprn >= 808 && sprn <= 811)) {
4680 /* This is a nop */
4681 return;
4682 }
4683 /* Not defined */
4684 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
4685 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4686 if (qemu_log_separate()) {
4687 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4688 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4689 }
4690
4691 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4692 * it can generate a priv, a hv emu or a no-op
4693 */
4694 if (sprn & 0x10) {
4695 if (ctx->pr) {
4696 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4697 }
4698 } else {
4699 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
4700 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4701 }
4702 }
4703 }
4704 }
4705
4706 static void gen_mfspr(DisasContext *ctx)
4707 {
4708 gen_op_mfspr(ctx);
4709 }
4710
4711 /* mftb */
4712 static void gen_mftb(DisasContext *ctx)
4713 {
4714 gen_op_mfspr(ctx);
4715 }
4716
4717 /* mtcrf mtocrf*/
4718 static void gen_mtcrf(DisasContext *ctx)
4719 {
4720 uint32_t crm, crn;
4721
4722 crm = CRM(ctx->opcode);
4723 if (likely((ctx->opcode & 0x00100000))) {
4724 if (crm && ((crm & (crm - 1)) == 0)) {
4725 TCGv_i32 temp = tcg_temp_new_i32();
4726 crn = ctz32 (crm);
4727 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4728 tcg_gen_shri_i32(temp, temp, crn * 4);
4729 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4730 tcg_temp_free_i32(temp);
4731 }
4732 } else {
4733 TCGv_i32 temp = tcg_temp_new_i32();
4734 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4735 for (crn = 0 ; crn < 8 ; crn++) {
4736 if (crm & (1 << crn)) {
4737 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4738 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4739 }
4740 }
4741 tcg_temp_free_i32(temp);
4742 }
4743 }
4744
4745 /* mtmsr */
4746 #if defined(TARGET_PPC64)
4747 static void gen_mtmsrd(DisasContext *ctx)
4748 {
4749 CHK_SV;
4750
4751 #if !defined(CONFIG_USER_ONLY)
4752 if (ctx->opcode & 0x00010000) {
4753 /* Special form that does not need any synchronisation */
4754 TCGv t0 = tcg_temp_new();
4755 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4756 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4757 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4758 tcg_temp_free(t0);
4759 } else {
4760 /* XXX: we need to update nip before the store
4761 * if we enter power saving mode, we will exit the loop
4762 * directly from ppc_store_msr
4763 */
4764 gen_update_nip(ctx, ctx->nip);
4765 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4766 /* Must stop the translation as machine state (may have) changed */
4767 /* Note that mtmsr is not always defined as context-synchronizing */
4768 gen_stop_exception(ctx);
4769 }
4770 #endif /* !defined(CONFIG_USER_ONLY) */
4771 }
4772 #endif /* defined(TARGET_PPC64) */
4773
4774 static void gen_mtmsr(DisasContext *ctx)
4775 {
4776 CHK_SV;
4777
4778 #if !defined(CONFIG_USER_ONLY)
4779 if (ctx->opcode & 0x00010000) {
4780 /* Special form that does not need any synchronisation */
4781 TCGv t0 = tcg_temp_new();
4782 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4783 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4784 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4785 tcg_temp_free(t0);
4786 } else {
4787 TCGv msr = tcg_temp_new();
4788
4789 /* XXX: we need to update nip before the store
4790 * if we enter power saving mode, we will exit the loop
4791 * directly from ppc_store_msr
4792 */
4793 gen_update_nip(ctx, ctx->nip);
4794 #if defined(TARGET_PPC64)
4795 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4796 #else
4797 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4798 #endif
4799 gen_helper_store_msr(cpu_env, msr);
4800 tcg_temp_free(msr);
4801 /* Must stop the translation as machine state (may have) changed */
4802 /* Note that mtmsr is not always defined as context-synchronizing */
4803 gen_stop_exception(ctx);
4804 }
4805 #endif
4806 }
4807
4808 /* mtspr */
4809 static void gen_mtspr(DisasContext *ctx)
4810 {
4811 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4812 uint32_t sprn = SPR(ctx->opcode);
4813
4814 #if defined(CONFIG_USER_ONLY)
4815 write_cb = ctx->spr_cb[sprn].uea_write;
4816 #else
4817 if (ctx->pr) {
4818 write_cb = ctx->spr_cb[sprn].uea_write;
4819 } else if (ctx->hv) {
4820 write_cb = ctx->spr_cb[sprn].hea_write;
4821 } else {
4822 write_cb = ctx->spr_cb[sprn].oea_write;
4823 }
4824 #endif
4825 if (likely(write_cb != NULL)) {
4826 if (likely(write_cb != SPR_NOACCESS)) {
4827 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4828 } else {
4829 /* Privilege exception */
4830 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4831 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4832 if (qemu_log_separate()) {
4833 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4834 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4835 }
4836 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4837 }
4838 } else {
4839 /* ISA 2.07 defines these as no-ops */
4840 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4841 (sprn >= 808 && sprn <= 811)) {
4842 /* This is a nop */
4843 return;
4844 }
4845
4846 /* Not defined */
4847 if (qemu_log_separate()) {
4848 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4849 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4850 }
4851 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4852 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4853
4854
4855 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4856 * it can generate a priv, a hv emu or a no-op
4857 */
4858 if (sprn & 0x10) {
4859 if (ctx->pr) {
4860 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4861 }
4862 } else {
4863 if (ctx->pr || sprn == 0) {
4864 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4865 }
4866 }
4867 }
4868 }
4869
4870 #if defined(TARGET_PPC64)
4871 /* setb */
4872 static void gen_setb(DisasContext *ctx)
4873 {
4874 TCGv_i32 t0 = tcg_temp_new_i32();
4875 TCGv_i32 t8 = tcg_temp_new_i32();
4876 TCGv_i32 tm1 = tcg_temp_new_i32();
4877 int crf = crfS(ctx->opcode);
4878
4879 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4880 tcg_gen_movi_i32(t8, 8);
4881 tcg_gen_movi_i32(tm1, -1);
4882 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4883 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4884
4885 tcg_temp_free_i32(t0);
4886 tcg_temp_free_i32(t8);
4887 tcg_temp_free_i32(tm1);
4888 }
4889 #endif
4890
4891 /*** Cache management ***/
4892
4893 /* dcbf */
4894 static void gen_dcbf(DisasContext *ctx)
4895 {
4896 /* XXX: specification says this is treated as a load by the MMU */
4897 TCGv t0;
4898 gen_set_access_type(ctx, ACCESS_CACHE);
4899 t0 = tcg_temp_new();
4900 gen_addr_reg_index(ctx, t0);
4901 gen_qemu_ld8u(ctx, t0, t0);
4902 tcg_temp_free(t0);
4903 }
4904
4905 /* dcbi (Supervisor only) */
4906 static void gen_dcbi(DisasContext *ctx)
4907 {
4908 #if defined(CONFIG_USER_ONLY)
4909 GEN_PRIV;
4910 #else
4911 TCGv EA, val;
4912
4913 CHK_SV;
4914 EA = tcg_temp_new();
4915 gen_set_access_type(ctx, ACCESS_CACHE);
4916 gen_addr_reg_index(ctx, EA);
4917 val = tcg_temp_new();
4918 /* XXX: specification says this should be treated as a store by the MMU */
4919 gen_qemu_ld8u(ctx, val, EA);
4920 gen_qemu_st8(ctx, val, EA);
4921 tcg_temp_free(val);
4922 tcg_temp_free(EA);
4923 #endif /* defined(CONFIG_USER_ONLY) */
4924 }
4925
4926 /* dcdst */
4927 static void gen_dcbst(DisasContext *ctx)
4928 {
4929 /* XXX: specification say this is treated as a load by the MMU */
4930 TCGv t0;
4931 gen_set_access_type(ctx, ACCESS_CACHE);
4932 t0 = tcg_temp_new();
4933 gen_addr_reg_index(ctx, t0);
4934 gen_qemu_ld8u(ctx, t0, t0);
4935 tcg_temp_free(t0);
4936 }
4937
4938 /* dcbt */
4939 static void gen_dcbt(DisasContext *ctx)
4940 {
4941 /* interpreted as no-op */
4942 /* XXX: specification say this is treated as a load by the MMU
4943 * but does not generate any exception
4944 */
4945 }
4946
4947 /* dcbtst */
4948 static void gen_dcbtst(DisasContext *ctx)
4949 {
4950 /* interpreted as no-op */
4951 /* XXX: specification say this is treated as a load by the MMU
4952 * but does not generate any exception
4953 */
4954 }
4955
4956 /* dcbtls */
4957 static void gen_dcbtls(DisasContext *ctx)
4958 {
4959 /* Always fails locking the cache */
4960 TCGv t0 = tcg_temp_new();
4961 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4962 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4963 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4964 tcg_temp_free(t0);
4965 }
4966
4967 /* dcbz */
4968 static void gen_dcbz(DisasContext *ctx)
4969 {
4970 TCGv tcgv_addr;
4971 TCGv_i32 tcgv_is_dcbzl;
4972 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4973
4974 gen_set_access_type(ctx, ACCESS_CACHE);
4975 /* NIP cannot be restored if the memory exception comes from an helper */
4976 gen_update_nip(ctx, ctx->nip - 4);
4977 tcgv_addr = tcg_temp_new();
4978 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4979
4980 gen_addr_reg_index(ctx, tcgv_addr);
4981 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4982
4983 tcg_temp_free(tcgv_addr);
4984 tcg_temp_free_i32(tcgv_is_dcbzl);
4985 }
4986
4987 /* dst / dstt */
4988 static void gen_dst(DisasContext *ctx)
4989 {
4990 if (rA(ctx->opcode) == 0) {
4991 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4992 } else {
4993 /* interpreted as no-op */
4994 }
4995 }
4996
4997 /* dstst /dststt */
4998 static void gen_dstst(DisasContext *ctx)
4999 {
5000 if (rA(ctx->opcode) == 0) {
5001 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
5002 } else {
5003 /* interpreted as no-op */
5004 }
5005
5006 }
5007
5008 /* dss / dssall */
5009 static void gen_dss(DisasContext *ctx)
5010 {
5011 /* interpreted as no-op */
5012 }
5013
5014 /* icbi */
5015 static void gen_icbi(DisasContext *ctx)
5016 {
5017 TCGv t0;
5018 gen_set_access_type(ctx, ACCESS_CACHE);
5019 /* NIP cannot be restored if the memory exception comes from an helper */
5020 gen_update_nip(ctx, ctx->nip - 4);
5021 t0 = tcg_temp_new();
5022 gen_addr_reg_index(ctx, t0);
5023 gen_helper_icbi(cpu_env, t0);
5024 tcg_temp_free(t0);
5025 }
5026
5027 /* Optional: */
5028 /* dcba */
5029 static void gen_dcba(DisasContext *ctx)
5030 {
5031 /* interpreted as no-op */
5032 /* XXX: specification say this is treated as a store by the MMU
5033 * but does not generate any exception
5034 */
5035 }
5036
5037 /*** Segment register manipulation ***/
5038 /* Supervisor only: */
5039
5040 /* mfsr */
5041 static void gen_mfsr(DisasContext *ctx)
5042 {
5043 #if defined(CONFIG_USER_ONLY)
5044 GEN_PRIV;
5045 #else
5046 TCGv t0;
5047
5048 CHK_SV;
5049 t0 = tcg_const_tl(SR(ctx->opcode));
5050 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5051 tcg_temp_free(t0);
5052 #endif /* defined(CONFIG_USER_ONLY) */
5053 }
5054
5055 /* mfsrin */
5056 static void gen_mfsrin(DisasContext *ctx)
5057 {
5058 #if defined(CONFIG_USER_ONLY)
5059 GEN_PRIV;
5060 #else
5061 TCGv t0;
5062
5063 CHK_SV;
5064 t0 = tcg_temp_new();
5065 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
5066 tcg_gen_andi_tl(t0, t0, 0xF);
5067 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5068 tcg_temp_free(t0);
5069 #endif /* defined(CONFIG_USER_ONLY) */
5070 }
5071
5072 /* mtsr */
5073 static void gen_mtsr(DisasContext *ctx)
5074 {
5075 #if defined(CONFIG_USER_ONLY)
5076 GEN_PRIV;
5077 #else
5078 TCGv t0;
5079
5080 CHK_SV;
5081 t0 = tcg_const_tl(SR(ctx->opcode));
5082 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5083 tcg_temp_free(t0);
5084 #endif /* defined(CONFIG_USER_ONLY) */
5085 }
5086
5087 /* mtsrin */
5088 static void gen_mtsrin(DisasContext *ctx)
5089 {
5090 #if defined(CONFIG_USER_ONLY)
5091 GEN_PRIV;
5092 #else
5093 TCGv t0;
5094 CHK_SV;
5095
5096 t0 = tcg_temp_new();
5097 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
5098 tcg_gen_andi_tl(t0, t0, 0xF);
5099 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
5100 tcg_temp_free(t0);
5101 #endif /* defined(CONFIG_USER_ONLY) */
5102 }
5103
5104 #if defined(TARGET_PPC64)
5105 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
5106
5107 /* mfsr */
5108 static void gen_mfsr_64b(DisasContext *ctx)
5109 {
5110 #if defined(CONFIG_USER_ONLY)
5111 GEN_PRIV;
5112 #else
5113 TCGv t0;
5114
5115 CHK_SV;
5116 t0 = tcg_const_tl(SR(ctx->opcode));
5117 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5118 tcg_temp_free(t0);
5119 #endif /* defined(CONFIG_USER_ONLY) */
5120 }
5121
5122 /* mfsrin */
5123 static void gen_mfsrin_64b(DisasContext *ctx)
5124 {
5125 #if defined(CONFIG_USER_ONLY)
5126 GEN_PRIV;
5127 #else
5128 TCGv t0;
5129
5130 CHK_SV;
5131 t0 = tcg_temp_new();
5132 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
5133 tcg_gen_andi_tl(t0, t0, 0xF);
5134 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5135 tcg_temp_free(t0);
5136 #endif /* defined(CONFIG_USER_ONLY) */
5137 }
5138
5139 /* mtsr */
5140 static void gen_mtsr_64b(DisasContext *ctx)
5141 {
5142 #if defined(CONFIG_USER_ONLY)
5143 GEN_PRIV;
5144 #else
5145 TCGv t0;
5146
5147 CHK_SV;
5148 t0 = tcg_const_tl(SR(ctx->opcode));
5149 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5150 tcg_temp_free(t0);
5151 #endif /* defined(CONFIG_USER_ONLY) */
5152 }
5153
5154 /* mtsrin */
5155 static void gen_mtsrin_64b(DisasContext *ctx)
5156 {
5157 #if defined(CONFIG_USER_ONLY)
5158 GEN_PRIV;
5159 #else
5160 TCGv t0;
5161
5162 CHK_SV;
5163 t0 = tcg_temp_new();
5164 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
5165 tcg_gen_andi_tl(t0, t0, 0xF);
5166 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5167 tcg_temp_free(t0);
5168 #endif /* defined(CONFIG_USER_ONLY) */
5169 }
5170
5171 /* slbmte */
5172 static void gen_slbmte(DisasContext *ctx)
5173 {
5174 #if defined(CONFIG_USER_ONLY)
5175 GEN_PRIV;
5176 #else
5177 CHK_SV;
5178
5179 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
5180 cpu_gpr[rS(ctx->opcode)]);
5181 #endif /* defined(CONFIG_USER_ONLY) */
5182 }
5183
5184 static void gen_slbmfee(DisasContext *ctx)
5185 {
5186 #if defined(CONFIG_USER_ONLY)
5187 GEN_PRIV;
5188 #else
5189 CHK_SV;
5190
5191 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
5192 cpu_gpr[rB(ctx->opcode)]);
5193 #endif /* defined(CONFIG_USER_ONLY) */
5194 }
5195
5196 static void gen_slbmfev(DisasContext *ctx)
5197 {
5198 #if defined(CONFIG_USER_ONLY)
5199 GEN_PRIV;
5200 #else
5201 CHK_SV;
5202
5203 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
5204 cpu_gpr[rB(ctx->opcode)]);
5205 #endif /* defined(CONFIG_USER_ONLY) */
5206 }
5207
5208 static void gen_slbfee_(DisasContext *ctx)
5209 {
5210 #if defined(CONFIG_USER_ONLY)
5211 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5212 #else
5213 TCGLabel *l1, *l2;
5214
5215 if (unlikely(ctx->pr)) {
5216 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5217 return;
5218 }
5219 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
5220 cpu_gpr[rB(ctx->opcode)]);
5221 l1 = gen_new_label();
5222 l2 = gen_new_label();
5223 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5224 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
5225 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
5226 tcg_gen_br(l2);
5227 gen_set_label(l1);
5228 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
5229 gen_set_label(l2);
5230 #endif
5231 }
5232 #endif /* defined(TARGET_PPC64) */
5233
5234 /*** Lookaside buffer management ***/
5235 /* Optional & supervisor only: */
5236
5237 /* tlbia */
5238 static void gen_tlbia(DisasContext *ctx)
5239 {
5240 #if defined(CONFIG_USER_ONLY)
5241 GEN_PRIV;
5242 #else
5243 CHK_HV;
5244
5245 gen_helper_tlbia(cpu_env);
5246 #endif /* defined(CONFIG_USER_ONLY) */
5247 }
5248
5249 /* tlbiel */
5250 static void gen_tlbiel(DisasContext *ctx)
5251 {
5252 #if defined(CONFIG_USER_ONLY)
5253 GEN_PRIV;
5254 #else
5255 CHK_SV;
5256
5257 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5258 #endif /* defined(CONFIG_USER_ONLY) */
5259 }
5260
5261 /* tlbie */
5262 static void gen_tlbie(DisasContext *ctx)
5263 {
5264 #if defined(CONFIG_USER_ONLY)
5265 GEN_PRIV;
5266 #else
5267 CHK_HV;
5268
5269 if (NARROW_MODE(ctx)) {
5270 TCGv t0 = tcg_temp_new();
5271 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
5272 gen_helper_tlbie(cpu_env, t0);
5273 tcg_temp_free(t0);
5274 } else {
5275 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5276 }
5277 #endif /* defined(CONFIG_USER_ONLY) */
5278 }
5279
5280 /* tlbsync */
5281 static void gen_tlbsync(DisasContext *ctx)
5282 {
5283 #if defined(CONFIG_USER_ONLY)
5284 GEN_PRIV;
5285 #else
5286 CHK_HV;
5287
5288 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
5289 * embedded however needs to deal with tlbsync. We don't try to be
5290 * fancy and swallow the overhead of checking for both.
5291 */
5292 gen_check_tlb_flush(ctx);
5293 #endif /* defined(CONFIG_USER_ONLY) */
5294 }
5295
5296 #if defined(TARGET_PPC64)
5297 /* slbia */
5298 static void gen_slbia(DisasContext *ctx)
5299 {
5300 #if defined(CONFIG_USER_ONLY)
5301 GEN_PRIV;
5302 #else
5303 CHK_SV;
5304
5305 gen_helper_slbia(cpu_env);
5306 #endif /* defined(CONFIG_USER_ONLY) */
5307 }
5308
5309 /* slbie */
5310 static void gen_slbie(DisasContext *ctx)
5311 {
5312 #if defined(CONFIG_USER_ONLY)
5313 GEN_PRIV;
5314 #else
5315 CHK_SV;
5316
5317 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5318 #endif /* defined(CONFIG_USER_ONLY) */
5319 }
5320 #endif /* defined(TARGET_PPC64) */
5321
5322 /*** External control ***/
5323 /* Optional: */
5324
5325 /* eciwx */
5326 static void gen_eciwx(DisasContext *ctx)
5327 {
5328 TCGv t0;
5329 /* Should check EAR[E] ! */
5330 gen_set_access_type(ctx, ACCESS_EXT);
5331 t0 = tcg_temp_new();
5332 gen_addr_reg_index(ctx, t0);
5333 gen_check_align(ctx, t0, 0x03);
5334 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
5335 tcg_temp_free(t0);
5336 }
5337
5338 /* ecowx */
5339 static void gen_ecowx(DisasContext *ctx)
5340 {
5341 TCGv t0;
5342 /* Should check EAR[E] ! */
5343 gen_set_access_type(ctx, ACCESS_EXT);
5344 t0 = tcg_temp_new();
5345 gen_addr_reg_index(ctx, t0);
5346 gen_check_align(ctx, t0, 0x03);
5347 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
5348 tcg_temp_free(t0);
5349 }
5350
5351 /* PowerPC 601 specific instructions */
5352
5353 /* abs - abs. */
5354 static void gen_abs(DisasContext *ctx)
5355 {
5356 TCGLabel *l1 = gen_new_label();
5357 TCGLabel *l2 = gen_new_label();
5358 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
5359 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5360 tcg_gen_br(l2);
5361 gen_set_label(l1);
5362 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5363 gen_set_label(l2);
5364 if (unlikely(Rc(ctx->opcode) != 0))
5365 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5366 }
5367
5368 /* abso - abso. */
5369 static void gen_abso(DisasContext *ctx)
5370 {
5371 TCGLabel *l1 = gen_new_label();
5372 TCGLabel *l2 = gen_new_label();
5373 TCGLabel *l3 = gen_new_label();
5374 /* Start with XER OV disabled, the most likely case */
5375 tcg_gen_movi_tl(cpu_ov, 0);
5376 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
5377 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
5378 tcg_gen_movi_tl(cpu_ov, 1);
5379 tcg_gen_movi_tl(cpu_so, 1);
5380 tcg_gen_br(l2);
5381 gen_set_label(l1);
5382 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5383 tcg_gen_br(l3);
5384 gen_set_label(l2);
5385 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5386 gen_set_label(l3);
5387 if (unlikely(Rc(ctx->opcode) != 0))
5388 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5389 }
5390
5391 /* clcs */
5392 static void gen_clcs(DisasContext *ctx)
5393 {
5394 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
5395 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5396 tcg_temp_free_i32(t0);
5397 /* Rc=1 sets CR0 to an undefined state */
5398 }
5399
5400 /* div - div. */
5401 static void gen_div(DisasContext *ctx)
5402 {
5403 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5404 cpu_gpr[rB(ctx->opcode)]);
5405 if (unlikely(Rc(ctx->opcode) != 0))
5406 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5407 }
5408
5409 /* divo - divo. */
5410 static void gen_divo(DisasContext *ctx)
5411 {
5412 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5413 cpu_gpr[rB(ctx->opcode)]);
5414 if (unlikely(Rc(ctx->opcode) != 0))
5415 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5416 }
5417
5418 /* divs - divs. */
5419 static void gen_divs(DisasContext *ctx)
5420 {
5421 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5422 cpu_gpr[rB(ctx->opcode)]);
5423 if (unlikely(Rc(ctx->opcode) != 0))
5424 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5425 }
5426
5427 /* divso - divso. */
5428 static void gen_divso(DisasContext *ctx)
5429 {
5430 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5431 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5432 if (unlikely(Rc(ctx->opcode) != 0))
5433 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5434 }
5435
5436 /* doz - doz. */
5437 static void gen_doz(DisasContext *ctx)
5438 {
5439 TCGLabel *l1 = gen_new_label();
5440 TCGLabel *l2 = gen_new_label();
5441 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5442 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5443 tcg_gen_br(l2);
5444 gen_set_label(l1);
5445 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5446 gen_set_label(l2);
5447 if (unlikely(Rc(ctx->opcode) != 0))
5448 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5449 }
5450
5451 /* dozo - dozo. */
5452 static void gen_dozo(DisasContext *ctx)
5453 {
5454 TCGLabel *l1 = gen_new_label();
5455 TCGLabel *l2 = gen_new_label();
5456 TCGv t0 = tcg_temp_new();
5457 TCGv t1 = tcg_temp_new();
5458 TCGv t2 = tcg_temp_new();
5459 /* Start with XER OV disabled, the most likely case */
5460 tcg_gen_movi_tl(cpu_ov, 0);
5461 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5462 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5463 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5464 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5465 tcg_gen_andc_tl(t1, t1, t2);
5466 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5467 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5468 tcg_gen_movi_tl(cpu_ov, 1);
5469 tcg_gen_movi_tl(cpu_so, 1);
5470 tcg_gen_br(l2);
5471 gen_set_label(l1);
5472 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5473 gen_set_label(l2);
5474 tcg_temp_free(t0);
5475 tcg_temp_free(t1);
5476 tcg_temp_free(t2);
5477 if (unlikely(Rc(ctx->opcode) != 0))
5478 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5479 }
5480
5481 /* dozi */
5482 static void gen_dozi(DisasContext *ctx)
5483 {
5484 target_long simm = SIMM(ctx->opcode);
5485 TCGLabel *l1 = gen_new_label();
5486 TCGLabel *l2 = gen_new_label();
5487 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5488 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5489 tcg_gen_br(l2);
5490 gen_set_label(l1);
5491 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5492 gen_set_label(l2);
5493 if (unlikely(Rc(ctx->opcode) != 0))
5494 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5495 }
5496
5497 /* lscbx - lscbx. */
5498 static void gen_lscbx(DisasContext *ctx)
5499 {
5500 TCGv t0 = tcg_temp_new();
5501 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5502 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5503 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5504
5505 gen_addr_reg_index(ctx, t0);
5506 /* NIP cannot be restored if the memory exception comes from an helper */
5507 gen_update_nip(ctx, ctx->nip - 4);
5508 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5509 tcg_temp_free_i32(t1);
5510 tcg_temp_free_i32(t2);
5511 tcg_temp_free_i32(t3);
5512 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5513 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5514 if (unlikely(Rc(ctx->opcode) != 0))
5515 gen_set_Rc0(ctx, t0);
5516 tcg_temp_free(t0);
5517 }
5518
5519 /* maskg - maskg. */
5520 static void gen_maskg(DisasContext *ctx)
5521 {
5522 TCGLabel *l1 = gen_new_label();
5523 TCGv t0 = tcg_temp_new();
5524 TCGv t1 = tcg_temp_new();
5525 TCGv t2 = tcg_temp_new();
5526 TCGv t3 = tcg_temp_new();
5527 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5528 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5529 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5530 tcg_gen_addi_tl(t2, t0, 1);
5531 tcg_gen_shr_tl(t2, t3, t2);
5532 tcg_gen_shr_tl(t3, t3, t1);
5533 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5534 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5535 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5536 gen_set_label(l1);
5537 tcg_temp_free(t0);
5538 tcg_temp_free(t1);
5539 tcg_temp_free(t2);
5540 tcg_temp_free(t3);
5541 if (unlikely(Rc(ctx->opcode) != 0))
5542 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5543 }
5544
5545 /* maskir - maskir. */
5546 static void gen_maskir(DisasContext *ctx)
5547 {
5548 TCGv t0 = tcg_temp_new();
5549 TCGv t1 = tcg_temp_new();
5550 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5551 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5552 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5553 tcg_temp_free(t0);
5554 tcg_temp_free(t1);
5555 if (unlikely(Rc(ctx->opcode) != 0))
5556 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5557 }
5558
5559 /* mul - mul. */
5560 static void gen_mul(DisasContext *ctx)
5561 {
5562 TCGv_i64 t0 = tcg_temp_new_i64();
5563 TCGv_i64 t1 = tcg_temp_new_i64();
5564 TCGv t2 = tcg_temp_new();
5565 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5566 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5567 tcg_gen_mul_i64(t0, t0, t1);
5568 tcg_gen_trunc_i64_tl(t2, t0);
5569 gen_store_spr(SPR_MQ, t2);
5570 tcg_gen_shri_i64(t1, t0, 32);
5571 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5572 tcg_temp_free_i64(t0);
5573 tcg_temp_free_i64(t1);
5574 tcg_temp_free(t2);
5575 if (unlikely(Rc(ctx->opcode) != 0))
5576 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5577 }
5578
5579 /* mulo - mulo. */
5580 static void gen_mulo(DisasContext *ctx)
5581 {
5582 TCGLabel *l1 = gen_new_label();
5583 TCGv_i64 t0 = tcg_temp_new_i64();
5584 TCGv_i64 t1 = tcg_temp_new_i64();
5585 TCGv t2 = tcg_temp_new();
5586 /* Start with XER OV disabled, the most likely case */
5587 tcg_gen_movi_tl(cpu_ov, 0);
5588 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5589 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5590 tcg_gen_mul_i64(t0, t0, t1);
5591 tcg_gen_trunc_i64_tl(t2, t0);
5592 gen_store_spr(SPR_MQ, t2);
5593 tcg_gen_shri_i64(t1, t0, 32);
5594 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5595 tcg_gen_ext32s_i64(t1, t0);
5596 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5597 tcg_gen_movi_tl(cpu_ov, 1);
5598 tcg_gen_movi_tl(cpu_so, 1);
5599 gen_set_label(l1);
5600 tcg_temp_free_i64(t0);
5601 tcg_temp_free_i64(t1);
5602 tcg_temp_free(t2);
5603 if (unlikely(Rc(ctx->opcode) != 0))
5604 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5605 }
5606
5607 /* nabs - nabs. */
5608 static void gen_nabs(DisasContext *ctx)
5609 {
5610 TCGLabel *l1 = gen_new_label();
5611 TCGLabel *l2 = gen_new_label();
5612 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5613 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5614 tcg_gen_br(l2);
5615 gen_set_label(l1);
5616 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5617 gen_set_label(l2);
5618 if (unlikely(Rc(ctx->opcode) != 0))
5619 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5620 }
5621
5622 /* nabso - nabso. */
5623 static void gen_nabso(DisasContext *ctx)
5624 {
5625 TCGLabel *l1 = gen_new_label();
5626 TCGLabel *l2 = gen_new_label();
5627 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5628 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5629 tcg_gen_br(l2);
5630 gen_set_label(l1);
5631 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5632 gen_set_label(l2);
5633 /* nabs never overflows */
5634 tcg_gen_movi_tl(cpu_ov, 0);
5635 if (unlikely(Rc(ctx->opcode) != 0))
5636 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5637 }
5638
5639 /* rlmi - rlmi. */
5640 static void gen_rlmi(DisasContext *ctx)
5641 {
5642 uint32_t mb = MB(ctx->opcode);
5643 uint32_t me = ME(ctx->opcode);
5644 TCGv t0 = tcg_temp_new();
5645 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5646 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5647 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5648 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5649 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5650 tcg_temp_free(t0);
5651 if (unlikely(Rc(ctx->opcode) != 0))
5652 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5653 }
5654
5655 /* rrib - rrib. */
5656 static void gen_rrib(DisasContext *ctx)
5657 {
5658 TCGv t0 = tcg_temp_new();
5659 TCGv t1 = tcg_temp_new();
5660 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5661 tcg_gen_movi_tl(t1, 0x80000000);
5662 tcg_gen_shr_tl(t1, t1, t0);
5663 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5664 tcg_gen_and_tl(t0, t0, t1);
5665 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5666 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5667 tcg_temp_free(t0);
5668 tcg_temp_free(t1);
5669 if (unlikely(Rc(ctx->opcode) != 0))
5670 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5671 }
5672
5673 /* sle - sle. */
5674 static void gen_sle(DisasContext *ctx)
5675 {
5676 TCGv t0 = tcg_temp_new();
5677 TCGv t1 = tcg_temp_new();
5678 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5679 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5680 tcg_gen_subfi_tl(t1, 32, t1);
5681 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5682 tcg_gen_or_tl(t1, t0, t1);
5683 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5684 gen_store_spr(SPR_MQ, t1);
5685 tcg_temp_free(t0);
5686 tcg_temp_free(t1);
5687 if (unlikely(Rc(ctx->opcode) != 0))
5688 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5689 }
5690
5691 /* sleq - sleq. */
5692 static void gen_sleq(DisasContext *ctx)
5693 {
5694 TCGv t0 = tcg_temp_new();
5695 TCGv t1 = tcg_temp_new();
5696 TCGv t2 = tcg_temp_new();
5697 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5698 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5699 tcg_gen_shl_tl(t2, t2, t0);
5700 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5701 gen_load_spr(t1, SPR_MQ);
5702 gen_store_spr(SPR_MQ, t0);
5703 tcg_gen_and_tl(t0, t0, t2);
5704 tcg_gen_andc_tl(t1, t1, t2);
5705 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5706 tcg_temp_free(t0);
5707 tcg_temp_free(t1);
5708 tcg_temp_free(t2);
5709 if (unlikely(Rc(ctx->opcode) != 0))
5710 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5711 }
5712
5713 /* sliq - sliq. */
5714 static void gen_sliq(DisasContext *ctx)
5715 {
5716 int sh = SH(ctx->opcode);
5717 TCGv t0 = tcg_temp_new();
5718 TCGv t1 = tcg_temp_new();
5719 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5720 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5721 tcg_gen_or_tl(t1, t0, t1);
5722 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5723 gen_store_spr(SPR_MQ, t1);
5724 tcg_temp_free(t0);
5725 tcg_temp_free(t1);
5726 if (unlikely(Rc(ctx->opcode) != 0))
5727 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5728 }
5729
5730 /* slliq - slliq. */
5731 static void gen_slliq(DisasContext *ctx)
5732 {
5733 int sh = SH(ctx->opcode);
5734 TCGv t0 = tcg_temp_new();
5735 TCGv t1 = tcg_temp_new();
5736 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5737 gen_load_spr(t1, SPR_MQ);
5738 gen_store_spr(SPR_MQ, t0);
5739 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5740 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5741 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5742 tcg_temp_free(t0);
5743 tcg_temp_free(t1);
5744 if (unlikely(Rc(ctx->opcode) != 0))
5745 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5746 }
5747
5748 /* sllq - sllq. */
5749 static void gen_sllq(DisasContext *ctx)
5750 {
5751 TCGLabel *l1 = gen_new_label();
5752 TCGLabel *l2 = gen_new_label();
5753 TCGv t0 = tcg_temp_local_new();
5754 TCGv t1 = tcg_temp_local_new();
5755 TCGv t2 = tcg_temp_local_new();
5756 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5757 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5758 tcg_gen_shl_tl(t1, t1, t2);
5759 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5760 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5761 gen_load_spr(t0, SPR_MQ);
5762 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5763 tcg_gen_br(l2);
5764 gen_set_label(l1);
5765 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5766 gen_load_spr(t2, SPR_MQ);
5767 tcg_gen_andc_tl(t1, t2, t1);
5768 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5769 gen_set_label(l2);
5770 tcg_temp_free(t0);
5771 tcg_temp_free(t1);
5772 tcg_temp_free(t2);
5773 if (unlikely(Rc(ctx->opcode) != 0))
5774 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5775 }
5776
5777 /* slq - slq. */
5778 static void gen_slq(DisasContext *ctx)
5779 {
5780 TCGLabel *l1 = gen_new_label();
5781 TCGv t0 = tcg_temp_new();
5782 TCGv t1 = tcg_temp_new();
5783 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5784 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5785 tcg_gen_subfi_tl(t1, 32, t1);
5786 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5787 tcg_gen_or_tl(t1, t0, t1);
5788 gen_store_spr(SPR_MQ, t1);
5789 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5790 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5791 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5792 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5793 gen_set_label(l1);
5794 tcg_temp_free(t0);
5795 tcg_temp_free(t1);
5796 if (unlikely(Rc(ctx->opcode) != 0))
5797 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5798 }
5799
5800 /* sraiq - sraiq. */
5801 static void gen_sraiq(DisasContext *ctx)
5802 {
5803 int sh = SH(ctx->opcode);
5804 TCGLabel *l1 = gen_new_label();
5805 TCGv t0 = tcg_temp_new();
5806 TCGv t1 = tcg_temp_new();
5807 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5808 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5809 tcg_gen_or_tl(t0, t0, t1);
5810 gen_store_spr(SPR_MQ, t0);
5811 tcg_gen_movi_tl(cpu_ca, 0);
5812 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5813 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5814 tcg_gen_movi_tl(cpu_ca, 1);
5815 gen_set_label(l1);
5816 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5817 tcg_temp_free(t0);
5818 tcg_temp_free(t1);
5819 if (unlikely(Rc(ctx->opcode) != 0))
5820 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5821 }
5822
5823 /* sraq - sraq. */
5824 static void gen_sraq(DisasContext *ctx)
5825 {
5826 TCGLabel *l1 = gen_new_label();
5827 TCGLabel *l2 = gen_new_label();
5828 TCGv t0 = tcg_temp_new();
5829 TCGv t1 = tcg_temp_local_new();
5830 TCGv t2 = tcg_temp_local_new();
5831 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5832 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5833 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5834 tcg_gen_subfi_tl(t2, 32, t2);
5835 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5836 tcg_gen_or_tl(t0, t0, t2);
5837 gen_store_spr(SPR_MQ, t0);
5838 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5839 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5840 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5841 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5842 gen_set_label(l1);
5843 tcg_temp_free(t0);
5844 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5845 tcg_gen_movi_tl(cpu_ca, 0);
5846 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5847 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5848 tcg_gen_movi_tl(cpu_ca, 1);
5849 gen_set_label(l2);
5850 tcg_temp_free(t1);
5851 tcg_temp_free(t2);
5852 if (unlikely(Rc(ctx->opcode) != 0))
5853 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5854 }
5855
5856 /* sre - sre. */
5857 static void gen_sre(DisasContext *ctx)
5858 {
5859 TCGv t0 = tcg_temp_new();
5860 TCGv t1 = tcg_temp_new();
5861 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5862 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5863 tcg_gen_subfi_tl(t1, 32, t1);
5864 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5865 tcg_gen_or_tl(t1, t0, t1);
5866 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5867 gen_store_spr(SPR_MQ, t1);
5868 tcg_temp_free(t0);
5869 tcg_temp_free(t1);
5870 if (unlikely(Rc(ctx->opcode) != 0))
5871 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5872 }
5873
5874 /* srea - srea. */
5875 static void gen_srea(DisasContext *ctx)
5876 {
5877 TCGv t0 = tcg_temp_new();
5878 TCGv t1 = tcg_temp_new();
5879 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5880 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5881 gen_store_spr(SPR_MQ, t0);
5882 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5883 tcg_temp_free(t0);
5884 tcg_temp_free(t1);
5885 if (unlikely(Rc(ctx->opcode) != 0))
5886 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5887 }
5888
5889 /* sreq */
5890 static void gen_sreq(DisasContext *ctx)
5891 {
5892 TCGv t0 = tcg_temp_new();
5893 TCGv t1 = tcg_temp_new();
5894 TCGv t2 = tcg_temp_new();
5895 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5896 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5897 tcg_gen_shr_tl(t1, t1, t0);
5898 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5899 gen_load_spr(t2, SPR_MQ);
5900 gen_store_spr(SPR_MQ, t0);
5901 tcg_gen_and_tl(t0, t0, t1);
5902 tcg_gen_andc_tl(t2, t2, t1);
5903 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5904 tcg_temp_free(t0);
5905 tcg_temp_free(t1);
5906 tcg_temp_free(t2);
5907 if (unlikely(Rc(ctx->opcode) != 0))
5908 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5909 }
5910
5911 /* sriq */
5912 static void gen_sriq(DisasContext *ctx)
5913 {
5914 int sh = SH(ctx->opcode);
5915 TCGv t0 = tcg_temp_new();
5916 TCGv t1 = tcg_temp_new();
5917 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5918 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5919 tcg_gen_or_tl(t1, t0, t1);
5920 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5921 gen_store_spr(SPR_MQ, t1);
5922 tcg_temp_free(t0);
5923 tcg_temp_free(t1);
5924 if (unlikely(Rc(ctx->opcode) != 0))
5925 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5926 }
5927
5928 /* srliq */
5929 static void gen_srliq(DisasContext *ctx)
5930 {
5931 int sh = SH(ctx->opcode);
5932 TCGv t0 = tcg_temp_new();
5933 TCGv t1 = tcg_temp_new();
5934 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5935 gen_load_spr(t1, SPR_MQ);
5936 gen_store_spr(SPR_MQ, t0);
5937 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5938 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5939 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5940 tcg_temp_free(t0);
5941 tcg_temp_free(t1);
5942 if (unlikely(Rc(ctx->opcode) != 0))
5943 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5944 }
5945
5946 /* srlq */
5947 static void gen_srlq(DisasContext *ctx)
5948 {
5949 TCGLabel *l1 = gen_new_label();
5950 TCGLabel *l2 = gen_new_label();
5951 TCGv t0 = tcg_temp_local_new();
5952 TCGv t1 = tcg_temp_local_new();
5953 TCGv t2 = tcg_temp_local_new();
5954 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5955 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5956 tcg_gen_shr_tl(t2, t1, t2);
5957 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5958 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5959 gen_load_spr(t0, SPR_MQ);
5960 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5961 tcg_gen_br(l2);
5962 gen_set_label(l1);
5963 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5964 tcg_gen_and_tl(t0, t0, t2);
5965 gen_load_spr(t1, SPR_MQ);
5966 tcg_gen_andc_tl(t1, t1, t2);
5967 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5968 gen_set_label(l2);
5969 tcg_temp_free(t0);
5970 tcg_temp_free(t1);
5971 tcg_temp_free(t2);
5972 if (unlikely(Rc(ctx->opcode) != 0))
5973 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5974 }
5975
5976 /* srq */
5977 static void gen_srq(DisasContext *ctx)
5978 {
5979 TCGLabel *l1 = gen_new_label();
5980 TCGv t0 = tcg_temp_new();
5981 TCGv t1 = tcg_temp_new();
5982 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5983 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5984 tcg_gen_subfi_tl(t1, 32, t1);
5985 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5986 tcg_gen_or_tl(t1, t0, t1);
5987 gen_store_spr(SPR_MQ, t1);
5988 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5989 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5990 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5991 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5992 gen_set_label(l1);
5993 tcg_temp_free(t0);
5994 tcg_temp_free(t1);
5995 if (unlikely(Rc(ctx->opcode) != 0))
5996 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5997 }
5998
5999 /* PowerPC 602 specific instructions */
6000
6001 /* dsa */
6002 static void gen_dsa(DisasContext *ctx)
6003 {
6004 /* XXX: TODO */
6005 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6006 }
6007
6008 /* esa */
6009 static void gen_esa(DisasContext *ctx)
6010 {
6011 /* XXX: TODO */
6012 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6013 }
6014
6015 /* mfrom */
6016 static void gen_mfrom(DisasContext *ctx)
6017 {
6018 #if defined(CONFIG_USER_ONLY)
6019 GEN_PRIV;
6020 #else
6021 CHK_SV;
6022 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6023 #endif /* defined(CONFIG_USER_ONLY) */
6024 }
6025
6026 /* 602 - 603 - G2 TLB management */
6027
6028 /* tlbld */
6029 static void gen_tlbld_6xx(DisasContext *ctx)
6030 {
6031 #if defined(CONFIG_USER_ONLY)
6032 GEN_PRIV;
6033 #else
6034 CHK_SV;
6035 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6036 #endif /* defined(CONFIG_USER_ONLY) */
6037 }
6038
6039 /* tlbli */
6040 static void gen_tlbli_6xx(DisasContext *ctx)
6041 {
6042 #if defined(CONFIG_USER_ONLY)
6043 GEN_PRIV;
6044 #else
6045 CHK_SV;
6046 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6047 #endif /* defined(CONFIG_USER_ONLY) */
6048 }
6049
6050 /* 74xx TLB management */
6051
6052 /* tlbld */
6053 static void gen_tlbld_74xx(DisasContext *ctx)
6054 {
6055 #if defined(CONFIG_USER_ONLY)
6056 GEN_PRIV;
6057 #else
6058 CHK_SV;
6059 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6060 #endif /* defined(CONFIG_USER_ONLY) */
6061 }
6062
6063 /* tlbli */
6064 static void gen_tlbli_74xx(DisasContext *ctx)
6065 {
6066 #if defined(CONFIG_USER_ONLY)
6067 GEN_PRIV;
6068 #else
6069 CHK_SV;
6070 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6071 #endif /* defined(CONFIG_USER_ONLY) */
6072 }
6073
6074 /* POWER instructions not in PowerPC 601 */
6075
6076 /* clf */
6077 static void gen_clf(DisasContext *ctx)
6078 {
6079 /* Cache line flush: implemented as no-op */
6080 }
6081
6082 /* cli */
6083 static void gen_cli(DisasContext *ctx)
6084 {
6085 #if defined(CONFIG_USER_ONLY)
6086 GEN_PRIV;
6087 #else
6088 /* Cache line invalidate: privileged and treated as no-op */
6089 CHK_SV;
6090 #endif /* defined(CONFIG_USER_ONLY) */
6091 }
6092
6093 /* dclst */
6094 static void gen_dclst(DisasContext *ctx)
6095 {
6096 /* Data cache line store: treated as no-op */
6097 }
6098
6099 static void gen_mfsri(DisasContext *ctx)
6100 {
6101 #if defined(CONFIG_USER_ONLY)
6102 GEN_PRIV;
6103 #else
6104 int ra = rA(ctx->opcode);
6105 int rd = rD(ctx->opcode);
6106 TCGv t0;
6107
6108 CHK_SV;
6109 t0 = tcg_temp_new();
6110 gen_addr_reg_index(ctx, t0);
6111 tcg_gen_shri_tl(t0, t0, 28);
6112 tcg_gen_andi_tl(t0, t0, 0xF);
6113 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
6114 tcg_temp_free(t0);
6115 if (ra != 0 && ra != rd)
6116 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
6117 #endif /* defined(CONFIG_USER_ONLY) */
6118 }
6119
6120 static void gen_rac(DisasContext *ctx)
6121 {
6122 #if defined(CONFIG_USER_ONLY)
6123 GEN_PRIV;
6124 #else
6125 TCGv t0;
6126
6127 CHK_SV;
6128 t0 = tcg_temp_new();
6129 gen_addr_reg_index(ctx, t0);
6130 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6131 tcg_temp_free(t0);
6132 #endif /* defined(CONFIG_USER_ONLY) */
6133 }
6134
6135 static void gen_rfsvc(DisasContext *ctx)
6136 {
6137 #if defined(CONFIG_USER_ONLY)
6138 GEN_PRIV;
6139 #else
6140 CHK_SV;
6141
6142 gen_helper_rfsvc(cpu_env);
6143 gen_sync_exception(ctx);
6144 #endif /* defined(CONFIG_USER_ONLY) */
6145 }
6146
6147 /* svc is not implemented for now */
6148
6149 /* POWER2 specific instructions */
6150 /* Quad manipulation (load/store two floats at a time) */
6151
6152 /* lfq */
6153 static void gen_lfq(DisasContext *ctx)
6154 {
6155 int rd = rD(ctx->opcode);
6156 TCGv t0;
6157 gen_set_access_type(ctx, ACCESS_FLOAT);
6158 t0 = tcg_temp_new();
6159 gen_addr_imm_index(ctx, t0, 0);
6160 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
6161 gen_addr_add(ctx, t0, t0, 8);
6162 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
6163 tcg_temp_free(t0);
6164 }
6165
6166 /* lfqu */
6167 static void gen_lfqu(DisasContext *ctx)
6168 {
6169 int ra = rA(ctx->opcode);
6170 int rd = rD(ctx->opcode);
6171 TCGv t0, t1;
6172 gen_set_access_type(ctx, ACCESS_FLOAT);
6173 t0 = tcg_temp_new();
6174 t1 = tcg_temp_new();
6175 gen_addr_imm_index(ctx, t0, 0);
6176 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
6177 gen_addr_add(ctx, t1, t0, 8);
6178 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
6179 if (ra != 0)
6180 tcg_gen_mov_tl(cpu_gpr[ra], t0);
6181 tcg_temp_free(t0);
6182 tcg_temp_free(t1);
6183 }
6184
6185 /* lfqux */
6186 static void gen_lfqux(DisasContext *ctx)
6187 {
6188 int ra = rA(ctx->opcode);
6189 int rd = rD(ctx->opcode);
6190 gen_set_access_type(ctx, ACCESS_FLOAT);
6191 TCGv t0, t1;
6192 t0 = tcg_temp_new();
6193 gen_addr_reg_index(ctx, t0);
6194 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
6195 t1 = tcg_temp_new();
6196 gen_addr_add(ctx, t1, t0, 8);
6197 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
6198 tcg_temp_free(t1);
6199 if (ra != 0)
6200 tcg_gen_mov_tl(cpu_gpr[ra], t0);
6201 tcg_temp_free(t0);
6202 }
6203
6204 /* lfqx */
6205 static void gen_lfqx(DisasContext *ctx)
6206 {
6207 int rd = rD(ctx->opcode);
6208 TCGv t0;
6209 gen_set_access_type(ctx, ACCESS_FLOAT);
6210 t0 = tcg_temp_new();
6211 gen_addr_reg_index(ctx, t0);
6212 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
6213 gen_addr_add(ctx, t0, t0, 8);
6214 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
6215 tcg_temp_free(t0);
6216 }
6217
6218 /* stfq */
6219 static void gen_stfq(DisasContext *ctx)
6220 {
6221 int rd = rD(ctx->opcode);
6222 TCGv t0;
6223 gen_set_access_type(ctx, ACCESS_FLOAT);
6224 t0 = tcg_temp_new();
6225 gen_addr_imm_index(ctx, t0, 0);
6226 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
6227 gen_addr_add(ctx, t0, t0, 8);
6228 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
6229 tcg_temp_free(t0);
6230 }
6231
6232 /* stfqu */
6233 static void gen_stfqu(DisasContext *ctx)
6234 {
6235 int ra = rA(ctx->opcode);
6236 int rd = rD(ctx->opcode);
6237 TCGv t0, t1;
6238 gen_set_access_type(ctx, ACCESS_FLOAT);
6239 t0 = tcg_temp_new();
6240 gen_addr_imm_index(ctx, t0, 0);
6241 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
6242 t1 = tcg_temp_new();
6243 gen_addr_add(ctx, t1, t0, 8);
6244 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
6245 tcg_temp_free(t1);
6246 if (ra != 0)
6247 tcg_gen_mov_tl(cpu_gpr[ra], t0);
6248 tcg_temp_free(t0);
6249 }
6250
6251 /* stfqux */
6252 static void gen_stfqux(DisasContext *ctx)
6253 {
6254 int ra = rA(ctx->opcode);
6255 int rd = rD(ctx->opcode);
6256 TCGv t0, t1;
6257 gen_set_access_type(ctx, ACCESS_FLOAT);
6258 t0 = tcg_temp_new();
6259 gen_addr_reg_index(ctx, t0);
6260 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
6261 t1 = tcg_temp_new();
6262 gen_addr_add(ctx, t1, t0, 8);
6263 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
6264 tcg_temp_free(t1);
6265 if (ra != 0)
6266 tcg_gen_mov_tl(cpu_gpr[ra], t0);
6267 tcg_temp_free(t0);
6268 }
6269
6270 /* stfqx */
6271 static void gen_stfqx(DisasContext *ctx)
6272 {
6273 int rd = rD(ctx->opcode);
6274 TCGv t0;
6275 gen_set_access_type(ctx, ACCESS_FLOAT);
6276 t0 = tcg_temp_new();
6277 gen_addr_reg_index(ctx, t0);
6278 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
6279 gen_addr_add(ctx, t0, t0, 8);
6280 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
6281 tcg_temp_free(t0);
6282 }
6283
6284 /* BookE specific instructions */
6285
6286 /* XXX: not implemented on 440 ? */
6287 static void gen_mfapidi(DisasContext *ctx)
6288 {
6289 /* XXX: TODO */
6290 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6291 }
6292
6293 /* XXX: not implemented on 440 ? */
6294 static void gen_tlbiva(DisasContext *ctx)
6295 {
6296 #if defined(CONFIG_USER_ONLY)
6297 GEN_PRIV;
6298 #else
6299 TCGv t0;
6300
6301 CHK_SV;
6302 t0 = tcg_temp_new();
6303 gen_addr_reg_index(ctx, t0);
6304 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6305 tcg_temp_free(t0);
6306 #endif /* defined(CONFIG_USER_ONLY) */
6307 }
6308
6309 /* All 405 MAC instructions are translated here */
6310 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
6311 int ra, int rb, int rt, int Rc)
6312 {
6313 TCGv t0, t1;
6314
6315 t0 = tcg_temp_local_new();
6316 t1 = tcg_temp_local_new();
6317
6318 switch (opc3 & 0x0D) {
6319 case 0x05:
6320 /* macchw - macchw. - macchwo - macchwo. */
6321 /* macchws - macchws. - macchwso - macchwso. */
6322 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
6323 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
6324 /* mulchw - mulchw. */
6325 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6326 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6327 tcg_gen_ext16s_tl(t1, t1);
6328 break;
6329 case 0x04:
6330 /* macchwu - macchwu. - macchwuo - macchwuo. */
6331 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
6332 /* mulchwu - mulchwu. */
6333 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6334 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6335 tcg_gen_ext16u_tl(t1, t1);
6336 break;
6337 case 0x01:
6338 /* machhw - machhw. - machhwo - machhwo. */
6339 /* machhws - machhws. - machhwso - machhwso. */
6340 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
6341 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
6342 /* mulhhw - mulhhw. */
6343 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
6344 tcg_gen_ext16s_tl(t0, t0);
6345 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6346 tcg_gen_ext16s_tl(t1, t1);
6347 break;
6348 case 0x00:
6349 /* machhwu - machhwu. - machhwuo - machhwuo. */
6350 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
6351 /* mulhhwu - mulhhwu. */
6352 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
6353 tcg_gen_ext16u_tl(t0, t0);
6354 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6355 tcg_gen_ext16u_tl(t1, t1);
6356 break;
6357 case 0x0D:
6358 /* maclhw - maclhw. - maclhwo - maclhwo. */
6359 /* maclhws - maclhws. - maclhwso - maclhwso. */
6360 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
6361 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
6362 /* mullhw - mullhw. */
6363 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6364 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
6365 break;
6366 case 0x0C:
6367 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
6368 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
6369 /* mullhwu - mullhwu. */
6370 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6371 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
6372 break;
6373 }
6374 if (opc2 & 0x04) {
6375 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
6376 tcg_gen_mul_tl(t1, t0, t1);
6377 if (opc2 & 0x02) {
6378 /* nmultiply-and-accumulate (0x0E) */
6379 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
6380 } else {
6381 /* multiply-and-accumulate (0x0C) */
6382 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
6383 }
6384
6385 if (opc3 & 0x12) {
6386 /* Check overflow and/or saturate */
6387 TCGLabel *l1 = gen_new_label();
6388
6389 if (opc3 & 0x10) {
6390 /* Start with XER OV disabled, the most likely case */
6391 tcg_gen_movi_tl(cpu_ov, 0);
6392 }
6393 if (opc3 & 0x01) {
6394 /* Signed */
6395 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
6396 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
6397 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
6398 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
6399 if (opc3 & 0x02) {
6400 /* Saturate */
6401 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
6402 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
6403 }
6404 } else {
6405 /* Unsigned */
6406 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
6407 if (opc3 & 0x02) {
6408 /* Saturate */
6409 tcg_gen_movi_tl(t0, UINT32_MAX);
6410 }
6411 }
6412 if (opc3 & 0x10) {
6413 /* Check overflow */
6414 tcg_gen_movi_tl(cpu_ov, 1);
6415 tcg_gen_movi_tl(cpu_so, 1);
6416 }
6417 gen_set_label(l1);
6418 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6419 }
6420 } else {
6421 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
6422 }
6423 tcg_temp_free(t0);
6424 tcg_temp_free(t1);
6425 if (unlikely(Rc) != 0) {
6426 /* Update Rc0 */
6427 gen_set_Rc0(ctx, cpu_gpr[rt]);
6428 }
6429 }
6430
6431 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6432 static void glue(gen_, name)(DisasContext *ctx) \
6433 { \
6434 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6435 rD(ctx->opcode), Rc(ctx->opcode)); \
6436 }
6437
6438 /* macchw - macchw. */
6439 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
6440 /* macchwo - macchwo. */
6441 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
6442 /* macchws - macchws. */
6443 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
6444 /* macchwso - macchwso. */
6445 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
6446 /* macchwsu - macchwsu. */
6447 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
6448 /* macchwsuo - macchwsuo. */
6449 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
6450 /* macchwu - macchwu. */
6451 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
6452 /* macchwuo - macchwuo. */
6453 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
6454 /* machhw - machhw. */
6455 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
6456 /* machhwo - machhwo. */
6457 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
6458 /* machhws - machhws. */
6459 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
6460 /* machhwso - machhwso. */
6461 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6462 /* machhwsu - machhwsu. */
6463 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6464 /* machhwsuo - machhwsuo. */
6465 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6466 /* machhwu - machhwu. */
6467 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6468 /* machhwuo - machhwuo. */
6469 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6470 /* maclhw - maclhw. */
6471 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6472 /* maclhwo - maclhwo. */
6473 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6474 /* maclhws - maclhws. */
6475 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6476 /* maclhwso - maclhwso. */
6477 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6478 /* maclhwu - maclhwu. */
6479 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6480 /* maclhwuo - maclhwuo. */
6481 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6482 /* maclhwsu - maclhwsu. */
6483 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6484 /* maclhwsuo - maclhwsuo. */
6485 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6486 /* nmacchw - nmacchw. */
6487 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6488 /* nmacchwo - nmacchwo. */
6489 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6490 /* nmacchws - nmacchws. */
6491 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6492 /* nmacchwso - nmacchwso. */
6493 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6494 /* nmachhw - nmachhw. */
6495 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6496 /* nmachhwo - nmachhwo. */
6497 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6498 /* nmachhws - nmachhws. */
6499 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6500 /* nmachhwso - nmachhwso. */
6501 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6502 /* nmaclhw - nmaclhw. */
6503 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6504 /* nmaclhwo - nmaclhwo. */
6505 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6506 /* nmaclhws - nmaclhws. */
6507 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6508 /* nmaclhwso - nmaclhwso. */
6509 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6510
6511 /* mulchw - mulchw. */
6512 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6513 /* mulchwu - mulchwu. */
6514 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6515 /* mulhhw - mulhhw. */
6516 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6517 /* mulhhwu - mulhhwu. */
6518 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6519 /* mullhw - mullhw. */
6520 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6521 /* mullhwu - mullhwu. */
6522 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6523
6524 /* mfdcr */
6525 static void gen_mfdcr(DisasContext *ctx)
6526 {
6527 #if defined(CONFIG_USER_ONLY)
6528 GEN_PRIV;
6529 #else
6530 TCGv dcrn;
6531
6532 CHK_SV;
6533 /* NIP cannot be restored if the memory exception comes from an helper */
6534 gen_update_nip(ctx, ctx->nip - 4);
6535 dcrn = tcg_const_tl(SPR(ctx->opcode));
6536 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6537 tcg_temp_free(dcrn);
6538 #endif /* defined(CONFIG_USER_ONLY) */
6539 }
6540
6541 /* mtdcr */
6542 static void gen_mtdcr(DisasContext *ctx)
6543 {
6544 #if defined(CONFIG_USER_ONLY)
6545 GEN_PRIV;
6546 #else
6547 TCGv dcrn;
6548
6549 CHK_SV;
6550 /* NIP cannot be restored if the memory exception comes from an helper */
6551 gen_update_nip(ctx, ctx->nip - 4);
6552 dcrn = tcg_const_tl(SPR(ctx->opcode));
6553 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6554 tcg_temp_free(dcrn);
6555 #endif /* defined(CONFIG_USER_ONLY) */
6556 }
6557
6558 /* mfdcrx */
6559 /* XXX: not implemented on 440 ? */
6560 static void gen_mfdcrx(DisasContext *ctx)
6561 {
6562 #if defined(CONFIG_USER_ONLY)
6563 GEN_PRIV;
6564 #else
6565 CHK_SV;
6566 /* NIP cannot be restored if the memory exception comes from an helper */
6567 gen_update_nip(ctx, ctx->nip - 4);
6568 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6569 cpu_gpr[rA(ctx->opcode)]);
6570 /* Note: Rc update flag set leads to undefined state of Rc0 */
6571 #endif /* defined(CONFIG_USER_ONLY) */
6572 }
6573
6574 /* mtdcrx */
6575 /* XXX: not implemented on 440 ? */
6576 static void gen_mtdcrx(DisasContext *ctx)
6577 {
6578 #if defined(CONFIG_USER_ONLY)
6579 GEN_PRIV;
6580 #else
6581 CHK_SV;
6582 /* NIP cannot be restored if the memory exception comes from an helper */
6583 gen_update_nip(ctx, ctx->nip - 4);
6584 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6585 cpu_gpr[rS(ctx->opcode)]);
6586 /* Note: Rc update flag set leads to undefined state of Rc0 */
6587 #endif /* defined(CONFIG_USER_ONLY) */
6588 }
6589
6590 /* mfdcrux (PPC 460) : user-mode access to DCR */
6591 static void gen_mfdcrux(DisasContext *ctx)
6592 {
6593 /* NIP cannot be restored if the memory exception comes from an helper */
6594 gen_update_nip(ctx, ctx->nip - 4);
6595 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6596 cpu_gpr[rA(ctx->opcode)]);
6597 /* Note: Rc update flag set leads to undefined state of Rc0 */
6598 }
6599
6600 /* mtdcrux (PPC 460) : user-mode access to DCR */
6601 static void gen_mtdcrux(DisasContext *ctx)
6602 {
6603 /* NIP cannot be restored if the memory exception comes from an helper */
6604 gen_update_nip(ctx, ctx->nip - 4);
6605 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6606 cpu_gpr[rS(ctx->opcode)]);
6607 /* Note: Rc update flag set leads to undefined state of Rc0 */
6608 }
6609
6610 /* dccci */
6611 static void gen_dccci(DisasContext *ctx)
6612 {
6613 CHK_SV;
6614 /* interpreted as no-op */
6615 }
6616
6617 /* dcread */
6618 static void gen_dcread(DisasContext *ctx)
6619 {
6620 #if defined(CONFIG_USER_ONLY)
6621 GEN_PRIV;
6622 #else
6623 TCGv EA, val;
6624
6625 CHK_SV;
6626 gen_set_access_type(ctx, ACCESS_CACHE);
6627 EA = tcg_temp_new();
6628 gen_addr_reg_index(ctx, EA);
6629 val = tcg_temp_new();
6630 gen_qemu_ld32u(ctx, val, EA);
6631 tcg_temp_free(val);
6632 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6633 tcg_temp_free(EA);
6634 #endif /* defined(CONFIG_USER_ONLY) */
6635 }
6636
6637 /* icbt */
6638 static void gen_icbt_40x(DisasContext *ctx)
6639 {
6640 /* interpreted as no-op */
6641 /* XXX: specification say this is treated as a load by the MMU
6642 * but does not generate any exception
6643 */
6644 }
6645
6646 /* iccci */
6647 static void gen_iccci(DisasContext *ctx)
6648 {
6649 CHK_SV;
6650 /* interpreted as no-op */
6651 }
6652
6653 /* icread */
6654 static void gen_icread(DisasContext *ctx)
6655 {
6656 CHK_SV;
6657 /* interpreted as no-op */
6658 }
6659
6660 /* rfci (supervisor only) */
6661 static void gen_rfci_40x(DisasContext *ctx)
6662 {
6663 #if defined(CONFIG_USER_ONLY)
6664 GEN_PRIV;
6665 #else
6666 CHK_SV;
6667 /* Restore CPU state */
6668 gen_helper_40x_rfci(cpu_env);
6669 gen_sync_exception(ctx);
6670 #endif /* defined(CONFIG_USER_ONLY) */
6671 }
6672
6673 static void gen_rfci(DisasContext *ctx)
6674 {
6675 #if defined(CONFIG_USER_ONLY)
6676 GEN_PRIV;
6677 #else
6678 CHK_SV;
6679 /* Restore CPU state */
6680 gen_helper_rfci(cpu_env);
6681 gen_sync_exception(ctx);
6682 #endif /* defined(CONFIG_USER_ONLY) */
6683 }
6684
6685 /* BookE specific */
6686
6687 /* XXX: not implemented on 440 ? */
6688 static void gen_rfdi(DisasContext *ctx)
6689 {
6690 #if defined(CONFIG_USER_ONLY)
6691 GEN_PRIV;
6692 #else
6693 CHK_SV;
6694 /* Restore CPU state */
6695 gen_helper_rfdi(cpu_env);
6696 gen_sync_exception(ctx);
6697 #endif /* defined(CONFIG_USER_ONLY) */
6698 }
6699
6700 /* XXX: not implemented on 440 ? */
6701 static void gen_rfmci(DisasContext *ctx)
6702 {
6703 #if defined(CONFIG_USER_ONLY)
6704 GEN_PRIV;
6705 #else
6706 CHK_SV;
6707 /* Restore CPU state */
6708 gen_helper_rfmci(cpu_env);
6709 gen_sync_exception(ctx);
6710 #endif /* defined(CONFIG_USER_ONLY) */
6711 }
6712
6713 /* TLB management - PowerPC 405 implementation */
6714
6715 /* tlbre */
6716 static void gen_tlbre_40x(DisasContext *ctx)
6717 {
6718 #if defined(CONFIG_USER_ONLY)
6719 GEN_PRIV;
6720 #else
6721 CHK_SV;
6722 switch (rB(ctx->opcode)) {
6723 case 0:
6724 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6725 cpu_gpr[rA(ctx->opcode)]);
6726 break;
6727 case 1:
6728 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6729 cpu_gpr[rA(ctx->opcode)]);
6730 break;
6731 default:
6732 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6733 break;
6734 }
6735 #endif /* defined(CONFIG_USER_ONLY) */
6736 }
6737
6738 /* tlbsx - tlbsx. */
6739 static void gen_tlbsx_40x(DisasContext *ctx)
6740 {
6741 #if defined(CONFIG_USER_ONLY)
6742 GEN_PRIV;
6743 #else
6744 TCGv t0;
6745
6746 CHK_SV;
6747 t0 = tcg_temp_new();
6748 gen_addr_reg_index(ctx, t0);
6749 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6750 tcg_temp_free(t0);
6751 if (Rc(ctx->opcode)) {
6752 TCGLabel *l1 = gen_new_label();
6753 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6754 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6755 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6756 gen_set_label(l1);
6757 }
6758 #endif /* defined(CONFIG_USER_ONLY) */
6759 }
6760
6761 /* tlbwe */
6762 static void gen_tlbwe_40x(DisasContext *ctx)
6763 {
6764 #if defined(CONFIG_USER_ONLY)
6765 GEN_PRIV;
6766 #else
6767 CHK_SV;
6768
6769 switch (rB(ctx->opcode)) {
6770 case 0:
6771 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6772 cpu_gpr[rS(ctx->opcode)]);
6773 break;
6774 case 1:
6775 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6776 cpu_gpr[rS(ctx->opcode)]);
6777 break;
6778 default:
6779 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6780 break;
6781 }
6782 #endif /* defined(CONFIG_USER_ONLY) */
6783 }
6784
6785 /* TLB management - PowerPC 440 implementation */
6786
6787 /* tlbre */
6788 static void gen_tlbre_440(DisasContext *ctx)
6789 {
6790 #if defined(CONFIG_USER_ONLY)
6791 GEN_PRIV;
6792 #else
6793 CHK_SV;
6794
6795 switch (rB(ctx->opcode)) {
6796 case 0:
6797 case 1:
6798 case 2:
6799 {
6800 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6801 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6802 t0, cpu_gpr[rA(ctx->opcode)]);
6803 tcg_temp_free_i32(t0);
6804 }
6805 break;
6806 default:
6807 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6808 break;
6809 }
6810 #endif /* defined(CONFIG_USER_ONLY) */
6811 }
6812
6813 /* tlbsx - tlbsx. */
6814 static void gen_tlbsx_440(DisasContext *ctx)
6815 {
6816 #if defined(CONFIG_USER_ONLY)
6817 GEN_PRIV;
6818 #else
6819 TCGv t0;
6820
6821 CHK_SV;
6822 t0 = tcg_temp_new();
6823 gen_addr_reg_index(ctx, t0);
6824 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6825 tcg_temp_free(t0);
6826 if (Rc(ctx->opcode)) {
6827 TCGLabel *l1 = gen_new_label();
6828 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6829 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6830 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6831 gen_set_label(l1);
6832 }
6833 #endif /* defined(CONFIG_USER_ONLY) */
6834 }
6835
6836 /* tlbwe */
6837 static void gen_tlbwe_440(DisasContext *ctx)
6838 {
6839 #if defined(CONFIG_USER_ONLY)
6840 GEN_PRIV;
6841 #else
6842 CHK_SV;
6843 switch (rB(ctx->opcode)) {
6844 case 0:
6845 case 1:
6846 case 2:
6847 {
6848 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6849 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6850 cpu_gpr[rS(ctx->opcode)]);
6851 tcg_temp_free_i32(t0);
6852 }
6853 break;
6854 default:
6855 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6856 break;
6857 }
6858 #endif /* defined(CONFIG_USER_ONLY) */
6859 }
6860
6861 /* TLB management - PowerPC BookE 2.06 implementation */
6862
6863 /* tlbre */
6864 static void gen_tlbre_booke206(DisasContext *ctx)
6865 {
6866 #if defined(CONFIG_USER_ONLY)
6867 GEN_PRIV;
6868 #else
6869 CHK_SV;
6870 gen_helper_booke206_tlbre(cpu_env);
6871 #endif /* defined(CONFIG_USER_ONLY) */
6872 }
6873
6874 /* tlbsx - tlbsx. */
6875 static void gen_tlbsx_booke206(DisasContext *ctx)
6876 {
6877 #if defined(CONFIG_USER_ONLY)
6878 GEN_PRIV;
6879 #else
6880 TCGv t0;
6881
6882 CHK_SV;
6883 if (rA(ctx->opcode)) {
6884 t0 = tcg_temp_new();
6885 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6886 } else {
6887 t0 = tcg_const_tl(0);
6888 }
6889
6890 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6891 gen_helper_booke206_tlbsx(cpu_env, t0);
6892 tcg_temp_free(t0);
6893 #endif /* defined(CONFIG_USER_ONLY) */
6894 }
6895
6896 /* tlbwe */
6897 static void gen_tlbwe_booke206(DisasContext *ctx)
6898 {
6899 #if defined(CONFIG_USER_ONLY)
6900 GEN_PRIV;
6901 #else
6902 CHK_SV;
6903 gen_update_nip(ctx, ctx->nip - 4);
6904 gen_helper_booke206_tlbwe(cpu_env);
6905 #endif /* defined(CONFIG_USER_ONLY) */
6906 }
6907
6908 static void gen_tlbivax_booke206(DisasContext *ctx)
6909 {
6910 #if defined(CONFIG_USER_ONLY)
6911 GEN_PRIV;
6912 #else
6913 TCGv t0;
6914
6915 CHK_SV;
6916 t0 = tcg_temp_new();
6917 gen_addr_reg_index(ctx, t0);
6918 gen_helper_booke206_tlbivax(cpu_env, t0);
6919 tcg_temp_free(t0);
6920 #endif /* defined(CONFIG_USER_ONLY) */
6921 }
6922
6923 static void gen_tlbilx_booke206(DisasContext *ctx)
6924 {
6925 #if defined(CONFIG_USER_ONLY)
6926 GEN_PRIV;
6927 #else
6928 TCGv t0;
6929
6930 CHK_SV;
6931 t0 = tcg_temp_new();
6932 gen_addr_reg_index(ctx, t0);
6933
6934 switch((ctx->opcode >> 21) & 0x3) {
6935 case 0:
6936 gen_helper_booke206_tlbilx0(cpu_env, t0);
6937 break;
6938 case 1:
6939 gen_helper_booke206_tlbilx1(cpu_env, t0);
6940 break;
6941 case 3:
6942 gen_helper_booke206_tlbilx3(cpu_env, t0);
6943 break;
6944 default:
6945 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6946 break;
6947 }
6948
6949 tcg_temp_free(t0);
6950 #endif /* defined(CONFIG_USER_ONLY) */
6951 }
6952
6953
6954 /* wrtee */
6955 static void gen_wrtee(DisasContext *ctx)
6956 {
6957 #if defined(CONFIG_USER_ONLY)
6958 GEN_PRIV;
6959 #else
6960 TCGv t0;
6961
6962 CHK_SV;
6963 t0 = tcg_temp_new();
6964 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6965 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6966 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6967 tcg_temp_free(t0);
6968 /* Stop translation to have a chance to raise an exception
6969 * if we just set msr_ee to 1
6970 */
6971 gen_stop_exception(ctx);
6972 #endif /* defined(CONFIG_USER_ONLY) */
6973 }
6974
6975 /* wrteei */
6976 static void gen_wrteei(DisasContext *ctx)
6977 {
6978 #if defined(CONFIG_USER_ONLY)
6979 GEN_PRIV;
6980 #else
6981 CHK_SV;
6982 if (ctx->opcode & 0x00008000) {
6983 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6984 /* Stop translation to have a chance to raise an exception */
6985 gen_stop_exception(ctx);
6986 } else {
6987 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6988 }
6989 #endif /* defined(CONFIG_USER_ONLY) */
6990 }
6991
6992 /* PowerPC 440 specific instructions */
6993
6994 /* dlmzb */
6995 static void gen_dlmzb(DisasContext *ctx)
6996 {
6997 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6998 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6999 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
7000 tcg_temp_free_i32(t0);
7001 }
7002
7003 /* mbar replaces eieio on 440 */
7004 static void gen_mbar(DisasContext *ctx)
7005 {
7006 /* interpreted as no-op */
7007 }
7008
7009 /* msync replaces sync on 440 */
7010 static void gen_msync_4xx(DisasContext *ctx)
7011 {
7012 /* interpreted as no-op */
7013 }
7014
7015 /* icbt */
7016 static void gen_icbt_440(DisasContext *ctx)
7017 {
7018 /* interpreted as no-op */
7019 /* XXX: specification say this is treated as a load by the MMU
7020 * but does not generate any exception
7021 */
7022 }
7023
7024 /* Embedded.Processor Control */
7025
7026 static void gen_msgclr(DisasContext *ctx)
7027 {
7028 #if defined(CONFIG_USER_ONLY)
7029 GEN_PRIV;
7030 #else
7031 CHK_SV;
7032 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7033 #endif /* defined(CONFIG_USER_ONLY) */
7034 }
7035
7036 static void gen_msgsnd(DisasContext *ctx)
7037 {
7038 #if defined(CONFIG_USER_ONLY)
7039 GEN_PRIV;
7040 #else
7041 CHK_SV;
7042 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
7043 #endif /* defined(CONFIG_USER_ONLY) */
7044 }
7045
7046 /*** Altivec vector extension ***/
7047 /* Altivec registers moves */
7048
7049 static inline TCGv_ptr gen_avr_ptr(int reg)
7050 {
7051 TCGv_ptr r = tcg_temp_new_ptr();
7052 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
7053 return r;
7054 }
7055
7056 #define GEN_VR_LDX(name, opc2, opc3) \
7057 static void glue(gen_, name)(DisasContext *ctx) \
7058 { \
7059 TCGv EA; \
7060 if (unlikely(!ctx->altivec_enabled)) { \
7061 gen_exception(ctx, POWERPC_EXCP_VPU); \
7062 return; \
7063 } \
7064 gen_set_access_type(ctx, ACCESS_INT); \
7065 EA = tcg_temp_new(); \
7066 gen_addr_reg_index(ctx, EA); \
7067 tcg_gen_andi_tl(EA, EA, ~0xf); \
7068 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
7069 64-bit byteswap already. */ \
7070 if (ctx->le_mode) { \
7071 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
7072 tcg_gen_addi_tl(EA, EA, 8); \
7073 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
7074 } else { \
7075 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
7076 tcg_gen_addi_tl(EA, EA, 8); \
7077 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
7078 } \
7079 tcg_temp_free(EA); \
7080 }
7081
7082 #define GEN_VR_STX(name, opc2, opc3) \
7083 static void gen_st##name(DisasContext *ctx) \
7084 { \
7085 TCGv EA; \
7086 if (unlikely(!ctx->altivec_enabled)) { \
7087 gen_exception(ctx, POWERPC_EXCP_VPU); \
7088 return; \
7089 } \
7090 gen_set_access_type(ctx, ACCESS_INT); \
7091 EA = tcg_temp_new(); \
7092 gen_addr_reg_index(ctx, EA); \
7093 tcg_gen_andi_tl(EA, EA, ~0xf); \
7094 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
7095 64-bit byteswap already. */ \
7096 if (ctx->le_mode) { \
7097 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
7098 tcg_gen_addi_tl(EA, EA, 8); \
7099 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
7100 } else { \
7101 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
7102 tcg_gen_addi_tl(EA, EA, 8); \
7103 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
7104 } \
7105 tcg_temp_free(EA); \
7106 }
7107
7108 #define GEN_VR_LVE(name, opc2, opc3, size) \
7109 static void gen_lve##name(DisasContext *ctx) \
7110 { \
7111 TCGv EA; \
7112 TCGv_ptr rs; \
7113 if (unlikely(!ctx->altivec_enabled)) { \
7114 gen_exception(ctx, POWERPC_EXCP_VPU); \
7115 return; \
7116 } \
7117 gen_set_access_type(ctx, ACCESS_INT); \
7118 EA = tcg_temp_new(); \
7119 gen_addr_reg_index(ctx, EA); \
7120 if (size > 1) { \
7121 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
7122 } \
7123 rs = gen_avr_ptr(rS(ctx->opcode)); \
7124 gen_helper_lve##name(cpu_env, rs, EA); \
7125 tcg_temp_free(EA); \
7126 tcg_temp_free_ptr(rs); \
7127 }
7128
7129 #define GEN_VR_STVE(name, opc2, opc3, size) \
7130 static void gen_stve##name(DisasContext *ctx) \
7131 { \
7132 TCGv EA; \
7133 TCGv_ptr rs; \
7134 if (unlikely(!ctx->altivec_enabled)) { \
7135 gen_exception(ctx, POWERPC_EXCP_VPU); \
7136 return; \
7137 } \
7138 gen_set_access_type(ctx, ACCESS_INT); \
7139 EA = tcg_temp_new(); \
7140 gen_addr_reg_index(ctx, EA); \
7141 if (size > 1) { \
7142 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
7143 } \
7144 rs = gen_avr_ptr(rS(ctx->opcode)); \
7145 gen_helper_stve##name(cpu_env, rs, EA); \
7146 tcg_temp_free(EA); \
7147 tcg_temp_free_ptr(rs); \
7148 }
7149
7150 GEN_VR_LDX(lvx, 0x07, 0x03);
7151 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
7152 GEN_VR_LDX(lvxl, 0x07, 0x0B);
7153
7154 GEN_VR_LVE(bx, 0x07, 0x00, 1);
7155 GEN_VR_LVE(hx, 0x07, 0x01, 2);
7156 GEN_VR_LVE(wx, 0x07, 0x02, 4);
7157
7158 GEN_VR_STX(svx, 0x07, 0x07);
7159 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
7160 GEN_VR_STX(svxl, 0x07, 0x0F);
7161
7162 GEN_VR_STVE(bx, 0x07, 0x04, 1);
7163 GEN_VR_STVE(hx, 0x07, 0x05, 2);
7164 GEN_VR_STVE(wx, 0x07, 0x06, 4);
7165
7166 static void gen_lvsl(DisasContext *ctx)
7167 {
7168 TCGv_ptr rd;
7169 TCGv EA;
7170 if (unlikely(!ctx->altivec_enabled)) {
7171 gen_exception(ctx, POWERPC_EXCP_VPU);
7172 return;
7173 }
7174 EA = tcg_temp_new();
7175 gen_addr_reg_index(ctx, EA);
7176 rd = gen_avr_ptr(rD(ctx->opcode));
7177 gen_helper_lvsl(rd, EA);
7178 tcg_temp_free(EA);
7179 tcg_temp_free_ptr(rd);
7180 }
7181
7182 static void gen_lvsr(DisasContext *ctx)
7183 {
7184 TCGv_ptr rd;
7185 TCGv EA;
7186 if (unlikely(!ctx->altivec_enabled)) {
7187 gen_exception(ctx, POWERPC_EXCP_VPU);
7188 return;
7189 }
7190 EA = tcg_temp_new();
7191 gen_addr_reg_index(ctx, EA);
7192 rd = gen_avr_ptr(rD(ctx->opcode));
7193 gen_helper_lvsr(rd, EA);
7194 tcg_temp_free(EA);
7195 tcg_temp_free_ptr(rd);
7196 }
7197
7198 static void gen_mfvscr(DisasContext *ctx)
7199 {
7200 TCGv_i32 t;
7201 if (unlikely(!ctx->altivec_enabled)) {
7202 gen_exception(ctx, POWERPC_EXCP_VPU);
7203 return;
7204 }
7205 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
7206 t = tcg_temp_new_i32();
7207 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
7208 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
7209 tcg_temp_free_i32(t);
7210 }
7211
7212 static void gen_mtvscr(DisasContext *ctx)
7213 {
7214 TCGv_ptr p;
7215 if (unlikely(!ctx->altivec_enabled)) {
7216 gen_exception(ctx, POWERPC_EXCP_VPU);
7217 return;
7218 }
7219 p = gen_avr_ptr(rB(ctx->opcode));
7220 gen_helper_mtvscr(cpu_env, p);
7221 tcg_temp_free_ptr(p);
7222 }
7223
7224 /* Logical operations */
7225 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
7226 static void glue(gen_, name)(DisasContext *ctx) \
7227 { \
7228 if (unlikely(!ctx->altivec_enabled)) { \
7229 gen_exception(ctx, POWERPC_EXCP_VPU); \
7230 return; \
7231 } \
7232 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
7233 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
7234 }
7235
7236 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
7237 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
7238 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
7239 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
7240 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
7241 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
7242 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
7243 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
7244
7245 #define GEN_VXFORM(name, opc2, opc3) \
7246 static void glue(gen_, name)(DisasContext *ctx) \
7247 { \
7248 TCGv_ptr ra, rb, rd; \
7249 if (unlikely(!ctx->altivec_enabled)) { \
7250 gen_exception(ctx, POWERPC_EXCP_VPU); \
7251 return; \
7252 } \
7253 ra = gen_avr_ptr(rA(ctx->opcode)); \
7254 rb = gen_avr_ptr(rB(ctx->opcode)); \
7255 rd = gen_avr_ptr(rD(ctx->opcode)); \
7256 gen_helper_##name (rd, ra, rb); \
7257 tcg_temp_free_ptr(ra); \
7258 tcg_temp_free_ptr(rb); \
7259 tcg_temp_free_ptr(rd); \
7260 }
7261
7262 #define GEN_VXFORM_ENV(name, opc2, opc3) \
7263 static void glue(gen_, name)(DisasContext *ctx) \
7264 { \
7265 TCGv_ptr ra, rb, rd; \
7266 if (unlikely(!ctx->altivec_enabled)) { \
7267 gen_exception(ctx, POWERPC_EXCP_VPU); \
7268 return; \
7269 } \
7270 ra = gen_avr_ptr(rA(ctx->opcode)); \
7271 rb = gen_avr_ptr(rB(ctx->opcode)); \
7272 rd = gen_avr_ptr(rD(ctx->opcode)); \
7273 gen_helper_##name(cpu_env, rd, ra, rb); \
7274 tcg_temp_free_ptr(ra); \
7275 tcg_temp_free_ptr(rb); \
7276 tcg_temp_free_ptr(rd); \
7277 }
7278
7279 #define GEN_VXFORM3(name, opc2, opc3) \
7280 static void glue(gen_, name)(DisasContext *ctx) \
7281 { \
7282 TCGv_ptr ra, rb, rc, rd; \
7283 if (unlikely(!ctx->altivec_enabled)) { \
7284 gen_exception(ctx, POWERPC_EXCP_VPU); \
7285 return; \
7286 } \
7287 ra = gen_avr_ptr(rA(ctx->opcode)); \
7288 rb = gen_avr_ptr(rB(ctx->opcode)); \
7289 rc = gen_avr_ptr(rC(ctx->opcode)); \
7290 rd = gen_avr_ptr(rD(ctx->opcode)); \
7291 gen_helper_##name(rd, ra, rb, rc); \
7292 tcg_temp_free_ptr(ra); \
7293 tcg_temp_free_ptr(rb); \
7294 tcg_temp_free_ptr(rc); \
7295 tcg_temp_free_ptr(rd); \
7296 }
7297
7298 /*
7299 * Support for Altivec instruction pairs that use bit 31 (Rc) as
7300 * an opcode bit. In general, these pairs come from different
7301 * versions of the ISA, so we must also support a pair of flags for
7302 * each instruction.
7303 */
7304 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7305 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7306 { \
7307 if ((Rc(ctx->opcode) == 0) && \
7308 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7309 gen_##name0(ctx); \
7310 } else if ((Rc(ctx->opcode) == 1) && \
7311 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7312 gen_##name1(ctx); \
7313 } else { \
7314 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7315 } \
7316 }
7317
7318 GEN_VXFORM(vaddubm, 0, 0);
7319 GEN_VXFORM(vadduhm, 0, 1);
7320 GEN_VXFORM(vadduwm, 0, 2);
7321 GEN_VXFORM(vaddudm, 0, 3);
7322 GEN_VXFORM(vsububm, 0, 16);
7323 GEN_VXFORM(vsubuhm, 0, 17);
7324 GEN_VXFORM(vsubuwm, 0, 18);
7325 GEN_VXFORM(vsubudm, 0, 19);
7326 GEN_VXFORM(vmaxub, 1, 0);
7327 GEN_VXFORM(vmaxuh, 1, 1);
7328 GEN_VXFORM(vmaxuw, 1, 2);
7329 GEN_VXFORM(vmaxud, 1, 3);
7330 GEN_VXFORM(vmaxsb, 1, 4);
7331 GEN_VXFORM(vmaxsh, 1, 5);
7332 GEN_VXFORM(vmaxsw, 1, 6);
7333 GEN_VXFORM(vmaxsd, 1, 7);
7334 GEN_VXFORM(vminub, 1, 8);
7335 GEN_VXFORM(vminuh, 1, 9);
7336 GEN_VXFORM(vminuw, 1, 10);
7337 GEN_VXFORM(vminud, 1, 11);
7338 GEN_VXFORM(vminsb, 1, 12);
7339 GEN_VXFORM(vminsh, 1, 13);
7340 GEN_VXFORM(vminsw, 1, 14);
7341 GEN_VXFORM(vminsd, 1, 15);
7342 GEN_VXFORM(vavgub, 1, 16);
7343 GEN_VXFORM(vavguh, 1, 17);
7344 GEN_VXFORM(vavguw, 1, 18);
7345 GEN_VXFORM(vavgsb, 1, 20);
7346 GEN_VXFORM(vavgsh, 1, 21);
7347 GEN_VXFORM(vavgsw, 1, 22);
7348 GEN_VXFORM(vmrghb, 6, 0);
7349 GEN_VXFORM(vmrghh, 6, 1);
7350 GEN_VXFORM(vmrghw, 6, 2);
7351 GEN_VXFORM(vmrglb, 6, 4);
7352 GEN_VXFORM(vmrglh, 6, 5);
7353 GEN_VXFORM(vmrglw, 6, 6);
7354
7355 static void gen_vmrgew(DisasContext *ctx)
7356 {
7357 TCGv_i64 tmp;
7358 int VT, VA, VB;
7359 if (unlikely(!ctx->altivec_enabled)) {
7360 gen_exception(ctx, POWERPC_EXCP_VPU);
7361 return;
7362 }
7363 VT = rD(ctx->opcode);
7364 VA = rA(ctx->opcode);
7365 VB = rB(ctx->opcode);
7366 tmp = tcg_temp_new_i64();
7367 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7368 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7369 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7370 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7371 tcg_temp_free_i64(tmp);
7372 }
7373
7374 static void gen_vmrgow(DisasContext *ctx)
7375 {
7376 int VT, VA, VB;
7377 if (unlikely(!ctx->altivec_enabled)) {
7378 gen_exception(ctx, POWERPC_EXCP_VPU);
7379 return;
7380 }
7381 VT = rD(ctx->opcode);
7382 VA = rA(ctx->opcode);
7383 VB = rB(ctx->opcode);
7384
7385 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7386 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7387 }
7388
7389 GEN_VXFORM(vmuloub, 4, 0);
7390 GEN_VXFORM(vmulouh, 4, 1);
7391 GEN_VXFORM(vmulouw, 4, 2);
7392 GEN_VXFORM(vmuluwm, 4, 2);
7393 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7394 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7395 GEN_VXFORM(vmulosb, 4, 4);
7396 GEN_VXFORM(vmulosh, 4, 5);
7397 GEN_VXFORM(vmulosw, 4, 6);
7398 GEN_VXFORM(vmuleub, 4, 8);
7399 GEN_VXFORM(vmuleuh, 4, 9);
7400 GEN_VXFORM(vmuleuw, 4, 10);
7401 GEN_VXFORM(vmulesb, 4, 12);
7402 GEN_VXFORM(vmulesh, 4, 13);
7403 GEN_VXFORM(vmulesw, 4, 14);
7404 GEN_VXFORM(vslb, 2, 4);
7405 GEN_VXFORM(vslh, 2, 5);
7406 GEN_VXFORM(vslw, 2, 6);
7407 GEN_VXFORM(vsld, 2, 23);
7408 GEN_VXFORM(vsrb, 2, 8);
7409 GEN_VXFORM(vsrh, 2, 9);
7410 GEN_VXFORM(vsrw, 2, 10);
7411 GEN_VXFORM(vsrd, 2, 27);
7412 GEN_VXFORM(vsrab, 2, 12);
7413 GEN_VXFORM(vsrah, 2, 13);
7414 GEN_VXFORM(vsraw, 2, 14);
7415 GEN_VXFORM(vsrad, 2, 15);
7416 GEN_VXFORM(vslo, 6, 16);
7417 GEN_VXFORM(vsro, 6, 17);
7418 GEN_VXFORM(vaddcuw, 0, 6);
7419 GEN_VXFORM(vsubcuw, 0, 22);
7420 GEN_VXFORM_ENV(vaddubs, 0, 8);
7421 GEN_VXFORM_ENV(vadduhs, 0, 9);
7422 GEN_VXFORM_ENV(vadduws, 0, 10);
7423 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7424 GEN_VXFORM_ENV(vaddshs, 0, 13);
7425 GEN_VXFORM_ENV(vaddsws, 0, 14);
7426 GEN_VXFORM_ENV(vsububs, 0, 24);
7427 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7428 GEN_VXFORM_ENV(vsubuws, 0, 26);
7429 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7430 GEN_VXFORM_ENV(vsubshs, 0, 29);
7431 GEN_VXFORM_ENV(vsubsws, 0, 30);
7432 GEN_VXFORM(vadduqm, 0, 4);
7433 GEN_VXFORM(vaddcuq, 0, 5);
7434 GEN_VXFORM3(vaddeuqm, 30, 0);
7435 GEN_VXFORM3(vaddecuq, 30, 0);
7436 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7437 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7438 GEN_VXFORM(vsubuqm, 0, 20);
7439 GEN_VXFORM(vsubcuq, 0, 21);
7440 GEN_VXFORM3(vsubeuqm, 31, 0);
7441 GEN_VXFORM3(vsubecuq, 31, 0);
7442 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7443 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7444 GEN_VXFORM(vrlb, 2, 0);
7445 GEN_VXFORM(vrlh, 2, 1);
7446 GEN_VXFORM(vrlw, 2, 2);
7447 GEN_VXFORM(vrld, 2, 3);
7448 GEN_VXFORM(vsl, 2, 7);
7449 GEN_VXFORM(vsr, 2, 11);
7450 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7451 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7452 GEN_VXFORM_ENV(vpkudum, 7, 17);
7453 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7454 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7455 GEN_VXFORM_ENV(vpkudus, 7, 19);
7456 GEN_VXFORM_ENV(vpkshus, 7, 4);
7457 GEN_VXFORM_ENV(vpkswus, 7, 5);
7458 GEN_VXFORM_ENV(vpksdus, 7, 21);
7459 GEN_VXFORM_ENV(vpkshss, 7, 6);
7460 GEN_VXFORM_ENV(vpkswss, 7, 7);
7461 GEN_VXFORM_ENV(vpksdss, 7, 23);
7462 GEN_VXFORM(vpkpx, 7, 12);
7463 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7464 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7465 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7466 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7467 GEN_VXFORM_ENV(vsumsws, 4, 30);
7468 GEN_VXFORM_ENV(vaddfp, 5, 0);
7469 GEN_VXFORM_ENV(vsubfp, 5, 1);
7470 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7471 GEN_VXFORM_ENV(vminfp, 5, 17);
7472
7473 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7474 static void glue(gen_, name)(DisasContext *ctx) \
7475 { \
7476 TCGv_ptr ra, rb, rd; \
7477 if (unlikely(!ctx->altivec_enabled)) { \
7478 gen_exception(ctx, POWERPC_EXCP_VPU); \
7479 return; \
7480 } \
7481 ra = gen_avr_ptr(rA(ctx->opcode)); \
7482 rb = gen_avr_ptr(rB(ctx->opcode)); \
7483 rd = gen_avr_ptr(rD(ctx->opcode)); \
7484 gen_helper_##opname(cpu_env, rd, ra, rb); \
7485 tcg_temp_free_ptr(ra); \
7486 tcg_temp_free_ptr(rb); \
7487 tcg_temp_free_ptr(rd); \
7488 }
7489
7490 #define GEN_VXRFORM(name, opc2, opc3) \
7491 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7492 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7493
7494 /*
7495 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7496 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7497 * come from different versions of the ISA, so we must also support a
7498 * pair of flags for each instruction.
7499 */
7500 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7501 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7502 { \
7503 if ((Rc(ctx->opcode) == 0) && \
7504 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7505 if (Rc21(ctx->opcode) == 0) { \
7506 gen_##name0(ctx); \
7507 } else { \
7508 gen_##name0##_(ctx); \
7509 } \
7510 } else if ((Rc(ctx->opcode) == 1) && \
7511 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7512 if (Rc21(ctx->opcode) == 0) { \
7513 gen_##name1(ctx); \
7514 } else { \
7515 gen_##name1##_(ctx); \
7516 } \
7517 } else { \
7518 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7519 } \
7520 }
7521
7522 GEN_VXRFORM(vcmpequb, 3, 0)
7523 GEN_VXRFORM(vcmpequh, 3, 1)
7524 GEN_VXRFORM(vcmpequw, 3, 2)
7525 GEN_VXRFORM(vcmpequd, 3, 3)
7526 GEN_VXRFORM(vcmpgtsb, 3, 12)
7527 GEN_VXRFORM(vcmpgtsh, 3, 13)
7528 GEN_VXRFORM(vcmpgtsw, 3, 14)
7529 GEN_VXRFORM(vcmpgtsd, 3, 15)
7530 GEN_VXRFORM(vcmpgtub, 3, 8)
7531 GEN_VXRFORM(vcmpgtuh, 3, 9)
7532 GEN_VXRFORM(vcmpgtuw, 3, 10)
7533 GEN_VXRFORM(vcmpgtud, 3, 11)
7534 GEN_VXRFORM(vcmpeqfp, 3, 3)
7535 GEN_VXRFORM(vcmpgefp, 3, 7)
7536 GEN_VXRFORM(vcmpgtfp, 3, 11)
7537 GEN_VXRFORM(vcmpbfp, 3, 15)
7538
7539 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7540 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7541 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7542 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7543 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7544 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7545
7546 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7547 static void glue(gen_, name)(DisasContext *ctx) \
7548 { \
7549 TCGv_ptr rd; \
7550 TCGv_i32 simm; \
7551 if (unlikely(!ctx->altivec_enabled)) { \
7552 gen_exception(ctx, POWERPC_EXCP_VPU); \
7553 return; \
7554 } \
7555 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7556 rd = gen_avr_ptr(rD(ctx->opcode)); \
7557 gen_helper_##name (rd, simm); \
7558 tcg_temp_free_i32(simm); \
7559 tcg_temp_free_ptr(rd); \
7560 }
7561
7562 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7563 GEN_VXFORM_SIMM(vspltish, 6, 13);
7564 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7565
7566 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7567 static void glue(gen_, name)(DisasContext *ctx) \
7568 { \
7569 TCGv_ptr rb, rd; \
7570 if (unlikely(!ctx->altivec_enabled)) { \
7571 gen_exception(ctx, POWERPC_EXCP_VPU); \
7572 return; \
7573 } \
7574 rb = gen_avr_ptr(rB(ctx->opcode)); \
7575 rd = gen_avr_ptr(rD(ctx->opcode)); \
7576 gen_helper_##name (rd, rb); \
7577 tcg_temp_free_ptr(rb); \
7578 tcg_temp_free_ptr(rd); \
7579 }
7580
7581 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7582 static void glue(gen_, name)(DisasContext *ctx) \
7583 { \
7584 TCGv_ptr rb, rd; \
7585 \
7586 if (unlikely(!ctx->altivec_enabled)) { \
7587 gen_exception(ctx, POWERPC_EXCP_VPU); \
7588 return; \
7589 } \
7590 rb = gen_avr_ptr(rB(ctx->opcode)); \
7591 rd = gen_avr_ptr(rD(ctx->opcode)); \
7592 gen_helper_##name(cpu_env, rd, rb); \
7593 tcg_temp_free_ptr(rb); \
7594 tcg_temp_free_ptr(rd); \
7595 }
7596
7597 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7598 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7599 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7600 GEN_VXFORM_NOA(vupklsb, 7, 10);
7601 GEN_VXFORM_NOA(vupklsh, 7, 11);
7602 GEN_VXFORM_NOA(vupklsw, 7, 27);
7603 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7604 GEN_VXFORM_NOA(vupklpx, 7, 15);
7605 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7606 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7607 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7608 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7609 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7610 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
7611 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7612 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
7613
7614 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7615 static void glue(gen_, name)(DisasContext *ctx) \
7616 { \
7617 TCGv_ptr rd; \
7618 TCGv_i32 simm; \
7619 if (unlikely(!ctx->altivec_enabled)) { \
7620 gen_exception(ctx, POWERPC_EXCP_VPU); \
7621 return; \
7622 } \
7623 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7624 rd = gen_avr_ptr(rD(ctx->opcode)); \
7625 gen_helper_##name (rd, simm); \
7626 tcg_temp_free_i32(simm); \
7627 tcg_temp_free_ptr(rd); \
7628 }
7629
7630 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7631 static void glue(gen_, name)(DisasContext *ctx) \
7632 { \
7633 TCGv_ptr rb, rd; \
7634 TCGv_i32 uimm; \
7635 if (unlikely(!ctx->altivec_enabled)) { \
7636 gen_exception(ctx, POWERPC_EXCP_VPU); \
7637 return; \
7638 } \
7639 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7640 rb = gen_avr_ptr(rB(ctx->opcode)); \
7641 rd = gen_avr_ptr(rD(ctx->opcode)); \
7642 gen_helper_##name (rd, rb, uimm); \
7643 tcg_temp_free_i32(uimm); \
7644 tcg_temp_free_ptr(rb); \
7645 tcg_temp_free_ptr(rd); \
7646 }
7647
7648 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7649 static void glue(gen_, name)(DisasContext *ctx) \
7650 { \
7651 TCGv_ptr rb, rd; \
7652 TCGv_i32 uimm; \
7653 \
7654 if (unlikely(!ctx->altivec_enabled)) { \
7655 gen_exception(ctx, POWERPC_EXCP_VPU); \
7656 return; \
7657 } \
7658 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7659 rb = gen_avr_ptr(rB(ctx->opcode)); \
7660 rd = gen_avr_ptr(rD(ctx->opcode)); \
7661 gen_helper_##name(cpu_env, rd, rb, uimm); \
7662 tcg_temp_free_i32(uimm); \
7663 tcg_temp_free_ptr(rb); \
7664 tcg_temp_free_ptr(rd); \
7665 }
7666
7667 GEN_VXFORM_UIMM(vspltb, 6, 8);
7668 GEN_VXFORM_UIMM(vsplth, 6, 9);
7669 GEN_VXFORM_UIMM(vspltw, 6, 10);
7670 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7671 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7672 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7673 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7674
7675 static void gen_vsldoi(DisasContext *ctx)
7676 {
7677 TCGv_ptr ra, rb, rd;
7678 TCGv_i32 sh;
7679 if (unlikely(!ctx->altivec_enabled)) {
7680 gen_exception(ctx, POWERPC_EXCP_VPU);
7681 return;
7682 }
7683 ra = gen_avr_ptr(rA(ctx->opcode));
7684 rb = gen_avr_ptr(rB(ctx->opcode));
7685 rd = gen_avr_ptr(rD(ctx->opcode));
7686 sh = tcg_const_i32(VSH(ctx->opcode));
7687 gen_helper_vsldoi (rd, ra, rb, sh);
7688 tcg_temp_free_ptr(ra);
7689 tcg_temp_free_ptr(rb);
7690 tcg_temp_free_ptr(rd);
7691 tcg_temp_free_i32(sh);
7692 }
7693
7694 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7695 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7696 { \
7697 TCGv_ptr ra, rb, rc, rd; \
7698 if (unlikely(!ctx->altivec_enabled)) { \
7699 gen_exception(ctx, POWERPC_EXCP_VPU); \
7700 return; \
7701 } \
7702 ra = gen_avr_ptr(rA(ctx->opcode)); \
7703 rb = gen_avr_ptr(rB(ctx->opcode)); \
7704 rc = gen_avr_ptr(rC(ctx->opcode)); \
7705 rd = gen_avr_ptr(rD(ctx->opcode)); \
7706 if (Rc(ctx->opcode)) { \
7707 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7708 } else { \
7709 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7710 } \
7711 tcg_temp_free_ptr(ra); \
7712 tcg_temp_free_ptr(rb); \
7713 tcg_temp_free_ptr(rc); \
7714 tcg_temp_free_ptr(rd); \
7715 }
7716
7717 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7718
7719 static void gen_vmladduhm(DisasContext *ctx)
7720 {
7721 TCGv_ptr ra, rb, rc, rd;
7722 if (unlikely(!ctx->altivec_enabled)) {
7723 gen_exception(ctx, POWERPC_EXCP_VPU);
7724 return;
7725 }
7726 ra = gen_avr_ptr(rA(ctx->opcode));
7727 rb = gen_avr_ptr(rB(ctx->opcode));
7728 rc = gen_avr_ptr(rC(ctx->opcode));
7729 rd = gen_avr_ptr(rD(ctx->opcode));
7730 gen_helper_vmladduhm(rd, ra, rb, rc);
7731 tcg_temp_free_ptr(ra);
7732 tcg_temp_free_ptr(rb);
7733 tcg_temp_free_ptr(rc);
7734 tcg_temp_free_ptr(rd);
7735 }
7736
7737 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7738 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7739 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7740 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7741 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7742
7743 #if defined(TARGET_PPC64)
7744 static void gen_maddld(DisasContext *ctx)
7745 {
7746 TCGv_i64 t1 = tcg_temp_new_i64();
7747
7748 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7749 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
7750 tcg_temp_free_i64(t1);
7751 }
7752
7753 /* maddhd maddhdu */
7754 static void gen_maddhd_maddhdu(DisasContext *ctx)
7755 {
7756 TCGv_i64 lo = tcg_temp_new_i64();
7757 TCGv_i64 hi = tcg_temp_new_i64();
7758 TCGv_i64 t1 = tcg_temp_new_i64();
7759
7760 if (Rc(ctx->opcode)) {
7761 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
7762 cpu_gpr[rB(ctx->opcode)]);
7763 tcg_gen_movi_i64(t1, 0);
7764 } else {
7765 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
7766 cpu_gpr[rB(ctx->opcode)]);
7767 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
7768 }
7769 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
7770 cpu_gpr[rC(ctx->opcode)], t1);
7771 tcg_temp_free_i64(lo);
7772 tcg_temp_free_i64(hi);
7773 tcg_temp_free_i64(t1);
7774 }
7775 #endif /* defined(TARGET_PPC64) */
7776
7777 GEN_VXFORM_NOA(vclzb, 1, 28)
7778 GEN_VXFORM_NOA(vclzh, 1, 29)
7779 GEN_VXFORM_NOA(vclzw, 1, 30)
7780 GEN_VXFORM_NOA(vclzd, 1, 31)
7781 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7782 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7783 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7784 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7785 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7786 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7787 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7788 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7789 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7790 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7791 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7792 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7793 GEN_VXFORM(vbpermq, 6, 21);
7794 GEN_VXFORM_NOA(vgbbd, 6, 20);
7795 GEN_VXFORM(vpmsumb, 4, 16)
7796 GEN_VXFORM(vpmsumh, 4, 17)
7797 GEN_VXFORM(vpmsumw, 4, 18)
7798 GEN_VXFORM(vpmsumd, 4, 19)
7799
7800 #define GEN_BCD(op) \
7801 static void gen_##op(DisasContext *ctx) \
7802 { \
7803 TCGv_ptr ra, rb, rd; \
7804 TCGv_i32 ps; \
7805 \
7806 if (unlikely(!ctx->altivec_enabled)) { \
7807 gen_exception(ctx, POWERPC_EXCP_VPU); \
7808 return; \
7809 } \
7810 \
7811 ra = gen_avr_ptr(rA(ctx->opcode)); \
7812 rb = gen_avr_ptr(rB(ctx->opcode)); \
7813 rd = gen_avr_ptr(rD(ctx->opcode)); \
7814 \
7815 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7816 \
7817 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7818 \
7819 tcg_temp_free_ptr(ra); \
7820 tcg_temp_free_ptr(rb); \
7821 tcg_temp_free_ptr(rd); \
7822 tcg_temp_free_i32(ps); \
7823 }
7824
7825 GEN_BCD(bcdadd)
7826 GEN_BCD(bcdsub)
7827
7828 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7829 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7830 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7831 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7832 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7833 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7834 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7835 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7836
7837 static void gen_vsbox(DisasContext *ctx)
7838 {
7839 TCGv_ptr ra, rd;
7840 if (unlikely(!ctx->altivec_enabled)) {
7841 gen_exception(ctx, POWERPC_EXCP_VPU);
7842 return;
7843 }
7844 ra = gen_avr_ptr(rA(ctx->opcode));
7845 rd = gen_avr_ptr(rD(ctx->opcode));
7846 gen_helper_vsbox(rd, ra);
7847 tcg_temp_free_ptr(ra);
7848 tcg_temp_free_ptr(rd);
7849 }
7850
7851 GEN_VXFORM(vcipher, 4, 20)
7852 GEN_VXFORM(vcipherlast, 4, 20)
7853 GEN_VXFORM(vncipher, 4, 21)
7854 GEN_VXFORM(vncipherlast, 4, 21)
7855
7856 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7857 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7858 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7859 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7860
7861 #define VSHASIGMA(op) \
7862 static void gen_##op(DisasContext *ctx) \
7863 { \
7864 TCGv_ptr ra, rd; \
7865 TCGv_i32 st_six; \
7866 if (unlikely(!ctx->altivec_enabled)) { \
7867 gen_exception(ctx, POWERPC_EXCP_VPU); \
7868 return; \
7869 } \
7870 ra = gen_avr_ptr(rA(ctx->opcode)); \
7871 rd = gen_avr_ptr(rD(ctx->opcode)); \
7872 st_six = tcg_const_i32(rB(ctx->opcode)); \
7873 gen_helper_##op(rd, ra, st_six); \
7874 tcg_temp_free_ptr(ra); \
7875 tcg_temp_free_ptr(rd); \
7876 tcg_temp_free_i32(st_six); \
7877 }
7878
7879 VSHASIGMA(vshasigmaw)
7880 VSHASIGMA(vshasigmad)
7881
7882 GEN_VXFORM3(vpermxor, 22, 0xFF)
7883 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7884 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7885
7886 /*** VSX extension ***/
7887
7888 static inline TCGv_i64 cpu_vsrh(int n)
7889 {
7890 if (n < 32) {
7891 return cpu_fpr[n];
7892 } else {
7893 return cpu_avrh[n-32];
7894 }
7895 }
7896
7897 static inline TCGv_i64 cpu_vsrl(int n)
7898 {
7899 if (n < 32) {
7900 return cpu_vsr[n];
7901 } else {
7902 return cpu_avrl[n-32];
7903 }
7904 }
7905
7906 #define VSX_LOAD_SCALAR(name, operation) \
7907 static void gen_##name(DisasContext *ctx) \
7908 { \
7909 TCGv EA; \
7910 if (unlikely(!ctx->vsx_enabled)) { \
7911 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7912 return; \
7913 } \
7914 gen_set_access_type(ctx, ACCESS_INT); \
7915 EA = tcg_temp_new(); \
7916 gen_addr_reg_index(ctx, EA); \
7917 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7918 /* NOTE: cpu_vsrl is undefined */ \
7919 tcg_temp_free(EA); \
7920 }
7921
7922 VSX_LOAD_SCALAR(lxsdx, ld64)
7923 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7924 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7925 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7926
7927 static void gen_lxvd2x(DisasContext *ctx)
7928 {
7929 TCGv EA;
7930 if (unlikely(!ctx->vsx_enabled)) {
7931 gen_exception(ctx, POWERPC_EXCP_VSXU);
7932 return;
7933 }
7934 gen_set_access_type(ctx, ACCESS_INT);
7935 EA = tcg_temp_new();
7936 gen_addr_reg_index(ctx, EA);
7937 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7938 tcg_gen_addi_tl(EA, EA, 8);
7939 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7940 tcg_temp_free(EA);
7941 }
7942
7943 static void gen_lxvdsx(DisasContext *ctx)
7944 {
7945 TCGv EA;
7946 if (unlikely(!ctx->vsx_enabled)) {
7947 gen_exception(ctx, POWERPC_EXCP_VSXU);
7948 return;
7949 }
7950 gen_set_access_type(ctx, ACCESS_INT);
7951 EA = tcg_temp_new();
7952 gen_addr_reg_index(ctx, EA);
7953 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7954 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7955 tcg_temp_free(EA);
7956 }
7957
7958 static void gen_lxvw4x(DisasContext *ctx)
7959 {
7960 TCGv EA;
7961 TCGv_i64 tmp;
7962 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7963 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7964 if (unlikely(!ctx->vsx_enabled)) {
7965 gen_exception(ctx, POWERPC_EXCP_VSXU);
7966 return;
7967 }
7968 gen_set_access_type(ctx, ACCESS_INT);
7969 EA = tcg_temp_new();
7970 tmp = tcg_temp_new_i64();
7971
7972 gen_addr_reg_index(ctx, EA);
7973 gen_qemu_ld32u_i64(ctx, tmp, EA);
7974 tcg_gen_addi_tl(EA, EA, 4);
7975 gen_qemu_ld32u_i64(ctx, xth, EA);
7976 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7977
7978 tcg_gen_addi_tl(EA, EA, 4);
7979 gen_qemu_ld32u_i64(ctx, tmp, EA);
7980 tcg_gen_addi_tl(EA, EA, 4);
7981 gen_qemu_ld32u_i64(ctx, xtl, EA);
7982 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7983
7984 tcg_temp_free(EA);
7985 tcg_temp_free_i64(tmp);
7986 }
7987
7988 #define VSX_STORE_SCALAR(name, operation) \
7989 static void gen_##name(DisasContext *ctx) \
7990 { \
7991 TCGv EA; \
7992 if (unlikely(!ctx->vsx_enabled)) { \
7993 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7994 return; \
7995 } \
7996 gen_set_access_type(ctx, ACCESS_INT); \
7997 EA = tcg_temp_new(); \
7998 gen_addr_reg_index(ctx, EA); \
7999 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
8000 tcg_temp_free(EA); \
8001 }
8002
8003 VSX_STORE_SCALAR(stxsdx, st64)
8004 VSX_STORE_SCALAR(stxsiwx, st32_i64)
8005 VSX_STORE_SCALAR(stxsspx, st32fs)
8006
8007 static void gen_stxvd2x(DisasContext *ctx)
8008 {
8009 TCGv EA;
8010 if (unlikely(!ctx->vsx_enabled)) {
8011 gen_exception(ctx, POWERPC_EXCP_VSXU);
8012 return;
8013 }
8014 gen_set_access_type(ctx, ACCESS_INT);
8015 EA = tcg_temp_new();
8016 gen_addr_reg_index(ctx, EA);
8017 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
8018 tcg_gen_addi_tl(EA, EA, 8);
8019 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
8020 tcg_temp_free(EA);
8021 }
8022
8023 static void gen_stxvw4x(DisasContext *ctx)
8024 {
8025 TCGv_i64 tmp;
8026 TCGv EA;
8027 if (unlikely(!ctx->vsx_enabled)) {
8028 gen_exception(ctx, POWERPC_EXCP_VSXU);
8029 return;
8030 }
8031 gen_set_access_type(ctx, ACCESS_INT);
8032 EA = tcg_temp_new();
8033 gen_addr_reg_index(ctx, EA);
8034 tmp = tcg_temp_new_i64();
8035
8036 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
8037 gen_qemu_st32_i64(ctx, tmp, EA);
8038 tcg_gen_addi_tl(EA, EA, 4);
8039 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
8040
8041 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
8042 tcg_gen_addi_tl(EA, EA, 4);
8043 gen_qemu_st32_i64(ctx, tmp, EA);
8044 tcg_gen_addi_tl(EA, EA, 4);
8045 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
8046
8047 tcg_temp_free(EA);
8048 tcg_temp_free_i64(tmp);
8049 }
8050
8051 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
8052 static void gen_##name(DisasContext *ctx) \
8053 { \
8054 if (xS(ctx->opcode) < 32) { \
8055 if (unlikely(!ctx->fpu_enabled)) { \
8056 gen_exception(ctx, POWERPC_EXCP_FPU); \
8057 return; \
8058 } \
8059 } else { \
8060 if (unlikely(!ctx->altivec_enabled)) { \
8061 gen_exception(ctx, POWERPC_EXCP_VPU); \
8062 return; \
8063 } \
8064 } \
8065 TCGv_i64 tmp = tcg_temp_new_i64(); \
8066 tcg_gen_##tcgop1(tmp, source); \
8067 tcg_gen_##tcgop2(target, tmp); \
8068 tcg_temp_free_i64(tmp); \
8069 }
8070
8071
8072 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
8073 cpu_vsrh(xS(ctx->opcode)))
8074 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
8075 cpu_gpr[rA(ctx->opcode)])
8076 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
8077 cpu_gpr[rA(ctx->opcode)])
8078
8079 #if defined(TARGET_PPC64)
8080 #define MV_VSRD(name, target, source) \
8081 static void gen_##name(DisasContext *ctx) \
8082 { \
8083 if (xS(ctx->opcode) < 32) { \
8084 if (unlikely(!ctx->fpu_enabled)) { \
8085 gen_exception(ctx, POWERPC_EXCP_FPU); \
8086 return; \
8087 } \
8088 } else { \
8089 if (unlikely(!ctx->altivec_enabled)) { \
8090 gen_exception(ctx, POWERPC_EXCP_VPU); \
8091 return; \
8092 } \
8093 } \
8094 tcg_gen_mov_i64(target, source); \
8095 }
8096
8097 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
8098 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
8099
8100 #endif
8101
8102 static void gen_xxpermdi(DisasContext *ctx)
8103 {
8104 if (unlikely(!ctx->vsx_enabled)) {
8105 gen_exception(ctx, POWERPC_EXCP_VSXU);
8106 return;
8107 }
8108
8109 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
8110 (xT(ctx->opcode) == xB(ctx->opcode)))) {
8111 TCGv_i64 xh, xl;
8112
8113 xh = tcg_temp_new_i64();
8114 xl = tcg_temp_new_i64();
8115
8116 if ((DM(ctx->opcode) & 2) == 0) {
8117 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
8118 } else {
8119 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
8120 }
8121 if ((DM(ctx->opcode) & 1) == 0) {
8122 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
8123 } else {
8124 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
8125 }
8126
8127 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
8128 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
8129
8130 tcg_temp_free_i64(xh);
8131 tcg_temp_free_i64(xl);
8132 } else {
8133 if ((DM(ctx->opcode) & 2) == 0) {
8134 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
8135 } else {
8136 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
8137 }
8138 if ((DM(ctx->opcode) & 1) == 0) {
8139 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
8140 } else {
8141 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
8142 }
8143 }
8144 }
8145
8146 #define OP_ABS 1
8147 #define OP_NABS 2
8148 #define OP_NEG 3
8149 #define OP_CPSGN 4
8150 #define SGN_MASK_DP 0x8000000000000000ull
8151 #define SGN_MASK_SP 0x8000000080000000ull
8152
8153 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
8154 static void glue(gen_, name)(DisasContext * ctx) \
8155 { \
8156 TCGv_i64 xb, sgm; \
8157 if (unlikely(!ctx->vsx_enabled)) { \
8158 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8159 return; \
8160 } \
8161 xb = tcg_temp_new_i64(); \
8162 sgm = tcg_temp_new_i64(); \
8163 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
8164 tcg_gen_movi_i64(sgm, sgn_mask); \
8165 switch (op) { \
8166 case OP_ABS: { \
8167 tcg_gen_andc_i64(xb, xb, sgm); \
8168 break; \
8169 } \
8170 case OP_NABS: { \
8171 tcg_gen_or_i64(xb, xb, sgm); \
8172 break; \
8173 } \
8174 case OP_NEG: { \
8175 tcg_gen_xor_i64(xb, xb, sgm); \
8176 break; \
8177 } \
8178 case OP_CPSGN: { \
8179 TCGv_i64 xa = tcg_temp_new_i64(); \
8180 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
8181 tcg_gen_and_i64(xa, xa, sgm); \
8182 tcg_gen_andc_i64(xb, xb, sgm); \
8183 tcg_gen_or_i64(xb, xb, xa); \
8184 tcg_temp_free_i64(xa); \
8185 break; \
8186 } \
8187 } \
8188 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
8189 tcg_temp_free_i64(xb); \
8190 tcg_temp_free_i64(sgm); \
8191 }
8192
8193 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
8194 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
8195 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
8196 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
8197
8198 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
8199 static void glue(gen_, name)(DisasContext * ctx) \
8200 { \
8201 TCGv_i64 xbh, xbl, sgm; \
8202 if (unlikely(!ctx->vsx_enabled)) { \
8203 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8204 return; \
8205 } \
8206 xbh = tcg_temp_new_i64(); \
8207 xbl = tcg_temp_new_i64(); \
8208 sgm = tcg_temp_new_i64(); \
8209 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
8210 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
8211 tcg_gen_movi_i64(sgm, sgn_mask); \
8212 switch (op) { \
8213 case OP_ABS: { \
8214 tcg_gen_andc_i64(xbh, xbh, sgm); \
8215 tcg_gen_andc_i64(xbl, xbl, sgm); \
8216 break; \
8217 } \
8218 case OP_NABS: { \
8219 tcg_gen_or_i64(xbh, xbh, sgm); \
8220 tcg_gen_or_i64(xbl, xbl, sgm); \
8221 break; \
8222 } \
8223 case OP_NEG: { \
8224 tcg_gen_xor_i64(xbh, xbh, sgm); \
8225 tcg_gen_xor_i64(xbl, xbl, sgm); \
8226 break; \
8227 } \
8228 case OP_CPSGN: { \
8229 TCGv_i64 xah = tcg_temp_new_i64(); \
8230 TCGv_i64 xal = tcg_temp_new_i64(); \
8231 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
8232 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
8233 tcg_gen_and_i64(xah, xah, sgm); \
8234 tcg_gen_and_i64(xal, xal, sgm); \
8235 tcg_gen_andc_i64(xbh, xbh, sgm); \
8236 tcg_gen_andc_i64(xbl, xbl, sgm); \
8237 tcg_gen_or_i64(xbh, xbh, xah); \
8238 tcg_gen_or_i64(xbl, xbl, xal); \
8239 tcg_temp_free_i64(xah); \
8240 tcg_temp_free_i64(xal); \
8241 break; \
8242 } \
8243 } \
8244 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
8245 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
8246 tcg_temp_free_i64(xbh); \
8247 tcg_temp_free_i64(xbl); \
8248 tcg_temp_free_i64(sgm); \
8249 }
8250
8251 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
8252 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
8253 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
8254 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
8255 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
8256 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
8257 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
8258 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
8259
8260 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
8261 static void gen_##name(DisasContext * ctx) \
8262 { \
8263 TCGv_i32 opc; \
8264 if (unlikely(!ctx->vsx_enabled)) { \
8265 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8266 return; \
8267 } \
8268 /* NIP cannot be restored if the memory exception comes from an helper */ \
8269 gen_update_nip(ctx, ctx->nip - 4); \
8270 opc = tcg_const_i32(ctx->opcode); \
8271 gen_helper_##name(cpu_env, opc); \
8272 tcg_temp_free_i32(opc); \
8273 }
8274
8275 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
8276 static void gen_##name(DisasContext * ctx) \
8277 { \
8278 if (unlikely(!ctx->vsx_enabled)) { \
8279 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8280 return; \
8281 } \
8282 /* NIP cannot be restored if the exception comes */ \
8283 /* from a helper. */ \
8284 gen_update_nip(ctx, ctx->nip - 4); \
8285 \
8286 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
8287 cpu_vsrh(xB(ctx->opcode))); \
8288 }
8289
8290 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
8291 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
8292 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
8293 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
8294 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
8295 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
8296 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
8297 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
8298 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
8299 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
8300 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
8301 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
8302 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
8303 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
8304 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
8305 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
8306 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
8307 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
8308 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
8309 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
8310 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
8311 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
8312 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
8313 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
8314 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
8315 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
8316 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
8317 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
8318 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
8319 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
8320 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
8321 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
8322 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
8323 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
8324 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
8325 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
8326 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
8327
8328 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
8329 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
8330 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
8331 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
8332 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
8333 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
8334 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
8335 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
8336 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
8337 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
8338 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
8339 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
8340 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
8341 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
8342 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
8343 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
8344 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
8345
8346 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
8347 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
8348 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
8349 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
8350 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
8351 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
8352 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
8353 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
8354 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
8355 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8356 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8357 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8358 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8359 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8360 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8361 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8362 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
8363 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8364 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
8365 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8366 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8367 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
8368 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
8369 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8370 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8371 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8372 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8373 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8374 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8375 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8376 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
8377 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8378 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8379 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8380 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8381 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
8382
8383 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8384 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
8385 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
8386 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
8387 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
8388 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
8389 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
8390 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
8391 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
8392 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8393 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8394 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8395 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8396 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8397 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8398 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8399 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
8400 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8401 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
8402 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8403 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8404 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
8405 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
8406 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8407 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8408 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8409 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8410 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8411 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8412 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8413 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
8414 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8415 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8416 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8417 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8418 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
8419
8420 #define VSX_LOGICAL(name, tcg_op) \
8421 static void glue(gen_, name)(DisasContext * ctx) \
8422 { \
8423 if (unlikely(!ctx->vsx_enabled)) { \
8424 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8425 return; \
8426 } \
8427 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8428 cpu_vsrh(xB(ctx->opcode))); \
8429 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8430 cpu_vsrl(xB(ctx->opcode))); \
8431 }
8432
8433 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8434 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8435 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8436 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8437 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8438 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8439 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8440 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8441
8442 #define VSX_XXMRG(name, high) \
8443 static void glue(gen_, name)(DisasContext * ctx) \
8444 { \
8445 TCGv_i64 a0, a1, b0, b1; \
8446 if (unlikely(!ctx->vsx_enabled)) { \
8447 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8448 return; \
8449 } \
8450 a0 = tcg_temp_new_i64(); \
8451 a1 = tcg_temp_new_i64(); \
8452 b0 = tcg_temp_new_i64(); \
8453 b1 = tcg_temp_new_i64(); \
8454 if (high) { \
8455 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8456 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8457 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8458 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8459 } else { \
8460 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8461 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8462 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8463 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8464 } \
8465 tcg_gen_shri_i64(a0, a0, 32); \
8466 tcg_gen_shri_i64(b0, b0, 32); \
8467 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8468 b0, a0, 32, 32); \
8469 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8470 b1, a1, 32, 32); \
8471 tcg_temp_free_i64(a0); \
8472 tcg_temp_free_i64(a1); \
8473 tcg_temp_free_i64(b0); \
8474 tcg_temp_free_i64(b1); \
8475 }
8476
8477 VSX_XXMRG(xxmrghw, 1)
8478 VSX_XXMRG(xxmrglw, 0)
8479
8480 static void gen_xxsel(DisasContext * ctx)
8481 {
8482 TCGv_i64 a, b, c;
8483 if (unlikely(!ctx->vsx_enabled)) {
8484 gen_exception(ctx, POWERPC_EXCP_VSXU);
8485 return;
8486 }
8487 a = tcg_temp_new_i64();
8488 b = tcg_temp_new_i64();
8489 c = tcg_temp_new_i64();
8490
8491 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8492 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8493 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8494
8495 tcg_gen_and_i64(b, b, c);
8496 tcg_gen_andc_i64(a, a, c);
8497 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8498
8499 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8500 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8501 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8502
8503 tcg_gen_and_i64(b, b, c);
8504 tcg_gen_andc_i64(a, a, c);
8505 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8506
8507 tcg_temp_free_i64(a);
8508 tcg_temp_free_i64(b);
8509 tcg_temp_free_i64(c);
8510 }
8511
8512 static void gen_xxspltw(DisasContext *ctx)
8513 {
8514 TCGv_i64 b, b2;
8515 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8516 cpu_vsrl(xB(ctx->opcode)) :
8517 cpu_vsrh(xB(ctx->opcode));
8518
8519 if (unlikely(!ctx->vsx_enabled)) {
8520 gen_exception(ctx, POWERPC_EXCP_VSXU);
8521 return;
8522 }
8523
8524 b = tcg_temp_new_i64();
8525 b2 = tcg_temp_new_i64();
8526
8527 if (UIM(ctx->opcode) & 1) {
8528 tcg_gen_ext32u_i64(b, vsr);
8529 } else {
8530 tcg_gen_shri_i64(b, vsr, 32);
8531 }
8532
8533 tcg_gen_shli_i64(b2, b, 32);
8534 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8535 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8536
8537 tcg_temp_free_i64(b);
8538 tcg_temp_free_i64(b2);
8539 }
8540
8541 static void gen_xxsldwi(DisasContext *ctx)
8542 {
8543 TCGv_i64 xth, xtl;
8544 if (unlikely(!ctx->vsx_enabled)) {
8545 gen_exception(ctx, POWERPC_EXCP_VSXU);
8546 return;
8547 }
8548 xth = tcg_temp_new_i64();
8549 xtl = tcg_temp_new_i64();
8550
8551 switch (SHW(ctx->opcode)) {
8552 case 0: {
8553 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8554 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8555 break;
8556 }
8557 case 1: {
8558 TCGv_i64 t0 = tcg_temp_new_i64();
8559 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8560 tcg_gen_shli_i64(xth, xth, 32);
8561 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8562 tcg_gen_shri_i64(t0, t0, 32);
8563 tcg_gen_or_i64(xth, xth, t0);
8564 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8565 tcg_gen_shli_i64(xtl, xtl, 32);
8566 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8567 tcg_gen_shri_i64(t0, t0, 32);
8568 tcg_gen_or_i64(xtl, xtl, t0);
8569 tcg_temp_free_i64(t0);
8570 break;
8571 }
8572 case 2: {
8573 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8574 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8575 break;
8576 }
8577 case 3: {
8578 TCGv_i64 t0 = tcg_temp_new_i64();
8579 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8580 tcg_gen_shli_i64(xth, xth, 32);
8581 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8582 tcg_gen_shri_i64(t0, t0, 32);
8583 tcg_gen_or_i64(xth, xth, t0);
8584 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8585 tcg_gen_shli_i64(xtl, xtl, 32);
8586 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8587 tcg_gen_shri_i64(t0, t0, 32);
8588 tcg_gen_or_i64(xtl, xtl, t0);
8589 tcg_temp_free_i64(t0);
8590 break;
8591 }
8592 }
8593
8594 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8595 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8596
8597 tcg_temp_free_i64(xth);
8598 tcg_temp_free_i64(xtl);
8599 }
8600
8601 /*** Decimal Floating Point ***/
8602
8603 static inline TCGv_ptr gen_fprp_ptr(int reg)
8604 {
8605 TCGv_ptr r = tcg_temp_new_ptr();
8606 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8607 return r;
8608 }
8609
8610 #define GEN_DFP_T_A_B_Rc(name) \
8611 static void gen_##name(DisasContext *ctx) \
8612 { \
8613 TCGv_ptr rd, ra, rb; \
8614 if (unlikely(!ctx->fpu_enabled)) { \
8615 gen_exception(ctx, POWERPC_EXCP_FPU); \
8616 return; \
8617 } \
8618 gen_update_nip(ctx, ctx->nip - 4); \
8619 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8620 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8621 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8622 gen_helper_##name(cpu_env, rd, ra, rb); \
8623 if (unlikely(Rc(ctx->opcode) != 0)) { \
8624 gen_set_cr1_from_fpscr(ctx); \
8625 } \
8626 tcg_temp_free_ptr(rd); \
8627 tcg_temp_free_ptr(ra); \
8628 tcg_temp_free_ptr(rb); \
8629 }
8630
8631 #define GEN_DFP_BF_A_B(name) \
8632 static void gen_##name(DisasContext *ctx) \
8633 { \
8634 TCGv_ptr ra, rb; \
8635 if (unlikely(!ctx->fpu_enabled)) { \
8636 gen_exception(ctx, POWERPC_EXCP_FPU); \
8637 return; \
8638 } \
8639 gen_update_nip(ctx, ctx->nip - 4); \
8640 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8641 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8642 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8643 cpu_env, ra, rb); \
8644 tcg_temp_free_ptr(ra); \
8645 tcg_temp_free_ptr(rb); \
8646 }
8647
8648 #define GEN_DFP_BF_A_DCM(name) \
8649 static void gen_##name(DisasContext *ctx) \
8650 { \
8651 TCGv_ptr ra; \
8652 TCGv_i32 dcm; \
8653 if (unlikely(!ctx->fpu_enabled)) { \
8654 gen_exception(ctx, POWERPC_EXCP_FPU); \
8655 return; \
8656 } \
8657 gen_update_nip(ctx, ctx->nip - 4); \
8658 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8659 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8660 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8661 cpu_env, ra, dcm); \
8662 tcg_temp_free_ptr(ra); \
8663 tcg_temp_free_i32(dcm); \
8664 }
8665
8666 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8667 static void gen_##name(DisasContext *ctx) \
8668 { \
8669 TCGv_ptr rt, rb; \
8670 TCGv_i32 u32_1, u32_2; \
8671 if (unlikely(!ctx->fpu_enabled)) { \
8672 gen_exception(ctx, POWERPC_EXCP_FPU); \
8673 return; \
8674 } \
8675 gen_update_nip(ctx, ctx->nip - 4); \
8676 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8677 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8678 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8679 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8680 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8681 if (unlikely(Rc(ctx->opcode) != 0)) { \
8682 gen_set_cr1_from_fpscr(ctx); \
8683 } \
8684 tcg_temp_free_ptr(rt); \
8685 tcg_temp_free_ptr(rb); \
8686 tcg_temp_free_i32(u32_1); \
8687 tcg_temp_free_i32(u32_2); \
8688 }
8689
8690 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8691 static void gen_##name(DisasContext *ctx) \
8692 { \
8693 TCGv_ptr rt, ra, rb; \
8694 TCGv_i32 i32; \
8695 if (unlikely(!ctx->fpu_enabled)) { \
8696 gen_exception(ctx, POWERPC_EXCP_FPU); \
8697 return; \
8698 } \
8699 gen_update_nip(ctx, ctx->nip - 4); \
8700 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8701 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8702 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8703 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8704 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8705 if (unlikely(Rc(ctx->opcode) != 0)) { \
8706 gen_set_cr1_from_fpscr(ctx); \
8707 } \
8708 tcg_temp_free_ptr(rt); \
8709 tcg_temp_free_ptr(rb); \
8710 tcg_temp_free_ptr(ra); \
8711 tcg_temp_free_i32(i32); \
8712 }
8713
8714 #define GEN_DFP_T_B_Rc(name) \
8715 static void gen_##name(DisasContext *ctx) \
8716 { \
8717 TCGv_ptr rt, rb; \
8718 if (unlikely(!ctx->fpu_enabled)) { \
8719 gen_exception(ctx, POWERPC_EXCP_FPU); \
8720 return; \
8721 } \
8722 gen_update_nip(ctx, ctx->nip - 4); \
8723 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8724 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8725 gen_helper_##name(cpu_env, rt, rb); \
8726 if (unlikely(Rc(ctx->opcode) != 0)) { \
8727 gen_set_cr1_from_fpscr(ctx); \
8728 } \
8729 tcg_temp_free_ptr(rt); \
8730 tcg_temp_free_ptr(rb); \
8731 }
8732
8733 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8734 static void gen_##name(DisasContext *ctx) \
8735 { \
8736 TCGv_ptr rt, rs; \
8737 TCGv_i32 i32; \
8738 if (unlikely(!ctx->fpu_enabled)) { \
8739 gen_exception(ctx, POWERPC_EXCP_FPU); \
8740 return; \
8741 } \
8742 gen_update_nip(ctx, ctx->nip - 4); \
8743 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8744 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8745 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8746 gen_helper_##name(cpu_env, rt, rs, i32); \
8747 if (unlikely(Rc(ctx->opcode) != 0)) { \
8748 gen_set_cr1_from_fpscr(ctx); \
8749 } \
8750 tcg_temp_free_ptr(rt); \
8751 tcg_temp_free_ptr(rs); \
8752 tcg_temp_free_i32(i32); \
8753 }
8754
8755 GEN_DFP_T_A_B_Rc(dadd)
8756 GEN_DFP_T_A_B_Rc(daddq)
8757 GEN_DFP_T_A_B_Rc(dsub)
8758 GEN_DFP_T_A_B_Rc(dsubq)
8759 GEN_DFP_T_A_B_Rc(dmul)
8760 GEN_DFP_T_A_B_Rc(dmulq)
8761 GEN_DFP_T_A_B_Rc(ddiv)
8762 GEN_DFP_T_A_B_Rc(ddivq)
8763 GEN_DFP_BF_A_B(dcmpu)
8764 GEN_DFP_BF_A_B(dcmpuq)
8765 GEN_DFP_BF_A_B(dcmpo)
8766 GEN_DFP_BF_A_B(dcmpoq)
8767 GEN_DFP_BF_A_DCM(dtstdc)
8768 GEN_DFP_BF_A_DCM(dtstdcq)
8769 GEN_DFP_BF_A_DCM(dtstdg)
8770 GEN_DFP_BF_A_DCM(dtstdgq)
8771 GEN_DFP_BF_A_B(dtstex)
8772 GEN_DFP_BF_A_B(dtstexq)
8773 GEN_DFP_BF_A_B(dtstsf)
8774 GEN_DFP_BF_A_B(dtstsfq)
8775 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8776 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8777 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8778 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8779 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8780 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8781 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8782 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8783 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8784 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8785 GEN_DFP_T_B_Rc(dctdp)
8786 GEN_DFP_T_B_Rc(dctqpq)
8787 GEN_DFP_T_B_Rc(drsp)
8788 GEN_DFP_T_B_Rc(drdpq)
8789 GEN_DFP_T_B_Rc(dcffix)
8790 GEN_DFP_T_B_Rc(dcffixq)
8791 GEN_DFP_T_B_Rc(dctfix)
8792 GEN_DFP_T_B_Rc(dctfixq)
8793 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8794 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8795 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8796 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8797 GEN_DFP_T_B_Rc(dxex)
8798 GEN_DFP_T_B_Rc(dxexq)
8799 GEN_DFP_T_A_B_Rc(diex)
8800 GEN_DFP_T_A_B_Rc(diexq)
8801 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8802 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8803 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8804 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8805
8806 /*** SPE extension ***/
8807 /* Register moves */
8808
8809 static inline void gen_evmra(DisasContext *ctx)
8810 {
8811
8812 if (unlikely(!ctx->spe_enabled)) {
8813 gen_exception(ctx, POWERPC_EXCP_SPEU);
8814 return;
8815 }
8816
8817 TCGv_i64 tmp = tcg_temp_new_i64();
8818
8819 /* tmp := rA_lo + rA_hi << 32 */
8820 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8821
8822 /* spe_acc := tmp */
8823 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8824 tcg_temp_free_i64(tmp);
8825
8826 /* rD := rA */
8827 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8828 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8829 }
8830
8831 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8832 {
8833 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8834 }
8835
8836 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8837 {
8838 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8839 }
8840
8841 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8842 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8843 { \
8844 if (Rc(ctx->opcode)) \
8845 gen_##name1(ctx); \
8846 else \
8847 gen_##name0(ctx); \
8848 }
8849
8850 /* Handler for undefined SPE opcodes */
8851 static inline void gen_speundef(DisasContext *ctx)
8852 {
8853 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8854 }
8855
8856 /* SPE logic */
8857 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8858 static inline void gen_##name(DisasContext *ctx) \
8859 { \
8860 if (unlikely(!ctx->spe_enabled)) { \
8861 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8862 return; \
8863 } \
8864 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8865 cpu_gpr[rB(ctx->opcode)]); \
8866 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8867 cpu_gprh[rB(ctx->opcode)]); \
8868 }
8869
8870 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8871 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8872 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8873 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8874 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8875 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8876 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8877 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8878
8879 /* SPE logic immediate */
8880 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8881 static inline void gen_##name(DisasContext *ctx) \
8882 { \
8883 TCGv_i32 t0; \
8884 if (unlikely(!ctx->spe_enabled)) { \
8885 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8886 return; \
8887 } \
8888 t0 = tcg_temp_new_i32(); \
8889 \
8890 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8891 tcg_opi(t0, t0, rB(ctx->opcode)); \
8892 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8893 \
8894 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8895 tcg_opi(t0, t0, rB(ctx->opcode)); \
8896 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8897 \
8898 tcg_temp_free_i32(t0); \
8899 }
8900 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8901 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8902 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8903 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8904
8905 /* SPE arithmetic */
8906 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8907 static inline void gen_##name(DisasContext *ctx) \
8908 { \
8909 TCGv_i32 t0; \
8910 if (unlikely(!ctx->spe_enabled)) { \
8911 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8912 return; \
8913 } \
8914 t0 = tcg_temp_new_i32(); \
8915 \
8916 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8917 tcg_op(t0, t0); \
8918 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8919 \
8920 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8921 tcg_op(t0, t0); \
8922 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8923 \
8924 tcg_temp_free_i32(t0); \
8925 }
8926
8927 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8928 {
8929 TCGLabel *l1 = gen_new_label();
8930 TCGLabel *l2 = gen_new_label();
8931
8932 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8933 tcg_gen_neg_i32(ret, arg1);
8934 tcg_gen_br(l2);
8935 gen_set_label(l1);
8936 tcg_gen_mov_i32(ret, arg1);
8937 gen_set_label(l2);
8938 }
8939 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8940 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8941 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8942 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8943 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8944 {
8945 tcg_gen_addi_i32(ret, arg1, 0x8000);
8946 tcg_gen_ext16u_i32(ret, ret);
8947 }
8948 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8949 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8950 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8951
8952 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8953 static inline void gen_##name(DisasContext *ctx) \
8954 { \
8955 TCGv_i32 t0, t1; \
8956 if (unlikely(!ctx->spe_enabled)) { \
8957 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8958 return; \
8959 } \
8960 t0 = tcg_temp_new_i32(); \
8961 t1 = tcg_temp_new_i32(); \
8962 \
8963 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8964 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8965 tcg_op(t0, t0, t1); \
8966 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8967 \
8968 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8969 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8970 tcg_op(t0, t0, t1); \
8971 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8972 \
8973 tcg_temp_free_i32(t0); \
8974 tcg_temp_free_i32(t1); \
8975 }
8976
8977 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8978 {
8979 TCGLabel *l1 = gen_new_label();
8980 TCGLabel *l2 = gen_new_label();
8981 TCGv_i32 t0 = tcg_temp_local_new_i32();
8982
8983 /* No error here: 6 bits are used */
8984 tcg_gen_andi_i32(t0, arg2, 0x3F);
8985 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8986 tcg_gen_shr_i32(ret, arg1, t0);
8987 tcg_gen_br(l2);
8988 gen_set_label(l1);
8989 tcg_gen_movi_i32(ret, 0);
8990 gen_set_label(l2);
8991 tcg_temp_free_i32(t0);
8992 }
8993 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8994 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8995 {
8996 TCGLabel *l1 = gen_new_label();
8997 TCGLabel *l2 = gen_new_label();
8998 TCGv_i32 t0 = tcg_temp_local_new_i32();
8999
9000 /* No error here: 6 bits are used */
9001 tcg_gen_andi_i32(t0, arg2, 0x3F);
9002 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
9003 tcg_gen_sar_i32(ret, arg1, t0);
9004 tcg_gen_br(l2);
9005 gen_set_label(l1);
9006 tcg_gen_movi_i32(ret, 0);
9007 gen_set_label(l2);
9008 tcg_temp_free_i32(t0);
9009 }
9010 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
9011 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
9012 {
9013 TCGLabel *l1 = gen_new_label();
9014 TCGLabel *l2 = gen_new_label();
9015 TCGv_i32 t0 = tcg_temp_local_new_i32();
9016
9017 /* No error here: 6 bits are used */
9018 tcg_gen_andi_i32(t0, arg2, 0x3F);
9019 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
9020 tcg_gen_shl_i32(ret, arg1, t0);
9021 tcg_gen_br(l2);
9022 gen_set_label(l1);
9023 tcg_gen_movi_i32(ret, 0);
9024 gen_set_label(l2);
9025 tcg_temp_free_i32(t0);
9026 }
9027 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
9028 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
9029 {
9030 TCGv_i32 t0 = tcg_temp_new_i32();
9031 tcg_gen_andi_i32(t0, arg2, 0x1F);
9032 tcg_gen_rotl_i32(ret, arg1, t0);
9033 tcg_temp_free_i32(t0);
9034 }
9035 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
9036 static inline void gen_evmergehi(DisasContext *ctx)
9037 {
9038 if (unlikely(!ctx->spe_enabled)) {
9039 gen_exception(ctx, POWERPC_EXCP_SPEU);
9040 return;
9041 }
9042 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
9043 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
9044 }
9045 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
9046 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
9047 {
9048 tcg_gen_sub_i32(ret, arg2, arg1);
9049 }
9050 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
9051
9052 /* SPE arithmetic immediate */
9053 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
9054 static inline void gen_##name(DisasContext *ctx) \
9055 { \
9056 TCGv_i32 t0; \
9057 if (unlikely(!ctx->spe_enabled)) { \
9058 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9059 return; \
9060 } \
9061 t0 = tcg_temp_new_i32(); \
9062 \
9063 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9064 tcg_op(t0, t0, rA(ctx->opcode)); \
9065 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9066 \
9067 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
9068 tcg_op(t0, t0, rA(ctx->opcode)); \
9069 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
9070 \
9071 tcg_temp_free_i32(t0); \
9072 }
9073 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
9074 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
9075
9076 /* SPE comparison */
9077 #define GEN_SPEOP_COMP(name, tcg_cond) \
9078 static inline void gen_##name(DisasContext *ctx) \
9079 { \
9080 if (unlikely(!ctx->spe_enabled)) { \
9081 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9082 return; \
9083 } \
9084 TCGLabel *l1 = gen_new_label(); \
9085 TCGLabel *l2 = gen_new_label(); \
9086 TCGLabel *l3 = gen_new_label(); \
9087 TCGLabel *l4 = gen_new_label(); \
9088 \
9089 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
9090 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9091 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
9092 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
9093 \
9094 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
9095 cpu_gpr[rB(ctx->opcode)], l1); \
9096 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
9097 tcg_gen_br(l2); \
9098 gen_set_label(l1); \
9099 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
9100 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
9101 gen_set_label(l2); \
9102 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
9103 cpu_gprh[rB(ctx->opcode)], l3); \
9104 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
9105 ~(CRF_CH | CRF_CH_AND_CL)); \
9106 tcg_gen_br(l4); \
9107 gen_set_label(l3); \
9108 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
9109 CRF_CH | CRF_CH_OR_CL); \
9110 gen_set_label(l4); \
9111 }
9112 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
9113 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
9114 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
9115 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
9116 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
9117
9118 /* SPE misc */
9119 static inline void gen_brinc(DisasContext *ctx)
9120 {
9121 /* Note: brinc is usable even if SPE is disabled */
9122 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
9123 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
9124 }
9125 static inline void gen_evmergelo(DisasContext *ctx)
9126 {
9127 if (unlikely(!ctx->spe_enabled)) {
9128 gen_exception(ctx, POWERPC_EXCP_SPEU);
9129 return;
9130 }
9131 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9132 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
9133 }
9134 static inline void gen_evmergehilo(DisasContext *ctx)
9135 {
9136 if (unlikely(!ctx->spe_enabled)) {
9137 gen_exception(ctx, POWERPC_EXCP_SPEU);
9138 return;
9139 }
9140 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
9141 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
9142 }
9143 static inline void gen_evmergelohi(DisasContext *ctx)
9144 {
9145 if (unlikely(!ctx->spe_enabled)) {
9146 gen_exception(ctx, POWERPC_EXCP_SPEU);
9147 return;
9148 }
9149 if (rD(ctx->opcode) == rA(ctx->opcode)) {
9150 TCGv tmp = tcg_temp_new();
9151 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
9152 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
9153 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
9154 tcg_temp_free(tmp);
9155 } else {
9156 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
9157 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9158 }
9159 }
9160 static inline void gen_evsplati(DisasContext *ctx)
9161 {
9162 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
9163
9164 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
9165 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
9166 }
9167 static inline void gen_evsplatfi(DisasContext *ctx)
9168 {
9169 uint64_t imm = rA(ctx->opcode) << 27;
9170
9171 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
9172 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
9173 }
9174
9175 static inline void gen_evsel(DisasContext *ctx)
9176 {
9177 TCGLabel *l1 = gen_new_label();
9178 TCGLabel *l2 = gen_new_label();
9179 TCGLabel *l3 = gen_new_label();
9180 TCGLabel *l4 = gen_new_label();
9181 TCGv_i32 t0 = tcg_temp_local_new_i32();
9182
9183 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
9184 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
9185 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
9186 tcg_gen_br(l2);
9187 gen_set_label(l1);
9188 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
9189 gen_set_label(l2);
9190 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
9191 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
9192 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9193 tcg_gen_br(l4);
9194 gen_set_label(l3);
9195 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
9196 gen_set_label(l4);
9197 tcg_temp_free_i32(t0);
9198 }
9199
9200 static void gen_evsel0(DisasContext *ctx)
9201 {
9202 gen_evsel(ctx);
9203 }
9204
9205 static void gen_evsel1(DisasContext *ctx)
9206 {
9207 gen_evsel(ctx);
9208 }
9209
9210 static void gen_evsel2(DisasContext *ctx)
9211 {
9212 gen_evsel(ctx);
9213 }
9214
9215 static void gen_evsel3(DisasContext *ctx)
9216 {
9217 gen_evsel(ctx);
9218 }
9219
9220 /* Multiply */
9221
9222 static inline void gen_evmwumi(DisasContext *ctx)
9223 {
9224 TCGv_i64 t0, t1;
9225
9226 if (unlikely(!ctx->spe_enabled)) {
9227 gen_exception(ctx, POWERPC_EXCP_SPEU);
9228 return;
9229 }
9230
9231 t0 = tcg_temp_new_i64();
9232 t1 = tcg_temp_new_i64();
9233
9234 /* t0 := rA; t1 := rB */
9235 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
9236 tcg_gen_ext32u_i64(t0, t0);
9237 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
9238 tcg_gen_ext32u_i64(t1, t1);
9239
9240 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9241
9242 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9243
9244 tcg_temp_free_i64(t0);
9245 tcg_temp_free_i64(t1);
9246 }
9247
9248 static inline void gen_evmwumia(DisasContext *ctx)
9249 {
9250 TCGv_i64 tmp;
9251
9252 if (unlikely(!ctx->spe_enabled)) {
9253 gen_exception(ctx, POWERPC_EXCP_SPEU);
9254 return;
9255 }
9256
9257 gen_evmwumi(ctx); /* rD := rA * rB */
9258
9259 tmp = tcg_temp_new_i64();
9260
9261 /* acc := rD */
9262 gen_load_gpr64(tmp, rD(ctx->opcode));
9263 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
9264 tcg_temp_free_i64(tmp);
9265 }
9266
9267 static inline void gen_evmwumiaa(DisasContext *ctx)
9268 {
9269 TCGv_i64 acc;
9270 TCGv_i64 tmp;
9271
9272 if (unlikely(!ctx->spe_enabled)) {
9273 gen_exception(ctx, POWERPC_EXCP_SPEU);
9274 return;
9275 }
9276
9277 gen_evmwumi(ctx); /* rD := rA * rB */
9278
9279 acc = tcg_temp_new_i64();
9280 tmp = tcg_temp_new_i64();
9281
9282 /* tmp := rD */
9283 gen_load_gpr64(tmp, rD(ctx->opcode));
9284
9285 /* Load acc */
9286 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9287
9288 /* acc := tmp + acc */
9289 tcg_gen_add_i64(acc, acc, tmp);
9290
9291 /* Store acc */
9292 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9293
9294 /* rD := acc */
9295 gen_store_gpr64(rD(ctx->opcode), acc);
9296
9297 tcg_temp_free_i64(acc);
9298 tcg_temp_free_i64(tmp);
9299 }
9300
9301 static inline void gen_evmwsmi(DisasContext *ctx)
9302 {
9303 TCGv_i64 t0, t1;
9304
9305 if (unlikely(!ctx->spe_enabled)) {
9306 gen_exception(ctx, POWERPC_EXCP_SPEU);
9307 return;
9308 }
9309
9310 t0 = tcg_temp_new_i64();
9311 t1 = tcg_temp_new_i64();
9312
9313 /* t0 := rA; t1 := rB */
9314 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
9315 tcg_gen_ext32s_i64(t0, t0);
9316 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
9317 tcg_gen_ext32s_i64(t1, t1);
9318
9319 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9320
9321 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9322
9323 tcg_temp_free_i64(t0);
9324 tcg_temp_free_i64(t1);
9325 }
9326
9327 static inline void gen_evmwsmia(DisasContext *ctx)
9328 {
9329 TCGv_i64 tmp;
9330
9331 gen_evmwsmi(ctx); /* rD := rA * rB */
9332
9333 tmp = tcg_temp_new_i64();
9334
9335 /* acc := rD */
9336 gen_load_gpr64(tmp, rD(ctx->opcode));
9337 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
9338
9339 tcg_temp_free_i64(tmp);
9340 }
9341
9342 static inline void gen_evmwsmiaa(DisasContext *ctx)
9343 {
9344 TCGv_i64 acc = tcg_temp_new_i64();
9345 TCGv_i64 tmp = tcg_temp_new_i64();
9346
9347 gen_evmwsmi(ctx); /* rD := rA * rB */
9348
9349 acc = tcg_temp_new_i64();
9350 tmp = tcg_temp_new_i64();
9351
9352 /* tmp := rD */
9353 gen_load_gpr64(tmp, rD(ctx->opcode));
9354
9355 /* Load acc */
9356 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9357
9358 /* acc := tmp + acc */
9359 tcg_gen_add_i64(acc, acc, tmp);
9360
9361 /* Store acc */
9362 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9363
9364 /* rD := acc */
9365 gen_store_gpr64(rD(ctx->opcode), acc);
9366
9367 tcg_temp_free_i64(acc);
9368 tcg_temp_free_i64(tmp);
9369 }
9370
9371 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9372 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9373 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9374 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9375 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9376 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9377 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9378 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9379 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9380 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9381 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9382 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9383 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9384 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9385 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9386 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9387 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9388 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9389 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9390 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9391 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9392 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9393 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9394 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9395 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9396 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9397 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9398 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9399 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
9400
9401 /* SPE load and stores */
9402 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
9403 {
9404 target_ulong uimm = rB(ctx->opcode);
9405
9406 if (rA(ctx->opcode) == 0) {
9407 tcg_gen_movi_tl(EA, uimm << sh);
9408 } else {
9409 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9410 if (NARROW_MODE(ctx)) {
9411 tcg_gen_ext32u_tl(EA, EA);
9412 }
9413 }
9414 }
9415
9416 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9417 {
9418 TCGv_i64 t0 = tcg_temp_new_i64();
9419 gen_qemu_ld64(ctx, t0, addr);
9420 gen_store_gpr64(rD(ctx->opcode), t0);
9421 tcg_temp_free_i64(t0);
9422 }
9423
9424 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9425 {
9426 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9427 gen_addr_add(ctx, addr, addr, 4);
9428 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9429 }
9430
9431 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9432 {
9433 TCGv t0 = tcg_temp_new();
9434 gen_qemu_ld16u(ctx, t0, addr);
9435 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9436 gen_addr_add(ctx, addr, addr, 2);
9437 gen_qemu_ld16u(ctx, t0, addr);
9438 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9439 gen_addr_add(ctx, addr, addr, 2);
9440 gen_qemu_ld16u(ctx, t0, addr);
9441 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9442 gen_addr_add(ctx, addr, addr, 2);
9443 gen_qemu_ld16u(ctx, t0, addr);
9444 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9445 tcg_temp_free(t0);
9446 }
9447
9448 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9449 {
9450 TCGv t0 = tcg_temp_new();
9451 gen_qemu_ld16u(ctx, t0, addr);
9452 tcg_gen_shli_tl(t0, t0, 16);
9453 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9454 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9455 tcg_temp_free(t0);
9456 }
9457
9458 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9459 {
9460 TCGv t0 = tcg_temp_new();
9461 gen_qemu_ld16u(ctx, t0, addr);
9462 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9463 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9464 tcg_temp_free(t0);
9465 }
9466
9467 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9468 {
9469 TCGv t0 = tcg_temp_new();
9470 gen_qemu_ld16s(ctx, t0, addr);
9471 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9472 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9473 tcg_temp_free(t0);
9474 }
9475
9476 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9477 {
9478 TCGv t0 = tcg_temp_new();
9479 gen_qemu_ld16u(ctx, t0, addr);
9480 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9481 gen_addr_add(ctx, addr, addr, 2);
9482 gen_qemu_ld16u(ctx, t0, addr);
9483 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9484 tcg_temp_free(t0);
9485 }
9486
9487 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9488 {
9489 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9490 gen_addr_add(ctx, addr, addr, 2);
9491 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9492 }
9493
9494 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9495 {
9496 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9497 gen_addr_add(ctx, addr, addr, 2);
9498 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9499 }
9500
9501 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9502 {
9503 TCGv t0 = tcg_temp_new();
9504 gen_qemu_ld32u(ctx, t0, addr);
9505 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9506 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9507 tcg_temp_free(t0);
9508 }
9509
9510 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9511 {
9512 TCGv t0 = tcg_temp_new();
9513 gen_qemu_ld16u(ctx, t0, addr);
9514 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9515 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9516 gen_addr_add(ctx, addr, addr, 2);
9517 gen_qemu_ld16u(ctx, t0, addr);
9518 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9519 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9520 tcg_temp_free(t0);
9521 }
9522
9523 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9524 {
9525 TCGv_i64 t0 = tcg_temp_new_i64();
9526 gen_load_gpr64(t0, rS(ctx->opcode));
9527 gen_qemu_st64(ctx, t0, addr);
9528 tcg_temp_free_i64(t0);
9529 }
9530
9531 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9532 {
9533 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9534 gen_addr_add(ctx, addr, addr, 4);
9535 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9536 }
9537
9538 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9539 {
9540 TCGv t0 = tcg_temp_new();
9541 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9542 gen_qemu_st16(ctx, t0, addr);
9543 gen_addr_add(ctx, addr, addr, 2);
9544 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9545 gen_addr_add(ctx, addr, addr, 2);
9546 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9547 gen_qemu_st16(ctx, t0, addr);
9548 tcg_temp_free(t0);
9549 gen_addr_add(ctx, addr, addr, 2);
9550 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9551 }
9552
9553 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9554 {
9555 TCGv t0 = tcg_temp_new();
9556 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9557 gen_qemu_st16(ctx, t0, addr);
9558 gen_addr_add(ctx, addr, addr, 2);
9559 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9560 gen_qemu_st16(ctx, t0, addr);
9561 tcg_temp_free(t0);
9562 }
9563
9564 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9565 {
9566 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9567 gen_addr_add(ctx, addr, addr, 2);
9568 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9569 }
9570
9571 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9572 {
9573 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9574 }
9575
9576 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9577 {
9578 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9579 }
9580
9581 #define GEN_SPEOP_LDST(name, opc2, sh) \
9582 static void glue(gen_, name)(DisasContext *ctx) \
9583 { \
9584 TCGv t0; \
9585 if (unlikely(!ctx->spe_enabled)) { \
9586 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9587 return; \
9588 } \
9589 gen_set_access_type(ctx, ACCESS_INT); \
9590 t0 = tcg_temp_new(); \
9591 if (Rc(ctx->opcode)) { \
9592 gen_addr_spe_imm_index(ctx, t0, sh); \
9593 } else { \
9594 gen_addr_reg_index(ctx, t0); \
9595 } \
9596 gen_op_##name(ctx, t0); \
9597 tcg_temp_free(t0); \
9598 }
9599
9600 GEN_SPEOP_LDST(evldd, 0x00, 3);
9601 GEN_SPEOP_LDST(evldw, 0x01, 3);
9602 GEN_SPEOP_LDST(evldh, 0x02, 3);
9603 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9604 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9605 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9606 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9607 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9608 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9609 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9610 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9611
9612 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9613 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9614 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9615 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9616 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9617 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9618 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9619
9620 /* Multiply and add - TODO */
9621 #if 0
9622 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9623 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9624 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9625 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9626 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9627 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9628 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9629 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9630 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9631 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9632 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9633 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9634
9635 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9636 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9637 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9638 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9639 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9640 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9641 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9642 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9643 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9644 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9645 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9646 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9647
9648 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9649 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9650 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9651 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9652 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9653
9654 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9655 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9656 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9657 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9658 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9659 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9660 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9661 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9662 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9663 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9664 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9665 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9666
9667 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9668 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9669 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9670 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9671
9672 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9673 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9674 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9675 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9676 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9677 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9678 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9679 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9680 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9681 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9682 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9683 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9684
9685 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9686 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9687 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9688 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9689 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9690 #endif
9691
9692 /*** SPE floating-point extension ***/
9693 #define GEN_SPEFPUOP_CONV_32_32(name) \
9694 static inline void gen_##name(DisasContext *ctx) \
9695 { \
9696 TCGv_i32 t0 = tcg_temp_new_i32(); \
9697 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9698 gen_helper_##name(t0, cpu_env, t0); \
9699 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9700 tcg_temp_free_i32(t0); \
9701 }
9702 #define GEN_SPEFPUOP_CONV_32_64(name) \
9703 static inline void gen_##name(DisasContext *ctx) \
9704 { \
9705 TCGv_i64 t0 = tcg_temp_new_i64(); \
9706 TCGv_i32 t1 = tcg_temp_new_i32(); \
9707 gen_load_gpr64(t0, rB(ctx->opcode)); \
9708 gen_helper_##name(t1, cpu_env, t0); \
9709 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9710 tcg_temp_free_i64(t0); \
9711 tcg_temp_free_i32(t1); \
9712 }
9713 #define GEN_SPEFPUOP_CONV_64_32(name) \
9714 static inline void gen_##name(DisasContext *ctx) \
9715 { \
9716 TCGv_i64 t0 = tcg_temp_new_i64(); \
9717 TCGv_i32 t1 = tcg_temp_new_i32(); \
9718 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9719 gen_helper_##name(t0, cpu_env, t1); \
9720 gen_store_gpr64(rD(ctx->opcode), t0); \
9721 tcg_temp_free_i64(t0); \
9722 tcg_temp_free_i32(t1); \
9723 }
9724 #define GEN_SPEFPUOP_CONV_64_64(name) \
9725 static inline void gen_##name(DisasContext *ctx) \
9726 { \
9727 TCGv_i64 t0 = tcg_temp_new_i64(); \
9728 gen_load_gpr64(t0, rB(ctx->opcode)); \
9729 gen_helper_##name(t0, cpu_env, t0); \
9730 gen_store_gpr64(rD(ctx->opcode), t0); \
9731 tcg_temp_free_i64(t0); \
9732 }
9733 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9734 static inline void gen_##name(DisasContext *ctx) \
9735 { \
9736 TCGv_i32 t0, t1; \
9737 if (unlikely(!ctx->spe_enabled)) { \
9738 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9739 return; \
9740 } \
9741 t0 = tcg_temp_new_i32(); \
9742 t1 = tcg_temp_new_i32(); \
9743 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9744 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9745 gen_helper_##name(t0, cpu_env, t0, t1); \
9746 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9747 \
9748 tcg_temp_free_i32(t0); \
9749 tcg_temp_free_i32(t1); \
9750 }
9751 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9752 static inline void gen_##name(DisasContext *ctx) \
9753 { \
9754 TCGv_i64 t0, t1; \
9755 if (unlikely(!ctx->spe_enabled)) { \
9756 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9757 return; \
9758 } \
9759 t0 = tcg_temp_new_i64(); \
9760 t1 = tcg_temp_new_i64(); \
9761 gen_load_gpr64(t0, rA(ctx->opcode)); \
9762 gen_load_gpr64(t1, rB(ctx->opcode)); \
9763 gen_helper_##name(t0, cpu_env, t0, t1); \
9764 gen_store_gpr64(rD(ctx->opcode), t0); \
9765 tcg_temp_free_i64(t0); \
9766 tcg_temp_free_i64(t1); \
9767 }
9768 #define GEN_SPEFPUOP_COMP_32(name) \
9769 static inline void gen_##name(DisasContext *ctx) \
9770 { \
9771 TCGv_i32 t0, t1; \
9772 if (unlikely(!ctx->spe_enabled)) { \
9773 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9774 return; \
9775 } \
9776 t0 = tcg_temp_new_i32(); \
9777 t1 = tcg_temp_new_i32(); \
9778 \
9779 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9780 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9781 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9782 \
9783 tcg_temp_free_i32(t0); \
9784 tcg_temp_free_i32(t1); \
9785 }
9786 #define GEN_SPEFPUOP_COMP_64(name) \
9787 static inline void gen_##name(DisasContext *ctx) \
9788 { \
9789 TCGv_i64 t0, t1; \
9790 if (unlikely(!ctx->spe_enabled)) { \
9791 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9792 return; \
9793 } \
9794 t0 = tcg_temp_new_i64(); \
9795 t1 = tcg_temp_new_i64(); \
9796 gen_load_gpr64(t0, rA(ctx->opcode)); \
9797 gen_load_gpr64(t1, rB(ctx->opcode)); \
9798 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9799 tcg_temp_free_i64(t0); \
9800 tcg_temp_free_i64(t1); \
9801 }
9802
9803 /* Single precision floating-point vectors operations */
9804 /* Arithmetic */
9805 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9806 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9807 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9808 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9809 static inline void gen_evfsabs(DisasContext *ctx)
9810 {
9811 if (unlikely(!ctx->spe_enabled)) {
9812 gen_exception(ctx, POWERPC_EXCP_SPEU);
9813 return;
9814 }
9815 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9816 ~0x80000000);
9817 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9818 ~0x80000000);
9819 }
9820 static inline void gen_evfsnabs(DisasContext *ctx)
9821 {
9822 if (unlikely(!ctx->spe_enabled)) {
9823 gen_exception(ctx, POWERPC_EXCP_SPEU);
9824 return;
9825 }
9826 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9827 0x80000000);
9828 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9829 0x80000000);
9830 }
9831 static inline void gen_evfsneg(DisasContext *ctx)
9832 {
9833 if (unlikely(!ctx->spe_enabled)) {
9834 gen_exception(ctx, POWERPC_EXCP_SPEU);
9835 return;
9836 }
9837 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9838 0x80000000);
9839 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9840 0x80000000);
9841 }
9842
9843 /* Conversion */
9844 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9845 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9846 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9847 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9848 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9849 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9850 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9851 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9852 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9853 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9854
9855 /* Comparison */
9856 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9857 GEN_SPEFPUOP_COMP_64(evfscmplt);
9858 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9859 GEN_SPEFPUOP_COMP_64(evfststgt);
9860 GEN_SPEFPUOP_COMP_64(evfststlt);
9861 GEN_SPEFPUOP_COMP_64(evfststeq);
9862
9863 /* Opcodes definitions */
9864 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9865 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9866 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9867 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9868 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9869 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9870 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9871 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9872 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9873 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9874 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9875 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9876 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9877 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9878
9879 /* Single precision floating-point operations */
9880 /* Arithmetic */
9881 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9882 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9883 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9884 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9885 static inline void gen_efsabs(DisasContext *ctx)
9886 {
9887 if (unlikely(!ctx->spe_enabled)) {
9888 gen_exception(ctx, POWERPC_EXCP_SPEU);
9889 return;
9890 }
9891 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9892 }
9893 static inline void gen_efsnabs(DisasContext *ctx)
9894 {
9895 if (unlikely(!ctx->spe_enabled)) {
9896 gen_exception(ctx, POWERPC_EXCP_SPEU);
9897 return;
9898 }
9899 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9900 }
9901 static inline void gen_efsneg(DisasContext *ctx)
9902 {
9903 if (unlikely(!ctx->spe_enabled)) {
9904 gen_exception(ctx, POWERPC_EXCP_SPEU);
9905 return;
9906 }
9907 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9908 }
9909
9910 /* Conversion */
9911 GEN_SPEFPUOP_CONV_32_32(efscfui);
9912 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9913 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9914 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9915 GEN_SPEFPUOP_CONV_32_32(efsctui);
9916 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9917 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9918 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9919 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9920 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9921 GEN_SPEFPUOP_CONV_32_64(efscfd);
9922
9923 /* Comparison */
9924 GEN_SPEFPUOP_COMP_32(efscmpgt);
9925 GEN_SPEFPUOP_COMP_32(efscmplt);
9926 GEN_SPEFPUOP_COMP_32(efscmpeq);
9927 GEN_SPEFPUOP_COMP_32(efststgt);
9928 GEN_SPEFPUOP_COMP_32(efststlt);
9929 GEN_SPEFPUOP_COMP_32(efststeq);
9930
9931 /* Opcodes definitions */
9932 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9933 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9934 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9935 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9936 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9937 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9938 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9939 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9940 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9941 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9942 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9943 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9944 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9945 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9946
9947 /* Double precision floating-point operations */
9948 /* Arithmetic */
9949 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9950 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9951 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9952 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9953 static inline void gen_efdabs(DisasContext *ctx)
9954 {
9955 if (unlikely(!ctx->spe_enabled)) {
9956 gen_exception(ctx, POWERPC_EXCP_SPEU);
9957 return;
9958 }
9959 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9960 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9961 ~0x80000000);
9962 }
9963 static inline void gen_efdnabs(DisasContext *ctx)
9964 {
9965 if (unlikely(!ctx->spe_enabled)) {
9966 gen_exception(ctx, POWERPC_EXCP_SPEU);
9967 return;
9968 }
9969 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9970 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9971 0x80000000);
9972 }
9973 static inline void gen_efdneg(DisasContext *ctx)
9974 {
9975 if (unlikely(!ctx->spe_enabled)) {
9976 gen_exception(ctx, POWERPC_EXCP_SPEU);
9977 return;
9978 }
9979 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9980 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9981 0x80000000);
9982 }
9983
9984 /* Conversion */
9985 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9986 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9987 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9988 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9989 GEN_SPEFPUOP_CONV_32_64(efdctui);
9990 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9991 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9992 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9993 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9994 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9995 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9996 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9997 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9998 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9999 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
10000
10001 /* Comparison */
10002 GEN_SPEFPUOP_COMP_64(efdcmpgt);
10003 GEN_SPEFPUOP_COMP_64(efdcmplt);
10004 GEN_SPEFPUOP_COMP_64(efdcmpeq);
10005 GEN_SPEFPUOP_COMP_64(efdtstgt);
10006 GEN_SPEFPUOP_COMP_64(efdtstlt);
10007 GEN_SPEFPUOP_COMP_64(efdtsteq);
10008
10009 /* Opcodes definitions */
10010 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
10011 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
10012 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
10013 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
10014 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
10015 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
10016 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
10017 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
10018 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
10019 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
10020 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
10021 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
10022 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
10023 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
10024 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
10025 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
10026
10027 static void gen_tbegin(DisasContext *ctx)
10028 {
10029 if (unlikely(!ctx->tm_enabled)) {
10030 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
10031 return;
10032 }
10033 gen_helper_tbegin(cpu_env);
10034 }
10035
10036 #define GEN_TM_NOOP(name) \
10037 static inline void gen_##name(DisasContext *ctx) \
10038 { \
10039 if (unlikely(!ctx->tm_enabled)) { \
10040 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
10041 return; \
10042 } \
10043 /* Because tbegin always fails in QEMU, these user \
10044 * space instructions all have a simple implementation: \
10045 * \
10046 * CR[0] = 0b0 || MSR[TS] || 0b0 \
10047 * = 0b0 || 0b00 || 0b0 \
10048 */ \
10049 tcg_gen_movi_i32(cpu_crf[0], 0); \
10050 }
10051
10052 GEN_TM_NOOP(tend);
10053 GEN_TM_NOOP(tabort);
10054 GEN_TM_NOOP(tabortwc);
10055 GEN_TM_NOOP(tabortwci);
10056 GEN_TM_NOOP(tabortdc);
10057 GEN_TM_NOOP(tabortdci);
10058 GEN_TM_NOOP(tsr);
10059
10060 static void gen_tcheck(DisasContext *ctx)
10061 {
10062 if (unlikely(!ctx->tm_enabled)) {
10063 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
10064 return;
10065 }
10066 /* Because tbegin always fails, the tcheck implementation
10067 * is simple:
10068 *
10069 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
10070 * = 0b1 || 0b00 || 0b0
10071 */
10072 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
10073 }
10074
10075 #if defined(CONFIG_USER_ONLY)
10076 #define GEN_TM_PRIV_NOOP(name) \
10077 static inline void gen_##name(DisasContext *ctx) \
10078 { \
10079 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
10080 }
10081
10082 #else
10083
10084 #define GEN_TM_PRIV_NOOP(name) \
10085 static inline void gen_##name(DisasContext *ctx) \
10086 { \
10087 CHK_SV; \
10088 if (unlikely(!ctx->tm_enabled)) { \
10089 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
10090 return; \
10091 } \
10092 /* Because tbegin always fails, the implementation is \
10093 * simple: \
10094 * \
10095 * CR[0] = 0b0 || MSR[TS] || 0b0 \
10096 * = 0b0 || 0b00 | 0b0 \
10097 */ \
10098 tcg_gen_movi_i32(cpu_crf[0], 0); \
10099 }
10100
10101 #endif
10102
10103 GEN_TM_PRIV_NOOP(treclaim);
10104 GEN_TM_PRIV_NOOP(trechkpt);
10105
10106 static opcode_t opcodes[] = {
10107 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
10108 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
10109 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
10110 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
10111 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
10112 #if defined(TARGET_PPC64)
10113 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
10114 #endif
10115 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
10116 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
10117 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
10118 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10119 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10120 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10121 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10122 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
10123 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
10124 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
10125 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
10126 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
10127 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10128 #if defined(TARGET_PPC64)
10129 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
10130 #endif
10131 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
10132 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
10133 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10134 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10135 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10136 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
10137 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
10138 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
10139 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
10140 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10141 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10142 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10143 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10144 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
10145 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
10146 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
10147 #if defined(TARGET_PPC64)
10148 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
10149 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
10150 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
10151 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
10152 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
10153 #endif
10154 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10155 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10156 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10157 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
10158 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
10159 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
10160 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
10161 #if defined(TARGET_PPC64)
10162 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
10163 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
10164 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
10165 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
10166 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
10167 #endif
10168 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
10169 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
10170 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
10171 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
10172 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
10173 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
10174 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
10175 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
10176 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
10177 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
10178 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
10179 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
10180 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
10181 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
10182 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
10183 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
10184 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
10185 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
10186 #if defined(TARGET_PPC64)
10187 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
10188 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
10189 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
10190 #endif
10191 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10192 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10193 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
10194 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
10195 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
10196 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
10197 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
10198 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
10199 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
10200 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
10201 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
10202 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
10203 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
10204 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
10205 #if defined(TARGET_PPC64)
10206 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
10207 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
10208 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
10209 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
10210 #endif
10211 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
10212 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
10213 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
10214 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
10215 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
10216 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
10217 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
10218 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
10219 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
10220 #if defined(TARGET_PPC64)
10221 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
10222 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
10223 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
10224 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
10225 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
10226 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
10227 #endif
10228 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
10229 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
10230 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
10231 #if defined(TARGET_PPC64)
10232 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
10233 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
10234 #endif
10235 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
10236 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
10237 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
10238 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
10239 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
10240 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
10241 #if defined(TARGET_PPC64)
10242 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
10243 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
10244 #endif
10245 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
10246 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
10247 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
10248 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
10249 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
10250 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
10251 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
10252 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
10253 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
10254 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
10255 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
10256 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
10257 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
10258 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
10259 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
10260 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
10261 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
10262 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
10263 #if defined(TARGET_PPC64)
10264 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
10265 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
10266 PPC_SEGMENT_64B),
10267 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
10268 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
10269 PPC_SEGMENT_64B),
10270 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
10271 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
10272 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
10273 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
10274 #endif
10275 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
10276 /* XXX Those instructions will need to be handled differently for
10277 * different ISA versions */
10278 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
10279 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
10280 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
10281 #if defined(TARGET_PPC64)
10282 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
10283 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
10284 #endif
10285 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
10286 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
10287 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
10288 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
10289 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
10290 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
10291 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
10292 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
10293 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
10294 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
10295 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
10296 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
10297 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
10298 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
10299 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
10300 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
10301 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
10302 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
10303 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
10304 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
10305 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
10306 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
10307 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
10308 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
10309 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
10310 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
10311 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
10312 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
10313 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
10314 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
10315 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
10316 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
10317 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
10318 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
10319 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
10320 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
10321 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
10322 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
10323 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
10324 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
10325 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
10326 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
10327 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
10328 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
10329 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
10330 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
10331 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
10332 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
10333 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
10334 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10335 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10336 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
10337 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
10338 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10339 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10340 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
10341 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
10342 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
10343 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
10344 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
10345 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
10346 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
10347 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
10348 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
10349 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
10350 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
10351 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
10352 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
10353 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
10354 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
10355 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
10356 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
10357 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
10358 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
10359 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
10360 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
10361 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10362 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10363 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10364 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
10365 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10366 PPC_NONE, PPC2_BOOKE206),
10367 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10368 PPC_NONE, PPC2_BOOKE206),
10369 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10370 PPC_NONE, PPC2_BOOKE206),
10371 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10372 PPC_NONE, PPC2_BOOKE206),
10373 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10374 PPC_NONE, PPC2_BOOKE206),
10375 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10376 PPC_NONE, PPC2_PRCNTL),
10377 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10378 PPC_NONE, PPC2_PRCNTL),
10379 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
10380 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
10381 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
10382 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10383 PPC_BOOKE, PPC2_BOOKE206),
10384 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
10385 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10386 PPC_BOOKE, PPC2_BOOKE206),
10387 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10388 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10389 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10390 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
10391 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10392 #if defined(TARGET_PPC64)
10393 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
10394 PPC2_ISA300),
10395 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
10396 #endif
10397 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10398 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10399 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10400 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10401
10402 #undef GEN_INT_ARITH_ADD
10403 #undef GEN_INT_ARITH_ADD_CONST
10404 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10405 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10406 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10407 add_ca, compute_ca, compute_ov) \
10408 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10409 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10410 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10411 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10412 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10413 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10414 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10415 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10416 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10417 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10418 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10419
10420 #undef GEN_INT_ARITH_DIVW
10421 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10422 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10423 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10424 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10425 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10426 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
10427 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10428 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10429 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10430 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10431 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
10432 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
10433
10434 #if defined(TARGET_PPC64)
10435 #undef GEN_INT_ARITH_DIVD
10436 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10437 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10438 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10439 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10440 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10441 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10442
10443 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10444 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10445 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10446 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10447 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
10448 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
10449
10450 #undef GEN_INT_ARITH_MUL_HELPER
10451 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10452 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10453 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10454 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10455 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10456 #endif
10457
10458 #undef GEN_INT_ARITH_SUBF
10459 #undef GEN_INT_ARITH_SUBF_CONST
10460 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10461 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10462 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10463 add_ca, compute_ca, compute_ov) \
10464 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10465 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10466 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10467 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10468 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10469 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10470 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10471 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10472 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10473 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10474 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10475
10476 #undef GEN_LOGICAL1
10477 #undef GEN_LOGICAL2
10478 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10479 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10480 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10481 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10482 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10483 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10484 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10485 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10486 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10487 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10488 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10489 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10490 #if defined(TARGET_PPC64)
10491 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10492 #endif
10493
10494 #if defined(TARGET_PPC64)
10495 #undef GEN_PPC64_R2
10496 #undef GEN_PPC64_R4
10497 #define GEN_PPC64_R2(name, opc1, opc2) \
10498 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10499 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10500 PPC_64B)
10501 #define GEN_PPC64_R4(name, opc1, opc2) \
10502 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10503 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10504 PPC_64B), \
10505 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10506 PPC_64B), \
10507 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10508 PPC_64B)
10509 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10510 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10511 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10512 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10513 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10514 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10515 #endif
10516
10517 #undef _GEN_FLOAT_ACB
10518 #undef GEN_FLOAT_ACB
10519 #undef _GEN_FLOAT_AB
10520 #undef GEN_FLOAT_AB
10521 #undef _GEN_FLOAT_AC
10522 #undef GEN_FLOAT_AC
10523 #undef GEN_FLOAT_B
10524 #undef GEN_FLOAT_BS
10525 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10526 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10527 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10528 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10529 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10530 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10531 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10532 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10533 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10534 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10535 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10536 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10537 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10538 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10539 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10540 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10541 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10542 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10543 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10544
10545 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10546 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10547 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10548 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10549 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10550 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10551 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10552 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10553 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10554 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10555 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10556 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10557 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10558 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10559 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10560 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10561 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10562 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10563 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10564 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10565 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10566 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10567 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10568 GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10569 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10570 GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10571 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10572 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10573 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10574 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10575 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10576
10577 #undef GEN_LD
10578 #undef GEN_LDU
10579 #undef GEN_LDUX
10580 #undef GEN_LDX_E
10581 #undef GEN_LDS
10582 #define GEN_LD(name, ldop, opc, type) \
10583 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10584 #define GEN_LDU(name, ldop, opc, type) \
10585 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10586 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10587 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10588 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
10589 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10590 #define GEN_LDS(name, ldop, op, type) \
10591 GEN_LD(name, ldop, op | 0x20, type) \
10592 GEN_LDU(name, ldop, op | 0x21, type) \
10593 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10594 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10595
10596 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10597 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10598 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10599 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10600 #if defined(TARGET_PPC64)
10601 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10602 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10603 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10604 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10605 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
10606
10607 /* HV/P7 and later only */
10608 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
10609 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
10610 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
10611 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
10612 #endif
10613 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10614 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10615
10616 #undef GEN_ST
10617 #undef GEN_STU
10618 #undef GEN_STUX
10619 #undef GEN_STX_E
10620 #undef GEN_STS
10621 #define GEN_ST(name, stop, opc, type) \
10622 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10623 #define GEN_STU(name, stop, opc, type) \
10624 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10625 #define GEN_STUX(name, stop, opc2, opc3, type) \
10626 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10627 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
10628 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10629 #define GEN_STS(name, stop, op, type) \
10630 GEN_ST(name, stop, op | 0x20, type) \
10631 GEN_STU(name, stop, op | 0x21, type) \
10632 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10633 GEN_STX(name, stop, 0x17, op | 0x00, type)
10634
10635 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10636 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10637 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10638 #if defined(TARGET_PPC64)
10639 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10640 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10641 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
10642 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
10643 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
10644 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
10645 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
10646 #endif
10647 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10648 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10649
10650 #undef GEN_LDF
10651 #undef GEN_LDUF
10652 #undef GEN_LDUXF
10653 #undef GEN_LDXF
10654 #undef GEN_LDFS
10655 #define GEN_LDF(name, ldop, opc, type) \
10656 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10657 #define GEN_LDUF(name, ldop, opc, type) \
10658 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10659 #define GEN_LDUXF(name, ldop, opc, type) \
10660 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10661 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10662 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10663 #define GEN_LDFS(name, ldop, op, type) \
10664 GEN_LDF(name, ldop, op | 0x20, type) \
10665 GEN_LDUF(name, ldop, op | 0x21, type) \
10666 GEN_LDUXF(name, ldop, op | 0x01, type) \
10667 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10668
10669 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10670 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10671 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10672 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10673 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10674 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10675
10676 #undef GEN_STF
10677 #undef GEN_STUF
10678 #undef GEN_STUXF
10679 #undef GEN_STXF
10680 #undef GEN_STFS
10681 #define GEN_STF(name, stop, opc, type) \
10682 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10683 #define GEN_STUF(name, stop, opc, type) \
10684 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10685 #define GEN_STUXF(name, stop, opc, type) \
10686 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10687 #define GEN_STXF(name, stop, opc2, opc3, type) \
10688 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10689 #define GEN_STFS(name, stop, op, type) \
10690 GEN_STF(name, stop, op | 0x20, type) \
10691 GEN_STUF(name, stop, op | 0x21, type) \
10692 GEN_STUXF(name, stop, op | 0x01, type) \
10693 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10694
10695 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10696 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10697 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10698 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10699 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10700
10701 #undef GEN_CRLOGIC
10702 #define GEN_CRLOGIC(name, tcg_op, opc) \
10703 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10704 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10705 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10706 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10707 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10708 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10709 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10710 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10711 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10712
10713 #undef GEN_MAC_HANDLER
10714 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10715 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10716 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10717 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10718 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10719 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10720 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10721 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10722 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10723 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10724 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10725 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10726 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10727 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10728 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10729 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10730 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10731 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10732 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10733 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10734 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10735 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10736 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10737 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10738 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10739 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10740 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10741 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10742 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10743 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10744 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10745 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10746 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10747 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10748 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10749 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10750 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10751 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10752 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10753 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10754 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10755 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10756 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10757 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10758
10759 #undef GEN_VR_LDX
10760 #undef GEN_VR_STX
10761 #undef GEN_VR_LVE
10762 #undef GEN_VR_STVE
10763 #define GEN_VR_LDX(name, opc2, opc3) \
10764 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10765 #define GEN_VR_STX(name, opc2, opc3) \
10766 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10767 #define GEN_VR_LVE(name, opc2, opc3) \
10768 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10769 #define GEN_VR_STVE(name, opc2, opc3) \
10770 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10771 GEN_VR_LDX(lvx, 0x07, 0x03),
10772 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10773 GEN_VR_LVE(bx, 0x07, 0x00),
10774 GEN_VR_LVE(hx, 0x07, 0x01),
10775 GEN_VR_LVE(wx, 0x07, 0x02),
10776 GEN_VR_STX(svx, 0x07, 0x07),
10777 GEN_VR_STX(svxl, 0x07, 0x0F),
10778 GEN_VR_STVE(bx, 0x07, 0x04),
10779 GEN_VR_STVE(hx, 0x07, 0x05),
10780 GEN_VR_STVE(wx, 0x07, 0x06),
10781
10782 #undef GEN_VX_LOGICAL
10783 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10784 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10785
10786 #undef GEN_VX_LOGICAL_207
10787 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10788 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10789
10790 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10791 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10792 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10793 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10794 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10795 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10796 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10797 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10798
10799 #undef GEN_VXFORM
10800 #define GEN_VXFORM(name, opc2, opc3) \
10801 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10802
10803 #undef GEN_VXFORM_207
10804 #define GEN_VXFORM_207(name, opc2, opc3) \
10805 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10806
10807 #undef GEN_VXFORM_DUAL
10808 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10809 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10810
10811 #undef GEN_VXRFORM_DUAL
10812 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10813 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10814 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10815
10816 GEN_VXFORM(vaddubm, 0, 0),
10817 GEN_VXFORM(vadduhm, 0, 1),
10818 GEN_VXFORM(vadduwm, 0, 2),
10819 GEN_VXFORM_207(vaddudm, 0, 3),
10820 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10821 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10822 GEN_VXFORM(vsubuwm, 0, 18),
10823 GEN_VXFORM_207(vsubudm, 0, 19),
10824 GEN_VXFORM(vmaxub, 1, 0),
10825 GEN_VXFORM(vmaxuh, 1, 1),
10826 GEN_VXFORM(vmaxuw, 1, 2),
10827 GEN_VXFORM_207(vmaxud, 1, 3),
10828 GEN_VXFORM(vmaxsb, 1, 4),
10829 GEN_VXFORM(vmaxsh, 1, 5),
10830 GEN_VXFORM(vmaxsw, 1, 6),
10831 GEN_VXFORM_207(vmaxsd, 1, 7),
10832 GEN_VXFORM(vminub, 1, 8),
10833 GEN_VXFORM(vminuh, 1, 9),
10834 GEN_VXFORM(vminuw, 1, 10),
10835 GEN_VXFORM_207(vminud, 1, 11),
10836 GEN_VXFORM(vminsb, 1, 12),
10837 GEN_VXFORM(vminsh, 1, 13),
10838 GEN_VXFORM(vminsw, 1, 14),
10839 GEN_VXFORM_207(vminsd, 1, 15),
10840 GEN_VXFORM(vavgub, 1, 16),
10841 GEN_VXFORM(vavguh, 1, 17),
10842 GEN_VXFORM(vavguw, 1, 18),
10843 GEN_VXFORM(vavgsb, 1, 20),
10844 GEN_VXFORM(vavgsh, 1, 21),
10845 GEN_VXFORM(vavgsw, 1, 22),
10846 GEN_VXFORM(vmrghb, 6, 0),
10847 GEN_VXFORM(vmrghh, 6, 1),
10848 GEN_VXFORM(vmrghw, 6, 2),
10849 GEN_VXFORM(vmrglb, 6, 4),
10850 GEN_VXFORM(vmrglh, 6, 5),
10851 GEN_VXFORM(vmrglw, 6, 6),
10852 GEN_VXFORM_207(vmrgew, 6, 30),
10853 GEN_VXFORM_207(vmrgow, 6, 26),
10854 GEN_VXFORM(vmuloub, 4, 0),
10855 GEN_VXFORM(vmulouh, 4, 1),
10856 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10857 GEN_VXFORM(vmulosb, 4, 4),
10858 GEN_VXFORM(vmulosh, 4, 5),
10859 GEN_VXFORM_207(vmulosw, 4, 6),
10860 GEN_VXFORM(vmuleub, 4, 8),
10861 GEN_VXFORM(vmuleuh, 4, 9),
10862 GEN_VXFORM_207(vmuleuw, 4, 10),
10863 GEN_VXFORM(vmulesb, 4, 12),
10864 GEN_VXFORM(vmulesh, 4, 13),
10865 GEN_VXFORM_207(vmulesw, 4, 14),
10866 GEN_VXFORM(vslb, 2, 4),
10867 GEN_VXFORM(vslh, 2, 5),
10868 GEN_VXFORM(vslw, 2, 6),
10869 GEN_VXFORM_207(vsld, 2, 23),
10870 GEN_VXFORM(vsrb, 2, 8),
10871 GEN_VXFORM(vsrh, 2, 9),
10872 GEN_VXFORM(vsrw, 2, 10),
10873 GEN_VXFORM_207(vsrd, 2, 27),
10874 GEN_VXFORM(vsrab, 2, 12),
10875 GEN_VXFORM(vsrah, 2, 13),
10876 GEN_VXFORM(vsraw, 2, 14),
10877 GEN_VXFORM_207(vsrad, 2, 15),
10878 GEN_VXFORM(vslo, 6, 16),
10879 GEN_VXFORM(vsro, 6, 17),
10880 GEN_VXFORM(vaddcuw, 0, 6),
10881 GEN_VXFORM(vsubcuw, 0, 22),
10882 GEN_VXFORM(vaddubs, 0, 8),
10883 GEN_VXFORM(vadduhs, 0, 9),
10884 GEN_VXFORM(vadduws, 0, 10),
10885 GEN_VXFORM(vaddsbs, 0, 12),
10886 GEN_VXFORM(vaddshs, 0, 13),
10887 GEN_VXFORM(vaddsws, 0, 14),
10888 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10889 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10890 GEN_VXFORM(vsubuws, 0, 26),
10891 GEN_VXFORM(vsubsbs, 0, 28),
10892 GEN_VXFORM(vsubshs, 0, 29),
10893 GEN_VXFORM(vsubsws, 0, 30),
10894 GEN_VXFORM_207(vadduqm, 0, 4),
10895 GEN_VXFORM_207(vaddcuq, 0, 5),
10896 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10897 GEN_VXFORM_207(vsubuqm, 0, 20),
10898 GEN_VXFORM_207(vsubcuq, 0, 21),
10899 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10900 GEN_VXFORM(vrlb, 2, 0),
10901 GEN_VXFORM(vrlh, 2, 1),
10902 GEN_VXFORM(vrlw, 2, 2),
10903 GEN_VXFORM_207(vrld, 2, 3),
10904 GEN_VXFORM(vsl, 2, 7),
10905 GEN_VXFORM(vsr, 2, 11),
10906 GEN_VXFORM(vpkuhum, 7, 0),
10907 GEN_VXFORM(vpkuwum, 7, 1),
10908 GEN_VXFORM_207(vpkudum, 7, 17),
10909 GEN_VXFORM(vpkuhus, 7, 2),
10910 GEN_VXFORM(vpkuwus, 7, 3),
10911 GEN_VXFORM_207(vpkudus, 7, 19),
10912 GEN_VXFORM(vpkshus, 7, 4),
10913 GEN_VXFORM(vpkswus, 7, 5),
10914 GEN_VXFORM_207(vpksdus, 7, 21),
10915 GEN_VXFORM(vpkshss, 7, 6),
10916 GEN_VXFORM(vpkswss, 7, 7),
10917 GEN_VXFORM_207(vpksdss, 7, 23),
10918 GEN_VXFORM(vpkpx, 7, 12),
10919 GEN_VXFORM(vsum4ubs, 4, 24),
10920 GEN_VXFORM(vsum4sbs, 4, 28),
10921 GEN_VXFORM(vsum4shs, 4, 25),
10922 GEN_VXFORM(vsum2sws, 4, 26),
10923 GEN_VXFORM(vsumsws, 4, 30),
10924 GEN_VXFORM(vaddfp, 5, 0),
10925 GEN_VXFORM(vsubfp, 5, 1),
10926 GEN_VXFORM(vmaxfp, 5, 16),
10927 GEN_VXFORM(vminfp, 5, 17),
10928
10929 #undef GEN_VXRFORM1
10930 #undef GEN_VXRFORM
10931 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10932 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10933 #define GEN_VXRFORM(name, opc2, opc3) \
10934 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10935 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10936 GEN_VXRFORM(vcmpequb, 3, 0)
10937 GEN_VXRFORM(vcmpequh, 3, 1)
10938 GEN_VXRFORM(vcmpequw, 3, 2)
10939 GEN_VXRFORM(vcmpgtsb, 3, 12)
10940 GEN_VXRFORM(vcmpgtsh, 3, 13)
10941 GEN_VXRFORM(vcmpgtsw, 3, 14)
10942 GEN_VXRFORM(vcmpgtub, 3, 8)
10943 GEN_VXRFORM(vcmpgtuh, 3, 9)
10944 GEN_VXRFORM(vcmpgtuw, 3, 10)
10945 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10946 GEN_VXRFORM(vcmpgefp, 3, 7)
10947 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10948 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10949
10950 #undef GEN_VXFORM_SIMM
10951 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10952 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10953 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10954 GEN_VXFORM_SIMM(vspltish, 6, 13),
10955 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10956
10957 #undef GEN_VXFORM_NOA
10958 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10959 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10960 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10961 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10962 GEN_VXFORM_207(vupkhsw, 7, 25),
10963 GEN_VXFORM_NOA(vupklsb, 7, 10),
10964 GEN_VXFORM_NOA(vupklsh, 7, 11),
10965 GEN_VXFORM_207(vupklsw, 7, 27),
10966 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10967 GEN_VXFORM_NOA(vupklpx, 7, 15),
10968 GEN_VXFORM_NOA(vrefp, 5, 4),
10969 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10970 GEN_VXFORM_NOA(vexptefp, 5, 6),
10971 GEN_VXFORM_NOA(vlogefp, 5, 7),
10972 GEN_VXFORM_NOA(vrfim, 5, 11),
10973 GEN_VXFORM_NOA(vrfin, 5, 8),
10974 GEN_VXFORM_NOA(vrfip, 5, 10),
10975 GEN_VXFORM_NOA(vrfiz, 5, 9),
10976
10977 #undef GEN_VXFORM_UIMM
10978 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10979 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10980 GEN_VXFORM_UIMM(vspltb, 6, 8),
10981 GEN_VXFORM_UIMM(vsplth, 6, 9),
10982 GEN_VXFORM_UIMM(vspltw, 6, 10),
10983 GEN_VXFORM_UIMM(vcfux, 5, 12),
10984 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10985 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10986 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10987
10988 #undef GEN_VAFORM_PAIRED
10989 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10990 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10991 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10992 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10993 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10994 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10995 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10996 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10997
10998 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10999 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
11000 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
11001 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
11002
11003 GEN_VXFORM_207(vbpermq, 6, 21),
11004 GEN_VXFORM_207(vgbbd, 6, 20),
11005 GEN_VXFORM_207(vpmsumb, 4, 16),
11006 GEN_VXFORM_207(vpmsumh, 4, 17),
11007 GEN_VXFORM_207(vpmsumw, 4, 18),
11008 GEN_VXFORM_207(vpmsumd, 4, 19),
11009
11010 GEN_VXFORM_207(vsbox, 4, 23),
11011
11012 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
11013 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
11014
11015 GEN_VXFORM_207(vshasigmaw, 1, 26),
11016 GEN_VXFORM_207(vshasigmad, 1, 27),
11017
11018 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
11019
11020 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
11021 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
11022 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
11023 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
11024 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
11025 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
11026 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
11027
11028 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
11029 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
11030 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
11031 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
11032 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
11033
11034 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
11035 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
11036 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
11037 #if defined(TARGET_PPC64)
11038 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
11039 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
11040 #endif
11041
11042 #undef GEN_XX2FORM
11043 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
11044 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
11045 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
11046
11047 #undef GEN_XX3FORM
11048 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
11049 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
11050 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
11051 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
11052 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
11053
11054 #undef GEN_XX2IFORM
11055 #define GEN_XX2IFORM(name, opc2, opc3, fl2) \
11056 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
11057 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
11058 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
11059 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
11060
11061 #undef GEN_XX3_RC_FORM
11062 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
11063 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
11064 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
11065 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
11066 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
11067 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
11068 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
11069 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
11070 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
11071
11072 #undef GEN_XX3FORM_DM
11073 #define GEN_XX3FORM_DM(name, opc2, opc3) \
11074 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
11075 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
11076 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
11077 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
11078 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
11079 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
11080 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
11081 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
11082 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
11083 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
11084 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
11085 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
11086 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
11087 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
11088 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
11089 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
11090
11091 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
11092 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
11093 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
11094 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
11095
11096 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
11097 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
11098 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
11099 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
11100 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
11101 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
11102 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
11103 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
11104
11105 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
11106 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
11107 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
11108 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
11109 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
11110 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
11111 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
11112 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
11113 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
11114 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
11115 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
11116 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
11117 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
11118 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
11119 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
11120 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
11121 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
11122 GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
11123 GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
11124 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
11125 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
11126 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
11127 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
11128 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
11129 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
11130 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
11131 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
11132 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
11133 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
11134 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
11135 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
11136 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
11137 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
11138 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
11139 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
11140 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
11141
11142 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
11143 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
11144 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
11145 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
11146 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
11147 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
11148 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
11149 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
11150 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
11151 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
11152 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
11153 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
11154 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
11155 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
11156 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
11157 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
11158 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
11159 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
11160
11161 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
11162 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
11163 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
11164 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
11165 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
11166 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
11167 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
11168 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
11169 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
11170 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
11171 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
11172 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
11173 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
11174 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
11175 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
11176 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
11177 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
11178 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
11179 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
11180 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
11181 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
11182 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
11183 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
11184 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
11185 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
11186 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
11187 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
11188 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
11189 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
11190 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
11191 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
11192 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
11193 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
11194 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
11195 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
11196 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
11197
11198 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
11199 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
11200 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
11201 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
11202 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
11203 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
11204 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
11205 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
11206 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
11207 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
11208 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
11209 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
11210 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
11211 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
11212 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
11213 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
11214 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
11215 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
11216 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
11217 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
11218 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
11219 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
11220 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
11221 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
11222 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
11223 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
11224 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
11225 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
11226 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
11227 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
11228 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
11229 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
11230 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
11231 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
11232 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
11233 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
11234
11235 #undef VSX_LOGICAL
11236 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
11237 GEN_XX3FORM(name, opc2, opc3, fl2)
11238
11239 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
11240 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
11241 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
11242 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
11243 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
11244 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
11245 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
11246 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
11247 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
11248 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
11249 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
11250 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
11251
11252 #define GEN_XXSEL_ROW(opc3) \
11253 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
11254 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
11255 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
11256 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
11257 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
11258 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
11259 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
11260 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
11261
11262 GEN_XXSEL_ROW(0x00)
11263 GEN_XXSEL_ROW(0x01)
11264 GEN_XXSEL_ROW(0x02)
11265 GEN_XXSEL_ROW(0x03)
11266 GEN_XXSEL_ROW(0x04)
11267 GEN_XXSEL_ROW(0x05)
11268 GEN_XXSEL_ROW(0x06)
11269 GEN_XXSEL_ROW(0x07)
11270 GEN_XXSEL_ROW(0x08)
11271 GEN_XXSEL_ROW(0x09)
11272 GEN_XXSEL_ROW(0x0A)
11273 GEN_XXSEL_ROW(0x0B)
11274 GEN_XXSEL_ROW(0x0C)
11275 GEN_XXSEL_ROW(0x0D)
11276 GEN_XXSEL_ROW(0x0E)
11277 GEN_XXSEL_ROW(0x0F)
11278 GEN_XXSEL_ROW(0x10)
11279 GEN_XXSEL_ROW(0x11)
11280 GEN_XXSEL_ROW(0x12)
11281 GEN_XXSEL_ROW(0x13)
11282 GEN_XXSEL_ROW(0x14)
11283 GEN_XXSEL_ROW(0x15)
11284 GEN_XXSEL_ROW(0x16)
11285 GEN_XXSEL_ROW(0x17)
11286 GEN_XXSEL_ROW(0x18)
11287 GEN_XXSEL_ROW(0x19)
11288 GEN_XXSEL_ROW(0x1A)
11289 GEN_XXSEL_ROW(0x1B)
11290 GEN_XXSEL_ROW(0x1C)
11291 GEN_XXSEL_ROW(0x1D)
11292 GEN_XXSEL_ROW(0x1E)
11293 GEN_XXSEL_ROW(0x1F)
11294
11295 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
11296
11297 #undef GEN_DFP_T_A_B_Rc
11298 #undef GEN_DFP_BF_A_B
11299 #undef GEN_DFP_BF_A_DCM
11300 #undef GEN_DFP_T_B_U32_U32_Rc
11301 #undef GEN_DFP_T_A_B_I32_Rc
11302 #undef GEN_DFP_T_B_Rc
11303 #undef GEN_DFP_T_FPR_I32_Rc
11304
11305 #define _GEN_DFP_LONG(name, op1, op2, mask) \
11306 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
11307
11308 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
11309 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11310 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11311
11312 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
11313 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11314 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11315 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11316 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11317
11318 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
11319 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
11320
11321 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
11322 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11323 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11324
11325 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
11326 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11327 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11328 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11329 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11330
11331 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
11332 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
11333
11334 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
11335 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
11336
11337 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
11338 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
11339
11340 #define GEN_DFP_T_B_Rc(name, op1, op2) \
11341 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
11342
11343 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
11344 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
11345
11346 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
11347 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
11348
11349 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
11350 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
11351
11352 #define GEN_DFP_BF_A_B(name, op1, op2) \
11353 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
11354
11355 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
11356 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
11357
11358 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
11359 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
11360
11361 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
11362 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
11363
11364 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
11365 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
11366
11367 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
11368 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11369
11370 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
11371 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
11372
11373 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
11374 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
11375
11376 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
11377 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11378
11379 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
11380 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11381
11382 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11383 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11384
11385 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11386 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11387
11388 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11389 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
11390
11391 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11392 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11393
11394 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11395 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11396
11397 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11398 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11399
11400 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11401 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11402
11403 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11404 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11405
11406 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11407 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
11408 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11409 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
11410 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11411 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
11412 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11413 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
11414 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11415 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11416 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11417 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
11418 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11419 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
11420 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11421 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
11422 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11423 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
11424 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11425 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
11426 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11427 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11428 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11429 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
11430 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11431 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
11432 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11433 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11434 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11435 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
11436 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11437 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
11438 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11439 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
11440 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11441 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
11442 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11443 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
11444 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11445 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
11446 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11447 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
11448 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11449 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
11450 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11451 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
11452 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11453 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11454 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11455 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11456
11457 #undef GEN_SPE
11458 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11459 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11460 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11461 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11462 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11463 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11464 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11465 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11466 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11467 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11468 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11469 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11470 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11471 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11472 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11473 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11474 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11475 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11476 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11477 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11478 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11479 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11480 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11481 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11482 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11483 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11484 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11485 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11486 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11487 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11488 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11489
11490 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11491 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11492 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11493 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11494 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11495 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11496 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11497 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11498 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11499 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11500 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11501 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11502 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11503 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11504
11505 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11506 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11507 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11508 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11509 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11510 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11511 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11512 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11513 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11514 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11515 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11516 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11517 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11518 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11519
11520 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11521 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11522 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11523 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11524 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11525 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11526 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11527 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11528 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11529 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11530 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11531 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11532 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11533 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11534 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11535 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11536
11537 #undef GEN_SPEOP_LDST
11538 #define GEN_SPEOP_LDST(name, opc2, sh) \
11539 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11540 GEN_SPEOP_LDST(evldd, 0x00, 3),
11541 GEN_SPEOP_LDST(evldw, 0x01, 3),
11542 GEN_SPEOP_LDST(evldh, 0x02, 3),
11543 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11544 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11545 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11546 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11547 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11548 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11549 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11550 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11551
11552 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11553 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11554 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11555 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11556 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11557 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11558 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11559
11560 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11561 PPC_NONE, PPC2_TM),
11562 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11563 PPC_NONE, PPC2_TM),
11564 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11565 PPC_NONE, PPC2_TM),
11566 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11567 PPC_NONE, PPC2_TM),
11568 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11569 PPC_NONE, PPC2_TM),
11570 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11571 PPC_NONE, PPC2_TM),
11572 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11573 PPC_NONE, PPC2_TM),
11574 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11575 PPC_NONE, PPC2_TM),
11576 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11577 PPC_NONE, PPC2_TM),
11578 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11579 PPC_NONE, PPC2_TM),
11580 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11581 PPC_NONE, PPC2_TM),
11582 };
11583
11584 #include "helper_regs.h"
11585 #include "translate_init.c"
11586
11587 /*****************************************************************************/
11588 /* Misc PowerPC helpers */
11589 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11590 int flags)
11591 {
11592 #define RGPL 4
11593 #define RFPL 4
11594
11595 PowerPCCPU *cpu = POWERPC_CPU(cs);
11596 CPUPPCState *env = &cpu->env;
11597 int i;
11598
11599 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11600 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
11601 env->nip, env->lr, env->ctr, cpu_read_xer(env),
11602 cs->cpu_index);
11603 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11604 TARGET_FMT_lx " iidx %d didx %d\n",
11605 env->msr, env->spr[SPR_HID0],
11606 env->hflags, env->immu_idx, env->dmmu_idx);
11607 #if !defined(NO_TIMER_DUMP)
11608 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11609 #if !defined(CONFIG_USER_ONLY)
11610 " DECR %08" PRIu32
11611 #endif
11612 "\n",
11613 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11614 #if !defined(CONFIG_USER_ONLY)
11615 , cpu_ppc_load_decr(env)
11616 #endif
11617 );
11618 #endif
11619 for (i = 0; i < 32; i++) {
11620 if ((i & (RGPL - 1)) == 0)
11621 cpu_fprintf(f, "GPR%02d", i);
11622 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11623 if ((i & (RGPL - 1)) == (RGPL - 1))
11624 cpu_fprintf(f, "\n");
11625 }
11626 cpu_fprintf(f, "CR ");
11627 for (i = 0; i < 8; i++)
11628 cpu_fprintf(f, "%01x", env->crf[i]);
11629 cpu_fprintf(f, " [");
11630 for (i = 0; i < 8; i++) {
11631 char a = '-';
11632 if (env->crf[i] & 0x08)
11633 a = 'L';
11634 else if (env->crf[i] & 0x04)
11635 a = 'G';
11636 else if (env->crf[i] & 0x02)
11637 a = 'E';
11638 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11639 }
11640 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11641 env->reserve_addr);
11642 for (i = 0; i < 32; i++) {
11643 if ((i & (RFPL - 1)) == 0)
11644 cpu_fprintf(f, "FPR%02d", i);
11645 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11646 if ((i & (RFPL - 1)) == (RFPL - 1))
11647 cpu_fprintf(f, "\n");
11648 }
11649 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11650 #if !defined(CONFIG_USER_ONLY)
11651 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11652 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11653 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11654 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11655
11656 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11657 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11658 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11659 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11660
11661 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11662 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11663 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11664 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11665
11666 #if defined(TARGET_PPC64)
11667 if (env->excp_model == POWERPC_EXCP_POWER7 ||
11668 env->excp_model == POWERPC_EXCP_POWER8) {
11669 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
11670 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
11671 }
11672 #endif
11673 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11674 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11675 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11676 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11677 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11678
11679 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11680 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11681 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11682 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11683
11684 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11685 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11686 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11687 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11688
11689 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11690 " EPR " TARGET_FMT_lx "\n",
11691 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11692 env->spr[SPR_BOOKE_EPR]);
11693
11694 /* FSL-specific */
11695 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11696 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11697 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11698 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11699
11700 /*
11701 * IVORs are left out as they are large and do not change often --
11702 * they can be read with "p $ivor0", "p $ivor1", etc.
11703 */
11704 }
11705
11706 #if defined(TARGET_PPC64)
11707 if (env->flags & POWERPC_FLAG_CFAR) {
11708 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11709 }
11710 #endif
11711
11712 switch (env->mmu_model) {
11713 case POWERPC_MMU_32B:
11714 case POWERPC_MMU_601:
11715 case POWERPC_MMU_SOFT_6xx:
11716 case POWERPC_MMU_SOFT_74xx:
11717 #if defined(TARGET_PPC64)
11718 case POWERPC_MMU_64B:
11719 case POWERPC_MMU_2_03:
11720 case POWERPC_MMU_2_06:
11721 case POWERPC_MMU_2_06a:
11722 case POWERPC_MMU_2_07:
11723 case POWERPC_MMU_2_07a:
11724 #endif
11725 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11726 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11727 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11728 break;
11729 case POWERPC_MMU_BOOKE206:
11730 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11731 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11732 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11733 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11734
11735 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11736 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11737 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11738 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11739
11740 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11741 " TLB1CFG " TARGET_FMT_lx "\n",
11742 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11743 env->spr[SPR_BOOKE_TLB1CFG]);
11744 break;
11745 default:
11746 break;
11747 }
11748 #endif
11749
11750 #undef RGPL
11751 #undef RFPL
11752 }
11753
11754 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11755 fprintf_function cpu_fprintf, int flags)
11756 {
11757 #if defined(DO_PPC_STATISTICS)
11758 PowerPCCPU *cpu = POWERPC_CPU(cs);
11759 opc_handler_t **t1, **t2, **t3, *handler;
11760 int op1, op2, op3;
11761
11762 t1 = cpu->env.opcodes;
11763 for (op1 = 0; op1 < 64; op1++) {
11764 handler = t1[op1];
11765 if (is_indirect_opcode(handler)) {
11766 t2 = ind_table(handler);
11767 for (op2 = 0; op2 < 32; op2++) {
11768 handler = t2[op2];
11769 if (is_indirect_opcode(handler)) {
11770 t3 = ind_table(handler);
11771 for (op3 = 0; op3 < 32; op3++) {
11772 handler = t3[op3];
11773 if (handler->count == 0)
11774 continue;
11775 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11776 "%016" PRIx64 " %" PRId64 "\n",
11777 op1, op2, op3, op1, (op3 << 5) | op2,
11778 handler->oname,
11779 handler->count, handler->count);
11780 }
11781 } else {
11782 if (handler->count == 0)
11783 continue;
11784 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11785 "%016" PRIx64 " %" PRId64 "\n",
11786 op1, op2, op1, op2, handler->oname,
11787 handler->count, handler->count);
11788 }
11789 }
11790 } else {
11791 if (handler->count == 0)
11792 continue;
11793 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11794 " %" PRId64 "\n",
11795 op1, op1, handler->oname,
11796 handler->count, handler->count);
11797 }
11798 }
11799 #endif
11800 }
11801
11802 /*****************************************************************************/
11803 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
11804 {
11805 PowerPCCPU *cpu = ppc_env_get_cpu(env);
11806 CPUState *cs = CPU(cpu);
11807 DisasContext ctx, *ctxp = &ctx;
11808 opc_handler_t **table, *handler;
11809 target_ulong pc_start;
11810 int num_insns;
11811 int max_insns;
11812
11813 pc_start = tb->pc;
11814 ctx.nip = pc_start;
11815 ctx.tb = tb;
11816 ctx.exception = POWERPC_EXCP_NONE;
11817 ctx.spr_cb = env->spr_cb;
11818 ctx.pr = msr_pr;
11819 ctx.mem_idx = env->dmmu_idx;
11820 ctx.dr = msr_dr;
11821 #if !defined(CONFIG_USER_ONLY)
11822 ctx.hv = msr_hv || !env->has_hv_mode;
11823 #endif
11824 ctx.insns_flags = env->insns_flags;
11825 ctx.insns_flags2 = env->insns_flags2;
11826 ctx.access_type = -1;
11827 ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
11828 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11829 #if defined(TARGET_PPC64)
11830 ctx.sf_mode = msr_is_64bit(env, env->msr);
11831 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11832 #endif
11833 if (env->mmu_model == POWERPC_MMU_32B ||
11834 env->mmu_model == POWERPC_MMU_601 ||
11835 (env->mmu_model & POWERPC_MMU_64B))
11836 ctx.lazy_tlb_flush = true;
11837
11838 ctx.fpu_enabled = !!msr_fp;
11839 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11840 ctx.spe_enabled = !!msr_spe;
11841 else
11842 ctx.spe_enabled = false;
11843 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11844 ctx.altivec_enabled = !!msr_vr;
11845 else
11846 ctx.altivec_enabled = false;
11847 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11848 ctx.vsx_enabled = !!msr_vsx;
11849 } else {
11850 ctx.vsx_enabled = false;
11851 }
11852 #if defined(TARGET_PPC64)
11853 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11854 ctx.tm_enabled = !!msr_tm;
11855 } else {
11856 ctx.tm_enabled = false;
11857 }
11858 #endif
11859 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11860 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11861 else
11862 ctx.singlestep_enabled = 0;
11863 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11864 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11865 if (unlikely(cs->singlestep_enabled)) {
11866 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11867 }
11868 #if defined (DO_SINGLE_STEP) && 0
11869 /* Single step trace mode */
11870 msr_se = 1;
11871 #endif
11872 num_insns = 0;
11873 max_insns = tb->cflags & CF_COUNT_MASK;
11874 if (max_insns == 0) {
11875 max_insns = CF_COUNT_MASK;
11876 }
11877 if (max_insns > TCG_MAX_INSNS) {
11878 max_insns = TCG_MAX_INSNS;
11879 }
11880
11881 gen_tb_start(tb);
11882 tcg_clear_temp_count();
11883 /* Set env in case of segfault during code fetch */
11884 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
11885 tcg_gen_insn_start(ctx.nip);
11886 num_insns++;
11887
11888 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
11889 gen_debug_exception(ctxp);
11890 /* The address covered by the breakpoint must be included in
11891 [tb->pc, tb->pc + tb->size) in order to for it to be
11892 properly cleared -- thus we increment the PC here so that
11893 the logic setting tb->size below does the right thing. */
11894 ctx.nip += 4;
11895 break;
11896 }
11897
11898 LOG_DISAS("----------------\n");
11899 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11900 ctx.nip, ctx.mem_idx, (int)msr_ir);
11901 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
11902 gen_io_start();
11903 if (unlikely(need_byteswap(&ctx))) {
11904 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11905 } else {
11906 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11907 }
11908 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11909 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11910 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11911 ctx.nip += 4;
11912 table = env->opcodes;
11913 handler = table[opc1(ctx.opcode)];
11914 if (is_indirect_opcode(handler)) {
11915 table = ind_table(handler);
11916 handler = table[opc2(ctx.opcode)];
11917 if (is_indirect_opcode(handler)) {
11918 table = ind_table(handler);
11919 handler = table[opc3(ctx.opcode)];
11920 }
11921 }
11922 /* Is opcode *REALLY* valid ? */
11923 if (unlikely(handler->handler == &gen_invalid)) {
11924 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
11925 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11926 opc1(ctx.opcode), opc2(ctx.opcode),
11927 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11928 } else {
11929 uint32_t inval;
11930
11931 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11932 inval = handler->inval2;
11933 } else {
11934 inval = handler->inval1;
11935 }
11936
11937 if (unlikely((ctx.opcode & inval) != 0)) {
11938 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
11939 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11940 ctx.opcode & inval, opc1(ctx.opcode),
11941 opc2(ctx.opcode), opc3(ctx.opcode),
11942 ctx.opcode, ctx.nip - 4);
11943 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11944 break;
11945 }
11946 }
11947 (*(handler->handler))(&ctx);
11948 #if defined(DO_PPC_STATISTICS)
11949 handler->count++;
11950 #endif
11951 /* Check trace mode exceptions */
11952 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11953 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11954 ctx.exception != POWERPC_SYSCALL &&
11955 ctx.exception != POWERPC_EXCP_TRAP &&
11956 ctx.exception != POWERPC_EXCP_BRANCH)) {
11957 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11958 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11959 (cs->singlestep_enabled) ||
11960 singlestep ||
11961 num_insns >= max_insns)) {
11962 /* if we reach a page boundary or are single stepping, stop
11963 * generation
11964 */
11965 break;
11966 }
11967 if (tcg_check_temp_count()) {
11968 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11969 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11970 ctx.opcode);
11971 exit(1);
11972 }
11973 }
11974 if (tb->cflags & CF_LAST_IO)
11975 gen_io_end();
11976 if (ctx.exception == POWERPC_EXCP_NONE) {
11977 gen_goto_tb(&ctx, 0, ctx.nip);
11978 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11979 if (unlikely(cs->singlestep_enabled)) {
11980 gen_debug_exception(ctxp);
11981 }
11982 /* Generate the return instruction */
11983 tcg_gen_exit_tb(0);
11984 }
11985 gen_tb_end(tb, num_insns);
11986
11987 tb->size = ctx.nip - pc_start;
11988 tb->icount = num_insns;
11989
11990 #if defined(DEBUG_DISAS)
11991 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
11992 && qemu_log_in_addr_range(pc_start)) {
11993 int flags;
11994 flags = env->bfd_mach;
11995 flags |= ctx.le_mode << 16;
11996 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11997 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
11998 qemu_log("\n");
11999 }
12000 #endif
12001 }
12002
12003 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
12004 target_ulong *data)
12005 {
12006 env->nip = data[0];
12007 }
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