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[qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i32 cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_msr;
64 static TCGv cpu_ctr;
65 static TCGv cpu_lr;
66 #if defined(TARGET_PPC64)
67 static TCGv cpu_cfar;
68 #endif
69 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
70 static TCGv cpu_reserve;
71 static TCGv cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "exec/gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111 #endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154 #if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157 #endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161 cpu_so = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUPPCState, so), "SO");
163 cpu_ov = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, ov), "OV");
165 cpu_ca = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, ca), "CA");
167
168 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, reserve_addr),
170 "reserve_addr");
171
172 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, fpscr), "fpscr");
174
175 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
176 offsetof(CPUPPCState, access_type), "access_type");
177
178 /* register helpers */
179 #define GEN_HELPER 2
180 #include "helper.h"
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 int mem_idx;
193 int access_type;
194 /* Translation flags */
195 int le_mode;
196 #if defined(TARGET_PPC64)
197 int sf_mode;
198 int has_cfar;
199 #endif
200 int fpu_enabled;
201 int altivec_enabled;
202 int spe_enabled;
203 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
204 int singlestep_enabled;
205 } DisasContext;
206
207 /* True when active word size < size of target_long. */
208 #ifdef TARGET_PPC64
209 # define NARROW_MODE(C) (!(C)->sf_mode)
210 #else
211 # define NARROW_MODE(C) 0
212 #endif
213
214 struct opc_handler_t {
215 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
216 uint32_t inval1;
217 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
218 uint32_t inval2;
219 /* instruction type */
220 uint64_t type;
221 /* extended instruction type */
222 uint64_t type2;
223 /* handler */
224 void (*handler)(DisasContext *ctx);
225 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
226 const char *oname;
227 #endif
228 #if defined(DO_PPC_STATISTICS)
229 uint64_t count;
230 #endif
231 };
232
233 static inline void gen_reset_fpstatus(void)
234 {
235 gen_helper_reset_fpstatus(cpu_env);
236 }
237
238 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
239 {
240 TCGv_i32 t0 = tcg_temp_new_i32();
241
242 if (set_fprf != 0) {
243 /* This case might be optimized later */
244 tcg_gen_movi_i32(t0, 1);
245 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
246 if (unlikely(set_rc)) {
247 tcg_gen_mov_i32(cpu_crf[1], t0);
248 }
249 gen_helper_float_check_status(cpu_env);
250 } else if (unlikely(set_rc)) {
251 /* We always need to compute fpcc */
252 tcg_gen_movi_i32(t0, 0);
253 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
254 tcg_gen_mov_i32(cpu_crf[1], t0);
255 }
256
257 tcg_temp_free_i32(t0);
258 }
259
260 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
261 {
262 if (ctx->access_type != access_type) {
263 tcg_gen_movi_i32(cpu_access_type, access_type);
264 ctx->access_type = access_type;
265 }
266 }
267
268 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
269 {
270 if (NARROW_MODE(ctx)) {
271 nip = (uint32_t)nip;
272 }
273 tcg_gen_movi_tl(cpu_nip, nip);
274 }
275
276 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
277 {
278 TCGv_i32 t0, t1;
279 if (ctx->exception == POWERPC_EXCP_NONE) {
280 gen_update_nip(ctx, ctx->nip);
281 }
282 t0 = tcg_const_i32(excp);
283 t1 = tcg_const_i32(error);
284 gen_helper_raise_exception_err(cpu_env, t0, t1);
285 tcg_temp_free_i32(t0);
286 tcg_temp_free_i32(t1);
287 ctx->exception = (excp);
288 }
289
290 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
291 {
292 TCGv_i32 t0;
293 if (ctx->exception == POWERPC_EXCP_NONE) {
294 gen_update_nip(ctx, ctx->nip);
295 }
296 t0 = tcg_const_i32(excp);
297 gen_helper_raise_exception(cpu_env, t0);
298 tcg_temp_free_i32(t0);
299 ctx->exception = (excp);
300 }
301
302 static inline void gen_debug_exception(DisasContext *ctx)
303 {
304 TCGv_i32 t0;
305
306 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
307 (ctx->exception != POWERPC_EXCP_SYNC)) {
308 gen_update_nip(ctx, ctx->nip);
309 }
310 t0 = tcg_const_i32(EXCP_DEBUG);
311 gen_helper_raise_exception(cpu_env, t0);
312 tcg_temp_free_i32(t0);
313 }
314
315 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
316 {
317 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
318 }
319
320 /* Stop translation */
321 static inline void gen_stop_exception(DisasContext *ctx)
322 {
323 gen_update_nip(ctx, ctx->nip);
324 ctx->exception = POWERPC_EXCP_STOP;
325 }
326
327 /* No need to update nip here, as execution flow will change */
328 static inline void gen_sync_exception(DisasContext *ctx)
329 {
330 ctx->exception = POWERPC_EXCP_SYNC;
331 }
332
333 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
334 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
335
336 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
337 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
338
339 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
340 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
341
342 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
343 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
344
345 typedef struct opcode_t {
346 unsigned char opc1, opc2, opc3;
347 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
348 unsigned char pad[5];
349 #else
350 unsigned char pad[1];
351 #endif
352 opc_handler_t handler;
353 const char *oname;
354 } opcode_t;
355
356 /*****************************************************************************/
357 /*** Instruction decoding ***/
358 #define EXTRACT_HELPER(name, shift, nb) \
359 static inline uint32_t name(uint32_t opcode) \
360 { \
361 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
362 }
363
364 #define EXTRACT_SHELPER(name, shift, nb) \
365 static inline int32_t name(uint32_t opcode) \
366 { \
367 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
368 }
369
370 /* Opcode part 1 */
371 EXTRACT_HELPER(opc1, 26, 6);
372 /* Opcode part 2 */
373 EXTRACT_HELPER(opc2, 1, 5);
374 /* Opcode part 3 */
375 EXTRACT_HELPER(opc3, 6, 5);
376 /* Update Cr0 flags */
377 EXTRACT_HELPER(Rc, 0, 1);
378 /* Destination */
379 EXTRACT_HELPER(rD, 21, 5);
380 /* Source */
381 EXTRACT_HELPER(rS, 21, 5);
382 /* First operand */
383 EXTRACT_HELPER(rA, 16, 5);
384 /* Second operand */
385 EXTRACT_HELPER(rB, 11, 5);
386 /* Third operand */
387 EXTRACT_HELPER(rC, 6, 5);
388 /*** Get CRn ***/
389 EXTRACT_HELPER(crfD, 23, 3);
390 EXTRACT_HELPER(crfS, 18, 3);
391 EXTRACT_HELPER(crbD, 21, 5);
392 EXTRACT_HELPER(crbA, 16, 5);
393 EXTRACT_HELPER(crbB, 11, 5);
394 /* SPR / TBL */
395 EXTRACT_HELPER(_SPR, 11, 10);
396 static inline uint32_t SPR(uint32_t opcode)
397 {
398 uint32_t sprn = _SPR(opcode);
399
400 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
401 }
402 /*** Get constants ***/
403 EXTRACT_HELPER(IMM, 12, 8);
404 /* 16 bits signed immediate value */
405 EXTRACT_SHELPER(SIMM, 0, 16);
406 /* 16 bits unsigned immediate value */
407 EXTRACT_HELPER(UIMM, 0, 16);
408 /* 5 bits signed immediate value */
409 EXTRACT_HELPER(SIMM5, 16, 5);
410 /* 5 bits signed immediate value */
411 EXTRACT_HELPER(UIMM5, 16, 5);
412 /* Bit count */
413 EXTRACT_HELPER(NB, 11, 5);
414 /* Shift count */
415 EXTRACT_HELPER(SH, 11, 5);
416 /* Vector shift count */
417 EXTRACT_HELPER(VSH, 6, 4);
418 /* Mask start */
419 EXTRACT_HELPER(MB, 6, 5);
420 /* Mask end */
421 EXTRACT_HELPER(ME, 1, 5);
422 /* Trap operand */
423 EXTRACT_HELPER(TO, 21, 5);
424
425 EXTRACT_HELPER(CRM, 12, 8);
426 EXTRACT_HELPER(FM, 17, 8);
427 EXTRACT_HELPER(SR, 16, 4);
428 EXTRACT_HELPER(FPIMM, 12, 4);
429
430 /*** Jump target decoding ***/
431 /* Displacement */
432 EXTRACT_SHELPER(d, 0, 16);
433 /* Immediate address */
434 static inline target_ulong LI(uint32_t opcode)
435 {
436 return (opcode >> 0) & 0x03FFFFFC;
437 }
438
439 static inline uint32_t BD(uint32_t opcode)
440 {
441 return (opcode >> 0) & 0xFFFC;
442 }
443
444 EXTRACT_HELPER(BO, 21, 5);
445 EXTRACT_HELPER(BI, 16, 5);
446 /* Absolute/relative address */
447 EXTRACT_HELPER(AA, 1, 1);
448 /* Link */
449 EXTRACT_HELPER(LK, 0, 1);
450
451 /* Create a mask between <start> and <end> bits */
452 static inline target_ulong MASK(uint32_t start, uint32_t end)
453 {
454 target_ulong ret;
455
456 #if defined(TARGET_PPC64)
457 if (likely(start == 0)) {
458 ret = UINT64_MAX << (63 - end);
459 } else if (likely(end == 63)) {
460 ret = UINT64_MAX >> start;
461 }
462 #else
463 if (likely(start == 0)) {
464 ret = UINT32_MAX << (31 - end);
465 } else if (likely(end == 31)) {
466 ret = UINT32_MAX >> start;
467 }
468 #endif
469 else {
470 ret = (((target_ulong)(-1ULL)) >> (start)) ^
471 (((target_ulong)(-1ULL) >> (end)) >> 1);
472 if (unlikely(start > end))
473 return ~ret;
474 }
475
476 return ret;
477 }
478
479 /*****************************************************************************/
480 /* PowerPC instructions table */
481
482 #if defined(DO_PPC_STATISTICS)
483 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
484 { \
485 .opc1 = op1, \
486 .opc2 = op2, \
487 .opc3 = op3, \
488 .pad = { 0, }, \
489 .handler = { \
490 .inval1 = invl, \
491 .type = _typ, \
492 .type2 = _typ2, \
493 .handler = &gen_##name, \
494 .oname = stringify(name), \
495 }, \
496 .oname = stringify(name), \
497 }
498 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
499 { \
500 .opc1 = op1, \
501 .opc2 = op2, \
502 .opc3 = op3, \
503 .pad = { 0, }, \
504 .handler = { \
505 .inval1 = invl1, \
506 .inval2 = invl2, \
507 .type = _typ, \
508 .type2 = _typ2, \
509 .handler = &gen_##name, \
510 .oname = stringify(name), \
511 }, \
512 .oname = stringify(name), \
513 }
514 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
515 { \
516 .opc1 = op1, \
517 .opc2 = op2, \
518 .opc3 = op3, \
519 .pad = { 0, }, \
520 .handler = { \
521 .inval1 = invl, \
522 .type = _typ, \
523 .type2 = _typ2, \
524 .handler = &gen_##name, \
525 .oname = onam, \
526 }, \
527 .oname = onam, \
528 }
529 #else
530 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
531 { \
532 .opc1 = op1, \
533 .opc2 = op2, \
534 .opc3 = op3, \
535 .pad = { 0, }, \
536 .handler = { \
537 .inval1 = invl, \
538 .type = _typ, \
539 .type2 = _typ2, \
540 .handler = &gen_##name, \
541 }, \
542 .oname = stringify(name), \
543 }
544 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
545 { \
546 .opc1 = op1, \
547 .opc2 = op2, \
548 .opc3 = op3, \
549 .pad = { 0, }, \
550 .handler = { \
551 .inval1 = invl1, \
552 .inval2 = invl2, \
553 .type = _typ, \
554 .type2 = _typ2, \
555 .handler = &gen_##name, \
556 }, \
557 .oname = stringify(name), \
558 }
559 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
560 { \
561 .opc1 = op1, \
562 .opc2 = op2, \
563 .opc3 = op3, \
564 .pad = { 0, }, \
565 .handler = { \
566 .inval1 = invl, \
567 .type = _typ, \
568 .type2 = _typ2, \
569 .handler = &gen_##name, \
570 }, \
571 .oname = onam, \
572 }
573 #endif
574
575 /* SPR load/store helpers */
576 static inline void gen_load_spr(TCGv t, int reg)
577 {
578 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
579 }
580
581 static inline void gen_store_spr(int reg, TCGv t)
582 {
583 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
584 }
585
586 /* Invalid instruction */
587 static void gen_invalid(DisasContext *ctx)
588 {
589 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
590 }
591
592 static opc_handler_t invalid_handler = {
593 .inval1 = 0xFFFFFFFF,
594 .inval2 = 0xFFFFFFFF,
595 .type = PPC_NONE,
596 .type2 = PPC_NONE,
597 .handler = gen_invalid,
598 };
599
600 /*** Integer comparison ***/
601
602 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
603 {
604 TCGv t0 = tcg_temp_new();
605 TCGv_i32 t1 = tcg_temp_new_i32();
606
607 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
608
609 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
610 tcg_gen_trunc_tl_i32(t1, t0);
611 tcg_gen_shli_i32(t1, t1, CRF_LT);
612 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
613
614 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
615 tcg_gen_trunc_tl_i32(t1, t0);
616 tcg_gen_shli_i32(t1, t1, CRF_GT);
617 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
618
619 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
620 tcg_gen_trunc_tl_i32(t1, t0);
621 tcg_gen_shli_i32(t1, t1, CRF_EQ);
622 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
623
624 tcg_temp_free(t0);
625 tcg_temp_free_i32(t1);
626 }
627
628 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
629 {
630 TCGv t0 = tcg_const_tl(arg1);
631 gen_op_cmp(arg0, t0, s, crf);
632 tcg_temp_free(t0);
633 }
634
635 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
636 {
637 TCGv t0, t1;
638 t0 = tcg_temp_new();
639 t1 = tcg_temp_new();
640 if (s) {
641 tcg_gen_ext32s_tl(t0, arg0);
642 tcg_gen_ext32s_tl(t1, arg1);
643 } else {
644 tcg_gen_ext32u_tl(t0, arg0);
645 tcg_gen_ext32u_tl(t1, arg1);
646 }
647 gen_op_cmp(t0, t1, s, crf);
648 tcg_temp_free(t1);
649 tcg_temp_free(t0);
650 }
651
652 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
653 {
654 TCGv t0 = tcg_const_tl(arg1);
655 gen_op_cmp32(arg0, t0, s, crf);
656 tcg_temp_free(t0);
657 }
658
659 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
660 {
661 if (NARROW_MODE(ctx)) {
662 gen_op_cmpi32(reg, 0, 1, 0);
663 } else {
664 gen_op_cmpi(reg, 0, 1, 0);
665 }
666 }
667
668 /* cmp */
669 static void gen_cmp(DisasContext *ctx)
670 {
671 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
672 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
673 1, crfD(ctx->opcode));
674 } else {
675 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
676 1, crfD(ctx->opcode));
677 }
678 }
679
680 /* cmpi */
681 static void gen_cmpi(DisasContext *ctx)
682 {
683 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
684 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
685 1, crfD(ctx->opcode));
686 } else {
687 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
688 1, crfD(ctx->opcode));
689 }
690 }
691
692 /* cmpl */
693 static void gen_cmpl(DisasContext *ctx)
694 {
695 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
696 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
697 0, crfD(ctx->opcode));
698 } else {
699 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
700 0, crfD(ctx->opcode));
701 }
702 }
703
704 /* cmpli */
705 static void gen_cmpli(DisasContext *ctx)
706 {
707 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
708 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
709 0, crfD(ctx->opcode));
710 } else {
711 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
712 0, crfD(ctx->opcode));
713 }
714 }
715
716 /* isel (PowerPC 2.03 specification) */
717 static void gen_isel(DisasContext *ctx)
718 {
719 int l1, l2;
720 uint32_t bi = rC(ctx->opcode);
721 uint32_t mask;
722 TCGv_i32 t0;
723
724 l1 = gen_new_label();
725 l2 = gen_new_label();
726
727 mask = 1 << (3 - (bi & 0x03));
728 t0 = tcg_temp_new_i32();
729 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
730 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
731 if (rA(ctx->opcode) == 0)
732 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
733 else
734 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
735 tcg_gen_br(l2);
736 gen_set_label(l1);
737 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
738 gen_set_label(l2);
739 tcg_temp_free_i32(t0);
740 }
741
742 /* cmpb: PowerPC 2.05 specification */
743 static void gen_cmpb(DisasContext *ctx)
744 {
745 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
746 cpu_gpr[rB(ctx->opcode)]);
747 }
748
749 /*** Integer arithmetic ***/
750
751 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
752 TCGv arg1, TCGv arg2, int sub)
753 {
754 TCGv t0 = tcg_temp_new();
755
756 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
757 tcg_gen_xor_tl(t0, arg1, arg2);
758 if (sub) {
759 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
760 } else {
761 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
762 }
763 tcg_temp_free(t0);
764 if (NARROW_MODE(ctx)) {
765 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
766 }
767 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
768 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
769 }
770
771 /* Common add function */
772 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
773 TCGv arg2, bool add_ca, bool compute_ca,
774 bool compute_ov, bool compute_rc0)
775 {
776 TCGv t0 = ret;
777
778 if (compute_ca || compute_ov) {
779 t0 = tcg_temp_new();
780 }
781
782 if (compute_ca) {
783 if (NARROW_MODE(ctx)) {
784 /* Caution: a non-obvious corner case of the spec is that we
785 must produce the *entire* 64-bit addition, but produce the
786 carry into bit 32. */
787 TCGv t1 = tcg_temp_new();
788 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
789 tcg_gen_add_tl(t0, arg1, arg2);
790 if (add_ca) {
791 tcg_gen_add_tl(t0, t0, cpu_ca);
792 }
793 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
794 tcg_temp_free(t1);
795 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
796 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
797 } else {
798 TCGv zero = tcg_const_tl(0);
799 if (add_ca) {
800 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
801 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
802 } else {
803 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
804 }
805 tcg_temp_free(zero);
806 }
807 } else {
808 tcg_gen_add_tl(t0, arg1, arg2);
809 if (add_ca) {
810 tcg_gen_add_tl(t0, t0, cpu_ca);
811 }
812 }
813
814 if (compute_ov) {
815 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
816 }
817 if (unlikely(compute_rc0)) {
818 gen_set_Rc0(ctx, t0);
819 }
820
821 if (!TCGV_EQUAL(t0, ret)) {
822 tcg_gen_mov_tl(ret, t0);
823 tcg_temp_free(t0);
824 }
825 }
826 /* Add functions with two operands */
827 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
828 static void glue(gen_, name)(DisasContext *ctx) \
829 { \
830 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
831 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
832 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
833 }
834 /* Add functions with one operand and one immediate */
835 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
836 add_ca, compute_ca, compute_ov) \
837 static void glue(gen_, name)(DisasContext *ctx) \
838 { \
839 TCGv t0 = tcg_const_tl(const_val); \
840 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
841 cpu_gpr[rA(ctx->opcode)], t0, \
842 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
843 tcg_temp_free(t0); \
844 }
845
846 /* add add. addo addo. */
847 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
848 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
849 /* addc addc. addco addco. */
850 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
851 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
852 /* adde adde. addeo addeo. */
853 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
854 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
855 /* addme addme. addmeo addmeo. */
856 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
857 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
858 /* addze addze. addzeo addzeo.*/
859 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
860 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
861 /* addi */
862 static void gen_addi(DisasContext *ctx)
863 {
864 target_long simm = SIMM(ctx->opcode);
865
866 if (rA(ctx->opcode) == 0) {
867 /* li case */
868 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
869 } else {
870 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
871 cpu_gpr[rA(ctx->opcode)], simm);
872 }
873 }
874 /* addic addic.*/
875 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
876 {
877 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
878 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
879 c, 0, 1, 0, compute_rc0);
880 tcg_temp_free(c);
881 }
882
883 static void gen_addic(DisasContext *ctx)
884 {
885 gen_op_addic(ctx, 0);
886 }
887
888 static void gen_addic_(DisasContext *ctx)
889 {
890 gen_op_addic(ctx, 1);
891 }
892
893 /* addis */
894 static void gen_addis(DisasContext *ctx)
895 {
896 target_long simm = SIMM(ctx->opcode);
897
898 if (rA(ctx->opcode) == 0) {
899 /* lis case */
900 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
901 } else {
902 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
903 cpu_gpr[rA(ctx->opcode)], simm << 16);
904 }
905 }
906
907 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
908 TCGv arg2, int sign, int compute_ov)
909 {
910 int l1 = gen_new_label();
911 int l2 = gen_new_label();
912 TCGv_i32 t0 = tcg_temp_local_new_i32();
913 TCGv_i32 t1 = tcg_temp_local_new_i32();
914
915 tcg_gen_trunc_tl_i32(t0, arg1);
916 tcg_gen_trunc_tl_i32(t1, arg2);
917 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
918 if (sign) {
919 int l3 = gen_new_label();
920 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
921 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
922 gen_set_label(l3);
923 tcg_gen_div_i32(t0, t0, t1);
924 } else {
925 tcg_gen_divu_i32(t0, t0, t1);
926 }
927 if (compute_ov) {
928 tcg_gen_movi_tl(cpu_ov, 0);
929 }
930 tcg_gen_br(l2);
931 gen_set_label(l1);
932 if (sign) {
933 tcg_gen_sari_i32(t0, t0, 31);
934 } else {
935 tcg_gen_movi_i32(t0, 0);
936 }
937 if (compute_ov) {
938 tcg_gen_movi_tl(cpu_ov, 1);
939 tcg_gen_movi_tl(cpu_so, 1);
940 }
941 gen_set_label(l2);
942 tcg_gen_extu_i32_tl(ret, t0);
943 tcg_temp_free_i32(t0);
944 tcg_temp_free_i32(t1);
945 if (unlikely(Rc(ctx->opcode) != 0))
946 gen_set_Rc0(ctx, ret);
947 }
948 /* Div functions */
949 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
950 static void glue(gen_, name)(DisasContext *ctx) \
951 { \
952 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
953 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
954 sign, compute_ov); \
955 }
956 /* divwu divwu. divwuo divwuo. */
957 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
958 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
959 /* divw divw. divwo divwo. */
960 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
961 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
962 #if defined(TARGET_PPC64)
963 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
964 TCGv arg2, int sign, int compute_ov)
965 {
966 int l1 = gen_new_label();
967 int l2 = gen_new_label();
968
969 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
970 if (sign) {
971 int l3 = gen_new_label();
972 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
973 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
974 gen_set_label(l3);
975 tcg_gen_div_i64(ret, arg1, arg2);
976 } else {
977 tcg_gen_divu_i64(ret, arg1, arg2);
978 }
979 if (compute_ov) {
980 tcg_gen_movi_tl(cpu_ov, 0);
981 }
982 tcg_gen_br(l2);
983 gen_set_label(l1);
984 if (sign) {
985 tcg_gen_sari_i64(ret, arg1, 63);
986 } else {
987 tcg_gen_movi_i64(ret, 0);
988 }
989 if (compute_ov) {
990 tcg_gen_movi_tl(cpu_ov, 1);
991 tcg_gen_movi_tl(cpu_so, 1);
992 }
993 gen_set_label(l2);
994 if (unlikely(Rc(ctx->opcode) != 0))
995 gen_set_Rc0(ctx, ret);
996 }
997 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
998 static void glue(gen_, name)(DisasContext *ctx) \
999 { \
1000 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1001 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1002 sign, compute_ov); \
1003 }
1004 /* divwu divwu. divwuo divwuo. */
1005 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1006 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1007 /* divw divw. divwo divwo. */
1008 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1009 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1010 #endif
1011
1012 /* mulhw mulhw. */
1013 static void gen_mulhw(DisasContext *ctx)
1014 {
1015 TCGv_i32 t0 = tcg_temp_new_i32();
1016 TCGv_i32 t1 = tcg_temp_new_i32();
1017
1018 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1019 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1020 tcg_gen_muls2_i32(t0, t1, t0, t1);
1021 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1022 tcg_temp_free_i32(t0);
1023 tcg_temp_free_i32(t1);
1024 if (unlikely(Rc(ctx->opcode) != 0))
1025 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1026 }
1027
1028 /* mulhwu mulhwu. */
1029 static void gen_mulhwu(DisasContext *ctx)
1030 {
1031 TCGv_i32 t0 = tcg_temp_new_i32();
1032 TCGv_i32 t1 = tcg_temp_new_i32();
1033
1034 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1035 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1036 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1037 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1038 tcg_temp_free_i32(t0);
1039 tcg_temp_free_i32(t1);
1040 if (unlikely(Rc(ctx->opcode) != 0))
1041 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1042 }
1043
1044 /* mullw mullw. */
1045 static void gen_mullw(DisasContext *ctx)
1046 {
1047 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1048 cpu_gpr[rB(ctx->opcode)]);
1049 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1050 if (unlikely(Rc(ctx->opcode) != 0))
1051 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1052 }
1053
1054 /* mullwo mullwo. */
1055 static void gen_mullwo(DisasContext *ctx)
1056 {
1057 TCGv_i32 t0 = tcg_temp_new_i32();
1058 TCGv_i32 t1 = tcg_temp_new_i32();
1059
1060 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1061 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1062 tcg_gen_muls2_i32(t0, t1, t0, t1);
1063 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1064
1065 tcg_gen_sari_i32(t0, t0, 31);
1066 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1067 tcg_gen_extu_i32_tl(cpu_ov, t0);
1068 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1069
1070 tcg_temp_free_i32(t0);
1071 tcg_temp_free_i32(t1);
1072 if (unlikely(Rc(ctx->opcode) != 0))
1073 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1074 }
1075
1076 /* mulli */
1077 static void gen_mulli(DisasContext *ctx)
1078 {
1079 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1080 SIMM(ctx->opcode));
1081 }
1082
1083 #if defined(TARGET_PPC64)
1084 /* mulhd mulhd. */
1085 static void gen_mulhd(DisasContext *ctx)
1086 {
1087 TCGv lo = tcg_temp_new();
1088 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1089 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1090 tcg_temp_free(lo);
1091 if (unlikely(Rc(ctx->opcode) != 0)) {
1092 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1093 }
1094 }
1095
1096 /* mulhdu mulhdu. */
1097 static void gen_mulhdu(DisasContext *ctx)
1098 {
1099 TCGv lo = tcg_temp_new();
1100 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1101 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1102 tcg_temp_free(lo);
1103 if (unlikely(Rc(ctx->opcode) != 0)) {
1104 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1105 }
1106 }
1107
1108 /* mulld mulld. */
1109 static void gen_mulld(DisasContext *ctx)
1110 {
1111 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1112 cpu_gpr[rB(ctx->opcode)]);
1113 if (unlikely(Rc(ctx->opcode) != 0))
1114 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1115 }
1116
1117 /* mulldo mulldo. */
1118 static void gen_mulldo(DisasContext *ctx)
1119 {
1120 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1121 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1122 if (unlikely(Rc(ctx->opcode) != 0)) {
1123 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1124 }
1125 }
1126 #endif
1127
1128 /* Common subf function */
1129 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1130 TCGv arg2, bool add_ca, bool compute_ca,
1131 bool compute_ov, bool compute_rc0)
1132 {
1133 TCGv t0 = ret;
1134
1135 if (compute_ca || compute_ov) {
1136 t0 = tcg_temp_new();
1137 }
1138
1139 if (compute_ca) {
1140 /* dest = ~arg1 + arg2 [+ ca]. */
1141 if (NARROW_MODE(ctx)) {
1142 /* Caution: a non-obvious corner case of the spec is that we
1143 must produce the *entire* 64-bit addition, but produce the
1144 carry into bit 32. */
1145 TCGv inv1 = tcg_temp_new();
1146 TCGv t1 = tcg_temp_new();
1147 tcg_gen_not_tl(inv1, arg1);
1148 if (add_ca) {
1149 tcg_gen_add_tl(t0, arg2, cpu_ca);
1150 } else {
1151 tcg_gen_addi_tl(t0, arg2, 1);
1152 }
1153 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1154 tcg_gen_add_tl(t0, t0, inv1);
1155 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1156 tcg_temp_free(t1);
1157 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1158 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1159 } else if (add_ca) {
1160 TCGv zero, inv1 = tcg_temp_new();
1161 tcg_gen_not_tl(inv1, arg1);
1162 zero = tcg_const_tl(0);
1163 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1164 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1165 tcg_temp_free(zero);
1166 tcg_temp_free(inv1);
1167 } else {
1168 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1169 tcg_gen_sub_tl(t0, arg2, arg1);
1170 }
1171 } else if (add_ca) {
1172 /* Since we're ignoring carry-out, we can simplify the
1173 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1174 tcg_gen_sub_tl(t0, arg2, arg1);
1175 tcg_gen_add_tl(t0, t0, cpu_ca);
1176 tcg_gen_subi_tl(t0, t0, 1);
1177 } else {
1178 tcg_gen_sub_tl(t0, arg2, arg1);
1179 }
1180
1181 if (compute_ov) {
1182 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1183 }
1184 if (unlikely(compute_rc0)) {
1185 gen_set_Rc0(ctx, t0);
1186 }
1187
1188 if (!TCGV_EQUAL(t0, ret)) {
1189 tcg_gen_mov_tl(ret, t0);
1190 tcg_temp_free(t0);
1191 }
1192 }
1193 /* Sub functions with Two operands functions */
1194 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1195 static void glue(gen_, name)(DisasContext *ctx) \
1196 { \
1197 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1198 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1199 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1200 }
1201 /* Sub functions with one operand and one immediate */
1202 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1203 add_ca, compute_ca, compute_ov) \
1204 static void glue(gen_, name)(DisasContext *ctx) \
1205 { \
1206 TCGv t0 = tcg_const_tl(const_val); \
1207 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1208 cpu_gpr[rA(ctx->opcode)], t0, \
1209 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1210 tcg_temp_free(t0); \
1211 }
1212 /* subf subf. subfo subfo. */
1213 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1214 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1215 /* subfc subfc. subfco subfco. */
1216 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1217 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1218 /* subfe subfe. subfeo subfo. */
1219 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1220 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1221 /* subfme subfme. subfmeo subfmeo. */
1222 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1223 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1224 /* subfze subfze. subfzeo subfzeo.*/
1225 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1226 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1227
1228 /* subfic */
1229 static void gen_subfic(DisasContext *ctx)
1230 {
1231 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1232 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1233 c, 0, 1, 0, 0);
1234 tcg_temp_free(c);
1235 }
1236
1237 /* neg neg. nego nego. */
1238 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1239 {
1240 TCGv zero = tcg_const_tl(0);
1241 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1242 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1243 tcg_temp_free(zero);
1244 }
1245
1246 static void gen_neg(DisasContext *ctx)
1247 {
1248 gen_op_arith_neg(ctx, 0);
1249 }
1250
1251 static void gen_nego(DisasContext *ctx)
1252 {
1253 gen_op_arith_neg(ctx, 1);
1254 }
1255
1256 /*** Integer logical ***/
1257 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1258 static void glue(gen_, name)(DisasContext *ctx) \
1259 { \
1260 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1261 cpu_gpr[rB(ctx->opcode)]); \
1262 if (unlikely(Rc(ctx->opcode) != 0)) \
1263 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1264 }
1265
1266 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1267 static void glue(gen_, name)(DisasContext *ctx) \
1268 { \
1269 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1270 if (unlikely(Rc(ctx->opcode) != 0)) \
1271 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1272 }
1273
1274 /* and & and. */
1275 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1276 /* andc & andc. */
1277 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1278
1279 /* andi. */
1280 static void gen_andi_(DisasContext *ctx)
1281 {
1282 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1283 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1284 }
1285
1286 /* andis. */
1287 static void gen_andis_(DisasContext *ctx)
1288 {
1289 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1290 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1291 }
1292
1293 /* cntlzw */
1294 static void gen_cntlzw(DisasContext *ctx)
1295 {
1296 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1297 if (unlikely(Rc(ctx->opcode) != 0))
1298 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1299 }
1300 /* eqv & eqv. */
1301 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1302 /* extsb & extsb. */
1303 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1304 /* extsh & extsh. */
1305 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1306 /* nand & nand. */
1307 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1308 /* nor & nor. */
1309 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1310
1311 /* or & or. */
1312 static void gen_or(DisasContext *ctx)
1313 {
1314 int rs, ra, rb;
1315
1316 rs = rS(ctx->opcode);
1317 ra = rA(ctx->opcode);
1318 rb = rB(ctx->opcode);
1319 /* Optimisation for mr. ri case */
1320 if (rs != ra || rs != rb) {
1321 if (rs != rb)
1322 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1323 else
1324 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1325 if (unlikely(Rc(ctx->opcode) != 0))
1326 gen_set_Rc0(ctx, cpu_gpr[ra]);
1327 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1328 gen_set_Rc0(ctx, cpu_gpr[rs]);
1329 #if defined(TARGET_PPC64)
1330 } else {
1331 int prio = 0;
1332
1333 switch (rs) {
1334 case 1:
1335 /* Set process priority to low */
1336 prio = 2;
1337 break;
1338 case 6:
1339 /* Set process priority to medium-low */
1340 prio = 3;
1341 break;
1342 case 2:
1343 /* Set process priority to normal */
1344 prio = 4;
1345 break;
1346 #if !defined(CONFIG_USER_ONLY)
1347 case 31:
1348 if (ctx->mem_idx > 0) {
1349 /* Set process priority to very low */
1350 prio = 1;
1351 }
1352 break;
1353 case 5:
1354 if (ctx->mem_idx > 0) {
1355 /* Set process priority to medium-hight */
1356 prio = 5;
1357 }
1358 break;
1359 case 3:
1360 if (ctx->mem_idx > 0) {
1361 /* Set process priority to high */
1362 prio = 6;
1363 }
1364 break;
1365 case 7:
1366 if (ctx->mem_idx > 1) {
1367 /* Set process priority to very high */
1368 prio = 7;
1369 }
1370 break;
1371 #endif
1372 default:
1373 /* nop */
1374 break;
1375 }
1376 if (prio) {
1377 TCGv t0 = tcg_temp_new();
1378 gen_load_spr(t0, SPR_PPR);
1379 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1380 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1381 gen_store_spr(SPR_PPR, t0);
1382 tcg_temp_free(t0);
1383 }
1384 #endif
1385 }
1386 }
1387 /* orc & orc. */
1388 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1389
1390 /* xor & xor. */
1391 static void gen_xor(DisasContext *ctx)
1392 {
1393 /* Optimisation for "set to zero" case */
1394 if (rS(ctx->opcode) != rB(ctx->opcode))
1395 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1396 else
1397 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1398 if (unlikely(Rc(ctx->opcode) != 0))
1399 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1400 }
1401
1402 /* ori */
1403 static void gen_ori(DisasContext *ctx)
1404 {
1405 target_ulong uimm = UIMM(ctx->opcode);
1406
1407 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1408 /* NOP */
1409 /* XXX: should handle special NOPs for POWER series */
1410 return;
1411 }
1412 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1413 }
1414
1415 /* oris */
1416 static void gen_oris(DisasContext *ctx)
1417 {
1418 target_ulong uimm = UIMM(ctx->opcode);
1419
1420 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1421 /* NOP */
1422 return;
1423 }
1424 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1425 }
1426
1427 /* xori */
1428 static void gen_xori(DisasContext *ctx)
1429 {
1430 target_ulong uimm = UIMM(ctx->opcode);
1431
1432 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1433 /* NOP */
1434 return;
1435 }
1436 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1437 }
1438
1439 /* xoris */
1440 static void gen_xoris(DisasContext *ctx)
1441 {
1442 target_ulong uimm = UIMM(ctx->opcode);
1443
1444 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1445 /* NOP */
1446 return;
1447 }
1448 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1449 }
1450
1451 /* popcntb : PowerPC 2.03 specification */
1452 static void gen_popcntb(DisasContext *ctx)
1453 {
1454 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1455 }
1456
1457 static void gen_popcntw(DisasContext *ctx)
1458 {
1459 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1460 }
1461
1462 #if defined(TARGET_PPC64)
1463 /* popcntd: PowerPC 2.06 specification */
1464 static void gen_popcntd(DisasContext *ctx)
1465 {
1466 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1467 }
1468 #endif
1469
1470 #if defined(TARGET_PPC64)
1471 /* extsw & extsw. */
1472 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1473
1474 /* cntlzd */
1475 static void gen_cntlzd(DisasContext *ctx)
1476 {
1477 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1478 if (unlikely(Rc(ctx->opcode) != 0))
1479 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1480 }
1481 #endif
1482
1483 /*** Integer rotate ***/
1484
1485 /* rlwimi & rlwimi. */
1486 static void gen_rlwimi(DisasContext *ctx)
1487 {
1488 uint32_t mb, me, sh;
1489
1490 mb = MB(ctx->opcode);
1491 me = ME(ctx->opcode);
1492 sh = SH(ctx->opcode);
1493 if (likely(sh == 0 && mb == 0 && me == 31)) {
1494 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1495 } else {
1496 target_ulong mask;
1497 TCGv t1;
1498 TCGv t0 = tcg_temp_new();
1499 #if defined(TARGET_PPC64)
1500 TCGv_i32 t2 = tcg_temp_new_i32();
1501 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1502 tcg_gen_rotli_i32(t2, t2, sh);
1503 tcg_gen_extu_i32_i64(t0, t2);
1504 tcg_temp_free_i32(t2);
1505 #else
1506 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1507 #endif
1508 #if defined(TARGET_PPC64)
1509 mb += 32;
1510 me += 32;
1511 #endif
1512 mask = MASK(mb, me);
1513 t1 = tcg_temp_new();
1514 tcg_gen_andi_tl(t0, t0, mask);
1515 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1516 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1517 tcg_temp_free(t0);
1518 tcg_temp_free(t1);
1519 }
1520 if (unlikely(Rc(ctx->opcode) != 0))
1521 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1522 }
1523
1524 /* rlwinm & rlwinm. */
1525 static void gen_rlwinm(DisasContext *ctx)
1526 {
1527 uint32_t mb, me, sh;
1528
1529 sh = SH(ctx->opcode);
1530 mb = MB(ctx->opcode);
1531 me = ME(ctx->opcode);
1532
1533 if (likely(mb == 0 && me == (31 - sh))) {
1534 if (likely(sh == 0)) {
1535 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1536 } else {
1537 TCGv t0 = tcg_temp_new();
1538 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1539 tcg_gen_shli_tl(t0, t0, sh);
1540 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1541 tcg_temp_free(t0);
1542 }
1543 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1544 TCGv t0 = tcg_temp_new();
1545 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1546 tcg_gen_shri_tl(t0, t0, mb);
1547 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1548 tcg_temp_free(t0);
1549 } else {
1550 TCGv t0 = tcg_temp_new();
1551 #if defined(TARGET_PPC64)
1552 TCGv_i32 t1 = tcg_temp_new_i32();
1553 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1554 tcg_gen_rotli_i32(t1, t1, sh);
1555 tcg_gen_extu_i32_i64(t0, t1);
1556 tcg_temp_free_i32(t1);
1557 #else
1558 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1559 #endif
1560 #if defined(TARGET_PPC64)
1561 mb += 32;
1562 me += 32;
1563 #endif
1564 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1565 tcg_temp_free(t0);
1566 }
1567 if (unlikely(Rc(ctx->opcode) != 0))
1568 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1569 }
1570
1571 /* rlwnm & rlwnm. */
1572 static void gen_rlwnm(DisasContext *ctx)
1573 {
1574 uint32_t mb, me;
1575 TCGv t0;
1576 #if defined(TARGET_PPC64)
1577 TCGv_i32 t1, t2;
1578 #endif
1579
1580 mb = MB(ctx->opcode);
1581 me = ME(ctx->opcode);
1582 t0 = tcg_temp_new();
1583 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1584 #if defined(TARGET_PPC64)
1585 t1 = tcg_temp_new_i32();
1586 t2 = tcg_temp_new_i32();
1587 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1588 tcg_gen_trunc_i64_i32(t2, t0);
1589 tcg_gen_rotl_i32(t1, t1, t2);
1590 tcg_gen_extu_i32_i64(t0, t1);
1591 tcg_temp_free_i32(t1);
1592 tcg_temp_free_i32(t2);
1593 #else
1594 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1595 #endif
1596 if (unlikely(mb != 0 || me != 31)) {
1597 #if defined(TARGET_PPC64)
1598 mb += 32;
1599 me += 32;
1600 #endif
1601 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1602 } else {
1603 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1604 }
1605 tcg_temp_free(t0);
1606 if (unlikely(Rc(ctx->opcode) != 0))
1607 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1608 }
1609
1610 #if defined(TARGET_PPC64)
1611 #define GEN_PPC64_R2(name, opc1, opc2) \
1612 static void glue(gen_, name##0)(DisasContext *ctx) \
1613 { \
1614 gen_##name(ctx, 0); \
1615 } \
1616 \
1617 static void glue(gen_, name##1)(DisasContext *ctx) \
1618 { \
1619 gen_##name(ctx, 1); \
1620 }
1621 #define GEN_PPC64_R4(name, opc1, opc2) \
1622 static void glue(gen_, name##0)(DisasContext *ctx) \
1623 { \
1624 gen_##name(ctx, 0, 0); \
1625 } \
1626 \
1627 static void glue(gen_, name##1)(DisasContext *ctx) \
1628 { \
1629 gen_##name(ctx, 0, 1); \
1630 } \
1631 \
1632 static void glue(gen_, name##2)(DisasContext *ctx) \
1633 { \
1634 gen_##name(ctx, 1, 0); \
1635 } \
1636 \
1637 static void glue(gen_, name##3)(DisasContext *ctx) \
1638 { \
1639 gen_##name(ctx, 1, 1); \
1640 }
1641
1642 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1643 uint32_t sh)
1644 {
1645 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1646 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1647 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1648 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1649 } else {
1650 TCGv t0 = tcg_temp_new();
1651 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1652 if (likely(mb == 0 && me == 63)) {
1653 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1654 } else {
1655 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1656 }
1657 tcg_temp_free(t0);
1658 }
1659 if (unlikely(Rc(ctx->opcode) != 0))
1660 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1661 }
1662 /* rldicl - rldicl. */
1663 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1664 {
1665 uint32_t sh, mb;
1666
1667 sh = SH(ctx->opcode) | (shn << 5);
1668 mb = MB(ctx->opcode) | (mbn << 5);
1669 gen_rldinm(ctx, mb, 63, sh);
1670 }
1671 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1672 /* rldicr - rldicr. */
1673 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1674 {
1675 uint32_t sh, me;
1676
1677 sh = SH(ctx->opcode) | (shn << 5);
1678 me = MB(ctx->opcode) | (men << 5);
1679 gen_rldinm(ctx, 0, me, sh);
1680 }
1681 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1682 /* rldic - rldic. */
1683 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1684 {
1685 uint32_t sh, mb;
1686
1687 sh = SH(ctx->opcode) | (shn << 5);
1688 mb = MB(ctx->opcode) | (mbn << 5);
1689 gen_rldinm(ctx, mb, 63 - sh, sh);
1690 }
1691 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1692
1693 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1694 {
1695 TCGv t0;
1696
1697 mb = MB(ctx->opcode);
1698 me = ME(ctx->opcode);
1699 t0 = tcg_temp_new();
1700 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1701 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1702 if (unlikely(mb != 0 || me != 63)) {
1703 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1704 } else {
1705 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1706 }
1707 tcg_temp_free(t0);
1708 if (unlikely(Rc(ctx->opcode) != 0))
1709 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1710 }
1711
1712 /* rldcl - rldcl. */
1713 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1714 {
1715 uint32_t mb;
1716
1717 mb = MB(ctx->opcode) | (mbn << 5);
1718 gen_rldnm(ctx, mb, 63);
1719 }
1720 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1721 /* rldcr - rldcr. */
1722 static inline void gen_rldcr(DisasContext *ctx, int men)
1723 {
1724 uint32_t me;
1725
1726 me = MB(ctx->opcode) | (men << 5);
1727 gen_rldnm(ctx, 0, me);
1728 }
1729 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1730 /* rldimi - rldimi. */
1731 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1732 {
1733 uint32_t sh, mb, me;
1734
1735 sh = SH(ctx->opcode) | (shn << 5);
1736 mb = MB(ctx->opcode) | (mbn << 5);
1737 me = 63 - sh;
1738 if (unlikely(sh == 0 && mb == 0)) {
1739 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1740 } else {
1741 TCGv t0, t1;
1742 target_ulong mask;
1743
1744 t0 = tcg_temp_new();
1745 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1746 t1 = tcg_temp_new();
1747 mask = MASK(mb, me);
1748 tcg_gen_andi_tl(t0, t0, mask);
1749 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1750 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1751 tcg_temp_free(t0);
1752 tcg_temp_free(t1);
1753 }
1754 if (unlikely(Rc(ctx->opcode) != 0))
1755 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1756 }
1757 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1758 #endif
1759
1760 /*** Integer shift ***/
1761
1762 /* slw & slw. */
1763 static void gen_slw(DisasContext *ctx)
1764 {
1765 TCGv t0, t1;
1766
1767 t0 = tcg_temp_new();
1768 /* AND rS with a mask that is 0 when rB >= 0x20 */
1769 #if defined(TARGET_PPC64)
1770 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1771 tcg_gen_sari_tl(t0, t0, 0x3f);
1772 #else
1773 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1774 tcg_gen_sari_tl(t0, t0, 0x1f);
1775 #endif
1776 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1777 t1 = tcg_temp_new();
1778 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1779 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1780 tcg_temp_free(t1);
1781 tcg_temp_free(t0);
1782 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1783 if (unlikely(Rc(ctx->opcode) != 0))
1784 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1785 }
1786
1787 /* sraw & sraw. */
1788 static void gen_sraw(DisasContext *ctx)
1789 {
1790 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1791 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1792 if (unlikely(Rc(ctx->opcode) != 0))
1793 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1794 }
1795
1796 /* srawi & srawi. */
1797 static void gen_srawi(DisasContext *ctx)
1798 {
1799 int sh = SH(ctx->opcode);
1800 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1801 TCGv src = cpu_gpr[rS(ctx->opcode)];
1802 if (sh == 0) {
1803 tcg_gen_mov_tl(dst, src);
1804 tcg_gen_movi_tl(cpu_ca, 0);
1805 } else {
1806 TCGv t0;
1807 tcg_gen_ext32s_tl(dst, src);
1808 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1809 t0 = tcg_temp_new();
1810 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1811 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1812 tcg_temp_free(t0);
1813 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1814 tcg_gen_sari_tl(dst, dst, sh);
1815 }
1816 if (unlikely(Rc(ctx->opcode) != 0)) {
1817 gen_set_Rc0(ctx, dst);
1818 }
1819 }
1820
1821 /* srw & srw. */
1822 static void gen_srw(DisasContext *ctx)
1823 {
1824 TCGv t0, t1;
1825
1826 t0 = tcg_temp_new();
1827 /* AND rS with a mask that is 0 when rB >= 0x20 */
1828 #if defined(TARGET_PPC64)
1829 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1830 tcg_gen_sari_tl(t0, t0, 0x3f);
1831 #else
1832 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1833 tcg_gen_sari_tl(t0, t0, 0x1f);
1834 #endif
1835 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1836 tcg_gen_ext32u_tl(t0, t0);
1837 t1 = tcg_temp_new();
1838 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1839 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1840 tcg_temp_free(t1);
1841 tcg_temp_free(t0);
1842 if (unlikely(Rc(ctx->opcode) != 0))
1843 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1844 }
1845
1846 #if defined(TARGET_PPC64)
1847 /* sld & sld. */
1848 static void gen_sld(DisasContext *ctx)
1849 {
1850 TCGv t0, t1;
1851
1852 t0 = tcg_temp_new();
1853 /* AND rS with a mask that is 0 when rB >= 0x40 */
1854 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1855 tcg_gen_sari_tl(t0, t0, 0x3f);
1856 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1857 t1 = tcg_temp_new();
1858 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1859 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1860 tcg_temp_free(t1);
1861 tcg_temp_free(t0);
1862 if (unlikely(Rc(ctx->opcode) != 0))
1863 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1864 }
1865
1866 /* srad & srad. */
1867 static void gen_srad(DisasContext *ctx)
1868 {
1869 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1870 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1871 if (unlikely(Rc(ctx->opcode) != 0))
1872 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1873 }
1874 /* sradi & sradi. */
1875 static inline void gen_sradi(DisasContext *ctx, int n)
1876 {
1877 int sh = SH(ctx->opcode) + (n << 5);
1878 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1879 TCGv src = cpu_gpr[rS(ctx->opcode)];
1880 if (sh == 0) {
1881 tcg_gen_mov_tl(dst, src);
1882 tcg_gen_movi_tl(cpu_ca, 0);
1883 } else {
1884 TCGv t0;
1885 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1886 t0 = tcg_temp_new();
1887 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1888 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1889 tcg_temp_free(t0);
1890 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1891 tcg_gen_sari_tl(dst, src, sh);
1892 }
1893 if (unlikely(Rc(ctx->opcode) != 0)) {
1894 gen_set_Rc0(ctx, dst);
1895 }
1896 }
1897
1898 static void gen_sradi0(DisasContext *ctx)
1899 {
1900 gen_sradi(ctx, 0);
1901 }
1902
1903 static void gen_sradi1(DisasContext *ctx)
1904 {
1905 gen_sradi(ctx, 1);
1906 }
1907
1908 /* srd & srd. */
1909 static void gen_srd(DisasContext *ctx)
1910 {
1911 TCGv t0, t1;
1912
1913 t0 = tcg_temp_new();
1914 /* AND rS with a mask that is 0 when rB >= 0x40 */
1915 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1916 tcg_gen_sari_tl(t0, t0, 0x3f);
1917 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1918 t1 = tcg_temp_new();
1919 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1920 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1921 tcg_temp_free(t1);
1922 tcg_temp_free(t0);
1923 if (unlikely(Rc(ctx->opcode) != 0))
1924 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1925 }
1926 #endif
1927
1928 /*** Floating-Point arithmetic ***/
1929 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1930 static void gen_f##name(DisasContext *ctx) \
1931 { \
1932 if (unlikely(!ctx->fpu_enabled)) { \
1933 gen_exception(ctx, POWERPC_EXCP_FPU); \
1934 return; \
1935 } \
1936 /* NIP cannot be restored if the memory exception comes from an helper */ \
1937 gen_update_nip(ctx, ctx->nip - 4); \
1938 gen_reset_fpstatus(); \
1939 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1940 cpu_fpr[rA(ctx->opcode)], \
1941 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1942 if (isfloat) { \
1943 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1944 cpu_fpr[rD(ctx->opcode)]); \
1945 } \
1946 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
1947 Rc(ctx->opcode) != 0); \
1948 }
1949
1950 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1951 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1952 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1953
1954 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1955 static void gen_f##name(DisasContext *ctx) \
1956 { \
1957 if (unlikely(!ctx->fpu_enabled)) { \
1958 gen_exception(ctx, POWERPC_EXCP_FPU); \
1959 return; \
1960 } \
1961 /* NIP cannot be restored if the memory exception comes from an helper */ \
1962 gen_update_nip(ctx, ctx->nip - 4); \
1963 gen_reset_fpstatus(); \
1964 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1965 cpu_fpr[rA(ctx->opcode)], \
1966 cpu_fpr[rB(ctx->opcode)]); \
1967 if (isfloat) { \
1968 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1969 cpu_fpr[rD(ctx->opcode)]); \
1970 } \
1971 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1972 set_fprf, Rc(ctx->opcode) != 0); \
1973 }
1974 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1975 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1976 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1977
1978 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1979 static void gen_f##name(DisasContext *ctx) \
1980 { \
1981 if (unlikely(!ctx->fpu_enabled)) { \
1982 gen_exception(ctx, POWERPC_EXCP_FPU); \
1983 return; \
1984 } \
1985 /* NIP cannot be restored if the memory exception comes from an helper */ \
1986 gen_update_nip(ctx, ctx->nip - 4); \
1987 gen_reset_fpstatus(); \
1988 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1989 cpu_fpr[rA(ctx->opcode)], \
1990 cpu_fpr[rC(ctx->opcode)]); \
1991 if (isfloat) { \
1992 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1993 cpu_fpr[rD(ctx->opcode)]); \
1994 } \
1995 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1996 set_fprf, Rc(ctx->opcode) != 0); \
1997 }
1998 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1999 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2000 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2001
2002 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2003 static void gen_f##name(DisasContext *ctx) \
2004 { \
2005 if (unlikely(!ctx->fpu_enabled)) { \
2006 gen_exception(ctx, POWERPC_EXCP_FPU); \
2007 return; \
2008 } \
2009 /* NIP cannot be restored if the memory exception comes from an helper */ \
2010 gen_update_nip(ctx, ctx->nip - 4); \
2011 gen_reset_fpstatus(); \
2012 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2013 cpu_fpr[rB(ctx->opcode)]); \
2014 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2015 set_fprf, Rc(ctx->opcode) != 0); \
2016 }
2017
2018 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2019 static void gen_f##name(DisasContext *ctx) \
2020 { \
2021 if (unlikely(!ctx->fpu_enabled)) { \
2022 gen_exception(ctx, POWERPC_EXCP_FPU); \
2023 return; \
2024 } \
2025 /* NIP cannot be restored if the memory exception comes from an helper */ \
2026 gen_update_nip(ctx, ctx->nip - 4); \
2027 gen_reset_fpstatus(); \
2028 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2029 cpu_fpr[rB(ctx->opcode)]); \
2030 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2031 set_fprf, Rc(ctx->opcode) != 0); \
2032 }
2033
2034 /* fadd - fadds */
2035 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2036 /* fdiv - fdivs */
2037 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2038 /* fmul - fmuls */
2039 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2040
2041 /* fre */
2042 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2043
2044 /* fres */
2045 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2046
2047 /* frsqrte */
2048 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2049
2050 /* frsqrtes */
2051 static void gen_frsqrtes(DisasContext *ctx)
2052 {
2053 if (unlikely(!ctx->fpu_enabled)) {
2054 gen_exception(ctx, POWERPC_EXCP_FPU);
2055 return;
2056 }
2057 /* NIP cannot be restored if the memory exception comes from an helper */
2058 gen_update_nip(ctx, ctx->nip - 4);
2059 gen_reset_fpstatus();
2060 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2061 cpu_fpr[rB(ctx->opcode)]);
2062 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2063 cpu_fpr[rD(ctx->opcode)]);
2064 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2065 }
2066
2067 /* fsel */
2068 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2069 /* fsub - fsubs */
2070 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2071 /* Optional: */
2072
2073 /* fsqrt */
2074 static void gen_fsqrt(DisasContext *ctx)
2075 {
2076 if (unlikely(!ctx->fpu_enabled)) {
2077 gen_exception(ctx, POWERPC_EXCP_FPU);
2078 return;
2079 }
2080 /* NIP cannot be restored if the memory exception comes from an helper */
2081 gen_update_nip(ctx, ctx->nip - 4);
2082 gen_reset_fpstatus();
2083 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2084 cpu_fpr[rB(ctx->opcode)]);
2085 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2086 }
2087
2088 static void gen_fsqrts(DisasContext *ctx)
2089 {
2090 if (unlikely(!ctx->fpu_enabled)) {
2091 gen_exception(ctx, POWERPC_EXCP_FPU);
2092 return;
2093 }
2094 /* NIP cannot be restored if the memory exception comes from an helper */
2095 gen_update_nip(ctx, ctx->nip - 4);
2096 gen_reset_fpstatus();
2097 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2098 cpu_fpr[rB(ctx->opcode)]);
2099 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2100 cpu_fpr[rD(ctx->opcode)]);
2101 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2102 }
2103
2104 /*** Floating-Point multiply-and-add ***/
2105 /* fmadd - fmadds */
2106 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2107 /* fmsub - fmsubs */
2108 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2109 /* fnmadd - fnmadds */
2110 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2111 /* fnmsub - fnmsubs */
2112 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2113
2114 /*** Floating-Point round & convert ***/
2115 /* fctiw */
2116 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2117 /* fctiwz */
2118 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2119 /* frsp */
2120 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2121 #if defined(TARGET_PPC64)
2122 /* fcfid */
2123 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2124 /* fctid */
2125 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2126 /* fctidz */
2127 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2128 #endif
2129
2130 /* frin */
2131 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2132 /* friz */
2133 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2134 /* frip */
2135 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2136 /* frim */
2137 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2138
2139 /*** Floating-Point compare ***/
2140
2141 /* fcmpo */
2142 static void gen_fcmpo(DisasContext *ctx)
2143 {
2144 TCGv_i32 crf;
2145 if (unlikely(!ctx->fpu_enabled)) {
2146 gen_exception(ctx, POWERPC_EXCP_FPU);
2147 return;
2148 }
2149 /* NIP cannot be restored if the memory exception comes from an helper */
2150 gen_update_nip(ctx, ctx->nip - 4);
2151 gen_reset_fpstatus();
2152 crf = tcg_const_i32(crfD(ctx->opcode));
2153 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2154 cpu_fpr[rB(ctx->opcode)], crf);
2155 tcg_temp_free_i32(crf);
2156 gen_helper_float_check_status(cpu_env);
2157 }
2158
2159 /* fcmpu */
2160 static void gen_fcmpu(DisasContext *ctx)
2161 {
2162 TCGv_i32 crf;
2163 if (unlikely(!ctx->fpu_enabled)) {
2164 gen_exception(ctx, POWERPC_EXCP_FPU);
2165 return;
2166 }
2167 /* NIP cannot be restored if the memory exception comes from an helper */
2168 gen_update_nip(ctx, ctx->nip - 4);
2169 gen_reset_fpstatus();
2170 crf = tcg_const_i32(crfD(ctx->opcode));
2171 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2172 cpu_fpr[rB(ctx->opcode)], crf);
2173 tcg_temp_free_i32(crf);
2174 gen_helper_float_check_status(cpu_env);
2175 }
2176
2177 /*** Floating-point move ***/
2178 /* fabs */
2179 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2180 static void gen_fabs(DisasContext *ctx)
2181 {
2182 if (unlikely(!ctx->fpu_enabled)) {
2183 gen_exception(ctx, POWERPC_EXCP_FPU);
2184 return;
2185 }
2186 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2187 ~(1ULL << 63));
2188 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2189 }
2190
2191 /* fmr - fmr. */
2192 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2193 static void gen_fmr(DisasContext *ctx)
2194 {
2195 if (unlikely(!ctx->fpu_enabled)) {
2196 gen_exception(ctx, POWERPC_EXCP_FPU);
2197 return;
2198 }
2199 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2200 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2201 }
2202
2203 /* fnabs */
2204 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2205 static void gen_fnabs(DisasContext *ctx)
2206 {
2207 if (unlikely(!ctx->fpu_enabled)) {
2208 gen_exception(ctx, POWERPC_EXCP_FPU);
2209 return;
2210 }
2211 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2212 1ULL << 63);
2213 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2214 }
2215
2216 /* fneg */
2217 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2218 static void gen_fneg(DisasContext *ctx)
2219 {
2220 if (unlikely(!ctx->fpu_enabled)) {
2221 gen_exception(ctx, POWERPC_EXCP_FPU);
2222 return;
2223 }
2224 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2225 1ULL << 63);
2226 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2227 }
2228
2229 /*** Floating-Point status & ctrl register ***/
2230
2231 /* mcrfs */
2232 static void gen_mcrfs(DisasContext *ctx)
2233 {
2234 TCGv tmp = tcg_temp_new();
2235 int bfa;
2236
2237 if (unlikely(!ctx->fpu_enabled)) {
2238 gen_exception(ctx, POWERPC_EXCP_FPU);
2239 return;
2240 }
2241 bfa = 4 * (7 - crfS(ctx->opcode));
2242 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2243 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2244 tcg_temp_free(tmp);
2245 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2246 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2247 }
2248
2249 /* mffs */
2250 static void gen_mffs(DisasContext *ctx)
2251 {
2252 if (unlikely(!ctx->fpu_enabled)) {
2253 gen_exception(ctx, POWERPC_EXCP_FPU);
2254 return;
2255 }
2256 gen_reset_fpstatus();
2257 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2258 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2259 }
2260
2261 /* mtfsb0 */
2262 static void gen_mtfsb0(DisasContext *ctx)
2263 {
2264 uint8_t crb;
2265
2266 if (unlikely(!ctx->fpu_enabled)) {
2267 gen_exception(ctx, POWERPC_EXCP_FPU);
2268 return;
2269 }
2270 crb = 31 - crbD(ctx->opcode);
2271 gen_reset_fpstatus();
2272 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2273 TCGv_i32 t0;
2274 /* NIP cannot be restored if the memory exception comes from an helper */
2275 gen_update_nip(ctx, ctx->nip - 4);
2276 t0 = tcg_const_i32(crb);
2277 gen_helper_fpscr_clrbit(cpu_env, t0);
2278 tcg_temp_free_i32(t0);
2279 }
2280 if (unlikely(Rc(ctx->opcode) != 0)) {
2281 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2282 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2283 }
2284 }
2285
2286 /* mtfsb1 */
2287 static void gen_mtfsb1(DisasContext *ctx)
2288 {
2289 uint8_t crb;
2290
2291 if (unlikely(!ctx->fpu_enabled)) {
2292 gen_exception(ctx, POWERPC_EXCP_FPU);
2293 return;
2294 }
2295 crb = 31 - crbD(ctx->opcode);
2296 gen_reset_fpstatus();
2297 /* XXX: we pretend we can only do IEEE floating-point computations */
2298 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2299 TCGv_i32 t0;
2300 /* NIP cannot be restored if the memory exception comes from an helper */
2301 gen_update_nip(ctx, ctx->nip - 4);
2302 t0 = tcg_const_i32(crb);
2303 gen_helper_fpscr_setbit(cpu_env, t0);
2304 tcg_temp_free_i32(t0);
2305 }
2306 if (unlikely(Rc(ctx->opcode) != 0)) {
2307 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2308 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2309 }
2310 /* We can raise a differed exception */
2311 gen_helper_float_check_status(cpu_env);
2312 }
2313
2314 /* mtfsf */
2315 static void gen_mtfsf(DisasContext *ctx)
2316 {
2317 TCGv_i32 t0;
2318 int L = ctx->opcode & 0x02000000;
2319
2320 if (unlikely(!ctx->fpu_enabled)) {
2321 gen_exception(ctx, POWERPC_EXCP_FPU);
2322 return;
2323 }
2324 /* NIP cannot be restored if the memory exception comes from an helper */
2325 gen_update_nip(ctx, ctx->nip - 4);
2326 gen_reset_fpstatus();
2327 if (L)
2328 t0 = tcg_const_i32(0xff);
2329 else
2330 t0 = tcg_const_i32(FM(ctx->opcode));
2331 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2332 tcg_temp_free_i32(t0);
2333 if (unlikely(Rc(ctx->opcode) != 0)) {
2334 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2335 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2336 }
2337 /* We can raise a differed exception */
2338 gen_helper_float_check_status(cpu_env);
2339 }
2340
2341 /* mtfsfi */
2342 static void gen_mtfsfi(DisasContext *ctx)
2343 {
2344 int bf, sh;
2345 TCGv_i64 t0;
2346 TCGv_i32 t1;
2347
2348 if (unlikely(!ctx->fpu_enabled)) {
2349 gen_exception(ctx, POWERPC_EXCP_FPU);
2350 return;
2351 }
2352 bf = crbD(ctx->opcode) >> 2;
2353 sh = 7 - bf;
2354 /* NIP cannot be restored if the memory exception comes from an helper */
2355 gen_update_nip(ctx, ctx->nip - 4);
2356 gen_reset_fpstatus();
2357 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2358 t1 = tcg_const_i32(1 << sh);
2359 gen_helper_store_fpscr(cpu_env, t0, t1);
2360 tcg_temp_free_i64(t0);
2361 tcg_temp_free_i32(t1);
2362 if (unlikely(Rc(ctx->opcode) != 0)) {
2363 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2364 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2365 }
2366 /* We can raise a differed exception */
2367 gen_helper_float_check_status(cpu_env);
2368 }
2369
2370 /*** Addressing modes ***/
2371 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2372 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2373 target_long maskl)
2374 {
2375 target_long simm = SIMM(ctx->opcode);
2376
2377 simm &= ~maskl;
2378 if (rA(ctx->opcode) == 0) {
2379 if (NARROW_MODE(ctx)) {
2380 simm = (uint32_t)simm;
2381 }
2382 tcg_gen_movi_tl(EA, simm);
2383 } else if (likely(simm != 0)) {
2384 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2385 if (NARROW_MODE(ctx)) {
2386 tcg_gen_ext32u_tl(EA, EA);
2387 }
2388 } else {
2389 if (NARROW_MODE(ctx)) {
2390 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2391 } else {
2392 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2393 }
2394 }
2395 }
2396
2397 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2398 {
2399 if (rA(ctx->opcode) == 0) {
2400 if (NARROW_MODE(ctx)) {
2401 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2402 } else {
2403 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2404 }
2405 } else {
2406 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2407 if (NARROW_MODE(ctx)) {
2408 tcg_gen_ext32u_tl(EA, EA);
2409 }
2410 }
2411 }
2412
2413 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2414 {
2415 if (rA(ctx->opcode) == 0) {
2416 tcg_gen_movi_tl(EA, 0);
2417 } else if (NARROW_MODE(ctx)) {
2418 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2419 } else {
2420 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2421 }
2422 }
2423
2424 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2425 target_long val)
2426 {
2427 tcg_gen_addi_tl(ret, arg1, val);
2428 if (NARROW_MODE(ctx)) {
2429 tcg_gen_ext32u_tl(ret, ret);
2430 }
2431 }
2432
2433 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2434 {
2435 int l1 = gen_new_label();
2436 TCGv t0 = tcg_temp_new();
2437 TCGv_i32 t1, t2;
2438 /* NIP cannot be restored if the memory exception comes from an helper */
2439 gen_update_nip(ctx, ctx->nip - 4);
2440 tcg_gen_andi_tl(t0, EA, mask);
2441 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2442 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2443 t2 = tcg_const_i32(0);
2444 gen_helper_raise_exception_err(cpu_env, t1, t2);
2445 tcg_temp_free_i32(t1);
2446 tcg_temp_free_i32(t2);
2447 gen_set_label(l1);
2448 tcg_temp_free(t0);
2449 }
2450
2451 /*** Integer load ***/
2452 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2453 {
2454 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2455 }
2456
2457 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2458 {
2459 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2460 }
2461
2462 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2463 {
2464 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2465 if (unlikely(ctx->le_mode)) {
2466 tcg_gen_bswap16_tl(arg1, arg1);
2467 }
2468 }
2469
2470 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2471 {
2472 if (unlikely(ctx->le_mode)) {
2473 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2474 tcg_gen_bswap16_tl(arg1, arg1);
2475 tcg_gen_ext16s_tl(arg1, arg1);
2476 } else {
2477 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2478 }
2479 }
2480
2481 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2482 {
2483 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2484 if (unlikely(ctx->le_mode)) {
2485 tcg_gen_bswap32_tl(arg1, arg1);
2486 }
2487 }
2488
2489 #if defined(TARGET_PPC64)
2490 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2491 {
2492 if (unlikely(ctx->le_mode)) {
2493 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2494 tcg_gen_bswap32_tl(arg1, arg1);
2495 tcg_gen_ext32s_tl(arg1, arg1);
2496 } else
2497 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2498 }
2499 #endif
2500
2501 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2502 {
2503 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2504 if (unlikely(ctx->le_mode)) {
2505 tcg_gen_bswap64_i64(arg1, arg1);
2506 }
2507 }
2508
2509 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2510 {
2511 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2512 }
2513
2514 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2515 {
2516 if (unlikely(ctx->le_mode)) {
2517 TCGv t0 = tcg_temp_new();
2518 tcg_gen_ext16u_tl(t0, arg1);
2519 tcg_gen_bswap16_tl(t0, t0);
2520 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2521 tcg_temp_free(t0);
2522 } else {
2523 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2524 }
2525 }
2526
2527 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2528 {
2529 if (unlikely(ctx->le_mode)) {
2530 TCGv t0 = tcg_temp_new();
2531 tcg_gen_ext32u_tl(t0, arg1);
2532 tcg_gen_bswap32_tl(t0, t0);
2533 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2534 tcg_temp_free(t0);
2535 } else {
2536 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2537 }
2538 }
2539
2540 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2541 {
2542 if (unlikely(ctx->le_mode)) {
2543 TCGv_i64 t0 = tcg_temp_new_i64();
2544 tcg_gen_bswap64_i64(t0, arg1);
2545 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2546 tcg_temp_free_i64(t0);
2547 } else
2548 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2549 }
2550
2551 #define GEN_LD(name, ldop, opc, type) \
2552 static void glue(gen_, name)(DisasContext *ctx) \
2553 { \
2554 TCGv EA; \
2555 gen_set_access_type(ctx, ACCESS_INT); \
2556 EA = tcg_temp_new(); \
2557 gen_addr_imm_index(ctx, EA, 0); \
2558 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2559 tcg_temp_free(EA); \
2560 }
2561
2562 #define GEN_LDU(name, ldop, opc, type) \
2563 static void glue(gen_, name##u)(DisasContext *ctx) \
2564 { \
2565 TCGv EA; \
2566 if (unlikely(rA(ctx->opcode) == 0 || \
2567 rA(ctx->opcode) == rD(ctx->opcode))) { \
2568 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2569 return; \
2570 } \
2571 gen_set_access_type(ctx, ACCESS_INT); \
2572 EA = tcg_temp_new(); \
2573 if (type == PPC_64B) \
2574 gen_addr_imm_index(ctx, EA, 0x03); \
2575 else \
2576 gen_addr_imm_index(ctx, EA, 0); \
2577 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2578 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2579 tcg_temp_free(EA); \
2580 }
2581
2582 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2583 static void glue(gen_, name##ux)(DisasContext *ctx) \
2584 { \
2585 TCGv EA; \
2586 if (unlikely(rA(ctx->opcode) == 0 || \
2587 rA(ctx->opcode) == rD(ctx->opcode))) { \
2588 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2589 return; \
2590 } \
2591 gen_set_access_type(ctx, ACCESS_INT); \
2592 EA = tcg_temp_new(); \
2593 gen_addr_reg_index(ctx, EA); \
2594 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2595 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2596 tcg_temp_free(EA); \
2597 }
2598
2599 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2600 static void glue(gen_, name##x)(DisasContext *ctx) \
2601 { \
2602 TCGv EA; \
2603 gen_set_access_type(ctx, ACCESS_INT); \
2604 EA = tcg_temp_new(); \
2605 gen_addr_reg_index(ctx, EA); \
2606 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2607 tcg_temp_free(EA); \
2608 }
2609 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2610 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2611
2612 #define GEN_LDS(name, ldop, op, type) \
2613 GEN_LD(name, ldop, op | 0x20, type); \
2614 GEN_LDU(name, ldop, op | 0x21, type); \
2615 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2616 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2617
2618 /* lbz lbzu lbzux lbzx */
2619 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2620 /* lha lhau lhaux lhax */
2621 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2622 /* lhz lhzu lhzux lhzx */
2623 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2624 /* lwz lwzu lwzux lwzx */
2625 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2626 #if defined(TARGET_PPC64)
2627 /* lwaux */
2628 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2629 /* lwax */
2630 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2631 /* ldux */
2632 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2633 /* ldx */
2634 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2635
2636 static void gen_ld(DisasContext *ctx)
2637 {
2638 TCGv EA;
2639 if (Rc(ctx->opcode)) {
2640 if (unlikely(rA(ctx->opcode) == 0 ||
2641 rA(ctx->opcode) == rD(ctx->opcode))) {
2642 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2643 return;
2644 }
2645 }
2646 gen_set_access_type(ctx, ACCESS_INT);
2647 EA = tcg_temp_new();
2648 gen_addr_imm_index(ctx, EA, 0x03);
2649 if (ctx->opcode & 0x02) {
2650 /* lwa (lwau is undefined) */
2651 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2652 } else {
2653 /* ld - ldu */
2654 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2655 }
2656 if (Rc(ctx->opcode))
2657 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2658 tcg_temp_free(EA);
2659 }
2660
2661 /* lq */
2662 static void gen_lq(DisasContext *ctx)
2663 {
2664 #if defined(CONFIG_USER_ONLY)
2665 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2666 #else
2667 int ra, rd;
2668 TCGv EA;
2669
2670 /* Restore CPU state */
2671 if (unlikely(ctx->mem_idx == 0)) {
2672 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2673 return;
2674 }
2675 ra = rA(ctx->opcode);
2676 rd = rD(ctx->opcode);
2677 if (unlikely((rd & 1) || rd == ra)) {
2678 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2679 return;
2680 }
2681 if (unlikely(ctx->le_mode)) {
2682 /* Little-endian mode is not handled */
2683 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2684 return;
2685 }
2686 gen_set_access_type(ctx, ACCESS_INT);
2687 EA = tcg_temp_new();
2688 gen_addr_imm_index(ctx, EA, 0x0F);
2689 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2690 gen_addr_add(ctx, EA, EA, 8);
2691 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2692 tcg_temp_free(EA);
2693 #endif
2694 }
2695 #endif
2696
2697 /*** Integer store ***/
2698 #define GEN_ST(name, stop, opc, type) \
2699 static void glue(gen_, name)(DisasContext *ctx) \
2700 { \
2701 TCGv EA; \
2702 gen_set_access_type(ctx, ACCESS_INT); \
2703 EA = tcg_temp_new(); \
2704 gen_addr_imm_index(ctx, EA, 0); \
2705 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2706 tcg_temp_free(EA); \
2707 }
2708
2709 #define GEN_STU(name, stop, opc, type) \
2710 static void glue(gen_, stop##u)(DisasContext *ctx) \
2711 { \
2712 TCGv EA; \
2713 if (unlikely(rA(ctx->opcode) == 0)) { \
2714 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2715 return; \
2716 } \
2717 gen_set_access_type(ctx, ACCESS_INT); \
2718 EA = tcg_temp_new(); \
2719 if (type == PPC_64B) \
2720 gen_addr_imm_index(ctx, EA, 0x03); \
2721 else \
2722 gen_addr_imm_index(ctx, EA, 0); \
2723 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2724 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2725 tcg_temp_free(EA); \
2726 }
2727
2728 #define GEN_STUX(name, stop, opc2, opc3, type) \
2729 static void glue(gen_, name##ux)(DisasContext *ctx) \
2730 { \
2731 TCGv EA; \
2732 if (unlikely(rA(ctx->opcode) == 0)) { \
2733 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2734 return; \
2735 } \
2736 gen_set_access_type(ctx, ACCESS_INT); \
2737 EA = tcg_temp_new(); \
2738 gen_addr_reg_index(ctx, EA); \
2739 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2740 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2741 tcg_temp_free(EA); \
2742 }
2743
2744 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2745 static void glue(gen_, name##x)(DisasContext *ctx) \
2746 { \
2747 TCGv EA; \
2748 gen_set_access_type(ctx, ACCESS_INT); \
2749 EA = tcg_temp_new(); \
2750 gen_addr_reg_index(ctx, EA); \
2751 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2752 tcg_temp_free(EA); \
2753 }
2754 #define GEN_STX(name, stop, opc2, opc3, type) \
2755 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2756
2757 #define GEN_STS(name, stop, op, type) \
2758 GEN_ST(name, stop, op | 0x20, type); \
2759 GEN_STU(name, stop, op | 0x21, type); \
2760 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2761 GEN_STX(name, stop, 0x17, op | 0x00, type)
2762
2763 /* stb stbu stbux stbx */
2764 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2765 /* sth sthu sthux sthx */
2766 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2767 /* stw stwu stwux stwx */
2768 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2769 #if defined(TARGET_PPC64)
2770 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2771 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2772
2773 static void gen_std(DisasContext *ctx)
2774 {
2775 int rs;
2776 TCGv EA;
2777
2778 rs = rS(ctx->opcode);
2779 if ((ctx->opcode & 0x3) == 0x2) {
2780 #if defined(CONFIG_USER_ONLY)
2781 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2782 #else
2783 /* stq */
2784 if (unlikely(ctx->mem_idx == 0)) {
2785 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2786 return;
2787 }
2788 if (unlikely(rs & 1)) {
2789 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2790 return;
2791 }
2792 if (unlikely(ctx->le_mode)) {
2793 /* Little-endian mode is not handled */
2794 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2795 return;
2796 }
2797 gen_set_access_type(ctx, ACCESS_INT);
2798 EA = tcg_temp_new();
2799 gen_addr_imm_index(ctx, EA, 0x03);
2800 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2801 gen_addr_add(ctx, EA, EA, 8);
2802 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2803 tcg_temp_free(EA);
2804 #endif
2805 } else {
2806 /* std / stdu */
2807 if (Rc(ctx->opcode)) {
2808 if (unlikely(rA(ctx->opcode) == 0)) {
2809 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2810 return;
2811 }
2812 }
2813 gen_set_access_type(ctx, ACCESS_INT);
2814 EA = tcg_temp_new();
2815 gen_addr_imm_index(ctx, EA, 0x03);
2816 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2817 if (Rc(ctx->opcode))
2818 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2819 tcg_temp_free(EA);
2820 }
2821 }
2822 #endif
2823 /*** Integer load and store with byte reverse ***/
2824 /* lhbrx */
2825 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2826 {
2827 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2828 if (likely(!ctx->le_mode)) {
2829 tcg_gen_bswap16_tl(arg1, arg1);
2830 }
2831 }
2832 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2833
2834 /* lwbrx */
2835 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2836 {
2837 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2838 if (likely(!ctx->le_mode)) {
2839 tcg_gen_bswap32_tl(arg1, arg1);
2840 }
2841 }
2842 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2843
2844 #if defined(TARGET_PPC64)
2845 /* ldbrx */
2846 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2847 {
2848 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2849 if (likely(!ctx->le_mode)) {
2850 tcg_gen_bswap64_tl(arg1, arg1);
2851 }
2852 }
2853 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2854 #endif /* TARGET_PPC64 */
2855
2856 /* sthbrx */
2857 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2858 {
2859 if (likely(!ctx->le_mode)) {
2860 TCGv t0 = tcg_temp_new();
2861 tcg_gen_ext16u_tl(t0, arg1);
2862 tcg_gen_bswap16_tl(t0, t0);
2863 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2864 tcg_temp_free(t0);
2865 } else {
2866 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2867 }
2868 }
2869 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2870
2871 /* stwbrx */
2872 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2873 {
2874 if (likely(!ctx->le_mode)) {
2875 TCGv t0 = tcg_temp_new();
2876 tcg_gen_ext32u_tl(t0, arg1);
2877 tcg_gen_bswap32_tl(t0, t0);
2878 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2879 tcg_temp_free(t0);
2880 } else {
2881 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2882 }
2883 }
2884 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2885
2886 #if defined(TARGET_PPC64)
2887 /* stdbrx */
2888 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2889 {
2890 if (likely(!ctx->le_mode)) {
2891 TCGv t0 = tcg_temp_new();
2892 tcg_gen_bswap64_tl(t0, arg1);
2893 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2894 tcg_temp_free(t0);
2895 } else {
2896 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2897 }
2898 }
2899 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2900 #endif /* TARGET_PPC64 */
2901
2902 /*** Integer load and store multiple ***/
2903
2904 /* lmw */
2905 static void gen_lmw(DisasContext *ctx)
2906 {
2907 TCGv t0;
2908 TCGv_i32 t1;
2909 gen_set_access_type(ctx, ACCESS_INT);
2910 /* NIP cannot be restored if the memory exception comes from an helper */
2911 gen_update_nip(ctx, ctx->nip - 4);
2912 t0 = tcg_temp_new();
2913 t1 = tcg_const_i32(rD(ctx->opcode));
2914 gen_addr_imm_index(ctx, t0, 0);
2915 gen_helper_lmw(cpu_env, t0, t1);
2916 tcg_temp_free(t0);
2917 tcg_temp_free_i32(t1);
2918 }
2919
2920 /* stmw */
2921 static void gen_stmw(DisasContext *ctx)
2922 {
2923 TCGv t0;
2924 TCGv_i32 t1;
2925 gen_set_access_type(ctx, ACCESS_INT);
2926 /* NIP cannot be restored if the memory exception comes from an helper */
2927 gen_update_nip(ctx, ctx->nip - 4);
2928 t0 = tcg_temp_new();
2929 t1 = tcg_const_i32(rS(ctx->opcode));
2930 gen_addr_imm_index(ctx, t0, 0);
2931 gen_helper_stmw(cpu_env, t0, t1);
2932 tcg_temp_free(t0);
2933 tcg_temp_free_i32(t1);
2934 }
2935
2936 /*** Integer load and store strings ***/
2937
2938 /* lswi */
2939 /* PowerPC32 specification says we must generate an exception if
2940 * rA is in the range of registers to be loaded.
2941 * In an other hand, IBM says this is valid, but rA won't be loaded.
2942 * For now, I'll follow the spec...
2943 */
2944 static void gen_lswi(DisasContext *ctx)
2945 {
2946 TCGv t0;
2947 TCGv_i32 t1, t2;
2948 int nb = NB(ctx->opcode);
2949 int start = rD(ctx->opcode);
2950 int ra = rA(ctx->opcode);
2951 int nr;
2952
2953 if (nb == 0)
2954 nb = 32;
2955 nr = nb / 4;
2956 if (unlikely(((start + nr) > 32 &&
2957 start <= ra && (start + nr - 32) > ra) ||
2958 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2959 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2960 return;
2961 }
2962 gen_set_access_type(ctx, ACCESS_INT);
2963 /* NIP cannot be restored if the memory exception comes from an helper */
2964 gen_update_nip(ctx, ctx->nip - 4);
2965 t0 = tcg_temp_new();
2966 gen_addr_register(ctx, t0);
2967 t1 = tcg_const_i32(nb);
2968 t2 = tcg_const_i32(start);
2969 gen_helper_lsw(cpu_env, t0, t1, t2);
2970 tcg_temp_free(t0);
2971 tcg_temp_free_i32(t1);
2972 tcg_temp_free_i32(t2);
2973 }
2974
2975 /* lswx */
2976 static void gen_lswx(DisasContext *ctx)
2977 {
2978 TCGv t0;
2979 TCGv_i32 t1, t2, t3;
2980 gen_set_access_type(ctx, ACCESS_INT);
2981 /* NIP cannot be restored if the memory exception comes from an helper */
2982 gen_update_nip(ctx, ctx->nip - 4);
2983 t0 = tcg_temp_new();
2984 gen_addr_reg_index(ctx, t0);
2985 t1 = tcg_const_i32(rD(ctx->opcode));
2986 t2 = tcg_const_i32(rA(ctx->opcode));
2987 t3 = tcg_const_i32(rB(ctx->opcode));
2988 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2989 tcg_temp_free(t0);
2990 tcg_temp_free_i32(t1);
2991 tcg_temp_free_i32(t2);
2992 tcg_temp_free_i32(t3);
2993 }
2994
2995 /* stswi */
2996 static void gen_stswi(DisasContext *ctx)
2997 {
2998 TCGv t0;
2999 TCGv_i32 t1, t2;
3000 int nb = NB(ctx->opcode);
3001 gen_set_access_type(ctx, ACCESS_INT);
3002 /* NIP cannot be restored if the memory exception comes from an helper */
3003 gen_update_nip(ctx, ctx->nip - 4);
3004 t0 = tcg_temp_new();
3005 gen_addr_register(ctx, t0);
3006 if (nb == 0)
3007 nb = 32;
3008 t1 = tcg_const_i32(nb);
3009 t2 = tcg_const_i32(rS(ctx->opcode));
3010 gen_helper_stsw(cpu_env, t0, t1, t2);
3011 tcg_temp_free(t0);
3012 tcg_temp_free_i32(t1);
3013 tcg_temp_free_i32(t2);
3014 }
3015
3016 /* stswx */
3017 static void gen_stswx(DisasContext *ctx)
3018 {
3019 TCGv t0;
3020 TCGv_i32 t1, t2;
3021 gen_set_access_type(ctx, ACCESS_INT);
3022 /* NIP cannot be restored if the memory exception comes from an helper */
3023 gen_update_nip(ctx, ctx->nip - 4);
3024 t0 = tcg_temp_new();
3025 gen_addr_reg_index(ctx, t0);
3026 t1 = tcg_temp_new_i32();
3027 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3028 tcg_gen_andi_i32(t1, t1, 0x7F);
3029 t2 = tcg_const_i32(rS(ctx->opcode));
3030 gen_helper_stsw(cpu_env, t0, t1, t2);
3031 tcg_temp_free(t0);
3032 tcg_temp_free_i32(t1);
3033 tcg_temp_free_i32(t2);
3034 }
3035
3036 /*** Memory synchronisation ***/
3037 /* eieio */
3038 static void gen_eieio(DisasContext *ctx)
3039 {
3040 }
3041
3042 /* isync */
3043 static void gen_isync(DisasContext *ctx)
3044 {
3045 gen_stop_exception(ctx);
3046 }
3047
3048 /* lwarx */
3049 static void gen_lwarx(DisasContext *ctx)
3050 {
3051 TCGv t0;
3052 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3053 gen_set_access_type(ctx, ACCESS_RES);
3054 t0 = tcg_temp_local_new();
3055 gen_addr_reg_index(ctx, t0);
3056 gen_check_align(ctx, t0, 0x03);
3057 gen_qemu_ld32u(ctx, gpr, t0);
3058 tcg_gen_mov_tl(cpu_reserve, t0);
3059 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3060 tcg_temp_free(t0);
3061 }
3062
3063 #if defined(CONFIG_USER_ONLY)
3064 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3065 int reg, int size)
3066 {
3067 TCGv t0 = tcg_temp_new();
3068 uint32_t save_exception = ctx->exception;
3069
3070 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3071 tcg_gen_movi_tl(t0, (size << 5) | reg);
3072 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3073 tcg_temp_free(t0);
3074 gen_update_nip(ctx, ctx->nip-4);
3075 ctx->exception = POWERPC_EXCP_BRANCH;
3076 gen_exception(ctx, POWERPC_EXCP_STCX);
3077 ctx->exception = save_exception;
3078 }
3079 #endif
3080
3081 /* stwcx. */
3082 static void gen_stwcx_(DisasContext *ctx)
3083 {
3084 TCGv t0;
3085 gen_set_access_type(ctx, ACCESS_RES);
3086 t0 = tcg_temp_local_new();
3087 gen_addr_reg_index(ctx, t0);
3088 gen_check_align(ctx, t0, 0x03);
3089 #if defined(CONFIG_USER_ONLY)
3090 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3091 #else
3092 {
3093 int l1;
3094
3095 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3096 l1 = gen_new_label();
3097 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3098 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3099 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3100 gen_set_label(l1);
3101 tcg_gen_movi_tl(cpu_reserve, -1);
3102 }
3103 #endif
3104 tcg_temp_free(t0);
3105 }
3106
3107 #if defined(TARGET_PPC64)
3108 /* ldarx */
3109 static void gen_ldarx(DisasContext *ctx)
3110 {
3111 TCGv t0;
3112 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3113 gen_set_access_type(ctx, ACCESS_RES);
3114 t0 = tcg_temp_local_new();
3115 gen_addr_reg_index(ctx, t0);
3116 gen_check_align(ctx, t0, 0x07);
3117 gen_qemu_ld64(ctx, gpr, t0);
3118 tcg_gen_mov_tl(cpu_reserve, t0);
3119 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3120 tcg_temp_free(t0);
3121 }
3122
3123 /* stdcx. */
3124 static void gen_stdcx_(DisasContext *ctx)
3125 {
3126 TCGv t0;
3127 gen_set_access_type(ctx, ACCESS_RES);
3128 t0 = tcg_temp_local_new();
3129 gen_addr_reg_index(ctx, t0);
3130 gen_check_align(ctx, t0, 0x07);
3131 #if defined(CONFIG_USER_ONLY)
3132 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3133 #else
3134 {
3135 int l1;
3136 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3137 l1 = gen_new_label();
3138 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3139 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3140 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3141 gen_set_label(l1);
3142 tcg_gen_movi_tl(cpu_reserve, -1);
3143 }
3144 #endif
3145 tcg_temp_free(t0);
3146 }
3147 #endif /* defined(TARGET_PPC64) */
3148
3149 /* sync */
3150 static void gen_sync(DisasContext *ctx)
3151 {
3152 }
3153
3154 /* wait */
3155 static void gen_wait(DisasContext *ctx)
3156 {
3157 TCGv_i32 t0 = tcg_temp_new_i32();
3158 tcg_gen_st_i32(t0, cpu_env,
3159 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3160 tcg_temp_free_i32(t0);
3161 /* Stop translation, as the CPU is supposed to sleep from now */
3162 gen_exception_err(ctx, EXCP_HLT, 1);
3163 }
3164
3165 /*** Floating-point load ***/
3166 #define GEN_LDF(name, ldop, opc, type) \
3167 static void glue(gen_, name)(DisasContext *ctx) \
3168 { \
3169 TCGv EA; \
3170 if (unlikely(!ctx->fpu_enabled)) { \
3171 gen_exception(ctx, POWERPC_EXCP_FPU); \
3172 return; \
3173 } \
3174 gen_set_access_type(ctx, ACCESS_FLOAT); \
3175 EA = tcg_temp_new(); \
3176 gen_addr_imm_index(ctx, EA, 0); \
3177 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3178 tcg_temp_free(EA); \
3179 }
3180
3181 #define GEN_LDUF(name, ldop, opc, type) \
3182 static void glue(gen_, name##u)(DisasContext *ctx) \
3183 { \
3184 TCGv EA; \
3185 if (unlikely(!ctx->fpu_enabled)) { \
3186 gen_exception(ctx, POWERPC_EXCP_FPU); \
3187 return; \
3188 } \
3189 if (unlikely(rA(ctx->opcode) == 0)) { \
3190 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3191 return; \
3192 } \
3193 gen_set_access_type(ctx, ACCESS_FLOAT); \
3194 EA = tcg_temp_new(); \
3195 gen_addr_imm_index(ctx, EA, 0); \
3196 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3197 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3198 tcg_temp_free(EA); \
3199 }
3200
3201 #define GEN_LDUXF(name, ldop, opc, type) \
3202 static void glue(gen_, name##ux)(DisasContext *ctx) \
3203 { \
3204 TCGv EA; \
3205 if (unlikely(!ctx->fpu_enabled)) { \
3206 gen_exception(ctx, POWERPC_EXCP_FPU); \
3207 return; \
3208 } \
3209 if (unlikely(rA(ctx->opcode) == 0)) { \
3210 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3211 return; \
3212 } \
3213 gen_set_access_type(ctx, ACCESS_FLOAT); \
3214 EA = tcg_temp_new(); \
3215 gen_addr_reg_index(ctx, EA); \
3216 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3217 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3218 tcg_temp_free(EA); \
3219 }
3220
3221 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3222 static void glue(gen_, name##x)(DisasContext *ctx) \
3223 { \
3224 TCGv EA; \
3225 if (unlikely(!ctx->fpu_enabled)) { \
3226 gen_exception(ctx, POWERPC_EXCP_FPU); \
3227 return; \
3228 } \
3229 gen_set_access_type(ctx, ACCESS_FLOAT); \
3230 EA = tcg_temp_new(); \
3231 gen_addr_reg_index(ctx, EA); \
3232 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3233 tcg_temp_free(EA); \
3234 }
3235
3236 #define GEN_LDFS(name, ldop, op, type) \
3237 GEN_LDF(name, ldop, op | 0x20, type); \
3238 GEN_LDUF(name, ldop, op | 0x21, type); \
3239 GEN_LDUXF(name, ldop, op | 0x01, type); \
3240 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3241
3242 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3243 {
3244 TCGv t0 = tcg_temp_new();
3245 TCGv_i32 t1 = tcg_temp_new_i32();
3246 gen_qemu_ld32u(ctx, t0, arg2);
3247 tcg_gen_trunc_tl_i32(t1, t0);
3248 tcg_temp_free(t0);
3249 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3250 tcg_temp_free_i32(t1);
3251 }
3252
3253 /* lfd lfdu lfdux lfdx */
3254 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3255 /* lfs lfsu lfsux lfsx */
3256 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3257
3258 /*** Floating-point store ***/
3259 #define GEN_STF(name, stop, opc, type) \
3260 static void glue(gen_, name)(DisasContext *ctx) \
3261 { \
3262 TCGv EA; \
3263 if (unlikely(!ctx->fpu_enabled)) { \
3264 gen_exception(ctx, POWERPC_EXCP_FPU); \
3265 return; \
3266 } \
3267 gen_set_access_type(ctx, ACCESS_FLOAT); \
3268 EA = tcg_temp_new(); \
3269 gen_addr_imm_index(ctx, EA, 0); \
3270 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3271 tcg_temp_free(EA); \
3272 }
3273
3274 #define GEN_STUF(name, stop, opc, type) \
3275 static void glue(gen_, name##u)(DisasContext *ctx) \
3276 { \
3277 TCGv EA; \
3278 if (unlikely(!ctx->fpu_enabled)) { \
3279 gen_exception(ctx, POWERPC_EXCP_FPU); \
3280 return; \
3281 } \
3282 if (unlikely(rA(ctx->opcode) == 0)) { \
3283 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3284 return; \
3285 } \
3286 gen_set_access_type(ctx, ACCESS_FLOAT); \
3287 EA = tcg_temp_new(); \
3288 gen_addr_imm_index(ctx, EA, 0); \
3289 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3290 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3291 tcg_temp_free(EA); \
3292 }
3293
3294 #define GEN_STUXF(name, stop, opc, type) \
3295 static void glue(gen_, name##ux)(DisasContext *ctx) \
3296 { \
3297 TCGv EA; \
3298 if (unlikely(!ctx->fpu_enabled)) { \
3299 gen_exception(ctx, POWERPC_EXCP_FPU); \
3300 return; \
3301 } \
3302 if (unlikely(rA(ctx->opcode) == 0)) { \
3303 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3304 return; \
3305 } \
3306 gen_set_access_type(ctx, ACCESS_FLOAT); \
3307 EA = tcg_temp_new(); \
3308 gen_addr_reg_index(ctx, EA); \
3309 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3310 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3311 tcg_temp_free(EA); \
3312 }
3313
3314 #define GEN_STXF(name, stop, opc2, opc3, type) \
3315 static void glue(gen_, name##x)(DisasContext *ctx) \
3316 { \
3317 TCGv EA; \
3318 if (unlikely(!ctx->fpu_enabled)) { \
3319 gen_exception(ctx, POWERPC_EXCP_FPU); \
3320 return; \
3321 } \
3322 gen_set_access_type(ctx, ACCESS_FLOAT); \
3323 EA = tcg_temp_new(); \
3324 gen_addr_reg_index(ctx, EA); \
3325 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3326 tcg_temp_free(EA); \
3327 }
3328
3329 #define GEN_STFS(name, stop, op, type) \
3330 GEN_STF(name, stop, op | 0x20, type); \
3331 GEN_STUF(name, stop, op | 0x21, type); \
3332 GEN_STUXF(name, stop, op | 0x01, type); \
3333 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3334
3335 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3336 {
3337 TCGv_i32 t0 = tcg_temp_new_i32();
3338 TCGv t1 = tcg_temp_new();
3339 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3340 tcg_gen_extu_i32_tl(t1, t0);
3341 tcg_temp_free_i32(t0);
3342 gen_qemu_st32(ctx, t1, arg2);
3343 tcg_temp_free(t1);
3344 }
3345
3346 /* stfd stfdu stfdux stfdx */
3347 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3348 /* stfs stfsu stfsux stfsx */
3349 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3350
3351 /* Optional: */
3352 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3353 {
3354 TCGv t0 = tcg_temp_new();
3355 tcg_gen_trunc_i64_tl(t0, arg1),
3356 gen_qemu_st32(ctx, t0, arg2);
3357 tcg_temp_free(t0);
3358 }
3359 /* stfiwx */
3360 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3361
3362 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3363 {
3364 #if defined(TARGET_PPC64)
3365 if (ctx->has_cfar)
3366 tcg_gen_movi_tl(cpu_cfar, nip);
3367 #endif
3368 }
3369
3370 /*** Branch ***/
3371 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3372 {
3373 TranslationBlock *tb;
3374 tb = ctx->tb;
3375 if (NARROW_MODE(ctx)) {
3376 dest = (uint32_t) dest;
3377 }
3378 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3379 likely(!ctx->singlestep_enabled)) {
3380 tcg_gen_goto_tb(n);
3381 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3382 tcg_gen_exit_tb((tcg_target_long)tb + n);
3383 } else {
3384 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3385 if (unlikely(ctx->singlestep_enabled)) {
3386 if ((ctx->singlestep_enabled &
3387 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3388 (ctx->exception == POWERPC_EXCP_BRANCH ||
3389 ctx->exception == POWERPC_EXCP_TRACE)) {
3390 target_ulong tmp = ctx->nip;
3391 ctx->nip = dest;
3392 gen_exception(ctx, POWERPC_EXCP_TRACE);
3393 ctx->nip = tmp;
3394 }
3395 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3396 gen_debug_exception(ctx);
3397 }
3398 }
3399 tcg_gen_exit_tb(0);
3400 }
3401 }
3402
3403 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3404 {
3405 if (NARROW_MODE(ctx)) {
3406 nip = (uint32_t)nip;
3407 }
3408 tcg_gen_movi_tl(cpu_lr, nip);
3409 }
3410
3411 /* b ba bl bla */
3412 static void gen_b(DisasContext *ctx)
3413 {
3414 target_ulong li, target;
3415
3416 ctx->exception = POWERPC_EXCP_BRANCH;
3417 /* sign extend LI */
3418 li = LI(ctx->opcode);
3419 li = (li ^ 0x02000000) - 0x02000000;
3420 if (likely(AA(ctx->opcode) == 0)) {
3421 target = ctx->nip + li - 4;
3422 } else {
3423 target = li;
3424 }
3425 if (LK(ctx->opcode)) {
3426 gen_setlr(ctx, ctx->nip);
3427 }
3428 gen_update_cfar(ctx, ctx->nip);
3429 gen_goto_tb(ctx, 0, target);
3430 }
3431
3432 #define BCOND_IM 0
3433 #define BCOND_LR 1
3434 #define BCOND_CTR 2
3435
3436 static inline void gen_bcond(DisasContext *ctx, int type)
3437 {
3438 uint32_t bo = BO(ctx->opcode);
3439 int l1;
3440 TCGv target;
3441
3442 ctx->exception = POWERPC_EXCP_BRANCH;
3443 if (type == BCOND_LR || type == BCOND_CTR) {
3444 target = tcg_temp_local_new();
3445 if (type == BCOND_CTR)
3446 tcg_gen_mov_tl(target, cpu_ctr);
3447 else
3448 tcg_gen_mov_tl(target, cpu_lr);
3449 } else {
3450 TCGV_UNUSED(target);
3451 }
3452 if (LK(ctx->opcode))
3453 gen_setlr(ctx, ctx->nip);
3454 l1 = gen_new_label();
3455 if ((bo & 0x4) == 0) {
3456 /* Decrement and test CTR */
3457 TCGv temp = tcg_temp_new();
3458 if (unlikely(type == BCOND_CTR)) {
3459 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3460 return;
3461 }
3462 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3463 if (NARROW_MODE(ctx)) {
3464 tcg_gen_ext32u_tl(temp, cpu_ctr);
3465 } else {
3466 tcg_gen_mov_tl(temp, cpu_ctr);
3467 }
3468 if (bo & 0x2) {
3469 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3470 } else {
3471 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3472 }
3473 tcg_temp_free(temp);
3474 }
3475 if ((bo & 0x10) == 0) {
3476 /* Test CR */
3477 uint32_t bi = BI(ctx->opcode);
3478 uint32_t mask = 1 << (3 - (bi & 0x03));
3479 TCGv_i32 temp = tcg_temp_new_i32();
3480
3481 if (bo & 0x8) {
3482 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3483 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3484 } else {
3485 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3486 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3487 }
3488 tcg_temp_free_i32(temp);
3489 }
3490 gen_update_cfar(ctx, ctx->nip);
3491 if (type == BCOND_IM) {
3492 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3493 if (likely(AA(ctx->opcode) == 0)) {
3494 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3495 } else {
3496 gen_goto_tb(ctx, 0, li);
3497 }
3498 gen_set_label(l1);
3499 gen_goto_tb(ctx, 1, ctx->nip);
3500 } else {
3501 if (NARROW_MODE(ctx)) {
3502 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3503 } else {
3504 tcg_gen_andi_tl(cpu_nip, target, ~3);
3505 }
3506 tcg_gen_exit_tb(0);
3507 gen_set_label(l1);
3508 gen_update_nip(ctx, ctx->nip);
3509 tcg_gen_exit_tb(0);
3510 }
3511 }
3512
3513 static void gen_bc(DisasContext *ctx)
3514 {
3515 gen_bcond(ctx, BCOND_IM);
3516 }
3517
3518 static void gen_bcctr(DisasContext *ctx)
3519 {
3520 gen_bcond(ctx, BCOND_CTR);
3521 }
3522
3523 static void gen_bclr(DisasContext *ctx)
3524 {
3525 gen_bcond(ctx, BCOND_LR);
3526 }
3527
3528 /*** Condition register logical ***/
3529 #define GEN_CRLOGIC(name, tcg_op, opc) \
3530 static void glue(gen_, name)(DisasContext *ctx) \
3531 { \
3532 uint8_t bitmask; \
3533 int sh; \
3534 TCGv_i32 t0, t1; \
3535 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3536 t0 = tcg_temp_new_i32(); \
3537 if (sh > 0) \
3538 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3539 else if (sh < 0) \
3540 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3541 else \
3542 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3543 t1 = tcg_temp_new_i32(); \
3544 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3545 if (sh > 0) \
3546 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3547 else if (sh < 0) \
3548 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3549 else \
3550 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3551 tcg_op(t0, t0, t1); \
3552 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3553 tcg_gen_andi_i32(t0, t0, bitmask); \
3554 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3555 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3556 tcg_temp_free_i32(t0); \
3557 tcg_temp_free_i32(t1); \
3558 }
3559
3560 /* crand */
3561 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3562 /* crandc */
3563 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3564 /* creqv */
3565 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3566 /* crnand */
3567 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3568 /* crnor */
3569 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3570 /* cror */
3571 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3572 /* crorc */
3573 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3574 /* crxor */
3575 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3576
3577 /* mcrf */
3578 static void gen_mcrf(DisasContext *ctx)
3579 {
3580 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3581 }
3582
3583 /*** System linkage ***/
3584
3585 /* rfi (mem_idx only) */
3586 static void gen_rfi(DisasContext *ctx)
3587 {
3588 #if defined(CONFIG_USER_ONLY)
3589 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3590 #else
3591 /* Restore CPU state */
3592 if (unlikely(!ctx->mem_idx)) {
3593 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3594 return;
3595 }
3596 gen_update_cfar(ctx, ctx->nip);
3597 gen_helper_rfi(cpu_env);
3598 gen_sync_exception(ctx);
3599 #endif
3600 }
3601
3602 #if defined(TARGET_PPC64)
3603 static void gen_rfid(DisasContext *ctx)
3604 {
3605 #if defined(CONFIG_USER_ONLY)
3606 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3607 #else
3608 /* Restore CPU state */
3609 if (unlikely(!ctx->mem_idx)) {
3610 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3611 return;
3612 }
3613 gen_update_cfar(ctx, ctx->nip);
3614 gen_helper_rfid(cpu_env);
3615 gen_sync_exception(ctx);
3616 #endif
3617 }
3618
3619 static void gen_hrfid(DisasContext *ctx)
3620 {
3621 #if defined(CONFIG_USER_ONLY)
3622 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3623 #else
3624 /* Restore CPU state */
3625 if (unlikely(ctx->mem_idx <= 1)) {
3626 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3627 return;
3628 }
3629 gen_helper_hrfid(cpu_env);
3630 gen_sync_exception(ctx);
3631 #endif
3632 }
3633 #endif
3634
3635 /* sc */
3636 #if defined(CONFIG_USER_ONLY)
3637 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3638 #else
3639 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3640 #endif
3641 static void gen_sc(DisasContext *ctx)
3642 {
3643 uint32_t lev;
3644
3645 lev = (ctx->opcode >> 5) & 0x7F;
3646 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3647 }
3648
3649 /*** Trap ***/
3650
3651 /* tw */
3652 static void gen_tw(DisasContext *ctx)
3653 {
3654 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3655 /* Update the nip since this might generate a trap exception */
3656 gen_update_nip(ctx, ctx->nip);
3657 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3658 t0);
3659 tcg_temp_free_i32(t0);
3660 }
3661
3662 /* twi */
3663 static void gen_twi(DisasContext *ctx)
3664 {
3665 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3666 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3667 /* Update the nip since this might generate a trap exception */
3668 gen_update_nip(ctx, ctx->nip);
3669 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3670 tcg_temp_free(t0);
3671 tcg_temp_free_i32(t1);
3672 }
3673
3674 #if defined(TARGET_PPC64)
3675 /* td */
3676 static void gen_td(DisasContext *ctx)
3677 {
3678 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3679 /* Update the nip since this might generate a trap exception */
3680 gen_update_nip(ctx, ctx->nip);
3681 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3682 t0);
3683 tcg_temp_free_i32(t0);
3684 }
3685
3686 /* tdi */
3687 static void gen_tdi(DisasContext *ctx)
3688 {
3689 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3690 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3691 /* Update the nip since this might generate a trap exception */
3692 gen_update_nip(ctx, ctx->nip);
3693 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3694 tcg_temp_free(t0);
3695 tcg_temp_free_i32(t1);
3696 }
3697 #endif
3698
3699 /*** Processor control ***/
3700
3701 static void gen_read_xer(TCGv dst)
3702 {
3703 TCGv t0 = tcg_temp_new();
3704 TCGv t1 = tcg_temp_new();
3705 TCGv t2 = tcg_temp_new();
3706 tcg_gen_mov_tl(dst, cpu_xer);
3707 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3708 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3709 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3710 tcg_gen_or_tl(t0, t0, t1);
3711 tcg_gen_or_tl(dst, dst, t2);
3712 tcg_gen_or_tl(dst, dst, t0);
3713 tcg_temp_free(t0);
3714 tcg_temp_free(t1);
3715 tcg_temp_free(t2);
3716 }
3717
3718 static void gen_write_xer(TCGv src)
3719 {
3720 tcg_gen_andi_tl(cpu_xer, src,
3721 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3722 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3723 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3724 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3725 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3726 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3727 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3728 }
3729
3730 /* mcrxr */
3731 static void gen_mcrxr(DisasContext *ctx)
3732 {
3733 TCGv_i32 t0 = tcg_temp_new_i32();
3734 TCGv_i32 t1 = tcg_temp_new_i32();
3735 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3736
3737 tcg_gen_trunc_tl_i32(t0, cpu_so);
3738 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3739 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3740 tcg_gen_shri_i32(t0, t0, 2);
3741 tcg_gen_shri_i32(t1, t1, 1);
3742 tcg_gen_or_i32(dst, dst, t0);
3743 tcg_gen_or_i32(dst, dst, t1);
3744 tcg_temp_free_i32(t0);
3745 tcg_temp_free_i32(t1);
3746
3747 tcg_gen_movi_tl(cpu_so, 0);
3748 tcg_gen_movi_tl(cpu_ov, 0);
3749 tcg_gen_movi_tl(cpu_ca, 0);
3750 }
3751
3752 /* mfcr mfocrf */
3753 static void gen_mfcr(DisasContext *ctx)
3754 {
3755 uint32_t crm, crn;
3756
3757 if (likely(ctx->opcode & 0x00100000)) {
3758 crm = CRM(ctx->opcode);
3759 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3760 crn = ctz32 (crm);
3761 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3762 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3763 cpu_gpr[rD(ctx->opcode)], crn * 4);
3764 }
3765 } else {
3766 TCGv_i32 t0 = tcg_temp_new_i32();
3767 tcg_gen_mov_i32(t0, cpu_crf[0]);
3768 tcg_gen_shli_i32(t0, t0, 4);
3769 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3770 tcg_gen_shli_i32(t0, t0, 4);
3771 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3772 tcg_gen_shli_i32(t0, t0, 4);
3773 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3774 tcg_gen_shli_i32(t0, t0, 4);
3775 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3776 tcg_gen_shli_i32(t0, t0, 4);
3777 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3778 tcg_gen_shli_i32(t0, t0, 4);
3779 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3780 tcg_gen_shli_i32(t0, t0, 4);
3781 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3782 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3783 tcg_temp_free_i32(t0);
3784 }
3785 }
3786
3787 /* mfmsr */
3788 static void gen_mfmsr(DisasContext *ctx)
3789 {
3790 #if defined(CONFIG_USER_ONLY)
3791 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3792 #else
3793 if (unlikely(!ctx->mem_idx)) {
3794 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3795 return;
3796 }
3797 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3798 #endif
3799 }
3800
3801 static void spr_noaccess(void *opaque, int gprn, int sprn)
3802 {
3803 #if 0
3804 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3805 printf("ERROR: try to access SPR %d !\n", sprn);
3806 #endif
3807 }
3808 #define SPR_NOACCESS (&spr_noaccess)
3809
3810 /* mfspr */
3811 static inline void gen_op_mfspr(DisasContext *ctx)
3812 {
3813 void (*read_cb)(void *opaque, int gprn, int sprn);
3814 uint32_t sprn = SPR(ctx->opcode);
3815
3816 #if !defined(CONFIG_USER_ONLY)
3817 if (ctx->mem_idx == 2)
3818 read_cb = ctx->spr_cb[sprn].hea_read;
3819 else if (ctx->mem_idx)
3820 read_cb = ctx->spr_cb[sprn].oea_read;
3821 else
3822 #endif
3823 read_cb = ctx->spr_cb[sprn].uea_read;
3824 if (likely(read_cb != NULL)) {
3825 if (likely(read_cb != SPR_NOACCESS)) {
3826 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3827 } else {
3828 /* Privilege exception */
3829 /* This is a hack to avoid warnings when running Linux:
3830 * this OS breaks the PowerPC virtualisation model,
3831 * allowing userland application to read the PVR
3832 */
3833 if (sprn != SPR_PVR) {
3834 qemu_log("Trying to read privileged spr %d %03x at "
3835 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3836 printf("Trying to read privileged spr %d %03x at "
3837 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3838 }
3839 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3840 }
3841 } else {
3842 /* Not defined */
3843 qemu_log("Trying to read invalid spr %d %03x at "
3844 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3845 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3846 sprn, sprn, ctx->nip);
3847 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3848 }
3849 }
3850
3851 static void gen_mfspr(DisasContext *ctx)
3852 {
3853 gen_op_mfspr(ctx);
3854 }
3855
3856 /* mftb */
3857 static void gen_mftb(DisasContext *ctx)
3858 {
3859 gen_op_mfspr(ctx);
3860 }
3861
3862 /* mtcrf mtocrf*/
3863 static void gen_mtcrf(DisasContext *ctx)
3864 {
3865 uint32_t crm, crn;
3866
3867 crm = CRM(ctx->opcode);
3868 if (likely((ctx->opcode & 0x00100000))) {
3869 if (crm && ((crm & (crm - 1)) == 0)) {
3870 TCGv_i32 temp = tcg_temp_new_i32();
3871 crn = ctz32 (crm);
3872 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3873 tcg_gen_shri_i32(temp, temp, crn * 4);
3874 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3875 tcg_temp_free_i32(temp);
3876 }
3877 } else {
3878 TCGv_i32 temp = tcg_temp_new_i32();
3879 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3880 for (crn = 0 ; crn < 8 ; crn++) {
3881 if (crm & (1 << crn)) {
3882 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3883 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3884 }
3885 }
3886 tcg_temp_free_i32(temp);
3887 }
3888 }
3889
3890 /* mtmsr */
3891 #if defined(TARGET_PPC64)
3892 static void gen_mtmsrd(DisasContext *ctx)
3893 {
3894 #if defined(CONFIG_USER_ONLY)
3895 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3896 #else
3897 if (unlikely(!ctx->mem_idx)) {
3898 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3899 return;
3900 }
3901 if (ctx->opcode & 0x00010000) {
3902 /* Special form that does not need any synchronisation */
3903 TCGv t0 = tcg_temp_new();
3904 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3905 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3906 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3907 tcg_temp_free(t0);
3908 } else {
3909 /* XXX: we need to update nip before the store
3910 * if we enter power saving mode, we will exit the loop
3911 * directly from ppc_store_msr
3912 */
3913 gen_update_nip(ctx, ctx->nip);
3914 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3915 /* Must stop the translation as machine state (may have) changed */
3916 /* Note that mtmsr is not always defined as context-synchronizing */
3917 gen_stop_exception(ctx);
3918 }
3919 #endif
3920 }
3921 #endif
3922
3923 static void gen_mtmsr(DisasContext *ctx)
3924 {
3925 #if defined(CONFIG_USER_ONLY)
3926 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3927 #else
3928 if (unlikely(!ctx->mem_idx)) {
3929 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3930 return;
3931 }
3932 if (ctx->opcode & 0x00010000) {
3933 /* Special form that does not need any synchronisation */
3934 TCGv t0 = tcg_temp_new();
3935 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3936 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3937 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3938 tcg_temp_free(t0);
3939 } else {
3940 TCGv msr = tcg_temp_new();
3941
3942 /* XXX: we need to update nip before the store
3943 * if we enter power saving mode, we will exit the loop
3944 * directly from ppc_store_msr
3945 */
3946 gen_update_nip(ctx, ctx->nip);
3947 #if defined(TARGET_PPC64)
3948 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3949 #else
3950 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3951 #endif
3952 gen_helper_store_msr(cpu_env, msr);
3953 /* Must stop the translation as machine state (may have) changed */
3954 /* Note that mtmsr is not always defined as context-synchronizing */
3955 gen_stop_exception(ctx);
3956 }
3957 #endif
3958 }
3959
3960 /* mtspr */
3961 static void gen_mtspr(DisasContext *ctx)
3962 {
3963 void (*write_cb)(void *opaque, int sprn, int gprn);
3964 uint32_t sprn = SPR(ctx->opcode);
3965
3966 #if !defined(CONFIG_USER_ONLY)
3967 if (ctx->mem_idx == 2)
3968 write_cb = ctx->spr_cb[sprn].hea_write;
3969 else if (ctx->mem_idx)
3970 write_cb = ctx->spr_cb[sprn].oea_write;
3971 else
3972 #endif
3973 write_cb = ctx->spr_cb[sprn].uea_write;
3974 if (likely(write_cb != NULL)) {
3975 if (likely(write_cb != SPR_NOACCESS)) {
3976 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3977 } else {
3978 /* Privilege exception */
3979 qemu_log("Trying to write privileged spr %d %03x at "
3980 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3981 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
3982 "\n", sprn, sprn, ctx->nip);
3983 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3984 }
3985 } else {
3986 /* Not defined */
3987 qemu_log("Trying to write invalid spr %d %03x at "
3988 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3989 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
3990 sprn, sprn, ctx->nip);
3991 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3992 }
3993 }
3994
3995 /*** Cache management ***/
3996
3997 /* dcbf */
3998 static void gen_dcbf(DisasContext *ctx)
3999 {
4000 /* XXX: specification says this is treated as a load by the MMU */
4001 TCGv t0;
4002 gen_set_access_type(ctx, ACCESS_CACHE);
4003 t0 = tcg_temp_new();
4004 gen_addr_reg_index(ctx, t0);
4005 gen_qemu_ld8u(ctx, t0, t0);
4006 tcg_temp_free(t0);
4007 }
4008
4009 /* dcbi (Supervisor only) */
4010 static void gen_dcbi(DisasContext *ctx)
4011 {
4012 #if defined(CONFIG_USER_ONLY)
4013 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4014 #else
4015 TCGv EA, val;
4016 if (unlikely(!ctx->mem_idx)) {
4017 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4018 return;
4019 }
4020 EA = tcg_temp_new();
4021 gen_set_access_type(ctx, ACCESS_CACHE);
4022 gen_addr_reg_index(ctx, EA);
4023 val = tcg_temp_new();
4024 /* XXX: specification says this should be treated as a store by the MMU */
4025 gen_qemu_ld8u(ctx, val, EA);
4026 gen_qemu_st8(ctx, val, EA);
4027 tcg_temp_free(val);
4028 tcg_temp_free(EA);
4029 #endif
4030 }
4031
4032 /* dcdst */
4033 static void gen_dcbst(DisasContext *ctx)
4034 {
4035 /* XXX: specification say this is treated as a load by the MMU */
4036 TCGv t0;
4037 gen_set_access_type(ctx, ACCESS_CACHE);
4038 t0 = tcg_temp_new();
4039 gen_addr_reg_index(ctx, t0);
4040 gen_qemu_ld8u(ctx, t0, t0);
4041 tcg_temp_free(t0);
4042 }
4043
4044 /* dcbt */
4045 static void gen_dcbt(DisasContext *ctx)
4046 {
4047 /* interpreted as no-op */
4048 /* XXX: specification say this is treated as a load by the MMU
4049 * but does not generate any exception
4050 */
4051 }
4052
4053 /* dcbtst */
4054 static void gen_dcbtst(DisasContext *ctx)
4055 {
4056 /* interpreted as no-op */
4057 /* XXX: specification say this is treated as a load by the MMU
4058 * but does not generate any exception
4059 */
4060 }
4061
4062 /* dcbz */
4063 static void gen_dcbz(DisasContext *ctx)
4064 {
4065 TCGv tcgv_addr;
4066 TCGv_i32 tcgv_is_dcbzl;
4067 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4068
4069 gen_set_access_type(ctx, ACCESS_CACHE);
4070 /* NIP cannot be restored if the memory exception comes from an helper */
4071 gen_update_nip(ctx, ctx->nip - 4);
4072 tcgv_addr = tcg_temp_new();
4073 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4074
4075 gen_addr_reg_index(ctx, tcgv_addr);
4076 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4077
4078 tcg_temp_free(tcgv_addr);
4079 tcg_temp_free_i32(tcgv_is_dcbzl);
4080 }
4081
4082 /* dst / dstt */
4083 static void gen_dst(DisasContext *ctx)
4084 {
4085 if (rA(ctx->opcode) == 0) {
4086 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4087 } else {
4088 /* interpreted as no-op */
4089 }
4090 }
4091
4092 /* dstst /dststt */
4093 static void gen_dstst(DisasContext *ctx)
4094 {
4095 if (rA(ctx->opcode) == 0) {
4096 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4097 } else {
4098 /* interpreted as no-op */
4099 }
4100
4101 }
4102
4103 /* dss / dssall */
4104 static void gen_dss(DisasContext *ctx)
4105 {
4106 /* interpreted as no-op */
4107 }
4108
4109 /* icbi */
4110 static void gen_icbi(DisasContext *ctx)
4111 {
4112 TCGv t0;
4113 gen_set_access_type(ctx, ACCESS_CACHE);
4114 /* NIP cannot be restored if the memory exception comes from an helper */
4115 gen_update_nip(ctx, ctx->nip - 4);
4116 t0 = tcg_temp_new();
4117 gen_addr_reg_index(ctx, t0);
4118 gen_helper_icbi(cpu_env, t0);
4119 tcg_temp_free(t0);
4120 }
4121
4122 /* Optional: */
4123 /* dcba */
4124 static void gen_dcba(DisasContext *ctx)
4125 {
4126 /* interpreted as no-op */
4127 /* XXX: specification say this is treated as a store by the MMU
4128 * but does not generate any exception
4129 */
4130 }
4131
4132 /*** Segment register manipulation ***/
4133 /* Supervisor only: */
4134
4135 /* mfsr */
4136 static void gen_mfsr(DisasContext *ctx)
4137 {
4138 #if defined(CONFIG_USER_ONLY)
4139 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4140 #else
4141 TCGv t0;
4142 if (unlikely(!ctx->mem_idx)) {
4143 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4144 return;
4145 }
4146 t0 = tcg_const_tl(SR(ctx->opcode));
4147 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4148 tcg_temp_free(t0);
4149 #endif
4150 }
4151
4152 /* mfsrin */
4153 static void gen_mfsrin(DisasContext *ctx)
4154 {
4155 #if defined(CONFIG_USER_ONLY)
4156 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4157 #else
4158 TCGv t0;
4159 if (unlikely(!ctx->mem_idx)) {
4160 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4161 return;
4162 }
4163 t0 = tcg_temp_new();
4164 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4165 tcg_gen_andi_tl(t0, t0, 0xF);
4166 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4167 tcg_temp_free(t0);
4168 #endif
4169 }
4170
4171 /* mtsr */
4172 static void gen_mtsr(DisasContext *ctx)
4173 {
4174 #if defined(CONFIG_USER_ONLY)
4175 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4176 #else
4177 TCGv t0;
4178 if (unlikely(!ctx->mem_idx)) {
4179 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4180 return;
4181 }
4182 t0 = tcg_const_tl(SR(ctx->opcode));
4183 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4184 tcg_temp_free(t0);
4185 #endif
4186 }
4187
4188 /* mtsrin */
4189 static void gen_mtsrin(DisasContext *ctx)
4190 {
4191 #if defined(CONFIG_USER_ONLY)
4192 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4193 #else
4194 TCGv t0;
4195 if (unlikely(!ctx->mem_idx)) {
4196 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4197 return;
4198 }
4199 t0 = tcg_temp_new();
4200 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4201 tcg_gen_andi_tl(t0, t0, 0xF);
4202 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4203 tcg_temp_free(t0);
4204 #endif
4205 }
4206
4207 #if defined(TARGET_PPC64)
4208 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4209
4210 /* mfsr */
4211 static void gen_mfsr_64b(DisasContext *ctx)
4212 {
4213 #if defined(CONFIG_USER_ONLY)
4214 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4215 #else
4216 TCGv t0;
4217 if (unlikely(!ctx->mem_idx)) {
4218 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4219 return;
4220 }
4221 t0 = tcg_const_tl(SR(ctx->opcode));
4222 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4223 tcg_temp_free(t0);
4224 #endif
4225 }
4226
4227 /* mfsrin */
4228 static void gen_mfsrin_64b(DisasContext *ctx)
4229 {
4230 #if defined(CONFIG_USER_ONLY)
4231 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4232 #else
4233 TCGv t0;
4234 if (unlikely(!ctx->mem_idx)) {
4235 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4236 return;
4237 }
4238 t0 = tcg_temp_new();
4239 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4240 tcg_gen_andi_tl(t0, t0, 0xF);
4241 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4242 tcg_temp_free(t0);
4243 #endif
4244 }
4245
4246 /* mtsr */
4247 static void gen_mtsr_64b(DisasContext *ctx)
4248 {
4249 #if defined(CONFIG_USER_ONLY)
4250 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4251 #else
4252 TCGv t0;
4253 if (unlikely(!ctx->mem_idx)) {
4254 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4255 return;
4256 }
4257 t0 = tcg_const_tl(SR(ctx->opcode));
4258 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4259 tcg_temp_free(t0);
4260 #endif
4261 }
4262
4263 /* mtsrin */
4264 static void gen_mtsrin_64b(DisasContext *ctx)
4265 {
4266 #if defined(CONFIG_USER_ONLY)
4267 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4268 #else
4269 TCGv t0;
4270 if (unlikely(!ctx->mem_idx)) {
4271 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4272 return;
4273 }
4274 t0 = tcg_temp_new();
4275 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4276 tcg_gen_andi_tl(t0, t0, 0xF);
4277 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4278 tcg_temp_free(t0);
4279 #endif
4280 }
4281
4282 /* slbmte */
4283 static void gen_slbmte(DisasContext *ctx)
4284 {
4285 #if defined(CONFIG_USER_ONLY)
4286 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4287 #else
4288 if (unlikely(!ctx->mem_idx)) {
4289 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4290 return;
4291 }
4292 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4293 cpu_gpr[rS(ctx->opcode)]);
4294 #endif
4295 }
4296
4297 static void gen_slbmfee(DisasContext *ctx)
4298 {
4299 #if defined(CONFIG_USER_ONLY)
4300 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4301 #else
4302 if (unlikely(!ctx->mem_idx)) {
4303 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4304 return;
4305 }
4306 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4307 cpu_gpr[rB(ctx->opcode)]);
4308 #endif
4309 }
4310
4311 static void gen_slbmfev(DisasContext *ctx)
4312 {
4313 #if defined(CONFIG_USER_ONLY)
4314 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4315 #else
4316 if (unlikely(!ctx->mem_idx)) {
4317 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4318 return;
4319 }
4320 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4321 cpu_gpr[rB(ctx->opcode)]);
4322 #endif
4323 }
4324 #endif /* defined(TARGET_PPC64) */
4325
4326 /*** Lookaside buffer management ***/
4327 /* Optional & mem_idx only: */
4328
4329 /* tlbia */
4330 static void gen_tlbia(DisasContext *ctx)
4331 {
4332 #if defined(CONFIG_USER_ONLY)
4333 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4334 #else
4335 if (unlikely(!ctx->mem_idx)) {
4336 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4337 return;
4338 }
4339 gen_helper_tlbia(cpu_env);
4340 #endif
4341 }
4342
4343 /* tlbiel */
4344 static void gen_tlbiel(DisasContext *ctx)
4345 {
4346 #if defined(CONFIG_USER_ONLY)
4347 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4348 #else
4349 if (unlikely(!ctx->mem_idx)) {
4350 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4351 return;
4352 }
4353 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4354 #endif
4355 }
4356
4357 /* tlbie */
4358 static void gen_tlbie(DisasContext *ctx)
4359 {
4360 #if defined(CONFIG_USER_ONLY)
4361 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4362 #else
4363 if (unlikely(!ctx->mem_idx)) {
4364 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4365 return;
4366 }
4367 if (NARROW_MODE(ctx)) {
4368 TCGv t0 = tcg_temp_new();
4369 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4370 gen_helper_tlbie(cpu_env, t0);
4371 tcg_temp_free(t0);
4372 } else {
4373 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4374 }
4375 #endif
4376 }
4377
4378 /* tlbsync */
4379 static void gen_tlbsync(DisasContext *ctx)
4380 {
4381 #if defined(CONFIG_USER_ONLY)
4382 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4383 #else
4384 if (unlikely(!ctx->mem_idx)) {
4385 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4386 return;
4387 }
4388 /* This has no effect: it should ensure that all previous
4389 * tlbie have completed
4390 */
4391 gen_stop_exception(ctx);
4392 #endif
4393 }
4394
4395 #if defined(TARGET_PPC64)
4396 /* slbia */
4397 static void gen_slbia(DisasContext *ctx)
4398 {
4399 #if defined(CONFIG_USER_ONLY)
4400 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4401 #else
4402 if (unlikely(!ctx->mem_idx)) {
4403 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4404 return;
4405 }
4406 gen_helper_slbia(cpu_env);
4407 #endif
4408 }
4409
4410 /* slbie */
4411 static void gen_slbie(DisasContext *ctx)
4412 {
4413 #if defined(CONFIG_USER_ONLY)
4414 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4415 #else
4416 if (unlikely(!ctx->mem_idx)) {
4417 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4418 return;
4419 }
4420 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4421 #endif
4422 }
4423 #endif
4424
4425 /*** External control ***/
4426 /* Optional: */
4427
4428 /* eciwx */
4429 static void gen_eciwx(DisasContext *ctx)
4430 {
4431 TCGv t0;
4432 /* Should check EAR[E] ! */
4433 gen_set_access_type(ctx, ACCESS_EXT);
4434 t0 = tcg_temp_new();
4435 gen_addr_reg_index(ctx, t0);
4436 gen_check_align(ctx, t0, 0x03);
4437 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4438 tcg_temp_free(t0);
4439 }
4440
4441 /* ecowx */
4442 static void gen_ecowx(DisasContext *ctx)
4443 {
4444 TCGv t0;
4445 /* Should check EAR[E] ! */
4446 gen_set_access_type(ctx, ACCESS_EXT);
4447 t0 = tcg_temp_new();
4448 gen_addr_reg_index(ctx, t0);
4449 gen_check_align(ctx, t0, 0x03);
4450 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4451 tcg_temp_free(t0);
4452 }
4453
4454 /* PowerPC 601 specific instructions */
4455
4456 /* abs - abs. */
4457 static void gen_abs(DisasContext *ctx)
4458 {
4459 int l1 = gen_new_label();
4460 int l2 = gen_new_label();
4461 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4462 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4463 tcg_gen_br(l2);
4464 gen_set_label(l1);
4465 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4466 gen_set_label(l2);
4467 if (unlikely(Rc(ctx->opcode) != 0))
4468 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4469 }
4470
4471 /* abso - abso. */
4472 static void gen_abso(DisasContext *ctx)
4473 {
4474 int l1 = gen_new_label();
4475 int l2 = gen_new_label();
4476 int l3 = gen_new_label();
4477 /* Start with XER OV disabled, the most likely case */
4478 tcg_gen_movi_tl(cpu_ov, 0);
4479 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4480 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4481 tcg_gen_movi_tl(cpu_ov, 1);
4482 tcg_gen_movi_tl(cpu_so, 1);
4483 tcg_gen_br(l2);
4484 gen_set_label(l1);
4485 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4486 tcg_gen_br(l3);
4487 gen_set_label(l2);
4488 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4489 gen_set_label(l3);
4490 if (unlikely(Rc(ctx->opcode) != 0))
4491 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4492 }
4493
4494 /* clcs */
4495 static void gen_clcs(DisasContext *ctx)
4496 {
4497 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4498 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4499 tcg_temp_free_i32(t0);
4500 /* Rc=1 sets CR0 to an undefined state */
4501 }
4502
4503 /* div - div. */
4504 static void gen_div(DisasContext *ctx)
4505 {
4506 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4507 cpu_gpr[rB(ctx->opcode)]);
4508 if (unlikely(Rc(ctx->opcode) != 0))
4509 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4510 }
4511
4512 /* divo - divo. */
4513 static void gen_divo(DisasContext *ctx)
4514 {
4515 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4516 cpu_gpr[rB(ctx->opcode)]);
4517 if (unlikely(Rc(ctx->opcode) != 0))
4518 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4519 }
4520
4521 /* divs - divs. */
4522 static void gen_divs(DisasContext *ctx)
4523 {
4524 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4525 cpu_gpr[rB(ctx->opcode)]);
4526 if (unlikely(Rc(ctx->opcode) != 0))
4527 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4528 }
4529
4530 /* divso - divso. */
4531 static void gen_divso(DisasContext *ctx)
4532 {
4533 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4534 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4535 if (unlikely(Rc(ctx->opcode) != 0))
4536 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4537 }
4538
4539 /* doz - doz. */
4540 static void gen_doz(DisasContext *ctx)
4541 {
4542 int l1 = gen_new_label();
4543 int l2 = gen_new_label();
4544 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4545 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4546 tcg_gen_br(l2);
4547 gen_set_label(l1);
4548 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4549 gen_set_label(l2);
4550 if (unlikely(Rc(ctx->opcode) != 0))
4551 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4552 }
4553
4554 /* dozo - dozo. */
4555 static void gen_dozo(DisasContext *ctx)
4556 {
4557 int l1 = gen_new_label();
4558 int l2 = gen_new_label();
4559 TCGv t0 = tcg_temp_new();
4560 TCGv t1 = tcg_temp_new();
4561 TCGv t2 = tcg_temp_new();
4562 /* Start with XER OV disabled, the most likely case */
4563 tcg_gen_movi_tl(cpu_ov, 0);
4564 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4565 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4566 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4567 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4568 tcg_gen_andc_tl(t1, t1, t2);
4569 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4570 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4571 tcg_gen_movi_tl(cpu_ov, 1);
4572 tcg_gen_movi_tl(cpu_so, 1);
4573 tcg_gen_br(l2);
4574 gen_set_label(l1);
4575 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4576 gen_set_label(l2);
4577 tcg_temp_free(t0);
4578 tcg_temp_free(t1);
4579 tcg_temp_free(t2);
4580 if (unlikely(Rc(ctx->opcode) != 0))
4581 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4582 }
4583
4584 /* dozi */
4585 static void gen_dozi(DisasContext *ctx)
4586 {
4587 target_long simm = SIMM(ctx->opcode);
4588 int l1 = gen_new_label();
4589 int l2 = gen_new_label();
4590 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4591 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4592 tcg_gen_br(l2);
4593 gen_set_label(l1);
4594 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4595 gen_set_label(l2);
4596 if (unlikely(Rc(ctx->opcode) != 0))
4597 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4598 }
4599
4600 /* lscbx - lscbx. */
4601 static void gen_lscbx(DisasContext *ctx)
4602 {
4603 TCGv t0 = tcg_temp_new();
4604 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4605 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4606 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4607
4608 gen_addr_reg_index(ctx, t0);
4609 /* NIP cannot be restored if the memory exception comes from an helper */
4610 gen_update_nip(ctx, ctx->nip - 4);
4611 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4612 tcg_temp_free_i32(t1);
4613 tcg_temp_free_i32(t2);
4614 tcg_temp_free_i32(t3);
4615 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4616 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4617 if (unlikely(Rc(ctx->opcode) != 0))
4618 gen_set_Rc0(ctx, t0);
4619 tcg_temp_free(t0);
4620 }
4621
4622 /* maskg - maskg. */
4623 static void gen_maskg(DisasContext *ctx)
4624 {
4625 int l1 = gen_new_label();
4626 TCGv t0 = tcg_temp_new();
4627 TCGv t1 = tcg_temp_new();
4628 TCGv t2 = tcg_temp_new();
4629 TCGv t3 = tcg_temp_new();
4630 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4631 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4632 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4633 tcg_gen_addi_tl(t2, t0, 1);
4634 tcg_gen_shr_tl(t2, t3, t2);
4635 tcg_gen_shr_tl(t3, t3, t1);
4636 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4637 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4638 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4639 gen_set_label(l1);
4640 tcg_temp_free(t0);
4641 tcg_temp_free(t1);
4642 tcg_temp_free(t2);
4643 tcg_temp_free(t3);
4644 if (unlikely(Rc(ctx->opcode) != 0))
4645 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4646 }
4647
4648 /* maskir - maskir. */
4649 static void gen_maskir(DisasContext *ctx)
4650 {
4651 TCGv t0 = tcg_temp_new();
4652 TCGv t1 = tcg_temp_new();
4653 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4654 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4655 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4656 tcg_temp_free(t0);
4657 tcg_temp_free(t1);
4658 if (unlikely(Rc(ctx->opcode) != 0))
4659 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4660 }
4661
4662 /* mul - mul. */
4663 static void gen_mul(DisasContext *ctx)
4664 {
4665 TCGv_i64 t0 = tcg_temp_new_i64();
4666 TCGv_i64 t1 = tcg_temp_new_i64();
4667 TCGv t2 = tcg_temp_new();
4668 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4669 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4670 tcg_gen_mul_i64(t0, t0, t1);
4671 tcg_gen_trunc_i64_tl(t2, t0);
4672 gen_store_spr(SPR_MQ, t2);
4673 tcg_gen_shri_i64(t1, t0, 32);
4674 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4675 tcg_temp_free_i64(t0);
4676 tcg_temp_free_i64(t1);
4677 tcg_temp_free(t2);
4678 if (unlikely(Rc(ctx->opcode) != 0))
4679 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4680 }
4681
4682 /* mulo - mulo. */
4683 static void gen_mulo(DisasContext *ctx)
4684 {
4685 int l1 = gen_new_label();
4686 TCGv_i64 t0 = tcg_temp_new_i64();
4687 TCGv_i64 t1 = tcg_temp_new_i64();
4688 TCGv t2 = tcg_temp_new();
4689 /* Start with XER OV disabled, the most likely case */
4690 tcg_gen_movi_tl(cpu_ov, 0);
4691 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4692 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4693 tcg_gen_mul_i64(t0, t0, t1);
4694 tcg_gen_trunc_i64_tl(t2, t0);
4695 gen_store_spr(SPR_MQ, t2);
4696 tcg_gen_shri_i64(t1, t0, 32);
4697 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4698 tcg_gen_ext32s_i64(t1, t0);
4699 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4700 tcg_gen_movi_tl(cpu_ov, 1);
4701 tcg_gen_movi_tl(cpu_so, 1);
4702 gen_set_label(l1);
4703 tcg_temp_free_i64(t0);
4704 tcg_temp_free_i64(t1);
4705 tcg_temp_free(t2);
4706 if (unlikely(Rc(ctx->opcode) != 0))
4707 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4708 }
4709
4710 /* nabs - nabs. */
4711 static void gen_nabs(DisasContext *ctx)
4712 {
4713 int l1 = gen_new_label();
4714 int l2 = gen_new_label();
4715 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4716 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4717 tcg_gen_br(l2);
4718 gen_set_label(l1);
4719 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4720 gen_set_label(l2);
4721 if (unlikely(Rc(ctx->opcode) != 0))
4722 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4723 }
4724
4725 /* nabso - nabso. */
4726 static void gen_nabso(DisasContext *ctx)
4727 {
4728 int l1 = gen_new_label();
4729 int l2 = gen_new_label();
4730 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4731 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4732 tcg_gen_br(l2);
4733 gen_set_label(l1);
4734 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4735 gen_set_label(l2);
4736 /* nabs never overflows */
4737 tcg_gen_movi_tl(cpu_ov, 0);
4738 if (unlikely(Rc(ctx->opcode) != 0))
4739 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4740 }
4741
4742 /* rlmi - rlmi. */
4743 static void gen_rlmi(DisasContext *ctx)
4744 {
4745 uint32_t mb = MB(ctx->opcode);
4746 uint32_t me = ME(ctx->opcode);
4747 TCGv t0 = tcg_temp_new();
4748 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4749 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4750 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4751 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4752 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4753 tcg_temp_free(t0);
4754 if (unlikely(Rc(ctx->opcode) != 0))
4755 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4756 }
4757
4758 /* rrib - rrib. */
4759 static void gen_rrib(DisasContext *ctx)
4760 {
4761 TCGv t0 = tcg_temp_new();
4762 TCGv t1 = tcg_temp_new();
4763 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4764 tcg_gen_movi_tl(t1, 0x80000000);
4765 tcg_gen_shr_tl(t1, t1, t0);
4766 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4767 tcg_gen_and_tl(t0, t0, t1);
4768 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4769 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4770 tcg_temp_free(t0);
4771 tcg_temp_free(t1);
4772 if (unlikely(Rc(ctx->opcode) != 0))
4773 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4774 }
4775
4776 /* sle - sle. */
4777 static void gen_sle(DisasContext *ctx)
4778 {
4779 TCGv t0 = tcg_temp_new();
4780 TCGv t1 = tcg_temp_new();
4781 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4782 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4783 tcg_gen_subfi_tl(t1, 32, t1);
4784 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4785 tcg_gen_or_tl(t1, t0, t1);
4786 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4787 gen_store_spr(SPR_MQ, t1);
4788 tcg_temp_free(t0);
4789 tcg_temp_free(t1);
4790 if (unlikely(Rc(ctx->opcode) != 0))
4791 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4792 }
4793
4794 /* sleq - sleq. */
4795 static void gen_sleq(DisasContext *ctx)
4796 {
4797 TCGv t0 = tcg_temp_new();
4798 TCGv t1 = tcg_temp_new();
4799 TCGv t2 = tcg_temp_new();
4800 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4801 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4802 tcg_gen_shl_tl(t2, t2, t0);
4803 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4804 gen_load_spr(t1, SPR_MQ);
4805 gen_store_spr(SPR_MQ, t0);
4806 tcg_gen_and_tl(t0, t0, t2);
4807 tcg_gen_andc_tl(t1, t1, t2);
4808 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4809 tcg_temp_free(t0);
4810 tcg_temp_free(t1);
4811 tcg_temp_free(t2);
4812 if (unlikely(Rc(ctx->opcode) != 0))
4813 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4814 }
4815
4816 /* sliq - sliq. */
4817 static void gen_sliq(DisasContext *ctx)
4818 {
4819 int sh = SH(ctx->opcode);
4820 TCGv t0 = tcg_temp_new();
4821 TCGv t1 = tcg_temp_new();
4822 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4823 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4824 tcg_gen_or_tl(t1, t0, t1);
4825 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4826 gen_store_spr(SPR_MQ, t1);
4827 tcg_temp_free(t0);
4828 tcg_temp_free(t1);
4829 if (unlikely(Rc(ctx->opcode) != 0))
4830 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4831 }
4832
4833 /* slliq - slliq. */
4834 static void gen_slliq(DisasContext *ctx)
4835 {
4836 int sh = SH(ctx->opcode);
4837 TCGv t0 = tcg_temp_new();
4838 TCGv t1 = tcg_temp_new();
4839 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4840 gen_load_spr(t1, SPR_MQ);
4841 gen_store_spr(SPR_MQ, t0);
4842 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4843 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4844 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4845 tcg_temp_free(t0);
4846 tcg_temp_free(t1);
4847 if (unlikely(Rc(ctx->opcode) != 0))
4848 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4849 }
4850
4851 /* sllq - sllq. */
4852 static void gen_sllq(DisasContext *ctx)
4853 {
4854 int l1 = gen_new_label();
4855 int l2 = gen_new_label();
4856 TCGv t0 = tcg_temp_local_new();
4857 TCGv t1 = tcg_temp_local_new();
4858 TCGv t2 = tcg_temp_local_new();
4859 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4860 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4861 tcg_gen_shl_tl(t1, t1, t2);
4862 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4863 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4864 gen_load_spr(t0, SPR_MQ);
4865 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4866 tcg_gen_br(l2);
4867 gen_set_label(l1);
4868 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4869 gen_load_spr(t2, SPR_MQ);
4870 tcg_gen_andc_tl(t1, t2, t1);
4871 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4872 gen_set_label(l2);
4873 tcg_temp_free(t0);
4874 tcg_temp_free(t1);
4875 tcg_temp_free(t2);
4876 if (unlikely(Rc(ctx->opcode) != 0))
4877 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4878 }
4879
4880 /* slq - slq. */
4881 static void gen_slq(DisasContext *ctx)
4882 {
4883 int l1 = gen_new_label();
4884 TCGv t0 = tcg_temp_new();
4885 TCGv t1 = tcg_temp_new();
4886 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4887 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4888 tcg_gen_subfi_tl(t1, 32, t1);
4889 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4890 tcg_gen_or_tl(t1, t0, t1);
4891 gen_store_spr(SPR_MQ, t1);
4892 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4893 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4894 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4895 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4896 gen_set_label(l1);
4897 tcg_temp_free(t0);
4898 tcg_temp_free(t1);
4899 if (unlikely(Rc(ctx->opcode) != 0))
4900 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4901 }
4902
4903 /* sraiq - sraiq. */
4904 static void gen_sraiq(DisasContext *ctx)
4905 {
4906 int sh = SH(ctx->opcode);
4907 int l1 = gen_new_label();
4908 TCGv t0 = tcg_temp_new();
4909 TCGv t1 = tcg_temp_new();
4910 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4911 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4912 tcg_gen_or_tl(t0, t0, t1);
4913 gen_store_spr(SPR_MQ, t0);
4914 tcg_gen_movi_tl(cpu_ca, 0);
4915 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4916 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4917 tcg_gen_movi_tl(cpu_ca, 1);
4918 gen_set_label(l1);
4919 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4920 tcg_temp_free(t0);
4921 tcg_temp_free(t1);
4922 if (unlikely(Rc(ctx->opcode) != 0))
4923 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4924 }
4925
4926 /* sraq - sraq. */
4927 static void gen_sraq(DisasContext *ctx)
4928 {
4929 int l1 = gen_new_label();
4930 int l2 = gen_new_label();
4931 TCGv t0 = tcg_temp_new();
4932 TCGv t1 = tcg_temp_local_new();
4933 TCGv t2 = tcg_temp_local_new();
4934 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4935 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4936 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4937 tcg_gen_subfi_tl(t2, 32, t2);
4938 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4939 tcg_gen_or_tl(t0, t0, t2);
4940 gen_store_spr(SPR_MQ, t0);
4941 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4942 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4943 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4944 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4945 gen_set_label(l1);
4946 tcg_temp_free(t0);
4947 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4948 tcg_gen_movi_tl(cpu_ca, 0);
4949 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4950 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4951 tcg_gen_movi_tl(cpu_ca, 1);
4952 gen_set_label(l2);
4953 tcg_temp_free(t1);
4954 tcg_temp_free(t2);
4955 if (unlikely(Rc(ctx->opcode) != 0))
4956 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4957 }
4958
4959 /* sre - sre. */
4960 static void gen_sre(DisasContext *ctx)
4961 {
4962 TCGv t0 = tcg_temp_new();
4963 TCGv t1 = tcg_temp_new();
4964 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4965 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4966 tcg_gen_subfi_tl(t1, 32, t1);
4967 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4968 tcg_gen_or_tl(t1, t0, t1);
4969 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4970 gen_store_spr(SPR_MQ, t1);
4971 tcg_temp_free(t0);
4972 tcg_temp_free(t1);
4973 if (unlikely(Rc(ctx->opcode) != 0))
4974 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4975 }
4976
4977 /* srea - srea. */
4978 static void gen_srea(DisasContext *ctx)
4979 {
4980 TCGv t0 = tcg_temp_new();
4981 TCGv t1 = tcg_temp_new();
4982 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4983 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4984 gen_store_spr(SPR_MQ, t0);
4985 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4986 tcg_temp_free(t0);
4987 tcg_temp_free(t1);
4988 if (unlikely(Rc(ctx->opcode) != 0))
4989 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4990 }
4991
4992 /* sreq */
4993 static void gen_sreq(DisasContext *ctx)
4994 {
4995 TCGv t0 = tcg_temp_new();
4996 TCGv t1 = tcg_temp_new();
4997 TCGv t2 = tcg_temp_new();
4998 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4999 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5000 tcg_gen_shr_tl(t1, t1, t0);
5001 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5002 gen_load_spr(t2, SPR_MQ);
5003 gen_store_spr(SPR_MQ, t0);
5004 tcg_gen_and_tl(t0, t0, t1);
5005 tcg_gen_andc_tl(t2, t2, t1);
5006 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5007 tcg_temp_free(t0);
5008 tcg_temp_free(t1);
5009 tcg_temp_free(t2);
5010 if (unlikely(Rc(ctx->opcode) != 0))
5011 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5012 }
5013
5014 /* sriq */
5015 static void gen_sriq(DisasContext *ctx)
5016 {
5017 int sh = SH(ctx->opcode);
5018 TCGv t0 = tcg_temp_new();
5019 TCGv t1 = tcg_temp_new();
5020 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5021 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5022 tcg_gen_or_tl(t1, t0, t1);
5023 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5024 gen_store_spr(SPR_MQ, t1);
5025 tcg_temp_free(t0);
5026 tcg_temp_free(t1);
5027 if (unlikely(Rc(ctx->opcode) != 0))
5028 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5029 }
5030
5031 /* srliq */
5032 static void gen_srliq(DisasContext *ctx)
5033 {
5034 int sh = SH(ctx->opcode);
5035 TCGv t0 = tcg_temp_new();
5036 TCGv t1 = tcg_temp_new();
5037 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5038 gen_load_spr(t1, SPR_MQ);
5039 gen_store_spr(SPR_MQ, t0);
5040 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5041 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5042 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5043 tcg_temp_free(t0);
5044 tcg_temp_free(t1);
5045 if (unlikely(Rc(ctx->opcode) != 0))
5046 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5047 }
5048
5049 /* srlq */
5050 static void gen_srlq(DisasContext *ctx)
5051 {
5052 int l1 = gen_new_label();
5053 int l2 = gen_new_label();
5054 TCGv t0 = tcg_temp_local_new();
5055 TCGv t1 = tcg_temp_local_new();
5056 TCGv t2 = tcg_temp_local_new();
5057 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5058 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5059 tcg_gen_shr_tl(t2, t1, t2);
5060 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5061 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5062 gen_load_spr(t0, SPR_MQ);
5063 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5064 tcg_gen_br(l2);
5065 gen_set_label(l1);
5066 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5067 tcg_gen_and_tl(t0, t0, t2);
5068 gen_load_spr(t1, SPR_MQ);
5069 tcg_gen_andc_tl(t1, t1, t2);
5070 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5071 gen_set_label(l2);
5072 tcg_temp_free(t0);
5073 tcg_temp_free(t1);
5074 tcg_temp_free(t2);
5075 if (unlikely(Rc(ctx->opcode) != 0))
5076 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5077 }
5078
5079 /* srq */
5080 static void gen_srq(DisasContext *ctx)
5081 {
5082 int l1 = gen_new_label();
5083 TCGv t0 = tcg_temp_new();
5084 TCGv t1 = tcg_temp_new();
5085 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5086 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5087 tcg_gen_subfi_tl(t1, 32, t1);
5088 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5089 tcg_gen_or_tl(t1, t0, t1);
5090 gen_store_spr(SPR_MQ, t1);
5091 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5092 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5093 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5094 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5095 gen_set_label(l1);
5096 tcg_temp_free(t0);
5097 tcg_temp_free(t1);
5098 if (unlikely(Rc(ctx->opcode) != 0))
5099 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5100 }
5101
5102 /* PowerPC 602 specific instructions */
5103
5104 /* dsa */
5105 static void gen_dsa(DisasContext *ctx)
5106 {
5107 /* XXX: TODO */
5108 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5109 }
5110
5111 /* esa */
5112 static void gen_esa(DisasContext *ctx)
5113 {
5114 /* XXX: TODO */
5115 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5116 }
5117
5118 /* mfrom */
5119 static void gen_mfrom(DisasContext *ctx)
5120 {
5121 #if defined(CONFIG_USER_ONLY)
5122 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5123 #else
5124 if (unlikely(!ctx->mem_idx)) {
5125 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5126 return;
5127 }
5128 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5129 #endif
5130 }
5131
5132 /* 602 - 603 - G2 TLB management */
5133
5134 /* tlbld */
5135 static void gen_tlbld_6xx(DisasContext *ctx)
5136 {
5137 #if defined(CONFIG_USER_ONLY)
5138 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5139 #else
5140 if (unlikely(!ctx->mem_idx)) {
5141 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5142 return;
5143 }
5144 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5145 #endif
5146 }
5147
5148 /* tlbli */
5149 static void gen_tlbli_6xx(DisasContext *ctx)
5150 {
5151 #if defined(CONFIG_USER_ONLY)
5152 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5153 #else
5154 if (unlikely(!ctx->mem_idx)) {
5155 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5156 return;
5157 }
5158 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5159 #endif
5160 }
5161
5162 /* 74xx TLB management */
5163
5164 /* tlbld */
5165 static void gen_tlbld_74xx(DisasContext *ctx)
5166 {
5167 #if defined(CONFIG_USER_ONLY)
5168 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5169 #else
5170 if (unlikely(!ctx->mem_idx)) {
5171 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5172 return;
5173 }
5174 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5175 #endif
5176 }
5177
5178 /* tlbli */
5179 static void gen_tlbli_74xx(DisasContext *ctx)
5180 {
5181 #if defined(CONFIG_USER_ONLY)
5182 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5183 #else
5184 if (unlikely(!ctx->mem_idx)) {
5185 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5186 return;
5187 }
5188 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5189 #endif
5190 }
5191
5192 /* POWER instructions not in PowerPC 601 */
5193
5194 /* clf */
5195 static void gen_clf(DisasContext *ctx)
5196 {
5197 /* Cache line flush: implemented as no-op */
5198 }
5199
5200 /* cli */
5201 static void gen_cli(DisasContext *ctx)
5202 {
5203 /* Cache line invalidate: privileged and treated as no-op */
5204 #if defined(CONFIG_USER_ONLY)
5205 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5206 #else
5207 if (unlikely(!ctx->mem_idx)) {
5208 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5209 return;
5210 }
5211 #endif
5212 }
5213
5214 /* dclst */
5215 static void gen_dclst(DisasContext *ctx)
5216 {
5217 /* Data cache line store: treated as no-op */
5218 }
5219
5220 static void gen_mfsri(DisasContext *ctx)
5221 {
5222 #if defined(CONFIG_USER_ONLY)
5223 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5224 #else
5225 int ra = rA(ctx->opcode);
5226 int rd = rD(ctx->opcode);
5227 TCGv t0;
5228 if (unlikely(!ctx->mem_idx)) {
5229 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5230 return;
5231 }
5232 t0 = tcg_temp_new();
5233 gen_addr_reg_index(ctx, t0);
5234 tcg_gen_shri_tl(t0, t0, 28);
5235 tcg_gen_andi_tl(t0, t0, 0xF);
5236 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5237 tcg_temp_free(t0);
5238 if (ra != 0 && ra != rd)
5239 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5240 #endif
5241 }
5242
5243 static void gen_rac(DisasContext *ctx)
5244 {
5245 #if defined(CONFIG_USER_ONLY)
5246 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5247 #else
5248 TCGv t0;
5249 if (unlikely(!ctx->mem_idx)) {
5250 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5251 return;
5252 }
5253 t0 = tcg_temp_new();
5254 gen_addr_reg_index(ctx, t0);
5255 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5256 tcg_temp_free(t0);
5257 #endif
5258 }
5259
5260 static void gen_rfsvc(DisasContext *ctx)
5261 {
5262 #if defined(CONFIG_USER_ONLY)
5263 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5264 #else
5265 if (unlikely(!ctx->mem_idx)) {
5266 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5267 return;
5268 }
5269 gen_helper_rfsvc(cpu_env);
5270 gen_sync_exception(ctx);
5271 #endif
5272 }
5273
5274 /* svc is not implemented for now */
5275
5276 /* POWER2 specific instructions */
5277 /* Quad manipulation (load/store two floats at a time) */
5278
5279 /* lfq */
5280 static void gen_lfq(DisasContext *ctx)
5281 {
5282 int rd = rD(ctx->opcode);
5283 TCGv t0;
5284 gen_set_access_type(ctx, ACCESS_FLOAT);
5285 t0 = tcg_temp_new();
5286 gen_addr_imm_index(ctx, t0, 0);
5287 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5288 gen_addr_add(ctx, t0, t0, 8);
5289 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5290 tcg_temp_free(t0);
5291 }
5292
5293 /* lfqu */
5294 static void gen_lfqu(DisasContext *ctx)
5295 {
5296 int ra = rA(ctx->opcode);
5297 int rd = rD(ctx->opcode);
5298 TCGv t0, t1;
5299 gen_set_access_type(ctx, ACCESS_FLOAT);
5300 t0 = tcg_temp_new();
5301 t1 = tcg_temp_new();
5302 gen_addr_imm_index(ctx, t0, 0);
5303 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5304 gen_addr_add(ctx, t1, t0, 8);
5305 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5306 if (ra != 0)
5307 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5308 tcg_temp_free(t0);
5309 tcg_temp_free(t1);
5310 }
5311
5312 /* lfqux */
5313 static void gen_lfqux(DisasContext *ctx)
5314 {
5315 int ra = rA(ctx->opcode);
5316 int rd = rD(ctx->opcode);
5317 gen_set_access_type(ctx, ACCESS_FLOAT);
5318 TCGv t0, t1;
5319 t0 = tcg_temp_new();
5320 gen_addr_reg_index(ctx, t0);
5321 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5322 t1 = tcg_temp_new();
5323 gen_addr_add(ctx, t1, t0, 8);
5324 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5325 tcg_temp_free(t1);
5326 if (ra != 0)
5327 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5328 tcg_temp_free(t0);
5329 }
5330
5331 /* lfqx */
5332 static void gen_lfqx(DisasContext *ctx)
5333 {
5334 int rd = rD(ctx->opcode);
5335 TCGv t0;
5336 gen_set_access_type(ctx, ACCESS_FLOAT);
5337 t0 = tcg_temp_new();
5338 gen_addr_reg_index(ctx, t0);
5339 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5340 gen_addr_add(ctx, t0, t0, 8);
5341 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5342 tcg_temp_free(t0);
5343 }
5344
5345 /* stfq */
5346 static void gen_stfq(DisasContext *ctx)
5347 {
5348 int rd = rD(ctx->opcode);
5349 TCGv t0;
5350 gen_set_access_type(ctx, ACCESS_FLOAT);
5351 t0 = tcg_temp_new();
5352 gen_addr_imm_index(ctx, t0, 0);
5353 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5354 gen_addr_add(ctx, t0, t0, 8);
5355 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5356 tcg_temp_free(t0);
5357 }
5358
5359 /* stfqu */
5360 static void gen_stfqu(DisasContext *ctx)
5361 {
5362 int ra = rA(ctx->opcode);
5363 int rd = rD(ctx->opcode);
5364 TCGv t0, t1;
5365 gen_set_access_type(ctx, ACCESS_FLOAT);
5366 t0 = tcg_temp_new();
5367 gen_addr_imm_index(ctx, t0, 0);
5368 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5369 t1 = tcg_temp_new();
5370 gen_addr_add(ctx, t1, t0, 8);
5371 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5372 tcg_temp_free(t1);
5373 if (ra != 0)
5374 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5375 tcg_temp_free(t0);
5376 }
5377
5378 /* stfqux */
5379 static void gen_stfqux(DisasContext *ctx)
5380 {
5381 int ra = rA(ctx->opcode);
5382 int rd = rD(ctx->opcode);
5383 TCGv t0, t1;
5384 gen_set_access_type(ctx, ACCESS_FLOAT);
5385 t0 = tcg_temp_new();
5386 gen_addr_reg_index(ctx, t0);
5387 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5388 t1 = tcg_temp_new();
5389 gen_addr_add(ctx, t1, t0, 8);
5390 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5391 tcg_temp_free(t1);
5392 if (ra != 0)
5393 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5394 tcg_temp_free(t0);
5395 }
5396
5397 /* stfqx */
5398 static void gen_stfqx(DisasContext *ctx)
5399 {
5400 int rd = rD(ctx->opcode);
5401 TCGv t0;
5402 gen_set_access_type(ctx, ACCESS_FLOAT);
5403 t0 = tcg_temp_new();
5404 gen_addr_reg_index(ctx, t0);
5405 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5406 gen_addr_add(ctx, t0, t0, 8);
5407 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5408 tcg_temp_free(t0);
5409 }
5410
5411 /* BookE specific instructions */
5412
5413 /* XXX: not implemented on 440 ? */
5414 static void gen_mfapidi(DisasContext *ctx)
5415 {
5416 /* XXX: TODO */
5417 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5418 }
5419
5420 /* XXX: not implemented on 440 ? */
5421 static void gen_tlbiva(DisasContext *ctx)
5422 {
5423 #if defined(CONFIG_USER_ONLY)
5424 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5425 #else
5426 TCGv t0;
5427 if (unlikely(!ctx->mem_idx)) {
5428 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5429 return;
5430 }
5431 t0 = tcg_temp_new();
5432 gen_addr_reg_index(ctx, t0);
5433 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5434 tcg_temp_free(t0);
5435 #endif
5436 }
5437
5438 /* All 405 MAC instructions are translated here */
5439 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5440 int ra, int rb, int rt, int Rc)
5441 {
5442 TCGv t0, t1;
5443
5444 t0 = tcg_temp_local_new();
5445 t1 = tcg_temp_local_new();
5446
5447 switch (opc3 & 0x0D) {
5448 case 0x05:
5449 /* macchw - macchw. - macchwo - macchwo. */
5450 /* macchws - macchws. - macchwso - macchwso. */
5451 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5452 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5453 /* mulchw - mulchw. */
5454 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5455 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5456 tcg_gen_ext16s_tl(t1, t1);
5457 break;
5458 case 0x04:
5459 /* macchwu - macchwu. - macchwuo - macchwuo. */
5460 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5461 /* mulchwu - mulchwu. */
5462 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5463 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5464 tcg_gen_ext16u_tl(t1, t1);
5465 break;
5466 case 0x01:
5467 /* machhw - machhw. - machhwo - machhwo. */
5468 /* machhws - machhws. - machhwso - machhwso. */
5469 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5470 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5471 /* mulhhw - mulhhw. */
5472 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5473 tcg_gen_ext16s_tl(t0, t0);
5474 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5475 tcg_gen_ext16s_tl(t1, t1);
5476 break;
5477 case 0x00:
5478 /* machhwu - machhwu. - machhwuo - machhwuo. */
5479 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5480 /* mulhhwu - mulhhwu. */
5481 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5482 tcg_gen_ext16u_tl(t0, t0);
5483 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5484 tcg_gen_ext16u_tl(t1, t1);
5485 break;
5486 case 0x0D:
5487 /* maclhw - maclhw. - maclhwo - maclhwo. */
5488 /* maclhws - maclhws. - maclhwso - maclhwso. */
5489 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5490 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5491 /* mullhw - mullhw. */
5492 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5493 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5494 break;
5495 case 0x0C:
5496 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5497 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5498 /* mullhwu - mullhwu. */
5499 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5500 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5501 break;
5502 }
5503 if (opc2 & 0x04) {
5504 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5505 tcg_gen_mul_tl(t1, t0, t1);
5506 if (opc2 & 0x02) {
5507 /* nmultiply-and-accumulate (0x0E) */
5508 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5509 } else {
5510 /* multiply-and-accumulate (0x0C) */
5511 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5512 }
5513
5514 if (opc3 & 0x12) {
5515 /* Check overflow and/or saturate */
5516 int l1 = gen_new_label();
5517
5518 if (opc3 & 0x10) {
5519 /* Start with XER OV disabled, the most likely case */
5520 tcg_gen_movi_tl(cpu_ov, 0);
5521 }
5522 if (opc3 & 0x01) {
5523 /* Signed */
5524 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5525 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5526 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5527 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5528 if (opc3 & 0x02) {
5529 /* Saturate */
5530 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5531 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5532 }
5533 } else {
5534 /* Unsigned */
5535 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5536 if (opc3 & 0x02) {
5537 /* Saturate */
5538 tcg_gen_movi_tl(t0, UINT32_MAX);
5539 }
5540 }
5541 if (opc3 & 0x10) {
5542 /* Check overflow */
5543 tcg_gen_movi_tl(cpu_ov, 1);
5544 tcg_gen_movi_tl(cpu_so, 1);
5545 }
5546 gen_set_label(l1);
5547 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5548 }
5549 } else {
5550 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5551 }
5552 tcg_temp_free(t0);
5553 tcg_temp_free(t1);
5554 if (unlikely(Rc) != 0) {
5555 /* Update Rc0 */
5556 gen_set_Rc0(ctx, cpu_gpr[rt]);
5557 }
5558 }
5559
5560 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5561 static void glue(gen_, name)(DisasContext *ctx) \
5562 { \
5563 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5564 rD(ctx->opcode), Rc(ctx->opcode)); \
5565 }
5566
5567 /* macchw - macchw. */
5568 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5569 /* macchwo - macchwo. */
5570 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5571 /* macchws - macchws. */
5572 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5573 /* macchwso - macchwso. */
5574 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5575 /* macchwsu - macchwsu. */
5576 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5577 /* macchwsuo - macchwsuo. */
5578 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5579 /* macchwu - macchwu. */
5580 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5581 /* macchwuo - macchwuo. */
5582 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5583 /* machhw - machhw. */
5584 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5585 /* machhwo - machhwo. */
5586 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5587 /* machhws - machhws. */
5588 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5589 /* machhwso - machhwso. */
5590 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5591 /* machhwsu - machhwsu. */
5592 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5593 /* machhwsuo - machhwsuo. */
5594 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5595 /* machhwu - machhwu. */
5596 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5597 /* machhwuo - machhwuo. */
5598 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5599 /* maclhw - maclhw. */
5600 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5601 /* maclhwo - maclhwo. */
5602 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5603 /* maclhws - maclhws. */
5604 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5605 /* maclhwso - maclhwso. */
5606 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5607 /* maclhwu - maclhwu. */
5608 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5609 /* maclhwuo - maclhwuo. */
5610 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5611 /* maclhwsu - maclhwsu. */
5612 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5613 /* maclhwsuo - maclhwsuo. */
5614 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5615 /* nmacchw - nmacchw. */
5616 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5617 /* nmacchwo - nmacchwo. */
5618 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5619 /* nmacchws - nmacchws. */
5620 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5621 /* nmacchwso - nmacchwso. */
5622 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5623 /* nmachhw - nmachhw. */
5624 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5625 /* nmachhwo - nmachhwo. */
5626 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5627 /* nmachhws - nmachhws. */
5628 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5629 /* nmachhwso - nmachhwso. */
5630 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5631 /* nmaclhw - nmaclhw. */
5632 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5633 /* nmaclhwo - nmaclhwo. */
5634 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5635 /* nmaclhws - nmaclhws. */
5636 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5637 /* nmaclhwso - nmaclhwso. */
5638 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5639
5640 /* mulchw - mulchw. */
5641 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5642 /* mulchwu - mulchwu. */
5643 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5644 /* mulhhw - mulhhw. */
5645 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5646 /* mulhhwu - mulhhwu. */
5647 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5648 /* mullhw - mullhw. */
5649 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5650 /* mullhwu - mullhwu. */
5651 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5652
5653 /* mfdcr */
5654 static void gen_mfdcr(DisasContext *ctx)
5655 {
5656 #if defined(CONFIG_USER_ONLY)
5657 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5658 #else
5659 TCGv dcrn;
5660 if (unlikely(!ctx->mem_idx)) {
5661 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5662 return;
5663 }
5664 /* NIP cannot be restored if the memory exception comes from an helper */
5665 gen_update_nip(ctx, ctx->nip - 4);
5666 dcrn = tcg_const_tl(SPR(ctx->opcode));
5667 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5668 tcg_temp_free(dcrn);
5669 #endif
5670 }
5671
5672 /* mtdcr */
5673 static void gen_mtdcr(DisasContext *ctx)
5674 {
5675 #if defined(CONFIG_USER_ONLY)
5676 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5677 #else
5678 TCGv dcrn;
5679 if (unlikely(!ctx->mem_idx)) {
5680 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5681 return;
5682 }
5683 /* NIP cannot be restored if the memory exception comes from an helper */
5684 gen_update_nip(ctx, ctx->nip - 4);
5685 dcrn = tcg_const_tl(SPR(ctx->opcode));
5686 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5687 tcg_temp_free(dcrn);
5688 #endif
5689 }
5690
5691 /* mfdcrx */
5692 /* XXX: not implemented on 440 ? */
5693 static void gen_mfdcrx(DisasContext *ctx)
5694 {
5695 #if defined(CONFIG_USER_ONLY)
5696 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5697 #else
5698 if (unlikely(!ctx->mem_idx)) {
5699 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5700 return;
5701 }
5702 /* NIP cannot be restored if the memory exception comes from an helper */
5703 gen_update_nip(ctx, ctx->nip - 4);
5704 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5705 cpu_gpr[rA(ctx->opcode)]);
5706 /* Note: Rc update flag set leads to undefined state of Rc0 */
5707 #endif
5708 }
5709
5710 /* mtdcrx */
5711 /* XXX: not implemented on 440 ? */
5712 static void gen_mtdcrx(DisasContext *ctx)
5713 {
5714 #if defined(CONFIG_USER_ONLY)
5715 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5716 #else
5717 if (unlikely(!ctx->mem_idx)) {
5718 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5719 return;
5720 }
5721 /* NIP cannot be restored if the memory exception comes from an helper */
5722 gen_update_nip(ctx, ctx->nip - 4);
5723 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5724 cpu_gpr[rS(ctx->opcode)]);
5725 /* Note: Rc update flag set leads to undefined state of Rc0 */
5726 #endif
5727 }
5728
5729 /* mfdcrux (PPC 460) : user-mode access to DCR */
5730 static void gen_mfdcrux(DisasContext *ctx)
5731 {
5732 /* NIP cannot be restored if the memory exception comes from an helper */
5733 gen_update_nip(ctx, ctx->nip - 4);
5734 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5735 cpu_gpr[rA(ctx->opcode)]);
5736 /* Note: Rc update flag set leads to undefined state of Rc0 */
5737 }
5738
5739 /* mtdcrux (PPC 460) : user-mode access to DCR */
5740 static void gen_mtdcrux(DisasContext *ctx)
5741 {
5742 /* NIP cannot be restored if the memory exception comes from an helper */
5743 gen_update_nip(ctx, ctx->nip - 4);
5744 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5745 cpu_gpr[rS(ctx->opcode)]);
5746 /* Note: Rc update flag set leads to undefined state of Rc0 */
5747 }
5748
5749 /* dccci */
5750 static void gen_dccci(DisasContext *ctx)
5751 {
5752 #if defined(CONFIG_USER_ONLY)
5753 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5754 #else
5755 if (unlikely(!ctx->mem_idx)) {
5756 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5757 return;
5758 }
5759 /* interpreted as no-op */
5760 #endif
5761 }
5762
5763 /* dcread */
5764 static void gen_dcread(DisasContext *ctx)
5765 {
5766 #if defined(CONFIG_USER_ONLY)
5767 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5768 #else
5769 TCGv EA, val;
5770 if (unlikely(!ctx->mem_idx)) {
5771 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5772 return;
5773 }
5774 gen_set_access_type(ctx, ACCESS_CACHE);
5775 EA = tcg_temp_new();
5776 gen_addr_reg_index(ctx, EA);
5777 val = tcg_temp_new();
5778 gen_qemu_ld32u(ctx, val, EA);
5779 tcg_temp_free(val);
5780 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5781 tcg_temp_free(EA);
5782 #endif
5783 }
5784
5785 /* icbt */
5786 static void gen_icbt_40x(DisasContext *ctx)
5787 {
5788 /* interpreted as no-op */
5789 /* XXX: specification say this is treated as a load by the MMU
5790 * but does not generate any exception
5791 */
5792 }
5793
5794 /* iccci */
5795 static void gen_iccci(DisasContext *ctx)
5796 {
5797 #if defined(CONFIG_USER_ONLY)
5798 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5799 #else
5800 if (unlikely(!ctx->mem_idx)) {
5801 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5802 return;
5803 }
5804 /* interpreted as no-op */
5805 #endif
5806 }
5807
5808 /* icread */
5809 static void gen_icread(DisasContext *ctx)
5810 {
5811 #if defined(CONFIG_USER_ONLY)
5812 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5813 #else
5814 if (unlikely(!ctx->mem_idx)) {
5815 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5816 return;
5817 }
5818 /* interpreted as no-op */
5819 #endif
5820 }
5821
5822 /* rfci (mem_idx only) */
5823 static void gen_rfci_40x(DisasContext *ctx)
5824 {
5825 #if defined(CONFIG_USER_ONLY)
5826 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5827 #else
5828 if (unlikely(!ctx->mem_idx)) {
5829 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5830 return;
5831 }
5832 /* Restore CPU state */
5833 gen_helper_40x_rfci(cpu_env);
5834 gen_sync_exception(ctx);
5835 #endif
5836 }
5837
5838 static void gen_rfci(DisasContext *ctx)
5839 {
5840 #if defined(CONFIG_USER_ONLY)
5841 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5842 #else
5843 if (unlikely(!ctx->mem_idx)) {
5844 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5845 return;
5846 }
5847 /* Restore CPU state */
5848 gen_helper_rfci(cpu_env);
5849 gen_sync_exception(ctx);
5850 #endif
5851 }
5852
5853 /* BookE specific */
5854
5855 /* XXX: not implemented on 440 ? */
5856 static void gen_rfdi(DisasContext *ctx)
5857 {
5858 #if defined(CONFIG_USER_ONLY)
5859 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5860 #else
5861 if (unlikely(!ctx->mem_idx)) {
5862 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5863 return;
5864 }
5865 /* Restore CPU state */
5866 gen_helper_rfdi(cpu_env);
5867 gen_sync_exception(ctx);
5868 #endif
5869 }
5870
5871 /* XXX: not implemented on 440 ? */
5872 static void gen_rfmci(DisasContext *ctx)
5873 {
5874 #if defined(CONFIG_USER_ONLY)
5875 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5876 #else
5877 if (unlikely(!ctx->mem_idx)) {
5878 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5879 return;
5880 }
5881 /* Restore CPU state */
5882 gen_helper_rfmci(cpu_env);
5883 gen_sync_exception(ctx);
5884 #endif
5885 }
5886
5887 /* TLB management - PowerPC 405 implementation */
5888
5889 /* tlbre */
5890 static void gen_tlbre_40x(DisasContext *ctx)
5891 {
5892 #if defined(CONFIG_USER_ONLY)
5893 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5894 #else
5895 if (unlikely(!ctx->mem_idx)) {
5896 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5897 return;
5898 }
5899 switch (rB(ctx->opcode)) {
5900 case 0:
5901 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5902 cpu_gpr[rA(ctx->opcode)]);
5903 break;
5904 case 1:
5905 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5906 cpu_gpr[rA(ctx->opcode)]);
5907 break;
5908 default:
5909 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5910 break;
5911 }
5912 #endif
5913 }
5914
5915 /* tlbsx - tlbsx. */
5916 static void gen_tlbsx_40x(DisasContext *ctx)
5917 {
5918 #if defined(CONFIG_USER_ONLY)
5919 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5920 #else
5921 TCGv t0;
5922 if (unlikely(!ctx->mem_idx)) {
5923 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5924 return;
5925 }
5926 t0 = tcg_temp_new();
5927 gen_addr_reg_index(ctx, t0);
5928 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5929 tcg_temp_free(t0);
5930 if (Rc(ctx->opcode)) {
5931 int l1 = gen_new_label();
5932 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5933 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5934 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5935 gen_set_label(l1);
5936 }
5937 #endif
5938 }
5939
5940 /* tlbwe */
5941 static void gen_tlbwe_40x(DisasContext *ctx)
5942 {
5943 #if defined(CONFIG_USER_ONLY)
5944 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5945 #else
5946 if (unlikely(!ctx->mem_idx)) {
5947 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5948 return;
5949 }
5950 switch (rB(ctx->opcode)) {
5951 case 0:
5952 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5953 cpu_gpr[rS(ctx->opcode)]);
5954 break;
5955 case 1:
5956 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5957 cpu_gpr[rS(ctx->opcode)]);
5958 break;
5959 default:
5960 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5961 break;
5962 }
5963 #endif
5964 }
5965
5966 /* TLB management - PowerPC 440 implementation */
5967
5968 /* tlbre */
5969 static void gen_tlbre_440(DisasContext *ctx)
5970 {
5971 #if defined(CONFIG_USER_ONLY)
5972 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5973 #else
5974 if (unlikely(!ctx->mem_idx)) {
5975 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5976 return;
5977 }
5978 switch (rB(ctx->opcode)) {
5979 case 0:
5980 case 1:
5981 case 2:
5982 {
5983 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5984 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5985 t0, cpu_gpr[rA(ctx->opcode)]);
5986 tcg_temp_free_i32(t0);
5987 }
5988 break;
5989 default:
5990 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5991 break;
5992 }
5993 #endif
5994 }
5995
5996 /* tlbsx - tlbsx. */
5997 static void gen_tlbsx_440(DisasContext *ctx)
5998 {
5999 #if defined(CONFIG_USER_ONLY)
6000 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6001 #else
6002 TCGv t0;
6003 if (unlikely(!ctx->mem_idx)) {
6004 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6005 return;
6006 }
6007 t0 = tcg_temp_new();
6008 gen_addr_reg_index(ctx, t0);
6009 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6010 tcg_temp_free(t0);
6011 if (Rc(ctx->opcode)) {
6012 int l1 = gen_new_label();
6013 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6014 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6015 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6016 gen_set_label(l1);
6017 }
6018 #endif
6019 }
6020
6021 /* tlbwe */
6022 static void gen_tlbwe_440(DisasContext *ctx)
6023 {
6024 #if defined(CONFIG_USER_ONLY)
6025 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6026 #else
6027 if (unlikely(!ctx->mem_idx)) {
6028 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6029 return;
6030 }
6031 switch (rB(ctx->opcode)) {
6032 case 0:
6033 case 1:
6034 case 2:
6035 {
6036 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6037 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6038 cpu_gpr[rS(ctx->opcode)]);
6039 tcg_temp_free_i32(t0);
6040 }
6041 break;
6042 default:
6043 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6044 break;
6045 }
6046 #endif
6047 }
6048
6049 /* TLB management - PowerPC BookE 2.06 implementation */
6050
6051 /* tlbre */
6052 static void gen_tlbre_booke206(DisasContext *ctx)
6053 {
6054 #if defined(CONFIG_USER_ONLY)
6055 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6056 #else
6057 if (unlikely(!ctx->mem_idx)) {
6058 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6059 return;
6060 }
6061
6062 gen_helper_booke206_tlbre(cpu_env);
6063 #endif
6064 }
6065
6066 /* tlbsx - tlbsx. */
6067 static void gen_tlbsx_booke206(DisasContext *ctx)
6068 {
6069 #if defined(CONFIG_USER_ONLY)
6070 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6071 #else
6072 TCGv t0;
6073 if (unlikely(!ctx->mem_idx)) {
6074 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6075 return;
6076 }
6077
6078 if (rA(ctx->opcode)) {
6079 t0 = tcg_temp_new();
6080 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6081 } else {
6082 t0 = tcg_const_tl(0);
6083 }
6084
6085 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6086 gen_helper_booke206_tlbsx(cpu_env, t0);
6087 #endif
6088 }
6089
6090 /* tlbwe */
6091 static void gen_tlbwe_booke206(DisasContext *ctx)
6092 {
6093 #if defined(CONFIG_USER_ONLY)
6094 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6095 #else
6096 if (unlikely(!ctx->mem_idx)) {
6097 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6098 return;
6099 }
6100 gen_update_nip(ctx, ctx->nip - 4);
6101 gen_helper_booke206_tlbwe(cpu_env);
6102 #endif
6103 }
6104
6105 static void gen_tlbivax_booke206(DisasContext *ctx)
6106 {
6107 #if defined(CONFIG_USER_ONLY)
6108 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6109 #else
6110 TCGv t0;
6111 if (unlikely(!ctx->mem_idx)) {
6112 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6113 return;
6114 }
6115
6116 t0 = tcg_temp_new();
6117 gen_addr_reg_index(ctx, t0);
6118
6119 gen_helper_booke206_tlbivax(cpu_env, t0);
6120 #endif
6121 }
6122
6123 static void gen_tlbilx_booke206(DisasContext *ctx)
6124 {
6125 #if defined(CONFIG_USER_ONLY)
6126 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6127 #else
6128 TCGv t0;
6129 if (unlikely(!ctx->mem_idx)) {
6130 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6131 return;
6132 }
6133
6134 t0 = tcg_temp_new();
6135 gen_addr_reg_index(ctx, t0);
6136
6137 switch((ctx->opcode >> 21) & 0x3) {
6138 case 0:
6139 gen_helper_booke206_tlbilx0(cpu_env, t0);
6140 break;
6141 case 1:
6142 gen_helper_booke206_tlbilx1(cpu_env, t0);
6143 break;
6144 case 3:
6145 gen_helper_booke206_tlbilx3(cpu_env, t0);
6146 break;
6147 default:
6148 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6149 break;
6150 }
6151
6152 tcg_temp_free(t0);
6153 #endif
6154 }
6155
6156
6157 /* wrtee */
6158 static void gen_wrtee(DisasContext *ctx)
6159 {
6160 #if defined(CONFIG_USER_ONLY)
6161 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6162 #else
6163 TCGv t0;
6164 if (unlikely(!ctx->mem_idx)) {
6165 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6166 return;
6167 }
6168 t0 = tcg_temp_new();
6169 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6170 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6171 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6172 tcg_temp_free(t0);
6173 /* Stop translation to have a chance to raise an exception
6174 * if we just set msr_ee to 1
6175 */
6176 gen_stop_exception(ctx);
6177 #endif
6178 }
6179
6180 /* wrteei */
6181 static void gen_wrteei(DisasContext *ctx)
6182 {
6183 #if defined(CONFIG_USER_ONLY)
6184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6185 #else
6186 if (unlikely(!ctx->mem_idx)) {
6187 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6188 return;
6189 }
6190 if (ctx->opcode & 0x00008000) {
6191 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6192 /* Stop translation to have a chance to raise an exception */
6193 gen_stop_exception(ctx);
6194 } else {
6195 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6196 }
6197 #endif
6198 }
6199
6200 /* PowerPC 440 specific instructions */
6201
6202 /* dlmzb */
6203 static void gen_dlmzb(DisasContext *ctx)
6204 {
6205 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6206 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6207 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6208 tcg_temp_free_i32(t0);
6209 }
6210
6211 /* mbar replaces eieio on 440 */
6212 static void gen_mbar(DisasContext *ctx)
6213 {
6214 /* interpreted as no-op */
6215 }
6216
6217 /* msync replaces sync on 440 */
6218 static void gen_msync_4xx(DisasContext *ctx)
6219 {
6220 /* interpreted as no-op */
6221 }
6222
6223 /* icbt */
6224 static void gen_icbt_440(DisasContext *ctx)
6225 {
6226 /* interpreted as no-op */
6227 /* XXX: specification say this is treated as a load by the MMU
6228 * but does not generate any exception
6229 */
6230 }
6231
6232 /* Embedded.Processor Control */
6233
6234 static void gen_msgclr(DisasContext *ctx)
6235 {
6236 #if defined(CONFIG_USER_ONLY)
6237 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6238 #else
6239 if (unlikely(ctx->mem_idx == 0)) {
6240 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6241 return;
6242 }
6243
6244 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6245 #endif
6246 }
6247
6248 static void gen_msgsnd(DisasContext *ctx)
6249 {
6250 #if defined(CONFIG_USER_ONLY)
6251 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6252 #else
6253 if (unlikely(ctx->mem_idx == 0)) {
6254 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6255 return;
6256 }
6257
6258 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6259 #endif
6260 }
6261
6262 /*** Altivec vector extension ***/
6263 /* Altivec registers moves */
6264
6265 static inline TCGv_ptr gen_avr_ptr(int reg)
6266 {
6267 TCGv_ptr r = tcg_temp_new_ptr();
6268 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6269 return r;
6270 }
6271
6272 #define GEN_VR_LDX(name, opc2, opc3) \
6273 static void glue(gen_, name)(DisasContext *ctx) \
6274 { \
6275 TCGv EA; \
6276 if (unlikely(!ctx->altivec_enabled)) { \
6277 gen_exception(ctx, POWERPC_EXCP_VPU); \
6278 return; \
6279 } \
6280 gen_set_access_type(ctx, ACCESS_INT); \
6281 EA = tcg_temp_new(); \
6282 gen_addr_reg_index(ctx, EA); \
6283 tcg_gen_andi_tl(EA, EA, ~0xf); \
6284 if (ctx->le_mode) { \
6285 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6286 tcg_gen_addi_tl(EA, EA, 8); \
6287 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6288 } else { \
6289 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6290 tcg_gen_addi_tl(EA, EA, 8); \
6291 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6292 } \
6293 tcg_temp_free(EA); \
6294 }
6295
6296 #define GEN_VR_STX(name, opc2, opc3) \
6297 static void gen_st##name(DisasContext *ctx) \
6298 { \
6299 TCGv EA; \
6300 if (unlikely(!ctx->altivec_enabled)) { \
6301 gen_exception(ctx, POWERPC_EXCP_VPU); \
6302 return; \
6303 } \
6304 gen_set_access_type(ctx, ACCESS_INT); \
6305 EA = tcg_temp_new(); \
6306 gen_addr_reg_index(ctx, EA); \
6307 tcg_gen_andi_tl(EA, EA, ~0xf); \
6308 if (ctx->le_mode) { \
6309 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6310 tcg_gen_addi_tl(EA, EA, 8); \
6311 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6312 } else { \
6313 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6314 tcg_gen_addi_tl(EA, EA, 8); \
6315 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6316 } \
6317 tcg_temp_free(EA); \
6318 }
6319
6320 #define GEN_VR_LVE(name, opc2, opc3) \
6321 static void gen_lve##name(DisasContext *ctx) \
6322 { \
6323 TCGv EA; \
6324 TCGv_ptr rs; \
6325 if (unlikely(!ctx->altivec_enabled)) { \
6326 gen_exception(ctx, POWERPC_EXCP_VPU); \
6327 return; \
6328 } \
6329 gen_set_access_type(ctx, ACCESS_INT); \
6330 EA = tcg_temp_new(); \
6331 gen_addr_reg_index(ctx, EA); \
6332 rs = gen_avr_ptr(rS(ctx->opcode)); \
6333 gen_helper_lve##name(cpu_env, rs, EA); \
6334 tcg_temp_free(EA); \
6335 tcg_temp_free_ptr(rs); \
6336 }
6337
6338 #define GEN_VR_STVE(name, opc2, opc3) \
6339 static void gen_stve##name(DisasContext *ctx) \
6340 { \
6341 TCGv EA; \
6342 TCGv_ptr rs; \
6343 if (unlikely(!ctx->altivec_enabled)) { \
6344 gen_exception(ctx, POWERPC_EXCP_VPU); \
6345 return; \
6346 } \
6347 gen_set_access_type(ctx, ACCESS_INT); \
6348 EA = tcg_temp_new(); \
6349 gen_addr_reg_index(ctx, EA); \
6350 rs = gen_avr_ptr(rS(ctx->opcode)); \
6351 gen_helper_stve##name(cpu_env, rs, EA); \
6352 tcg_temp_free(EA); \
6353 tcg_temp_free_ptr(rs); \
6354 }
6355
6356 GEN_VR_LDX(lvx, 0x07, 0x03);
6357 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6358 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6359
6360 GEN_VR_LVE(bx, 0x07, 0x00);
6361 GEN_VR_LVE(hx, 0x07, 0x01);
6362 GEN_VR_LVE(wx, 0x07, 0x02);
6363
6364 GEN_VR_STX(svx, 0x07, 0x07);
6365 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6366 GEN_VR_STX(svxl, 0x07, 0x0F);
6367
6368 GEN_VR_STVE(bx, 0x07, 0x04);
6369 GEN_VR_STVE(hx, 0x07, 0x05);
6370 GEN_VR_STVE(wx, 0x07, 0x06);
6371
6372 static void gen_lvsl(DisasContext *ctx)
6373 {
6374 TCGv_ptr rd;
6375 TCGv EA;
6376 if (unlikely(!ctx->altivec_enabled)) {
6377 gen_exception(ctx, POWERPC_EXCP_VPU);
6378 return;
6379 }
6380 EA = tcg_temp_new();
6381 gen_addr_reg_index(ctx, EA);
6382 rd = gen_avr_ptr(rD(ctx->opcode));
6383 gen_helper_lvsl(rd, EA);
6384 tcg_temp_free(EA);
6385 tcg_temp_free_ptr(rd);
6386 }
6387
6388 static void gen_lvsr(DisasContext *ctx)
6389 {
6390 TCGv_ptr rd;
6391 TCGv EA;
6392 if (unlikely(!ctx->altivec_enabled)) {
6393 gen_exception(ctx, POWERPC_EXCP_VPU);
6394 return;
6395 }
6396 EA = tcg_temp_new();
6397 gen_addr_reg_index(ctx, EA);
6398 rd = gen_avr_ptr(rD(ctx->opcode));
6399 gen_helper_lvsr(rd, EA);
6400 tcg_temp_free(EA);
6401 tcg_temp_free_ptr(rd);
6402 }
6403
6404 static void gen_mfvscr(DisasContext *ctx)
6405 {
6406 TCGv_i32 t;
6407 if (unlikely(!ctx->altivec_enabled)) {
6408 gen_exception(ctx, POWERPC_EXCP_VPU);
6409 return;
6410 }
6411 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6412 t = tcg_temp_new_i32();
6413 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6414 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6415 tcg_temp_free_i32(t);
6416 }
6417
6418 static void gen_mtvscr(DisasContext *ctx)
6419 {
6420 TCGv_ptr p;
6421 if (unlikely(!ctx->altivec_enabled)) {
6422 gen_exception(ctx, POWERPC_EXCP_VPU);
6423 return;
6424 }
6425 p = gen_avr_ptr(rD(ctx->opcode));
6426 gen_helper_mtvscr(cpu_env, p);
6427 tcg_temp_free_ptr(p);
6428 }
6429
6430 /* Logical operations */
6431 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6432 static void glue(gen_, name)(DisasContext *ctx) \
6433 { \
6434 if (unlikely(!ctx->altivec_enabled)) { \
6435 gen_exception(ctx, POWERPC_EXCP_VPU); \
6436 return; \
6437 } \
6438 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6439 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6440 }
6441
6442 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6443 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6444 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6445 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6446 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6447
6448 #define GEN_VXFORM(name, opc2, opc3) \
6449 static void glue(gen_, name)(DisasContext *ctx) \
6450 { \
6451 TCGv_ptr ra, rb, rd; \
6452 if (unlikely(!ctx->altivec_enabled)) { \
6453 gen_exception(ctx, POWERPC_EXCP_VPU); \
6454 return; \
6455 } \
6456 ra = gen_avr_ptr(rA(ctx->opcode)); \
6457 rb = gen_avr_ptr(rB(ctx->opcode)); \
6458 rd = gen_avr_ptr(rD(ctx->opcode)); \
6459 gen_helper_##name (rd, ra, rb); \
6460 tcg_temp_free_ptr(ra); \
6461 tcg_temp_free_ptr(rb); \
6462 tcg_temp_free_ptr(rd); \
6463 }
6464
6465 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6466 static void glue(gen_, name)(DisasContext *ctx) \
6467 { \
6468 TCGv_ptr ra, rb, rd; \
6469 if (unlikely(!ctx->altivec_enabled)) { \
6470 gen_exception(ctx, POWERPC_EXCP_VPU); \
6471 return; \
6472 } \
6473 ra = gen_avr_ptr(rA(ctx->opcode)); \
6474 rb = gen_avr_ptr(rB(ctx->opcode)); \
6475 rd = gen_avr_ptr(rD(ctx->opcode)); \
6476 gen_helper_##name(cpu_env, rd, ra, rb); \
6477 tcg_temp_free_ptr(ra); \
6478 tcg_temp_free_ptr(rb); \
6479 tcg_temp_free_ptr(rd); \
6480 }
6481
6482 GEN_VXFORM(vaddubm, 0, 0);
6483 GEN_VXFORM(vadduhm, 0, 1);
6484 GEN_VXFORM(vadduwm, 0, 2);
6485 GEN_VXFORM(vsububm, 0, 16);
6486 GEN_VXFORM(vsubuhm, 0, 17);
6487 GEN_VXFORM(vsubuwm, 0, 18);
6488 GEN_VXFORM(vmaxub, 1, 0);
6489 GEN_VXFORM(vmaxuh, 1, 1);
6490 GEN_VXFORM(vmaxuw, 1, 2);
6491 GEN_VXFORM(vmaxsb, 1, 4);
6492 GEN_VXFORM(vmaxsh, 1, 5);
6493 GEN_VXFORM(vmaxsw, 1, 6);
6494 GEN_VXFORM(vminub, 1, 8);
6495 GEN_VXFORM(vminuh, 1, 9);
6496 GEN_VXFORM(vminuw, 1, 10);
6497 GEN_VXFORM(vminsb, 1, 12);
6498 GEN_VXFORM(vminsh, 1, 13);
6499 GEN_VXFORM(vminsw, 1, 14);
6500 GEN_VXFORM(vavgub, 1, 16);
6501 GEN_VXFORM(vavguh, 1, 17);
6502 GEN_VXFORM(vavguw, 1, 18);
6503 GEN_VXFORM(vavgsb, 1, 20);
6504 GEN_VXFORM(vavgsh, 1, 21);
6505 GEN_VXFORM(vavgsw, 1, 22);
6506 GEN_VXFORM(vmrghb, 6, 0);
6507 GEN_VXFORM(vmrghh, 6, 1);
6508 GEN_VXFORM(vmrghw, 6, 2);
6509 GEN_VXFORM(vmrglb, 6, 4);
6510 GEN_VXFORM(vmrglh, 6, 5);
6511 GEN_VXFORM(vmrglw, 6, 6);
6512 GEN_VXFORM(vmuloub, 4, 0);
6513 GEN_VXFORM(vmulouh, 4, 1);
6514 GEN_VXFORM(vmulosb, 4, 4);
6515 GEN_VXFORM(vmulosh, 4, 5);
6516 GEN_VXFORM(vmuleub, 4, 8);
6517 GEN_VXFORM(vmuleuh, 4, 9);
6518 GEN_VXFORM(vmulesb, 4, 12);
6519 GEN_VXFORM(vmulesh, 4, 13);
6520 GEN_VXFORM(vslb, 2, 4);
6521 GEN_VXFORM(vslh, 2, 5);
6522 GEN_VXFORM(vslw, 2, 6);
6523 GEN_VXFORM(vsrb, 2, 8);
6524 GEN_VXFORM(vsrh, 2, 9);
6525 GEN_VXFORM(vsrw, 2, 10);
6526 GEN_VXFORM(vsrab, 2, 12);
6527 GEN_VXFORM(vsrah, 2, 13);
6528 GEN_VXFORM(vsraw, 2, 14);
6529 GEN_VXFORM(vslo, 6, 16);
6530 GEN_VXFORM(vsro, 6, 17);
6531 GEN_VXFORM(vaddcuw, 0, 6);
6532 GEN_VXFORM(vsubcuw, 0, 22);
6533 GEN_VXFORM_ENV(vaddubs, 0, 8);
6534 GEN_VXFORM_ENV(vadduhs, 0, 9);
6535 GEN_VXFORM_ENV(vadduws, 0, 10);
6536 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6537 GEN_VXFORM_ENV(vaddshs, 0, 13);
6538 GEN_VXFORM_ENV(vaddsws, 0, 14);
6539 GEN_VXFORM_ENV(vsububs, 0, 24);
6540 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6541 GEN_VXFORM_ENV(vsubuws, 0, 26);
6542 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6543 GEN_VXFORM_ENV(vsubshs, 0, 29);
6544 GEN_VXFORM_ENV(vsubsws, 0, 30);
6545 GEN_VXFORM(vrlb, 2, 0);
6546 GEN_VXFORM(vrlh, 2, 1);
6547 GEN_VXFORM(vrlw, 2, 2);
6548 GEN_VXFORM(vsl, 2, 7);
6549 GEN_VXFORM(vsr, 2, 11);
6550 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6551 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6552 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6553 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6554 GEN_VXFORM_ENV(vpkshus, 7, 4);
6555 GEN_VXFORM_ENV(vpkswus, 7, 5);
6556 GEN_VXFORM_ENV(vpkshss, 7, 6);
6557 GEN_VXFORM_ENV(vpkswss, 7, 7);
6558 GEN_VXFORM(vpkpx, 7, 12);
6559 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6560 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6561 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6562 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6563 GEN_VXFORM_ENV(vsumsws, 4, 30);
6564 GEN_VXFORM_ENV(vaddfp, 5, 0);
6565 GEN_VXFORM_ENV(vsubfp, 5, 1);
6566 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6567 GEN_VXFORM_ENV(vminfp, 5, 17);
6568
6569 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6570 static void glue(gen_, name)(DisasContext *ctx) \
6571 { \
6572 TCGv_ptr ra, rb, rd; \
6573 if (unlikely(!ctx->altivec_enabled)) { \
6574 gen_exception(ctx, POWERPC_EXCP_VPU); \
6575 return; \
6576 } \
6577 ra = gen_avr_ptr(rA(ctx->opcode)); \
6578 rb = gen_avr_ptr(rB(ctx->opcode)); \
6579 rd = gen_avr_ptr(rD(ctx->opcode)); \
6580 gen_helper_##opname(cpu_env, rd, ra, rb); \
6581 tcg_temp_free_ptr(ra); \
6582 tcg_temp_free_ptr(rb); \
6583 tcg_temp_free_ptr(rd); \
6584 }
6585
6586 #define GEN_VXRFORM(name, opc2, opc3) \
6587 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6588 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6589
6590 GEN_VXRFORM(vcmpequb, 3, 0)
6591 GEN_VXRFORM(vcmpequh, 3, 1)
6592 GEN_VXRFORM(vcmpequw, 3, 2)
6593 GEN_VXRFORM(vcmpgtsb, 3, 12)
6594 GEN_VXRFORM(vcmpgtsh, 3, 13)
6595 GEN_VXRFORM(vcmpgtsw, 3, 14)
6596 GEN_VXRFORM(vcmpgtub, 3, 8)
6597 GEN_VXRFORM(vcmpgtuh, 3, 9)
6598 GEN_VXRFORM(vcmpgtuw, 3, 10)
6599 GEN_VXRFORM(vcmpeqfp, 3, 3)
6600 GEN_VXRFORM(vcmpgefp, 3, 7)
6601 GEN_VXRFORM(vcmpgtfp, 3, 11)
6602 GEN_VXRFORM(vcmpbfp, 3, 15)
6603
6604 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6605 static void glue(gen_, name)(DisasContext *ctx) \
6606 { \
6607 TCGv_ptr rd; \
6608 TCGv_i32 simm; \
6609 if (unlikely(!ctx->altivec_enabled)) { \
6610 gen_exception(ctx, POWERPC_EXCP_VPU); \
6611 return; \
6612 } \
6613 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6614 rd = gen_avr_ptr(rD(ctx->opcode)); \
6615 gen_helper_##name (rd, simm); \
6616 tcg_temp_free_i32(simm); \
6617 tcg_temp_free_ptr(rd); \
6618 }
6619
6620 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6621 GEN_VXFORM_SIMM(vspltish, 6, 13);
6622 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6623
6624 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6625 static void glue(gen_, name)(DisasContext *ctx) \
6626 { \
6627 TCGv_ptr rb, rd; \
6628 if (unlikely(!ctx->altivec_enabled)) { \
6629 gen_exception(ctx, POWERPC_EXCP_VPU); \
6630 return; \
6631 } \
6632 rb = gen_avr_ptr(rB(ctx->opcode)); \
6633 rd = gen_avr_ptr(rD(ctx->opcode)); \
6634 gen_helper_##name (rd, rb); \
6635 tcg_temp_free_ptr(rb); \
6636 tcg_temp_free_ptr(rd); \
6637 }
6638
6639 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6640 static void glue(gen_, name)(DisasContext *ctx) \
6641 { \
6642 TCGv_ptr rb, rd; \
6643 \
6644 if (unlikely(!ctx->altivec_enabled)) { \
6645 gen_exception(ctx, POWERPC_EXCP_VPU); \
6646 return; \
6647 } \
6648 rb = gen_avr_ptr(rB(ctx->opcode)); \
6649 rd = gen_avr_ptr(rD(ctx->opcode)); \
6650 gen_helper_##name(cpu_env, rd, rb); \
6651 tcg_temp_free_ptr(rb); \
6652 tcg_temp_free_ptr(rd); \
6653 }
6654
6655 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6656 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6657 GEN_VXFORM_NOA(vupklsb, 7, 10);
6658 GEN_VXFORM_NOA(vupklsh, 7, 11);
6659 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6660 GEN_VXFORM_NOA(vupklpx, 7, 15);
6661 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6662 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6663 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6664 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6665 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6666 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6667 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6668 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6669
6670 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6671 static void glue(gen_, name)(DisasContext *ctx) \
6672 { \
6673 TCGv_ptr rd; \
6674 TCGv_i32 simm; \
6675 if (unlikely(!ctx->altivec_enabled)) { \
6676 gen_exception(ctx, POWERPC_EXCP_VPU); \
6677 return; \
6678 } \
6679 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6680 rd = gen_avr_ptr(rD(ctx->opcode)); \
6681 gen_helper_##name (rd, simm); \
6682 tcg_temp_free_i32(simm); \
6683 tcg_temp_free_ptr(rd); \
6684 }
6685
6686 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6687 static void glue(gen_, name)(DisasContext *ctx) \
6688 { \
6689 TCGv_ptr rb, rd; \
6690 TCGv_i32 uimm; \
6691 if (unlikely(!ctx->altivec_enabled)) { \
6692 gen_exception(ctx, POWERPC_EXCP_VPU); \
6693 return; \
6694 } \
6695 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6696 rb = gen_avr_ptr(rB(ctx->opcode)); \
6697 rd = gen_avr_ptr(rD(ctx->opcode)); \
6698 gen_helper_##name (rd, rb, uimm); \
6699 tcg_temp_free_i32(uimm); \
6700 tcg_temp_free_ptr(rb); \
6701 tcg_temp_free_ptr(rd); \
6702 }
6703
6704 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6705 static void glue(gen_, name)(DisasContext *ctx) \
6706 { \
6707 TCGv_ptr rb, rd; \
6708 TCGv_i32 uimm; \
6709 \
6710 if (unlikely(!ctx->altivec_enabled)) { \
6711 gen_exception(ctx, POWERPC_EXCP_VPU); \
6712 return; \
6713 } \
6714 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6715 rb = gen_avr_ptr(rB(ctx->opcode)); \
6716 rd = gen_avr_ptr(rD(ctx->opcode)); \
6717 gen_helper_##name(cpu_env, rd, rb, uimm); \
6718 tcg_temp_free_i32(uimm); \
6719 tcg_temp_free_ptr(rb); \
6720 tcg_temp_free_ptr(rd); \
6721 }
6722
6723 GEN_VXFORM_UIMM(vspltb, 6, 8);
6724 GEN_VXFORM_UIMM(vsplth, 6, 9);
6725 GEN_VXFORM_UIMM(vspltw, 6, 10);
6726 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6727 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6728 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6729 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6730
6731 static void gen_vsldoi(DisasContext *ctx)
6732 {
6733 TCGv_ptr ra, rb, rd;
6734 TCGv_i32 sh;
6735 if (unlikely(!ctx->altivec_enabled)) {
6736 gen_exception(ctx, POWERPC_EXCP_VPU);
6737 return;
6738 }
6739 ra = gen_avr_ptr(rA(ctx->opcode));
6740 rb = gen_avr_ptr(rB(ctx->opcode));
6741 rd = gen_avr_ptr(rD(ctx->opcode));
6742 sh = tcg_const_i32(VSH(ctx->opcode));
6743 gen_helper_vsldoi (rd, ra, rb, sh);
6744 tcg_temp_free_ptr(ra);
6745 tcg_temp_free_ptr(rb);
6746 tcg_temp_free_ptr(rd);
6747 tcg_temp_free_i32(sh);
6748 }
6749
6750 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6751 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6752 { \
6753 TCGv_ptr ra, rb, rc, rd; \
6754 if (unlikely(!ctx->altivec_enabled)) { \
6755 gen_exception(ctx, POWERPC_EXCP_VPU); \
6756 return; \
6757 } \
6758 ra = gen_avr_ptr(rA(ctx->opcode)); \
6759 rb = gen_avr_ptr(rB(ctx->opcode)); \
6760 rc = gen_avr_ptr(rC(ctx->opcode)); \
6761 rd = gen_avr_ptr(rD(ctx->opcode)); \
6762 if (Rc(ctx->opcode)) { \
6763 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6764 } else { \
6765 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6766 } \
6767 tcg_temp_free_ptr(ra); \
6768 tcg_temp_free_ptr(rb); \
6769 tcg_temp_free_ptr(rc); \
6770 tcg_temp_free_ptr(rd); \
6771 }
6772
6773 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6774
6775 static void gen_vmladduhm(DisasContext *ctx)
6776 {
6777 TCGv_ptr ra, rb, rc, rd;
6778 if (unlikely(!ctx->altivec_enabled)) {
6779 gen_exception(ctx, POWERPC_EXCP_VPU);
6780 return;
6781 }
6782 ra = gen_avr_ptr(rA(ctx->opcode));
6783 rb = gen_avr_ptr(rB(ctx->opcode));
6784 rc = gen_avr_ptr(rC(ctx->opcode));
6785 rd = gen_avr_ptr(rD(ctx->opcode));
6786 gen_helper_vmladduhm(rd, ra, rb, rc);
6787 tcg_temp_free_ptr(ra);
6788 tcg_temp_free_ptr(rb);
6789 tcg_temp_free_ptr(rc);
6790 tcg_temp_free_ptr(rd);
6791 }
6792
6793 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6794 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6795 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6796 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6797 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6798
6799 /*** SPE extension ***/
6800 /* Register moves */
6801
6802
6803 static inline void gen_evmra(DisasContext *ctx)
6804 {
6805
6806 if (unlikely(!ctx->spe_enabled)) {
6807 gen_exception(ctx, POWERPC_EXCP_SPEU);
6808 return;
6809 }
6810
6811 #if defined(TARGET_PPC64)
6812 /* rD := rA */
6813 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6814
6815 /* spe_acc := rA */
6816 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6817 cpu_env,
6818 offsetof(CPUPPCState, spe_acc));
6819 #else
6820 TCGv_i64 tmp = tcg_temp_new_i64();
6821
6822 /* tmp := rA_lo + rA_hi << 32 */
6823 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6824
6825 /* spe_acc := tmp */
6826 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6827 tcg_temp_free_i64(tmp);
6828
6829 /* rD := rA */
6830 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6831 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6832 #endif
6833 }
6834
6835 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6836 {
6837 #if defined(TARGET_PPC64)
6838 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6839 #else
6840 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6841 #endif
6842 }
6843
6844 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6845 {
6846 #if defined(TARGET_PPC64)
6847 tcg_gen_mov_i64(cpu_gpr[reg], t);
6848 #else
6849 TCGv_i64 tmp = tcg_temp_new_i64();
6850 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6851 tcg_gen_shri_i64(tmp, t, 32);
6852 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6853 tcg_temp_free_i64(tmp);
6854 #endif
6855 }
6856
6857 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6858 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6859 { \
6860 if (Rc(ctx->opcode)) \
6861 gen_##name1(ctx); \
6862 else \
6863 gen_##name0(ctx); \
6864 }
6865
6866 /* Handler for undefined SPE opcodes */
6867 static inline void gen_speundef(DisasContext *ctx)
6868 {
6869 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6870 }
6871
6872 /* SPE logic */
6873 #if defined(TARGET_PPC64)
6874 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6875 static inline void gen_##name(DisasContext *ctx) \
6876 { \
6877 if (unlikely(!ctx->spe_enabled)) { \
6878 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6879 return; \
6880 } \
6881 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6882 cpu_gpr[rB(ctx->opcode)]); \
6883 }
6884 #else
6885 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6886 static inline void gen_##name(DisasContext *ctx) \
6887 { \
6888 if (unlikely(!ctx->spe_enabled)) { \
6889 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6890 return; \
6891 } \
6892 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6893 cpu_gpr[rB(ctx->opcode)]); \
6894 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6895 cpu_gprh[rB(ctx->opcode)]); \
6896 }
6897 #endif
6898
6899 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6900 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6901 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6902 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6903 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6904 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6905 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6906 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6907
6908 /* SPE logic immediate */
6909 #if defined(TARGET_PPC64)
6910 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6911 static inline void gen_##name(DisasContext *ctx) \
6912 { \
6913 if (unlikely(!ctx->spe_enabled)) { \
6914 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6915 return; \
6916 } \
6917 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6918 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6919 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6920 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6921 tcg_opi(t0, t0, rB(ctx->opcode)); \
6922 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6923 tcg_gen_trunc_i64_i32(t1, t2); \
6924 tcg_temp_free_i64(t2); \
6925 tcg_opi(t1, t1, rB(ctx->opcode)); \
6926 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6927 tcg_temp_free_i32(t0); \
6928 tcg_temp_free_i32(t1); \
6929 }
6930 #else
6931 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6932 static inline void gen_##name(DisasContext *ctx) \
6933 { \
6934 if (unlikely(!ctx->spe_enabled)) { \
6935 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6936 return; \
6937 } \
6938 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6939 rB(ctx->opcode)); \
6940 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6941 rB(ctx->opcode)); \
6942 }
6943 #endif
6944 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6945 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6946 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6947 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6948
6949 /* SPE arithmetic */
6950 #if defined(TARGET_PPC64)
6951 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6952 static inline void gen_##name(DisasContext *ctx) \
6953 { \
6954 if (unlikely(!ctx->spe_enabled)) { \
6955 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6956 return; \
6957 } \
6958 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6959 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6960 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6961 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6962 tcg_op(t0, t0); \
6963 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6964 tcg_gen_trunc_i64_i32(t1, t2); \
6965 tcg_temp_free_i64(t2); \
6966 tcg_op(t1, t1); \
6967 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6968 tcg_temp_free_i32(t0); \
6969 tcg_temp_free_i32(t1); \
6970 }
6971 #else
6972 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6973 static inline void gen_##name(DisasContext *ctx) \
6974 { \
6975 if (unlikely(!ctx->spe_enabled)) { \
6976 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6977 return; \
6978 } \
6979 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6980 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6981 }
6982 #endif
6983
6984 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
6985 {
6986 int l1 = gen_new_label();
6987 int l2 = gen_new_label();
6988
6989 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6990 tcg_gen_neg_i32(ret, arg1);
6991 tcg_gen_br(l2);
6992 gen_set_label(l1);
6993 tcg_gen_mov_i32(ret, arg1);
6994 gen_set_label(l2);
6995 }
6996 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6997 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6998 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6999 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
7000 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
7001 {
7002 tcg_gen_addi_i32(ret, arg1, 0x8000);
7003 tcg_gen_ext16u_i32(ret, ret);
7004 }
7005 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
7006 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
7007 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
7008
7009 #if defined(TARGET_PPC64)
7010 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7011 static inline void gen_##name(DisasContext *ctx) \
7012 { \
7013 if (unlikely(!ctx->spe_enabled)) { \
7014 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7015 return; \
7016 } \
7017 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7018 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7019 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
7020 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
7021 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7022 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
7023 tcg_op(t0, t0, t2); \
7024 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
7025 tcg_gen_trunc_i64_i32(t1, t3); \
7026 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
7027 tcg_gen_trunc_i64_i32(t2, t3); \
7028 tcg_temp_free_i64(t3); \
7029 tcg_op(t1, t1, t2); \
7030 tcg_temp_free_i32(t2); \
7031 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7032 tcg_temp_free_i32(t0); \
7033 tcg_temp_free_i32(t1); \
7034 }
7035 #else
7036 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7037 static inline void gen_##name(DisasContext *ctx) \
7038 { \
7039 if (unlikely(!ctx->spe_enabled)) { \
7040 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7041 return; \
7042 } \
7043 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7044 cpu_gpr[rB(ctx->opcode)]); \
7045 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7046 cpu_gprh[rB(ctx->opcode)]); \
7047 }
7048 #endif
7049
7050 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7051 {
7052 TCGv_i32 t0;
7053 int l1, l2;
7054
7055 l1 = gen_new_label();
7056 l2 = gen_new_label();
7057 t0 = tcg_temp_local_new_i32();
7058 /* No error here: 6 bits are used */
7059 tcg_gen_andi_i32(t0, arg2, 0x3F);
7060 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7061 tcg_gen_shr_i32(ret, arg1, t0);
7062 tcg_gen_br(l2);
7063 gen_set_label(l1);
7064 tcg_gen_movi_i32(ret, 0);
7065 gen_set_label(l2);
7066 tcg_temp_free_i32(t0);
7067 }
7068 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7069 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7070 {
7071 TCGv_i32 t0;
7072 int l1, l2;
7073
7074 l1 = gen_new_label();
7075 l2 = gen_new_label();
7076 t0 = tcg_temp_local_new_i32();
7077 /* No error here: 6 bits are used */
7078 tcg_gen_andi_i32(t0, arg2, 0x3F);
7079 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7080 tcg_gen_sar_i32(ret, arg1, t0);
7081 tcg_gen_br(l2);
7082 gen_set_label(l1);
7083 tcg_gen_movi_i32(ret, 0);
7084 gen_set_label(l2);
7085 tcg_temp_free_i32(t0);
7086 }
7087 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7088 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7089 {
7090 TCGv_i32 t0;
7091 int l1, l2;
7092
7093 l1 = gen_new_label();
7094 l2 = gen_new_label();
7095 t0 = tcg_temp_local_new_i32();
7096 /* No error here: 6 bits are used */
7097 tcg_gen_andi_i32(t0, arg2, 0x3F);
7098 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7099 tcg_gen_shl_i32(ret, arg1, t0);
7100 tcg_gen_br(l2);
7101 gen_set_label(l1);
7102 tcg_gen_movi_i32(ret, 0);
7103 gen_set_label(l2);
7104 tcg_temp_free_i32(t0);
7105 }
7106 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7107 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7108 {
7109 TCGv_i32 t0 = tcg_temp_new_i32();
7110 tcg_gen_andi_i32(t0, arg2, 0x1F);
7111 tcg_gen_rotl_i32(ret, arg1, t0);
7112 tcg_temp_free_i32(t0);
7113 }
7114 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7115 static inline void gen_evmergehi(DisasContext *ctx)
7116 {
7117 if (unlikely(!ctx->spe_enabled)) {
7118 gen_exception(ctx, POWERPC_EXCP_SPEU);
7119 return;
7120 }
7121 #if defined(TARGET_PPC64)
7122 TCGv t0 = tcg_temp_new();
7123 TCGv t1 = tcg_temp_new();
7124 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7125 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7126 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7127 tcg_temp_free(t0);
7128 tcg_temp_free(t1);
7129 #else
7130 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7131 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7132 #endif
7133 }
7134 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7135 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7136 {
7137 tcg_gen_sub_i32(ret, arg2, arg1);
7138 }
7139 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7140
7141 /* SPE arithmetic immediate */
7142 #if defined(TARGET_PPC64)
7143 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7144 static inline void gen_##name(DisasContext *ctx) \
7145 { \
7146 if (unlikely(!ctx->spe_enabled)) { \
7147 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7148 return; \
7149 } \
7150 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7151 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7152 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7153 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7154 tcg_op(t0, t0, rA(ctx->opcode)); \
7155 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7156 tcg_gen_trunc_i64_i32(t1, t2); \
7157 tcg_temp_free_i64(t2); \
7158 tcg_op(t1, t1, rA(ctx->opcode)); \
7159 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7160 tcg_temp_free_i32(t0); \
7161 tcg_temp_free_i32(t1); \
7162 }
7163 #else
7164 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7165 static inline void gen_##name(DisasContext *ctx) \
7166 { \
7167 if (unlikely(!ctx->spe_enabled)) { \
7168 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7169 return; \
7170 } \
7171 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7172 rA(ctx->opcode)); \
7173 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7174 rA(ctx->opcode)); \
7175 }
7176 #endif
7177 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7178 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7179
7180 /* SPE comparison */
7181 #if defined(TARGET_PPC64)
7182 #define GEN_SPEOP_COMP(name, tcg_cond) \
7183 static inline void gen_##name(DisasContext *ctx) \
7184 { \
7185 if (unlikely(!ctx->spe_enabled)) { \
7186 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7187 return; \
7188 } \
7189 int l1 = gen_new_label(); \
7190 int l2 = gen_new_label(); \
7191 int l3 = gen_new_label(); \
7192 int l4 = gen_new_label(); \
7193 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7194 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7195 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7196 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7197 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7198 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7199 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7200 tcg_gen_br(l2); \
7201 gen_set_label(l1); \
7202 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7203 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7204 gen_set_label(l2); \
7205 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7206 tcg_gen_trunc_i64_i32(t0, t2); \
7207 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7208 tcg_gen_trunc_i64_i32(t1, t2); \
7209 tcg_temp_free_i64(t2); \
7210 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7211 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7212 ~(CRF_CH | CRF_CH_AND_CL)); \
7213 tcg_gen_br(l4); \
7214 gen_set_label(l3); \
7215 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7216 CRF_CH | CRF_CH_OR_CL); \
7217 gen_set_label(l4); \
7218 tcg_temp_free_i32(t0); \
7219 tcg_temp_free_i32(t1); \
7220 }
7221 #else
7222 #define GEN_SPEOP_COMP(name, tcg_cond) \
7223 static inline void gen_##name(DisasContext *ctx) \
7224 { \
7225 if (unlikely(!ctx->spe_enabled)) { \
7226 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7227 return; \
7228 } \
7229 int l1 = gen_new_label(); \
7230 int l2 = gen_new_label(); \
7231 int l3 = gen_new_label(); \
7232 int l4 = gen_new_label(); \
7233 \
7234 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7235 cpu_gpr[rB(ctx->opcode)], l1); \
7236 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7237 tcg_gen_br(l2); \
7238 gen_set_label(l1); \
7239 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7240 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7241 gen_set_label(l2); \
7242 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7243 cpu_gprh[rB(ctx->opcode)], l3); \
7244 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7245 ~(CRF_CH | CRF_CH_AND_CL)); \
7246 tcg_gen_br(l4); \
7247 gen_set_label(l3); \
7248 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7249 CRF_CH | CRF_CH_OR_CL); \
7250 gen_set_label(l4); \
7251 }
7252 #endif
7253 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7254 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7255 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7256 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7257 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7258
7259 /* SPE misc */
7260 static inline void gen_brinc(DisasContext *ctx)
7261 {
7262 /* Note: brinc is usable even if SPE is disabled */
7263 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7264 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7265 }
7266 static inline void gen_evmergelo(DisasContext *ctx)
7267 {
7268 if (unlikely(!ctx->spe_enabled)) {
7269 gen_exception(ctx, POWERPC_EXCP_SPEU);
7270 return;
7271 }
7272 #if defined(TARGET_PPC64)
7273 TCGv t0 = tcg_temp_new();
7274 TCGv t1 = tcg_temp_new();
7275 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7276 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7277 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7278 tcg_temp_free(t0);
7279 tcg_temp_free(t1);
7280 #else
7281 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7282 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7283 #endif
7284 }
7285 static inline void gen_evmergehilo(DisasContext *ctx)
7286 {
7287 if (unlikely(!ctx->spe_enabled)) {
7288 gen_exception(ctx, POWERPC_EXCP_SPEU);
7289 return;
7290 }
7291 #if defined(TARGET_PPC64)
7292 TCGv t0 = tcg_temp_new();
7293 TCGv t1 = tcg_temp_new();
7294 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7295 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7296 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7297 tcg_temp_free(t0);
7298 tcg_temp_free(t1);
7299 #else
7300 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7301 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7302 #endif
7303 }
7304 static inline void gen_evmergelohi(DisasContext *ctx)
7305 {
7306 if (unlikely(!ctx->spe_enabled)) {
7307 gen_exception(ctx, POWERPC_EXCP_SPEU);
7308 return;
7309 }
7310 #if defined(TARGET_PPC64)
7311 TCGv t0 = tcg_temp_new();
7312 TCGv t1 = tcg_temp_new();
7313 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7314 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7315 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7316 tcg_temp_free(t0);
7317 tcg_temp_free(t1);
7318 #else
7319 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7320 TCGv_i32 tmp = tcg_temp_new_i32();
7321 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7322 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7323 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7324 tcg_temp_free_i32(tmp);
7325 } else {
7326 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7327 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7328 }
7329 #endif
7330 }
7331 static inline void gen_evsplati(DisasContext *ctx)
7332 {
7333 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7334
7335 #if defined(TARGET_PPC64)
7336 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7337 #else
7338 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7339 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7340 #endif
7341 }
7342 static inline void gen_evsplatfi(DisasContext *ctx)
7343 {
7344 uint64_t imm = rA(ctx->opcode) << 27;
7345
7346 #if defined(TARGET_PPC64)
7347 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7348 #else
7349 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7350 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7351 #endif
7352 }
7353
7354 static inline void gen_evsel(DisasContext *ctx)
7355 {
7356 int l1 = gen_new_label();
7357 int l2 = gen_new_label();
7358 int l3 = gen_new_label();
7359 int l4 = gen_new_label();
7360 TCGv_i32 t0 = tcg_temp_local_new_i32();
7361 #if defined(TARGET_PPC64)
7362 TCGv t1 = tcg_temp_local_new();
7363 TCGv t2 = tcg_temp_local_new();
7364 #endif
7365 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7366 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7367 #if defined(TARGET_PPC64)
7368 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7369 #else
7370 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7371 #endif
7372 tcg_gen_br(l2);
7373 gen_set_label(l1);
7374 #if defined(TARGET_PPC64)
7375 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7376 #else
7377 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7378 #endif
7379 gen_set_label(l2);
7380 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7381 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7382 #if defined(TARGET_PPC64)
7383 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7384 #else
7385 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7386 #endif
7387 tcg_gen_br(l4);
7388 gen_set_label(l3);
7389 #if defined(TARGET_PPC64)
7390 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7391 #else
7392 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7393 #endif
7394 gen_set_label(l4);
7395 tcg_temp_free_i32(t0);
7396 #if defined(TARGET_PPC64)
7397 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7398 tcg_temp_free(t1);
7399 tcg_temp_free(t2);
7400 #endif
7401 }
7402
7403 static void gen_evsel0(DisasContext *ctx)
7404 {
7405 gen_evsel(ctx);
7406 }
7407
7408 static void gen_evsel1(DisasContext *ctx)
7409 {
7410 gen_evsel(ctx);
7411 }
7412
7413 static void gen_evsel2(DisasContext *ctx)
7414 {
7415 gen_evsel(ctx);
7416 }
7417
7418 static void gen_evsel3(DisasContext *ctx)
7419 {
7420 gen_evsel(ctx);
7421 }
7422
7423 /* Multiply */
7424
7425 static inline void gen_evmwumi(DisasContext *ctx)
7426 {
7427 TCGv_i64 t0, t1;
7428
7429 if (unlikely(!ctx->spe_enabled)) {
7430 gen_exception(ctx, POWERPC_EXCP_SPEU);
7431 return;
7432 }
7433
7434 t0 = tcg_temp_new_i64();
7435 t1 = tcg_temp_new_i64();
7436
7437 /* t0 := rA; t1 := rB */
7438 #if defined(TARGET_PPC64)
7439 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7440 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7441 #else
7442 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7443 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7444 #endif
7445
7446 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7447
7448 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7449
7450 tcg_temp_free_i64(t0);
7451 tcg_temp_free_i64(t1);
7452 }
7453
7454 static inline void gen_evmwumia(DisasContext *ctx)
7455 {
7456 TCGv_i64 tmp;
7457
7458 if (unlikely(!ctx->spe_enabled)) {
7459 gen_exception(ctx, POWERPC_EXCP_SPEU);
7460 return;
7461 }
7462
7463 gen_evmwumi(ctx); /* rD := rA * rB */
7464
7465 tmp = tcg_temp_new_i64();
7466
7467 /* acc := rD */
7468 gen_load_gpr64(tmp, rD(ctx->opcode));
7469 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7470 tcg_temp_free_i64(tmp);
7471 }
7472
7473 static inline void gen_evmwumiaa(DisasContext *ctx)
7474 {
7475 TCGv_i64 acc;
7476 TCGv_i64 tmp;
7477
7478 if (unlikely(!ctx->spe_enabled)) {
7479 gen_exception(ctx, POWERPC_EXCP_SPEU);
7480 return;
7481 }
7482
7483 gen_evmwumi(ctx); /* rD := rA * rB */
7484
7485 acc = tcg_temp_new_i64();
7486 tmp = tcg_temp_new_i64();
7487
7488 /* tmp := rD */
7489 gen_load_gpr64(tmp, rD(ctx->opcode));
7490
7491 /* Load acc */
7492 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7493
7494 /* acc := tmp + acc */
7495 tcg_gen_add_i64(acc, acc, tmp);
7496
7497 /* Store acc */
7498 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7499
7500 /* rD := acc */
7501 gen_store_gpr64(rD(ctx->opcode), acc);
7502
7503 tcg_temp_free_i64(acc);
7504 tcg_temp_free_i64(tmp);
7505 }
7506
7507 static inline void gen_evmwsmi(DisasContext *ctx)
7508 {
7509 TCGv_i64 t0, t1;
7510
7511 if (unlikely(!ctx->spe_enabled)) {
7512 gen_exception(ctx, POWERPC_EXCP_SPEU);
7513 return;
7514 }
7515
7516 t0 = tcg_temp_new_i64();
7517 t1 = tcg_temp_new_i64();
7518
7519 /* t0 := rA; t1 := rB */
7520 #if defined(TARGET_PPC64)
7521 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7522 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7523 #else
7524 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7525 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7526 #endif
7527
7528 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7529
7530 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7531
7532 tcg_temp_free_i64(t0);
7533 tcg_temp_free_i64(t1);
7534 }
7535
7536 static inline void gen_evmwsmia(DisasContext *ctx)
7537 {
7538 TCGv_i64 tmp;
7539
7540 gen_evmwsmi(ctx); /* rD := rA * rB */
7541
7542 tmp = tcg_temp_new_i64();
7543
7544 /* acc := rD */
7545 gen_load_gpr64(tmp, rD(ctx->opcode));
7546 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7547
7548 tcg_temp_free_i64(tmp);
7549 }
7550
7551 static inline void gen_evmwsmiaa(DisasContext *ctx)
7552 {
7553 TCGv_i64 acc = tcg_temp_new_i64();
7554 TCGv_i64 tmp = tcg_temp_new_i64();
7555
7556 gen_evmwsmi(ctx); /* rD := rA * rB */
7557
7558 acc = tcg_temp_new_i64();
7559 tmp = tcg_temp_new_i64();
7560
7561 /* tmp := rD */
7562 gen_load_gpr64(tmp, rD(ctx->opcode));
7563
7564 /* Load acc */
7565 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7566
7567 /* acc := tmp + acc */
7568 tcg_gen_add_i64(acc, acc, tmp);
7569
7570 /* Store acc */
7571 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7572
7573 /* rD := acc */
7574 gen_store_gpr64(rD(ctx->opcode), acc);
7575
7576 tcg_temp_free_i64(acc);
7577 tcg_temp_free_i64(tmp);
7578 }
7579
7580 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7581 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7582 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7583 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7584 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7585 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7586 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7587 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7588 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7589 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7590 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7591 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7592 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7593 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7594 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7595 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7596 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7597 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7598 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7599 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7600 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7601 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7602 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7603 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7604 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7605 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7606 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7607 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7608 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7609
7610 /* SPE load and stores */
7611 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7612 {
7613 target_ulong uimm = rB(ctx->opcode);
7614
7615 if (rA(ctx->opcode) == 0) {
7616 tcg_gen_movi_tl(EA, uimm << sh);
7617 } else {
7618 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7619 if (NARROW_MODE(ctx)) {
7620 tcg_gen_ext32u_tl(EA, EA);
7621 }
7622 }
7623 }
7624
7625 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7626 {
7627 #if defined(TARGET_PPC64)
7628 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7629 #else
7630 TCGv_i64 t0 = tcg_temp_new_i64();
7631 gen_qemu_ld64(ctx, t0, addr);
7632 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7633 tcg_gen_shri_i64(t0, t0, 32);
7634 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7635 tcg_temp_free_i64(t0);
7636 #endif
7637 }
7638
7639 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7640 {
7641 #if defined(TARGET_PPC64)
7642 TCGv t0 = tcg_temp_new();
7643 gen_qemu_ld32u(ctx, t0, addr);
7644 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7645 gen_addr_add(ctx, addr, addr, 4);
7646 gen_qemu_ld32u(ctx, t0, addr);
7647 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7648 tcg_temp_free(t0);
7649 #else
7650 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7651 gen_addr_add(ctx, addr, addr, 4);
7652 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7653 #endif
7654 }
7655
7656 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7657 {
7658 TCGv t0 = tcg_temp_new();
7659 #if defined(TARGET_PPC64)
7660 gen_qemu_ld16u(ctx, t0, addr);
7661 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7662 gen_addr_add(ctx, addr, addr, 2);
7663 gen_qemu_ld16u(ctx, t0, addr);
7664 tcg_gen_shli_tl(t0, t0, 32);
7665 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7666 gen_addr_add(ctx, addr, addr, 2);
7667 gen_qemu_ld16u(ctx, t0, addr);
7668 tcg_gen_shli_tl(t0, t0, 16);
7669 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7670 gen_addr_add(ctx, addr, addr, 2);
7671 gen_qemu_ld16u(ctx, t0, addr);
7672 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7673 #else
7674 gen_qemu_ld16u(ctx, t0, addr);
7675 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7676 gen_addr_add(ctx, addr, addr, 2);
7677 gen_qemu_ld16u(ctx, t0, addr);
7678 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7679 gen_addr_add(ctx, addr, addr, 2);
7680 gen_qemu_ld16u(ctx, t0, addr);
7681 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7682 gen_addr_add(ctx, addr, addr, 2);
7683 gen_qemu_ld16u(ctx, t0, addr);
7684 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7685 #endif
7686 tcg_temp_free(t0);
7687 }
7688
7689 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7690 {
7691 TCGv t0 = tcg_temp_new();
7692 gen_qemu_ld16u(ctx, t0, addr);
7693 #if defined(TARGET_PPC64)
7694 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7695 tcg_gen_shli_tl(t0, t0, 16);
7696 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7697 #else
7698 tcg_gen_shli_tl(t0, t0, 16);
7699 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7700 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7701 #endif
7702 tcg_temp_free(t0);
7703 }
7704
7705 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7706 {
7707 TCGv t0 = tcg_temp_new();
7708 gen_qemu_ld16u(ctx, t0, addr);
7709 #if defined(TARGET_PPC64)
7710 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7711 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7712 #else
7713 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7714 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7715 #endif
7716 tcg_temp_free(t0);
7717 }
7718
7719 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7720 {
7721 TCGv t0 = tcg_temp_new();
7722 gen_qemu_ld16s(ctx, t0, addr);
7723 #if defined(TARGET_PPC64)
7724 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7725 tcg_gen_ext32u_tl(t0, t0);
7726 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7727 #else
7728 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7729 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7730 #endif
7731 tcg_temp_free(t0);
7732 }
7733
7734 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7735 {
7736 TCGv t0 = tcg_temp_new();
7737 #if defined(TARGET_PPC64)
7738 gen_qemu_ld16u(ctx, t0, addr);
7739 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7740 gen_addr_add(ctx, addr, addr, 2);
7741 gen_qemu_ld16u(ctx, t0, addr);
7742 tcg_gen_shli_tl(t0, t0, 16);
7743 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7744 #else
7745 gen_qemu_ld16u(ctx, t0, addr);
7746 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7747 gen_addr_add(ctx, addr, addr, 2);
7748 gen_qemu_ld16u(ctx, t0, addr);
7749 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7750 #endif
7751 tcg_temp_free(t0);
7752 }
7753
7754 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7755 {
7756 #if defined(TARGET_PPC64)
7757 TCGv t0 = tcg_temp_new();
7758 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7759 gen_addr_add(ctx, addr, addr, 2);
7760 gen_qemu_ld16u(ctx, t0, addr);
7761 tcg_gen_shli_tl(t0, t0, 32);
7762 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7763 tcg_temp_free(t0);
7764 #else
7765 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7766 gen_addr_add(ctx, addr, addr, 2);
7767 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7768 #endif
7769 }
7770
7771 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7772 {
7773 #if defined(TARGET_PPC64)
7774 TCGv t0 = tcg_temp_new();
7775 gen_qemu_ld16s(ctx, t0, addr);
7776 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7777 gen_addr_add(ctx, addr, addr, 2);
7778 gen_qemu_ld16s(ctx, t0, addr);
7779 tcg_gen_shli_tl(t0, t0, 32);
7780 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7781 tcg_temp_free(t0);
7782 #else
7783 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7784 gen_addr_add(ctx, addr, addr, 2);
7785 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7786 #endif
7787 }
7788
7789 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7790 {
7791 TCGv t0 = tcg_temp_new();
7792 gen_qemu_ld32u(ctx, t0, addr);
7793 #if defined(TARGET_PPC64)
7794 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7795 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7796 #else
7797 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7798 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7799 #endif
7800 tcg_temp_free(t0);
7801 }
7802
7803 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7804 {
7805 TCGv t0 = tcg_temp_new();
7806 #if defined(TARGET_PPC64)
7807 gen_qemu_ld16u(ctx, t0, addr);
7808 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7809 tcg_gen_shli_tl(t0, t0, 32);
7810 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7811 gen_addr_add(ctx, addr, addr, 2);
7812 gen_qemu_ld16u(ctx, t0, addr);
7813 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7814 tcg_gen_shli_tl(t0, t0, 16);
7815 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7816 #else
7817 gen_qemu_ld16u(ctx, t0, addr);
7818 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7819 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7820 gen_addr_add(ctx, addr, addr, 2);
7821 gen_qemu_ld16u(ctx, t0, addr);
7822 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7823 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7824 #endif
7825 tcg_temp_free(t0);
7826 }
7827
7828 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7829 {
7830 #if defined(TARGET_PPC64)
7831 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7832 #else
7833 TCGv_i64 t0 = tcg_temp_new_i64();
7834 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7835 gen_qemu_st64(ctx, t0, addr);
7836 tcg_temp_free_i64(t0);
7837 #endif
7838 }
7839
7840 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7841 {
7842 #if defined(TARGET_PPC64)
7843 TCGv t0 = tcg_temp_new();
7844 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7845 gen_qemu_st32(ctx, t0, addr);
7846 tcg_temp_free(t0);
7847 #else
7848 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7849 #endif
7850 gen_addr_add(ctx, addr, addr, 4);
7851 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7852 }
7853
7854 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7855 {
7856 TCGv t0 = tcg_temp_new();
7857 #if defined(TARGET_PPC64)
7858 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7859 #else
7860 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7861 #endif
7862 gen_qemu_st16(ctx, t0, addr);
7863 gen_addr_add(ctx, addr, addr, 2);
7864 #if defined(TARGET_PPC64)
7865 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7866 gen_qemu_st16(ctx, t0, addr);
7867 #else
7868 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7869 #endif
7870 gen_addr_add(ctx, addr, addr, 2);
7871 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7872 gen_qemu_st16(ctx, t0, addr);
7873 tcg_temp_free(t0);
7874 gen_addr_add(ctx, addr, addr, 2);
7875 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7876 }
7877
7878 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7879 {
7880 TCGv t0 = tcg_temp_new();
7881 #if defined(TARGET_PPC64)
7882 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7883 #else
7884 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7885 #endif
7886 gen_qemu_st16(ctx, t0, addr);
7887 gen_addr_add(ctx, addr, addr, 2);
7888 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7889 gen_qemu_st16(ctx, t0, addr);
7890 tcg_temp_free(t0);
7891 }
7892
7893 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7894 {
7895 #if defined(TARGET_PPC64)
7896 TCGv t0 = tcg_temp_new();
7897 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7898 gen_qemu_st16(ctx, t0, addr);
7899 tcg_temp_free(t0);
7900 #else
7901 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7902 #endif
7903 gen_addr_add(ctx, addr, addr, 2);
7904 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7905 }
7906
7907 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7908 {
7909 #if defined(TARGET_PPC64)
7910 TCGv t0 = tcg_temp_new();
7911 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7912 gen_qemu_st32(ctx, t0, addr);
7913 tcg_temp_free(t0);
7914 #else
7915 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7916 #endif
7917 }
7918
7919 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7920 {
7921 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7922 }
7923
7924 #define GEN_SPEOP_LDST(name, opc2, sh) \
7925 static void glue(gen_, name)(DisasContext *ctx) \
7926 { \
7927 TCGv t0; \
7928 if (unlikely(!ctx->spe_enabled)) { \
7929 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7930 return; \
7931 } \
7932 gen_set_access_type(ctx, ACCESS_INT); \
7933 t0 = tcg_temp_new(); \
7934 if (Rc(ctx->opcode)) { \
7935 gen_addr_spe_imm_index(ctx, t0, sh); \
7936 } else { \
7937 gen_addr_reg_index(ctx, t0); \
7938 } \
7939 gen_op_##name(ctx, t0); \
7940 tcg_temp_free(t0); \
7941 }
7942
7943 GEN_SPEOP_LDST(evldd, 0x00, 3);
7944 GEN_SPEOP_LDST(evldw, 0x01, 3);
7945 GEN_SPEOP_LDST(evldh, 0x02, 3);
7946 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7947 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7948 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7949 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7950 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7951 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7952 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7953 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7954
7955 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7956 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7957 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7958 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7959 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7960 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7961 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7962
7963 /* Multiply and add - TODO */
7964 #if 0
7965 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
7966 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7967 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7968 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7969 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7970 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7971 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7972 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7973 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7974 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7975 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7976 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7977
7978 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7979 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7980 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7981 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7982 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7983 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7984 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7985 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7986 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7987 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7988 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7989 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7990
7991 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7992 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7993 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7994 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7995 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
7996
7997 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7998 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7999 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8000 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8001 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8002 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8003 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8004 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8005 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8006 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8007 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8008 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8009
8010 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8011 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8012 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8013 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8014
8015 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8016 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8017 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8018 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8019 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8020 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8021 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8022 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8023 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8024 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8025 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8026 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8027
8028 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8029 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8030 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8031 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8032 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8033 #endif
8034
8035 /*** SPE floating-point extension ***/
8036 #if defined(TARGET_PPC64)
8037 #define GEN_SPEFPUOP_CONV_32_32(name) \
8038 static inline void gen_##name(DisasContext *ctx) \
8039 { \
8040 TCGv_i32 t0; \
8041 TCGv t1; \
8042 t0 = tcg_temp_new_i32(); \
8043 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8044 gen_helper_##name(t0, cpu_env, t0); \
8045 t1 = tcg_temp_new(); \
8046 tcg_gen_extu_i32_tl(t1, t0); \
8047 tcg_temp_free_i32(t0); \
8048 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8049 0xFFFFFFFF00000000ULL); \
8050 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8051 tcg_temp_free(t1); \
8052 }
8053 #define GEN_SPEFPUOP_CONV_32_64(name) \
8054 static inline void gen_##name(DisasContext *ctx) \
8055 { \
8056 TCGv_i32 t0; \
8057 TCGv t1; \
8058 t0 = tcg_temp_new_i32(); \
8059 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8060 t1 = tcg_temp_new(); \
8061 tcg_gen_extu_i32_tl(t1, t0); \
8062 tcg_temp_free_i32(t0); \
8063 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8064 0xFFFFFFFF00000000ULL); \
8065 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8066 tcg_temp_free(t1); \
8067 }
8068 #define GEN_SPEFPUOP_CONV_64_32(name) \
8069 static inline void gen_##name(DisasContext *ctx) \
8070 { \
8071 TCGv_i32 t0 = tcg_temp_new_i32(); \
8072 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8073 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8074 tcg_temp_free_i32(t0); \
8075 }
8076 #define GEN_SPEFPUOP_CONV_64_64(name) \
8077 static inline void gen_##name(DisasContext *ctx) \
8078 { \
8079 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8080 cpu_gpr[rB(ctx->opcode)]); \
8081 }
8082 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8083 static inline void gen_##name(DisasContext *ctx) \
8084 { \
8085 TCGv_i32 t0, t1; \
8086 TCGv_i64 t2; \
8087 if (unlikely(!ctx->spe_enabled)) { \
8088 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8089 return; \
8090 } \
8091 t0 = tcg_temp_new_i32(); \
8092 t1 = tcg_temp_new_i32(); \
8093 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8094 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8095 gen_helper_##name(t0, cpu_env, t0, t1); \
8096 tcg_temp_free_i32(t1); \
8097 t2 = tcg_temp_new(); \
8098 tcg_gen_extu_i32_tl(t2, t0); \
8099 tcg_temp_free_i32(t0); \
8100 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8101 0xFFFFFFFF00000000ULL); \
8102 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8103 tcg_temp_free(t2); \
8104 }
8105 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8106 static inline void gen_##name(DisasContext *ctx) \
8107 { \
8108 if (unlikely(!ctx->spe_enabled)) { \
8109 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8110 return; \
8111 } \
8112 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8113 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8114 }
8115 #define GEN_SPEFPUOP_COMP_32(name) \
8116 static inline void gen_##name(DisasContext *ctx) \
8117 { \
8118 TCGv_i32 t0, t1; \
8119 if (unlikely(!ctx->spe_enabled)) { \
8120 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8121 return; \
8122 } \
8123 t0 = tcg_temp_new_i32(); \
8124 t1 = tcg_temp_new_i32(); \
8125 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8126 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8127 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8128 tcg_temp_free_i32(t0); \
8129 tcg_temp_free_i32(t1); \
8130 }
8131 #define GEN_SPEFPUOP_COMP_64(name) \
8132 static inline void gen_##name(DisasContext *ctx) \
8133 { \
8134 if (unlikely(!ctx->spe_enabled)) { \
8135 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8136 return; \
8137 } \
8138 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8139 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8140 }
8141 #else
8142 #define GEN_SPEFPUOP_CONV_32_32(name) \
8143 static inline void gen_##name(DisasContext *ctx) \
8144 { \
8145 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8146 cpu_gpr[rB(ctx->opcode)]); \
8147 }
8148 #define GEN_SPEFPUOP_CONV_32_64(name) \
8149 static inline void gen_##name(DisasContext *ctx) \
8150 { \
8151 TCGv_i64 t0 = tcg_temp_new_i64(); \
8152 gen_load_gpr64(t0, rB(ctx->opcode)); \
8153 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8154 tcg_temp_free_i64(t0); \
8155 }
8156 #define GEN_SPEFPUOP_CONV_64_32(name) \
8157 static inline void gen_##name(DisasContext *ctx) \
8158 { \
8159 TCGv_i64 t0 = tcg_temp_new_i64(); \
8160 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8161 gen_store_gpr64(rD(ctx->opcode), t0); \
8162 tcg_temp_free_i64(t0); \
8163 }
8164 #define GEN_SPEFPUOP_CONV_64_64(name) \
8165 static inline void gen_##name(DisasContext *ctx) \
8166 { \
8167 TCGv_i64 t0 = tcg_temp_new_i64(); \
8168 gen_load_gpr64(t0, rB(ctx->opcode)); \
8169 gen_helper_##name(t0, cpu_env, t0); \
8170 gen_store_gpr64(rD(ctx->opcode), t0); \
8171 tcg_temp_free_i64(t0); \
8172 }
8173 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8174 static inline void gen_##name(DisasContext *ctx) \
8175 { \
8176 if (unlikely(!ctx->spe_enabled)) { \
8177 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8178 return; \
8179 } \
8180 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8181 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8182 }
8183 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8184 static inline void gen_##name(DisasContext *ctx) \
8185 { \
8186 TCGv_i64 t0, t1; \
8187 if (unlikely(!ctx->spe_enabled)) { \
8188 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8189 return; \
8190 } \
8191 t0 = tcg_temp_new_i64(); \
8192 t1 = tcg_temp_new_i64(); \
8193 gen_load_gpr64(t0, rA(ctx->opcode)); \
8194 gen_load_gpr64(t1, rB(ctx->opcode)); \
8195 gen_helper_##name(t0, cpu_env, t0, t1); \
8196 gen_store_gpr64(rD(ctx->opcode), t0); \
8197 tcg_temp_free_i64(t0); \
8198 tcg_temp_free_i64(t1); \
8199 }
8200 #define GEN_SPEFPUOP_COMP_32(name) \
8201 static inline void gen_##name(DisasContext *ctx) \
8202 { \
8203 if (unlikely(!ctx->spe_enabled)) { \
8204 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8205 return; \
8206 } \
8207 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8208 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8209 }
8210 #define GEN_SPEFPUOP_COMP_64(name) \
8211 static inline void gen_##name(DisasContext *ctx) \
8212 { \
8213 TCGv_i64 t0, t1; \
8214 if (unlikely(!ctx->spe_enabled)) { \
8215 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8216 return; \
8217 } \
8218 t0 = tcg_temp_new_i64(); \
8219 t1 = tcg_temp_new_i64(); \
8220 gen_load_gpr64(t0, rA(ctx->opcode)); \
8221 gen_load_gpr64(t1, rB(ctx->opcode)); \
8222 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8223 tcg_temp_free_i64(t0); \
8224 tcg_temp_free_i64(t1); \
8225 }
8226 #endif
8227
8228 /* Single precision floating-point vectors operations */
8229 /* Arithmetic */
8230 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8231 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8232 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8233 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8234 static inline void gen_evfsabs(DisasContext *ctx)
8235 {
8236 if (unlikely(!ctx->spe_enabled)) {
8237 gen_exception(ctx, POWERPC_EXCP_SPEU);
8238 return;
8239 }
8240 #if defined(TARGET_PPC64)
8241 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8242 #else
8243 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8244 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8245 #endif
8246 }
8247 static inline void gen_evfsnabs(DisasContext *ctx)
8248 {
8249 if (unlikely(!ctx->spe_enabled)) {
8250 gen_exception(ctx, POWERPC_EXCP_SPEU);
8251 return;
8252 }
8253 #if defined(TARGET_PPC64)
8254 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8255 #else
8256 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8257 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8258 #endif
8259 }
8260 static inline void gen_evfsneg(DisasContext *ctx)
8261 {
8262 if (unlikely(!ctx->spe_enabled)) {
8263 gen_exception(ctx, POWERPC_EXCP_SPEU);
8264 return;
8265 }
8266 #if defined(TARGET_PPC64)
8267 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8268 #else
8269 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8270 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8271 #endif
8272 }
8273
8274 /* Conversion */
8275 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8276 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8277 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8278 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8279 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8280 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8281 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8282 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8283 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8284 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8285
8286 /* Comparison */
8287 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8288 GEN_SPEFPUOP_COMP_64(evfscmplt);
8289 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8290 GEN_SPEFPUOP_COMP_64(evfststgt);
8291 GEN_SPEFPUOP_COMP_64(evfststlt);
8292 GEN_SPEFPUOP_COMP_64(evfststeq);
8293
8294 /* Opcodes definitions */
8295 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8296 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8297 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8298 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8299 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8300 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8301 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8302 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8303 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8304 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8305 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8306 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8307 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8308 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8309
8310 /* Single precision floating-point operations */
8311 /* Arithmetic */
8312 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8313 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8314 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8315 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8316 static inline void gen_efsabs(DisasContext *ctx)
8317 {
8318 if (unlikely(!ctx->spe_enabled)) {
8319 gen_exception(ctx, POWERPC_EXCP_SPEU);
8320 return;
8321 }
8322 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8323 }
8324 static inline void gen_efsnabs(DisasContext *ctx)
8325 {
8326 if (unlikely(!ctx->spe_enabled)) {
8327 gen_exception(ctx, POWERPC_EXCP_SPEU);
8328 return;
8329 }
8330 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8331 }
8332 static inline void gen_efsneg(DisasContext *ctx)
8333 {
8334 if (unlikely(!ctx->spe_enabled)) {
8335 gen_exception(ctx, POWERPC_EXCP_SPEU);
8336 return;
8337 }
8338 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8339 }
8340
8341 /* Conversion */
8342 GEN_SPEFPUOP_CONV_32_32(efscfui);
8343 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8344 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8345 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8346 GEN_SPEFPUOP_CONV_32_32(efsctui);
8347 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8348 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8349 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8350 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8351 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8352 GEN_SPEFPUOP_CONV_32_64(efscfd);
8353
8354 /* Comparison */
8355 GEN_SPEFPUOP_COMP_32(efscmpgt);
8356 GEN_SPEFPUOP_COMP_32(efscmplt);
8357 GEN_SPEFPUOP_COMP_32(efscmpeq);
8358 GEN_SPEFPUOP_COMP_32(efststgt);
8359 GEN_SPEFPUOP_COMP_32(efststlt);
8360 GEN_SPEFPUOP_COMP_32(efststeq);
8361
8362 /* Opcodes definitions */
8363 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8364 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8365 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8366 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8367 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8368 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8369 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8370 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8371 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8372 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8373 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8374 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8375 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8376 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8377
8378 /* Double precision floating-point operations */
8379 /* Arithmetic */
8380 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8381 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8382 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8383 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8384 static inline void gen_efdabs(DisasContext *ctx)
8385 {
8386 if (unlikely(!ctx->spe_enabled)) {
8387 gen_exception(ctx, POWERPC_EXCP_SPEU);
8388 return;
8389 }
8390 #if defined(TARGET_PPC64)
8391 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8392 #else
8393 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8394 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8395 #endif
8396 }
8397 static inline void gen_efdnabs(DisasContext *ctx)
8398 {
8399 if (unlikely(!ctx->spe_enabled)) {
8400 gen_exception(ctx, POWERPC_EXCP_SPEU);
8401 return;
8402 }
8403 #if defined(TARGET_PPC64)
8404 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8405 #else
8406 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8407 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8408 #endif
8409 }
8410 static inline void gen_efdneg(DisasContext *ctx)
8411 {
8412 if (unlikely(!ctx->spe_enabled)) {
8413 gen_exception(ctx, POWERPC_EXCP_SPEU);
8414 return;
8415 }
8416 #if defined(TARGET_PPC64)
8417 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8418 #else
8419 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8420 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8421 #endif
8422 }
8423
8424 /* Conversion */
8425 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8426 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8427 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8428 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8429 GEN_SPEFPUOP_CONV_32_64(efdctui);
8430 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8431 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8432 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8433 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8434 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8435 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8436 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8437 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8438 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8439 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8440
8441 /* Comparison */
8442 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8443 GEN_SPEFPUOP_COMP_64(efdcmplt);
8444 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8445 GEN_SPEFPUOP_COMP_64(efdtstgt);
8446 GEN_SPEFPUOP_COMP_64(efdtstlt);
8447 GEN_SPEFPUOP_COMP_64(efdtsteq);
8448
8449 /* Opcodes definitions */
8450 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8451 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8452 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8453 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8454 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8455 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8456 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8457 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8458 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8459 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8460 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8461 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8462 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8463 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8464 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8465 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8466
8467 static opcode_t opcodes[] = {
8468 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8469 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8470 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8471 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8472 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8473 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
8474 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8475 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8476 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8477 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8478 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8479 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8480 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8481 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8482 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8483 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8484 #if defined(TARGET_PPC64)
8485 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8486 #endif
8487 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8488 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8489 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8490 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8491 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8492 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8493 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8494 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8495 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8496 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8497 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8498 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8499 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8500 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8501 #if defined(TARGET_PPC64)
8502 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8503 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8504 #endif
8505 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8506 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8507 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8508 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8509 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8510 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8511 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8512 #if defined(TARGET_PPC64)
8513 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8514 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8515 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8516 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8517 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8518 #endif
8519 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8520 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8521 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8522 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8523 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8524 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
8525 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8526 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
8527 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
8528 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8529 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8530 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8531 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8532 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8533 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8534 #if defined(TARGET_PPC64)
8535 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8536 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8537 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8538 #endif
8539 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8540 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8541 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8542 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8543 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8544 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8545 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8546 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8547 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8548 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8549 #if defined(TARGET_PPC64)
8550 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8551 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8552 #endif
8553 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8554 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8555 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8556 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8557 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8558 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8559 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8560 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8561 #if defined(TARGET_PPC64)
8562 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8563 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8564 #endif
8565 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8566 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8567 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8568 #if defined(TARGET_PPC64)
8569 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8570 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8571 #endif
8572 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8573 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8574 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8575 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8576 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8577 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8578 #if defined(TARGET_PPC64)
8579 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8580 #endif
8581 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8582 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8583 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8584 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8585 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8586 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8587 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8588 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
8589 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8590 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8591 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8592 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8593 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8594 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8595 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8596 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8597 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8598 #if defined(TARGET_PPC64)
8599 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8600 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8601 PPC_SEGMENT_64B),
8602 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8603 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8604 PPC_SEGMENT_64B),
8605 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8606 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8607 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8608 #endif
8609 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8610 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8611 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8612 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8613 #if defined(TARGET_PPC64)
8614 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8615 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8616 #endif
8617 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8618 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8619 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8620 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8621 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8622 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8623 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8624 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8625 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8626 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8627 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8628 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8629 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8630 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8631 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8632 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8633 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8634 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8635 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8636 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8637 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8638 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8639 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8640 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8641 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8642 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8643 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8644 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8645 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8646 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8647 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8648 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8649 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8650 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8651 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8652 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8653 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8654 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8655 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8656 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8657 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8658 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8659 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8660 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8661 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8662 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8663 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8664 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8665 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8666 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8667 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8668 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8669 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8670 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8671 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8672 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8673 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8674 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8675 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8676 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8677 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8678 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8679 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8680 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8681 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8682 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8683 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8684 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8685 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8686 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8687 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8688 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8689 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8690 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8691 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8692 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8693 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8694 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8695 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8696 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8697 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8698 PPC_NONE, PPC2_BOOKE206),
8699 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8700 PPC_NONE, PPC2_BOOKE206),
8701 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8702 PPC_NONE, PPC2_BOOKE206),
8703 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8704 PPC_NONE, PPC2_BOOKE206),
8705 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8706 PPC_NONE, PPC2_BOOKE206),
8707 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8708 PPC_NONE, PPC2_PRCNTL),
8709 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8710 PPC_NONE, PPC2_PRCNTL),
8711 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8712 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8713 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8714 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8715 PPC_BOOKE, PPC2_BOOKE206),
8716 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8717 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8718 PPC_BOOKE, PPC2_BOOKE206),
8719 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8720 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8721 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8722 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8723 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8724 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8725 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8726 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8727 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8728 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8729
8730 #undef GEN_INT_ARITH_ADD
8731 #undef GEN_INT_ARITH_ADD_CONST
8732 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8733 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8734 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8735 add_ca, compute_ca, compute_ov) \
8736 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8737 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8738 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8739 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8740 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8741 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8742 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8743 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8744 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8745 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8746 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8747
8748 #undef GEN_INT_ARITH_DIVW
8749 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8750 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8751 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8752 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8753 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8754 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8755
8756 #if defined(TARGET_PPC64)
8757 #undef GEN_INT_ARITH_DIVD
8758 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8759 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8760 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8761 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8762 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8763 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8764
8765 #undef GEN_INT_ARITH_MUL_HELPER
8766 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8767 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8768 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8769 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8770 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8771 #endif
8772
8773 #undef GEN_INT_ARITH_SUBF
8774 #undef GEN_INT_ARITH_SUBF_CONST
8775 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8776 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8777 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8778 add_ca, compute_ca, compute_ov) \
8779 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8780 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8781 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8782 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8783 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8784 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8785 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8786 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8787 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8788 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8789 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8790
8791 #undef GEN_LOGICAL1
8792 #undef GEN_LOGICAL2
8793 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8794 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8795 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8796 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8797 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8798 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8799 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8800 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8801 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8802 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8803 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8804 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8805 #if defined(TARGET_PPC64)
8806 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8807 #endif
8808
8809 #if defined(TARGET_PPC64)
8810 #undef GEN_PPC64_R2
8811 #undef GEN_PPC64_R4
8812 #define GEN_PPC64_R2(name, opc1, opc2) \
8813 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8814 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8815 PPC_64B)
8816 #define GEN_PPC64_R4(name, opc1, opc2) \
8817 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8818 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8819 PPC_64B), \
8820 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8821 PPC_64B), \
8822 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8823 PPC_64B)
8824 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8825 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8826 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8827 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8828 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8829 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8830 #endif
8831
8832 #undef _GEN_FLOAT_ACB
8833 #undef GEN_FLOAT_ACB
8834 #undef _GEN_FLOAT_AB
8835 #undef GEN_FLOAT_AB
8836 #undef _GEN_FLOAT_AC
8837 #undef GEN_FLOAT_AC
8838 #undef GEN_FLOAT_B
8839 #undef GEN_FLOAT_BS
8840 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8841 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8842 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8843 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8844 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8845 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8846 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8847 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8848 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8849 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8850 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8851 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8852 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8853 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8854 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8855 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8856 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8857 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8858 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8859
8860 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8861 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8862 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8863 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8864 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8865 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8866 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8867 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8868 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8869 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8870 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8871 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8872 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8873 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8874 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8875 #if defined(TARGET_PPC64)
8876 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8877 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8878 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8879 #endif
8880 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8881 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8882 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8883 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8884
8885 #undef GEN_LD
8886 #undef GEN_LDU
8887 #undef GEN_LDUX
8888 #undef GEN_LDX_E
8889 #undef GEN_LDS
8890 #define GEN_LD(name, ldop, opc, type) \
8891 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8892 #define GEN_LDU(name, ldop, opc, type) \
8893 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8894 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8895 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8896 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8897 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8898 #define GEN_LDS(name, ldop, op, type) \
8899 GEN_LD(name, ldop, op | 0x20, type) \
8900 GEN_LDU(name, ldop, op | 0x21, type) \
8901 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8902 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8903
8904 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8905 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8906 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8907 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8908 #if defined(TARGET_PPC64)
8909 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8910 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8911 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8912 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8913 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
8914 #endif
8915 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8916 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8917
8918 #undef GEN_ST
8919 #undef GEN_STU
8920 #undef GEN_STUX
8921 #undef GEN_STX_E
8922 #undef GEN_STS
8923 #define GEN_ST(name, stop, opc, type) \
8924 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8925 #define GEN_STU(name, stop, opc, type) \
8926 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8927 #define GEN_STUX(name, stop, opc2, opc3, type) \
8928 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8929 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
8930 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8931 #define GEN_STS(name, stop, op, type) \
8932 GEN_ST(name, stop, op | 0x20, type) \
8933 GEN_STU(name, stop, op | 0x21, type) \
8934 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8935 GEN_STX(name, stop, 0x17, op | 0x00, type)
8936
8937 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8938 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8939 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8940 #if defined(TARGET_PPC64)
8941 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8942 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8943 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
8944 #endif
8945 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8946 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8947
8948 #undef GEN_LDF
8949 #undef GEN_LDUF
8950 #undef GEN_LDUXF
8951 #undef GEN_LDXF
8952 #undef GEN_LDFS
8953 #define GEN_LDF(name, ldop, opc, type) \
8954 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8955 #define GEN_LDUF(name, ldop, opc, type) \
8956 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8957 #define GEN_LDUXF(name, ldop, opc, type) \
8958 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8959 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
8960 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8961 #define GEN_LDFS(name, ldop, op, type) \
8962 GEN_LDF(name, ldop, op | 0x20, type) \
8963 GEN_LDUF(name, ldop, op | 0x21, type) \
8964 GEN_LDUXF(name, ldop, op | 0x01, type) \
8965 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
8966
8967 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
8968 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
8969
8970 #undef GEN_STF
8971 #undef GEN_STUF
8972 #undef GEN_STUXF
8973 #undef GEN_STXF
8974 #undef GEN_STFS
8975 #define GEN_STF(name, stop, opc, type) \
8976 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8977 #define GEN_STUF(name, stop, opc, type) \
8978 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8979 #define GEN_STUXF(name, stop, opc, type) \
8980 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8981 #define GEN_STXF(name, stop, opc2, opc3, type) \
8982 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8983 #define GEN_STFS(name, stop, op, type) \
8984 GEN_STF(name, stop, op | 0x20, type) \
8985 GEN_STUF(name, stop, op | 0x21, type) \
8986 GEN_STUXF(name, stop, op | 0x01, type) \
8987 GEN_STXF(name, stop, 0x17, op | 0x00, type)
8988
8989 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
8990 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
8991 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
8992
8993 #undef GEN_CRLOGIC
8994 #define GEN_CRLOGIC(name, tcg_op, opc) \
8995 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8996 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8997 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8998 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8999 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
9000 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
9001 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
9002 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
9003 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
9004
9005 #undef GEN_MAC_HANDLER
9006 #define GEN_MAC_HANDLER(name, opc2, opc3) \
9007 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
9008 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
9009 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
9010 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
9011 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
9012 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
9013 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
9014 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
9015 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
9016 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
9017 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
9018 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
9019 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
9020 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
9021 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
9022 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
9023 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
9024 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
9025 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
9026 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
9027 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
9028 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
9029 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
9030 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
9031 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
9032 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
9033 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
9034 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
9035 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
9036 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
9037 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
9038 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
9039 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
9040 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
9041 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
9042 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
9043 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
9044 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9045 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9046 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9047 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9048 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9049 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9050
9051 #undef GEN_VR_LDX
9052 #undef GEN_VR_STX
9053 #undef GEN_VR_LVE
9054 #undef GEN_VR_STVE
9055 #define GEN_VR_LDX(name, opc2, opc3) \
9056 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9057 #define GEN_VR_STX(name, opc2, opc3) \
9058 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9059 #define GEN_VR_LVE(name, opc2, opc3) \
9060 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9061 #define GEN_VR_STVE(name, opc2, opc3) \
9062 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9063 GEN_VR_LDX(lvx, 0x07, 0x03),
9064 GEN_VR_LDX(lvxl, 0x07, 0x0B),
9065 GEN_VR_LVE(bx, 0x07, 0x00),
9066 GEN_VR_LVE(hx, 0x07, 0x01),
9067 GEN_VR_LVE(wx, 0x07, 0x02),
9068 GEN_VR_STX(svx, 0x07, 0x07),
9069 GEN_VR_STX(svxl, 0x07, 0x0F),
9070 GEN_VR_STVE(bx, 0x07, 0x04),
9071 GEN_VR_STVE(hx, 0x07, 0x05),
9072 GEN_VR_STVE(wx, 0x07, 0x06),
9073
9074 #undef GEN_VX_LOGICAL
9075 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9076 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9077 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9078 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9079 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9080 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9081 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9082
9083 #undef GEN_VXFORM
9084 #define GEN_VXFORM(name, opc2, opc3) \
9085 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9086 GEN_VXFORM(vaddubm, 0, 0),
9087 GEN_VXFORM(vadduhm, 0, 1),
9088 GEN_VXFORM(vadduwm, 0, 2),
9089 GEN_VXFORM(vsububm, 0, 16),
9090 GEN_VXFORM(vsubuhm, 0, 17),
9091 GEN_VXFORM(vsubuwm, 0, 18),
9092 GEN_VXFORM(vmaxub, 1, 0),
9093 GEN_VXFORM(vmaxuh, 1, 1),
9094 GEN_VXFORM(vmaxuw, 1, 2),
9095 GEN_VXFORM(vmaxsb, 1, 4),
9096 GEN_VXFORM(vmaxsh, 1, 5),
9097 GEN_VXFORM(vmaxsw, 1, 6),
9098 GEN_VXFORM(vminub, 1, 8),
9099 GEN_VXFORM(vminuh, 1, 9),
9100 GEN_VXFORM(vminuw, 1, 10),
9101 GEN_VXFORM(vminsb, 1, 12),
9102 GEN_VXFORM(vminsh, 1, 13),
9103 GEN_VXFORM(vminsw, 1, 14),
9104 GEN_VXFORM(vavgub, 1, 16),
9105 GEN_VXFORM(vavguh, 1, 17),
9106 GEN_VXFORM(vavguw, 1, 18),
9107 GEN_VXFORM(vavgsb, 1, 20),
9108 GEN_VXFORM(vavgsh, 1, 21),
9109 GEN_VXFORM(vavgsw, 1, 22),
9110 GEN_VXFORM(vmrghb, 6, 0),
9111 GEN_VXFORM(vmrghh, 6, 1),
9112 GEN_VXFORM(vmrghw, 6, 2),
9113 GEN_VXFORM(vmrglb, 6, 4),
9114 GEN_VXFORM(vmrglh, 6, 5),
9115 GEN_VXFORM(vmrglw, 6, 6),
9116 GEN_VXFORM(vmuloub, 4, 0),
9117 GEN_VXFORM(vmulouh, 4, 1),
9118 GEN_VXFORM(vmulosb, 4, 4),
9119 GEN_VXFORM(vmulosh, 4, 5),
9120 GEN_VXFORM(vmuleub, 4, 8),
9121 GEN_VXFORM(vmuleuh, 4, 9),
9122 GEN_VXFORM(vmulesb, 4, 12),
9123 GEN_VXFORM(vmulesh, 4, 13),
9124 GEN_VXFORM(vslb, 2, 4),
9125 GEN_VXFORM(vslh, 2, 5),
9126 GEN_VXFORM(vslw, 2, 6),
9127 GEN_VXFORM(vsrb, 2, 8),
9128 GEN_VXFORM(vsrh, 2, 9),
9129 GEN_VXFORM(vsrw, 2, 10),
9130 GEN_VXFORM(vsrab, 2, 12),
9131 GEN_VXFORM(vsrah, 2, 13),
9132 GEN_VXFORM(vsraw, 2, 14),
9133 GEN_VXFORM(vslo, 6, 16),
9134 GEN_VXFORM(vsro, 6, 17),
9135 GEN_VXFORM(vaddcuw, 0, 6),
9136 GEN_VXFORM(vsubcuw, 0, 22),
9137 GEN_VXFORM(vaddubs, 0, 8),
9138 GEN_VXFORM(vadduhs, 0, 9),
9139 GEN_VXFORM(vadduws, 0, 10),
9140 GEN_VXFORM(vaddsbs, 0, 12),
9141 GEN_VXFORM(vaddshs, 0, 13),
9142 GEN_VXFORM(vaddsws, 0, 14),
9143 GEN_VXFORM(vsububs, 0, 24),
9144 GEN_VXFORM(vsubuhs, 0, 25),
9145 GEN_VXFORM(vsubuws, 0, 26),
9146 GEN_VXFORM(vsubsbs, 0, 28),
9147 GEN_VXFORM(vsubshs, 0, 29),
9148 GEN_VXFORM(vsubsws, 0, 30),
9149 GEN_VXFORM(vrlb, 2, 0),
9150 GEN_VXFORM(vrlh, 2, 1),
9151 GEN_VXFORM(vrlw, 2, 2),
9152 GEN_VXFORM(vsl, 2, 7),
9153 GEN_VXFORM(vsr, 2, 11),
9154 GEN_VXFORM(vpkuhum, 7, 0),
9155 GEN_VXFORM(vpkuwum, 7, 1),
9156 GEN_VXFORM(vpkuhus, 7, 2),
9157 GEN_VXFORM(vpkuwus, 7, 3),
9158 GEN_VXFORM(vpkshus, 7, 4),
9159 GEN_VXFORM(vpkswus, 7, 5),
9160 GEN_VXFORM(vpkshss, 7, 6),
9161 GEN_VXFORM(vpkswss, 7, 7),
9162 GEN_VXFORM(vpkpx, 7, 12),
9163 GEN_VXFORM(vsum4ubs, 4, 24),
9164 GEN_VXFORM(vsum4sbs, 4, 28),
9165 GEN_VXFORM(vsum4shs, 4, 25),
9166 GEN_VXFORM(vsum2sws, 4, 26),
9167 GEN_VXFORM(vsumsws, 4, 30),
9168 GEN_VXFORM(vaddfp, 5, 0),
9169 GEN_VXFORM(vsubfp, 5, 1),
9170 GEN_VXFORM(vmaxfp, 5, 16),
9171 GEN_VXFORM(vminfp, 5, 17),
9172
9173 #undef GEN_VXRFORM1
9174 #undef GEN_VXRFORM
9175 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9176 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9177 #define GEN_VXRFORM(name, opc2, opc3) \
9178 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9179 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9180 GEN_VXRFORM(vcmpequb, 3, 0)
9181 GEN_VXRFORM(vcmpequh, 3, 1)
9182 GEN_VXRFORM(vcmpequw, 3, 2)
9183 GEN_VXRFORM(vcmpgtsb, 3, 12)
9184 GEN_VXRFORM(vcmpgtsh, 3, 13)
9185 GEN_VXRFORM(vcmpgtsw, 3, 14)
9186 GEN_VXRFORM(vcmpgtub, 3, 8)
9187 GEN_VXRFORM(vcmpgtuh, 3, 9)
9188 GEN_VXRFORM(vcmpgtuw, 3, 10)
9189 GEN_VXRFORM(vcmpeqfp, 3, 3)
9190 GEN_VXRFORM(vcmpgefp, 3, 7)
9191 GEN_VXRFORM(vcmpgtfp, 3, 11)
9192 GEN_VXRFORM(vcmpbfp, 3, 15)
9193
9194 #undef GEN_VXFORM_SIMM
9195 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9196 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9197 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9198 GEN_VXFORM_SIMM(vspltish, 6, 13),
9199 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9200
9201 #undef GEN_VXFORM_NOA
9202 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9203 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9204 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9205 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9206 GEN_VXFORM_NOA(vupklsb, 7, 10),
9207 GEN_VXFORM_NOA(vupklsh, 7, 11),
9208 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9209 GEN_VXFORM_NOA(vupklpx, 7, 15),
9210 GEN_VXFORM_NOA(vrefp, 5, 4),
9211 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9212 GEN_VXFORM_NOA(vexptefp, 5, 6),
9213 GEN_VXFORM_NOA(vlogefp, 5, 7),
9214 GEN_VXFORM_NOA(vrfim, 5, 8),
9215 GEN_VXFORM_NOA(vrfin, 5, 9),
9216 GEN_VXFORM_NOA(vrfip, 5, 10),
9217 GEN_VXFORM_NOA(vrfiz, 5, 11),
9218
9219 #undef GEN_VXFORM_UIMM
9220 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9221 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9222 GEN_VXFORM_UIMM(vspltb, 6, 8),
9223 GEN_VXFORM_UIMM(vsplth, 6, 9),
9224 GEN_VXFORM_UIMM(vspltw, 6, 10),
9225 GEN_VXFORM_UIMM(vcfux, 5, 12),
9226 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9227 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9228 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9229
9230 #undef GEN_VAFORM_PAIRED
9231 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9232 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9233 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9234 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9235 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9236 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9237 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9238 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9239
9240 #undef GEN_SPE
9241 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9242 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9243 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9244 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9245 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9246 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9247 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9248 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9249 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9250 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9251 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9252 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9253 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9254 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9255 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9256 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9257 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9258 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9259 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9260 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9261 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9262 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9263 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9264 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9265 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9266 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9267 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9268 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9269 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9270 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9271 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9272
9273 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9274 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9275 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9276 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9277 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9278 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9279 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9280 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9281 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9282 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9283 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9284 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9285 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9286 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9287
9288 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9289 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9290 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9291 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9292 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9293 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9294 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9295 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9296 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9297 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9298 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9299 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9300 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9301 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9302
9303 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9304 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9305 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9306 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9307 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9308 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9309 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9310 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9311 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9312 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9313 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9314 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9315 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9316 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9317 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9318 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9319
9320 #undef GEN_SPEOP_LDST
9321 #define GEN_SPEOP_LDST(name, opc2, sh) \
9322 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9323 GEN_SPEOP_LDST(evldd, 0x00, 3),
9324 GEN_SPEOP_LDST(evldw, 0x01, 3),
9325 GEN_SPEOP_LDST(evldh, 0x02, 3),
9326 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9327 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9328 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9329 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9330 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9331 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9332 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9333 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9334
9335 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9336 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9337 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9338 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9339 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9340 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9341 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9342 };
9343
9344 #include "helper_regs.h"
9345 #include "translate_init.c"
9346
9347 /*****************************************************************************/
9348 /* Misc PowerPC helpers */
9349 void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
9350 int flags)
9351 {
9352 #define RGPL 4
9353 #define RFPL 4
9354
9355 int i;
9356
9357 cpu_synchronize_state(env);
9358
9359 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9360 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9361 env->nip, env->lr, env->ctr, cpu_read_xer(env));
9362 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9363 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9364 env->hflags, env->mmu_idx);
9365 #if !defined(NO_TIMER_DUMP)
9366 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9367 #if !defined(CONFIG_USER_ONLY)
9368 " DECR %08" PRIu32
9369 #endif
9370 "\n",
9371 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9372 #if !defined(CONFIG_USER_ONLY)
9373 , cpu_ppc_load_decr(env)
9374 #endif
9375 );
9376 #endif
9377 for (i = 0; i < 32; i++) {
9378 if ((i & (RGPL - 1)) == 0)
9379 cpu_fprintf(f, "GPR%02d", i);
9380 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9381 if ((i & (RGPL - 1)) == (RGPL - 1))
9382 cpu_fprintf(f, "\n");
9383 }
9384 cpu_fprintf(f, "CR ");
9385 for (i = 0; i < 8; i++)
9386 cpu_fprintf(f, "%01x", env->crf[i]);
9387 cpu_fprintf(f, " [");
9388 for (i = 0; i < 8; i++) {
9389 char a = '-';
9390 if (env->crf[i] & 0x08)
9391 a = 'L';
9392 else if (env->crf[i] & 0x04)
9393 a = 'G';
9394 else if (env->crf[i] & 0x02)
9395 a = 'E';
9396 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9397 }
9398 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9399 env->reserve_addr);
9400 for (i = 0; i < 32; i++) {
9401 if ((i & (RFPL - 1)) == 0)
9402 cpu_fprintf(f, "FPR%02d", i);
9403 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9404 if ((i & (RFPL - 1)) == (RFPL - 1))
9405 cpu_fprintf(f, "\n");
9406 }
9407 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9408 #if !defined(CONFIG_USER_ONLY)
9409 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9410 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9411 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9412 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9413
9414 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9415 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9416 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9417 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9418
9419 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9420 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9421 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9422 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9423
9424 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9425 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9426 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9427 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9428 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9429
9430 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9431 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9432 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9433 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9434
9435 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9436 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9437 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9438 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9439
9440 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9441 " EPR " TARGET_FMT_lx "\n",
9442 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9443 env->spr[SPR_BOOKE_EPR]);
9444
9445 /* FSL-specific */
9446 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9447 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9448 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9449 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9450
9451 /*
9452 * IVORs are left out as they are large and do not change often --
9453 * they can be read with "p $ivor0", "p $ivor1", etc.
9454 */
9455 }
9456
9457 #if defined(TARGET_PPC64)
9458 if (env->flags & POWERPC_FLAG_CFAR) {
9459 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9460 }
9461 #endif
9462
9463 switch (env->mmu_model) {
9464 case POWERPC_MMU_32B:
9465 case POWERPC_MMU_601:
9466 case POWERPC_MMU_SOFT_6xx:
9467 case POWERPC_MMU_SOFT_74xx:
9468 #if defined(TARGET_PPC64)
9469 case POWERPC_MMU_64B:
9470 #endif
9471 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9472 break;
9473 case POWERPC_MMU_BOOKE206:
9474 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9475 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9476 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9477 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9478
9479 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9480 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9481 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9482 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9483
9484 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9485 " TLB1CFG " TARGET_FMT_lx "\n",
9486 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9487 env->spr[SPR_BOOKE_TLB1CFG]);
9488 break;
9489 default:
9490 break;
9491 }
9492 #endif
9493
9494 #undef RGPL
9495 #undef RFPL
9496 }
9497
9498 void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
9499 int flags)
9500 {
9501 #if defined(DO_PPC_STATISTICS)
9502 opc_handler_t **t1, **t2, **t3, *handler;
9503 int op1, op2, op3;
9504
9505 t1 = env->opcodes;
9506 for (op1 = 0; op1 < 64; op1++) {
9507 handler = t1[op1];
9508 if (is_indirect_opcode(handler)) {
9509 t2 = ind_table(handler);
9510 for (op2 = 0; op2 < 32; op2++) {
9511 handler = t2[op2];
9512 if (is_indirect_opcode(handler)) {
9513 t3 = ind_table(handler);
9514 for (op3 = 0; op3 < 32; op3++) {
9515 handler = t3[op3];
9516 if (handler->count == 0)
9517 continue;
9518 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9519 "%016" PRIx64 " %" PRId64 "\n",
9520 op1, op2, op3, op1, (op3 << 5) | op2,
9521 handler->oname,
9522 handler->count, handler->count);
9523 }
9524 } else {
9525 if (handler->count == 0)
9526 continue;
9527 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9528 "%016" PRIx64 " %" PRId64 "\n",
9529 op1, op2, op1, op2, handler->oname,
9530 handler->count, handler->count);
9531 }
9532 }
9533 } else {
9534 if (handler->count == 0)
9535 continue;
9536 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9537 " %" PRId64 "\n",
9538 op1, op1, handler->oname,
9539 handler->count, handler->count);
9540 }
9541 }
9542 #endif
9543 }
9544
9545 /*****************************************************************************/
9546 static inline void gen_intermediate_code_internal(CPUPPCState *env,
9547 TranslationBlock *tb,
9548 int search_pc)
9549 {
9550 DisasContext ctx, *ctxp = &ctx;
9551 opc_handler_t **table, *handler;
9552 target_ulong pc_start;
9553 uint16_t *gen_opc_end;
9554 CPUBreakpoint *bp;
9555 int j, lj = -1;
9556 int num_insns;
9557 int max_insns;
9558
9559 pc_start = tb->pc;
9560 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
9561 ctx.nip = pc_start;
9562 ctx.tb = tb;
9563 ctx.exception = POWERPC_EXCP_NONE;
9564 ctx.spr_cb = env->spr_cb;
9565 ctx.mem_idx = env->mmu_idx;
9566 ctx.access_type = -1;
9567 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9568 #if defined(TARGET_PPC64)
9569 ctx.sf_mode = msr_is_64bit(env, env->msr);
9570 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9571 #endif
9572 ctx.fpu_enabled = msr_fp;
9573 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9574 ctx.spe_enabled = msr_spe;
9575 else
9576 ctx.spe_enabled = 0;
9577 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9578 ctx.altivec_enabled = msr_vr;
9579 else
9580 ctx.altivec_enabled = 0;
9581 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9582 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9583 else
9584 ctx.singlestep_enabled = 0;
9585 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9586 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9587 if (unlikely(env->singlestep_enabled))
9588 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9589 #if defined (DO_SINGLE_STEP) && 0
9590 /* Single step trace mode */
9591 msr_se = 1;
9592 #endif
9593 num_insns = 0;
9594 max_insns = tb->cflags & CF_COUNT_MASK;
9595 if (max_insns == 0)
9596 max_insns = CF_COUNT_MASK;
9597
9598 gen_tb_start();
9599 /* Set env in case of segfault during code fetch */
9600 while (ctx.exception == POWERPC_EXCP_NONE
9601 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
9602 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9603 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9604 if (bp->pc == ctx.nip) {
9605 gen_debug_exception(ctxp);
9606 break;
9607 }
9608 }
9609 }
9610 if (unlikely(search_pc)) {
9611 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9612 if (lj < j) {
9613 lj++;
9614 while (lj < j)
9615 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9616 }
9617 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
9618 tcg_ctx.gen_opc_instr_start[lj] = 1;
9619 tcg_ctx.gen_opc_icount[lj] = num_insns;
9620 }
9621 LOG_DISAS("----------------\n");
9622 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9623 ctx.nip, ctx.mem_idx, (int)msr_ir);
9624 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9625 gen_io_start();
9626 if (unlikely(ctx.le_mode)) {
9627 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
9628 } else {
9629 ctx.opcode = cpu_ldl_code(env, ctx.nip);
9630 }
9631 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9632 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9633 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
9634 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
9635 tcg_gen_debug_insn_start(ctx.nip);
9636 }
9637 ctx.nip += 4;
9638 table = env->opcodes;
9639 num_insns++;
9640 handler = table[opc1(ctx.opcode)];
9641 if (is_indirect_opcode(handler)) {
9642 table = ind_table(handler);
9643 handler = table[opc2(ctx.opcode)];
9644 if (is_indirect_opcode(handler)) {
9645 table = ind_table(handler);
9646 handler = table[opc3(ctx.opcode)];
9647 }
9648 }
9649 /* Is opcode *REALLY* valid ? */
9650 if (unlikely(handler->handler == &gen_invalid)) {
9651 if (qemu_log_enabled()) {
9652 qemu_log("invalid/unsupported opcode: "
9653 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9654 opc1(ctx.opcode), opc2(ctx.opcode),
9655 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9656 }
9657 } else {
9658 uint32_t inval;
9659
9660 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9661 inval = handler->inval2;
9662 } else {
9663 inval = handler->inval1;
9664 }
9665
9666 if (unlikely((ctx.opcode & inval) != 0)) {
9667 if (qemu_log_enabled()) {
9668 qemu_log("invalid bits: %08x for opcode: "
9669 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9670 ctx.opcode & inval, opc1(ctx.opcode),
9671 opc2(ctx.opcode), opc3(ctx.opcode),
9672 ctx.opcode, ctx.nip - 4);
9673 }
9674 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9675 break;
9676 }
9677 }
9678 (*(handler->handler))(&ctx);
9679 #if defined(DO_PPC_STATISTICS)
9680 handler->count++;
9681 #endif
9682 /* Check trace mode exceptions */
9683 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9684 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9685 ctx.exception != POWERPC_SYSCALL &&
9686 ctx.exception != POWERPC_EXCP_TRAP &&
9687 ctx.exception != POWERPC_EXCP_BRANCH)) {
9688 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9689 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9690 (env->singlestep_enabled) ||
9691 singlestep ||
9692 num_insns >= max_insns)) {
9693 /* if we reach a page boundary or are single stepping, stop
9694 * generation
9695 */
9696 break;
9697 }
9698 }
9699 if (tb->cflags & CF_LAST_IO)
9700 gen_io_end();
9701 if (ctx.exception == POWERPC_EXCP_NONE) {
9702 gen_goto_tb(&ctx, 0, ctx.nip);
9703 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9704 if (unlikely(env->singlestep_enabled)) {
9705 gen_debug_exception(ctxp);
9706 }
9707 /* Generate the return instruction */
9708 tcg_gen_exit_tb(0);
9709 }
9710 gen_tb_end(tb, num_insns);
9711 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
9712 if (unlikely(search_pc)) {
9713 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9714 lj++;
9715 while (lj <= j)
9716 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9717 } else {
9718 tb->size = ctx.nip - pc_start;
9719 tb->icount = num_insns;
9720 }
9721 #if defined(DEBUG_DISAS)
9722 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9723 int flags;
9724 flags = env->bfd_mach;
9725 flags |= ctx.le_mode << 16;
9726 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9727 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
9728 qemu_log("\n");
9729 }
9730 #endif
9731 }
9732
9733 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9734 {
9735 gen_intermediate_code_internal(env, tb, 0);
9736 }
9737
9738 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9739 {
9740 gen_intermediate_code_internal(env, tb, 1);
9741 }
9742
9743 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9744 {
9745 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
9746 }
Qemu copy for testing