]> git.proxmox.com Git - mirror_qemu.git/blob - target-ppc/translate.c
projects / mirror_qemu.git / blob
? search:


85dad7fa0c16ecace064044ada7f375537834496
[mirror_qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 10*5 + 22*6 /* VSR */
55 + 8*5 /* CRF */];
56 static TCGv cpu_gpr[32];
57 #if !defined(TARGET_PPC64)
58 static TCGv cpu_gprh[32];
59 #endif
60 static TCGv_i64 cpu_fpr[32];
61 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
62 static TCGv_i64 cpu_vsr[32];
63 static TCGv_i32 cpu_crf[8];
64 static TCGv cpu_nip;
65 static TCGv cpu_msr;
66 static TCGv cpu_ctr;
67 static TCGv cpu_lr;
68 #if defined(TARGET_PPC64)
69 static TCGv cpu_cfar;
70 #endif
71 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
72 static TCGv cpu_reserve;
73 static TCGv cpu_fpscr;
74 static TCGv_i32 cpu_access_type;
75
76 #include "exec/gen-icount.h"
77
78 void ppc_translate_init(void)
79 {
80 int i;
81 char* p;
82 size_t cpu_reg_names_size;
83 static int done_init = 0;
84
85 if (done_init)
86 return;
87
88 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
89
90 p = cpu_reg_names;
91 cpu_reg_names_size = sizeof(cpu_reg_names);
92
93 for (i = 0; i < 8; i++) {
94 snprintf(p, cpu_reg_names_size, "crf%d", i);
95 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
96 offsetof(CPUPPCState, crf[i]), p);
97 p += 5;
98 cpu_reg_names_size -= 5;
99 }
100
101 for (i = 0; i < 32; i++) {
102 snprintf(p, cpu_reg_names_size, "r%d", i);
103 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
104 offsetof(CPUPPCState, gpr[i]), p);
105 p += (i < 10) ? 3 : 4;
106 cpu_reg_names_size -= (i < 10) ? 3 : 4;
107 #if !defined(TARGET_PPC64)
108 snprintf(p, cpu_reg_names_size, "r%dH", i);
109 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
110 offsetof(CPUPPCState, gprh[i]), p);
111 p += (i < 10) ? 4 : 5;
112 cpu_reg_names_size -= (i < 10) ? 4 : 5;
113 #endif
114
115 snprintf(p, cpu_reg_names_size, "fp%d", i);
116 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
117 offsetof(CPUPPCState, fpr[i]), p);
118 p += (i < 10) ? 4 : 5;
119 cpu_reg_names_size -= (i < 10) ? 4 : 5;
120
121 snprintf(p, cpu_reg_names_size, "avr%dH", i);
122 #ifdef HOST_WORDS_BIGENDIAN
123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
124 offsetof(CPUPPCState, avr[i].u64[0]), p);
125 #else
126 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
127 offsetof(CPUPPCState, avr[i].u64[1]), p);
128 #endif
129 p += (i < 10) ? 6 : 7;
130 cpu_reg_names_size -= (i < 10) ? 6 : 7;
131
132 snprintf(p, cpu_reg_names_size, "avr%dL", i);
133 #ifdef HOST_WORDS_BIGENDIAN
134 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
135 offsetof(CPUPPCState, avr[i].u64[1]), p);
136 #else
137 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
138 offsetof(CPUPPCState, avr[i].u64[0]), p);
139 #endif
140 p += (i < 10) ? 6 : 7;
141 cpu_reg_names_size -= (i < 10) ? 6 : 7;
142 snprintf(p, cpu_reg_names_size, "vsr%d", i);
143 cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
144 offsetof(CPUPPCState, vsr[i]), p);
145 p += (i < 10) ? 5 : 6;
146 cpu_reg_names_size -= (i < 10) ? 5 : 6;
147 }
148
149 cpu_nip = tcg_global_mem_new(TCG_AREG0,
150 offsetof(CPUPPCState, nip), "nip");
151
152 cpu_msr = tcg_global_mem_new(TCG_AREG0,
153 offsetof(CPUPPCState, msr), "msr");
154
155 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, ctr), "ctr");
157
158 cpu_lr = tcg_global_mem_new(TCG_AREG0,
159 offsetof(CPUPPCState, lr), "lr");
160
161 #if defined(TARGET_PPC64)
162 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
163 offsetof(CPUPPCState, cfar), "cfar");
164 #endif
165
166 cpu_xer = tcg_global_mem_new(TCG_AREG0,
167 offsetof(CPUPPCState, xer), "xer");
168 cpu_so = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, so), "SO");
170 cpu_ov = tcg_global_mem_new(TCG_AREG0,
171 offsetof(CPUPPCState, ov), "OV");
172 cpu_ca = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, ca), "CA");
174
175 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
176 offsetof(CPUPPCState, reserve_addr),
177 "reserve_addr");
178
179 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
180 offsetof(CPUPPCState, fpscr), "fpscr");
181
182 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
183 offsetof(CPUPPCState, access_type), "access_type");
184
185 done_init = 1;
186 }
187
188 /* internal defines */
189 typedef struct DisasContext {
190 struct TranslationBlock *tb;
191 target_ulong nip;
192 uint32_t opcode;
193 uint32_t exception;
194 /* Routine used to access memory */
195 int mem_idx;
196 int access_type;
197 /* Translation flags */
198 int le_mode;
199 #if defined(TARGET_PPC64)
200 int sf_mode;
201 int has_cfar;
202 #endif
203 int fpu_enabled;
204 int altivec_enabled;
205 int vsx_enabled;
206 int spe_enabled;
207 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
208 int singlestep_enabled;
209 uint64_t insns_flags;
210 uint64_t insns_flags2;
211 } DisasContext;
212
213 /* True when active word size < size of target_long. */
214 #ifdef TARGET_PPC64
215 # define NARROW_MODE(C) (!(C)->sf_mode)
216 #else
217 # define NARROW_MODE(C) 0
218 #endif
219
220 struct opc_handler_t {
221 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
222 uint32_t inval1;
223 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
224 uint32_t inval2;
225 /* instruction type */
226 uint64_t type;
227 /* extended instruction type */
228 uint64_t type2;
229 /* handler */
230 void (*handler)(DisasContext *ctx);
231 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
232 const char *oname;
233 #endif
234 #if defined(DO_PPC_STATISTICS)
235 uint64_t count;
236 #endif
237 };
238
239 static inline void gen_reset_fpstatus(void)
240 {
241 gen_helper_reset_fpstatus(cpu_env);
242 }
243
244 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
245 {
246 TCGv_i32 t0 = tcg_temp_new_i32();
247
248 if (set_fprf != 0) {
249 /* This case might be optimized later */
250 tcg_gen_movi_i32(t0, 1);
251 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
252 if (unlikely(set_rc)) {
253 tcg_gen_mov_i32(cpu_crf[1], t0);
254 }
255 gen_helper_float_check_status(cpu_env);
256 } else if (unlikely(set_rc)) {
257 /* We always need to compute fpcc */
258 tcg_gen_movi_i32(t0, 0);
259 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
260 tcg_gen_mov_i32(cpu_crf[1], t0);
261 }
262
263 tcg_temp_free_i32(t0);
264 }
265
266 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
267 {
268 if (ctx->access_type != access_type) {
269 tcg_gen_movi_i32(cpu_access_type, access_type);
270 ctx->access_type = access_type;
271 }
272 }
273
274 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
275 {
276 if (NARROW_MODE(ctx)) {
277 nip = (uint32_t)nip;
278 }
279 tcg_gen_movi_tl(cpu_nip, nip);
280 }
281
282 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
283 {
284 TCGv_i32 t0, t1;
285 if (ctx->exception == POWERPC_EXCP_NONE) {
286 gen_update_nip(ctx, ctx->nip);
287 }
288 t0 = tcg_const_i32(excp);
289 t1 = tcg_const_i32(error);
290 gen_helper_raise_exception_err(cpu_env, t0, t1);
291 tcg_temp_free_i32(t0);
292 tcg_temp_free_i32(t1);
293 ctx->exception = (excp);
294 }
295
296 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
297 {
298 TCGv_i32 t0;
299 if (ctx->exception == POWERPC_EXCP_NONE) {
300 gen_update_nip(ctx, ctx->nip);
301 }
302 t0 = tcg_const_i32(excp);
303 gen_helper_raise_exception(cpu_env, t0);
304 tcg_temp_free_i32(t0);
305 ctx->exception = (excp);
306 }
307
308 static inline void gen_debug_exception(DisasContext *ctx)
309 {
310 TCGv_i32 t0;
311
312 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
313 (ctx->exception != POWERPC_EXCP_SYNC)) {
314 gen_update_nip(ctx, ctx->nip);
315 }
316 t0 = tcg_const_i32(EXCP_DEBUG);
317 gen_helper_raise_exception(cpu_env, t0);
318 tcg_temp_free_i32(t0);
319 }
320
321 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
322 {
323 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
324 }
325
326 /* Stop translation */
327 static inline void gen_stop_exception(DisasContext *ctx)
328 {
329 gen_update_nip(ctx, ctx->nip);
330 ctx->exception = POWERPC_EXCP_STOP;
331 }
332
333 /* No need to update nip here, as execution flow will change */
334 static inline void gen_sync_exception(DisasContext *ctx)
335 {
336 ctx->exception = POWERPC_EXCP_SYNC;
337 }
338
339 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
340 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
341
342 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
343 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
344
345 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
346 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
347
348 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
349 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
350
351 typedef struct opcode_t {
352 unsigned char opc1, opc2, opc3;
353 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
354 unsigned char pad[5];
355 #else
356 unsigned char pad[1];
357 #endif
358 opc_handler_t handler;
359 const char *oname;
360 } opcode_t;
361
362 /*****************************************************************************/
363 /*** Instruction decoding ***/
364 #define EXTRACT_HELPER(name, shift, nb) \
365 static inline uint32_t name(uint32_t opcode) \
366 { \
367 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
368 }
369
370 #define EXTRACT_SHELPER(name, shift, nb) \
371 static inline int32_t name(uint32_t opcode) \
372 { \
373 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
374 }
375
376 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
377 static inline uint32_t name(uint32_t opcode) \
378 { \
379 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
380 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
381 }
382 /* Opcode part 1 */
383 EXTRACT_HELPER(opc1, 26, 6);
384 /* Opcode part 2 */
385 EXTRACT_HELPER(opc2, 1, 5);
386 /* Opcode part 3 */
387 EXTRACT_HELPER(opc3, 6, 5);
388 /* Update Cr0 flags */
389 EXTRACT_HELPER(Rc, 0, 1);
390 /* Destination */
391 EXTRACT_HELPER(rD, 21, 5);
392 /* Source */
393 EXTRACT_HELPER(rS, 21, 5);
394 /* First operand */
395 EXTRACT_HELPER(rA, 16, 5);
396 /* Second operand */
397 EXTRACT_HELPER(rB, 11, 5);
398 /* Third operand */
399 EXTRACT_HELPER(rC, 6, 5);
400 /*** Get CRn ***/
401 EXTRACT_HELPER(crfD, 23, 3);
402 EXTRACT_HELPER(crfS, 18, 3);
403 EXTRACT_HELPER(crbD, 21, 5);
404 EXTRACT_HELPER(crbA, 16, 5);
405 EXTRACT_HELPER(crbB, 11, 5);
406 /* SPR / TBL */
407 EXTRACT_HELPER(_SPR, 11, 10);
408 static inline uint32_t SPR(uint32_t opcode)
409 {
410 uint32_t sprn = _SPR(opcode);
411
412 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
413 }
414 /*** Get constants ***/
415 EXTRACT_HELPER(IMM, 12, 8);
416 /* 16 bits signed immediate value */
417 EXTRACT_SHELPER(SIMM, 0, 16);
418 /* 16 bits unsigned immediate value */
419 EXTRACT_HELPER(UIMM, 0, 16);
420 /* 5 bits signed immediate value */
421 EXTRACT_HELPER(SIMM5, 16, 5);
422 /* 5 bits signed immediate value */
423 EXTRACT_HELPER(UIMM5, 16, 5);
424 /* Bit count */
425 EXTRACT_HELPER(NB, 11, 5);
426 /* Shift count */
427 EXTRACT_HELPER(SH, 11, 5);
428 /* Vector shift count */
429 EXTRACT_HELPER(VSH, 6, 4);
430 /* Mask start */
431 EXTRACT_HELPER(MB, 6, 5);
432 /* Mask end */
433 EXTRACT_HELPER(ME, 1, 5);
434 /* Trap operand */
435 EXTRACT_HELPER(TO, 21, 5);
436
437 EXTRACT_HELPER(CRM, 12, 8);
438 EXTRACT_HELPER(SR, 16, 4);
439
440 /* mtfsf/mtfsfi */
441 EXTRACT_HELPER(FPBF, 23, 3);
442 EXTRACT_HELPER(FPIMM, 12, 4);
443 EXTRACT_HELPER(FPL, 25, 1);
444 EXTRACT_HELPER(FPFLM, 17, 8);
445 EXTRACT_HELPER(FPW, 16, 1);
446
447 /*** Jump target decoding ***/
448 /* Displacement */
449 EXTRACT_SHELPER(d, 0, 16);
450 /* Immediate address */
451 static inline target_ulong LI(uint32_t opcode)
452 {
453 return (opcode >> 0) & 0x03FFFFFC;
454 }
455
456 static inline uint32_t BD(uint32_t opcode)
457 {
458 return (opcode >> 0) & 0xFFFC;
459 }
460
461 EXTRACT_HELPER(BO, 21, 5);
462 EXTRACT_HELPER(BI, 16, 5);
463 /* Absolute/relative address */
464 EXTRACT_HELPER(AA, 1, 1);
465 /* Link */
466 EXTRACT_HELPER(LK, 0, 1);
467
468 /* Create a mask between <start> and <end> bits */
469 static inline target_ulong MASK(uint32_t start, uint32_t end)
470 {
471 target_ulong ret;
472
473 #if defined(TARGET_PPC64)
474 if (likely(start == 0)) {
475 ret = UINT64_MAX << (63 - end);
476 } else if (likely(end == 63)) {
477 ret = UINT64_MAX >> start;
478 }
479 #else
480 if (likely(start == 0)) {
481 ret = UINT32_MAX << (31 - end);
482 } else if (likely(end == 31)) {
483 ret = UINT32_MAX >> start;
484 }
485 #endif
486 else {
487 ret = (((target_ulong)(-1ULL)) >> (start)) ^
488 (((target_ulong)(-1ULL) >> (end)) >> 1);
489 if (unlikely(start > end))
490 return ~ret;
491 }
492
493 return ret;
494 }
495
496 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
497 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
498 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
499 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
500 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
501 EXTRACT_HELPER(DM, 8, 2);
502 EXTRACT_HELPER(UIM, 16, 2);
503 EXTRACT_HELPER(SHW, 8, 2);
504 /*****************************************************************************/
505 /* PowerPC instructions table */
506
507 #if defined(DO_PPC_STATISTICS)
508 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
509 { \
510 .opc1 = op1, \
511 .opc2 = op2, \
512 .opc3 = op3, \
513 .pad = { 0, }, \
514 .handler = { \
515 .inval1 = invl, \
516 .type = _typ, \
517 .type2 = _typ2, \
518 .handler = &gen_##name, \
519 .oname = stringify(name), \
520 }, \
521 .oname = stringify(name), \
522 }
523 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
524 { \
525 .opc1 = op1, \
526 .opc2 = op2, \
527 .opc3 = op3, \
528 .pad = { 0, }, \
529 .handler = { \
530 .inval1 = invl1, \
531 .inval2 = invl2, \
532 .type = _typ, \
533 .type2 = _typ2, \
534 .handler = &gen_##name, \
535 .oname = stringify(name), \
536 }, \
537 .oname = stringify(name), \
538 }
539 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
540 { \
541 .opc1 = op1, \
542 .opc2 = op2, \
543 .opc3 = op3, \
544 .pad = { 0, }, \
545 .handler = { \
546 .inval1 = invl, \
547 .type = _typ, \
548 .type2 = _typ2, \
549 .handler = &gen_##name, \
550 .oname = onam, \
551 }, \
552 .oname = onam, \
553 }
554 #else
555 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
556 { \
557 .opc1 = op1, \
558 .opc2 = op2, \
559 .opc3 = op3, \
560 .pad = { 0, }, \
561 .handler = { \
562 .inval1 = invl, \
563 .type = _typ, \
564 .type2 = _typ2, \
565 .handler = &gen_##name, \
566 }, \
567 .oname = stringify(name), \
568 }
569 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
570 { \
571 .opc1 = op1, \
572 .opc2 = op2, \
573 .opc3 = op3, \
574 .pad = { 0, }, \
575 .handler = { \
576 .inval1 = invl1, \
577 .inval2 = invl2, \
578 .type = _typ, \
579 .type2 = _typ2, \
580 .handler = &gen_##name, \
581 }, \
582 .oname = stringify(name), \
583 }
584 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
585 { \
586 .opc1 = op1, \
587 .opc2 = op2, \
588 .opc3 = op3, \
589 .pad = { 0, }, \
590 .handler = { \
591 .inval1 = invl, \
592 .type = _typ, \
593 .type2 = _typ2, \
594 .handler = &gen_##name, \
595 }, \
596 .oname = onam, \
597 }
598 #endif
599
600 /* SPR load/store helpers */
601 static inline void gen_load_spr(TCGv t, int reg)
602 {
603 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
604 }
605
606 static inline void gen_store_spr(int reg, TCGv t)
607 {
608 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
609 }
610
611 /* Invalid instruction */
612 static void gen_invalid(DisasContext *ctx)
613 {
614 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
615 }
616
617 static opc_handler_t invalid_handler = {
618 .inval1 = 0xFFFFFFFF,
619 .inval2 = 0xFFFFFFFF,
620 .type = PPC_NONE,
621 .type2 = PPC_NONE,
622 .handler = gen_invalid,
623 };
624
625 #if defined(TARGET_PPC64)
626 /* NOTE: as this time, the only use of is_user_mode() is in 64 bit code. And */
627 /* so the function is wrapped in the standard 64-bit ifdef in order to */
628 /* avoid compiler warnings in 32-bit implementations. */
629 static bool is_user_mode(DisasContext *ctx)
630 {
631 #if defined(CONFIG_USER_ONLY)
632 return true;
633 #else
634 return ctx->mem_idx == 0;
635 #endif
636 }
637 #endif
638
639 /*** Integer comparison ***/
640
641 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
642 {
643 TCGv t0 = tcg_temp_new();
644 TCGv_i32 t1 = tcg_temp_new_i32();
645
646 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
647
648 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
649 tcg_gen_trunc_tl_i32(t1, t0);
650 tcg_gen_shli_i32(t1, t1, CRF_LT);
651 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
652
653 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
654 tcg_gen_trunc_tl_i32(t1, t0);
655 tcg_gen_shli_i32(t1, t1, CRF_GT);
656 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
657
658 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
659 tcg_gen_trunc_tl_i32(t1, t0);
660 tcg_gen_shli_i32(t1, t1, CRF_EQ);
661 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
662
663 tcg_temp_free(t0);
664 tcg_temp_free_i32(t1);
665 }
666
667 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
668 {
669 TCGv t0 = tcg_const_tl(arg1);
670 gen_op_cmp(arg0, t0, s, crf);
671 tcg_temp_free(t0);
672 }
673
674 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
675 {
676 TCGv t0, t1;
677 t0 = tcg_temp_new();
678 t1 = tcg_temp_new();
679 if (s) {
680 tcg_gen_ext32s_tl(t0, arg0);
681 tcg_gen_ext32s_tl(t1, arg1);
682 } else {
683 tcg_gen_ext32u_tl(t0, arg0);
684 tcg_gen_ext32u_tl(t1, arg1);
685 }
686 gen_op_cmp(t0, t1, s, crf);
687 tcg_temp_free(t1);
688 tcg_temp_free(t0);
689 }
690
691 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
692 {
693 TCGv t0 = tcg_const_tl(arg1);
694 gen_op_cmp32(arg0, t0, s, crf);
695 tcg_temp_free(t0);
696 }
697
698 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
699 {
700 if (NARROW_MODE(ctx)) {
701 gen_op_cmpi32(reg, 0, 1, 0);
702 } else {
703 gen_op_cmpi(reg, 0, 1, 0);
704 }
705 }
706
707 /* cmp */
708 static void gen_cmp(DisasContext *ctx)
709 {
710 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
711 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
712 1, crfD(ctx->opcode));
713 } else {
714 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
715 1, crfD(ctx->opcode));
716 }
717 }
718
719 /* cmpi */
720 static void gen_cmpi(DisasContext *ctx)
721 {
722 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
723 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
724 1, crfD(ctx->opcode));
725 } else {
726 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
727 1, crfD(ctx->opcode));
728 }
729 }
730
731 /* cmpl */
732 static void gen_cmpl(DisasContext *ctx)
733 {
734 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
735 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
736 0, crfD(ctx->opcode));
737 } else {
738 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
739 0, crfD(ctx->opcode));
740 }
741 }
742
743 /* cmpli */
744 static void gen_cmpli(DisasContext *ctx)
745 {
746 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
747 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
748 0, crfD(ctx->opcode));
749 } else {
750 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
751 0, crfD(ctx->opcode));
752 }
753 }
754
755 /* isel (PowerPC 2.03 specification) */
756 static void gen_isel(DisasContext *ctx)
757 {
758 int l1, l2;
759 uint32_t bi = rC(ctx->opcode);
760 uint32_t mask;
761 TCGv_i32 t0;
762
763 l1 = gen_new_label();
764 l2 = gen_new_label();
765
766 mask = 1 << (3 - (bi & 0x03));
767 t0 = tcg_temp_new_i32();
768 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
769 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
770 if (rA(ctx->opcode) == 0)
771 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
772 else
773 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
774 tcg_gen_br(l2);
775 gen_set_label(l1);
776 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
777 gen_set_label(l2);
778 tcg_temp_free_i32(t0);
779 }
780
781 /* cmpb: PowerPC 2.05 specification */
782 static void gen_cmpb(DisasContext *ctx)
783 {
784 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
785 cpu_gpr[rB(ctx->opcode)]);
786 }
787
788 /*** Integer arithmetic ***/
789
790 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
791 TCGv arg1, TCGv arg2, int sub)
792 {
793 TCGv t0 = tcg_temp_new();
794
795 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
796 tcg_gen_xor_tl(t0, arg1, arg2);
797 if (sub) {
798 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
799 } else {
800 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
801 }
802 tcg_temp_free(t0);
803 if (NARROW_MODE(ctx)) {
804 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
805 }
806 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
807 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
808 }
809
810 /* Common add function */
811 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
812 TCGv arg2, bool add_ca, bool compute_ca,
813 bool compute_ov, bool compute_rc0)
814 {
815 TCGv t0 = ret;
816
817 if (compute_ca || compute_ov) {
818 t0 = tcg_temp_new();
819 }
820
821 if (compute_ca) {
822 if (NARROW_MODE(ctx)) {
823 /* Caution: a non-obvious corner case of the spec is that we
824 must produce the *entire* 64-bit addition, but produce the
825 carry into bit 32. */
826 TCGv t1 = tcg_temp_new();
827 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
828 tcg_gen_add_tl(t0, arg1, arg2);
829 if (add_ca) {
830 tcg_gen_add_tl(t0, t0, cpu_ca);
831 }
832 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
833 tcg_temp_free(t1);
834 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
835 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
836 } else {
837 TCGv zero = tcg_const_tl(0);
838 if (add_ca) {
839 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
840 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
841 } else {
842 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
843 }
844 tcg_temp_free(zero);
845 }
846 } else {
847 tcg_gen_add_tl(t0, arg1, arg2);
848 if (add_ca) {
849 tcg_gen_add_tl(t0, t0, cpu_ca);
850 }
851 }
852
853 if (compute_ov) {
854 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
855 }
856 if (unlikely(compute_rc0)) {
857 gen_set_Rc0(ctx, t0);
858 }
859
860 if (!TCGV_EQUAL(t0, ret)) {
861 tcg_gen_mov_tl(ret, t0);
862 tcg_temp_free(t0);
863 }
864 }
865 /* Add functions with two operands */
866 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
867 static void glue(gen_, name)(DisasContext *ctx) \
868 { \
869 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
870 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
871 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
872 }
873 /* Add functions with one operand and one immediate */
874 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
875 add_ca, compute_ca, compute_ov) \
876 static void glue(gen_, name)(DisasContext *ctx) \
877 { \
878 TCGv t0 = tcg_const_tl(const_val); \
879 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
880 cpu_gpr[rA(ctx->opcode)], t0, \
881 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
882 tcg_temp_free(t0); \
883 }
884
885 /* add add. addo addo. */
886 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
887 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
888 /* addc addc. addco addco. */
889 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
890 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
891 /* adde adde. addeo addeo. */
892 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
893 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
894 /* addme addme. addmeo addmeo. */
895 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
896 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
897 /* addze addze. addzeo addzeo.*/
898 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
899 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
900 /* addi */
901 static void gen_addi(DisasContext *ctx)
902 {
903 target_long simm = SIMM(ctx->opcode);
904
905 if (rA(ctx->opcode) == 0) {
906 /* li case */
907 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
908 } else {
909 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
910 cpu_gpr[rA(ctx->opcode)], simm);
911 }
912 }
913 /* addic addic.*/
914 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
915 {
916 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
917 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
918 c, 0, 1, 0, compute_rc0);
919 tcg_temp_free(c);
920 }
921
922 static void gen_addic(DisasContext *ctx)
923 {
924 gen_op_addic(ctx, 0);
925 }
926
927 static void gen_addic_(DisasContext *ctx)
928 {
929 gen_op_addic(ctx, 1);
930 }
931
932 /* addis */
933 static void gen_addis(DisasContext *ctx)
934 {
935 target_long simm = SIMM(ctx->opcode);
936
937 if (rA(ctx->opcode) == 0) {
938 /* lis case */
939 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
940 } else {
941 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
942 cpu_gpr[rA(ctx->opcode)], simm << 16);
943 }
944 }
945
946 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
947 TCGv arg2, int sign, int compute_ov)
948 {
949 int l1 = gen_new_label();
950 int l2 = gen_new_label();
951 TCGv_i32 t0 = tcg_temp_local_new_i32();
952 TCGv_i32 t1 = tcg_temp_local_new_i32();
953
954 tcg_gen_trunc_tl_i32(t0, arg1);
955 tcg_gen_trunc_tl_i32(t1, arg2);
956 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
957 if (sign) {
958 int l3 = gen_new_label();
959 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
960 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
961 gen_set_label(l3);
962 tcg_gen_div_i32(t0, t0, t1);
963 } else {
964 tcg_gen_divu_i32(t0, t0, t1);
965 }
966 if (compute_ov) {
967 tcg_gen_movi_tl(cpu_ov, 0);
968 }
969 tcg_gen_br(l2);
970 gen_set_label(l1);
971 if (sign) {
972 tcg_gen_sari_i32(t0, t0, 31);
973 } else {
974 tcg_gen_movi_i32(t0, 0);
975 }
976 if (compute_ov) {
977 tcg_gen_movi_tl(cpu_ov, 1);
978 tcg_gen_movi_tl(cpu_so, 1);
979 }
980 gen_set_label(l2);
981 tcg_gen_extu_i32_tl(ret, t0);
982 tcg_temp_free_i32(t0);
983 tcg_temp_free_i32(t1);
984 if (unlikely(Rc(ctx->opcode) != 0))
985 gen_set_Rc0(ctx, ret);
986 }
987 /* Div functions */
988 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
989 static void glue(gen_, name)(DisasContext *ctx) \
990 { \
991 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
992 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
993 sign, compute_ov); \
994 }
995 /* divwu divwu. divwuo divwuo. */
996 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
997 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
998 /* divw divw. divwo divwo. */
999 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1000 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1001
1002 /* div[wd]eu[o][.] */
1003 #define GEN_DIVE(name, hlpr, compute_ov) \
1004 static void gen_##name(DisasContext *ctx) \
1005 { \
1006 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1007 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1008 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1009 tcg_temp_free_i32(t0); \
1010 if (unlikely(Rc(ctx->opcode) != 0)) { \
1011 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1012 } \
1013 }
1014
1015 GEN_DIVE(divweu, divweu, 0);
1016 GEN_DIVE(divweuo, divweu, 1);
1017 GEN_DIVE(divwe, divwe, 0);
1018 GEN_DIVE(divweo, divwe, 1);
1019
1020 #if defined(TARGET_PPC64)
1021 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1022 TCGv arg2, int sign, int compute_ov)
1023 {
1024 int l1 = gen_new_label();
1025 int l2 = gen_new_label();
1026
1027 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1028 if (sign) {
1029 int l3 = gen_new_label();
1030 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1031 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1032 gen_set_label(l3);
1033 tcg_gen_div_i64(ret, arg1, arg2);
1034 } else {
1035 tcg_gen_divu_i64(ret, arg1, arg2);
1036 }
1037 if (compute_ov) {
1038 tcg_gen_movi_tl(cpu_ov, 0);
1039 }
1040 tcg_gen_br(l2);
1041 gen_set_label(l1);
1042 if (sign) {
1043 tcg_gen_sari_i64(ret, arg1, 63);
1044 } else {
1045 tcg_gen_movi_i64(ret, 0);
1046 }
1047 if (compute_ov) {
1048 tcg_gen_movi_tl(cpu_ov, 1);
1049 tcg_gen_movi_tl(cpu_so, 1);
1050 }
1051 gen_set_label(l2);
1052 if (unlikely(Rc(ctx->opcode) != 0))
1053 gen_set_Rc0(ctx, ret);
1054 }
1055 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1056 static void glue(gen_, name)(DisasContext *ctx) \
1057 { \
1058 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1059 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1060 sign, compute_ov); \
1061 }
1062 /* divwu divwu. divwuo divwuo. */
1063 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1064 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1065 /* divw divw. divwo divwo. */
1066 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1067 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1068
1069 GEN_DIVE(divdeu, divdeu, 0);
1070 GEN_DIVE(divdeuo, divdeu, 1);
1071 GEN_DIVE(divde, divde, 0);
1072 GEN_DIVE(divdeo, divde, 1);
1073 #endif
1074
1075 /* mulhw mulhw. */
1076 static void gen_mulhw(DisasContext *ctx)
1077 {
1078 TCGv_i32 t0 = tcg_temp_new_i32();
1079 TCGv_i32 t1 = tcg_temp_new_i32();
1080
1081 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1082 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1083 tcg_gen_muls2_i32(t0, t1, t0, t1);
1084 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1085 tcg_temp_free_i32(t0);
1086 tcg_temp_free_i32(t1);
1087 if (unlikely(Rc(ctx->opcode) != 0))
1088 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1089 }
1090
1091 /* mulhwu mulhwu. */
1092 static void gen_mulhwu(DisasContext *ctx)
1093 {
1094 TCGv_i32 t0 = tcg_temp_new_i32();
1095 TCGv_i32 t1 = tcg_temp_new_i32();
1096
1097 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1098 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1099 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1100 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1101 tcg_temp_free_i32(t0);
1102 tcg_temp_free_i32(t1);
1103 if (unlikely(Rc(ctx->opcode) != 0))
1104 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1105 }
1106
1107 /* mullw mullw. */
1108 static void gen_mullw(DisasContext *ctx)
1109 {
1110 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1111 cpu_gpr[rB(ctx->opcode)]);
1112 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1113 if (unlikely(Rc(ctx->opcode) != 0))
1114 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1115 }
1116
1117 /* mullwo mullwo. */
1118 static void gen_mullwo(DisasContext *ctx)
1119 {
1120 TCGv_i32 t0 = tcg_temp_new_i32();
1121 TCGv_i32 t1 = tcg_temp_new_i32();
1122
1123 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1124 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1125 tcg_gen_muls2_i32(t0, t1, t0, t1);
1126 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1127
1128 tcg_gen_sari_i32(t0, t0, 31);
1129 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1130 tcg_gen_extu_i32_tl(cpu_ov, t0);
1131 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1132
1133 tcg_temp_free_i32(t0);
1134 tcg_temp_free_i32(t1);
1135 if (unlikely(Rc(ctx->opcode) != 0))
1136 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1137 }
1138
1139 /* mulli */
1140 static void gen_mulli(DisasContext *ctx)
1141 {
1142 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1143 SIMM(ctx->opcode));
1144 }
1145
1146 #if defined(TARGET_PPC64)
1147 /* mulhd mulhd. */
1148 static void gen_mulhd(DisasContext *ctx)
1149 {
1150 TCGv lo = tcg_temp_new();
1151 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1152 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1153 tcg_temp_free(lo);
1154 if (unlikely(Rc(ctx->opcode) != 0)) {
1155 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1156 }
1157 }
1158
1159 /* mulhdu mulhdu. */
1160 static void gen_mulhdu(DisasContext *ctx)
1161 {
1162 TCGv lo = tcg_temp_new();
1163 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1164 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1165 tcg_temp_free(lo);
1166 if (unlikely(Rc(ctx->opcode) != 0)) {
1167 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1168 }
1169 }
1170
1171 /* mulld mulld. */
1172 static void gen_mulld(DisasContext *ctx)
1173 {
1174 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1175 cpu_gpr[rB(ctx->opcode)]);
1176 if (unlikely(Rc(ctx->opcode) != 0))
1177 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1178 }
1179
1180 /* mulldo mulldo. */
1181 static void gen_mulldo(DisasContext *ctx)
1182 {
1183 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1184 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1185 if (unlikely(Rc(ctx->opcode) != 0)) {
1186 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1187 }
1188 }
1189 #endif
1190
1191 /* Common subf function */
1192 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1193 TCGv arg2, bool add_ca, bool compute_ca,
1194 bool compute_ov, bool compute_rc0)
1195 {
1196 TCGv t0 = ret;
1197
1198 if (compute_ca || compute_ov) {
1199 t0 = tcg_temp_new();
1200 }
1201
1202 if (compute_ca) {
1203 /* dest = ~arg1 + arg2 [+ ca]. */
1204 if (NARROW_MODE(ctx)) {
1205 /* Caution: a non-obvious corner case of the spec is that we
1206 must produce the *entire* 64-bit addition, but produce the
1207 carry into bit 32. */
1208 TCGv inv1 = tcg_temp_new();
1209 TCGv t1 = tcg_temp_new();
1210 tcg_gen_not_tl(inv1, arg1);
1211 if (add_ca) {
1212 tcg_gen_add_tl(t0, arg2, cpu_ca);
1213 } else {
1214 tcg_gen_addi_tl(t0, arg2, 1);
1215 }
1216 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1217 tcg_gen_add_tl(t0, t0, inv1);
1218 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1219 tcg_temp_free(t1);
1220 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1221 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1222 } else if (add_ca) {
1223 TCGv zero, inv1 = tcg_temp_new();
1224 tcg_gen_not_tl(inv1, arg1);
1225 zero = tcg_const_tl(0);
1226 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1227 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1228 tcg_temp_free(zero);
1229 tcg_temp_free(inv1);
1230 } else {
1231 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1232 tcg_gen_sub_tl(t0, arg2, arg1);
1233 }
1234 } else if (add_ca) {
1235 /* Since we're ignoring carry-out, we can simplify the
1236 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1237 tcg_gen_sub_tl(t0, arg2, arg1);
1238 tcg_gen_add_tl(t0, t0, cpu_ca);
1239 tcg_gen_subi_tl(t0, t0, 1);
1240 } else {
1241 tcg_gen_sub_tl(t0, arg2, arg1);
1242 }
1243
1244 if (compute_ov) {
1245 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1246 }
1247 if (unlikely(compute_rc0)) {
1248 gen_set_Rc0(ctx, t0);
1249 }
1250
1251 if (!TCGV_EQUAL(t0, ret)) {
1252 tcg_gen_mov_tl(ret, t0);
1253 tcg_temp_free(t0);
1254 }
1255 }
1256 /* Sub functions with Two operands functions */
1257 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1258 static void glue(gen_, name)(DisasContext *ctx) \
1259 { \
1260 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1261 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1262 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1263 }
1264 /* Sub functions with one operand and one immediate */
1265 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1266 add_ca, compute_ca, compute_ov) \
1267 static void glue(gen_, name)(DisasContext *ctx) \
1268 { \
1269 TCGv t0 = tcg_const_tl(const_val); \
1270 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1271 cpu_gpr[rA(ctx->opcode)], t0, \
1272 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1273 tcg_temp_free(t0); \
1274 }
1275 /* subf subf. subfo subfo. */
1276 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1277 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1278 /* subfc subfc. subfco subfco. */
1279 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1280 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1281 /* subfe subfe. subfeo subfo. */
1282 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1283 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1284 /* subfme subfme. subfmeo subfmeo. */
1285 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1286 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1287 /* subfze subfze. subfzeo subfzeo.*/
1288 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1289 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1290
1291 /* subfic */
1292 static void gen_subfic(DisasContext *ctx)
1293 {
1294 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1295 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1296 c, 0, 1, 0, 0);
1297 tcg_temp_free(c);
1298 }
1299
1300 /* neg neg. nego nego. */
1301 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1302 {
1303 TCGv zero = tcg_const_tl(0);
1304 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1305 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1306 tcg_temp_free(zero);
1307 }
1308
1309 static void gen_neg(DisasContext *ctx)
1310 {
1311 gen_op_arith_neg(ctx, 0);
1312 }
1313
1314 static void gen_nego(DisasContext *ctx)
1315 {
1316 gen_op_arith_neg(ctx, 1);
1317 }
1318
1319 /*** Integer logical ***/
1320 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1321 static void glue(gen_, name)(DisasContext *ctx) \
1322 { \
1323 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1324 cpu_gpr[rB(ctx->opcode)]); \
1325 if (unlikely(Rc(ctx->opcode) != 0)) \
1326 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1327 }
1328
1329 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1330 static void glue(gen_, name)(DisasContext *ctx) \
1331 { \
1332 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1333 if (unlikely(Rc(ctx->opcode) != 0)) \
1334 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1335 }
1336
1337 /* and & and. */
1338 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1339 /* andc & andc. */
1340 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1341
1342 /* andi. */
1343 static void gen_andi_(DisasContext *ctx)
1344 {
1345 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1346 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1347 }
1348
1349 /* andis. */
1350 static void gen_andis_(DisasContext *ctx)
1351 {
1352 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1353 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1354 }
1355
1356 /* cntlzw */
1357 static void gen_cntlzw(DisasContext *ctx)
1358 {
1359 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1360 if (unlikely(Rc(ctx->opcode) != 0))
1361 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1362 }
1363 /* eqv & eqv. */
1364 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1365 /* extsb & extsb. */
1366 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1367 /* extsh & extsh. */
1368 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1369 /* nand & nand. */
1370 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1371 /* nor & nor. */
1372 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1373
1374 /* or & or. */
1375 static void gen_or(DisasContext *ctx)
1376 {
1377 int rs, ra, rb;
1378
1379 rs = rS(ctx->opcode);
1380 ra = rA(ctx->opcode);
1381 rb = rB(ctx->opcode);
1382 /* Optimisation for mr. ri case */
1383 if (rs != ra || rs != rb) {
1384 if (rs != rb)
1385 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1386 else
1387 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1388 if (unlikely(Rc(ctx->opcode) != 0))
1389 gen_set_Rc0(ctx, cpu_gpr[ra]);
1390 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1391 gen_set_Rc0(ctx, cpu_gpr[rs]);
1392 #if defined(TARGET_PPC64)
1393 } else {
1394 int prio = 0;
1395
1396 switch (rs) {
1397 case 1:
1398 /* Set process priority to low */
1399 prio = 2;
1400 break;
1401 case 6:
1402 /* Set process priority to medium-low */
1403 prio = 3;
1404 break;
1405 case 2:
1406 /* Set process priority to normal */
1407 prio = 4;
1408 break;
1409 #if !defined(CONFIG_USER_ONLY)
1410 case 31:
1411 if (ctx->mem_idx > 0) {
1412 /* Set process priority to very low */
1413 prio = 1;
1414 }
1415 break;
1416 case 5:
1417 if (ctx->mem_idx > 0) {
1418 /* Set process priority to medium-hight */
1419 prio = 5;
1420 }
1421 break;
1422 case 3:
1423 if (ctx->mem_idx > 0) {
1424 /* Set process priority to high */
1425 prio = 6;
1426 }
1427 break;
1428 case 7:
1429 if (ctx->mem_idx > 1) {
1430 /* Set process priority to very high */
1431 prio = 7;
1432 }
1433 break;
1434 #endif
1435 default:
1436 /* nop */
1437 break;
1438 }
1439 if (prio) {
1440 TCGv t0 = tcg_temp_new();
1441 gen_load_spr(t0, SPR_PPR);
1442 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1443 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1444 gen_store_spr(SPR_PPR, t0);
1445 tcg_temp_free(t0);
1446 }
1447 #endif
1448 }
1449 }
1450 /* orc & orc. */
1451 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1452
1453 /* xor & xor. */
1454 static void gen_xor(DisasContext *ctx)
1455 {
1456 /* Optimisation for "set to zero" case */
1457 if (rS(ctx->opcode) != rB(ctx->opcode))
1458 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1459 else
1460 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1461 if (unlikely(Rc(ctx->opcode) != 0))
1462 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1463 }
1464
1465 /* ori */
1466 static void gen_ori(DisasContext *ctx)
1467 {
1468 target_ulong uimm = UIMM(ctx->opcode);
1469
1470 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1471 /* NOP */
1472 /* XXX: should handle special NOPs for POWER series */
1473 return;
1474 }
1475 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1476 }
1477
1478 /* oris */
1479 static void gen_oris(DisasContext *ctx)
1480 {
1481 target_ulong uimm = UIMM(ctx->opcode);
1482
1483 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1484 /* NOP */
1485 return;
1486 }
1487 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1488 }
1489
1490 /* xori */
1491 static void gen_xori(DisasContext *ctx)
1492 {
1493 target_ulong uimm = UIMM(ctx->opcode);
1494
1495 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1496 /* NOP */
1497 return;
1498 }
1499 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1500 }
1501
1502 /* xoris */
1503 static void gen_xoris(DisasContext *ctx)
1504 {
1505 target_ulong uimm = UIMM(ctx->opcode);
1506
1507 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1508 /* NOP */
1509 return;
1510 }
1511 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1512 }
1513
1514 /* popcntb : PowerPC 2.03 specification */
1515 static void gen_popcntb(DisasContext *ctx)
1516 {
1517 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1518 }
1519
1520 static void gen_popcntw(DisasContext *ctx)
1521 {
1522 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1523 }
1524
1525 #if defined(TARGET_PPC64)
1526 /* popcntd: PowerPC 2.06 specification */
1527 static void gen_popcntd(DisasContext *ctx)
1528 {
1529 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1530 }
1531 #endif
1532
1533 /* prtyw: PowerPC 2.05 specification */
1534 static void gen_prtyw(DisasContext *ctx)
1535 {
1536 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1537 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1538 TCGv t0 = tcg_temp_new();
1539 tcg_gen_shri_tl(t0, rs, 16);
1540 tcg_gen_xor_tl(ra, rs, t0);
1541 tcg_gen_shri_tl(t0, ra, 8);
1542 tcg_gen_xor_tl(ra, ra, t0);
1543 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1544 tcg_temp_free(t0);
1545 }
1546
1547 #if defined(TARGET_PPC64)
1548 /* prtyd: PowerPC 2.05 specification */
1549 static void gen_prtyd(DisasContext *ctx)
1550 {
1551 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1552 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1553 TCGv t0 = tcg_temp_new();
1554 tcg_gen_shri_tl(t0, rs, 32);
1555 tcg_gen_xor_tl(ra, rs, t0);
1556 tcg_gen_shri_tl(t0, ra, 16);
1557 tcg_gen_xor_tl(ra, ra, t0);
1558 tcg_gen_shri_tl(t0, ra, 8);
1559 tcg_gen_xor_tl(ra, ra, t0);
1560 tcg_gen_andi_tl(ra, ra, 1);
1561 tcg_temp_free(t0);
1562 }
1563 #endif
1564
1565 #if defined(TARGET_PPC64)
1566 /* bpermd */
1567 static void gen_bpermd(DisasContext *ctx)
1568 {
1569 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1570 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1571 }
1572 #endif
1573
1574 #if defined(TARGET_PPC64)
1575 /* extsw & extsw. */
1576 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1577
1578 /* cntlzd */
1579 static void gen_cntlzd(DisasContext *ctx)
1580 {
1581 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1582 if (unlikely(Rc(ctx->opcode) != 0))
1583 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1584 }
1585 #endif
1586
1587 /*** Integer rotate ***/
1588
1589 /* rlwimi & rlwimi. */
1590 static void gen_rlwimi(DisasContext *ctx)
1591 {
1592 uint32_t mb, me, sh;
1593
1594 mb = MB(ctx->opcode);
1595 me = ME(ctx->opcode);
1596 sh = SH(ctx->opcode);
1597 if (likely(sh == 0 && mb == 0 && me == 31)) {
1598 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1599 } else {
1600 target_ulong mask;
1601 TCGv t1;
1602 TCGv t0 = tcg_temp_new();
1603 #if defined(TARGET_PPC64)
1604 TCGv_i32 t2 = tcg_temp_new_i32();
1605 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1606 tcg_gen_rotli_i32(t2, t2, sh);
1607 tcg_gen_extu_i32_i64(t0, t2);
1608 tcg_temp_free_i32(t2);
1609 #else
1610 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1611 #endif
1612 #if defined(TARGET_PPC64)
1613 mb += 32;
1614 me += 32;
1615 #endif
1616 mask = MASK(mb, me);
1617 t1 = tcg_temp_new();
1618 tcg_gen_andi_tl(t0, t0, mask);
1619 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1620 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1621 tcg_temp_free(t0);
1622 tcg_temp_free(t1);
1623 }
1624 if (unlikely(Rc(ctx->opcode) != 0))
1625 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1626 }
1627
1628 /* rlwinm & rlwinm. */
1629 static void gen_rlwinm(DisasContext *ctx)
1630 {
1631 uint32_t mb, me, sh;
1632
1633 sh = SH(ctx->opcode);
1634 mb = MB(ctx->opcode);
1635 me = ME(ctx->opcode);
1636
1637 if (likely(mb == 0 && me == (31 - sh))) {
1638 if (likely(sh == 0)) {
1639 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1640 } else {
1641 TCGv t0 = tcg_temp_new();
1642 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1643 tcg_gen_shli_tl(t0, t0, sh);
1644 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1645 tcg_temp_free(t0);
1646 }
1647 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1648 TCGv t0 = tcg_temp_new();
1649 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1650 tcg_gen_shri_tl(t0, t0, mb);
1651 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1652 tcg_temp_free(t0);
1653 } else {
1654 TCGv t0 = tcg_temp_new();
1655 #if defined(TARGET_PPC64)
1656 TCGv_i32 t1 = tcg_temp_new_i32();
1657 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1658 tcg_gen_rotli_i32(t1, t1, sh);
1659 tcg_gen_extu_i32_i64(t0, t1);
1660 tcg_temp_free_i32(t1);
1661 #else
1662 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1663 #endif
1664 #if defined(TARGET_PPC64)
1665 mb += 32;
1666 me += 32;
1667 #endif
1668 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1669 tcg_temp_free(t0);
1670 }
1671 if (unlikely(Rc(ctx->opcode) != 0))
1672 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1673 }
1674
1675 /* rlwnm & rlwnm. */
1676 static void gen_rlwnm(DisasContext *ctx)
1677 {
1678 uint32_t mb, me;
1679 TCGv t0;
1680 #if defined(TARGET_PPC64)
1681 TCGv_i32 t1, t2;
1682 #endif
1683
1684 mb = MB(ctx->opcode);
1685 me = ME(ctx->opcode);
1686 t0 = tcg_temp_new();
1687 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1688 #if defined(TARGET_PPC64)
1689 t1 = tcg_temp_new_i32();
1690 t2 = tcg_temp_new_i32();
1691 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1692 tcg_gen_trunc_i64_i32(t2, t0);
1693 tcg_gen_rotl_i32(t1, t1, t2);
1694 tcg_gen_extu_i32_i64(t0, t1);
1695 tcg_temp_free_i32(t1);
1696 tcg_temp_free_i32(t2);
1697 #else
1698 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1699 #endif
1700 if (unlikely(mb != 0 || me != 31)) {
1701 #if defined(TARGET_PPC64)
1702 mb += 32;
1703 me += 32;
1704 #endif
1705 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1706 } else {
1707 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1708 }
1709 tcg_temp_free(t0);
1710 if (unlikely(Rc(ctx->opcode) != 0))
1711 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1712 }
1713
1714 #if defined(TARGET_PPC64)
1715 #define GEN_PPC64_R2(name, opc1, opc2) \
1716 static void glue(gen_, name##0)(DisasContext *ctx) \
1717 { \
1718 gen_##name(ctx, 0); \
1719 } \
1720 \
1721 static void glue(gen_, name##1)(DisasContext *ctx) \
1722 { \
1723 gen_##name(ctx, 1); \
1724 }
1725 #define GEN_PPC64_R4(name, opc1, opc2) \
1726 static void glue(gen_, name##0)(DisasContext *ctx) \
1727 { \
1728 gen_##name(ctx, 0, 0); \
1729 } \
1730 \
1731 static void glue(gen_, name##1)(DisasContext *ctx) \
1732 { \
1733 gen_##name(ctx, 0, 1); \
1734 } \
1735 \
1736 static void glue(gen_, name##2)(DisasContext *ctx) \
1737 { \
1738 gen_##name(ctx, 1, 0); \
1739 } \
1740 \
1741 static void glue(gen_, name##3)(DisasContext *ctx) \
1742 { \
1743 gen_##name(ctx, 1, 1); \
1744 }
1745
1746 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1747 uint32_t sh)
1748 {
1749 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1750 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1751 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1752 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1753 } else {
1754 TCGv t0 = tcg_temp_new();
1755 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1756 if (likely(mb == 0 && me == 63)) {
1757 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1758 } else {
1759 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1760 }
1761 tcg_temp_free(t0);
1762 }
1763 if (unlikely(Rc(ctx->opcode) != 0))
1764 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1765 }
1766 /* rldicl - rldicl. */
1767 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1768 {
1769 uint32_t sh, mb;
1770
1771 sh = SH(ctx->opcode) | (shn << 5);
1772 mb = MB(ctx->opcode) | (mbn << 5);
1773 gen_rldinm(ctx, mb, 63, sh);
1774 }
1775 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1776 /* rldicr - rldicr. */
1777 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1778 {
1779 uint32_t sh, me;
1780
1781 sh = SH(ctx->opcode) | (shn << 5);
1782 me = MB(ctx->opcode) | (men << 5);
1783 gen_rldinm(ctx, 0, me, sh);
1784 }
1785 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1786 /* rldic - rldic. */
1787 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1788 {
1789 uint32_t sh, mb;
1790
1791 sh = SH(ctx->opcode) | (shn << 5);
1792 mb = MB(ctx->opcode) | (mbn << 5);
1793 gen_rldinm(ctx, mb, 63 - sh, sh);
1794 }
1795 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1796
1797 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1798 {
1799 TCGv t0;
1800
1801 t0 = tcg_temp_new();
1802 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1803 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1804 if (unlikely(mb != 0 || me != 63)) {
1805 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1806 } else {
1807 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1808 }
1809 tcg_temp_free(t0);
1810 if (unlikely(Rc(ctx->opcode) != 0))
1811 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1812 }
1813
1814 /* rldcl - rldcl. */
1815 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1816 {
1817 uint32_t mb;
1818
1819 mb = MB(ctx->opcode) | (mbn << 5);
1820 gen_rldnm(ctx, mb, 63);
1821 }
1822 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1823 /* rldcr - rldcr. */
1824 static inline void gen_rldcr(DisasContext *ctx, int men)
1825 {
1826 uint32_t me;
1827
1828 me = MB(ctx->opcode) | (men << 5);
1829 gen_rldnm(ctx, 0, me);
1830 }
1831 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1832 /* rldimi - rldimi. */
1833 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1834 {
1835 uint32_t sh, mb, me;
1836
1837 sh = SH(ctx->opcode) | (shn << 5);
1838 mb = MB(ctx->opcode) | (mbn << 5);
1839 me = 63 - sh;
1840 if (unlikely(sh == 0 && mb == 0)) {
1841 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1842 } else {
1843 TCGv t0, t1;
1844 target_ulong mask;
1845
1846 t0 = tcg_temp_new();
1847 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1848 t1 = tcg_temp_new();
1849 mask = MASK(mb, me);
1850 tcg_gen_andi_tl(t0, t0, mask);
1851 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1852 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1853 tcg_temp_free(t0);
1854 tcg_temp_free(t1);
1855 }
1856 if (unlikely(Rc(ctx->opcode) != 0))
1857 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1858 }
1859 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1860 #endif
1861
1862 /*** Integer shift ***/
1863
1864 /* slw & slw. */
1865 static void gen_slw(DisasContext *ctx)
1866 {
1867 TCGv t0, t1;
1868
1869 t0 = tcg_temp_new();
1870 /* AND rS with a mask that is 0 when rB >= 0x20 */
1871 #if defined(TARGET_PPC64)
1872 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1873 tcg_gen_sari_tl(t0, t0, 0x3f);
1874 #else
1875 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1876 tcg_gen_sari_tl(t0, t0, 0x1f);
1877 #endif
1878 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1879 t1 = tcg_temp_new();
1880 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1881 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1882 tcg_temp_free(t1);
1883 tcg_temp_free(t0);
1884 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1885 if (unlikely(Rc(ctx->opcode) != 0))
1886 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1887 }
1888
1889 /* sraw & sraw. */
1890 static void gen_sraw(DisasContext *ctx)
1891 {
1892 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1893 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1894 if (unlikely(Rc(ctx->opcode) != 0))
1895 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1896 }
1897
1898 /* srawi & srawi. */
1899 static void gen_srawi(DisasContext *ctx)
1900 {
1901 int sh = SH(ctx->opcode);
1902 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1903 TCGv src = cpu_gpr[rS(ctx->opcode)];
1904 if (sh == 0) {
1905 tcg_gen_mov_tl(dst, src);
1906 tcg_gen_movi_tl(cpu_ca, 0);
1907 } else {
1908 TCGv t0;
1909 tcg_gen_ext32s_tl(dst, src);
1910 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1911 t0 = tcg_temp_new();
1912 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1913 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1914 tcg_temp_free(t0);
1915 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1916 tcg_gen_sari_tl(dst, dst, sh);
1917 }
1918 if (unlikely(Rc(ctx->opcode) != 0)) {
1919 gen_set_Rc0(ctx, dst);
1920 }
1921 }
1922
1923 /* srw & srw. */
1924 static void gen_srw(DisasContext *ctx)
1925 {
1926 TCGv t0, t1;
1927
1928 t0 = tcg_temp_new();
1929 /* AND rS with a mask that is 0 when rB >= 0x20 */
1930 #if defined(TARGET_PPC64)
1931 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1932 tcg_gen_sari_tl(t0, t0, 0x3f);
1933 #else
1934 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1935 tcg_gen_sari_tl(t0, t0, 0x1f);
1936 #endif
1937 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1938 tcg_gen_ext32u_tl(t0, t0);
1939 t1 = tcg_temp_new();
1940 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1941 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1942 tcg_temp_free(t1);
1943 tcg_temp_free(t0);
1944 if (unlikely(Rc(ctx->opcode) != 0))
1945 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1946 }
1947
1948 #if defined(TARGET_PPC64)
1949 /* sld & sld. */
1950 static void gen_sld(DisasContext *ctx)
1951 {
1952 TCGv t0, t1;
1953
1954 t0 = tcg_temp_new();
1955 /* AND rS with a mask that is 0 when rB >= 0x40 */
1956 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1957 tcg_gen_sari_tl(t0, t0, 0x3f);
1958 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1959 t1 = tcg_temp_new();
1960 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1961 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1962 tcg_temp_free(t1);
1963 tcg_temp_free(t0);
1964 if (unlikely(Rc(ctx->opcode) != 0))
1965 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1966 }
1967
1968 /* srad & srad. */
1969 static void gen_srad(DisasContext *ctx)
1970 {
1971 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1972 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1973 if (unlikely(Rc(ctx->opcode) != 0))
1974 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1975 }
1976 /* sradi & sradi. */
1977 static inline void gen_sradi(DisasContext *ctx, int n)
1978 {
1979 int sh = SH(ctx->opcode) + (n << 5);
1980 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1981 TCGv src = cpu_gpr[rS(ctx->opcode)];
1982 if (sh == 0) {
1983 tcg_gen_mov_tl(dst, src);
1984 tcg_gen_movi_tl(cpu_ca, 0);
1985 } else {
1986 TCGv t0;
1987 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1988 t0 = tcg_temp_new();
1989 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1990 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1991 tcg_temp_free(t0);
1992 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1993 tcg_gen_sari_tl(dst, src, sh);
1994 }
1995 if (unlikely(Rc(ctx->opcode) != 0)) {
1996 gen_set_Rc0(ctx, dst);
1997 }
1998 }
1999
2000 static void gen_sradi0(DisasContext *ctx)
2001 {
2002 gen_sradi(ctx, 0);
2003 }
2004
2005 static void gen_sradi1(DisasContext *ctx)
2006 {
2007 gen_sradi(ctx, 1);
2008 }
2009
2010 /* srd & srd. */
2011 static void gen_srd(DisasContext *ctx)
2012 {
2013 TCGv t0, t1;
2014
2015 t0 = tcg_temp_new();
2016 /* AND rS with a mask that is 0 when rB >= 0x40 */
2017 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2018 tcg_gen_sari_tl(t0, t0, 0x3f);
2019 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2020 t1 = tcg_temp_new();
2021 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2022 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2023 tcg_temp_free(t1);
2024 tcg_temp_free(t0);
2025 if (unlikely(Rc(ctx->opcode) != 0))
2026 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2027 }
2028 #endif
2029
2030 /*** Floating-Point arithmetic ***/
2031 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2032 static void gen_f##name(DisasContext *ctx) \
2033 { \
2034 if (unlikely(!ctx->fpu_enabled)) { \
2035 gen_exception(ctx, POWERPC_EXCP_FPU); \
2036 return; \
2037 } \
2038 /* NIP cannot be restored if the memory exception comes from an helper */ \
2039 gen_update_nip(ctx, ctx->nip - 4); \
2040 gen_reset_fpstatus(); \
2041 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2042 cpu_fpr[rA(ctx->opcode)], \
2043 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2044 if (isfloat) { \
2045 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2046 cpu_fpr[rD(ctx->opcode)]); \
2047 } \
2048 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2049 Rc(ctx->opcode) != 0); \
2050 }
2051
2052 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2053 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2054 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2055
2056 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2057 static void gen_f##name(DisasContext *ctx) \
2058 { \
2059 if (unlikely(!ctx->fpu_enabled)) { \
2060 gen_exception(ctx, POWERPC_EXCP_FPU); \
2061 return; \
2062 } \
2063 /* NIP cannot be restored if the memory exception comes from an helper */ \
2064 gen_update_nip(ctx, ctx->nip - 4); \
2065 gen_reset_fpstatus(); \
2066 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2067 cpu_fpr[rA(ctx->opcode)], \
2068 cpu_fpr[rB(ctx->opcode)]); \
2069 if (isfloat) { \
2070 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2071 cpu_fpr[rD(ctx->opcode)]); \
2072 } \
2073 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2074 set_fprf, Rc(ctx->opcode) != 0); \
2075 }
2076 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2077 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2078 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2079
2080 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2081 static void gen_f##name(DisasContext *ctx) \
2082 { \
2083 if (unlikely(!ctx->fpu_enabled)) { \
2084 gen_exception(ctx, POWERPC_EXCP_FPU); \
2085 return; \
2086 } \
2087 /* NIP cannot be restored if the memory exception comes from an helper */ \
2088 gen_update_nip(ctx, ctx->nip - 4); \
2089 gen_reset_fpstatus(); \
2090 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2091 cpu_fpr[rA(ctx->opcode)], \
2092 cpu_fpr[rC(ctx->opcode)]); \
2093 if (isfloat) { \
2094 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2095 cpu_fpr[rD(ctx->opcode)]); \
2096 } \
2097 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2098 set_fprf, Rc(ctx->opcode) != 0); \
2099 }
2100 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2101 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2102 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2103
2104 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2105 static void gen_f##name(DisasContext *ctx) \
2106 { \
2107 if (unlikely(!ctx->fpu_enabled)) { \
2108 gen_exception(ctx, POWERPC_EXCP_FPU); \
2109 return; \
2110 } \
2111 /* NIP cannot be restored if the memory exception comes from an helper */ \
2112 gen_update_nip(ctx, ctx->nip - 4); \
2113 gen_reset_fpstatus(); \
2114 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2115 cpu_fpr[rB(ctx->opcode)]); \
2116 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2117 set_fprf, Rc(ctx->opcode) != 0); \
2118 }
2119
2120 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2121 static void gen_f##name(DisasContext *ctx) \
2122 { \
2123 if (unlikely(!ctx->fpu_enabled)) { \
2124 gen_exception(ctx, POWERPC_EXCP_FPU); \
2125 return; \
2126 } \
2127 /* NIP cannot be restored if the memory exception comes from an helper */ \
2128 gen_update_nip(ctx, ctx->nip - 4); \
2129 gen_reset_fpstatus(); \
2130 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2131 cpu_fpr[rB(ctx->opcode)]); \
2132 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2133 set_fprf, Rc(ctx->opcode) != 0); \
2134 }
2135
2136 /* fadd - fadds */
2137 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2138 /* fdiv - fdivs */
2139 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2140 /* fmul - fmuls */
2141 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2142
2143 /* fre */
2144 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2145
2146 /* fres */
2147 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2148
2149 /* frsqrte */
2150 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2151
2152 /* frsqrtes */
2153 static void gen_frsqrtes(DisasContext *ctx)
2154 {
2155 if (unlikely(!ctx->fpu_enabled)) {
2156 gen_exception(ctx, POWERPC_EXCP_FPU);
2157 return;
2158 }
2159 /* NIP cannot be restored if the memory exception comes from an helper */
2160 gen_update_nip(ctx, ctx->nip - 4);
2161 gen_reset_fpstatus();
2162 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2163 cpu_fpr[rB(ctx->opcode)]);
2164 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2165 cpu_fpr[rD(ctx->opcode)]);
2166 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2167 }
2168
2169 /* fsel */
2170 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2171 /* fsub - fsubs */
2172 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2173 /* Optional: */
2174
2175 /* fsqrt */
2176 static void gen_fsqrt(DisasContext *ctx)
2177 {
2178 if (unlikely(!ctx->fpu_enabled)) {
2179 gen_exception(ctx, POWERPC_EXCP_FPU);
2180 return;
2181 }
2182 /* NIP cannot be restored if the memory exception comes from an helper */
2183 gen_update_nip(ctx, ctx->nip - 4);
2184 gen_reset_fpstatus();
2185 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2186 cpu_fpr[rB(ctx->opcode)]);
2187 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2188 }
2189
2190 static void gen_fsqrts(DisasContext *ctx)
2191 {
2192 if (unlikely(!ctx->fpu_enabled)) {
2193 gen_exception(ctx, POWERPC_EXCP_FPU);
2194 return;
2195 }
2196 /* NIP cannot be restored if the memory exception comes from an helper */
2197 gen_update_nip(ctx, ctx->nip - 4);
2198 gen_reset_fpstatus();
2199 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2200 cpu_fpr[rB(ctx->opcode)]);
2201 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2202 cpu_fpr[rD(ctx->opcode)]);
2203 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2204 }
2205
2206 /*** Floating-Point multiply-and-add ***/
2207 /* fmadd - fmadds */
2208 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2209 /* fmsub - fmsubs */
2210 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2211 /* fnmadd - fnmadds */
2212 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2213 /* fnmsub - fnmsubs */
2214 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2215
2216 /*** Floating-Point round & convert ***/
2217 /* fctiw */
2218 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2219 /* fctiwu */
2220 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2221 /* fctiwz */
2222 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2223 /* fctiwuz */
2224 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2225 /* frsp */
2226 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2227 #if defined(TARGET_PPC64)
2228 /* fcfid */
2229 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2230 /* fcfids */
2231 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2232 /* fcfidu */
2233 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2234 /* fcfidus */
2235 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2236 /* fctid */
2237 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2238 /* fctidu */
2239 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2240 /* fctidz */
2241 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2242 /* fctidu */
2243 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2244 #endif
2245
2246 /* frin */
2247 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2248 /* friz */
2249 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2250 /* frip */
2251 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2252 /* frim */
2253 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2254
2255 static void gen_ftdiv(DisasContext *ctx)
2256 {
2257 if (unlikely(!ctx->fpu_enabled)) {
2258 gen_exception(ctx, POWERPC_EXCP_FPU);
2259 return;
2260 }
2261 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2262 cpu_fpr[rB(ctx->opcode)]);
2263 }
2264
2265 static void gen_ftsqrt(DisasContext *ctx)
2266 {
2267 if (unlikely(!ctx->fpu_enabled)) {
2268 gen_exception(ctx, POWERPC_EXCP_FPU);
2269 return;
2270 }
2271 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2272 }
2273
2274
2275
2276 /*** Floating-Point compare ***/
2277
2278 /* fcmpo */
2279 static void gen_fcmpo(DisasContext *ctx)
2280 {
2281 TCGv_i32 crf;
2282 if (unlikely(!ctx->fpu_enabled)) {
2283 gen_exception(ctx, POWERPC_EXCP_FPU);
2284 return;
2285 }
2286 /* NIP cannot be restored if the memory exception comes from an helper */
2287 gen_update_nip(ctx, ctx->nip - 4);
2288 gen_reset_fpstatus();
2289 crf = tcg_const_i32(crfD(ctx->opcode));
2290 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2291 cpu_fpr[rB(ctx->opcode)], crf);
2292 tcg_temp_free_i32(crf);
2293 gen_helper_float_check_status(cpu_env);
2294 }
2295
2296 /* fcmpu */
2297 static void gen_fcmpu(DisasContext *ctx)
2298 {
2299 TCGv_i32 crf;
2300 if (unlikely(!ctx->fpu_enabled)) {
2301 gen_exception(ctx, POWERPC_EXCP_FPU);
2302 return;
2303 }
2304 /* NIP cannot be restored if the memory exception comes from an helper */
2305 gen_update_nip(ctx, ctx->nip - 4);
2306 gen_reset_fpstatus();
2307 crf = tcg_const_i32(crfD(ctx->opcode));
2308 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2309 cpu_fpr[rB(ctx->opcode)], crf);
2310 tcg_temp_free_i32(crf);
2311 gen_helper_float_check_status(cpu_env);
2312 }
2313
2314 /*** Floating-point move ***/
2315 /* fabs */
2316 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2317 static void gen_fabs(DisasContext *ctx)
2318 {
2319 if (unlikely(!ctx->fpu_enabled)) {
2320 gen_exception(ctx, POWERPC_EXCP_FPU);
2321 return;
2322 }
2323 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2324 ~(1ULL << 63));
2325 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2326 }
2327
2328 /* fmr - fmr. */
2329 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2330 static void gen_fmr(DisasContext *ctx)
2331 {
2332 if (unlikely(!ctx->fpu_enabled)) {
2333 gen_exception(ctx, POWERPC_EXCP_FPU);
2334 return;
2335 }
2336 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2337 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2338 }
2339
2340 /* fnabs */
2341 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2342 static void gen_fnabs(DisasContext *ctx)
2343 {
2344 if (unlikely(!ctx->fpu_enabled)) {
2345 gen_exception(ctx, POWERPC_EXCP_FPU);
2346 return;
2347 }
2348 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2349 1ULL << 63);
2350 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2351 }
2352
2353 /* fneg */
2354 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2355 static void gen_fneg(DisasContext *ctx)
2356 {
2357 if (unlikely(!ctx->fpu_enabled)) {
2358 gen_exception(ctx, POWERPC_EXCP_FPU);
2359 return;
2360 }
2361 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2362 1ULL << 63);
2363 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2364 }
2365
2366 /* fcpsgn: PowerPC 2.05 specification */
2367 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2368 static void gen_fcpsgn(DisasContext *ctx)
2369 {
2370 if (unlikely(!ctx->fpu_enabled)) {
2371 gen_exception(ctx, POWERPC_EXCP_FPU);
2372 return;
2373 }
2374 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2375 cpu_fpr[rB(ctx->opcode)], 0, 63);
2376 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2377 }
2378
2379 static void gen_fmrgew(DisasContext *ctx)
2380 {
2381 TCGv_i64 b0;
2382 if (unlikely(!ctx->fpu_enabled)) {
2383 gen_exception(ctx, POWERPC_EXCP_FPU);
2384 return;
2385 }
2386 b0 = tcg_temp_new_i64();
2387 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2388 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2389 b0, 0, 32);
2390 tcg_temp_free_i64(b0);
2391 }
2392
2393 static void gen_fmrgow(DisasContext *ctx)
2394 {
2395 if (unlikely(!ctx->fpu_enabled)) {
2396 gen_exception(ctx, POWERPC_EXCP_FPU);
2397 return;
2398 }
2399 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2400 cpu_fpr[rB(ctx->opcode)],
2401 cpu_fpr[rA(ctx->opcode)],
2402 32, 32);
2403 }
2404
2405 /*** Floating-Point status & ctrl register ***/
2406
2407 /* mcrfs */
2408 static void gen_mcrfs(DisasContext *ctx)
2409 {
2410 TCGv tmp = tcg_temp_new();
2411 int bfa;
2412
2413 if (unlikely(!ctx->fpu_enabled)) {
2414 gen_exception(ctx, POWERPC_EXCP_FPU);
2415 return;
2416 }
2417 bfa = 4 * (7 - crfS(ctx->opcode));
2418 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2419 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2420 tcg_temp_free(tmp);
2421 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2422 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2423 }
2424
2425 /* mffs */
2426 static void gen_mffs(DisasContext *ctx)
2427 {
2428 if (unlikely(!ctx->fpu_enabled)) {
2429 gen_exception(ctx, POWERPC_EXCP_FPU);
2430 return;
2431 }
2432 gen_reset_fpstatus();
2433 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2434 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2435 }
2436
2437 /* mtfsb0 */
2438 static void gen_mtfsb0(DisasContext *ctx)
2439 {
2440 uint8_t crb;
2441
2442 if (unlikely(!ctx->fpu_enabled)) {
2443 gen_exception(ctx, POWERPC_EXCP_FPU);
2444 return;
2445 }
2446 crb = 31 - crbD(ctx->opcode);
2447 gen_reset_fpstatus();
2448 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2449 TCGv_i32 t0;
2450 /* NIP cannot be restored if the memory exception comes from an helper */
2451 gen_update_nip(ctx, ctx->nip - 4);
2452 t0 = tcg_const_i32(crb);
2453 gen_helper_fpscr_clrbit(cpu_env, t0);
2454 tcg_temp_free_i32(t0);
2455 }
2456 if (unlikely(Rc(ctx->opcode) != 0)) {
2457 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2458 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2459 }
2460 }
2461
2462 /* mtfsb1 */
2463 static void gen_mtfsb1(DisasContext *ctx)
2464 {
2465 uint8_t crb;
2466
2467 if (unlikely(!ctx->fpu_enabled)) {
2468 gen_exception(ctx, POWERPC_EXCP_FPU);
2469 return;
2470 }
2471 crb = 31 - crbD(ctx->opcode);
2472 gen_reset_fpstatus();
2473 /* XXX: we pretend we can only do IEEE floating-point computations */
2474 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2475 TCGv_i32 t0;
2476 /* NIP cannot be restored if the memory exception comes from an helper */
2477 gen_update_nip(ctx, ctx->nip - 4);
2478 t0 = tcg_const_i32(crb);
2479 gen_helper_fpscr_setbit(cpu_env, t0);
2480 tcg_temp_free_i32(t0);
2481 }
2482 if (unlikely(Rc(ctx->opcode) != 0)) {
2483 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2484 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2485 }
2486 /* We can raise a differed exception */
2487 gen_helper_float_check_status(cpu_env);
2488 }
2489
2490 /* mtfsf */
2491 static void gen_mtfsf(DisasContext *ctx)
2492 {
2493 TCGv_i32 t0;
2494 int flm, l, w;
2495
2496 if (unlikely(!ctx->fpu_enabled)) {
2497 gen_exception(ctx, POWERPC_EXCP_FPU);
2498 return;
2499 }
2500 flm = FPFLM(ctx->opcode);
2501 l = FPL(ctx->opcode);
2502 w = FPW(ctx->opcode);
2503 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2504 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2505 return;
2506 }
2507 /* NIP cannot be restored if the memory exception comes from an helper */
2508 gen_update_nip(ctx, ctx->nip - 4);
2509 gen_reset_fpstatus();
2510 if (l) {
2511 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2512 } else {
2513 t0 = tcg_const_i32(flm << (w * 8));
2514 }
2515 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2516 tcg_temp_free_i32(t0);
2517 if (unlikely(Rc(ctx->opcode) != 0)) {
2518 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2519 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2520 }
2521 /* We can raise a differed exception */
2522 gen_helper_float_check_status(cpu_env);
2523 }
2524
2525 /* mtfsfi */
2526 static void gen_mtfsfi(DisasContext *ctx)
2527 {
2528 int bf, sh, w;
2529 TCGv_i64 t0;
2530 TCGv_i32 t1;
2531
2532 if (unlikely(!ctx->fpu_enabled)) {
2533 gen_exception(ctx, POWERPC_EXCP_FPU);
2534 return;
2535 }
2536 w = FPW(ctx->opcode);
2537 bf = FPBF(ctx->opcode);
2538 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2539 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2540 return;
2541 }
2542 sh = (8 * w) + 7 - bf;
2543 /* NIP cannot be restored if the memory exception comes from an helper */
2544 gen_update_nip(ctx, ctx->nip - 4);
2545 gen_reset_fpstatus();
2546 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2547 t1 = tcg_const_i32(1 << sh);
2548 gen_helper_store_fpscr(cpu_env, t0, t1);
2549 tcg_temp_free_i64(t0);
2550 tcg_temp_free_i32(t1);
2551 if (unlikely(Rc(ctx->opcode) != 0)) {
2552 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2553 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2554 }
2555 /* We can raise a differed exception */
2556 gen_helper_float_check_status(cpu_env);
2557 }
2558
2559 /*** Addressing modes ***/
2560 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2561 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2562 target_long maskl)
2563 {
2564 target_long simm = SIMM(ctx->opcode);
2565
2566 simm &= ~maskl;
2567 if (rA(ctx->opcode) == 0) {
2568 if (NARROW_MODE(ctx)) {
2569 simm = (uint32_t)simm;
2570 }
2571 tcg_gen_movi_tl(EA, simm);
2572 } else if (likely(simm != 0)) {
2573 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2574 if (NARROW_MODE(ctx)) {
2575 tcg_gen_ext32u_tl(EA, EA);
2576 }
2577 } else {
2578 if (NARROW_MODE(ctx)) {
2579 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2580 } else {
2581 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2582 }
2583 }
2584 }
2585
2586 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2587 {
2588 if (rA(ctx->opcode) == 0) {
2589 if (NARROW_MODE(ctx)) {
2590 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2591 } else {
2592 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2593 }
2594 } else {
2595 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2596 if (NARROW_MODE(ctx)) {
2597 tcg_gen_ext32u_tl(EA, EA);
2598 }
2599 }
2600 }
2601
2602 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2603 {
2604 if (rA(ctx->opcode) == 0) {
2605 tcg_gen_movi_tl(EA, 0);
2606 } else if (NARROW_MODE(ctx)) {
2607 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2608 } else {
2609 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2610 }
2611 }
2612
2613 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2614 target_long val)
2615 {
2616 tcg_gen_addi_tl(ret, arg1, val);
2617 if (NARROW_MODE(ctx)) {
2618 tcg_gen_ext32u_tl(ret, ret);
2619 }
2620 }
2621
2622 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2623 {
2624 int l1 = gen_new_label();
2625 TCGv t0 = tcg_temp_new();
2626 TCGv_i32 t1, t2;
2627 /* NIP cannot be restored if the memory exception comes from an helper */
2628 gen_update_nip(ctx, ctx->nip - 4);
2629 tcg_gen_andi_tl(t0, EA, mask);
2630 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2631 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2632 t2 = tcg_const_i32(0);
2633 gen_helper_raise_exception_err(cpu_env, t1, t2);
2634 tcg_temp_free_i32(t1);
2635 tcg_temp_free_i32(t2);
2636 gen_set_label(l1);
2637 tcg_temp_free(t0);
2638 }
2639
2640 /*** Integer load ***/
2641 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2642 {
2643 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2644 }
2645
2646 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2647 {
2648 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2649 }
2650
2651 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2652 {
2653 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2654 if (unlikely(ctx->le_mode)) {
2655 tcg_gen_bswap16_tl(arg1, arg1);
2656 }
2657 }
2658
2659 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2660 {
2661 if (unlikely(ctx->le_mode)) {
2662 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2663 tcg_gen_bswap16_tl(arg1, arg1);
2664 tcg_gen_ext16s_tl(arg1, arg1);
2665 } else {
2666 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2667 }
2668 }
2669
2670 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2671 {
2672 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2673 if (unlikely(ctx->le_mode)) {
2674 tcg_gen_bswap32_tl(arg1, arg1);
2675 }
2676 }
2677
2678 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2679 {
2680 TCGv tmp = tcg_temp_new();
2681 gen_qemu_ld32u(ctx, tmp, addr);
2682 tcg_gen_extu_tl_i64(val, tmp);
2683 tcg_temp_free(tmp);
2684 }
2685
2686 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2687 {
2688 if (unlikely(ctx->le_mode)) {
2689 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2690 tcg_gen_bswap32_tl(arg1, arg1);
2691 tcg_gen_ext32s_tl(arg1, arg1);
2692 } else
2693 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2694 }
2695
2696 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2697 {
2698 TCGv tmp = tcg_temp_new();
2699 gen_qemu_ld32s(ctx, tmp, addr);
2700 tcg_gen_ext_tl_i64(val, tmp);
2701 tcg_temp_free(tmp);
2702 }
2703
2704 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2705 {
2706 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2707 if (unlikely(ctx->le_mode)) {
2708 tcg_gen_bswap64_i64(arg1, arg1);
2709 }
2710 }
2711
2712 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2713 {
2714 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2715 }
2716
2717 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2718 {
2719 if (unlikely(ctx->le_mode)) {
2720 TCGv t0 = tcg_temp_new();
2721 tcg_gen_ext16u_tl(t0, arg1);
2722 tcg_gen_bswap16_tl(t0, t0);
2723 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2724 tcg_temp_free(t0);
2725 } else {
2726 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2727 }
2728 }
2729
2730 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2731 {
2732 if (unlikely(ctx->le_mode)) {
2733 TCGv t0 = tcg_temp_new();
2734 tcg_gen_ext32u_tl(t0, arg1);
2735 tcg_gen_bswap32_tl(t0, t0);
2736 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2737 tcg_temp_free(t0);
2738 } else {
2739 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2740 }
2741 }
2742
2743 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2744 {
2745 TCGv tmp = tcg_temp_new();
2746 tcg_gen_trunc_i64_tl(tmp, val);
2747 gen_qemu_st32(ctx, tmp, addr);
2748 tcg_temp_free(tmp);
2749 }
2750
2751 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2752 {
2753 if (unlikely(ctx->le_mode)) {
2754 TCGv_i64 t0 = tcg_temp_new_i64();
2755 tcg_gen_bswap64_i64(t0, arg1);
2756 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2757 tcg_temp_free_i64(t0);
2758 } else
2759 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2760 }
2761
2762 #define GEN_LD(name, ldop, opc, type) \
2763 static void glue(gen_, name)(DisasContext *ctx) \
2764 { \
2765 TCGv EA; \
2766 gen_set_access_type(ctx, ACCESS_INT); \
2767 EA = tcg_temp_new(); \
2768 gen_addr_imm_index(ctx, EA, 0); \
2769 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2770 tcg_temp_free(EA); \
2771 }
2772
2773 #define GEN_LDU(name, ldop, opc, type) \
2774 static void glue(gen_, name##u)(DisasContext *ctx) \
2775 { \
2776 TCGv EA; \
2777 if (unlikely(rA(ctx->opcode) == 0 || \
2778 rA(ctx->opcode) == rD(ctx->opcode))) { \
2779 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2780 return; \
2781 } \
2782 gen_set_access_type(ctx, ACCESS_INT); \
2783 EA = tcg_temp_new(); \
2784 if (type == PPC_64B) \
2785 gen_addr_imm_index(ctx, EA, 0x03); \
2786 else \
2787 gen_addr_imm_index(ctx, EA, 0); \
2788 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2789 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2790 tcg_temp_free(EA); \
2791 }
2792
2793 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2794 static void glue(gen_, name##ux)(DisasContext *ctx) \
2795 { \
2796 TCGv EA; \
2797 if (unlikely(rA(ctx->opcode) == 0 || \
2798 rA(ctx->opcode) == rD(ctx->opcode))) { \
2799 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2800 return; \
2801 } \
2802 gen_set_access_type(ctx, ACCESS_INT); \
2803 EA = tcg_temp_new(); \
2804 gen_addr_reg_index(ctx, EA); \
2805 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2806 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2807 tcg_temp_free(EA); \
2808 }
2809
2810 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2811 static void glue(gen_, name##x)(DisasContext *ctx) \
2812 { \
2813 TCGv EA; \
2814 gen_set_access_type(ctx, ACCESS_INT); \
2815 EA = tcg_temp_new(); \
2816 gen_addr_reg_index(ctx, EA); \
2817 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2818 tcg_temp_free(EA); \
2819 }
2820 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2821 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2822
2823 #define GEN_LDS(name, ldop, op, type) \
2824 GEN_LD(name, ldop, op | 0x20, type); \
2825 GEN_LDU(name, ldop, op | 0x21, type); \
2826 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2827 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2828
2829 /* lbz lbzu lbzux lbzx */
2830 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2831 /* lha lhau lhaux lhax */
2832 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2833 /* lhz lhzu lhzux lhzx */
2834 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2835 /* lwz lwzu lwzux lwzx */
2836 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2837 #if defined(TARGET_PPC64)
2838 /* lwaux */
2839 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2840 /* lwax */
2841 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2842 /* ldux */
2843 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2844 /* ldx */
2845 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2846
2847 static void gen_ld(DisasContext *ctx)
2848 {
2849 TCGv EA;
2850 if (Rc(ctx->opcode)) {
2851 if (unlikely(rA(ctx->opcode) == 0 ||
2852 rA(ctx->opcode) == rD(ctx->opcode))) {
2853 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2854 return;
2855 }
2856 }
2857 gen_set_access_type(ctx, ACCESS_INT);
2858 EA = tcg_temp_new();
2859 gen_addr_imm_index(ctx, EA, 0x03);
2860 if (ctx->opcode & 0x02) {
2861 /* lwa (lwau is undefined) */
2862 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2863 } else {
2864 /* ld - ldu */
2865 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2866 }
2867 if (Rc(ctx->opcode))
2868 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2869 tcg_temp_free(EA);
2870 }
2871
2872 /* lq */
2873 static void gen_lq(DisasContext *ctx)
2874 {
2875 int ra, rd;
2876 TCGv EA;
2877
2878 /* lq is a legal user mode instruction starting in ISA 2.07 */
2879 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2880 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2881
2882 if (!legal_in_user_mode && is_user_mode(ctx)) {
2883 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2884 return;
2885 }
2886
2887 if (!le_is_supported && ctx->le_mode) {
2888 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2889 return;
2890 }
2891
2892 ra = rA(ctx->opcode);
2893 rd = rD(ctx->opcode);
2894 if (unlikely((rd & 1) || rd == ra)) {
2895 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2896 return;
2897 }
2898
2899 gen_set_access_type(ctx, ACCESS_INT);
2900 EA = tcg_temp_new();
2901 gen_addr_imm_index(ctx, EA, 0x0F);
2902
2903 if (unlikely(ctx->le_mode)) {
2904 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2905 gen_addr_add(ctx, EA, EA, 8);
2906 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2907 } else {
2908 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2909 gen_addr_add(ctx, EA, EA, 8);
2910 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2911 }
2912 tcg_temp_free(EA);
2913 }
2914 #endif
2915
2916 /*** Integer store ***/
2917 #define GEN_ST(name, stop, opc, type) \
2918 static void glue(gen_, name)(DisasContext *ctx) \
2919 { \
2920 TCGv EA; \
2921 gen_set_access_type(ctx, ACCESS_INT); \
2922 EA = tcg_temp_new(); \
2923 gen_addr_imm_index(ctx, EA, 0); \
2924 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2925 tcg_temp_free(EA); \
2926 }
2927
2928 #define GEN_STU(name, stop, opc, type) \
2929 static void glue(gen_, stop##u)(DisasContext *ctx) \
2930 { \
2931 TCGv EA; \
2932 if (unlikely(rA(ctx->opcode) == 0)) { \
2933 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2934 return; \
2935 } \
2936 gen_set_access_type(ctx, ACCESS_INT); \
2937 EA = tcg_temp_new(); \
2938 if (type == PPC_64B) \
2939 gen_addr_imm_index(ctx, EA, 0x03); \
2940 else \
2941 gen_addr_imm_index(ctx, EA, 0); \
2942 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2943 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2944 tcg_temp_free(EA); \
2945 }
2946
2947 #define GEN_STUX(name, stop, opc2, opc3, type) \
2948 static void glue(gen_, name##ux)(DisasContext *ctx) \
2949 { \
2950 TCGv EA; \
2951 if (unlikely(rA(ctx->opcode) == 0)) { \
2952 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2953 return; \
2954 } \
2955 gen_set_access_type(ctx, ACCESS_INT); \
2956 EA = tcg_temp_new(); \
2957 gen_addr_reg_index(ctx, EA); \
2958 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2959 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2960 tcg_temp_free(EA); \
2961 }
2962
2963 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2964 static void glue(gen_, name##x)(DisasContext *ctx) \
2965 { \
2966 TCGv EA; \
2967 gen_set_access_type(ctx, ACCESS_INT); \
2968 EA = tcg_temp_new(); \
2969 gen_addr_reg_index(ctx, EA); \
2970 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2971 tcg_temp_free(EA); \
2972 }
2973 #define GEN_STX(name, stop, opc2, opc3, type) \
2974 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2975
2976 #define GEN_STS(name, stop, op, type) \
2977 GEN_ST(name, stop, op | 0x20, type); \
2978 GEN_STU(name, stop, op | 0x21, type); \
2979 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2980 GEN_STX(name, stop, 0x17, op | 0x00, type)
2981
2982 /* stb stbu stbux stbx */
2983 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2984 /* sth sthu sthux sthx */
2985 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2986 /* stw stwu stwux stwx */
2987 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2988 #if defined(TARGET_PPC64)
2989 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2990 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2991
2992 static void gen_std(DisasContext *ctx)
2993 {
2994 int rs;
2995 TCGv EA;
2996
2997 rs = rS(ctx->opcode);
2998 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2999
3000 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3001 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3002
3003 if (!legal_in_user_mode && is_user_mode(ctx)) {
3004 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3005 return;
3006 }
3007
3008 if (!le_is_supported && ctx->le_mode) {
3009 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3010 return;
3011 }
3012
3013 if (unlikely(rs & 1)) {
3014 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3015 return;
3016 }
3017 gen_set_access_type(ctx, ACCESS_INT);
3018 EA = tcg_temp_new();
3019 gen_addr_imm_index(ctx, EA, 0x03);
3020
3021 if (unlikely(ctx->le_mode)) {
3022 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3023 gen_addr_add(ctx, EA, EA, 8);
3024 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3025 } else {
3026 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3027 gen_addr_add(ctx, EA, EA, 8);
3028 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3029 }
3030 tcg_temp_free(EA);
3031 } else {
3032 /* std / stdu*/
3033 if (Rc(ctx->opcode)) {
3034 if (unlikely(rA(ctx->opcode) == 0)) {
3035 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3036 return;
3037 }
3038 }
3039 gen_set_access_type(ctx, ACCESS_INT);
3040 EA = tcg_temp_new();
3041 gen_addr_imm_index(ctx, EA, 0x03);
3042 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3043 if (Rc(ctx->opcode))
3044 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3045 tcg_temp_free(EA);
3046 }
3047 }
3048 #endif
3049 /*** Integer load and store with byte reverse ***/
3050 /* lhbrx */
3051 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3052 {
3053 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
3054 if (likely(!ctx->le_mode)) {
3055 tcg_gen_bswap16_tl(arg1, arg1);
3056 }
3057 }
3058 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3059
3060 /* lwbrx */
3061 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3062 {
3063 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
3064 if (likely(!ctx->le_mode)) {
3065 tcg_gen_bswap32_tl(arg1, arg1);
3066 }
3067 }
3068 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3069
3070 #if defined(TARGET_PPC64)
3071 /* ldbrx */
3072 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3073 {
3074 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
3075 if (likely(!ctx->le_mode)) {
3076 tcg_gen_bswap64_tl(arg1, arg1);
3077 }
3078 }
3079 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3080 #endif /* TARGET_PPC64 */
3081
3082 /* sthbrx */
3083 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3084 {
3085 if (likely(!ctx->le_mode)) {
3086 TCGv t0 = tcg_temp_new();
3087 tcg_gen_ext16u_tl(t0, arg1);
3088 tcg_gen_bswap16_tl(t0, t0);
3089 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3090 tcg_temp_free(t0);
3091 } else {
3092 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3093 }
3094 }
3095 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3096
3097 /* stwbrx */
3098 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3099 {
3100 if (likely(!ctx->le_mode)) {
3101 TCGv t0 = tcg_temp_new();
3102 tcg_gen_ext32u_tl(t0, arg1);
3103 tcg_gen_bswap32_tl(t0, t0);
3104 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3105 tcg_temp_free(t0);
3106 } else {
3107 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3108 }
3109 }
3110 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3111
3112 #if defined(TARGET_PPC64)
3113 /* stdbrx */
3114 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3115 {
3116 if (likely(!ctx->le_mode)) {
3117 TCGv t0 = tcg_temp_new();
3118 tcg_gen_bswap64_tl(t0, arg1);
3119 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
3120 tcg_temp_free(t0);
3121 } else {
3122 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
3123 }
3124 }
3125 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3126 #endif /* TARGET_PPC64 */
3127
3128 /*** Integer load and store multiple ***/
3129
3130 /* lmw */
3131 static void gen_lmw(DisasContext *ctx)
3132 {
3133 TCGv t0;
3134 TCGv_i32 t1;
3135 gen_set_access_type(ctx, ACCESS_INT);
3136 /* NIP cannot be restored if the memory exception comes from an helper */
3137 gen_update_nip(ctx, ctx->nip - 4);
3138 t0 = tcg_temp_new();
3139 t1 = tcg_const_i32(rD(ctx->opcode));
3140 gen_addr_imm_index(ctx, t0, 0);
3141 gen_helper_lmw(cpu_env, t0, t1);
3142 tcg_temp_free(t0);
3143 tcg_temp_free_i32(t1);
3144 }
3145
3146 /* stmw */
3147 static void gen_stmw(DisasContext *ctx)
3148 {
3149 TCGv t0;
3150 TCGv_i32 t1;
3151 gen_set_access_type(ctx, ACCESS_INT);
3152 /* NIP cannot be restored if the memory exception comes from an helper */
3153 gen_update_nip(ctx, ctx->nip - 4);
3154 t0 = tcg_temp_new();
3155 t1 = tcg_const_i32(rS(ctx->opcode));
3156 gen_addr_imm_index(ctx, t0, 0);
3157 gen_helper_stmw(cpu_env, t0, t1);
3158 tcg_temp_free(t0);
3159 tcg_temp_free_i32(t1);
3160 }
3161
3162 /*** Integer load and store strings ***/
3163
3164 /* lswi */
3165 /* PowerPC32 specification says we must generate an exception if
3166 * rA is in the range of registers to be loaded.
3167 * In an other hand, IBM says this is valid, but rA won't be loaded.
3168 * For now, I'll follow the spec...
3169 */
3170 static void gen_lswi(DisasContext *ctx)
3171 {
3172 TCGv t0;
3173 TCGv_i32 t1, t2;
3174 int nb = NB(ctx->opcode);
3175 int start = rD(ctx->opcode);
3176 int ra = rA(ctx->opcode);
3177 int nr;
3178
3179 if (nb == 0)
3180 nb = 32;
3181 nr = nb / 4;
3182 if (unlikely(((start + nr) > 32 &&
3183 start <= ra && (start + nr - 32) > ra) ||
3184 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3185 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3186 return;
3187 }
3188 gen_set_access_type(ctx, ACCESS_INT);
3189 /* NIP cannot be restored if the memory exception comes from an helper */
3190 gen_update_nip(ctx, ctx->nip - 4);
3191 t0 = tcg_temp_new();
3192 gen_addr_register(ctx, t0);
3193 t1 = tcg_const_i32(nb);
3194 t2 = tcg_const_i32(start);
3195 gen_helper_lsw(cpu_env, t0, t1, t2);
3196 tcg_temp_free(t0);
3197 tcg_temp_free_i32(t1);
3198 tcg_temp_free_i32(t2);
3199 }
3200
3201 /* lswx */
3202 static void gen_lswx(DisasContext *ctx)
3203 {
3204 TCGv t0;
3205 TCGv_i32 t1, t2, t3;
3206 gen_set_access_type(ctx, ACCESS_INT);
3207 /* NIP cannot be restored if the memory exception comes from an helper */
3208 gen_update_nip(ctx, ctx->nip - 4);
3209 t0 = tcg_temp_new();
3210 gen_addr_reg_index(ctx, t0);
3211 t1 = tcg_const_i32(rD(ctx->opcode));
3212 t2 = tcg_const_i32(rA(ctx->opcode));
3213 t3 = tcg_const_i32(rB(ctx->opcode));
3214 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3215 tcg_temp_free(t0);
3216 tcg_temp_free_i32(t1);
3217 tcg_temp_free_i32(t2);
3218 tcg_temp_free_i32(t3);
3219 }
3220
3221 /* stswi */
3222 static void gen_stswi(DisasContext *ctx)
3223 {
3224 TCGv t0;
3225 TCGv_i32 t1, t2;
3226 int nb = NB(ctx->opcode);
3227 gen_set_access_type(ctx, ACCESS_INT);
3228 /* NIP cannot be restored if the memory exception comes from an helper */
3229 gen_update_nip(ctx, ctx->nip - 4);
3230 t0 = tcg_temp_new();
3231 gen_addr_register(ctx, t0);
3232 if (nb == 0)
3233 nb = 32;
3234 t1 = tcg_const_i32(nb);
3235 t2 = tcg_const_i32(rS(ctx->opcode));
3236 gen_helper_stsw(cpu_env, t0, t1, t2);
3237 tcg_temp_free(t0);
3238 tcg_temp_free_i32(t1);
3239 tcg_temp_free_i32(t2);
3240 }
3241
3242 /* stswx */
3243 static void gen_stswx(DisasContext *ctx)
3244 {
3245 TCGv t0;
3246 TCGv_i32 t1, t2;
3247 gen_set_access_type(ctx, ACCESS_INT);
3248 /* NIP cannot be restored if the memory exception comes from an helper */
3249 gen_update_nip(ctx, ctx->nip - 4);
3250 t0 = tcg_temp_new();
3251 gen_addr_reg_index(ctx, t0);
3252 t1 = tcg_temp_new_i32();
3253 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3254 tcg_gen_andi_i32(t1, t1, 0x7F);
3255 t2 = tcg_const_i32(rS(ctx->opcode));
3256 gen_helper_stsw(cpu_env, t0, t1, t2);
3257 tcg_temp_free(t0);
3258 tcg_temp_free_i32(t1);
3259 tcg_temp_free_i32(t2);
3260 }
3261
3262 /*** Memory synchronisation ***/
3263 /* eieio */
3264 static void gen_eieio(DisasContext *ctx)
3265 {
3266 }
3267
3268 /* isync */
3269 static void gen_isync(DisasContext *ctx)
3270 {
3271 gen_stop_exception(ctx);
3272 }
3273
3274 #define LARX(name, len, loadop) \
3275 static void gen_##name(DisasContext *ctx) \
3276 { \
3277 TCGv t0; \
3278 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3279 gen_set_access_type(ctx, ACCESS_RES); \
3280 t0 = tcg_temp_local_new(); \
3281 gen_addr_reg_index(ctx, t0); \
3282 if ((len) > 1) { \
3283 gen_check_align(ctx, t0, (len)-1); \
3284 } \
3285 gen_qemu_##loadop(ctx, gpr, t0); \
3286 tcg_gen_mov_tl(cpu_reserve, t0); \
3287 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3288 tcg_temp_free(t0); \
3289 }
3290
3291 /* lwarx */
3292 LARX(lbarx, 1, ld8u);
3293 LARX(lharx, 2, ld16u);
3294 LARX(lwarx, 4, ld32u);
3295
3296
3297 #if defined(CONFIG_USER_ONLY)
3298 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3299 int reg, int size)
3300 {
3301 TCGv t0 = tcg_temp_new();
3302 uint32_t save_exception = ctx->exception;
3303
3304 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3305 tcg_gen_movi_tl(t0, (size << 5) | reg);
3306 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3307 tcg_temp_free(t0);
3308 gen_update_nip(ctx, ctx->nip-4);
3309 ctx->exception = POWERPC_EXCP_BRANCH;
3310 gen_exception(ctx, POWERPC_EXCP_STCX);
3311 ctx->exception = save_exception;
3312 }
3313 #else
3314 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3315 int reg, int size)
3316 {
3317 int l1;
3318
3319 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3320 l1 = gen_new_label();
3321 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3322 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3323 #if defined(TARGET_PPC64)
3324 if (size == 8) {
3325 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3326 } else
3327 #endif
3328 if (size == 4) {
3329 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3330 } else if (size == 2) {
3331 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3332 #if defined(TARGET_PPC64)
3333 } else if (size == 16) {
3334 TCGv gpr1, gpr2;
3335 if (unlikely(ctx->le_mode)) {
3336 gpr1 = cpu_gpr[reg+1];
3337 gpr2 = cpu_gpr[reg];
3338 } else {
3339 gpr1 = cpu_gpr[reg];
3340 gpr2 = cpu_gpr[reg+1];
3341 }
3342 gen_qemu_st64(ctx, gpr1, EA);
3343 gen_addr_add(ctx, EA, EA, 8);
3344 gen_qemu_st64(ctx, gpr2, EA);
3345 #endif
3346 } else {
3347 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3348 }
3349 gen_set_label(l1);
3350 tcg_gen_movi_tl(cpu_reserve, -1);
3351 }
3352 #endif
3353
3354 #define STCX(name, len) \
3355 static void gen_##name(DisasContext *ctx) \
3356 { \
3357 TCGv t0; \
3358 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3359 gen_inval_exception(ctx, \
3360 POWERPC_EXCP_INVAL_INVAL); \
3361 return; \
3362 } \
3363 gen_set_access_type(ctx, ACCESS_RES); \
3364 t0 = tcg_temp_local_new(); \
3365 gen_addr_reg_index(ctx, t0); \
3366 if (len > 1) { \
3367 gen_check_align(ctx, t0, (len)-1); \
3368 } \
3369 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3370 tcg_temp_free(t0); \
3371 }
3372
3373 STCX(stbcx_, 1);
3374 STCX(sthcx_, 2);
3375 STCX(stwcx_, 4);
3376
3377 #if defined(TARGET_PPC64)
3378 /* ldarx */
3379 LARX(ldarx, 8, ld64);
3380
3381 /* lqarx */
3382 static void gen_lqarx(DisasContext *ctx)
3383 {
3384 TCGv EA;
3385 int rd = rD(ctx->opcode);
3386 TCGv gpr1, gpr2;
3387
3388 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3389 (rd == rB(ctx->opcode)))) {
3390 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3391 return;
3392 }
3393
3394 gen_set_access_type(ctx, ACCESS_RES);
3395 EA = tcg_temp_local_new();
3396 gen_addr_reg_index(ctx, EA);
3397 gen_check_align(ctx, EA, 15);
3398 if (unlikely(ctx->le_mode)) {
3399 gpr1 = cpu_gpr[rd+1];
3400 gpr2 = cpu_gpr[rd];
3401 } else {
3402 gpr1 = cpu_gpr[rd];
3403 gpr2 = cpu_gpr[rd+1];
3404 }
3405 gen_qemu_ld64(ctx, gpr1, EA);
3406 tcg_gen_mov_tl(cpu_reserve, EA);
3407
3408 gen_addr_add(ctx, EA, EA, 8);
3409 gen_qemu_ld64(ctx, gpr2, EA);
3410
3411 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3412 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3413
3414 tcg_temp_free(EA);
3415 }
3416
3417 /* stdcx. */
3418 STCX(stdcx_, 8);
3419 STCX(stqcx_, 16);
3420 #endif /* defined(TARGET_PPC64) */
3421
3422 /* sync */
3423 static void gen_sync(DisasContext *ctx)
3424 {
3425 }
3426
3427 /* wait */
3428 static void gen_wait(DisasContext *ctx)
3429 {
3430 TCGv_i32 t0 = tcg_temp_new_i32();
3431 tcg_gen_st_i32(t0, cpu_env,
3432 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3433 tcg_temp_free_i32(t0);
3434 /* Stop translation, as the CPU is supposed to sleep from now */
3435 gen_exception_err(ctx, EXCP_HLT, 1);
3436 }
3437
3438 /*** Floating-point load ***/
3439 #define GEN_LDF(name, ldop, opc, type) \
3440 static void glue(gen_, name)(DisasContext *ctx) \
3441 { \
3442 TCGv EA; \
3443 if (unlikely(!ctx->fpu_enabled)) { \
3444 gen_exception(ctx, POWERPC_EXCP_FPU); \
3445 return; \
3446 } \
3447 gen_set_access_type(ctx, ACCESS_FLOAT); \
3448 EA = tcg_temp_new(); \
3449 gen_addr_imm_index(ctx, EA, 0); \
3450 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3451 tcg_temp_free(EA); \
3452 }
3453
3454 #define GEN_LDUF(name, ldop, opc, type) \
3455 static void glue(gen_, name##u)(DisasContext *ctx) \
3456 { \
3457 TCGv EA; \
3458 if (unlikely(!ctx->fpu_enabled)) { \
3459 gen_exception(ctx, POWERPC_EXCP_FPU); \
3460 return; \
3461 } \
3462 if (unlikely(rA(ctx->opcode) == 0)) { \
3463 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3464 return; \
3465 } \
3466 gen_set_access_type(ctx, ACCESS_FLOAT); \
3467 EA = tcg_temp_new(); \
3468 gen_addr_imm_index(ctx, EA, 0); \
3469 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3470 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3471 tcg_temp_free(EA); \
3472 }
3473
3474 #define GEN_LDUXF(name, ldop, opc, type) \
3475 static void glue(gen_, name##ux)(DisasContext *ctx) \
3476 { \
3477 TCGv EA; \
3478 if (unlikely(!ctx->fpu_enabled)) { \
3479 gen_exception(ctx, POWERPC_EXCP_FPU); \
3480 return; \
3481 } \
3482 if (unlikely(rA(ctx->opcode) == 0)) { \
3483 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3484 return; \
3485 } \
3486 gen_set_access_type(ctx, ACCESS_FLOAT); \
3487 EA = tcg_temp_new(); \
3488 gen_addr_reg_index(ctx, EA); \
3489 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3490 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3491 tcg_temp_free(EA); \
3492 }
3493
3494 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3495 static void glue(gen_, name##x)(DisasContext *ctx) \
3496 { \
3497 TCGv EA; \
3498 if (unlikely(!ctx->fpu_enabled)) { \
3499 gen_exception(ctx, POWERPC_EXCP_FPU); \
3500 return; \
3501 } \
3502 gen_set_access_type(ctx, ACCESS_FLOAT); \
3503 EA = tcg_temp_new(); \
3504 gen_addr_reg_index(ctx, EA); \
3505 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3506 tcg_temp_free(EA); \
3507 }
3508
3509 #define GEN_LDFS(name, ldop, op, type) \
3510 GEN_LDF(name, ldop, op | 0x20, type); \
3511 GEN_LDUF(name, ldop, op | 0x21, type); \
3512 GEN_LDUXF(name, ldop, op | 0x01, type); \
3513 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3514
3515 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3516 {
3517 TCGv t0 = tcg_temp_new();
3518 TCGv_i32 t1 = tcg_temp_new_i32();
3519 gen_qemu_ld32u(ctx, t0, arg2);
3520 tcg_gen_trunc_tl_i32(t1, t0);
3521 tcg_temp_free(t0);
3522 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3523 tcg_temp_free_i32(t1);
3524 }
3525
3526 /* lfd lfdu lfdux lfdx */
3527 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3528 /* lfs lfsu lfsux lfsx */
3529 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3530
3531 /* lfdp */
3532 static void gen_lfdp(DisasContext *ctx)
3533 {
3534 TCGv EA;
3535 if (unlikely(!ctx->fpu_enabled)) {
3536 gen_exception(ctx, POWERPC_EXCP_FPU);
3537 return;
3538 }
3539 gen_set_access_type(ctx, ACCESS_FLOAT);
3540 EA = tcg_temp_new();
3541 gen_addr_imm_index(ctx, EA, 0); \
3542 if (unlikely(ctx->le_mode)) {
3543 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3544 tcg_gen_addi_tl(EA, EA, 8);
3545 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3546 } else {
3547 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3548 tcg_gen_addi_tl(EA, EA, 8);
3549 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3550 }
3551 tcg_temp_free(EA);
3552 }
3553
3554 /* lfdpx */
3555 static void gen_lfdpx(DisasContext *ctx)
3556 {
3557 TCGv EA;
3558 if (unlikely(!ctx->fpu_enabled)) {
3559 gen_exception(ctx, POWERPC_EXCP_FPU);
3560 return;
3561 }
3562 gen_set_access_type(ctx, ACCESS_FLOAT);
3563 EA = tcg_temp_new();
3564 gen_addr_reg_index(ctx, EA);
3565 if (unlikely(ctx->le_mode)) {
3566 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3567 tcg_gen_addi_tl(EA, EA, 8);
3568 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3569 } else {
3570 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3571 tcg_gen_addi_tl(EA, EA, 8);
3572 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3573 }
3574 tcg_temp_free(EA);
3575 }
3576
3577 /* lfiwax */
3578 static void gen_lfiwax(DisasContext *ctx)
3579 {
3580 TCGv EA;
3581 TCGv t0;
3582 if (unlikely(!ctx->fpu_enabled)) {
3583 gen_exception(ctx, POWERPC_EXCP_FPU);
3584 return;
3585 }
3586 gen_set_access_type(ctx, ACCESS_FLOAT);
3587 EA = tcg_temp_new();
3588 t0 = tcg_temp_new();
3589 gen_addr_reg_index(ctx, EA);
3590 gen_qemu_ld32s(ctx, t0, EA);
3591 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3592 tcg_temp_free(EA);
3593 tcg_temp_free(t0);
3594 }
3595
3596 /* lfiwzx */
3597 static void gen_lfiwzx(DisasContext *ctx)
3598 {
3599 TCGv EA;
3600 if (unlikely(!ctx->fpu_enabled)) {
3601 gen_exception(ctx, POWERPC_EXCP_FPU);
3602 return;
3603 }
3604 gen_set_access_type(ctx, ACCESS_FLOAT);
3605 EA = tcg_temp_new();
3606 gen_addr_reg_index(ctx, EA);
3607 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3608 tcg_temp_free(EA);
3609 }
3610 /*** Floating-point store ***/
3611 #define GEN_STF(name, stop, opc, type) \
3612 static void glue(gen_, name)(DisasContext *ctx) \
3613 { \
3614 TCGv EA; \
3615 if (unlikely(!ctx->fpu_enabled)) { \
3616 gen_exception(ctx, POWERPC_EXCP_FPU); \
3617 return; \
3618 } \
3619 gen_set_access_type(ctx, ACCESS_FLOAT); \
3620 EA = tcg_temp_new(); \
3621 gen_addr_imm_index(ctx, EA, 0); \
3622 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3623 tcg_temp_free(EA); \
3624 }
3625
3626 #define GEN_STUF(name, stop, opc, type) \
3627 static void glue(gen_, name##u)(DisasContext *ctx) \
3628 { \
3629 TCGv EA; \
3630 if (unlikely(!ctx->fpu_enabled)) { \
3631 gen_exception(ctx, POWERPC_EXCP_FPU); \
3632 return; \
3633 } \
3634 if (unlikely(rA(ctx->opcode) == 0)) { \
3635 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3636 return; \
3637 } \
3638 gen_set_access_type(ctx, ACCESS_FLOAT); \
3639 EA = tcg_temp_new(); \
3640 gen_addr_imm_index(ctx, EA, 0); \
3641 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3642 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3643 tcg_temp_free(EA); \
3644 }
3645
3646 #define GEN_STUXF(name, stop, opc, type) \
3647 static void glue(gen_, name##ux)(DisasContext *ctx) \
3648 { \
3649 TCGv EA; \
3650 if (unlikely(!ctx->fpu_enabled)) { \
3651 gen_exception(ctx, POWERPC_EXCP_FPU); \
3652 return; \
3653 } \
3654 if (unlikely(rA(ctx->opcode) == 0)) { \
3655 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3656 return; \
3657 } \
3658 gen_set_access_type(ctx, ACCESS_FLOAT); \
3659 EA = tcg_temp_new(); \
3660 gen_addr_reg_index(ctx, EA); \
3661 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3662 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3663 tcg_temp_free(EA); \
3664 }
3665
3666 #define GEN_STXF(name, stop, opc2, opc3, type) \
3667 static void glue(gen_, name##x)(DisasContext *ctx) \
3668 { \
3669 TCGv EA; \
3670 if (unlikely(!ctx->fpu_enabled)) { \
3671 gen_exception(ctx, POWERPC_EXCP_FPU); \
3672 return; \
3673 } \
3674 gen_set_access_type(ctx, ACCESS_FLOAT); \
3675 EA = tcg_temp_new(); \
3676 gen_addr_reg_index(ctx, EA); \
3677 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3678 tcg_temp_free(EA); \
3679 }
3680
3681 #define GEN_STFS(name, stop, op, type) \
3682 GEN_STF(name, stop, op | 0x20, type); \
3683 GEN_STUF(name, stop, op | 0x21, type); \
3684 GEN_STUXF(name, stop, op | 0x01, type); \
3685 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3686
3687 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3688 {
3689 TCGv_i32 t0 = tcg_temp_new_i32();
3690 TCGv t1 = tcg_temp_new();
3691 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3692 tcg_gen_extu_i32_tl(t1, t0);
3693 tcg_temp_free_i32(t0);
3694 gen_qemu_st32(ctx, t1, arg2);
3695 tcg_temp_free(t1);
3696 }
3697
3698 /* stfd stfdu stfdux stfdx */
3699 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3700 /* stfs stfsu stfsux stfsx */
3701 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3702
3703 /* stfdp */
3704 static void gen_stfdp(DisasContext *ctx)
3705 {
3706 TCGv EA;
3707 if (unlikely(!ctx->fpu_enabled)) {
3708 gen_exception(ctx, POWERPC_EXCP_FPU);
3709 return;
3710 }
3711 gen_set_access_type(ctx, ACCESS_FLOAT);
3712 EA = tcg_temp_new();
3713 gen_addr_imm_index(ctx, EA, 0); \
3714 if (unlikely(ctx->le_mode)) {
3715 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3716 tcg_gen_addi_tl(EA, EA, 8);
3717 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3718 } else {
3719 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3720 tcg_gen_addi_tl(EA, EA, 8);
3721 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3722 }
3723 tcg_temp_free(EA);
3724 }
3725
3726 /* stfdpx */
3727 static void gen_stfdpx(DisasContext *ctx)
3728 {
3729 TCGv EA;
3730 if (unlikely(!ctx->fpu_enabled)) {
3731 gen_exception(ctx, POWERPC_EXCP_FPU);
3732 return;
3733 }
3734 gen_set_access_type(ctx, ACCESS_FLOAT);
3735 EA = tcg_temp_new();
3736 gen_addr_reg_index(ctx, EA);
3737 if (unlikely(ctx->le_mode)) {
3738 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3739 tcg_gen_addi_tl(EA, EA, 8);
3740 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3741 } else {
3742 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3743 tcg_gen_addi_tl(EA, EA, 8);
3744 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3745 }
3746 tcg_temp_free(EA);
3747 }
3748
3749 /* Optional: */
3750 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3751 {
3752 TCGv t0 = tcg_temp_new();
3753 tcg_gen_trunc_i64_tl(t0, arg1),
3754 gen_qemu_st32(ctx, t0, arg2);
3755 tcg_temp_free(t0);
3756 }
3757 /* stfiwx */
3758 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3759
3760 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3761 {
3762 #if defined(TARGET_PPC64)
3763 if (ctx->has_cfar)
3764 tcg_gen_movi_tl(cpu_cfar, nip);
3765 #endif
3766 }
3767
3768 /*** Branch ***/
3769 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3770 {
3771 TranslationBlock *tb;
3772 tb = ctx->tb;
3773 if (NARROW_MODE(ctx)) {
3774 dest = (uint32_t) dest;
3775 }
3776 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3777 likely(!ctx->singlestep_enabled)) {
3778 tcg_gen_goto_tb(n);
3779 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3780 tcg_gen_exit_tb((uintptr_t)tb + n);
3781 } else {
3782 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3783 if (unlikely(ctx->singlestep_enabled)) {
3784 if ((ctx->singlestep_enabled &
3785 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3786 (ctx->exception == POWERPC_EXCP_BRANCH ||
3787 ctx->exception == POWERPC_EXCP_TRACE)) {
3788 target_ulong tmp = ctx->nip;
3789 ctx->nip = dest;
3790 gen_exception(ctx, POWERPC_EXCP_TRACE);
3791 ctx->nip = tmp;
3792 }
3793 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3794 gen_debug_exception(ctx);
3795 }
3796 }
3797 tcg_gen_exit_tb(0);
3798 }
3799 }
3800
3801 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3802 {
3803 if (NARROW_MODE(ctx)) {
3804 nip = (uint32_t)nip;
3805 }
3806 tcg_gen_movi_tl(cpu_lr, nip);
3807 }
3808
3809 /* b ba bl bla */
3810 static void gen_b(DisasContext *ctx)
3811 {
3812 target_ulong li, target;
3813
3814 ctx->exception = POWERPC_EXCP_BRANCH;
3815 /* sign extend LI */
3816 li = LI(ctx->opcode);
3817 li = (li ^ 0x02000000) - 0x02000000;
3818 if (likely(AA(ctx->opcode) == 0)) {
3819 target = ctx->nip + li - 4;
3820 } else {
3821 target = li;
3822 }
3823 if (LK(ctx->opcode)) {
3824 gen_setlr(ctx, ctx->nip);
3825 }
3826 gen_update_cfar(ctx, ctx->nip);
3827 gen_goto_tb(ctx, 0, target);
3828 }
3829
3830 #define BCOND_IM 0
3831 #define BCOND_LR 1
3832 #define BCOND_CTR 2
3833 #define BCOND_TAR 3
3834
3835 static inline void gen_bcond(DisasContext *ctx, int type)
3836 {
3837 uint32_t bo = BO(ctx->opcode);
3838 int l1;
3839 TCGv target;
3840
3841 ctx->exception = POWERPC_EXCP_BRANCH;
3842 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3843 target = tcg_temp_local_new();
3844 if (type == BCOND_CTR)
3845 tcg_gen_mov_tl(target, cpu_ctr);
3846 else if (type == BCOND_TAR)
3847 gen_load_spr(target, SPR_TAR);
3848 else
3849 tcg_gen_mov_tl(target, cpu_lr);
3850 } else {
3851 TCGV_UNUSED(target);
3852 }
3853 if (LK(ctx->opcode))
3854 gen_setlr(ctx, ctx->nip);
3855 l1 = gen_new_label();
3856 if ((bo & 0x4) == 0) {
3857 /* Decrement and test CTR */
3858 TCGv temp = tcg_temp_new();
3859 if (unlikely(type == BCOND_CTR)) {
3860 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3861 return;
3862 }
3863 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3864 if (NARROW_MODE(ctx)) {
3865 tcg_gen_ext32u_tl(temp, cpu_ctr);
3866 } else {
3867 tcg_gen_mov_tl(temp, cpu_ctr);
3868 }
3869 if (bo & 0x2) {
3870 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3871 } else {
3872 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3873 }
3874 tcg_temp_free(temp);
3875 }
3876 if ((bo & 0x10) == 0) {
3877 /* Test CR */
3878 uint32_t bi = BI(ctx->opcode);
3879 uint32_t mask = 1 << (3 - (bi & 0x03));
3880 TCGv_i32 temp = tcg_temp_new_i32();
3881
3882 if (bo & 0x8) {
3883 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3884 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3885 } else {
3886 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3887 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3888 }
3889 tcg_temp_free_i32(temp);
3890 }
3891 gen_update_cfar(ctx, ctx->nip);
3892 if (type == BCOND_IM) {
3893 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3894 if (likely(AA(ctx->opcode) == 0)) {
3895 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3896 } else {
3897 gen_goto_tb(ctx, 0, li);
3898 }
3899 gen_set_label(l1);
3900 gen_goto_tb(ctx, 1, ctx->nip);
3901 } else {
3902 if (NARROW_MODE(ctx)) {
3903 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3904 } else {
3905 tcg_gen_andi_tl(cpu_nip, target, ~3);
3906 }
3907 tcg_gen_exit_tb(0);
3908 gen_set_label(l1);
3909 gen_update_nip(ctx, ctx->nip);
3910 tcg_gen_exit_tb(0);
3911 }
3912 }
3913
3914 static void gen_bc(DisasContext *ctx)
3915 {
3916 gen_bcond(ctx, BCOND_IM);
3917 }
3918
3919 static void gen_bcctr(DisasContext *ctx)
3920 {
3921 gen_bcond(ctx, BCOND_CTR);
3922 }
3923
3924 static void gen_bclr(DisasContext *ctx)
3925 {
3926 gen_bcond(ctx, BCOND_LR);
3927 }
3928
3929 static void gen_bctar(DisasContext *ctx)
3930 {
3931 gen_bcond(ctx, BCOND_TAR);
3932 }
3933
3934 /*** Condition register logical ***/
3935 #define GEN_CRLOGIC(name, tcg_op, opc) \
3936 static void glue(gen_, name)(DisasContext *ctx) \
3937 { \
3938 uint8_t bitmask; \
3939 int sh; \
3940 TCGv_i32 t0, t1; \
3941 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3942 t0 = tcg_temp_new_i32(); \
3943 if (sh > 0) \
3944 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3945 else if (sh < 0) \
3946 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3947 else \
3948 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3949 t1 = tcg_temp_new_i32(); \
3950 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3951 if (sh > 0) \
3952 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3953 else if (sh < 0) \
3954 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3955 else \
3956 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3957 tcg_op(t0, t0, t1); \
3958 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3959 tcg_gen_andi_i32(t0, t0, bitmask); \
3960 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3961 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3962 tcg_temp_free_i32(t0); \
3963 tcg_temp_free_i32(t1); \
3964 }
3965
3966 /* crand */
3967 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3968 /* crandc */
3969 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3970 /* creqv */
3971 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3972 /* crnand */
3973 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3974 /* crnor */
3975 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3976 /* cror */
3977 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3978 /* crorc */
3979 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3980 /* crxor */
3981 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3982
3983 /* mcrf */
3984 static void gen_mcrf(DisasContext *ctx)
3985 {
3986 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3987 }
3988
3989 /*** System linkage ***/
3990
3991 /* rfi (mem_idx only) */
3992 static void gen_rfi(DisasContext *ctx)
3993 {
3994 #if defined(CONFIG_USER_ONLY)
3995 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3996 #else
3997 /* Restore CPU state */
3998 if (unlikely(!ctx->mem_idx)) {
3999 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4000 return;
4001 }
4002 gen_update_cfar(ctx, ctx->nip);
4003 gen_helper_rfi(cpu_env);
4004 gen_sync_exception(ctx);
4005 #endif
4006 }
4007
4008 #if defined(TARGET_PPC64)
4009 static void gen_rfid(DisasContext *ctx)
4010 {
4011 #if defined(CONFIG_USER_ONLY)
4012 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4013 #else
4014 /* Restore CPU state */
4015 if (unlikely(!ctx->mem_idx)) {
4016 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4017 return;
4018 }
4019 gen_update_cfar(ctx, ctx->nip);
4020 gen_helper_rfid(cpu_env);
4021 gen_sync_exception(ctx);
4022 #endif
4023 }
4024
4025 static void gen_hrfid(DisasContext *ctx)
4026 {
4027 #if defined(CONFIG_USER_ONLY)
4028 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4029 #else
4030 /* Restore CPU state */
4031 if (unlikely(ctx->mem_idx <= 1)) {
4032 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4033 return;
4034 }
4035 gen_helper_hrfid(cpu_env);
4036 gen_sync_exception(ctx);
4037 #endif
4038 }
4039 #endif
4040
4041 /* sc */
4042 #if defined(CONFIG_USER_ONLY)
4043 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4044 #else
4045 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4046 #endif
4047 static void gen_sc(DisasContext *ctx)
4048 {
4049 uint32_t lev;
4050
4051 lev = (ctx->opcode >> 5) & 0x7F;
4052 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4053 }
4054
4055 /*** Trap ***/
4056
4057 /* tw */
4058 static void gen_tw(DisasContext *ctx)
4059 {
4060 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4061 /* Update the nip since this might generate a trap exception */
4062 gen_update_nip(ctx, ctx->nip);
4063 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4064 t0);
4065 tcg_temp_free_i32(t0);
4066 }
4067
4068 /* twi */
4069 static void gen_twi(DisasContext *ctx)
4070 {
4071 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4072 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4073 /* Update the nip since this might generate a trap exception */
4074 gen_update_nip(ctx, ctx->nip);
4075 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4076 tcg_temp_free(t0);
4077 tcg_temp_free_i32(t1);
4078 }
4079
4080 #if defined(TARGET_PPC64)
4081 /* td */
4082 static void gen_td(DisasContext *ctx)
4083 {
4084 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4085 /* Update the nip since this might generate a trap exception */
4086 gen_update_nip(ctx, ctx->nip);
4087 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4088 t0);
4089 tcg_temp_free_i32(t0);
4090 }
4091
4092 /* tdi */
4093 static void gen_tdi(DisasContext *ctx)
4094 {
4095 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4096 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4097 /* Update the nip since this might generate a trap exception */
4098 gen_update_nip(ctx, ctx->nip);
4099 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4100 tcg_temp_free(t0);
4101 tcg_temp_free_i32(t1);
4102 }
4103 #endif
4104
4105 /*** Processor control ***/
4106
4107 static void gen_read_xer(TCGv dst)
4108 {
4109 TCGv t0 = tcg_temp_new();
4110 TCGv t1 = tcg_temp_new();
4111 TCGv t2 = tcg_temp_new();
4112 tcg_gen_mov_tl(dst, cpu_xer);
4113 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4114 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4115 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4116 tcg_gen_or_tl(t0, t0, t1);
4117 tcg_gen_or_tl(dst, dst, t2);
4118 tcg_gen_or_tl(dst, dst, t0);
4119 tcg_temp_free(t0);
4120 tcg_temp_free(t1);
4121 tcg_temp_free(t2);
4122 }
4123
4124 static void gen_write_xer(TCGv src)
4125 {
4126 tcg_gen_andi_tl(cpu_xer, src,
4127 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4128 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4129 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4130 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4131 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4132 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4133 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4134 }
4135
4136 /* mcrxr */
4137 static void gen_mcrxr(DisasContext *ctx)
4138 {
4139 TCGv_i32 t0 = tcg_temp_new_i32();
4140 TCGv_i32 t1 = tcg_temp_new_i32();
4141 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4142
4143 tcg_gen_trunc_tl_i32(t0, cpu_so);
4144 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4145 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4146 tcg_gen_shri_i32(t0, t0, 2);
4147 tcg_gen_shri_i32(t1, t1, 1);
4148 tcg_gen_or_i32(dst, dst, t0);
4149 tcg_gen_or_i32(dst, dst, t1);
4150 tcg_temp_free_i32(t0);
4151 tcg_temp_free_i32(t1);
4152
4153 tcg_gen_movi_tl(cpu_so, 0);
4154 tcg_gen_movi_tl(cpu_ov, 0);
4155 tcg_gen_movi_tl(cpu_ca, 0);
4156 }
4157
4158 /* mfcr mfocrf */
4159 static void gen_mfcr(DisasContext *ctx)
4160 {
4161 uint32_t crm, crn;
4162
4163 if (likely(ctx->opcode & 0x00100000)) {
4164 crm = CRM(ctx->opcode);
4165 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4166 crn = ctz32 (crm);
4167 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4168 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4169 cpu_gpr[rD(ctx->opcode)], crn * 4);
4170 }
4171 } else {
4172 TCGv_i32 t0 = tcg_temp_new_i32();
4173 tcg_gen_mov_i32(t0, cpu_crf[0]);
4174 tcg_gen_shli_i32(t0, t0, 4);
4175 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4176 tcg_gen_shli_i32(t0, t0, 4);
4177 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4178 tcg_gen_shli_i32(t0, t0, 4);
4179 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4180 tcg_gen_shli_i32(t0, t0, 4);
4181 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4182 tcg_gen_shli_i32(t0, t0, 4);
4183 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4184 tcg_gen_shli_i32(t0, t0, 4);
4185 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4186 tcg_gen_shli_i32(t0, t0, 4);
4187 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4188 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4189 tcg_temp_free_i32(t0);
4190 }
4191 }
4192
4193 /* mfmsr */
4194 static void gen_mfmsr(DisasContext *ctx)
4195 {
4196 #if defined(CONFIG_USER_ONLY)
4197 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4198 #else
4199 if (unlikely(!ctx->mem_idx)) {
4200 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4201 return;
4202 }
4203 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4204 #endif
4205 }
4206
4207 static void spr_noaccess(void *opaque, int gprn, int sprn)
4208 {
4209 #if 0
4210 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4211 printf("ERROR: try to access SPR %d !\n", sprn);
4212 #endif
4213 }
4214 #define SPR_NOACCESS (&spr_noaccess)
4215
4216 /* mfspr */
4217 static inline void gen_op_mfspr(DisasContext *ctx)
4218 {
4219 void (*read_cb)(void *opaque, int gprn, int sprn);
4220 uint32_t sprn = SPR(ctx->opcode);
4221
4222 #if !defined(CONFIG_USER_ONLY)
4223 if (ctx->mem_idx == 2)
4224 read_cb = ctx->spr_cb[sprn].hea_read;
4225 else if (ctx->mem_idx)
4226 read_cb = ctx->spr_cb[sprn].oea_read;
4227 else
4228 #endif
4229 read_cb = ctx->spr_cb[sprn].uea_read;
4230 if (likely(read_cb != NULL)) {
4231 if (likely(read_cb != SPR_NOACCESS)) {
4232 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4233 } else {
4234 /* Privilege exception */
4235 /* This is a hack to avoid warnings when running Linux:
4236 * this OS breaks the PowerPC virtualisation model,
4237 * allowing userland application to read the PVR
4238 */
4239 if (sprn != SPR_PVR) {
4240 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4241 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4242 printf("Trying to read privileged spr %d (0x%03x) at "
4243 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4244 }
4245 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4246 }
4247 } else {
4248 /* Not defined */
4249 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4250 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4251 printf("Trying to read invalid spr %d (0x%03x) at "
4252 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4253 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4254 }
4255 }
4256
4257 static void gen_mfspr(DisasContext *ctx)
4258 {
4259 gen_op_mfspr(ctx);
4260 }
4261
4262 /* mftb */
4263 static void gen_mftb(DisasContext *ctx)
4264 {
4265 gen_op_mfspr(ctx);
4266 }
4267
4268 /* mtcrf mtocrf*/
4269 static void gen_mtcrf(DisasContext *ctx)
4270 {
4271 uint32_t crm, crn;
4272
4273 crm = CRM(ctx->opcode);
4274 if (likely((ctx->opcode & 0x00100000))) {
4275 if (crm && ((crm & (crm - 1)) == 0)) {
4276 TCGv_i32 temp = tcg_temp_new_i32();
4277 crn = ctz32 (crm);
4278 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4279 tcg_gen_shri_i32(temp, temp, crn * 4);
4280 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4281 tcg_temp_free_i32(temp);
4282 }
4283 } else {
4284 TCGv_i32 temp = tcg_temp_new_i32();
4285 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4286 for (crn = 0 ; crn < 8 ; crn++) {
4287 if (crm & (1 << crn)) {
4288 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4289 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4290 }
4291 }
4292 tcg_temp_free_i32(temp);
4293 }
4294 }
4295
4296 /* mtmsr */
4297 #if defined(TARGET_PPC64)
4298 static void gen_mtmsrd(DisasContext *ctx)
4299 {
4300 #if defined(CONFIG_USER_ONLY)
4301 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4302 #else
4303 if (unlikely(!ctx->mem_idx)) {
4304 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4305 return;
4306 }
4307 if (ctx->opcode & 0x00010000) {
4308 /* Special form that does not need any synchronisation */
4309 TCGv t0 = tcg_temp_new();
4310 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4311 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4312 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4313 tcg_temp_free(t0);
4314 } else {
4315 /* XXX: we need to update nip before the store
4316 * if we enter power saving mode, we will exit the loop
4317 * directly from ppc_store_msr
4318 */
4319 gen_update_nip(ctx, ctx->nip);
4320 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4321 /* Must stop the translation as machine state (may have) changed */
4322 /* Note that mtmsr is not always defined as context-synchronizing */
4323 gen_stop_exception(ctx);
4324 }
4325 #endif
4326 }
4327 #endif
4328
4329 static void gen_mtmsr(DisasContext *ctx)
4330 {
4331 #if defined(CONFIG_USER_ONLY)
4332 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4333 #else
4334 if (unlikely(!ctx->mem_idx)) {
4335 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4336 return;
4337 }
4338 if (ctx->opcode & 0x00010000) {
4339 /* Special form that does not need any synchronisation */
4340 TCGv t0 = tcg_temp_new();
4341 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4342 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4343 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4344 tcg_temp_free(t0);
4345 } else {
4346 TCGv msr = tcg_temp_new();
4347
4348 /* XXX: we need to update nip before the store
4349 * if we enter power saving mode, we will exit the loop
4350 * directly from ppc_store_msr
4351 */
4352 gen_update_nip(ctx, ctx->nip);
4353 #if defined(TARGET_PPC64)
4354 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4355 #else
4356 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4357 #endif
4358 gen_helper_store_msr(cpu_env, msr);
4359 /* Must stop the translation as machine state (may have) changed */
4360 /* Note that mtmsr is not always defined as context-synchronizing */
4361 gen_stop_exception(ctx);
4362 }
4363 #endif
4364 }
4365
4366 /* mtspr */
4367 static void gen_mtspr(DisasContext *ctx)
4368 {
4369 void (*write_cb)(void *opaque, int sprn, int gprn);
4370 uint32_t sprn = SPR(ctx->opcode);
4371
4372 #if !defined(CONFIG_USER_ONLY)
4373 if (ctx->mem_idx == 2)
4374 write_cb = ctx->spr_cb[sprn].hea_write;
4375 else if (ctx->mem_idx)
4376 write_cb = ctx->spr_cb[sprn].oea_write;
4377 else
4378 #endif
4379 write_cb = ctx->spr_cb[sprn].uea_write;
4380 if (likely(write_cb != NULL)) {
4381 if (likely(write_cb != SPR_NOACCESS)) {
4382 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4383 } else {
4384 /* Privilege exception */
4385 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4386 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4387 printf("Trying to write privileged spr %d (0x%03x) at "
4388 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4389 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4390 }
4391 } else {
4392 /* Not defined */
4393 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4394 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4395 printf("Trying to write invalid spr %d (0x%03x) at "
4396 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4397 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4398 }
4399 }
4400
4401 /*** Cache management ***/
4402
4403 /* dcbf */
4404 static void gen_dcbf(DisasContext *ctx)
4405 {
4406 /* XXX: specification says this is treated as a load by the MMU */
4407 TCGv t0;
4408 gen_set_access_type(ctx, ACCESS_CACHE);
4409 t0 = tcg_temp_new();
4410 gen_addr_reg_index(ctx, t0);
4411 gen_qemu_ld8u(ctx, t0, t0);
4412 tcg_temp_free(t0);
4413 }
4414
4415 /* dcbi (Supervisor only) */
4416 static void gen_dcbi(DisasContext *ctx)
4417 {
4418 #if defined(CONFIG_USER_ONLY)
4419 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4420 #else
4421 TCGv EA, val;
4422 if (unlikely(!ctx->mem_idx)) {
4423 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4424 return;
4425 }
4426 EA = tcg_temp_new();
4427 gen_set_access_type(ctx, ACCESS_CACHE);
4428 gen_addr_reg_index(ctx, EA);
4429 val = tcg_temp_new();
4430 /* XXX: specification says this should be treated as a store by the MMU */
4431 gen_qemu_ld8u(ctx, val, EA);
4432 gen_qemu_st8(ctx, val, EA);
4433 tcg_temp_free(val);
4434 tcg_temp_free(EA);
4435 #endif
4436 }
4437
4438 /* dcdst */
4439 static void gen_dcbst(DisasContext *ctx)
4440 {
4441 /* XXX: specification say this is treated as a load by the MMU */
4442 TCGv t0;
4443 gen_set_access_type(ctx, ACCESS_CACHE);
4444 t0 = tcg_temp_new();
4445 gen_addr_reg_index(ctx, t0);
4446 gen_qemu_ld8u(ctx, t0, t0);
4447 tcg_temp_free(t0);
4448 }
4449
4450 /* dcbt */
4451 static void gen_dcbt(DisasContext *ctx)
4452 {
4453 /* interpreted as no-op */
4454 /* XXX: specification say this is treated as a load by the MMU
4455 * but does not generate any exception
4456 */
4457 }
4458
4459 /* dcbtst */
4460 static void gen_dcbtst(DisasContext *ctx)
4461 {
4462 /* interpreted as no-op */
4463 /* XXX: specification say this is treated as a load by the MMU
4464 * but does not generate any exception
4465 */
4466 }
4467
4468 /* dcbz */
4469 static void gen_dcbz(DisasContext *ctx)
4470 {
4471 TCGv tcgv_addr;
4472 TCGv_i32 tcgv_is_dcbzl;
4473 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4474
4475 gen_set_access_type(ctx, ACCESS_CACHE);
4476 /* NIP cannot be restored if the memory exception comes from an helper */
4477 gen_update_nip(ctx, ctx->nip - 4);
4478 tcgv_addr = tcg_temp_new();
4479 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4480
4481 gen_addr_reg_index(ctx, tcgv_addr);
4482 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4483
4484 tcg_temp_free(tcgv_addr);
4485 tcg_temp_free_i32(tcgv_is_dcbzl);
4486 }
4487
4488 /* dst / dstt */
4489 static void gen_dst(DisasContext *ctx)
4490 {
4491 if (rA(ctx->opcode) == 0) {
4492 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4493 } else {
4494 /* interpreted as no-op */
4495 }
4496 }
4497
4498 /* dstst /dststt */
4499 static void gen_dstst(DisasContext *ctx)
4500 {
4501 if (rA(ctx->opcode) == 0) {
4502 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4503 } else {
4504 /* interpreted as no-op */
4505 }
4506
4507 }
4508
4509 /* dss / dssall */
4510 static void gen_dss(DisasContext *ctx)
4511 {
4512 /* interpreted as no-op */
4513 }
4514
4515 /* icbi */
4516 static void gen_icbi(DisasContext *ctx)
4517 {
4518 TCGv t0;
4519 gen_set_access_type(ctx, ACCESS_CACHE);
4520 /* NIP cannot be restored if the memory exception comes from an helper */
4521 gen_update_nip(ctx, ctx->nip - 4);
4522 t0 = tcg_temp_new();
4523 gen_addr_reg_index(ctx, t0);
4524 gen_helper_icbi(cpu_env, t0);
4525 tcg_temp_free(t0);
4526 }
4527
4528 /* Optional: */
4529 /* dcba */
4530 static void gen_dcba(DisasContext *ctx)
4531 {
4532 /* interpreted as no-op */
4533 /* XXX: specification say this is treated as a store by the MMU
4534 * but does not generate any exception
4535 */
4536 }
4537
4538 /*** Segment register manipulation ***/
4539 /* Supervisor only: */
4540
4541 /* mfsr */
4542 static void gen_mfsr(DisasContext *ctx)
4543 {
4544 #if defined(CONFIG_USER_ONLY)
4545 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4546 #else
4547 TCGv t0;
4548 if (unlikely(!ctx->mem_idx)) {
4549 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4550 return;
4551 }
4552 t0 = tcg_const_tl(SR(ctx->opcode));
4553 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4554 tcg_temp_free(t0);
4555 #endif
4556 }
4557
4558 /* mfsrin */
4559 static void gen_mfsrin(DisasContext *ctx)
4560 {
4561 #if defined(CONFIG_USER_ONLY)
4562 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4563 #else
4564 TCGv t0;
4565 if (unlikely(!ctx->mem_idx)) {
4566 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4567 return;
4568 }
4569 t0 = tcg_temp_new();
4570 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4571 tcg_gen_andi_tl(t0, t0, 0xF);
4572 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4573 tcg_temp_free(t0);
4574 #endif
4575 }
4576
4577 /* mtsr */
4578 static void gen_mtsr(DisasContext *ctx)
4579 {
4580 #if defined(CONFIG_USER_ONLY)
4581 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4582 #else
4583 TCGv t0;
4584 if (unlikely(!ctx->mem_idx)) {
4585 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4586 return;
4587 }
4588 t0 = tcg_const_tl(SR(ctx->opcode));
4589 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4590 tcg_temp_free(t0);
4591 #endif
4592 }
4593
4594 /* mtsrin */
4595 static void gen_mtsrin(DisasContext *ctx)
4596 {
4597 #if defined(CONFIG_USER_ONLY)
4598 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4599 #else
4600 TCGv t0;
4601 if (unlikely(!ctx->mem_idx)) {
4602 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4603 return;
4604 }
4605 t0 = tcg_temp_new();
4606 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4607 tcg_gen_andi_tl(t0, t0, 0xF);
4608 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4609 tcg_temp_free(t0);
4610 #endif
4611 }
4612
4613 #if defined(TARGET_PPC64)
4614 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4615
4616 /* mfsr */
4617 static void gen_mfsr_64b(DisasContext *ctx)
4618 {
4619 #if defined(CONFIG_USER_ONLY)
4620 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4621 #else
4622 TCGv t0;
4623 if (unlikely(!ctx->mem_idx)) {
4624 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4625 return;
4626 }
4627 t0 = tcg_const_tl(SR(ctx->opcode));
4628 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4629 tcg_temp_free(t0);
4630 #endif
4631 }
4632
4633 /* mfsrin */
4634 static void gen_mfsrin_64b(DisasContext *ctx)
4635 {
4636 #if defined(CONFIG_USER_ONLY)
4637 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4638 #else
4639 TCGv t0;
4640 if (unlikely(!ctx->mem_idx)) {
4641 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4642 return;
4643 }
4644 t0 = tcg_temp_new();
4645 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4646 tcg_gen_andi_tl(t0, t0, 0xF);
4647 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4648 tcg_temp_free(t0);
4649 #endif
4650 }
4651
4652 /* mtsr */
4653 static void gen_mtsr_64b(DisasContext *ctx)
4654 {
4655 #if defined(CONFIG_USER_ONLY)
4656 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4657 #else
4658 TCGv t0;
4659 if (unlikely(!ctx->mem_idx)) {
4660 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4661 return;
4662 }
4663 t0 = tcg_const_tl(SR(ctx->opcode));
4664 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4665 tcg_temp_free(t0);
4666 #endif
4667 }
4668
4669 /* mtsrin */
4670 static void gen_mtsrin_64b(DisasContext *ctx)
4671 {
4672 #if defined(CONFIG_USER_ONLY)
4673 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4674 #else
4675 TCGv t0;
4676 if (unlikely(!ctx->mem_idx)) {
4677 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4678 return;
4679 }
4680 t0 = tcg_temp_new();
4681 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4682 tcg_gen_andi_tl(t0, t0, 0xF);
4683 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4684 tcg_temp_free(t0);
4685 #endif
4686 }
4687
4688 /* slbmte */
4689 static void gen_slbmte(DisasContext *ctx)
4690 {
4691 #if defined(CONFIG_USER_ONLY)
4692 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4693 #else
4694 if (unlikely(!ctx->mem_idx)) {
4695 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4696 return;
4697 }
4698 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4699 cpu_gpr[rS(ctx->opcode)]);
4700 #endif
4701 }
4702
4703 static void gen_slbmfee(DisasContext *ctx)
4704 {
4705 #if defined(CONFIG_USER_ONLY)
4706 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4707 #else
4708 if (unlikely(!ctx->mem_idx)) {
4709 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4710 return;
4711 }
4712 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4713 cpu_gpr[rB(ctx->opcode)]);
4714 #endif
4715 }
4716
4717 static void gen_slbmfev(DisasContext *ctx)
4718 {
4719 #if defined(CONFIG_USER_ONLY)
4720 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4721 #else
4722 if (unlikely(!ctx->mem_idx)) {
4723 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4724 return;
4725 }
4726 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4727 cpu_gpr[rB(ctx->opcode)]);
4728 #endif
4729 }
4730 #endif /* defined(TARGET_PPC64) */
4731
4732 /*** Lookaside buffer management ***/
4733 /* Optional & mem_idx only: */
4734
4735 /* tlbia */
4736 static void gen_tlbia(DisasContext *ctx)
4737 {
4738 #if defined(CONFIG_USER_ONLY)
4739 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4740 #else
4741 if (unlikely(!ctx->mem_idx)) {
4742 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4743 return;
4744 }
4745 gen_helper_tlbia(cpu_env);
4746 #endif
4747 }
4748
4749 /* tlbiel */
4750 static void gen_tlbiel(DisasContext *ctx)
4751 {
4752 #if defined(CONFIG_USER_ONLY)
4753 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4754 #else
4755 if (unlikely(!ctx->mem_idx)) {
4756 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4757 return;
4758 }
4759 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4760 #endif
4761 }
4762
4763 /* tlbie */
4764 static void gen_tlbie(DisasContext *ctx)
4765 {
4766 #if defined(CONFIG_USER_ONLY)
4767 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4768 #else
4769 if (unlikely(!ctx->mem_idx)) {
4770 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4771 return;
4772 }
4773 if (NARROW_MODE(ctx)) {
4774 TCGv t0 = tcg_temp_new();
4775 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4776 gen_helper_tlbie(cpu_env, t0);
4777 tcg_temp_free(t0);
4778 } else {
4779 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4780 }
4781 #endif
4782 }
4783
4784 /* tlbsync */
4785 static void gen_tlbsync(DisasContext *ctx)
4786 {
4787 #if defined(CONFIG_USER_ONLY)
4788 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4789 #else
4790 if (unlikely(!ctx->mem_idx)) {
4791 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4792 return;
4793 }
4794 /* This has no effect: it should ensure that all previous
4795 * tlbie have completed
4796 */
4797 gen_stop_exception(ctx);
4798 #endif
4799 }
4800
4801 #if defined(TARGET_PPC64)
4802 /* slbia */
4803 static void gen_slbia(DisasContext *ctx)
4804 {
4805 #if defined(CONFIG_USER_ONLY)
4806 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4807 #else
4808 if (unlikely(!ctx->mem_idx)) {
4809 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4810 return;
4811 }
4812 gen_helper_slbia(cpu_env);
4813 #endif
4814 }
4815
4816 /* slbie */
4817 static void gen_slbie(DisasContext *ctx)
4818 {
4819 #if defined(CONFIG_USER_ONLY)
4820 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4821 #else
4822 if (unlikely(!ctx->mem_idx)) {
4823 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4824 return;
4825 }
4826 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4827 #endif
4828 }
4829 #endif
4830
4831 /*** External control ***/
4832 /* Optional: */
4833
4834 /* eciwx */
4835 static void gen_eciwx(DisasContext *ctx)
4836 {
4837 TCGv t0;
4838 /* Should check EAR[E] ! */
4839 gen_set_access_type(ctx, ACCESS_EXT);
4840 t0 = tcg_temp_new();
4841 gen_addr_reg_index(ctx, t0);
4842 gen_check_align(ctx, t0, 0x03);
4843 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4844 tcg_temp_free(t0);
4845 }
4846
4847 /* ecowx */
4848 static void gen_ecowx(DisasContext *ctx)
4849 {
4850 TCGv t0;
4851 /* Should check EAR[E] ! */
4852 gen_set_access_type(ctx, ACCESS_EXT);
4853 t0 = tcg_temp_new();
4854 gen_addr_reg_index(ctx, t0);
4855 gen_check_align(ctx, t0, 0x03);
4856 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4857 tcg_temp_free(t0);
4858 }
4859
4860 /* PowerPC 601 specific instructions */
4861
4862 /* abs - abs. */
4863 static void gen_abs(DisasContext *ctx)
4864 {
4865 int l1 = gen_new_label();
4866 int l2 = gen_new_label();
4867 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4868 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4869 tcg_gen_br(l2);
4870 gen_set_label(l1);
4871 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4872 gen_set_label(l2);
4873 if (unlikely(Rc(ctx->opcode) != 0))
4874 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4875 }
4876
4877 /* abso - abso. */
4878 static void gen_abso(DisasContext *ctx)
4879 {
4880 int l1 = gen_new_label();
4881 int l2 = gen_new_label();
4882 int l3 = gen_new_label();
4883 /* Start with XER OV disabled, the most likely case */
4884 tcg_gen_movi_tl(cpu_ov, 0);
4885 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4886 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4887 tcg_gen_movi_tl(cpu_ov, 1);
4888 tcg_gen_movi_tl(cpu_so, 1);
4889 tcg_gen_br(l2);
4890 gen_set_label(l1);
4891 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4892 tcg_gen_br(l3);
4893 gen_set_label(l2);
4894 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4895 gen_set_label(l3);
4896 if (unlikely(Rc(ctx->opcode) != 0))
4897 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4898 }
4899
4900 /* clcs */
4901 static void gen_clcs(DisasContext *ctx)
4902 {
4903 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4904 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4905 tcg_temp_free_i32(t0);
4906 /* Rc=1 sets CR0 to an undefined state */
4907 }
4908
4909 /* div - div. */
4910 static void gen_div(DisasContext *ctx)
4911 {
4912 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4913 cpu_gpr[rB(ctx->opcode)]);
4914 if (unlikely(Rc(ctx->opcode) != 0))
4915 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4916 }
4917
4918 /* divo - divo. */
4919 static void gen_divo(DisasContext *ctx)
4920 {
4921 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4922 cpu_gpr[rB(ctx->opcode)]);
4923 if (unlikely(Rc(ctx->opcode) != 0))
4924 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4925 }
4926
4927 /* divs - divs. */
4928 static void gen_divs(DisasContext *ctx)
4929 {
4930 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4931 cpu_gpr[rB(ctx->opcode)]);
4932 if (unlikely(Rc(ctx->opcode) != 0))
4933 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4934 }
4935
4936 /* divso - divso. */
4937 static void gen_divso(DisasContext *ctx)
4938 {
4939 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4940 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4941 if (unlikely(Rc(ctx->opcode) != 0))
4942 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4943 }
4944
4945 /* doz - doz. */
4946 static void gen_doz(DisasContext *ctx)
4947 {
4948 int l1 = gen_new_label();
4949 int l2 = gen_new_label();
4950 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4951 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4952 tcg_gen_br(l2);
4953 gen_set_label(l1);
4954 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4955 gen_set_label(l2);
4956 if (unlikely(Rc(ctx->opcode) != 0))
4957 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4958 }
4959
4960 /* dozo - dozo. */
4961 static void gen_dozo(DisasContext *ctx)
4962 {
4963 int l1 = gen_new_label();
4964 int l2 = gen_new_label();
4965 TCGv t0 = tcg_temp_new();
4966 TCGv t1 = tcg_temp_new();
4967 TCGv t2 = tcg_temp_new();
4968 /* Start with XER OV disabled, the most likely case */
4969 tcg_gen_movi_tl(cpu_ov, 0);
4970 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4971 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4972 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4973 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4974 tcg_gen_andc_tl(t1, t1, t2);
4975 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4976 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4977 tcg_gen_movi_tl(cpu_ov, 1);
4978 tcg_gen_movi_tl(cpu_so, 1);
4979 tcg_gen_br(l2);
4980 gen_set_label(l1);
4981 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4982 gen_set_label(l2);
4983 tcg_temp_free(t0);
4984 tcg_temp_free(t1);
4985 tcg_temp_free(t2);
4986 if (unlikely(Rc(ctx->opcode) != 0))
4987 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4988 }
4989
4990 /* dozi */
4991 static void gen_dozi(DisasContext *ctx)
4992 {
4993 target_long simm = SIMM(ctx->opcode);
4994 int l1 = gen_new_label();
4995 int l2 = gen_new_label();
4996 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4997 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4998 tcg_gen_br(l2);
4999 gen_set_label(l1);
5000 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5001 gen_set_label(l2);
5002 if (unlikely(Rc(ctx->opcode) != 0))
5003 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5004 }
5005
5006 /* lscbx - lscbx. */
5007 static void gen_lscbx(DisasContext *ctx)
5008 {
5009 TCGv t0 = tcg_temp_new();
5010 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5011 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5012 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5013
5014 gen_addr_reg_index(ctx, t0);
5015 /* NIP cannot be restored if the memory exception comes from an helper */
5016 gen_update_nip(ctx, ctx->nip - 4);
5017 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5018 tcg_temp_free_i32(t1);
5019 tcg_temp_free_i32(t2);
5020 tcg_temp_free_i32(t3);
5021 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5022 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5023 if (unlikely(Rc(ctx->opcode) != 0))
5024 gen_set_Rc0(ctx, t0);
5025 tcg_temp_free(t0);
5026 }
5027
5028 /* maskg - maskg. */
5029 static void gen_maskg(DisasContext *ctx)
5030 {
5031 int l1 = gen_new_label();
5032 TCGv t0 = tcg_temp_new();
5033 TCGv t1 = tcg_temp_new();
5034 TCGv t2 = tcg_temp_new();
5035 TCGv t3 = tcg_temp_new();
5036 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5037 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5038 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5039 tcg_gen_addi_tl(t2, t0, 1);
5040 tcg_gen_shr_tl(t2, t3, t2);
5041 tcg_gen_shr_tl(t3, t3, t1);
5042 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5043 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5044 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5045 gen_set_label(l1);
5046 tcg_temp_free(t0);
5047 tcg_temp_free(t1);
5048 tcg_temp_free(t2);
5049 tcg_temp_free(t3);
5050 if (unlikely(Rc(ctx->opcode) != 0))
5051 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5052 }
5053
5054 /* maskir - maskir. */
5055 static void gen_maskir(DisasContext *ctx)
5056 {
5057 TCGv t0 = tcg_temp_new();
5058 TCGv t1 = tcg_temp_new();
5059 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5060 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5061 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5062 tcg_temp_free(t0);
5063 tcg_temp_free(t1);
5064 if (unlikely(Rc(ctx->opcode) != 0))
5065 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5066 }
5067
5068 /* mul - mul. */
5069 static void gen_mul(DisasContext *ctx)
5070 {
5071 TCGv_i64 t0 = tcg_temp_new_i64();
5072 TCGv_i64 t1 = tcg_temp_new_i64();
5073 TCGv t2 = tcg_temp_new();
5074 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5075 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5076 tcg_gen_mul_i64(t0, t0, t1);
5077 tcg_gen_trunc_i64_tl(t2, t0);
5078 gen_store_spr(SPR_MQ, t2);
5079 tcg_gen_shri_i64(t1, t0, 32);
5080 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5081 tcg_temp_free_i64(t0);
5082 tcg_temp_free_i64(t1);
5083 tcg_temp_free(t2);
5084 if (unlikely(Rc(ctx->opcode) != 0))
5085 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5086 }
5087
5088 /* mulo - mulo. */
5089 static void gen_mulo(DisasContext *ctx)
5090 {
5091 int l1 = gen_new_label();
5092 TCGv_i64 t0 = tcg_temp_new_i64();
5093 TCGv_i64 t1 = tcg_temp_new_i64();
5094 TCGv t2 = tcg_temp_new();
5095 /* Start with XER OV disabled, the most likely case */
5096 tcg_gen_movi_tl(cpu_ov, 0);
5097 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5098 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5099 tcg_gen_mul_i64(t0, t0, t1);
5100 tcg_gen_trunc_i64_tl(t2, t0);
5101 gen_store_spr(SPR_MQ, t2);
5102 tcg_gen_shri_i64(t1, t0, 32);
5103 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5104 tcg_gen_ext32s_i64(t1, t0);
5105 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5106 tcg_gen_movi_tl(cpu_ov, 1);
5107 tcg_gen_movi_tl(cpu_so, 1);
5108 gen_set_label(l1);
5109 tcg_temp_free_i64(t0);
5110 tcg_temp_free_i64(t1);
5111 tcg_temp_free(t2);
5112 if (unlikely(Rc(ctx->opcode) != 0))
5113 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5114 }
5115
5116 /* nabs - nabs. */
5117 static void gen_nabs(DisasContext *ctx)
5118 {
5119 int l1 = gen_new_label();
5120 int l2 = gen_new_label();
5121 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5122 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5123 tcg_gen_br(l2);
5124 gen_set_label(l1);
5125 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5126 gen_set_label(l2);
5127 if (unlikely(Rc(ctx->opcode) != 0))
5128 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5129 }
5130
5131 /* nabso - nabso. */
5132 static void gen_nabso(DisasContext *ctx)
5133 {
5134 int l1 = gen_new_label();
5135 int l2 = gen_new_label();
5136 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5137 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5138 tcg_gen_br(l2);
5139 gen_set_label(l1);
5140 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5141 gen_set_label(l2);
5142 /* nabs never overflows */
5143 tcg_gen_movi_tl(cpu_ov, 0);
5144 if (unlikely(Rc(ctx->opcode) != 0))
5145 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5146 }
5147
5148 /* rlmi - rlmi. */
5149 static void gen_rlmi(DisasContext *ctx)
5150 {
5151 uint32_t mb = MB(ctx->opcode);
5152 uint32_t me = ME(ctx->opcode);
5153 TCGv t0 = tcg_temp_new();
5154 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5155 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5156 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5157 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5158 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5159 tcg_temp_free(t0);
5160 if (unlikely(Rc(ctx->opcode) != 0))
5161 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5162 }
5163
5164 /* rrib - rrib. */
5165 static void gen_rrib(DisasContext *ctx)
5166 {
5167 TCGv t0 = tcg_temp_new();
5168 TCGv t1 = tcg_temp_new();
5169 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5170 tcg_gen_movi_tl(t1, 0x80000000);
5171 tcg_gen_shr_tl(t1, t1, t0);
5172 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5173 tcg_gen_and_tl(t0, t0, t1);
5174 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5175 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5176 tcg_temp_free(t0);
5177 tcg_temp_free(t1);
5178 if (unlikely(Rc(ctx->opcode) != 0))
5179 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5180 }
5181
5182 /* sle - sle. */
5183 static void gen_sle(DisasContext *ctx)
5184 {
5185 TCGv t0 = tcg_temp_new();
5186 TCGv t1 = tcg_temp_new();
5187 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5188 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5189 tcg_gen_subfi_tl(t1, 32, t1);
5190 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5191 tcg_gen_or_tl(t1, t0, t1);
5192 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5193 gen_store_spr(SPR_MQ, t1);
5194 tcg_temp_free(t0);
5195 tcg_temp_free(t1);
5196 if (unlikely(Rc(ctx->opcode) != 0))
5197 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5198 }
5199
5200 /* sleq - sleq. */
5201 static void gen_sleq(DisasContext *ctx)
5202 {
5203 TCGv t0 = tcg_temp_new();
5204 TCGv t1 = tcg_temp_new();
5205 TCGv t2 = tcg_temp_new();
5206 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5207 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5208 tcg_gen_shl_tl(t2, t2, t0);
5209 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5210 gen_load_spr(t1, SPR_MQ);
5211 gen_store_spr(SPR_MQ, t0);
5212 tcg_gen_and_tl(t0, t0, t2);
5213 tcg_gen_andc_tl(t1, t1, t2);
5214 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5215 tcg_temp_free(t0);
5216 tcg_temp_free(t1);
5217 tcg_temp_free(t2);
5218 if (unlikely(Rc(ctx->opcode) != 0))
5219 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5220 }
5221
5222 /* sliq - sliq. */
5223 static void gen_sliq(DisasContext *ctx)
5224 {
5225 int sh = SH(ctx->opcode);
5226 TCGv t0 = tcg_temp_new();
5227 TCGv t1 = tcg_temp_new();
5228 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5229 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5230 tcg_gen_or_tl(t1, t0, t1);
5231 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5232 gen_store_spr(SPR_MQ, t1);
5233 tcg_temp_free(t0);
5234 tcg_temp_free(t1);
5235 if (unlikely(Rc(ctx->opcode) != 0))
5236 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5237 }
5238
5239 /* slliq - slliq. */
5240 static void gen_slliq(DisasContext *ctx)
5241 {
5242 int sh = SH(ctx->opcode);
5243 TCGv t0 = tcg_temp_new();
5244 TCGv t1 = tcg_temp_new();
5245 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5246 gen_load_spr(t1, SPR_MQ);
5247 gen_store_spr(SPR_MQ, t0);
5248 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5249 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5250 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5251 tcg_temp_free(t0);
5252 tcg_temp_free(t1);
5253 if (unlikely(Rc(ctx->opcode) != 0))
5254 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5255 }
5256
5257 /* sllq - sllq. */
5258 static void gen_sllq(DisasContext *ctx)
5259 {
5260 int l1 = gen_new_label();
5261 int l2 = gen_new_label();
5262 TCGv t0 = tcg_temp_local_new();
5263 TCGv t1 = tcg_temp_local_new();
5264 TCGv t2 = tcg_temp_local_new();
5265 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5266 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5267 tcg_gen_shl_tl(t1, t1, t2);
5268 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5269 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5270 gen_load_spr(t0, SPR_MQ);
5271 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5272 tcg_gen_br(l2);
5273 gen_set_label(l1);
5274 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5275 gen_load_spr(t2, SPR_MQ);
5276 tcg_gen_andc_tl(t1, t2, t1);
5277 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5278 gen_set_label(l2);
5279 tcg_temp_free(t0);
5280 tcg_temp_free(t1);
5281 tcg_temp_free(t2);
5282 if (unlikely(Rc(ctx->opcode) != 0))
5283 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5284 }
5285
5286 /* slq - slq. */
5287 static void gen_slq(DisasContext *ctx)
5288 {
5289 int l1 = gen_new_label();
5290 TCGv t0 = tcg_temp_new();
5291 TCGv t1 = tcg_temp_new();
5292 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5293 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5294 tcg_gen_subfi_tl(t1, 32, t1);
5295 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5296 tcg_gen_or_tl(t1, t0, t1);
5297 gen_store_spr(SPR_MQ, t1);
5298 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5299 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5300 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5301 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5302 gen_set_label(l1);
5303 tcg_temp_free(t0);
5304 tcg_temp_free(t1);
5305 if (unlikely(Rc(ctx->opcode) != 0))
5306 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5307 }
5308
5309 /* sraiq - sraiq. */
5310 static void gen_sraiq(DisasContext *ctx)
5311 {
5312 int sh = SH(ctx->opcode);
5313 int l1 = gen_new_label();
5314 TCGv t0 = tcg_temp_new();
5315 TCGv t1 = tcg_temp_new();
5316 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5317 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5318 tcg_gen_or_tl(t0, t0, t1);
5319 gen_store_spr(SPR_MQ, t0);
5320 tcg_gen_movi_tl(cpu_ca, 0);
5321 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5322 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5323 tcg_gen_movi_tl(cpu_ca, 1);
5324 gen_set_label(l1);
5325 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5326 tcg_temp_free(t0);
5327 tcg_temp_free(t1);
5328 if (unlikely(Rc(ctx->opcode) != 0))
5329 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5330 }
5331
5332 /* sraq - sraq. */
5333 static void gen_sraq(DisasContext *ctx)
5334 {
5335 int l1 = gen_new_label();
5336 int l2 = gen_new_label();
5337 TCGv t0 = tcg_temp_new();
5338 TCGv t1 = tcg_temp_local_new();
5339 TCGv t2 = tcg_temp_local_new();
5340 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5341 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5342 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5343 tcg_gen_subfi_tl(t2, 32, t2);
5344 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5345 tcg_gen_or_tl(t0, t0, t2);
5346 gen_store_spr(SPR_MQ, t0);
5347 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5348 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5349 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5350 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5351 gen_set_label(l1);
5352 tcg_temp_free(t0);
5353 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5354 tcg_gen_movi_tl(cpu_ca, 0);
5355 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5356 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5357 tcg_gen_movi_tl(cpu_ca, 1);
5358 gen_set_label(l2);
5359 tcg_temp_free(t1);
5360 tcg_temp_free(t2);
5361 if (unlikely(Rc(ctx->opcode) != 0))
5362 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5363 }
5364
5365 /* sre - sre. */
5366 static void gen_sre(DisasContext *ctx)
5367 {
5368 TCGv t0 = tcg_temp_new();
5369 TCGv t1 = tcg_temp_new();
5370 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5371 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5372 tcg_gen_subfi_tl(t1, 32, t1);
5373 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5374 tcg_gen_or_tl(t1, t0, t1);
5375 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5376 gen_store_spr(SPR_MQ, t1);
5377 tcg_temp_free(t0);
5378 tcg_temp_free(t1);
5379 if (unlikely(Rc(ctx->opcode) != 0))
5380 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5381 }
5382
5383 /* srea - srea. */
5384 static void gen_srea(DisasContext *ctx)
5385 {
5386 TCGv t0 = tcg_temp_new();
5387 TCGv t1 = tcg_temp_new();
5388 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5389 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5390 gen_store_spr(SPR_MQ, t0);
5391 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5392 tcg_temp_free(t0);
5393 tcg_temp_free(t1);
5394 if (unlikely(Rc(ctx->opcode) != 0))
5395 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5396 }
5397
5398 /* sreq */
5399 static void gen_sreq(DisasContext *ctx)
5400 {
5401 TCGv t0 = tcg_temp_new();
5402 TCGv t1 = tcg_temp_new();
5403 TCGv t2 = tcg_temp_new();
5404 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5405 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5406 tcg_gen_shr_tl(t1, t1, t0);
5407 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5408 gen_load_spr(t2, SPR_MQ);
5409 gen_store_spr(SPR_MQ, t0);
5410 tcg_gen_and_tl(t0, t0, t1);
5411 tcg_gen_andc_tl(t2, t2, t1);
5412 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5413 tcg_temp_free(t0);
5414 tcg_temp_free(t1);
5415 tcg_temp_free(t2);
5416 if (unlikely(Rc(ctx->opcode) != 0))
5417 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5418 }
5419
5420 /* sriq */
5421 static void gen_sriq(DisasContext *ctx)
5422 {
5423 int sh = SH(ctx->opcode);
5424 TCGv t0 = tcg_temp_new();
5425 TCGv t1 = tcg_temp_new();
5426 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5427 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5428 tcg_gen_or_tl(t1, t0, t1);
5429 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5430 gen_store_spr(SPR_MQ, t1);
5431 tcg_temp_free(t0);
5432 tcg_temp_free(t1);
5433 if (unlikely(Rc(ctx->opcode) != 0))
5434 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5435 }
5436
5437 /* srliq */
5438 static void gen_srliq(DisasContext *ctx)
5439 {
5440 int sh = SH(ctx->opcode);
5441 TCGv t0 = tcg_temp_new();
5442 TCGv t1 = tcg_temp_new();
5443 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5444 gen_load_spr(t1, SPR_MQ);
5445 gen_store_spr(SPR_MQ, t0);
5446 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5447 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5448 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5449 tcg_temp_free(t0);
5450 tcg_temp_free(t1);
5451 if (unlikely(Rc(ctx->opcode) != 0))
5452 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5453 }
5454
5455 /* srlq */
5456 static void gen_srlq(DisasContext *ctx)
5457 {
5458 int l1 = gen_new_label();
5459 int l2 = gen_new_label();
5460 TCGv t0 = tcg_temp_local_new();
5461 TCGv t1 = tcg_temp_local_new();
5462 TCGv t2 = tcg_temp_local_new();
5463 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5464 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5465 tcg_gen_shr_tl(t2, t1, t2);
5466 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5467 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5468 gen_load_spr(t0, SPR_MQ);
5469 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5470 tcg_gen_br(l2);
5471 gen_set_label(l1);
5472 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5473 tcg_gen_and_tl(t0, t0, t2);
5474 gen_load_spr(t1, SPR_MQ);
5475 tcg_gen_andc_tl(t1, t1, t2);
5476 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5477 gen_set_label(l2);
5478 tcg_temp_free(t0);
5479 tcg_temp_free(t1);
5480 tcg_temp_free(t2);
5481 if (unlikely(Rc(ctx->opcode) != 0))
5482 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5483 }
5484
5485 /* srq */
5486 static void gen_srq(DisasContext *ctx)
5487 {
5488 int l1 = gen_new_label();
5489 TCGv t0 = tcg_temp_new();
5490 TCGv t1 = tcg_temp_new();
5491 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5492 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5493 tcg_gen_subfi_tl(t1, 32, t1);
5494 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5495 tcg_gen_or_tl(t1, t0, t1);
5496 gen_store_spr(SPR_MQ, t1);
5497 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5498 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5499 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5500 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5501 gen_set_label(l1);
5502 tcg_temp_free(t0);
5503 tcg_temp_free(t1);
5504 if (unlikely(Rc(ctx->opcode) != 0))
5505 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5506 }
5507
5508 /* PowerPC 602 specific instructions */
5509
5510 /* dsa */
5511 static void gen_dsa(DisasContext *ctx)
5512 {
5513 /* XXX: TODO */
5514 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5515 }
5516
5517 /* esa */
5518 static void gen_esa(DisasContext *ctx)
5519 {
5520 /* XXX: TODO */
5521 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5522 }
5523
5524 /* mfrom */
5525 static void gen_mfrom(DisasContext *ctx)
5526 {
5527 #if defined(CONFIG_USER_ONLY)
5528 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5529 #else
5530 if (unlikely(!ctx->mem_idx)) {
5531 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5532 return;
5533 }
5534 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5535 #endif
5536 }
5537
5538 /* 602 - 603 - G2 TLB management */
5539
5540 /* tlbld */
5541 static void gen_tlbld_6xx(DisasContext *ctx)
5542 {
5543 #if defined(CONFIG_USER_ONLY)
5544 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5545 #else
5546 if (unlikely(!ctx->mem_idx)) {
5547 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5548 return;
5549 }
5550 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5551 #endif
5552 }
5553
5554 /* tlbli */
5555 static void gen_tlbli_6xx(DisasContext *ctx)
5556 {
5557 #if defined(CONFIG_USER_ONLY)
5558 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5559 #else
5560 if (unlikely(!ctx->mem_idx)) {
5561 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5562 return;
5563 }
5564 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5565 #endif
5566 }
5567
5568 /* 74xx TLB management */
5569
5570 /* tlbld */
5571 static void gen_tlbld_74xx(DisasContext *ctx)
5572 {
5573 #if defined(CONFIG_USER_ONLY)
5574 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5575 #else
5576 if (unlikely(!ctx->mem_idx)) {
5577 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5578 return;
5579 }
5580 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5581 #endif
5582 }
5583
5584 /* tlbli */
5585 static void gen_tlbli_74xx(DisasContext *ctx)
5586 {
5587 #if defined(CONFIG_USER_ONLY)
5588 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5589 #else
5590 if (unlikely(!ctx->mem_idx)) {
5591 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5592 return;
5593 }
5594 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5595 #endif
5596 }
5597
5598 /* POWER instructions not in PowerPC 601 */
5599
5600 /* clf */
5601 static void gen_clf(DisasContext *ctx)
5602 {
5603 /* Cache line flush: implemented as no-op */
5604 }
5605
5606 /* cli */
5607 static void gen_cli(DisasContext *ctx)
5608 {
5609 /* Cache line invalidate: privileged and treated as no-op */
5610 #if defined(CONFIG_USER_ONLY)
5611 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5612 #else
5613 if (unlikely(!ctx->mem_idx)) {
5614 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5615 return;
5616 }
5617 #endif
5618 }
5619
5620 /* dclst */
5621 static void gen_dclst(DisasContext *ctx)
5622 {
5623 /* Data cache line store: treated as no-op */
5624 }
5625
5626 static void gen_mfsri(DisasContext *ctx)
5627 {
5628 #if defined(CONFIG_USER_ONLY)
5629 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5630 #else
5631 int ra = rA(ctx->opcode);
5632 int rd = rD(ctx->opcode);
5633 TCGv t0;
5634 if (unlikely(!ctx->mem_idx)) {
5635 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5636 return;
5637 }
5638 t0 = tcg_temp_new();
5639 gen_addr_reg_index(ctx, t0);
5640 tcg_gen_shri_tl(t0, t0, 28);
5641 tcg_gen_andi_tl(t0, t0, 0xF);
5642 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5643 tcg_temp_free(t0);
5644 if (ra != 0 && ra != rd)
5645 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5646 #endif
5647 }
5648
5649 static void gen_rac(DisasContext *ctx)
5650 {
5651 #if defined(CONFIG_USER_ONLY)
5652 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5653 #else
5654 TCGv t0;
5655 if (unlikely(!ctx->mem_idx)) {
5656 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5657 return;
5658 }
5659 t0 = tcg_temp_new();
5660 gen_addr_reg_index(ctx, t0);
5661 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5662 tcg_temp_free(t0);
5663 #endif
5664 }
5665
5666 static void gen_rfsvc(DisasContext *ctx)
5667 {
5668 #if defined(CONFIG_USER_ONLY)
5669 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5670 #else
5671 if (unlikely(!ctx->mem_idx)) {
5672 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5673 return;
5674 }
5675 gen_helper_rfsvc(cpu_env);
5676 gen_sync_exception(ctx);
5677 #endif
5678 }
5679
5680 /* svc is not implemented for now */
5681
5682 /* POWER2 specific instructions */
5683 /* Quad manipulation (load/store two floats at a time) */
5684
5685 /* lfq */
5686 static void gen_lfq(DisasContext *ctx)
5687 {
5688 int rd = rD(ctx->opcode);
5689 TCGv t0;
5690 gen_set_access_type(ctx, ACCESS_FLOAT);
5691 t0 = tcg_temp_new();
5692 gen_addr_imm_index(ctx, t0, 0);
5693 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5694 gen_addr_add(ctx, t0, t0, 8);
5695 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5696 tcg_temp_free(t0);
5697 }
5698
5699 /* lfqu */
5700 static void gen_lfqu(DisasContext *ctx)
5701 {
5702 int ra = rA(ctx->opcode);
5703 int rd = rD(ctx->opcode);
5704 TCGv t0, t1;
5705 gen_set_access_type(ctx, ACCESS_FLOAT);
5706 t0 = tcg_temp_new();
5707 t1 = tcg_temp_new();
5708 gen_addr_imm_index(ctx, t0, 0);
5709 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5710 gen_addr_add(ctx, t1, t0, 8);
5711 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5712 if (ra != 0)
5713 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5714 tcg_temp_free(t0);
5715 tcg_temp_free(t1);
5716 }
5717
5718 /* lfqux */
5719 static void gen_lfqux(DisasContext *ctx)
5720 {
5721 int ra = rA(ctx->opcode);
5722 int rd = rD(ctx->opcode);
5723 gen_set_access_type(ctx, ACCESS_FLOAT);
5724 TCGv t0, t1;
5725 t0 = tcg_temp_new();
5726 gen_addr_reg_index(ctx, t0);
5727 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5728 t1 = tcg_temp_new();
5729 gen_addr_add(ctx, t1, t0, 8);
5730 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5731 tcg_temp_free(t1);
5732 if (ra != 0)
5733 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5734 tcg_temp_free(t0);
5735 }
5736
5737 /* lfqx */
5738 static void gen_lfqx(DisasContext *ctx)
5739 {
5740 int rd = rD(ctx->opcode);
5741 TCGv t0;
5742 gen_set_access_type(ctx, ACCESS_FLOAT);
5743 t0 = tcg_temp_new();
5744 gen_addr_reg_index(ctx, t0);
5745 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5746 gen_addr_add(ctx, t0, t0, 8);
5747 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5748 tcg_temp_free(t0);
5749 }
5750
5751 /* stfq */
5752 static void gen_stfq(DisasContext *ctx)
5753 {
5754 int rd = rD(ctx->opcode);
5755 TCGv t0;
5756 gen_set_access_type(ctx, ACCESS_FLOAT);
5757 t0 = tcg_temp_new();
5758 gen_addr_imm_index(ctx, t0, 0);
5759 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5760 gen_addr_add(ctx, t0, t0, 8);
5761 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5762 tcg_temp_free(t0);
5763 }
5764
5765 /* stfqu */
5766 static void gen_stfqu(DisasContext *ctx)
5767 {
5768 int ra = rA(ctx->opcode);
5769 int rd = rD(ctx->opcode);
5770 TCGv t0, t1;
5771 gen_set_access_type(ctx, ACCESS_FLOAT);
5772 t0 = tcg_temp_new();
5773 gen_addr_imm_index(ctx, t0, 0);
5774 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5775 t1 = tcg_temp_new();
5776 gen_addr_add(ctx, t1, t0, 8);
5777 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5778 tcg_temp_free(t1);
5779 if (ra != 0)
5780 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5781 tcg_temp_free(t0);
5782 }
5783
5784 /* stfqux */
5785 static void gen_stfqux(DisasContext *ctx)
5786 {
5787 int ra = rA(ctx->opcode);
5788 int rd = rD(ctx->opcode);
5789 TCGv t0, t1;
5790 gen_set_access_type(ctx, ACCESS_FLOAT);
5791 t0 = tcg_temp_new();
5792 gen_addr_reg_index(ctx, t0);
5793 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5794 t1 = tcg_temp_new();
5795 gen_addr_add(ctx, t1, t0, 8);
5796 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5797 tcg_temp_free(t1);
5798 if (ra != 0)
5799 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5800 tcg_temp_free(t0);
5801 }
5802
5803 /* stfqx */
5804 static void gen_stfqx(DisasContext *ctx)
5805 {
5806 int rd = rD(ctx->opcode);
5807 TCGv t0;
5808 gen_set_access_type(ctx, ACCESS_FLOAT);
5809 t0 = tcg_temp_new();
5810 gen_addr_reg_index(ctx, t0);
5811 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5812 gen_addr_add(ctx, t0, t0, 8);
5813 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5814 tcg_temp_free(t0);
5815 }
5816
5817 /* BookE specific instructions */
5818
5819 /* XXX: not implemented on 440 ? */
5820 static void gen_mfapidi(DisasContext *ctx)
5821 {
5822 /* XXX: TODO */
5823 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5824 }
5825
5826 /* XXX: not implemented on 440 ? */
5827 static void gen_tlbiva(DisasContext *ctx)
5828 {
5829 #if defined(CONFIG_USER_ONLY)
5830 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5831 #else
5832 TCGv t0;
5833 if (unlikely(!ctx->mem_idx)) {
5834 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5835 return;
5836 }
5837 t0 = tcg_temp_new();
5838 gen_addr_reg_index(ctx, t0);
5839 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5840 tcg_temp_free(t0);
5841 #endif
5842 }
5843
5844 /* All 405 MAC instructions are translated here */
5845 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5846 int ra, int rb, int rt, int Rc)
5847 {
5848 TCGv t0, t1;
5849
5850 t0 = tcg_temp_local_new();
5851 t1 = tcg_temp_local_new();
5852
5853 switch (opc3 & 0x0D) {
5854 case 0x05:
5855 /* macchw - macchw. - macchwo - macchwo. */
5856 /* macchws - macchws. - macchwso - macchwso. */
5857 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5858 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5859 /* mulchw - mulchw. */
5860 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5861 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5862 tcg_gen_ext16s_tl(t1, t1);
5863 break;
5864 case 0x04:
5865 /* macchwu - macchwu. - macchwuo - macchwuo. */
5866 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5867 /* mulchwu - mulchwu. */
5868 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5869 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5870 tcg_gen_ext16u_tl(t1, t1);
5871 break;
5872 case 0x01:
5873 /* machhw - machhw. - machhwo - machhwo. */
5874 /* machhws - machhws. - machhwso - machhwso. */
5875 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5876 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5877 /* mulhhw - mulhhw. */
5878 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5879 tcg_gen_ext16s_tl(t0, t0);
5880 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5881 tcg_gen_ext16s_tl(t1, t1);
5882 break;
5883 case 0x00:
5884 /* machhwu - machhwu. - machhwuo - machhwuo. */
5885 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5886 /* mulhhwu - mulhhwu. */
5887 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5888 tcg_gen_ext16u_tl(t0, t0);
5889 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5890 tcg_gen_ext16u_tl(t1, t1);
5891 break;
5892 case 0x0D:
5893 /* maclhw - maclhw. - maclhwo - maclhwo. */
5894 /* maclhws - maclhws. - maclhwso - maclhwso. */
5895 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5896 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5897 /* mullhw - mullhw. */
5898 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5899 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5900 break;
5901 case 0x0C:
5902 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5903 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5904 /* mullhwu - mullhwu. */
5905 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5906 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5907 break;
5908 }
5909 if (opc2 & 0x04) {
5910 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5911 tcg_gen_mul_tl(t1, t0, t1);
5912 if (opc2 & 0x02) {
5913 /* nmultiply-and-accumulate (0x0E) */
5914 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5915 } else {
5916 /* multiply-and-accumulate (0x0C) */
5917 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5918 }
5919
5920 if (opc3 & 0x12) {
5921 /* Check overflow and/or saturate */
5922 int l1 = gen_new_label();
5923
5924 if (opc3 & 0x10) {
5925 /* Start with XER OV disabled, the most likely case */
5926 tcg_gen_movi_tl(cpu_ov, 0);
5927 }
5928 if (opc3 & 0x01) {
5929 /* Signed */
5930 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5931 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5932 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5933 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5934 if (opc3 & 0x02) {
5935 /* Saturate */
5936 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5937 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5938 }
5939 } else {
5940 /* Unsigned */
5941 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5942 if (opc3 & 0x02) {
5943 /* Saturate */
5944 tcg_gen_movi_tl(t0, UINT32_MAX);
5945 }
5946 }
5947 if (opc3 & 0x10) {
5948 /* Check overflow */
5949 tcg_gen_movi_tl(cpu_ov, 1);
5950 tcg_gen_movi_tl(cpu_so, 1);
5951 }
5952 gen_set_label(l1);
5953 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5954 }
5955 } else {
5956 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5957 }
5958 tcg_temp_free(t0);
5959 tcg_temp_free(t1);
5960 if (unlikely(Rc) != 0) {
5961 /* Update Rc0 */
5962 gen_set_Rc0(ctx, cpu_gpr[rt]);
5963 }
5964 }
5965
5966 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5967 static void glue(gen_, name)(DisasContext *ctx) \
5968 { \
5969 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5970 rD(ctx->opcode), Rc(ctx->opcode)); \
5971 }
5972
5973 /* macchw - macchw. */
5974 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5975 /* macchwo - macchwo. */
5976 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5977 /* macchws - macchws. */
5978 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5979 /* macchwso - macchwso. */
5980 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5981 /* macchwsu - macchwsu. */
5982 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5983 /* macchwsuo - macchwsuo. */
5984 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5985 /* macchwu - macchwu. */
5986 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5987 /* macchwuo - macchwuo. */
5988 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5989 /* machhw - machhw. */
5990 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5991 /* machhwo - machhwo. */
5992 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5993 /* machhws - machhws. */
5994 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5995 /* machhwso - machhwso. */
5996 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5997 /* machhwsu - machhwsu. */
5998 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5999 /* machhwsuo - machhwsuo. */
6000 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6001 /* machhwu - machhwu. */
6002 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6003 /* machhwuo - machhwuo. */
6004 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6005 /* maclhw - maclhw. */
6006 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6007 /* maclhwo - maclhwo. */
6008 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6009 /* maclhws - maclhws. */
6010 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6011 /* maclhwso - maclhwso. */
6012 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6013 /* maclhwu - maclhwu. */
6014 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6015 /* maclhwuo - maclhwuo. */
6016 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6017 /* maclhwsu - maclhwsu. */
6018 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6019 /* maclhwsuo - maclhwsuo. */
6020 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6021 /* nmacchw - nmacchw. */
6022 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6023 /* nmacchwo - nmacchwo. */
6024 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6025 /* nmacchws - nmacchws. */
6026 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6027 /* nmacchwso - nmacchwso. */
6028 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6029 /* nmachhw - nmachhw. */
6030 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6031 /* nmachhwo - nmachhwo. */
6032 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6033 /* nmachhws - nmachhws. */
6034 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6035 /* nmachhwso - nmachhwso. */
6036 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6037 /* nmaclhw - nmaclhw. */
6038 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6039 /* nmaclhwo - nmaclhwo. */
6040 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6041 /* nmaclhws - nmaclhws. */
6042 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6043 /* nmaclhwso - nmaclhwso. */
6044 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6045
6046 /* mulchw - mulchw. */
6047 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6048 /* mulchwu - mulchwu. */
6049 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6050 /* mulhhw - mulhhw. */
6051 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6052 /* mulhhwu - mulhhwu. */
6053 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6054 /* mullhw - mullhw. */
6055 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6056 /* mullhwu - mullhwu. */
6057 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6058
6059 /* mfdcr */
6060 static void gen_mfdcr(DisasContext *ctx)
6061 {
6062 #if defined(CONFIG_USER_ONLY)
6063 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6064 #else
6065 TCGv dcrn;
6066 if (unlikely(!ctx->mem_idx)) {
6067 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6068 return;
6069 }
6070 /* NIP cannot be restored if the memory exception comes from an helper */
6071 gen_update_nip(ctx, ctx->nip - 4);
6072 dcrn = tcg_const_tl(SPR(ctx->opcode));
6073 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6074 tcg_temp_free(dcrn);
6075 #endif
6076 }
6077
6078 /* mtdcr */
6079 static void gen_mtdcr(DisasContext *ctx)
6080 {
6081 #if defined(CONFIG_USER_ONLY)
6082 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6083 #else
6084 TCGv dcrn;
6085 if (unlikely(!ctx->mem_idx)) {
6086 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6087 return;
6088 }
6089 /* NIP cannot be restored if the memory exception comes from an helper */
6090 gen_update_nip(ctx, ctx->nip - 4);
6091 dcrn = tcg_const_tl(SPR(ctx->opcode));
6092 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6093 tcg_temp_free(dcrn);
6094 #endif
6095 }
6096
6097 /* mfdcrx */
6098 /* XXX: not implemented on 440 ? */
6099 static void gen_mfdcrx(DisasContext *ctx)
6100 {
6101 #if defined(CONFIG_USER_ONLY)
6102 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6103 #else
6104 if (unlikely(!ctx->mem_idx)) {
6105 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6106 return;
6107 }
6108 /* NIP cannot be restored if the memory exception comes from an helper */
6109 gen_update_nip(ctx, ctx->nip - 4);
6110 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6111 cpu_gpr[rA(ctx->opcode)]);
6112 /* Note: Rc update flag set leads to undefined state of Rc0 */
6113 #endif
6114 }
6115
6116 /* mtdcrx */
6117 /* XXX: not implemented on 440 ? */
6118 static void gen_mtdcrx(DisasContext *ctx)
6119 {
6120 #if defined(CONFIG_USER_ONLY)
6121 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6122 #else
6123 if (unlikely(!ctx->mem_idx)) {
6124 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6125 return;
6126 }
6127 /* NIP cannot be restored if the memory exception comes from an helper */
6128 gen_update_nip(ctx, ctx->nip - 4);
6129 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6130 cpu_gpr[rS(ctx->opcode)]);
6131 /* Note: Rc update flag set leads to undefined state of Rc0 */
6132 #endif
6133 }
6134
6135 /* mfdcrux (PPC 460) : user-mode access to DCR */
6136 static void gen_mfdcrux(DisasContext *ctx)
6137 {
6138 /* NIP cannot be restored if the memory exception comes from an helper */
6139 gen_update_nip(ctx, ctx->nip - 4);
6140 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6141 cpu_gpr[rA(ctx->opcode)]);
6142 /* Note: Rc update flag set leads to undefined state of Rc0 */
6143 }
6144
6145 /* mtdcrux (PPC 460) : user-mode access to DCR */
6146 static void gen_mtdcrux(DisasContext *ctx)
6147 {
6148 /* NIP cannot be restored if the memory exception comes from an helper */
6149 gen_update_nip(ctx, ctx->nip - 4);
6150 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6151 cpu_gpr[rS(ctx->opcode)]);
6152 /* Note: Rc update flag set leads to undefined state of Rc0 */
6153 }
6154
6155 /* dccci */
6156 static void gen_dccci(DisasContext *ctx)
6157 {
6158 #if defined(CONFIG_USER_ONLY)
6159 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6160 #else
6161 if (unlikely(!ctx->mem_idx)) {
6162 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6163 return;
6164 }
6165 /* interpreted as no-op */
6166 #endif
6167 }
6168
6169 /* dcread */
6170 static void gen_dcread(DisasContext *ctx)
6171 {
6172 #if defined(CONFIG_USER_ONLY)
6173 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6174 #else
6175 TCGv EA, val;
6176 if (unlikely(!ctx->mem_idx)) {
6177 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6178 return;
6179 }
6180 gen_set_access_type(ctx, ACCESS_CACHE);
6181 EA = tcg_temp_new();
6182 gen_addr_reg_index(ctx, EA);
6183 val = tcg_temp_new();
6184 gen_qemu_ld32u(ctx, val, EA);
6185 tcg_temp_free(val);
6186 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6187 tcg_temp_free(EA);
6188 #endif
6189 }
6190
6191 /* icbt */
6192 static void gen_icbt_40x(DisasContext *ctx)
6193 {
6194 /* interpreted as no-op */
6195 /* XXX: specification say this is treated as a load by the MMU
6196 * but does not generate any exception
6197 */
6198 }
6199
6200 /* iccci */
6201 static void gen_iccci(DisasContext *ctx)
6202 {
6203 #if defined(CONFIG_USER_ONLY)
6204 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6205 #else
6206 if (unlikely(!ctx->mem_idx)) {
6207 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6208 return;
6209 }
6210 /* interpreted as no-op */
6211 #endif
6212 }
6213
6214 /* icread */
6215 static void gen_icread(DisasContext *ctx)
6216 {
6217 #if defined(CONFIG_USER_ONLY)
6218 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6219 #else
6220 if (unlikely(!ctx->mem_idx)) {
6221 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6222 return;
6223 }
6224 /* interpreted as no-op */
6225 #endif
6226 }
6227
6228 /* rfci (mem_idx only) */
6229 static void gen_rfci_40x(DisasContext *ctx)
6230 {
6231 #if defined(CONFIG_USER_ONLY)
6232 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6233 #else
6234 if (unlikely(!ctx->mem_idx)) {
6235 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6236 return;
6237 }
6238 /* Restore CPU state */
6239 gen_helper_40x_rfci(cpu_env);
6240 gen_sync_exception(ctx);
6241 #endif
6242 }
6243
6244 static void gen_rfci(DisasContext *ctx)
6245 {
6246 #if defined(CONFIG_USER_ONLY)
6247 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6248 #else
6249 if (unlikely(!ctx->mem_idx)) {
6250 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6251 return;
6252 }
6253 /* Restore CPU state */
6254 gen_helper_rfci(cpu_env);
6255 gen_sync_exception(ctx);
6256 #endif
6257 }
6258
6259 /* BookE specific */
6260
6261 /* XXX: not implemented on 440 ? */
6262 static void gen_rfdi(DisasContext *ctx)
6263 {
6264 #if defined(CONFIG_USER_ONLY)
6265 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6266 #else
6267 if (unlikely(!ctx->mem_idx)) {
6268 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6269 return;
6270 }
6271 /* Restore CPU state */
6272 gen_helper_rfdi(cpu_env);
6273 gen_sync_exception(ctx);
6274 #endif
6275 }
6276
6277 /* XXX: not implemented on 440 ? */
6278 static void gen_rfmci(DisasContext *ctx)
6279 {
6280 #if defined(CONFIG_USER_ONLY)
6281 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6282 #else
6283 if (unlikely(!ctx->mem_idx)) {
6284 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6285 return;
6286 }
6287 /* Restore CPU state */
6288 gen_helper_rfmci(cpu_env);
6289 gen_sync_exception(ctx);
6290 #endif
6291 }
6292
6293 /* TLB management - PowerPC 405 implementation */
6294
6295 /* tlbre */
6296 static void gen_tlbre_40x(DisasContext *ctx)
6297 {
6298 #if defined(CONFIG_USER_ONLY)
6299 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6300 #else
6301 if (unlikely(!ctx->mem_idx)) {
6302 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6303 return;
6304 }
6305 switch (rB(ctx->opcode)) {
6306 case 0:
6307 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6308 cpu_gpr[rA(ctx->opcode)]);
6309 break;
6310 case 1:
6311 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6312 cpu_gpr[rA(ctx->opcode)]);
6313 break;
6314 default:
6315 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6316 break;
6317 }
6318 #endif
6319 }
6320
6321 /* tlbsx - tlbsx. */
6322 static void gen_tlbsx_40x(DisasContext *ctx)
6323 {
6324 #if defined(CONFIG_USER_ONLY)
6325 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6326 #else
6327 TCGv t0;
6328 if (unlikely(!ctx->mem_idx)) {
6329 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6330 return;
6331 }
6332 t0 = tcg_temp_new();
6333 gen_addr_reg_index(ctx, t0);
6334 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6335 tcg_temp_free(t0);
6336 if (Rc(ctx->opcode)) {
6337 int l1 = gen_new_label();
6338 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6339 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6340 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6341 gen_set_label(l1);
6342 }
6343 #endif
6344 }
6345
6346 /* tlbwe */
6347 static void gen_tlbwe_40x(DisasContext *ctx)
6348 {
6349 #if defined(CONFIG_USER_ONLY)
6350 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6351 #else
6352 if (unlikely(!ctx->mem_idx)) {
6353 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6354 return;
6355 }
6356 switch (rB(ctx->opcode)) {
6357 case 0:
6358 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6359 cpu_gpr[rS(ctx->opcode)]);
6360 break;
6361 case 1:
6362 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6363 cpu_gpr[rS(ctx->opcode)]);
6364 break;
6365 default:
6366 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6367 break;
6368 }
6369 #endif
6370 }
6371
6372 /* TLB management - PowerPC 440 implementation */
6373
6374 /* tlbre */
6375 static void gen_tlbre_440(DisasContext *ctx)
6376 {
6377 #if defined(CONFIG_USER_ONLY)
6378 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6379 #else
6380 if (unlikely(!ctx->mem_idx)) {
6381 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6382 return;
6383 }
6384 switch (rB(ctx->opcode)) {
6385 case 0:
6386 case 1:
6387 case 2:
6388 {
6389 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6390 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6391 t0, cpu_gpr[rA(ctx->opcode)]);
6392 tcg_temp_free_i32(t0);
6393 }
6394 break;
6395 default:
6396 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6397 break;
6398 }
6399 #endif
6400 }
6401
6402 /* tlbsx - tlbsx. */
6403 static void gen_tlbsx_440(DisasContext *ctx)
6404 {
6405 #if defined(CONFIG_USER_ONLY)
6406 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6407 #else
6408 TCGv t0;
6409 if (unlikely(!ctx->mem_idx)) {
6410 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6411 return;
6412 }
6413 t0 = tcg_temp_new();
6414 gen_addr_reg_index(ctx, t0);
6415 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6416 tcg_temp_free(t0);
6417 if (Rc(ctx->opcode)) {
6418 int l1 = gen_new_label();
6419 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6420 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6421 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6422 gen_set_label(l1);
6423 }
6424 #endif
6425 }
6426
6427 /* tlbwe */
6428 static void gen_tlbwe_440(DisasContext *ctx)
6429 {
6430 #if defined(CONFIG_USER_ONLY)
6431 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6432 #else
6433 if (unlikely(!ctx->mem_idx)) {
6434 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6435 return;
6436 }
6437 switch (rB(ctx->opcode)) {
6438 case 0:
6439 case 1:
6440 case 2:
6441 {
6442 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6443 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6444 cpu_gpr[rS(ctx->opcode)]);
6445 tcg_temp_free_i32(t0);
6446 }
6447 break;
6448 default:
6449 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6450 break;
6451 }
6452 #endif
6453 }
6454
6455 /* TLB management - PowerPC BookE 2.06 implementation */
6456
6457 /* tlbre */
6458 static void gen_tlbre_booke206(DisasContext *ctx)
6459 {
6460 #if defined(CONFIG_USER_ONLY)
6461 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6462 #else
6463 if (unlikely(!ctx->mem_idx)) {
6464 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6465 return;
6466 }
6467
6468 gen_helper_booke206_tlbre(cpu_env);
6469 #endif
6470 }
6471
6472 /* tlbsx - tlbsx. */
6473 static void gen_tlbsx_booke206(DisasContext *ctx)
6474 {
6475 #if defined(CONFIG_USER_ONLY)
6476 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6477 #else
6478 TCGv t0;
6479 if (unlikely(!ctx->mem_idx)) {
6480 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6481 return;
6482 }
6483
6484 if (rA(ctx->opcode)) {
6485 t0 = tcg_temp_new();
6486 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6487 } else {
6488 t0 = tcg_const_tl(0);
6489 }
6490
6491 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6492 gen_helper_booke206_tlbsx(cpu_env, t0);
6493 #endif
6494 }
6495
6496 /* tlbwe */
6497 static void gen_tlbwe_booke206(DisasContext *ctx)
6498 {
6499 #if defined(CONFIG_USER_ONLY)
6500 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6501 #else
6502 if (unlikely(!ctx->mem_idx)) {
6503 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6504 return;
6505 }
6506 gen_update_nip(ctx, ctx->nip - 4);
6507 gen_helper_booke206_tlbwe(cpu_env);
6508 #endif
6509 }
6510
6511 static void gen_tlbivax_booke206(DisasContext *ctx)
6512 {
6513 #if defined(CONFIG_USER_ONLY)
6514 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6515 #else
6516 TCGv t0;
6517 if (unlikely(!ctx->mem_idx)) {
6518 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6519 return;
6520 }
6521
6522 t0 = tcg_temp_new();
6523 gen_addr_reg_index(ctx, t0);
6524
6525 gen_helper_booke206_tlbivax(cpu_env, t0);
6526 #endif
6527 }
6528
6529 static void gen_tlbilx_booke206(DisasContext *ctx)
6530 {
6531 #if defined(CONFIG_USER_ONLY)
6532 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6533 #else
6534 TCGv t0;
6535 if (unlikely(!ctx->mem_idx)) {
6536 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6537 return;
6538 }
6539
6540 t0 = tcg_temp_new();
6541 gen_addr_reg_index(ctx, t0);
6542
6543 switch((ctx->opcode >> 21) & 0x3) {
6544 case 0:
6545 gen_helper_booke206_tlbilx0(cpu_env, t0);
6546 break;
6547 case 1:
6548 gen_helper_booke206_tlbilx1(cpu_env, t0);
6549 break;
6550 case 3:
6551 gen_helper_booke206_tlbilx3(cpu_env, t0);
6552 break;
6553 default:
6554 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6555 break;
6556 }
6557
6558 tcg_temp_free(t0);
6559 #endif
6560 }
6561
6562
6563 /* wrtee */
6564 static void gen_wrtee(DisasContext *ctx)
6565 {
6566 #if defined(CONFIG_USER_ONLY)
6567 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6568 #else
6569 TCGv t0;
6570 if (unlikely(!ctx->mem_idx)) {
6571 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6572 return;
6573 }
6574 t0 = tcg_temp_new();
6575 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6576 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6577 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6578 tcg_temp_free(t0);
6579 /* Stop translation to have a chance to raise an exception
6580 * if we just set msr_ee to 1
6581 */
6582 gen_stop_exception(ctx);
6583 #endif
6584 }
6585
6586 /* wrteei */
6587 static void gen_wrteei(DisasContext *ctx)
6588 {
6589 #if defined(CONFIG_USER_ONLY)
6590 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6591 #else
6592 if (unlikely(!ctx->mem_idx)) {
6593 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6594 return;
6595 }
6596 if (ctx->opcode & 0x00008000) {
6597 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6598 /* Stop translation to have a chance to raise an exception */
6599 gen_stop_exception(ctx);
6600 } else {
6601 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6602 }
6603 #endif
6604 }
6605
6606 /* PowerPC 440 specific instructions */
6607
6608 /* dlmzb */
6609 static void gen_dlmzb(DisasContext *ctx)
6610 {
6611 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6612 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6613 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6614 tcg_temp_free_i32(t0);
6615 }
6616
6617 /* mbar replaces eieio on 440 */
6618 static void gen_mbar(DisasContext *ctx)
6619 {
6620 /* interpreted as no-op */
6621 }
6622
6623 /* msync replaces sync on 440 */
6624 static void gen_msync_4xx(DisasContext *ctx)
6625 {
6626 /* interpreted as no-op */
6627 }
6628
6629 /* icbt */
6630 static void gen_icbt_440(DisasContext *ctx)
6631 {
6632 /* interpreted as no-op */
6633 /* XXX: specification say this is treated as a load by the MMU
6634 * but does not generate any exception
6635 */
6636 }
6637
6638 /* Embedded.Processor Control */
6639
6640 static void gen_msgclr(DisasContext *ctx)
6641 {
6642 #if defined(CONFIG_USER_ONLY)
6643 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6644 #else
6645 if (unlikely(ctx->mem_idx == 0)) {
6646 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6647 return;
6648 }
6649
6650 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6651 #endif
6652 }
6653
6654 static void gen_msgsnd(DisasContext *ctx)
6655 {
6656 #if defined(CONFIG_USER_ONLY)
6657 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6658 #else
6659 if (unlikely(ctx->mem_idx == 0)) {
6660 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6661 return;
6662 }
6663
6664 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6665 #endif
6666 }
6667
6668 /*** Altivec vector extension ***/
6669 /* Altivec registers moves */
6670
6671 static inline TCGv_ptr gen_avr_ptr(int reg)
6672 {
6673 TCGv_ptr r = tcg_temp_new_ptr();
6674 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6675 return r;
6676 }
6677
6678 #define GEN_VR_LDX(name, opc2, opc3) \
6679 static void glue(gen_, name)(DisasContext *ctx) \
6680 { \
6681 TCGv EA; \
6682 if (unlikely(!ctx->altivec_enabled)) { \
6683 gen_exception(ctx, POWERPC_EXCP_VPU); \
6684 return; \
6685 } \
6686 gen_set_access_type(ctx, ACCESS_INT); \
6687 EA = tcg_temp_new(); \
6688 gen_addr_reg_index(ctx, EA); \
6689 tcg_gen_andi_tl(EA, EA, ~0xf); \
6690 if (ctx->le_mode) { \
6691 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6692 tcg_gen_addi_tl(EA, EA, 8); \
6693 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6694 } else { \
6695 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6696 tcg_gen_addi_tl(EA, EA, 8); \
6697 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6698 } \
6699 tcg_temp_free(EA); \
6700 }
6701
6702 #define GEN_VR_STX(name, opc2, opc3) \
6703 static void gen_st##name(DisasContext *ctx) \
6704 { \
6705 TCGv EA; \
6706 if (unlikely(!ctx->altivec_enabled)) { \
6707 gen_exception(ctx, POWERPC_EXCP_VPU); \
6708 return; \
6709 } \
6710 gen_set_access_type(ctx, ACCESS_INT); \
6711 EA = tcg_temp_new(); \
6712 gen_addr_reg_index(ctx, EA); \
6713 tcg_gen_andi_tl(EA, EA, ~0xf); \
6714 if (ctx->le_mode) { \
6715 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6716 tcg_gen_addi_tl(EA, EA, 8); \
6717 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6718 } else { \
6719 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6720 tcg_gen_addi_tl(EA, EA, 8); \
6721 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6722 } \
6723 tcg_temp_free(EA); \
6724 }
6725
6726 #define GEN_VR_LVE(name, opc2, opc3) \
6727 static void gen_lve##name(DisasContext *ctx) \
6728 { \
6729 TCGv EA; \
6730 TCGv_ptr rs; \
6731 if (unlikely(!ctx->altivec_enabled)) { \
6732 gen_exception(ctx, POWERPC_EXCP_VPU); \
6733 return; \
6734 } \
6735 gen_set_access_type(ctx, ACCESS_INT); \
6736 EA = tcg_temp_new(); \
6737 gen_addr_reg_index(ctx, EA); \
6738 rs = gen_avr_ptr(rS(ctx->opcode)); \
6739 gen_helper_lve##name(cpu_env, rs, EA); \
6740 tcg_temp_free(EA); \
6741 tcg_temp_free_ptr(rs); \
6742 }
6743
6744 #define GEN_VR_STVE(name, opc2, opc3) \
6745 static void gen_stve##name(DisasContext *ctx) \
6746 { \
6747 TCGv EA; \
6748 TCGv_ptr rs; \
6749 if (unlikely(!ctx->altivec_enabled)) { \
6750 gen_exception(ctx, POWERPC_EXCP_VPU); \
6751 return; \
6752 } \
6753 gen_set_access_type(ctx, ACCESS_INT); \
6754 EA = tcg_temp_new(); \
6755 gen_addr_reg_index(ctx, EA); \
6756 rs = gen_avr_ptr(rS(ctx->opcode)); \
6757 gen_helper_stve##name(cpu_env, rs, EA); \
6758 tcg_temp_free(EA); \
6759 tcg_temp_free_ptr(rs); \
6760 }
6761
6762 GEN_VR_LDX(lvx, 0x07, 0x03);
6763 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6764 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6765
6766 GEN_VR_LVE(bx, 0x07, 0x00);
6767 GEN_VR_LVE(hx, 0x07, 0x01);
6768 GEN_VR_LVE(wx, 0x07, 0x02);
6769
6770 GEN_VR_STX(svx, 0x07, 0x07);
6771 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6772 GEN_VR_STX(svxl, 0x07, 0x0F);
6773
6774 GEN_VR_STVE(bx, 0x07, 0x04);
6775 GEN_VR_STVE(hx, 0x07, 0x05);
6776 GEN_VR_STVE(wx, 0x07, 0x06);
6777
6778 static void gen_lvsl(DisasContext *ctx)
6779 {
6780 TCGv_ptr rd;
6781 TCGv EA;
6782 if (unlikely(!ctx->altivec_enabled)) {
6783 gen_exception(ctx, POWERPC_EXCP_VPU);
6784 return;
6785 }
6786 EA = tcg_temp_new();
6787 gen_addr_reg_index(ctx, EA);
6788 rd = gen_avr_ptr(rD(ctx->opcode));
6789 gen_helper_lvsl(rd, EA);
6790 tcg_temp_free(EA);
6791 tcg_temp_free_ptr(rd);
6792 }
6793
6794 static void gen_lvsr(DisasContext *ctx)
6795 {
6796 TCGv_ptr rd;
6797 TCGv EA;
6798 if (unlikely(!ctx->altivec_enabled)) {
6799 gen_exception(ctx, POWERPC_EXCP_VPU);
6800 return;
6801 }
6802 EA = tcg_temp_new();
6803 gen_addr_reg_index(ctx, EA);
6804 rd = gen_avr_ptr(rD(ctx->opcode));
6805 gen_helper_lvsr(rd, EA);
6806 tcg_temp_free(EA);
6807 tcg_temp_free_ptr(rd);
6808 }
6809
6810 static void gen_mfvscr(DisasContext *ctx)
6811 {
6812 TCGv_i32 t;
6813 if (unlikely(!ctx->altivec_enabled)) {
6814 gen_exception(ctx, POWERPC_EXCP_VPU);
6815 return;
6816 }
6817 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6818 t = tcg_temp_new_i32();
6819 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6820 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6821 tcg_temp_free_i32(t);
6822 }
6823
6824 static void gen_mtvscr(DisasContext *ctx)
6825 {
6826 TCGv_ptr p;
6827 if (unlikely(!ctx->altivec_enabled)) {
6828 gen_exception(ctx, POWERPC_EXCP_VPU);
6829 return;
6830 }
6831 p = gen_avr_ptr(rD(ctx->opcode));
6832 gen_helper_mtvscr(cpu_env, p);
6833 tcg_temp_free_ptr(p);
6834 }
6835
6836 /* Logical operations */
6837 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6838 static void glue(gen_, name)(DisasContext *ctx) \
6839 { \
6840 if (unlikely(!ctx->altivec_enabled)) { \
6841 gen_exception(ctx, POWERPC_EXCP_VPU); \
6842 return; \
6843 } \
6844 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6845 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6846 }
6847
6848 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6849 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6850 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6851 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6852 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6853
6854 #define GEN_VXFORM(name, opc2, opc3) \
6855 static void glue(gen_, name)(DisasContext *ctx) \
6856 { \
6857 TCGv_ptr ra, rb, rd; \
6858 if (unlikely(!ctx->altivec_enabled)) { \
6859 gen_exception(ctx, POWERPC_EXCP_VPU); \
6860 return; \
6861 } \
6862 ra = gen_avr_ptr(rA(ctx->opcode)); \
6863 rb = gen_avr_ptr(rB(ctx->opcode)); \
6864 rd = gen_avr_ptr(rD(ctx->opcode)); \
6865 gen_helper_##name (rd, ra, rb); \
6866 tcg_temp_free_ptr(ra); \
6867 tcg_temp_free_ptr(rb); \
6868 tcg_temp_free_ptr(rd); \
6869 }
6870
6871 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6872 static void glue(gen_, name)(DisasContext *ctx) \
6873 { \
6874 TCGv_ptr ra, rb, rd; \
6875 if (unlikely(!ctx->altivec_enabled)) { \
6876 gen_exception(ctx, POWERPC_EXCP_VPU); \
6877 return; \
6878 } \
6879 ra = gen_avr_ptr(rA(ctx->opcode)); \
6880 rb = gen_avr_ptr(rB(ctx->opcode)); \
6881 rd = gen_avr_ptr(rD(ctx->opcode)); \
6882 gen_helper_##name(cpu_env, rd, ra, rb); \
6883 tcg_temp_free_ptr(ra); \
6884 tcg_temp_free_ptr(rb); \
6885 tcg_temp_free_ptr(rd); \
6886 }
6887
6888 #define GEN_VXFORM3(name, opc2, opc3) \
6889 static void glue(gen_, name)(DisasContext *ctx) \
6890 { \
6891 TCGv_ptr ra, rb, rc, rd; \
6892 if (unlikely(!ctx->altivec_enabled)) { \
6893 gen_exception(ctx, POWERPC_EXCP_VPU); \
6894 return; \
6895 } \
6896 ra = gen_avr_ptr(rA(ctx->opcode)); \
6897 rb = gen_avr_ptr(rB(ctx->opcode)); \
6898 rc = gen_avr_ptr(rC(ctx->opcode)); \
6899 rd = gen_avr_ptr(rD(ctx->opcode)); \
6900 gen_helper_##name(rd, ra, rb, rc); \
6901 tcg_temp_free_ptr(ra); \
6902 tcg_temp_free_ptr(rb); \
6903 tcg_temp_free_ptr(rc); \
6904 tcg_temp_free_ptr(rd); \
6905 }
6906
6907 GEN_VXFORM(vaddubm, 0, 0);
6908 GEN_VXFORM(vadduhm, 0, 1);
6909 GEN_VXFORM(vadduwm, 0, 2);
6910 GEN_VXFORM(vsububm, 0, 16);
6911 GEN_VXFORM(vsubuhm, 0, 17);
6912 GEN_VXFORM(vsubuwm, 0, 18);
6913 GEN_VXFORM(vmaxub, 1, 0);
6914 GEN_VXFORM(vmaxuh, 1, 1);
6915 GEN_VXFORM(vmaxuw, 1, 2);
6916 GEN_VXFORM(vmaxsb, 1, 4);
6917 GEN_VXFORM(vmaxsh, 1, 5);
6918 GEN_VXFORM(vmaxsw, 1, 6);
6919 GEN_VXFORM(vminub, 1, 8);
6920 GEN_VXFORM(vminuh, 1, 9);
6921 GEN_VXFORM(vminuw, 1, 10);
6922 GEN_VXFORM(vminsb, 1, 12);
6923 GEN_VXFORM(vminsh, 1, 13);
6924 GEN_VXFORM(vminsw, 1, 14);
6925 GEN_VXFORM(vavgub, 1, 16);
6926 GEN_VXFORM(vavguh, 1, 17);
6927 GEN_VXFORM(vavguw, 1, 18);
6928 GEN_VXFORM(vavgsb, 1, 20);
6929 GEN_VXFORM(vavgsh, 1, 21);
6930 GEN_VXFORM(vavgsw, 1, 22);
6931 GEN_VXFORM(vmrghb, 6, 0);
6932 GEN_VXFORM(vmrghh, 6, 1);
6933 GEN_VXFORM(vmrghw, 6, 2);
6934 GEN_VXFORM(vmrglb, 6, 4);
6935 GEN_VXFORM(vmrglh, 6, 5);
6936 GEN_VXFORM(vmrglw, 6, 6);
6937 GEN_VXFORM(vmuloub, 4, 0);
6938 GEN_VXFORM(vmulouh, 4, 1);
6939 GEN_VXFORM(vmulosb, 4, 4);
6940 GEN_VXFORM(vmulosh, 4, 5);
6941 GEN_VXFORM(vmuleub, 4, 8);
6942 GEN_VXFORM(vmuleuh, 4, 9);
6943 GEN_VXFORM(vmulesb, 4, 12);
6944 GEN_VXFORM(vmulesh, 4, 13);
6945 GEN_VXFORM(vslb, 2, 4);
6946 GEN_VXFORM(vslh, 2, 5);
6947 GEN_VXFORM(vslw, 2, 6);
6948 GEN_VXFORM(vsrb, 2, 8);
6949 GEN_VXFORM(vsrh, 2, 9);
6950 GEN_VXFORM(vsrw, 2, 10);
6951 GEN_VXFORM(vsrab, 2, 12);
6952 GEN_VXFORM(vsrah, 2, 13);
6953 GEN_VXFORM(vsraw, 2, 14);
6954 GEN_VXFORM(vslo, 6, 16);
6955 GEN_VXFORM(vsro, 6, 17);
6956 GEN_VXFORM(vaddcuw, 0, 6);
6957 GEN_VXFORM(vsubcuw, 0, 22);
6958 GEN_VXFORM_ENV(vaddubs, 0, 8);
6959 GEN_VXFORM_ENV(vadduhs, 0, 9);
6960 GEN_VXFORM_ENV(vadduws, 0, 10);
6961 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6962 GEN_VXFORM_ENV(vaddshs, 0, 13);
6963 GEN_VXFORM_ENV(vaddsws, 0, 14);
6964 GEN_VXFORM_ENV(vsububs, 0, 24);
6965 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6966 GEN_VXFORM_ENV(vsubuws, 0, 26);
6967 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6968 GEN_VXFORM_ENV(vsubshs, 0, 29);
6969 GEN_VXFORM_ENV(vsubsws, 0, 30);
6970 GEN_VXFORM(vrlb, 2, 0);
6971 GEN_VXFORM(vrlh, 2, 1);
6972 GEN_VXFORM(vrlw, 2, 2);
6973 GEN_VXFORM(vsl, 2, 7);
6974 GEN_VXFORM(vsr, 2, 11);
6975 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6976 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6977 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6978 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6979 GEN_VXFORM_ENV(vpkshus, 7, 4);
6980 GEN_VXFORM_ENV(vpkswus, 7, 5);
6981 GEN_VXFORM_ENV(vpkshss, 7, 6);
6982 GEN_VXFORM_ENV(vpkswss, 7, 7);
6983 GEN_VXFORM(vpkpx, 7, 12);
6984 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6985 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6986 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6987 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6988 GEN_VXFORM_ENV(vsumsws, 4, 30);
6989 GEN_VXFORM_ENV(vaddfp, 5, 0);
6990 GEN_VXFORM_ENV(vsubfp, 5, 1);
6991 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6992 GEN_VXFORM_ENV(vminfp, 5, 17);
6993
6994 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6995 static void glue(gen_, name)(DisasContext *ctx) \
6996 { \
6997 TCGv_ptr ra, rb, rd; \
6998 if (unlikely(!ctx->altivec_enabled)) { \
6999 gen_exception(ctx, POWERPC_EXCP_VPU); \
7000 return; \
7001 } \
7002 ra = gen_avr_ptr(rA(ctx->opcode)); \
7003 rb = gen_avr_ptr(rB(ctx->opcode)); \
7004 rd = gen_avr_ptr(rD(ctx->opcode)); \
7005 gen_helper_##opname(cpu_env, rd, ra, rb); \
7006 tcg_temp_free_ptr(ra); \
7007 tcg_temp_free_ptr(rb); \
7008 tcg_temp_free_ptr(rd); \
7009 }
7010
7011 #define GEN_VXRFORM(name, opc2, opc3) \
7012 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7013 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7014
7015 GEN_VXRFORM(vcmpequb, 3, 0)
7016 GEN_VXRFORM(vcmpequh, 3, 1)
7017 GEN_VXRFORM(vcmpequw, 3, 2)
7018 GEN_VXRFORM(vcmpgtsb, 3, 12)
7019 GEN_VXRFORM(vcmpgtsh, 3, 13)
7020 GEN_VXRFORM(vcmpgtsw, 3, 14)
7021 GEN_VXRFORM(vcmpgtub, 3, 8)
7022 GEN_VXRFORM(vcmpgtuh, 3, 9)
7023 GEN_VXRFORM(vcmpgtuw, 3, 10)
7024 GEN_VXRFORM(vcmpeqfp, 3, 3)
7025 GEN_VXRFORM(vcmpgefp, 3, 7)
7026 GEN_VXRFORM(vcmpgtfp, 3, 11)
7027 GEN_VXRFORM(vcmpbfp, 3, 15)
7028
7029 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7030 static void glue(gen_, name)(DisasContext *ctx) \
7031 { \
7032 TCGv_ptr rd; \
7033 TCGv_i32 simm; \
7034 if (unlikely(!ctx->altivec_enabled)) { \
7035 gen_exception(ctx, POWERPC_EXCP_VPU); \
7036 return; \
7037 } \
7038 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7039 rd = gen_avr_ptr(rD(ctx->opcode)); \
7040 gen_helper_##name (rd, simm); \
7041 tcg_temp_free_i32(simm); \
7042 tcg_temp_free_ptr(rd); \
7043 }
7044
7045 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7046 GEN_VXFORM_SIMM(vspltish, 6, 13);
7047 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7048
7049 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7050 static void glue(gen_, name)(DisasContext *ctx) \
7051 { \
7052 TCGv_ptr rb, rd; \
7053 if (unlikely(!ctx->altivec_enabled)) { \
7054 gen_exception(ctx, POWERPC_EXCP_VPU); \
7055 return; \
7056 } \
7057 rb = gen_avr_ptr(rB(ctx->opcode)); \
7058 rd = gen_avr_ptr(rD(ctx->opcode)); \
7059 gen_helper_##name (rd, rb); \
7060 tcg_temp_free_ptr(rb); \
7061 tcg_temp_free_ptr(rd); \
7062 }
7063
7064 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7065 static void glue(gen_, name)(DisasContext *ctx) \
7066 { \
7067 TCGv_ptr rb, rd; \
7068 \
7069 if (unlikely(!ctx->altivec_enabled)) { \
7070 gen_exception(ctx, POWERPC_EXCP_VPU); \
7071 return; \
7072 } \
7073 rb = gen_avr_ptr(rB(ctx->opcode)); \
7074 rd = gen_avr_ptr(rD(ctx->opcode)); \
7075 gen_helper_##name(cpu_env, rd, rb); \
7076 tcg_temp_free_ptr(rb); \
7077 tcg_temp_free_ptr(rd); \
7078 }
7079
7080 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7081 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7082 GEN_VXFORM_NOA(vupklsb, 7, 10);
7083 GEN_VXFORM_NOA(vupklsh, 7, 11);
7084 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7085 GEN_VXFORM_NOA(vupklpx, 7, 15);
7086 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7087 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7088 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7089 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7090 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
7091 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
7092 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7093 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
7094
7095 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7096 static void glue(gen_, name)(DisasContext *ctx) \
7097 { \
7098 TCGv_ptr rd; \
7099 TCGv_i32 simm; \
7100 if (unlikely(!ctx->altivec_enabled)) { \
7101 gen_exception(ctx, POWERPC_EXCP_VPU); \
7102 return; \
7103 } \
7104 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7105 rd = gen_avr_ptr(rD(ctx->opcode)); \
7106 gen_helper_##name (rd, simm); \
7107 tcg_temp_free_i32(simm); \
7108 tcg_temp_free_ptr(rd); \
7109 }
7110
7111 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7112 static void glue(gen_, name)(DisasContext *ctx) \
7113 { \
7114 TCGv_ptr rb, rd; \
7115 TCGv_i32 uimm; \
7116 if (unlikely(!ctx->altivec_enabled)) { \
7117 gen_exception(ctx, POWERPC_EXCP_VPU); \
7118 return; \
7119 } \
7120 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7121 rb = gen_avr_ptr(rB(ctx->opcode)); \
7122 rd = gen_avr_ptr(rD(ctx->opcode)); \
7123 gen_helper_##name (rd, rb, uimm); \
7124 tcg_temp_free_i32(uimm); \
7125 tcg_temp_free_ptr(rb); \
7126 tcg_temp_free_ptr(rd); \
7127 }
7128
7129 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7130 static void glue(gen_, name)(DisasContext *ctx) \
7131 { \
7132 TCGv_ptr rb, rd; \
7133 TCGv_i32 uimm; \
7134 \
7135 if (unlikely(!ctx->altivec_enabled)) { \
7136 gen_exception(ctx, POWERPC_EXCP_VPU); \
7137 return; \
7138 } \
7139 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7140 rb = gen_avr_ptr(rB(ctx->opcode)); \
7141 rd = gen_avr_ptr(rD(ctx->opcode)); \
7142 gen_helper_##name(cpu_env, rd, rb, uimm); \
7143 tcg_temp_free_i32(uimm); \
7144 tcg_temp_free_ptr(rb); \
7145 tcg_temp_free_ptr(rd); \
7146 }
7147
7148 GEN_VXFORM_UIMM(vspltb, 6, 8);
7149 GEN_VXFORM_UIMM(vsplth, 6, 9);
7150 GEN_VXFORM_UIMM(vspltw, 6, 10);
7151 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7152 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7153 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7154 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7155
7156 static void gen_vsldoi(DisasContext *ctx)
7157 {
7158 TCGv_ptr ra, rb, rd;
7159 TCGv_i32 sh;
7160 if (unlikely(!ctx->altivec_enabled)) {
7161 gen_exception(ctx, POWERPC_EXCP_VPU);
7162 return;
7163 }
7164 ra = gen_avr_ptr(rA(ctx->opcode));
7165 rb = gen_avr_ptr(rB(ctx->opcode));
7166 rd = gen_avr_ptr(rD(ctx->opcode));
7167 sh = tcg_const_i32(VSH(ctx->opcode));
7168 gen_helper_vsldoi (rd, ra, rb, sh);
7169 tcg_temp_free_ptr(ra);
7170 tcg_temp_free_ptr(rb);
7171 tcg_temp_free_ptr(rd);
7172 tcg_temp_free_i32(sh);
7173 }
7174
7175 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7176 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7177 { \
7178 TCGv_ptr ra, rb, rc, rd; \
7179 if (unlikely(!ctx->altivec_enabled)) { \
7180 gen_exception(ctx, POWERPC_EXCP_VPU); \
7181 return; \
7182 } \
7183 ra = gen_avr_ptr(rA(ctx->opcode)); \
7184 rb = gen_avr_ptr(rB(ctx->opcode)); \
7185 rc = gen_avr_ptr(rC(ctx->opcode)); \
7186 rd = gen_avr_ptr(rD(ctx->opcode)); \
7187 if (Rc(ctx->opcode)) { \
7188 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7189 } else { \
7190 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7191 } \
7192 tcg_temp_free_ptr(ra); \
7193 tcg_temp_free_ptr(rb); \
7194 tcg_temp_free_ptr(rc); \
7195 tcg_temp_free_ptr(rd); \
7196 }
7197
7198 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7199
7200 static void gen_vmladduhm(DisasContext *ctx)
7201 {
7202 TCGv_ptr ra, rb, rc, rd;
7203 if (unlikely(!ctx->altivec_enabled)) {
7204 gen_exception(ctx, POWERPC_EXCP_VPU);
7205 return;
7206 }
7207 ra = gen_avr_ptr(rA(ctx->opcode));
7208 rb = gen_avr_ptr(rB(ctx->opcode));
7209 rc = gen_avr_ptr(rC(ctx->opcode));
7210 rd = gen_avr_ptr(rD(ctx->opcode));
7211 gen_helper_vmladduhm(rd, ra, rb, rc);
7212 tcg_temp_free_ptr(ra);
7213 tcg_temp_free_ptr(rb);
7214 tcg_temp_free_ptr(rc);
7215 tcg_temp_free_ptr(rd);
7216 }
7217
7218 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7219 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7220 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7221 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7222 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7223
7224 /*** VSX extension ***/
7225
7226 static inline TCGv_i64 cpu_vsrh(int n)
7227 {
7228 if (n < 32) {
7229 return cpu_fpr[n];
7230 } else {
7231 return cpu_avrh[n-32];
7232 }
7233 }
7234
7235 static inline TCGv_i64 cpu_vsrl(int n)
7236 {
7237 if (n < 32) {
7238 return cpu_vsr[n];
7239 } else {
7240 return cpu_avrl[n-32];
7241 }
7242 }
7243
7244 #define VSX_LOAD_SCALAR(name, operation) \
7245 static void gen_##name(DisasContext *ctx) \
7246 { \
7247 TCGv EA; \
7248 if (unlikely(!ctx->vsx_enabled)) { \
7249 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7250 return; \
7251 } \
7252 gen_set_access_type(ctx, ACCESS_INT); \
7253 EA = tcg_temp_new(); \
7254 gen_addr_reg_index(ctx, EA); \
7255 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7256 /* NOTE: cpu_vsrl is undefined */ \
7257 tcg_temp_free(EA); \
7258 }
7259
7260 VSX_LOAD_SCALAR(lxsdx, ld64)
7261 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7262 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7263 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7264
7265 static void gen_lxvd2x(DisasContext *ctx)
7266 {
7267 TCGv EA;
7268 if (unlikely(!ctx->vsx_enabled)) {
7269 gen_exception(ctx, POWERPC_EXCP_VSXU);
7270 return;
7271 }
7272 gen_set_access_type(ctx, ACCESS_INT);
7273 EA = tcg_temp_new();
7274 gen_addr_reg_index(ctx, EA);
7275 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7276 tcg_gen_addi_tl(EA, EA, 8);
7277 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7278 tcg_temp_free(EA);
7279 }
7280
7281 static void gen_lxvdsx(DisasContext *ctx)
7282 {
7283 TCGv EA;
7284 if (unlikely(!ctx->vsx_enabled)) {
7285 gen_exception(ctx, POWERPC_EXCP_VSXU);
7286 return;
7287 }
7288 gen_set_access_type(ctx, ACCESS_INT);
7289 EA = tcg_temp_new();
7290 gen_addr_reg_index(ctx, EA);
7291 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7292 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7293 tcg_temp_free(EA);
7294 }
7295
7296 static void gen_lxvw4x(DisasContext *ctx)
7297 {
7298 TCGv EA;
7299 TCGv_i64 tmp;
7300 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7301 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7302 if (unlikely(!ctx->vsx_enabled)) {
7303 gen_exception(ctx, POWERPC_EXCP_VSXU);
7304 return;
7305 }
7306 gen_set_access_type(ctx, ACCESS_INT);
7307 EA = tcg_temp_new();
7308 tmp = tcg_temp_new_i64();
7309
7310 gen_addr_reg_index(ctx, EA);
7311 gen_qemu_ld32u_i64(ctx, tmp, EA);
7312 tcg_gen_addi_tl(EA, EA, 4);
7313 gen_qemu_ld32u_i64(ctx, xth, EA);
7314 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7315
7316 tcg_gen_addi_tl(EA, EA, 4);
7317 gen_qemu_ld32u_i64(ctx, tmp, EA);
7318 tcg_gen_addi_tl(EA, EA, 4);
7319 gen_qemu_ld32u_i64(ctx, xtl, EA);
7320 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7321
7322 tcg_temp_free(EA);
7323 tcg_temp_free_i64(tmp);
7324 }
7325
7326 #define VSX_STORE_SCALAR(name, operation) \
7327 static void gen_##name(DisasContext *ctx) \
7328 { \
7329 TCGv EA; \
7330 if (unlikely(!ctx->vsx_enabled)) { \
7331 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7332 return; \
7333 } \
7334 gen_set_access_type(ctx, ACCESS_INT); \
7335 EA = tcg_temp_new(); \
7336 gen_addr_reg_index(ctx, EA); \
7337 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7338 tcg_temp_free(EA); \
7339 }
7340
7341 VSX_STORE_SCALAR(stxsdx, st64)
7342 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7343 VSX_STORE_SCALAR(stxsspx, st32fs)
7344
7345 static void gen_stxvd2x(DisasContext *ctx)
7346 {
7347 TCGv EA;
7348 if (unlikely(!ctx->vsx_enabled)) {
7349 gen_exception(ctx, POWERPC_EXCP_VSXU);
7350 return;
7351 }
7352 gen_set_access_type(ctx, ACCESS_INT);
7353 EA = tcg_temp_new();
7354 gen_addr_reg_index(ctx, EA);
7355 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7356 tcg_gen_addi_tl(EA, EA, 8);
7357 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7358 tcg_temp_free(EA);
7359 }
7360
7361 static void gen_stxvw4x(DisasContext *ctx)
7362 {
7363 TCGv_i64 tmp;
7364 TCGv EA;
7365 if (unlikely(!ctx->vsx_enabled)) {
7366 gen_exception(ctx, POWERPC_EXCP_VSXU);
7367 return;
7368 }
7369 gen_set_access_type(ctx, ACCESS_INT);
7370 EA = tcg_temp_new();
7371 gen_addr_reg_index(ctx, EA);
7372 tmp = tcg_temp_new_i64();
7373
7374 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7375 gen_qemu_st32_i64(ctx, tmp, EA);
7376 tcg_gen_addi_tl(EA, EA, 4);
7377 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7378
7379 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7380 tcg_gen_addi_tl(EA, EA, 4);
7381 gen_qemu_st32_i64(ctx, tmp, EA);
7382 tcg_gen_addi_tl(EA, EA, 4);
7383 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7384
7385 tcg_temp_free(EA);
7386 tcg_temp_free_i64(tmp);
7387 }
7388
7389 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7390 static void gen_##name(DisasContext *ctx) \
7391 { \
7392 if (xS(ctx->opcode) < 32) { \
7393 if (unlikely(!ctx->fpu_enabled)) { \
7394 gen_exception(ctx, POWERPC_EXCP_FPU); \
7395 return; \
7396 } \
7397 } else { \
7398 if (unlikely(!ctx->altivec_enabled)) { \
7399 gen_exception(ctx, POWERPC_EXCP_VPU); \
7400 return; \
7401 } \
7402 } \
7403 TCGv_i64 tmp = tcg_temp_new_i64(); \
7404 tcg_gen_##tcgop1(tmp, source); \
7405 tcg_gen_##tcgop2(target, tmp); \
7406 tcg_temp_free_i64(tmp); \
7407 }
7408
7409
7410 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7411 cpu_vsrh(xS(ctx->opcode)))
7412 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7413 cpu_gpr[rA(ctx->opcode)])
7414 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7415 cpu_gpr[rA(ctx->opcode)])
7416
7417 #if defined(TARGET_PPC64)
7418 #define MV_VSRD(name, target, source) \
7419 static void gen_##name(DisasContext *ctx) \
7420 { \
7421 if (xS(ctx->opcode) < 32) { \
7422 if (unlikely(!ctx->fpu_enabled)) { \
7423 gen_exception(ctx, POWERPC_EXCP_FPU); \
7424 return; \
7425 } \
7426 } else { \
7427 if (unlikely(!ctx->altivec_enabled)) { \
7428 gen_exception(ctx, POWERPC_EXCP_VPU); \
7429 return; \
7430 } \
7431 } \
7432 tcg_gen_mov_i64(target, source); \
7433 }
7434
7435 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7436 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7437
7438 #endif
7439
7440 static void gen_xxpermdi(DisasContext *ctx)
7441 {
7442 if (unlikely(!ctx->vsx_enabled)) {
7443 gen_exception(ctx, POWERPC_EXCP_VSXU);
7444 return;
7445 }
7446
7447 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7448 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7449 TCGv_i64 xh, xl;
7450
7451 xh = tcg_temp_new_i64();
7452 xl = tcg_temp_new_i64();
7453
7454 if ((DM(ctx->opcode) & 2) == 0) {
7455 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7456 } else {
7457 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7458 }
7459 if ((DM(ctx->opcode) & 1) == 0) {
7460 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7461 } else {
7462 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7463 }
7464
7465 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7466 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7467
7468 tcg_temp_free_i64(xh);
7469 tcg_temp_free_i64(xl);
7470 } else {
7471 if ((DM(ctx->opcode) & 2) == 0) {
7472 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7473 } else {
7474 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7475 }
7476 if ((DM(ctx->opcode) & 1) == 0) {
7477 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7478 } else {
7479 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7480 }
7481 }
7482 }
7483
7484 #define OP_ABS 1
7485 #define OP_NABS 2
7486 #define OP_NEG 3
7487 #define OP_CPSGN 4
7488 #define SGN_MASK_DP 0x8000000000000000ul
7489 #define SGN_MASK_SP 0x8000000080000000ul
7490
7491 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7492 static void glue(gen_, name)(DisasContext * ctx) \
7493 { \
7494 TCGv_i64 xb, sgm; \
7495 if (unlikely(!ctx->vsx_enabled)) { \
7496 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7497 return; \
7498 } \
7499 xb = tcg_temp_new_i64(); \
7500 sgm = tcg_temp_new_i64(); \
7501 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7502 tcg_gen_movi_i64(sgm, sgn_mask); \
7503 switch (op) { \
7504 case OP_ABS: { \
7505 tcg_gen_andc_i64(xb, xb, sgm); \
7506 break; \
7507 } \
7508 case OP_NABS: { \
7509 tcg_gen_or_i64(xb, xb, sgm); \
7510 break; \
7511 } \
7512 case OP_NEG: { \
7513 tcg_gen_xor_i64(xb, xb, sgm); \
7514 break; \
7515 } \
7516 case OP_CPSGN: { \
7517 TCGv_i64 xa = tcg_temp_new_i64(); \
7518 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7519 tcg_gen_and_i64(xa, xa, sgm); \
7520 tcg_gen_andc_i64(xb, xb, sgm); \
7521 tcg_gen_or_i64(xb, xb, xa); \
7522 tcg_temp_free_i64(xa); \
7523 break; \
7524 } \
7525 } \
7526 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7527 tcg_temp_free_i64(xb); \
7528 tcg_temp_free_i64(sgm); \
7529 }
7530
7531 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7532 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7533 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7534 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7535
7536 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7537 static void glue(gen_, name)(DisasContext * ctx) \
7538 { \
7539 TCGv_i64 xbh, xbl, sgm; \
7540 if (unlikely(!ctx->vsx_enabled)) { \
7541 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7542 return; \
7543 } \
7544 xbh = tcg_temp_new_i64(); \
7545 xbl = tcg_temp_new_i64(); \
7546 sgm = tcg_temp_new_i64(); \
7547 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7548 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7549 tcg_gen_movi_i64(sgm, sgn_mask); \
7550 switch (op) { \
7551 case OP_ABS: { \
7552 tcg_gen_andc_i64(xbh, xbh, sgm); \
7553 tcg_gen_andc_i64(xbl, xbl, sgm); \
7554 break; \
7555 } \
7556 case OP_NABS: { \
7557 tcg_gen_or_i64(xbh, xbh, sgm); \
7558 tcg_gen_or_i64(xbl, xbl, sgm); \
7559 break; \
7560 } \
7561 case OP_NEG: { \
7562 tcg_gen_xor_i64(xbh, xbh, sgm); \
7563 tcg_gen_xor_i64(xbl, xbl, sgm); \
7564 break; \
7565 } \
7566 case OP_CPSGN: { \
7567 TCGv_i64 xah = tcg_temp_new_i64(); \
7568 TCGv_i64 xal = tcg_temp_new_i64(); \
7569 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7570 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7571 tcg_gen_and_i64(xah, xah, sgm); \
7572 tcg_gen_and_i64(xal, xal, sgm); \
7573 tcg_gen_andc_i64(xbh, xbh, sgm); \
7574 tcg_gen_andc_i64(xbl, xbl, sgm); \
7575 tcg_gen_or_i64(xbh, xbh, xah); \
7576 tcg_gen_or_i64(xbl, xbl, xal); \
7577 tcg_temp_free_i64(xah); \
7578 tcg_temp_free_i64(xal); \
7579 break; \
7580 } \
7581 } \
7582 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7583 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7584 tcg_temp_free_i64(xbh); \
7585 tcg_temp_free_i64(xbl); \
7586 tcg_temp_free_i64(sgm); \
7587 }
7588
7589 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7590 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7591 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7592 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7593 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7594 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7595 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7596 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7597
7598 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7599 static void gen_##name(DisasContext * ctx) \
7600 { \
7601 TCGv_i32 opc; \
7602 if (unlikely(!ctx->vsx_enabled)) { \
7603 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7604 return; \
7605 } \
7606 /* NIP cannot be restored if the memory exception comes from an helper */ \
7607 gen_update_nip(ctx, ctx->nip - 4); \
7608 opc = tcg_const_i32(ctx->opcode); \
7609 gen_helper_##name(cpu_env, opc); \
7610 tcg_temp_free_i32(opc); \
7611 }
7612
7613 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7614 static void gen_##name(DisasContext * ctx) \
7615 { \
7616 if (unlikely(!ctx->vsx_enabled)) { \
7617 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7618 return; \
7619 } \
7620 /* NIP cannot be restored if the exception comes */ \
7621 /* from a helper. */ \
7622 gen_update_nip(ctx, ctx->nip - 4); \
7623 \
7624 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7625 cpu_vsrh(xB(ctx->opcode))); \
7626 }
7627
7628 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7629 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7630 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7631 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7632 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7633 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7634 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7635 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7636 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7637 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7638 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7639 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7640 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7641 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7642 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7643 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7644 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7645 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7646 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7647 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7648 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7649 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7650 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
7651 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7652 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
7653 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7654 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7655 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7656 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7657 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7658 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
7659 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7660 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7661 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7662 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7663 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
7664 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
7665
7666 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
7667 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
7668 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
7669 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
7670 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
7671 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
7672 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
7673 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
7674 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
7675 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
7676 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
7677 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
7678 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
7679 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
7680 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
7681 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
7682 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
7683
7684 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
7685 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
7686 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
7687 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
7688 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
7689 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
7690 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
7691 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
7692 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
7693 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
7694 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
7695 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
7696 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
7697 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
7698 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
7699 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
7700 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
7701 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
7702 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
7703 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
7704 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
7705 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
7706 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
7707 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
7708 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
7709 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
7710 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
7711 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
7712 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
7713 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
7714 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
7715 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
7716 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
7717 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
7718 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
7719 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
7720
7721 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
7722 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
7723 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
7724 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
7725 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
7726 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
7727 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
7728 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
7729 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
7730 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
7731 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
7732 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
7733 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
7734 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
7735 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
7736 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
7737 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
7738 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
7739 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
7740 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
7741 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
7742 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
7743 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
7744 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
7745 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
7746 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
7747 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
7748 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
7749 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
7750 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
7751 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
7752 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
7753 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
7754 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
7755 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
7756 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
7757
7758 #define VSX_LOGICAL(name, tcg_op) \
7759 static void glue(gen_, name)(DisasContext * ctx) \
7760 { \
7761 if (unlikely(!ctx->vsx_enabled)) { \
7762 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7763 return; \
7764 } \
7765 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
7766 cpu_vsrh(xB(ctx->opcode))); \
7767 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
7768 cpu_vsrl(xB(ctx->opcode))); \
7769 }
7770
7771 VSX_LOGICAL(xxland, tcg_gen_and_i64)
7772 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
7773 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
7774 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
7775 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
7776 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
7777 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
7778 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
7779
7780 #define VSX_XXMRG(name, high) \
7781 static void glue(gen_, name)(DisasContext * ctx) \
7782 { \
7783 TCGv_i64 a0, a1, b0, b1; \
7784 if (unlikely(!ctx->vsx_enabled)) { \
7785 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7786 return; \
7787 } \
7788 a0 = tcg_temp_new_i64(); \
7789 a1 = tcg_temp_new_i64(); \
7790 b0 = tcg_temp_new_i64(); \
7791 b1 = tcg_temp_new_i64(); \
7792 if (high) { \
7793 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
7794 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
7795 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
7796 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
7797 } else { \
7798 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
7799 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
7800 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
7801 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
7802 } \
7803 tcg_gen_shri_i64(a0, a0, 32); \
7804 tcg_gen_shri_i64(b0, b0, 32); \
7805 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
7806 b0, a0, 32, 32); \
7807 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
7808 b1, a1, 32, 32); \
7809 tcg_temp_free_i64(a0); \
7810 tcg_temp_free_i64(a1); \
7811 tcg_temp_free_i64(b0); \
7812 tcg_temp_free_i64(b1); \
7813 }
7814
7815 VSX_XXMRG(xxmrghw, 1)
7816 VSX_XXMRG(xxmrglw, 0)
7817
7818 static void gen_xxsel(DisasContext * ctx)
7819 {
7820 TCGv_i64 a, b, c;
7821 if (unlikely(!ctx->vsx_enabled)) {
7822 gen_exception(ctx, POWERPC_EXCP_VSXU);
7823 return;
7824 }
7825 a = tcg_temp_new_i64();
7826 b = tcg_temp_new_i64();
7827 c = tcg_temp_new_i64();
7828
7829 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
7830 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
7831 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
7832
7833 tcg_gen_and_i64(b, b, c);
7834 tcg_gen_andc_i64(a, a, c);
7835 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
7836
7837 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
7838 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
7839 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
7840
7841 tcg_gen_and_i64(b, b, c);
7842 tcg_gen_andc_i64(a, a, c);
7843 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
7844
7845 tcg_temp_free_i64(a);
7846 tcg_temp_free_i64(b);
7847 tcg_temp_free_i64(c);
7848 }
7849
7850 static void gen_xxspltw(DisasContext *ctx)
7851 {
7852 TCGv_i64 b, b2;
7853 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
7854 cpu_vsrl(xB(ctx->opcode)) :
7855 cpu_vsrh(xB(ctx->opcode));
7856
7857 if (unlikely(!ctx->vsx_enabled)) {
7858 gen_exception(ctx, POWERPC_EXCP_VSXU);
7859 return;
7860 }
7861
7862 b = tcg_temp_new_i64();
7863 b2 = tcg_temp_new_i64();
7864
7865 if (UIM(ctx->opcode) & 1) {
7866 tcg_gen_ext32u_i64(b, vsr);
7867 } else {
7868 tcg_gen_shri_i64(b, vsr, 32);
7869 }
7870
7871 tcg_gen_shli_i64(b2, b, 32);
7872 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
7873 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7874
7875 tcg_temp_free_i64(b);
7876 tcg_temp_free_i64(b2);
7877 }
7878
7879 static void gen_xxsldwi(DisasContext *ctx)
7880 {
7881 TCGv_i64 xth, xtl;
7882 if (unlikely(!ctx->vsx_enabled)) {
7883 gen_exception(ctx, POWERPC_EXCP_VSXU);
7884 return;
7885 }
7886 xth = tcg_temp_new_i64();
7887 xtl = tcg_temp_new_i64();
7888
7889 switch (SHW(ctx->opcode)) {
7890 case 0: {
7891 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
7892 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
7893 break;
7894 }
7895 case 1: {
7896 TCGv_i64 t0 = tcg_temp_new_i64();
7897 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
7898 tcg_gen_shli_i64(xth, xth, 32);
7899 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
7900 tcg_gen_shri_i64(t0, t0, 32);
7901 tcg_gen_or_i64(xth, xth, t0);
7902 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
7903 tcg_gen_shli_i64(xtl, xtl, 32);
7904 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
7905 tcg_gen_shri_i64(t0, t0, 32);
7906 tcg_gen_or_i64(xtl, xtl, t0);
7907 tcg_temp_free_i64(t0);
7908 break;
7909 }
7910 case 2: {
7911 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
7912 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
7913 break;
7914 }
7915 case 3: {
7916 TCGv_i64 t0 = tcg_temp_new_i64();
7917 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
7918 tcg_gen_shli_i64(xth, xth, 32);
7919 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
7920 tcg_gen_shri_i64(t0, t0, 32);
7921 tcg_gen_or_i64(xth, xth, t0);
7922 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
7923 tcg_gen_shli_i64(xtl, xtl, 32);
7924 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
7925 tcg_gen_shri_i64(t0, t0, 32);
7926 tcg_gen_or_i64(xtl, xtl, t0);
7927 tcg_temp_free_i64(t0);
7928 break;
7929 }
7930 }
7931
7932 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
7933 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
7934
7935 tcg_temp_free_i64(xth);
7936 tcg_temp_free_i64(xtl);
7937 }
7938
7939
7940 /*** SPE extension ***/
7941 /* Register moves */
7942
7943 static inline void gen_evmra(DisasContext *ctx)
7944 {
7945
7946 if (unlikely(!ctx->spe_enabled)) {
7947 gen_exception(ctx, POWERPC_EXCP_SPEU);
7948 return;
7949 }
7950
7951 #if defined(TARGET_PPC64)
7952 /* rD := rA */
7953 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7954
7955 /* spe_acc := rA */
7956 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
7957 cpu_env,
7958 offsetof(CPUPPCState, spe_acc));
7959 #else
7960 TCGv_i64 tmp = tcg_temp_new_i64();
7961
7962 /* tmp := rA_lo + rA_hi << 32 */
7963 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7964
7965 /* spe_acc := tmp */
7966 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7967 tcg_temp_free_i64(tmp);
7968
7969 /* rD := rA */
7970 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7971 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7972 #endif
7973 }
7974
7975 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
7976 {
7977 #if defined(TARGET_PPC64)
7978 tcg_gen_mov_i64(t, cpu_gpr[reg]);
7979 #else
7980 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
7981 #endif
7982 }
7983
7984 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
7985 {
7986 #if defined(TARGET_PPC64)
7987 tcg_gen_mov_i64(cpu_gpr[reg], t);
7988 #else
7989 TCGv_i64 tmp = tcg_temp_new_i64();
7990 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
7991 tcg_gen_shri_i64(tmp, t, 32);
7992 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
7993 tcg_temp_free_i64(tmp);
7994 #endif
7995 }
7996
7997 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
7998 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7999 { \
8000 if (Rc(ctx->opcode)) \
8001 gen_##name1(ctx); \
8002 else \
8003 gen_##name0(ctx); \
8004 }
8005
8006 /* Handler for undefined SPE opcodes */
8007 static inline void gen_speundef(DisasContext *ctx)
8008 {
8009 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8010 }
8011
8012 /* SPE logic */
8013 #if defined(TARGET_PPC64)
8014 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8015 static inline void gen_##name(DisasContext *ctx) \
8016 { \
8017 if (unlikely(!ctx->spe_enabled)) { \
8018 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8019 return; \
8020 } \
8021 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8022 cpu_gpr[rB(ctx->opcode)]); \
8023 }
8024 #else
8025 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8026 static inline void gen_##name(DisasContext *ctx) \
8027 { \
8028 if (unlikely(!ctx->spe_enabled)) { \
8029 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8030 return; \
8031 } \
8032 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8033 cpu_gpr[rB(ctx->opcode)]); \
8034 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8035 cpu_gprh[rB(ctx->opcode)]); \
8036 }
8037 #endif
8038
8039 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8040 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8041 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8042 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8043 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8044 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8045 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8046 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8047
8048 /* SPE logic immediate */
8049 #if defined(TARGET_PPC64)
8050 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8051 static inline void gen_##name(DisasContext *ctx) \
8052 { \
8053 if (unlikely(!ctx->spe_enabled)) { \
8054 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8055 return; \
8056 } \
8057 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8058 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8059 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8060 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8061 tcg_opi(t0, t0, rB(ctx->opcode)); \
8062 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
8063 tcg_gen_trunc_i64_i32(t1, t2); \
8064 tcg_temp_free_i64(t2); \
8065 tcg_opi(t1, t1, rB(ctx->opcode)); \
8066 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
8067 tcg_temp_free_i32(t0); \
8068 tcg_temp_free_i32(t1); \
8069 }
8070 #else
8071 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8072 static inline void gen_##name(DisasContext *ctx) \
8073 { \
8074 if (unlikely(!ctx->spe_enabled)) { \
8075 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8076 return; \
8077 } \
8078 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8079 rB(ctx->opcode)); \
8080 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8081 rB(ctx->opcode)); \
8082 }
8083 #endif
8084 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8085 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8086 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8087 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8088
8089 /* SPE arithmetic */
8090 #if defined(TARGET_PPC64)
8091 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8092 static inline void gen_##name(DisasContext *ctx) \
8093 { \
8094 if (unlikely(!ctx->spe_enabled)) { \
8095 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8096 return; \
8097 } \
8098 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8099 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8100 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8101 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8102 tcg_op(t0, t0); \
8103 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
8104 tcg_gen_trunc_i64_i32(t1, t2); \
8105 tcg_temp_free_i64(t2); \
8106 tcg_op(t1, t1); \
8107 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
8108 tcg_temp_free_i32(t0); \
8109 tcg_temp_free_i32(t1); \
8110 }
8111 #else
8112 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8113 static inline void gen_##name(DisasContext *ctx) \
8114 { \
8115 if (unlikely(!ctx->spe_enabled)) { \
8116 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8117 return; \
8118 } \
8119 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8120 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8121 }
8122 #endif
8123
8124 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8125 {
8126 int l1 = gen_new_label();
8127 int l2 = gen_new_label();
8128
8129 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8130 tcg_gen_neg_i32(ret, arg1);
8131 tcg_gen_br(l2);
8132 gen_set_label(l1);
8133 tcg_gen_mov_i32(ret, arg1);
8134 gen_set_label(l2);
8135 }
8136 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8137 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8138 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8139 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8140 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8141 {
8142 tcg_gen_addi_i32(ret, arg1, 0x8000);
8143 tcg_gen_ext16u_i32(ret, ret);
8144 }
8145 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8146 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8147 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8148
8149 #if defined(TARGET_PPC64)
8150 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8151 static inline void gen_##name(DisasContext *ctx) \
8152 { \
8153 if (unlikely(!ctx->spe_enabled)) { \
8154 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8155 return; \
8156 } \
8157 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8158 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8159 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
8160 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
8161 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8162 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
8163 tcg_op(t0, t0, t2); \
8164 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
8165 tcg_gen_trunc_i64_i32(t1, t3); \
8166 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
8167 tcg_gen_trunc_i64_i32(t2, t3); \
8168 tcg_temp_free_i64(t3); \
8169 tcg_op(t1, t1, t2); \
8170 tcg_temp_free_i32(t2); \
8171 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
8172 tcg_temp_free_i32(t0); \
8173 tcg_temp_free_i32(t1); \
8174 }
8175 #else
8176 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8177 static inline void gen_##name(DisasContext *ctx) \
8178 { \
8179 if (unlikely(!ctx->spe_enabled)) { \
8180 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8181 return; \
8182 } \
8183 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8184 cpu_gpr[rB(ctx->opcode)]); \
8185 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8186 cpu_gprh[rB(ctx->opcode)]); \
8187 }
8188 #endif
8189
8190 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8191 {
8192 TCGv_i32 t0;
8193 int l1, l2;
8194
8195 l1 = gen_new_label();
8196 l2 = gen_new_label();
8197 t0 = tcg_temp_local_new_i32();
8198 /* No error here: 6 bits are used */
8199 tcg_gen_andi_i32(t0, arg2, 0x3F);
8200 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8201 tcg_gen_shr_i32(ret, arg1, t0);
8202 tcg_gen_br(l2);
8203 gen_set_label(l1);
8204 tcg_gen_movi_i32(ret, 0);
8205 gen_set_label(l2);
8206 tcg_temp_free_i32(t0);
8207 }
8208 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8209 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8210 {
8211 TCGv_i32 t0;
8212 int l1, l2;
8213
8214 l1 = gen_new_label();
8215 l2 = gen_new_label();
8216 t0 = tcg_temp_local_new_i32();
8217 /* No error here: 6 bits are used */
8218 tcg_gen_andi_i32(t0, arg2, 0x3F);
8219 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8220 tcg_gen_sar_i32(ret, arg1, t0);
8221 tcg_gen_br(l2);
8222 gen_set_label(l1);
8223 tcg_gen_movi_i32(ret, 0);
8224 gen_set_label(l2);
8225 tcg_temp_free_i32(t0);
8226 }
8227 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8228 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8229 {
8230 TCGv_i32 t0;
8231 int l1, l2;
8232
8233 l1 = gen_new_label();
8234 l2 = gen_new_label();
8235 t0 = tcg_temp_local_new_i32();
8236 /* No error here: 6 bits are used */
8237 tcg_gen_andi_i32(t0, arg2, 0x3F);
8238 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8239 tcg_gen_shl_i32(ret, arg1, t0);
8240 tcg_gen_br(l2);
8241 gen_set_label(l1);
8242 tcg_gen_movi_i32(ret, 0);
8243 gen_set_label(l2);
8244 tcg_temp_free_i32(t0);
8245 }
8246 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8247 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8248 {
8249 TCGv_i32 t0 = tcg_temp_new_i32();
8250 tcg_gen_andi_i32(t0, arg2, 0x1F);
8251 tcg_gen_rotl_i32(ret, arg1, t0);
8252 tcg_temp_free_i32(t0);
8253 }
8254 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8255 static inline void gen_evmergehi(DisasContext *ctx)
8256 {
8257 if (unlikely(!ctx->spe_enabled)) {
8258 gen_exception(ctx, POWERPC_EXCP_SPEU);
8259 return;
8260 }
8261 #if defined(TARGET_PPC64)
8262 TCGv t0 = tcg_temp_new();
8263 TCGv t1 = tcg_temp_new();
8264 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
8265 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
8266 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8267 tcg_temp_free(t0);
8268 tcg_temp_free(t1);
8269 #else
8270 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8271 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8272 #endif
8273 }
8274 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8275 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8276 {
8277 tcg_gen_sub_i32(ret, arg2, arg1);
8278 }
8279 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8280
8281 /* SPE arithmetic immediate */
8282 #if defined(TARGET_PPC64)
8283 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8284 static inline void gen_##name(DisasContext *ctx) \
8285 { \
8286 if (unlikely(!ctx->spe_enabled)) { \
8287 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8288 return; \
8289 } \
8290 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8291 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8292 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8293 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8294 tcg_op(t0, t0, rA(ctx->opcode)); \
8295 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
8296 tcg_gen_trunc_i64_i32(t1, t2); \
8297 tcg_temp_free_i64(t2); \
8298 tcg_op(t1, t1, rA(ctx->opcode)); \
8299 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
8300 tcg_temp_free_i32(t0); \
8301 tcg_temp_free_i32(t1); \
8302 }
8303 #else
8304 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8305 static inline void gen_##name(DisasContext *ctx) \
8306 { \
8307 if (unlikely(!ctx->spe_enabled)) { \
8308 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8309 return; \
8310 } \
8311 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
8312 rA(ctx->opcode)); \
8313 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
8314 rA(ctx->opcode)); \
8315 }
8316 #endif
8317 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8318 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8319
8320 /* SPE comparison */
8321 #if defined(TARGET_PPC64)
8322 #define GEN_SPEOP_COMP(name, tcg_cond) \
8323 static inline void gen_##name(DisasContext *ctx) \
8324 { \
8325 if (unlikely(!ctx->spe_enabled)) { \
8326 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8327 return; \
8328 } \
8329 int l1 = gen_new_label(); \
8330 int l2 = gen_new_label(); \
8331 int l3 = gen_new_label(); \
8332 int l4 = gen_new_label(); \
8333 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8334 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8335 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8336 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8337 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8338 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
8339 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8340 tcg_gen_br(l2); \
8341 gen_set_label(l1); \
8342 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8343 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8344 gen_set_label(l2); \
8345 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
8346 tcg_gen_trunc_i64_i32(t0, t2); \
8347 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
8348 tcg_gen_trunc_i64_i32(t1, t2); \
8349 tcg_temp_free_i64(t2); \
8350 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
8351 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8352 ~(CRF_CH | CRF_CH_AND_CL)); \
8353 tcg_gen_br(l4); \
8354 gen_set_label(l3); \
8355 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8356 CRF_CH | CRF_CH_OR_CL); \
8357 gen_set_label(l4); \
8358 tcg_temp_free_i32(t0); \
8359 tcg_temp_free_i32(t1); \
8360 }
8361 #else
8362 #define GEN_SPEOP_COMP(name, tcg_cond) \
8363 static inline void gen_##name(DisasContext *ctx) \
8364 { \
8365 if (unlikely(!ctx->spe_enabled)) { \
8366 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8367 return; \
8368 } \
8369 int l1 = gen_new_label(); \
8370 int l2 = gen_new_label(); \
8371 int l3 = gen_new_label(); \
8372 int l4 = gen_new_label(); \
8373 \
8374 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8375 cpu_gpr[rB(ctx->opcode)], l1); \
8376 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
8377 tcg_gen_br(l2); \
8378 gen_set_label(l1); \
8379 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8380 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8381 gen_set_label(l2); \
8382 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8383 cpu_gprh[rB(ctx->opcode)], l3); \
8384 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8385 ~(CRF_CH | CRF_CH_AND_CL)); \
8386 tcg_gen_br(l4); \
8387 gen_set_label(l3); \
8388 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8389 CRF_CH | CRF_CH_OR_CL); \
8390 gen_set_label(l4); \
8391 }
8392 #endif
8393 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8394 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8395 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8396 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8397 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8398
8399 /* SPE misc */
8400 static inline void gen_brinc(DisasContext *ctx)
8401 {
8402 /* Note: brinc is usable even if SPE is disabled */
8403 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8404 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8405 }
8406 static inline void gen_evmergelo(DisasContext *ctx)
8407 {
8408 if (unlikely(!ctx->spe_enabled)) {
8409 gen_exception(ctx, POWERPC_EXCP_SPEU);
8410 return;
8411 }
8412 #if defined(TARGET_PPC64)
8413 TCGv t0 = tcg_temp_new();
8414 TCGv t1 = tcg_temp_new();
8415 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
8416 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
8417 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8418 tcg_temp_free(t0);
8419 tcg_temp_free(t1);
8420 #else
8421 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8422 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8423 #endif
8424 }
8425 static inline void gen_evmergehilo(DisasContext *ctx)
8426 {
8427 if (unlikely(!ctx->spe_enabled)) {
8428 gen_exception(ctx, POWERPC_EXCP_SPEU);
8429 return;
8430 }
8431 #if defined(TARGET_PPC64)
8432 TCGv t0 = tcg_temp_new();
8433 TCGv t1 = tcg_temp_new();
8434 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
8435 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
8436 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8437 tcg_temp_free(t0);
8438 tcg_temp_free(t1);
8439 #else
8440 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8441 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8442 #endif
8443 }
8444 static inline void gen_evmergelohi(DisasContext *ctx)
8445 {
8446 if (unlikely(!ctx->spe_enabled)) {
8447 gen_exception(ctx, POWERPC_EXCP_SPEU);
8448 return;
8449 }
8450 #if defined(TARGET_PPC64)
8451 TCGv t0 = tcg_temp_new();
8452 TCGv t1 = tcg_temp_new();
8453 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
8454 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
8455 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8456 tcg_temp_free(t0);
8457 tcg_temp_free(t1);
8458 #else
8459 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8460 TCGv_i32 tmp = tcg_temp_new_i32();
8461 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
8462 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8463 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
8464 tcg_temp_free_i32(tmp);
8465 } else {
8466 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8467 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8468 }
8469 #endif
8470 }
8471 static inline void gen_evsplati(DisasContext *ctx)
8472 {
8473 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8474
8475 #if defined(TARGET_PPC64)
8476 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
8477 #else
8478 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
8479 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
8480 #endif
8481 }
8482 static inline void gen_evsplatfi(DisasContext *ctx)
8483 {
8484 uint64_t imm = rA(ctx->opcode) << 27;
8485
8486 #if defined(TARGET_PPC64)
8487 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
8488 #else
8489 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
8490 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
8491 #endif
8492 }
8493
8494 static inline void gen_evsel(DisasContext *ctx)
8495 {
8496 int l1 = gen_new_label();
8497 int l2 = gen_new_label();
8498 int l3 = gen_new_label();
8499 int l4 = gen_new_label();
8500 TCGv_i32 t0 = tcg_temp_local_new_i32();
8501 #if defined(TARGET_PPC64)
8502 TCGv t1 = tcg_temp_local_new();
8503 TCGv t2 = tcg_temp_local_new();
8504 #endif
8505 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8506 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8507 #if defined(TARGET_PPC64)
8508 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
8509 #else
8510 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8511 #endif
8512 tcg_gen_br(l2);
8513 gen_set_label(l1);
8514 #if defined(TARGET_PPC64)
8515 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
8516 #else
8517 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8518 #endif
8519 gen_set_label(l2);
8520 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8521 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8522 #if defined(TARGET_PPC64)
8523 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
8524 #else
8525 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8526 #endif
8527 tcg_gen_br(l4);
8528 gen_set_label(l3);
8529 #if defined(TARGET_PPC64)
8530 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
8531 #else
8532 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8533 #endif
8534 gen_set_label(l4);
8535 tcg_temp_free_i32(t0);
8536 #if defined(TARGET_PPC64)
8537 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
8538 tcg_temp_free(t1);
8539 tcg_temp_free(t2);
8540 #endif
8541 }
8542
8543 static void gen_evsel0(DisasContext *ctx)
8544 {
8545 gen_evsel(ctx);
8546 }
8547
8548 static void gen_evsel1(DisasContext *ctx)
8549 {
8550 gen_evsel(ctx);
8551 }
8552
8553 static void gen_evsel2(DisasContext *ctx)
8554 {
8555 gen_evsel(ctx);
8556 }
8557
8558 static void gen_evsel3(DisasContext *ctx)
8559 {
8560 gen_evsel(ctx);
8561 }
8562
8563 /* Multiply */
8564
8565 static inline void gen_evmwumi(DisasContext *ctx)
8566 {
8567 TCGv_i64 t0, t1;
8568
8569 if (unlikely(!ctx->spe_enabled)) {
8570 gen_exception(ctx, POWERPC_EXCP_SPEU);
8571 return;
8572 }
8573
8574 t0 = tcg_temp_new_i64();
8575 t1 = tcg_temp_new_i64();
8576
8577 /* t0 := rA; t1 := rB */
8578 #if defined(TARGET_PPC64)
8579 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
8580 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
8581 #else
8582 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8583 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8584 #endif
8585
8586 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8587
8588 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8589
8590 tcg_temp_free_i64(t0);
8591 tcg_temp_free_i64(t1);
8592 }
8593
8594 static inline void gen_evmwumia(DisasContext *ctx)
8595 {
8596 TCGv_i64 tmp;
8597
8598 if (unlikely(!ctx->spe_enabled)) {
8599 gen_exception(ctx, POWERPC_EXCP_SPEU);
8600 return;
8601 }
8602
8603 gen_evmwumi(ctx); /* rD := rA * rB */
8604
8605 tmp = tcg_temp_new_i64();
8606
8607 /* acc := rD */
8608 gen_load_gpr64(tmp, rD(ctx->opcode));
8609 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8610 tcg_temp_free_i64(tmp);
8611 }
8612
8613 static inline void gen_evmwumiaa(DisasContext *ctx)
8614 {
8615 TCGv_i64 acc;
8616 TCGv_i64 tmp;
8617
8618 if (unlikely(!ctx->spe_enabled)) {
8619 gen_exception(ctx, POWERPC_EXCP_SPEU);
8620 return;
8621 }
8622
8623 gen_evmwumi(ctx); /* rD := rA * rB */
8624
8625 acc = tcg_temp_new_i64();
8626 tmp = tcg_temp_new_i64();
8627
8628 /* tmp := rD */
8629 gen_load_gpr64(tmp, rD(ctx->opcode));
8630
8631 /* Load acc */
8632 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8633
8634 /* acc := tmp + acc */
8635 tcg_gen_add_i64(acc, acc, tmp);
8636
8637 /* Store acc */
8638 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8639
8640 /* rD := acc */
8641 gen_store_gpr64(rD(ctx->opcode), acc);
8642
8643 tcg_temp_free_i64(acc);
8644 tcg_temp_free_i64(tmp);
8645 }
8646
8647 static inline void gen_evmwsmi(DisasContext *ctx)
8648 {
8649 TCGv_i64 t0, t1;
8650
8651 if (unlikely(!ctx->spe_enabled)) {
8652 gen_exception(ctx, POWERPC_EXCP_SPEU);
8653 return;
8654 }
8655
8656 t0 = tcg_temp_new_i64();
8657 t1 = tcg_temp_new_i64();
8658
8659 /* t0 := rA; t1 := rB */
8660 #if defined(TARGET_PPC64)
8661 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
8662 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
8663 #else
8664 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8665 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8666 #endif
8667
8668 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8669
8670 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8671
8672 tcg_temp_free_i64(t0);
8673 tcg_temp_free_i64(t1);
8674 }
8675
8676 static inline void gen_evmwsmia(DisasContext *ctx)
8677 {
8678 TCGv_i64 tmp;
8679
8680 gen_evmwsmi(ctx); /* rD := rA * rB */
8681
8682 tmp = tcg_temp_new_i64();
8683
8684 /* acc := rD */
8685 gen_load_gpr64(tmp, rD(ctx->opcode));
8686 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8687
8688 tcg_temp_free_i64(tmp);
8689 }
8690
8691 static inline void gen_evmwsmiaa(DisasContext *ctx)
8692 {
8693 TCGv_i64 acc = tcg_temp_new_i64();
8694 TCGv_i64 tmp = tcg_temp_new_i64();
8695
8696 gen_evmwsmi(ctx); /* rD := rA * rB */
8697
8698 acc = tcg_temp_new_i64();
8699 tmp = tcg_temp_new_i64();
8700
8701 /* tmp := rD */
8702 gen_load_gpr64(tmp, rD(ctx->opcode));
8703
8704 /* Load acc */
8705 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8706
8707 /* acc := tmp + acc */
8708 tcg_gen_add_i64(acc, acc, tmp);
8709
8710 /* Store acc */
8711 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8712
8713 /* rD := acc */
8714 gen_store_gpr64(rD(ctx->opcode), acc);
8715
8716 tcg_temp_free_i64(acc);
8717 tcg_temp_free_i64(tmp);
8718 }
8719
8720 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8721 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8722 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8723 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8724 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8725 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8726 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8727 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
8728 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
8729 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8730 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8731 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8732 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8733 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8734 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8735 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8736 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8737 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8738 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8739 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
8740 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8741 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8742 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
8743 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
8744 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8745 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8746 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8747 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8748 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
8749
8750 /* SPE load and stores */
8751 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
8752 {
8753 target_ulong uimm = rB(ctx->opcode);
8754
8755 if (rA(ctx->opcode) == 0) {
8756 tcg_gen_movi_tl(EA, uimm << sh);
8757 } else {
8758 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
8759 if (NARROW_MODE(ctx)) {
8760 tcg_gen_ext32u_tl(EA, EA);
8761 }
8762 }
8763 }
8764
8765 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
8766 {
8767 #if defined(TARGET_PPC64)
8768 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8769 #else
8770 TCGv_i64 t0 = tcg_temp_new_i64();
8771 gen_qemu_ld64(ctx, t0, addr);
8772 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
8773 tcg_gen_shri_i64(t0, t0, 32);
8774 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
8775 tcg_temp_free_i64(t0);
8776 #endif
8777 }
8778
8779 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
8780 {
8781 #if defined(TARGET_PPC64)
8782 TCGv t0 = tcg_temp_new();
8783 gen_qemu_ld32u(ctx, t0, addr);
8784 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8785 gen_addr_add(ctx, addr, addr, 4);
8786 gen_qemu_ld32u(ctx, t0, addr);
8787 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8788 tcg_temp_free(t0);
8789 #else
8790 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
8791 gen_addr_add(ctx, addr, addr, 4);
8792 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8793 #endif
8794 }
8795
8796 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
8797 {
8798 TCGv t0 = tcg_temp_new();
8799 #if defined(TARGET_PPC64)
8800 gen_qemu_ld16u(ctx, t0, addr);
8801 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8802 gen_addr_add(ctx, addr, addr, 2);
8803 gen_qemu_ld16u(ctx, t0, addr);
8804 tcg_gen_shli_tl(t0, t0, 32);
8805 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8806 gen_addr_add(ctx, addr, addr, 2);
8807 gen_qemu_ld16u(ctx, t0, addr);
8808 tcg_gen_shli_tl(t0, t0, 16);
8809 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8810 gen_addr_add(ctx, addr, addr, 2);
8811 gen_qemu_ld16u(ctx, t0, addr);
8812 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8813 #else
8814 gen_qemu_ld16u(ctx, t0, addr);
8815 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8816 gen_addr_add(ctx, addr, addr, 2);
8817 gen_qemu_ld16u(ctx, t0, addr);
8818 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
8819 gen_addr_add(ctx, addr, addr, 2);
8820 gen_qemu_ld16u(ctx, t0, addr);
8821 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8822 gen_addr_add(ctx, addr, addr, 2);
8823 gen_qemu_ld16u(ctx, t0, addr);
8824 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8825 #endif
8826 tcg_temp_free(t0);
8827 }
8828
8829 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
8830 {
8831 TCGv t0 = tcg_temp_new();
8832 gen_qemu_ld16u(ctx, t0, addr);
8833 #if defined(TARGET_PPC64)
8834 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8835 tcg_gen_shli_tl(t0, t0, 16);
8836 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8837 #else
8838 tcg_gen_shli_tl(t0, t0, 16);
8839 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8840 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8841 #endif
8842 tcg_temp_free(t0);
8843 }
8844
8845 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
8846 {
8847 TCGv t0 = tcg_temp_new();
8848 gen_qemu_ld16u(ctx, t0, addr);
8849 #if defined(TARGET_PPC64)
8850 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8851 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8852 #else
8853 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8854 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8855 #endif
8856 tcg_temp_free(t0);
8857 }
8858
8859 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
8860 {
8861 TCGv t0 = tcg_temp_new();
8862 gen_qemu_ld16s(ctx, t0, addr);
8863 #if defined(TARGET_PPC64)
8864 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8865 tcg_gen_ext32u_tl(t0, t0);
8866 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8867 #else
8868 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8869 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8870 #endif
8871 tcg_temp_free(t0);
8872 }
8873
8874 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
8875 {
8876 TCGv t0 = tcg_temp_new();
8877 #if defined(TARGET_PPC64)
8878 gen_qemu_ld16u(ctx, t0, addr);
8879 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8880 gen_addr_add(ctx, addr, addr, 2);
8881 gen_qemu_ld16u(ctx, t0, addr);
8882 tcg_gen_shli_tl(t0, t0, 16);
8883 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8884 #else
8885 gen_qemu_ld16u(ctx, t0, addr);
8886 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8887 gen_addr_add(ctx, addr, addr, 2);
8888 gen_qemu_ld16u(ctx, t0, addr);
8889 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
8890 #endif
8891 tcg_temp_free(t0);
8892 }
8893
8894 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
8895 {
8896 #if defined(TARGET_PPC64)
8897 TCGv t0 = tcg_temp_new();
8898 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8899 gen_addr_add(ctx, addr, addr, 2);
8900 gen_qemu_ld16u(ctx, t0, addr);
8901 tcg_gen_shli_tl(t0, t0, 32);
8902 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8903 tcg_temp_free(t0);
8904 #else
8905 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
8906 gen_addr_add(ctx, addr, addr, 2);
8907 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8908 #endif
8909 }
8910
8911 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
8912 {
8913 #if defined(TARGET_PPC64)
8914 TCGv t0 = tcg_temp_new();
8915 gen_qemu_ld16s(ctx, t0, addr);
8916 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
8917 gen_addr_add(ctx, addr, addr, 2);
8918 gen_qemu_ld16s(ctx, t0, addr);
8919 tcg_gen_shli_tl(t0, t0, 32);
8920 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8921 tcg_temp_free(t0);
8922 #else
8923 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
8924 gen_addr_add(ctx, addr, addr, 2);
8925 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8926 #endif
8927 }
8928
8929 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
8930 {
8931 TCGv t0 = tcg_temp_new();
8932 gen_qemu_ld32u(ctx, t0, addr);
8933 #if defined(TARGET_PPC64)
8934 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8935 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8936 #else
8937 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8938 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8939 #endif
8940 tcg_temp_free(t0);
8941 }
8942
8943 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
8944 {
8945 TCGv t0 = tcg_temp_new();
8946 #if defined(TARGET_PPC64)
8947 gen_qemu_ld16u(ctx, t0, addr);
8948 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8949 tcg_gen_shli_tl(t0, t0, 32);
8950 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8951 gen_addr_add(ctx, addr, addr, 2);
8952 gen_qemu_ld16u(ctx, t0, addr);
8953 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8954 tcg_gen_shli_tl(t0, t0, 16);
8955 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8956 #else
8957 gen_qemu_ld16u(ctx, t0, addr);
8958 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8959 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
8960 gen_addr_add(ctx, addr, addr, 2);
8961 gen_qemu_ld16u(ctx, t0, addr);
8962 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
8963 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
8964 #endif
8965 tcg_temp_free(t0);
8966 }
8967
8968 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
8969 {
8970 #if defined(TARGET_PPC64)
8971 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8972 #else
8973 TCGv_i64 t0 = tcg_temp_new_i64();
8974 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
8975 gen_qemu_st64(ctx, t0, addr);
8976 tcg_temp_free_i64(t0);
8977 #endif
8978 }
8979
8980 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
8981 {
8982 #if defined(TARGET_PPC64)
8983 TCGv t0 = tcg_temp_new();
8984 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8985 gen_qemu_st32(ctx, t0, addr);
8986 tcg_temp_free(t0);
8987 #else
8988 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8989 #endif
8990 gen_addr_add(ctx, addr, addr, 4);
8991 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8992 }
8993
8994 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
8995 {
8996 TCGv t0 = tcg_temp_new();
8997 #if defined(TARGET_PPC64)
8998 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
8999 #else
9000 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9001 #endif
9002 gen_qemu_st16(ctx, t0, addr);
9003 gen_addr_add(ctx, addr, addr, 2);
9004 #if defined(TARGET_PPC64)
9005 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
9006 gen_qemu_st16(ctx, t0, addr);
9007 #else
9008 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9009 #endif
9010 gen_addr_add(ctx, addr, addr, 2);
9011 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9012 gen_qemu_st16(ctx, t0, addr);
9013 tcg_temp_free(t0);
9014 gen_addr_add(ctx, addr, addr, 2);
9015 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9016 }
9017
9018 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9019 {
9020 TCGv t0 = tcg_temp_new();
9021 #if defined(TARGET_PPC64)
9022 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
9023 #else
9024 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9025 #endif
9026 gen_qemu_st16(ctx, t0, addr);
9027 gen_addr_add(ctx, addr, addr, 2);
9028 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9029 gen_qemu_st16(ctx, t0, addr);
9030 tcg_temp_free(t0);
9031 }
9032
9033 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9034 {
9035 #if defined(TARGET_PPC64)
9036 TCGv t0 = tcg_temp_new();
9037 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
9038 gen_qemu_st16(ctx, t0, addr);
9039 tcg_temp_free(t0);
9040 #else
9041 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9042 #endif
9043 gen_addr_add(ctx, addr, addr, 2);
9044 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9045 }
9046
9047 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9048 {
9049 #if defined(TARGET_PPC64)
9050 TCGv t0 = tcg_temp_new();
9051 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
9052 gen_qemu_st32(ctx, t0, addr);
9053 tcg_temp_free(t0);
9054 #else
9055 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9056 #endif
9057 }
9058
9059 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9060 {
9061 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9062 }
9063
9064 #define GEN_SPEOP_LDST(name, opc2, sh) \
9065 static void glue(gen_, name)(DisasContext *ctx) \
9066 { \
9067 TCGv t0; \
9068 if (unlikely(!ctx->spe_enabled)) { \
9069 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9070 return; \
9071 } \
9072 gen_set_access_type(ctx, ACCESS_INT); \
9073 t0 = tcg_temp_new(); \
9074 if (Rc(ctx->opcode)) { \
9075 gen_addr_spe_imm_index(ctx, t0, sh); \
9076 } else { \
9077 gen_addr_reg_index(ctx, t0); \
9078 } \
9079 gen_op_##name(ctx, t0); \
9080 tcg_temp_free(t0); \
9081 }
9082
9083 GEN_SPEOP_LDST(evldd, 0x00, 3);
9084 GEN_SPEOP_LDST(evldw, 0x01, 3);
9085 GEN_SPEOP_LDST(evldh, 0x02, 3);
9086 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9087 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9088 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9089 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9090 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9091 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9092 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9093 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9094
9095 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9096 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9097 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9098 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9099 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9100 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9101 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9102
9103 /* Multiply and add - TODO */
9104 #if 0
9105 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9106 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9107 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9108 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9109 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9110 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9111 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9112 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9113 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9114 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9115 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9116 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9117
9118 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9119 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9120 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9121 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9122 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9123 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9124 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9125 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9126 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9127 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9128 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9129 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9130
9131 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9132 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9133 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9134 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9135 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9136
9137 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9138 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9139 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9140 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9141 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9142 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9143 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9144 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9145 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9146 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9147 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9148 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9149
9150 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9151 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9152 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9153 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9154
9155 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9156 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9157 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9158 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9159 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9160 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9161 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9162 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9163 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9164 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9165 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9166 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9167
9168 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9169 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9170 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9171 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9172 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9173 #endif
9174
9175 /*** SPE floating-point extension ***/
9176 #if defined(TARGET_PPC64)
9177 #define GEN_SPEFPUOP_CONV_32_32(name) \
9178 static inline void gen_##name(DisasContext *ctx) \
9179 { \
9180 TCGv_i32 t0; \
9181 TCGv t1; \
9182 t0 = tcg_temp_new_i32(); \
9183 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9184 gen_helper_##name(t0, cpu_env, t0); \
9185 t1 = tcg_temp_new(); \
9186 tcg_gen_extu_i32_tl(t1, t0); \
9187 tcg_temp_free_i32(t0); \
9188 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9189 0xFFFFFFFF00000000ULL); \
9190 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
9191 tcg_temp_free(t1); \
9192 }
9193 #define GEN_SPEFPUOP_CONV_32_64(name) \
9194 static inline void gen_##name(DisasContext *ctx) \
9195 { \
9196 TCGv_i32 t0; \
9197 TCGv t1; \
9198 t0 = tcg_temp_new_i32(); \
9199 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
9200 t1 = tcg_temp_new(); \
9201 tcg_gen_extu_i32_tl(t1, t0); \
9202 tcg_temp_free_i32(t0); \
9203 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9204 0xFFFFFFFF00000000ULL); \
9205 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
9206 tcg_temp_free(t1); \
9207 }
9208 #define GEN_SPEFPUOP_CONV_64_32(name) \
9209 static inline void gen_##name(DisasContext *ctx) \
9210 { \
9211 TCGv_i32 t0 = tcg_temp_new_i32(); \
9212 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9213 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
9214 tcg_temp_free_i32(t0); \
9215 }
9216 #define GEN_SPEFPUOP_CONV_64_64(name) \
9217 static inline void gen_##name(DisasContext *ctx) \
9218 { \
9219 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9220 cpu_gpr[rB(ctx->opcode)]); \
9221 }
9222 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9223 static inline void gen_##name(DisasContext *ctx) \
9224 { \
9225 TCGv_i32 t0, t1; \
9226 TCGv_i64 t2; \
9227 if (unlikely(!ctx->spe_enabled)) { \
9228 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9229 return; \
9230 } \
9231 t0 = tcg_temp_new_i32(); \
9232 t1 = tcg_temp_new_i32(); \
9233 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9234 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9235 gen_helper_##name(t0, cpu_env, t0, t1); \
9236 tcg_temp_free_i32(t1); \
9237 t2 = tcg_temp_new(); \
9238 tcg_gen_extu_i32_tl(t2, t0); \
9239 tcg_temp_free_i32(t0); \
9240 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9241 0xFFFFFFFF00000000ULL); \
9242 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
9243 tcg_temp_free(t2); \
9244 }
9245 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9246 static inline void gen_##name(DisasContext *ctx) \
9247 { \
9248 if (unlikely(!ctx->spe_enabled)) { \
9249 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9250 return; \
9251 } \
9252 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9253 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9254 }
9255 #define GEN_SPEFPUOP_COMP_32(name) \
9256 static inline void gen_##name(DisasContext *ctx) \
9257 { \
9258 TCGv_i32 t0, t1; \
9259 if (unlikely(!ctx->spe_enabled)) { \
9260 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9261 return; \
9262 } \
9263 t0 = tcg_temp_new_i32(); \
9264 t1 = tcg_temp_new_i32(); \
9265 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9266 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9267 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9268 tcg_temp_free_i32(t0); \
9269 tcg_temp_free_i32(t1); \
9270 }
9271 #define GEN_SPEFPUOP_COMP_64(name) \
9272 static inline void gen_##name(DisasContext *ctx) \
9273 { \
9274 if (unlikely(!ctx->spe_enabled)) { \
9275 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9276 return; \
9277 } \
9278 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
9279 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9280 }
9281 #else
9282 #define GEN_SPEFPUOP_CONV_32_32(name) \
9283 static inline void gen_##name(DisasContext *ctx) \
9284 { \
9285 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9286 cpu_gpr[rB(ctx->opcode)]); \
9287 }
9288 #define GEN_SPEFPUOP_CONV_32_64(name) \
9289 static inline void gen_##name(DisasContext *ctx) \
9290 { \
9291 TCGv_i64 t0 = tcg_temp_new_i64(); \
9292 gen_load_gpr64(t0, rB(ctx->opcode)); \
9293 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
9294 tcg_temp_free_i64(t0); \
9295 }
9296 #define GEN_SPEFPUOP_CONV_64_32(name) \
9297 static inline void gen_##name(DisasContext *ctx) \
9298 { \
9299 TCGv_i64 t0 = tcg_temp_new_i64(); \
9300 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
9301 gen_store_gpr64(rD(ctx->opcode), t0); \
9302 tcg_temp_free_i64(t0); \
9303 }
9304 #define GEN_SPEFPUOP_CONV_64_64(name) \
9305 static inline void gen_##name(DisasContext *ctx) \
9306 { \
9307 TCGv_i64 t0 = tcg_temp_new_i64(); \
9308 gen_load_gpr64(t0, rB(ctx->opcode)); \
9309 gen_helper_##name(t0, cpu_env, t0); \
9310 gen_store_gpr64(rD(ctx->opcode), t0); \
9311 tcg_temp_free_i64(t0); \
9312 }
9313 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9314 static inline void gen_##name(DisasContext *ctx) \
9315 { \
9316 if (unlikely(!ctx->spe_enabled)) { \
9317 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9318 return; \
9319 } \
9320 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9321 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9322 }
9323 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9324 static inline void gen_##name(DisasContext *ctx) \
9325 { \
9326 TCGv_i64 t0, t1; \
9327 if (unlikely(!ctx->spe_enabled)) { \
9328 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9329 return; \
9330 } \
9331 t0 = tcg_temp_new_i64(); \
9332 t1 = tcg_temp_new_i64(); \
9333 gen_load_gpr64(t0, rA(ctx->opcode)); \
9334 gen_load_gpr64(t1, rB(ctx->opcode)); \
9335 gen_helper_##name(t0, cpu_env, t0, t1); \
9336 gen_store_gpr64(rD(ctx->opcode), t0); \
9337 tcg_temp_free_i64(t0); \
9338 tcg_temp_free_i64(t1); \
9339 }
9340 #define GEN_SPEFPUOP_COMP_32(name) \
9341 static inline void gen_##name(DisasContext *ctx) \
9342 { \
9343 if (unlikely(!ctx->spe_enabled)) { \
9344 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9345 return; \
9346 } \
9347 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
9348 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9349 }
9350 #define GEN_SPEFPUOP_COMP_64(name) \
9351 static inline void gen_##name(DisasContext *ctx) \
9352 { \
9353 TCGv_i64 t0, t1; \
9354 if (unlikely(!ctx->spe_enabled)) { \
9355 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9356 return; \
9357 } \
9358 t0 = tcg_temp_new_i64(); \
9359 t1 = tcg_temp_new_i64(); \
9360 gen_load_gpr64(t0, rA(ctx->opcode)); \
9361 gen_load_gpr64(t1, rB(ctx->opcode)); \
9362 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9363 tcg_temp_free_i64(t0); \
9364 tcg_temp_free_i64(t1); \
9365 }
9366 #endif
9367
9368 /* Single precision floating-point vectors operations */
9369 /* Arithmetic */
9370 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9371 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9372 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9373 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9374 static inline void gen_evfsabs(DisasContext *ctx)
9375 {
9376 if (unlikely(!ctx->spe_enabled)) {
9377 gen_exception(ctx, POWERPC_EXCP_SPEU);
9378 return;
9379 }
9380 #if defined(TARGET_PPC64)
9381 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
9382 #else
9383 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
9384 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
9385 #endif
9386 }
9387 static inline void gen_evfsnabs(DisasContext *ctx)
9388 {
9389 if (unlikely(!ctx->spe_enabled)) {
9390 gen_exception(ctx, POWERPC_EXCP_SPEU);
9391 return;
9392 }
9393 #if defined(TARGET_PPC64)
9394 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
9395 #else
9396 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9397 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9398 #endif
9399 }
9400 static inline void gen_evfsneg(DisasContext *ctx)
9401 {
9402 if (unlikely(!ctx->spe_enabled)) {
9403 gen_exception(ctx, POWERPC_EXCP_SPEU);
9404 return;
9405 }
9406 #if defined(TARGET_PPC64)
9407 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
9408 #else
9409 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9410 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9411 #endif
9412 }
9413
9414 /* Conversion */
9415 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9416 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9417 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9418 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9419 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9420 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9421 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9422 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9423 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9424 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9425
9426 /* Comparison */
9427 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9428 GEN_SPEFPUOP_COMP_64(evfscmplt);
9429 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9430 GEN_SPEFPUOP_COMP_64(evfststgt);
9431 GEN_SPEFPUOP_COMP_64(evfststlt);
9432 GEN_SPEFPUOP_COMP_64(evfststeq);
9433
9434 /* Opcodes definitions */
9435 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9436 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9437 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9438 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9439 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9440 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9441 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9442 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9443 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9444 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9445 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9446 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9447 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9448 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9449
9450 /* Single precision floating-point operations */
9451 /* Arithmetic */
9452 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9453 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9454 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9455 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9456 static inline void gen_efsabs(DisasContext *ctx)
9457 {
9458 if (unlikely(!ctx->spe_enabled)) {
9459 gen_exception(ctx, POWERPC_EXCP_SPEU);
9460 return;
9461 }
9462 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9463 }
9464 static inline void gen_efsnabs(DisasContext *ctx)
9465 {
9466 if (unlikely(!ctx->spe_enabled)) {
9467 gen_exception(ctx, POWERPC_EXCP_SPEU);
9468 return;
9469 }
9470 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9471 }
9472 static inline void gen_efsneg(DisasContext *ctx)
9473 {
9474 if (unlikely(!ctx->spe_enabled)) {
9475 gen_exception(ctx, POWERPC_EXCP_SPEU);
9476 return;
9477 }
9478 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9479 }
9480
9481 /* Conversion */
9482 GEN_SPEFPUOP_CONV_32_32(efscfui);
9483 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9484 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9485 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9486 GEN_SPEFPUOP_CONV_32_32(efsctui);
9487 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9488 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9489 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9490 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9491 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9492 GEN_SPEFPUOP_CONV_32_64(efscfd);
9493
9494 /* Comparison */
9495 GEN_SPEFPUOP_COMP_32(efscmpgt);
9496 GEN_SPEFPUOP_COMP_32(efscmplt);
9497 GEN_SPEFPUOP_COMP_32(efscmpeq);
9498 GEN_SPEFPUOP_COMP_32(efststgt);
9499 GEN_SPEFPUOP_COMP_32(efststlt);
9500 GEN_SPEFPUOP_COMP_32(efststeq);
9501
9502 /* Opcodes definitions */
9503 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9504 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9505 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9506 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9507 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9508 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9509 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9510 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9511 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9512 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9513 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9514 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9515 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9516 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9517
9518 /* Double precision floating-point operations */
9519 /* Arithmetic */
9520 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9521 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9522 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9523 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9524 static inline void gen_efdabs(DisasContext *ctx)
9525 {
9526 if (unlikely(!ctx->spe_enabled)) {
9527 gen_exception(ctx, POWERPC_EXCP_SPEU);
9528 return;
9529 }
9530 #if defined(TARGET_PPC64)
9531 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
9532 #else
9533 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9534 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
9535 #endif
9536 }
9537 static inline void gen_efdnabs(DisasContext *ctx)
9538 {
9539 if (unlikely(!ctx->spe_enabled)) {
9540 gen_exception(ctx, POWERPC_EXCP_SPEU);
9541 return;
9542 }
9543 #if defined(TARGET_PPC64)
9544 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
9545 #else
9546 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9547 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9548 #endif
9549 }
9550 static inline void gen_efdneg(DisasContext *ctx)
9551 {
9552 if (unlikely(!ctx->spe_enabled)) {
9553 gen_exception(ctx, POWERPC_EXCP_SPEU);
9554 return;
9555 }
9556 #if defined(TARGET_PPC64)
9557 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
9558 #else
9559 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9560 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9561 #endif
9562 }
9563
9564 /* Conversion */
9565 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9566 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9567 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9568 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9569 GEN_SPEFPUOP_CONV_32_64(efdctui);
9570 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9571 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9572 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9573 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9574 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9575 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9576 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9577 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9578 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9579 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9580
9581 /* Comparison */
9582 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9583 GEN_SPEFPUOP_COMP_64(efdcmplt);
9584 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9585 GEN_SPEFPUOP_COMP_64(efdtstgt);
9586 GEN_SPEFPUOP_COMP_64(efdtstlt);
9587 GEN_SPEFPUOP_COMP_64(efdtsteq);
9588
9589 /* Opcodes definitions */
9590 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9591 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9592 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9593 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9594 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9595 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9596 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9597 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9598 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9599 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9600 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9601 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9602 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9603 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9604 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9605 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9606
9607 static opcode_t opcodes[] = {
9608 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9609 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9610 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9611 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9612 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9613 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9614 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9615 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9616 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9617 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9618 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9619 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9620 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9621 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9622 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9623 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9624 #if defined(TARGET_PPC64)
9625 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9626 #endif
9627 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9628 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9629 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9630 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9631 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9632 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9633 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9634 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9635 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9636 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9637 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9638 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9639 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
9640 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9641 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9642 #if defined(TARGET_PPC64)
9643 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9644 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9645 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9646 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9647 #endif
9648 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9649 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9650 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9651 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9652 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9653 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9654 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9655 #if defined(TARGET_PPC64)
9656 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9657 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9658 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9659 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9660 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9661 #endif
9662 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9663 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9664 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9665 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9666 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9667 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9668 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9669 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9670 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9671 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9672 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9673 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9674 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9675 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9676 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9677 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9678 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9679 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9680 #if defined(TARGET_PPC64)
9681 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9682 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9683 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9684 #endif
9685 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9686 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9687 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9688 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9689 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9690 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9691 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9692 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9693 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9694 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9695 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9696 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9697 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9698 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9699 #if defined(TARGET_PPC64)
9700 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9701 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9702 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9703 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9704 #endif
9705 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9706 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9707 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9708 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9709 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9710 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9711 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9712 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9713 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9714 #if defined(TARGET_PPC64)
9715 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9716 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9717 #endif
9718 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9719 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9720 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9721 #if defined(TARGET_PPC64)
9722 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9723 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9724 #endif
9725 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9726 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9727 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9728 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9729 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9730 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9731 #if defined(TARGET_PPC64)
9732 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9733 #endif
9734 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9735 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
9736 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9737 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9738 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9739 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9740 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9741 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9742 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9743 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9744 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9745 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9746 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9747 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9748 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9749 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9750 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9751 #if defined(TARGET_PPC64)
9752 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9753 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9754 PPC_SEGMENT_64B),
9755 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9756 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9757 PPC_SEGMENT_64B),
9758 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9759 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9760 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9761 #endif
9762 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9763 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9764 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9765 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9766 #if defined(TARGET_PPC64)
9767 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9768 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9769 #endif
9770 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9771 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9772 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9773 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9774 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9775 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9776 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9777 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9778 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9779 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9780 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9781 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9782 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9783 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9784 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9785 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9786 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9787 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9788 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9789 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9790 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9791 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9792 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9793 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9794 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9795 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9796 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9797 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9798 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9799 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9800 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9801 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9802 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9803 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9804 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9805 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9806 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9807 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9808 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9809 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
9810 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
9811 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
9812 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
9813 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
9814 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
9815 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
9816 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
9817 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
9818 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
9819 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9820 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9821 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
9822 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
9823 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9824 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9825 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
9826 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
9827 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
9828 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
9829 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
9830 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
9831 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
9832 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
9833 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
9834 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
9835 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
9836 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
9837 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
9838 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
9839 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
9840 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
9841 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
9842 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
9843 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
9844 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
9845 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
9846 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
9847 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
9848 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
9849 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
9850 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
9851 PPC_NONE, PPC2_BOOKE206),
9852 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
9853 PPC_NONE, PPC2_BOOKE206),
9854 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
9855 PPC_NONE, PPC2_BOOKE206),
9856 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
9857 PPC_NONE, PPC2_BOOKE206),
9858 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
9859 PPC_NONE, PPC2_BOOKE206),
9860 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
9861 PPC_NONE, PPC2_PRCNTL),
9862 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
9863 PPC_NONE, PPC2_PRCNTL),
9864 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
9865 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
9866 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
9867 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
9868 PPC_BOOKE, PPC2_BOOKE206),
9869 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
9870 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
9871 PPC_BOOKE, PPC2_BOOKE206),
9872 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
9873 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
9874 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
9875 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
9876 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
9877 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
9878 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
9879 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
9880 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
9881 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
9882
9883 #undef GEN_INT_ARITH_ADD
9884 #undef GEN_INT_ARITH_ADD_CONST
9885 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
9886 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
9887 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
9888 add_ca, compute_ca, compute_ov) \
9889 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
9890 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
9891 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
9892 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
9893 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
9894 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
9895 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
9896 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
9897 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
9898 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
9899 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
9900
9901 #undef GEN_INT_ARITH_DIVW
9902 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
9903 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
9904 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
9905 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
9906 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
9907 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
9908 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9909 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9910 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9911 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9912
9913 #if defined(TARGET_PPC64)
9914 #undef GEN_INT_ARITH_DIVD
9915 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
9916 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9917 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
9918 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
9919 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
9920 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
9921
9922 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9923 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9924 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9925 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9926
9927 #undef GEN_INT_ARITH_MUL_HELPER
9928 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
9929 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9930 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
9931 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
9932 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
9933 #endif
9934
9935 #undef GEN_INT_ARITH_SUBF
9936 #undef GEN_INT_ARITH_SUBF_CONST
9937 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
9938 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
9939 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
9940 add_ca, compute_ca, compute_ov) \
9941 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
9942 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
9943 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
9944 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
9945 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
9946 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
9947 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
9948 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
9949 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
9950 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
9951 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
9952
9953 #undef GEN_LOGICAL1
9954 #undef GEN_LOGICAL2
9955 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
9956 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
9957 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
9958 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
9959 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
9960 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
9961 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
9962 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
9963 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
9964 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
9965 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
9966 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
9967 #if defined(TARGET_PPC64)
9968 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
9969 #endif
9970
9971 #if defined(TARGET_PPC64)
9972 #undef GEN_PPC64_R2
9973 #undef GEN_PPC64_R4
9974 #define GEN_PPC64_R2(name, opc1, opc2) \
9975 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9976 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9977 PPC_64B)
9978 #define GEN_PPC64_R4(name, opc1, opc2) \
9979 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9980 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
9981 PPC_64B), \
9982 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9983 PPC_64B), \
9984 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
9985 PPC_64B)
9986 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
9987 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
9988 GEN_PPC64_R4(rldic, 0x1E, 0x04),
9989 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
9990 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
9991 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
9992 #endif
9993
9994 #undef _GEN_FLOAT_ACB
9995 #undef GEN_FLOAT_ACB
9996 #undef _GEN_FLOAT_AB
9997 #undef GEN_FLOAT_AB
9998 #undef _GEN_FLOAT_AC
9999 #undef GEN_FLOAT_AC
10000 #undef GEN_FLOAT_B
10001 #undef GEN_FLOAT_BS
10002 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10003 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10004 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10005 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10006 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10007 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10008 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10009 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10010 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10011 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10012 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10013 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10014 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10015 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10016 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10017 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10018 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10019 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10020 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10021
10022 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10023 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10024 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10025 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10026 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10027 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10028 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10029 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10030 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10031 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10032 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10033 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10034 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10035 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10036 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10037 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10038 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10039 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10040 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10041 #if defined(TARGET_PPC64)
10042 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
10043 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10044 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10045 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10046 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
10047 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10048 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
10049 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10050 #endif
10051 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10052 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10053 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10054 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10055
10056 #undef GEN_LD
10057 #undef GEN_LDU
10058 #undef GEN_LDUX
10059 #undef GEN_LDX_E
10060 #undef GEN_LDS
10061 #define GEN_LD(name, ldop, opc, type) \
10062 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10063 #define GEN_LDU(name, ldop, opc, type) \
10064 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10065 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10066 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10067 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10068 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10069 #define GEN_LDS(name, ldop, op, type) \
10070 GEN_LD(name, ldop, op | 0x20, type) \
10071 GEN_LDU(name, ldop, op | 0x21, type) \
10072 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10073 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10074
10075 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10076 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10077 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10078 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10079 #if defined(TARGET_PPC64)
10080 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10081 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10082 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10083 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10084 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10085 #endif
10086 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10087 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10088
10089 #undef GEN_ST
10090 #undef GEN_STU
10091 #undef GEN_STUX
10092 #undef GEN_STX_E
10093 #undef GEN_STS
10094 #define GEN_ST(name, stop, opc, type) \
10095 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10096 #define GEN_STU(name, stop, opc, type) \
10097 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10098 #define GEN_STUX(name, stop, opc2, opc3, type) \
10099 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10100 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10101 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10102 #define GEN_STS(name, stop, op, type) \
10103 GEN_ST(name, stop, op | 0x20, type) \
10104 GEN_STU(name, stop, op | 0x21, type) \
10105 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10106 GEN_STX(name, stop, 0x17, op | 0x00, type)
10107
10108 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10109 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10110 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10111 #if defined(TARGET_PPC64)
10112 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10113 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10114 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10115 #endif
10116 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10117 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10118
10119 #undef GEN_LDF
10120 #undef GEN_LDUF
10121 #undef GEN_LDUXF
10122 #undef GEN_LDXF
10123 #undef GEN_LDFS
10124 #define GEN_LDF(name, ldop, opc, type) \
10125 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10126 #define GEN_LDUF(name, ldop, opc, type) \
10127 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10128 #define GEN_LDUXF(name, ldop, opc, type) \
10129 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10130 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10131 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10132 #define GEN_LDFS(name, ldop, op, type) \
10133 GEN_LDF(name, ldop, op | 0x20, type) \
10134 GEN_LDUF(name, ldop, op | 0x21, type) \
10135 GEN_LDUXF(name, ldop, op | 0x01, type) \
10136 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10137
10138 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10139 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10140 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10141 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10142 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10143 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10144
10145 #undef GEN_STF
10146 #undef GEN_STUF
10147 #undef GEN_STUXF
10148 #undef GEN_STXF
10149 #undef GEN_STFS
10150 #define GEN_STF(name, stop, opc, type) \
10151 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10152 #define GEN_STUF(name, stop, opc, type) \
10153 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10154 #define GEN_STUXF(name, stop, opc, type) \
10155 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10156 #define GEN_STXF(name, stop, opc2, opc3, type) \
10157 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10158 #define GEN_STFS(name, stop, op, type) \
10159 GEN_STF(name, stop, op | 0x20, type) \
10160 GEN_STUF(name, stop, op | 0x21, type) \
10161 GEN_STUXF(name, stop, op | 0x01, type) \
10162 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10163
10164 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10165 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10166 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10167 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10168 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10169
10170 #undef GEN_CRLOGIC
10171 #define GEN_CRLOGIC(name, tcg_op, opc) \
10172 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10173 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10174 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10175 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10176 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10177 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10178 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10179 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10180 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10181
10182 #undef GEN_MAC_HANDLER
10183 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10184 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10185 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10186 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10187 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10188 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10189 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10190 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10191 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10192 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10193 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10194 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10195 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10196 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10197 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10198 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10199 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10200 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10201 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10202 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10203 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10204 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10205 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10206 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10207 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10208 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10209 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10210 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10211 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10212 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10213 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10214 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10215 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10216 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10217 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10218 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10219 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10220 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10221 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10222 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10223 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10224 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10225 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10226 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10227
10228 #undef GEN_VR_LDX
10229 #undef GEN_VR_STX
10230 #undef GEN_VR_LVE
10231 #undef GEN_VR_STVE
10232 #define GEN_VR_LDX(name, opc2, opc3) \
10233 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10234 #define GEN_VR_STX(name, opc2, opc3) \
10235 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10236 #define GEN_VR_LVE(name, opc2, opc3) \
10237 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10238 #define GEN_VR_STVE(name, opc2, opc3) \
10239 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10240 GEN_VR_LDX(lvx, 0x07, 0x03),
10241 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10242 GEN_VR_LVE(bx, 0x07, 0x00),
10243 GEN_VR_LVE(hx, 0x07, 0x01),
10244 GEN_VR_LVE(wx, 0x07, 0x02),
10245 GEN_VR_STX(svx, 0x07, 0x07),
10246 GEN_VR_STX(svxl, 0x07, 0x0F),
10247 GEN_VR_STVE(bx, 0x07, 0x04),
10248 GEN_VR_STVE(hx, 0x07, 0x05),
10249 GEN_VR_STVE(wx, 0x07, 0x06),
10250
10251 #undef GEN_VX_LOGICAL
10252 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10253 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10254 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10255 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10256 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10257 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10258 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10259
10260 #undef GEN_VXFORM
10261 #define GEN_VXFORM(name, opc2, opc3) \
10262 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10263 GEN_VXFORM(vaddubm, 0, 0),
10264 GEN_VXFORM(vadduhm, 0, 1),
10265 GEN_VXFORM(vadduwm, 0, 2),
10266 GEN_VXFORM(vsububm, 0, 16),
10267 GEN_VXFORM(vsubuhm, 0, 17),
10268 GEN_VXFORM(vsubuwm, 0, 18),
10269 GEN_VXFORM(vmaxub, 1, 0),
10270 GEN_VXFORM(vmaxuh, 1, 1),
10271 GEN_VXFORM(vmaxuw, 1, 2),
10272 GEN_VXFORM(vmaxsb, 1, 4),
10273 GEN_VXFORM(vmaxsh, 1, 5),
10274 GEN_VXFORM(vmaxsw, 1, 6),
10275 GEN_VXFORM(vminub, 1, 8),
10276 GEN_VXFORM(vminuh, 1, 9),
10277 GEN_VXFORM(vminuw, 1, 10),
10278 GEN_VXFORM(vminsb, 1, 12),
10279 GEN_VXFORM(vminsh, 1, 13),
10280 GEN_VXFORM(vminsw, 1, 14),
10281 GEN_VXFORM(vavgub, 1, 16),
10282 GEN_VXFORM(vavguh, 1, 17),
10283 GEN_VXFORM(vavguw, 1, 18),
10284 GEN_VXFORM(vavgsb, 1, 20),
10285 GEN_VXFORM(vavgsh, 1, 21),
10286 GEN_VXFORM(vavgsw, 1, 22),
10287 GEN_VXFORM(vmrghb, 6, 0),
10288 GEN_VXFORM(vmrghh, 6, 1),
10289 GEN_VXFORM(vmrghw, 6, 2),
10290 GEN_VXFORM(vmrglb, 6, 4),
10291 GEN_VXFORM(vmrglh, 6, 5),
10292 GEN_VXFORM(vmrglw, 6, 6),
10293 GEN_VXFORM(vmuloub, 4, 0),
10294 GEN_VXFORM(vmulouh, 4, 1),
10295 GEN_VXFORM(vmulosb, 4, 4),
10296 GEN_VXFORM(vmulosh, 4, 5),
10297 GEN_VXFORM(vmuleub, 4, 8),
10298 GEN_VXFORM(vmuleuh, 4, 9),
10299 GEN_VXFORM(vmulesb, 4, 12),
10300 GEN_VXFORM(vmulesh, 4, 13),
10301 GEN_VXFORM(vslb, 2, 4),
10302 GEN_VXFORM(vslh, 2, 5),
10303 GEN_VXFORM(vslw, 2, 6),
10304 GEN_VXFORM(vsrb, 2, 8),
10305 GEN_VXFORM(vsrh, 2, 9),
10306 GEN_VXFORM(vsrw, 2, 10),
10307 GEN_VXFORM(vsrab, 2, 12),
10308 GEN_VXFORM(vsrah, 2, 13),
10309 GEN_VXFORM(vsraw, 2, 14),
10310 GEN_VXFORM(vslo, 6, 16),
10311 GEN_VXFORM(vsro, 6, 17),
10312 GEN_VXFORM(vaddcuw, 0, 6),
10313 GEN_VXFORM(vsubcuw, 0, 22),
10314 GEN_VXFORM(vaddubs, 0, 8),
10315 GEN_VXFORM(vadduhs, 0, 9),
10316 GEN_VXFORM(vadduws, 0, 10),
10317 GEN_VXFORM(vaddsbs, 0, 12),
10318 GEN_VXFORM(vaddshs, 0, 13),
10319 GEN_VXFORM(vaddsws, 0, 14),
10320 GEN_VXFORM(vsububs, 0, 24),
10321 GEN_VXFORM(vsubuhs, 0, 25),
10322 GEN_VXFORM(vsubuws, 0, 26),
10323 GEN_VXFORM(vsubsbs, 0, 28),
10324 GEN_VXFORM(vsubshs, 0, 29),
10325 GEN_VXFORM(vsubsws, 0, 30),
10326 GEN_VXFORM(vrlb, 2, 0),
10327 GEN_VXFORM(vrlh, 2, 1),
10328 GEN_VXFORM(vrlw, 2, 2),
10329 GEN_VXFORM(vsl, 2, 7),
10330 GEN_VXFORM(vsr, 2, 11),
10331 GEN_VXFORM(vpkuhum, 7, 0),
10332 GEN_VXFORM(vpkuwum, 7, 1),
10333 GEN_VXFORM(vpkuhus, 7, 2),
10334 GEN_VXFORM(vpkuwus, 7, 3),
10335 GEN_VXFORM(vpkshus, 7, 4),
10336 GEN_VXFORM(vpkswus, 7, 5),
10337 GEN_VXFORM(vpkshss, 7, 6),
10338 GEN_VXFORM(vpkswss, 7, 7),
10339 GEN_VXFORM(vpkpx, 7, 12),
10340 GEN_VXFORM(vsum4ubs, 4, 24),
10341 GEN_VXFORM(vsum4sbs, 4, 28),
10342 GEN_VXFORM(vsum4shs, 4, 25),
10343 GEN_VXFORM(vsum2sws, 4, 26),
10344 GEN_VXFORM(vsumsws, 4, 30),
10345 GEN_VXFORM(vaddfp, 5, 0),
10346 GEN_VXFORM(vsubfp, 5, 1),
10347 GEN_VXFORM(vmaxfp, 5, 16),
10348 GEN_VXFORM(vminfp, 5, 17),
10349
10350 #undef GEN_VXRFORM1
10351 #undef GEN_VXRFORM
10352 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10353 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10354 #define GEN_VXRFORM(name, opc2, opc3) \
10355 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10356 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10357 GEN_VXRFORM(vcmpequb, 3, 0)
10358 GEN_VXRFORM(vcmpequh, 3, 1)
10359 GEN_VXRFORM(vcmpequw, 3, 2)
10360 GEN_VXRFORM(vcmpgtsb, 3, 12)
10361 GEN_VXRFORM(vcmpgtsh, 3, 13)
10362 GEN_VXRFORM(vcmpgtsw, 3, 14)
10363 GEN_VXRFORM(vcmpgtub, 3, 8)
10364 GEN_VXRFORM(vcmpgtuh, 3, 9)
10365 GEN_VXRFORM(vcmpgtuw, 3, 10)
10366 GEN_VXRFORM(vcmpeqfp, 3, 3)
10367 GEN_VXRFORM(vcmpgefp, 3, 7)
10368 GEN_VXRFORM(vcmpgtfp, 3, 11)
10369 GEN_VXRFORM(vcmpbfp, 3, 15)
10370
10371 #undef GEN_VXFORM_SIMM
10372 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10373 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10374 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10375 GEN_VXFORM_SIMM(vspltish, 6, 13),
10376 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10377
10378 #undef GEN_VXFORM_NOA
10379 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10380 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10381 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10382 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10383 GEN_VXFORM_NOA(vupklsb, 7, 10),
10384 GEN_VXFORM_NOA(vupklsh, 7, 11),
10385 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10386 GEN_VXFORM_NOA(vupklpx, 7, 15),
10387 GEN_VXFORM_NOA(vrefp, 5, 4),
10388 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10389 GEN_VXFORM_NOA(vexptefp, 5, 6),
10390 GEN_VXFORM_NOA(vlogefp, 5, 7),
10391 GEN_VXFORM_NOA(vrfim, 5, 8),
10392 GEN_VXFORM_NOA(vrfin, 5, 9),
10393 GEN_VXFORM_NOA(vrfip, 5, 10),
10394 GEN_VXFORM_NOA(vrfiz, 5, 11),
10395
10396 #undef GEN_VXFORM_UIMM
10397 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10398 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10399 GEN_VXFORM_UIMM(vspltb, 6, 8),
10400 GEN_VXFORM_UIMM(vsplth, 6, 9),
10401 GEN_VXFORM_UIMM(vspltw, 6, 10),
10402 GEN_VXFORM_UIMM(vcfux, 5, 12),
10403 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10404 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10405 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10406
10407 #undef GEN_VAFORM_PAIRED
10408 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10409 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10410 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10411 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10412 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10413 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10414 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10415 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10416
10417 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10418 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10419 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10420 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10421 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10422 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10423 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10424
10425 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10426 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10427 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10428 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10429 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10430
10431 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10432 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10433 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10434 #if defined(TARGET_PPC64)
10435 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10436 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10437 #endif
10438
10439 #undef GEN_XX2FORM
10440 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10441 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10442 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10443
10444 #undef GEN_XX3FORM
10445 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10446 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10447 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10448 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10449 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10450
10451 #undef GEN_XX3_RC_FORM
10452 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10453 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10454 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10455 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10456 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10457 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10458 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10459 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10460 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10461
10462 #undef GEN_XX3FORM_DM
10463 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10464 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10465 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10466 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10467 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10468 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10469 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10470 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10471 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10472 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10473 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10474 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10475 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10476 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10477 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10478 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10479 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10480
10481 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10482 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10483 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10484 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10485
10486 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10487 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10488 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10489 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10490 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10491 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10492 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10493 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10494
10495 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10496 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10497 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10498 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10499 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10500 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10501 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10502 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10503 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10504 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10505 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10506 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10507 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10508 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10509 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10510 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10511 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10512 GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10513 GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10514 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10515 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10516 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10517 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10518 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10519 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10520 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10521 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10522 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10523 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10524 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10525 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10526 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10527 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10528 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10529 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10530 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10531
10532 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10533 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10534 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10535 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10536 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10537 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10538 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10539 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10540 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10541 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10542 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10543 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10544 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10545 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10546 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10547 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10548 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10549 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10550
10551 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10552 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10553 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10554 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10555 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10556 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10557 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10558 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10559 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10560 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10561 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10562 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10563 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10564 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10565 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10566 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10567 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10568 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10569 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10570 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10571 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10572 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10573 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10574 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10575 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10576 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10577 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10578 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10579 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10580 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10581 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10582 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10583 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10584 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10585 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10586 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10587
10588 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10589 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10590 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10591 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10592 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10593 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10594 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10595 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10596 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10597 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10598 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10599 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10600 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10601 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10602 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10603 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10604 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10605 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10606 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10607 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10608 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10609 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10610 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10611 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10612 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10613 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10614 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10615 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10616 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10617 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10618 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10619 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10620 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10621 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10622 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10623 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10624
10625 #undef VSX_LOGICAL
10626 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10627 GEN_XX3FORM(name, opc2, opc3, fl2)
10628
10629 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10630 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10631 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10632 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10633 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10634 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10635 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10636 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10637 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10638 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10639 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10640 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10641
10642 #define GEN_XXSEL_ROW(opc3) \
10643 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10644 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10645 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10646 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10647 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10648 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10649 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10650 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10651
10652 GEN_XXSEL_ROW(0x00)
10653 GEN_XXSEL_ROW(0x01)
10654 GEN_XXSEL_ROW(0x02)
10655 GEN_XXSEL_ROW(0x03)
10656 GEN_XXSEL_ROW(0x04)
10657 GEN_XXSEL_ROW(0x05)
10658 GEN_XXSEL_ROW(0x06)
10659 GEN_XXSEL_ROW(0x07)
10660 GEN_XXSEL_ROW(0x08)
10661 GEN_XXSEL_ROW(0x09)
10662 GEN_XXSEL_ROW(0x0A)
10663 GEN_XXSEL_ROW(0x0B)
10664 GEN_XXSEL_ROW(0x0C)
10665 GEN_XXSEL_ROW(0x0D)
10666 GEN_XXSEL_ROW(0x0E)
10667 GEN_XXSEL_ROW(0x0F)
10668 GEN_XXSEL_ROW(0x10)
10669 GEN_XXSEL_ROW(0x11)
10670 GEN_XXSEL_ROW(0x12)
10671 GEN_XXSEL_ROW(0x13)
10672 GEN_XXSEL_ROW(0x14)
10673 GEN_XXSEL_ROW(0x15)
10674 GEN_XXSEL_ROW(0x16)
10675 GEN_XXSEL_ROW(0x17)
10676 GEN_XXSEL_ROW(0x18)
10677 GEN_XXSEL_ROW(0x19)
10678 GEN_XXSEL_ROW(0x1A)
10679 GEN_XXSEL_ROW(0x1B)
10680 GEN_XXSEL_ROW(0x1C)
10681 GEN_XXSEL_ROW(0x1D)
10682 GEN_XXSEL_ROW(0x1E)
10683 GEN_XXSEL_ROW(0x1F)
10684
10685 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10686
10687 #undef GEN_SPE
10688 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
10689 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
10690 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10691 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10692 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10693 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10694 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10695 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10696 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10697 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
10698 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
10699 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10700 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10701 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10702 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10703 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10704 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10705 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
10706 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10707 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10708 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10709 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10710 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10711 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10712 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10713 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10714 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10715 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10716 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10717 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10718 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
10719
10720 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10721 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10722 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10723 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10724 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10725 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10726 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10727 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10728 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10729 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10730 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10731 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10732 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10733 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10734
10735 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10736 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10737 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10738 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10739 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10740 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
10741 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10742 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10743 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10744 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10745 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10746 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10747 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10748 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10749
10750 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
10751 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10752 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
10753 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10754 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
10755 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10756 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
10757 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
10758 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10759 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10760 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10761 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10762 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10763 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10764 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
10765 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10766
10767 #undef GEN_SPEOP_LDST
10768 #define GEN_SPEOP_LDST(name, opc2, sh) \
10769 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
10770 GEN_SPEOP_LDST(evldd, 0x00, 3),
10771 GEN_SPEOP_LDST(evldw, 0x01, 3),
10772 GEN_SPEOP_LDST(evldh, 0x02, 3),
10773 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
10774 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
10775 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
10776 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
10777 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
10778 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
10779 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
10780 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
10781
10782 GEN_SPEOP_LDST(evstdd, 0x10, 3),
10783 GEN_SPEOP_LDST(evstdw, 0x11, 3),
10784 GEN_SPEOP_LDST(evstdh, 0x12, 3),
10785 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
10786 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
10787 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
10788 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
10789 };
10790
10791 #include "helper_regs.h"
10792 #include "translate_init.c"
10793
10794 /*****************************************************************************/
10795 /* Misc PowerPC helpers */
10796 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
10797 int flags)
10798 {
10799 #define RGPL 4
10800 #define RFPL 4
10801
10802 PowerPCCPU *cpu = POWERPC_CPU(cs);
10803 CPUPPCState *env = &cpu->env;
10804 int i;
10805
10806 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
10807 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
10808 env->nip, env->lr, env->ctr, cpu_read_xer(env));
10809 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
10810 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
10811 env->hflags, env->mmu_idx);
10812 #if !defined(NO_TIMER_DUMP)
10813 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
10814 #if !defined(CONFIG_USER_ONLY)
10815 " DECR %08" PRIu32
10816 #endif
10817 "\n",
10818 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
10819 #if !defined(CONFIG_USER_ONLY)
10820 , cpu_ppc_load_decr(env)
10821 #endif
10822 );
10823 #endif
10824 for (i = 0; i < 32; i++) {
10825 if ((i & (RGPL - 1)) == 0)
10826 cpu_fprintf(f, "GPR%02d", i);
10827 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
10828 if ((i & (RGPL - 1)) == (RGPL - 1))
10829 cpu_fprintf(f, "\n");
10830 }
10831 cpu_fprintf(f, "CR ");
10832 for (i = 0; i < 8; i++)
10833 cpu_fprintf(f, "%01x", env->crf[i]);
10834 cpu_fprintf(f, " [");
10835 for (i = 0; i < 8; i++) {
10836 char a = '-';
10837 if (env->crf[i] & 0x08)
10838 a = 'L';
10839 else if (env->crf[i] & 0x04)
10840 a = 'G';
10841 else if (env->crf[i] & 0x02)
10842 a = 'E';
10843 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
10844 }
10845 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
10846 env->reserve_addr);
10847 for (i = 0; i < 32; i++) {
10848 if ((i & (RFPL - 1)) == 0)
10849 cpu_fprintf(f, "FPR%02d", i);
10850 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
10851 if ((i & (RFPL - 1)) == (RFPL - 1))
10852 cpu_fprintf(f, "\n");
10853 }
10854 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
10855 #if !defined(CONFIG_USER_ONLY)
10856 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
10857 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
10858 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
10859 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
10860
10861 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
10862 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
10863 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
10864 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
10865
10866 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
10867 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
10868 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
10869 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
10870
10871 if (env->excp_model == POWERPC_EXCP_BOOKE) {
10872 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
10873 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
10874 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
10875 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
10876
10877 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
10878 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
10879 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
10880 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
10881
10882 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
10883 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
10884 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
10885 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
10886
10887 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
10888 " EPR " TARGET_FMT_lx "\n",
10889 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
10890 env->spr[SPR_BOOKE_EPR]);
10891
10892 /* FSL-specific */
10893 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
10894 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
10895 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
10896 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
10897
10898 /*
10899 * IVORs are left out as they are large and do not change often --
10900 * they can be read with "p $ivor0", "p $ivor1", etc.
10901 */
10902 }
10903
10904 #if defined(TARGET_PPC64)
10905 if (env->flags & POWERPC_FLAG_CFAR) {
10906 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
10907 }
10908 #endif
10909
10910 switch (env->mmu_model) {
10911 case POWERPC_MMU_32B:
10912 case POWERPC_MMU_601:
10913 case POWERPC_MMU_SOFT_6xx:
10914 case POWERPC_MMU_SOFT_74xx:
10915 #if defined(TARGET_PPC64)
10916 case POWERPC_MMU_64B:
10917 case POWERPC_MMU_2_06:
10918 case POWERPC_MMU_2_06a:
10919 case POWERPC_MMU_2_06d:
10920 #endif
10921 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
10922 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
10923 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
10924 break;
10925 case POWERPC_MMU_BOOKE206:
10926 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
10927 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
10928 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
10929 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
10930
10931 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
10932 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
10933 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
10934 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
10935
10936 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
10937 " TLB1CFG " TARGET_FMT_lx "\n",
10938 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
10939 env->spr[SPR_BOOKE_TLB1CFG]);
10940 break;
10941 default:
10942 break;
10943 }
10944 #endif
10945
10946 #undef RGPL
10947 #undef RFPL
10948 }
10949
10950 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
10951 fprintf_function cpu_fprintf, int flags)
10952 {
10953 #if defined(DO_PPC_STATISTICS)
10954 PowerPCCPU *cpu = POWERPC_CPU(cs);
10955 opc_handler_t **t1, **t2, **t3, *handler;
10956 int op1, op2, op3;
10957
10958 t1 = cpu->env.opcodes;
10959 for (op1 = 0; op1 < 64; op1++) {
10960 handler = t1[op1];
10961 if (is_indirect_opcode(handler)) {
10962 t2 = ind_table(handler);
10963 for (op2 = 0; op2 < 32; op2++) {
10964 handler = t2[op2];
10965 if (is_indirect_opcode(handler)) {
10966 t3 = ind_table(handler);
10967 for (op3 = 0; op3 < 32; op3++) {
10968 handler = t3[op3];
10969 if (handler->count == 0)
10970 continue;
10971 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
10972 "%016" PRIx64 " %" PRId64 "\n",
10973 op1, op2, op3, op1, (op3 << 5) | op2,
10974 handler->oname,
10975 handler->count, handler->count);
10976 }
10977 } else {
10978 if (handler->count == 0)
10979 continue;
10980 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
10981 "%016" PRIx64 " %" PRId64 "\n",
10982 op1, op2, op1, op2, handler->oname,
10983 handler->count, handler->count);
10984 }
10985 }
10986 } else {
10987 if (handler->count == 0)
10988 continue;
10989 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
10990 " %" PRId64 "\n",
10991 op1, op1, handler->oname,
10992 handler->count, handler->count);
10993 }
10994 }
10995 #endif
10996 }
10997
10998 /*****************************************************************************/
10999 static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
11000 TranslationBlock *tb,
11001 bool search_pc)
11002 {
11003 CPUState *cs = CPU(cpu);
11004 CPUPPCState *env = &cpu->env;
11005 DisasContext ctx, *ctxp = &ctx;
11006 opc_handler_t **table, *handler;
11007 target_ulong pc_start;
11008 uint16_t *gen_opc_end;
11009 CPUBreakpoint *bp;
11010 int j, lj = -1;
11011 int num_insns;
11012 int max_insns;
11013
11014 pc_start = tb->pc;
11015 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
11016 ctx.nip = pc_start;
11017 ctx.tb = tb;
11018 ctx.exception = POWERPC_EXCP_NONE;
11019 ctx.spr_cb = env->spr_cb;
11020 ctx.mem_idx = env->mmu_idx;
11021 ctx.insns_flags = env->insns_flags;
11022 ctx.insns_flags2 = env->insns_flags2;
11023 ctx.access_type = -1;
11024 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11025 #if defined(TARGET_PPC64)
11026 ctx.sf_mode = msr_is_64bit(env, env->msr);
11027 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11028 #endif
11029 ctx.fpu_enabled = msr_fp;
11030 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11031 ctx.spe_enabled = msr_spe;
11032 else
11033 ctx.spe_enabled = 0;
11034 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11035 ctx.altivec_enabled = msr_vr;
11036 else
11037 ctx.altivec_enabled = 0;
11038 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11039 ctx.vsx_enabled = msr_vsx;
11040 } else {
11041 ctx.vsx_enabled = 0;
11042 }
11043 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11044 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11045 else
11046 ctx.singlestep_enabled = 0;
11047 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11048 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11049 if (unlikely(cs->singlestep_enabled)) {
11050 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11051 }
11052 #if defined (DO_SINGLE_STEP) && 0
11053 /* Single step trace mode */
11054 msr_se = 1;
11055 #endif
11056 num_insns = 0;
11057 max_insns = tb->cflags & CF_COUNT_MASK;
11058 if (max_insns == 0)
11059 max_insns = CF_COUNT_MASK;
11060
11061 gen_tb_start();
11062 /* Set env in case of segfault during code fetch */
11063 while (ctx.exception == POWERPC_EXCP_NONE
11064 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
11065 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
11066 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
11067 if (bp->pc == ctx.nip) {
11068 gen_debug_exception(ctxp);
11069 break;
11070 }
11071 }
11072 }
11073 if (unlikely(search_pc)) {
11074 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11075 if (lj < j) {
11076 lj++;
11077 while (lj < j)
11078 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11079 }
11080 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
11081 tcg_ctx.gen_opc_instr_start[lj] = 1;
11082 tcg_ctx.gen_opc_icount[lj] = num_insns;
11083 }
11084 LOG_DISAS("----------------\n");
11085 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11086 ctx.nip, ctx.mem_idx, (int)msr_ir);
11087 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
11088 gen_io_start();
11089 if (unlikely(ctx.le_mode)) {
11090 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11091 } else {
11092 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11093 }
11094 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11095 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11096 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11097 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
11098 tcg_gen_debug_insn_start(ctx.nip);
11099 }
11100 ctx.nip += 4;
11101 table = env->opcodes;
11102 num_insns++;
11103 handler = table[opc1(ctx.opcode)];
11104 if (is_indirect_opcode(handler)) {
11105 table = ind_table(handler);
11106 handler = table[opc2(ctx.opcode)];
11107 if (is_indirect_opcode(handler)) {
11108 table = ind_table(handler);
11109 handler = table[opc3(ctx.opcode)];
11110 }
11111 }
11112 /* Is opcode *REALLY* valid ? */
11113 if (unlikely(handler->handler == &gen_invalid)) {
11114 if (qemu_log_enabled()) {
11115 qemu_log("invalid/unsupported opcode: "
11116 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11117 opc1(ctx.opcode), opc2(ctx.opcode),
11118 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11119 }
11120 } else {
11121 uint32_t inval;
11122
11123 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11124 inval = handler->inval2;
11125 } else {
11126 inval = handler->inval1;
11127 }
11128
11129 if (unlikely((ctx.opcode & inval) != 0)) {
11130 if (qemu_log_enabled()) {
11131 qemu_log("invalid bits: %08x for opcode: "
11132 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11133 ctx.opcode & inval, opc1(ctx.opcode),
11134 opc2(ctx.opcode), opc3(ctx.opcode),
11135 ctx.opcode, ctx.nip - 4);
11136 }
11137 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11138 break;
11139 }
11140 }
11141 (*(handler->handler))(&ctx);
11142 #if defined(DO_PPC_STATISTICS)
11143 handler->count++;
11144 #endif
11145 /* Check trace mode exceptions */
11146 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11147 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11148 ctx.exception != POWERPC_SYSCALL &&
11149 ctx.exception != POWERPC_EXCP_TRAP &&
11150 ctx.exception != POWERPC_EXCP_BRANCH)) {
11151 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11152 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11153 (cs->singlestep_enabled) ||
11154 singlestep ||
11155 num_insns >= max_insns)) {
11156 /* if we reach a page boundary or are single stepping, stop
11157 * generation
11158 */
11159 break;
11160 }
11161 }
11162 if (tb->cflags & CF_LAST_IO)
11163 gen_io_end();
11164 if (ctx.exception == POWERPC_EXCP_NONE) {
11165 gen_goto_tb(&ctx, 0, ctx.nip);
11166 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11167 if (unlikely(cs->singlestep_enabled)) {
11168 gen_debug_exception(ctxp);
11169 }
11170 /* Generate the return instruction */
11171 tcg_gen_exit_tb(0);
11172 }
11173 gen_tb_end(tb, num_insns);
11174 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
11175 if (unlikely(search_pc)) {
11176 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11177 lj++;
11178 while (lj <= j)
11179 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11180 } else {
11181 tb->size = ctx.nip - pc_start;
11182 tb->icount = num_insns;
11183 }
11184 #if defined(DEBUG_DISAS)
11185 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11186 int flags;
11187 flags = env->bfd_mach;
11188 flags |= ctx.le_mode << 16;
11189 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11190 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
11191 qemu_log("\n");
11192 }
11193 #endif
11194 }
11195
11196 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
11197 {
11198 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false);
11199 }
11200
11201 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
11202 {
11203 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true);
11204 }
11205
11206 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
11207 {
11208 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
11209 }
QEMU mirror