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[qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i32 cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_msr;
64 static TCGv cpu_ctr;
65 static TCGv cpu_lr;
66 #if defined(TARGET_PPC64)
67 static TCGv cpu_cfar;
68 #endif
69 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
70 static TCGv cpu_reserve;
71 static TCGv cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "exec/gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111 #endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154 #if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157 #endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161 cpu_so = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUPPCState, so), "SO");
163 cpu_ov = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, ov), "OV");
165 cpu_ca = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, ca), "CA");
167
168 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, reserve_addr),
170 "reserve_addr");
171
172 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, fpscr), "fpscr");
174
175 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
176 offsetof(CPUPPCState, access_type), "access_type");
177
178 /* register helpers */
179 #define GEN_HELPER 2
180 #include "helper.h"
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 int mem_idx;
193 int access_type;
194 /* Translation flags */
195 int le_mode;
196 #if defined(TARGET_PPC64)
197 int sf_mode;
198 int has_cfar;
199 #endif
200 int fpu_enabled;
201 int altivec_enabled;
202 int spe_enabled;
203 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
204 int singlestep_enabled;
205 } DisasContext;
206
207 /* True when active word size < size of target_long. */
208 #ifdef TARGET_PPC64
209 # define NARROW_MODE(C) (!(C)->sf_mode)
210 #else
211 # define NARROW_MODE(C) 0
212 #endif
213
214 struct opc_handler_t {
215 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
216 uint32_t inval1;
217 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
218 uint32_t inval2;
219 /* instruction type */
220 uint64_t type;
221 /* extended instruction type */
222 uint64_t type2;
223 /* handler */
224 void (*handler)(DisasContext *ctx);
225 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
226 const char *oname;
227 #endif
228 #if defined(DO_PPC_STATISTICS)
229 uint64_t count;
230 #endif
231 };
232
233 static inline void gen_reset_fpstatus(void)
234 {
235 gen_helper_reset_fpstatus(cpu_env);
236 }
237
238 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
239 {
240 TCGv_i32 t0 = tcg_temp_new_i32();
241
242 if (set_fprf != 0) {
243 /* This case might be optimized later */
244 tcg_gen_movi_i32(t0, 1);
245 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
246 if (unlikely(set_rc)) {
247 tcg_gen_mov_i32(cpu_crf[1], t0);
248 }
249 gen_helper_float_check_status(cpu_env);
250 } else if (unlikely(set_rc)) {
251 /* We always need to compute fpcc */
252 tcg_gen_movi_i32(t0, 0);
253 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
254 tcg_gen_mov_i32(cpu_crf[1], t0);
255 }
256
257 tcg_temp_free_i32(t0);
258 }
259
260 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
261 {
262 if (ctx->access_type != access_type) {
263 tcg_gen_movi_i32(cpu_access_type, access_type);
264 ctx->access_type = access_type;
265 }
266 }
267
268 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
269 {
270 if (NARROW_MODE(ctx)) {
271 nip = (uint32_t)nip;
272 }
273 tcg_gen_movi_tl(cpu_nip, nip);
274 }
275
276 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
277 {
278 TCGv_i32 t0, t1;
279 if (ctx->exception == POWERPC_EXCP_NONE) {
280 gen_update_nip(ctx, ctx->nip);
281 }
282 t0 = tcg_const_i32(excp);
283 t1 = tcg_const_i32(error);
284 gen_helper_raise_exception_err(cpu_env, t0, t1);
285 tcg_temp_free_i32(t0);
286 tcg_temp_free_i32(t1);
287 ctx->exception = (excp);
288 }
289
290 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
291 {
292 TCGv_i32 t0;
293 if (ctx->exception == POWERPC_EXCP_NONE) {
294 gen_update_nip(ctx, ctx->nip);
295 }
296 t0 = tcg_const_i32(excp);
297 gen_helper_raise_exception(cpu_env, t0);
298 tcg_temp_free_i32(t0);
299 ctx->exception = (excp);
300 }
301
302 static inline void gen_debug_exception(DisasContext *ctx)
303 {
304 TCGv_i32 t0;
305
306 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
307 (ctx->exception != POWERPC_EXCP_SYNC)) {
308 gen_update_nip(ctx, ctx->nip);
309 }
310 t0 = tcg_const_i32(EXCP_DEBUG);
311 gen_helper_raise_exception(cpu_env, t0);
312 tcg_temp_free_i32(t0);
313 }
314
315 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
316 {
317 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
318 }
319
320 /* Stop translation */
321 static inline void gen_stop_exception(DisasContext *ctx)
322 {
323 gen_update_nip(ctx, ctx->nip);
324 ctx->exception = POWERPC_EXCP_STOP;
325 }
326
327 /* No need to update nip here, as execution flow will change */
328 static inline void gen_sync_exception(DisasContext *ctx)
329 {
330 ctx->exception = POWERPC_EXCP_SYNC;
331 }
332
333 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
334 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
335
336 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
337 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
338
339 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
340 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
341
342 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
343 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
344
345 typedef struct opcode_t {
346 unsigned char opc1, opc2, opc3;
347 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
348 unsigned char pad[5];
349 #else
350 unsigned char pad[1];
351 #endif
352 opc_handler_t handler;
353 const char *oname;
354 } opcode_t;
355
356 /*****************************************************************************/
357 /*** Instruction decoding ***/
358 #define EXTRACT_HELPER(name, shift, nb) \
359 static inline uint32_t name(uint32_t opcode) \
360 { \
361 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
362 }
363
364 #define EXTRACT_SHELPER(name, shift, nb) \
365 static inline int32_t name(uint32_t opcode) \
366 { \
367 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
368 }
369
370 /* Opcode part 1 */
371 EXTRACT_HELPER(opc1, 26, 6);
372 /* Opcode part 2 */
373 EXTRACT_HELPER(opc2, 1, 5);
374 /* Opcode part 3 */
375 EXTRACT_HELPER(opc3, 6, 5);
376 /* Update Cr0 flags */
377 EXTRACT_HELPER(Rc, 0, 1);
378 /* Destination */
379 EXTRACT_HELPER(rD, 21, 5);
380 /* Source */
381 EXTRACT_HELPER(rS, 21, 5);
382 /* First operand */
383 EXTRACT_HELPER(rA, 16, 5);
384 /* Second operand */
385 EXTRACT_HELPER(rB, 11, 5);
386 /* Third operand */
387 EXTRACT_HELPER(rC, 6, 5);
388 /*** Get CRn ***/
389 EXTRACT_HELPER(crfD, 23, 3);
390 EXTRACT_HELPER(crfS, 18, 3);
391 EXTRACT_HELPER(crbD, 21, 5);
392 EXTRACT_HELPER(crbA, 16, 5);
393 EXTRACT_HELPER(crbB, 11, 5);
394 /* SPR / TBL */
395 EXTRACT_HELPER(_SPR, 11, 10);
396 static inline uint32_t SPR(uint32_t opcode)
397 {
398 uint32_t sprn = _SPR(opcode);
399
400 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
401 }
402 /*** Get constants ***/
403 EXTRACT_HELPER(IMM, 12, 8);
404 /* 16 bits signed immediate value */
405 EXTRACT_SHELPER(SIMM, 0, 16);
406 /* 16 bits unsigned immediate value */
407 EXTRACT_HELPER(UIMM, 0, 16);
408 /* 5 bits signed immediate value */
409 EXTRACT_HELPER(SIMM5, 16, 5);
410 /* 5 bits signed immediate value */
411 EXTRACT_HELPER(UIMM5, 16, 5);
412 /* Bit count */
413 EXTRACT_HELPER(NB, 11, 5);
414 /* Shift count */
415 EXTRACT_HELPER(SH, 11, 5);
416 /* Vector shift count */
417 EXTRACT_HELPER(VSH, 6, 4);
418 /* Mask start */
419 EXTRACT_HELPER(MB, 6, 5);
420 /* Mask end */
421 EXTRACT_HELPER(ME, 1, 5);
422 /* Trap operand */
423 EXTRACT_HELPER(TO, 21, 5);
424
425 EXTRACT_HELPER(CRM, 12, 8);
426 EXTRACT_HELPER(FM, 17, 8);
427 EXTRACT_HELPER(SR, 16, 4);
428 EXTRACT_HELPER(FPIMM, 12, 4);
429
430 /*** Jump target decoding ***/
431 /* Displacement */
432 EXTRACT_SHELPER(d, 0, 16);
433 /* Immediate address */
434 static inline target_ulong LI(uint32_t opcode)
435 {
436 return (opcode >> 0) & 0x03FFFFFC;
437 }
438
439 static inline uint32_t BD(uint32_t opcode)
440 {
441 return (opcode >> 0) & 0xFFFC;
442 }
443
444 EXTRACT_HELPER(BO, 21, 5);
445 EXTRACT_HELPER(BI, 16, 5);
446 /* Absolute/relative address */
447 EXTRACT_HELPER(AA, 1, 1);
448 /* Link */
449 EXTRACT_HELPER(LK, 0, 1);
450
451 /* Create a mask between <start> and <end> bits */
452 static inline target_ulong MASK(uint32_t start, uint32_t end)
453 {
454 target_ulong ret;
455
456 #if defined(TARGET_PPC64)
457 if (likely(start == 0)) {
458 ret = UINT64_MAX << (63 - end);
459 } else if (likely(end == 63)) {
460 ret = UINT64_MAX >> start;
461 }
462 #else
463 if (likely(start == 0)) {
464 ret = UINT32_MAX << (31 - end);
465 } else if (likely(end == 31)) {
466 ret = UINT32_MAX >> start;
467 }
468 #endif
469 else {
470 ret = (((target_ulong)(-1ULL)) >> (start)) ^
471 (((target_ulong)(-1ULL) >> (end)) >> 1);
472 if (unlikely(start > end))
473 return ~ret;
474 }
475
476 return ret;
477 }
478
479 /*****************************************************************************/
480 /* PowerPC instructions table */
481
482 #if defined(DO_PPC_STATISTICS)
483 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
484 { \
485 .opc1 = op1, \
486 .opc2 = op2, \
487 .opc3 = op3, \
488 .pad = { 0, }, \
489 .handler = { \
490 .inval1 = invl, \
491 .type = _typ, \
492 .type2 = _typ2, \
493 .handler = &gen_##name, \
494 .oname = stringify(name), \
495 }, \
496 .oname = stringify(name), \
497 }
498 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
499 { \
500 .opc1 = op1, \
501 .opc2 = op2, \
502 .opc3 = op3, \
503 .pad = { 0, }, \
504 .handler = { \
505 .inval1 = invl1, \
506 .inval2 = invl2, \
507 .type = _typ, \
508 .type2 = _typ2, \
509 .handler = &gen_##name, \
510 .oname = stringify(name), \
511 }, \
512 .oname = stringify(name), \
513 }
514 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
515 { \
516 .opc1 = op1, \
517 .opc2 = op2, \
518 .opc3 = op3, \
519 .pad = { 0, }, \
520 .handler = { \
521 .inval1 = invl, \
522 .type = _typ, \
523 .type2 = _typ2, \
524 .handler = &gen_##name, \
525 .oname = onam, \
526 }, \
527 .oname = onam, \
528 }
529 #else
530 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
531 { \
532 .opc1 = op1, \
533 .opc2 = op2, \
534 .opc3 = op3, \
535 .pad = { 0, }, \
536 .handler = { \
537 .inval1 = invl, \
538 .type = _typ, \
539 .type2 = _typ2, \
540 .handler = &gen_##name, \
541 }, \
542 .oname = stringify(name), \
543 }
544 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
545 { \
546 .opc1 = op1, \
547 .opc2 = op2, \
548 .opc3 = op3, \
549 .pad = { 0, }, \
550 .handler = { \
551 .inval1 = invl1, \
552 .inval2 = invl2, \
553 .type = _typ, \
554 .type2 = _typ2, \
555 .handler = &gen_##name, \
556 }, \
557 .oname = stringify(name), \
558 }
559 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
560 { \
561 .opc1 = op1, \
562 .opc2 = op2, \
563 .opc3 = op3, \
564 .pad = { 0, }, \
565 .handler = { \
566 .inval1 = invl, \
567 .type = _typ, \
568 .type2 = _typ2, \
569 .handler = &gen_##name, \
570 }, \
571 .oname = onam, \
572 }
573 #endif
574
575 /* SPR load/store helpers */
576 static inline void gen_load_spr(TCGv t, int reg)
577 {
578 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
579 }
580
581 static inline void gen_store_spr(int reg, TCGv t)
582 {
583 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
584 }
585
586 /* Invalid instruction */
587 static void gen_invalid(DisasContext *ctx)
588 {
589 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
590 }
591
592 static opc_handler_t invalid_handler = {
593 .inval1 = 0xFFFFFFFF,
594 .inval2 = 0xFFFFFFFF,
595 .type = PPC_NONE,
596 .type2 = PPC_NONE,
597 .handler = gen_invalid,
598 };
599
600 /*** Integer comparison ***/
601
602 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
603 {
604 TCGv t0 = tcg_temp_new();
605 TCGv_i32 t1 = tcg_temp_new_i32();
606
607 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
608
609 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
610 tcg_gen_trunc_tl_i32(t1, t0);
611 tcg_gen_shli_i32(t1, t1, CRF_LT);
612 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
613
614 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
615 tcg_gen_trunc_tl_i32(t1, t0);
616 tcg_gen_shli_i32(t1, t1, CRF_GT);
617 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
618
619 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
620 tcg_gen_trunc_tl_i32(t1, t0);
621 tcg_gen_shli_i32(t1, t1, CRF_EQ);
622 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
623
624 tcg_temp_free(t0);
625 tcg_temp_free_i32(t1);
626 }
627
628 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
629 {
630 TCGv t0 = tcg_const_tl(arg1);
631 gen_op_cmp(arg0, t0, s, crf);
632 tcg_temp_free(t0);
633 }
634
635 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
636 {
637 TCGv t0, t1;
638 t0 = tcg_temp_new();
639 t1 = tcg_temp_new();
640 if (s) {
641 tcg_gen_ext32s_tl(t0, arg0);
642 tcg_gen_ext32s_tl(t1, arg1);
643 } else {
644 tcg_gen_ext32u_tl(t0, arg0);
645 tcg_gen_ext32u_tl(t1, arg1);
646 }
647 gen_op_cmp(t0, t1, s, crf);
648 tcg_temp_free(t1);
649 tcg_temp_free(t0);
650 }
651
652 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
653 {
654 TCGv t0 = tcg_const_tl(arg1);
655 gen_op_cmp32(arg0, t0, s, crf);
656 tcg_temp_free(t0);
657 }
658
659 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
660 {
661 if (NARROW_MODE(ctx)) {
662 gen_op_cmpi32(reg, 0, 1, 0);
663 } else {
664 gen_op_cmpi(reg, 0, 1, 0);
665 }
666 }
667
668 /* cmp */
669 static void gen_cmp(DisasContext *ctx)
670 {
671 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
672 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
673 1, crfD(ctx->opcode));
674 } else {
675 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
676 1, crfD(ctx->opcode));
677 }
678 }
679
680 /* cmpi */
681 static void gen_cmpi(DisasContext *ctx)
682 {
683 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
684 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
685 1, crfD(ctx->opcode));
686 } else {
687 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
688 1, crfD(ctx->opcode));
689 }
690 }
691
692 /* cmpl */
693 static void gen_cmpl(DisasContext *ctx)
694 {
695 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
696 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
697 0, crfD(ctx->opcode));
698 } else {
699 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
700 0, crfD(ctx->opcode));
701 }
702 }
703
704 /* cmpli */
705 static void gen_cmpli(DisasContext *ctx)
706 {
707 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
708 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
709 0, crfD(ctx->opcode));
710 } else {
711 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
712 0, crfD(ctx->opcode));
713 }
714 }
715
716 /* isel (PowerPC 2.03 specification) */
717 static void gen_isel(DisasContext *ctx)
718 {
719 int l1, l2;
720 uint32_t bi = rC(ctx->opcode);
721 uint32_t mask;
722 TCGv_i32 t0;
723
724 l1 = gen_new_label();
725 l2 = gen_new_label();
726
727 mask = 1 << (3 - (bi & 0x03));
728 t0 = tcg_temp_new_i32();
729 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
730 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
731 if (rA(ctx->opcode) == 0)
732 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
733 else
734 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
735 tcg_gen_br(l2);
736 gen_set_label(l1);
737 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
738 gen_set_label(l2);
739 tcg_temp_free_i32(t0);
740 }
741
742 /*** Integer arithmetic ***/
743
744 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
745 TCGv arg1, TCGv arg2, int sub)
746 {
747 TCGv t0 = tcg_temp_new();
748
749 tcg_gen_xor_tl(cpu_ov, arg0, arg1);
750 tcg_gen_xor_tl(t0, arg1, arg2);
751 if (sub) {
752 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
753 } else {
754 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
755 }
756 tcg_temp_free(t0);
757 if (NARROW_MODE(ctx)) {
758 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
759 }
760 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
761 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
762 }
763
764 /* Common add function */
765 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
766 TCGv arg2, bool add_ca, bool compute_ca,
767 bool compute_ov, bool compute_rc0)
768 {
769 TCGv t0 = ret;
770
771 if (((compute_ca && add_ca) || compute_ov)
772 && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) {
773 t0 = tcg_temp_new();
774 }
775
776 if (compute_ca) {
777 if (NARROW_MODE(ctx)) {
778 TCGv t1 = tcg_temp_new();
779 tcg_gen_ext32u_tl(t1, arg2);
780 tcg_gen_ext32u_tl(t0, arg1);
781 tcg_gen_add_tl(t0, t0, t1);
782 tcg_temp_free(t1);
783 if (add_ca) {
784 tcg_gen_add_tl(t0, t0, cpu_ca);
785 }
786 tcg_gen_shri_tl(cpu_ca, t0, 32);
787 } else {
788 TCGv zero = tcg_const_tl(0);
789 if (add_ca) {
790 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
791 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
792 } else {
793 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
794 }
795 tcg_temp_free(zero);
796 }
797 } else {
798 tcg_gen_add_tl(t0, arg1, arg2);
799 if (add_ca) {
800 tcg_gen_add_tl(t0, t0, cpu_ca);
801 }
802 }
803
804 if (compute_ov) {
805 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
806 }
807 if (unlikely(compute_rc0)) {
808 gen_set_Rc0(ctx, t0);
809 }
810
811 if (!TCGV_EQUAL(t0, ret)) {
812 tcg_gen_mov_tl(ret, t0);
813 tcg_temp_free(t0);
814 }
815 }
816 /* Add functions with two operands */
817 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
818 static void glue(gen_, name)(DisasContext *ctx) \
819 { \
820 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
821 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
822 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
823 }
824 /* Add functions with one operand and one immediate */
825 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
826 add_ca, compute_ca, compute_ov) \
827 static void glue(gen_, name)(DisasContext *ctx) \
828 { \
829 TCGv t0 = tcg_const_tl(const_val); \
830 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
831 cpu_gpr[rA(ctx->opcode)], t0, \
832 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
833 tcg_temp_free(t0); \
834 }
835
836 /* add add. addo addo. */
837 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
838 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
839 /* addc addc. addco addco. */
840 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
841 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
842 /* adde adde. addeo addeo. */
843 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
844 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
845 /* addme addme. addmeo addmeo. */
846 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
847 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
848 /* addze addze. addzeo addzeo.*/
849 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
850 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
851 /* addi */
852 static void gen_addi(DisasContext *ctx)
853 {
854 target_long simm = SIMM(ctx->opcode);
855
856 if (rA(ctx->opcode) == 0) {
857 /* li case */
858 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
859 } else {
860 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
861 cpu_gpr[rA(ctx->opcode)], simm);
862 }
863 }
864 /* addic addic.*/
865 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
866 {
867 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
868 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
869 c, 0, 1, 0, compute_rc0);
870 tcg_temp_free(c);
871 }
872
873 static void gen_addic(DisasContext *ctx)
874 {
875 gen_op_addic(ctx, 0);
876 }
877
878 static void gen_addic_(DisasContext *ctx)
879 {
880 gen_op_addic(ctx, 1);
881 }
882
883 /* addis */
884 static void gen_addis(DisasContext *ctx)
885 {
886 target_long simm = SIMM(ctx->opcode);
887
888 if (rA(ctx->opcode) == 0) {
889 /* lis case */
890 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
891 } else {
892 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
893 cpu_gpr[rA(ctx->opcode)], simm << 16);
894 }
895 }
896
897 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
898 TCGv arg2, int sign, int compute_ov)
899 {
900 int l1 = gen_new_label();
901 int l2 = gen_new_label();
902 TCGv_i32 t0 = tcg_temp_local_new_i32();
903 TCGv_i32 t1 = tcg_temp_local_new_i32();
904
905 tcg_gen_trunc_tl_i32(t0, arg1);
906 tcg_gen_trunc_tl_i32(t1, arg2);
907 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
908 if (sign) {
909 int l3 = gen_new_label();
910 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
911 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
912 gen_set_label(l3);
913 tcg_gen_div_i32(t0, t0, t1);
914 } else {
915 tcg_gen_divu_i32(t0, t0, t1);
916 }
917 if (compute_ov) {
918 tcg_gen_movi_tl(cpu_ov, 0);
919 }
920 tcg_gen_br(l2);
921 gen_set_label(l1);
922 if (sign) {
923 tcg_gen_sari_i32(t0, t0, 31);
924 } else {
925 tcg_gen_movi_i32(t0, 0);
926 }
927 if (compute_ov) {
928 tcg_gen_movi_tl(cpu_ov, 1);
929 tcg_gen_movi_tl(cpu_so, 1);
930 }
931 gen_set_label(l2);
932 tcg_gen_extu_i32_tl(ret, t0);
933 tcg_temp_free_i32(t0);
934 tcg_temp_free_i32(t1);
935 if (unlikely(Rc(ctx->opcode) != 0))
936 gen_set_Rc0(ctx, ret);
937 }
938 /* Div functions */
939 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
940 static void glue(gen_, name)(DisasContext *ctx) \
941 { \
942 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
943 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
944 sign, compute_ov); \
945 }
946 /* divwu divwu. divwuo divwuo. */
947 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
948 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
949 /* divw divw. divwo divwo. */
950 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
951 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
952 #if defined(TARGET_PPC64)
953 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
954 TCGv arg2, int sign, int compute_ov)
955 {
956 int l1 = gen_new_label();
957 int l2 = gen_new_label();
958
959 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
960 if (sign) {
961 int l3 = gen_new_label();
962 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
963 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
964 gen_set_label(l3);
965 tcg_gen_div_i64(ret, arg1, arg2);
966 } else {
967 tcg_gen_divu_i64(ret, arg1, arg2);
968 }
969 if (compute_ov) {
970 tcg_gen_movi_tl(cpu_ov, 0);
971 }
972 tcg_gen_br(l2);
973 gen_set_label(l1);
974 if (sign) {
975 tcg_gen_sari_i64(ret, arg1, 63);
976 } else {
977 tcg_gen_movi_i64(ret, 0);
978 }
979 if (compute_ov) {
980 tcg_gen_movi_tl(cpu_ov, 1);
981 tcg_gen_movi_tl(cpu_so, 1);
982 }
983 gen_set_label(l2);
984 if (unlikely(Rc(ctx->opcode) != 0))
985 gen_set_Rc0(ctx, ret);
986 }
987 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
988 static void glue(gen_, name)(DisasContext *ctx) \
989 { \
990 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
991 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
992 sign, compute_ov); \
993 }
994 /* divwu divwu. divwuo divwuo. */
995 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
996 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
997 /* divw divw. divwo divwo. */
998 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
999 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1000 #endif
1001
1002 /* mulhw mulhw. */
1003 static void gen_mulhw(DisasContext *ctx)
1004 {
1005 TCGv_i32 t0 = tcg_temp_new_i32();
1006 TCGv_i32 t1 = tcg_temp_new_i32();
1007
1008 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1009 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1010 tcg_gen_muls2_i32(t0, t1, t0, t1);
1011 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1012 tcg_temp_free_i32(t0);
1013 tcg_temp_free_i32(t1);
1014 if (unlikely(Rc(ctx->opcode) != 0))
1015 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1016 }
1017
1018 /* mulhwu mulhwu. */
1019 static void gen_mulhwu(DisasContext *ctx)
1020 {
1021 TCGv_i32 t0 = tcg_temp_new_i32();
1022 TCGv_i32 t1 = tcg_temp_new_i32();
1023
1024 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1025 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1026 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1027 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1028 tcg_temp_free_i32(t0);
1029 tcg_temp_free_i32(t1);
1030 if (unlikely(Rc(ctx->opcode) != 0))
1031 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1032 }
1033
1034 /* mullw mullw. */
1035 static void gen_mullw(DisasContext *ctx)
1036 {
1037 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1038 cpu_gpr[rB(ctx->opcode)]);
1039 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1040 if (unlikely(Rc(ctx->opcode) != 0))
1041 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1042 }
1043
1044 /* mullwo mullwo. */
1045 static void gen_mullwo(DisasContext *ctx)
1046 {
1047 TCGv_i32 t0 = tcg_temp_new_i32();
1048 TCGv_i32 t1 = tcg_temp_new_i32();
1049
1050 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1051 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1052 tcg_gen_muls2_i32(t0, t1, t0, t1);
1053 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1054
1055 tcg_gen_sari_i32(t0, t0, 31);
1056 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1057 tcg_gen_extu_i32_tl(cpu_ov, t0);
1058 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1059
1060 tcg_temp_free_i32(t0);
1061 tcg_temp_free_i32(t1);
1062 if (unlikely(Rc(ctx->opcode) != 0))
1063 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1064 }
1065
1066 /* mulli */
1067 static void gen_mulli(DisasContext *ctx)
1068 {
1069 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1070 SIMM(ctx->opcode));
1071 }
1072
1073 #if defined(TARGET_PPC64)
1074 /* mulhd mulhd. */
1075 static void gen_mulhd(DisasContext *ctx)
1076 {
1077 TCGv lo = tcg_temp_new();
1078 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1079 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1080 tcg_temp_free(lo);
1081 if (unlikely(Rc(ctx->opcode) != 0)) {
1082 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1083 }
1084 }
1085
1086 /* mulhdu mulhdu. */
1087 static void gen_mulhdu(DisasContext *ctx)
1088 {
1089 TCGv lo = tcg_temp_new();
1090 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1091 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1092 tcg_temp_free(lo);
1093 if (unlikely(Rc(ctx->opcode) != 0)) {
1094 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1095 }
1096 }
1097
1098 /* mulld mulld. */
1099 static void gen_mulld(DisasContext *ctx)
1100 {
1101 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1102 cpu_gpr[rB(ctx->opcode)]);
1103 if (unlikely(Rc(ctx->opcode) != 0))
1104 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1105 }
1106
1107 /* mulldo mulldo. */
1108 static void gen_mulldo(DisasContext *ctx)
1109 {
1110 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1111 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1112 if (unlikely(Rc(ctx->opcode) != 0)) {
1113 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1114 }
1115 }
1116 #endif
1117
1118 /* Common subf function */
1119 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1120 TCGv arg2, bool add_ca, bool compute_ca,
1121 bool compute_ov, bool compute_rc0)
1122 {
1123 TCGv t0 = ret;
1124
1125 if (compute_ov && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) {
1126 t0 = tcg_temp_new();
1127 }
1128
1129 if (compute_ca) {
1130 /* dest = ~arg1 + arg2 [+ ca]. */
1131 if (NARROW_MODE(ctx)) {
1132 TCGv inv1 = tcg_temp_new();
1133 tcg_gen_not_tl(inv1, arg1);
1134 tcg_gen_ext32u_tl(t0, arg2);
1135 tcg_gen_ext32u_tl(inv1, inv1);
1136 if (add_ca) {
1137 tcg_gen_add_tl(t0, t0, cpu_ca);
1138 } else {
1139 tcg_gen_addi_tl(t0, t0, 1);
1140 }
1141 tcg_gen_add_tl(t0, t0, inv1);
1142 tcg_gen_shri_tl(cpu_ca, t0, 32);
1143 } else if (add_ca) {
1144 TCGv zero, inv1 = tcg_temp_new();
1145 tcg_gen_not_tl(inv1, arg1);
1146 zero = tcg_const_tl(0);
1147 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1148 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1149 tcg_temp_free(zero);
1150 tcg_temp_free(inv1);
1151 } else {
1152 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1153 tcg_gen_sub_tl(t0, arg2, arg1);
1154 }
1155 } else if (add_ca) {
1156 /* Since we're ignoring carry-out, we can simplify the
1157 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1158 tcg_gen_sub_tl(t0, arg2, arg1);
1159 tcg_gen_add_tl(t0, t0, cpu_ca);
1160 tcg_gen_subi_tl(t0, t0, 1);
1161 } else {
1162 tcg_gen_sub_tl(t0, arg2, arg1);
1163 }
1164
1165 if (compute_ov) {
1166 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1167 }
1168 if (unlikely(compute_rc0)) {
1169 gen_set_Rc0(ctx, t0);
1170 }
1171
1172 if (!TCGV_EQUAL(t0, ret)) {
1173 tcg_gen_mov_tl(ret, t0);
1174 tcg_temp_free(t0);
1175 }
1176 }
1177 /* Sub functions with Two operands functions */
1178 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1179 static void glue(gen_, name)(DisasContext *ctx) \
1180 { \
1181 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1182 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1183 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1184 }
1185 /* Sub functions with one operand and one immediate */
1186 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1187 add_ca, compute_ca, compute_ov) \
1188 static void glue(gen_, name)(DisasContext *ctx) \
1189 { \
1190 TCGv t0 = tcg_const_tl(const_val); \
1191 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1192 cpu_gpr[rA(ctx->opcode)], t0, \
1193 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1194 tcg_temp_free(t0); \
1195 }
1196 /* subf subf. subfo subfo. */
1197 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1198 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1199 /* subfc subfc. subfco subfco. */
1200 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1201 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1202 /* subfe subfe. subfeo subfo. */
1203 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1204 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1205 /* subfme subfme. subfmeo subfmeo. */
1206 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1207 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1208 /* subfze subfze. subfzeo subfzeo.*/
1209 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1210 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1211
1212 /* subfic */
1213 static void gen_subfic(DisasContext *ctx)
1214 {
1215 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1216 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1217 c, 0, 1, 0, 0);
1218 tcg_temp_free(c);
1219 }
1220
1221 /* neg neg. nego nego. */
1222 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1223 {
1224 TCGv zero = tcg_const_tl(0);
1225 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1226 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1227 tcg_temp_free(zero);
1228 }
1229
1230 static void gen_neg(DisasContext *ctx)
1231 {
1232 gen_op_arith_neg(ctx, 0);
1233 }
1234
1235 static void gen_nego(DisasContext *ctx)
1236 {
1237 gen_op_arith_neg(ctx, 1);
1238 }
1239
1240 /*** Integer logical ***/
1241 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1242 static void glue(gen_, name)(DisasContext *ctx) \
1243 { \
1244 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1245 cpu_gpr[rB(ctx->opcode)]); \
1246 if (unlikely(Rc(ctx->opcode) != 0)) \
1247 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1248 }
1249
1250 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1251 static void glue(gen_, name)(DisasContext *ctx) \
1252 { \
1253 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1254 if (unlikely(Rc(ctx->opcode) != 0)) \
1255 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1256 }
1257
1258 /* and & and. */
1259 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1260 /* andc & andc. */
1261 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1262
1263 /* andi. */
1264 static void gen_andi_(DisasContext *ctx)
1265 {
1266 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1267 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1268 }
1269
1270 /* andis. */
1271 static void gen_andis_(DisasContext *ctx)
1272 {
1273 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1274 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1275 }
1276
1277 /* cntlzw */
1278 static void gen_cntlzw(DisasContext *ctx)
1279 {
1280 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1281 if (unlikely(Rc(ctx->opcode) != 0))
1282 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1283 }
1284 /* eqv & eqv. */
1285 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1286 /* extsb & extsb. */
1287 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1288 /* extsh & extsh. */
1289 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1290 /* nand & nand. */
1291 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1292 /* nor & nor. */
1293 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1294
1295 /* or & or. */
1296 static void gen_or(DisasContext *ctx)
1297 {
1298 int rs, ra, rb;
1299
1300 rs = rS(ctx->opcode);
1301 ra = rA(ctx->opcode);
1302 rb = rB(ctx->opcode);
1303 /* Optimisation for mr. ri case */
1304 if (rs != ra || rs != rb) {
1305 if (rs != rb)
1306 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1307 else
1308 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1309 if (unlikely(Rc(ctx->opcode) != 0))
1310 gen_set_Rc0(ctx, cpu_gpr[ra]);
1311 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1312 gen_set_Rc0(ctx, cpu_gpr[rs]);
1313 #if defined(TARGET_PPC64)
1314 } else {
1315 int prio = 0;
1316
1317 switch (rs) {
1318 case 1:
1319 /* Set process priority to low */
1320 prio = 2;
1321 break;
1322 case 6:
1323 /* Set process priority to medium-low */
1324 prio = 3;
1325 break;
1326 case 2:
1327 /* Set process priority to normal */
1328 prio = 4;
1329 break;
1330 #if !defined(CONFIG_USER_ONLY)
1331 case 31:
1332 if (ctx->mem_idx > 0) {
1333 /* Set process priority to very low */
1334 prio = 1;
1335 }
1336 break;
1337 case 5:
1338 if (ctx->mem_idx > 0) {
1339 /* Set process priority to medium-hight */
1340 prio = 5;
1341 }
1342 break;
1343 case 3:
1344 if (ctx->mem_idx > 0) {
1345 /* Set process priority to high */
1346 prio = 6;
1347 }
1348 break;
1349 case 7:
1350 if (ctx->mem_idx > 1) {
1351 /* Set process priority to very high */
1352 prio = 7;
1353 }
1354 break;
1355 #endif
1356 default:
1357 /* nop */
1358 break;
1359 }
1360 if (prio) {
1361 TCGv t0 = tcg_temp_new();
1362 gen_load_spr(t0, SPR_PPR);
1363 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1364 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1365 gen_store_spr(SPR_PPR, t0);
1366 tcg_temp_free(t0);
1367 }
1368 #endif
1369 }
1370 }
1371 /* orc & orc. */
1372 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1373
1374 /* xor & xor. */
1375 static void gen_xor(DisasContext *ctx)
1376 {
1377 /* Optimisation for "set to zero" case */
1378 if (rS(ctx->opcode) != rB(ctx->opcode))
1379 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1380 else
1381 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1382 if (unlikely(Rc(ctx->opcode) != 0))
1383 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1384 }
1385
1386 /* ori */
1387 static void gen_ori(DisasContext *ctx)
1388 {
1389 target_ulong uimm = UIMM(ctx->opcode);
1390
1391 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1392 /* NOP */
1393 /* XXX: should handle special NOPs for POWER series */
1394 return;
1395 }
1396 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1397 }
1398
1399 /* oris */
1400 static void gen_oris(DisasContext *ctx)
1401 {
1402 target_ulong uimm = UIMM(ctx->opcode);
1403
1404 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1405 /* NOP */
1406 return;
1407 }
1408 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1409 }
1410
1411 /* xori */
1412 static void gen_xori(DisasContext *ctx)
1413 {
1414 target_ulong uimm = UIMM(ctx->opcode);
1415
1416 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1417 /* NOP */
1418 return;
1419 }
1420 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1421 }
1422
1423 /* xoris */
1424 static void gen_xoris(DisasContext *ctx)
1425 {
1426 target_ulong uimm = UIMM(ctx->opcode);
1427
1428 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1429 /* NOP */
1430 return;
1431 }
1432 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1433 }
1434
1435 /* popcntb : PowerPC 2.03 specification */
1436 static void gen_popcntb(DisasContext *ctx)
1437 {
1438 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1439 }
1440
1441 static void gen_popcntw(DisasContext *ctx)
1442 {
1443 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1444 }
1445
1446 #if defined(TARGET_PPC64)
1447 /* popcntd: PowerPC 2.06 specification */
1448 static void gen_popcntd(DisasContext *ctx)
1449 {
1450 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1451 }
1452 #endif
1453
1454 #if defined(TARGET_PPC64)
1455 /* extsw & extsw. */
1456 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1457
1458 /* cntlzd */
1459 static void gen_cntlzd(DisasContext *ctx)
1460 {
1461 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1462 if (unlikely(Rc(ctx->opcode) != 0))
1463 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1464 }
1465 #endif
1466
1467 /*** Integer rotate ***/
1468
1469 /* rlwimi & rlwimi. */
1470 static void gen_rlwimi(DisasContext *ctx)
1471 {
1472 uint32_t mb, me, sh;
1473
1474 mb = MB(ctx->opcode);
1475 me = ME(ctx->opcode);
1476 sh = SH(ctx->opcode);
1477 if (likely(sh == 0 && mb == 0 && me == 31)) {
1478 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1479 } else {
1480 target_ulong mask;
1481 TCGv t1;
1482 TCGv t0 = tcg_temp_new();
1483 #if defined(TARGET_PPC64)
1484 TCGv_i32 t2 = tcg_temp_new_i32();
1485 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1486 tcg_gen_rotli_i32(t2, t2, sh);
1487 tcg_gen_extu_i32_i64(t0, t2);
1488 tcg_temp_free_i32(t2);
1489 #else
1490 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1491 #endif
1492 #if defined(TARGET_PPC64)
1493 mb += 32;
1494 me += 32;
1495 #endif
1496 mask = MASK(mb, me);
1497 t1 = tcg_temp_new();
1498 tcg_gen_andi_tl(t0, t0, mask);
1499 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1500 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1501 tcg_temp_free(t0);
1502 tcg_temp_free(t1);
1503 }
1504 if (unlikely(Rc(ctx->opcode) != 0))
1505 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1506 }
1507
1508 /* rlwinm & rlwinm. */
1509 static void gen_rlwinm(DisasContext *ctx)
1510 {
1511 uint32_t mb, me, sh;
1512
1513 sh = SH(ctx->opcode);
1514 mb = MB(ctx->opcode);
1515 me = ME(ctx->opcode);
1516
1517 if (likely(mb == 0 && me == (31 - sh))) {
1518 if (likely(sh == 0)) {
1519 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1520 } else {
1521 TCGv t0 = tcg_temp_new();
1522 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1523 tcg_gen_shli_tl(t0, t0, sh);
1524 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1525 tcg_temp_free(t0);
1526 }
1527 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1528 TCGv t0 = tcg_temp_new();
1529 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1530 tcg_gen_shri_tl(t0, t0, mb);
1531 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1532 tcg_temp_free(t0);
1533 } else {
1534 TCGv t0 = tcg_temp_new();
1535 #if defined(TARGET_PPC64)
1536 TCGv_i32 t1 = tcg_temp_new_i32();
1537 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1538 tcg_gen_rotli_i32(t1, t1, sh);
1539 tcg_gen_extu_i32_i64(t0, t1);
1540 tcg_temp_free_i32(t1);
1541 #else
1542 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1543 #endif
1544 #if defined(TARGET_PPC64)
1545 mb += 32;
1546 me += 32;
1547 #endif
1548 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1549 tcg_temp_free(t0);
1550 }
1551 if (unlikely(Rc(ctx->opcode) != 0))
1552 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1553 }
1554
1555 /* rlwnm & rlwnm. */
1556 static void gen_rlwnm(DisasContext *ctx)
1557 {
1558 uint32_t mb, me;
1559 TCGv t0;
1560 #if defined(TARGET_PPC64)
1561 TCGv_i32 t1, t2;
1562 #endif
1563
1564 mb = MB(ctx->opcode);
1565 me = ME(ctx->opcode);
1566 t0 = tcg_temp_new();
1567 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1568 #if defined(TARGET_PPC64)
1569 t1 = tcg_temp_new_i32();
1570 t2 = tcg_temp_new_i32();
1571 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1572 tcg_gen_trunc_i64_i32(t2, t0);
1573 tcg_gen_rotl_i32(t1, t1, t2);
1574 tcg_gen_extu_i32_i64(t0, t1);
1575 tcg_temp_free_i32(t1);
1576 tcg_temp_free_i32(t2);
1577 #else
1578 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1579 #endif
1580 if (unlikely(mb != 0 || me != 31)) {
1581 #if defined(TARGET_PPC64)
1582 mb += 32;
1583 me += 32;
1584 #endif
1585 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1586 } else {
1587 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1588 }
1589 tcg_temp_free(t0);
1590 if (unlikely(Rc(ctx->opcode) != 0))
1591 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1592 }
1593
1594 #if defined(TARGET_PPC64)
1595 #define GEN_PPC64_R2(name, opc1, opc2) \
1596 static void glue(gen_, name##0)(DisasContext *ctx) \
1597 { \
1598 gen_##name(ctx, 0); \
1599 } \
1600 \
1601 static void glue(gen_, name##1)(DisasContext *ctx) \
1602 { \
1603 gen_##name(ctx, 1); \
1604 }
1605 #define GEN_PPC64_R4(name, opc1, opc2) \
1606 static void glue(gen_, name##0)(DisasContext *ctx) \
1607 { \
1608 gen_##name(ctx, 0, 0); \
1609 } \
1610 \
1611 static void glue(gen_, name##1)(DisasContext *ctx) \
1612 { \
1613 gen_##name(ctx, 0, 1); \
1614 } \
1615 \
1616 static void glue(gen_, name##2)(DisasContext *ctx) \
1617 { \
1618 gen_##name(ctx, 1, 0); \
1619 } \
1620 \
1621 static void glue(gen_, name##3)(DisasContext *ctx) \
1622 { \
1623 gen_##name(ctx, 1, 1); \
1624 }
1625
1626 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1627 uint32_t sh)
1628 {
1629 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1630 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1631 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1632 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1633 } else {
1634 TCGv t0 = tcg_temp_new();
1635 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1636 if (likely(mb == 0 && me == 63)) {
1637 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1638 } else {
1639 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1640 }
1641 tcg_temp_free(t0);
1642 }
1643 if (unlikely(Rc(ctx->opcode) != 0))
1644 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1645 }
1646 /* rldicl - rldicl. */
1647 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1648 {
1649 uint32_t sh, mb;
1650
1651 sh = SH(ctx->opcode) | (shn << 5);
1652 mb = MB(ctx->opcode) | (mbn << 5);
1653 gen_rldinm(ctx, mb, 63, sh);
1654 }
1655 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1656 /* rldicr - rldicr. */
1657 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1658 {
1659 uint32_t sh, me;
1660
1661 sh = SH(ctx->opcode) | (shn << 5);
1662 me = MB(ctx->opcode) | (men << 5);
1663 gen_rldinm(ctx, 0, me, sh);
1664 }
1665 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1666 /* rldic - rldic. */
1667 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1668 {
1669 uint32_t sh, mb;
1670
1671 sh = SH(ctx->opcode) | (shn << 5);
1672 mb = MB(ctx->opcode) | (mbn << 5);
1673 gen_rldinm(ctx, mb, 63 - sh, sh);
1674 }
1675 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1676
1677 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1678 {
1679 TCGv t0;
1680
1681 mb = MB(ctx->opcode);
1682 me = ME(ctx->opcode);
1683 t0 = tcg_temp_new();
1684 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1685 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1686 if (unlikely(mb != 0 || me != 63)) {
1687 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1688 } else {
1689 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1690 }
1691 tcg_temp_free(t0);
1692 if (unlikely(Rc(ctx->opcode) != 0))
1693 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1694 }
1695
1696 /* rldcl - rldcl. */
1697 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1698 {
1699 uint32_t mb;
1700
1701 mb = MB(ctx->opcode) | (mbn << 5);
1702 gen_rldnm(ctx, mb, 63);
1703 }
1704 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1705 /* rldcr - rldcr. */
1706 static inline void gen_rldcr(DisasContext *ctx, int men)
1707 {
1708 uint32_t me;
1709
1710 me = MB(ctx->opcode) | (men << 5);
1711 gen_rldnm(ctx, 0, me);
1712 }
1713 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1714 /* rldimi - rldimi. */
1715 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1716 {
1717 uint32_t sh, mb, me;
1718
1719 sh = SH(ctx->opcode) | (shn << 5);
1720 mb = MB(ctx->opcode) | (mbn << 5);
1721 me = 63 - sh;
1722 if (unlikely(sh == 0 && mb == 0)) {
1723 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1724 } else {
1725 TCGv t0, t1;
1726 target_ulong mask;
1727
1728 t0 = tcg_temp_new();
1729 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1730 t1 = tcg_temp_new();
1731 mask = MASK(mb, me);
1732 tcg_gen_andi_tl(t0, t0, mask);
1733 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1734 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1735 tcg_temp_free(t0);
1736 tcg_temp_free(t1);
1737 }
1738 if (unlikely(Rc(ctx->opcode) != 0))
1739 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1740 }
1741 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1742 #endif
1743
1744 /*** Integer shift ***/
1745
1746 /* slw & slw. */
1747 static void gen_slw(DisasContext *ctx)
1748 {
1749 TCGv t0, t1;
1750
1751 t0 = tcg_temp_new();
1752 /* AND rS with a mask that is 0 when rB >= 0x20 */
1753 #if defined(TARGET_PPC64)
1754 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1755 tcg_gen_sari_tl(t0, t0, 0x3f);
1756 #else
1757 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1758 tcg_gen_sari_tl(t0, t0, 0x1f);
1759 #endif
1760 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1761 t1 = tcg_temp_new();
1762 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1763 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1764 tcg_temp_free(t1);
1765 tcg_temp_free(t0);
1766 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1767 if (unlikely(Rc(ctx->opcode) != 0))
1768 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1769 }
1770
1771 /* sraw & sraw. */
1772 static void gen_sraw(DisasContext *ctx)
1773 {
1774 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1775 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1776 if (unlikely(Rc(ctx->opcode) != 0))
1777 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1778 }
1779
1780 /* srawi & srawi. */
1781 static void gen_srawi(DisasContext *ctx)
1782 {
1783 int sh = SH(ctx->opcode);
1784 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1785 TCGv src = cpu_gpr[rS(ctx->opcode)];
1786 if (sh == 0) {
1787 tcg_gen_mov_tl(dst, src);
1788 tcg_gen_movi_tl(cpu_ca, 0);
1789 } else {
1790 TCGv t0;
1791 tcg_gen_ext32s_tl(dst, src);
1792 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1793 t0 = tcg_temp_new();
1794 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1795 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1796 tcg_temp_free(t0);
1797 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1798 tcg_gen_sari_tl(dst, dst, sh);
1799 }
1800 if (unlikely(Rc(ctx->opcode) != 0)) {
1801 gen_set_Rc0(ctx, dst);
1802 }
1803 }
1804
1805 /* srw & srw. */
1806 static void gen_srw(DisasContext *ctx)
1807 {
1808 TCGv t0, t1;
1809
1810 t0 = tcg_temp_new();
1811 /* AND rS with a mask that is 0 when rB >= 0x20 */
1812 #if defined(TARGET_PPC64)
1813 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1814 tcg_gen_sari_tl(t0, t0, 0x3f);
1815 #else
1816 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1817 tcg_gen_sari_tl(t0, t0, 0x1f);
1818 #endif
1819 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1820 tcg_gen_ext32u_tl(t0, t0);
1821 t1 = tcg_temp_new();
1822 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1823 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1824 tcg_temp_free(t1);
1825 tcg_temp_free(t0);
1826 if (unlikely(Rc(ctx->opcode) != 0))
1827 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1828 }
1829
1830 #if defined(TARGET_PPC64)
1831 /* sld & sld. */
1832 static void gen_sld(DisasContext *ctx)
1833 {
1834 TCGv t0, t1;
1835
1836 t0 = tcg_temp_new();
1837 /* AND rS with a mask that is 0 when rB >= 0x40 */
1838 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1839 tcg_gen_sari_tl(t0, t0, 0x3f);
1840 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1841 t1 = tcg_temp_new();
1842 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1843 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1844 tcg_temp_free(t1);
1845 tcg_temp_free(t0);
1846 if (unlikely(Rc(ctx->opcode) != 0))
1847 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1848 }
1849
1850 /* srad & srad. */
1851 static void gen_srad(DisasContext *ctx)
1852 {
1853 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1854 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1855 if (unlikely(Rc(ctx->opcode) != 0))
1856 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1857 }
1858 /* sradi & sradi. */
1859 static inline void gen_sradi(DisasContext *ctx, int n)
1860 {
1861 int sh = SH(ctx->opcode) + (n << 5);
1862 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1863 TCGv src = cpu_gpr[rS(ctx->opcode)];
1864 if (sh == 0) {
1865 tcg_gen_mov_tl(dst, src);
1866 tcg_gen_movi_tl(cpu_ca, 0);
1867 } else {
1868 TCGv t0;
1869 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1870 t0 = tcg_temp_new();
1871 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1872 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1873 tcg_temp_free(t0);
1874 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1875 tcg_gen_sari_tl(dst, src, sh);
1876 }
1877 if (unlikely(Rc(ctx->opcode) != 0)) {
1878 gen_set_Rc0(ctx, dst);
1879 }
1880 }
1881
1882 static void gen_sradi0(DisasContext *ctx)
1883 {
1884 gen_sradi(ctx, 0);
1885 }
1886
1887 static void gen_sradi1(DisasContext *ctx)
1888 {
1889 gen_sradi(ctx, 1);
1890 }
1891
1892 /* srd & srd. */
1893 static void gen_srd(DisasContext *ctx)
1894 {
1895 TCGv t0, t1;
1896
1897 t0 = tcg_temp_new();
1898 /* AND rS with a mask that is 0 when rB >= 0x40 */
1899 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1900 tcg_gen_sari_tl(t0, t0, 0x3f);
1901 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1902 t1 = tcg_temp_new();
1903 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1904 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1905 tcg_temp_free(t1);
1906 tcg_temp_free(t0);
1907 if (unlikely(Rc(ctx->opcode) != 0))
1908 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1909 }
1910 #endif
1911
1912 /*** Floating-Point arithmetic ***/
1913 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1914 static void gen_f##name(DisasContext *ctx) \
1915 { \
1916 if (unlikely(!ctx->fpu_enabled)) { \
1917 gen_exception(ctx, POWERPC_EXCP_FPU); \
1918 return; \
1919 } \
1920 /* NIP cannot be restored if the memory exception comes from an helper */ \
1921 gen_update_nip(ctx, ctx->nip - 4); \
1922 gen_reset_fpstatus(); \
1923 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1924 cpu_fpr[rA(ctx->opcode)], \
1925 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1926 if (isfloat) { \
1927 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1928 cpu_fpr[rD(ctx->opcode)]); \
1929 } \
1930 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
1931 Rc(ctx->opcode) != 0); \
1932 }
1933
1934 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1935 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1936 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1937
1938 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1939 static void gen_f##name(DisasContext *ctx) \
1940 { \
1941 if (unlikely(!ctx->fpu_enabled)) { \
1942 gen_exception(ctx, POWERPC_EXCP_FPU); \
1943 return; \
1944 } \
1945 /* NIP cannot be restored if the memory exception comes from an helper */ \
1946 gen_update_nip(ctx, ctx->nip - 4); \
1947 gen_reset_fpstatus(); \
1948 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1949 cpu_fpr[rA(ctx->opcode)], \
1950 cpu_fpr[rB(ctx->opcode)]); \
1951 if (isfloat) { \
1952 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1953 cpu_fpr[rD(ctx->opcode)]); \
1954 } \
1955 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1956 set_fprf, Rc(ctx->opcode) != 0); \
1957 }
1958 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1959 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1960 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1961
1962 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1963 static void gen_f##name(DisasContext *ctx) \
1964 { \
1965 if (unlikely(!ctx->fpu_enabled)) { \
1966 gen_exception(ctx, POWERPC_EXCP_FPU); \
1967 return; \
1968 } \
1969 /* NIP cannot be restored if the memory exception comes from an helper */ \
1970 gen_update_nip(ctx, ctx->nip - 4); \
1971 gen_reset_fpstatus(); \
1972 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1973 cpu_fpr[rA(ctx->opcode)], \
1974 cpu_fpr[rC(ctx->opcode)]); \
1975 if (isfloat) { \
1976 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1977 cpu_fpr[rD(ctx->opcode)]); \
1978 } \
1979 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1980 set_fprf, Rc(ctx->opcode) != 0); \
1981 }
1982 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1983 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1984 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1985
1986 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
1987 static void gen_f##name(DisasContext *ctx) \
1988 { \
1989 if (unlikely(!ctx->fpu_enabled)) { \
1990 gen_exception(ctx, POWERPC_EXCP_FPU); \
1991 return; \
1992 } \
1993 /* NIP cannot be restored if the memory exception comes from an helper */ \
1994 gen_update_nip(ctx, ctx->nip - 4); \
1995 gen_reset_fpstatus(); \
1996 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1997 cpu_fpr[rB(ctx->opcode)]); \
1998 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1999 set_fprf, Rc(ctx->opcode) != 0); \
2000 }
2001
2002 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2003 static void gen_f##name(DisasContext *ctx) \
2004 { \
2005 if (unlikely(!ctx->fpu_enabled)) { \
2006 gen_exception(ctx, POWERPC_EXCP_FPU); \
2007 return; \
2008 } \
2009 /* NIP cannot be restored if the memory exception comes from an helper */ \
2010 gen_update_nip(ctx, ctx->nip - 4); \
2011 gen_reset_fpstatus(); \
2012 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2013 cpu_fpr[rB(ctx->opcode)]); \
2014 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2015 set_fprf, Rc(ctx->opcode) != 0); \
2016 }
2017
2018 /* fadd - fadds */
2019 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2020 /* fdiv - fdivs */
2021 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2022 /* fmul - fmuls */
2023 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2024
2025 /* fre */
2026 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2027
2028 /* fres */
2029 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2030
2031 /* frsqrte */
2032 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2033
2034 /* frsqrtes */
2035 static void gen_frsqrtes(DisasContext *ctx)
2036 {
2037 if (unlikely(!ctx->fpu_enabled)) {
2038 gen_exception(ctx, POWERPC_EXCP_FPU);
2039 return;
2040 }
2041 /* NIP cannot be restored if the memory exception comes from an helper */
2042 gen_update_nip(ctx, ctx->nip - 4);
2043 gen_reset_fpstatus();
2044 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2045 cpu_fpr[rB(ctx->opcode)]);
2046 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2047 cpu_fpr[rD(ctx->opcode)]);
2048 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2049 }
2050
2051 /* fsel */
2052 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2053 /* fsub - fsubs */
2054 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2055 /* Optional: */
2056
2057 /* fsqrt */
2058 static void gen_fsqrt(DisasContext *ctx)
2059 {
2060 if (unlikely(!ctx->fpu_enabled)) {
2061 gen_exception(ctx, POWERPC_EXCP_FPU);
2062 return;
2063 }
2064 /* NIP cannot be restored if the memory exception comes from an helper */
2065 gen_update_nip(ctx, ctx->nip - 4);
2066 gen_reset_fpstatus();
2067 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2068 cpu_fpr[rB(ctx->opcode)]);
2069 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2070 }
2071
2072 static void gen_fsqrts(DisasContext *ctx)
2073 {
2074 if (unlikely(!ctx->fpu_enabled)) {
2075 gen_exception(ctx, POWERPC_EXCP_FPU);
2076 return;
2077 }
2078 /* NIP cannot be restored if the memory exception comes from an helper */
2079 gen_update_nip(ctx, ctx->nip - 4);
2080 gen_reset_fpstatus();
2081 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2082 cpu_fpr[rB(ctx->opcode)]);
2083 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2084 cpu_fpr[rD(ctx->opcode)]);
2085 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2086 }
2087
2088 /*** Floating-Point multiply-and-add ***/
2089 /* fmadd - fmadds */
2090 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2091 /* fmsub - fmsubs */
2092 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2093 /* fnmadd - fnmadds */
2094 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2095 /* fnmsub - fnmsubs */
2096 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2097
2098 /*** Floating-Point round & convert ***/
2099 /* fctiw */
2100 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2101 /* fctiwz */
2102 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2103 /* frsp */
2104 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2105 #if defined(TARGET_PPC64)
2106 /* fcfid */
2107 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2108 /* fctid */
2109 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2110 /* fctidz */
2111 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2112 #endif
2113
2114 /* frin */
2115 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2116 /* friz */
2117 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2118 /* frip */
2119 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2120 /* frim */
2121 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2122
2123 /*** Floating-Point compare ***/
2124
2125 /* fcmpo */
2126 static void gen_fcmpo(DisasContext *ctx)
2127 {
2128 TCGv_i32 crf;
2129 if (unlikely(!ctx->fpu_enabled)) {
2130 gen_exception(ctx, POWERPC_EXCP_FPU);
2131 return;
2132 }
2133 /* NIP cannot be restored if the memory exception comes from an helper */
2134 gen_update_nip(ctx, ctx->nip - 4);
2135 gen_reset_fpstatus();
2136 crf = tcg_const_i32(crfD(ctx->opcode));
2137 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2138 cpu_fpr[rB(ctx->opcode)], crf);
2139 tcg_temp_free_i32(crf);
2140 gen_helper_float_check_status(cpu_env);
2141 }
2142
2143 /* fcmpu */
2144 static void gen_fcmpu(DisasContext *ctx)
2145 {
2146 TCGv_i32 crf;
2147 if (unlikely(!ctx->fpu_enabled)) {
2148 gen_exception(ctx, POWERPC_EXCP_FPU);
2149 return;
2150 }
2151 /* NIP cannot be restored if the memory exception comes from an helper */
2152 gen_update_nip(ctx, ctx->nip - 4);
2153 gen_reset_fpstatus();
2154 crf = tcg_const_i32(crfD(ctx->opcode));
2155 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2156 cpu_fpr[rB(ctx->opcode)], crf);
2157 tcg_temp_free_i32(crf);
2158 gen_helper_float_check_status(cpu_env);
2159 }
2160
2161 /*** Floating-point move ***/
2162 /* fabs */
2163 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2164 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2165
2166 /* fmr - fmr. */
2167 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2168 static void gen_fmr(DisasContext *ctx)
2169 {
2170 if (unlikely(!ctx->fpu_enabled)) {
2171 gen_exception(ctx, POWERPC_EXCP_FPU);
2172 return;
2173 }
2174 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2175 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2176 }
2177
2178 /* fnabs */
2179 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2180 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2181 /* fneg */
2182 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2183 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2184
2185 /*** Floating-Point status & ctrl register ***/
2186
2187 /* mcrfs */
2188 static void gen_mcrfs(DisasContext *ctx)
2189 {
2190 TCGv tmp = tcg_temp_new();
2191 int bfa;
2192
2193 if (unlikely(!ctx->fpu_enabled)) {
2194 gen_exception(ctx, POWERPC_EXCP_FPU);
2195 return;
2196 }
2197 bfa = 4 * (7 - crfS(ctx->opcode));
2198 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2199 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2200 tcg_temp_free(tmp);
2201 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2202 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2203 }
2204
2205 /* mffs */
2206 static void gen_mffs(DisasContext *ctx)
2207 {
2208 if (unlikely(!ctx->fpu_enabled)) {
2209 gen_exception(ctx, POWERPC_EXCP_FPU);
2210 return;
2211 }
2212 gen_reset_fpstatus();
2213 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2214 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2215 }
2216
2217 /* mtfsb0 */
2218 static void gen_mtfsb0(DisasContext *ctx)
2219 {
2220 uint8_t crb;
2221
2222 if (unlikely(!ctx->fpu_enabled)) {
2223 gen_exception(ctx, POWERPC_EXCP_FPU);
2224 return;
2225 }
2226 crb = 31 - crbD(ctx->opcode);
2227 gen_reset_fpstatus();
2228 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2229 TCGv_i32 t0;
2230 /* NIP cannot be restored if the memory exception comes from an helper */
2231 gen_update_nip(ctx, ctx->nip - 4);
2232 t0 = tcg_const_i32(crb);
2233 gen_helper_fpscr_clrbit(cpu_env, t0);
2234 tcg_temp_free_i32(t0);
2235 }
2236 if (unlikely(Rc(ctx->opcode) != 0)) {
2237 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2238 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2239 }
2240 }
2241
2242 /* mtfsb1 */
2243 static void gen_mtfsb1(DisasContext *ctx)
2244 {
2245 uint8_t crb;
2246
2247 if (unlikely(!ctx->fpu_enabled)) {
2248 gen_exception(ctx, POWERPC_EXCP_FPU);
2249 return;
2250 }
2251 crb = 31 - crbD(ctx->opcode);
2252 gen_reset_fpstatus();
2253 /* XXX: we pretend we can only do IEEE floating-point computations */
2254 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2255 TCGv_i32 t0;
2256 /* NIP cannot be restored if the memory exception comes from an helper */
2257 gen_update_nip(ctx, ctx->nip - 4);
2258 t0 = tcg_const_i32(crb);
2259 gen_helper_fpscr_setbit(cpu_env, t0);
2260 tcg_temp_free_i32(t0);
2261 }
2262 if (unlikely(Rc(ctx->opcode) != 0)) {
2263 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2264 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2265 }
2266 /* We can raise a differed exception */
2267 gen_helper_float_check_status(cpu_env);
2268 }
2269
2270 /* mtfsf */
2271 static void gen_mtfsf(DisasContext *ctx)
2272 {
2273 TCGv_i32 t0;
2274 int L = ctx->opcode & 0x02000000;
2275
2276 if (unlikely(!ctx->fpu_enabled)) {
2277 gen_exception(ctx, POWERPC_EXCP_FPU);
2278 return;
2279 }
2280 /* NIP cannot be restored if the memory exception comes from an helper */
2281 gen_update_nip(ctx, ctx->nip - 4);
2282 gen_reset_fpstatus();
2283 if (L)
2284 t0 = tcg_const_i32(0xff);
2285 else
2286 t0 = tcg_const_i32(FM(ctx->opcode));
2287 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2288 tcg_temp_free_i32(t0);
2289 if (unlikely(Rc(ctx->opcode) != 0)) {
2290 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2291 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2292 }
2293 /* We can raise a differed exception */
2294 gen_helper_float_check_status(cpu_env);
2295 }
2296
2297 /* mtfsfi */
2298 static void gen_mtfsfi(DisasContext *ctx)
2299 {
2300 int bf, sh;
2301 TCGv_i64 t0;
2302 TCGv_i32 t1;
2303
2304 if (unlikely(!ctx->fpu_enabled)) {
2305 gen_exception(ctx, POWERPC_EXCP_FPU);
2306 return;
2307 }
2308 bf = crbD(ctx->opcode) >> 2;
2309 sh = 7 - bf;
2310 /* NIP cannot be restored if the memory exception comes from an helper */
2311 gen_update_nip(ctx, ctx->nip - 4);
2312 gen_reset_fpstatus();
2313 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2314 t1 = tcg_const_i32(1 << sh);
2315 gen_helper_store_fpscr(cpu_env, t0, t1);
2316 tcg_temp_free_i64(t0);
2317 tcg_temp_free_i32(t1);
2318 if (unlikely(Rc(ctx->opcode) != 0)) {
2319 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2320 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2321 }
2322 /* We can raise a differed exception */
2323 gen_helper_float_check_status(cpu_env);
2324 }
2325
2326 /*** Addressing modes ***/
2327 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2328 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2329 target_long maskl)
2330 {
2331 target_long simm = SIMM(ctx->opcode);
2332
2333 simm &= ~maskl;
2334 if (rA(ctx->opcode) == 0) {
2335 #if defined(TARGET_PPC64)
2336 if (!ctx->sf_mode) {
2337 tcg_gen_movi_tl(EA, (uint32_t)simm);
2338 } else
2339 #endif
2340 tcg_gen_movi_tl(EA, simm);
2341 } else if (likely(simm != 0)) {
2342 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2343 #if defined(TARGET_PPC64)
2344 if (!ctx->sf_mode) {
2345 tcg_gen_ext32u_tl(EA, EA);
2346 }
2347 #endif
2348 } else {
2349 #if defined(TARGET_PPC64)
2350 if (!ctx->sf_mode) {
2351 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2352 } else
2353 #endif
2354 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2355 }
2356 }
2357
2358 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2359 {
2360 if (rA(ctx->opcode) == 0) {
2361 #if defined(TARGET_PPC64)
2362 if (!ctx->sf_mode) {
2363 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2364 } else
2365 #endif
2366 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2367 } else {
2368 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2369 #if defined(TARGET_PPC64)
2370 if (!ctx->sf_mode) {
2371 tcg_gen_ext32u_tl(EA, EA);
2372 }
2373 #endif
2374 }
2375 }
2376
2377 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2378 {
2379 if (rA(ctx->opcode) == 0) {
2380 tcg_gen_movi_tl(EA, 0);
2381 } else {
2382 #if defined(TARGET_PPC64)
2383 if (!ctx->sf_mode) {
2384 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2385 } else
2386 #endif
2387 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2388 }
2389 }
2390
2391 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2392 target_long val)
2393 {
2394 tcg_gen_addi_tl(ret, arg1, val);
2395 #if defined(TARGET_PPC64)
2396 if (!ctx->sf_mode) {
2397 tcg_gen_ext32u_tl(ret, ret);
2398 }
2399 #endif
2400 }
2401
2402 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2403 {
2404 int l1 = gen_new_label();
2405 TCGv t0 = tcg_temp_new();
2406 TCGv_i32 t1, t2;
2407 /* NIP cannot be restored if the memory exception comes from an helper */
2408 gen_update_nip(ctx, ctx->nip - 4);
2409 tcg_gen_andi_tl(t0, EA, mask);
2410 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2411 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2412 t2 = tcg_const_i32(0);
2413 gen_helper_raise_exception_err(cpu_env, t1, t2);
2414 tcg_temp_free_i32(t1);
2415 tcg_temp_free_i32(t2);
2416 gen_set_label(l1);
2417 tcg_temp_free(t0);
2418 }
2419
2420 /*** Integer load ***/
2421 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2422 {
2423 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2424 }
2425
2426 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2427 {
2428 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2429 }
2430
2431 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2432 {
2433 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2434 if (unlikely(ctx->le_mode)) {
2435 tcg_gen_bswap16_tl(arg1, arg1);
2436 }
2437 }
2438
2439 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2440 {
2441 if (unlikely(ctx->le_mode)) {
2442 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2443 tcg_gen_bswap16_tl(arg1, arg1);
2444 tcg_gen_ext16s_tl(arg1, arg1);
2445 } else {
2446 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2447 }
2448 }
2449
2450 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2451 {
2452 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2453 if (unlikely(ctx->le_mode)) {
2454 tcg_gen_bswap32_tl(arg1, arg1);
2455 }
2456 }
2457
2458 #if defined(TARGET_PPC64)
2459 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2460 {
2461 if (unlikely(ctx->le_mode)) {
2462 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2463 tcg_gen_bswap32_tl(arg1, arg1);
2464 tcg_gen_ext32s_tl(arg1, arg1);
2465 } else
2466 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2467 }
2468 #endif
2469
2470 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2471 {
2472 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2473 if (unlikely(ctx->le_mode)) {
2474 tcg_gen_bswap64_i64(arg1, arg1);
2475 }
2476 }
2477
2478 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2479 {
2480 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2481 }
2482
2483 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2484 {
2485 if (unlikely(ctx->le_mode)) {
2486 TCGv t0 = tcg_temp_new();
2487 tcg_gen_ext16u_tl(t0, arg1);
2488 tcg_gen_bswap16_tl(t0, t0);
2489 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2490 tcg_temp_free(t0);
2491 } else {
2492 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2493 }
2494 }
2495
2496 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2497 {
2498 if (unlikely(ctx->le_mode)) {
2499 TCGv t0 = tcg_temp_new();
2500 tcg_gen_ext32u_tl(t0, arg1);
2501 tcg_gen_bswap32_tl(t0, t0);
2502 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2503 tcg_temp_free(t0);
2504 } else {
2505 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2506 }
2507 }
2508
2509 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2510 {
2511 if (unlikely(ctx->le_mode)) {
2512 TCGv_i64 t0 = tcg_temp_new_i64();
2513 tcg_gen_bswap64_i64(t0, arg1);
2514 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2515 tcg_temp_free_i64(t0);
2516 } else
2517 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2518 }
2519
2520 #define GEN_LD(name, ldop, opc, type) \
2521 static void glue(gen_, name)(DisasContext *ctx) \
2522 { \
2523 TCGv EA; \
2524 gen_set_access_type(ctx, ACCESS_INT); \
2525 EA = tcg_temp_new(); \
2526 gen_addr_imm_index(ctx, EA, 0); \
2527 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2528 tcg_temp_free(EA); \
2529 }
2530
2531 #define GEN_LDU(name, ldop, opc, type) \
2532 static void glue(gen_, name##u)(DisasContext *ctx) \
2533 { \
2534 TCGv EA; \
2535 if (unlikely(rA(ctx->opcode) == 0 || \
2536 rA(ctx->opcode) == rD(ctx->opcode))) { \
2537 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2538 return; \
2539 } \
2540 gen_set_access_type(ctx, ACCESS_INT); \
2541 EA = tcg_temp_new(); \
2542 if (type == PPC_64B) \
2543 gen_addr_imm_index(ctx, EA, 0x03); \
2544 else \
2545 gen_addr_imm_index(ctx, EA, 0); \
2546 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2547 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2548 tcg_temp_free(EA); \
2549 }
2550
2551 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2552 static void glue(gen_, name##ux)(DisasContext *ctx) \
2553 { \
2554 TCGv EA; \
2555 if (unlikely(rA(ctx->opcode) == 0 || \
2556 rA(ctx->opcode) == rD(ctx->opcode))) { \
2557 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2558 return; \
2559 } \
2560 gen_set_access_type(ctx, ACCESS_INT); \
2561 EA = tcg_temp_new(); \
2562 gen_addr_reg_index(ctx, EA); \
2563 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2564 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2565 tcg_temp_free(EA); \
2566 }
2567
2568 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2569 static void glue(gen_, name##x)(DisasContext *ctx) \
2570 { \
2571 TCGv EA; \
2572 gen_set_access_type(ctx, ACCESS_INT); \
2573 EA = tcg_temp_new(); \
2574 gen_addr_reg_index(ctx, EA); \
2575 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2576 tcg_temp_free(EA); \
2577 }
2578 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2579 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2580
2581 #define GEN_LDS(name, ldop, op, type) \
2582 GEN_LD(name, ldop, op | 0x20, type); \
2583 GEN_LDU(name, ldop, op | 0x21, type); \
2584 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2585 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2586
2587 /* lbz lbzu lbzux lbzx */
2588 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2589 /* lha lhau lhaux lhax */
2590 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2591 /* lhz lhzu lhzux lhzx */
2592 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2593 /* lwz lwzu lwzux lwzx */
2594 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2595 #if defined(TARGET_PPC64)
2596 /* lwaux */
2597 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2598 /* lwax */
2599 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2600 /* ldux */
2601 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2602 /* ldx */
2603 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2604
2605 static void gen_ld(DisasContext *ctx)
2606 {
2607 TCGv EA;
2608 if (Rc(ctx->opcode)) {
2609 if (unlikely(rA(ctx->opcode) == 0 ||
2610 rA(ctx->opcode) == rD(ctx->opcode))) {
2611 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2612 return;
2613 }
2614 }
2615 gen_set_access_type(ctx, ACCESS_INT);
2616 EA = tcg_temp_new();
2617 gen_addr_imm_index(ctx, EA, 0x03);
2618 if (ctx->opcode & 0x02) {
2619 /* lwa (lwau is undefined) */
2620 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2621 } else {
2622 /* ld - ldu */
2623 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2624 }
2625 if (Rc(ctx->opcode))
2626 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2627 tcg_temp_free(EA);
2628 }
2629
2630 /* lq */
2631 static void gen_lq(DisasContext *ctx)
2632 {
2633 #if defined(CONFIG_USER_ONLY)
2634 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2635 #else
2636 int ra, rd;
2637 TCGv EA;
2638
2639 /* Restore CPU state */
2640 if (unlikely(ctx->mem_idx == 0)) {
2641 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2642 return;
2643 }
2644 ra = rA(ctx->opcode);
2645 rd = rD(ctx->opcode);
2646 if (unlikely((rd & 1) || rd == ra)) {
2647 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2648 return;
2649 }
2650 if (unlikely(ctx->le_mode)) {
2651 /* Little-endian mode is not handled */
2652 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2653 return;
2654 }
2655 gen_set_access_type(ctx, ACCESS_INT);
2656 EA = tcg_temp_new();
2657 gen_addr_imm_index(ctx, EA, 0x0F);
2658 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2659 gen_addr_add(ctx, EA, EA, 8);
2660 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2661 tcg_temp_free(EA);
2662 #endif
2663 }
2664 #endif
2665
2666 /*** Integer store ***/
2667 #define GEN_ST(name, stop, opc, type) \
2668 static void glue(gen_, name)(DisasContext *ctx) \
2669 { \
2670 TCGv EA; \
2671 gen_set_access_type(ctx, ACCESS_INT); \
2672 EA = tcg_temp_new(); \
2673 gen_addr_imm_index(ctx, EA, 0); \
2674 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2675 tcg_temp_free(EA); \
2676 }
2677
2678 #define GEN_STU(name, stop, opc, type) \
2679 static void glue(gen_, stop##u)(DisasContext *ctx) \
2680 { \
2681 TCGv EA; \
2682 if (unlikely(rA(ctx->opcode) == 0)) { \
2683 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2684 return; \
2685 } \
2686 gen_set_access_type(ctx, ACCESS_INT); \
2687 EA = tcg_temp_new(); \
2688 if (type == PPC_64B) \
2689 gen_addr_imm_index(ctx, EA, 0x03); \
2690 else \
2691 gen_addr_imm_index(ctx, EA, 0); \
2692 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2693 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2694 tcg_temp_free(EA); \
2695 }
2696
2697 #define GEN_STUX(name, stop, opc2, opc3, type) \
2698 static void glue(gen_, name##ux)(DisasContext *ctx) \
2699 { \
2700 TCGv EA; \
2701 if (unlikely(rA(ctx->opcode) == 0)) { \
2702 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2703 return; \
2704 } \
2705 gen_set_access_type(ctx, ACCESS_INT); \
2706 EA = tcg_temp_new(); \
2707 gen_addr_reg_index(ctx, EA); \
2708 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2709 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2710 tcg_temp_free(EA); \
2711 }
2712
2713 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2714 static void glue(gen_, name##x)(DisasContext *ctx) \
2715 { \
2716 TCGv EA; \
2717 gen_set_access_type(ctx, ACCESS_INT); \
2718 EA = tcg_temp_new(); \
2719 gen_addr_reg_index(ctx, EA); \
2720 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2721 tcg_temp_free(EA); \
2722 }
2723 #define GEN_STX(name, stop, opc2, opc3, type) \
2724 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2725
2726 #define GEN_STS(name, stop, op, type) \
2727 GEN_ST(name, stop, op | 0x20, type); \
2728 GEN_STU(name, stop, op | 0x21, type); \
2729 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2730 GEN_STX(name, stop, 0x17, op | 0x00, type)
2731
2732 /* stb stbu stbux stbx */
2733 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2734 /* sth sthu sthux sthx */
2735 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2736 /* stw stwu stwux stwx */
2737 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2738 #if defined(TARGET_PPC64)
2739 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2740 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2741
2742 static void gen_std(DisasContext *ctx)
2743 {
2744 int rs;
2745 TCGv EA;
2746
2747 rs = rS(ctx->opcode);
2748 if ((ctx->opcode & 0x3) == 0x2) {
2749 #if defined(CONFIG_USER_ONLY)
2750 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2751 #else
2752 /* stq */
2753 if (unlikely(ctx->mem_idx == 0)) {
2754 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2755 return;
2756 }
2757 if (unlikely(rs & 1)) {
2758 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2759 return;
2760 }
2761 if (unlikely(ctx->le_mode)) {
2762 /* Little-endian mode is not handled */
2763 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2764 return;
2765 }
2766 gen_set_access_type(ctx, ACCESS_INT);
2767 EA = tcg_temp_new();
2768 gen_addr_imm_index(ctx, EA, 0x03);
2769 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2770 gen_addr_add(ctx, EA, EA, 8);
2771 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2772 tcg_temp_free(EA);
2773 #endif
2774 } else {
2775 /* std / stdu */
2776 if (Rc(ctx->opcode)) {
2777 if (unlikely(rA(ctx->opcode) == 0)) {
2778 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2779 return;
2780 }
2781 }
2782 gen_set_access_type(ctx, ACCESS_INT);
2783 EA = tcg_temp_new();
2784 gen_addr_imm_index(ctx, EA, 0x03);
2785 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2786 if (Rc(ctx->opcode))
2787 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2788 tcg_temp_free(EA);
2789 }
2790 }
2791 #endif
2792 /*** Integer load and store with byte reverse ***/
2793 /* lhbrx */
2794 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2795 {
2796 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2797 if (likely(!ctx->le_mode)) {
2798 tcg_gen_bswap16_tl(arg1, arg1);
2799 }
2800 }
2801 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2802
2803 /* lwbrx */
2804 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2805 {
2806 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2807 if (likely(!ctx->le_mode)) {
2808 tcg_gen_bswap32_tl(arg1, arg1);
2809 }
2810 }
2811 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2812
2813 #if defined(TARGET_PPC64)
2814 /* ldbrx */
2815 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2816 {
2817 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2818 if (likely(!ctx->le_mode)) {
2819 tcg_gen_bswap64_tl(arg1, arg1);
2820 }
2821 }
2822 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2823 #endif /* TARGET_PPC64 */
2824
2825 /* sthbrx */
2826 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2827 {
2828 if (likely(!ctx->le_mode)) {
2829 TCGv t0 = tcg_temp_new();
2830 tcg_gen_ext16u_tl(t0, arg1);
2831 tcg_gen_bswap16_tl(t0, t0);
2832 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2833 tcg_temp_free(t0);
2834 } else {
2835 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2836 }
2837 }
2838 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2839
2840 /* stwbrx */
2841 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2842 {
2843 if (likely(!ctx->le_mode)) {
2844 TCGv t0 = tcg_temp_new();
2845 tcg_gen_ext32u_tl(t0, arg1);
2846 tcg_gen_bswap32_tl(t0, t0);
2847 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2848 tcg_temp_free(t0);
2849 } else {
2850 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2851 }
2852 }
2853 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2854
2855 #if defined(TARGET_PPC64)
2856 /* stdbrx */
2857 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2858 {
2859 if (likely(!ctx->le_mode)) {
2860 TCGv t0 = tcg_temp_new();
2861 tcg_gen_bswap64_tl(t0, arg1);
2862 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2863 tcg_temp_free(t0);
2864 } else {
2865 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2866 }
2867 }
2868 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2869 #endif /* TARGET_PPC64 */
2870
2871 /*** Integer load and store multiple ***/
2872
2873 /* lmw */
2874 static void gen_lmw(DisasContext *ctx)
2875 {
2876 TCGv t0;
2877 TCGv_i32 t1;
2878 gen_set_access_type(ctx, ACCESS_INT);
2879 /* NIP cannot be restored if the memory exception comes from an helper */
2880 gen_update_nip(ctx, ctx->nip - 4);
2881 t0 = tcg_temp_new();
2882 t1 = tcg_const_i32(rD(ctx->opcode));
2883 gen_addr_imm_index(ctx, t0, 0);
2884 gen_helper_lmw(cpu_env, t0, t1);
2885 tcg_temp_free(t0);
2886 tcg_temp_free_i32(t1);
2887 }
2888
2889 /* stmw */
2890 static void gen_stmw(DisasContext *ctx)
2891 {
2892 TCGv t0;
2893 TCGv_i32 t1;
2894 gen_set_access_type(ctx, ACCESS_INT);
2895 /* NIP cannot be restored if the memory exception comes from an helper */
2896 gen_update_nip(ctx, ctx->nip - 4);
2897 t0 = tcg_temp_new();
2898 t1 = tcg_const_i32(rS(ctx->opcode));
2899 gen_addr_imm_index(ctx, t0, 0);
2900 gen_helper_stmw(cpu_env, t0, t1);
2901 tcg_temp_free(t0);
2902 tcg_temp_free_i32(t1);
2903 }
2904
2905 /*** Integer load and store strings ***/
2906
2907 /* lswi */
2908 /* PowerPC32 specification says we must generate an exception if
2909 * rA is in the range of registers to be loaded.
2910 * In an other hand, IBM says this is valid, but rA won't be loaded.
2911 * For now, I'll follow the spec...
2912 */
2913 static void gen_lswi(DisasContext *ctx)
2914 {
2915 TCGv t0;
2916 TCGv_i32 t1, t2;
2917 int nb = NB(ctx->opcode);
2918 int start = rD(ctx->opcode);
2919 int ra = rA(ctx->opcode);
2920 int nr;
2921
2922 if (nb == 0)
2923 nb = 32;
2924 nr = nb / 4;
2925 if (unlikely(((start + nr) > 32 &&
2926 start <= ra && (start + nr - 32) > ra) ||
2927 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2928 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2929 return;
2930 }
2931 gen_set_access_type(ctx, ACCESS_INT);
2932 /* NIP cannot be restored if the memory exception comes from an helper */
2933 gen_update_nip(ctx, ctx->nip - 4);
2934 t0 = tcg_temp_new();
2935 gen_addr_register(ctx, t0);
2936 t1 = tcg_const_i32(nb);
2937 t2 = tcg_const_i32(start);
2938 gen_helper_lsw(cpu_env, t0, t1, t2);
2939 tcg_temp_free(t0);
2940 tcg_temp_free_i32(t1);
2941 tcg_temp_free_i32(t2);
2942 }
2943
2944 /* lswx */
2945 static void gen_lswx(DisasContext *ctx)
2946 {
2947 TCGv t0;
2948 TCGv_i32 t1, t2, t3;
2949 gen_set_access_type(ctx, ACCESS_INT);
2950 /* NIP cannot be restored if the memory exception comes from an helper */
2951 gen_update_nip(ctx, ctx->nip - 4);
2952 t0 = tcg_temp_new();
2953 gen_addr_reg_index(ctx, t0);
2954 t1 = tcg_const_i32(rD(ctx->opcode));
2955 t2 = tcg_const_i32(rA(ctx->opcode));
2956 t3 = tcg_const_i32(rB(ctx->opcode));
2957 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2958 tcg_temp_free(t0);
2959 tcg_temp_free_i32(t1);
2960 tcg_temp_free_i32(t2);
2961 tcg_temp_free_i32(t3);
2962 }
2963
2964 /* stswi */
2965 static void gen_stswi(DisasContext *ctx)
2966 {
2967 TCGv t0;
2968 TCGv_i32 t1, t2;
2969 int nb = NB(ctx->opcode);
2970 gen_set_access_type(ctx, ACCESS_INT);
2971 /* NIP cannot be restored if the memory exception comes from an helper */
2972 gen_update_nip(ctx, ctx->nip - 4);
2973 t0 = tcg_temp_new();
2974 gen_addr_register(ctx, t0);
2975 if (nb == 0)
2976 nb = 32;
2977 t1 = tcg_const_i32(nb);
2978 t2 = tcg_const_i32(rS(ctx->opcode));
2979 gen_helper_stsw(cpu_env, t0, t1, t2);
2980 tcg_temp_free(t0);
2981 tcg_temp_free_i32(t1);
2982 tcg_temp_free_i32(t2);
2983 }
2984
2985 /* stswx */
2986 static void gen_stswx(DisasContext *ctx)
2987 {
2988 TCGv t0;
2989 TCGv_i32 t1, t2;
2990 gen_set_access_type(ctx, ACCESS_INT);
2991 /* NIP cannot be restored if the memory exception comes from an helper */
2992 gen_update_nip(ctx, ctx->nip - 4);
2993 t0 = tcg_temp_new();
2994 gen_addr_reg_index(ctx, t0);
2995 t1 = tcg_temp_new_i32();
2996 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2997 tcg_gen_andi_i32(t1, t1, 0x7F);
2998 t2 = tcg_const_i32(rS(ctx->opcode));
2999 gen_helper_stsw(cpu_env, t0, t1, t2);
3000 tcg_temp_free(t0);
3001 tcg_temp_free_i32(t1);
3002 tcg_temp_free_i32(t2);
3003 }
3004
3005 /*** Memory synchronisation ***/
3006 /* eieio */
3007 static void gen_eieio(DisasContext *ctx)
3008 {
3009 }
3010
3011 /* isync */
3012 static void gen_isync(DisasContext *ctx)
3013 {
3014 gen_stop_exception(ctx);
3015 }
3016
3017 /* lwarx */
3018 static void gen_lwarx(DisasContext *ctx)
3019 {
3020 TCGv t0;
3021 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3022 gen_set_access_type(ctx, ACCESS_RES);
3023 t0 = tcg_temp_local_new();
3024 gen_addr_reg_index(ctx, t0);
3025 gen_check_align(ctx, t0, 0x03);
3026 gen_qemu_ld32u(ctx, gpr, t0);
3027 tcg_gen_mov_tl(cpu_reserve, t0);
3028 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3029 tcg_temp_free(t0);
3030 }
3031
3032 #if defined(CONFIG_USER_ONLY)
3033 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3034 int reg, int size)
3035 {
3036 TCGv t0 = tcg_temp_new();
3037 uint32_t save_exception = ctx->exception;
3038
3039 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3040 tcg_gen_movi_tl(t0, (size << 5) | reg);
3041 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3042 tcg_temp_free(t0);
3043 gen_update_nip(ctx, ctx->nip-4);
3044 ctx->exception = POWERPC_EXCP_BRANCH;
3045 gen_exception(ctx, POWERPC_EXCP_STCX);
3046 ctx->exception = save_exception;
3047 }
3048 #endif
3049
3050 /* stwcx. */
3051 static void gen_stwcx_(DisasContext *ctx)
3052 {
3053 TCGv t0;
3054 gen_set_access_type(ctx, ACCESS_RES);
3055 t0 = tcg_temp_local_new();
3056 gen_addr_reg_index(ctx, t0);
3057 gen_check_align(ctx, t0, 0x03);
3058 #if defined(CONFIG_USER_ONLY)
3059 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3060 #else
3061 {
3062 int l1;
3063
3064 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3065 l1 = gen_new_label();
3066 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3067 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3068 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3069 gen_set_label(l1);
3070 tcg_gen_movi_tl(cpu_reserve, -1);
3071 }
3072 #endif
3073 tcg_temp_free(t0);
3074 }
3075
3076 #if defined(TARGET_PPC64)
3077 /* ldarx */
3078 static void gen_ldarx(DisasContext *ctx)
3079 {
3080 TCGv t0;
3081 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3082 gen_set_access_type(ctx, ACCESS_RES);
3083 t0 = tcg_temp_local_new();
3084 gen_addr_reg_index(ctx, t0);
3085 gen_check_align(ctx, t0, 0x07);
3086 gen_qemu_ld64(ctx, gpr, t0);
3087 tcg_gen_mov_tl(cpu_reserve, t0);
3088 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3089 tcg_temp_free(t0);
3090 }
3091
3092 /* stdcx. */
3093 static void gen_stdcx_(DisasContext *ctx)
3094 {
3095 TCGv t0;
3096 gen_set_access_type(ctx, ACCESS_RES);
3097 t0 = tcg_temp_local_new();
3098 gen_addr_reg_index(ctx, t0);
3099 gen_check_align(ctx, t0, 0x07);
3100 #if defined(CONFIG_USER_ONLY)
3101 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3102 #else
3103 {
3104 int l1;
3105 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3106 l1 = gen_new_label();
3107 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3108 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3109 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3110 gen_set_label(l1);
3111 tcg_gen_movi_tl(cpu_reserve, -1);
3112 }
3113 #endif
3114 tcg_temp_free(t0);
3115 }
3116 #endif /* defined(TARGET_PPC64) */
3117
3118 /* sync */
3119 static void gen_sync(DisasContext *ctx)
3120 {
3121 }
3122
3123 /* wait */
3124 static void gen_wait(DisasContext *ctx)
3125 {
3126 TCGv_i32 t0 = tcg_temp_new_i32();
3127 tcg_gen_st_i32(t0, cpu_env,
3128 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3129 tcg_temp_free_i32(t0);
3130 /* Stop translation, as the CPU is supposed to sleep from now */
3131 gen_exception_err(ctx, EXCP_HLT, 1);
3132 }
3133
3134 /*** Floating-point load ***/
3135 #define GEN_LDF(name, ldop, opc, type) \
3136 static void glue(gen_, name)(DisasContext *ctx) \
3137 { \
3138 TCGv EA; \
3139 if (unlikely(!ctx->fpu_enabled)) { \
3140 gen_exception(ctx, POWERPC_EXCP_FPU); \
3141 return; \
3142 } \
3143 gen_set_access_type(ctx, ACCESS_FLOAT); \
3144 EA = tcg_temp_new(); \
3145 gen_addr_imm_index(ctx, EA, 0); \
3146 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3147 tcg_temp_free(EA); \
3148 }
3149
3150 #define GEN_LDUF(name, ldop, opc, type) \
3151 static void glue(gen_, name##u)(DisasContext *ctx) \
3152 { \
3153 TCGv EA; \
3154 if (unlikely(!ctx->fpu_enabled)) { \
3155 gen_exception(ctx, POWERPC_EXCP_FPU); \
3156 return; \
3157 } \
3158 if (unlikely(rA(ctx->opcode) == 0)) { \
3159 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3160 return; \
3161 } \
3162 gen_set_access_type(ctx, ACCESS_FLOAT); \
3163 EA = tcg_temp_new(); \
3164 gen_addr_imm_index(ctx, EA, 0); \
3165 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3166 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3167 tcg_temp_free(EA); \
3168 }
3169
3170 #define GEN_LDUXF(name, ldop, opc, type) \
3171 static void glue(gen_, name##ux)(DisasContext *ctx) \
3172 { \
3173 TCGv EA; \
3174 if (unlikely(!ctx->fpu_enabled)) { \
3175 gen_exception(ctx, POWERPC_EXCP_FPU); \
3176 return; \
3177 } \
3178 if (unlikely(rA(ctx->opcode) == 0)) { \
3179 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3180 return; \
3181 } \
3182 gen_set_access_type(ctx, ACCESS_FLOAT); \
3183 EA = tcg_temp_new(); \
3184 gen_addr_reg_index(ctx, EA); \
3185 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3186 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3187 tcg_temp_free(EA); \
3188 }
3189
3190 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3191 static void glue(gen_, name##x)(DisasContext *ctx) \
3192 { \
3193 TCGv EA; \
3194 if (unlikely(!ctx->fpu_enabled)) { \
3195 gen_exception(ctx, POWERPC_EXCP_FPU); \
3196 return; \
3197 } \
3198 gen_set_access_type(ctx, ACCESS_FLOAT); \
3199 EA = tcg_temp_new(); \
3200 gen_addr_reg_index(ctx, EA); \
3201 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3202 tcg_temp_free(EA); \
3203 }
3204
3205 #define GEN_LDFS(name, ldop, op, type) \
3206 GEN_LDF(name, ldop, op | 0x20, type); \
3207 GEN_LDUF(name, ldop, op | 0x21, type); \
3208 GEN_LDUXF(name, ldop, op | 0x01, type); \
3209 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3210
3211 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3212 {
3213 TCGv t0 = tcg_temp_new();
3214 TCGv_i32 t1 = tcg_temp_new_i32();
3215 gen_qemu_ld32u(ctx, t0, arg2);
3216 tcg_gen_trunc_tl_i32(t1, t0);
3217 tcg_temp_free(t0);
3218 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3219 tcg_temp_free_i32(t1);
3220 }
3221
3222 /* lfd lfdu lfdux lfdx */
3223 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3224 /* lfs lfsu lfsux lfsx */
3225 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3226
3227 /*** Floating-point store ***/
3228 #define GEN_STF(name, stop, opc, type) \
3229 static void glue(gen_, name)(DisasContext *ctx) \
3230 { \
3231 TCGv EA; \
3232 if (unlikely(!ctx->fpu_enabled)) { \
3233 gen_exception(ctx, POWERPC_EXCP_FPU); \
3234 return; \
3235 } \
3236 gen_set_access_type(ctx, ACCESS_FLOAT); \
3237 EA = tcg_temp_new(); \
3238 gen_addr_imm_index(ctx, EA, 0); \
3239 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3240 tcg_temp_free(EA); \
3241 }
3242
3243 #define GEN_STUF(name, stop, opc, type) \
3244 static void glue(gen_, name##u)(DisasContext *ctx) \
3245 { \
3246 TCGv EA; \
3247 if (unlikely(!ctx->fpu_enabled)) { \
3248 gen_exception(ctx, POWERPC_EXCP_FPU); \
3249 return; \
3250 } \
3251 if (unlikely(rA(ctx->opcode) == 0)) { \
3252 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3253 return; \
3254 } \
3255 gen_set_access_type(ctx, ACCESS_FLOAT); \
3256 EA = tcg_temp_new(); \
3257 gen_addr_imm_index(ctx, EA, 0); \
3258 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3259 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3260 tcg_temp_free(EA); \
3261 }
3262
3263 #define GEN_STUXF(name, stop, opc, type) \
3264 static void glue(gen_, name##ux)(DisasContext *ctx) \
3265 { \
3266 TCGv EA; \
3267 if (unlikely(!ctx->fpu_enabled)) { \
3268 gen_exception(ctx, POWERPC_EXCP_FPU); \
3269 return; \
3270 } \
3271 if (unlikely(rA(ctx->opcode) == 0)) { \
3272 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3273 return; \
3274 } \
3275 gen_set_access_type(ctx, ACCESS_FLOAT); \
3276 EA = tcg_temp_new(); \
3277 gen_addr_reg_index(ctx, EA); \
3278 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3279 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3280 tcg_temp_free(EA); \
3281 }
3282
3283 #define GEN_STXF(name, stop, opc2, opc3, type) \
3284 static void glue(gen_, name##x)(DisasContext *ctx) \
3285 { \
3286 TCGv EA; \
3287 if (unlikely(!ctx->fpu_enabled)) { \
3288 gen_exception(ctx, POWERPC_EXCP_FPU); \
3289 return; \
3290 } \
3291 gen_set_access_type(ctx, ACCESS_FLOAT); \
3292 EA = tcg_temp_new(); \
3293 gen_addr_reg_index(ctx, EA); \
3294 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3295 tcg_temp_free(EA); \
3296 }
3297
3298 #define GEN_STFS(name, stop, op, type) \
3299 GEN_STF(name, stop, op | 0x20, type); \
3300 GEN_STUF(name, stop, op | 0x21, type); \
3301 GEN_STUXF(name, stop, op | 0x01, type); \
3302 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3303
3304 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3305 {
3306 TCGv_i32 t0 = tcg_temp_new_i32();
3307 TCGv t1 = tcg_temp_new();
3308 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3309 tcg_gen_extu_i32_tl(t1, t0);
3310 tcg_temp_free_i32(t0);
3311 gen_qemu_st32(ctx, t1, arg2);
3312 tcg_temp_free(t1);
3313 }
3314
3315 /* stfd stfdu stfdux stfdx */
3316 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3317 /* stfs stfsu stfsux stfsx */
3318 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3319
3320 /* Optional: */
3321 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3322 {
3323 TCGv t0 = tcg_temp_new();
3324 tcg_gen_trunc_i64_tl(t0, arg1),
3325 gen_qemu_st32(ctx, t0, arg2);
3326 tcg_temp_free(t0);
3327 }
3328 /* stfiwx */
3329 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3330
3331 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3332 {
3333 #if defined(TARGET_PPC64)
3334 if (ctx->has_cfar)
3335 tcg_gen_movi_tl(cpu_cfar, nip);
3336 #endif
3337 }
3338
3339 /*** Branch ***/
3340 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3341 {
3342 TranslationBlock *tb;
3343 tb = ctx->tb;
3344 if (NARROW_MODE(ctx)) {
3345 dest = (uint32_t) dest;
3346 }
3347 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3348 likely(!ctx->singlestep_enabled)) {
3349 tcg_gen_goto_tb(n);
3350 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3351 tcg_gen_exit_tb((tcg_target_long)tb + n);
3352 } else {
3353 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3354 if (unlikely(ctx->singlestep_enabled)) {
3355 if ((ctx->singlestep_enabled &
3356 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3357 (ctx->exception == POWERPC_EXCP_BRANCH ||
3358 ctx->exception == POWERPC_EXCP_TRACE)) {
3359 target_ulong tmp = ctx->nip;
3360 ctx->nip = dest;
3361 gen_exception(ctx, POWERPC_EXCP_TRACE);
3362 ctx->nip = tmp;
3363 }
3364 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3365 gen_debug_exception(ctx);
3366 }
3367 }
3368 tcg_gen_exit_tb(0);
3369 }
3370 }
3371
3372 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3373 {
3374 if (NARROW_MODE(ctx)) {
3375 nip = (uint32_t)nip;
3376 }
3377 tcg_gen_movi_tl(cpu_lr, nip);
3378 }
3379
3380 /* b ba bl bla */
3381 static void gen_b(DisasContext *ctx)
3382 {
3383 target_ulong li, target;
3384
3385 ctx->exception = POWERPC_EXCP_BRANCH;
3386 /* sign extend LI */
3387 li = LI(ctx->opcode);
3388 li = (li ^ 0x02000000) - 0x02000000;
3389 if (likely(AA(ctx->opcode) == 0)) {
3390 target = ctx->nip + li - 4;
3391 } else {
3392 target = li;
3393 }
3394 if (LK(ctx->opcode)) {
3395 gen_setlr(ctx, ctx->nip);
3396 }
3397 gen_update_cfar(ctx, ctx->nip);
3398 gen_goto_tb(ctx, 0, target);
3399 }
3400
3401 #define BCOND_IM 0
3402 #define BCOND_LR 1
3403 #define BCOND_CTR 2
3404
3405 static inline void gen_bcond(DisasContext *ctx, int type)
3406 {
3407 uint32_t bo = BO(ctx->opcode);
3408 int l1;
3409 TCGv target;
3410
3411 ctx->exception = POWERPC_EXCP_BRANCH;
3412 if (type == BCOND_LR || type == BCOND_CTR) {
3413 target = tcg_temp_local_new();
3414 if (type == BCOND_CTR)
3415 tcg_gen_mov_tl(target, cpu_ctr);
3416 else
3417 tcg_gen_mov_tl(target, cpu_lr);
3418 } else {
3419 TCGV_UNUSED(target);
3420 }
3421 if (LK(ctx->opcode))
3422 gen_setlr(ctx, ctx->nip);
3423 l1 = gen_new_label();
3424 if ((bo & 0x4) == 0) {
3425 /* Decrement and test CTR */
3426 TCGv temp = tcg_temp_new();
3427 if (unlikely(type == BCOND_CTR)) {
3428 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3429 return;
3430 }
3431 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3432 if (NARROW_MODE(ctx)) {
3433 tcg_gen_ext32u_tl(temp, cpu_ctr);
3434 } else {
3435 tcg_gen_mov_tl(temp, cpu_ctr);
3436 }
3437 if (bo & 0x2) {
3438 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3439 } else {
3440 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3441 }
3442 tcg_temp_free(temp);
3443 }
3444 if ((bo & 0x10) == 0) {
3445 /* Test CR */
3446 uint32_t bi = BI(ctx->opcode);
3447 uint32_t mask = 1 << (3 - (bi & 0x03));
3448 TCGv_i32 temp = tcg_temp_new_i32();
3449
3450 if (bo & 0x8) {
3451 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3452 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3453 } else {
3454 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3455 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3456 }
3457 tcg_temp_free_i32(temp);
3458 }
3459 gen_update_cfar(ctx, ctx->nip);
3460 if (type == BCOND_IM) {
3461 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3462 if (likely(AA(ctx->opcode) == 0)) {
3463 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3464 } else {
3465 gen_goto_tb(ctx, 0, li);
3466 }
3467 gen_set_label(l1);
3468 gen_goto_tb(ctx, 1, ctx->nip);
3469 } else {
3470 if (NARROW_MODE(ctx)) {
3471 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3472 } else {
3473 tcg_gen_andi_tl(cpu_nip, target, ~3);
3474 }
3475 tcg_gen_exit_tb(0);
3476 gen_set_label(l1);
3477 gen_update_nip(ctx, ctx->nip);
3478 tcg_gen_exit_tb(0);
3479 }
3480 }
3481
3482 static void gen_bc(DisasContext *ctx)
3483 {
3484 gen_bcond(ctx, BCOND_IM);
3485 }
3486
3487 static void gen_bcctr(DisasContext *ctx)
3488 {
3489 gen_bcond(ctx, BCOND_CTR);
3490 }
3491
3492 static void gen_bclr(DisasContext *ctx)
3493 {
3494 gen_bcond(ctx, BCOND_LR);
3495 }
3496
3497 /*** Condition register logical ***/
3498 #define GEN_CRLOGIC(name, tcg_op, opc) \
3499 static void glue(gen_, name)(DisasContext *ctx) \
3500 { \
3501 uint8_t bitmask; \
3502 int sh; \
3503 TCGv_i32 t0, t1; \
3504 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3505 t0 = tcg_temp_new_i32(); \
3506 if (sh > 0) \
3507 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3508 else if (sh < 0) \
3509 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3510 else \
3511 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3512 t1 = tcg_temp_new_i32(); \
3513 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3514 if (sh > 0) \
3515 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3516 else if (sh < 0) \
3517 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3518 else \
3519 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3520 tcg_op(t0, t0, t1); \
3521 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3522 tcg_gen_andi_i32(t0, t0, bitmask); \
3523 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3524 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3525 tcg_temp_free_i32(t0); \
3526 tcg_temp_free_i32(t1); \
3527 }
3528
3529 /* crand */
3530 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3531 /* crandc */
3532 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3533 /* creqv */
3534 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3535 /* crnand */
3536 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3537 /* crnor */
3538 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3539 /* cror */
3540 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3541 /* crorc */
3542 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3543 /* crxor */
3544 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3545
3546 /* mcrf */
3547 static void gen_mcrf(DisasContext *ctx)
3548 {
3549 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3550 }
3551
3552 /*** System linkage ***/
3553
3554 /* rfi (mem_idx only) */
3555 static void gen_rfi(DisasContext *ctx)
3556 {
3557 #if defined(CONFIG_USER_ONLY)
3558 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3559 #else
3560 /* Restore CPU state */
3561 if (unlikely(!ctx->mem_idx)) {
3562 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3563 return;
3564 }
3565 gen_update_cfar(ctx, ctx->nip);
3566 gen_helper_rfi(cpu_env);
3567 gen_sync_exception(ctx);
3568 #endif
3569 }
3570
3571 #if defined(TARGET_PPC64)
3572 static void gen_rfid(DisasContext *ctx)
3573 {
3574 #if defined(CONFIG_USER_ONLY)
3575 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3576 #else
3577 /* Restore CPU state */
3578 if (unlikely(!ctx->mem_idx)) {
3579 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3580 return;
3581 }
3582 gen_update_cfar(ctx, ctx->nip);
3583 gen_helper_rfid(cpu_env);
3584 gen_sync_exception(ctx);
3585 #endif
3586 }
3587
3588 static void gen_hrfid(DisasContext *ctx)
3589 {
3590 #if defined(CONFIG_USER_ONLY)
3591 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3592 #else
3593 /* Restore CPU state */
3594 if (unlikely(ctx->mem_idx <= 1)) {
3595 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3596 return;
3597 }
3598 gen_helper_hrfid(cpu_env);
3599 gen_sync_exception(ctx);
3600 #endif
3601 }
3602 #endif
3603
3604 /* sc */
3605 #if defined(CONFIG_USER_ONLY)
3606 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3607 #else
3608 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3609 #endif
3610 static void gen_sc(DisasContext *ctx)
3611 {
3612 uint32_t lev;
3613
3614 lev = (ctx->opcode >> 5) & 0x7F;
3615 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3616 }
3617
3618 /*** Trap ***/
3619
3620 /* tw */
3621 static void gen_tw(DisasContext *ctx)
3622 {
3623 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3624 /* Update the nip since this might generate a trap exception */
3625 gen_update_nip(ctx, ctx->nip);
3626 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3627 t0);
3628 tcg_temp_free_i32(t0);
3629 }
3630
3631 /* twi */
3632 static void gen_twi(DisasContext *ctx)
3633 {
3634 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3635 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3636 /* Update the nip since this might generate a trap exception */
3637 gen_update_nip(ctx, ctx->nip);
3638 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3639 tcg_temp_free(t0);
3640 tcg_temp_free_i32(t1);
3641 }
3642
3643 #if defined(TARGET_PPC64)
3644 /* td */
3645 static void gen_td(DisasContext *ctx)
3646 {
3647 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3648 /* Update the nip since this might generate a trap exception */
3649 gen_update_nip(ctx, ctx->nip);
3650 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3651 t0);
3652 tcg_temp_free_i32(t0);
3653 }
3654
3655 /* tdi */
3656 static void gen_tdi(DisasContext *ctx)
3657 {
3658 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3659 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3660 /* Update the nip since this might generate a trap exception */
3661 gen_update_nip(ctx, ctx->nip);
3662 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3663 tcg_temp_free(t0);
3664 tcg_temp_free_i32(t1);
3665 }
3666 #endif
3667
3668 /*** Processor control ***/
3669
3670 static void gen_read_xer(TCGv dst)
3671 {
3672 TCGv t0 = tcg_temp_new();
3673 TCGv t1 = tcg_temp_new();
3674 TCGv t2 = tcg_temp_new();
3675 tcg_gen_mov_tl(dst, cpu_xer);
3676 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3677 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3678 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3679 tcg_gen_or_tl(t0, t0, t1);
3680 tcg_gen_or_tl(dst, dst, t2);
3681 tcg_gen_or_tl(dst, dst, t0);
3682 tcg_temp_free(t0);
3683 tcg_temp_free(t1);
3684 tcg_temp_free(t2);
3685 }
3686
3687 static void gen_write_xer(TCGv src)
3688 {
3689 tcg_gen_andi_tl(cpu_xer, src,
3690 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3691 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3692 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3693 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3694 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3695 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3696 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3697 }
3698
3699 /* mcrxr */
3700 static void gen_mcrxr(DisasContext *ctx)
3701 {
3702 TCGv_i32 t0 = tcg_temp_new_i32();
3703 TCGv_i32 t1 = tcg_temp_new_i32();
3704 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3705
3706 tcg_gen_trunc_tl_i32(t0, cpu_so);
3707 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3708 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3709 tcg_gen_shri_i32(t0, t0, 2);
3710 tcg_gen_shri_i32(t1, t1, 1);
3711 tcg_gen_or_i32(dst, dst, t0);
3712 tcg_gen_or_i32(dst, dst, t1);
3713 tcg_temp_free_i32(t0);
3714 tcg_temp_free_i32(t1);
3715
3716 tcg_gen_movi_tl(cpu_so, 0);
3717 tcg_gen_movi_tl(cpu_ov, 0);
3718 tcg_gen_movi_tl(cpu_ca, 0);
3719 }
3720
3721 /* mfcr mfocrf */
3722 static void gen_mfcr(DisasContext *ctx)
3723 {
3724 uint32_t crm, crn;
3725
3726 if (likely(ctx->opcode & 0x00100000)) {
3727 crm = CRM(ctx->opcode);
3728 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3729 crn = ctz32 (crm);
3730 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3731 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3732 cpu_gpr[rD(ctx->opcode)], crn * 4);
3733 }
3734 } else {
3735 TCGv_i32 t0 = tcg_temp_new_i32();
3736 tcg_gen_mov_i32(t0, cpu_crf[0]);
3737 tcg_gen_shli_i32(t0, t0, 4);
3738 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3739 tcg_gen_shli_i32(t0, t0, 4);
3740 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3741 tcg_gen_shli_i32(t0, t0, 4);
3742 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3743 tcg_gen_shli_i32(t0, t0, 4);
3744 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3745 tcg_gen_shli_i32(t0, t0, 4);
3746 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3747 tcg_gen_shli_i32(t0, t0, 4);
3748 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3749 tcg_gen_shli_i32(t0, t0, 4);
3750 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3751 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3752 tcg_temp_free_i32(t0);
3753 }
3754 }
3755
3756 /* mfmsr */
3757 static void gen_mfmsr(DisasContext *ctx)
3758 {
3759 #if defined(CONFIG_USER_ONLY)
3760 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3761 #else
3762 if (unlikely(!ctx->mem_idx)) {
3763 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3764 return;
3765 }
3766 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3767 #endif
3768 }
3769
3770 static void spr_noaccess(void *opaque, int gprn, int sprn)
3771 {
3772 #if 0
3773 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3774 printf("ERROR: try to access SPR %d !\n", sprn);
3775 #endif
3776 }
3777 #define SPR_NOACCESS (&spr_noaccess)
3778
3779 /* mfspr */
3780 static inline void gen_op_mfspr(DisasContext *ctx)
3781 {
3782 void (*read_cb)(void *opaque, int gprn, int sprn);
3783 uint32_t sprn = SPR(ctx->opcode);
3784
3785 #if !defined(CONFIG_USER_ONLY)
3786 if (ctx->mem_idx == 2)
3787 read_cb = ctx->spr_cb[sprn].hea_read;
3788 else if (ctx->mem_idx)
3789 read_cb = ctx->spr_cb[sprn].oea_read;
3790 else
3791 #endif
3792 read_cb = ctx->spr_cb[sprn].uea_read;
3793 if (likely(read_cb != NULL)) {
3794 if (likely(read_cb != SPR_NOACCESS)) {
3795 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3796 } else {
3797 /* Privilege exception */
3798 /* This is a hack to avoid warnings when running Linux:
3799 * this OS breaks the PowerPC virtualisation model,
3800 * allowing userland application to read the PVR
3801 */
3802 if (sprn != SPR_PVR) {
3803 qemu_log("Trying to read privileged spr %d %03x at "
3804 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3805 printf("Trying to read privileged spr %d %03x at "
3806 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3807 }
3808 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3809 }
3810 } else {
3811 /* Not defined */
3812 qemu_log("Trying to read invalid spr %d %03x at "
3813 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3814 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3815 sprn, sprn, ctx->nip);
3816 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3817 }
3818 }
3819
3820 static void gen_mfspr(DisasContext *ctx)
3821 {
3822 gen_op_mfspr(ctx);
3823 }
3824
3825 /* mftb */
3826 static void gen_mftb(DisasContext *ctx)
3827 {
3828 gen_op_mfspr(ctx);
3829 }
3830
3831 /* mtcrf mtocrf*/
3832 static void gen_mtcrf(DisasContext *ctx)
3833 {
3834 uint32_t crm, crn;
3835
3836 crm = CRM(ctx->opcode);
3837 if (likely((ctx->opcode & 0x00100000))) {
3838 if (crm && ((crm & (crm - 1)) == 0)) {
3839 TCGv_i32 temp = tcg_temp_new_i32();
3840 crn = ctz32 (crm);
3841 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3842 tcg_gen_shri_i32(temp, temp, crn * 4);
3843 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3844 tcg_temp_free_i32(temp);
3845 }
3846 } else {
3847 TCGv_i32 temp = tcg_temp_new_i32();
3848 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3849 for (crn = 0 ; crn < 8 ; crn++) {
3850 if (crm & (1 << crn)) {
3851 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3852 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3853 }
3854 }
3855 tcg_temp_free_i32(temp);
3856 }
3857 }
3858
3859 /* mtmsr */
3860 #if defined(TARGET_PPC64)
3861 static void gen_mtmsrd(DisasContext *ctx)
3862 {
3863 #if defined(CONFIG_USER_ONLY)
3864 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3865 #else
3866 if (unlikely(!ctx->mem_idx)) {
3867 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3868 return;
3869 }
3870 if (ctx->opcode & 0x00010000) {
3871 /* Special form that does not need any synchronisation */
3872 TCGv t0 = tcg_temp_new();
3873 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3874 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3875 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3876 tcg_temp_free(t0);
3877 } else {
3878 /* XXX: we need to update nip before the store
3879 * if we enter power saving mode, we will exit the loop
3880 * directly from ppc_store_msr
3881 */
3882 gen_update_nip(ctx, ctx->nip);
3883 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3884 /* Must stop the translation as machine state (may have) changed */
3885 /* Note that mtmsr is not always defined as context-synchronizing */
3886 gen_stop_exception(ctx);
3887 }
3888 #endif
3889 }
3890 #endif
3891
3892 static void gen_mtmsr(DisasContext *ctx)
3893 {
3894 #if defined(CONFIG_USER_ONLY)
3895 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3896 #else
3897 if (unlikely(!ctx->mem_idx)) {
3898 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3899 return;
3900 }
3901 if (ctx->opcode & 0x00010000) {
3902 /* Special form that does not need any synchronisation */
3903 TCGv t0 = tcg_temp_new();
3904 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3905 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3906 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3907 tcg_temp_free(t0);
3908 } else {
3909 TCGv msr = tcg_temp_new();
3910
3911 /* XXX: we need to update nip before the store
3912 * if we enter power saving mode, we will exit the loop
3913 * directly from ppc_store_msr
3914 */
3915 gen_update_nip(ctx, ctx->nip);
3916 #if defined(TARGET_PPC64)
3917 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3918 #else
3919 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3920 #endif
3921 gen_helper_store_msr(cpu_env, msr);
3922 /* Must stop the translation as machine state (may have) changed */
3923 /* Note that mtmsr is not always defined as context-synchronizing */
3924 gen_stop_exception(ctx);
3925 }
3926 #endif
3927 }
3928
3929 /* mtspr */
3930 static void gen_mtspr(DisasContext *ctx)
3931 {
3932 void (*write_cb)(void *opaque, int sprn, int gprn);
3933 uint32_t sprn = SPR(ctx->opcode);
3934
3935 #if !defined(CONFIG_USER_ONLY)
3936 if (ctx->mem_idx == 2)
3937 write_cb = ctx->spr_cb[sprn].hea_write;
3938 else if (ctx->mem_idx)
3939 write_cb = ctx->spr_cb[sprn].oea_write;
3940 else
3941 #endif
3942 write_cb = ctx->spr_cb[sprn].uea_write;
3943 if (likely(write_cb != NULL)) {
3944 if (likely(write_cb != SPR_NOACCESS)) {
3945 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3946 } else {
3947 /* Privilege exception */
3948 qemu_log("Trying to write privileged spr %d %03x at "
3949 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3950 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
3951 "\n", sprn, sprn, ctx->nip);
3952 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3953 }
3954 } else {
3955 /* Not defined */
3956 qemu_log("Trying to write invalid spr %d %03x at "
3957 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3958 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
3959 sprn, sprn, ctx->nip);
3960 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3961 }
3962 }
3963
3964 /*** Cache management ***/
3965
3966 /* dcbf */
3967 static void gen_dcbf(DisasContext *ctx)
3968 {
3969 /* XXX: specification says this is treated as a load by the MMU */
3970 TCGv t0;
3971 gen_set_access_type(ctx, ACCESS_CACHE);
3972 t0 = tcg_temp_new();
3973 gen_addr_reg_index(ctx, t0);
3974 gen_qemu_ld8u(ctx, t0, t0);
3975 tcg_temp_free(t0);
3976 }
3977
3978 /* dcbi (Supervisor only) */
3979 static void gen_dcbi(DisasContext *ctx)
3980 {
3981 #if defined(CONFIG_USER_ONLY)
3982 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3983 #else
3984 TCGv EA, val;
3985 if (unlikely(!ctx->mem_idx)) {
3986 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3987 return;
3988 }
3989 EA = tcg_temp_new();
3990 gen_set_access_type(ctx, ACCESS_CACHE);
3991 gen_addr_reg_index(ctx, EA);
3992 val = tcg_temp_new();
3993 /* XXX: specification says this should be treated as a store by the MMU */
3994 gen_qemu_ld8u(ctx, val, EA);
3995 gen_qemu_st8(ctx, val, EA);
3996 tcg_temp_free(val);
3997 tcg_temp_free(EA);
3998 #endif
3999 }
4000
4001 /* dcdst */
4002 static void gen_dcbst(DisasContext *ctx)
4003 {
4004 /* XXX: specification say this is treated as a load by the MMU */
4005 TCGv t0;
4006 gen_set_access_type(ctx, ACCESS_CACHE);
4007 t0 = tcg_temp_new();
4008 gen_addr_reg_index(ctx, t0);
4009 gen_qemu_ld8u(ctx, t0, t0);
4010 tcg_temp_free(t0);
4011 }
4012
4013 /* dcbt */
4014 static void gen_dcbt(DisasContext *ctx)
4015 {
4016 /* interpreted as no-op */
4017 /* XXX: specification say this is treated as a load by the MMU
4018 * but does not generate any exception
4019 */
4020 }
4021
4022 /* dcbtst */
4023 static void gen_dcbtst(DisasContext *ctx)
4024 {
4025 /* interpreted as no-op */
4026 /* XXX: specification say this is treated as a load by the MMU
4027 * but does not generate any exception
4028 */
4029 }
4030
4031 /* dcbz */
4032 static void gen_dcbz(DisasContext *ctx)
4033 {
4034 TCGv tcgv_addr;
4035 TCGv_i32 tcgv_is_dcbzl;
4036 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4037
4038 gen_set_access_type(ctx, ACCESS_CACHE);
4039 /* NIP cannot be restored if the memory exception comes from an helper */
4040 gen_update_nip(ctx, ctx->nip - 4);
4041 tcgv_addr = tcg_temp_new();
4042 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4043
4044 gen_addr_reg_index(ctx, tcgv_addr);
4045 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4046
4047 tcg_temp_free(tcgv_addr);
4048 tcg_temp_free_i32(tcgv_is_dcbzl);
4049 }
4050
4051 /* dst / dstt */
4052 static void gen_dst(DisasContext *ctx)
4053 {
4054 if (rA(ctx->opcode) == 0) {
4055 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4056 } else {
4057 /* interpreted as no-op */
4058 }
4059 }
4060
4061 /* dstst /dststt */
4062 static void gen_dstst(DisasContext *ctx)
4063 {
4064 if (rA(ctx->opcode) == 0) {
4065 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4066 } else {
4067 /* interpreted as no-op */
4068 }
4069
4070 }
4071
4072 /* dss / dssall */
4073 static void gen_dss(DisasContext *ctx)
4074 {
4075 /* interpreted as no-op */
4076 }
4077
4078 /* icbi */
4079 static void gen_icbi(DisasContext *ctx)
4080 {
4081 TCGv t0;
4082 gen_set_access_type(ctx, ACCESS_CACHE);
4083 /* NIP cannot be restored if the memory exception comes from an helper */
4084 gen_update_nip(ctx, ctx->nip - 4);
4085 t0 = tcg_temp_new();
4086 gen_addr_reg_index(ctx, t0);
4087 gen_helper_icbi(cpu_env, t0);
4088 tcg_temp_free(t0);
4089 }
4090
4091 /* Optional: */
4092 /* dcba */
4093 static void gen_dcba(DisasContext *ctx)
4094 {
4095 /* interpreted as no-op */
4096 /* XXX: specification say this is treated as a store by the MMU
4097 * but does not generate any exception
4098 */
4099 }
4100
4101 /*** Segment register manipulation ***/
4102 /* Supervisor only: */
4103
4104 /* mfsr */
4105 static void gen_mfsr(DisasContext *ctx)
4106 {
4107 #if defined(CONFIG_USER_ONLY)
4108 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4109 #else
4110 TCGv t0;
4111 if (unlikely(!ctx->mem_idx)) {
4112 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4113 return;
4114 }
4115 t0 = tcg_const_tl(SR(ctx->opcode));
4116 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4117 tcg_temp_free(t0);
4118 #endif
4119 }
4120
4121 /* mfsrin */
4122 static void gen_mfsrin(DisasContext *ctx)
4123 {
4124 #if defined(CONFIG_USER_ONLY)
4125 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4126 #else
4127 TCGv t0;
4128 if (unlikely(!ctx->mem_idx)) {
4129 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4130 return;
4131 }
4132 t0 = tcg_temp_new();
4133 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4134 tcg_gen_andi_tl(t0, t0, 0xF);
4135 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4136 tcg_temp_free(t0);
4137 #endif
4138 }
4139
4140 /* mtsr */
4141 static void gen_mtsr(DisasContext *ctx)
4142 {
4143 #if defined(CONFIG_USER_ONLY)
4144 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4145 #else
4146 TCGv t0;
4147 if (unlikely(!ctx->mem_idx)) {
4148 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4149 return;
4150 }
4151 t0 = tcg_const_tl(SR(ctx->opcode));
4152 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4153 tcg_temp_free(t0);
4154 #endif
4155 }
4156
4157 /* mtsrin */
4158 static void gen_mtsrin(DisasContext *ctx)
4159 {
4160 #if defined(CONFIG_USER_ONLY)
4161 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4162 #else
4163 TCGv t0;
4164 if (unlikely(!ctx->mem_idx)) {
4165 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4166 return;
4167 }
4168 t0 = tcg_temp_new();
4169 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4170 tcg_gen_andi_tl(t0, t0, 0xF);
4171 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4172 tcg_temp_free(t0);
4173 #endif
4174 }
4175
4176 #if defined(TARGET_PPC64)
4177 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4178
4179 /* mfsr */
4180 static void gen_mfsr_64b(DisasContext *ctx)
4181 {
4182 #if defined(CONFIG_USER_ONLY)
4183 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4184 #else
4185 TCGv t0;
4186 if (unlikely(!ctx->mem_idx)) {
4187 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4188 return;
4189 }
4190 t0 = tcg_const_tl(SR(ctx->opcode));
4191 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4192 tcg_temp_free(t0);
4193 #endif
4194 }
4195
4196 /* mfsrin */
4197 static void gen_mfsrin_64b(DisasContext *ctx)
4198 {
4199 #if defined(CONFIG_USER_ONLY)
4200 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4201 #else
4202 TCGv t0;
4203 if (unlikely(!ctx->mem_idx)) {
4204 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4205 return;
4206 }
4207 t0 = tcg_temp_new();
4208 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4209 tcg_gen_andi_tl(t0, t0, 0xF);
4210 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4211 tcg_temp_free(t0);
4212 #endif
4213 }
4214
4215 /* mtsr */
4216 static void gen_mtsr_64b(DisasContext *ctx)
4217 {
4218 #if defined(CONFIG_USER_ONLY)
4219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4220 #else
4221 TCGv t0;
4222 if (unlikely(!ctx->mem_idx)) {
4223 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4224 return;
4225 }
4226 t0 = tcg_const_tl(SR(ctx->opcode));
4227 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4228 tcg_temp_free(t0);
4229 #endif
4230 }
4231
4232 /* mtsrin */
4233 static void gen_mtsrin_64b(DisasContext *ctx)
4234 {
4235 #if defined(CONFIG_USER_ONLY)
4236 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4237 #else
4238 TCGv t0;
4239 if (unlikely(!ctx->mem_idx)) {
4240 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4241 return;
4242 }
4243 t0 = tcg_temp_new();
4244 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4245 tcg_gen_andi_tl(t0, t0, 0xF);
4246 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4247 tcg_temp_free(t0);
4248 #endif
4249 }
4250
4251 /* slbmte */
4252 static void gen_slbmte(DisasContext *ctx)
4253 {
4254 #if defined(CONFIG_USER_ONLY)
4255 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4256 #else
4257 if (unlikely(!ctx->mem_idx)) {
4258 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4259 return;
4260 }
4261 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4262 cpu_gpr[rS(ctx->opcode)]);
4263 #endif
4264 }
4265
4266 static void gen_slbmfee(DisasContext *ctx)
4267 {
4268 #if defined(CONFIG_USER_ONLY)
4269 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4270 #else
4271 if (unlikely(!ctx->mem_idx)) {
4272 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4273 return;
4274 }
4275 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4276 cpu_gpr[rB(ctx->opcode)]);
4277 #endif
4278 }
4279
4280 static void gen_slbmfev(DisasContext *ctx)
4281 {
4282 #if defined(CONFIG_USER_ONLY)
4283 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4284 #else
4285 if (unlikely(!ctx->mem_idx)) {
4286 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4287 return;
4288 }
4289 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4290 cpu_gpr[rB(ctx->opcode)]);
4291 #endif
4292 }
4293 #endif /* defined(TARGET_PPC64) */
4294
4295 /*** Lookaside buffer management ***/
4296 /* Optional & mem_idx only: */
4297
4298 /* tlbia */
4299 static void gen_tlbia(DisasContext *ctx)
4300 {
4301 #if defined(CONFIG_USER_ONLY)
4302 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4303 #else
4304 if (unlikely(!ctx->mem_idx)) {
4305 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4306 return;
4307 }
4308 gen_helper_tlbia(cpu_env);
4309 #endif
4310 }
4311
4312 /* tlbiel */
4313 static void gen_tlbiel(DisasContext *ctx)
4314 {
4315 #if defined(CONFIG_USER_ONLY)
4316 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4317 #else
4318 if (unlikely(!ctx->mem_idx)) {
4319 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4320 return;
4321 }
4322 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4323 #endif
4324 }
4325
4326 /* tlbie */
4327 static void gen_tlbie(DisasContext *ctx)
4328 {
4329 #if defined(CONFIG_USER_ONLY)
4330 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4331 #else
4332 if (unlikely(!ctx->mem_idx)) {
4333 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4334 return;
4335 }
4336 #if defined(TARGET_PPC64)
4337 if (!ctx->sf_mode) {
4338 TCGv t0 = tcg_temp_new();
4339 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4340 gen_helper_tlbie(cpu_env, t0);
4341 tcg_temp_free(t0);
4342 } else
4343 #endif
4344 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4345 #endif
4346 }
4347
4348 /* tlbsync */
4349 static void gen_tlbsync(DisasContext *ctx)
4350 {
4351 #if defined(CONFIG_USER_ONLY)
4352 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4353 #else
4354 if (unlikely(!ctx->mem_idx)) {
4355 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4356 return;
4357 }
4358 /* This has no effect: it should ensure that all previous
4359 * tlbie have completed
4360 */
4361 gen_stop_exception(ctx);
4362 #endif
4363 }
4364
4365 #if defined(TARGET_PPC64)
4366 /* slbia */
4367 static void gen_slbia(DisasContext *ctx)
4368 {
4369 #if defined(CONFIG_USER_ONLY)
4370 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4371 #else
4372 if (unlikely(!ctx->mem_idx)) {
4373 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4374 return;
4375 }
4376 gen_helper_slbia(cpu_env);
4377 #endif
4378 }
4379
4380 /* slbie */
4381 static void gen_slbie(DisasContext *ctx)
4382 {
4383 #if defined(CONFIG_USER_ONLY)
4384 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4385 #else
4386 if (unlikely(!ctx->mem_idx)) {
4387 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4388 return;
4389 }
4390 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4391 #endif
4392 }
4393 #endif
4394
4395 /*** External control ***/
4396 /* Optional: */
4397
4398 /* eciwx */
4399 static void gen_eciwx(DisasContext *ctx)
4400 {
4401 TCGv t0;
4402 /* Should check EAR[E] ! */
4403 gen_set_access_type(ctx, ACCESS_EXT);
4404 t0 = tcg_temp_new();
4405 gen_addr_reg_index(ctx, t0);
4406 gen_check_align(ctx, t0, 0x03);
4407 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4408 tcg_temp_free(t0);
4409 }
4410
4411 /* ecowx */
4412 static void gen_ecowx(DisasContext *ctx)
4413 {
4414 TCGv t0;
4415 /* Should check EAR[E] ! */
4416 gen_set_access_type(ctx, ACCESS_EXT);
4417 t0 = tcg_temp_new();
4418 gen_addr_reg_index(ctx, t0);
4419 gen_check_align(ctx, t0, 0x03);
4420 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4421 tcg_temp_free(t0);
4422 }
4423
4424 /* PowerPC 601 specific instructions */
4425
4426 /* abs - abs. */
4427 static void gen_abs(DisasContext *ctx)
4428 {
4429 int l1 = gen_new_label();
4430 int l2 = gen_new_label();
4431 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4432 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4433 tcg_gen_br(l2);
4434 gen_set_label(l1);
4435 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4436 gen_set_label(l2);
4437 if (unlikely(Rc(ctx->opcode) != 0))
4438 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4439 }
4440
4441 /* abso - abso. */
4442 static void gen_abso(DisasContext *ctx)
4443 {
4444 int l1 = gen_new_label();
4445 int l2 = gen_new_label();
4446 int l3 = gen_new_label();
4447 /* Start with XER OV disabled, the most likely case */
4448 tcg_gen_movi_tl(cpu_ov, 0);
4449 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4450 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4451 tcg_gen_movi_tl(cpu_ov, 1);
4452 tcg_gen_movi_tl(cpu_so, 1);
4453 tcg_gen_br(l2);
4454 gen_set_label(l1);
4455 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4456 tcg_gen_br(l3);
4457 gen_set_label(l2);
4458 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4459 gen_set_label(l3);
4460 if (unlikely(Rc(ctx->opcode) != 0))
4461 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4462 }
4463
4464 /* clcs */
4465 static void gen_clcs(DisasContext *ctx)
4466 {
4467 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4468 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4469 tcg_temp_free_i32(t0);
4470 /* Rc=1 sets CR0 to an undefined state */
4471 }
4472
4473 /* div - div. */
4474 static void gen_div(DisasContext *ctx)
4475 {
4476 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4477 cpu_gpr[rB(ctx->opcode)]);
4478 if (unlikely(Rc(ctx->opcode) != 0))
4479 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4480 }
4481
4482 /* divo - divo. */
4483 static void gen_divo(DisasContext *ctx)
4484 {
4485 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4486 cpu_gpr[rB(ctx->opcode)]);
4487 if (unlikely(Rc(ctx->opcode) != 0))
4488 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4489 }
4490
4491 /* divs - divs. */
4492 static void gen_divs(DisasContext *ctx)
4493 {
4494 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4495 cpu_gpr[rB(ctx->opcode)]);
4496 if (unlikely(Rc(ctx->opcode) != 0))
4497 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4498 }
4499
4500 /* divso - divso. */
4501 static void gen_divso(DisasContext *ctx)
4502 {
4503 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4504 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4505 if (unlikely(Rc(ctx->opcode) != 0))
4506 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4507 }
4508
4509 /* doz - doz. */
4510 static void gen_doz(DisasContext *ctx)
4511 {
4512 int l1 = gen_new_label();
4513 int l2 = gen_new_label();
4514 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4515 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4516 tcg_gen_br(l2);
4517 gen_set_label(l1);
4518 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4519 gen_set_label(l2);
4520 if (unlikely(Rc(ctx->opcode) != 0))
4521 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4522 }
4523
4524 /* dozo - dozo. */
4525 static void gen_dozo(DisasContext *ctx)
4526 {
4527 int l1 = gen_new_label();
4528 int l2 = gen_new_label();
4529 TCGv t0 = tcg_temp_new();
4530 TCGv t1 = tcg_temp_new();
4531 TCGv t2 = tcg_temp_new();
4532 /* Start with XER OV disabled, the most likely case */
4533 tcg_gen_movi_tl(cpu_ov, 0);
4534 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4535 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4536 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4537 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4538 tcg_gen_andc_tl(t1, t1, t2);
4539 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4540 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4541 tcg_gen_movi_tl(cpu_ov, 1);
4542 tcg_gen_movi_tl(cpu_so, 1);
4543 tcg_gen_br(l2);
4544 gen_set_label(l1);
4545 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4546 gen_set_label(l2);
4547 tcg_temp_free(t0);
4548 tcg_temp_free(t1);
4549 tcg_temp_free(t2);
4550 if (unlikely(Rc(ctx->opcode) != 0))
4551 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4552 }
4553
4554 /* dozi */
4555 static void gen_dozi(DisasContext *ctx)
4556 {
4557 target_long simm = SIMM(ctx->opcode);
4558 int l1 = gen_new_label();
4559 int l2 = gen_new_label();
4560 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4561 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4562 tcg_gen_br(l2);
4563 gen_set_label(l1);
4564 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4565 gen_set_label(l2);
4566 if (unlikely(Rc(ctx->opcode) != 0))
4567 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4568 }
4569
4570 /* lscbx - lscbx. */
4571 static void gen_lscbx(DisasContext *ctx)
4572 {
4573 TCGv t0 = tcg_temp_new();
4574 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4575 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4576 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4577
4578 gen_addr_reg_index(ctx, t0);
4579 /* NIP cannot be restored if the memory exception comes from an helper */
4580 gen_update_nip(ctx, ctx->nip - 4);
4581 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4582 tcg_temp_free_i32(t1);
4583 tcg_temp_free_i32(t2);
4584 tcg_temp_free_i32(t3);
4585 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4586 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4587 if (unlikely(Rc(ctx->opcode) != 0))
4588 gen_set_Rc0(ctx, t0);
4589 tcg_temp_free(t0);
4590 }
4591
4592 /* maskg - maskg. */
4593 static void gen_maskg(DisasContext *ctx)
4594 {
4595 int l1 = gen_new_label();
4596 TCGv t0 = tcg_temp_new();
4597 TCGv t1 = tcg_temp_new();
4598 TCGv t2 = tcg_temp_new();
4599 TCGv t3 = tcg_temp_new();
4600 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4601 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4602 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4603 tcg_gen_addi_tl(t2, t0, 1);
4604 tcg_gen_shr_tl(t2, t3, t2);
4605 tcg_gen_shr_tl(t3, t3, t1);
4606 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4607 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4608 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4609 gen_set_label(l1);
4610 tcg_temp_free(t0);
4611 tcg_temp_free(t1);
4612 tcg_temp_free(t2);
4613 tcg_temp_free(t3);
4614 if (unlikely(Rc(ctx->opcode) != 0))
4615 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4616 }
4617
4618 /* maskir - maskir. */
4619 static void gen_maskir(DisasContext *ctx)
4620 {
4621 TCGv t0 = tcg_temp_new();
4622 TCGv t1 = tcg_temp_new();
4623 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4624 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4625 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4626 tcg_temp_free(t0);
4627 tcg_temp_free(t1);
4628 if (unlikely(Rc(ctx->opcode) != 0))
4629 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4630 }
4631
4632 /* mul - mul. */
4633 static void gen_mul(DisasContext *ctx)
4634 {
4635 TCGv_i64 t0 = tcg_temp_new_i64();
4636 TCGv_i64 t1 = tcg_temp_new_i64();
4637 TCGv t2 = tcg_temp_new();
4638 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4639 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4640 tcg_gen_mul_i64(t0, t0, t1);
4641 tcg_gen_trunc_i64_tl(t2, t0);
4642 gen_store_spr(SPR_MQ, t2);
4643 tcg_gen_shri_i64(t1, t0, 32);
4644 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4645 tcg_temp_free_i64(t0);
4646 tcg_temp_free_i64(t1);
4647 tcg_temp_free(t2);
4648 if (unlikely(Rc(ctx->opcode) != 0))
4649 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4650 }
4651
4652 /* mulo - mulo. */
4653 static void gen_mulo(DisasContext *ctx)
4654 {
4655 int l1 = gen_new_label();
4656 TCGv_i64 t0 = tcg_temp_new_i64();
4657 TCGv_i64 t1 = tcg_temp_new_i64();
4658 TCGv t2 = tcg_temp_new();
4659 /* Start with XER OV disabled, the most likely case */
4660 tcg_gen_movi_tl(cpu_ov, 0);
4661 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4662 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4663 tcg_gen_mul_i64(t0, t0, t1);
4664 tcg_gen_trunc_i64_tl(t2, t0);
4665 gen_store_spr(SPR_MQ, t2);
4666 tcg_gen_shri_i64(t1, t0, 32);
4667 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4668 tcg_gen_ext32s_i64(t1, t0);
4669 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4670 tcg_gen_movi_tl(cpu_ov, 1);
4671 tcg_gen_movi_tl(cpu_so, 1);
4672 gen_set_label(l1);
4673 tcg_temp_free_i64(t0);
4674 tcg_temp_free_i64(t1);
4675 tcg_temp_free(t2);
4676 if (unlikely(Rc(ctx->opcode) != 0))
4677 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4678 }
4679
4680 /* nabs - nabs. */
4681 static void gen_nabs(DisasContext *ctx)
4682 {
4683 int l1 = gen_new_label();
4684 int l2 = gen_new_label();
4685 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4686 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4687 tcg_gen_br(l2);
4688 gen_set_label(l1);
4689 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4690 gen_set_label(l2);
4691 if (unlikely(Rc(ctx->opcode) != 0))
4692 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4693 }
4694
4695 /* nabso - nabso. */
4696 static void gen_nabso(DisasContext *ctx)
4697 {
4698 int l1 = gen_new_label();
4699 int l2 = gen_new_label();
4700 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4701 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4702 tcg_gen_br(l2);
4703 gen_set_label(l1);
4704 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4705 gen_set_label(l2);
4706 /* nabs never overflows */
4707 tcg_gen_movi_tl(cpu_ov, 0);
4708 if (unlikely(Rc(ctx->opcode) != 0))
4709 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4710 }
4711
4712 /* rlmi - rlmi. */
4713 static void gen_rlmi(DisasContext *ctx)
4714 {
4715 uint32_t mb = MB(ctx->opcode);
4716 uint32_t me = ME(ctx->opcode);
4717 TCGv t0 = tcg_temp_new();
4718 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4719 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4720 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4721 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4722 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4723 tcg_temp_free(t0);
4724 if (unlikely(Rc(ctx->opcode) != 0))
4725 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4726 }
4727
4728 /* rrib - rrib. */
4729 static void gen_rrib(DisasContext *ctx)
4730 {
4731 TCGv t0 = tcg_temp_new();
4732 TCGv t1 = tcg_temp_new();
4733 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4734 tcg_gen_movi_tl(t1, 0x80000000);
4735 tcg_gen_shr_tl(t1, t1, t0);
4736 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4737 tcg_gen_and_tl(t0, t0, t1);
4738 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4739 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4740 tcg_temp_free(t0);
4741 tcg_temp_free(t1);
4742 if (unlikely(Rc(ctx->opcode) != 0))
4743 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4744 }
4745
4746 /* sle - sle. */
4747 static void gen_sle(DisasContext *ctx)
4748 {
4749 TCGv t0 = tcg_temp_new();
4750 TCGv t1 = tcg_temp_new();
4751 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4752 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4753 tcg_gen_subfi_tl(t1, 32, t1);
4754 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4755 tcg_gen_or_tl(t1, t0, t1);
4756 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4757 gen_store_spr(SPR_MQ, t1);
4758 tcg_temp_free(t0);
4759 tcg_temp_free(t1);
4760 if (unlikely(Rc(ctx->opcode) != 0))
4761 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4762 }
4763
4764 /* sleq - sleq. */
4765 static void gen_sleq(DisasContext *ctx)
4766 {
4767 TCGv t0 = tcg_temp_new();
4768 TCGv t1 = tcg_temp_new();
4769 TCGv t2 = tcg_temp_new();
4770 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4771 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4772 tcg_gen_shl_tl(t2, t2, t0);
4773 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4774 gen_load_spr(t1, SPR_MQ);
4775 gen_store_spr(SPR_MQ, t0);
4776 tcg_gen_and_tl(t0, t0, t2);
4777 tcg_gen_andc_tl(t1, t1, t2);
4778 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4779 tcg_temp_free(t0);
4780 tcg_temp_free(t1);
4781 tcg_temp_free(t2);
4782 if (unlikely(Rc(ctx->opcode) != 0))
4783 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4784 }
4785
4786 /* sliq - sliq. */
4787 static void gen_sliq(DisasContext *ctx)
4788 {
4789 int sh = SH(ctx->opcode);
4790 TCGv t0 = tcg_temp_new();
4791 TCGv t1 = tcg_temp_new();
4792 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4793 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4794 tcg_gen_or_tl(t1, t0, t1);
4795 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4796 gen_store_spr(SPR_MQ, t1);
4797 tcg_temp_free(t0);
4798 tcg_temp_free(t1);
4799 if (unlikely(Rc(ctx->opcode) != 0))
4800 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4801 }
4802
4803 /* slliq - slliq. */
4804 static void gen_slliq(DisasContext *ctx)
4805 {
4806 int sh = SH(ctx->opcode);
4807 TCGv t0 = tcg_temp_new();
4808 TCGv t1 = tcg_temp_new();
4809 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4810 gen_load_spr(t1, SPR_MQ);
4811 gen_store_spr(SPR_MQ, t0);
4812 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4813 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4814 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4815 tcg_temp_free(t0);
4816 tcg_temp_free(t1);
4817 if (unlikely(Rc(ctx->opcode) != 0))
4818 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4819 }
4820
4821 /* sllq - sllq. */
4822 static void gen_sllq(DisasContext *ctx)
4823 {
4824 int l1 = gen_new_label();
4825 int l2 = gen_new_label();
4826 TCGv t0 = tcg_temp_local_new();
4827 TCGv t1 = tcg_temp_local_new();
4828 TCGv t2 = tcg_temp_local_new();
4829 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4830 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4831 tcg_gen_shl_tl(t1, t1, t2);
4832 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4833 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4834 gen_load_spr(t0, SPR_MQ);
4835 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4836 tcg_gen_br(l2);
4837 gen_set_label(l1);
4838 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4839 gen_load_spr(t2, SPR_MQ);
4840 tcg_gen_andc_tl(t1, t2, t1);
4841 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4842 gen_set_label(l2);
4843 tcg_temp_free(t0);
4844 tcg_temp_free(t1);
4845 tcg_temp_free(t2);
4846 if (unlikely(Rc(ctx->opcode) != 0))
4847 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4848 }
4849
4850 /* slq - slq. */
4851 static void gen_slq(DisasContext *ctx)
4852 {
4853 int l1 = gen_new_label();
4854 TCGv t0 = tcg_temp_new();
4855 TCGv t1 = tcg_temp_new();
4856 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4857 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4858 tcg_gen_subfi_tl(t1, 32, t1);
4859 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4860 tcg_gen_or_tl(t1, t0, t1);
4861 gen_store_spr(SPR_MQ, t1);
4862 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4863 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4864 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4865 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4866 gen_set_label(l1);
4867 tcg_temp_free(t0);
4868 tcg_temp_free(t1);
4869 if (unlikely(Rc(ctx->opcode) != 0))
4870 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4871 }
4872
4873 /* sraiq - sraiq. */
4874 static void gen_sraiq(DisasContext *ctx)
4875 {
4876 int sh = SH(ctx->opcode);
4877 int l1 = gen_new_label();
4878 TCGv t0 = tcg_temp_new();
4879 TCGv t1 = tcg_temp_new();
4880 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4881 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4882 tcg_gen_or_tl(t0, t0, t1);
4883 gen_store_spr(SPR_MQ, t0);
4884 tcg_gen_movi_tl(cpu_ca, 0);
4885 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4886 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4887 tcg_gen_movi_tl(cpu_ca, 1);
4888 gen_set_label(l1);
4889 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4890 tcg_temp_free(t0);
4891 tcg_temp_free(t1);
4892 if (unlikely(Rc(ctx->opcode) != 0))
4893 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4894 }
4895
4896 /* sraq - sraq. */
4897 static void gen_sraq(DisasContext *ctx)
4898 {
4899 int l1 = gen_new_label();
4900 int l2 = gen_new_label();
4901 TCGv t0 = tcg_temp_new();
4902 TCGv t1 = tcg_temp_local_new();
4903 TCGv t2 = tcg_temp_local_new();
4904 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4905 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4906 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4907 tcg_gen_subfi_tl(t2, 32, t2);
4908 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4909 tcg_gen_or_tl(t0, t0, t2);
4910 gen_store_spr(SPR_MQ, t0);
4911 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4912 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4913 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4914 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4915 gen_set_label(l1);
4916 tcg_temp_free(t0);
4917 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4918 tcg_gen_movi_tl(cpu_ca, 0);
4919 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4920 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4921 tcg_gen_movi_tl(cpu_ca, 1);
4922 gen_set_label(l2);
4923 tcg_temp_free(t1);
4924 tcg_temp_free(t2);
4925 if (unlikely(Rc(ctx->opcode) != 0))
4926 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4927 }
4928
4929 /* sre - sre. */
4930 static void gen_sre(DisasContext *ctx)
4931 {
4932 TCGv t0 = tcg_temp_new();
4933 TCGv t1 = tcg_temp_new();
4934 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4935 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4936 tcg_gen_subfi_tl(t1, 32, t1);
4937 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4938 tcg_gen_or_tl(t1, t0, t1);
4939 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4940 gen_store_spr(SPR_MQ, t1);
4941 tcg_temp_free(t0);
4942 tcg_temp_free(t1);
4943 if (unlikely(Rc(ctx->opcode) != 0))
4944 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4945 }
4946
4947 /* srea - srea. */
4948 static void gen_srea(DisasContext *ctx)
4949 {
4950 TCGv t0 = tcg_temp_new();
4951 TCGv t1 = tcg_temp_new();
4952 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4953 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4954 gen_store_spr(SPR_MQ, t0);
4955 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4956 tcg_temp_free(t0);
4957 tcg_temp_free(t1);
4958 if (unlikely(Rc(ctx->opcode) != 0))
4959 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4960 }
4961
4962 /* sreq */
4963 static void gen_sreq(DisasContext *ctx)
4964 {
4965 TCGv t0 = tcg_temp_new();
4966 TCGv t1 = tcg_temp_new();
4967 TCGv t2 = tcg_temp_new();
4968 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4969 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4970 tcg_gen_shr_tl(t1, t1, t0);
4971 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4972 gen_load_spr(t2, SPR_MQ);
4973 gen_store_spr(SPR_MQ, t0);
4974 tcg_gen_and_tl(t0, t0, t1);
4975 tcg_gen_andc_tl(t2, t2, t1);
4976 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4977 tcg_temp_free(t0);
4978 tcg_temp_free(t1);
4979 tcg_temp_free(t2);
4980 if (unlikely(Rc(ctx->opcode) != 0))
4981 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4982 }
4983
4984 /* sriq */
4985 static void gen_sriq(DisasContext *ctx)
4986 {
4987 int sh = SH(ctx->opcode);
4988 TCGv t0 = tcg_temp_new();
4989 TCGv t1 = tcg_temp_new();
4990 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4991 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4992 tcg_gen_or_tl(t1, t0, t1);
4993 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4994 gen_store_spr(SPR_MQ, t1);
4995 tcg_temp_free(t0);
4996 tcg_temp_free(t1);
4997 if (unlikely(Rc(ctx->opcode) != 0))
4998 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4999 }
5000
5001 /* srliq */
5002 static void gen_srliq(DisasContext *ctx)
5003 {
5004 int sh = SH(ctx->opcode);
5005 TCGv t0 = tcg_temp_new();
5006 TCGv t1 = tcg_temp_new();
5007 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5008 gen_load_spr(t1, SPR_MQ);
5009 gen_store_spr(SPR_MQ, t0);
5010 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5011 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5012 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5013 tcg_temp_free(t0);
5014 tcg_temp_free(t1);
5015 if (unlikely(Rc(ctx->opcode) != 0))
5016 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5017 }
5018
5019 /* srlq */
5020 static void gen_srlq(DisasContext *ctx)
5021 {
5022 int l1 = gen_new_label();
5023 int l2 = gen_new_label();
5024 TCGv t0 = tcg_temp_local_new();
5025 TCGv t1 = tcg_temp_local_new();
5026 TCGv t2 = tcg_temp_local_new();
5027 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5028 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5029 tcg_gen_shr_tl(t2, t1, t2);
5030 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5031 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5032 gen_load_spr(t0, SPR_MQ);
5033 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5034 tcg_gen_br(l2);
5035 gen_set_label(l1);
5036 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5037 tcg_gen_and_tl(t0, t0, t2);
5038 gen_load_spr(t1, SPR_MQ);
5039 tcg_gen_andc_tl(t1, t1, t2);
5040 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5041 gen_set_label(l2);
5042 tcg_temp_free(t0);
5043 tcg_temp_free(t1);
5044 tcg_temp_free(t2);
5045 if (unlikely(Rc(ctx->opcode) != 0))
5046 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5047 }
5048
5049 /* srq */
5050 static void gen_srq(DisasContext *ctx)
5051 {
5052 int l1 = gen_new_label();
5053 TCGv t0 = tcg_temp_new();
5054 TCGv t1 = tcg_temp_new();
5055 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5056 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5057 tcg_gen_subfi_tl(t1, 32, t1);
5058 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5059 tcg_gen_or_tl(t1, t0, t1);
5060 gen_store_spr(SPR_MQ, t1);
5061 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5062 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5063 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5064 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5065 gen_set_label(l1);
5066 tcg_temp_free(t0);
5067 tcg_temp_free(t1);
5068 if (unlikely(Rc(ctx->opcode) != 0))
5069 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5070 }
5071
5072 /* PowerPC 602 specific instructions */
5073
5074 /* dsa */
5075 static void gen_dsa(DisasContext *ctx)
5076 {
5077 /* XXX: TODO */
5078 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5079 }
5080
5081 /* esa */
5082 static void gen_esa(DisasContext *ctx)
5083 {
5084 /* XXX: TODO */
5085 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5086 }
5087
5088 /* mfrom */
5089 static void gen_mfrom(DisasContext *ctx)
5090 {
5091 #if defined(CONFIG_USER_ONLY)
5092 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5093 #else
5094 if (unlikely(!ctx->mem_idx)) {
5095 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5096 return;
5097 }
5098 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5099 #endif
5100 }
5101
5102 /* 602 - 603 - G2 TLB management */
5103
5104 /* tlbld */
5105 static void gen_tlbld_6xx(DisasContext *ctx)
5106 {
5107 #if defined(CONFIG_USER_ONLY)
5108 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5109 #else
5110 if (unlikely(!ctx->mem_idx)) {
5111 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5112 return;
5113 }
5114 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5115 #endif
5116 }
5117
5118 /* tlbli */
5119 static void gen_tlbli_6xx(DisasContext *ctx)
5120 {
5121 #if defined(CONFIG_USER_ONLY)
5122 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5123 #else
5124 if (unlikely(!ctx->mem_idx)) {
5125 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5126 return;
5127 }
5128 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5129 #endif
5130 }
5131
5132 /* 74xx TLB management */
5133
5134 /* tlbld */
5135 static void gen_tlbld_74xx(DisasContext *ctx)
5136 {
5137 #if defined(CONFIG_USER_ONLY)
5138 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5139 #else
5140 if (unlikely(!ctx->mem_idx)) {
5141 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5142 return;
5143 }
5144 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5145 #endif
5146 }
5147
5148 /* tlbli */
5149 static void gen_tlbli_74xx(DisasContext *ctx)
5150 {
5151 #if defined(CONFIG_USER_ONLY)
5152 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5153 #else
5154 if (unlikely(!ctx->mem_idx)) {
5155 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5156 return;
5157 }
5158 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5159 #endif
5160 }
5161
5162 /* POWER instructions not in PowerPC 601 */
5163
5164 /* clf */
5165 static void gen_clf(DisasContext *ctx)
5166 {
5167 /* Cache line flush: implemented as no-op */
5168 }
5169
5170 /* cli */
5171 static void gen_cli(DisasContext *ctx)
5172 {
5173 /* Cache line invalidate: privileged and treated as no-op */
5174 #if defined(CONFIG_USER_ONLY)
5175 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5176 #else
5177 if (unlikely(!ctx->mem_idx)) {
5178 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5179 return;
5180 }
5181 #endif
5182 }
5183
5184 /* dclst */
5185 static void gen_dclst(DisasContext *ctx)
5186 {
5187 /* Data cache line store: treated as no-op */
5188 }
5189
5190 static void gen_mfsri(DisasContext *ctx)
5191 {
5192 #if defined(CONFIG_USER_ONLY)
5193 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5194 #else
5195 int ra = rA(ctx->opcode);
5196 int rd = rD(ctx->opcode);
5197 TCGv t0;
5198 if (unlikely(!ctx->mem_idx)) {
5199 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5200 return;
5201 }
5202 t0 = tcg_temp_new();
5203 gen_addr_reg_index(ctx, t0);
5204 tcg_gen_shri_tl(t0, t0, 28);
5205 tcg_gen_andi_tl(t0, t0, 0xF);
5206 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5207 tcg_temp_free(t0);
5208 if (ra != 0 && ra != rd)
5209 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5210 #endif
5211 }
5212
5213 static void gen_rac(DisasContext *ctx)
5214 {
5215 #if defined(CONFIG_USER_ONLY)
5216 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5217 #else
5218 TCGv t0;
5219 if (unlikely(!ctx->mem_idx)) {
5220 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5221 return;
5222 }
5223 t0 = tcg_temp_new();
5224 gen_addr_reg_index(ctx, t0);
5225 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5226 tcg_temp_free(t0);
5227 #endif
5228 }
5229
5230 static void gen_rfsvc(DisasContext *ctx)
5231 {
5232 #if defined(CONFIG_USER_ONLY)
5233 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5234 #else
5235 if (unlikely(!ctx->mem_idx)) {
5236 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5237 return;
5238 }
5239 gen_helper_rfsvc(cpu_env);
5240 gen_sync_exception(ctx);
5241 #endif
5242 }
5243
5244 /* svc is not implemented for now */
5245
5246 /* POWER2 specific instructions */
5247 /* Quad manipulation (load/store two floats at a time) */
5248
5249 /* lfq */
5250 static void gen_lfq(DisasContext *ctx)
5251 {
5252 int rd = rD(ctx->opcode);
5253 TCGv t0;
5254 gen_set_access_type(ctx, ACCESS_FLOAT);
5255 t0 = tcg_temp_new();
5256 gen_addr_imm_index(ctx, t0, 0);
5257 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5258 gen_addr_add(ctx, t0, t0, 8);
5259 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5260 tcg_temp_free(t0);
5261 }
5262
5263 /* lfqu */
5264 static void gen_lfqu(DisasContext *ctx)
5265 {
5266 int ra = rA(ctx->opcode);
5267 int rd = rD(ctx->opcode);
5268 TCGv t0, t1;
5269 gen_set_access_type(ctx, ACCESS_FLOAT);
5270 t0 = tcg_temp_new();
5271 t1 = tcg_temp_new();
5272 gen_addr_imm_index(ctx, t0, 0);
5273 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5274 gen_addr_add(ctx, t1, t0, 8);
5275 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5276 if (ra != 0)
5277 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5278 tcg_temp_free(t0);
5279 tcg_temp_free(t1);
5280 }
5281
5282 /* lfqux */
5283 static void gen_lfqux(DisasContext *ctx)
5284 {
5285 int ra = rA(ctx->opcode);
5286 int rd = rD(ctx->opcode);
5287 gen_set_access_type(ctx, ACCESS_FLOAT);
5288 TCGv t0, t1;
5289 t0 = tcg_temp_new();
5290 gen_addr_reg_index(ctx, t0);
5291 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5292 t1 = tcg_temp_new();
5293 gen_addr_add(ctx, t1, t0, 8);
5294 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5295 tcg_temp_free(t1);
5296 if (ra != 0)
5297 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5298 tcg_temp_free(t0);
5299 }
5300
5301 /* lfqx */
5302 static void gen_lfqx(DisasContext *ctx)
5303 {
5304 int rd = rD(ctx->opcode);
5305 TCGv t0;
5306 gen_set_access_type(ctx, ACCESS_FLOAT);
5307 t0 = tcg_temp_new();
5308 gen_addr_reg_index(ctx, t0);
5309 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5310 gen_addr_add(ctx, t0, t0, 8);
5311 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5312 tcg_temp_free(t0);
5313 }
5314
5315 /* stfq */
5316 static void gen_stfq(DisasContext *ctx)
5317 {
5318 int rd = rD(ctx->opcode);
5319 TCGv t0;
5320 gen_set_access_type(ctx, ACCESS_FLOAT);
5321 t0 = tcg_temp_new();
5322 gen_addr_imm_index(ctx, t0, 0);
5323 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5324 gen_addr_add(ctx, t0, t0, 8);
5325 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5326 tcg_temp_free(t0);
5327 }
5328
5329 /* stfqu */
5330 static void gen_stfqu(DisasContext *ctx)
5331 {
5332 int ra = rA(ctx->opcode);
5333 int rd = rD(ctx->opcode);
5334 TCGv t0, t1;
5335 gen_set_access_type(ctx, ACCESS_FLOAT);
5336 t0 = tcg_temp_new();
5337 gen_addr_imm_index(ctx, t0, 0);
5338 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5339 t1 = tcg_temp_new();
5340 gen_addr_add(ctx, t1, t0, 8);
5341 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5342 tcg_temp_free(t1);
5343 if (ra != 0)
5344 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5345 tcg_temp_free(t0);
5346 }
5347
5348 /* stfqux */
5349 static void gen_stfqux(DisasContext *ctx)
5350 {
5351 int ra = rA(ctx->opcode);
5352 int rd = rD(ctx->opcode);
5353 TCGv t0, t1;
5354 gen_set_access_type(ctx, ACCESS_FLOAT);
5355 t0 = tcg_temp_new();
5356 gen_addr_reg_index(ctx, t0);
5357 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5358 t1 = tcg_temp_new();
5359 gen_addr_add(ctx, t1, t0, 8);
5360 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5361 tcg_temp_free(t1);
5362 if (ra != 0)
5363 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5364 tcg_temp_free(t0);
5365 }
5366
5367 /* stfqx */
5368 static void gen_stfqx(DisasContext *ctx)
5369 {
5370 int rd = rD(ctx->opcode);
5371 TCGv t0;
5372 gen_set_access_type(ctx, ACCESS_FLOAT);
5373 t0 = tcg_temp_new();
5374 gen_addr_reg_index(ctx, t0);
5375 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5376 gen_addr_add(ctx, t0, t0, 8);
5377 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5378 tcg_temp_free(t0);
5379 }
5380
5381 /* BookE specific instructions */
5382
5383 /* XXX: not implemented on 440 ? */
5384 static void gen_mfapidi(DisasContext *ctx)
5385 {
5386 /* XXX: TODO */
5387 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5388 }
5389
5390 /* XXX: not implemented on 440 ? */
5391 static void gen_tlbiva(DisasContext *ctx)
5392 {
5393 #if defined(CONFIG_USER_ONLY)
5394 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5395 #else
5396 TCGv t0;
5397 if (unlikely(!ctx->mem_idx)) {
5398 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5399 return;
5400 }
5401 t0 = tcg_temp_new();
5402 gen_addr_reg_index(ctx, t0);
5403 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5404 tcg_temp_free(t0);
5405 #endif
5406 }
5407
5408 /* All 405 MAC instructions are translated here */
5409 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5410 int ra, int rb, int rt, int Rc)
5411 {
5412 TCGv t0, t1;
5413
5414 t0 = tcg_temp_local_new();
5415 t1 = tcg_temp_local_new();
5416
5417 switch (opc3 & 0x0D) {
5418 case 0x05:
5419 /* macchw - macchw. - macchwo - macchwo. */
5420 /* macchws - macchws. - macchwso - macchwso. */
5421 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5422 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5423 /* mulchw - mulchw. */
5424 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5425 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5426 tcg_gen_ext16s_tl(t1, t1);
5427 break;
5428 case 0x04:
5429 /* macchwu - macchwu. - macchwuo - macchwuo. */
5430 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5431 /* mulchwu - mulchwu. */
5432 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5433 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5434 tcg_gen_ext16u_tl(t1, t1);
5435 break;
5436 case 0x01:
5437 /* machhw - machhw. - machhwo - machhwo. */
5438 /* machhws - machhws. - machhwso - machhwso. */
5439 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5440 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5441 /* mulhhw - mulhhw. */
5442 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5443 tcg_gen_ext16s_tl(t0, t0);
5444 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5445 tcg_gen_ext16s_tl(t1, t1);
5446 break;
5447 case 0x00:
5448 /* machhwu - machhwu. - machhwuo - machhwuo. */
5449 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5450 /* mulhhwu - mulhhwu. */
5451 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5452 tcg_gen_ext16u_tl(t0, t0);
5453 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5454 tcg_gen_ext16u_tl(t1, t1);
5455 break;
5456 case 0x0D:
5457 /* maclhw - maclhw. - maclhwo - maclhwo. */
5458 /* maclhws - maclhws. - maclhwso - maclhwso. */
5459 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5460 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5461 /* mullhw - mullhw. */
5462 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5463 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5464 break;
5465 case 0x0C:
5466 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5467 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5468 /* mullhwu - mullhwu. */
5469 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5470 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5471 break;
5472 }
5473 if (opc2 & 0x04) {
5474 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5475 tcg_gen_mul_tl(t1, t0, t1);
5476 if (opc2 & 0x02) {
5477 /* nmultiply-and-accumulate (0x0E) */
5478 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5479 } else {
5480 /* multiply-and-accumulate (0x0C) */
5481 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5482 }
5483
5484 if (opc3 & 0x12) {
5485 /* Check overflow and/or saturate */
5486 int l1 = gen_new_label();
5487
5488 if (opc3 & 0x10) {
5489 /* Start with XER OV disabled, the most likely case */
5490 tcg_gen_movi_tl(cpu_ov, 0);
5491 }
5492 if (opc3 & 0x01) {
5493 /* Signed */
5494 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5495 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5496 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5497 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5498 if (opc3 & 0x02) {
5499 /* Saturate */
5500 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5501 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5502 }
5503 } else {
5504 /* Unsigned */
5505 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5506 if (opc3 & 0x02) {
5507 /* Saturate */
5508 tcg_gen_movi_tl(t0, UINT32_MAX);
5509 }
5510 }
5511 if (opc3 & 0x10) {
5512 /* Check overflow */
5513 tcg_gen_movi_tl(cpu_ov, 1);
5514 tcg_gen_movi_tl(cpu_so, 1);
5515 }
5516 gen_set_label(l1);
5517 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5518 }
5519 } else {
5520 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5521 }
5522 tcg_temp_free(t0);
5523 tcg_temp_free(t1);
5524 if (unlikely(Rc) != 0) {
5525 /* Update Rc0 */
5526 gen_set_Rc0(ctx, cpu_gpr[rt]);
5527 }
5528 }
5529
5530 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5531 static void glue(gen_, name)(DisasContext *ctx) \
5532 { \
5533 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5534 rD(ctx->opcode), Rc(ctx->opcode)); \
5535 }
5536
5537 /* macchw - macchw. */
5538 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5539 /* macchwo - macchwo. */
5540 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5541 /* macchws - macchws. */
5542 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5543 /* macchwso - macchwso. */
5544 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5545 /* macchwsu - macchwsu. */
5546 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5547 /* macchwsuo - macchwsuo. */
5548 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5549 /* macchwu - macchwu. */
5550 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5551 /* macchwuo - macchwuo. */
5552 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5553 /* machhw - machhw. */
5554 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5555 /* machhwo - machhwo. */
5556 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5557 /* machhws - machhws. */
5558 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5559 /* machhwso - machhwso. */
5560 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5561 /* machhwsu - machhwsu. */
5562 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5563 /* machhwsuo - machhwsuo. */
5564 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5565 /* machhwu - machhwu. */
5566 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5567 /* machhwuo - machhwuo. */
5568 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5569 /* maclhw - maclhw. */
5570 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5571 /* maclhwo - maclhwo. */
5572 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5573 /* maclhws - maclhws. */
5574 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5575 /* maclhwso - maclhwso. */
5576 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5577 /* maclhwu - maclhwu. */
5578 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5579 /* maclhwuo - maclhwuo. */
5580 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5581 /* maclhwsu - maclhwsu. */
5582 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5583 /* maclhwsuo - maclhwsuo. */
5584 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5585 /* nmacchw - nmacchw. */
5586 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5587 /* nmacchwo - nmacchwo. */
5588 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5589 /* nmacchws - nmacchws. */
5590 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5591 /* nmacchwso - nmacchwso. */
5592 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5593 /* nmachhw - nmachhw. */
5594 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5595 /* nmachhwo - nmachhwo. */
5596 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5597 /* nmachhws - nmachhws. */
5598 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5599 /* nmachhwso - nmachhwso. */
5600 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5601 /* nmaclhw - nmaclhw. */
5602 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5603 /* nmaclhwo - nmaclhwo. */
5604 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5605 /* nmaclhws - nmaclhws. */
5606 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5607 /* nmaclhwso - nmaclhwso. */
5608 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5609
5610 /* mulchw - mulchw. */
5611 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5612 /* mulchwu - mulchwu. */
5613 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5614 /* mulhhw - mulhhw. */
5615 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5616 /* mulhhwu - mulhhwu. */
5617 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5618 /* mullhw - mullhw. */
5619 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5620 /* mullhwu - mullhwu. */
5621 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5622
5623 /* mfdcr */
5624 static void gen_mfdcr(DisasContext *ctx)
5625 {
5626 #if defined(CONFIG_USER_ONLY)
5627 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5628 #else
5629 TCGv dcrn;
5630 if (unlikely(!ctx->mem_idx)) {
5631 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5632 return;
5633 }
5634 /* NIP cannot be restored if the memory exception comes from an helper */
5635 gen_update_nip(ctx, ctx->nip - 4);
5636 dcrn = tcg_const_tl(SPR(ctx->opcode));
5637 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5638 tcg_temp_free(dcrn);
5639 #endif
5640 }
5641
5642 /* mtdcr */
5643 static void gen_mtdcr(DisasContext *ctx)
5644 {
5645 #if defined(CONFIG_USER_ONLY)
5646 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5647 #else
5648 TCGv dcrn;
5649 if (unlikely(!ctx->mem_idx)) {
5650 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5651 return;
5652 }
5653 /* NIP cannot be restored if the memory exception comes from an helper */
5654 gen_update_nip(ctx, ctx->nip - 4);
5655 dcrn = tcg_const_tl(SPR(ctx->opcode));
5656 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5657 tcg_temp_free(dcrn);
5658 #endif
5659 }
5660
5661 /* mfdcrx */
5662 /* XXX: not implemented on 440 ? */
5663 static void gen_mfdcrx(DisasContext *ctx)
5664 {
5665 #if defined(CONFIG_USER_ONLY)
5666 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5667 #else
5668 if (unlikely(!ctx->mem_idx)) {
5669 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5670 return;
5671 }
5672 /* NIP cannot be restored if the memory exception comes from an helper */
5673 gen_update_nip(ctx, ctx->nip - 4);
5674 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5675 cpu_gpr[rA(ctx->opcode)]);
5676 /* Note: Rc update flag set leads to undefined state of Rc0 */
5677 #endif
5678 }
5679
5680 /* mtdcrx */
5681 /* XXX: not implemented on 440 ? */
5682 static void gen_mtdcrx(DisasContext *ctx)
5683 {
5684 #if defined(CONFIG_USER_ONLY)
5685 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5686 #else
5687 if (unlikely(!ctx->mem_idx)) {
5688 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5689 return;
5690 }
5691 /* NIP cannot be restored if the memory exception comes from an helper */
5692 gen_update_nip(ctx, ctx->nip - 4);
5693 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5694 cpu_gpr[rS(ctx->opcode)]);
5695 /* Note: Rc update flag set leads to undefined state of Rc0 */
5696 #endif
5697 }
5698
5699 /* mfdcrux (PPC 460) : user-mode access to DCR */
5700 static void gen_mfdcrux(DisasContext *ctx)
5701 {
5702 /* NIP cannot be restored if the memory exception comes from an helper */
5703 gen_update_nip(ctx, ctx->nip - 4);
5704 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5705 cpu_gpr[rA(ctx->opcode)]);
5706 /* Note: Rc update flag set leads to undefined state of Rc0 */
5707 }
5708
5709 /* mtdcrux (PPC 460) : user-mode access to DCR */
5710 static void gen_mtdcrux(DisasContext *ctx)
5711 {
5712 /* NIP cannot be restored if the memory exception comes from an helper */
5713 gen_update_nip(ctx, ctx->nip - 4);
5714 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5715 cpu_gpr[rS(ctx->opcode)]);
5716 /* Note: Rc update flag set leads to undefined state of Rc0 */
5717 }
5718
5719 /* dccci */
5720 static void gen_dccci(DisasContext *ctx)
5721 {
5722 #if defined(CONFIG_USER_ONLY)
5723 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5724 #else
5725 if (unlikely(!ctx->mem_idx)) {
5726 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5727 return;
5728 }
5729 /* interpreted as no-op */
5730 #endif
5731 }
5732
5733 /* dcread */
5734 static void gen_dcread(DisasContext *ctx)
5735 {
5736 #if defined(CONFIG_USER_ONLY)
5737 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5738 #else
5739 TCGv EA, val;
5740 if (unlikely(!ctx->mem_idx)) {
5741 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5742 return;
5743 }
5744 gen_set_access_type(ctx, ACCESS_CACHE);
5745 EA = tcg_temp_new();
5746 gen_addr_reg_index(ctx, EA);
5747 val = tcg_temp_new();
5748 gen_qemu_ld32u(ctx, val, EA);
5749 tcg_temp_free(val);
5750 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5751 tcg_temp_free(EA);
5752 #endif
5753 }
5754
5755 /* icbt */
5756 static void gen_icbt_40x(DisasContext *ctx)
5757 {
5758 /* interpreted as no-op */
5759 /* XXX: specification say this is treated as a load by the MMU
5760 * but does not generate any exception
5761 */
5762 }
5763
5764 /* iccci */
5765 static void gen_iccci(DisasContext *ctx)
5766 {
5767 #if defined(CONFIG_USER_ONLY)
5768 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5769 #else
5770 if (unlikely(!ctx->mem_idx)) {
5771 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5772 return;
5773 }
5774 /* interpreted as no-op */
5775 #endif
5776 }
5777
5778 /* icread */
5779 static void gen_icread(DisasContext *ctx)
5780 {
5781 #if defined(CONFIG_USER_ONLY)
5782 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5783 #else
5784 if (unlikely(!ctx->mem_idx)) {
5785 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5786 return;
5787 }
5788 /* interpreted as no-op */
5789 #endif
5790 }
5791
5792 /* rfci (mem_idx only) */
5793 static void gen_rfci_40x(DisasContext *ctx)
5794 {
5795 #if defined(CONFIG_USER_ONLY)
5796 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5797 #else
5798 if (unlikely(!ctx->mem_idx)) {
5799 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5800 return;
5801 }
5802 /* Restore CPU state */
5803 gen_helper_40x_rfci(cpu_env);
5804 gen_sync_exception(ctx);
5805 #endif
5806 }
5807
5808 static void gen_rfci(DisasContext *ctx)
5809 {
5810 #if defined(CONFIG_USER_ONLY)
5811 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5812 #else
5813 if (unlikely(!ctx->mem_idx)) {
5814 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5815 return;
5816 }
5817 /* Restore CPU state */
5818 gen_helper_rfci(cpu_env);
5819 gen_sync_exception(ctx);
5820 #endif
5821 }
5822
5823 /* BookE specific */
5824
5825 /* XXX: not implemented on 440 ? */
5826 static void gen_rfdi(DisasContext *ctx)
5827 {
5828 #if defined(CONFIG_USER_ONLY)
5829 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5830 #else
5831 if (unlikely(!ctx->mem_idx)) {
5832 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5833 return;
5834 }
5835 /* Restore CPU state */
5836 gen_helper_rfdi(cpu_env);
5837 gen_sync_exception(ctx);
5838 #endif
5839 }
5840
5841 /* XXX: not implemented on 440 ? */
5842 static void gen_rfmci(DisasContext *ctx)
5843 {
5844 #if defined(CONFIG_USER_ONLY)
5845 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5846 #else
5847 if (unlikely(!ctx->mem_idx)) {
5848 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5849 return;
5850 }
5851 /* Restore CPU state */
5852 gen_helper_rfmci(cpu_env);
5853 gen_sync_exception(ctx);
5854 #endif
5855 }
5856
5857 /* TLB management - PowerPC 405 implementation */
5858
5859 /* tlbre */
5860 static void gen_tlbre_40x(DisasContext *ctx)
5861 {
5862 #if defined(CONFIG_USER_ONLY)
5863 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5864 #else
5865 if (unlikely(!ctx->mem_idx)) {
5866 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5867 return;
5868 }
5869 switch (rB(ctx->opcode)) {
5870 case 0:
5871 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5872 cpu_gpr[rA(ctx->opcode)]);
5873 break;
5874 case 1:
5875 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5876 cpu_gpr[rA(ctx->opcode)]);
5877 break;
5878 default:
5879 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5880 break;
5881 }
5882 #endif
5883 }
5884
5885 /* tlbsx - tlbsx. */
5886 static void gen_tlbsx_40x(DisasContext *ctx)
5887 {
5888 #if defined(CONFIG_USER_ONLY)
5889 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5890 #else
5891 TCGv t0;
5892 if (unlikely(!ctx->mem_idx)) {
5893 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5894 return;
5895 }
5896 t0 = tcg_temp_new();
5897 gen_addr_reg_index(ctx, t0);
5898 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5899 tcg_temp_free(t0);
5900 if (Rc(ctx->opcode)) {
5901 int l1 = gen_new_label();
5902 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5903 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5904 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5905 gen_set_label(l1);
5906 }
5907 #endif
5908 }
5909
5910 /* tlbwe */
5911 static void gen_tlbwe_40x(DisasContext *ctx)
5912 {
5913 #if defined(CONFIG_USER_ONLY)
5914 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5915 #else
5916 if (unlikely(!ctx->mem_idx)) {
5917 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5918 return;
5919 }
5920 switch (rB(ctx->opcode)) {
5921 case 0:
5922 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5923 cpu_gpr[rS(ctx->opcode)]);
5924 break;
5925 case 1:
5926 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5927 cpu_gpr[rS(ctx->opcode)]);
5928 break;
5929 default:
5930 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5931 break;
5932 }
5933 #endif
5934 }
5935
5936 /* TLB management - PowerPC 440 implementation */
5937
5938 /* tlbre */
5939 static void gen_tlbre_440(DisasContext *ctx)
5940 {
5941 #if defined(CONFIG_USER_ONLY)
5942 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5943 #else
5944 if (unlikely(!ctx->mem_idx)) {
5945 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5946 return;
5947 }
5948 switch (rB(ctx->opcode)) {
5949 case 0:
5950 case 1:
5951 case 2:
5952 {
5953 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5954 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5955 t0, cpu_gpr[rA(ctx->opcode)]);
5956 tcg_temp_free_i32(t0);
5957 }
5958 break;
5959 default:
5960 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5961 break;
5962 }
5963 #endif
5964 }
5965
5966 /* tlbsx - tlbsx. */
5967 static void gen_tlbsx_440(DisasContext *ctx)
5968 {
5969 #if defined(CONFIG_USER_ONLY)
5970 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5971 #else
5972 TCGv t0;
5973 if (unlikely(!ctx->mem_idx)) {
5974 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5975 return;
5976 }
5977 t0 = tcg_temp_new();
5978 gen_addr_reg_index(ctx, t0);
5979 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5980 tcg_temp_free(t0);
5981 if (Rc(ctx->opcode)) {
5982 int l1 = gen_new_label();
5983 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5984 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5985 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5986 gen_set_label(l1);
5987 }
5988 #endif
5989 }
5990
5991 /* tlbwe */
5992 static void gen_tlbwe_440(DisasContext *ctx)
5993 {
5994 #if defined(CONFIG_USER_ONLY)
5995 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5996 #else
5997 if (unlikely(!ctx->mem_idx)) {
5998 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5999 return;
6000 }
6001 switch (rB(ctx->opcode)) {
6002 case 0:
6003 case 1:
6004 case 2:
6005 {
6006 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6007 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6008 cpu_gpr[rS(ctx->opcode)]);
6009 tcg_temp_free_i32(t0);
6010 }
6011 break;
6012 default:
6013 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6014 break;
6015 }
6016 #endif
6017 }
6018
6019 /* TLB management - PowerPC BookE 2.06 implementation */
6020
6021 /* tlbre */
6022 static void gen_tlbre_booke206(DisasContext *ctx)
6023 {
6024 #if defined(CONFIG_USER_ONLY)
6025 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6026 #else
6027 if (unlikely(!ctx->mem_idx)) {
6028 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6029 return;
6030 }
6031
6032 gen_helper_booke206_tlbre(cpu_env);
6033 #endif
6034 }
6035
6036 /* tlbsx - tlbsx. */
6037 static void gen_tlbsx_booke206(DisasContext *ctx)
6038 {
6039 #if defined(CONFIG_USER_ONLY)
6040 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6041 #else
6042 TCGv t0;
6043 if (unlikely(!ctx->mem_idx)) {
6044 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6045 return;
6046 }
6047
6048 if (rA(ctx->opcode)) {
6049 t0 = tcg_temp_new();
6050 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6051 } else {
6052 t0 = tcg_const_tl(0);
6053 }
6054
6055 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6056 gen_helper_booke206_tlbsx(cpu_env, t0);
6057 #endif
6058 }
6059
6060 /* tlbwe */
6061 static void gen_tlbwe_booke206(DisasContext *ctx)
6062 {
6063 #if defined(CONFIG_USER_ONLY)
6064 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6065 #else
6066 if (unlikely(!ctx->mem_idx)) {
6067 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6068 return;
6069 }
6070 gen_update_nip(ctx, ctx->nip - 4);
6071 gen_helper_booke206_tlbwe(cpu_env);
6072 #endif
6073 }
6074
6075 static void gen_tlbivax_booke206(DisasContext *ctx)
6076 {
6077 #if defined(CONFIG_USER_ONLY)
6078 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6079 #else
6080 TCGv t0;
6081 if (unlikely(!ctx->mem_idx)) {
6082 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6083 return;
6084 }
6085
6086 t0 = tcg_temp_new();
6087 gen_addr_reg_index(ctx, t0);
6088
6089 gen_helper_booke206_tlbivax(cpu_env, t0);
6090 #endif
6091 }
6092
6093 static void gen_tlbilx_booke206(DisasContext *ctx)
6094 {
6095 #if defined(CONFIG_USER_ONLY)
6096 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6097 #else
6098 TCGv t0;
6099 if (unlikely(!ctx->mem_idx)) {
6100 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6101 return;
6102 }
6103
6104 t0 = tcg_temp_new();
6105 gen_addr_reg_index(ctx, t0);
6106
6107 switch((ctx->opcode >> 21) & 0x3) {
6108 case 0:
6109 gen_helper_booke206_tlbilx0(cpu_env, t0);
6110 break;
6111 case 1:
6112 gen_helper_booke206_tlbilx1(cpu_env, t0);
6113 break;
6114 case 3:
6115 gen_helper_booke206_tlbilx3(cpu_env, t0);
6116 break;
6117 default:
6118 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6119 break;
6120 }
6121
6122 tcg_temp_free(t0);
6123 #endif
6124 }
6125
6126
6127 /* wrtee */
6128 static void gen_wrtee(DisasContext *ctx)
6129 {
6130 #if defined(CONFIG_USER_ONLY)
6131 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6132 #else
6133 TCGv t0;
6134 if (unlikely(!ctx->mem_idx)) {
6135 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6136 return;
6137 }
6138 t0 = tcg_temp_new();
6139 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6140 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6141 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6142 tcg_temp_free(t0);
6143 /* Stop translation to have a chance to raise an exception
6144 * if we just set msr_ee to 1
6145 */
6146 gen_stop_exception(ctx);
6147 #endif
6148 }
6149
6150 /* wrteei */
6151 static void gen_wrteei(DisasContext *ctx)
6152 {
6153 #if defined(CONFIG_USER_ONLY)
6154 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6155 #else
6156 if (unlikely(!ctx->mem_idx)) {
6157 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6158 return;
6159 }
6160 if (ctx->opcode & 0x00008000) {
6161 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6162 /* Stop translation to have a chance to raise an exception */
6163 gen_stop_exception(ctx);
6164 } else {
6165 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6166 }
6167 #endif
6168 }
6169
6170 /* PowerPC 440 specific instructions */
6171
6172 /* dlmzb */
6173 static void gen_dlmzb(DisasContext *ctx)
6174 {
6175 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6176 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6177 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6178 tcg_temp_free_i32(t0);
6179 }
6180
6181 /* mbar replaces eieio on 440 */
6182 static void gen_mbar(DisasContext *ctx)
6183 {
6184 /* interpreted as no-op */
6185 }
6186
6187 /* msync replaces sync on 440 */
6188 static void gen_msync_4xx(DisasContext *ctx)
6189 {
6190 /* interpreted as no-op */
6191 }
6192
6193 /* icbt */
6194 static void gen_icbt_440(DisasContext *ctx)
6195 {
6196 /* interpreted as no-op */
6197 /* XXX: specification say this is treated as a load by the MMU
6198 * but does not generate any exception
6199 */
6200 }
6201
6202 /* Embedded.Processor Control */
6203
6204 static void gen_msgclr(DisasContext *ctx)
6205 {
6206 #if defined(CONFIG_USER_ONLY)
6207 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6208 #else
6209 if (unlikely(ctx->mem_idx == 0)) {
6210 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6211 return;
6212 }
6213
6214 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6215 #endif
6216 }
6217
6218 static void gen_msgsnd(DisasContext *ctx)
6219 {
6220 #if defined(CONFIG_USER_ONLY)
6221 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6222 #else
6223 if (unlikely(ctx->mem_idx == 0)) {
6224 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6225 return;
6226 }
6227
6228 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6229 #endif
6230 }
6231
6232 /*** Altivec vector extension ***/
6233 /* Altivec registers moves */
6234
6235 static inline TCGv_ptr gen_avr_ptr(int reg)
6236 {
6237 TCGv_ptr r = tcg_temp_new_ptr();
6238 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6239 return r;
6240 }
6241
6242 #define GEN_VR_LDX(name, opc2, opc3) \
6243 static void glue(gen_, name)(DisasContext *ctx) \
6244 { \
6245 TCGv EA; \
6246 if (unlikely(!ctx->altivec_enabled)) { \
6247 gen_exception(ctx, POWERPC_EXCP_VPU); \
6248 return; \
6249 } \
6250 gen_set_access_type(ctx, ACCESS_INT); \
6251 EA = tcg_temp_new(); \
6252 gen_addr_reg_index(ctx, EA); \
6253 tcg_gen_andi_tl(EA, EA, ~0xf); \
6254 if (ctx->le_mode) { \
6255 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6256 tcg_gen_addi_tl(EA, EA, 8); \
6257 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6258 } else { \
6259 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6260 tcg_gen_addi_tl(EA, EA, 8); \
6261 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6262 } \
6263 tcg_temp_free(EA); \
6264 }
6265
6266 #define GEN_VR_STX(name, opc2, opc3) \
6267 static void gen_st##name(DisasContext *ctx) \
6268 { \
6269 TCGv EA; \
6270 if (unlikely(!ctx->altivec_enabled)) { \
6271 gen_exception(ctx, POWERPC_EXCP_VPU); \
6272 return; \
6273 } \
6274 gen_set_access_type(ctx, ACCESS_INT); \
6275 EA = tcg_temp_new(); \
6276 gen_addr_reg_index(ctx, EA); \
6277 tcg_gen_andi_tl(EA, EA, ~0xf); \
6278 if (ctx->le_mode) { \
6279 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6280 tcg_gen_addi_tl(EA, EA, 8); \
6281 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6282 } else { \
6283 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6284 tcg_gen_addi_tl(EA, EA, 8); \
6285 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6286 } \
6287 tcg_temp_free(EA); \
6288 }
6289
6290 #define GEN_VR_LVE(name, opc2, opc3) \
6291 static void gen_lve##name(DisasContext *ctx) \
6292 { \
6293 TCGv EA; \
6294 TCGv_ptr rs; \
6295 if (unlikely(!ctx->altivec_enabled)) { \
6296 gen_exception(ctx, POWERPC_EXCP_VPU); \
6297 return; \
6298 } \
6299 gen_set_access_type(ctx, ACCESS_INT); \
6300 EA = tcg_temp_new(); \
6301 gen_addr_reg_index(ctx, EA); \
6302 rs = gen_avr_ptr(rS(ctx->opcode)); \
6303 gen_helper_lve##name(cpu_env, rs, EA); \
6304 tcg_temp_free(EA); \
6305 tcg_temp_free_ptr(rs); \
6306 }
6307
6308 #define GEN_VR_STVE(name, opc2, opc3) \
6309 static void gen_stve##name(DisasContext *ctx) \
6310 { \
6311 TCGv EA; \
6312 TCGv_ptr rs; \
6313 if (unlikely(!ctx->altivec_enabled)) { \
6314 gen_exception(ctx, POWERPC_EXCP_VPU); \
6315 return; \
6316 } \
6317 gen_set_access_type(ctx, ACCESS_INT); \
6318 EA = tcg_temp_new(); \
6319 gen_addr_reg_index(ctx, EA); \
6320 rs = gen_avr_ptr(rS(ctx->opcode)); \
6321 gen_helper_stve##name(cpu_env, rs, EA); \
6322 tcg_temp_free(EA); \
6323 tcg_temp_free_ptr(rs); \
6324 }
6325
6326 GEN_VR_LDX(lvx, 0x07, 0x03);
6327 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6328 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6329
6330 GEN_VR_LVE(bx, 0x07, 0x00);
6331 GEN_VR_LVE(hx, 0x07, 0x01);
6332 GEN_VR_LVE(wx, 0x07, 0x02);
6333
6334 GEN_VR_STX(svx, 0x07, 0x07);
6335 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6336 GEN_VR_STX(svxl, 0x07, 0x0F);
6337
6338 GEN_VR_STVE(bx, 0x07, 0x04);
6339 GEN_VR_STVE(hx, 0x07, 0x05);
6340 GEN_VR_STVE(wx, 0x07, 0x06);
6341
6342 static void gen_lvsl(DisasContext *ctx)
6343 {
6344 TCGv_ptr rd;
6345 TCGv EA;
6346 if (unlikely(!ctx->altivec_enabled)) {
6347 gen_exception(ctx, POWERPC_EXCP_VPU);
6348 return;
6349 }
6350 EA = tcg_temp_new();
6351 gen_addr_reg_index(ctx, EA);
6352 rd = gen_avr_ptr(rD(ctx->opcode));
6353 gen_helper_lvsl(rd, EA);
6354 tcg_temp_free(EA);
6355 tcg_temp_free_ptr(rd);
6356 }
6357
6358 static void gen_lvsr(DisasContext *ctx)
6359 {
6360 TCGv_ptr rd;
6361 TCGv EA;
6362 if (unlikely(!ctx->altivec_enabled)) {
6363 gen_exception(ctx, POWERPC_EXCP_VPU);
6364 return;
6365 }
6366 EA = tcg_temp_new();
6367 gen_addr_reg_index(ctx, EA);
6368 rd = gen_avr_ptr(rD(ctx->opcode));
6369 gen_helper_lvsr(rd, EA);
6370 tcg_temp_free(EA);
6371 tcg_temp_free_ptr(rd);
6372 }
6373
6374 static void gen_mfvscr(DisasContext *ctx)
6375 {
6376 TCGv_i32 t;
6377 if (unlikely(!ctx->altivec_enabled)) {
6378 gen_exception(ctx, POWERPC_EXCP_VPU);
6379 return;
6380 }
6381 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6382 t = tcg_temp_new_i32();
6383 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6384 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6385 tcg_temp_free_i32(t);
6386 }
6387
6388 static void gen_mtvscr(DisasContext *ctx)
6389 {
6390 TCGv_ptr p;
6391 if (unlikely(!ctx->altivec_enabled)) {
6392 gen_exception(ctx, POWERPC_EXCP_VPU);
6393 return;
6394 }
6395 p = gen_avr_ptr(rD(ctx->opcode));
6396 gen_helper_mtvscr(cpu_env, p);
6397 tcg_temp_free_ptr(p);
6398 }
6399
6400 /* Logical operations */
6401 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6402 static void glue(gen_, name)(DisasContext *ctx) \
6403 { \
6404 if (unlikely(!ctx->altivec_enabled)) { \
6405 gen_exception(ctx, POWERPC_EXCP_VPU); \
6406 return; \
6407 } \
6408 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6409 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6410 }
6411
6412 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6413 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6414 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6415 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6416 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6417
6418 #define GEN_VXFORM(name, opc2, opc3) \
6419 static void glue(gen_, name)(DisasContext *ctx) \
6420 { \
6421 TCGv_ptr ra, rb, rd; \
6422 if (unlikely(!ctx->altivec_enabled)) { \
6423 gen_exception(ctx, POWERPC_EXCP_VPU); \
6424 return; \
6425 } \
6426 ra = gen_avr_ptr(rA(ctx->opcode)); \
6427 rb = gen_avr_ptr(rB(ctx->opcode)); \
6428 rd = gen_avr_ptr(rD(ctx->opcode)); \
6429 gen_helper_##name (rd, ra, rb); \
6430 tcg_temp_free_ptr(ra); \
6431 tcg_temp_free_ptr(rb); \
6432 tcg_temp_free_ptr(rd); \
6433 }
6434
6435 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6436 static void glue(gen_, name)(DisasContext *ctx) \
6437 { \
6438 TCGv_ptr ra, rb, rd; \
6439 if (unlikely(!ctx->altivec_enabled)) { \
6440 gen_exception(ctx, POWERPC_EXCP_VPU); \
6441 return; \
6442 } \
6443 ra = gen_avr_ptr(rA(ctx->opcode)); \
6444 rb = gen_avr_ptr(rB(ctx->opcode)); \
6445 rd = gen_avr_ptr(rD(ctx->opcode)); \
6446 gen_helper_##name(cpu_env, rd, ra, rb); \
6447 tcg_temp_free_ptr(ra); \
6448 tcg_temp_free_ptr(rb); \
6449 tcg_temp_free_ptr(rd); \
6450 }
6451
6452 GEN_VXFORM(vaddubm, 0, 0);
6453 GEN_VXFORM(vadduhm, 0, 1);
6454 GEN_VXFORM(vadduwm, 0, 2);
6455 GEN_VXFORM(vsububm, 0, 16);
6456 GEN_VXFORM(vsubuhm, 0, 17);
6457 GEN_VXFORM(vsubuwm, 0, 18);
6458 GEN_VXFORM(vmaxub, 1, 0);
6459 GEN_VXFORM(vmaxuh, 1, 1);
6460 GEN_VXFORM(vmaxuw, 1, 2);
6461 GEN_VXFORM(vmaxsb, 1, 4);
6462 GEN_VXFORM(vmaxsh, 1, 5);
6463 GEN_VXFORM(vmaxsw, 1, 6);
6464 GEN_VXFORM(vminub, 1, 8);
6465 GEN_VXFORM(vminuh, 1, 9);
6466 GEN_VXFORM(vminuw, 1, 10);
6467 GEN_VXFORM(vminsb, 1, 12);
6468 GEN_VXFORM(vminsh, 1, 13);
6469 GEN_VXFORM(vminsw, 1, 14);
6470 GEN_VXFORM(vavgub, 1, 16);
6471 GEN_VXFORM(vavguh, 1, 17);
6472 GEN_VXFORM(vavguw, 1, 18);
6473 GEN_VXFORM(vavgsb, 1, 20);
6474 GEN_VXFORM(vavgsh, 1, 21);
6475 GEN_VXFORM(vavgsw, 1, 22);
6476 GEN_VXFORM(vmrghb, 6, 0);
6477 GEN_VXFORM(vmrghh, 6, 1);
6478 GEN_VXFORM(vmrghw, 6, 2);
6479 GEN_VXFORM(vmrglb, 6, 4);
6480 GEN_VXFORM(vmrglh, 6, 5);
6481 GEN_VXFORM(vmrglw, 6, 6);
6482 GEN_VXFORM(vmuloub, 4, 0);
6483 GEN_VXFORM(vmulouh, 4, 1);
6484 GEN_VXFORM(vmulosb, 4, 4);
6485 GEN_VXFORM(vmulosh, 4, 5);
6486 GEN_VXFORM(vmuleub, 4, 8);
6487 GEN_VXFORM(vmuleuh, 4, 9);
6488 GEN_VXFORM(vmulesb, 4, 12);
6489 GEN_VXFORM(vmulesh, 4, 13);
6490 GEN_VXFORM(vslb, 2, 4);
6491 GEN_VXFORM(vslh, 2, 5);
6492 GEN_VXFORM(vslw, 2, 6);
6493 GEN_VXFORM(vsrb, 2, 8);
6494 GEN_VXFORM(vsrh, 2, 9);
6495 GEN_VXFORM(vsrw, 2, 10);
6496 GEN_VXFORM(vsrab, 2, 12);
6497 GEN_VXFORM(vsrah, 2, 13);
6498 GEN_VXFORM(vsraw, 2, 14);
6499 GEN_VXFORM(vslo, 6, 16);
6500 GEN_VXFORM(vsro, 6, 17);
6501 GEN_VXFORM(vaddcuw, 0, 6);
6502 GEN_VXFORM(vsubcuw, 0, 22);
6503 GEN_VXFORM_ENV(vaddubs, 0, 8);
6504 GEN_VXFORM_ENV(vadduhs, 0, 9);
6505 GEN_VXFORM_ENV(vadduws, 0, 10);
6506 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6507 GEN_VXFORM_ENV(vaddshs, 0, 13);
6508 GEN_VXFORM_ENV(vaddsws, 0, 14);
6509 GEN_VXFORM_ENV(vsububs, 0, 24);
6510 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6511 GEN_VXFORM_ENV(vsubuws, 0, 26);
6512 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6513 GEN_VXFORM_ENV(vsubshs, 0, 29);
6514 GEN_VXFORM_ENV(vsubsws, 0, 30);
6515 GEN_VXFORM(vrlb, 2, 0);
6516 GEN_VXFORM(vrlh, 2, 1);
6517 GEN_VXFORM(vrlw, 2, 2);
6518 GEN_VXFORM(vsl, 2, 7);
6519 GEN_VXFORM(vsr, 2, 11);
6520 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6521 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6522 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6523 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6524 GEN_VXFORM_ENV(vpkshus, 7, 4);
6525 GEN_VXFORM_ENV(vpkswus, 7, 5);
6526 GEN_VXFORM_ENV(vpkshss, 7, 6);
6527 GEN_VXFORM_ENV(vpkswss, 7, 7);
6528 GEN_VXFORM(vpkpx, 7, 12);
6529 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6530 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6531 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6532 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6533 GEN_VXFORM_ENV(vsumsws, 4, 30);
6534 GEN_VXFORM_ENV(vaddfp, 5, 0);
6535 GEN_VXFORM_ENV(vsubfp, 5, 1);
6536 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6537 GEN_VXFORM_ENV(vminfp, 5, 17);
6538
6539 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6540 static void glue(gen_, name)(DisasContext *ctx) \
6541 { \
6542 TCGv_ptr ra, rb, rd; \
6543 if (unlikely(!ctx->altivec_enabled)) { \
6544 gen_exception(ctx, POWERPC_EXCP_VPU); \
6545 return; \
6546 } \
6547 ra = gen_avr_ptr(rA(ctx->opcode)); \
6548 rb = gen_avr_ptr(rB(ctx->opcode)); \
6549 rd = gen_avr_ptr(rD(ctx->opcode)); \
6550 gen_helper_##opname(cpu_env, rd, ra, rb); \
6551 tcg_temp_free_ptr(ra); \
6552 tcg_temp_free_ptr(rb); \
6553 tcg_temp_free_ptr(rd); \
6554 }
6555
6556 #define GEN_VXRFORM(name, opc2, opc3) \
6557 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6558 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6559
6560 GEN_VXRFORM(vcmpequb, 3, 0)
6561 GEN_VXRFORM(vcmpequh, 3, 1)
6562 GEN_VXRFORM(vcmpequw, 3, 2)
6563 GEN_VXRFORM(vcmpgtsb, 3, 12)
6564 GEN_VXRFORM(vcmpgtsh, 3, 13)
6565 GEN_VXRFORM(vcmpgtsw, 3, 14)
6566 GEN_VXRFORM(vcmpgtub, 3, 8)
6567 GEN_VXRFORM(vcmpgtuh, 3, 9)
6568 GEN_VXRFORM(vcmpgtuw, 3, 10)
6569 GEN_VXRFORM(vcmpeqfp, 3, 3)
6570 GEN_VXRFORM(vcmpgefp, 3, 7)
6571 GEN_VXRFORM(vcmpgtfp, 3, 11)
6572 GEN_VXRFORM(vcmpbfp, 3, 15)
6573
6574 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6575 static void glue(gen_, name)(DisasContext *ctx) \
6576 { \
6577 TCGv_ptr rd; \
6578 TCGv_i32 simm; \
6579 if (unlikely(!ctx->altivec_enabled)) { \
6580 gen_exception(ctx, POWERPC_EXCP_VPU); \
6581 return; \
6582 } \
6583 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6584 rd = gen_avr_ptr(rD(ctx->opcode)); \
6585 gen_helper_##name (rd, simm); \
6586 tcg_temp_free_i32(simm); \
6587 tcg_temp_free_ptr(rd); \
6588 }
6589
6590 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6591 GEN_VXFORM_SIMM(vspltish, 6, 13);
6592 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6593
6594 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6595 static void glue(gen_, name)(DisasContext *ctx) \
6596 { \
6597 TCGv_ptr rb, rd; \
6598 if (unlikely(!ctx->altivec_enabled)) { \
6599 gen_exception(ctx, POWERPC_EXCP_VPU); \
6600 return; \
6601 } \
6602 rb = gen_avr_ptr(rB(ctx->opcode)); \
6603 rd = gen_avr_ptr(rD(ctx->opcode)); \
6604 gen_helper_##name (rd, rb); \
6605 tcg_temp_free_ptr(rb); \
6606 tcg_temp_free_ptr(rd); \
6607 }
6608
6609 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6610 static void glue(gen_, name)(DisasContext *ctx) \
6611 { \
6612 TCGv_ptr rb, rd; \
6613 \
6614 if (unlikely(!ctx->altivec_enabled)) { \
6615 gen_exception(ctx, POWERPC_EXCP_VPU); \
6616 return; \
6617 } \
6618 rb = gen_avr_ptr(rB(ctx->opcode)); \
6619 rd = gen_avr_ptr(rD(ctx->opcode)); \
6620 gen_helper_##name(cpu_env, rd, rb); \
6621 tcg_temp_free_ptr(rb); \
6622 tcg_temp_free_ptr(rd); \
6623 }
6624
6625 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6626 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6627 GEN_VXFORM_NOA(vupklsb, 7, 10);
6628 GEN_VXFORM_NOA(vupklsh, 7, 11);
6629 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6630 GEN_VXFORM_NOA(vupklpx, 7, 15);
6631 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6632 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6633 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6634 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6635 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6636 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6637 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6638 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6639
6640 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6641 static void glue(gen_, name)(DisasContext *ctx) \
6642 { \
6643 TCGv_ptr rd; \
6644 TCGv_i32 simm; \
6645 if (unlikely(!ctx->altivec_enabled)) { \
6646 gen_exception(ctx, POWERPC_EXCP_VPU); \
6647 return; \
6648 } \
6649 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6650 rd = gen_avr_ptr(rD(ctx->opcode)); \
6651 gen_helper_##name (rd, simm); \
6652 tcg_temp_free_i32(simm); \
6653 tcg_temp_free_ptr(rd); \
6654 }
6655
6656 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6657 static void glue(gen_, name)(DisasContext *ctx) \
6658 { \
6659 TCGv_ptr rb, rd; \
6660 TCGv_i32 uimm; \
6661 if (unlikely(!ctx->altivec_enabled)) { \
6662 gen_exception(ctx, POWERPC_EXCP_VPU); \
6663 return; \
6664 } \
6665 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6666 rb = gen_avr_ptr(rB(ctx->opcode)); \
6667 rd = gen_avr_ptr(rD(ctx->opcode)); \
6668 gen_helper_##name (rd, rb, uimm); \
6669 tcg_temp_free_i32(uimm); \
6670 tcg_temp_free_ptr(rb); \
6671 tcg_temp_free_ptr(rd); \
6672 }
6673
6674 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6675 static void glue(gen_, name)(DisasContext *ctx) \
6676 { \
6677 TCGv_ptr rb, rd; \
6678 TCGv_i32 uimm; \
6679 \
6680 if (unlikely(!ctx->altivec_enabled)) { \
6681 gen_exception(ctx, POWERPC_EXCP_VPU); \
6682 return; \
6683 } \
6684 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6685 rb = gen_avr_ptr(rB(ctx->opcode)); \
6686 rd = gen_avr_ptr(rD(ctx->opcode)); \
6687 gen_helper_##name(cpu_env, rd, rb, uimm); \
6688 tcg_temp_free_i32(uimm); \
6689 tcg_temp_free_ptr(rb); \
6690 tcg_temp_free_ptr(rd); \
6691 }
6692
6693 GEN_VXFORM_UIMM(vspltb, 6, 8);
6694 GEN_VXFORM_UIMM(vsplth, 6, 9);
6695 GEN_VXFORM_UIMM(vspltw, 6, 10);
6696 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6697 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6698 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6699 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6700
6701 static void gen_vsldoi(DisasContext *ctx)
6702 {
6703 TCGv_ptr ra, rb, rd;
6704 TCGv_i32 sh;
6705 if (unlikely(!ctx->altivec_enabled)) {
6706 gen_exception(ctx, POWERPC_EXCP_VPU);
6707 return;
6708 }
6709 ra = gen_avr_ptr(rA(ctx->opcode));
6710 rb = gen_avr_ptr(rB(ctx->opcode));
6711 rd = gen_avr_ptr(rD(ctx->opcode));
6712 sh = tcg_const_i32(VSH(ctx->opcode));
6713 gen_helper_vsldoi (rd, ra, rb, sh);
6714 tcg_temp_free_ptr(ra);
6715 tcg_temp_free_ptr(rb);
6716 tcg_temp_free_ptr(rd);
6717 tcg_temp_free_i32(sh);
6718 }
6719
6720 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6721 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6722 { \
6723 TCGv_ptr ra, rb, rc, rd; \
6724 if (unlikely(!ctx->altivec_enabled)) { \
6725 gen_exception(ctx, POWERPC_EXCP_VPU); \
6726 return; \
6727 } \
6728 ra = gen_avr_ptr(rA(ctx->opcode)); \
6729 rb = gen_avr_ptr(rB(ctx->opcode)); \
6730 rc = gen_avr_ptr(rC(ctx->opcode)); \
6731 rd = gen_avr_ptr(rD(ctx->opcode)); \
6732 if (Rc(ctx->opcode)) { \
6733 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6734 } else { \
6735 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6736 } \
6737 tcg_temp_free_ptr(ra); \
6738 tcg_temp_free_ptr(rb); \
6739 tcg_temp_free_ptr(rc); \
6740 tcg_temp_free_ptr(rd); \
6741 }
6742
6743 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6744
6745 static void gen_vmladduhm(DisasContext *ctx)
6746 {
6747 TCGv_ptr ra, rb, rc, rd;
6748 if (unlikely(!ctx->altivec_enabled)) {
6749 gen_exception(ctx, POWERPC_EXCP_VPU);
6750 return;
6751 }
6752 ra = gen_avr_ptr(rA(ctx->opcode));
6753 rb = gen_avr_ptr(rB(ctx->opcode));
6754 rc = gen_avr_ptr(rC(ctx->opcode));
6755 rd = gen_avr_ptr(rD(ctx->opcode));
6756 gen_helper_vmladduhm(rd, ra, rb, rc);
6757 tcg_temp_free_ptr(ra);
6758 tcg_temp_free_ptr(rb);
6759 tcg_temp_free_ptr(rc);
6760 tcg_temp_free_ptr(rd);
6761 }
6762
6763 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6764 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6765 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6766 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6767 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6768
6769 /*** SPE extension ***/
6770 /* Register moves */
6771
6772
6773 static inline void gen_evmra(DisasContext *ctx)
6774 {
6775
6776 if (unlikely(!ctx->spe_enabled)) {
6777 gen_exception(ctx, POWERPC_EXCP_SPEU);
6778 return;
6779 }
6780
6781 #if defined(TARGET_PPC64)
6782 /* rD := rA */
6783 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6784
6785 /* spe_acc := rA */
6786 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6787 cpu_env,
6788 offsetof(CPUPPCState, spe_acc));
6789 #else
6790 TCGv_i64 tmp = tcg_temp_new_i64();
6791
6792 /* tmp := rA_lo + rA_hi << 32 */
6793 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6794
6795 /* spe_acc := tmp */
6796 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6797 tcg_temp_free_i64(tmp);
6798
6799 /* rD := rA */
6800 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6801 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6802 #endif
6803 }
6804
6805 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6806 {
6807 #if defined(TARGET_PPC64)
6808 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6809 #else
6810 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6811 #endif
6812 }
6813
6814 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6815 {
6816 #if defined(TARGET_PPC64)
6817 tcg_gen_mov_i64(cpu_gpr[reg], t);
6818 #else
6819 TCGv_i64 tmp = tcg_temp_new_i64();
6820 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6821 tcg_gen_shri_i64(tmp, t, 32);
6822 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6823 tcg_temp_free_i64(tmp);
6824 #endif
6825 }
6826
6827 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6828 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6829 { \
6830 if (Rc(ctx->opcode)) \
6831 gen_##name1(ctx); \
6832 else \
6833 gen_##name0(ctx); \
6834 }
6835
6836 /* Handler for undefined SPE opcodes */
6837 static inline void gen_speundef(DisasContext *ctx)
6838 {
6839 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6840 }
6841
6842 /* SPE logic */
6843 #if defined(TARGET_PPC64)
6844 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6845 static inline void gen_##name(DisasContext *ctx) \
6846 { \
6847 if (unlikely(!ctx->spe_enabled)) { \
6848 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6849 return; \
6850 } \
6851 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6852 cpu_gpr[rB(ctx->opcode)]); \
6853 }
6854 #else
6855 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6856 static inline void gen_##name(DisasContext *ctx) \
6857 { \
6858 if (unlikely(!ctx->spe_enabled)) { \
6859 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6860 return; \
6861 } \
6862 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6863 cpu_gpr[rB(ctx->opcode)]); \
6864 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6865 cpu_gprh[rB(ctx->opcode)]); \
6866 }
6867 #endif
6868
6869 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6870 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6871 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6872 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6873 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6874 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6875 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6876 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6877
6878 /* SPE logic immediate */
6879 #if defined(TARGET_PPC64)
6880 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6881 static inline void gen_##name(DisasContext *ctx) \
6882 { \
6883 if (unlikely(!ctx->spe_enabled)) { \
6884 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6885 return; \
6886 } \
6887 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6888 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6889 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6890 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6891 tcg_opi(t0, t0, rB(ctx->opcode)); \
6892 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6893 tcg_gen_trunc_i64_i32(t1, t2); \
6894 tcg_temp_free_i64(t2); \
6895 tcg_opi(t1, t1, rB(ctx->opcode)); \
6896 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6897 tcg_temp_free_i32(t0); \
6898 tcg_temp_free_i32(t1); \
6899 }
6900 #else
6901 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6902 static inline void gen_##name(DisasContext *ctx) \
6903 { \
6904 if (unlikely(!ctx->spe_enabled)) { \
6905 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6906 return; \
6907 } \
6908 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6909 rB(ctx->opcode)); \
6910 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6911 rB(ctx->opcode)); \
6912 }
6913 #endif
6914 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6915 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6916 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6917 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6918
6919 /* SPE arithmetic */
6920 #if defined(TARGET_PPC64)
6921 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6922 static inline void gen_##name(DisasContext *ctx) \
6923 { \
6924 if (unlikely(!ctx->spe_enabled)) { \
6925 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6926 return; \
6927 } \
6928 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6929 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6930 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6931 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6932 tcg_op(t0, t0); \
6933 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6934 tcg_gen_trunc_i64_i32(t1, t2); \
6935 tcg_temp_free_i64(t2); \
6936 tcg_op(t1, t1); \
6937 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6938 tcg_temp_free_i32(t0); \
6939 tcg_temp_free_i32(t1); \
6940 }
6941 #else
6942 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6943 static inline void gen_##name(DisasContext *ctx) \
6944 { \
6945 if (unlikely(!ctx->spe_enabled)) { \
6946 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6947 return; \
6948 } \
6949 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6950 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6951 }
6952 #endif
6953
6954 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
6955 {
6956 int l1 = gen_new_label();
6957 int l2 = gen_new_label();
6958
6959 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6960 tcg_gen_neg_i32(ret, arg1);
6961 tcg_gen_br(l2);
6962 gen_set_label(l1);
6963 tcg_gen_mov_i32(ret, arg1);
6964 gen_set_label(l2);
6965 }
6966 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6967 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6968 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6969 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6970 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
6971 {
6972 tcg_gen_addi_i32(ret, arg1, 0x8000);
6973 tcg_gen_ext16u_i32(ret, ret);
6974 }
6975 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6976 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6977 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6978
6979 #if defined(TARGET_PPC64)
6980 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6981 static inline void gen_##name(DisasContext *ctx) \
6982 { \
6983 if (unlikely(!ctx->spe_enabled)) { \
6984 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6985 return; \
6986 } \
6987 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6988 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6989 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6990 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6991 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6992 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6993 tcg_op(t0, t0, t2); \
6994 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6995 tcg_gen_trunc_i64_i32(t1, t3); \
6996 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6997 tcg_gen_trunc_i64_i32(t2, t3); \
6998 tcg_temp_free_i64(t3); \
6999 tcg_op(t1, t1, t2); \
7000 tcg_temp_free_i32(t2); \
7001 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7002 tcg_temp_free_i32(t0); \
7003 tcg_temp_free_i32(t1); \
7004 }
7005 #else
7006 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7007 static inline void gen_##name(DisasContext *ctx) \
7008 { \
7009 if (unlikely(!ctx->spe_enabled)) { \
7010 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7011 return; \
7012 } \
7013 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7014 cpu_gpr[rB(ctx->opcode)]); \
7015 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7016 cpu_gprh[rB(ctx->opcode)]); \
7017 }
7018 #endif
7019
7020 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7021 {
7022 TCGv_i32 t0;
7023 int l1, l2;
7024
7025 l1 = gen_new_label();
7026 l2 = gen_new_label();
7027 t0 = tcg_temp_local_new_i32();
7028 /* No error here: 6 bits are used */
7029 tcg_gen_andi_i32(t0, arg2, 0x3F);
7030 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7031 tcg_gen_shr_i32(ret, arg1, t0);
7032 tcg_gen_br(l2);
7033 gen_set_label(l1);
7034 tcg_gen_movi_i32(ret, 0);
7035 gen_set_label(l2);
7036 tcg_temp_free_i32(t0);
7037 }
7038 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7039 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7040 {
7041 TCGv_i32 t0;
7042 int l1, l2;
7043
7044 l1 = gen_new_label();
7045 l2 = gen_new_label();
7046 t0 = tcg_temp_local_new_i32();
7047 /* No error here: 6 bits are used */
7048 tcg_gen_andi_i32(t0, arg2, 0x3F);
7049 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7050 tcg_gen_sar_i32(ret, arg1, t0);
7051 tcg_gen_br(l2);
7052 gen_set_label(l1);
7053 tcg_gen_movi_i32(ret, 0);
7054 gen_set_label(l2);
7055 tcg_temp_free_i32(t0);
7056 }
7057 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7058 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7059 {
7060 TCGv_i32 t0;
7061 int l1, l2;
7062
7063 l1 = gen_new_label();
7064 l2 = gen_new_label();
7065 t0 = tcg_temp_local_new_i32();
7066 /* No error here: 6 bits are used */
7067 tcg_gen_andi_i32(t0, arg2, 0x3F);
7068 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7069 tcg_gen_shl_i32(ret, arg1, t0);
7070 tcg_gen_br(l2);
7071 gen_set_label(l1);
7072 tcg_gen_movi_i32(ret, 0);
7073 gen_set_label(l2);
7074 tcg_temp_free_i32(t0);
7075 }
7076 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7077 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7078 {
7079 TCGv_i32 t0 = tcg_temp_new_i32();
7080 tcg_gen_andi_i32(t0, arg2, 0x1F);
7081 tcg_gen_rotl_i32(ret, arg1, t0);
7082 tcg_temp_free_i32(t0);
7083 }
7084 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7085 static inline void gen_evmergehi(DisasContext *ctx)
7086 {
7087 if (unlikely(!ctx->spe_enabled)) {
7088 gen_exception(ctx, POWERPC_EXCP_SPEU);
7089 return;
7090 }
7091 #if defined(TARGET_PPC64)
7092 TCGv t0 = tcg_temp_new();
7093 TCGv t1 = tcg_temp_new();
7094 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7095 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7096 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7097 tcg_temp_free(t0);
7098 tcg_temp_free(t1);
7099 #else
7100 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7101 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7102 #endif
7103 }
7104 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7105 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7106 {
7107 tcg_gen_sub_i32(ret, arg2, arg1);
7108 }
7109 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7110
7111 /* SPE arithmetic immediate */
7112 #if defined(TARGET_PPC64)
7113 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7114 static inline void gen_##name(DisasContext *ctx) \
7115 { \
7116 if (unlikely(!ctx->spe_enabled)) { \
7117 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7118 return; \
7119 } \
7120 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7121 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7122 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7123 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7124 tcg_op(t0, t0, rA(ctx->opcode)); \
7125 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7126 tcg_gen_trunc_i64_i32(t1, t2); \
7127 tcg_temp_free_i64(t2); \
7128 tcg_op(t1, t1, rA(ctx->opcode)); \
7129 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7130 tcg_temp_free_i32(t0); \
7131 tcg_temp_free_i32(t1); \
7132 }
7133 #else
7134 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7135 static inline void gen_##name(DisasContext *ctx) \
7136 { \
7137 if (unlikely(!ctx->spe_enabled)) { \
7138 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7139 return; \
7140 } \
7141 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7142 rA(ctx->opcode)); \
7143 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7144 rA(ctx->opcode)); \
7145 }
7146 #endif
7147 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7148 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7149
7150 /* SPE comparison */
7151 #if defined(TARGET_PPC64)
7152 #define GEN_SPEOP_COMP(name, tcg_cond) \
7153 static inline void gen_##name(DisasContext *ctx) \
7154 { \
7155 if (unlikely(!ctx->spe_enabled)) { \
7156 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7157 return; \
7158 } \
7159 int l1 = gen_new_label(); \
7160 int l2 = gen_new_label(); \
7161 int l3 = gen_new_label(); \
7162 int l4 = gen_new_label(); \
7163 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7164 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7165 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7166 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7167 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7168 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7169 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7170 tcg_gen_br(l2); \
7171 gen_set_label(l1); \
7172 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7173 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7174 gen_set_label(l2); \
7175 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7176 tcg_gen_trunc_i64_i32(t0, t2); \
7177 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7178 tcg_gen_trunc_i64_i32(t1, t2); \
7179 tcg_temp_free_i64(t2); \
7180 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7181 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7182 ~(CRF_CH | CRF_CH_AND_CL)); \
7183 tcg_gen_br(l4); \
7184 gen_set_label(l3); \
7185 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7186 CRF_CH | CRF_CH_OR_CL); \
7187 gen_set_label(l4); \
7188 tcg_temp_free_i32(t0); \
7189 tcg_temp_free_i32(t1); \
7190 }
7191 #else
7192 #define GEN_SPEOP_COMP(name, tcg_cond) \
7193 static inline void gen_##name(DisasContext *ctx) \
7194 { \
7195 if (unlikely(!ctx->spe_enabled)) { \
7196 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7197 return; \
7198 } \
7199 int l1 = gen_new_label(); \
7200 int l2 = gen_new_label(); \
7201 int l3 = gen_new_label(); \
7202 int l4 = gen_new_label(); \
7203 \
7204 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7205 cpu_gpr[rB(ctx->opcode)], l1); \
7206 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7207 tcg_gen_br(l2); \
7208 gen_set_label(l1); \
7209 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7210 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7211 gen_set_label(l2); \
7212 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7213 cpu_gprh[rB(ctx->opcode)], l3); \
7214 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7215 ~(CRF_CH | CRF_CH_AND_CL)); \
7216 tcg_gen_br(l4); \
7217 gen_set_label(l3); \
7218 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7219 CRF_CH | CRF_CH_OR_CL); \
7220 gen_set_label(l4); \
7221 }
7222 #endif
7223 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7224 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7225 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7226 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7227 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7228
7229 /* SPE misc */
7230 static inline void gen_brinc(DisasContext *ctx)
7231 {
7232 /* Note: brinc is usable even if SPE is disabled */
7233 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7234 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7235 }
7236 static inline void gen_evmergelo(DisasContext *ctx)
7237 {
7238 if (unlikely(!ctx->spe_enabled)) {
7239 gen_exception(ctx, POWERPC_EXCP_SPEU);
7240 return;
7241 }
7242 #if defined(TARGET_PPC64)
7243 TCGv t0 = tcg_temp_new();
7244 TCGv t1 = tcg_temp_new();
7245 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7246 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7247 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7248 tcg_temp_free(t0);
7249 tcg_temp_free(t1);
7250 #else
7251 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7252 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7253 #endif
7254 }
7255 static inline void gen_evmergehilo(DisasContext *ctx)
7256 {
7257 if (unlikely(!ctx->spe_enabled)) {
7258 gen_exception(ctx, POWERPC_EXCP_SPEU);
7259 return;
7260 }
7261 #if defined(TARGET_PPC64)
7262 TCGv t0 = tcg_temp_new();
7263 TCGv t1 = tcg_temp_new();
7264 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7265 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7266 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7267 tcg_temp_free(t0);
7268 tcg_temp_free(t1);
7269 #else
7270 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7271 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7272 #endif
7273 }
7274 static inline void gen_evmergelohi(DisasContext *ctx)
7275 {
7276 if (unlikely(!ctx->spe_enabled)) {
7277 gen_exception(ctx, POWERPC_EXCP_SPEU);
7278 return;
7279 }
7280 #if defined(TARGET_PPC64)
7281 TCGv t0 = tcg_temp_new();
7282 TCGv t1 = tcg_temp_new();
7283 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7284 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7285 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7286 tcg_temp_free(t0);
7287 tcg_temp_free(t1);
7288 #else
7289 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7290 TCGv_i32 tmp = tcg_temp_new_i32();
7291 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7292 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7293 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7294 tcg_temp_free_i32(tmp);
7295 } else {
7296 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7297 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7298 }
7299 #endif
7300 }
7301 static inline void gen_evsplati(DisasContext *ctx)
7302 {
7303 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7304
7305 #if defined(TARGET_PPC64)
7306 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7307 #else
7308 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7309 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7310 #endif
7311 }
7312 static inline void gen_evsplatfi(DisasContext *ctx)
7313 {
7314 uint64_t imm = rA(ctx->opcode) << 27;
7315
7316 #if defined(TARGET_PPC64)
7317 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7318 #else
7319 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7320 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7321 #endif
7322 }
7323
7324 static inline void gen_evsel(DisasContext *ctx)
7325 {
7326 int l1 = gen_new_label();
7327 int l2 = gen_new_label();
7328 int l3 = gen_new_label();
7329 int l4 = gen_new_label();
7330 TCGv_i32 t0 = tcg_temp_local_new_i32();
7331 #if defined(TARGET_PPC64)
7332 TCGv t1 = tcg_temp_local_new();
7333 TCGv t2 = tcg_temp_local_new();
7334 #endif
7335 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7336 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7337 #if defined(TARGET_PPC64)
7338 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7339 #else
7340 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7341 #endif
7342 tcg_gen_br(l2);
7343 gen_set_label(l1);
7344 #if defined(TARGET_PPC64)
7345 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7346 #else
7347 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7348 #endif
7349 gen_set_label(l2);
7350 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7351 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7352 #if defined(TARGET_PPC64)
7353 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7354 #else
7355 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7356 #endif
7357 tcg_gen_br(l4);
7358 gen_set_label(l3);
7359 #if defined(TARGET_PPC64)
7360 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7361 #else
7362 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7363 #endif
7364 gen_set_label(l4);
7365 tcg_temp_free_i32(t0);
7366 #if defined(TARGET_PPC64)
7367 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7368 tcg_temp_free(t1);
7369 tcg_temp_free(t2);
7370 #endif
7371 }
7372
7373 static void gen_evsel0(DisasContext *ctx)
7374 {
7375 gen_evsel(ctx);
7376 }
7377
7378 static void gen_evsel1(DisasContext *ctx)
7379 {
7380 gen_evsel(ctx);
7381 }
7382
7383 static void gen_evsel2(DisasContext *ctx)
7384 {
7385 gen_evsel(ctx);
7386 }
7387
7388 static void gen_evsel3(DisasContext *ctx)
7389 {
7390 gen_evsel(ctx);
7391 }
7392
7393 /* Multiply */
7394
7395 static inline void gen_evmwumi(DisasContext *ctx)
7396 {
7397 TCGv_i64 t0, t1;
7398
7399 if (unlikely(!ctx->spe_enabled)) {
7400 gen_exception(ctx, POWERPC_EXCP_SPEU);
7401 return;
7402 }
7403
7404 t0 = tcg_temp_new_i64();
7405 t1 = tcg_temp_new_i64();
7406
7407 /* t0 := rA; t1 := rB */
7408 #if defined(TARGET_PPC64)
7409 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7410 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7411 #else
7412 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7413 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7414 #endif
7415
7416 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7417
7418 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7419
7420 tcg_temp_free_i64(t0);
7421 tcg_temp_free_i64(t1);
7422 }
7423
7424 static inline void gen_evmwumia(DisasContext *ctx)
7425 {
7426 TCGv_i64 tmp;
7427
7428 if (unlikely(!ctx->spe_enabled)) {
7429 gen_exception(ctx, POWERPC_EXCP_SPEU);
7430 return;
7431 }
7432
7433 gen_evmwumi(ctx); /* rD := rA * rB */
7434
7435 tmp = tcg_temp_new_i64();
7436
7437 /* acc := rD */
7438 gen_load_gpr64(tmp, rD(ctx->opcode));
7439 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7440 tcg_temp_free_i64(tmp);
7441 }
7442
7443 static inline void gen_evmwumiaa(DisasContext *ctx)
7444 {
7445 TCGv_i64 acc;
7446 TCGv_i64 tmp;
7447
7448 if (unlikely(!ctx->spe_enabled)) {
7449 gen_exception(ctx, POWERPC_EXCP_SPEU);
7450 return;
7451 }
7452
7453 gen_evmwumi(ctx); /* rD := rA * rB */
7454
7455 acc = tcg_temp_new_i64();
7456 tmp = tcg_temp_new_i64();
7457
7458 /* tmp := rD */
7459 gen_load_gpr64(tmp, rD(ctx->opcode));
7460
7461 /* Load acc */
7462 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7463
7464 /* acc := tmp + acc */
7465 tcg_gen_add_i64(acc, acc, tmp);
7466
7467 /* Store acc */
7468 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7469
7470 /* rD := acc */
7471 gen_store_gpr64(rD(ctx->opcode), acc);
7472
7473 tcg_temp_free_i64(acc);
7474 tcg_temp_free_i64(tmp);
7475 }
7476
7477 static inline void gen_evmwsmi(DisasContext *ctx)
7478 {
7479 TCGv_i64 t0, t1;
7480
7481 if (unlikely(!ctx->spe_enabled)) {
7482 gen_exception(ctx, POWERPC_EXCP_SPEU);
7483 return;
7484 }
7485
7486 t0 = tcg_temp_new_i64();
7487 t1 = tcg_temp_new_i64();
7488
7489 /* t0 := rA; t1 := rB */
7490 #if defined(TARGET_PPC64)
7491 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7492 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7493 #else
7494 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7495 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7496 #endif
7497
7498 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7499
7500 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7501
7502 tcg_temp_free_i64(t0);
7503 tcg_temp_free_i64(t1);
7504 }
7505
7506 static inline void gen_evmwsmia(DisasContext *ctx)
7507 {
7508 TCGv_i64 tmp;
7509
7510 gen_evmwsmi(ctx); /* rD := rA * rB */
7511
7512 tmp = tcg_temp_new_i64();
7513
7514 /* acc := rD */
7515 gen_load_gpr64(tmp, rD(ctx->opcode));
7516 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7517
7518 tcg_temp_free_i64(tmp);
7519 }
7520
7521 static inline void gen_evmwsmiaa(DisasContext *ctx)
7522 {
7523 TCGv_i64 acc = tcg_temp_new_i64();
7524 TCGv_i64 tmp = tcg_temp_new_i64();
7525
7526 gen_evmwsmi(ctx); /* rD := rA * rB */
7527
7528 acc = tcg_temp_new_i64();
7529 tmp = tcg_temp_new_i64();
7530
7531 /* tmp := rD */
7532 gen_load_gpr64(tmp, rD(ctx->opcode));
7533
7534 /* Load acc */
7535 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7536
7537 /* acc := tmp + acc */
7538 tcg_gen_add_i64(acc, acc, tmp);
7539
7540 /* Store acc */
7541 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7542
7543 /* rD := acc */
7544 gen_store_gpr64(rD(ctx->opcode), acc);
7545
7546 tcg_temp_free_i64(acc);
7547 tcg_temp_free_i64(tmp);
7548 }
7549
7550 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7551 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7552 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7553 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7554 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7555 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7556 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7557 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7558 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7559 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7560 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7561 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7562 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7563 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7564 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7565 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7566 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7567 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7568 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7569 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7570 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7571 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7572 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7573 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7574 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7575 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7576 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7577 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7578 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7579
7580 /* SPE load and stores */
7581 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7582 {
7583 target_ulong uimm = rB(ctx->opcode);
7584
7585 if (rA(ctx->opcode) == 0) {
7586 tcg_gen_movi_tl(EA, uimm << sh);
7587 } else {
7588 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7589 #if defined(TARGET_PPC64)
7590 if (!ctx->sf_mode) {
7591 tcg_gen_ext32u_tl(EA, EA);
7592 }
7593 #endif
7594 }
7595 }
7596
7597 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7598 {
7599 #if defined(TARGET_PPC64)
7600 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7601 #else
7602 TCGv_i64 t0 = tcg_temp_new_i64();
7603 gen_qemu_ld64(ctx, t0, addr);
7604 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7605 tcg_gen_shri_i64(t0, t0, 32);
7606 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7607 tcg_temp_free_i64(t0);
7608 #endif
7609 }
7610
7611 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7612 {
7613 #if defined(TARGET_PPC64)
7614 TCGv t0 = tcg_temp_new();
7615 gen_qemu_ld32u(ctx, t0, addr);
7616 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7617 gen_addr_add(ctx, addr, addr, 4);
7618 gen_qemu_ld32u(ctx, t0, addr);
7619 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7620 tcg_temp_free(t0);
7621 #else
7622 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7623 gen_addr_add(ctx, addr, addr, 4);
7624 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7625 #endif
7626 }
7627
7628 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7629 {
7630 TCGv t0 = tcg_temp_new();
7631 #if defined(TARGET_PPC64)
7632 gen_qemu_ld16u(ctx, t0, addr);
7633 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7634 gen_addr_add(ctx, addr, addr, 2);
7635 gen_qemu_ld16u(ctx, t0, addr);
7636 tcg_gen_shli_tl(t0, t0, 32);
7637 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7638 gen_addr_add(ctx, addr, addr, 2);
7639 gen_qemu_ld16u(ctx, t0, addr);
7640 tcg_gen_shli_tl(t0, t0, 16);
7641 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7642 gen_addr_add(ctx, addr, addr, 2);
7643 gen_qemu_ld16u(ctx, t0, addr);
7644 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7645 #else
7646 gen_qemu_ld16u(ctx, t0, addr);
7647 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7648 gen_addr_add(ctx, addr, addr, 2);
7649 gen_qemu_ld16u(ctx, t0, addr);
7650 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7651 gen_addr_add(ctx, addr, addr, 2);
7652 gen_qemu_ld16u(ctx, t0, addr);
7653 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7654 gen_addr_add(ctx, addr, addr, 2);
7655 gen_qemu_ld16u(ctx, t0, addr);
7656 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7657 #endif
7658 tcg_temp_free(t0);
7659 }
7660
7661 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7662 {
7663 TCGv t0 = tcg_temp_new();
7664 gen_qemu_ld16u(ctx, t0, addr);
7665 #if defined(TARGET_PPC64)
7666 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7667 tcg_gen_shli_tl(t0, t0, 16);
7668 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7669 #else
7670 tcg_gen_shli_tl(t0, t0, 16);
7671 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7672 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7673 #endif
7674 tcg_temp_free(t0);
7675 }
7676
7677 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7678 {
7679 TCGv t0 = tcg_temp_new();
7680 gen_qemu_ld16u(ctx, t0, addr);
7681 #if defined(TARGET_PPC64)
7682 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7683 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7684 #else
7685 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7686 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7687 #endif
7688 tcg_temp_free(t0);
7689 }
7690
7691 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7692 {
7693 TCGv t0 = tcg_temp_new();
7694 gen_qemu_ld16s(ctx, t0, addr);
7695 #if defined(TARGET_PPC64)
7696 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7697 tcg_gen_ext32u_tl(t0, t0);
7698 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7699 #else
7700 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7701 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7702 #endif
7703 tcg_temp_free(t0);
7704 }
7705
7706 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7707 {
7708 TCGv t0 = tcg_temp_new();
7709 #if defined(TARGET_PPC64)
7710 gen_qemu_ld16u(ctx, t0, addr);
7711 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7712 gen_addr_add(ctx, addr, addr, 2);
7713 gen_qemu_ld16u(ctx, t0, addr);
7714 tcg_gen_shli_tl(t0, t0, 16);
7715 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7716 #else
7717 gen_qemu_ld16u(ctx, t0, addr);
7718 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7719 gen_addr_add(ctx, addr, addr, 2);
7720 gen_qemu_ld16u(ctx, t0, addr);
7721 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7722 #endif
7723 tcg_temp_free(t0);
7724 }
7725
7726 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7727 {
7728 #if defined(TARGET_PPC64)
7729 TCGv t0 = tcg_temp_new();
7730 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7731 gen_addr_add(ctx, addr, addr, 2);
7732 gen_qemu_ld16u(ctx, t0, addr);
7733 tcg_gen_shli_tl(t0, t0, 32);
7734 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7735 tcg_temp_free(t0);
7736 #else
7737 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7738 gen_addr_add(ctx, addr, addr, 2);
7739 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7740 #endif
7741 }
7742
7743 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7744 {
7745 #if defined(TARGET_PPC64)
7746 TCGv t0 = tcg_temp_new();
7747 gen_qemu_ld16s(ctx, t0, addr);
7748 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7749 gen_addr_add(ctx, addr, addr, 2);
7750 gen_qemu_ld16s(ctx, t0, addr);
7751 tcg_gen_shli_tl(t0, t0, 32);
7752 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7753 tcg_temp_free(t0);
7754 #else
7755 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7756 gen_addr_add(ctx, addr, addr, 2);
7757 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7758 #endif
7759 }
7760
7761 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7762 {
7763 TCGv t0 = tcg_temp_new();
7764 gen_qemu_ld32u(ctx, t0, addr);
7765 #if defined(TARGET_PPC64)
7766 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7767 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7768 #else
7769 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7770 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7771 #endif
7772 tcg_temp_free(t0);
7773 }
7774
7775 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7776 {
7777 TCGv t0 = tcg_temp_new();
7778 #if defined(TARGET_PPC64)
7779 gen_qemu_ld16u(ctx, t0, addr);
7780 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7781 tcg_gen_shli_tl(t0, t0, 32);
7782 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7783 gen_addr_add(ctx, addr, addr, 2);
7784 gen_qemu_ld16u(ctx, t0, addr);
7785 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7786 tcg_gen_shli_tl(t0, t0, 16);
7787 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7788 #else
7789 gen_qemu_ld16u(ctx, t0, addr);
7790 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7791 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7792 gen_addr_add(ctx, addr, addr, 2);
7793 gen_qemu_ld16u(ctx, t0, addr);
7794 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7795 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7796 #endif
7797 tcg_temp_free(t0);
7798 }
7799
7800 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7801 {
7802 #if defined(TARGET_PPC64)
7803 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7804 #else
7805 TCGv_i64 t0 = tcg_temp_new_i64();
7806 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7807 gen_qemu_st64(ctx, t0, addr);
7808 tcg_temp_free_i64(t0);
7809 #endif
7810 }
7811
7812 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7813 {
7814 #if defined(TARGET_PPC64)
7815 TCGv t0 = tcg_temp_new();
7816 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7817 gen_qemu_st32(ctx, t0, addr);
7818 tcg_temp_free(t0);
7819 #else
7820 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7821 #endif
7822 gen_addr_add(ctx, addr, addr, 4);
7823 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7824 }
7825
7826 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7827 {
7828 TCGv t0 = tcg_temp_new();
7829 #if defined(TARGET_PPC64)
7830 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7831 #else
7832 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7833 #endif
7834 gen_qemu_st16(ctx, t0, addr);
7835 gen_addr_add(ctx, addr, addr, 2);
7836 #if defined(TARGET_PPC64)
7837 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7838 gen_qemu_st16(ctx, t0, addr);
7839 #else
7840 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7841 #endif
7842 gen_addr_add(ctx, addr, addr, 2);
7843 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7844 gen_qemu_st16(ctx, t0, addr);
7845 tcg_temp_free(t0);
7846 gen_addr_add(ctx, addr, addr, 2);
7847 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7848 }
7849
7850 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7851 {
7852 TCGv t0 = tcg_temp_new();
7853 #if defined(TARGET_PPC64)
7854 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7855 #else
7856 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7857 #endif
7858 gen_qemu_st16(ctx, t0, addr);
7859 gen_addr_add(ctx, addr, addr, 2);
7860 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7861 gen_qemu_st16(ctx, t0, addr);
7862 tcg_temp_free(t0);
7863 }
7864
7865 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7866 {
7867 #if defined(TARGET_PPC64)
7868 TCGv t0 = tcg_temp_new();
7869 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7870 gen_qemu_st16(ctx, t0, addr);
7871 tcg_temp_free(t0);
7872 #else
7873 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7874 #endif
7875 gen_addr_add(ctx, addr, addr, 2);
7876 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7877 }
7878
7879 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7880 {
7881 #if defined(TARGET_PPC64)
7882 TCGv t0 = tcg_temp_new();
7883 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7884 gen_qemu_st32(ctx, t0, addr);
7885 tcg_temp_free(t0);
7886 #else
7887 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7888 #endif
7889 }
7890
7891 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7892 {
7893 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7894 }
7895
7896 #define GEN_SPEOP_LDST(name, opc2, sh) \
7897 static void glue(gen_, name)(DisasContext *ctx) \
7898 { \
7899 TCGv t0; \
7900 if (unlikely(!ctx->spe_enabled)) { \
7901 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7902 return; \
7903 } \
7904 gen_set_access_type(ctx, ACCESS_INT); \
7905 t0 = tcg_temp_new(); \
7906 if (Rc(ctx->opcode)) { \
7907 gen_addr_spe_imm_index(ctx, t0, sh); \
7908 } else { \
7909 gen_addr_reg_index(ctx, t0); \
7910 } \
7911 gen_op_##name(ctx, t0); \
7912 tcg_temp_free(t0); \
7913 }
7914
7915 GEN_SPEOP_LDST(evldd, 0x00, 3);
7916 GEN_SPEOP_LDST(evldw, 0x01, 3);
7917 GEN_SPEOP_LDST(evldh, 0x02, 3);
7918 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7919 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7920 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7921 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7922 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7923 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7924 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7925 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7926
7927 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7928 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7929 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7930 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7931 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7932 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7933 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7934
7935 /* Multiply and add - TODO */
7936 #if 0
7937 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
7938 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7939 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7940 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7941 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7942 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7943 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7944 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7945 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7946 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7947 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7948 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7949
7950 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7951 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7952 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7953 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7954 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7955 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7956 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7957 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7958 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7959 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7960 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7961 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7962
7963 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7964 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7965 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7966 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7967 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
7968
7969 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7970 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7971 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7972 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7973 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7974 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7975 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7976 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7977 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7978 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7979 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7980 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7981
7982 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7983 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7984 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7985 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7986
7987 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7988 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7989 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7990 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7991 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7992 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7993 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7994 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7995 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7996 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7997 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7998 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7999
8000 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8001 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8002 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8003 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8004 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8005 #endif
8006
8007 /*** SPE floating-point extension ***/
8008 #if defined(TARGET_PPC64)
8009 #define GEN_SPEFPUOP_CONV_32_32(name) \
8010 static inline void gen_##name(DisasContext *ctx) \
8011 { \
8012 TCGv_i32 t0; \
8013 TCGv t1; \
8014 t0 = tcg_temp_new_i32(); \
8015 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8016 gen_helper_##name(t0, cpu_env, t0); \
8017 t1 = tcg_temp_new(); \
8018 tcg_gen_extu_i32_tl(t1, t0); \
8019 tcg_temp_free_i32(t0); \
8020 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8021 0xFFFFFFFF00000000ULL); \
8022 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8023 tcg_temp_free(t1); \
8024 }
8025 #define GEN_SPEFPUOP_CONV_32_64(name) \
8026 static inline void gen_##name(DisasContext *ctx) \
8027 { \
8028 TCGv_i32 t0; \
8029 TCGv t1; \
8030 t0 = tcg_temp_new_i32(); \
8031 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8032 t1 = tcg_temp_new(); \
8033 tcg_gen_extu_i32_tl(t1, t0); \
8034 tcg_temp_free_i32(t0); \
8035 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8036 0xFFFFFFFF00000000ULL); \
8037 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8038 tcg_temp_free(t1); \
8039 }
8040 #define GEN_SPEFPUOP_CONV_64_32(name) \
8041 static inline void gen_##name(DisasContext *ctx) \
8042 { \
8043 TCGv_i32 t0 = tcg_temp_new_i32(); \
8044 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8045 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8046 tcg_temp_free_i32(t0); \
8047 }
8048 #define GEN_SPEFPUOP_CONV_64_64(name) \
8049 static inline void gen_##name(DisasContext *ctx) \
8050 { \
8051 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8052 cpu_gpr[rB(ctx->opcode)]); \
8053 }
8054 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8055 static inline void gen_##name(DisasContext *ctx) \
8056 { \
8057 TCGv_i32 t0, t1; \
8058 TCGv_i64 t2; \
8059 if (unlikely(!ctx->spe_enabled)) { \
8060 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8061 return; \
8062 } \
8063 t0 = tcg_temp_new_i32(); \
8064 t1 = tcg_temp_new_i32(); \
8065 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8066 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8067 gen_helper_##name(t0, cpu_env, t0, t1); \
8068 tcg_temp_free_i32(t1); \
8069 t2 = tcg_temp_new(); \
8070 tcg_gen_extu_i32_tl(t2, t0); \
8071 tcg_temp_free_i32(t0); \
8072 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8073 0xFFFFFFFF00000000ULL); \
8074 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8075 tcg_temp_free(t2); \
8076 }
8077 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8078 static inline void gen_##name(DisasContext *ctx) \
8079 { \
8080 if (unlikely(!ctx->spe_enabled)) { \
8081 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8082 return; \
8083 } \
8084 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8085 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8086 }
8087 #define GEN_SPEFPUOP_COMP_32(name) \
8088 static inline void gen_##name(DisasContext *ctx) \
8089 { \
8090 TCGv_i32 t0, t1; \
8091 if (unlikely(!ctx->spe_enabled)) { \
8092 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8093 return; \
8094 } \
8095 t0 = tcg_temp_new_i32(); \
8096 t1 = tcg_temp_new_i32(); \
8097 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8098 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8099 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8100 tcg_temp_free_i32(t0); \
8101 tcg_temp_free_i32(t1); \
8102 }
8103 #define GEN_SPEFPUOP_COMP_64(name) \
8104 static inline void gen_##name(DisasContext *ctx) \
8105 { \
8106 if (unlikely(!ctx->spe_enabled)) { \
8107 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8108 return; \
8109 } \
8110 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8111 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8112 }
8113 #else
8114 #define GEN_SPEFPUOP_CONV_32_32(name) \
8115 static inline void gen_##name(DisasContext *ctx) \
8116 { \
8117 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8118 cpu_gpr[rB(ctx->opcode)]); \
8119 }
8120 #define GEN_SPEFPUOP_CONV_32_64(name) \
8121 static inline void gen_##name(DisasContext *ctx) \
8122 { \
8123 TCGv_i64 t0 = tcg_temp_new_i64(); \
8124 gen_load_gpr64(t0, rB(ctx->opcode)); \
8125 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8126 tcg_temp_free_i64(t0); \
8127 }
8128 #define GEN_SPEFPUOP_CONV_64_32(name) \
8129 static inline void gen_##name(DisasContext *ctx) \
8130 { \
8131 TCGv_i64 t0 = tcg_temp_new_i64(); \
8132 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8133 gen_store_gpr64(rD(ctx->opcode), t0); \
8134 tcg_temp_free_i64(t0); \
8135 }
8136 #define GEN_SPEFPUOP_CONV_64_64(name) \
8137 static inline void gen_##name(DisasContext *ctx) \
8138 { \
8139 TCGv_i64 t0 = tcg_temp_new_i64(); \
8140 gen_load_gpr64(t0, rB(ctx->opcode)); \
8141 gen_helper_##name(t0, cpu_env, t0); \
8142 gen_store_gpr64(rD(ctx->opcode), t0); \
8143 tcg_temp_free_i64(t0); \
8144 }
8145 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8146 static inline void gen_##name(DisasContext *ctx) \
8147 { \
8148 if (unlikely(!ctx->spe_enabled)) { \
8149 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8150 return; \
8151 } \
8152 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8153 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8154 }
8155 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8156 static inline void gen_##name(DisasContext *ctx) \
8157 { \
8158 TCGv_i64 t0, t1; \
8159 if (unlikely(!ctx->spe_enabled)) { \
8160 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8161 return; \
8162 } \
8163 t0 = tcg_temp_new_i64(); \
8164 t1 = tcg_temp_new_i64(); \
8165 gen_load_gpr64(t0, rA(ctx->opcode)); \
8166 gen_load_gpr64(t1, rB(ctx->opcode)); \
8167 gen_helper_##name(t0, cpu_env, t0, t1); \
8168 gen_store_gpr64(rD(ctx->opcode), t0); \
8169 tcg_temp_free_i64(t0); \
8170 tcg_temp_free_i64(t1); \
8171 }
8172 #define GEN_SPEFPUOP_COMP_32(name) \
8173 static inline void gen_##name(DisasContext *ctx) \
8174 { \
8175 if (unlikely(!ctx->spe_enabled)) { \
8176 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8177 return; \
8178 } \
8179 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8180 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8181 }
8182 #define GEN_SPEFPUOP_COMP_64(name) \
8183 static inline void gen_##name(DisasContext *ctx) \
8184 { \
8185 TCGv_i64 t0, t1; \
8186 if (unlikely(!ctx->spe_enabled)) { \
8187 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8188 return; \
8189 } \
8190 t0 = tcg_temp_new_i64(); \
8191 t1 = tcg_temp_new_i64(); \
8192 gen_load_gpr64(t0, rA(ctx->opcode)); \
8193 gen_load_gpr64(t1, rB(ctx->opcode)); \
8194 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8195 tcg_temp_free_i64(t0); \
8196 tcg_temp_free_i64(t1); \
8197 }
8198 #endif
8199
8200 /* Single precision floating-point vectors operations */
8201 /* Arithmetic */
8202 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8203 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8204 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8205 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8206 static inline void gen_evfsabs(DisasContext *ctx)
8207 {
8208 if (unlikely(!ctx->spe_enabled)) {
8209 gen_exception(ctx, POWERPC_EXCP_SPEU);
8210 return;
8211 }
8212 #if defined(TARGET_PPC64)
8213 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8214 #else
8215 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8216 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8217 #endif
8218 }
8219 static inline void gen_evfsnabs(DisasContext *ctx)
8220 {
8221 if (unlikely(!ctx->spe_enabled)) {
8222 gen_exception(ctx, POWERPC_EXCP_SPEU);
8223 return;
8224 }
8225 #if defined(TARGET_PPC64)
8226 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8227 #else
8228 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8229 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8230 #endif
8231 }
8232 static inline void gen_evfsneg(DisasContext *ctx)
8233 {
8234 if (unlikely(!ctx->spe_enabled)) {
8235 gen_exception(ctx, POWERPC_EXCP_SPEU);
8236 return;
8237 }
8238 #if defined(TARGET_PPC64)
8239 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8240 #else
8241 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8242 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8243 #endif
8244 }
8245
8246 /* Conversion */
8247 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8248 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8249 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8250 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8251 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8252 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8253 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8254 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8255 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8256 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8257
8258 /* Comparison */
8259 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8260 GEN_SPEFPUOP_COMP_64(evfscmplt);
8261 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8262 GEN_SPEFPUOP_COMP_64(evfststgt);
8263 GEN_SPEFPUOP_COMP_64(evfststlt);
8264 GEN_SPEFPUOP_COMP_64(evfststeq);
8265
8266 /* Opcodes definitions */
8267 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8268 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8269 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8270 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8271 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8272 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8273 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8274 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8275 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8276 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8277 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8278 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8279 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8280 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8281
8282 /* Single precision floating-point operations */
8283 /* Arithmetic */
8284 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8285 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8286 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8287 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8288 static inline void gen_efsabs(DisasContext *ctx)
8289 {
8290 if (unlikely(!ctx->spe_enabled)) {
8291 gen_exception(ctx, POWERPC_EXCP_SPEU);
8292 return;
8293 }
8294 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8295 }
8296 static inline void gen_efsnabs(DisasContext *ctx)
8297 {
8298 if (unlikely(!ctx->spe_enabled)) {
8299 gen_exception(ctx, POWERPC_EXCP_SPEU);
8300 return;
8301 }
8302 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8303 }
8304 static inline void gen_efsneg(DisasContext *ctx)
8305 {
8306 if (unlikely(!ctx->spe_enabled)) {
8307 gen_exception(ctx, POWERPC_EXCP_SPEU);
8308 return;
8309 }
8310 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8311 }
8312
8313 /* Conversion */
8314 GEN_SPEFPUOP_CONV_32_32(efscfui);
8315 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8316 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8317 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8318 GEN_SPEFPUOP_CONV_32_32(efsctui);
8319 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8320 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8321 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8322 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8323 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8324 GEN_SPEFPUOP_CONV_32_64(efscfd);
8325
8326 /* Comparison */
8327 GEN_SPEFPUOP_COMP_32(efscmpgt);
8328 GEN_SPEFPUOP_COMP_32(efscmplt);
8329 GEN_SPEFPUOP_COMP_32(efscmpeq);
8330 GEN_SPEFPUOP_COMP_32(efststgt);
8331 GEN_SPEFPUOP_COMP_32(efststlt);
8332 GEN_SPEFPUOP_COMP_32(efststeq);
8333
8334 /* Opcodes definitions */
8335 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8336 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8337 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8338 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8339 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8340 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8341 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8342 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8343 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8344 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8345 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8346 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8347 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8348 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8349
8350 /* Double precision floating-point operations */
8351 /* Arithmetic */
8352 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8353 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8354 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8355 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8356 static inline void gen_efdabs(DisasContext *ctx)
8357 {
8358 if (unlikely(!ctx->spe_enabled)) {
8359 gen_exception(ctx, POWERPC_EXCP_SPEU);
8360 return;
8361 }
8362 #if defined(TARGET_PPC64)
8363 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8364 #else
8365 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8366 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8367 #endif
8368 }
8369 static inline void gen_efdnabs(DisasContext *ctx)
8370 {
8371 if (unlikely(!ctx->spe_enabled)) {
8372 gen_exception(ctx, POWERPC_EXCP_SPEU);
8373 return;
8374 }
8375 #if defined(TARGET_PPC64)
8376 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8377 #else
8378 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8379 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8380 #endif
8381 }
8382 static inline void gen_efdneg(DisasContext *ctx)
8383 {
8384 if (unlikely(!ctx->spe_enabled)) {
8385 gen_exception(ctx, POWERPC_EXCP_SPEU);
8386 return;
8387 }
8388 #if defined(TARGET_PPC64)
8389 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8390 #else
8391 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8392 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8393 #endif
8394 }
8395
8396 /* Conversion */
8397 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8398 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8399 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8400 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8401 GEN_SPEFPUOP_CONV_32_64(efdctui);
8402 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8403 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8404 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8405 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8406 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8407 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8408 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8409 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8410 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8411 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8412
8413 /* Comparison */
8414 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8415 GEN_SPEFPUOP_COMP_64(efdcmplt);
8416 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8417 GEN_SPEFPUOP_COMP_64(efdtstgt);
8418 GEN_SPEFPUOP_COMP_64(efdtstlt);
8419 GEN_SPEFPUOP_COMP_64(efdtsteq);
8420
8421 /* Opcodes definitions */
8422 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8423 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8424 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8425 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8426 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8427 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8428 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8429 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8430 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8431 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8432 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8433 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8434 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8435 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8436 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8437 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8438
8439 static opcode_t opcodes[] = {
8440 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8441 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8442 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8443 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8444 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8445 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8446 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8447 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8448 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8449 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8450 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8451 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8452 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8453 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8454 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8455 #if defined(TARGET_PPC64)
8456 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8457 #endif
8458 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8459 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8460 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8461 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8462 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8463 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8464 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8465 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8466 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8467 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8468 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8469 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8470 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8471 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8472 #if defined(TARGET_PPC64)
8473 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8474 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8475 #endif
8476 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8477 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8478 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8479 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8480 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8481 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8482 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8483 #if defined(TARGET_PPC64)
8484 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8485 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8486 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8487 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8488 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8489 #endif
8490 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8491 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8492 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8493 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8494 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8495 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8496 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8497 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8498 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8499 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8500 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8501 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8502 #if defined(TARGET_PPC64)
8503 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8504 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8505 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8506 #endif
8507 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8508 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8509 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8510 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8511 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8512 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8513 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8514 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8515 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8516 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8517 #if defined(TARGET_PPC64)
8518 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8519 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8520 #endif
8521 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8522 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8523 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8524 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8525 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8526 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8527 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8528 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8529 #if defined(TARGET_PPC64)
8530 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8531 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8532 #endif
8533 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8534 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8535 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8536 #if defined(TARGET_PPC64)
8537 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8538 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8539 #endif
8540 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8541 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8542 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8543 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8544 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8545 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8546 #if defined(TARGET_PPC64)
8547 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8548 #endif
8549 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8550 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8551 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8552 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8553 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8554 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8555 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8556 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
8557 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8558 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8559 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8560 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8561 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8562 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8563 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8564 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8565 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8566 #if defined(TARGET_PPC64)
8567 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8568 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8569 PPC_SEGMENT_64B),
8570 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8571 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8572 PPC_SEGMENT_64B),
8573 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8574 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8575 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8576 #endif
8577 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8578 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8579 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8580 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8581 #if defined(TARGET_PPC64)
8582 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8583 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8584 #endif
8585 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8586 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8587 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8588 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8589 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8590 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8591 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8592 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8593 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8594 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8595 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8596 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8597 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8598 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8599 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8600 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8601 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8602 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8603 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8604 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8605 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8606 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8607 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8608 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8609 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8610 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8611 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8612 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8613 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8614 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8615 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8616 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8617 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8618 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8619 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8620 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8621 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8622 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8623 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8624 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8625 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8626 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8627 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8628 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8629 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8630 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8631 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8632 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8633 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8634 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8635 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8636 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8637 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8638 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8639 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8640 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8641 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8642 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8643 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8644 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8645 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8646 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8647 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8648 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8649 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8650 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8651 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8652 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8653 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8654 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8655 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8656 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8657 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8658 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8659 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8660 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8661 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8662 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8663 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8664 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8665 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8666 PPC_NONE, PPC2_BOOKE206),
8667 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8668 PPC_NONE, PPC2_BOOKE206),
8669 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8670 PPC_NONE, PPC2_BOOKE206),
8671 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8672 PPC_NONE, PPC2_BOOKE206),
8673 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8674 PPC_NONE, PPC2_BOOKE206),
8675 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8676 PPC_NONE, PPC2_PRCNTL),
8677 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8678 PPC_NONE, PPC2_PRCNTL),
8679 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8680 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8681 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8682 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8683 PPC_BOOKE, PPC2_BOOKE206),
8684 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8685 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8686 PPC_BOOKE, PPC2_BOOKE206),
8687 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8688 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8689 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8690 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8691 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8692 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8693 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8694 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8695 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8696 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8697
8698 #undef GEN_INT_ARITH_ADD
8699 #undef GEN_INT_ARITH_ADD_CONST
8700 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8701 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8702 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8703 add_ca, compute_ca, compute_ov) \
8704 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8705 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8706 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8707 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8708 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8709 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8710 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8711 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8712 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8713 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8714 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8715
8716 #undef GEN_INT_ARITH_DIVW
8717 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8718 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8719 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8720 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8721 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8722 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8723
8724 #if defined(TARGET_PPC64)
8725 #undef GEN_INT_ARITH_DIVD
8726 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8727 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8728 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8729 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8730 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8731 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8732
8733 #undef GEN_INT_ARITH_MUL_HELPER
8734 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8735 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8736 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8737 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8738 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8739 #endif
8740
8741 #undef GEN_INT_ARITH_SUBF
8742 #undef GEN_INT_ARITH_SUBF_CONST
8743 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8744 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8745 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8746 add_ca, compute_ca, compute_ov) \
8747 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8748 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8749 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8750 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8751 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8752 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8753 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8754 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8755 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8756 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8757 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8758
8759 #undef GEN_LOGICAL1
8760 #undef GEN_LOGICAL2
8761 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8762 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8763 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8764 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8765 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8766 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8767 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8768 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8769 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8770 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8771 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8772 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8773 #if defined(TARGET_PPC64)
8774 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8775 #endif
8776
8777 #if defined(TARGET_PPC64)
8778 #undef GEN_PPC64_R2
8779 #undef GEN_PPC64_R4
8780 #define GEN_PPC64_R2(name, opc1, opc2) \
8781 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8782 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8783 PPC_64B)
8784 #define GEN_PPC64_R4(name, opc1, opc2) \
8785 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8786 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8787 PPC_64B), \
8788 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8789 PPC_64B), \
8790 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8791 PPC_64B)
8792 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8793 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8794 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8795 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8796 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8797 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8798 #endif
8799
8800 #undef _GEN_FLOAT_ACB
8801 #undef GEN_FLOAT_ACB
8802 #undef _GEN_FLOAT_AB
8803 #undef GEN_FLOAT_AB
8804 #undef _GEN_FLOAT_AC
8805 #undef GEN_FLOAT_AC
8806 #undef GEN_FLOAT_B
8807 #undef GEN_FLOAT_BS
8808 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8809 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8810 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8811 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8812 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8813 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8814 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8815 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8816 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8817 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8818 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8819 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8820 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8821 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8822 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8823 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8824 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8825 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8826 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8827
8828 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8829 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8830 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8831 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8832 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8833 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8834 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8835 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8836 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8837 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8838 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8839 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8840 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8841 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8842 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8843 #if defined(TARGET_PPC64)
8844 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8845 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8846 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8847 #endif
8848 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8849 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8850 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8851 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8852 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8853 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8854 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8855
8856 #undef GEN_LD
8857 #undef GEN_LDU
8858 #undef GEN_LDUX
8859 #undef GEN_LDX_E
8860 #undef GEN_LDS
8861 #define GEN_LD(name, ldop, opc, type) \
8862 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8863 #define GEN_LDU(name, ldop, opc, type) \
8864 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8865 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8866 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8867 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8868 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8869 #define GEN_LDS(name, ldop, op, type) \
8870 GEN_LD(name, ldop, op | 0x20, type) \
8871 GEN_LDU(name, ldop, op | 0x21, type) \
8872 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8873 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8874
8875 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8876 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8877 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8878 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8879 #if defined(TARGET_PPC64)
8880 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8881 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8882 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8883 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8884 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
8885 #endif
8886 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8887 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8888
8889 #undef GEN_ST
8890 #undef GEN_STU
8891 #undef GEN_STUX
8892 #undef GEN_STX_E
8893 #undef GEN_STS
8894 #define GEN_ST(name, stop, opc, type) \
8895 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8896 #define GEN_STU(name, stop, opc, type) \
8897 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8898 #define GEN_STUX(name, stop, opc2, opc3, type) \
8899 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8900 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
8901 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8902 #define GEN_STS(name, stop, op, type) \
8903 GEN_ST(name, stop, op | 0x20, type) \
8904 GEN_STU(name, stop, op | 0x21, type) \
8905 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8906 GEN_STX(name, stop, 0x17, op | 0x00, type)
8907
8908 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8909 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8910 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8911 #if defined(TARGET_PPC64)
8912 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8913 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8914 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
8915 #endif
8916 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8917 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8918
8919 #undef GEN_LDF
8920 #undef GEN_LDUF
8921 #undef GEN_LDUXF
8922 #undef GEN_LDXF
8923 #undef GEN_LDFS
8924 #define GEN_LDF(name, ldop, opc, type) \
8925 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8926 #define GEN_LDUF(name, ldop, opc, type) \
8927 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8928 #define GEN_LDUXF(name, ldop, opc, type) \
8929 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8930 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
8931 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8932 #define GEN_LDFS(name, ldop, op, type) \
8933 GEN_LDF(name, ldop, op | 0x20, type) \
8934 GEN_LDUF(name, ldop, op | 0x21, type) \
8935 GEN_LDUXF(name, ldop, op | 0x01, type) \
8936 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
8937
8938 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
8939 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
8940
8941 #undef GEN_STF
8942 #undef GEN_STUF
8943 #undef GEN_STUXF
8944 #undef GEN_STXF
8945 #undef GEN_STFS
8946 #define GEN_STF(name, stop, opc, type) \
8947 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8948 #define GEN_STUF(name, stop, opc, type) \
8949 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8950 #define GEN_STUXF(name, stop, opc, type) \
8951 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8952 #define GEN_STXF(name, stop, opc2, opc3, type) \
8953 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8954 #define GEN_STFS(name, stop, op, type) \
8955 GEN_STF(name, stop, op | 0x20, type) \
8956 GEN_STUF(name, stop, op | 0x21, type) \
8957 GEN_STUXF(name, stop, op | 0x01, type) \
8958 GEN_STXF(name, stop, 0x17, op | 0x00, type)
8959
8960 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
8961 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
8962 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
8963
8964 #undef GEN_CRLOGIC
8965 #define GEN_CRLOGIC(name, tcg_op, opc) \
8966 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8967 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8968 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8969 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8970 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
8971 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
8972 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
8973 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
8974 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
8975
8976 #undef GEN_MAC_HANDLER
8977 #define GEN_MAC_HANDLER(name, opc2, opc3) \
8978 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8979 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
8980 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
8981 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
8982 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
8983 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
8984 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
8985 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
8986 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
8987 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
8988 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
8989 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
8990 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
8991 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
8992 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
8993 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
8994 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
8995 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
8996 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
8997 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
8998 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
8999 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
9000 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
9001 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
9002 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
9003 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
9004 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
9005 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
9006 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
9007 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
9008 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
9009 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
9010 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
9011 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
9012 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
9013 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
9014 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
9015 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9016 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9017 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9018 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9019 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9020 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9021
9022 #undef GEN_VR_LDX
9023 #undef GEN_VR_STX
9024 #undef GEN_VR_LVE
9025 #undef GEN_VR_STVE
9026 #define GEN_VR_LDX(name, opc2, opc3) \
9027 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9028 #define GEN_VR_STX(name, opc2, opc3) \
9029 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9030 #define GEN_VR_LVE(name, opc2, opc3) \
9031 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9032 #define GEN_VR_STVE(name, opc2, opc3) \
9033 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9034 GEN_VR_LDX(lvx, 0x07, 0x03),
9035 GEN_VR_LDX(lvxl, 0x07, 0x0B),
9036 GEN_VR_LVE(bx, 0x07, 0x00),
9037 GEN_VR_LVE(hx, 0x07, 0x01),
9038 GEN_VR_LVE(wx, 0x07, 0x02),
9039 GEN_VR_STX(svx, 0x07, 0x07),
9040 GEN_VR_STX(svxl, 0x07, 0x0F),
9041 GEN_VR_STVE(bx, 0x07, 0x04),
9042 GEN_VR_STVE(hx, 0x07, 0x05),
9043 GEN_VR_STVE(wx, 0x07, 0x06),
9044
9045 #undef GEN_VX_LOGICAL
9046 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9047 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9048 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9049 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9050 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9051 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9052 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9053
9054 #undef GEN_VXFORM
9055 #define GEN_VXFORM(name, opc2, opc3) \
9056 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9057 GEN_VXFORM(vaddubm, 0, 0),
9058 GEN_VXFORM(vadduhm, 0, 1),
9059 GEN_VXFORM(vadduwm, 0, 2),
9060 GEN_VXFORM(vsububm, 0, 16),
9061 GEN_VXFORM(vsubuhm, 0, 17),
9062 GEN_VXFORM(vsubuwm, 0, 18),
9063 GEN_VXFORM(vmaxub, 1, 0),
9064 GEN_VXFORM(vmaxuh, 1, 1),
9065 GEN_VXFORM(vmaxuw, 1, 2),
9066 GEN_VXFORM(vmaxsb, 1, 4),
9067 GEN_VXFORM(vmaxsh, 1, 5),
9068 GEN_VXFORM(vmaxsw, 1, 6),
9069 GEN_VXFORM(vminub, 1, 8),
9070 GEN_VXFORM(vminuh, 1, 9),
9071 GEN_VXFORM(vminuw, 1, 10),
9072 GEN_VXFORM(vminsb, 1, 12),
9073 GEN_VXFORM(vminsh, 1, 13),
9074 GEN_VXFORM(vminsw, 1, 14),
9075 GEN_VXFORM(vavgub, 1, 16),
9076 GEN_VXFORM(vavguh, 1, 17),
9077 GEN_VXFORM(vavguw, 1, 18),
9078 GEN_VXFORM(vavgsb, 1, 20),
9079 GEN_VXFORM(vavgsh, 1, 21),
9080 GEN_VXFORM(vavgsw, 1, 22),
9081 GEN_VXFORM(vmrghb, 6, 0),
9082 GEN_VXFORM(vmrghh, 6, 1),
9083 GEN_VXFORM(vmrghw, 6, 2),
9084 GEN_VXFORM(vmrglb, 6, 4),
9085 GEN_VXFORM(vmrglh, 6, 5),
9086 GEN_VXFORM(vmrglw, 6, 6),
9087 GEN_VXFORM(vmuloub, 4, 0),
9088 GEN_VXFORM(vmulouh, 4, 1),
9089 GEN_VXFORM(vmulosb, 4, 4),
9090 GEN_VXFORM(vmulosh, 4, 5),
9091 GEN_VXFORM(vmuleub, 4, 8),
9092 GEN_VXFORM(vmuleuh, 4, 9),
9093 GEN_VXFORM(vmulesb, 4, 12),
9094 GEN_VXFORM(vmulesh, 4, 13),
9095 GEN_VXFORM(vslb, 2, 4),
9096 GEN_VXFORM(vslh, 2, 5),
9097 GEN_VXFORM(vslw, 2, 6),
9098 GEN_VXFORM(vsrb, 2, 8),
9099 GEN_VXFORM(vsrh, 2, 9),
9100 GEN_VXFORM(vsrw, 2, 10),
9101 GEN_VXFORM(vsrab, 2, 12),
9102 GEN_VXFORM(vsrah, 2, 13),
9103 GEN_VXFORM(vsraw, 2, 14),
9104 GEN_VXFORM(vslo, 6, 16),
9105 GEN_VXFORM(vsro, 6, 17),
9106 GEN_VXFORM(vaddcuw, 0, 6),
9107 GEN_VXFORM(vsubcuw, 0, 22),
9108 GEN_VXFORM(vaddubs, 0, 8),
9109 GEN_VXFORM(vadduhs, 0, 9),
9110 GEN_VXFORM(vadduws, 0, 10),
9111 GEN_VXFORM(vaddsbs, 0, 12),
9112 GEN_VXFORM(vaddshs, 0, 13),
9113 GEN_VXFORM(vaddsws, 0, 14),
9114 GEN_VXFORM(vsububs, 0, 24),
9115 GEN_VXFORM(vsubuhs, 0, 25),
9116 GEN_VXFORM(vsubuws, 0, 26),
9117 GEN_VXFORM(vsubsbs, 0, 28),
9118 GEN_VXFORM(vsubshs, 0, 29),
9119 GEN_VXFORM(vsubsws, 0, 30),
9120 GEN_VXFORM(vrlb, 2, 0),
9121 GEN_VXFORM(vrlh, 2, 1),
9122 GEN_VXFORM(vrlw, 2, 2),
9123 GEN_VXFORM(vsl, 2, 7),
9124 GEN_VXFORM(vsr, 2, 11),
9125 GEN_VXFORM(vpkuhum, 7, 0),
9126 GEN_VXFORM(vpkuwum, 7, 1),
9127 GEN_VXFORM(vpkuhus, 7, 2),
9128 GEN_VXFORM(vpkuwus, 7, 3),
9129 GEN_VXFORM(vpkshus, 7, 4),
9130 GEN_VXFORM(vpkswus, 7, 5),
9131 GEN_VXFORM(vpkshss, 7, 6),
9132 GEN_VXFORM(vpkswss, 7, 7),
9133 GEN_VXFORM(vpkpx, 7, 12),
9134 GEN_VXFORM(vsum4ubs, 4, 24),
9135 GEN_VXFORM(vsum4sbs, 4, 28),
9136 GEN_VXFORM(vsum4shs, 4, 25),
9137 GEN_VXFORM(vsum2sws, 4, 26),
9138 GEN_VXFORM(vsumsws, 4, 30),
9139 GEN_VXFORM(vaddfp, 5, 0),
9140 GEN_VXFORM(vsubfp, 5, 1),
9141 GEN_VXFORM(vmaxfp, 5, 16),
9142 GEN_VXFORM(vminfp, 5, 17),
9143
9144 #undef GEN_VXRFORM1
9145 #undef GEN_VXRFORM
9146 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9147 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9148 #define GEN_VXRFORM(name, opc2, opc3) \
9149 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9150 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9151 GEN_VXRFORM(vcmpequb, 3, 0)
9152 GEN_VXRFORM(vcmpequh, 3, 1)
9153 GEN_VXRFORM(vcmpequw, 3, 2)
9154 GEN_VXRFORM(vcmpgtsb, 3, 12)
9155 GEN_VXRFORM(vcmpgtsh, 3, 13)
9156 GEN_VXRFORM(vcmpgtsw, 3, 14)
9157 GEN_VXRFORM(vcmpgtub, 3, 8)
9158 GEN_VXRFORM(vcmpgtuh, 3, 9)
9159 GEN_VXRFORM(vcmpgtuw, 3, 10)
9160 GEN_VXRFORM(vcmpeqfp, 3, 3)
9161 GEN_VXRFORM(vcmpgefp, 3, 7)
9162 GEN_VXRFORM(vcmpgtfp, 3, 11)
9163 GEN_VXRFORM(vcmpbfp, 3, 15)
9164
9165 #undef GEN_VXFORM_SIMM
9166 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9167 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9168 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9169 GEN_VXFORM_SIMM(vspltish, 6, 13),
9170 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9171
9172 #undef GEN_VXFORM_NOA
9173 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9174 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9175 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9176 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9177 GEN_VXFORM_NOA(vupklsb, 7, 10),
9178 GEN_VXFORM_NOA(vupklsh, 7, 11),
9179 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9180 GEN_VXFORM_NOA(vupklpx, 7, 15),
9181 GEN_VXFORM_NOA(vrefp, 5, 4),
9182 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9183 GEN_VXFORM_NOA(vexptefp, 5, 6),
9184 GEN_VXFORM_NOA(vlogefp, 5, 7),
9185 GEN_VXFORM_NOA(vrfim, 5, 8),
9186 GEN_VXFORM_NOA(vrfin, 5, 9),
9187 GEN_VXFORM_NOA(vrfip, 5, 10),
9188 GEN_VXFORM_NOA(vrfiz, 5, 11),
9189
9190 #undef GEN_VXFORM_UIMM
9191 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9192 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9193 GEN_VXFORM_UIMM(vspltb, 6, 8),
9194 GEN_VXFORM_UIMM(vsplth, 6, 9),
9195 GEN_VXFORM_UIMM(vspltw, 6, 10),
9196 GEN_VXFORM_UIMM(vcfux, 5, 12),
9197 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9198 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9199 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9200
9201 #undef GEN_VAFORM_PAIRED
9202 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9203 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9204 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9205 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9206 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9207 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9208 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9209 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9210
9211 #undef GEN_SPE
9212 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9213 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9214 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9215 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9216 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9217 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9218 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9219 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9220 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9221 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9222 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9223 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9224 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9225 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9226 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9227 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9228 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9229 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9230 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9231 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9232 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9233 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9234 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9235 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9236 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9237 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9238 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9239 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9240 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9241 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9242 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9243
9244 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9245 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9246 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9247 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9248 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9249 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9250 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9251 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9252 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9253 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9254 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9255 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9256 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9257 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9258
9259 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9260 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9261 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9262 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9263 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9264 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9265 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9266 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9267 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9268 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9269 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9270 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9271 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9272 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9273
9274 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9275 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9276 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9277 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9278 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9279 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9280 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9281 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9282 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9283 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9284 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9285 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9286 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9287 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9288 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9289 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9290
9291 #undef GEN_SPEOP_LDST
9292 #define GEN_SPEOP_LDST(name, opc2, sh) \
9293 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9294 GEN_SPEOP_LDST(evldd, 0x00, 3),
9295 GEN_SPEOP_LDST(evldw, 0x01, 3),
9296 GEN_SPEOP_LDST(evldh, 0x02, 3),
9297 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9298 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9299 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9300 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9301 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9302 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9303 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9304 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9305
9306 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9307 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9308 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9309 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9310 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9311 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9312 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9313 };
9314
9315 #include "helper_regs.h"
9316 #include "translate_init.c"
9317
9318 /*****************************************************************************/
9319 /* Misc PowerPC helpers */
9320 void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
9321 int flags)
9322 {
9323 #define RGPL 4
9324 #define RFPL 4
9325
9326 int i;
9327
9328 cpu_synchronize_state(env);
9329
9330 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9331 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9332 env->nip, env->lr, env->ctr, cpu_read_xer(env));
9333 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9334 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9335 env->hflags, env->mmu_idx);
9336 #if !defined(NO_TIMER_DUMP)
9337 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9338 #if !defined(CONFIG_USER_ONLY)
9339 " DECR %08" PRIu32
9340 #endif
9341 "\n",
9342 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9343 #if !defined(CONFIG_USER_ONLY)
9344 , cpu_ppc_load_decr(env)
9345 #endif
9346 );
9347 #endif
9348 for (i = 0; i < 32; i++) {
9349 if ((i & (RGPL - 1)) == 0)
9350 cpu_fprintf(f, "GPR%02d", i);
9351 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9352 if ((i & (RGPL - 1)) == (RGPL - 1))
9353 cpu_fprintf(f, "\n");
9354 }
9355 cpu_fprintf(f, "CR ");
9356 for (i = 0; i < 8; i++)
9357 cpu_fprintf(f, "%01x", env->crf[i]);
9358 cpu_fprintf(f, " [");
9359 for (i = 0; i < 8; i++) {
9360 char a = '-';
9361 if (env->crf[i] & 0x08)
9362 a = 'L';
9363 else if (env->crf[i] & 0x04)
9364 a = 'G';
9365 else if (env->crf[i] & 0x02)
9366 a = 'E';
9367 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9368 }
9369 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9370 env->reserve_addr);
9371 for (i = 0; i < 32; i++) {
9372 if ((i & (RFPL - 1)) == 0)
9373 cpu_fprintf(f, "FPR%02d", i);
9374 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9375 if ((i & (RFPL - 1)) == (RFPL - 1))
9376 cpu_fprintf(f, "\n");
9377 }
9378 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9379 #if !defined(CONFIG_USER_ONLY)
9380 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9381 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9382 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9383 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9384
9385 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9386 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9387 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9388 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9389
9390 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9391 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9392 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9393 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9394
9395 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9396 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9397 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9398 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9399 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9400
9401 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9402 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9403 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9404 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9405
9406 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9407 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9408 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9409 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9410
9411 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9412 " EPR " TARGET_FMT_lx "\n",
9413 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9414 env->spr[SPR_BOOKE_EPR]);
9415
9416 /* FSL-specific */
9417 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9418 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9419 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9420 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9421
9422 /*
9423 * IVORs are left out as they are large and do not change often --
9424 * they can be read with "p $ivor0", "p $ivor1", etc.
9425 */
9426 }
9427
9428 #if defined(TARGET_PPC64)
9429 if (env->flags & POWERPC_FLAG_CFAR) {
9430 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9431 }
9432 #endif
9433
9434 switch (env->mmu_model) {
9435 case POWERPC_MMU_32B:
9436 case POWERPC_MMU_601:
9437 case POWERPC_MMU_SOFT_6xx:
9438 case POWERPC_MMU_SOFT_74xx:
9439 #if defined(TARGET_PPC64)
9440 case POWERPC_MMU_64B:
9441 #endif
9442 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9443 break;
9444 case POWERPC_MMU_BOOKE206:
9445 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9446 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9447 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9448 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9449
9450 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9451 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9452 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9453 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9454
9455 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9456 " TLB1CFG " TARGET_FMT_lx "\n",
9457 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9458 env->spr[SPR_BOOKE_TLB1CFG]);
9459 break;
9460 default:
9461 break;
9462 }
9463 #endif
9464
9465 #undef RGPL
9466 #undef RFPL
9467 }
9468
9469 void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
9470 int flags)
9471 {
9472 #if defined(DO_PPC_STATISTICS)
9473 opc_handler_t **t1, **t2, **t3, *handler;
9474 int op1, op2, op3;
9475
9476 t1 = env->opcodes;
9477 for (op1 = 0; op1 < 64; op1++) {
9478 handler = t1[op1];
9479 if (is_indirect_opcode(handler)) {
9480 t2 = ind_table(handler);
9481 for (op2 = 0; op2 < 32; op2++) {
9482 handler = t2[op2];
9483 if (is_indirect_opcode(handler)) {
9484 t3 = ind_table(handler);
9485 for (op3 = 0; op3 < 32; op3++) {
9486 handler = t3[op3];
9487 if (handler->count == 0)
9488 continue;
9489 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9490 "%016" PRIx64 " %" PRId64 "\n",
9491 op1, op2, op3, op1, (op3 << 5) | op2,
9492 handler->oname,
9493 handler->count, handler->count);
9494 }
9495 } else {
9496 if (handler->count == 0)
9497 continue;
9498 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9499 "%016" PRIx64 " %" PRId64 "\n",
9500 op1, op2, op1, op2, handler->oname,
9501 handler->count, handler->count);
9502 }
9503 }
9504 } else {
9505 if (handler->count == 0)
9506 continue;
9507 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9508 " %" PRId64 "\n",
9509 op1, op1, handler->oname,
9510 handler->count, handler->count);
9511 }
9512 }
9513 #endif
9514 }
9515
9516 /*****************************************************************************/
9517 static inline void gen_intermediate_code_internal(CPUPPCState *env,
9518 TranslationBlock *tb,
9519 int search_pc)
9520 {
9521 DisasContext ctx, *ctxp = &ctx;
9522 opc_handler_t **table, *handler;
9523 target_ulong pc_start;
9524 uint16_t *gen_opc_end;
9525 CPUBreakpoint *bp;
9526 int j, lj = -1;
9527 int num_insns;
9528 int max_insns;
9529
9530 pc_start = tb->pc;
9531 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
9532 ctx.nip = pc_start;
9533 ctx.tb = tb;
9534 ctx.exception = POWERPC_EXCP_NONE;
9535 ctx.spr_cb = env->spr_cb;
9536 ctx.mem_idx = env->mmu_idx;
9537 ctx.access_type = -1;
9538 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9539 #if defined(TARGET_PPC64)
9540 ctx.sf_mode = msr_is_64bit(env, env->msr);
9541 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9542 #endif
9543 ctx.fpu_enabled = msr_fp;
9544 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9545 ctx.spe_enabled = msr_spe;
9546 else
9547 ctx.spe_enabled = 0;
9548 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9549 ctx.altivec_enabled = msr_vr;
9550 else
9551 ctx.altivec_enabled = 0;
9552 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9553 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9554 else
9555 ctx.singlestep_enabled = 0;
9556 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9557 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9558 if (unlikely(env->singlestep_enabled))
9559 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9560 #if defined (DO_SINGLE_STEP) && 0
9561 /* Single step trace mode */
9562 msr_se = 1;
9563 #endif
9564 num_insns = 0;
9565 max_insns = tb->cflags & CF_COUNT_MASK;
9566 if (max_insns == 0)
9567 max_insns = CF_COUNT_MASK;
9568
9569 gen_tb_start();
9570 /* Set env in case of segfault during code fetch */
9571 while (ctx.exception == POWERPC_EXCP_NONE
9572 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
9573 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9574 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9575 if (bp->pc == ctx.nip) {
9576 gen_debug_exception(ctxp);
9577 break;
9578 }
9579 }
9580 }
9581 if (unlikely(search_pc)) {
9582 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9583 if (lj < j) {
9584 lj++;
9585 while (lj < j)
9586 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9587 }
9588 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
9589 tcg_ctx.gen_opc_instr_start[lj] = 1;
9590 tcg_ctx.gen_opc_icount[lj] = num_insns;
9591 }
9592 LOG_DISAS("----------------\n");
9593 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9594 ctx.nip, ctx.mem_idx, (int)msr_ir);
9595 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9596 gen_io_start();
9597 if (unlikely(ctx.le_mode)) {
9598 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
9599 } else {
9600 ctx.opcode = cpu_ldl_code(env, ctx.nip);
9601 }
9602 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9603 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9604 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
9605 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
9606 tcg_gen_debug_insn_start(ctx.nip);
9607 }
9608 ctx.nip += 4;
9609 table = env->opcodes;
9610 num_insns++;
9611 handler = table[opc1(ctx.opcode)];
9612 if (is_indirect_opcode(handler)) {
9613 table = ind_table(handler);
9614 handler = table[opc2(ctx.opcode)];
9615 if (is_indirect_opcode(handler)) {
9616 table = ind_table(handler);
9617 handler = table[opc3(ctx.opcode)];
9618 }
9619 }
9620 /* Is opcode *REALLY* valid ? */
9621 if (unlikely(handler->handler == &gen_invalid)) {
9622 if (qemu_log_enabled()) {
9623 qemu_log("invalid/unsupported opcode: "
9624 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9625 opc1(ctx.opcode), opc2(ctx.opcode),
9626 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9627 }
9628 } else {
9629 uint32_t inval;
9630
9631 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9632 inval = handler->inval2;
9633 } else {
9634 inval = handler->inval1;
9635 }
9636
9637 if (unlikely((ctx.opcode & inval) != 0)) {
9638 if (qemu_log_enabled()) {
9639 qemu_log("invalid bits: %08x for opcode: "
9640 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9641 ctx.opcode & inval, opc1(ctx.opcode),
9642 opc2(ctx.opcode), opc3(ctx.opcode),
9643 ctx.opcode, ctx.nip - 4);
9644 }
9645 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9646 break;
9647 }
9648 }
9649 (*(handler->handler))(&ctx);
9650 #if defined(DO_PPC_STATISTICS)
9651 handler->count++;
9652 #endif
9653 /* Check trace mode exceptions */
9654 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9655 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9656 ctx.exception != POWERPC_SYSCALL &&
9657 ctx.exception != POWERPC_EXCP_TRAP &&
9658 ctx.exception != POWERPC_EXCP_BRANCH)) {
9659 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9660 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9661 (env->singlestep_enabled) ||
9662 singlestep ||
9663 num_insns >= max_insns)) {
9664 /* if we reach a page boundary or are single stepping, stop
9665 * generation
9666 */
9667 break;
9668 }
9669 }
9670 if (tb->cflags & CF_LAST_IO)
9671 gen_io_end();
9672 if (ctx.exception == POWERPC_EXCP_NONE) {
9673 gen_goto_tb(&ctx, 0, ctx.nip);
9674 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9675 if (unlikely(env->singlestep_enabled)) {
9676 gen_debug_exception(ctxp);
9677 }
9678 /* Generate the return instruction */
9679 tcg_gen_exit_tb(0);
9680 }
9681 gen_tb_end(tb, num_insns);
9682 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
9683 if (unlikely(search_pc)) {
9684 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9685 lj++;
9686 while (lj <= j)
9687 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9688 } else {
9689 tb->size = ctx.nip - pc_start;
9690 tb->icount = num_insns;
9691 }
9692 #if defined(DEBUG_DISAS)
9693 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9694 int flags;
9695 flags = env->bfd_mach;
9696 flags |= ctx.le_mode << 16;
9697 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9698 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
9699 qemu_log("\n");
9700 }
9701 #endif
9702 }
9703
9704 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9705 {
9706 gen_intermediate_code_internal(env, tb, 0);
9707 }
9708
9709 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9710 {
9711 gen_intermediate_code_internal(env, tb, 1);
9712 }
9713
9714 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9715 {
9716 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
9717 }
Qemu copy for testing