2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 /* Include definitions for instructions classes and implementations flags */
31 //#define DO_SINGLE_STEP
32 //#define PPC_DEBUG_DISAS
33 //#define DEBUG_MEMORY_ACCESSES
34 //#define DO_PPC_STATISTICS
35 //#define OPTIMIZE_FPRF_UPDATE
37 /*****************************************************************************/
38 /* Code translation helpers */
39 #if defined(USE_DIRECT_JUMP)
42 #define TBPARAM(x) (long)(x)
46 #define DEF(s, n, copy_size) INDEX_op_ ## s,
52 static uint16_t *gen_opc_ptr
;
53 static uint32_t *gen_opparam_ptr
;
54 #if defined(OPTIMIZE_FPRF_UPDATE)
55 static uint16_t *gen_fprf_buf
[OPC_BUF_SIZE
];
56 static uint16_t **gen_fprf_ptr
;
61 static always_inline
void gen_set_T0 (target_ulong val
)
63 #if defined(TARGET_PPC64)
65 gen_op_set_T0_64(val
>> 32, val
);
71 static always_inline
void gen_set_T1 (target_ulong val
)
73 #if defined(TARGET_PPC64)
75 gen_op_set_T1_64(val
>> 32, val
);
81 #define GEN8(func, NAME) \
82 static GenOpFunc *NAME ## _table [8] = { \
83 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
84 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
86 static always_inline void func (int n) \
88 NAME ## _table[n](); \
91 #define GEN16(func, NAME) \
92 static GenOpFunc *NAME ## _table [16] = { \
93 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
94 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
95 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
96 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
98 static always_inline void func (int n) \
100 NAME ## _table[n](); \
103 #define GEN32(func, NAME) \
104 static GenOpFunc *NAME ## _table [32] = { \
105 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
106 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
107 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
108 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
109 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
110 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
111 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
112 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
114 static always_inline void func (int n) \
116 NAME ## _table[n](); \
119 /* Condition register moves */
120 GEN8(gen_op_load_crf_T0
, gen_op_load_crf_T0_crf
);
121 GEN8(gen_op_load_crf_T1
, gen_op_load_crf_T1_crf
);
122 GEN8(gen_op_store_T0_crf
, gen_op_store_T0_crf_crf
);
124 GEN8(gen_op_store_T1_crf
, gen_op_store_T1_crf_crf
);
127 /* General purpose registers moves */
128 GEN32(gen_op_load_gpr_T0
, gen_op_load_gpr_T0_gpr
);
129 GEN32(gen_op_load_gpr_T1
, gen_op_load_gpr_T1_gpr
);
130 GEN32(gen_op_load_gpr_T2
, gen_op_load_gpr_T2_gpr
);
132 GEN32(gen_op_store_T0_gpr
, gen_op_store_T0_gpr_gpr
);
133 GEN32(gen_op_store_T1_gpr
, gen_op_store_T1_gpr_gpr
);
135 GEN32(gen_op_store_T2_gpr
, gen_op_store_T2_gpr_gpr
);
138 /* floating point registers moves */
139 GEN32(gen_op_load_fpr_FT0
, gen_op_load_fpr_FT0_fpr
);
140 GEN32(gen_op_load_fpr_FT1
, gen_op_load_fpr_FT1_fpr
);
141 GEN32(gen_op_load_fpr_FT2
, gen_op_load_fpr_FT2_fpr
);
142 GEN32(gen_op_store_FT0_fpr
, gen_op_store_FT0_fpr_fpr
);
143 GEN32(gen_op_store_FT1_fpr
, gen_op_store_FT1_fpr_fpr
);
145 GEN32(gen_op_store_FT2_fpr
, gen_op_store_FT2_fpr_fpr
);
148 /* internal defines */
149 typedef struct DisasContext
{
150 struct TranslationBlock
*tb
;
154 /* Routine used to access memory */
156 /* Translation flags */
157 #if !defined(CONFIG_USER_ONLY)
160 #if defined(TARGET_PPC64)
165 #if defined(TARGET_PPCEMB)
168 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
169 int singlestep_enabled
;
170 int dcache_line_size
;
173 struct opc_handler_t
{
176 /* instruction type */
179 void (*handler
)(DisasContext
*ctx
);
180 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
181 const unsigned char *oname
;
183 #if defined(DO_PPC_STATISTICS)
188 static always_inline
void gen_set_Rc0 (DisasContext
*ctx
)
190 #if defined(TARGET_PPC64)
199 static always_inline
void gen_reset_fpstatus (void)
201 #ifdef CONFIG_SOFTFLOAT
202 gen_op_reset_fpstatus();
206 static always_inline
void gen_compute_fprf (int set_fprf
, int set_rc
)
209 /* This case might be optimized later */
210 #if defined(OPTIMIZE_FPRF_UPDATE)
211 *gen_fprf_ptr
++ = gen_opc_ptr
;
213 gen_op_compute_fprf(1);
214 if (unlikely(set_rc
))
215 gen_op_store_T0_crf(1);
216 gen_op_float_check_status();
217 } else if (unlikely(set_rc
)) {
218 /* We always need to compute fpcc */
219 gen_op_compute_fprf(0);
220 gen_op_store_T0_crf(1);
222 gen_op_float_check_status();
226 static always_inline
void gen_optimize_fprf (void)
228 #if defined(OPTIMIZE_FPRF_UPDATE)
231 for (ptr
= gen_fprf_buf
; ptr
!= (gen_fprf_ptr
- 1); ptr
++)
232 *ptr
= INDEX_op_nop1
;
233 gen_fprf_ptr
= gen_fprf_buf
;
237 static always_inline
void gen_update_nip (DisasContext
*ctx
, target_ulong nip
)
239 #if defined(TARGET_PPC64)
241 gen_op_update_nip_64(nip
>> 32, nip
);
244 gen_op_update_nip(nip
);
247 #define GEN_EXCP(ctx, excp, error) \
249 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
250 gen_update_nip(ctx, (ctx)->nip); \
252 gen_op_raise_exception_err((excp), (error)); \
253 ctx->exception = (excp); \
256 #define GEN_EXCP_INVAL(ctx) \
257 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
258 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
260 #define GEN_EXCP_PRIVOPC(ctx) \
261 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
262 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
264 #define GEN_EXCP_PRIVREG(ctx) \
265 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
266 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
268 #define GEN_EXCP_NO_FP(ctx) \
269 GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
271 #define GEN_EXCP_NO_AP(ctx) \
272 GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
274 #define GEN_EXCP_NO_VR(ctx) \
275 GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
277 /* Stop translation */
278 static always_inline
void GEN_STOP (DisasContext
*ctx
)
280 gen_update_nip(ctx
, ctx
->nip
);
281 ctx
->exception
= POWERPC_EXCP_STOP
;
284 /* No need to update nip here, as execution flow will change */
285 static always_inline
void GEN_SYNC (DisasContext
*ctx
)
287 ctx
->exception
= POWERPC_EXCP_SYNC
;
290 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
291 static void gen_##name (DisasContext *ctx); \
292 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
293 static void gen_##name (DisasContext *ctx)
295 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
296 static void gen_##name (DisasContext *ctx); \
297 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
298 static void gen_##name (DisasContext *ctx)
300 typedef struct opcode_t
{
301 unsigned char opc1
, opc2
, opc3
;
302 #if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
303 unsigned char pad
[5];
305 unsigned char pad
[1];
307 opc_handler_t handler
;
308 const unsigned char *oname
;
311 /*****************************************************************************/
312 /*** Instruction decoding ***/
313 #define EXTRACT_HELPER(name, shift, nb) \
314 static always_inline uint32_t name (uint32_t opcode) \
316 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
319 #define EXTRACT_SHELPER(name, shift, nb) \
320 static always_inline int32_t name (uint32_t opcode) \
322 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
326 EXTRACT_HELPER(opc1
, 26, 6);
328 EXTRACT_HELPER(opc2
, 1, 5);
330 EXTRACT_HELPER(opc3
, 6, 5);
331 /* Update Cr0 flags */
332 EXTRACT_HELPER(Rc
, 0, 1);
334 EXTRACT_HELPER(rD
, 21, 5);
336 EXTRACT_HELPER(rS
, 21, 5);
338 EXTRACT_HELPER(rA
, 16, 5);
340 EXTRACT_HELPER(rB
, 11, 5);
342 EXTRACT_HELPER(rC
, 6, 5);
344 EXTRACT_HELPER(crfD
, 23, 3);
345 EXTRACT_HELPER(crfS
, 18, 3);
346 EXTRACT_HELPER(crbD
, 21, 5);
347 EXTRACT_HELPER(crbA
, 16, 5);
348 EXTRACT_HELPER(crbB
, 11, 5);
350 EXTRACT_HELPER(_SPR
, 11, 10);
351 static always_inline
uint32_t SPR (uint32_t opcode
)
353 uint32_t sprn
= _SPR(opcode
);
355 return ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
357 /*** Get constants ***/
358 EXTRACT_HELPER(IMM
, 12, 8);
359 /* 16 bits signed immediate value */
360 EXTRACT_SHELPER(SIMM
, 0, 16);
361 /* 16 bits unsigned immediate value */
362 EXTRACT_HELPER(UIMM
, 0, 16);
364 EXTRACT_HELPER(NB
, 11, 5);
366 EXTRACT_HELPER(SH
, 11, 5);
368 EXTRACT_HELPER(MB
, 6, 5);
370 EXTRACT_HELPER(ME
, 1, 5);
372 EXTRACT_HELPER(TO
, 21, 5);
374 EXTRACT_HELPER(CRM
, 12, 8);
375 EXTRACT_HELPER(FM
, 17, 8);
376 EXTRACT_HELPER(SR
, 16, 4);
377 EXTRACT_HELPER(FPIMM
, 20, 4);
379 /*** Jump target decoding ***/
381 EXTRACT_SHELPER(d
, 0, 16);
382 /* Immediate address */
383 static always_inline target_ulong
LI (uint32_t opcode
)
385 return (opcode
>> 0) & 0x03FFFFFC;
388 static always_inline
uint32_t BD (uint32_t opcode
)
390 return (opcode
>> 0) & 0xFFFC;
393 EXTRACT_HELPER(BO
, 21, 5);
394 EXTRACT_HELPER(BI
, 16, 5);
395 /* Absolute/relative address */
396 EXTRACT_HELPER(AA
, 1, 1);
398 EXTRACT_HELPER(LK
, 0, 1);
400 /* Create a mask between <start> and <end> bits */
401 static always_inline target_ulong
MASK (uint32_t start
, uint32_t end
)
405 #if defined(TARGET_PPC64)
406 if (likely(start
== 0)) {
407 ret
= (uint64_t)(-1ULL) << (63 - end
);
408 } else if (likely(end
== 63)) {
409 ret
= (uint64_t)(-1ULL) >> start
;
412 if (likely(start
== 0)) {
413 ret
= (uint32_t)(-1ULL) << (31 - end
);
414 } else if (likely(end
== 31)) {
415 ret
= (uint32_t)(-1ULL) >> start
;
419 ret
= (((target_ulong
)(-1ULL)) >> (start
)) ^
420 (((target_ulong
)(-1ULL) >> (end
)) >> 1);
421 if (unlikely(start
> end
))
428 /*****************************************************************************/
429 /* PowerPC Instructions types definitions */
431 PPC_NONE
= 0x0000000000000000ULL
,
432 /* PowerPC base instructions set */
433 PPC_INSNS_BASE
= 0x0000000000000001ULL
,
434 /* integer operations instructions */
435 #define PPC_INTEGER PPC_INSNS_BASE
436 /* flow control instructions */
437 #define PPC_FLOW PPC_INSNS_BASE
438 /* virtual memory instructions */
439 #define PPC_MEM PPC_INSNS_BASE
440 /* ld/st with reservation instructions */
441 #define PPC_RES PPC_INSNS_BASE
442 /* cache control instructions */
443 #define PPC_CACHE PPC_INSNS_BASE
444 /* spr/msr access instructions */
445 #define PPC_MISC PPC_INSNS_BASE
446 /* Optional floating point instructions */
447 PPC_FLOAT
= 0x0000000000000002ULL
,
448 PPC_FLOAT_FSQRT
= 0x0000000000000004ULL
,
449 PPC_FLOAT_FRES
= 0x0000000000000008ULL
,
450 PPC_FLOAT_FRSQRTE
= 0x0000000000000010ULL
,
451 PPC_FLOAT_FSEL
= 0x0000000000000020ULL
,
452 PPC_FLOAT_STFIWX
= 0x0000000000000040ULL
,
453 /* external control instructions */
454 PPC_EXTERN
= 0x0000000000000080ULL
,
455 /* segment register access instructions */
456 PPC_SEGMENT
= 0x0000000000000100ULL
,
457 /* Optional cache control instruction */
458 PPC_CACHE_DCBA
= 0x0000000000000200ULL
,
459 /* Optional memory control instructions */
460 PPC_MEM_TLBIA
= 0x0000000000000400ULL
,
461 PPC_MEM_TLBIE
= 0x0000000000000800ULL
,
462 PPC_MEM_TLBSYNC
= 0x0000000000001000ULL
,
464 PPC_MEM_SYNC
= 0x0000000000002000ULL
,
465 /* PowerPC 6xx TLB management instructions */
466 PPC_6xx_TLB
= 0x0000000000004000ULL
,
467 /* Altivec support */
468 PPC_ALTIVEC
= 0x0000000000008000ULL
,
469 /* Time base mftb instruction */
470 PPC_MFTB
= 0x0000000000010000ULL
,
471 /* Embedded PowerPC dedicated instructions */
472 PPC_EMB_COMMON
= 0x0000000000020000ULL
,
473 /* PowerPC 40x exception model */
474 PPC_40x_EXCP
= 0x0000000000040000ULL
,
475 /* PowerPC 40x TLB management instructions */
476 PPC_40x_TLB
= 0x0000000000080000ULL
,
477 /* PowerPC 405 Mac instructions */
478 PPC_405_MAC
= 0x0000000000100000ULL
,
479 /* PowerPC 440 specific instructions */
480 PPC_440_SPEC
= 0x0000000000200000ULL
,
481 /* Power-to-PowerPC bridge (601) */
482 PPC_POWER_BR
= 0x0000000000400000ULL
,
483 /* PowerPC 602 specific */
484 PPC_602_SPEC
= 0x0000000000800000ULL
,
485 /* Deprecated instructions */
486 /* Original POWER instruction set */
487 PPC_POWER
= 0x0000000001000000ULL
,
488 /* POWER2 instruction set extension */
489 PPC_POWER2
= 0x0000000002000000ULL
,
490 /* Power RTC support */
491 PPC_POWER_RTC
= 0x0000000004000000ULL
,
492 /* 64 bits PowerPC instruction set */
493 PPC_64B
= 0x0000000008000000ULL
,
494 /* 64 bits hypervisor extensions */
495 PPC_64H
= 0x0000000010000000ULL
,
496 /* segment register access instructions for PowerPC 64 "bridge" */
497 PPC_SEGMENT_64B
= 0x0000000020000000ULL
,
498 /* BookE (embedded) PowerPC specification */
499 PPC_BOOKE
= 0x0000000040000000ULL
,
501 PPC_MEM_EIEIO
= 0x0000000080000000ULL
,
502 /* e500 vector instructions */
503 PPC_E500_VECTOR
= 0x0000000100000000ULL
,
504 /* PowerPC 4xx dedicated instructions */
505 PPC_4xx_COMMON
= 0x0000000200000000ULL
,
506 /* PowerPC 2.03 specification extensions */
507 PPC_203
= 0x0000000400000000ULL
,
508 /* PowerPC 2.03 SPE extension */
509 PPC_SPE
= 0x0000000800000000ULL
,
510 /* PowerPC 2.03 SPE floating-point extension */
511 PPC_SPEFPU
= 0x0000001000000000ULL
,
513 PPC_SLBI
= 0x0000002000000000ULL
,
514 /* PowerPC 40x ibct instructions */
515 PPC_40x_ICBT
= 0x0000004000000000ULL
,
516 /* PowerPC 74xx TLB management instructions */
517 PPC_74xx_TLB
= 0x0000008000000000ULL
,
518 /* More BookE (embedded) instructions... */
519 PPC_BOOKE_EXT
= 0x0000010000000000ULL
,
520 /* rfmci is not implemented in all BookE PowerPC */
521 PPC_RFMCI
= 0x0000020000000000ULL
,
522 /* user-mode DCR access, implemented in PowerPC 460 */
523 PPC_DCRUX
= 0x0000040000000000ULL
,
524 /* New floating-point extensions (PowerPC 2.0x) */
525 PPC_FLOAT_EXT
= 0x0000080000000000ULL
,
526 /* New wait instruction (PowerPC 2.0x) */
527 PPC_WAIT
= 0x0000100000000000ULL
,
528 /* New 64 bits extensions (PowerPC 2.0x) */
529 PPC_64BX
= 0x0000200000000000ULL
,
530 /* dcbz instruction with fixed cache line size */
531 PPC_CACHE_DCBZ
= 0x0000400000000000ULL
,
532 /* dcbz instruction with tunable cache line size */
533 PPC_CACHE_DCBZT
= 0x0000800000000000ULL
,
534 /* frsqrtes extension */
535 PPC_FLOAT_FRSQRTES
= 0x0001000000000000ULL
,
538 /*****************************************************************************/
539 /* PowerPC instructions table */
540 #if HOST_LONG_BITS == 64
545 #if defined(__APPLE__)
546 #define OPCODES_SECTION \
547 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
549 #define OPCODES_SECTION \
550 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
553 #if defined(DO_PPC_STATISTICS)
554 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
555 OPCODES_SECTION opcode_t opc_##name = { \
563 .handler = &gen_##name, \
564 .oname = stringify(name), \
566 .oname = stringify(name), \
568 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
569 OPCODES_SECTION opcode_t opc_##name = { \
577 .handler = &gen_##name, \
583 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
584 OPCODES_SECTION opcode_t opc_##name = { \
592 .handler = &gen_##name, \
594 .oname = stringify(name), \
596 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
597 OPCODES_SECTION opcode_t opc_##name = { \
605 .handler = &gen_##name, \
611 #define GEN_OPCODE_MARK(name) \
612 OPCODES_SECTION opcode_t opc_##name = { \
618 .inval = 0x00000000, \
622 .oname = stringify(name), \
625 /* Start opcode list */
626 GEN_OPCODE_MARK(start
);
628 /* Invalid instruction */
629 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
)
634 static opc_handler_t invalid_handler
= {
637 .handler
= gen_invalid
,
640 /*** Integer arithmetic ***/
641 #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
642 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
644 gen_op_load_gpr_T0(rA(ctx->opcode)); \
645 gen_op_load_gpr_T1(rB(ctx->opcode)); \
647 gen_op_store_T0_gpr(rD(ctx->opcode)); \
648 if (unlikely(Rc(ctx->opcode) != 0)) \
652 #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
653 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
655 gen_op_load_gpr_T0(rA(ctx->opcode)); \
656 gen_op_load_gpr_T1(rB(ctx->opcode)); \
658 gen_op_store_T0_gpr(rD(ctx->opcode)); \
659 if (unlikely(Rc(ctx->opcode) != 0)) \
663 #define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
664 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
666 gen_op_load_gpr_T0(rA(ctx->opcode)); \
668 gen_op_store_T0_gpr(rD(ctx->opcode)); \
669 if (unlikely(Rc(ctx->opcode) != 0)) \
672 #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
673 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
675 gen_op_load_gpr_T0(rA(ctx->opcode)); \
677 gen_op_store_T0_gpr(rD(ctx->opcode)); \
678 if (unlikely(Rc(ctx->opcode) != 0)) \
682 /* Two operands arithmetic functions */
683 #define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
684 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
685 __GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
687 /* Two operands arithmetic functions with no overflow allowed */
688 #define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
689 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
691 /* One operand arithmetic functions */
692 #define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
693 __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
694 __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
696 #if defined(TARGET_PPC64)
697 #define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
698 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
700 gen_op_load_gpr_T0(rA(ctx->opcode)); \
701 gen_op_load_gpr_T1(rB(ctx->opcode)); \
703 gen_op_##name##_64(); \
706 gen_op_store_T0_gpr(rD(ctx->opcode)); \
707 if (unlikely(Rc(ctx->opcode) != 0)) \
711 #define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
712 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
714 gen_op_load_gpr_T0(rA(ctx->opcode)); \
715 gen_op_load_gpr_T1(rB(ctx->opcode)); \
717 gen_op_##name##_64(); \
720 gen_op_store_T0_gpr(rD(ctx->opcode)); \
721 if (unlikely(Rc(ctx->opcode) != 0)) \
725 #define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
726 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
728 gen_op_load_gpr_T0(rA(ctx->opcode)); \
730 gen_op_##name##_64(); \
733 gen_op_store_T0_gpr(rD(ctx->opcode)); \
734 if (unlikely(Rc(ctx->opcode) != 0)) \
737 #define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
738 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
740 gen_op_load_gpr_T0(rA(ctx->opcode)); \
742 gen_op_##name##_64(); \
745 gen_op_store_T0_gpr(rD(ctx->opcode)); \
746 if (unlikely(Rc(ctx->opcode) != 0)) \
750 /* Two operands arithmetic functions */
751 #define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
752 __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
753 __GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
755 /* Two operands arithmetic functions with no overflow allowed */
756 #define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
757 __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
759 /* One operand arithmetic functions */
760 #define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
761 __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
762 __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
764 #define GEN_INT_ARITH2_64 GEN_INT_ARITH2
765 #define GEN_INT_ARITHN_64 GEN_INT_ARITHN
766 #define GEN_INT_ARITH1_64 GEN_INT_ARITH1
769 /* add add. addo addo. */
770 static always_inline
void gen_op_addo (void)
776 #if defined(TARGET_PPC64)
777 #define gen_op_add_64 gen_op_add
778 static always_inline
void gen_op_addo_64 (void)
782 gen_op_check_addo_64();
785 GEN_INT_ARITH2_64 (add
, 0x1F, 0x0A, 0x08, PPC_INTEGER
);
786 /* addc addc. addco addco. */
787 static always_inline
void gen_op_addc (void)
793 static always_inline
void gen_op_addco (void)
800 #if defined(TARGET_PPC64)
801 static always_inline
void gen_op_addc_64 (void)
805 gen_op_check_addc_64();
807 static always_inline
void gen_op_addco_64 (void)
811 gen_op_check_addc_64();
812 gen_op_check_addo_64();
815 GEN_INT_ARITH2_64 (addc
, 0x1F, 0x0A, 0x00, PPC_INTEGER
);
816 /* adde adde. addeo addeo. */
817 static always_inline
void gen_op_addeo (void)
823 #if defined(TARGET_PPC64)
824 static always_inline
void gen_op_addeo_64 (void)
828 gen_op_check_addo_64();
831 GEN_INT_ARITH2_64 (adde
, 0x1F, 0x0A, 0x04, PPC_INTEGER
);
832 /* addme addme. addmeo addmeo. */
833 static always_inline
void gen_op_addme (void)
838 #if defined(TARGET_PPC64)
839 static always_inline
void gen_op_addme_64 (void)
845 GEN_INT_ARITH1_64 (addme
, 0x1F, 0x0A, 0x07, PPC_INTEGER
);
846 /* addze addze. addzeo addzeo. */
847 static always_inline
void gen_op_addze (void)
853 static always_inline
void gen_op_addzeo (void)
860 #if defined(TARGET_PPC64)
861 static always_inline
void gen_op_addze_64 (void)
865 gen_op_check_addc_64();
867 static always_inline
void gen_op_addzeo_64 (void)
871 gen_op_check_addc_64();
872 gen_op_check_addo_64();
875 GEN_INT_ARITH1_64 (addze
, 0x1F, 0x0A, 0x06, PPC_INTEGER
);
876 /* divw divw. divwo divwo. */
877 GEN_INT_ARITH2 (divw
, 0x1F, 0x0B, 0x0F, PPC_INTEGER
);
878 /* divwu divwu. divwuo divwuo. */
879 GEN_INT_ARITH2 (divwu
, 0x1F, 0x0B, 0x0E, PPC_INTEGER
);
881 GEN_INT_ARITHN (mulhw
, 0x1F, 0x0B, 0x02, PPC_INTEGER
);
883 GEN_INT_ARITHN (mulhwu
, 0x1F, 0x0B, 0x00, PPC_INTEGER
);
884 /* mullw mullw. mullwo mullwo. */
885 GEN_INT_ARITH2 (mullw
, 0x1F, 0x0B, 0x07, PPC_INTEGER
);
886 /* neg neg. nego nego. */
887 GEN_INT_ARITH1_64 (neg
, 0x1F, 0x08, 0x03, PPC_INTEGER
);
888 /* subf subf. subfo subfo. */
889 static always_inline
void gen_op_subfo (void)
893 gen_op_check_subfo();
895 #if defined(TARGET_PPC64)
896 #define gen_op_subf_64 gen_op_subf
897 static always_inline
void gen_op_subfo_64 (void)
901 gen_op_check_subfo_64();
904 GEN_INT_ARITH2_64 (subf
, 0x1F, 0x08, 0x01, PPC_INTEGER
);
905 /* subfc subfc. subfco subfco. */
906 static always_inline
void gen_op_subfc (void)
909 gen_op_check_subfc();
911 static always_inline
void gen_op_subfco (void)
915 gen_op_check_subfc();
916 gen_op_check_subfo();
918 #if defined(TARGET_PPC64)
919 static always_inline
void gen_op_subfc_64 (void)
922 gen_op_check_subfc_64();
924 static always_inline
void gen_op_subfco_64 (void)
928 gen_op_check_subfc_64();
929 gen_op_check_subfo_64();
932 GEN_INT_ARITH2_64 (subfc
, 0x1F, 0x08, 0x00, PPC_INTEGER
);
933 /* subfe subfe. subfeo subfeo. */
934 static always_inline
void gen_op_subfeo (void)
938 gen_op_check_subfo();
940 #if defined(TARGET_PPC64)
941 #define gen_op_subfe_64 gen_op_subfe
942 static always_inline
void gen_op_subfeo_64 (void)
946 gen_op_check_subfo_64();
949 GEN_INT_ARITH2_64 (subfe
, 0x1F, 0x08, 0x04, PPC_INTEGER
);
950 /* subfme subfme. subfmeo subfmeo. */
951 GEN_INT_ARITH1_64 (subfme
, 0x1F, 0x08, 0x07, PPC_INTEGER
);
952 /* subfze subfze. subfzeo subfzeo. */
953 GEN_INT_ARITH1_64 (subfze
, 0x1F, 0x08, 0x06, PPC_INTEGER
);
955 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
957 target_long simm
= SIMM(ctx
->opcode
);
959 if (rA(ctx
->opcode
) == 0) {
963 gen_op_load_gpr_T0(rA(ctx
->opcode
));
964 if (likely(simm
!= 0))
967 gen_op_store_T0_gpr(rD(ctx
->opcode
));
970 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
972 target_long simm
= SIMM(ctx
->opcode
);
974 gen_op_load_gpr_T0(rA(ctx
->opcode
));
975 if (likely(simm
!= 0)) {
978 #if defined(TARGET_PPC64)
980 gen_op_check_addc_64();
985 gen_op_clear_xer_ca();
987 gen_op_store_T0_gpr(rD(ctx
->opcode
));
990 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
992 target_long simm
= SIMM(ctx
->opcode
);
994 gen_op_load_gpr_T0(rA(ctx
->opcode
));
995 if (likely(simm
!= 0)) {
998 #if defined(TARGET_PPC64)
1000 gen_op_check_addc_64();
1003 gen_op_check_addc();
1005 gen_op_clear_xer_ca();
1007 gen_op_store_T0_gpr(rD(ctx
->opcode
));
1011 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1013 target_long simm
= SIMM(ctx
->opcode
);
1015 if (rA(ctx
->opcode
) == 0) {
1017 gen_set_T0(simm
<< 16);
1019 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1020 if (likely(simm
!= 0))
1021 gen_op_addi(simm
<< 16);
1023 gen_op_store_T0_gpr(rD(ctx
->opcode
));
1026 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1028 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1029 gen_op_mulli(SIMM(ctx
->opcode
));
1030 gen_op_store_T0_gpr(rD(ctx
->opcode
));
1033 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1035 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1036 #if defined(TARGET_PPC64)
1038 gen_op_subfic_64(SIMM(ctx
->opcode
));
1041 gen_op_subfic(SIMM(ctx
->opcode
));
1042 gen_op_store_T0_gpr(rD(ctx
->opcode
));
1045 #if defined(TARGET_PPC64)
1047 GEN_INT_ARITHN (mulhd
, 0x1F, 0x09, 0x02, PPC_64B
);
1048 /* mulhdu mulhdu. */
1049 GEN_INT_ARITHN (mulhdu
, 0x1F, 0x09, 0x00, PPC_64B
);
1050 /* mulld mulld. mulldo mulldo. */
1051 GEN_INT_ARITH2 (mulld
, 0x1F, 0x09, 0x07, PPC_64B
);
1052 /* divd divd. divdo divdo. */
1053 GEN_INT_ARITH2 (divd
, 0x1F, 0x09, 0x0F, PPC_64B
);
1054 /* divdu divdu. divduo divduo. */
1055 GEN_INT_ARITH2 (divdu
, 0x1F, 0x09, 0x0E, PPC_64B
);
1058 /*** Integer comparison ***/
1059 #if defined(TARGET_PPC64)
1060 #define GEN_CMP(name, opc, type) \
1061 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1063 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1064 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1065 if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \
1066 gen_op_##name##_64(); \
1069 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1072 #define GEN_CMP(name, opc, type) \
1073 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1075 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1076 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1078 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1083 GEN_CMP(cmp
, 0x00, PPC_INTEGER
);
1085 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
)
1087 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1088 #if defined(TARGET_PPC64)
1089 if (ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000))
1090 gen_op_cmpi_64(SIMM(ctx
->opcode
));
1093 gen_op_cmpi(SIMM(ctx
->opcode
));
1094 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1097 GEN_CMP(cmpl
, 0x01, PPC_INTEGER
);
1099 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
)
1101 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1102 #if defined(TARGET_PPC64)
1103 if (ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000))
1104 gen_op_cmpli_64(UIMM(ctx
->opcode
));
1107 gen_op_cmpli(UIMM(ctx
->opcode
));
1108 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1111 /* isel (PowerPC 2.03 specification) */
1112 GEN_HANDLER(isel
, 0x1F, 0x0F, 0x00, 0x00000001, PPC_203
)
1114 uint32_t bi
= rC(ctx
->opcode
);
1117 if (rA(ctx
->opcode
) == 0) {
1120 gen_op_load_gpr_T1(rA(ctx
->opcode
));
1122 gen_op_load_gpr_T2(rB(ctx
->opcode
));
1123 mask
= 1 << (3 - (bi
& 0x03));
1124 gen_op_load_crf_T0(bi
>> 2);
1125 gen_op_test_true(mask
);
1127 gen_op_store_T0_gpr(rD(ctx
->opcode
));
1130 /*** Integer logical ***/
1131 #define __GEN_LOGICAL2(name, opc2, opc3, type) \
1132 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \
1134 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1135 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1137 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1138 if (unlikely(Rc(ctx->opcode) != 0)) \
1141 #define GEN_LOGICAL2(name, opc, type) \
1142 __GEN_LOGICAL2(name, 0x1C, opc, type)
1144 #define GEN_LOGICAL1(name, opc, type) \
1145 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1147 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1149 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1150 if (unlikely(Rc(ctx->opcode) != 0)) \
1155 GEN_LOGICAL2(and, 0x00, PPC_INTEGER
);
1157 GEN_LOGICAL2(andc
, 0x01, PPC_INTEGER
);
1159 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1161 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1162 gen_op_andi_T0(UIMM(ctx
->opcode
));
1163 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1167 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1169 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1170 gen_op_andi_T0(UIMM(ctx
->opcode
) << 16);
1171 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1176 GEN_LOGICAL1(cntlzw
, 0x00, PPC_INTEGER
);
1178 GEN_LOGICAL2(eqv
, 0x08, PPC_INTEGER
);
1179 /* extsb & extsb. */
1180 GEN_LOGICAL1(extsb
, 0x1D, PPC_INTEGER
);
1181 /* extsh & extsh. */
1182 GEN_LOGICAL1(extsh
, 0x1C, PPC_INTEGER
);
1184 GEN_LOGICAL2(nand
, 0x0E, PPC_INTEGER
);
1186 GEN_LOGICAL2(nor
, 0x03, PPC_INTEGER
);
1189 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
)
1193 rs
= rS(ctx
->opcode
);
1194 ra
= rA(ctx
->opcode
);
1195 rb
= rB(ctx
->opcode
);
1196 /* Optimisation for mr. ri case */
1197 if (rs
!= ra
|| rs
!= rb
) {
1198 gen_op_load_gpr_T0(rs
);
1200 gen_op_load_gpr_T1(rb
);
1203 gen_op_store_T0_gpr(ra
);
1204 if (unlikely(Rc(ctx
->opcode
) != 0))
1206 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1207 gen_op_load_gpr_T0(rs
);
1209 #if defined(TARGET_PPC64)
1213 /* Set process priority to low */
1214 gen_op_store_pri(2);
1217 /* Set process priority to medium-low */
1218 gen_op_store_pri(3);
1221 /* Set process priority to normal */
1222 gen_op_store_pri(4);
1224 #if !defined(CONFIG_USER_ONLY)
1226 if (ctx
->supervisor
> 0) {
1227 /* Set process priority to very low */
1228 gen_op_store_pri(1);
1232 if (ctx
->supervisor
> 0) {
1233 /* Set process priority to medium-hight */
1234 gen_op_store_pri(5);
1238 if (ctx
->supervisor
> 0) {
1239 /* Set process priority to high */
1240 gen_op_store_pri(6);
1243 #if defined(TARGET_PPC64H)
1245 if (ctx
->supervisor
> 1) {
1246 /* Set process priority to very high */
1247 gen_op_store_pri(7);
1261 GEN_LOGICAL2(orc
, 0x0C, PPC_INTEGER
);
1263 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
)
1265 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1266 /* Optimisation for "set to zero" case */
1267 if (rS(ctx
->opcode
) != rB(ctx
->opcode
)) {
1268 gen_op_load_gpr_T1(rB(ctx
->opcode
));
1273 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1274 if (unlikely(Rc(ctx
->opcode
) != 0))
1278 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1280 target_ulong uimm
= UIMM(ctx
->opcode
);
1282 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1284 /* XXX: should handle special NOPs for POWER series */
1287 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1288 if (likely(uimm
!= 0))
1290 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1293 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1295 target_ulong uimm
= UIMM(ctx
->opcode
);
1297 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1301 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1302 if (likely(uimm
!= 0))
1303 gen_op_ori(uimm
<< 16);
1304 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1307 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1309 target_ulong uimm
= UIMM(ctx
->opcode
);
1311 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1315 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1316 if (likely(uimm
!= 0))
1318 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1322 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1324 target_ulong uimm
= UIMM(ctx
->opcode
);
1326 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1330 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1331 if (likely(uimm
!= 0))
1332 gen_op_xori(uimm
<< 16);
1333 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1336 /* popcntb : PowerPC 2.03 specification */
1337 GEN_HANDLER(popcntb
, 0x1F, 0x03, 0x03, 0x0000F801, PPC_203
)
1339 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1340 #if defined(TARGET_PPC64)
1342 gen_op_popcntb_64();
1346 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1349 #if defined(TARGET_PPC64)
1350 /* extsw & extsw. */
1351 GEN_LOGICAL1(extsw
, 0x1E, PPC_64B
);
1353 GEN_LOGICAL1(cntlzd
, 0x01, PPC_64B
);
1356 /*** Integer rotate ***/
1357 /* rlwimi & rlwimi. */
1358 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1361 uint32_t mb
, me
, sh
;
1363 mb
= MB(ctx
->opcode
);
1364 me
= ME(ctx
->opcode
);
1365 sh
= SH(ctx
->opcode
);
1366 if (likely(sh
== 0)) {
1367 if (likely(mb
== 0 && me
== 31)) {
1368 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1370 } else if (likely(mb
== 31 && me
== 0)) {
1371 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1374 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1375 gen_op_load_gpr_T1(rA(ctx
->opcode
));
1378 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1379 gen_op_load_gpr_T1(rA(ctx
->opcode
));
1380 gen_op_rotli32_T0(SH(ctx
->opcode
));
1382 #if defined(TARGET_PPC64)
1386 mask
= MASK(mb
, me
);
1387 gen_op_andi_T0(mask
);
1388 gen_op_andi_T1(~mask
);
1391 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1392 if (unlikely(Rc(ctx
->opcode
) != 0))
1395 /* rlwinm & rlwinm. */
1396 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1398 uint32_t mb
, me
, sh
;
1400 sh
= SH(ctx
->opcode
);
1401 mb
= MB(ctx
->opcode
);
1402 me
= ME(ctx
->opcode
);
1403 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1404 if (likely(sh
== 0)) {
1407 if (likely(mb
== 0)) {
1408 if (likely(me
== 31)) {
1409 gen_op_rotli32_T0(sh
);
1411 } else if (likely(me
== (31 - sh
))) {
1415 } else if (likely(me
== 31)) {
1416 if (likely(sh
== (32 - mb
))) {
1421 gen_op_rotli32_T0(sh
);
1423 #if defined(TARGET_PPC64)
1427 gen_op_andi_T0(MASK(mb
, me
));
1429 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1430 if (unlikely(Rc(ctx
->opcode
) != 0))
1433 /* rlwnm & rlwnm. */
1434 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1438 mb
= MB(ctx
->opcode
);
1439 me
= ME(ctx
->opcode
);
1440 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1441 gen_op_load_gpr_T1(rB(ctx
->opcode
));
1442 gen_op_rotl32_T0_T1();
1443 if (unlikely(mb
!= 0 || me
!= 31)) {
1444 #if defined(TARGET_PPC64)
1448 gen_op_andi_T0(MASK(mb
, me
));
1450 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1451 if (unlikely(Rc(ctx
->opcode
) != 0))
1455 #if defined(TARGET_PPC64)
1456 #define GEN_PPC64_R2(name, opc1, opc2) \
1457 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1459 gen_##name(ctx, 0); \
1461 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1464 gen_##name(ctx, 1); \
1466 #define GEN_PPC64_R4(name, opc1, opc2) \
1467 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1469 gen_##name(ctx, 0, 0); \
1471 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1474 gen_##name(ctx, 0, 1); \
1476 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1479 gen_##name(ctx, 1, 0); \
1481 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1484 gen_##name(ctx, 1, 1); \
1487 static always_inline
void gen_andi_T0_64 (DisasContext
*ctx
, uint64_t mask
)
1490 gen_op_andi_T0_64(mask
>> 32, mask
& 0xFFFFFFFF);
1492 gen_op_andi_T0(mask
);
1495 static always_inline
void gen_andi_T1_64 (DisasContext
*ctx
, uint64_t mask
)
1498 gen_op_andi_T1_64(mask
>> 32, mask
& 0xFFFFFFFF);
1500 gen_op_andi_T1(mask
);
1503 static always_inline
void gen_rldinm (DisasContext
*ctx
, uint32_t mb
,
1504 uint32_t me
, uint32_t sh
)
1506 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1507 if (likely(sh
== 0)) {
1510 if (likely(mb
== 0)) {
1511 if (likely(me
== 63)) {
1512 gen_op_rotli64_T0(sh
);
1514 } else if (likely(me
== (63 - sh
))) {
1518 } else if (likely(me
== 63)) {
1519 if (likely(sh
== (64 - mb
))) {
1520 gen_op_srli_T0_64(mb
);
1524 gen_op_rotli64_T0(sh
);
1526 gen_andi_T0_64(ctx
, MASK(mb
, me
));
1528 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1529 if (unlikely(Rc(ctx
->opcode
) != 0))
1532 /* rldicl - rldicl. */
1533 static always_inline
void gen_rldicl (DisasContext
*ctx
, int mbn
, int shn
)
1537 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1538 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1539 gen_rldinm(ctx
, mb
, 63, sh
);
1541 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
1542 /* rldicr - rldicr. */
1543 static always_inline
void gen_rldicr (DisasContext
*ctx
, int men
, int shn
)
1547 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1548 me
= MB(ctx
->opcode
) | (men
<< 5);
1549 gen_rldinm(ctx
, 0, me
, sh
);
1551 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
1552 /* rldic - rldic. */
1553 static always_inline
void gen_rldic (DisasContext
*ctx
, int mbn
, int shn
)
1557 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1558 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1559 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
1561 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
1563 static always_inline
void gen_rldnm (DisasContext
*ctx
, uint32_t mb
,
1566 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1567 gen_op_load_gpr_T1(rB(ctx
->opcode
));
1568 gen_op_rotl64_T0_T1();
1569 if (unlikely(mb
!= 0 || me
!= 63)) {
1570 gen_andi_T0_64(ctx
, MASK(mb
, me
));
1572 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1573 if (unlikely(Rc(ctx
->opcode
) != 0))
1577 /* rldcl - rldcl. */
1578 static always_inline
void gen_rldcl (DisasContext
*ctx
, int mbn
)
1582 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1583 gen_rldnm(ctx
, mb
, 63);
1585 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
1586 /* rldcr - rldcr. */
1587 static always_inline
void gen_rldcr (DisasContext
*ctx
, int men
)
1591 me
= MB(ctx
->opcode
) | (men
<< 5);
1592 gen_rldnm(ctx
, 0, me
);
1594 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
1595 /* rldimi - rldimi. */
1596 static always_inline
void gen_rldimi (DisasContext
*ctx
, int mbn
, int shn
)
1601 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1602 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1603 if (likely(sh
== 0)) {
1604 if (likely(mb
== 0)) {
1605 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1607 } else if (likely(mb
== 63)) {
1608 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1611 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1612 gen_op_load_gpr_T1(rA(ctx
->opcode
));
1615 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1616 gen_op_load_gpr_T1(rA(ctx
->opcode
));
1617 gen_op_rotli64_T0(sh
);
1619 mask
= MASK(mb
, 63 - sh
);
1620 gen_andi_T0_64(ctx
, mask
);
1621 gen_andi_T1_64(ctx
, ~mask
);
1624 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1625 if (unlikely(Rc(ctx
->opcode
) != 0))
1628 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
1631 /*** Integer shift ***/
1633 __GEN_LOGICAL2(slw
, 0x18, 0x00, PPC_INTEGER
);
1635 __GEN_LOGICAL2(sraw
, 0x18, 0x18, PPC_INTEGER
);
1636 /* srawi & srawi. */
1637 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
)
1640 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1641 if (SH(ctx
->opcode
) != 0) {
1642 gen_op_move_T1_T0();
1643 mb
= 32 - SH(ctx
->opcode
);
1645 #if defined(TARGET_PPC64)
1649 gen_op_srawi(SH(ctx
->opcode
), MASK(mb
, me
));
1651 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1652 if (unlikely(Rc(ctx
->opcode
) != 0))
1656 __GEN_LOGICAL2(srw
, 0x18, 0x10, PPC_INTEGER
);
1658 #if defined(TARGET_PPC64)
1660 __GEN_LOGICAL2(sld
, 0x1B, 0x00, PPC_64B
);
1662 __GEN_LOGICAL2(srad
, 0x1A, 0x18, PPC_64B
);
1663 /* sradi & sradi. */
1664 static always_inline
void gen_sradi (DisasContext
*ctx
, int n
)
1669 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1670 sh
= SH(ctx
->opcode
) + (n
<< 5);
1672 gen_op_move_T1_T0();
1673 mb
= 64 - SH(ctx
->opcode
);
1675 mask
= MASK(mb
, me
);
1676 gen_op_sradi(sh
, mask
>> 32, mask
);
1678 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1679 if (unlikely(Rc(ctx
->opcode
) != 0))
1682 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
)
1686 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
)
1691 __GEN_LOGICAL2(srd
, 0x1B, 0x10, PPC_64B
);
1694 /*** Floating-Point arithmetic ***/
1695 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1696 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
1698 if (unlikely(!ctx->fpu_enabled)) { \
1699 GEN_EXCP_NO_FP(ctx); \
1702 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1703 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1704 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
1705 gen_reset_fpstatus(); \
1710 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1711 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1714 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1715 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1716 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1718 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1719 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
1721 if (unlikely(!ctx->fpu_enabled)) { \
1722 GEN_EXCP_NO_FP(ctx); \
1725 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1726 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
1727 gen_reset_fpstatus(); \
1732 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1733 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1735 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1736 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1737 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1739 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1740 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
1742 if (unlikely(!ctx->fpu_enabled)) { \
1743 GEN_EXCP_NO_FP(ctx); \
1746 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1747 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1748 gen_reset_fpstatus(); \
1753 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1754 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1756 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1757 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1758 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1760 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
1761 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
1763 if (unlikely(!ctx->fpu_enabled)) { \
1764 GEN_EXCP_NO_FP(ctx); \
1767 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
1768 gen_reset_fpstatus(); \
1770 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1771 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1774 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
1775 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
1777 if (unlikely(!ctx->fpu_enabled)) { \
1778 GEN_EXCP_NO_FP(ctx); \
1781 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
1782 gen_reset_fpstatus(); \
1784 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1785 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1789 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
);
1791 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
);
1793 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
);
1796 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
);
1799 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
);
1802 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
);
1805 static always_inline
void gen_op_frsqrtes (void)
1810 GEN_FLOAT_BS(rsqrtes
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTES
);
1813 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
);
1815 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
);
1818 GEN_HANDLER(fsqrt
, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
)
1820 if (unlikely(!ctx
->fpu_enabled
)) {
1821 GEN_EXCP_NO_FP(ctx
);
1824 gen_op_load_fpr_FT0(rB(ctx
->opcode
));
1825 gen_reset_fpstatus();
1827 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
1828 gen_compute_fprf(1, Rc(ctx
->opcode
) != 0);
1831 GEN_HANDLER(fsqrts
, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
)
1833 if (unlikely(!ctx
->fpu_enabled
)) {
1834 GEN_EXCP_NO_FP(ctx
);
1837 gen_op_load_fpr_FT0(rB(ctx
->opcode
));
1838 gen_reset_fpstatus();
1841 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
1842 gen_compute_fprf(1, Rc(ctx
->opcode
) != 0);
1845 /*** Floating-Point multiply-and-add ***/
1846 /* fmadd - fmadds */
1847 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
);
1848 /* fmsub - fmsubs */
1849 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
);
1850 /* fnmadd - fnmadds */
1851 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
);
1852 /* fnmsub - fnmsubs */
1853 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
);
1855 /*** Floating-Point round & convert ***/
1857 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
);
1859 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
);
1861 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
);
1862 #if defined(TARGET_PPC64)
1864 GEN_FLOAT_B(cfid
, 0x0E, 0x1A, 1, PPC_64B
);
1866 GEN_FLOAT_B(ctid
, 0x0E, 0x19, 0, PPC_64B
);
1868 GEN_FLOAT_B(ctidz
, 0x0F, 0x19, 0, PPC_64B
);
1872 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
);
1874 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
);
1876 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
);
1878 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
);
1880 /*** Floating-Point compare ***/
1882 GEN_HANDLER(fcmpo
, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT
)
1884 if (unlikely(!ctx
->fpu_enabled
)) {
1885 GEN_EXCP_NO_FP(ctx
);
1888 gen_op_load_fpr_FT0(rA(ctx
->opcode
));
1889 gen_op_load_fpr_FT1(rB(ctx
->opcode
));
1890 gen_reset_fpstatus();
1892 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1893 gen_op_float_check_status();
1897 GEN_HANDLER(fcmpu
, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT
)
1899 if (unlikely(!ctx
->fpu_enabled
)) {
1900 GEN_EXCP_NO_FP(ctx
);
1903 gen_op_load_fpr_FT0(rA(ctx
->opcode
));
1904 gen_op_load_fpr_FT1(rB(ctx
->opcode
));
1905 gen_reset_fpstatus();
1907 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1908 gen_op_float_check_status();
1911 /*** Floating-point move ***/
1913 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
1914 GEN_FLOAT_B(abs
, 0x08, 0x08, 0, PPC_FLOAT
);
1917 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
1918 GEN_HANDLER(fmr
, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT
)
1920 if (unlikely(!ctx
->fpu_enabled
)) {
1921 GEN_EXCP_NO_FP(ctx
);
1924 gen_op_load_fpr_FT0(rB(ctx
->opcode
));
1925 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
1926 gen_compute_fprf(0, Rc(ctx
->opcode
) != 0);
1930 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
1931 GEN_FLOAT_B(nabs
, 0x08, 0x04, 0, PPC_FLOAT
);
1933 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
1934 GEN_FLOAT_B(neg
, 0x08, 0x01, 0, PPC_FLOAT
);
1936 /*** Floating-Point status & ctrl register ***/
1938 GEN_HANDLER(mcrfs
, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT
)
1942 if (unlikely(!ctx
->fpu_enabled
)) {
1943 GEN_EXCP_NO_FP(ctx
);
1946 gen_optimize_fprf();
1947 bfa
= 4 * (7 - crfS(ctx
->opcode
));
1948 gen_op_load_fpscr_T0(bfa
);
1949 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1950 gen_op_fpscr_resetbit(~(0xF << bfa
));
1954 GEN_HANDLER(mffs
, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT
)
1956 if (unlikely(!ctx
->fpu_enabled
)) {
1957 GEN_EXCP_NO_FP(ctx
);
1960 gen_optimize_fprf();
1961 gen_reset_fpstatus();
1962 gen_op_load_fpscr_FT0();
1963 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
1964 gen_compute_fprf(0, Rc(ctx
->opcode
) != 0);
1968 GEN_HANDLER(mtfsb0
, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT
)
1972 if (unlikely(!ctx
->fpu_enabled
)) {
1973 GEN_EXCP_NO_FP(ctx
);
1976 crb
= 32 - (crbD(ctx
->opcode
) >> 2);
1977 gen_optimize_fprf();
1978 gen_reset_fpstatus();
1979 if (likely(crb
!= 30 && crb
!= 29))
1980 gen_op_fpscr_resetbit(~(1 << crb
));
1981 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1988 GEN_HANDLER(mtfsb1
, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT
)
1992 if (unlikely(!ctx
->fpu_enabled
)) {
1993 GEN_EXCP_NO_FP(ctx
);
1996 crb
= 32 - (crbD(ctx
->opcode
) >> 2);
1997 gen_optimize_fprf();
1998 gen_reset_fpstatus();
1999 /* XXX: we pretend we can only do IEEE floating-point computations */
2000 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
&& crb
!= FPSCR_NI
))
2001 gen_op_fpscr_setbit(crb
);
2002 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2006 /* We can raise a differed exception */
2007 gen_op_float_check_status();
2011 GEN_HANDLER(mtfsf
, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT
)
2013 if (unlikely(!ctx
->fpu_enabled
)) {
2014 GEN_EXCP_NO_FP(ctx
);
2017 gen_optimize_fprf();
2018 gen_op_load_fpr_FT0(rB(ctx
->opcode
));
2019 gen_reset_fpstatus();
2020 gen_op_store_fpscr(FM(ctx
->opcode
));
2021 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2025 /* We can raise a differed exception */
2026 gen_op_float_check_status();
2030 GEN_HANDLER(mtfsfi
, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT
)
2034 if (unlikely(!ctx
->fpu_enabled
)) {
2035 GEN_EXCP_NO_FP(ctx
);
2038 bf
= crbD(ctx
->opcode
) >> 2;
2040 gen_optimize_fprf();
2041 gen_op_set_FT0(FPIMM(ctx
->opcode
) << (4 * sh
));
2042 gen_reset_fpstatus();
2043 gen_op_store_fpscr(1 << sh
);
2044 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2048 /* We can raise a differed exception */
2049 gen_op_float_check_status();
2052 /*** Addressing modes ***/
2053 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2054 static always_inline
void gen_addr_imm_index (DisasContext
*ctx
,
2057 target_long simm
= SIMM(ctx
->opcode
);
2060 if (rA(ctx
->opcode
) == 0) {
2063 gen_op_load_gpr_T0(rA(ctx
->opcode
));
2064 if (likely(simm
!= 0))
2067 #ifdef DEBUG_MEMORY_ACCESSES
2068 gen_op_print_mem_EA();
2072 static always_inline
void gen_addr_reg_index (DisasContext
*ctx
)
2074 if (rA(ctx
->opcode
) == 0) {
2075 gen_op_load_gpr_T0(rB(ctx
->opcode
));
2077 gen_op_load_gpr_T0(rA(ctx
->opcode
));
2078 gen_op_load_gpr_T1(rB(ctx
->opcode
));
2081 #ifdef DEBUG_MEMORY_ACCESSES
2082 gen_op_print_mem_EA();
2086 static always_inline
void gen_addr_register (DisasContext
*ctx
)
2088 if (rA(ctx
->opcode
) == 0) {
2091 gen_op_load_gpr_T0(rA(ctx
->opcode
));
2093 #ifdef DEBUG_MEMORY_ACCESSES
2094 gen_op_print_mem_EA();
2098 /*** Integer load ***/
2099 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
2100 #if defined(CONFIG_USER_ONLY)
2101 #if defined(TARGET_PPC64)
2102 /* User mode only - 64 bits */
2103 #define OP_LD_TABLE(width) \
2104 static GenOpFunc *gen_op_l##width[] = { \
2105 &gen_op_l##width##_raw, \
2106 &gen_op_l##width##_le_raw, \
2107 &gen_op_l##width##_64_raw, \
2108 &gen_op_l##width##_le_64_raw, \
2110 #define OP_ST_TABLE(width) \
2111 static GenOpFunc *gen_op_st##width[] = { \
2112 &gen_op_st##width##_raw, \
2113 &gen_op_st##width##_le_raw, \
2114 &gen_op_st##width##_64_raw, \
2115 &gen_op_st##width##_le_64_raw, \
2117 /* Byte access routine are endian safe */
2118 #define gen_op_stb_le_64_raw gen_op_stb_64_raw
2119 #define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
2121 /* User mode only - 32 bits */
2122 #define OP_LD_TABLE(width) \
2123 static GenOpFunc *gen_op_l##width[] = { \
2124 &gen_op_l##width##_raw, \
2125 &gen_op_l##width##_le_raw, \
2127 #define OP_ST_TABLE(width) \
2128 static GenOpFunc *gen_op_st##width[] = { \
2129 &gen_op_st##width##_raw, \
2130 &gen_op_st##width##_le_raw, \
2133 /* Byte access routine are endian safe */
2134 #define gen_op_stb_le_raw gen_op_stb_raw
2135 #define gen_op_lbz_le_raw gen_op_lbz_raw
2137 #if defined(TARGET_PPC64)
2138 #if defined(TARGET_PPC64H)
2139 /* Full system - 64 bits with hypervisor mode */
2140 #define OP_LD_TABLE(width) \
2141 static GenOpFunc *gen_op_l##width[] = { \
2142 &gen_op_l##width##_user, \
2143 &gen_op_l##width##_le_user, \
2144 &gen_op_l##width##_64_user, \
2145 &gen_op_l##width##_le_64_user, \
2146 &gen_op_l##width##_kernel, \
2147 &gen_op_l##width##_le_kernel, \
2148 &gen_op_l##width##_64_kernel, \
2149 &gen_op_l##width##_le_64_kernel, \
2150 &gen_op_l##width##_hypv, \
2151 &gen_op_l##width##_le_hypv, \
2152 &gen_op_l##width##_64_hypv, \
2153 &gen_op_l##width##_le_64_hypv, \
2155 #define OP_ST_TABLE(width) \
2156 static GenOpFunc *gen_op_st##width[] = { \
2157 &gen_op_st##width##_user, \
2158 &gen_op_st##width##_le_user, \
2159 &gen_op_st##width##_64_user, \
2160 &gen_op_st##width##_le_64_user, \
2161 &gen_op_st##width##_kernel, \
2162 &gen_op_st##width##_le_kernel, \
2163 &gen_op_st##width##_64_kernel, \
2164 &gen_op_st##width##_le_64_kernel, \
2165 &gen_op_st##width##_hypv, \
2166 &gen_op_st##width##_le_hypv, \
2167 &gen_op_st##width##_64_hypv, \
2168 &gen_op_st##width##_le_64_hypv, \
2170 /* Byte access routine are endian safe */
2171 #define gen_op_stb_le_hypv gen_op_stb_64_hypv
2172 #define gen_op_lbz_le_hypv gen_op_lbz_64_hypv
2173 #define gen_op_stb_le_64_hypv gen_op_stb_64_hypv
2174 #define gen_op_lbz_le_64_hypv gen_op_lbz_64_hypv
2176 /* Full system - 64 bits */
2177 #define OP_LD_TABLE(width) \
2178 static GenOpFunc *gen_op_l##width[] = { \
2179 &gen_op_l##width##_user, \
2180 &gen_op_l##width##_le_user, \
2181 &gen_op_l##width##_64_user, \
2182 &gen_op_l##width##_le_64_user, \
2183 &gen_op_l##width##_kernel, \
2184 &gen_op_l##width##_le_kernel, \
2185 &gen_op_l##width##_64_kernel, \
2186 &gen_op_l##width##_le_64_kernel, \
2188 #define OP_ST_TABLE(width) \
2189 static GenOpFunc *gen_op_st##width[] = { \
2190 &gen_op_st##width##_user, \
2191 &gen_op_st##width##_le_user, \
2192 &gen_op_st##width##_64_user, \
2193 &gen_op_st##width##_le_64_user, \
2194 &gen_op_st##width##_kernel, \
2195 &gen_op_st##width##_le_kernel, \
2196 &gen_op_st##width##_64_kernel, \
2197 &gen_op_st##width##_le_64_kernel, \
2200 /* Byte access routine are endian safe */
2201 #define gen_op_stb_le_64_user gen_op_stb_64_user
2202 #define gen_op_lbz_le_64_user gen_op_lbz_64_user
2203 #define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2204 #define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
2206 /* Full system - 32 bits */
2207 #define OP_LD_TABLE(width) \
2208 static GenOpFunc *gen_op_l##width[] = { \
2209 &gen_op_l##width##_user, \
2210 &gen_op_l##width##_le_user, \
2211 &gen_op_l##width##_kernel, \
2212 &gen_op_l##width##_le_kernel, \
2214 #define OP_ST_TABLE(width) \
2215 static GenOpFunc *gen_op_st##width[] = { \
2216 &gen_op_st##width##_user, \
2217 &gen_op_st##width##_le_user, \
2218 &gen_op_st##width##_kernel, \
2219 &gen_op_st##width##_le_kernel, \
2222 /* Byte access routine are endian safe */
2223 #define gen_op_stb_le_user gen_op_stb_user
2224 #define gen_op_lbz_le_user gen_op_lbz_user
2225 #define gen_op_stb_le_kernel gen_op_stb_kernel
2226 #define gen_op_lbz_le_kernel gen_op_lbz_kernel
2229 #define GEN_LD(width, opc, type) \
2230 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2232 gen_addr_imm_index(ctx, 0); \
2233 op_ldst(l##width); \
2234 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2237 #define GEN_LDU(width, opc, type) \
2238 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2240 if (unlikely(rA(ctx->opcode) == 0 || \
2241 rA(ctx->opcode) == rD(ctx->opcode))) { \
2242 GEN_EXCP_INVAL(ctx); \
2245 if (type == PPC_64B) \
2246 gen_addr_imm_index(ctx, 0x03); \
2248 gen_addr_imm_index(ctx, 0); \
2249 op_ldst(l##width); \
2250 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2251 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2254 #define GEN_LDUX(width, opc2, opc3, type) \
2255 GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2257 if (unlikely(rA(ctx->opcode) == 0 || \
2258 rA(ctx->opcode) == rD(ctx->opcode))) { \
2259 GEN_EXCP_INVAL(ctx); \
2262 gen_addr_reg_index(ctx); \
2263 op_ldst(l##width); \
2264 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2265 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2268 #define GEN_LDX(width, opc2, opc3, type) \
2269 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2271 gen_addr_reg_index(ctx); \
2272 op_ldst(l##width); \
2273 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2276 #define GEN_LDS(width, op, type) \
2277 OP_LD_TABLE(width); \
2278 GEN_LD(width, op | 0x20, type); \
2279 GEN_LDU(width, op | 0x21, type); \
2280 GEN_LDUX(width, 0x17, op | 0x01, type); \
2281 GEN_LDX(width, 0x17, op | 0x00, type)
2283 /* lbz lbzu lbzux lbzx */
2284 GEN_LDS(bz
, 0x02, PPC_INTEGER
);
2285 /* lha lhau lhaux lhax */
2286 GEN_LDS(ha
, 0x0A, PPC_INTEGER
);
2287 /* lhz lhzu lhzux lhzx */
2288 GEN_LDS(hz
, 0x08, PPC_INTEGER
);
2289 /* lwz lwzu lwzux lwzx */
2290 GEN_LDS(wz
, 0x00, PPC_INTEGER
);
2291 #if defined(TARGET_PPC64)
2295 GEN_LDUX(wa
, 0x15, 0x0B, PPC_64B
);
2297 GEN_LDX(wa
, 0x15, 0x0A, PPC_64B
);
2299 GEN_LDUX(d
, 0x15, 0x01, PPC_64B
);
2301 GEN_LDX(d
, 0x15, 0x00, PPC_64B
);
2302 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
)
2304 if (Rc(ctx
->opcode
)) {
2305 if (unlikely(rA(ctx
->opcode
) == 0 ||
2306 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2307 GEN_EXCP_INVAL(ctx
);
2311 gen_addr_imm_index(ctx
, 0x03);
2312 if (ctx
->opcode
& 0x02) {
2313 /* lwa (lwau is undefined) */
2319 gen_op_store_T1_gpr(rD(ctx
->opcode
));
2320 if (Rc(ctx
->opcode
))
2321 gen_op_store_T0_gpr(rA(ctx
->opcode
));
2324 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
)
2326 #if defined(CONFIG_USER_ONLY)
2327 GEN_EXCP_PRIVOPC(ctx
);
2331 /* Restore CPU state */
2332 if (unlikely(ctx
->supervisor
== 0)) {
2333 GEN_EXCP_PRIVOPC(ctx
);
2336 ra
= rA(ctx
->opcode
);
2337 rd
= rD(ctx
->opcode
);
2338 if (unlikely((rd
& 1) || rd
== ra
)) {
2339 GEN_EXCP_INVAL(ctx
);
2342 if (unlikely(ctx
->mem_idx
& 1)) {
2343 /* Little-endian mode is not handled */
2344 GEN_EXCP(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2347 gen_addr_imm_index(ctx
, 0x0F);
2349 gen_op_store_T1_gpr(rd
);
2352 gen_op_store_T1_gpr(rd
+ 1);
2357 /*** Integer store ***/
2358 #define GEN_ST(width, opc, type) \
2359 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2361 gen_addr_imm_index(ctx, 0); \
2362 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2363 op_ldst(st##width); \
2366 #define GEN_STU(width, opc, type) \
2367 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2369 if (unlikely(rA(ctx->opcode) == 0)) { \
2370 GEN_EXCP_INVAL(ctx); \
2373 if (type == PPC_64B) \
2374 gen_addr_imm_index(ctx, 0x03); \
2376 gen_addr_imm_index(ctx, 0); \
2377 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2378 op_ldst(st##width); \
2379 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2382 #define GEN_STUX(width, opc2, opc3, type) \
2383 GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2385 if (unlikely(rA(ctx->opcode) == 0)) { \
2386 GEN_EXCP_INVAL(ctx); \
2389 gen_addr_reg_index(ctx); \
2390 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2391 op_ldst(st##width); \
2392 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2395 #define GEN_STX(width, opc2, opc3, type) \
2396 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2398 gen_addr_reg_index(ctx); \
2399 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2400 op_ldst(st##width); \
2403 #define GEN_STS(width, op, type) \
2404 OP_ST_TABLE(width); \
2405 GEN_ST(width, op | 0x20, type); \
2406 GEN_STU(width, op | 0x21, type); \
2407 GEN_STUX(width, 0x17, op | 0x01, type); \
2408 GEN_STX(width, 0x17, op | 0x00, type)
2410 /* stb stbu stbux stbx */
2411 GEN_STS(b
, 0x06, PPC_INTEGER
);
2412 /* sth sthu sthux sthx */
2413 GEN_STS(h
, 0x0C, PPC_INTEGER
);
2414 /* stw stwu stwux stwx */
2415 GEN_STS(w
, 0x04, PPC_INTEGER
);
2416 #if defined(TARGET_PPC64)
2418 GEN_STUX(d
, 0x15, 0x05, PPC_64B
);
2419 GEN_STX(d
, 0x15, 0x04, PPC_64B
);
2420 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
)
2424 rs
= rS(ctx
->opcode
);
2425 if ((ctx
->opcode
& 0x3) == 0x2) {
2426 #if defined(CONFIG_USER_ONLY)
2427 GEN_EXCP_PRIVOPC(ctx
);
2430 if (unlikely(ctx
->supervisor
== 0)) {
2431 GEN_EXCP_PRIVOPC(ctx
);
2434 if (unlikely(rs
& 1)) {
2435 GEN_EXCP_INVAL(ctx
);
2438 if (unlikely(ctx
->mem_idx
& 1)) {
2439 /* Little-endian mode is not handled */
2440 GEN_EXCP(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2443 gen_addr_imm_index(ctx
, 0x03);
2444 gen_op_load_gpr_T1(rs
);
2447 gen_op_load_gpr_T1(rs
+ 1);
2452 if (Rc(ctx
->opcode
)) {
2453 if (unlikely(rA(ctx
->opcode
) == 0)) {
2454 GEN_EXCP_INVAL(ctx
);
2458 gen_addr_imm_index(ctx
, 0x03);
2459 gen_op_load_gpr_T1(rs
);
2461 if (Rc(ctx
->opcode
))
2462 gen_op_store_T0_gpr(rA(ctx
->opcode
));
2466 /*** Integer load and store with byte reverse ***/
2469 GEN_LDX(hbr
, 0x16, 0x18, PPC_INTEGER
);
2472 GEN_LDX(wbr
, 0x16, 0x10, PPC_INTEGER
);
2475 GEN_STX(hbr
, 0x16, 0x1C, PPC_INTEGER
);
2478 GEN_STX(wbr
, 0x16, 0x14, PPC_INTEGER
);
2480 /*** Integer load and store multiple ***/
2481 #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
2482 #if defined(CONFIG_USER_ONLY)
2483 /* User-mode only */
2484 static GenOpFunc1
*gen_op_lmw
[] = {
2487 #if defined(TARGET_PPC64)
2489 &gen_op_lmw_le_64_raw
,
2492 static GenOpFunc1
*gen_op_stmw
[] = {
2494 &gen_op_stmw_le_raw
,
2495 #if defined(TARGET_PPC64)
2496 &gen_op_stmw_64_raw
,
2497 &gen_op_stmw_le_64_raw
,
2501 #if defined(TARGET_PPC64)
2502 /* Full system - 64 bits mode */
2503 static GenOpFunc1
*gen_op_lmw
[] = {
2505 &gen_op_lmw_le_user
,
2506 &gen_op_lmw_64_user
,
2507 &gen_op_lmw_le_64_user
,
2509 &gen_op_lmw_le_kernel
,
2510 &gen_op_lmw_64_kernel
,
2511 &gen_op_lmw_le_64_kernel
,
2512 #if defined(TARGET_PPC64H)
2514 &gen_op_lmw_le_hypv
,
2515 &gen_op_lmw_64_hypv
,
2516 &gen_op_lmw_le_64_hypv
,
2519 static GenOpFunc1
*gen_op_stmw
[] = {
2521 &gen_op_stmw_le_user
,
2522 &gen_op_stmw_64_user
,
2523 &gen_op_stmw_le_64_user
,
2524 &gen_op_stmw_kernel
,
2525 &gen_op_stmw_le_kernel
,
2526 &gen_op_stmw_64_kernel
,
2527 &gen_op_stmw_le_64_kernel
,
2528 #if defined(TARGET_PPC64H)
2530 &gen_op_stmw_le_hypv
,
2531 &gen_op_stmw_64_hypv
,
2532 &gen_op_stmw_le_64_hypv
,
2536 /* Full system - 32 bits mode */
2537 static GenOpFunc1
*gen_op_lmw
[] = {
2539 &gen_op_lmw_le_user
,
2541 &gen_op_lmw_le_kernel
,
2543 static GenOpFunc1
*gen_op_stmw
[] = {
2545 &gen_op_stmw_le_user
,
2546 &gen_op_stmw_kernel
,
2547 &gen_op_stmw_le_kernel
,
2553 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
2555 /* NIP cannot be restored if the memory exception comes from an helper */
2556 gen_update_nip(ctx
, ctx
->nip
- 4);
2557 gen_addr_imm_index(ctx
, 0);
2558 op_ldstm(lmw
, rD(ctx
->opcode
));
2562 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
2564 /* NIP cannot be restored if the memory exception comes from an helper */
2565 gen_update_nip(ctx
, ctx
->nip
- 4);
2566 gen_addr_imm_index(ctx
, 0);
2567 op_ldstm(stmw
, rS(ctx
->opcode
));
2570 /*** Integer load and store strings ***/
2571 #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2572 #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
2573 #if defined(CONFIG_USER_ONLY)
2574 /* User-mode only */
2575 static GenOpFunc1
*gen_op_lswi
[] = {
2577 &gen_op_lswi_le_raw
,
2578 #if defined(TARGET_PPC64)
2579 &gen_op_lswi_64_raw
,
2580 &gen_op_lswi_le_64_raw
,
2583 static GenOpFunc3
*gen_op_lswx
[] = {
2585 &gen_op_lswx_le_raw
,
2586 #if defined(TARGET_PPC64)
2587 &gen_op_lswx_64_raw
,
2588 &gen_op_lswx_le_64_raw
,
2591 static GenOpFunc1
*gen_op_stsw
[] = {
2593 &gen_op_stsw_le_raw
,
2594 #if defined(TARGET_PPC64)
2595 &gen_op_stsw_64_raw
,
2596 &gen_op_stsw_le_64_raw
,
2600 #if defined(TARGET_PPC64)
2601 /* Full system - 64 bits mode */
2602 static GenOpFunc1
*gen_op_lswi
[] = {
2604 &gen_op_lswi_le_user
,
2605 &gen_op_lswi_64_user
,
2606 &gen_op_lswi_le_64_user
,
2607 &gen_op_lswi_kernel
,
2608 &gen_op_lswi_le_kernel
,
2609 &gen_op_lswi_64_kernel
,
2610 &gen_op_lswi_le_64_kernel
,
2611 #if defined(TARGET_PPC64H)
2613 &gen_op_lswi_le_hypv
,
2614 &gen_op_lswi_64_hypv
,
2615 &gen_op_lswi_le_64_hypv
,
2618 static GenOpFunc3
*gen_op_lswx
[] = {
2620 &gen_op_lswx_le_user
,
2621 &gen_op_lswx_64_user
,
2622 &gen_op_lswx_le_64_user
,
2623 &gen_op_lswx_kernel
,
2624 &gen_op_lswx_le_kernel
,
2625 &gen_op_lswx_64_kernel
,
2626 &gen_op_lswx_le_64_kernel
,
2627 #if defined(TARGET_PPC64H)
2629 &gen_op_lswx_le_hypv
,
2630 &gen_op_lswx_64_hypv
,
2631 &gen_op_lswx_le_64_hypv
,
2634 static GenOpFunc1
*gen_op_stsw
[] = {
2636 &gen_op_stsw_le_user
,
2637 &gen_op_stsw_64_user
,
2638 &gen_op_stsw_le_64_user
,
2639 &gen_op_stsw_kernel
,
2640 &gen_op_stsw_le_kernel
,
2641 &gen_op_stsw_64_kernel
,
2642 &gen_op_stsw_le_64_kernel
,
2643 #if defined(TARGET_PPC64H)
2645 &gen_op_stsw_le_hypv
,
2646 &gen_op_stsw_64_hypv
,
2647 &gen_op_stsw_le_64_hypv
,
2651 /* Full system - 32 bits mode */
2652 static GenOpFunc1
*gen_op_lswi
[] = {
2654 &gen_op_lswi_le_user
,
2655 &gen_op_lswi_kernel
,
2656 &gen_op_lswi_le_kernel
,
2658 static GenOpFunc3
*gen_op_lswx
[] = {
2660 &gen_op_lswx_le_user
,
2661 &gen_op_lswx_kernel
,
2662 &gen_op_lswx_le_kernel
,
2664 static GenOpFunc1
*gen_op_stsw
[] = {
2666 &gen_op_stsw_le_user
,
2667 &gen_op_stsw_kernel
,
2668 &gen_op_stsw_le_kernel
,
2674 /* PowerPC32 specification says we must generate an exception if
2675 * rA is in the range of registers to be loaded.
2676 * In an other hand, IBM says this is valid, but rA won't be loaded.
2677 * For now, I'll follow the spec...
2679 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER
)
2681 int nb
= NB(ctx
->opcode
);
2682 int start
= rD(ctx
->opcode
);
2683 int ra
= rA(ctx
->opcode
);
2689 if (unlikely(((start
+ nr
) > 32 &&
2690 start
<= ra
&& (start
+ nr
- 32) > ra
) ||
2691 ((start
+ nr
) <= 32 && start
<= ra
&& (start
+ nr
) > ra
))) {
2692 GEN_EXCP(ctx
, POWERPC_EXCP_PROGRAM
,
2693 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_LSWX
);
2696 /* NIP cannot be restored if the memory exception comes from an helper */
2697 gen_update_nip(ctx
, ctx
->nip
- 4);
2698 gen_addr_register(ctx
);
2700 op_ldsts(lswi
, start
);
2704 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER
)
2706 int ra
= rA(ctx
->opcode
);
2707 int rb
= rB(ctx
->opcode
);
2709 /* NIP cannot be restored if the memory exception comes from an helper */
2710 gen_update_nip(ctx
, ctx
->nip
- 4);
2711 gen_addr_reg_index(ctx
);
2715 gen_op_load_xer_bc();
2716 op_ldstsx(lswx
, rD(ctx
->opcode
), ra
, rb
);
2720 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER
)
2722 int nb
= NB(ctx
->opcode
);
2724 /* NIP cannot be restored if the memory exception comes from an helper */
2725 gen_update_nip(ctx
, ctx
->nip
- 4);
2726 gen_addr_register(ctx
);
2730 op_ldsts(stsw
, rS(ctx
->opcode
));
2734 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER
)
2736 /* NIP cannot be restored if the memory exception comes from an helper */
2737 gen_update_nip(ctx
, ctx
->nip
- 4);
2738 gen_addr_reg_index(ctx
);
2739 gen_op_load_xer_bc();
2740 op_ldsts(stsw
, rS(ctx
->opcode
));
2743 /*** Memory synchronisation ***/
2745 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO
)
2750 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
)
2755 #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2756 #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
2757 #if defined(CONFIG_USER_ONLY)
2758 /* User-mode only */
2759 static GenOpFunc
*gen_op_lwarx
[] = {
2761 &gen_op_lwarx_le_raw
,
2762 #if defined(TARGET_PPC64)
2763 &gen_op_lwarx_64_raw
,
2764 &gen_op_lwarx_le_64_raw
,
2767 static GenOpFunc
*gen_op_stwcx
[] = {
2769 &gen_op_stwcx_le_raw
,
2770 #if defined(TARGET_PPC64)
2771 &gen_op_stwcx_64_raw
,
2772 &gen_op_stwcx_le_64_raw
,
2776 #if defined(TARGET_PPC64)
2777 /* Full system - 64 bits mode */
2778 static GenOpFunc
*gen_op_lwarx
[] = {
2780 &gen_op_lwarx_le_user
,
2781 &gen_op_lwarx_64_user
,
2782 &gen_op_lwarx_le_64_user
,
2783 &gen_op_lwarx_kernel
,
2784 &gen_op_lwarx_le_kernel
,
2785 &gen_op_lwarx_64_kernel
,
2786 &gen_op_lwarx_le_64_kernel
,
2787 #if defined(TARGET_PPC64H)
2789 &gen_op_lwarx_le_hypv
,
2790 &gen_op_lwarx_64_hypv
,
2791 &gen_op_lwarx_le_64_hypv
,
2794 static GenOpFunc
*gen_op_stwcx
[] = {
2796 &gen_op_stwcx_le_user
,
2797 &gen_op_stwcx_64_user
,
2798 &gen_op_stwcx_le_64_user
,
2799 &gen_op_stwcx_kernel
,
2800 &gen_op_stwcx_le_kernel
,
2801 &gen_op_stwcx_64_kernel
,
2802 &gen_op_stwcx_le_64_kernel
,
2803 #if defined(TARGET_PPC64H)
2805 &gen_op_stwcx_le_hypv
,
2806 &gen_op_stwcx_64_hypv
,
2807 &gen_op_stwcx_le_64_hypv
,
2811 /* Full system - 32 bits mode */
2812 static GenOpFunc
*gen_op_lwarx
[] = {
2814 &gen_op_lwarx_le_user
,
2815 &gen_op_lwarx_kernel
,
2816 &gen_op_lwarx_le_kernel
,
2818 static GenOpFunc
*gen_op_stwcx
[] = {
2820 &gen_op_stwcx_le_user
,
2821 &gen_op_stwcx_kernel
,
2822 &gen_op_stwcx_le_kernel
,
2828 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES
)
2830 /* NIP cannot be restored if the memory exception comes from an helper */
2831 gen_update_nip(ctx
, ctx
->nip
- 4);
2832 gen_addr_reg_index(ctx
);
2834 gen_op_store_T1_gpr(rD(ctx
->opcode
));
2838 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
)
2840 /* NIP cannot be restored if the memory exception comes from an helper */
2841 gen_update_nip(ctx
, ctx
->nip
- 4);
2842 gen_addr_reg_index(ctx
);
2843 gen_op_load_gpr_T1(rS(ctx
->opcode
));
2847 #if defined(TARGET_PPC64)
2848 #define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2849 #define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
2850 #if defined(CONFIG_USER_ONLY)
2851 /* User-mode only */
2852 static GenOpFunc
*gen_op_ldarx
[] = {
2854 &gen_op_ldarx_le_raw
,
2855 &gen_op_ldarx_64_raw
,
2856 &gen_op_ldarx_le_64_raw
,
2858 static GenOpFunc
*gen_op_stdcx
[] = {
2860 &gen_op_stdcx_le_raw
,
2861 &gen_op_stdcx_64_raw
,
2862 &gen_op_stdcx_le_64_raw
,
2866 static GenOpFunc
*gen_op_ldarx
[] = {
2868 &gen_op_ldarx_le_user
,
2869 &gen_op_ldarx_64_user
,
2870 &gen_op_ldarx_le_64_user
,
2871 &gen_op_ldarx_kernel
,
2872 &gen_op_ldarx_le_kernel
,
2873 &gen_op_ldarx_64_kernel
,
2874 &gen_op_ldarx_le_64_kernel
,
2875 #if defined(TARGET_PPC64H)
2877 &gen_op_ldarx_le_hypv
,
2878 &gen_op_ldarx_64_hypv
,
2879 &gen_op_ldarx_le_64_hypv
,
2882 static GenOpFunc
*gen_op_stdcx
[] = {
2884 &gen_op_stdcx_le_user
,
2885 &gen_op_stdcx_64_user
,
2886 &gen_op_stdcx_le_64_user
,
2887 &gen_op_stdcx_kernel
,
2888 &gen_op_stdcx_le_kernel
,
2889 &gen_op_stdcx_64_kernel
,
2890 &gen_op_stdcx_le_64_kernel
,
2891 #if defined(TARGET_PPC64H)
2893 &gen_op_stdcx_le_hypv
,
2894 &gen_op_stdcx_64_hypv
,
2895 &gen_op_stdcx_le_64_hypv
,
2901 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B
)
2903 /* NIP cannot be restored if the memory exception comes from an helper */
2904 gen_update_nip(ctx
, ctx
->nip
- 4);
2905 gen_addr_reg_index(ctx
);
2907 gen_op_store_T1_gpr(rD(ctx
->opcode
));
2911 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
)
2913 /* NIP cannot be restored if the memory exception comes from an helper */
2914 gen_update_nip(ctx
, ctx
->nip
- 4);
2915 gen_addr_reg_index(ctx
);
2916 gen_op_load_gpr_T1(rS(ctx
->opcode
));
2919 #endif /* defined(TARGET_PPC64) */
2922 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
)
2927 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
)
2929 /* Stop translation, as the CPU is supposed to sleep from now */
2931 GEN_EXCP(ctx
, EXCP_HLT
, 1);
2934 /*** Floating-point load ***/
2935 #define GEN_LDF(width, opc, type) \
2936 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2938 if (unlikely(!ctx->fpu_enabled)) { \
2939 GEN_EXCP_NO_FP(ctx); \
2942 gen_addr_imm_index(ctx, 0); \
2943 op_ldst(l##width); \
2944 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2947 #define GEN_LDUF(width, opc, type) \
2948 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2950 if (unlikely(!ctx->fpu_enabled)) { \
2951 GEN_EXCP_NO_FP(ctx); \
2954 if (unlikely(rA(ctx->opcode) == 0)) { \
2955 GEN_EXCP_INVAL(ctx); \
2958 gen_addr_imm_index(ctx, 0); \
2959 op_ldst(l##width); \
2960 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2961 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2964 #define GEN_LDUXF(width, opc, type) \
2965 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
2967 if (unlikely(!ctx->fpu_enabled)) { \
2968 GEN_EXCP_NO_FP(ctx); \
2971 if (unlikely(rA(ctx->opcode) == 0)) { \
2972 GEN_EXCP_INVAL(ctx); \
2975 gen_addr_reg_index(ctx); \
2976 op_ldst(l##width); \
2977 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2978 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2981 #define GEN_LDXF(width, opc2, opc3, type) \
2982 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2984 if (unlikely(!ctx->fpu_enabled)) { \
2985 GEN_EXCP_NO_FP(ctx); \
2988 gen_addr_reg_index(ctx); \
2989 op_ldst(l##width); \
2990 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2993 #define GEN_LDFS(width, op, type) \
2994 OP_LD_TABLE(width); \
2995 GEN_LDF(width, op | 0x20, type); \
2996 GEN_LDUF(width, op | 0x21, type); \
2997 GEN_LDUXF(width, op | 0x01, type); \
2998 GEN_LDXF(width, 0x17, op | 0x00, type)
3000 /* lfd lfdu lfdux lfdx */
3001 GEN_LDFS(fd
, 0x12, PPC_FLOAT
);
3002 /* lfs lfsu lfsux lfsx */
3003 GEN_LDFS(fs
, 0x10, PPC_FLOAT
);
3005 /*** Floating-point store ***/
3006 #define GEN_STF(width, opc, type) \
3007 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
3009 if (unlikely(!ctx->fpu_enabled)) { \
3010 GEN_EXCP_NO_FP(ctx); \
3013 gen_addr_imm_index(ctx, 0); \
3014 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
3015 op_ldst(st##width); \
3018 #define GEN_STUF(width, opc, type) \
3019 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3021 if (unlikely(!ctx->fpu_enabled)) { \
3022 GEN_EXCP_NO_FP(ctx); \
3025 if (unlikely(rA(ctx->opcode) == 0)) { \
3026 GEN_EXCP_INVAL(ctx); \
3029 gen_addr_imm_index(ctx, 0); \
3030 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
3031 op_ldst(st##width); \
3032 gen_op_store_T0_gpr(rA(ctx->opcode)); \
3035 #define GEN_STUXF(width, opc, type) \
3036 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3038 if (unlikely(!ctx->fpu_enabled)) { \
3039 GEN_EXCP_NO_FP(ctx); \
3042 if (unlikely(rA(ctx->opcode) == 0)) { \
3043 GEN_EXCP_INVAL(ctx); \
3046 gen_addr_reg_index(ctx); \
3047 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
3048 op_ldst(st##width); \
3049 gen_op_store_T0_gpr(rA(ctx->opcode)); \
3052 #define GEN_STXF(width, opc2, opc3, type) \
3053 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
3055 if (unlikely(!ctx->fpu_enabled)) { \
3056 GEN_EXCP_NO_FP(ctx); \
3059 gen_addr_reg_index(ctx); \
3060 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
3061 op_ldst(st##width); \
3064 #define GEN_STFS(width, op, type) \
3065 OP_ST_TABLE(width); \
3066 GEN_STF(width, op | 0x20, type); \
3067 GEN_STUF(width, op | 0x21, type); \
3068 GEN_STUXF(width, op | 0x01, type); \
3069 GEN_STXF(width, 0x17, op | 0x00, type)
3071 /* stfd stfdu stfdux stfdx */
3072 GEN_STFS(fd
, 0x16, PPC_FLOAT
);
3073 /* stfs stfsu stfsux stfsx */
3074 GEN_STFS(fs
, 0x14, PPC_FLOAT
);
3079 GEN_STXF(fiwx
, 0x17, 0x1E, PPC_FLOAT_STFIWX
);
3082 static always_inline
void gen_goto_tb (DisasContext
*ctx
, int n
,
3085 TranslationBlock
*tb
;
3087 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
3089 gen_op_goto_tb0(TBPARAM(tb
));
3091 gen_op_goto_tb1(TBPARAM(tb
));
3093 #if defined(TARGET_PPC64)
3099 gen_op_set_T0((long)tb
+ n
);
3100 if (ctx
->singlestep_enabled
)
3105 #if defined(TARGET_PPC64)
3112 if (ctx
->singlestep_enabled
)
3118 static always_inline
void gen_setlr (DisasContext
*ctx
, target_ulong nip
)
3120 #if defined(TARGET_PPC64)
3121 if (ctx
->sf_mode
!= 0 && (nip
>> 32))
3122 gen_op_setlr_64(ctx
->nip
>> 32, ctx
->nip
);
3125 gen_op_setlr(ctx
->nip
);
3129 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
)
3131 target_ulong li
, target
;
3133 /* sign extend LI */
3134 #if defined(TARGET_PPC64)
3136 li
= ((int64_t)LI(ctx
->opcode
) << 38) >> 38;
3139 li
= ((int32_t)LI(ctx
->opcode
) << 6) >> 6;
3140 if (likely(AA(ctx
->opcode
) == 0))
3141 target
= ctx
->nip
+ li
- 4;
3144 #if defined(TARGET_PPC64)
3146 target
= (uint32_t)target
;
3148 if (LK(ctx
->opcode
))
3149 gen_setlr(ctx
, ctx
->nip
);
3150 gen_goto_tb(ctx
, 0, target
);
3151 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3158 static always_inline
void gen_bcond (DisasContext
*ctx
, int type
)
3160 target_ulong target
= 0;
3162 uint32_t bo
= BO(ctx
->opcode
);
3163 uint32_t bi
= BI(ctx
->opcode
);
3166 if ((bo
& 0x4) == 0)
3170 li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
3171 if (likely(AA(ctx
->opcode
) == 0)) {
3172 target
= ctx
->nip
+ li
- 4;
3176 #if defined(TARGET_PPC64)
3178 target
= (uint32_t)target
;
3182 gen_op_movl_T1_ctr();
3186 gen_op_movl_T1_lr();
3189 if (LK(ctx
->opcode
))
3190 gen_setlr(ctx
, ctx
->nip
);
3192 /* No CR condition */
3195 #if defined(TARGET_PPC64)
3197 gen_op_test_ctr_64();
3203 #if defined(TARGET_PPC64)
3205 gen_op_test_ctrz_64();
3213 if (type
== BCOND_IM
) {
3214 gen_goto_tb(ctx
, 0, target
);
3217 #if defined(TARGET_PPC64)
3229 mask
= 1 << (3 - (bi
& 0x03));
3230 gen_op_load_crf_T0(bi
>> 2);
3234 #if defined(TARGET_PPC64)
3236 gen_op_test_ctr_true_64(mask
);
3239 gen_op_test_ctr_true(mask
);
3242 #if defined(TARGET_PPC64)
3244 gen_op_test_ctrz_true_64(mask
);
3247 gen_op_test_ctrz_true(mask
);
3252 gen_op_test_true(mask
);
3258 #if defined(TARGET_PPC64)
3260 gen_op_test_ctr_false_64(mask
);
3263 gen_op_test_ctr_false(mask
);
3266 #if defined(TARGET_PPC64)
3268 gen_op_test_ctrz_false_64(mask
);
3271 gen_op_test_ctrz_false(mask
);
3276 gen_op_test_false(mask
);
3281 if (type
== BCOND_IM
) {
3282 int l1
= gen_new_label();
3284 gen_goto_tb(ctx
, 0, target
);
3286 gen_goto_tb(ctx
, 1, ctx
->nip
);
3288 #if defined(TARGET_PPC64)
3290 gen_op_btest_T1_64(ctx
->nip
>> 32, ctx
->nip
);
3293 gen_op_btest_T1(ctx
->nip
);
3296 if (ctx
->singlestep_enabled
)
3301 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3304 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
)
3306 gen_bcond(ctx
, BCOND_IM
);
3309 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
)
3311 gen_bcond(ctx
, BCOND_CTR
);
3314 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
)
3316 gen_bcond(ctx
, BCOND_LR
);
3319 /*** Condition register logical ***/
3320 #define GEN_CRLOGIC(op, opc) \
3321 GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3325 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
3326 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3328 gen_op_srli_T0(sh); \
3330 gen_op_sli_T0(-sh); \
3331 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
3332 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3334 gen_op_srli_T1(sh); \
3336 gen_op_sli_T1(-sh); \
3338 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3339 gen_op_andi_T0(bitmask); \
3340 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
3341 gen_op_andi_T1(~bitmask); \
3343 gen_op_store_T0_crf(crbD(ctx->opcode) >> 2); \
3347 GEN_CRLOGIC(and, 0x08);
3349 GEN_CRLOGIC(andc
, 0x04);
3351 GEN_CRLOGIC(eqv
, 0x09);
3353 GEN_CRLOGIC(nand
, 0x07);
3355 GEN_CRLOGIC(nor
, 0x01);
3357 GEN_CRLOGIC(or, 0x0E);
3359 GEN_CRLOGIC(orc
, 0x0D);
3361 GEN_CRLOGIC(xor, 0x06);
3363 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
)
3365 gen_op_load_crf_T0(crfS(ctx
->opcode
));
3366 gen_op_store_T0_crf(crfD(ctx
->opcode
));
3369 /*** System linkage ***/
3370 /* rfi (supervisor only) */
3371 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
)
3373 #if defined(CONFIG_USER_ONLY)
3374 GEN_EXCP_PRIVOPC(ctx
);
3376 /* Restore CPU state */
3377 if (unlikely(!ctx
->supervisor
)) {
3378 GEN_EXCP_PRIVOPC(ctx
);
3386 #if defined(TARGET_PPC64)
3387 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
)
3389 #if defined(CONFIG_USER_ONLY)
3390 GEN_EXCP_PRIVOPC(ctx
);
3392 /* Restore CPU state */
3393 if (unlikely(!ctx
->supervisor
)) {
3394 GEN_EXCP_PRIVOPC(ctx
);
3403 #if defined(TARGET_PPC64H)
3404 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64B
)
3406 #if defined(CONFIG_USER_ONLY)
3407 GEN_EXCP_PRIVOPC(ctx
);
3409 /* Restore CPU state */
3410 if (unlikely(ctx
->supervisor
<= 1)) {
3411 GEN_EXCP_PRIVOPC(ctx
);
3421 #if defined(CONFIG_USER_ONLY)
3422 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3424 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3426 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
)
3430 lev
= (ctx
->opcode
>> 5) & 0x7F;
3431 GEN_EXCP(ctx
, POWERPC_SYSCALL
, lev
);
3436 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
)
3438 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3439 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3440 /* Update the nip since this might generate a trap exception */
3441 gen_update_nip(ctx
, ctx
->nip
);
3442 gen_op_tw(TO(ctx
->opcode
));
3446 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
)
3448 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3449 gen_set_T1(SIMM(ctx
->opcode
));
3450 /* Update the nip since this might generate a trap exception */
3451 gen_update_nip(ctx
, ctx
->nip
);
3452 gen_op_tw(TO(ctx
->opcode
));
3455 #if defined(TARGET_PPC64)
3457 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
)
3459 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3460 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3461 /* Update the nip since this might generate a trap exception */
3462 gen_update_nip(ctx
, ctx
->nip
);
3463 gen_op_td(TO(ctx
->opcode
));
3467 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
)
3469 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3470 gen_set_T1(SIMM(ctx
->opcode
));
3471 /* Update the nip since this might generate a trap exception */
3472 gen_update_nip(ctx
, ctx
->nip
);
3473 gen_op_td(TO(ctx
->opcode
));
3477 /*** Processor control ***/
3479 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
)
3481 gen_op_load_xer_cr();
3482 gen_op_store_T0_crf(crfD(ctx
->opcode
));
3483 gen_op_clear_xer_ov();
3484 gen_op_clear_xer_ca();
3488 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
)
3492 if (likely(ctx
->opcode
& 0x00100000)) {
3493 crm
= CRM(ctx
->opcode
);
3494 if (likely((crm
^ (crm
- 1)) == 0)) {
3496 gen_op_load_cro(7 - crn
);
3501 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3505 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
)
3507 #if defined(CONFIG_USER_ONLY)
3508 GEN_EXCP_PRIVREG(ctx
);
3510 if (unlikely(!ctx
->supervisor
)) {
3511 GEN_EXCP_PRIVREG(ctx
);
3515 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3520 #define SPR_NOACCESS ((void *)(-1))
3522 static void spr_noaccess (void *opaque
, int sprn
)
3524 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
3525 printf("ERROR: try to access SPR %d !\n", sprn
);
3527 #define SPR_NOACCESS (&spr_noaccess)
3531 static always_inline
void gen_op_mfspr (DisasContext
*ctx
)
3533 void (*read_cb
)(void *opaque
, int sprn
);
3534 uint32_t sprn
= SPR(ctx
->opcode
);
3536 #if !defined(CONFIG_USER_ONLY)
3537 #if defined(TARGET_PPC64H)
3538 if (ctx
->supervisor
== 2)
3539 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
3542 if (ctx
->supervisor
)
3543 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
3546 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
3547 if (likely(read_cb
!= NULL
)) {
3548 if (likely(read_cb
!= SPR_NOACCESS
)) {
3549 (*read_cb
)(ctx
, sprn
);
3550 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3552 /* Privilege exception */
3553 /* This is a hack to avoid warnings when running Linux:
3554 * this OS breaks the PowerPC virtualisation model,
3555 * allowing userland application to read the PVR
3557 if (sprn
!= SPR_PVR
) {
3558 if (loglevel
!= 0) {
3559 fprintf(logfile
, "Trying to read privileged spr %d %03x at"
3560 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
3562 printf("Trying to read privileged spr %d %03x at " ADDRX
"\n",
3563 sprn
, sprn
, ctx
->nip
);
3565 GEN_EXCP_PRIVREG(ctx
);
3569 if (loglevel
!= 0) {
3570 fprintf(logfile
, "Trying to read invalid spr %d %03x at "
3571 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
3573 printf("Trying to read invalid spr %d %03x at " ADDRX
"\n",
3574 sprn
, sprn
, ctx
->nip
);
3575 GEN_EXCP(ctx
, POWERPC_EXCP_PROGRAM
,
3576 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_SPR
);
3580 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
)
3586 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
)
3592 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
)
3596 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3597 crm
= CRM(ctx
->opcode
);
3598 if (likely((ctx
->opcode
& 0x00100000) || (crm
^ (crm
- 1)) == 0)) {
3600 gen_op_srli_T0(crn
* 4);
3601 gen_op_andi_T0(0xF);
3602 gen_op_store_cro(7 - crn
);
3604 gen_op_store_cr(crm
);
3609 #if defined(TARGET_PPC64)
3610 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
)
3612 #if defined(CONFIG_USER_ONLY)
3613 GEN_EXCP_PRIVREG(ctx
);
3615 if (unlikely(!ctx
->supervisor
)) {
3616 GEN_EXCP_PRIVREG(ctx
);
3619 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3620 if (ctx
->opcode
& 0x00010000) {
3621 /* Special form that does not need any synchronisation */
3622 gen_op_update_riee();
3624 /* XXX: we need to update nip before the store
3625 * if we enter power saving mode, we will exit the loop
3626 * directly from ppc_store_msr
3628 gen_update_nip(ctx
, ctx
->nip
);
3630 /* Must stop the translation as machine state (may have) changed */
3631 /* Note that mtmsr is not always defined as context-synchronizing */
3632 ctx
->exception
= POWERPC_EXCP_STOP
;
3638 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC
)
3640 #if defined(CONFIG_USER_ONLY)
3641 GEN_EXCP_PRIVREG(ctx
);
3643 if (unlikely(!ctx
->supervisor
)) {
3644 GEN_EXCP_PRIVREG(ctx
);
3647 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3648 if (ctx
->opcode
& 0x00010000) {
3649 /* Special form that does not need any synchronisation */
3650 gen_op_update_riee();
3652 /* XXX: we need to update nip before the store
3653 * if we enter power saving mode, we will exit the loop
3654 * directly from ppc_store_msr
3656 gen_update_nip(ctx
, ctx
->nip
);
3657 #if defined(TARGET_PPC64)
3659 gen_op_store_msr_32();
3663 /* Must stop the translation as machine state (may have) changed */
3664 /* Note that mtmsrd is not always defined as context-synchronizing */
3665 ctx
->exception
= POWERPC_EXCP_STOP
;
3671 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC
)
3673 void (*write_cb
)(void *opaque
, int sprn
);
3674 uint32_t sprn
= SPR(ctx
->opcode
);
3676 #if !defined(CONFIG_USER_ONLY)
3677 #if defined(TARGET_PPC64H)
3678 if (ctx
->supervisor
== 2)
3679 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
3682 if (ctx
->supervisor
)
3683 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
3686 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
3687 if (likely(write_cb
!= NULL
)) {
3688 if (likely(write_cb
!= SPR_NOACCESS
)) {
3689 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3690 (*write_cb
)(ctx
, sprn
);
3692 /* Privilege exception */
3693 if (loglevel
!= 0) {
3694 fprintf(logfile
, "Trying to write privileged spr %d %03x at "
3695 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
3697 printf("Trying to write privileged spr %d %03x at " ADDRX
"\n",
3698 sprn
, sprn
, ctx
->nip
);
3699 GEN_EXCP_PRIVREG(ctx
);
3703 if (loglevel
!= 0) {
3704 fprintf(logfile
, "Trying to write invalid spr %d %03x at "
3705 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
3707 printf("Trying to write invalid spr %d %03x at " ADDRX
"\n",
3708 sprn
, sprn
, ctx
->nip
);
3709 GEN_EXCP(ctx
, POWERPC_EXCP_PROGRAM
,
3710 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_SPR
);
3714 /*** Cache management ***/
3716 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
)
3718 /* XXX: specification says this is treated as a load by the MMU */
3719 gen_addr_reg_index(ctx
);
3723 /* dcbi (Supervisor only) */
3724 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
)
3726 #if defined(CONFIG_USER_ONLY)
3727 GEN_EXCP_PRIVOPC(ctx
);
3729 if (unlikely(!ctx
->supervisor
)) {
3730 GEN_EXCP_PRIVOPC(ctx
);
3733 gen_addr_reg_index(ctx
);
3734 /* XXX: specification says this should be treated as a store by the MMU */
3741 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
)
3743 /* XXX: specification say this is treated as a load by the MMU */
3744 gen_addr_reg_index(ctx
);
3749 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE
)
3751 /* interpreted as no-op */
3752 /* XXX: specification say this is treated as a load by the MMU
3753 * but does not generate any exception
3758 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE
)
3760 /* interpreted as no-op */
3761 /* XXX: specification say this is treated as a load by the MMU
3762 * but does not generate any exception
3767 #define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
3768 #if defined(CONFIG_USER_ONLY)
3769 /* User-mode only */
3770 static GenOpFunc
*gen_op_dcbz
[4][4] = {
3772 &gen_op_dcbz_l32_raw
,
3773 &gen_op_dcbz_l32_raw
,
3774 #if defined(TARGET_PPC64)
3775 &gen_op_dcbz_l32_64_raw
,
3776 &gen_op_dcbz_l32_64_raw
,
3780 &gen_op_dcbz_l64_raw
,
3781 &gen_op_dcbz_l64_raw
,
3782 #if defined(TARGET_PPC64)
3783 &gen_op_dcbz_l64_64_raw
,
3784 &gen_op_dcbz_l64_64_raw
,
3788 &gen_op_dcbz_l128_raw
,
3789 &gen_op_dcbz_l128_raw
,
3790 #if defined(TARGET_PPC64)
3791 &gen_op_dcbz_l128_64_raw
,
3792 &gen_op_dcbz_l128_64_raw
,
3798 #if defined(TARGET_PPC64)
3799 &gen_op_dcbz_64_raw
,
3800 &gen_op_dcbz_64_raw
,
3805 #if defined(TARGET_PPC64)
3806 /* Full system - 64 bits mode */
3807 static GenOpFunc
*gen_op_dcbz
[4][12] = {
3809 &gen_op_dcbz_l32_user
,
3810 &gen_op_dcbz_l32_user
,
3811 &gen_op_dcbz_l32_64_user
,
3812 &gen_op_dcbz_l32_64_user
,
3813 &gen_op_dcbz_l32_kernel
,
3814 &gen_op_dcbz_l32_kernel
,
3815 &gen_op_dcbz_l32_64_kernel
,
3816 &gen_op_dcbz_l32_64_kernel
,
3817 #if defined(TARGET_PPC64H)
3818 &gen_op_dcbz_l32_hypv
,
3819 &gen_op_dcbz_l32_hypv
,
3820 &gen_op_dcbz_l32_64_hypv
,
3821 &gen_op_dcbz_l32_64_hypv
,
3825 &gen_op_dcbz_l64_user
,
3826 &gen_op_dcbz_l64_user
,
3827 &gen_op_dcbz_l64_64_user
,
3828 &gen_op_dcbz_l64_64_user
,
3829 &gen_op_dcbz_l64_kernel
,
3830 &gen_op_dcbz_l64_kernel
,
3831 &gen_op_dcbz_l64_64_kernel
,
3832 &gen_op_dcbz_l64_64_kernel
,
3833 #if defined(TARGET_PPC64H)
3834 &gen_op_dcbz_l64_hypv
,
3835 &gen_op_dcbz_l64_hypv
,
3836 &gen_op_dcbz_l64_64_hypv
,
3837 &gen_op_dcbz_l64_64_hypv
,
3841 &gen_op_dcbz_l128_user
,
3842 &gen_op_dcbz_l128_user
,
3843 &gen_op_dcbz_l128_64_user
,
3844 &gen_op_dcbz_l128_64_user
,
3845 &gen_op_dcbz_l128_kernel
,
3846 &gen_op_dcbz_l128_kernel
,
3847 &gen_op_dcbz_l128_64_kernel
,
3848 &gen_op_dcbz_l128_64_kernel
,
3849 #if defined(TARGET_PPC64H)
3850 &gen_op_dcbz_l128_hypv
,
3851 &gen_op_dcbz_l128_hypv
,
3852 &gen_op_dcbz_l128_64_hypv
,
3853 &gen_op_dcbz_l128_64_hypv
,
3859 &gen_op_dcbz_64_user
,
3860 &gen_op_dcbz_64_user
,
3861 &gen_op_dcbz_kernel
,
3862 &gen_op_dcbz_kernel
,
3863 &gen_op_dcbz_64_kernel
,
3864 &gen_op_dcbz_64_kernel
,
3865 #if defined(TARGET_PPC64H)
3868 &gen_op_dcbz_64_hypv
,
3869 &gen_op_dcbz_64_hypv
,
3874 /* Full system - 32 bits mode */
3875 static GenOpFunc
*gen_op_dcbz
[4][4] = {
3877 &gen_op_dcbz_l32_user
,
3878 &gen_op_dcbz_l32_user
,
3879 &gen_op_dcbz_l32_kernel
,
3880 &gen_op_dcbz_l32_kernel
,
3883 &gen_op_dcbz_l64_user
,
3884 &gen_op_dcbz_l64_user
,
3885 &gen_op_dcbz_l64_kernel
,
3886 &gen_op_dcbz_l64_kernel
,
3889 &gen_op_dcbz_l128_user
,
3890 &gen_op_dcbz_l128_user
,
3891 &gen_op_dcbz_l128_kernel
,
3892 &gen_op_dcbz_l128_kernel
,
3897 &gen_op_dcbz_kernel
,
3898 &gen_op_dcbz_kernel
,
3904 static always_inline
void handler_dcbz (DisasContext
*ctx
,
3905 int dcache_line_size
)
3909 switch (dcache_line_size
) {
3926 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ
)
3928 gen_addr_reg_index(ctx
);
3929 handler_dcbz(ctx
, ctx
->dcache_line_size
);
3930 gen_op_check_reservation();
3933 GEN_HANDLER2(dcbz_970
, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT
)
3935 gen_addr_reg_index(ctx
);
3936 if (ctx
->opcode
& 0x00200000)
3937 handler_dcbz(ctx
, ctx
->dcache_line_size
);
3939 handler_dcbz(ctx
, -1);
3940 gen_op_check_reservation();
3944 #define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
3945 #if defined(CONFIG_USER_ONLY)
3946 /* User-mode only */
3947 static GenOpFunc
*gen_op_icbi
[] = {
3950 #if defined(TARGET_PPC64)
3951 &gen_op_icbi_64_raw
,
3952 &gen_op_icbi_64_raw
,
3956 /* Full system - 64 bits mode */
3957 #if defined(TARGET_PPC64)
3958 static GenOpFunc
*gen_op_icbi
[] = {
3961 &gen_op_icbi_64_user
,
3962 &gen_op_icbi_64_user
,
3963 &gen_op_icbi_kernel
,
3964 &gen_op_icbi_kernel
,
3965 &gen_op_icbi_64_kernel
,
3966 &gen_op_icbi_64_kernel
,
3967 #if defined(TARGET_PPC64H)
3970 &gen_op_icbi_64_hypv
,
3971 &gen_op_icbi_64_hypv
,
3975 /* Full system - 32 bits mode */
3976 static GenOpFunc
*gen_op_icbi
[] = {
3979 &gen_op_icbi_kernel
,
3980 &gen_op_icbi_kernel
,
3985 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE
)
3987 /* NIP cannot be restored if the memory exception comes from an helper */
3988 gen_update_nip(ctx
, ctx
->nip
- 4);
3989 gen_addr_reg_index(ctx
);
3995 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
)
3997 /* interpreted as no-op */
3998 /* XXX: specification say this is treated as a store by the MMU
3999 * but does not generate any exception
4003 /*** Segment register manipulation ***/
4004 /* Supervisor only: */
4006 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
)
4008 #if defined(CONFIG_USER_ONLY)
4009 GEN_EXCP_PRIVREG(ctx
);
4011 if (unlikely(!ctx
->supervisor
)) {
4012 GEN_EXCP_PRIVREG(ctx
);
4015 gen_op_set_T1(SR(ctx
->opcode
));
4017 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4022 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
)
4024 #if defined(CONFIG_USER_ONLY)
4025 GEN_EXCP_PRIVREG(ctx
);
4027 if (unlikely(!ctx
->supervisor
)) {
4028 GEN_EXCP_PRIVREG(ctx
);
4031 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4034 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4039 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
)
4041 #if defined(CONFIG_USER_ONLY)
4042 GEN_EXCP_PRIVREG(ctx
);
4044 if (unlikely(!ctx
->supervisor
)) {
4045 GEN_EXCP_PRIVREG(ctx
);
4048 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4049 gen_op_set_T1(SR(ctx
->opcode
));
4055 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
)
4057 #if defined(CONFIG_USER_ONLY)
4058 GEN_EXCP_PRIVREG(ctx
);
4060 if (unlikely(!ctx
->supervisor
)) {
4061 GEN_EXCP_PRIVREG(ctx
);
4064 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4065 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4071 #if defined(TARGET_PPC64)
4072 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4074 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
)
4076 #if defined(CONFIG_USER_ONLY)
4077 GEN_EXCP_PRIVREG(ctx
);
4079 if (unlikely(!ctx
->supervisor
)) {
4080 GEN_EXCP_PRIVREG(ctx
);
4083 gen_op_set_T1(SR(ctx
->opcode
));
4085 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4090 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4093 #if defined(CONFIG_USER_ONLY)
4094 GEN_EXCP_PRIVREG(ctx
);
4096 if (unlikely(!ctx
->supervisor
)) {
4097 GEN_EXCP_PRIVREG(ctx
);
4100 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4103 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4108 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
)
4110 #if defined(CONFIG_USER_ONLY)
4111 GEN_EXCP_PRIVREG(ctx
);
4113 if (unlikely(!ctx
->supervisor
)) {
4114 GEN_EXCP_PRIVREG(ctx
);
4117 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4118 gen_op_set_T1(SR(ctx
->opcode
));
4124 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4127 #if defined(CONFIG_USER_ONLY)
4128 GEN_EXCP_PRIVREG(ctx
);
4130 if (unlikely(!ctx
->supervisor
)) {
4131 GEN_EXCP_PRIVREG(ctx
);
4134 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4135 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4140 #endif /* defined(TARGET_PPC64) */
4142 /*** Lookaside buffer management ***/
4143 /* Optional & supervisor only: */
4145 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
)
4147 #if defined(CONFIG_USER_ONLY)
4148 GEN_EXCP_PRIVOPC(ctx
);
4150 if (unlikely(!ctx
->supervisor
)) {
4152 fprintf(logfile
, "%s: ! supervisor\n", __func__
);
4153 GEN_EXCP_PRIVOPC(ctx
);
4161 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE
)
4163 #if defined(CONFIG_USER_ONLY)
4164 GEN_EXCP_PRIVOPC(ctx
);
4166 if (unlikely(!ctx
->supervisor
)) {
4167 GEN_EXCP_PRIVOPC(ctx
);
4170 gen_op_load_gpr_T0(rB(ctx
->opcode
));
4171 #if defined(TARGET_PPC64)
4181 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
)
4183 #if defined(CONFIG_USER_ONLY)
4184 GEN_EXCP_PRIVOPC(ctx
);
4186 if (unlikely(!ctx
->supervisor
)) {
4187 GEN_EXCP_PRIVOPC(ctx
);
4190 /* This has no effect: it should ensure that all previous
4191 * tlbie have completed
4197 #if defined(TARGET_PPC64)
4199 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI
)
4201 #if defined(CONFIG_USER_ONLY)
4202 GEN_EXCP_PRIVOPC(ctx
);
4204 if (unlikely(!ctx
->supervisor
)) {
4206 fprintf(logfile
, "%s: ! supervisor\n", __func__
);
4207 GEN_EXCP_PRIVOPC(ctx
);
4215 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
)
4217 #if defined(CONFIG_USER_ONLY)
4218 GEN_EXCP_PRIVOPC(ctx
);
4220 if (unlikely(!ctx
->supervisor
)) {
4221 GEN_EXCP_PRIVOPC(ctx
);
4224 gen_op_load_gpr_T0(rB(ctx
->opcode
));
4230 /*** External control ***/
4232 #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4233 #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
4234 #if defined(CONFIG_USER_ONLY)
4235 /* User-mode only */
4236 static GenOpFunc
*gen_op_eciwx
[] = {
4238 &gen_op_eciwx_le_raw
,
4239 #if defined(TARGET_PPC64)
4240 &gen_op_eciwx_64_raw
,
4241 &gen_op_eciwx_le_64_raw
,
4244 static GenOpFunc
*gen_op_ecowx
[] = {
4246 &gen_op_ecowx_le_raw
,
4247 #if defined(TARGET_PPC64)
4248 &gen_op_ecowx_64_raw
,
4249 &gen_op_ecowx_le_64_raw
,
4253 #if defined(TARGET_PPC64)
4254 /* Full system - 64 bits mode */
4255 static GenOpFunc
*gen_op_eciwx
[] = {
4257 &gen_op_eciwx_le_user
,
4258 &gen_op_eciwx_64_user
,
4259 &gen_op_eciwx_le_64_user
,
4260 &gen_op_eciwx_kernel
,
4261 &gen_op_eciwx_le_kernel
,
4262 &gen_op_eciwx_64_kernel
,
4263 &gen_op_eciwx_le_64_kernel
,
4264 #if defined(TARGET_PPC64H)
4266 &gen_op_eciwx_le_hypv
,
4267 &gen_op_eciwx_64_hypv
,
4268 &gen_op_eciwx_le_64_hypv
,
4271 static GenOpFunc
*gen_op_ecowx
[] = {
4273 &gen_op_ecowx_le_user
,
4274 &gen_op_ecowx_64_user
,
4275 &gen_op_ecowx_le_64_user
,
4276 &gen_op_ecowx_kernel
,
4277 &gen_op_ecowx_le_kernel
,
4278 &gen_op_ecowx_64_kernel
,
4279 &gen_op_ecowx_le_64_kernel
,
4280 #if defined(TARGET_PPC64H)
4282 &gen_op_ecowx_le_hypv
,
4283 &gen_op_ecowx_64_hypv
,
4284 &gen_op_ecowx_le_64_hypv
,
4288 /* Full system - 32 bits mode */
4289 static GenOpFunc
*gen_op_eciwx
[] = {
4291 &gen_op_eciwx_le_user
,
4292 &gen_op_eciwx_kernel
,
4293 &gen_op_eciwx_le_kernel
,
4295 static GenOpFunc
*gen_op_ecowx
[] = {
4297 &gen_op_ecowx_le_user
,
4298 &gen_op_ecowx_kernel
,
4299 &gen_op_ecowx_le_kernel
,
4305 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
)
4307 /* Should check EAR[E] & alignment ! */
4308 gen_addr_reg_index(ctx
);
4310 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4314 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
)
4316 /* Should check EAR[E] & alignment ! */
4317 gen_addr_reg_index(ctx
);
4318 gen_op_load_gpr_T1(rS(ctx
->opcode
));
4322 /* PowerPC 601 specific instructions */
4324 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
)
4326 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4328 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4329 if (unlikely(Rc(ctx
->opcode
) != 0))
4334 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
)
4336 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4337 gen_op_POWER_abso();
4338 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4339 if (unlikely(Rc(ctx
->opcode
) != 0))
4344 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
)
4346 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4347 gen_op_POWER_clcs();
4348 /* Rc=1 sets CR0 to an undefined state */
4349 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4353 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
)
4355 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4356 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4358 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4359 if (unlikely(Rc(ctx
->opcode
) != 0))
4364 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
)
4366 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4367 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4368 gen_op_POWER_divo();
4369 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4370 if (unlikely(Rc(ctx
->opcode
) != 0))
4375 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
)
4377 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4378 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4379 gen_op_POWER_divs();
4380 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4381 if (unlikely(Rc(ctx
->opcode
) != 0))
4385 /* divso - divso. */
4386 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
)
4388 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4389 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4390 gen_op_POWER_divso();
4391 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4392 if (unlikely(Rc(ctx
->opcode
) != 0))
4397 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
)
4399 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4400 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4402 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4403 if (unlikely(Rc(ctx
->opcode
) != 0))
4408 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
)
4410 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4411 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4412 gen_op_POWER_dozo();
4413 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4414 if (unlikely(Rc(ctx
->opcode
) != 0))
4419 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
)
4421 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4422 gen_op_set_T1(SIMM(ctx
->opcode
));
4424 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4427 /* As lscbx load from memory byte after byte, it's always endian safe */
4428 #define op_POWER_lscbx(start, ra, rb) \
4429 (*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
4430 #if defined(CONFIG_USER_ONLY)
4431 static GenOpFunc3
*gen_op_POWER_lscbx
[] = {
4432 &gen_op_POWER_lscbx_raw
,
4433 &gen_op_POWER_lscbx_raw
,
4436 static GenOpFunc3
*gen_op_POWER_lscbx
[] = {
4437 &gen_op_POWER_lscbx_user
,
4438 &gen_op_POWER_lscbx_user
,
4439 &gen_op_POWER_lscbx_kernel
,
4440 &gen_op_POWER_lscbx_kernel
,
4444 /* lscbx - lscbx. */
4445 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
)
4447 int ra
= rA(ctx
->opcode
);
4448 int rb
= rB(ctx
->opcode
);
4450 gen_addr_reg_index(ctx
);
4454 /* NIP cannot be restored if the memory exception comes from an helper */
4455 gen_update_nip(ctx
, ctx
->nip
- 4);
4456 gen_op_load_xer_bc();
4457 gen_op_load_xer_cmp();
4458 op_POWER_lscbx(rD(ctx
->opcode
), ra
, rb
);
4459 gen_op_store_xer_bc();
4460 if (unlikely(Rc(ctx
->opcode
) != 0))
4464 /* maskg - maskg. */
4465 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
)
4467 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4468 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4469 gen_op_POWER_maskg();
4470 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4471 if (unlikely(Rc(ctx
->opcode
) != 0))
4475 /* maskir - maskir. */
4476 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
)
4478 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4479 gen_op_load_gpr_T1(rS(ctx
->opcode
));
4480 gen_op_load_gpr_T2(rB(ctx
->opcode
));
4481 gen_op_POWER_maskir();
4482 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4483 if (unlikely(Rc(ctx
->opcode
) != 0))
4488 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
)
4490 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4491 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4493 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4494 if (unlikely(Rc(ctx
->opcode
) != 0))
4499 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
)
4501 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4502 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4503 gen_op_POWER_mulo();
4504 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4505 if (unlikely(Rc(ctx
->opcode
) != 0))
4510 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
)
4512 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4513 gen_op_POWER_nabs();
4514 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4515 if (unlikely(Rc(ctx
->opcode
) != 0))
4519 /* nabso - nabso. */
4520 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
)
4522 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4523 gen_op_POWER_nabso();
4524 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4525 if (unlikely(Rc(ctx
->opcode
) != 0))
4530 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
)
4534 mb
= MB(ctx
->opcode
);
4535 me
= ME(ctx
->opcode
);
4536 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4537 gen_op_load_gpr_T1(rA(ctx
->opcode
));
4538 gen_op_load_gpr_T2(rB(ctx
->opcode
));
4539 gen_op_POWER_rlmi(MASK(mb
, me
), ~MASK(mb
, me
));
4540 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4541 if (unlikely(Rc(ctx
->opcode
) != 0))
4546 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
)
4548 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4549 gen_op_load_gpr_T1(rA(ctx
->opcode
));
4550 gen_op_load_gpr_T2(rB(ctx
->opcode
));
4551 gen_op_POWER_rrib();
4552 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4553 if (unlikely(Rc(ctx
->opcode
) != 0))
4558 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
)
4560 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4561 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4563 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4564 if (unlikely(Rc(ctx
->opcode
) != 0))
4569 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
)
4571 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4572 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4573 gen_op_POWER_sleq();
4574 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4575 if (unlikely(Rc(ctx
->opcode
) != 0))
4580 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
)
4582 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4583 gen_op_set_T1(SH(ctx
->opcode
));
4585 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4586 if (unlikely(Rc(ctx
->opcode
) != 0))
4590 /* slliq - slliq. */
4591 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
)
4593 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4594 gen_op_set_T1(SH(ctx
->opcode
));
4595 gen_op_POWER_sleq();
4596 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4597 if (unlikely(Rc(ctx
->opcode
) != 0))
4602 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
)
4604 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4605 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4606 gen_op_POWER_sllq();
4607 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4608 if (unlikely(Rc(ctx
->opcode
) != 0))
4613 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
)
4615 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4616 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4618 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4619 if (unlikely(Rc(ctx
->opcode
) != 0))
4623 /* sraiq - sraiq. */
4624 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
)
4626 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4627 gen_op_set_T1(SH(ctx
->opcode
));
4628 gen_op_POWER_sraq();
4629 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4630 if (unlikely(Rc(ctx
->opcode
) != 0))
4635 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
)
4637 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4638 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4639 gen_op_POWER_sraq();
4640 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4641 if (unlikely(Rc(ctx
->opcode
) != 0))
4646 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
)
4648 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4649 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4651 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4652 if (unlikely(Rc(ctx
->opcode
) != 0))
4657 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
)
4659 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4660 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4661 gen_op_POWER_srea();
4662 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4663 if (unlikely(Rc(ctx
->opcode
) != 0))
4668 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
)
4670 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4671 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4672 gen_op_POWER_sreq();
4673 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4674 if (unlikely(Rc(ctx
->opcode
) != 0))
4679 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
)
4681 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4682 gen_op_set_T1(SH(ctx
->opcode
));
4684 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4685 if (unlikely(Rc(ctx
->opcode
) != 0))
4690 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
)
4692 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4693 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4694 gen_op_set_T1(SH(ctx
->opcode
));
4695 gen_op_POWER_srlq();
4696 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4697 if (unlikely(Rc(ctx
->opcode
) != 0))
4702 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
)
4704 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4705 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4706 gen_op_POWER_srlq();
4707 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4708 if (unlikely(Rc(ctx
->opcode
) != 0))
4713 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
)
4715 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4716 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4718 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4719 if (unlikely(Rc(ctx
->opcode
) != 0))
4723 /* PowerPC 602 specific instructions */
4725 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
)
4728 GEN_EXCP_INVAL(ctx
);
4732 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
)
4735 GEN_EXCP_INVAL(ctx
);
4739 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
)
4741 #if defined(CONFIG_USER_ONLY)
4742 GEN_EXCP_PRIVOPC(ctx
);
4744 if (unlikely(!ctx
->supervisor
)) {
4745 GEN_EXCP_PRIVOPC(ctx
);
4748 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4750 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4754 /* 602 - 603 - G2 TLB management */
4756 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
)
4758 #if defined(CONFIG_USER_ONLY)
4759 GEN_EXCP_PRIVOPC(ctx
);
4761 if (unlikely(!ctx
->supervisor
)) {
4762 GEN_EXCP_PRIVOPC(ctx
);
4765 gen_op_load_gpr_T0(rB(ctx
->opcode
));
4771 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
)
4773 #if defined(CONFIG_USER_ONLY)
4774 GEN_EXCP_PRIVOPC(ctx
);
4776 if (unlikely(!ctx
->supervisor
)) {
4777 GEN_EXCP_PRIVOPC(ctx
);
4780 gen_op_load_gpr_T0(rB(ctx
->opcode
));
4785 /* 74xx TLB management */
4787 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
)
4789 #if defined(CONFIG_USER_ONLY)
4790 GEN_EXCP_PRIVOPC(ctx
);
4792 if (unlikely(!ctx
->supervisor
)) {
4793 GEN_EXCP_PRIVOPC(ctx
);
4796 gen_op_load_gpr_T0(rB(ctx
->opcode
));
4797 gen_op_74xx_tlbld();
4802 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
)
4804 #if defined(CONFIG_USER_ONLY)
4805 GEN_EXCP_PRIVOPC(ctx
);
4807 if (unlikely(!ctx
->supervisor
)) {
4808 GEN_EXCP_PRIVOPC(ctx
);
4811 gen_op_load_gpr_T0(rB(ctx
->opcode
));
4812 gen_op_74xx_tlbli();
4816 /* POWER instructions not in PowerPC 601 */
4818 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
)
4820 /* Cache line flush: implemented as no-op */
4824 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
)
4826 /* Cache line invalidate: privileged and treated as no-op */
4827 #if defined(CONFIG_USER_ONLY)
4828 GEN_EXCP_PRIVOPC(ctx
);
4830 if (unlikely(!ctx
->supervisor
)) {
4831 GEN_EXCP_PRIVOPC(ctx
);
4838 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
)
4840 /* Data cache line store: treated as no-op */
4843 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
)
4845 #if defined(CONFIG_USER_ONLY)
4846 GEN_EXCP_PRIVOPC(ctx
);
4848 if (unlikely(!ctx
->supervisor
)) {
4849 GEN_EXCP_PRIVOPC(ctx
);
4852 int ra
= rA(ctx
->opcode
);
4853 int rd
= rD(ctx
->opcode
);
4855 gen_addr_reg_index(ctx
);
4856 gen_op_POWER_mfsri();
4857 gen_op_store_T0_gpr(rd
);
4858 if (ra
!= 0 && ra
!= rd
)
4859 gen_op_store_T1_gpr(ra
);
4863 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
)
4865 #if defined(CONFIG_USER_ONLY)
4866 GEN_EXCP_PRIVOPC(ctx
);
4868 if (unlikely(!ctx
->supervisor
)) {
4869 GEN_EXCP_PRIVOPC(ctx
);
4872 gen_addr_reg_index(ctx
);
4874 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4878 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
)
4880 #if defined(CONFIG_USER_ONLY)
4881 GEN_EXCP_PRIVOPC(ctx
);
4883 if (unlikely(!ctx
->supervisor
)) {
4884 GEN_EXCP_PRIVOPC(ctx
);
4887 gen_op_POWER_rfsvc();
4892 /* svc is not implemented for now */
4894 /* POWER2 specific instructions */
4895 /* Quad manipulation (load/store two floats at a time) */
4896 #define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4897 #define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
4898 #if defined(CONFIG_USER_ONLY)
4899 static GenOpFunc
*gen_op_POWER2_lfq
[] = {
4900 &gen_op_POWER2_lfq_le_raw
,
4901 &gen_op_POWER2_lfq_raw
,
4903 static GenOpFunc
*gen_op_POWER2_stfq
[] = {
4904 &gen_op_POWER2_stfq_le_raw
,
4905 &gen_op_POWER2_stfq_raw
,
4908 static GenOpFunc
*gen_op_POWER2_lfq
[] = {
4909 &gen_op_POWER2_lfq_le_user
,
4910 &gen_op_POWER2_lfq_user
,
4911 &gen_op_POWER2_lfq_le_kernel
,
4912 &gen_op_POWER2_lfq_kernel
,
4914 static GenOpFunc
*gen_op_POWER2_stfq
[] = {
4915 &gen_op_POWER2_stfq_le_user
,
4916 &gen_op_POWER2_stfq_user
,
4917 &gen_op_POWER2_stfq_le_kernel
,
4918 &gen_op_POWER2_stfq_kernel
,
4923 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
4925 /* NIP cannot be restored if the memory exception comes from an helper */
4926 gen_update_nip(ctx
, ctx
->nip
- 4);
4927 gen_addr_imm_index(ctx
, 0);
4929 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
4930 gen_op_store_FT1_fpr(rD(ctx
->opcode
) + 1);
4934 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
4936 int ra
= rA(ctx
->opcode
);
4938 /* NIP cannot be restored if the memory exception comes from an helper */
4939 gen_update_nip(ctx
, ctx
->nip
- 4);
4940 gen_addr_imm_index(ctx
, 0);
4942 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
4943 gen_op_store_FT1_fpr(rD(ctx
->opcode
) + 1);
4945 gen_op_store_T0_gpr(ra
);
4949 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
)
4951 int ra
= rA(ctx
->opcode
);
4953 /* NIP cannot be restored if the memory exception comes from an helper */
4954 gen_update_nip(ctx
, ctx
->nip
- 4);
4955 gen_addr_reg_index(ctx
);
4957 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
4958 gen_op_store_FT1_fpr(rD(ctx
->opcode
) + 1);
4960 gen_op_store_T0_gpr(ra
);
4964 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
)
4966 /* NIP cannot be restored if the memory exception comes from an helper */
4967 gen_update_nip(ctx
, ctx
->nip
- 4);
4968 gen_addr_reg_index(ctx
);
4970 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
4971 gen_op_store_FT1_fpr(rD(ctx
->opcode
) + 1);
4975 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
4977 /* NIP cannot be restored if the memory exception comes from an helper */
4978 gen_update_nip(ctx
, ctx
->nip
- 4);
4979 gen_addr_imm_index(ctx
, 0);
4980 gen_op_load_fpr_FT0(rS(ctx
->opcode
));
4981 gen_op_load_fpr_FT1(rS(ctx
->opcode
) + 1);
4986 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
4988 int ra
= rA(ctx
->opcode
);
4990 /* NIP cannot be restored if the memory exception comes from an helper */
4991 gen_update_nip(ctx
, ctx
->nip
- 4);
4992 gen_addr_imm_index(ctx
, 0);
4993 gen_op_load_fpr_FT0(rS(ctx
->opcode
));
4994 gen_op_load_fpr_FT1(rS(ctx
->opcode
) + 1);
4997 gen_op_store_T0_gpr(ra
);
5001 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
)
5003 int ra
= rA(ctx
->opcode
);
5005 /* NIP cannot be restored if the memory exception comes from an helper */
5006 gen_update_nip(ctx
, ctx
->nip
- 4);
5007 gen_addr_reg_index(ctx
);
5008 gen_op_load_fpr_FT0(rS(ctx
->opcode
));
5009 gen_op_load_fpr_FT1(rS(ctx
->opcode
) + 1);
5012 gen_op_store_T0_gpr(ra
);
5016 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
)
5018 /* NIP cannot be restored if the memory exception comes from an helper */
5019 gen_update_nip(ctx
, ctx
->nip
- 4);
5020 gen_addr_reg_index(ctx
);
5021 gen_op_load_fpr_FT0(rS(ctx
->opcode
));
5022 gen_op_load_fpr_FT1(rS(ctx
->opcode
) + 1);
5026 /* BookE specific instructions */
5027 /* XXX: not implemented on 440 ? */
5028 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE_EXT
)
5031 GEN_EXCP_INVAL(ctx
);
5034 /* XXX: not implemented on 440 ? */
5035 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_BOOKE_EXT
)
5037 #if defined(CONFIG_USER_ONLY)
5038 GEN_EXCP_PRIVOPC(ctx
);
5040 if (unlikely(!ctx
->supervisor
)) {
5041 GEN_EXCP_PRIVOPC(ctx
);
5044 gen_addr_reg_index(ctx
);
5045 /* Use the same micro-ops as for tlbie */
5046 #if defined(TARGET_PPC64)
5055 /* All 405 MAC instructions are translated here */
5056 static always_inline
void gen_405_mulladd_insn (DisasContext
*ctx
,
5058 int ra
, int rb
, int rt
, int Rc
)
5060 gen_op_load_gpr_T0(ra
);
5061 gen_op_load_gpr_T1(rb
);
5062 switch (opc3
& 0x0D) {
5064 /* macchw - macchw. - macchwo - macchwo. */
5065 /* macchws - macchws. - macchwso - macchwso. */
5066 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5067 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5068 /* mulchw - mulchw. */
5069 gen_op_405_mulchw();
5072 /* macchwu - macchwu. - macchwuo - macchwuo. */
5073 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5074 /* mulchwu - mulchwu. */
5075 gen_op_405_mulchwu();
5078 /* machhw - machhw. - machhwo - machhwo. */
5079 /* machhws - machhws. - machhwso - machhwso. */
5080 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5081 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5082 /* mulhhw - mulhhw. */
5083 gen_op_405_mulhhw();
5086 /* machhwu - machhwu. - machhwuo - machhwuo. */
5087 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5088 /* mulhhwu - mulhhwu. */
5089 gen_op_405_mulhhwu();
5092 /* maclhw - maclhw. - maclhwo - maclhwo. */
5093 /* maclhws - maclhws. - maclhwso - maclhwso. */
5094 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5095 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5096 /* mullhw - mullhw. */
5097 gen_op_405_mullhw();
5100 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5101 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5102 /* mullhwu - mullhwu. */
5103 gen_op_405_mullhwu();
5107 /* nmultiply-and-accumulate (0x0E) */
5111 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
5112 gen_op_load_gpr_T2(rt
);
5113 gen_op_move_T1_T0();
5114 gen_op_405_add_T0_T2();
5117 /* Check overflow */
5119 gen_op_405_check_ov();
5121 gen_op_405_check_ovu();
5126 gen_op_405_check_sat();
5128 gen_op_405_check_satu();
5130 gen_op_store_T0_gpr(rt
);
5131 if (unlikely(Rc
) != 0) {
5137 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5138 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
5140 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5141 rD(ctx->opcode), Rc(ctx->opcode)); \
5144 /* macchw - macchw. */
5145 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
5146 /* macchwo - macchwo. */
5147 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
5148 /* macchws - macchws. */
5149 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
5150 /* macchwso - macchwso. */
5151 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
5152 /* macchwsu - macchwsu. */
5153 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
5154 /* macchwsuo - macchwsuo. */
5155 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
5156 /* macchwu - macchwu. */
5157 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
5158 /* macchwuo - macchwuo. */
5159 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
5160 /* machhw - machhw. */
5161 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
5162 /* machhwo - machhwo. */
5163 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
5164 /* machhws - machhws. */
5165 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
5166 /* machhwso - machhwso. */
5167 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
5168 /* machhwsu - machhwsu. */
5169 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
5170 /* machhwsuo - machhwsuo. */
5171 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
5172 /* machhwu - machhwu. */
5173 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
5174 /* machhwuo - machhwuo. */
5175 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
5176 /* maclhw - maclhw. */
5177 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
5178 /* maclhwo - maclhwo. */
5179 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
5180 /* maclhws - maclhws. */
5181 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
5182 /* maclhwso - maclhwso. */
5183 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
5184 /* maclhwu - maclhwu. */
5185 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
5186 /* maclhwuo - maclhwuo. */
5187 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
5188 /* maclhwsu - maclhwsu. */
5189 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
5190 /* maclhwsuo - maclhwsuo. */
5191 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
5192 /* nmacchw - nmacchw. */
5193 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
5194 /* nmacchwo - nmacchwo. */
5195 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
5196 /* nmacchws - nmacchws. */
5197 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
5198 /* nmacchwso - nmacchwso. */
5199 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
5200 /* nmachhw - nmachhw. */
5201 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
5202 /* nmachhwo - nmachhwo. */
5203 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
5204 /* nmachhws - nmachhws. */
5205 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
5206 /* nmachhwso - nmachhwso. */
5207 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
5208 /* nmaclhw - nmaclhw. */
5209 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
5210 /* nmaclhwo - nmaclhwo. */
5211 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
5212 /* nmaclhws - nmaclhws. */
5213 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
5214 /* nmaclhwso - nmaclhwso. */
5215 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
5217 /* mulchw - mulchw. */
5218 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
5219 /* mulchwu - mulchwu. */
5220 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
5221 /* mulhhw - mulhhw. */
5222 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
5223 /* mulhhwu - mulhhwu. */
5224 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
5225 /* mullhw - mullhw. */
5226 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
5227 /* mullhwu - mullhwu. */
5228 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
5231 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_EMB_COMMON
)
5233 #if defined(CONFIG_USER_ONLY)
5234 GEN_EXCP_PRIVREG(ctx
);
5236 uint32_t dcrn
= SPR(ctx
->opcode
);
5238 if (unlikely(!ctx
->supervisor
)) {
5239 GEN_EXCP_PRIVREG(ctx
);
5242 gen_op_set_T0(dcrn
);
5244 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5249 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_EMB_COMMON
)
5251 #if defined(CONFIG_USER_ONLY)
5252 GEN_EXCP_PRIVREG(ctx
);
5254 uint32_t dcrn
= SPR(ctx
->opcode
);
5256 if (unlikely(!ctx
->supervisor
)) {
5257 GEN_EXCP_PRIVREG(ctx
);
5260 gen_op_set_T0(dcrn
);
5261 gen_op_load_gpr_T1(rS(ctx
->opcode
));
5267 /* XXX: not implemented on 440 ? */
5268 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_BOOKE_EXT
)
5270 #if defined(CONFIG_USER_ONLY)
5271 GEN_EXCP_PRIVREG(ctx
);
5273 if (unlikely(!ctx
->supervisor
)) {
5274 GEN_EXCP_PRIVREG(ctx
);
5277 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5279 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5280 /* Note: Rc update flag set leads to undefined state of Rc0 */
5285 /* XXX: not implemented on 440 ? */
5286 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_BOOKE_EXT
)
5288 #if defined(CONFIG_USER_ONLY)
5289 GEN_EXCP_PRIVREG(ctx
);
5291 if (unlikely(!ctx
->supervisor
)) {
5292 GEN_EXCP_PRIVREG(ctx
);
5295 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5296 gen_op_load_gpr_T1(rS(ctx
->opcode
));
5298 /* Note: Rc update flag set leads to undefined state of Rc0 */
5302 /* mfdcrux (PPC 460) : user-mode access to DCR */
5303 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
)
5305 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5307 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5308 /* Note: Rc update flag set leads to undefined state of Rc0 */
5311 /* mtdcrux (PPC 460) : user-mode access to DCR */
5312 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
)
5314 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5315 gen_op_load_gpr_T1(rS(ctx
->opcode
));
5317 /* Note: Rc update flag set leads to undefined state of Rc0 */
5321 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
)
5323 #if defined(CONFIG_USER_ONLY)
5324 GEN_EXCP_PRIVOPC(ctx
);
5326 if (unlikely(!ctx
->supervisor
)) {
5327 GEN_EXCP_PRIVOPC(ctx
);
5330 /* interpreted as no-op */
5335 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
)
5337 #if defined(CONFIG_USER_ONLY)
5338 GEN_EXCP_PRIVOPC(ctx
);
5340 if (unlikely(!ctx
->supervisor
)) {
5341 GEN_EXCP_PRIVOPC(ctx
);
5344 gen_addr_reg_index(ctx
);
5346 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5351 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
)
5353 /* interpreted as no-op */
5354 /* XXX: specification say this is treated as a load by the MMU
5355 * but does not generate any exception
5360 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
)
5362 #if defined(CONFIG_USER_ONLY)
5363 GEN_EXCP_PRIVOPC(ctx
);
5365 if (unlikely(!ctx
->supervisor
)) {
5366 GEN_EXCP_PRIVOPC(ctx
);
5369 /* interpreted as no-op */
5374 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
)
5376 #if defined(CONFIG_USER_ONLY)
5377 GEN_EXCP_PRIVOPC(ctx
);
5379 if (unlikely(!ctx
->supervisor
)) {
5380 GEN_EXCP_PRIVOPC(ctx
);
5383 /* interpreted as no-op */
5387 /* rfci (supervisor only) */
5388 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
)
5390 #if defined(CONFIG_USER_ONLY)
5391 GEN_EXCP_PRIVOPC(ctx
);
5393 if (unlikely(!ctx
->supervisor
)) {
5394 GEN_EXCP_PRIVOPC(ctx
);
5397 /* Restore CPU state */
5403 GEN_HANDLER(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
)
5405 #if defined(CONFIG_USER_ONLY)
5406 GEN_EXCP_PRIVOPC(ctx
);
5408 if (unlikely(!ctx
->supervisor
)) {
5409 GEN_EXCP_PRIVOPC(ctx
);
5412 /* Restore CPU state */
5418 /* BookE specific */
5419 /* XXX: not implemented on 440 ? */
5420 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE_EXT
)
5422 #if defined(CONFIG_USER_ONLY)
5423 GEN_EXCP_PRIVOPC(ctx
);
5425 if (unlikely(!ctx
->supervisor
)) {
5426 GEN_EXCP_PRIVOPC(ctx
);
5429 /* Restore CPU state */
5435 /* XXX: not implemented on 440 ? */
5436 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
)
5438 #if defined(CONFIG_USER_ONLY)
5439 GEN_EXCP_PRIVOPC(ctx
);
5441 if (unlikely(!ctx
->supervisor
)) {
5442 GEN_EXCP_PRIVOPC(ctx
);
5445 /* Restore CPU state */
5451 /* TLB management - PowerPC 405 implementation */
5453 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
)
5455 #if defined(CONFIG_USER_ONLY)
5456 GEN_EXCP_PRIVOPC(ctx
);
5458 if (unlikely(!ctx
->supervisor
)) {
5459 GEN_EXCP_PRIVOPC(ctx
);
5462 switch (rB(ctx
->opcode
)) {
5464 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5465 gen_op_4xx_tlbre_hi();
5466 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5469 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5470 gen_op_4xx_tlbre_lo();
5471 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5474 GEN_EXCP_INVAL(ctx
);
5480 /* tlbsx - tlbsx. */
5481 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
)
5483 #if defined(CONFIG_USER_ONLY)
5484 GEN_EXCP_PRIVOPC(ctx
);
5486 if (unlikely(!ctx
->supervisor
)) {
5487 GEN_EXCP_PRIVOPC(ctx
);
5490 gen_addr_reg_index(ctx
);
5492 if (Rc(ctx
->opcode
))
5493 gen_op_4xx_tlbsx_check();
5494 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5499 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
)
5501 #if defined(CONFIG_USER_ONLY)
5502 GEN_EXCP_PRIVOPC(ctx
);
5504 if (unlikely(!ctx
->supervisor
)) {
5505 GEN_EXCP_PRIVOPC(ctx
);
5508 switch (rB(ctx
->opcode
)) {
5510 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5511 gen_op_load_gpr_T1(rS(ctx
->opcode
));
5512 gen_op_4xx_tlbwe_hi();
5515 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5516 gen_op_load_gpr_T1(rS(ctx
->opcode
));
5517 gen_op_4xx_tlbwe_lo();
5520 GEN_EXCP_INVAL(ctx
);
5526 /* TLB management - PowerPC 440 implementation */
5528 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
)
5530 #if defined(CONFIG_USER_ONLY)
5531 GEN_EXCP_PRIVOPC(ctx
);
5533 if (unlikely(!ctx
->supervisor
)) {
5534 GEN_EXCP_PRIVOPC(ctx
);
5537 switch (rB(ctx
->opcode
)) {
5541 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5542 gen_op_440_tlbre(rB(ctx
->opcode
));
5543 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5546 GEN_EXCP_INVAL(ctx
);
5552 /* tlbsx - tlbsx. */
5553 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
)
5555 #if defined(CONFIG_USER_ONLY)
5556 GEN_EXCP_PRIVOPC(ctx
);
5558 if (unlikely(!ctx
->supervisor
)) {
5559 GEN_EXCP_PRIVOPC(ctx
);
5562 gen_addr_reg_index(ctx
);
5564 if (Rc(ctx
->opcode
))
5565 gen_op_4xx_tlbsx_check();
5566 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5571 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
)
5573 #if defined(CONFIG_USER_ONLY)
5574 GEN_EXCP_PRIVOPC(ctx
);
5576 if (unlikely(!ctx
->supervisor
)) {
5577 GEN_EXCP_PRIVOPC(ctx
);
5580 switch (rB(ctx
->opcode
)) {
5584 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5585 gen_op_load_gpr_T1(rS(ctx
->opcode
));
5586 gen_op_440_tlbwe(rB(ctx
->opcode
));
5589 GEN_EXCP_INVAL(ctx
);
5596 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_EMB_COMMON
)
5598 #if defined(CONFIG_USER_ONLY)
5599 GEN_EXCP_PRIVOPC(ctx
);
5601 if (unlikely(!ctx
->supervisor
)) {
5602 GEN_EXCP_PRIVOPC(ctx
);
5605 gen_op_load_gpr_T0(rD(ctx
->opcode
));
5607 /* Stop translation to have a chance to raise an exception
5608 * if we just set msr_ee to 1
5615 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_EMB_COMMON
)
5617 #if defined(CONFIG_USER_ONLY)
5618 GEN_EXCP_PRIVOPC(ctx
);
5620 if (unlikely(!ctx
->supervisor
)) {
5621 GEN_EXCP_PRIVOPC(ctx
);
5624 gen_op_set_T0(ctx
->opcode
& 0x00010000);
5626 /* Stop translation to have a chance to raise an exception
5627 * if we just set msr_ee to 1
5633 /* PowerPC 440 specific instructions */
5635 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
)
5637 gen_op_load_gpr_T0(rS(ctx
->opcode
));
5638 gen_op_load_gpr_T1(rB(ctx
->opcode
));
5640 gen_op_store_T0_gpr(rA(ctx
->opcode
));
5641 gen_op_store_xer_bc();
5642 if (Rc(ctx
->opcode
)) {
5643 gen_op_440_dlmzb_update_Rc();
5644 gen_op_store_T0_crf(0);
5648 /* mbar replaces eieio on 440 */
5649 GEN_HANDLER(mbar
, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE
)
5651 /* interpreted as no-op */
5654 /* msync replaces sync on 440 */
5655 GEN_HANDLER(msync
, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE
)
5657 /* interpreted as no-op */
5661 GEN_HANDLER2(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE
)
5663 /* interpreted as no-op */
5664 /* XXX: specification say this is treated as a load by the MMU
5665 * but does not generate any exception
5669 /*** Altivec vector extension ***/
5670 /* Altivec registers moves */
5671 GEN32(gen_op_load_avr_A0
, gen_op_load_avr_A0_avr
);
5672 GEN32(gen_op_load_avr_A1
, gen_op_load_avr_A1_avr
);
5673 GEN32(gen_op_load_avr_A2
, gen_op_load_avr_A2_avr
);
5675 GEN32(gen_op_store_A0_avr
, gen_op_store_A0_avr_avr
);
5676 GEN32(gen_op_store_A1_avr
, gen_op_store_A1_avr_avr
);
5678 GEN32(gen_op_store_A2_avr
, gen_op_store_A2_avr_avr
);
5681 #define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5682 #if defined(CONFIG_USER_ONLY)
5683 #if defined(TARGET_PPC64)
5684 /* User-mode only - 64 bits mode */
5685 #define OP_VR_LD_TABLE(name) \
5686 static GenOpFunc *gen_op_vr_l##name[] = { \
5687 &gen_op_vr_l##name##_raw, \
5688 &gen_op_vr_l##name##_le_raw, \
5689 &gen_op_vr_l##name##_64_raw, \
5690 &gen_op_vr_l##name##_le_64_raw, \
5692 #define OP_VR_ST_TABLE(name) \
5693 static GenOpFunc *gen_op_vr_st##name[] = { \
5694 &gen_op_vr_st##name##_raw, \
5695 &gen_op_vr_st##name##_le_raw, \
5696 &gen_op_vr_st##name##_64_raw, \
5697 &gen_op_vr_st##name##_le_64_raw, \
5699 #else /* defined(TARGET_PPC64) */
5700 /* User-mode only - 32 bits mode */
5701 #define OP_VR_LD_TABLE(name) \
5702 static GenOpFunc *gen_op_vr_l##name[] = { \
5703 &gen_op_vr_l##name##_raw, \
5704 &gen_op_vr_l##name##_le_raw, \
5706 #define OP_VR_ST_TABLE(name) \
5707 static GenOpFunc *gen_op_vr_st##name[] = { \
5708 &gen_op_vr_st##name##_raw, \
5709 &gen_op_vr_st##name##_le_raw, \
5711 #endif /* defined(TARGET_PPC64) */
5712 #else /* defined(CONFIG_USER_ONLY) */
5713 #if defined(TARGET_PPC64H)
5714 /* Full system with hypervisor mode */
5715 #define OP_VR_LD_TABLE(name) \
5716 static GenOpFunc *gen_op_vr_l##name[] = { \
5717 &gen_op_vr_l##name##_user, \
5718 &gen_op_vr_l##name##_le_user, \
5719 &gen_op_vr_l##name##_64_user, \
5720 &gen_op_vr_l##name##_le_64_user, \
5721 &gen_op_vr_l##name##_kernel, \
5722 &gen_op_vr_l##name##_le_kernel, \
5723 &gen_op_vr_l##name##_64_kernel, \
5724 &gen_op_vr_l##name##_le_64_kernel, \
5725 &gen_op_vr_l##name##_hypv, \
5726 &gen_op_vr_l##name##_le_hypv, \
5727 &gen_op_vr_l##name##_64_hypv, \
5728 &gen_op_vr_l##name##_le_64_hypv, \
5730 #define OP_VR_ST_TABLE(name) \
5731 static GenOpFunc *gen_op_vr_st##name[] = { \
5732 &gen_op_vr_st##name##_user, \
5733 &gen_op_vr_st##name##_le_user, \
5734 &gen_op_vr_st##name##_64_user, \
5735 &gen_op_vr_st##name##_le_64_user, \
5736 &gen_op_vr_st##name##_kernel, \
5737 &gen_op_vr_st##name##_le_kernel, \
5738 &gen_op_vr_st##name##_64_kernel, \
5739 &gen_op_vr_st##name##_le_64_kernel, \
5740 &gen_op_vr_st##name##_hypv, \
5741 &gen_op_vr_st##name##_le_hypv, \
5742 &gen_op_vr_st##name##_64_hypv, \
5743 &gen_op_vr_st##name##_le_64_hypv, \
5745 #elif defined(TARGET_PPC64)
5746 /* Full system - 64 bits mode */
5747 #define OP_VR_LD_TABLE(name) \
5748 static GenOpFunc *gen_op_vr_l##name[] = { \
5749 &gen_op_vr_l##name##_user, \
5750 &gen_op_vr_l##name##_le_user, \
5751 &gen_op_vr_l##name##_64_user, \
5752 &gen_op_vr_l##name##_le_64_user, \
5753 &gen_op_vr_l##name##_kernel, \
5754 &gen_op_vr_l##name##_le_kernel, \
5755 &gen_op_vr_l##name##_64_kernel, \
5756 &gen_op_vr_l##name##_le_64_kernel, \
5758 #define OP_VR_ST_TABLE(name) \
5759 static GenOpFunc *gen_op_vr_st##name[] = { \
5760 &gen_op_vr_st##name##_user, \
5761 &gen_op_vr_st##name##_le_user, \
5762 &gen_op_vr_st##name##_64_user, \
5763 &gen_op_vr_st##name##_le_64_user, \
5764 &gen_op_vr_st##name##_kernel, \
5765 &gen_op_vr_st##name##_le_kernel, \
5766 &gen_op_vr_st##name##_64_kernel, \
5767 &gen_op_vr_st##name##_le_64_kernel, \
5769 #else /* defined(TARGET_PPC64) */
5770 /* Full system - 32 bits mode */
5771 #define OP_VR_LD_TABLE(name) \
5772 static GenOpFunc *gen_op_vr_l##name[] = { \
5773 &gen_op_vr_l##name##_user, \
5774 &gen_op_vr_l##name##_le_user, \
5775 &gen_op_vr_l##name##_kernel, \
5776 &gen_op_vr_l##name##_le_kernel, \
5778 #define OP_VR_ST_TABLE(name) \
5779 static GenOpFunc *gen_op_vr_st##name[] = { \
5780 &gen_op_vr_st##name##_user, \
5781 &gen_op_vr_st##name##_le_user, \
5782 &gen_op_vr_st##name##_kernel, \
5783 &gen_op_vr_st##name##_le_kernel, \
5785 #endif /* defined(TARGET_PPC64) */
5786 #endif /* defined(CONFIG_USER_ONLY) */
5788 #define GEN_VR_LDX(name, opc2, opc3) \
5789 GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5791 if (unlikely(!ctx->altivec_enabled)) { \
5792 GEN_EXCP_NO_VR(ctx); \
5795 gen_addr_reg_index(ctx); \
5796 op_vr_ldst(vr_l##name); \
5797 gen_op_store_A0_avr(rD(ctx->opcode)); \
5800 #define GEN_VR_STX(name, opc2, opc3) \
5801 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5803 if (unlikely(!ctx->altivec_enabled)) { \
5804 GEN_EXCP_NO_VR(ctx); \
5807 gen_addr_reg_index(ctx); \
5808 gen_op_load_avr_A0(rS(ctx->opcode)); \
5809 op_vr_ldst(vr_st##name); \
5813 GEN_VR_LDX(vx
, 0x07, 0x03);
5814 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5815 #define gen_op_vr_lvxl gen_op_vr_lvx
5816 GEN_VR_LDX(vxl
, 0x07, 0x0B);
5819 GEN_VR_STX(vx
, 0x07, 0x07);
5820 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5821 #define gen_op_vr_stvxl gen_op_vr_stvx
5822 GEN_VR_STX(vxl
, 0x07, 0x0F);
5824 #if defined(TARGET_PPCEMB)
5825 /*** SPE extension ***/
5827 /* Register moves */
5828 GEN32(gen_op_load_gpr64_T0
, gen_op_load_gpr64_T0_gpr
);
5829 GEN32(gen_op_load_gpr64_T1
, gen_op_load_gpr64_T1_gpr
);
5831 GEN32(gen_op_load_gpr64_T2
, gen_op_load_gpr64_T2_gpr
);
5834 GEN32(gen_op_store_T0_gpr64
, gen_op_store_T0_gpr64_gpr
);
5835 GEN32(gen_op_store_T1_gpr64
, gen_op_store_T1_gpr64_gpr
);
5837 GEN32(gen_op_store_T2_gpr64
, gen_op_store_T2_gpr64_gpr
);
5840 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5841 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5843 if (Rc(ctx->opcode)) \
5849 /* Handler for undefined SPE opcodes */
5850 static always_inline
void gen_speundef (DisasContext
*ctx
)
5852 GEN_EXCP_INVAL(ctx
);
5855 /* SPE load and stores */
5856 static always_inline
void gen_addr_spe_imm_index (DisasContext
*ctx
, int sh
)
5858 target_long simm
= rB(ctx
->opcode
);
5860 if (rA(ctx
->opcode
) == 0) {
5861 gen_set_T0(simm
<< sh
);
5863 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5864 if (likely(simm
!= 0))
5865 gen_op_addi(simm
<< sh
);
5869 #define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5870 #if defined(CONFIG_USER_ONLY)
5871 #if defined(TARGET_PPC64)
5872 /* User-mode only - 64 bits mode */
5873 #define OP_SPE_LD_TABLE(name) \
5874 static GenOpFunc *gen_op_spe_l##name[] = { \
5875 &gen_op_spe_l##name##_raw, \
5876 &gen_op_spe_l##name##_le_raw, \
5877 &gen_op_spe_l##name##_64_raw, \
5878 &gen_op_spe_l##name##_le_64_raw, \
5880 #define OP_SPE_ST_TABLE(name) \
5881 static GenOpFunc *gen_op_spe_st##name[] = { \
5882 &gen_op_spe_st##name##_raw, \
5883 &gen_op_spe_st##name##_le_raw, \
5884 &gen_op_spe_st##name##_64_raw, \
5885 &gen_op_spe_st##name##_le_64_raw, \
5887 #else /* defined(TARGET_PPC64) */
5888 /* User-mode only - 32 bits mode */
5889 #define OP_SPE_LD_TABLE(name) \
5890 static GenOpFunc *gen_op_spe_l##name[] = { \
5891 &gen_op_spe_l##name##_raw, \
5892 &gen_op_spe_l##name##_le_raw, \
5894 #define OP_SPE_ST_TABLE(name) \
5895 static GenOpFunc *gen_op_spe_st##name[] = { \
5896 &gen_op_spe_st##name##_raw, \
5897 &gen_op_spe_st##name##_le_raw, \
5899 #endif /* defined(TARGET_PPC64) */
5900 #else /* defined(CONFIG_USER_ONLY) */
5901 #if defined(TARGET_PPC64H)
5902 /* Full system with hypervisor mode */
5903 #define OP_SPE_LD_TABLE(name) \
5904 static GenOpFunc *gen_op_spe_l##name[] = { \
5905 &gen_op_spe_l##name##_user, \
5906 &gen_op_spe_l##name##_le_user, \
5907 &gen_op_spe_l##name##_64_user, \
5908 &gen_op_spe_l##name##_le_64_user, \
5909 &gen_op_spe_l##name##_kernel, \
5910 &gen_op_spe_l##name##_le_kernel, \
5911 &gen_op_spe_l##name##_64_kernel, \
5912 &gen_op_spe_l##name##_le_64_kernel, \
5913 &gen_op_spe_l##name##_hypv, \
5914 &gen_op_spe_l##name##_le_hypv, \
5915 &gen_op_spe_l##name##_64_hypv, \
5916 &gen_op_spe_l##name##_le_64_hypv, \
5918 #define OP_SPE_ST_TABLE(name) \
5919 static GenOpFunc *gen_op_spe_st##name[] = { \
5920 &gen_op_spe_st##name##_user, \
5921 &gen_op_spe_st##name##_le_user, \
5922 &gen_op_spe_st##name##_64_user, \
5923 &gen_op_spe_st##name##_le_64_user, \
5924 &gen_op_spe_st##name##_kernel, \
5925 &gen_op_spe_st##name##_le_kernel, \
5926 &gen_op_spe_st##name##_64_kernel, \
5927 &gen_op_spe_st##name##_le_64_kernel, \
5928 &gen_op_spe_st##name##_hypv, \
5929 &gen_op_spe_st##name##_le_hypv, \
5930 &gen_op_spe_st##name##_64_hypv, \
5931 &gen_op_spe_st##name##_le_64_hypv, \
5933 #elif defined(TARGET_PPC64)
5934 /* Full system - 64 bits mode */
5935 #define OP_SPE_LD_TABLE(name) \
5936 static GenOpFunc *gen_op_spe_l##name[] = { \
5937 &gen_op_spe_l##name##_user, \
5938 &gen_op_spe_l##name##_le_user, \
5939 &gen_op_spe_l##name##_64_user, \
5940 &gen_op_spe_l##name##_le_64_user, \
5941 &gen_op_spe_l##name##_kernel, \
5942 &gen_op_spe_l##name##_le_kernel, \
5943 &gen_op_spe_l##name##_64_kernel, \
5944 &gen_op_spe_l##name##_le_64_kernel, \
5946 #define OP_SPE_ST_TABLE(name) \
5947 static GenOpFunc *gen_op_spe_st##name[] = { \
5948 &gen_op_spe_st##name##_user, \
5949 &gen_op_spe_st##name##_le_user, \
5950 &gen_op_spe_st##name##_64_user, \
5951 &gen_op_spe_st##name##_le_64_user, \
5952 &gen_op_spe_st##name##_kernel, \
5953 &gen_op_spe_st##name##_le_kernel, \
5954 &gen_op_spe_st##name##_64_kernel, \
5955 &gen_op_spe_st##name##_le_64_kernel, \
5957 #else /* defined(TARGET_PPC64) */
5958 /* Full system - 32 bits mode */
5959 #define OP_SPE_LD_TABLE(name) \
5960 static GenOpFunc *gen_op_spe_l##name[] = { \
5961 &gen_op_spe_l##name##_user, \
5962 &gen_op_spe_l##name##_le_user, \
5963 &gen_op_spe_l##name##_kernel, \
5964 &gen_op_spe_l##name##_le_kernel, \
5966 #define OP_SPE_ST_TABLE(name) \
5967 static GenOpFunc *gen_op_spe_st##name[] = { \
5968 &gen_op_spe_st##name##_user, \
5969 &gen_op_spe_st##name##_le_user, \
5970 &gen_op_spe_st##name##_kernel, \
5971 &gen_op_spe_st##name##_le_kernel, \
5973 #endif /* defined(TARGET_PPC64) */
5974 #endif /* defined(CONFIG_USER_ONLY) */
5976 #define GEN_SPE_LD(name, sh) \
5977 static always_inline void gen_evl##name (DisasContext *ctx) \
5979 if (unlikely(!ctx->spe_enabled)) { \
5980 GEN_EXCP_NO_AP(ctx); \
5983 gen_addr_spe_imm_index(ctx, sh); \
5984 op_spe_ldst(spe_l##name); \
5985 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5988 #define GEN_SPE_LDX(name) \
5989 static always_inline void gen_evl##name##x (DisasContext *ctx) \
5991 if (unlikely(!ctx->spe_enabled)) { \
5992 GEN_EXCP_NO_AP(ctx); \
5995 gen_addr_reg_index(ctx); \
5996 op_spe_ldst(spe_l##name); \
5997 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
6000 #define GEN_SPEOP_LD(name, sh) \
6001 OP_SPE_LD_TABLE(name); \
6002 GEN_SPE_LD(name, sh); \
6005 #define GEN_SPE_ST(name, sh) \
6006 static always_inline void gen_evst##name (DisasContext *ctx) \
6008 if (unlikely(!ctx->spe_enabled)) { \
6009 GEN_EXCP_NO_AP(ctx); \
6012 gen_addr_spe_imm_index(ctx, sh); \
6013 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
6014 op_spe_ldst(spe_st##name); \
6017 #define GEN_SPE_STX(name) \
6018 static always_inline void gen_evst##name##x (DisasContext *ctx) \
6020 if (unlikely(!ctx->spe_enabled)) { \
6021 GEN_EXCP_NO_AP(ctx); \
6024 gen_addr_reg_index(ctx); \
6025 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
6026 op_spe_ldst(spe_st##name); \
6029 #define GEN_SPEOP_ST(name, sh) \
6030 OP_SPE_ST_TABLE(name); \
6031 GEN_SPE_ST(name, sh); \
6034 #define GEN_SPEOP_LDST(name, sh) \
6035 GEN_SPEOP_LD(name, sh); \
6036 GEN_SPEOP_ST(name, sh)
6038 /* SPE arithmetic and logic */
6039 #define GEN_SPEOP_ARITH2(name) \
6040 static always_inline void gen_##name (DisasContext *ctx) \
6042 if (unlikely(!ctx->spe_enabled)) { \
6043 GEN_EXCP_NO_AP(ctx); \
6046 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6047 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
6049 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6052 #define GEN_SPEOP_ARITH1(name) \
6053 static always_inline void gen_##name (DisasContext *ctx) \
6055 if (unlikely(!ctx->spe_enabled)) { \
6056 GEN_EXCP_NO_AP(ctx); \
6059 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6061 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6064 #define GEN_SPEOP_COMP(name) \
6065 static always_inline void gen_##name (DisasContext *ctx) \
6067 if (unlikely(!ctx->spe_enabled)) { \
6068 GEN_EXCP_NO_AP(ctx); \
6071 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6072 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
6074 gen_op_store_T0_crf(crfD(ctx->opcode)); \
6078 GEN_SPEOP_ARITH2(evand
);
6079 GEN_SPEOP_ARITH2(evandc
);
6080 GEN_SPEOP_ARITH2(evxor
);
6081 GEN_SPEOP_ARITH2(evor
);
6082 GEN_SPEOP_ARITH2(evnor
);
6083 GEN_SPEOP_ARITH2(eveqv
);
6084 GEN_SPEOP_ARITH2(evorc
);
6085 GEN_SPEOP_ARITH2(evnand
);
6086 GEN_SPEOP_ARITH2(evsrwu
);
6087 GEN_SPEOP_ARITH2(evsrws
);
6088 GEN_SPEOP_ARITH2(evslw
);
6089 GEN_SPEOP_ARITH2(evrlw
);
6090 GEN_SPEOP_ARITH2(evmergehi
);
6091 GEN_SPEOP_ARITH2(evmergelo
);
6092 GEN_SPEOP_ARITH2(evmergehilo
);
6093 GEN_SPEOP_ARITH2(evmergelohi
);
6096 GEN_SPEOP_ARITH2(evaddw
);
6097 GEN_SPEOP_ARITH2(evsubfw
);
6098 GEN_SPEOP_ARITH1(evabs
);
6099 GEN_SPEOP_ARITH1(evneg
);
6100 GEN_SPEOP_ARITH1(evextsb
);
6101 GEN_SPEOP_ARITH1(evextsh
);
6102 GEN_SPEOP_ARITH1(evrndw
);
6103 GEN_SPEOP_ARITH1(evcntlzw
);
6104 GEN_SPEOP_ARITH1(evcntlsw
);
6105 static always_inline
void gen_brinc (DisasContext
*ctx
)
6107 /* Note: brinc is usable even if SPE is disabled */
6108 gen_op_load_gpr64_T0(rA(ctx
->opcode
));
6109 gen_op_load_gpr64_T1(rB(ctx
->opcode
));
6111 gen_op_store_T0_gpr64(rD(ctx
->opcode
));
6114 #define GEN_SPEOP_ARITH_IMM2(name) \
6115 static always_inline void gen_##name##i (DisasContext *ctx) \
6117 if (unlikely(!ctx->spe_enabled)) { \
6118 GEN_EXCP_NO_AP(ctx); \
6121 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
6122 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
6124 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6127 #define GEN_SPEOP_LOGIC_IMM2(name) \
6128 static always_inline void gen_##name##i (DisasContext *ctx) \
6130 if (unlikely(!ctx->spe_enabled)) { \
6131 GEN_EXCP_NO_AP(ctx); \
6134 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6135 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
6137 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6140 GEN_SPEOP_ARITH_IMM2(evaddw
);
6141 #define gen_evaddiw gen_evaddwi
6142 GEN_SPEOP_ARITH_IMM2(evsubfw
);
6143 #define gen_evsubifw gen_evsubfwi
6144 GEN_SPEOP_LOGIC_IMM2(evslw
);
6145 GEN_SPEOP_LOGIC_IMM2(evsrwu
);
6146 #define gen_evsrwis gen_evsrwsi
6147 GEN_SPEOP_LOGIC_IMM2(evsrws
);
6148 #define gen_evsrwiu gen_evsrwui
6149 GEN_SPEOP_LOGIC_IMM2(evrlw
);
6151 static always_inline
void gen_evsplati (DisasContext
*ctx
)
6153 int32_t imm
= (int32_t)(rA(ctx
->opcode
) << 27) >> 27;
6155 gen_op_splatwi_T0_64(imm
);
6156 gen_op_store_T0_gpr64(rD(ctx
->opcode
));
6159 static always_inline
void gen_evsplatfi (DisasContext
*ctx
)
6161 uint32_t imm
= rA(ctx
->opcode
) << 27;
6163 gen_op_splatwi_T0_64(imm
);
6164 gen_op_store_T0_gpr64(rD(ctx
->opcode
));
6168 GEN_SPEOP_COMP(evcmpgtu
);
6169 GEN_SPEOP_COMP(evcmpgts
);
6170 GEN_SPEOP_COMP(evcmpltu
);
6171 GEN_SPEOP_COMP(evcmplts
);
6172 GEN_SPEOP_COMP(evcmpeq
);
6174 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, PPC_SPE
); ////
6175 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, PPC_SPE
);
6176 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, PPC_SPE
); ////
6177 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, PPC_SPE
);
6178 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, PPC_SPE
); ////
6179 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, PPC_SPE
); ////
6180 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, PPC_SPE
); ////
6181 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x00000000, PPC_SPE
); //
6182 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0x00000000, PPC_SPE
); ////
6183 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, PPC_SPE
); ////
6184 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, PPC_SPE
); ////
6185 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, PPC_SPE
); ////
6186 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0x00000000, PPC_SPE
); ////
6187 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, PPC_SPE
); ////
6188 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, PPC_SPE
); ////
6189 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, PPC_SPE
);
6190 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, PPC_SPE
); ////
6191 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, PPC_SPE
);
6192 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, PPC_SPE
); //
6193 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, PPC_SPE
);
6194 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, PPC_SPE
); ////
6195 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, PPC_SPE
); ////
6196 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, PPC_SPE
); ////
6197 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, PPC_SPE
); ////
6198 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, PPC_SPE
); ////
6200 static always_inline
void gen_evsel (DisasContext
*ctx
)
6202 if (unlikely(!ctx
->spe_enabled
)) {
6203 GEN_EXCP_NO_AP(ctx
);
6206 gen_op_load_crf_T0(ctx
->opcode
& 0x7);
6207 gen_op_load_gpr64_T0(rA(ctx
->opcode
));
6208 gen_op_load_gpr64_T1(rB(ctx
->opcode
));
6210 gen_op_store_T0_gpr64(rD(ctx
->opcode
));
6213 GEN_HANDLER2(evsel0
, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE
)
6217 GEN_HANDLER2(evsel1
, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE
)
6221 GEN_HANDLER2(evsel2
, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE
)
6225 GEN_HANDLER2(evsel3
, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE
)
6230 /* Load and stores */
6231 #if defined(TARGET_PPC64)
6232 /* In that case, we already have 64 bits load & stores
6233 * so, spe_ldd is equivalent to ld and spe_std is equivalent to std
6235 #if defined(CONFIG_USER_ONLY)
6236 #define gen_op_spe_ldd_raw gen_op_ld_raw
6237 #define gen_op_spe_ldd_64_raw gen_op_ld_64_raw
6238 #define gen_op_spe_ldd_le_raw gen_op_ld_le_raw
6239 #define gen_op_spe_ldd_le_64_raw gen_op_ld_le_64_raw
6240 #define gen_op_spe_stdd_raw gen_op_ld_raw
6241 #define gen_op_spe_stdd_64_raw gen_op_std_64_raw
6242 #define gen_op_spe_stdd_le_raw gen_op_std_le_raw
6243 #define gen_op_spe_stdd_le_64_raw gen_op_std_le_64_raw
6244 #else /* defined(CONFIG_USER_ONLY) */
6245 #define gen_op_spe_ldd_kernel gen_op_ld_kernel
6246 #define gen_op_spe_ldd_64_kernel gen_op_ld_64_kernel
6247 #define gen_op_spe_ldd_le_kernel gen_op_ld_kernel
6248 #define gen_op_spe_ldd_le_64_kernel gen_op_ld_64_kernel
6249 #define gen_op_spe_ldd_user gen_op_ld_user
6250 #define gen_op_spe_ldd_64_user gen_op_ld_64_user
6251 #define gen_op_spe_ldd_le_user gen_op_ld_le_user
6252 #define gen_op_spe_ldd_le_64_user gen_op_ld_le_64_user
6253 #define gen_op_spe_stdd_kernel gen_op_std_kernel
6254 #define gen_op_spe_stdd_64_kernel gen_op_std_64_kernel
6255 #define gen_op_spe_stdd_le_kernel gen_op_std_kernel
6256 #define gen_op_spe_stdd_le_64_kernel gen_op_std_64_kernel
6257 #define gen_op_spe_stdd_user gen_op_std_user
6258 #define gen_op_spe_stdd_64_user gen_op_std_64_user
6259 #define gen_op_spe_stdd_le_user gen_op_std_le_user
6260 #define gen_op_spe_stdd_le_64_user gen_op_std_le_64_user
6261 #endif /* defined(CONFIG_USER_ONLY) */
6262 #endif /* defined(TARGET_PPC64) */
6263 GEN_SPEOP_LDST(dd
, 3);
6264 GEN_SPEOP_LDST(dw
, 3);
6265 GEN_SPEOP_LDST(dh
, 3);
6266 GEN_SPEOP_LDST(whe
, 2);
6267 GEN_SPEOP_LD(whou
, 2);
6268 GEN_SPEOP_LD(whos
, 2);
6269 GEN_SPEOP_ST(who
, 2);
6271 #if defined(TARGET_PPC64)
6272 /* In that case, spe_stwwo is equivalent to stw */
6273 #if defined(CONFIG_USER_ONLY)
6274 #define gen_op_spe_stwwo_raw gen_op_stw_raw
6275 #define gen_op_spe_stwwo_le_raw gen_op_stw_le_raw
6276 #define gen_op_spe_stwwo_64_raw gen_op_stw_64_raw
6277 #define gen_op_spe_stwwo_le_64_raw gen_op_stw_le_64_raw
6279 #define gen_op_spe_stwwo_user gen_op_stw_user
6280 #define gen_op_spe_stwwo_le_user gen_op_stw_le_user
6281 #define gen_op_spe_stwwo_64_user gen_op_stw_64_user
6282 #define gen_op_spe_stwwo_le_64_user gen_op_stw_le_64_user
6283 #define gen_op_spe_stwwo_kernel gen_op_stw_kernel
6284 #define gen_op_spe_stwwo_le_kernel gen_op_stw_le_kernel
6285 #define gen_op_spe_stwwo_64_kernel gen_op_stw_64_kernel
6286 #define gen_op_spe_stwwo_le_64_kernel gen_op_stw_le_64_kernel
6289 #define _GEN_OP_SPE_STWWE(suffix) \
6290 static always_inline void gen_op_spe_stwwe_##suffix (void) \
6292 gen_op_srli32_T1_64(); \
6293 gen_op_spe_stwwo_##suffix(); \
6295 #define _GEN_OP_SPE_STWWE_LE(suffix) \
6296 static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
6298 gen_op_srli32_T1_64(); \
6299 gen_op_spe_stwwo_le_##suffix(); \
6301 #if defined(TARGET_PPC64)
6302 #define GEN_OP_SPE_STWWE(suffix) \
6303 _GEN_OP_SPE_STWWE(suffix); \
6304 _GEN_OP_SPE_STWWE_LE(suffix); \
6305 static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
6307 gen_op_srli32_T1_64(); \
6308 gen_op_spe_stwwo_64_##suffix(); \
6310 static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
6312 gen_op_srli32_T1_64(); \
6313 gen_op_spe_stwwo_le_64_##suffix(); \
6316 #define GEN_OP_SPE_STWWE(suffix) \
6317 _GEN_OP_SPE_STWWE(suffix); \
6318 _GEN_OP_SPE_STWWE_LE(suffix)
6320 #if defined(CONFIG_USER_ONLY)
6321 GEN_OP_SPE_STWWE(raw
);
6322 #else /* defined(CONFIG_USER_ONLY) */
6323 GEN_OP_SPE_STWWE(kernel
);
6324 GEN_OP_SPE_STWWE(user
);
6325 #endif /* defined(CONFIG_USER_ONLY) */
6326 GEN_SPEOP_ST(wwe
, 2);
6327 GEN_SPEOP_ST(wwo
, 2);
6329 #define GEN_SPE_LDSPLAT(name, op, suffix) \
6330 static always_inline void gen_op_spe_l##name##_##suffix (void) \
6332 gen_op_##op##_##suffix(); \
6333 gen_op_splatw_T1_64(); \
6336 #define GEN_OP_SPE_LHE(suffix) \
6337 static always_inline void gen_op_spe_lhe_##suffix (void) \
6339 gen_op_spe_lh_##suffix(); \
6340 gen_op_sli16_T1_64(); \
6343 #define GEN_OP_SPE_LHX(suffix) \
6344 static always_inline void gen_op_spe_lhx_##suffix (void) \
6346 gen_op_spe_lh_##suffix(); \
6347 gen_op_extsh_T1_64(); \
6350 #if defined(CONFIG_USER_ONLY)
6351 GEN_OP_SPE_LHE(raw
);
6352 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, raw
);
6353 GEN_OP_SPE_LHE(le_raw
);
6354 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_raw
);
6355 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, raw
);
6356 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_raw
);
6357 GEN_OP_SPE_LHX(raw
);
6358 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, raw
);
6359 GEN_OP_SPE_LHX(le_raw
);
6360 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_raw
);
6361 #if defined(TARGET_PPC64)
6362 GEN_OP_SPE_LHE(64_raw
);
6363 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, 64_raw
);
6364 GEN_OP_SPE_LHE(le_64_raw
);
6365 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_64_raw
);
6366 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, 64_raw
);
6367 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_64_raw
);
6368 GEN_OP_SPE_LHX(64_raw
);
6369 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, 64_raw
);
6370 GEN_OP_SPE_LHX(le_64_raw
);
6371 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_64_raw
);
6374 GEN_OP_SPE_LHE(kernel
);
6375 GEN_OP_SPE_LHE(user
);
6376 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, kernel
);
6377 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, user
);
6378 GEN_OP_SPE_LHE(le_kernel
);
6379 GEN_OP_SPE_LHE(le_user
);
6380 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_kernel
);
6381 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_user
);
6382 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, kernel
);
6383 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, user
);
6384 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_kernel
);
6385 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_user
);
6386 GEN_OP_SPE_LHX(kernel
);
6387 GEN_OP_SPE_LHX(user
);
6388 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, kernel
);
6389 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, user
);
6390 GEN_OP_SPE_LHX(le_kernel
);
6391 GEN_OP_SPE_LHX(le_user
);
6392 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_kernel
);
6393 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_user
);
6394 #if defined(TARGET_PPC64)
6395 GEN_OP_SPE_LHE(64_kernel
);
6396 GEN_OP_SPE_LHE(64_user
);
6397 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, 64_kernel
);
6398 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, 64_user
);
6399 GEN_OP_SPE_LHE(le_64_kernel
);
6400 GEN_OP_SPE_LHE(le_64_user
);
6401 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_64_kernel
);
6402 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_64_user
);
6403 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, 64_kernel
);
6404 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, 64_user
);
6405 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_64_kernel
);
6406 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_64_user
);
6407 GEN_OP_SPE_LHX(64_kernel
);
6408 GEN_OP_SPE_LHX(64_user
);
6409 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, 64_kernel
);
6410 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, 64_user
);
6411 GEN_OP_SPE_LHX(le_64_kernel
);
6412 GEN_OP_SPE_LHX(le_64_user
);
6413 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_64_kernel
);
6414 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_64_user
);
6417 GEN_SPEOP_LD(hhesplat
, 1);
6418 GEN_SPEOP_LD(hhousplat
, 1);
6419 GEN_SPEOP_LD(hhossplat
, 1);
6420 GEN_SPEOP_LD(wwsplat
, 2);
6421 GEN_SPEOP_LD(whsplat
, 2);
6423 GEN_SPE(evlddx
, evldd
, 0x00, 0x0C, 0x00000000, PPC_SPE
); //
6424 GEN_SPE(evldwx
, evldw
, 0x01, 0x0C, 0x00000000, PPC_SPE
); //
6425 GEN_SPE(evldhx
, evldh
, 0x02, 0x0C, 0x00000000, PPC_SPE
); //
6426 GEN_SPE(evlhhesplatx
, evlhhesplat
, 0x04, 0x0C, 0x00000000, PPC_SPE
); //
6427 GEN_SPE(evlhhousplatx
, evlhhousplat
, 0x06, 0x0C, 0x00000000, PPC_SPE
); //
6428 GEN_SPE(evlhhossplatx
, evlhhossplat
, 0x07, 0x0C, 0x00000000, PPC_SPE
); //
6429 GEN_SPE(evlwhex
, evlwhe
, 0x08, 0x0C, 0x00000000, PPC_SPE
); //
6430 GEN_SPE(evlwhoux
, evlwhou
, 0x0A, 0x0C, 0x00000000, PPC_SPE
); //
6431 GEN_SPE(evlwhosx
, evlwhos
, 0x0B, 0x0C, 0x00000000, PPC_SPE
); //
6432 GEN_SPE(evlwwsplatx
, evlwwsplat
, 0x0C, 0x0C, 0x00000000, PPC_SPE
); //
6433 GEN_SPE(evlwhsplatx
, evlwhsplat
, 0x0E, 0x0C, 0x00000000, PPC_SPE
); //
6434 GEN_SPE(evstddx
, evstdd
, 0x10, 0x0C, 0x00000000, PPC_SPE
); //
6435 GEN_SPE(evstdwx
, evstdw
, 0x11, 0x0C, 0x00000000, PPC_SPE
); //
6436 GEN_SPE(evstdhx
, evstdh
, 0x12, 0x0C, 0x00000000, PPC_SPE
); //
6437 GEN_SPE(evstwhex
, evstwhe
, 0x18, 0x0C, 0x00000000, PPC_SPE
); //
6438 GEN_SPE(evstwhox
, evstwho
, 0x1A, 0x0C, 0x00000000, PPC_SPE
); //
6439 GEN_SPE(evstwwex
, evstwwe
, 0x1C, 0x0C, 0x00000000, PPC_SPE
); //
6440 GEN_SPE(evstwwox
, evstwwo
, 0x1E, 0x0C, 0x00000000, PPC_SPE
); //
6442 /* Multiply and add - TODO */
6444 GEN_SPE(speundef
, evmhessf
, 0x01, 0x10, 0x00000000, PPC_SPE
);
6445 GEN_SPE(speundef
, evmhossf
, 0x03, 0x10, 0x00000000, PPC_SPE
);
6446 GEN_SPE(evmheumi
, evmhesmi
, 0x04, 0x10, 0x00000000, PPC_SPE
);
6447 GEN_SPE(speundef
, evmhesmf
, 0x05, 0x10, 0x00000000, PPC_SPE
);
6448 GEN_SPE(evmhoumi
, evmhosmi
, 0x06, 0x10, 0x00000000, PPC_SPE
);
6449 GEN_SPE(speundef
, evmhosmf
, 0x07, 0x10, 0x00000000, PPC_SPE
);
6450 GEN_SPE(speundef
, evmhessfa
, 0x11, 0x10, 0x00000000, PPC_SPE
);
6451 GEN_SPE(speundef
, evmhossfa
, 0x13, 0x10, 0x00000000, PPC_SPE
);
6452 GEN_SPE(evmheumia
, evmhesmia
, 0x14, 0x10, 0x00000000, PPC_SPE
);
6453 GEN_SPE(speundef
, evmhesmfa
, 0x15, 0x10, 0x00000000, PPC_SPE
);
6454 GEN_SPE(evmhoumia
, evmhosmia
, 0x16, 0x10, 0x00000000, PPC_SPE
);
6455 GEN_SPE(speundef
, evmhosmfa
, 0x17, 0x10, 0x00000000, PPC_SPE
);
6457 GEN_SPE(speundef
, evmwhssf
, 0x03, 0x11, 0x00000000, PPC_SPE
);
6458 GEN_SPE(evmwlumi
, speundef
, 0x04, 0x11, 0x00000000, PPC_SPE
);
6459 GEN_SPE(evmwhumi
, evmwhsmi
, 0x06, 0x11, 0x00000000, PPC_SPE
);
6460 GEN_SPE(speundef
, evmwhsmf
, 0x07, 0x11, 0x00000000, PPC_SPE
);
6461 GEN_SPE(speundef
, evmwssf
, 0x09, 0x11, 0x00000000, PPC_SPE
);
6462 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, PPC_SPE
);
6463 GEN_SPE(speundef
, evmwsmf
, 0x0D, 0x11, 0x00000000, PPC_SPE
);
6464 GEN_SPE(speundef
, evmwhssfa
, 0x13, 0x11, 0x00000000, PPC_SPE
);
6465 GEN_SPE(evmwlumia
, speundef
, 0x14, 0x11, 0x00000000, PPC_SPE
);
6466 GEN_SPE(evmwhumia
, evmwhsmia
, 0x16, 0x11, 0x00000000, PPC_SPE
);
6467 GEN_SPE(speundef
, evmwhsmfa
, 0x17, 0x11, 0x00000000, PPC_SPE
);
6468 GEN_SPE(speundef
, evmwssfa
, 0x19, 0x11, 0x00000000, PPC_SPE
);
6469 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, PPC_SPE
);
6470 GEN_SPE(speundef
, evmwsmfa
, 0x1D, 0x11, 0x00000000, PPC_SPE
);
6472 GEN_SPE(evadduiaaw
, evaddsiaaw
, 0x00, 0x13, 0x0000F800, PPC_SPE
);
6473 GEN_SPE(evsubfusiaaw
, evsubfssiaaw
, 0x01, 0x13, 0x0000F800, PPC_SPE
);
6474 GEN_SPE(evaddumiaaw
, evaddsmiaaw
, 0x04, 0x13, 0x0000F800, PPC_SPE
);
6475 GEN_SPE(evsubfumiaaw
, evsubfsmiaaw
, 0x05, 0x13, 0x0000F800, PPC_SPE
);
6476 GEN_SPE(evdivws
, evdivwu
, 0x06, 0x13, 0x00000000, PPC_SPE
);
6477 GEN_SPE(evmra
, speundef
, 0x07, 0x13, 0x0000F800, PPC_SPE
);
6479 GEN_SPE(evmheusiaaw
, evmhessiaaw
, 0x00, 0x14, 0x00000000, PPC_SPE
);
6480 GEN_SPE(speundef
, evmhessfaaw
, 0x01, 0x14, 0x00000000, PPC_SPE
);
6481 GEN_SPE(evmhousiaaw
, evmhossiaaw
, 0x02, 0x14, 0x00000000, PPC_SPE
);
6482 GEN_SPE(speundef
, evmhossfaaw
, 0x03, 0x14, 0x00000000, PPC_SPE
);
6483 GEN_SPE(evmheumiaaw
, evmhesmiaaw
, 0x04, 0x14, 0x00000000, PPC_SPE
);
6484 GEN_SPE(speundef
, evmhesmfaaw
, 0x05, 0x14, 0x00000000, PPC_SPE
);
6485 GEN_SPE(evmhoumiaaw
, evmhosmiaaw
, 0x06, 0x14, 0x00000000, PPC_SPE
);
6486 GEN_SPE(speundef
, evmhosmfaaw
, 0x07, 0x14, 0x00000000, PPC_SPE
);
6487 GEN_SPE(evmhegumiaa
, evmhegsmiaa
, 0x14, 0x14, 0x00000000, PPC_SPE
);
6488 GEN_SPE(speundef
, evmhegsmfaa
, 0x15, 0x14, 0x00000000, PPC_SPE
);
6489 GEN_SPE(evmhogumiaa
, evmhogsmiaa
, 0x16, 0x14, 0x00000000, PPC_SPE
);
6490 GEN_SPE(speundef
, evmhogsmfaa
, 0x17, 0x14, 0x00000000, PPC_SPE
);
6492 GEN_SPE(evmwlusiaaw
, evmwlssiaaw
, 0x00, 0x15, 0x00000000, PPC_SPE
);
6493 GEN_SPE(evmwlumiaaw
, evmwlsmiaaw
, 0x04, 0x15, 0x00000000, PPC_SPE
);
6494 GEN_SPE(speundef
, evmwssfaa
, 0x09, 0x15, 0x00000000, PPC_SPE
);
6495 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, PPC_SPE
);
6496 GEN_SPE(speundef
, evmwsmfaa
, 0x0D, 0x15, 0x00000000, PPC_SPE
);
6498 GEN_SPE(evmheusianw
, evmhessianw
, 0x00, 0x16, 0x00000000, PPC_SPE
);
6499 GEN_SPE(speundef
, evmhessfanw
, 0x01, 0x16, 0x00000000, PPC_SPE
);
6500 GEN_SPE(evmhousianw
, evmhossianw
, 0x02, 0x16, 0x00000000, PPC_SPE
);
6501 GEN_SPE(speundef
, evmhossfanw
, 0x03, 0x16, 0x00000000, PPC_SPE
);
6502 GEN_SPE(evmheumianw
, evmhesmianw
, 0x04, 0x16, 0x00000000, PPC_SPE
);
6503 GEN_SPE(speundef
, evmhesmfanw
, 0x05, 0x16, 0x00000000, PPC_SPE
);
6504 GEN_SPE(evmhoumianw
, evmhosmianw
, 0x06, 0x16, 0x00000000, PPC_SPE
);
6505 GEN_SPE(speundef
, evmhosmfanw
, 0x07, 0x16, 0x00000000, PPC_SPE
);
6506 GEN_SPE(evmhegumian
, evmhegsmian
, 0x14, 0x16, 0x00000000, PPC_SPE
);
6507 GEN_SPE(speundef
, evmhegsmfan
, 0x15, 0x16, 0x00000000, PPC_SPE
);
6508 GEN_SPE(evmhigumian
, evmhigsmian
, 0x16, 0x16, 0x00000000, PPC_SPE
);
6509 GEN_SPE(speundef
, evmhogsmfan
, 0x17, 0x16, 0x00000000, PPC_SPE
);
6511 GEN_SPE(evmwlusianw
, evmwlssianw
, 0x00, 0x17, 0x00000000, PPC_SPE
);
6512 GEN_SPE(evmwlumianw
, evmwlsmianw
, 0x04, 0x17, 0x00000000, PPC_SPE
);
6513 GEN_SPE(speundef
, evmwssfan
, 0x09, 0x17, 0x00000000, PPC_SPE
);
6514 GEN_SPE(evmwumian
, evmwsmian
, 0x0C, 0x17, 0x00000000, PPC_SPE
);
6515 GEN_SPE(speundef
, evmwsmfan
, 0x0D, 0x17, 0x00000000, PPC_SPE
);
6518 /*** SPE floating-point extension ***/
6519 #define GEN_SPEFPUOP_CONV(name) \
6520 static always_inline void gen_##name (DisasContext *ctx) \
6522 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
6524 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6527 /* Single precision floating-point vectors operations */
6529 GEN_SPEOP_ARITH2(evfsadd
);
6530 GEN_SPEOP_ARITH2(evfssub
);
6531 GEN_SPEOP_ARITH2(evfsmul
);
6532 GEN_SPEOP_ARITH2(evfsdiv
);
6533 GEN_SPEOP_ARITH1(evfsabs
);
6534 GEN_SPEOP_ARITH1(evfsnabs
);
6535 GEN_SPEOP_ARITH1(evfsneg
);
6537 GEN_SPEFPUOP_CONV(evfscfui
);
6538 GEN_SPEFPUOP_CONV(evfscfsi
);
6539 GEN_SPEFPUOP_CONV(evfscfuf
);
6540 GEN_SPEFPUOP_CONV(evfscfsf
);
6541 GEN_SPEFPUOP_CONV(evfsctui
);
6542 GEN_SPEFPUOP_CONV(evfsctsi
);
6543 GEN_SPEFPUOP_CONV(evfsctuf
);
6544 GEN_SPEFPUOP_CONV(evfsctsf
);
6545 GEN_SPEFPUOP_CONV(evfsctuiz
);
6546 GEN_SPEFPUOP_CONV(evfsctsiz
);
6548 GEN_SPEOP_COMP(evfscmpgt
);
6549 GEN_SPEOP_COMP(evfscmplt
);
6550 GEN_SPEOP_COMP(evfscmpeq
);
6551 GEN_SPEOP_COMP(evfststgt
);
6552 GEN_SPEOP_COMP(evfststlt
);
6553 GEN_SPEOP_COMP(evfststeq
);
6555 /* Opcodes definitions */
6556 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, PPC_SPEFPU
); //
6557 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU
); //
6558 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU
); //
6559 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, PPC_SPEFPU
); //
6560 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, PPC_SPEFPU
); //
6561 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, PPC_SPEFPU
); //
6562 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, PPC_SPEFPU
); //
6563 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, PPC_SPEFPU
); //
6564 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU
); //
6565 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU
); //
6566 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU
); //
6567 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU
); //
6568 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU
); //
6569 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU
); //
6571 /* Single precision floating-point operations */
6573 GEN_SPEOP_ARITH2(efsadd
);
6574 GEN_SPEOP_ARITH2(efssub
);
6575 GEN_SPEOP_ARITH2(efsmul
);
6576 GEN_SPEOP_ARITH2(efsdiv
);
6577 GEN_SPEOP_ARITH1(efsabs
);
6578 GEN_SPEOP_ARITH1(efsnabs
);
6579 GEN_SPEOP_ARITH1(efsneg
);
6581 GEN_SPEFPUOP_CONV(efscfui
);
6582 GEN_SPEFPUOP_CONV(efscfsi
);
6583 GEN_SPEFPUOP_CONV(efscfuf
);
6584 GEN_SPEFPUOP_CONV(efscfsf
);
6585 GEN_SPEFPUOP_CONV(efsctui
);
6586 GEN_SPEFPUOP_CONV(efsctsi
);
6587 GEN_SPEFPUOP_CONV(efsctuf
);
6588 GEN_SPEFPUOP_CONV(efsctsf
);
6589 GEN_SPEFPUOP_CONV(efsctuiz
);
6590 GEN_SPEFPUOP_CONV(efsctsiz
);
6591 GEN_SPEFPUOP_CONV(efscfd
);
6593 GEN_SPEOP_COMP(efscmpgt
);
6594 GEN_SPEOP_COMP(efscmplt
);
6595 GEN_SPEOP_COMP(efscmpeq
);
6596 GEN_SPEOP_COMP(efststgt
);
6597 GEN_SPEOP_COMP(efststlt
);
6598 GEN_SPEOP_COMP(efststeq
);
6600 /* Opcodes definitions */
6601 GEN_SPE(efsadd
, efssub
, 0x00, 0x0A, 0x00000000, PPC_SPEFPU
); //
6602 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU
); //
6603 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU
); //
6604 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, PPC_SPEFPU
); //
6605 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, PPC_SPEFPU
); //
6606 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, PPC_SPEFPU
); //
6607 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, PPC_SPEFPU
); //
6608 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, PPC_SPEFPU
); //
6609 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU
); //
6610 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU
); //
6611 GEN_SPE(efsctuiz
, efsctsiz
, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU
); //
6612 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU
); //
6613 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU
); //
6615 /* Double precision floating-point operations */
6617 GEN_SPEOP_ARITH2(efdadd
);
6618 GEN_SPEOP_ARITH2(efdsub
);
6619 GEN_SPEOP_ARITH2(efdmul
);
6620 GEN_SPEOP_ARITH2(efddiv
);
6621 GEN_SPEOP_ARITH1(efdabs
);
6622 GEN_SPEOP_ARITH1(efdnabs
);
6623 GEN_SPEOP_ARITH1(efdneg
);
6626 GEN_SPEFPUOP_CONV(efdcfui
);
6627 GEN_SPEFPUOP_CONV(efdcfsi
);
6628 GEN_SPEFPUOP_CONV(efdcfuf
);
6629 GEN_SPEFPUOP_CONV(efdcfsf
);
6630 GEN_SPEFPUOP_CONV(efdctui
);
6631 GEN_SPEFPUOP_CONV(efdctsi
);
6632 GEN_SPEFPUOP_CONV(efdctuf
);
6633 GEN_SPEFPUOP_CONV(efdctsf
);
6634 GEN_SPEFPUOP_CONV(efdctuiz
);
6635 GEN_SPEFPUOP_CONV(efdctsiz
);
6636 GEN_SPEFPUOP_CONV(efdcfs
);
6637 GEN_SPEFPUOP_CONV(efdcfuid
);
6638 GEN_SPEFPUOP_CONV(efdcfsid
);
6639 GEN_SPEFPUOP_CONV(efdctuidz
);
6640 GEN_SPEFPUOP_CONV(efdctsidz
);
6642 GEN_SPEOP_COMP(efdcmpgt
);
6643 GEN_SPEOP_COMP(efdcmplt
);
6644 GEN_SPEOP_COMP(efdcmpeq
);
6645 GEN_SPEOP_COMP(efdtstgt
);
6646 GEN_SPEOP_COMP(efdtstlt
);
6647 GEN_SPEOP_COMP(efdtsteq
);
6649 /* Opcodes definitions */
6650 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, PPC_SPEFPU
); //
6651 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, PPC_SPEFPU
); //
6652 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU
); //
6653 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU
); //
6654 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, PPC_SPEFPU
); //
6655 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, PPC_SPEFPU
); //
6656 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, PPC_SPEFPU
); //
6657 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, PPC_SPEFPU
); //
6658 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, PPC_SPEFPU
); //
6659 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, PPC_SPEFPU
); //
6660 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU
); //
6661 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU
); //
6662 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU
); //
6663 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU
); //
6664 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU
); //
6665 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU
); //
6668 /* End opcode list */
6669 GEN_OPCODE_MARK(end
);
6671 #include "translate_init.c"
6672 #include "helper_regs.h"
6674 /*****************************************************************************/
6675 /* Misc PowerPC helpers */
6676 void cpu_dump_state (CPUState
*env
, FILE *f
,
6677 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
6680 #if defined(TARGET_PPC64) || 1
6692 cpu_fprintf(f
, "NIP " ADDRX
" LR " ADDRX
" CTR " ADDRX
" XER %08x\n",
6693 env
->nip
, env
->lr
, env
->ctr
, hreg_load_xer(env
));
6694 cpu_fprintf(f
, "MSR " REGX FILL
" HID0 " REGX FILL
" HF " REGX FILL
6696 env
->msr
, env
->hflags
, env
->spr
[SPR_HID0
], env
->mmu_idx
);
6697 #if !defined(NO_TIMER_DUMP)
6698 cpu_fprintf(f
, "TB %08x %08x "
6699 #if !defined(CONFIG_USER_ONLY)
6703 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
6704 #if !defined(CONFIG_USER_ONLY)
6705 , cpu_ppc_load_decr(env
)
6709 for (i
= 0; i
< 32; i
++) {
6710 if ((i
& (RGPL
- 1)) == 0)
6711 cpu_fprintf(f
, "GPR%02d", i
);
6712 cpu_fprintf(f
, " " REGX
, (target_ulong
)env
->gpr
[i
]);
6713 if ((i
& (RGPL
- 1)) == (RGPL
- 1))
6714 cpu_fprintf(f
, "\n");
6716 cpu_fprintf(f
, "CR ");
6717 for (i
= 0; i
< 8; i
++)
6718 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
6719 cpu_fprintf(f
, " [");
6720 for (i
= 0; i
< 8; i
++) {
6722 if (env
->crf
[i
] & 0x08)
6724 else if (env
->crf
[i
] & 0x04)
6726 else if (env
->crf
[i
] & 0x02)
6728 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
6730 cpu_fprintf(f
, " ] " FILL
"RES " REGX
"\n", env
->reserve
);
6731 for (i
= 0; i
< 32; i
++) {
6732 if ((i
& (RFPL
- 1)) == 0)
6733 cpu_fprintf(f
, "FPR%02d", i
);
6734 cpu_fprintf(f
, " %016" PRIx64
, *((uint64_t *)&env
->fpr
[i
]));
6735 if ((i
& (RFPL
- 1)) == (RFPL
- 1))
6736 cpu_fprintf(f
, "\n");
6738 #if !defined(CONFIG_USER_ONLY)
6739 cpu_fprintf(f
, "SRR0 " REGX
" SRR1 " REGX
" SDR1 " REGX
"\n",
6740 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
], env
->sdr1
);
6748 void cpu_dump_statistics (CPUState
*env
, FILE*f
,
6749 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
6752 #if defined(DO_PPC_STATISTICS)
6753 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
6757 for (op1
= 0; op1
< 64; op1
++) {
6759 if (is_indirect_opcode(handler
)) {
6760 t2
= ind_table(handler
);
6761 for (op2
= 0; op2
< 32; op2
++) {
6763 if (is_indirect_opcode(handler
)) {
6764 t3
= ind_table(handler
);
6765 for (op3
= 0; op3
< 32; op3
++) {
6767 if (handler
->count
== 0)
6769 cpu_fprintf(f
, "%02x %02x %02x (%02x %04d) %16s: "
6771 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
6773 handler
->count
, handler
->count
);
6776 if (handler
->count
== 0)
6778 cpu_fprintf(f
, "%02x %02x (%02x %04d) %16s: "
6780 op1
, op2
, op1
, op2
, handler
->oname
,
6781 handler
->count
, handler
->count
);
6785 if (handler
->count
== 0)
6787 cpu_fprintf(f
, "%02x (%02x ) %16s: %016llx %lld\n",
6788 op1
, op1
, handler
->oname
,
6789 handler
->count
, handler
->count
);
6795 /*****************************************************************************/
6796 static always_inline
int gen_intermediate_code_internal (CPUState
*env
,
6797 TranslationBlock
*tb
,
6800 DisasContext ctx
, *ctxp
= &ctx
;
6801 opc_handler_t
**table
, *handler
;
6802 target_ulong pc_start
;
6803 uint16_t *gen_opc_end
;
6805 int single_step
, branch_step
;
6809 gen_opc_ptr
= gen_opc_buf
;
6810 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
6811 gen_opparam_ptr
= gen_opparam_buf
;
6812 #if defined(OPTIMIZE_FPRF_UPDATE)
6813 gen_fprf_ptr
= gen_fprf_buf
;
6818 ctx
.exception
= POWERPC_EXCP_NONE
;
6819 ctx
.spr_cb
= env
->spr_cb
;
6820 supervisor
= env
->mmu_idx
;
6821 #if !defined(CONFIG_USER_ONLY)
6822 ctx
.supervisor
= supervisor
;
6824 #if defined(TARGET_PPC64)
6825 ctx
.sf_mode
= msr_sf
;
6826 ctx
.mem_idx
= (supervisor
<< 2) | (msr_sf
<< 1) | msr_le
;
6828 ctx
.mem_idx
= (supervisor
<< 1) | msr_le
;
6830 ctx
.dcache_line_size
= env
->dcache_line_size
;
6831 ctx
.fpu_enabled
= msr_fp
;
6832 #if defined(TARGET_PPCEMB)
6833 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
)
6834 ctx
.spe_enabled
= msr_spe
;
6836 ctx
.spe_enabled
= 0;
6838 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
)
6839 ctx
.altivec_enabled
= msr_vr
;
6841 ctx
.altivec_enabled
= 0;
6842 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
)
6846 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
)
6850 ctx
.singlestep_enabled
= env
->singlestep_enabled
|| single_step
== 1;
6851 #if defined (DO_SINGLE_STEP) && 0
6852 /* Single step trace mode */
6855 /* Set env in case of segfault during code fetch */
6856 while (ctx
.exception
== POWERPC_EXCP_NONE
&& gen_opc_ptr
< gen_opc_end
) {
6857 if (unlikely(env
->nb_breakpoints
> 0)) {
6858 for (j
= 0; j
< env
->nb_breakpoints
; j
++) {
6859 if (env
->breakpoints
[j
] == ctx
.nip
) {
6860 gen_update_nip(&ctx
, ctx
.nip
);
6866 if (unlikely(search_pc
)) {
6867 j
= gen_opc_ptr
- gen_opc_buf
;
6871 gen_opc_instr_start
[lj
++] = 0;
6872 gen_opc_pc
[lj
] = ctx
.nip
;
6873 gen_opc_instr_start
[lj
] = 1;
6876 #if defined PPC_DEBUG_DISAS
6877 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
6878 fprintf(logfile
, "----------------\n");
6879 fprintf(logfile
, "nip=" ADDRX
" super=%d ir=%d\n",
6880 ctx
.nip
, supervisor
, (int)msr_ir
);
6883 ctx
.opcode
= ldl_code(ctx
.nip
);
6885 ctx
.opcode
= ((ctx
.opcode
& 0xFF000000) >> 24) |
6886 ((ctx
.opcode
& 0x00FF0000) >> 8) |
6887 ((ctx
.opcode
& 0x0000FF00) << 8) |
6888 ((ctx
.opcode
& 0x000000FF) << 24);
6890 #if defined PPC_DEBUG_DISAS
6891 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
6892 fprintf(logfile
, "translate opcode %08x (%02x %02x %02x) (%s)\n",
6893 ctx
.opcode
, opc1(ctx
.opcode
), opc2(ctx
.opcode
),
6894 opc3(ctx
.opcode
), msr_le
? "little" : "big");
6898 table
= env
->opcodes
;
6899 handler
= table
[opc1(ctx
.opcode
)];
6900 if (is_indirect_opcode(handler
)) {
6901 table
= ind_table(handler
);
6902 handler
= table
[opc2(ctx
.opcode
)];
6903 if (is_indirect_opcode(handler
)) {
6904 table
= ind_table(handler
);
6905 handler
= table
[opc3(ctx
.opcode
)];
6908 /* Is opcode *REALLY* valid ? */
6909 if (unlikely(handler
->handler
== &gen_invalid
)) {
6910 if (loglevel
!= 0) {
6911 fprintf(logfile
, "invalid/unsupported opcode: "
6912 "%02x - %02x - %02x (%08x) 0x" ADDRX
" %d\n",
6913 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
6914 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
6916 printf("invalid/unsupported opcode: "
6917 "%02x - %02x - %02x (%08x) 0x" ADDRX
" %d\n",
6918 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
6919 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
6922 if (unlikely((ctx
.opcode
& handler
->inval
) != 0)) {
6923 if (loglevel
!= 0) {
6924 fprintf(logfile
, "invalid bits: %08x for opcode: "
6925 "%02x - %02x - %02x (%08x) 0x" ADDRX
"\n",
6926 ctx
.opcode
& handler
->inval
, opc1(ctx
.opcode
),
6927 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
6928 ctx
.opcode
, ctx
.nip
- 4);
6930 printf("invalid bits: %08x for opcode: "
6931 "%02x - %02x - %02x (%08x) 0x" ADDRX
"\n",
6932 ctx
.opcode
& handler
->inval
, opc1(ctx
.opcode
),
6933 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
6934 ctx
.opcode
, ctx
.nip
- 4);
6936 GEN_EXCP_INVAL(ctxp
);
6940 (*(handler
->handler
))(&ctx
);
6941 #if defined(DO_PPC_STATISTICS)
6944 /* Check trace mode exceptions */
6945 if (unlikely(branch_step
!= 0 &&
6946 ctx
.exception
== POWERPC_EXCP_BRANCH
)) {
6947 GEN_EXCP(ctxp
, POWERPC_EXCP_TRACE
, 0);
6948 } else if (unlikely(single_step
!= 0 &&
6949 (ctx
.nip
<= 0x100 || ctx
.nip
> 0xF00 ||
6950 (ctx
.nip
& 0xFC) != 0x04) &&
6951 ctx
.exception
!= POWERPC_SYSCALL
&&
6952 ctx
.exception
!= POWERPC_EXCP_TRAP
)) {
6953 GEN_EXCP(ctxp
, POWERPC_EXCP_TRACE
, 0);
6954 } else if (unlikely(((ctx
.nip
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
6955 (env
->singlestep_enabled
))) {
6956 /* if we reach a page boundary or are single stepping, stop
6961 #if defined (DO_SINGLE_STEP)
6965 if (ctx
.exception
== POWERPC_EXCP_NONE
) {
6966 gen_goto_tb(&ctx
, 0, ctx
.nip
);
6967 } else if (ctx
.exception
!= POWERPC_EXCP_BRANCH
) {
6969 /* Generate the return instruction */
6972 *gen_opc_ptr
= INDEX_op_end
;
6973 if (unlikely(search_pc
)) {
6974 j
= gen_opc_ptr
- gen_opc_buf
;
6977 gen_opc_instr_start
[lj
++] = 0;
6979 tb
->size
= ctx
.nip
- pc_start
;
6981 #if defined(DEBUG_DISAS)
6982 if (loglevel
& CPU_LOG_TB_CPU
) {
6983 fprintf(logfile
, "---------------- excp: %04x\n", ctx
.exception
);
6984 cpu_dump_state(env
, logfile
, fprintf
, 0);
6986 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
6988 flags
= env
->bfd_mach
;
6989 flags
|= msr_le
<< 16;
6990 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
6991 target_disas(logfile
, pc_start
, ctx
.nip
- pc_start
, flags
);
6992 fprintf(logfile
, "\n");
6994 if (loglevel
& CPU_LOG_TB_OP
) {
6995 fprintf(logfile
, "OP:\n");
6996 dump_ops(gen_opc_buf
, gen_opparam_buf
);
6997 fprintf(logfile
, "\n");
7003 int gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
7005 return gen_intermediate_code_internal(env
, tb
, 0);
7008 int gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
7010 return gen_intermediate_code_internal(env
, tb
, 1);