2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "disas/disas.h"
24 #include "qemu/host-utils.h"
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
41 # define LOG_DISAS(...) do { } while (0)
43 /*****************************************************************************/
44 /* Code translation helpers */
46 /* global register indexes */
47 static TCGv_ptr cpu_env
;
48 static char cpu_reg_names
[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
55 static TCGv cpu_gpr
[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh
[32];
59 static TCGv_i64 cpu_fpr
[32];
60 static TCGv_i64 cpu_avrh
[32], cpu_avrl
[32];
61 static TCGv_i32 cpu_crf
[8];
66 #if defined(TARGET_PPC64)
69 static TCGv cpu_xer
, cpu_so
, cpu_ov
, cpu_ca
;
70 static TCGv cpu_reserve
;
71 static TCGv cpu_fpscr
;
72 static TCGv_i32 cpu_access_type
;
74 #include "exec/gen-icount.h"
76 void ppc_translate_init(void)
80 size_t cpu_reg_names_size
;
81 static int done_init
= 0;
86 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
89 cpu_reg_names_size
= sizeof(cpu_reg_names
);
91 for (i
= 0; i
< 8; i
++) {
92 snprintf(p
, cpu_reg_names_size
, "crf%d", i
);
93 cpu_crf
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
94 offsetof(CPUPPCState
, crf
[i
]), p
);
96 cpu_reg_names_size
-= 5;
99 for (i
= 0; i
< 32; i
++) {
100 snprintf(p
, cpu_reg_names_size
, "r%d", i
);
101 cpu_gpr
[i
] = tcg_global_mem_new(TCG_AREG0
,
102 offsetof(CPUPPCState
, gpr
[i
]), p
);
103 p
+= (i
< 10) ? 3 : 4;
104 cpu_reg_names_size
-= (i
< 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p
, cpu_reg_names_size
, "r%dH", i
);
107 cpu_gprh
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
108 offsetof(CPUPPCState
, gprh
[i
]), p
);
109 p
+= (i
< 10) ? 4 : 5;
110 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
113 snprintf(p
, cpu_reg_names_size
, "fp%d", i
);
114 cpu_fpr
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
115 offsetof(CPUPPCState
, fpr
[i
]), p
);
116 p
+= (i
< 10) ? 4 : 5;
117 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
119 snprintf(p
, cpu_reg_names_size
, "avr%dH", i
);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
122 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
124 cpu_avrh
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
125 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
127 p
+= (i
< 10) ? 6 : 7;
128 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
130 snprintf(p
, cpu_reg_names_size
, "avr%dL", i
);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
133 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
135 cpu_avrl
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
136 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
138 p
+= (i
< 10) ? 6 : 7;
139 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
142 cpu_nip
= tcg_global_mem_new(TCG_AREG0
,
143 offsetof(CPUPPCState
, nip
), "nip");
145 cpu_msr
= tcg_global_mem_new(TCG_AREG0
,
146 offsetof(CPUPPCState
, msr
), "msr");
148 cpu_ctr
= tcg_global_mem_new(TCG_AREG0
,
149 offsetof(CPUPPCState
, ctr
), "ctr");
151 cpu_lr
= tcg_global_mem_new(TCG_AREG0
,
152 offsetof(CPUPPCState
, lr
), "lr");
154 #if defined(TARGET_PPC64)
155 cpu_cfar
= tcg_global_mem_new(TCG_AREG0
,
156 offsetof(CPUPPCState
, cfar
), "cfar");
159 cpu_xer
= tcg_global_mem_new(TCG_AREG0
,
160 offsetof(CPUPPCState
, xer
), "xer");
161 cpu_so
= tcg_global_mem_new(TCG_AREG0
,
162 offsetof(CPUPPCState
, so
), "SO");
163 cpu_ov
= tcg_global_mem_new(TCG_AREG0
,
164 offsetof(CPUPPCState
, ov
), "OV");
165 cpu_ca
= tcg_global_mem_new(TCG_AREG0
,
166 offsetof(CPUPPCState
, ca
), "CA");
168 cpu_reserve
= tcg_global_mem_new(TCG_AREG0
,
169 offsetof(CPUPPCState
, reserve_addr
),
172 cpu_fpscr
= tcg_global_mem_new(TCG_AREG0
,
173 offsetof(CPUPPCState
, fpscr
), "fpscr");
175 cpu_access_type
= tcg_global_mem_new_i32(TCG_AREG0
,
176 offsetof(CPUPPCState
, access_type
), "access_type");
178 /* register helpers */
185 /* internal defines */
186 typedef struct DisasContext
{
187 struct TranslationBlock
*tb
;
191 /* Routine used to access memory */
194 /* Translation flags */
196 #if defined(TARGET_PPC64)
203 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
204 int singlestep_enabled
;
207 struct opc_handler_t
{
208 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
210 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
212 /* instruction type */
214 /* extended instruction type */
217 void (*handler
)(DisasContext
*ctx
);
218 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
221 #if defined(DO_PPC_STATISTICS)
226 static inline void gen_reset_fpstatus(void)
228 gen_helper_reset_fpstatus(cpu_env
);
231 static inline void gen_compute_fprf(TCGv_i64 arg
, int set_fprf
, int set_rc
)
233 TCGv_i32 t0
= tcg_temp_new_i32();
236 /* This case might be optimized later */
237 tcg_gen_movi_i32(t0
, 1);
238 gen_helper_compute_fprf(t0
, cpu_env
, arg
, t0
);
239 if (unlikely(set_rc
)) {
240 tcg_gen_mov_i32(cpu_crf
[1], t0
);
242 gen_helper_float_check_status(cpu_env
);
243 } else if (unlikely(set_rc
)) {
244 /* We always need to compute fpcc */
245 tcg_gen_movi_i32(t0
, 0);
246 gen_helper_compute_fprf(t0
, cpu_env
, arg
, t0
);
247 tcg_gen_mov_i32(cpu_crf
[1], t0
);
250 tcg_temp_free_i32(t0
);
253 static inline void gen_set_access_type(DisasContext
*ctx
, int access_type
)
255 if (ctx
->access_type
!= access_type
) {
256 tcg_gen_movi_i32(cpu_access_type
, access_type
);
257 ctx
->access_type
= access_type
;
261 static inline void gen_update_nip(DisasContext
*ctx
, target_ulong nip
)
263 #if defined(TARGET_PPC64)
265 tcg_gen_movi_tl(cpu_nip
, nip
);
268 tcg_gen_movi_tl(cpu_nip
, (uint32_t)nip
);
271 static inline void gen_exception_err(DisasContext
*ctx
, uint32_t excp
, uint32_t error
)
274 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
275 gen_update_nip(ctx
, ctx
->nip
);
277 t0
= tcg_const_i32(excp
);
278 t1
= tcg_const_i32(error
);
279 gen_helper_raise_exception_err(cpu_env
, t0
, t1
);
280 tcg_temp_free_i32(t0
);
281 tcg_temp_free_i32(t1
);
282 ctx
->exception
= (excp
);
285 static inline void gen_exception(DisasContext
*ctx
, uint32_t excp
)
288 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
289 gen_update_nip(ctx
, ctx
->nip
);
291 t0
= tcg_const_i32(excp
);
292 gen_helper_raise_exception(cpu_env
, t0
);
293 tcg_temp_free_i32(t0
);
294 ctx
->exception
= (excp
);
297 static inline void gen_debug_exception(DisasContext
*ctx
)
301 if ((ctx
->exception
!= POWERPC_EXCP_BRANCH
) &&
302 (ctx
->exception
!= POWERPC_EXCP_SYNC
)) {
303 gen_update_nip(ctx
, ctx
->nip
);
305 t0
= tcg_const_i32(EXCP_DEBUG
);
306 gen_helper_raise_exception(cpu_env
, t0
);
307 tcg_temp_free_i32(t0
);
310 static inline void gen_inval_exception(DisasContext
*ctx
, uint32_t error
)
312 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_INVAL
| error
);
315 /* Stop translation */
316 static inline void gen_stop_exception(DisasContext
*ctx
)
318 gen_update_nip(ctx
, ctx
->nip
);
319 ctx
->exception
= POWERPC_EXCP_STOP
;
322 /* No need to update nip here, as execution flow will change */
323 static inline void gen_sync_exception(DisasContext
*ctx
)
325 ctx
->exception
= POWERPC_EXCP_SYNC
;
328 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
329 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
331 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
332 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
334 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
335 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
337 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
338 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
340 typedef struct opcode_t
{
341 unsigned char opc1
, opc2
, opc3
;
342 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
343 unsigned char pad
[5];
345 unsigned char pad
[1];
347 opc_handler_t handler
;
351 /*****************************************************************************/
352 /*** Instruction decoding ***/
353 #define EXTRACT_HELPER(name, shift, nb) \
354 static inline uint32_t name(uint32_t opcode) \
356 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
359 #define EXTRACT_SHELPER(name, shift, nb) \
360 static inline int32_t name(uint32_t opcode) \
362 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
366 EXTRACT_HELPER(opc1
, 26, 6);
368 EXTRACT_HELPER(opc2
, 1, 5);
370 EXTRACT_HELPER(opc3
, 6, 5);
371 /* Update Cr0 flags */
372 EXTRACT_HELPER(Rc
, 0, 1);
374 EXTRACT_HELPER(rD
, 21, 5);
376 EXTRACT_HELPER(rS
, 21, 5);
378 EXTRACT_HELPER(rA
, 16, 5);
380 EXTRACT_HELPER(rB
, 11, 5);
382 EXTRACT_HELPER(rC
, 6, 5);
384 EXTRACT_HELPER(crfD
, 23, 3);
385 EXTRACT_HELPER(crfS
, 18, 3);
386 EXTRACT_HELPER(crbD
, 21, 5);
387 EXTRACT_HELPER(crbA
, 16, 5);
388 EXTRACT_HELPER(crbB
, 11, 5);
390 EXTRACT_HELPER(_SPR
, 11, 10);
391 static inline uint32_t SPR(uint32_t opcode
)
393 uint32_t sprn
= _SPR(opcode
);
395 return ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
397 /*** Get constants ***/
398 EXTRACT_HELPER(IMM
, 12, 8);
399 /* 16 bits signed immediate value */
400 EXTRACT_SHELPER(SIMM
, 0, 16);
401 /* 16 bits unsigned immediate value */
402 EXTRACT_HELPER(UIMM
, 0, 16);
403 /* 5 bits signed immediate value */
404 EXTRACT_HELPER(SIMM5
, 16, 5);
405 /* 5 bits signed immediate value */
406 EXTRACT_HELPER(UIMM5
, 16, 5);
408 EXTRACT_HELPER(NB
, 11, 5);
410 EXTRACT_HELPER(SH
, 11, 5);
411 /* Vector shift count */
412 EXTRACT_HELPER(VSH
, 6, 4);
414 EXTRACT_HELPER(MB
, 6, 5);
416 EXTRACT_HELPER(ME
, 1, 5);
418 EXTRACT_HELPER(TO
, 21, 5);
420 EXTRACT_HELPER(CRM
, 12, 8);
421 EXTRACT_HELPER(FM
, 17, 8);
422 EXTRACT_HELPER(SR
, 16, 4);
423 EXTRACT_HELPER(FPIMM
, 12, 4);
425 /*** Jump target decoding ***/
427 EXTRACT_SHELPER(d
, 0, 16);
428 /* Immediate address */
429 static inline target_ulong
LI(uint32_t opcode
)
431 return (opcode
>> 0) & 0x03FFFFFC;
434 static inline uint32_t BD(uint32_t opcode
)
436 return (opcode
>> 0) & 0xFFFC;
439 EXTRACT_HELPER(BO
, 21, 5);
440 EXTRACT_HELPER(BI
, 16, 5);
441 /* Absolute/relative address */
442 EXTRACT_HELPER(AA
, 1, 1);
444 EXTRACT_HELPER(LK
, 0, 1);
446 /* Create a mask between <start> and <end> bits */
447 static inline target_ulong
MASK(uint32_t start
, uint32_t end
)
451 #if defined(TARGET_PPC64)
452 if (likely(start
== 0)) {
453 ret
= UINT64_MAX
<< (63 - end
);
454 } else if (likely(end
== 63)) {
455 ret
= UINT64_MAX
>> start
;
458 if (likely(start
== 0)) {
459 ret
= UINT32_MAX
<< (31 - end
);
460 } else if (likely(end
== 31)) {
461 ret
= UINT32_MAX
>> start
;
465 ret
= (((target_ulong
)(-1ULL)) >> (start
)) ^
466 (((target_ulong
)(-1ULL) >> (end
)) >> 1);
467 if (unlikely(start
> end
))
474 /*****************************************************************************/
475 /* PowerPC instructions table */
477 #if defined(DO_PPC_STATISTICS)
478 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
488 .handler = &gen_##name, \
489 .oname = stringify(name), \
491 .oname = stringify(name), \
493 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
504 .handler = &gen_##name, \
505 .oname = stringify(name), \
507 .oname = stringify(name), \
509 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
519 .handler = &gen_##name, \
525 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
535 .handler = &gen_##name, \
537 .oname = stringify(name), \
539 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
550 .handler = &gen_##name, \
552 .oname = stringify(name), \
554 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
564 .handler = &gen_##name, \
570 /* SPR load/store helpers */
571 static inline void gen_load_spr(TCGv t
, int reg
)
573 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
576 static inline void gen_store_spr(int reg
, TCGv t
)
578 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
581 /* Invalid instruction */
582 static void gen_invalid(DisasContext
*ctx
)
584 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
587 static opc_handler_t invalid_handler
= {
588 .inval1
= 0xFFFFFFFF,
589 .inval2
= 0xFFFFFFFF,
592 .handler
= gen_invalid
,
595 /*** Integer comparison ***/
597 static inline void gen_op_cmp(TCGv arg0
, TCGv arg1
, int s
, int crf
)
599 TCGv t0
= tcg_temp_new();
600 TCGv_i32 t1
= tcg_temp_new_i32();
602 tcg_gen_trunc_tl_i32(cpu_crf
[crf
], cpu_so
);
604 tcg_gen_setcond_tl((s
? TCG_COND_LT
: TCG_COND_LTU
), t0
, arg0
, arg1
);
605 tcg_gen_trunc_tl_i32(t1
, t0
);
606 tcg_gen_shli_i32(t1
, t1
, CRF_LT
);
607 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
609 tcg_gen_setcond_tl((s
? TCG_COND_GT
: TCG_COND_GTU
), t0
, arg0
, arg1
);
610 tcg_gen_trunc_tl_i32(t1
, t0
);
611 tcg_gen_shli_i32(t1
, t1
, CRF_GT
);
612 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
614 tcg_gen_setcond_tl(TCG_COND_EQ
, t0
, arg0
, arg1
);
615 tcg_gen_trunc_tl_i32(t1
, t0
);
616 tcg_gen_shli_i32(t1
, t1
, CRF_EQ
);
617 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
620 tcg_temp_free_i32(t1
);
623 static inline void gen_op_cmpi(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
625 TCGv t0
= tcg_const_tl(arg1
);
626 gen_op_cmp(arg0
, t0
, s
, crf
);
630 #if defined(TARGET_PPC64)
631 static inline void gen_op_cmp32(TCGv arg0
, TCGv arg1
, int s
, int crf
)
637 tcg_gen_ext32s_tl(t0
, arg0
);
638 tcg_gen_ext32s_tl(t1
, arg1
);
640 tcg_gen_ext32u_tl(t0
, arg0
);
641 tcg_gen_ext32u_tl(t1
, arg1
);
643 gen_op_cmp(t0
, t1
, s
, crf
);
648 static inline void gen_op_cmpi32(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
650 TCGv t0
= tcg_const_tl(arg1
);
651 gen_op_cmp32(arg0
, t0
, s
, crf
);
656 static inline void gen_set_Rc0(DisasContext
*ctx
, TCGv reg
)
658 #if defined(TARGET_PPC64)
660 gen_op_cmpi32(reg
, 0, 1, 0);
663 gen_op_cmpi(reg
, 0, 1, 0);
667 static void gen_cmp(DisasContext
*ctx
)
669 #if defined(TARGET_PPC64)
670 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
671 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
672 1, crfD(ctx
->opcode
));
675 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
676 1, crfD(ctx
->opcode
));
680 static void gen_cmpi(DisasContext
*ctx
)
682 #if defined(TARGET_PPC64)
683 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
684 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
685 1, crfD(ctx
->opcode
));
688 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
689 1, crfD(ctx
->opcode
));
693 static void gen_cmpl(DisasContext
*ctx
)
695 #if defined(TARGET_PPC64)
696 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
697 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
698 0, crfD(ctx
->opcode
));
701 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
702 0, crfD(ctx
->opcode
));
706 static void gen_cmpli(DisasContext
*ctx
)
708 #if defined(TARGET_PPC64)
709 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
710 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
711 0, crfD(ctx
->opcode
));
714 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
715 0, crfD(ctx
->opcode
));
718 /* isel (PowerPC 2.03 specification) */
719 static void gen_isel(DisasContext
*ctx
)
722 uint32_t bi
= rC(ctx
->opcode
);
726 l1
= gen_new_label();
727 l2
= gen_new_label();
729 mask
= 1 << (3 - (bi
& 0x03));
730 t0
= tcg_temp_new_i32();
731 tcg_gen_andi_i32(t0
, cpu_crf
[bi
>> 2], mask
);
732 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
733 if (rA(ctx
->opcode
) == 0)
734 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
736 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
739 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
741 tcg_temp_free_i32(t0
);
744 /*** Integer arithmetic ***/
746 static inline void gen_op_arith_compute_ov(DisasContext
*ctx
, TCGv arg0
,
747 TCGv arg1
, TCGv arg2
, int sub
)
749 TCGv t0
= tcg_temp_new();
751 tcg_gen_xor_tl(cpu_ov
, arg0
, arg1
);
752 tcg_gen_xor_tl(t0
, arg1
, arg2
);
754 tcg_gen_and_tl(cpu_ov
, cpu_ov
, t0
);
756 tcg_gen_andc_tl(cpu_ov
, cpu_ov
, t0
);
759 #if defined(TARGET_PPC64)
761 tcg_gen_ext32s_tl(cpu_ov
, cpu_ov
);
764 tcg_gen_shri_tl(cpu_ov
, cpu_ov
, TARGET_LONG_BITS
- 1);
765 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
768 /* Common add function */
769 static inline void gen_op_arith_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
770 TCGv arg2
, bool add_ca
, bool compute_ca
,
771 bool compute_ov
, bool compute_rc0
)
775 if (((compute_ca
&& add_ca
) || compute_ov
)
776 && (TCGV_EQUAL(ret
, arg1
) || TCGV_EQUAL(ret
, arg2
))) {
781 TCGv zero
= tcg_const_tl(0);
783 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, cpu_ca
, zero
);
784 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, arg2
, zero
);
786 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, arg2
, zero
);
790 tcg_gen_add_tl(t0
, arg1
, arg2
);
792 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
797 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 0);
799 if (unlikely(compute_rc0
)) {
800 gen_set_Rc0(ctx
, t0
);
803 if (!TCGV_EQUAL(t0
, ret
)) {
804 tcg_gen_mov_tl(ret
, t0
);
808 /* Add functions with two operands */
809 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
810 static void glue(gen_, name)(DisasContext *ctx) \
812 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
813 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
814 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
816 /* Add functions with one operand and one immediate */
817 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
818 add_ca, compute_ca, compute_ov) \
819 static void glue(gen_, name)(DisasContext *ctx) \
821 TCGv t0 = tcg_const_tl(const_val); \
822 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
823 cpu_gpr[rA(ctx->opcode)], t0, \
824 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
828 /* add add. addo addo. */
829 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
830 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
831 /* addc addc. addco addco. */
832 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
833 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
834 /* adde adde. addeo addeo. */
835 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
836 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
837 /* addme addme. addmeo addmeo. */
838 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
839 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
840 /* addze addze. addzeo addzeo.*/
841 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
842 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
844 static void gen_addi(DisasContext
*ctx
)
846 target_long simm
= SIMM(ctx
->opcode
);
848 if (rA(ctx
->opcode
) == 0) {
850 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
);
852 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
853 cpu_gpr
[rA(ctx
->opcode
)], simm
);
857 static inline void gen_op_addic(DisasContext
*ctx
, bool compute_rc0
)
859 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
860 gen_op_arith_add(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
861 c
, 0, 1, 0, compute_rc0
);
865 static void gen_addic(DisasContext
*ctx
)
867 gen_op_addic(ctx
, 0);
870 static void gen_addic_(DisasContext
*ctx
)
872 gen_op_addic(ctx
, 1);
876 static void gen_addis(DisasContext
*ctx
)
878 target_long simm
= SIMM(ctx
->opcode
);
880 if (rA(ctx
->opcode
) == 0) {
882 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
<< 16);
884 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
885 cpu_gpr
[rA(ctx
->opcode
)], simm
<< 16);
889 static inline void gen_op_arith_divw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
890 TCGv arg2
, int sign
, int compute_ov
)
892 int l1
= gen_new_label();
893 int l2
= gen_new_label();
894 TCGv_i32 t0
= tcg_temp_local_new_i32();
895 TCGv_i32 t1
= tcg_temp_local_new_i32();
897 tcg_gen_trunc_tl_i32(t0
, arg1
);
898 tcg_gen_trunc_tl_i32(t1
, arg2
);
899 tcg_gen_brcondi_i32(TCG_COND_EQ
, t1
, 0, l1
);
901 int l3
= gen_new_label();
902 tcg_gen_brcondi_i32(TCG_COND_NE
, t1
, -1, l3
);
903 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, INT32_MIN
, l1
);
905 tcg_gen_div_i32(t0
, t0
, t1
);
907 tcg_gen_divu_i32(t0
, t0
, t1
);
910 tcg_gen_movi_tl(cpu_ov
, 0);
915 tcg_gen_sari_i32(t0
, t0
, 31);
917 tcg_gen_movi_i32(t0
, 0);
920 tcg_gen_movi_tl(cpu_ov
, 1);
921 tcg_gen_movi_tl(cpu_so
, 1);
924 tcg_gen_extu_i32_tl(ret
, t0
);
925 tcg_temp_free_i32(t0
);
926 tcg_temp_free_i32(t1
);
927 if (unlikely(Rc(ctx
->opcode
) != 0))
928 gen_set_Rc0(ctx
, ret
);
931 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
932 static void glue(gen_, name)(DisasContext *ctx) \
934 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
935 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
938 /* divwu divwu. divwuo divwuo. */
939 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0);
940 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1);
941 /* divw divw. divwo divwo. */
942 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0);
943 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1);
944 #if defined(TARGET_PPC64)
945 static inline void gen_op_arith_divd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
946 TCGv arg2
, int sign
, int compute_ov
)
948 int l1
= gen_new_label();
949 int l2
= gen_new_label();
951 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg2
, 0, l1
);
953 int l3
= gen_new_label();
954 tcg_gen_brcondi_i64(TCG_COND_NE
, arg2
, -1, l3
);
955 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg1
, INT64_MIN
, l1
);
957 tcg_gen_div_i64(ret
, arg1
, arg2
);
959 tcg_gen_divu_i64(ret
, arg1
, arg2
);
962 tcg_gen_movi_tl(cpu_ov
, 0);
967 tcg_gen_sari_i64(ret
, arg1
, 63);
969 tcg_gen_movi_i64(ret
, 0);
972 tcg_gen_movi_tl(cpu_ov
, 1);
973 tcg_gen_movi_tl(cpu_so
, 1);
976 if (unlikely(Rc(ctx
->opcode
) != 0))
977 gen_set_Rc0(ctx
, ret
);
979 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
980 static void glue(gen_, name)(DisasContext *ctx) \
982 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
983 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
986 /* divwu divwu. divwuo divwuo. */
987 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0);
988 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1);
989 /* divw divw. divwo divwo. */
990 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0);
991 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1);
995 static void gen_mulhw(DisasContext
*ctx
)
997 TCGv_i32 t0
= tcg_temp_new_i32();
998 TCGv_i32 t1
= tcg_temp_new_i32();
1000 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1001 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1002 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1003 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1004 tcg_temp_free_i32(t0
);
1005 tcg_temp_free_i32(t1
);
1006 if (unlikely(Rc(ctx
->opcode
) != 0))
1007 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1010 /* mulhwu mulhwu. */
1011 static void gen_mulhwu(DisasContext
*ctx
)
1013 TCGv_i32 t0
= tcg_temp_new_i32();
1014 TCGv_i32 t1
= tcg_temp_new_i32();
1016 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1017 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1018 tcg_gen_mulu2_i32(t0
, t1
, t0
, t1
);
1019 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1020 tcg_temp_free_i32(t0
);
1021 tcg_temp_free_i32(t1
);
1022 if (unlikely(Rc(ctx
->opcode
) != 0))
1023 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1027 static void gen_mullw(DisasContext
*ctx
)
1029 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1030 cpu_gpr
[rB(ctx
->opcode
)]);
1031 tcg_gen_ext32s_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)]);
1032 if (unlikely(Rc(ctx
->opcode
) != 0))
1033 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1036 /* mullwo mullwo. */
1037 static void gen_mullwo(DisasContext
*ctx
)
1039 TCGv_i32 t0
= tcg_temp_new_i32();
1040 TCGv_i32 t1
= tcg_temp_new_i32();
1042 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1043 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1044 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1045 tcg_gen_ext_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1047 tcg_gen_sari_i32(t0
, t0
, 31);
1048 tcg_gen_setcond_i32(TCG_COND_NE
, t0
, t0
, t1
);
1049 tcg_gen_extu_i32_tl(cpu_ov
, t0
);
1050 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1052 tcg_temp_free_i32(t0
);
1053 tcg_temp_free_i32(t1
);
1054 if (unlikely(Rc(ctx
->opcode
) != 0))
1055 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1059 static void gen_mulli(DisasContext
*ctx
)
1061 tcg_gen_muli_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1065 #if defined(TARGET_PPC64)
1067 static void gen_mulhd(DisasContext
*ctx
)
1069 TCGv lo
= tcg_temp_new();
1070 tcg_gen_muls2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1071 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1073 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1074 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1078 /* mulhdu mulhdu. */
1079 static void gen_mulhdu(DisasContext
*ctx
)
1081 TCGv lo
= tcg_temp_new();
1082 tcg_gen_mulu2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1083 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1085 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1086 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1091 static void gen_mulld(DisasContext
*ctx
)
1093 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1094 cpu_gpr
[rB(ctx
->opcode
)]);
1095 if (unlikely(Rc(ctx
->opcode
) != 0))
1096 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1099 /* mulldo mulldo. */
1100 static void gen_mulldo(DisasContext
*ctx
)
1102 gen_helper_mulldo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
1103 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1104 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1105 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1110 /* Common subf function */
1111 static inline void gen_op_arith_subf(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1112 TCGv arg2
, bool add_ca
, bool compute_ca
,
1113 bool compute_ov
, bool compute_rc0
)
1117 if (((add_ca
&& compute_ca
) || compute_ov
)
1118 && (TCGV_EQUAL(ret
, arg1
) || TCGV_EQUAL(ret
, arg2
))) {
1119 t0
= tcg_temp_new();
1123 /* dest = ~arg1 + arg2 + ca = arg2 - arg1 + ca - 1. */
1126 tcg_gen_subi_tl(cpu_ca
, cpu_ca
, 1);
1127 zero
= tcg_const_tl(0);
1128 tcg_gen_add2_tl(t0
, cpu_ca
, arg2
, zero
, cpu_ca
, zero
);
1129 tcg_gen_sub2_tl(t0
, cpu_ca
, t0
, cpu_ca
, arg1
, zero
);
1130 tcg_temp_free(zero
);
1132 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1133 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
1134 tcg_gen_subi_tl(t0
, t0
, 1);
1138 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_ca
, arg2
, arg1
);
1140 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1144 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 1);
1146 if (unlikely(compute_rc0
)) {
1147 gen_set_Rc0(ctx
, t0
);
1150 if (!TCGV_EQUAL(t0
, ret
)) {
1151 tcg_gen_mov_tl(ret
, t0
);
1155 /* Sub functions with Two operands functions */
1156 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1157 static void glue(gen_, name)(DisasContext *ctx) \
1159 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1160 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1161 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1163 /* Sub functions with one operand and one immediate */
1164 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1165 add_ca, compute_ca, compute_ov) \
1166 static void glue(gen_, name)(DisasContext *ctx) \
1168 TCGv t0 = tcg_const_tl(const_val); \
1169 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1170 cpu_gpr[rA(ctx->opcode)], t0, \
1171 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1172 tcg_temp_free(t0); \
1174 /* subf subf. subfo subfo. */
1175 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
1176 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
1177 /* subfc subfc. subfco subfco. */
1178 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
1179 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
1180 /* subfe subfe. subfeo subfo. */
1181 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
1182 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
1183 /* subfme subfme. subfmeo subfmeo. */
1184 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
1185 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
1186 /* subfze subfze. subfzeo subfzeo.*/
1187 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
1188 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
1191 static void gen_subfic(DisasContext
*ctx
)
1193 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
1194 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1199 /* neg neg. nego nego. */
1200 static inline void gen_op_arith_neg(DisasContext
*ctx
, bool compute_ov
)
1202 TCGv zero
= tcg_const_tl(0);
1203 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1204 zero
, 0, 0, compute_ov
, Rc(ctx
->opcode
));
1205 tcg_temp_free(zero
);
1208 static void gen_neg(DisasContext
*ctx
)
1210 gen_op_arith_neg(ctx
, 0);
1213 static void gen_nego(DisasContext
*ctx
)
1215 gen_op_arith_neg(ctx
, 1);
1218 /*** Integer logical ***/
1219 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1220 static void glue(gen_, name)(DisasContext *ctx) \
1222 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1223 cpu_gpr[rB(ctx->opcode)]); \
1224 if (unlikely(Rc(ctx->opcode) != 0)) \
1225 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1228 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1229 static void glue(gen_, name)(DisasContext *ctx) \
1231 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1232 if (unlikely(Rc(ctx->opcode) != 0)) \
1233 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1237 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
);
1239 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
);
1242 static void gen_andi_(DisasContext
*ctx
)
1244 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
));
1245 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1249 static void gen_andis_(DisasContext
*ctx
)
1251 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
) << 16);
1252 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1256 static void gen_cntlzw(DisasContext
*ctx
)
1258 gen_helper_cntlzw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1259 if (unlikely(Rc(ctx
->opcode
) != 0))
1260 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1263 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
);
1264 /* extsb & extsb. */
1265 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
);
1266 /* extsh & extsh. */
1267 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
);
1269 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
);
1271 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
);
1274 static void gen_or(DisasContext
*ctx
)
1278 rs
= rS(ctx
->opcode
);
1279 ra
= rA(ctx
->opcode
);
1280 rb
= rB(ctx
->opcode
);
1281 /* Optimisation for mr. ri case */
1282 if (rs
!= ra
|| rs
!= rb
) {
1284 tcg_gen_or_tl(cpu_gpr
[ra
], cpu_gpr
[rs
], cpu_gpr
[rb
]);
1286 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rs
]);
1287 if (unlikely(Rc(ctx
->opcode
) != 0))
1288 gen_set_Rc0(ctx
, cpu_gpr
[ra
]);
1289 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1290 gen_set_Rc0(ctx
, cpu_gpr
[rs
]);
1291 #if defined(TARGET_PPC64)
1297 /* Set process priority to low */
1301 /* Set process priority to medium-low */
1305 /* Set process priority to normal */
1308 #if !defined(CONFIG_USER_ONLY)
1310 if (ctx
->mem_idx
> 0) {
1311 /* Set process priority to very low */
1316 if (ctx
->mem_idx
> 0) {
1317 /* Set process priority to medium-hight */
1322 if (ctx
->mem_idx
> 0) {
1323 /* Set process priority to high */
1328 if (ctx
->mem_idx
> 1) {
1329 /* Set process priority to very high */
1339 TCGv t0
= tcg_temp_new();
1340 gen_load_spr(t0
, SPR_PPR
);
1341 tcg_gen_andi_tl(t0
, t0
, ~0x001C000000000000ULL
);
1342 tcg_gen_ori_tl(t0
, t0
, ((uint64_t)prio
) << 50);
1343 gen_store_spr(SPR_PPR
, t0
);
1350 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
);
1353 static void gen_xor(DisasContext
*ctx
)
1355 /* Optimisation for "set to zero" case */
1356 if (rS(ctx
->opcode
) != rB(ctx
->opcode
))
1357 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1359 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1360 if (unlikely(Rc(ctx
->opcode
) != 0))
1361 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1365 static void gen_ori(DisasContext
*ctx
)
1367 target_ulong uimm
= UIMM(ctx
->opcode
);
1369 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1371 /* XXX: should handle special NOPs for POWER series */
1374 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1378 static void gen_oris(DisasContext
*ctx
)
1380 target_ulong uimm
= UIMM(ctx
->opcode
);
1382 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1386 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1390 static void gen_xori(DisasContext
*ctx
)
1392 target_ulong uimm
= UIMM(ctx
->opcode
);
1394 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1398 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1402 static void gen_xoris(DisasContext
*ctx
)
1404 target_ulong uimm
= UIMM(ctx
->opcode
);
1406 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1410 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1413 /* popcntb : PowerPC 2.03 specification */
1414 static void gen_popcntb(DisasContext
*ctx
)
1416 gen_helper_popcntb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1419 static void gen_popcntw(DisasContext
*ctx
)
1421 gen_helper_popcntw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1424 #if defined(TARGET_PPC64)
1425 /* popcntd: PowerPC 2.06 specification */
1426 static void gen_popcntd(DisasContext
*ctx
)
1428 gen_helper_popcntd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1432 #if defined(TARGET_PPC64)
1433 /* extsw & extsw. */
1434 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
);
1437 static void gen_cntlzd(DisasContext
*ctx
)
1439 gen_helper_cntlzd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1440 if (unlikely(Rc(ctx
->opcode
) != 0))
1441 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1445 /*** Integer rotate ***/
1447 /* rlwimi & rlwimi. */
1448 static void gen_rlwimi(DisasContext
*ctx
)
1450 uint32_t mb
, me
, sh
;
1452 mb
= MB(ctx
->opcode
);
1453 me
= ME(ctx
->opcode
);
1454 sh
= SH(ctx
->opcode
);
1455 if (likely(sh
== 0 && mb
== 0 && me
== 31)) {
1456 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1460 TCGv t0
= tcg_temp_new();
1461 #if defined(TARGET_PPC64)
1462 TCGv_i32 t2
= tcg_temp_new_i32();
1463 tcg_gen_trunc_i64_i32(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
1464 tcg_gen_rotli_i32(t2
, t2
, sh
);
1465 tcg_gen_extu_i32_i64(t0
, t2
);
1466 tcg_temp_free_i32(t2
);
1468 tcg_gen_rotli_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1470 #if defined(TARGET_PPC64)
1474 mask
= MASK(mb
, me
);
1475 t1
= tcg_temp_new();
1476 tcg_gen_andi_tl(t0
, t0
, mask
);
1477 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], ~mask
);
1478 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1482 if (unlikely(Rc(ctx
->opcode
) != 0))
1483 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1486 /* rlwinm & rlwinm. */
1487 static void gen_rlwinm(DisasContext
*ctx
)
1489 uint32_t mb
, me
, sh
;
1491 sh
= SH(ctx
->opcode
);
1492 mb
= MB(ctx
->opcode
);
1493 me
= ME(ctx
->opcode
);
1495 if (likely(mb
== 0 && me
== (31 - sh
))) {
1496 if (likely(sh
== 0)) {
1497 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1499 TCGv t0
= tcg_temp_new();
1500 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1501 tcg_gen_shli_tl(t0
, t0
, sh
);
1502 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1505 } else if (likely(sh
!= 0 && me
== 31 && sh
== (32 - mb
))) {
1506 TCGv t0
= tcg_temp_new();
1507 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1508 tcg_gen_shri_tl(t0
, t0
, mb
);
1509 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1512 TCGv t0
= tcg_temp_new();
1513 #if defined(TARGET_PPC64)
1514 TCGv_i32 t1
= tcg_temp_new_i32();
1515 tcg_gen_trunc_i64_i32(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
1516 tcg_gen_rotli_i32(t1
, t1
, sh
);
1517 tcg_gen_extu_i32_i64(t0
, t1
);
1518 tcg_temp_free_i32(t1
);
1520 tcg_gen_rotli_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1522 #if defined(TARGET_PPC64)
1526 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1529 if (unlikely(Rc(ctx
->opcode
) != 0))
1530 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1533 /* rlwnm & rlwnm. */
1534 static void gen_rlwnm(DisasContext
*ctx
)
1538 #if defined(TARGET_PPC64)
1542 mb
= MB(ctx
->opcode
);
1543 me
= ME(ctx
->opcode
);
1544 t0
= tcg_temp_new();
1545 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1546 #if defined(TARGET_PPC64)
1547 t1
= tcg_temp_new_i32();
1548 t2
= tcg_temp_new_i32();
1549 tcg_gen_trunc_i64_i32(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
1550 tcg_gen_trunc_i64_i32(t2
, t0
);
1551 tcg_gen_rotl_i32(t1
, t1
, t2
);
1552 tcg_gen_extu_i32_i64(t0
, t1
);
1553 tcg_temp_free_i32(t1
);
1554 tcg_temp_free_i32(t2
);
1556 tcg_gen_rotl_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1558 if (unlikely(mb
!= 0 || me
!= 31)) {
1559 #if defined(TARGET_PPC64)
1563 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1565 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1568 if (unlikely(Rc(ctx
->opcode
) != 0))
1569 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1572 #if defined(TARGET_PPC64)
1573 #define GEN_PPC64_R2(name, opc1, opc2) \
1574 static void glue(gen_, name##0)(DisasContext *ctx) \
1576 gen_##name(ctx, 0); \
1579 static void glue(gen_, name##1)(DisasContext *ctx) \
1581 gen_##name(ctx, 1); \
1583 #define GEN_PPC64_R4(name, opc1, opc2) \
1584 static void glue(gen_, name##0)(DisasContext *ctx) \
1586 gen_##name(ctx, 0, 0); \
1589 static void glue(gen_, name##1)(DisasContext *ctx) \
1591 gen_##name(ctx, 0, 1); \
1594 static void glue(gen_, name##2)(DisasContext *ctx) \
1596 gen_##name(ctx, 1, 0); \
1599 static void glue(gen_, name##3)(DisasContext *ctx) \
1601 gen_##name(ctx, 1, 1); \
1604 static inline void gen_rldinm(DisasContext
*ctx
, uint32_t mb
, uint32_t me
,
1607 if (likely(sh
!= 0 && mb
== 0 && me
== (63 - sh
))) {
1608 tcg_gen_shli_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
1609 } else if (likely(sh
!= 0 && me
== 63 && sh
== (64 - mb
))) {
1610 tcg_gen_shri_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], mb
);
1612 TCGv t0
= tcg_temp_new();
1613 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1614 if (likely(mb
== 0 && me
== 63)) {
1615 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1617 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1621 if (unlikely(Rc(ctx
->opcode
) != 0))
1622 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1624 /* rldicl - rldicl. */
1625 static inline void gen_rldicl(DisasContext
*ctx
, int mbn
, int shn
)
1629 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1630 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1631 gen_rldinm(ctx
, mb
, 63, sh
);
1633 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
1634 /* rldicr - rldicr. */
1635 static inline void gen_rldicr(DisasContext
*ctx
, int men
, int shn
)
1639 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1640 me
= MB(ctx
->opcode
) | (men
<< 5);
1641 gen_rldinm(ctx
, 0, me
, sh
);
1643 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
1644 /* rldic - rldic. */
1645 static inline void gen_rldic(DisasContext
*ctx
, int mbn
, int shn
)
1649 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1650 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1651 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
1653 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
1655 static inline void gen_rldnm(DisasContext
*ctx
, uint32_t mb
, uint32_t me
)
1659 mb
= MB(ctx
->opcode
);
1660 me
= ME(ctx
->opcode
);
1661 t0
= tcg_temp_new();
1662 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
1663 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1664 if (unlikely(mb
!= 0 || me
!= 63)) {
1665 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1667 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1670 if (unlikely(Rc(ctx
->opcode
) != 0))
1671 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1674 /* rldcl - rldcl. */
1675 static inline void gen_rldcl(DisasContext
*ctx
, int mbn
)
1679 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1680 gen_rldnm(ctx
, mb
, 63);
1682 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
1683 /* rldcr - rldcr. */
1684 static inline void gen_rldcr(DisasContext
*ctx
, int men
)
1688 me
= MB(ctx
->opcode
) | (men
<< 5);
1689 gen_rldnm(ctx
, 0, me
);
1691 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
1692 /* rldimi - rldimi. */
1693 static inline void gen_rldimi(DisasContext
*ctx
, int mbn
, int shn
)
1695 uint32_t sh
, mb
, me
;
1697 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1698 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1700 if (unlikely(sh
== 0 && mb
== 0)) {
1701 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1706 t0
= tcg_temp_new();
1707 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1708 t1
= tcg_temp_new();
1709 mask
= MASK(mb
, me
);
1710 tcg_gen_andi_tl(t0
, t0
, mask
);
1711 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], ~mask
);
1712 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1716 if (unlikely(Rc(ctx
->opcode
) != 0))
1717 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1719 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
1722 /*** Integer shift ***/
1725 static void gen_slw(DisasContext
*ctx
)
1729 t0
= tcg_temp_new();
1730 /* AND rS with a mask that is 0 when rB >= 0x20 */
1731 #if defined(TARGET_PPC64)
1732 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
1733 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1735 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
1736 tcg_gen_sari_tl(t0
, t0
, 0x1f);
1738 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1739 t1
= tcg_temp_new();
1740 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1741 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1744 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
1745 if (unlikely(Rc(ctx
->opcode
) != 0))
1746 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1750 static void gen_sraw(DisasContext
*ctx
)
1752 gen_helper_sraw(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
1753 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1754 if (unlikely(Rc(ctx
->opcode
) != 0))
1755 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1758 /* srawi & srawi. */
1759 static void gen_srawi(DisasContext
*ctx
)
1761 int sh
= SH(ctx
->opcode
);
1762 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
1763 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
1765 tcg_gen_mov_tl(dst
, src
);
1766 tcg_gen_movi_tl(cpu_ca
, 0);
1769 tcg_gen_ext32s_tl(dst
, src
);
1770 tcg_gen_andi_tl(cpu_ca
, dst
, (1ULL << sh
) - 1);
1771 t0
= tcg_temp_new();
1772 tcg_gen_sari_tl(t0
, dst
, TARGET_LONG_BITS
- 1);
1773 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
1775 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
1776 tcg_gen_sari_tl(dst
, dst
, sh
);
1778 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1779 gen_set_Rc0(ctx
, dst
);
1784 static void gen_srw(DisasContext
*ctx
)
1788 t0
= tcg_temp_new();
1789 /* AND rS with a mask that is 0 when rB >= 0x20 */
1790 #if defined(TARGET_PPC64)
1791 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
1792 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1794 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
1795 tcg_gen_sari_tl(t0
, t0
, 0x1f);
1797 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1798 tcg_gen_ext32u_tl(t0
, t0
);
1799 t1
= tcg_temp_new();
1800 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1801 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1804 if (unlikely(Rc(ctx
->opcode
) != 0))
1805 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1808 #if defined(TARGET_PPC64)
1810 static void gen_sld(DisasContext
*ctx
)
1814 t0
= tcg_temp_new();
1815 /* AND rS with a mask that is 0 when rB >= 0x40 */
1816 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
1817 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1818 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1819 t1
= tcg_temp_new();
1820 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
1821 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1824 if (unlikely(Rc(ctx
->opcode
) != 0))
1825 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1829 static void gen_srad(DisasContext
*ctx
)
1831 gen_helper_srad(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
1832 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1833 if (unlikely(Rc(ctx
->opcode
) != 0))
1834 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1836 /* sradi & sradi. */
1837 static inline void gen_sradi(DisasContext
*ctx
, int n
)
1839 int sh
= SH(ctx
->opcode
) + (n
<< 5);
1840 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
1841 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
1843 tcg_gen_mov_tl(dst
, src
);
1844 tcg_gen_movi_tl(cpu_ca
, 0);
1847 tcg_gen_andi_tl(cpu_ca
, src
, (1ULL << sh
) - 1);
1848 t0
= tcg_temp_new();
1849 tcg_gen_sari_tl(t0
, src
, TARGET_LONG_BITS
- 1);
1850 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
1852 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
1853 tcg_gen_sari_tl(dst
, src
, sh
);
1855 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1856 gen_set_Rc0(ctx
, dst
);
1860 static void gen_sradi0(DisasContext
*ctx
)
1865 static void gen_sradi1(DisasContext
*ctx
)
1871 static void gen_srd(DisasContext
*ctx
)
1875 t0
= tcg_temp_new();
1876 /* AND rS with a mask that is 0 when rB >= 0x40 */
1877 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
1878 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1879 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1880 t1
= tcg_temp_new();
1881 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
1882 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1885 if (unlikely(Rc(ctx
->opcode
) != 0))
1886 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1890 /*** Floating-Point arithmetic ***/
1891 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1892 static void gen_f##name(DisasContext *ctx) \
1894 if (unlikely(!ctx->fpu_enabled)) { \
1895 gen_exception(ctx, POWERPC_EXCP_FPU); \
1898 /* NIP cannot be restored if the memory exception comes from an helper */ \
1899 gen_update_nip(ctx, ctx->nip - 4); \
1900 gen_reset_fpstatus(); \
1901 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1902 cpu_fpr[rA(ctx->opcode)], \
1903 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1905 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1906 cpu_fpr[rD(ctx->opcode)]); \
1908 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
1909 Rc(ctx->opcode) != 0); \
1912 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1913 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1914 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1916 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1917 static void gen_f##name(DisasContext *ctx) \
1919 if (unlikely(!ctx->fpu_enabled)) { \
1920 gen_exception(ctx, POWERPC_EXCP_FPU); \
1923 /* NIP cannot be restored if the memory exception comes from an helper */ \
1924 gen_update_nip(ctx, ctx->nip - 4); \
1925 gen_reset_fpstatus(); \
1926 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1927 cpu_fpr[rA(ctx->opcode)], \
1928 cpu_fpr[rB(ctx->opcode)]); \
1930 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1931 cpu_fpr[rD(ctx->opcode)]); \
1933 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1934 set_fprf, Rc(ctx->opcode) != 0); \
1936 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1937 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1938 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1940 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1941 static void gen_f##name(DisasContext *ctx) \
1943 if (unlikely(!ctx->fpu_enabled)) { \
1944 gen_exception(ctx, POWERPC_EXCP_FPU); \
1947 /* NIP cannot be restored if the memory exception comes from an helper */ \
1948 gen_update_nip(ctx, ctx->nip - 4); \
1949 gen_reset_fpstatus(); \
1950 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1951 cpu_fpr[rA(ctx->opcode)], \
1952 cpu_fpr[rC(ctx->opcode)]); \
1954 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1955 cpu_fpr[rD(ctx->opcode)]); \
1957 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1958 set_fprf, Rc(ctx->opcode) != 0); \
1960 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1961 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1962 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1964 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
1965 static void gen_f##name(DisasContext *ctx) \
1967 if (unlikely(!ctx->fpu_enabled)) { \
1968 gen_exception(ctx, POWERPC_EXCP_FPU); \
1971 /* NIP cannot be restored if the memory exception comes from an helper */ \
1972 gen_update_nip(ctx, ctx->nip - 4); \
1973 gen_reset_fpstatus(); \
1974 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1975 cpu_fpr[rB(ctx->opcode)]); \
1976 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1977 set_fprf, Rc(ctx->opcode) != 0); \
1980 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
1981 static void gen_f##name(DisasContext *ctx) \
1983 if (unlikely(!ctx->fpu_enabled)) { \
1984 gen_exception(ctx, POWERPC_EXCP_FPU); \
1987 /* NIP cannot be restored if the memory exception comes from an helper */ \
1988 gen_update_nip(ctx, ctx->nip - 4); \
1989 gen_reset_fpstatus(); \
1990 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1991 cpu_fpr[rB(ctx->opcode)]); \
1992 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1993 set_fprf, Rc(ctx->opcode) != 0); \
1997 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
);
1999 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
);
2001 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
);
2004 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
);
2007 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
);
2010 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
);
2013 static void gen_frsqrtes(DisasContext
*ctx
)
2015 if (unlikely(!ctx
->fpu_enabled
)) {
2016 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2019 /* NIP cannot be restored if the memory exception comes from an helper */
2020 gen_update_nip(ctx
, ctx
->nip
- 4);
2021 gen_reset_fpstatus();
2022 gen_helper_frsqrte(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2023 cpu_fpr
[rB(ctx
->opcode
)]);
2024 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2025 cpu_fpr
[rD(ctx
->opcode
)]);
2026 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 1, Rc(ctx
->opcode
) != 0);
2030 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
);
2032 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
);
2036 static void gen_fsqrt(DisasContext
*ctx
)
2038 if (unlikely(!ctx
->fpu_enabled
)) {
2039 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2042 /* NIP cannot be restored if the memory exception comes from an helper */
2043 gen_update_nip(ctx
, ctx
->nip
- 4);
2044 gen_reset_fpstatus();
2045 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2046 cpu_fpr
[rB(ctx
->opcode
)]);
2047 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 1, Rc(ctx
->opcode
) != 0);
2050 static void gen_fsqrts(DisasContext
*ctx
)
2052 if (unlikely(!ctx
->fpu_enabled
)) {
2053 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2056 /* NIP cannot be restored if the memory exception comes from an helper */
2057 gen_update_nip(ctx
, ctx
->nip
- 4);
2058 gen_reset_fpstatus();
2059 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2060 cpu_fpr
[rB(ctx
->opcode
)]);
2061 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2062 cpu_fpr
[rD(ctx
->opcode
)]);
2063 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 1, Rc(ctx
->opcode
) != 0);
2066 /*** Floating-Point multiply-and-add ***/
2067 /* fmadd - fmadds */
2068 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
);
2069 /* fmsub - fmsubs */
2070 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
);
2071 /* fnmadd - fnmadds */
2072 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
);
2073 /* fnmsub - fnmsubs */
2074 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
);
2076 /*** Floating-Point round & convert ***/
2078 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
);
2080 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
);
2082 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
);
2083 #if defined(TARGET_PPC64)
2085 GEN_FLOAT_B(cfid
, 0x0E, 0x1A, 1, PPC_64B
);
2087 GEN_FLOAT_B(ctid
, 0x0E, 0x19, 0, PPC_64B
);
2089 GEN_FLOAT_B(ctidz
, 0x0F, 0x19, 0, PPC_64B
);
2093 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
);
2095 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
);
2097 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
);
2099 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
);
2101 /*** Floating-Point compare ***/
2104 static void gen_fcmpo(DisasContext
*ctx
)
2107 if (unlikely(!ctx
->fpu_enabled
)) {
2108 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2111 /* NIP cannot be restored if the memory exception comes from an helper */
2112 gen_update_nip(ctx
, ctx
->nip
- 4);
2113 gen_reset_fpstatus();
2114 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2115 gen_helper_fcmpo(cpu_env
, cpu_fpr
[rA(ctx
->opcode
)],
2116 cpu_fpr
[rB(ctx
->opcode
)], crf
);
2117 tcg_temp_free_i32(crf
);
2118 gen_helper_float_check_status(cpu_env
);
2122 static void gen_fcmpu(DisasContext
*ctx
)
2125 if (unlikely(!ctx
->fpu_enabled
)) {
2126 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2129 /* NIP cannot be restored if the memory exception comes from an helper */
2130 gen_update_nip(ctx
, ctx
->nip
- 4);
2131 gen_reset_fpstatus();
2132 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2133 gen_helper_fcmpu(cpu_env
, cpu_fpr
[rA(ctx
->opcode
)],
2134 cpu_fpr
[rB(ctx
->opcode
)], crf
);
2135 tcg_temp_free_i32(crf
);
2136 gen_helper_float_check_status(cpu_env
);
2139 /*** Floating-point move ***/
2141 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2142 GEN_FLOAT_B(abs
, 0x08, 0x08, 0, PPC_FLOAT
);
2145 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2146 static void gen_fmr(DisasContext
*ctx
)
2148 if (unlikely(!ctx
->fpu_enabled
)) {
2149 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2152 tcg_gen_mov_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2153 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 0, Rc(ctx
->opcode
) != 0);
2157 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2158 GEN_FLOAT_B(nabs
, 0x08, 0x04, 0, PPC_FLOAT
);
2160 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2161 GEN_FLOAT_B(neg
, 0x08, 0x01, 0, PPC_FLOAT
);
2163 /*** Floating-Point status & ctrl register ***/
2166 static void gen_mcrfs(DisasContext
*ctx
)
2168 TCGv tmp
= tcg_temp_new();
2171 if (unlikely(!ctx
->fpu_enabled
)) {
2172 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2175 bfa
= 4 * (7 - crfS(ctx
->opcode
));
2176 tcg_gen_shri_tl(tmp
, cpu_fpscr
, bfa
);
2177 tcg_gen_trunc_tl_i32(cpu_crf
[crfD(ctx
->opcode
)], tmp
);
2179 tcg_gen_andi_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfD(ctx
->opcode
)], 0xf);
2180 tcg_gen_andi_tl(cpu_fpscr
, cpu_fpscr
, ~(0xF << bfa
));
2184 static void gen_mffs(DisasContext
*ctx
)
2186 if (unlikely(!ctx
->fpu_enabled
)) {
2187 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2190 gen_reset_fpstatus();
2191 tcg_gen_extu_tl_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpscr
);
2192 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 0, Rc(ctx
->opcode
) != 0);
2196 static void gen_mtfsb0(DisasContext
*ctx
)
2200 if (unlikely(!ctx
->fpu_enabled
)) {
2201 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2204 crb
= 31 - crbD(ctx
->opcode
);
2205 gen_reset_fpstatus();
2206 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
)) {
2208 /* NIP cannot be restored if the memory exception comes from an helper */
2209 gen_update_nip(ctx
, ctx
->nip
- 4);
2210 t0
= tcg_const_i32(crb
);
2211 gen_helper_fpscr_clrbit(cpu_env
, t0
);
2212 tcg_temp_free_i32(t0
);
2214 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2215 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2216 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2221 static void gen_mtfsb1(DisasContext
*ctx
)
2225 if (unlikely(!ctx
->fpu_enabled
)) {
2226 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2229 crb
= 31 - crbD(ctx
->opcode
);
2230 gen_reset_fpstatus();
2231 /* XXX: we pretend we can only do IEEE floating-point computations */
2232 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
&& crb
!= FPSCR_NI
)) {
2234 /* NIP cannot be restored if the memory exception comes from an helper */
2235 gen_update_nip(ctx
, ctx
->nip
- 4);
2236 t0
= tcg_const_i32(crb
);
2237 gen_helper_fpscr_setbit(cpu_env
, t0
);
2238 tcg_temp_free_i32(t0
);
2240 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2241 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2242 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2244 /* We can raise a differed exception */
2245 gen_helper_float_check_status(cpu_env
);
2249 static void gen_mtfsf(DisasContext
*ctx
)
2252 int L
= ctx
->opcode
& 0x02000000;
2254 if (unlikely(!ctx
->fpu_enabled
)) {
2255 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2258 /* NIP cannot be restored if the memory exception comes from an helper */
2259 gen_update_nip(ctx
, ctx
->nip
- 4);
2260 gen_reset_fpstatus();
2262 t0
= tcg_const_i32(0xff);
2264 t0
= tcg_const_i32(FM(ctx
->opcode
));
2265 gen_helper_store_fpscr(cpu_env
, cpu_fpr
[rB(ctx
->opcode
)], t0
);
2266 tcg_temp_free_i32(t0
);
2267 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2268 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2269 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2271 /* We can raise a differed exception */
2272 gen_helper_float_check_status(cpu_env
);
2276 static void gen_mtfsfi(DisasContext
*ctx
)
2282 if (unlikely(!ctx
->fpu_enabled
)) {
2283 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2286 bf
= crbD(ctx
->opcode
) >> 2;
2288 /* NIP cannot be restored if the memory exception comes from an helper */
2289 gen_update_nip(ctx
, ctx
->nip
- 4);
2290 gen_reset_fpstatus();
2291 t0
= tcg_const_i64(FPIMM(ctx
->opcode
) << (4 * sh
));
2292 t1
= tcg_const_i32(1 << sh
);
2293 gen_helper_store_fpscr(cpu_env
, t0
, t1
);
2294 tcg_temp_free_i64(t0
);
2295 tcg_temp_free_i32(t1
);
2296 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2297 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2298 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2300 /* We can raise a differed exception */
2301 gen_helper_float_check_status(cpu_env
);
2304 /*** Addressing modes ***/
2305 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2306 static inline void gen_addr_imm_index(DisasContext
*ctx
, TCGv EA
,
2309 target_long simm
= SIMM(ctx
->opcode
);
2312 if (rA(ctx
->opcode
) == 0) {
2313 #if defined(TARGET_PPC64)
2314 if (!ctx
->sf_mode
) {
2315 tcg_gen_movi_tl(EA
, (uint32_t)simm
);
2318 tcg_gen_movi_tl(EA
, simm
);
2319 } else if (likely(simm
!= 0)) {
2320 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], simm
);
2321 #if defined(TARGET_PPC64)
2322 if (!ctx
->sf_mode
) {
2323 tcg_gen_ext32u_tl(EA
, EA
);
2327 #if defined(TARGET_PPC64)
2328 if (!ctx
->sf_mode
) {
2329 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2332 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2336 static inline void gen_addr_reg_index(DisasContext
*ctx
, TCGv EA
)
2338 if (rA(ctx
->opcode
) == 0) {
2339 #if defined(TARGET_PPC64)
2340 if (!ctx
->sf_mode
) {
2341 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2344 tcg_gen_mov_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2346 tcg_gen_add_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2347 #if defined(TARGET_PPC64)
2348 if (!ctx
->sf_mode
) {
2349 tcg_gen_ext32u_tl(EA
, EA
);
2355 static inline void gen_addr_register(DisasContext
*ctx
, TCGv EA
)
2357 if (rA(ctx
->opcode
) == 0) {
2358 tcg_gen_movi_tl(EA
, 0);
2360 #if defined(TARGET_PPC64)
2361 if (!ctx
->sf_mode
) {
2362 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2365 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2369 static inline void gen_addr_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
2372 tcg_gen_addi_tl(ret
, arg1
, val
);
2373 #if defined(TARGET_PPC64)
2374 if (!ctx
->sf_mode
) {
2375 tcg_gen_ext32u_tl(ret
, ret
);
2380 static inline void gen_check_align(DisasContext
*ctx
, TCGv EA
, int mask
)
2382 int l1
= gen_new_label();
2383 TCGv t0
= tcg_temp_new();
2385 /* NIP cannot be restored if the memory exception comes from an helper */
2386 gen_update_nip(ctx
, ctx
->nip
- 4);
2387 tcg_gen_andi_tl(t0
, EA
, mask
);
2388 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2389 t1
= tcg_const_i32(POWERPC_EXCP_ALIGN
);
2390 t2
= tcg_const_i32(0);
2391 gen_helper_raise_exception_err(cpu_env
, t1
, t2
);
2392 tcg_temp_free_i32(t1
);
2393 tcg_temp_free_i32(t2
);
2398 /*** Integer load ***/
2399 static inline void gen_qemu_ld8u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2401 tcg_gen_qemu_ld8u(arg1
, arg2
, ctx
->mem_idx
);
2404 static inline void gen_qemu_ld8s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2406 tcg_gen_qemu_ld8s(arg1
, arg2
, ctx
->mem_idx
);
2409 static inline void gen_qemu_ld16u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2411 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2412 if (unlikely(ctx
->le_mode
)) {
2413 tcg_gen_bswap16_tl(arg1
, arg1
);
2417 static inline void gen_qemu_ld16s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2419 if (unlikely(ctx
->le_mode
)) {
2420 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2421 tcg_gen_bswap16_tl(arg1
, arg1
);
2422 tcg_gen_ext16s_tl(arg1
, arg1
);
2424 tcg_gen_qemu_ld16s(arg1
, arg2
, ctx
->mem_idx
);
2428 static inline void gen_qemu_ld32u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2430 tcg_gen_qemu_ld32u(arg1
, arg2
, ctx
->mem_idx
);
2431 if (unlikely(ctx
->le_mode
)) {
2432 tcg_gen_bswap32_tl(arg1
, arg1
);
2436 #if defined(TARGET_PPC64)
2437 static inline void gen_qemu_ld32s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2439 if (unlikely(ctx
->le_mode
)) {
2440 tcg_gen_qemu_ld32u(arg1
, arg2
, ctx
->mem_idx
);
2441 tcg_gen_bswap32_tl(arg1
, arg1
);
2442 tcg_gen_ext32s_tl(arg1
, arg1
);
2444 tcg_gen_qemu_ld32s(arg1
, arg2
, ctx
->mem_idx
);
2448 static inline void gen_qemu_ld64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2450 tcg_gen_qemu_ld64(arg1
, arg2
, ctx
->mem_idx
);
2451 if (unlikely(ctx
->le_mode
)) {
2452 tcg_gen_bswap64_i64(arg1
, arg1
);
2456 static inline void gen_qemu_st8(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2458 tcg_gen_qemu_st8(arg1
, arg2
, ctx
->mem_idx
);
2461 static inline void gen_qemu_st16(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2463 if (unlikely(ctx
->le_mode
)) {
2464 TCGv t0
= tcg_temp_new();
2465 tcg_gen_ext16u_tl(t0
, arg1
);
2466 tcg_gen_bswap16_tl(t0
, t0
);
2467 tcg_gen_qemu_st16(t0
, arg2
, ctx
->mem_idx
);
2470 tcg_gen_qemu_st16(arg1
, arg2
, ctx
->mem_idx
);
2474 static inline void gen_qemu_st32(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2476 if (unlikely(ctx
->le_mode
)) {
2477 TCGv t0
= tcg_temp_new();
2478 tcg_gen_ext32u_tl(t0
, arg1
);
2479 tcg_gen_bswap32_tl(t0
, t0
);
2480 tcg_gen_qemu_st32(t0
, arg2
, ctx
->mem_idx
);
2483 tcg_gen_qemu_st32(arg1
, arg2
, ctx
->mem_idx
);
2487 static inline void gen_qemu_st64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2489 if (unlikely(ctx
->le_mode
)) {
2490 TCGv_i64 t0
= tcg_temp_new_i64();
2491 tcg_gen_bswap64_i64(t0
, arg1
);
2492 tcg_gen_qemu_st64(t0
, arg2
, ctx
->mem_idx
);
2493 tcg_temp_free_i64(t0
);
2495 tcg_gen_qemu_st64(arg1
, arg2
, ctx
->mem_idx
);
2498 #define GEN_LD(name, ldop, opc, type) \
2499 static void glue(gen_, name)(DisasContext *ctx) \
2502 gen_set_access_type(ctx, ACCESS_INT); \
2503 EA = tcg_temp_new(); \
2504 gen_addr_imm_index(ctx, EA, 0); \
2505 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2506 tcg_temp_free(EA); \
2509 #define GEN_LDU(name, ldop, opc, type) \
2510 static void glue(gen_, name##u)(DisasContext *ctx) \
2513 if (unlikely(rA(ctx->opcode) == 0 || \
2514 rA(ctx->opcode) == rD(ctx->opcode))) { \
2515 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2518 gen_set_access_type(ctx, ACCESS_INT); \
2519 EA = tcg_temp_new(); \
2520 if (type == PPC_64B) \
2521 gen_addr_imm_index(ctx, EA, 0x03); \
2523 gen_addr_imm_index(ctx, EA, 0); \
2524 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2525 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2526 tcg_temp_free(EA); \
2529 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2530 static void glue(gen_, name##ux)(DisasContext *ctx) \
2533 if (unlikely(rA(ctx->opcode) == 0 || \
2534 rA(ctx->opcode) == rD(ctx->opcode))) { \
2535 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2538 gen_set_access_type(ctx, ACCESS_INT); \
2539 EA = tcg_temp_new(); \
2540 gen_addr_reg_index(ctx, EA); \
2541 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2542 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2543 tcg_temp_free(EA); \
2546 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2547 static void glue(gen_, name##x)(DisasContext *ctx) \
2550 gen_set_access_type(ctx, ACCESS_INT); \
2551 EA = tcg_temp_new(); \
2552 gen_addr_reg_index(ctx, EA); \
2553 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2554 tcg_temp_free(EA); \
2556 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2557 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2559 #define GEN_LDS(name, ldop, op, type) \
2560 GEN_LD(name, ldop, op | 0x20, type); \
2561 GEN_LDU(name, ldop, op | 0x21, type); \
2562 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2563 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2565 /* lbz lbzu lbzux lbzx */
2566 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
);
2567 /* lha lhau lhaux lhax */
2568 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
);
2569 /* lhz lhzu lhzux lhzx */
2570 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
);
2571 /* lwz lwzu lwzux lwzx */
2572 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
);
2573 #if defined(TARGET_PPC64)
2575 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
);
2577 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
);
2579 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
);
2581 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
);
2583 static void gen_ld(DisasContext
*ctx
)
2586 if (Rc(ctx
->opcode
)) {
2587 if (unlikely(rA(ctx
->opcode
) == 0 ||
2588 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2589 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2593 gen_set_access_type(ctx
, ACCESS_INT
);
2594 EA
= tcg_temp_new();
2595 gen_addr_imm_index(ctx
, EA
, 0x03);
2596 if (ctx
->opcode
& 0x02) {
2597 /* lwa (lwau is undefined) */
2598 gen_qemu_ld32s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2601 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2603 if (Rc(ctx
->opcode
))
2604 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2609 static void gen_lq(DisasContext
*ctx
)
2611 #if defined(CONFIG_USER_ONLY)
2612 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2617 /* Restore CPU state */
2618 if (unlikely(ctx
->mem_idx
== 0)) {
2619 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2622 ra
= rA(ctx
->opcode
);
2623 rd
= rD(ctx
->opcode
);
2624 if (unlikely((rd
& 1) || rd
== ra
)) {
2625 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2628 if (unlikely(ctx
->le_mode
)) {
2629 /* Little-endian mode is not handled */
2630 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2633 gen_set_access_type(ctx
, ACCESS_INT
);
2634 EA
= tcg_temp_new();
2635 gen_addr_imm_index(ctx
, EA
, 0x0F);
2636 gen_qemu_ld64(ctx
, cpu_gpr
[rd
], EA
);
2637 gen_addr_add(ctx
, EA
, EA
, 8);
2638 gen_qemu_ld64(ctx
, cpu_gpr
[rd
+1], EA
);
2644 /*** Integer store ***/
2645 #define GEN_ST(name, stop, opc, type) \
2646 static void glue(gen_, name)(DisasContext *ctx) \
2649 gen_set_access_type(ctx, ACCESS_INT); \
2650 EA = tcg_temp_new(); \
2651 gen_addr_imm_index(ctx, EA, 0); \
2652 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2653 tcg_temp_free(EA); \
2656 #define GEN_STU(name, stop, opc, type) \
2657 static void glue(gen_, stop##u)(DisasContext *ctx) \
2660 if (unlikely(rA(ctx->opcode) == 0)) { \
2661 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2664 gen_set_access_type(ctx, ACCESS_INT); \
2665 EA = tcg_temp_new(); \
2666 if (type == PPC_64B) \
2667 gen_addr_imm_index(ctx, EA, 0x03); \
2669 gen_addr_imm_index(ctx, EA, 0); \
2670 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2671 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2672 tcg_temp_free(EA); \
2675 #define GEN_STUX(name, stop, opc2, opc3, type) \
2676 static void glue(gen_, name##ux)(DisasContext *ctx) \
2679 if (unlikely(rA(ctx->opcode) == 0)) { \
2680 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2683 gen_set_access_type(ctx, ACCESS_INT); \
2684 EA = tcg_temp_new(); \
2685 gen_addr_reg_index(ctx, EA); \
2686 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2687 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2688 tcg_temp_free(EA); \
2691 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2692 static void glue(gen_, name##x)(DisasContext *ctx) \
2695 gen_set_access_type(ctx, ACCESS_INT); \
2696 EA = tcg_temp_new(); \
2697 gen_addr_reg_index(ctx, EA); \
2698 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2699 tcg_temp_free(EA); \
2701 #define GEN_STX(name, stop, opc2, opc3, type) \
2702 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2704 #define GEN_STS(name, stop, op, type) \
2705 GEN_ST(name, stop, op | 0x20, type); \
2706 GEN_STU(name, stop, op | 0x21, type); \
2707 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2708 GEN_STX(name, stop, 0x17, op | 0x00, type)
2710 /* stb stbu stbux stbx */
2711 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
);
2712 /* sth sthu sthux sthx */
2713 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
);
2714 /* stw stwu stwux stwx */
2715 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
);
2716 #if defined(TARGET_PPC64)
2717 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
);
2718 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
);
2720 static void gen_std(DisasContext
*ctx
)
2725 rs
= rS(ctx
->opcode
);
2726 if ((ctx
->opcode
& 0x3) == 0x2) {
2727 #if defined(CONFIG_USER_ONLY)
2728 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2731 if (unlikely(ctx
->mem_idx
== 0)) {
2732 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2735 if (unlikely(rs
& 1)) {
2736 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2739 if (unlikely(ctx
->le_mode
)) {
2740 /* Little-endian mode is not handled */
2741 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2744 gen_set_access_type(ctx
, ACCESS_INT
);
2745 EA
= tcg_temp_new();
2746 gen_addr_imm_index(ctx
, EA
, 0x03);
2747 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
2748 gen_addr_add(ctx
, EA
, EA
, 8);
2749 gen_qemu_st64(ctx
, cpu_gpr
[rs
+1], EA
);
2754 if (Rc(ctx
->opcode
)) {
2755 if (unlikely(rA(ctx
->opcode
) == 0)) {
2756 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2760 gen_set_access_type(ctx
, ACCESS_INT
);
2761 EA
= tcg_temp_new();
2762 gen_addr_imm_index(ctx
, EA
, 0x03);
2763 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
2764 if (Rc(ctx
->opcode
))
2765 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2770 /*** Integer load and store with byte reverse ***/
2772 static inline void gen_qemu_ld16ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2774 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2775 if (likely(!ctx
->le_mode
)) {
2776 tcg_gen_bswap16_tl(arg1
, arg1
);
2779 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
);
2782 static inline void gen_qemu_ld32ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2784 tcg_gen_qemu_ld32u(arg1
, arg2
, ctx
->mem_idx
);
2785 if (likely(!ctx
->le_mode
)) {
2786 tcg_gen_bswap32_tl(arg1
, arg1
);
2789 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
);
2791 #if defined(TARGET_PPC64)
2793 static inline void gen_qemu_ld64ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2795 tcg_gen_qemu_ld64(arg1
, arg2
, ctx
->mem_idx
);
2796 if (likely(!ctx
->le_mode
)) {
2797 tcg_gen_bswap64_tl(arg1
, arg1
);
2800 GEN_LDX_E(ldbr
, ld64ur
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
);
2801 #endif /* TARGET_PPC64 */
2804 static inline void gen_qemu_st16r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2806 if (likely(!ctx
->le_mode
)) {
2807 TCGv t0
= tcg_temp_new();
2808 tcg_gen_ext16u_tl(t0
, arg1
);
2809 tcg_gen_bswap16_tl(t0
, t0
);
2810 tcg_gen_qemu_st16(t0
, arg2
, ctx
->mem_idx
);
2813 tcg_gen_qemu_st16(arg1
, arg2
, ctx
->mem_idx
);
2816 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
);
2819 static inline void gen_qemu_st32r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2821 if (likely(!ctx
->le_mode
)) {
2822 TCGv t0
= tcg_temp_new();
2823 tcg_gen_ext32u_tl(t0
, arg1
);
2824 tcg_gen_bswap32_tl(t0
, t0
);
2825 tcg_gen_qemu_st32(t0
, arg2
, ctx
->mem_idx
);
2828 tcg_gen_qemu_st32(arg1
, arg2
, ctx
->mem_idx
);
2831 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
);
2833 #if defined(TARGET_PPC64)
2835 static inline void gen_qemu_st64r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2837 if (likely(!ctx
->le_mode
)) {
2838 TCGv t0
= tcg_temp_new();
2839 tcg_gen_bswap64_tl(t0
, arg1
);
2840 tcg_gen_qemu_st64(t0
, arg2
, ctx
->mem_idx
);
2843 tcg_gen_qemu_st64(arg1
, arg2
, ctx
->mem_idx
);
2846 GEN_STX_E(stdbr
, st64r
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
);
2847 #endif /* TARGET_PPC64 */
2849 /*** Integer load and store multiple ***/
2852 static void gen_lmw(DisasContext
*ctx
)
2856 gen_set_access_type(ctx
, ACCESS_INT
);
2857 /* NIP cannot be restored if the memory exception comes from an helper */
2858 gen_update_nip(ctx
, ctx
->nip
- 4);
2859 t0
= tcg_temp_new();
2860 t1
= tcg_const_i32(rD(ctx
->opcode
));
2861 gen_addr_imm_index(ctx
, t0
, 0);
2862 gen_helper_lmw(cpu_env
, t0
, t1
);
2864 tcg_temp_free_i32(t1
);
2868 static void gen_stmw(DisasContext
*ctx
)
2872 gen_set_access_type(ctx
, ACCESS_INT
);
2873 /* NIP cannot be restored if the memory exception comes from an helper */
2874 gen_update_nip(ctx
, ctx
->nip
- 4);
2875 t0
= tcg_temp_new();
2876 t1
= tcg_const_i32(rS(ctx
->opcode
));
2877 gen_addr_imm_index(ctx
, t0
, 0);
2878 gen_helper_stmw(cpu_env
, t0
, t1
);
2880 tcg_temp_free_i32(t1
);
2883 /*** Integer load and store strings ***/
2886 /* PowerPC32 specification says we must generate an exception if
2887 * rA is in the range of registers to be loaded.
2888 * In an other hand, IBM says this is valid, but rA won't be loaded.
2889 * For now, I'll follow the spec...
2891 static void gen_lswi(DisasContext
*ctx
)
2895 int nb
= NB(ctx
->opcode
);
2896 int start
= rD(ctx
->opcode
);
2897 int ra
= rA(ctx
->opcode
);
2903 if (unlikely(((start
+ nr
) > 32 &&
2904 start
<= ra
&& (start
+ nr
- 32) > ra
) ||
2905 ((start
+ nr
) <= 32 && start
<= ra
&& (start
+ nr
) > ra
))) {
2906 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
2909 gen_set_access_type(ctx
, ACCESS_INT
);
2910 /* NIP cannot be restored if the memory exception comes from an helper */
2911 gen_update_nip(ctx
, ctx
->nip
- 4);
2912 t0
= tcg_temp_new();
2913 gen_addr_register(ctx
, t0
);
2914 t1
= tcg_const_i32(nb
);
2915 t2
= tcg_const_i32(start
);
2916 gen_helper_lsw(cpu_env
, t0
, t1
, t2
);
2918 tcg_temp_free_i32(t1
);
2919 tcg_temp_free_i32(t2
);
2923 static void gen_lswx(DisasContext
*ctx
)
2926 TCGv_i32 t1
, t2
, t3
;
2927 gen_set_access_type(ctx
, ACCESS_INT
);
2928 /* NIP cannot be restored if the memory exception comes from an helper */
2929 gen_update_nip(ctx
, ctx
->nip
- 4);
2930 t0
= tcg_temp_new();
2931 gen_addr_reg_index(ctx
, t0
);
2932 t1
= tcg_const_i32(rD(ctx
->opcode
));
2933 t2
= tcg_const_i32(rA(ctx
->opcode
));
2934 t3
= tcg_const_i32(rB(ctx
->opcode
));
2935 gen_helper_lswx(cpu_env
, t0
, t1
, t2
, t3
);
2937 tcg_temp_free_i32(t1
);
2938 tcg_temp_free_i32(t2
);
2939 tcg_temp_free_i32(t3
);
2943 static void gen_stswi(DisasContext
*ctx
)
2947 int nb
= NB(ctx
->opcode
);
2948 gen_set_access_type(ctx
, ACCESS_INT
);
2949 /* NIP cannot be restored if the memory exception comes from an helper */
2950 gen_update_nip(ctx
, ctx
->nip
- 4);
2951 t0
= tcg_temp_new();
2952 gen_addr_register(ctx
, t0
);
2955 t1
= tcg_const_i32(nb
);
2956 t2
= tcg_const_i32(rS(ctx
->opcode
));
2957 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
2959 tcg_temp_free_i32(t1
);
2960 tcg_temp_free_i32(t2
);
2964 static void gen_stswx(DisasContext
*ctx
)
2968 gen_set_access_type(ctx
, ACCESS_INT
);
2969 /* NIP cannot be restored if the memory exception comes from an helper */
2970 gen_update_nip(ctx
, ctx
->nip
- 4);
2971 t0
= tcg_temp_new();
2972 gen_addr_reg_index(ctx
, t0
);
2973 t1
= tcg_temp_new_i32();
2974 tcg_gen_trunc_tl_i32(t1
, cpu_xer
);
2975 tcg_gen_andi_i32(t1
, t1
, 0x7F);
2976 t2
= tcg_const_i32(rS(ctx
->opcode
));
2977 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
2979 tcg_temp_free_i32(t1
);
2980 tcg_temp_free_i32(t2
);
2983 /*** Memory synchronisation ***/
2985 static void gen_eieio(DisasContext
*ctx
)
2990 static void gen_isync(DisasContext
*ctx
)
2992 gen_stop_exception(ctx
);
2996 static void gen_lwarx(DisasContext
*ctx
)
2999 TCGv gpr
= cpu_gpr
[rD(ctx
->opcode
)];
3000 gen_set_access_type(ctx
, ACCESS_RES
);
3001 t0
= tcg_temp_local_new();
3002 gen_addr_reg_index(ctx
, t0
);
3003 gen_check_align(ctx
, t0
, 0x03);
3004 gen_qemu_ld32u(ctx
, gpr
, t0
);
3005 tcg_gen_mov_tl(cpu_reserve
, t0
);
3006 tcg_gen_st_tl(gpr
, cpu_env
, offsetof(CPUPPCState
, reserve_val
));
3010 #if defined(CONFIG_USER_ONLY)
3011 static void gen_conditional_store (DisasContext
*ctx
, TCGv EA
,
3014 TCGv t0
= tcg_temp_new();
3015 uint32_t save_exception
= ctx
->exception
;
3017 tcg_gen_st_tl(EA
, cpu_env
, offsetof(CPUPPCState
, reserve_ea
));
3018 tcg_gen_movi_tl(t0
, (size
<< 5) | reg
);
3019 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUPPCState
, reserve_info
));
3021 gen_update_nip(ctx
, ctx
->nip
-4);
3022 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3023 gen_exception(ctx
, POWERPC_EXCP_STCX
);
3024 ctx
->exception
= save_exception
;
3029 static void gen_stwcx_(DisasContext
*ctx
)
3032 gen_set_access_type(ctx
, ACCESS_RES
);
3033 t0
= tcg_temp_local_new();
3034 gen_addr_reg_index(ctx
, t0
);
3035 gen_check_align(ctx
, t0
, 0x03);
3036 #if defined(CONFIG_USER_ONLY)
3037 gen_conditional_store(ctx
, t0
, rS(ctx
->opcode
), 4);
3042 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3043 l1
= gen_new_label();
3044 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, cpu_reserve
, l1
);
3045 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
3046 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
3048 tcg_gen_movi_tl(cpu_reserve
, -1);
3054 #if defined(TARGET_PPC64)
3056 static void gen_ldarx(DisasContext
*ctx
)
3059 TCGv gpr
= cpu_gpr
[rD(ctx
->opcode
)];
3060 gen_set_access_type(ctx
, ACCESS_RES
);
3061 t0
= tcg_temp_local_new();
3062 gen_addr_reg_index(ctx
, t0
);
3063 gen_check_align(ctx
, t0
, 0x07);
3064 gen_qemu_ld64(ctx
, gpr
, t0
);
3065 tcg_gen_mov_tl(cpu_reserve
, t0
);
3066 tcg_gen_st_tl(gpr
, cpu_env
, offsetof(CPUPPCState
, reserve_val
));
3071 static void gen_stdcx_(DisasContext
*ctx
)
3074 gen_set_access_type(ctx
, ACCESS_RES
);
3075 t0
= tcg_temp_local_new();
3076 gen_addr_reg_index(ctx
, t0
);
3077 gen_check_align(ctx
, t0
, 0x07);
3078 #if defined(CONFIG_USER_ONLY)
3079 gen_conditional_store(ctx
, t0
, rS(ctx
->opcode
), 8);
3083 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3084 l1
= gen_new_label();
3085 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, cpu_reserve
, l1
);
3086 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
3087 gen_qemu_st64(ctx
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
3089 tcg_gen_movi_tl(cpu_reserve
, -1);
3094 #endif /* defined(TARGET_PPC64) */
3097 static void gen_sync(DisasContext
*ctx
)
3102 static void gen_wait(DisasContext
*ctx
)
3104 TCGv_i32 t0
= tcg_temp_new_i32();
3105 tcg_gen_st_i32(t0
, cpu_env
, offsetof(CPUPPCState
, halted
));
3106 tcg_temp_free_i32(t0
);
3107 /* Stop translation, as the CPU is supposed to sleep from now */
3108 gen_exception_err(ctx
, EXCP_HLT
, 1);
3111 /*** Floating-point load ***/
3112 #define GEN_LDF(name, ldop, opc, type) \
3113 static void glue(gen_, name)(DisasContext *ctx) \
3116 if (unlikely(!ctx->fpu_enabled)) { \
3117 gen_exception(ctx, POWERPC_EXCP_FPU); \
3120 gen_set_access_type(ctx, ACCESS_FLOAT); \
3121 EA = tcg_temp_new(); \
3122 gen_addr_imm_index(ctx, EA, 0); \
3123 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3124 tcg_temp_free(EA); \
3127 #define GEN_LDUF(name, ldop, opc, type) \
3128 static void glue(gen_, name##u)(DisasContext *ctx) \
3131 if (unlikely(!ctx->fpu_enabled)) { \
3132 gen_exception(ctx, POWERPC_EXCP_FPU); \
3135 if (unlikely(rA(ctx->opcode) == 0)) { \
3136 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3139 gen_set_access_type(ctx, ACCESS_FLOAT); \
3140 EA = tcg_temp_new(); \
3141 gen_addr_imm_index(ctx, EA, 0); \
3142 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3143 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3144 tcg_temp_free(EA); \
3147 #define GEN_LDUXF(name, ldop, opc, type) \
3148 static void glue(gen_, name##ux)(DisasContext *ctx) \
3151 if (unlikely(!ctx->fpu_enabled)) { \
3152 gen_exception(ctx, POWERPC_EXCP_FPU); \
3155 if (unlikely(rA(ctx->opcode) == 0)) { \
3156 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3159 gen_set_access_type(ctx, ACCESS_FLOAT); \
3160 EA = tcg_temp_new(); \
3161 gen_addr_reg_index(ctx, EA); \
3162 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3163 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3164 tcg_temp_free(EA); \
3167 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3168 static void glue(gen_, name##x)(DisasContext *ctx) \
3171 if (unlikely(!ctx->fpu_enabled)) { \
3172 gen_exception(ctx, POWERPC_EXCP_FPU); \
3175 gen_set_access_type(ctx, ACCESS_FLOAT); \
3176 EA = tcg_temp_new(); \
3177 gen_addr_reg_index(ctx, EA); \
3178 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3179 tcg_temp_free(EA); \
3182 #define GEN_LDFS(name, ldop, op, type) \
3183 GEN_LDF(name, ldop, op | 0x20, type); \
3184 GEN_LDUF(name, ldop, op | 0x21, type); \
3185 GEN_LDUXF(name, ldop, op | 0x01, type); \
3186 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3188 static inline void gen_qemu_ld32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3190 TCGv t0
= tcg_temp_new();
3191 TCGv_i32 t1
= tcg_temp_new_i32();
3192 gen_qemu_ld32u(ctx
, t0
, arg2
);
3193 tcg_gen_trunc_tl_i32(t1
, t0
);
3195 gen_helper_float32_to_float64(arg1
, cpu_env
, t1
);
3196 tcg_temp_free_i32(t1
);
3199 /* lfd lfdu lfdux lfdx */
3200 GEN_LDFS(lfd
, ld64
, 0x12, PPC_FLOAT
);
3201 /* lfs lfsu lfsux lfsx */
3202 GEN_LDFS(lfs
, ld32fs
, 0x10, PPC_FLOAT
);
3204 /*** Floating-point store ***/
3205 #define GEN_STF(name, stop, opc, type) \
3206 static void glue(gen_, name)(DisasContext *ctx) \
3209 if (unlikely(!ctx->fpu_enabled)) { \
3210 gen_exception(ctx, POWERPC_EXCP_FPU); \
3213 gen_set_access_type(ctx, ACCESS_FLOAT); \
3214 EA = tcg_temp_new(); \
3215 gen_addr_imm_index(ctx, EA, 0); \
3216 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3217 tcg_temp_free(EA); \
3220 #define GEN_STUF(name, stop, opc, type) \
3221 static void glue(gen_, name##u)(DisasContext *ctx) \
3224 if (unlikely(!ctx->fpu_enabled)) { \
3225 gen_exception(ctx, POWERPC_EXCP_FPU); \
3228 if (unlikely(rA(ctx->opcode) == 0)) { \
3229 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3232 gen_set_access_type(ctx, ACCESS_FLOAT); \
3233 EA = tcg_temp_new(); \
3234 gen_addr_imm_index(ctx, EA, 0); \
3235 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3236 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3237 tcg_temp_free(EA); \
3240 #define GEN_STUXF(name, stop, opc, type) \
3241 static void glue(gen_, name##ux)(DisasContext *ctx) \
3244 if (unlikely(!ctx->fpu_enabled)) { \
3245 gen_exception(ctx, POWERPC_EXCP_FPU); \
3248 if (unlikely(rA(ctx->opcode) == 0)) { \
3249 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3252 gen_set_access_type(ctx, ACCESS_FLOAT); \
3253 EA = tcg_temp_new(); \
3254 gen_addr_reg_index(ctx, EA); \
3255 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3256 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3257 tcg_temp_free(EA); \
3260 #define GEN_STXF(name, stop, opc2, opc3, type) \
3261 static void glue(gen_, name##x)(DisasContext *ctx) \
3264 if (unlikely(!ctx->fpu_enabled)) { \
3265 gen_exception(ctx, POWERPC_EXCP_FPU); \
3268 gen_set_access_type(ctx, ACCESS_FLOAT); \
3269 EA = tcg_temp_new(); \
3270 gen_addr_reg_index(ctx, EA); \
3271 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3272 tcg_temp_free(EA); \
3275 #define GEN_STFS(name, stop, op, type) \
3276 GEN_STF(name, stop, op | 0x20, type); \
3277 GEN_STUF(name, stop, op | 0x21, type); \
3278 GEN_STUXF(name, stop, op | 0x01, type); \
3279 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3281 static inline void gen_qemu_st32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3283 TCGv_i32 t0
= tcg_temp_new_i32();
3284 TCGv t1
= tcg_temp_new();
3285 gen_helper_float64_to_float32(t0
, cpu_env
, arg1
);
3286 tcg_gen_extu_i32_tl(t1
, t0
);
3287 tcg_temp_free_i32(t0
);
3288 gen_qemu_st32(ctx
, t1
, arg2
);
3292 /* stfd stfdu stfdux stfdx */
3293 GEN_STFS(stfd
, st64
, 0x16, PPC_FLOAT
);
3294 /* stfs stfsu stfsux stfsx */
3295 GEN_STFS(stfs
, st32fs
, 0x14, PPC_FLOAT
);
3298 static inline void gen_qemu_st32fiw(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3300 TCGv t0
= tcg_temp_new();
3301 tcg_gen_trunc_i64_tl(t0
, arg1
),
3302 gen_qemu_st32(ctx
, t0
, arg2
);
3306 GEN_STXF(stfiw
, st32fiw
, 0x17, 0x1E, PPC_FLOAT_STFIWX
);
3308 static inline void gen_update_cfar(DisasContext
*ctx
, target_ulong nip
)
3310 #if defined(TARGET_PPC64)
3312 tcg_gen_movi_tl(cpu_cfar
, nip
);
3317 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
3319 TranslationBlock
*tb
;
3321 #if defined(TARGET_PPC64)
3323 dest
= (uint32_t) dest
;
3325 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) &&
3326 likely(!ctx
->singlestep_enabled
)) {
3328 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3329 tcg_gen_exit_tb((tcg_target_long
)tb
+ n
);
3331 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3332 if (unlikely(ctx
->singlestep_enabled
)) {
3333 if ((ctx
->singlestep_enabled
&
3334 (CPU_BRANCH_STEP
| CPU_SINGLE_STEP
)) &&
3335 (ctx
->exception
== POWERPC_EXCP_BRANCH
||
3336 ctx
->exception
== POWERPC_EXCP_TRACE
)) {
3337 target_ulong tmp
= ctx
->nip
;
3339 gen_exception(ctx
, POWERPC_EXCP_TRACE
);
3342 if (ctx
->singlestep_enabled
& GDBSTUB_SINGLE_STEP
) {
3343 gen_debug_exception(ctx
);
3350 static inline void gen_setlr(DisasContext
*ctx
, target_ulong nip
)
3352 #if defined(TARGET_PPC64)
3353 if (ctx
->sf_mode
== 0)
3354 tcg_gen_movi_tl(cpu_lr
, (uint32_t)nip
);
3357 tcg_gen_movi_tl(cpu_lr
, nip
);
3361 static void gen_b(DisasContext
*ctx
)
3363 target_ulong li
, target
;
3365 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3366 /* sign extend LI */
3367 #if defined(TARGET_PPC64)
3369 li
= ((int64_t)LI(ctx
->opcode
) << 38) >> 38;
3372 li
= ((int32_t)LI(ctx
->opcode
) << 6) >> 6;
3373 if (likely(AA(ctx
->opcode
) == 0))
3374 target
= ctx
->nip
+ li
- 4;
3377 if (LK(ctx
->opcode
))
3378 gen_setlr(ctx
, ctx
->nip
);
3379 gen_update_cfar(ctx
, ctx
->nip
);
3380 gen_goto_tb(ctx
, 0, target
);
3387 static inline void gen_bcond(DisasContext
*ctx
, int type
)
3389 uint32_t bo
= BO(ctx
->opcode
);
3393 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3394 if (type
== BCOND_LR
|| type
== BCOND_CTR
) {
3395 target
= tcg_temp_local_new();
3396 if (type
== BCOND_CTR
)
3397 tcg_gen_mov_tl(target
, cpu_ctr
);
3399 tcg_gen_mov_tl(target
, cpu_lr
);
3401 TCGV_UNUSED(target
);
3403 if (LK(ctx
->opcode
))
3404 gen_setlr(ctx
, ctx
->nip
);
3405 l1
= gen_new_label();
3406 if ((bo
& 0x4) == 0) {
3407 /* Decrement and test CTR */
3408 TCGv temp
= tcg_temp_new();
3409 if (unlikely(type
== BCOND_CTR
)) {
3410 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3413 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
3414 #if defined(TARGET_PPC64)
3416 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
3419 tcg_gen_mov_tl(temp
, cpu_ctr
);
3421 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
3423 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
3425 tcg_temp_free(temp
);
3427 if ((bo
& 0x10) == 0) {
3429 uint32_t bi
= BI(ctx
->opcode
);
3430 uint32_t mask
= 1 << (3 - (bi
& 0x03));
3431 TCGv_i32 temp
= tcg_temp_new_i32();
3434 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3435 tcg_gen_brcondi_i32(TCG_COND_EQ
, temp
, 0, l1
);
3437 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3438 tcg_gen_brcondi_i32(TCG_COND_NE
, temp
, 0, l1
);
3440 tcg_temp_free_i32(temp
);
3442 gen_update_cfar(ctx
, ctx
->nip
);
3443 if (type
== BCOND_IM
) {
3444 target_ulong li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
3445 if (likely(AA(ctx
->opcode
) == 0)) {
3446 gen_goto_tb(ctx
, 0, ctx
->nip
+ li
- 4);
3448 gen_goto_tb(ctx
, 0, li
);
3451 gen_goto_tb(ctx
, 1, ctx
->nip
);
3453 #if defined(TARGET_PPC64)
3454 if (!(ctx
->sf_mode
))
3455 tcg_gen_andi_tl(cpu_nip
, target
, (uint32_t)~3);
3458 tcg_gen_andi_tl(cpu_nip
, target
, ~3);
3461 #if defined(TARGET_PPC64)
3462 if (!(ctx
->sf_mode
))
3463 tcg_gen_movi_tl(cpu_nip
, (uint32_t)ctx
->nip
);
3466 tcg_gen_movi_tl(cpu_nip
, ctx
->nip
);
3471 static void gen_bc(DisasContext
*ctx
)
3473 gen_bcond(ctx
, BCOND_IM
);
3476 static void gen_bcctr(DisasContext
*ctx
)
3478 gen_bcond(ctx
, BCOND_CTR
);
3481 static void gen_bclr(DisasContext
*ctx
)
3483 gen_bcond(ctx
, BCOND_LR
);
3486 /*** Condition register logical ***/
3487 #define GEN_CRLOGIC(name, tcg_op, opc) \
3488 static void glue(gen_, name)(DisasContext *ctx) \
3493 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3494 t0 = tcg_temp_new_i32(); \
3496 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3498 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3500 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3501 t1 = tcg_temp_new_i32(); \
3502 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3504 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3506 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3508 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3509 tcg_op(t0, t0, t1); \
3510 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3511 tcg_gen_andi_i32(t0, t0, bitmask); \
3512 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3513 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3514 tcg_temp_free_i32(t0); \
3515 tcg_temp_free_i32(t1); \
3519 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08);
3521 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04);
3523 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09);
3525 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07);
3527 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01);
3529 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E);
3531 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D);
3533 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06);
3536 static void gen_mcrf(DisasContext
*ctx
)
3538 tcg_gen_mov_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfS(ctx
->opcode
)]);
3541 /*** System linkage ***/
3543 /* rfi (mem_idx only) */
3544 static void gen_rfi(DisasContext
*ctx
)
3546 #if defined(CONFIG_USER_ONLY)
3547 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3549 /* Restore CPU state */
3550 if (unlikely(!ctx
->mem_idx
)) {
3551 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3554 gen_update_cfar(ctx
, ctx
->nip
);
3555 gen_helper_rfi(cpu_env
);
3556 gen_sync_exception(ctx
);
3560 #if defined(TARGET_PPC64)
3561 static void gen_rfid(DisasContext
*ctx
)
3563 #if defined(CONFIG_USER_ONLY)
3564 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3566 /* Restore CPU state */
3567 if (unlikely(!ctx
->mem_idx
)) {
3568 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3571 gen_update_cfar(ctx
, ctx
->nip
);
3572 gen_helper_rfid(cpu_env
);
3573 gen_sync_exception(ctx
);
3577 static void gen_hrfid(DisasContext
*ctx
)
3579 #if defined(CONFIG_USER_ONLY)
3580 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3582 /* Restore CPU state */
3583 if (unlikely(ctx
->mem_idx
<= 1)) {
3584 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3587 gen_helper_hrfid(cpu_env
);
3588 gen_sync_exception(ctx
);
3594 #if defined(CONFIG_USER_ONLY)
3595 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3597 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3599 static void gen_sc(DisasContext
*ctx
)
3603 lev
= (ctx
->opcode
>> 5) & 0x7F;
3604 gen_exception_err(ctx
, POWERPC_SYSCALL
, lev
);
3610 static void gen_tw(DisasContext
*ctx
)
3612 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
3613 /* Update the nip since this might generate a trap exception */
3614 gen_update_nip(ctx
, ctx
->nip
);
3615 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
3617 tcg_temp_free_i32(t0
);
3621 static void gen_twi(DisasContext
*ctx
)
3623 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3624 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
3625 /* Update the nip since this might generate a trap exception */
3626 gen_update_nip(ctx
, ctx
->nip
);
3627 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3629 tcg_temp_free_i32(t1
);
3632 #if defined(TARGET_PPC64)
3634 static void gen_td(DisasContext
*ctx
)
3636 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
3637 /* Update the nip since this might generate a trap exception */
3638 gen_update_nip(ctx
, ctx
->nip
);
3639 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
3641 tcg_temp_free_i32(t0
);
3645 static void gen_tdi(DisasContext
*ctx
)
3647 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3648 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
3649 /* Update the nip since this might generate a trap exception */
3650 gen_update_nip(ctx
, ctx
->nip
);
3651 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3653 tcg_temp_free_i32(t1
);
3657 /*** Processor control ***/
3659 static void gen_read_xer(TCGv dst
)
3661 TCGv t0
= tcg_temp_new();
3662 TCGv t1
= tcg_temp_new();
3663 TCGv t2
= tcg_temp_new();
3664 tcg_gen_mov_tl(dst
, cpu_xer
);
3665 tcg_gen_shli_tl(t0
, cpu_so
, XER_SO
);
3666 tcg_gen_shli_tl(t1
, cpu_ov
, XER_OV
);
3667 tcg_gen_shli_tl(t2
, cpu_ca
, XER_CA
);
3668 tcg_gen_or_tl(t0
, t0
, t1
);
3669 tcg_gen_or_tl(dst
, dst
, t2
);
3670 tcg_gen_or_tl(dst
, dst
, t0
);
3676 static void gen_write_xer(TCGv src
)
3678 tcg_gen_andi_tl(cpu_xer
, src
,
3679 ~((1u << XER_SO
) | (1u << XER_OV
) | (1u << XER_CA
)));
3680 tcg_gen_shri_tl(cpu_so
, src
, XER_SO
);
3681 tcg_gen_shri_tl(cpu_ov
, src
, XER_OV
);
3682 tcg_gen_shri_tl(cpu_ca
, src
, XER_CA
);
3683 tcg_gen_andi_tl(cpu_so
, cpu_so
, 1);
3684 tcg_gen_andi_tl(cpu_ov
, cpu_ov
, 1);
3685 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
3689 static void gen_mcrxr(DisasContext
*ctx
)
3691 TCGv_i32 t0
= tcg_temp_new_i32();
3692 TCGv_i32 t1
= tcg_temp_new_i32();
3693 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
3695 tcg_gen_trunc_tl_i32(t0
, cpu_so
);
3696 tcg_gen_trunc_tl_i32(t1
, cpu_ov
);
3697 tcg_gen_trunc_tl_i32(dst
, cpu_ca
);
3698 tcg_gen_shri_i32(t0
, t0
, 2);
3699 tcg_gen_shri_i32(t1
, t1
, 1);
3700 tcg_gen_or_i32(dst
, dst
, t0
);
3701 tcg_gen_or_i32(dst
, dst
, t1
);
3702 tcg_temp_free_i32(t0
);
3703 tcg_temp_free_i32(t1
);
3705 tcg_gen_movi_tl(cpu_so
, 0);
3706 tcg_gen_movi_tl(cpu_ov
, 0);
3707 tcg_gen_movi_tl(cpu_ca
, 0);
3711 static void gen_mfcr(DisasContext
*ctx
)
3715 if (likely(ctx
->opcode
& 0x00100000)) {
3716 crm
= CRM(ctx
->opcode
);
3717 if (likely(crm
&& ((crm
& (crm
- 1)) == 0))) {
3719 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_crf
[7 - crn
]);
3720 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)],
3721 cpu_gpr
[rD(ctx
->opcode
)], crn
* 4);
3724 TCGv_i32 t0
= tcg_temp_new_i32();
3725 tcg_gen_mov_i32(t0
, cpu_crf
[0]);
3726 tcg_gen_shli_i32(t0
, t0
, 4);
3727 tcg_gen_or_i32(t0
, t0
, cpu_crf
[1]);
3728 tcg_gen_shli_i32(t0
, t0
, 4);
3729 tcg_gen_or_i32(t0
, t0
, cpu_crf
[2]);
3730 tcg_gen_shli_i32(t0
, t0
, 4);
3731 tcg_gen_or_i32(t0
, t0
, cpu_crf
[3]);
3732 tcg_gen_shli_i32(t0
, t0
, 4);
3733 tcg_gen_or_i32(t0
, t0
, cpu_crf
[4]);
3734 tcg_gen_shli_i32(t0
, t0
, 4);
3735 tcg_gen_or_i32(t0
, t0
, cpu_crf
[5]);
3736 tcg_gen_shli_i32(t0
, t0
, 4);
3737 tcg_gen_or_i32(t0
, t0
, cpu_crf
[6]);
3738 tcg_gen_shli_i32(t0
, t0
, 4);
3739 tcg_gen_or_i32(t0
, t0
, cpu_crf
[7]);
3740 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
3741 tcg_temp_free_i32(t0
);
3746 static void gen_mfmsr(DisasContext
*ctx
)
3748 #if defined(CONFIG_USER_ONLY)
3749 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3751 if (unlikely(!ctx
->mem_idx
)) {
3752 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3755 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_msr
);
3759 static void spr_noaccess(void *opaque
, int gprn
, int sprn
)
3762 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
3763 printf("ERROR: try to access SPR %d !\n", sprn
);
3766 #define SPR_NOACCESS (&spr_noaccess)
3769 static inline void gen_op_mfspr(DisasContext
*ctx
)
3771 void (*read_cb
)(void *opaque
, int gprn
, int sprn
);
3772 uint32_t sprn
= SPR(ctx
->opcode
);
3774 #if !defined(CONFIG_USER_ONLY)
3775 if (ctx
->mem_idx
== 2)
3776 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
3777 else if (ctx
->mem_idx
)
3778 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
3781 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
3782 if (likely(read_cb
!= NULL
)) {
3783 if (likely(read_cb
!= SPR_NOACCESS
)) {
3784 (*read_cb
)(ctx
, rD(ctx
->opcode
), sprn
);
3786 /* Privilege exception */
3787 /* This is a hack to avoid warnings when running Linux:
3788 * this OS breaks the PowerPC virtualisation model,
3789 * allowing userland application to read the PVR
3791 if (sprn
!= SPR_PVR
) {
3792 qemu_log("Trying to read privileged spr %d %03x at "
3793 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
);
3794 printf("Trying to read privileged spr %d %03x at "
3795 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
);
3797 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3801 qemu_log("Trying to read invalid spr %d %03x at "
3802 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
);
3803 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx
"\n",
3804 sprn
, sprn
, ctx
->nip
);
3805 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
3809 static void gen_mfspr(DisasContext
*ctx
)
3815 static void gen_mftb(DisasContext
*ctx
)
3821 static void gen_mtcrf(DisasContext
*ctx
)
3825 crm
= CRM(ctx
->opcode
);
3826 if (likely((ctx
->opcode
& 0x00100000))) {
3827 if (crm
&& ((crm
& (crm
- 1)) == 0)) {
3828 TCGv_i32 temp
= tcg_temp_new_i32();
3830 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
3831 tcg_gen_shri_i32(temp
, temp
, crn
* 4);
3832 tcg_gen_andi_i32(cpu_crf
[7 - crn
], temp
, 0xf);
3833 tcg_temp_free_i32(temp
);
3836 TCGv_i32 temp
= tcg_temp_new_i32();
3837 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
3838 for (crn
= 0 ; crn
< 8 ; crn
++) {
3839 if (crm
& (1 << crn
)) {
3840 tcg_gen_shri_i32(cpu_crf
[7 - crn
], temp
, crn
* 4);
3841 tcg_gen_andi_i32(cpu_crf
[7 - crn
], cpu_crf
[7 - crn
], 0xf);
3844 tcg_temp_free_i32(temp
);
3849 #if defined(TARGET_PPC64)
3850 static void gen_mtmsrd(DisasContext
*ctx
)
3852 #if defined(CONFIG_USER_ONLY)
3853 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3855 if (unlikely(!ctx
->mem_idx
)) {
3856 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3859 if (ctx
->opcode
& 0x00010000) {
3860 /* Special form that does not need any synchronisation */
3861 TCGv t0
= tcg_temp_new();
3862 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
3863 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~((1 << MSR_RI
) | (1 << MSR_EE
)));
3864 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
3867 /* XXX: we need to update nip before the store
3868 * if we enter power saving mode, we will exit the loop
3869 * directly from ppc_store_msr
3871 gen_update_nip(ctx
, ctx
->nip
);
3872 gen_helper_store_msr(cpu_env
, cpu_gpr
[rS(ctx
->opcode
)]);
3873 /* Must stop the translation as machine state (may have) changed */
3874 /* Note that mtmsr is not always defined as context-synchronizing */
3875 gen_stop_exception(ctx
);
3881 static void gen_mtmsr(DisasContext
*ctx
)
3883 #if defined(CONFIG_USER_ONLY)
3884 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3886 if (unlikely(!ctx
->mem_idx
)) {
3887 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3890 if (ctx
->opcode
& 0x00010000) {
3891 /* Special form that does not need any synchronisation */
3892 TCGv t0
= tcg_temp_new();
3893 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
3894 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~((1 << MSR_RI
) | (1 << MSR_EE
)));
3895 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
3898 TCGv msr
= tcg_temp_new();
3900 /* XXX: we need to update nip before the store
3901 * if we enter power saving mode, we will exit the loop
3902 * directly from ppc_store_msr
3904 gen_update_nip(ctx
, ctx
->nip
);
3905 #if defined(TARGET_PPC64)
3906 tcg_gen_deposit_tl(msr
, cpu_msr
, cpu_gpr
[rS(ctx
->opcode
)], 0, 32);
3908 tcg_gen_mov_tl(msr
, cpu_gpr
[rS(ctx
->opcode
)]);
3910 gen_helper_store_msr(cpu_env
, msr
);
3911 /* Must stop the translation as machine state (may have) changed */
3912 /* Note that mtmsr is not always defined as context-synchronizing */
3913 gen_stop_exception(ctx
);
3919 static void gen_mtspr(DisasContext
*ctx
)
3921 void (*write_cb
)(void *opaque
, int sprn
, int gprn
);
3922 uint32_t sprn
= SPR(ctx
->opcode
);
3924 #if !defined(CONFIG_USER_ONLY)
3925 if (ctx
->mem_idx
== 2)
3926 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
3927 else if (ctx
->mem_idx
)
3928 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
3931 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
3932 if (likely(write_cb
!= NULL
)) {
3933 if (likely(write_cb
!= SPR_NOACCESS
)) {
3934 (*write_cb
)(ctx
, sprn
, rS(ctx
->opcode
));
3936 /* Privilege exception */
3937 qemu_log("Trying to write privileged spr %d %03x at "
3938 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
);
3939 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
3940 "\n", sprn
, sprn
, ctx
->nip
);
3941 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3945 qemu_log("Trying to write invalid spr %d %03x at "
3946 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
);
3947 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx
"\n",
3948 sprn
, sprn
, ctx
->nip
);
3949 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
3953 /*** Cache management ***/
3956 static void gen_dcbf(DisasContext
*ctx
)
3958 /* XXX: specification says this is treated as a load by the MMU */
3960 gen_set_access_type(ctx
, ACCESS_CACHE
);
3961 t0
= tcg_temp_new();
3962 gen_addr_reg_index(ctx
, t0
);
3963 gen_qemu_ld8u(ctx
, t0
, t0
);
3967 /* dcbi (Supervisor only) */
3968 static void gen_dcbi(DisasContext
*ctx
)
3970 #if defined(CONFIG_USER_ONLY)
3971 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3974 if (unlikely(!ctx
->mem_idx
)) {
3975 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3978 EA
= tcg_temp_new();
3979 gen_set_access_type(ctx
, ACCESS_CACHE
);
3980 gen_addr_reg_index(ctx
, EA
);
3981 val
= tcg_temp_new();
3982 /* XXX: specification says this should be treated as a store by the MMU */
3983 gen_qemu_ld8u(ctx
, val
, EA
);
3984 gen_qemu_st8(ctx
, val
, EA
);
3991 static void gen_dcbst(DisasContext
*ctx
)
3993 /* XXX: specification say this is treated as a load by the MMU */
3995 gen_set_access_type(ctx
, ACCESS_CACHE
);
3996 t0
= tcg_temp_new();
3997 gen_addr_reg_index(ctx
, t0
);
3998 gen_qemu_ld8u(ctx
, t0
, t0
);
4003 static void gen_dcbt(DisasContext
*ctx
)
4005 /* interpreted as no-op */
4006 /* XXX: specification say this is treated as a load by the MMU
4007 * but does not generate any exception
4012 static void gen_dcbtst(DisasContext
*ctx
)
4014 /* interpreted as no-op */
4015 /* XXX: specification say this is treated as a load by the MMU
4016 * but does not generate any exception
4021 static void gen_dcbz(DisasContext
*ctx
)
4024 TCGv_i32 tcgv_is_dcbzl
;
4025 int is_dcbzl
= ctx
->opcode
& 0x00200000 ? 1 : 0;
4027 gen_set_access_type(ctx
, ACCESS_CACHE
);
4028 /* NIP cannot be restored if the memory exception comes from an helper */
4029 gen_update_nip(ctx
, ctx
->nip
- 4);
4030 tcgv_addr
= tcg_temp_new();
4031 tcgv_is_dcbzl
= tcg_const_i32(is_dcbzl
);
4033 gen_addr_reg_index(ctx
, tcgv_addr
);
4034 gen_helper_dcbz(cpu_env
, tcgv_addr
, tcgv_is_dcbzl
);
4036 tcg_temp_free(tcgv_addr
);
4037 tcg_temp_free_i32(tcgv_is_dcbzl
);
4041 static void gen_dst(DisasContext
*ctx
)
4043 if (rA(ctx
->opcode
) == 0) {
4044 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4046 /* interpreted as no-op */
4051 static void gen_dstst(DisasContext
*ctx
)
4053 if (rA(ctx
->opcode
) == 0) {
4054 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4056 /* interpreted as no-op */
4062 static void gen_dss(DisasContext
*ctx
)
4064 /* interpreted as no-op */
4068 static void gen_icbi(DisasContext
*ctx
)
4071 gen_set_access_type(ctx
, ACCESS_CACHE
);
4072 /* NIP cannot be restored if the memory exception comes from an helper */
4073 gen_update_nip(ctx
, ctx
->nip
- 4);
4074 t0
= tcg_temp_new();
4075 gen_addr_reg_index(ctx
, t0
);
4076 gen_helper_icbi(cpu_env
, t0
);
4082 static void gen_dcba(DisasContext
*ctx
)
4084 /* interpreted as no-op */
4085 /* XXX: specification say this is treated as a store by the MMU
4086 * but does not generate any exception
4090 /*** Segment register manipulation ***/
4091 /* Supervisor only: */
4094 static void gen_mfsr(DisasContext
*ctx
)
4096 #if defined(CONFIG_USER_ONLY)
4097 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4100 if (unlikely(!ctx
->mem_idx
)) {
4101 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4104 t0
= tcg_const_tl(SR(ctx
->opcode
));
4105 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4111 static void gen_mfsrin(DisasContext
*ctx
)
4113 #if defined(CONFIG_USER_ONLY)
4114 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4117 if (unlikely(!ctx
->mem_idx
)) {
4118 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4121 t0
= tcg_temp_new();
4122 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4123 tcg_gen_andi_tl(t0
, t0
, 0xF);
4124 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4130 static void gen_mtsr(DisasContext
*ctx
)
4132 #if defined(CONFIG_USER_ONLY)
4133 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4136 if (unlikely(!ctx
->mem_idx
)) {
4137 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4140 t0
= tcg_const_tl(SR(ctx
->opcode
));
4141 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4147 static void gen_mtsrin(DisasContext
*ctx
)
4149 #if defined(CONFIG_USER_ONLY)
4150 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4153 if (unlikely(!ctx
->mem_idx
)) {
4154 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4157 t0
= tcg_temp_new();
4158 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4159 tcg_gen_andi_tl(t0
, t0
, 0xF);
4160 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rD(ctx
->opcode
)]);
4165 #if defined(TARGET_PPC64)
4166 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4169 static void gen_mfsr_64b(DisasContext
*ctx
)
4171 #if defined(CONFIG_USER_ONLY)
4172 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4175 if (unlikely(!ctx
->mem_idx
)) {
4176 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4179 t0
= tcg_const_tl(SR(ctx
->opcode
));
4180 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4186 static void gen_mfsrin_64b(DisasContext
*ctx
)
4188 #if defined(CONFIG_USER_ONLY)
4189 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4192 if (unlikely(!ctx
->mem_idx
)) {
4193 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4196 t0
= tcg_temp_new();
4197 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4198 tcg_gen_andi_tl(t0
, t0
, 0xF);
4199 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4205 static void gen_mtsr_64b(DisasContext
*ctx
)
4207 #if defined(CONFIG_USER_ONLY)
4208 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4211 if (unlikely(!ctx
->mem_idx
)) {
4212 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4215 t0
= tcg_const_tl(SR(ctx
->opcode
));
4216 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4222 static void gen_mtsrin_64b(DisasContext
*ctx
)
4224 #if defined(CONFIG_USER_ONLY)
4225 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4228 if (unlikely(!ctx
->mem_idx
)) {
4229 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4232 t0
= tcg_temp_new();
4233 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4234 tcg_gen_andi_tl(t0
, t0
, 0xF);
4235 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4241 static void gen_slbmte(DisasContext
*ctx
)
4243 #if defined(CONFIG_USER_ONLY)
4244 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4246 if (unlikely(!ctx
->mem_idx
)) {
4247 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4250 gen_helper_store_slb(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)],
4251 cpu_gpr
[rS(ctx
->opcode
)]);
4255 static void gen_slbmfee(DisasContext
*ctx
)
4257 #if defined(CONFIG_USER_ONLY)
4258 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4260 if (unlikely(!ctx
->mem_idx
)) {
4261 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4264 gen_helper_load_slb_esid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4265 cpu_gpr
[rB(ctx
->opcode
)]);
4269 static void gen_slbmfev(DisasContext
*ctx
)
4271 #if defined(CONFIG_USER_ONLY)
4272 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4274 if (unlikely(!ctx
->mem_idx
)) {
4275 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4278 gen_helper_load_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4279 cpu_gpr
[rB(ctx
->opcode
)]);
4282 #endif /* defined(TARGET_PPC64) */
4284 /*** Lookaside buffer management ***/
4285 /* Optional & mem_idx only: */
4288 static void gen_tlbia(DisasContext
*ctx
)
4290 #if defined(CONFIG_USER_ONLY)
4291 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4293 if (unlikely(!ctx
->mem_idx
)) {
4294 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4297 gen_helper_tlbia(cpu_env
);
4302 static void gen_tlbiel(DisasContext
*ctx
)
4304 #if defined(CONFIG_USER_ONLY)
4305 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4307 if (unlikely(!ctx
->mem_idx
)) {
4308 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4311 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4316 static void gen_tlbie(DisasContext
*ctx
)
4318 #if defined(CONFIG_USER_ONLY)
4319 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4321 if (unlikely(!ctx
->mem_idx
)) {
4322 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4325 #if defined(TARGET_PPC64)
4326 if (!ctx
->sf_mode
) {
4327 TCGv t0
= tcg_temp_new();
4328 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
4329 gen_helper_tlbie(cpu_env
, t0
);
4333 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4338 static void gen_tlbsync(DisasContext
*ctx
)
4340 #if defined(CONFIG_USER_ONLY)
4341 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4343 if (unlikely(!ctx
->mem_idx
)) {
4344 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4347 /* This has no effect: it should ensure that all previous
4348 * tlbie have completed
4350 gen_stop_exception(ctx
);
4354 #if defined(TARGET_PPC64)
4356 static void gen_slbia(DisasContext
*ctx
)
4358 #if defined(CONFIG_USER_ONLY)
4359 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4361 if (unlikely(!ctx
->mem_idx
)) {
4362 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4365 gen_helper_slbia(cpu_env
);
4370 static void gen_slbie(DisasContext
*ctx
)
4372 #if defined(CONFIG_USER_ONLY)
4373 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4375 if (unlikely(!ctx
->mem_idx
)) {
4376 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4379 gen_helper_slbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4384 /*** External control ***/
4388 static void gen_eciwx(DisasContext
*ctx
)
4391 /* Should check EAR[E] ! */
4392 gen_set_access_type(ctx
, ACCESS_EXT
);
4393 t0
= tcg_temp_new();
4394 gen_addr_reg_index(ctx
, t0
);
4395 gen_check_align(ctx
, t0
, 0x03);
4396 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4401 static void gen_ecowx(DisasContext
*ctx
)
4404 /* Should check EAR[E] ! */
4405 gen_set_access_type(ctx
, ACCESS_EXT
);
4406 t0
= tcg_temp_new();
4407 gen_addr_reg_index(ctx
, t0
);
4408 gen_check_align(ctx
, t0
, 0x03);
4409 gen_qemu_st32(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4413 /* PowerPC 601 specific instructions */
4416 static void gen_abs(DisasContext
*ctx
)
4418 int l1
= gen_new_label();
4419 int l2
= gen_new_label();
4420 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4421 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4424 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4426 if (unlikely(Rc(ctx
->opcode
) != 0))
4427 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4431 static void gen_abso(DisasContext
*ctx
)
4433 int l1
= gen_new_label();
4434 int l2
= gen_new_label();
4435 int l3
= gen_new_label();
4436 /* Start with XER OV disabled, the most likely case */
4437 tcg_gen_movi_tl(cpu_ov
, 0);
4438 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l2
);
4439 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rA(ctx
->opcode
)], 0x80000000, l1
);
4440 tcg_gen_movi_tl(cpu_ov
, 1);
4441 tcg_gen_movi_tl(cpu_so
, 1);
4444 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4447 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4449 if (unlikely(Rc(ctx
->opcode
) != 0))
4450 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4454 static void gen_clcs(DisasContext
*ctx
)
4456 TCGv_i32 t0
= tcg_const_i32(rA(ctx
->opcode
));
4457 gen_helper_clcs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4458 tcg_temp_free_i32(t0
);
4459 /* Rc=1 sets CR0 to an undefined state */
4463 static void gen_div(DisasContext
*ctx
)
4465 gen_helper_div(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4466 cpu_gpr
[rB(ctx
->opcode
)]);
4467 if (unlikely(Rc(ctx
->opcode
) != 0))
4468 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4472 static void gen_divo(DisasContext
*ctx
)
4474 gen_helper_divo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4475 cpu_gpr
[rB(ctx
->opcode
)]);
4476 if (unlikely(Rc(ctx
->opcode
) != 0))
4477 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4481 static void gen_divs(DisasContext
*ctx
)
4483 gen_helper_divs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4484 cpu_gpr
[rB(ctx
->opcode
)]);
4485 if (unlikely(Rc(ctx
->opcode
) != 0))
4486 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4489 /* divso - divso. */
4490 static void gen_divso(DisasContext
*ctx
)
4492 gen_helper_divso(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
4493 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4494 if (unlikely(Rc(ctx
->opcode
) != 0))
4495 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4499 static void gen_doz(DisasContext
*ctx
)
4501 int l1
= gen_new_label();
4502 int l2
= gen_new_label();
4503 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4504 tcg_gen_sub_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4507 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4509 if (unlikely(Rc(ctx
->opcode
) != 0))
4510 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4514 static void gen_dozo(DisasContext
*ctx
)
4516 int l1
= gen_new_label();
4517 int l2
= gen_new_label();
4518 TCGv t0
= tcg_temp_new();
4519 TCGv t1
= tcg_temp_new();
4520 TCGv t2
= tcg_temp_new();
4521 /* Start with XER OV disabled, the most likely case */
4522 tcg_gen_movi_tl(cpu_ov
, 0);
4523 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4524 tcg_gen_sub_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4525 tcg_gen_xor_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4526 tcg_gen_xor_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], t0
);
4527 tcg_gen_andc_tl(t1
, t1
, t2
);
4528 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4529 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
4530 tcg_gen_movi_tl(cpu_ov
, 1);
4531 tcg_gen_movi_tl(cpu_so
, 1);
4534 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4539 if (unlikely(Rc(ctx
->opcode
) != 0))
4540 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4544 static void gen_dozi(DisasContext
*ctx
)
4546 target_long simm
= SIMM(ctx
->opcode
);
4547 int l1
= gen_new_label();
4548 int l2
= gen_new_label();
4549 tcg_gen_brcondi_tl(TCG_COND_LT
, cpu_gpr
[rA(ctx
->opcode
)], simm
, l1
);
4550 tcg_gen_subfi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
, cpu_gpr
[rA(ctx
->opcode
)]);
4553 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4555 if (unlikely(Rc(ctx
->opcode
) != 0))
4556 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4559 /* lscbx - lscbx. */
4560 static void gen_lscbx(DisasContext
*ctx
)
4562 TCGv t0
= tcg_temp_new();
4563 TCGv_i32 t1
= tcg_const_i32(rD(ctx
->opcode
));
4564 TCGv_i32 t2
= tcg_const_i32(rA(ctx
->opcode
));
4565 TCGv_i32 t3
= tcg_const_i32(rB(ctx
->opcode
));
4567 gen_addr_reg_index(ctx
, t0
);
4568 /* NIP cannot be restored if the memory exception comes from an helper */
4569 gen_update_nip(ctx
, ctx
->nip
- 4);
4570 gen_helper_lscbx(t0
, cpu_env
, t0
, t1
, t2
, t3
);
4571 tcg_temp_free_i32(t1
);
4572 tcg_temp_free_i32(t2
);
4573 tcg_temp_free_i32(t3
);
4574 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~0x7F);
4575 tcg_gen_or_tl(cpu_xer
, cpu_xer
, t0
);
4576 if (unlikely(Rc(ctx
->opcode
) != 0))
4577 gen_set_Rc0(ctx
, t0
);
4581 /* maskg - maskg. */
4582 static void gen_maskg(DisasContext
*ctx
)
4584 int l1
= gen_new_label();
4585 TCGv t0
= tcg_temp_new();
4586 TCGv t1
= tcg_temp_new();
4587 TCGv t2
= tcg_temp_new();
4588 TCGv t3
= tcg_temp_new();
4589 tcg_gen_movi_tl(t3
, 0xFFFFFFFF);
4590 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4591 tcg_gen_andi_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 0x1F);
4592 tcg_gen_addi_tl(t2
, t0
, 1);
4593 tcg_gen_shr_tl(t2
, t3
, t2
);
4594 tcg_gen_shr_tl(t3
, t3
, t1
);
4595 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], t2
, t3
);
4596 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
4597 tcg_gen_neg_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4603 if (unlikely(Rc(ctx
->opcode
) != 0))
4604 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4607 /* maskir - maskir. */
4608 static void gen_maskir(DisasContext
*ctx
)
4610 TCGv t0
= tcg_temp_new();
4611 TCGv t1
= tcg_temp_new();
4612 tcg_gen_and_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4613 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4614 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4617 if (unlikely(Rc(ctx
->opcode
) != 0))
4618 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4622 static void gen_mul(DisasContext
*ctx
)
4624 TCGv_i64 t0
= tcg_temp_new_i64();
4625 TCGv_i64 t1
= tcg_temp_new_i64();
4626 TCGv t2
= tcg_temp_new();
4627 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4628 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4629 tcg_gen_mul_i64(t0
, t0
, t1
);
4630 tcg_gen_trunc_i64_tl(t2
, t0
);
4631 gen_store_spr(SPR_MQ
, t2
);
4632 tcg_gen_shri_i64(t1
, t0
, 32);
4633 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4634 tcg_temp_free_i64(t0
);
4635 tcg_temp_free_i64(t1
);
4637 if (unlikely(Rc(ctx
->opcode
) != 0))
4638 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4642 static void gen_mulo(DisasContext
*ctx
)
4644 int l1
= gen_new_label();
4645 TCGv_i64 t0
= tcg_temp_new_i64();
4646 TCGv_i64 t1
= tcg_temp_new_i64();
4647 TCGv t2
= tcg_temp_new();
4648 /* Start with XER OV disabled, the most likely case */
4649 tcg_gen_movi_tl(cpu_ov
, 0);
4650 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4651 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4652 tcg_gen_mul_i64(t0
, t0
, t1
);
4653 tcg_gen_trunc_i64_tl(t2
, t0
);
4654 gen_store_spr(SPR_MQ
, t2
);
4655 tcg_gen_shri_i64(t1
, t0
, 32);
4656 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4657 tcg_gen_ext32s_i64(t1
, t0
);
4658 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
4659 tcg_gen_movi_tl(cpu_ov
, 1);
4660 tcg_gen_movi_tl(cpu_so
, 1);
4662 tcg_temp_free_i64(t0
);
4663 tcg_temp_free_i64(t1
);
4665 if (unlikely(Rc(ctx
->opcode
) != 0))
4666 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4670 static void gen_nabs(DisasContext
*ctx
)
4672 int l1
= gen_new_label();
4673 int l2
= gen_new_label();
4674 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4675 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4678 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4680 if (unlikely(Rc(ctx
->opcode
) != 0))
4681 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4684 /* nabso - nabso. */
4685 static void gen_nabso(DisasContext
*ctx
)
4687 int l1
= gen_new_label();
4688 int l2
= gen_new_label();
4689 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4690 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4693 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4695 /* nabs never overflows */
4696 tcg_gen_movi_tl(cpu_ov
, 0);
4697 if (unlikely(Rc(ctx
->opcode
) != 0))
4698 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4702 static void gen_rlmi(DisasContext
*ctx
)
4704 uint32_t mb
= MB(ctx
->opcode
);
4705 uint32_t me
= ME(ctx
->opcode
);
4706 TCGv t0
= tcg_temp_new();
4707 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4708 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4709 tcg_gen_andi_tl(t0
, t0
, MASK(mb
, me
));
4710 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~MASK(mb
, me
));
4711 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], t0
);
4713 if (unlikely(Rc(ctx
->opcode
) != 0))
4714 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4718 static void gen_rrib(DisasContext
*ctx
)
4720 TCGv t0
= tcg_temp_new();
4721 TCGv t1
= tcg_temp_new();
4722 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4723 tcg_gen_movi_tl(t1
, 0x80000000);
4724 tcg_gen_shr_tl(t1
, t1
, t0
);
4725 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4726 tcg_gen_and_tl(t0
, t0
, t1
);
4727 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], t1
);
4728 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4731 if (unlikely(Rc(ctx
->opcode
) != 0))
4732 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4736 static void gen_sle(DisasContext
*ctx
)
4738 TCGv t0
= tcg_temp_new();
4739 TCGv t1
= tcg_temp_new();
4740 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4741 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4742 tcg_gen_subfi_tl(t1
, 32, t1
);
4743 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4744 tcg_gen_or_tl(t1
, t0
, t1
);
4745 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4746 gen_store_spr(SPR_MQ
, t1
);
4749 if (unlikely(Rc(ctx
->opcode
) != 0))
4750 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4754 static void gen_sleq(DisasContext
*ctx
)
4756 TCGv t0
= tcg_temp_new();
4757 TCGv t1
= tcg_temp_new();
4758 TCGv t2
= tcg_temp_new();
4759 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4760 tcg_gen_movi_tl(t2
, 0xFFFFFFFF);
4761 tcg_gen_shl_tl(t2
, t2
, t0
);
4762 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4763 gen_load_spr(t1
, SPR_MQ
);
4764 gen_store_spr(SPR_MQ
, t0
);
4765 tcg_gen_and_tl(t0
, t0
, t2
);
4766 tcg_gen_andc_tl(t1
, t1
, t2
);
4767 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4771 if (unlikely(Rc(ctx
->opcode
) != 0))
4772 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4776 static void gen_sliq(DisasContext
*ctx
)
4778 int sh
= SH(ctx
->opcode
);
4779 TCGv t0
= tcg_temp_new();
4780 TCGv t1
= tcg_temp_new();
4781 tcg_gen_shli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4782 tcg_gen_shri_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
4783 tcg_gen_or_tl(t1
, t0
, t1
);
4784 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4785 gen_store_spr(SPR_MQ
, t1
);
4788 if (unlikely(Rc(ctx
->opcode
) != 0))
4789 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4792 /* slliq - slliq. */
4793 static void gen_slliq(DisasContext
*ctx
)
4795 int sh
= SH(ctx
->opcode
);
4796 TCGv t0
= tcg_temp_new();
4797 TCGv t1
= tcg_temp_new();
4798 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4799 gen_load_spr(t1
, SPR_MQ
);
4800 gen_store_spr(SPR_MQ
, t0
);
4801 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
<< sh
));
4802 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
<< sh
));
4803 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4806 if (unlikely(Rc(ctx
->opcode
) != 0))
4807 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4811 static void gen_sllq(DisasContext
*ctx
)
4813 int l1
= gen_new_label();
4814 int l2
= gen_new_label();
4815 TCGv t0
= tcg_temp_local_new();
4816 TCGv t1
= tcg_temp_local_new();
4817 TCGv t2
= tcg_temp_local_new();
4818 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4819 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
4820 tcg_gen_shl_tl(t1
, t1
, t2
);
4821 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4822 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
4823 gen_load_spr(t0
, SPR_MQ
);
4824 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4827 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4828 gen_load_spr(t2
, SPR_MQ
);
4829 tcg_gen_andc_tl(t1
, t2
, t1
);
4830 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4835 if (unlikely(Rc(ctx
->opcode
) != 0))
4836 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4840 static void gen_slq(DisasContext
*ctx
)
4842 int l1
= gen_new_label();
4843 TCGv t0
= tcg_temp_new();
4844 TCGv t1
= tcg_temp_new();
4845 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4846 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4847 tcg_gen_subfi_tl(t1
, 32, t1
);
4848 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4849 tcg_gen_or_tl(t1
, t0
, t1
);
4850 gen_store_spr(SPR_MQ
, t1
);
4851 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4852 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4853 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
4854 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
4858 if (unlikely(Rc(ctx
->opcode
) != 0))
4859 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4862 /* sraiq - sraiq. */
4863 static void gen_sraiq(DisasContext
*ctx
)
4865 int sh
= SH(ctx
->opcode
);
4866 int l1
= gen_new_label();
4867 TCGv t0
= tcg_temp_new();
4868 TCGv t1
= tcg_temp_new();
4869 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4870 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
4871 tcg_gen_or_tl(t0
, t0
, t1
);
4872 gen_store_spr(SPR_MQ
, t0
);
4873 tcg_gen_movi_tl(cpu_ca
, 0);
4874 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
4875 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
4876 tcg_gen_movi_tl(cpu_ca
, 1);
4878 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
4881 if (unlikely(Rc(ctx
->opcode
) != 0))
4882 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4886 static void gen_sraq(DisasContext
*ctx
)
4888 int l1
= gen_new_label();
4889 int l2
= gen_new_label();
4890 TCGv t0
= tcg_temp_new();
4891 TCGv t1
= tcg_temp_local_new();
4892 TCGv t2
= tcg_temp_local_new();
4893 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4894 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4895 tcg_gen_sar_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4896 tcg_gen_subfi_tl(t2
, 32, t2
);
4897 tcg_gen_shl_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4898 tcg_gen_or_tl(t0
, t0
, t2
);
4899 gen_store_spr(SPR_MQ
, t0
);
4900 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4901 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l1
);
4902 tcg_gen_mov_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
4903 tcg_gen_sari_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 31);
4906 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
4907 tcg_gen_movi_tl(cpu_ca
, 0);
4908 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
4909 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l2
);
4910 tcg_gen_movi_tl(cpu_ca
, 1);
4914 if (unlikely(Rc(ctx
->opcode
) != 0))
4915 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4919 static void gen_sre(DisasContext
*ctx
)
4921 TCGv t0
= tcg_temp_new();
4922 TCGv t1
= tcg_temp_new();
4923 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4924 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4925 tcg_gen_subfi_tl(t1
, 32, t1
);
4926 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4927 tcg_gen_or_tl(t1
, t0
, t1
);
4928 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4929 gen_store_spr(SPR_MQ
, t1
);
4932 if (unlikely(Rc(ctx
->opcode
) != 0))
4933 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4937 static void gen_srea(DisasContext
*ctx
)
4939 TCGv t0
= tcg_temp_new();
4940 TCGv t1
= tcg_temp_new();
4941 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4942 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4943 gen_store_spr(SPR_MQ
, t0
);
4944 tcg_gen_sar_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t1
);
4947 if (unlikely(Rc(ctx
->opcode
) != 0))
4948 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4952 static void gen_sreq(DisasContext
*ctx
)
4954 TCGv t0
= tcg_temp_new();
4955 TCGv t1
= tcg_temp_new();
4956 TCGv t2
= tcg_temp_new();
4957 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4958 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
4959 tcg_gen_shr_tl(t1
, t1
, t0
);
4960 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4961 gen_load_spr(t2
, SPR_MQ
);
4962 gen_store_spr(SPR_MQ
, t0
);
4963 tcg_gen_and_tl(t0
, t0
, t1
);
4964 tcg_gen_andc_tl(t2
, t2
, t1
);
4965 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
4969 if (unlikely(Rc(ctx
->opcode
) != 0))
4970 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4974 static void gen_sriq(DisasContext
*ctx
)
4976 int sh
= SH(ctx
->opcode
);
4977 TCGv t0
= tcg_temp_new();
4978 TCGv t1
= tcg_temp_new();
4979 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4980 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
4981 tcg_gen_or_tl(t1
, t0
, t1
);
4982 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4983 gen_store_spr(SPR_MQ
, t1
);
4986 if (unlikely(Rc(ctx
->opcode
) != 0))
4987 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4991 static void gen_srliq(DisasContext
*ctx
)
4993 int sh
= SH(ctx
->opcode
);
4994 TCGv t0
= tcg_temp_new();
4995 TCGv t1
= tcg_temp_new();
4996 tcg_gen_rotri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4997 gen_load_spr(t1
, SPR_MQ
);
4998 gen_store_spr(SPR_MQ
, t0
);
4999 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
>> sh
));
5000 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
>> sh
));
5001 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5004 if (unlikely(Rc(ctx
->opcode
) != 0))
5005 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5009 static void gen_srlq(DisasContext
*ctx
)
5011 int l1
= gen_new_label();
5012 int l2
= gen_new_label();
5013 TCGv t0
= tcg_temp_local_new();
5014 TCGv t1
= tcg_temp_local_new();
5015 TCGv t2
= tcg_temp_local_new();
5016 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5017 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5018 tcg_gen_shr_tl(t2
, t1
, t2
);
5019 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5020 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5021 gen_load_spr(t0
, SPR_MQ
);
5022 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5025 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5026 tcg_gen_and_tl(t0
, t0
, t2
);
5027 gen_load_spr(t1
, SPR_MQ
);
5028 tcg_gen_andc_tl(t1
, t1
, t2
);
5029 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5034 if (unlikely(Rc(ctx
->opcode
) != 0))
5035 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5039 static void gen_srq(DisasContext
*ctx
)
5041 int l1
= gen_new_label();
5042 TCGv t0
= tcg_temp_new();
5043 TCGv t1
= tcg_temp_new();
5044 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5045 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5046 tcg_gen_subfi_tl(t1
, 32, t1
);
5047 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5048 tcg_gen_or_tl(t1
, t0
, t1
);
5049 gen_store_spr(SPR_MQ
, t1
);
5050 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5051 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5052 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5053 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5057 if (unlikely(Rc(ctx
->opcode
) != 0))
5058 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5061 /* PowerPC 602 specific instructions */
5064 static void gen_dsa(DisasContext
*ctx
)
5067 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5071 static void gen_esa(DisasContext
*ctx
)
5074 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5078 static void gen_mfrom(DisasContext
*ctx
)
5080 #if defined(CONFIG_USER_ONLY)
5081 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5083 if (unlikely(!ctx
->mem_idx
)) {
5084 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5087 gen_helper_602_mfrom(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5091 /* 602 - 603 - G2 TLB management */
5094 static void gen_tlbld_6xx(DisasContext
*ctx
)
5096 #if defined(CONFIG_USER_ONLY)
5097 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5099 if (unlikely(!ctx
->mem_idx
)) {
5100 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5103 gen_helper_6xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5108 static void gen_tlbli_6xx(DisasContext
*ctx
)
5110 #if defined(CONFIG_USER_ONLY)
5111 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5113 if (unlikely(!ctx
->mem_idx
)) {
5114 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5117 gen_helper_6xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5121 /* 74xx TLB management */
5124 static void gen_tlbld_74xx(DisasContext
*ctx
)
5126 #if defined(CONFIG_USER_ONLY)
5127 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5129 if (unlikely(!ctx
->mem_idx
)) {
5130 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5133 gen_helper_74xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5138 static void gen_tlbli_74xx(DisasContext
*ctx
)
5140 #if defined(CONFIG_USER_ONLY)
5141 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5143 if (unlikely(!ctx
->mem_idx
)) {
5144 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5147 gen_helper_74xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5151 /* POWER instructions not in PowerPC 601 */
5154 static void gen_clf(DisasContext
*ctx
)
5156 /* Cache line flush: implemented as no-op */
5160 static void gen_cli(DisasContext
*ctx
)
5162 /* Cache line invalidate: privileged and treated as no-op */
5163 #if defined(CONFIG_USER_ONLY)
5164 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5166 if (unlikely(!ctx
->mem_idx
)) {
5167 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5174 static void gen_dclst(DisasContext
*ctx
)
5176 /* Data cache line store: treated as no-op */
5179 static void gen_mfsri(DisasContext
*ctx
)
5181 #if defined(CONFIG_USER_ONLY)
5182 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5184 int ra
= rA(ctx
->opcode
);
5185 int rd
= rD(ctx
->opcode
);
5187 if (unlikely(!ctx
->mem_idx
)) {
5188 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5191 t0
= tcg_temp_new();
5192 gen_addr_reg_index(ctx
, t0
);
5193 tcg_gen_shri_tl(t0
, t0
, 28);
5194 tcg_gen_andi_tl(t0
, t0
, 0xF);
5195 gen_helper_load_sr(cpu_gpr
[rd
], cpu_env
, t0
);
5197 if (ra
!= 0 && ra
!= rd
)
5198 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rd
]);
5202 static void gen_rac(DisasContext
*ctx
)
5204 #if defined(CONFIG_USER_ONLY)
5205 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5208 if (unlikely(!ctx
->mem_idx
)) {
5209 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5212 t0
= tcg_temp_new();
5213 gen_addr_reg_index(ctx
, t0
);
5214 gen_helper_rac(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5219 static void gen_rfsvc(DisasContext
*ctx
)
5221 #if defined(CONFIG_USER_ONLY)
5222 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5224 if (unlikely(!ctx
->mem_idx
)) {
5225 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5228 gen_helper_rfsvc(cpu_env
);
5229 gen_sync_exception(ctx
);
5233 /* svc is not implemented for now */
5235 /* POWER2 specific instructions */
5236 /* Quad manipulation (load/store two floats at a time) */
5239 static void gen_lfq(DisasContext
*ctx
)
5241 int rd
= rD(ctx
->opcode
);
5243 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5244 t0
= tcg_temp_new();
5245 gen_addr_imm_index(ctx
, t0
, 0);
5246 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5247 gen_addr_add(ctx
, t0
, t0
, 8);
5248 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5253 static void gen_lfqu(DisasContext
*ctx
)
5255 int ra
= rA(ctx
->opcode
);
5256 int rd
= rD(ctx
->opcode
);
5258 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5259 t0
= tcg_temp_new();
5260 t1
= tcg_temp_new();
5261 gen_addr_imm_index(ctx
, t0
, 0);
5262 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5263 gen_addr_add(ctx
, t1
, t0
, 8);
5264 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5266 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5272 static void gen_lfqux(DisasContext
*ctx
)
5274 int ra
= rA(ctx
->opcode
);
5275 int rd
= rD(ctx
->opcode
);
5276 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5278 t0
= tcg_temp_new();
5279 gen_addr_reg_index(ctx
, t0
);
5280 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5281 t1
= tcg_temp_new();
5282 gen_addr_add(ctx
, t1
, t0
, 8);
5283 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5286 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5291 static void gen_lfqx(DisasContext
*ctx
)
5293 int rd
= rD(ctx
->opcode
);
5295 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5296 t0
= tcg_temp_new();
5297 gen_addr_reg_index(ctx
, t0
);
5298 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5299 gen_addr_add(ctx
, t0
, t0
, 8);
5300 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5305 static void gen_stfq(DisasContext
*ctx
)
5307 int rd
= rD(ctx
->opcode
);
5309 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5310 t0
= tcg_temp_new();
5311 gen_addr_imm_index(ctx
, t0
, 0);
5312 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5313 gen_addr_add(ctx
, t0
, t0
, 8);
5314 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5319 static void gen_stfqu(DisasContext
*ctx
)
5321 int ra
= rA(ctx
->opcode
);
5322 int rd
= rD(ctx
->opcode
);
5324 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5325 t0
= tcg_temp_new();
5326 gen_addr_imm_index(ctx
, t0
, 0);
5327 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5328 t1
= tcg_temp_new();
5329 gen_addr_add(ctx
, t1
, t0
, 8);
5330 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5333 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5338 static void gen_stfqux(DisasContext
*ctx
)
5340 int ra
= rA(ctx
->opcode
);
5341 int rd
= rD(ctx
->opcode
);
5343 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5344 t0
= tcg_temp_new();
5345 gen_addr_reg_index(ctx
, t0
);
5346 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5347 t1
= tcg_temp_new();
5348 gen_addr_add(ctx
, t1
, t0
, 8);
5349 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5352 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5357 static void gen_stfqx(DisasContext
*ctx
)
5359 int rd
= rD(ctx
->opcode
);
5361 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5362 t0
= tcg_temp_new();
5363 gen_addr_reg_index(ctx
, t0
);
5364 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5365 gen_addr_add(ctx
, t0
, t0
, 8);
5366 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5370 /* BookE specific instructions */
5372 /* XXX: not implemented on 440 ? */
5373 static void gen_mfapidi(DisasContext
*ctx
)
5376 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5379 /* XXX: not implemented on 440 ? */
5380 static void gen_tlbiva(DisasContext
*ctx
)
5382 #if defined(CONFIG_USER_ONLY)
5383 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5386 if (unlikely(!ctx
->mem_idx
)) {
5387 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5390 t0
= tcg_temp_new();
5391 gen_addr_reg_index(ctx
, t0
);
5392 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5397 /* All 405 MAC instructions are translated here */
5398 static inline void gen_405_mulladd_insn(DisasContext
*ctx
, int opc2
, int opc3
,
5399 int ra
, int rb
, int rt
, int Rc
)
5403 t0
= tcg_temp_local_new();
5404 t1
= tcg_temp_local_new();
5406 switch (opc3
& 0x0D) {
5408 /* macchw - macchw. - macchwo - macchwo. */
5409 /* macchws - macchws. - macchwso - macchwso. */
5410 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5411 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5412 /* mulchw - mulchw. */
5413 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5414 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5415 tcg_gen_ext16s_tl(t1
, t1
);
5418 /* macchwu - macchwu. - macchwuo - macchwuo. */
5419 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5420 /* mulchwu - mulchwu. */
5421 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5422 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5423 tcg_gen_ext16u_tl(t1
, t1
);
5426 /* machhw - machhw. - machhwo - machhwo. */
5427 /* machhws - machhws. - machhwso - machhwso. */
5428 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5429 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5430 /* mulhhw - mulhhw. */
5431 tcg_gen_sari_tl(t0
, cpu_gpr
[ra
], 16);
5432 tcg_gen_ext16s_tl(t0
, t0
);
5433 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5434 tcg_gen_ext16s_tl(t1
, t1
);
5437 /* machhwu - machhwu. - machhwuo - machhwuo. */
5438 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5439 /* mulhhwu - mulhhwu. */
5440 tcg_gen_shri_tl(t0
, cpu_gpr
[ra
], 16);
5441 tcg_gen_ext16u_tl(t0
, t0
);
5442 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5443 tcg_gen_ext16u_tl(t1
, t1
);
5446 /* maclhw - maclhw. - maclhwo - maclhwo. */
5447 /* maclhws - maclhws. - maclhwso - maclhwso. */
5448 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5449 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5450 /* mullhw - mullhw. */
5451 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5452 tcg_gen_ext16s_tl(t1
, cpu_gpr
[rb
]);
5455 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5456 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5457 /* mullhwu - mullhwu. */
5458 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5459 tcg_gen_ext16u_tl(t1
, cpu_gpr
[rb
]);
5463 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5464 tcg_gen_mul_tl(t1
, t0
, t1
);
5466 /* nmultiply-and-accumulate (0x0E) */
5467 tcg_gen_sub_tl(t0
, cpu_gpr
[rt
], t1
);
5469 /* multiply-and-accumulate (0x0C) */
5470 tcg_gen_add_tl(t0
, cpu_gpr
[rt
], t1
);
5474 /* Check overflow and/or saturate */
5475 int l1
= gen_new_label();
5478 /* Start with XER OV disabled, the most likely case */
5479 tcg_gen_movi_tl(cpu_ov
, 0);
5483 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t1
);
5484 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
5485 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t0
);
5486 tcg_gen_brcondi_tl(TCG_COND_LT
, t1
, 0, l1
);
5489 tcg_gen_sari_tl(t0
, cpu_gpr
[rt
], 31);
5490 tcg_gen_xori_tl(t0
, t0
, 0x7fffffff);
5494 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
5497 tcg_gen_movi_tl(t0
, UINT32_MAX
);
5501 /* Check overflow */
5502 tcg_gen_movi_tl(cpu_ov
, 1);
5503 tcg_gen_movi_tl(cpu_so
, 1);
5506 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
5509 tcg_gen_mul_tl(cpu_gpr
[rt
], t0
, t1
);
5513 if (unlikely(Rc
) != 0) {
5515 gen_set_Rc0(ctx
, cpu_gpr
[rt
]);
5519 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5520 static void glue(gen_, name)(DisasContext *ctx) \
5522 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5523 rD(ctx->opcode), Rc(ctx->opcode)); \
5526 /* macchw - macchw. */
5527 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
5528 /* macchwo - macchwo. */
5529 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
5530 /* macchws - macchws. */
5531 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
5532 /* macchwso - macchwso. */
5533 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
5534 /* macchwsu - macchwsu. */
5535 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
5536 /* macchwsuo - macchwsuo. */
5537 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
5538 /* macchwu - macchwu. */
5539 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
5540 /* macchwuo - macchwuo. */
5541 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
5542 /* machhw - machhw. */
5543 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
5544 /* machhwo - machhwo. */
5545 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
5546 /* machhws - machhws. */
5547 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
5548 /* machhwso - machhwso. */
5549 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
5550 /* machhwsu - machhwsu. */
5551 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
5552 /* machhwsuo - machhwsuo. */
5553 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
5554 /* machhwu - machhwu. */
5555 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
5556 /* machhwuo - machhwuo. */
5557 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
5558 /* maclhw - maclhw. */
5559 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
5560 /* maclhwo - maclhwo. */
5561 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
5562 /* maclhws - maclhws. */
5563 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
5564 /* maclhwso - maclhwso. */
5565 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
5566 /* maclhwu - maclhwu. */
5567 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
5568 /* maclhwuo - maclhwuo. */
5569 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
5570 /* maclhwsu - maclhwsu. */
5571 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
5572 /* maclhwsuo - maclhwsuo. */
5573 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
5574 /* nmacchw - nmacchw. */
5575 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
5576 /* nmacchwo - nmacchwo. */
5577 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
5578 /* nmacchws - nmacchws. */
5579 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
5580 /* nmacchwso - nmacchwso. */
5581 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
5582 /* nmachhw - nmachhw. */
5583 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
5584 /* nmachhwo - nmachhwo. */
5585 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
5586 /* nmachhws - nmachhws. */
5587 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
5588 /* nmachhwso - nmachhwso. */
5589 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
5590 /* nmaclhw - nmaclhw. */
5591 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
5592 /* nmaclhwo - nmaclhwo. */
5593 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
5594 /* nmaclhws - nmaclhws. */
5595 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
5596 /* nmaclhwso - nmaclhwso. */
5597 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
5599 /* mulchw - mulchw. */
5600 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
5601 /* mulchwu - mulchwu. */
5602 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
5603 /* mulhhw - mulhhw. */
5604 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
5605 /* mulhhwu - mulhhwu. */
5606 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
5607 /* mullhw - mullhw. */
5608 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
5609 /* mullhwu - mullhwu. */
5610 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
5613 static void gen_mfdcr(DisasContext
*ctx
)
5615 #if defined(CONFIG_USER_ONLY)
5616 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5619 if (unlikely(!ctx
->mem_idx
)) {
5620 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5623 /* NIP cannot be restored if the memory exception comes from an helper */
5624 gen_update_nip(ctx
, ctx
->nip
- 4);
5625 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5626 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, dcrn
);
5627 tcg_temp_free(dcrn
);
5632 static void gen_mtdcr(DisasContext
*ctx
)
5634 #if defined(CONFIG_USER_ONLY)
5635 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5638 if (unlikely(!ctx
->mem_idx
)) {
5639 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5642 /* NIP cannot be restored if the memory exception comes from an helper */
5643 gen_update_nip(ctx
, ctx
->nip
- 4);
5644 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5645 gen_helper_store_dcr(cpu_env
, dcrn
, cpu_gpr
[rS(ctx
->opcode
)]);
5646 tcg_temp_free(dcrn
);
5651 /* XXX: not implemented on 440 ? */
5652 static void gen_mfdcrx(DisasContext
*ctx
)
5654 #if defined(CONFIG_USER_ONLY)
5655 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5657 if (unlikely(!ctx
->mem_idx
)) {
5658 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5661 /* NIP cannot be restored if the memory exception comes from an helper */
5662 gen_update_nip(ctx
, ctx
->nip
- 4);
5663 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5664 cpu_gpr
[rA(ctx
->opcode
)]);
5665 /* Note: Rc update flag set leads to undefined state of Rc0 */
5670 /* XXX: not implemented on 440 ? */
5671 static void gen_mtdcrx(DisasContext
*ctx
)
5673 #if defined(CONFIG_USER_ONLY)
5674 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5676 if (unlikely(!ctx
->mem_idx
)) {
5677 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5680 /* NIP cannot be restored if the memory exception comes from an helper */
5681 gen_update_nip(ctx
, ctx
->nip
- 4);
5682 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5683 cpu_gpr
[rS(ctx
->opcode
)]);
5684 /* Note: Rc update flag set leads to undefined state of Rc0 */
5688 /* mfdcrux (PPC 460) : user-mode access to DCR */
5689 static void gen_mfdcrux(DisasContext
*ctx
)
5691 /* NIP cannot be restored if the memory exception comes from an helper */
5692 gen_update_nip(ctx
, ctx
->nip
- 4);
5693 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5694 cpu_gpr
[rA(ctx
->opcode
)]);
5695 /* Note: Rc update flag set leads to undefined state of Rc0 */
5698 /* mtdcrux (PPC 460) : user-mode access to DCR */
5699 static void gen_mtdcrux(DisasContext
*ctx
)
5701 /* NIP cannot be restored if the memory exception comes from an helper */
5702 gen_update_nip(ctx
, ctx
->nip
- 4);
5703 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5704 cpu_gpr
[rS(ctx
->opcode
)]);
5705 /* Note: Rc update flag set leads to undefined state of Rc0 */
5709 static void gen_dccci(DisasContext
*ctx
)
5711 #if defined(CONFIG_USER_ONLY)
5712 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5714 if (unlikely(!ctx
->mem_idx
)) {
5715 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5718 /* interpreted as no-op */
5723 static void gen_dcread(DisasContext
*ctx
)
5725 #if defined(CONFIG_USER_ONLY)
5726 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5729 if (unlikely(!ctx
->mem_idx
)) {
5730 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5733 gen_set_access_type(ctx
, ACCESS_CACHE
);
5734 EA
= tcg_temp_new();
5735 gen_addr_reg_index(ctx
, EA
);
5736 val
= tcg_temp_new();
5737 gen_qemu_ld32u(ctx
, val
, EA
);
5739 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], EA
);
5745 static void gen_icbt_40x(DisasContext
*ctx
)
5747 /* interpreted as no-op */
5748 /* XXX: specification say this is treated as a load by the MMU
5749 * but does not generate any exception
5754 static void gen_iccci(DisasContext
*ctx
)
5756 #if defined(CONFIG_USER_ONLY)
5757 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5759 if (unlikely(!ctx
->mem_idx
)) {
5760 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5763 /* interpreted as no-op */
5768 static void gen_icread(DisasContext
*ctx
)
5770 #if defined(CONFIG_USER_ONLY)
5771 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5773 if (unlikely(!ctx
->mem_idx
)) {
5774 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5777 /* interpreted as no-op */
5781 /* rfci (mem_idx only) */
5782 static void gen_rfci_40x(DisasContext
*ctx
)
5784 #if defined(CONFIG_USER_ONLY)
5785 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5787 if (unlikely(!ctx
->mem_idx
)) {
5788 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5791 /* Restore CPU state */
5792 gen_helper_40x_rfci(cpu_env
);
5793 gen_sync_exception(ctx
);
5797 static void gen_rfci(DisasContext
*ctx
)
5799 #if defined(CONFIG_USER_ONLY)
5800 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5802 if (unlikely(!ctx
->mem_idx
)) {
5803 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5806 /* Restore CPU state */
5807 gen_helper_rfci(cpu_env
);
5808 gen_sync_exception(ctx
);
5812 /* BookE specific */
5814 /* XXX: not implemented on 440 ? */
5815 static void gen_rfdi(DisasContext
*ctx
)
5817 #if defined(CONFIG_USER_ONLY)
5818 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5820 if (unlikely(!ctx
->mem_idx
)) {
5821 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5824 /* Restore CPU state */
5825 gen_helper_rfdi(cpu_env
);
5826 gen_sync_exception(ctx
);
5830 /* XXX: not implemented on 440 ? */
5831 static void gen_rfmci(DisasContext
*ctx
)
5833 #if defined(CONFIG_USER_ONLY)
5834 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5836 if (unlikely(!ctx
->mem_idx
)) {
5837 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5840 /* Restore CPU state */
5841 gen_helper_rfmci(cpu_env
);
5842 gen_sync_exception(ctx
);
5846 /* TLB management - PowerPC 405 implementation */
5849 static void gen_tlbre_40x(DisasContext
*ctx
)
5851 #if defined(CONFIG_USER_ONLY)
5852 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5854 if (unlikely(!ctx
->mem_idx
)) {
5855 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5858 switch (rB(ctx
->opcode
)) {
5860 gen_helper_4xx_tlbre_hi(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5861 cpu_gpr
[rA(ctx
->opcode
)]);
5864 gen_helper_4xx_tlbre_lo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5865 cpu_gpr
[rA(ctx
->opcode
)]);
5868 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5874 /* tlbsx - tlbsx. */
5875 static void gen_tlbsx_40x(DisasContext
*ctx
)
5877 #if defined(CONFIG_USER_ONLY)
5878 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5881 if (unlikely(!ctx
->mem_idx
)) {
5882 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5885 t0
= tcg_temp_new();
5886 gen_addr_reg_index(ctx
, t0
);
5887 gen_helper_4xx_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5889 if (Rc(ctx
->opcode
)) {
5890 int l1
= gen_new_label();
5891 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
5892 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
5893 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
5900 static void gen_tlbwe_40x(DisasContext
*ctx
)
5902 #if defined(CONFIG_USER_ONLY)
5903 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5905 if (unlikely(!ctx
->mem_idx
)) {
5906 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5909 switch (rB(ctx
->opcode
)) {
5911 gen_helper_4xx_tlbwe_hi(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5912 cpu_gpr
[rS(ctx
->opcode
)]);
5915 gen_helper_4xx_tlbwe_lo(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5916 cpu_gpr
[rS(ctx
->opcode
)]);
5919 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5925 /* TLB management - PowerPC 440 implementation */
5928 static void gen_tlbre_440(DisasContext
*ctx
)
5930 #if defined(CONFIG_USER_ONLY)
5931 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5933 if (unlikely(!ctx
->mem_idx
)) {
5934 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5937 switch (rB(ctx
->opcode
)) {
5942 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
5943 gen_helper_440_tlbre(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5944 t0
, cpu_gpr
[rA(ctx
->opcode
)]);
5945 tcg_temp_free_i32(t0
);
5949 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5955 /* tlbsx - tlbsx. */
5956 static void gen_tlbsx_440(DisasContext
*ctx
)
5958 #if defined(CONFIG_USER_ONLY)
5959 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5962 if (unlikely(!ctx
->mem_idx
)) {
5963 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5966 t0
= tcg_temp_new();
5967 gen_addr_reg_index(ctx
, t0
);
5968 gen_helper_440_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5970 if (Rc(ctx
->opcode
)) {
5971 int l1
= gen_new_label();
5972 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
5973 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
5974 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
5981 static void gen_tlbwe_440(DisasContext
*ctx
)
5983 #if defined(CONFIG_USER_ONLY)
5984 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5986 if (unlikely(!ctx
->mem_idx
)) {
5987 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5990 switch (rB(ctx
->opcode
)) {
5995 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
5996 gen_helper_440_tlbwe(cpu_env
, t0
, cpu_gpr
[rA(ctx
->opcode
)],
5997 cpu_gpr
[rS(ctx
->opcode
)]);
5998 tcg_temp_free_i32(t0
);
6002 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6008 /* TLB management - PowerPC BookE 2.06 implementation */
6011 static void gen_tlbre_booke206(DisasContext
*ctx
)
6013 #if defined(CONFIG_USER_ONLY)
6014 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6016 if (unlikely(!ctx
->mem_idx
)) {
6017 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6021 gen_helper_booke206_tlbre(cpu_env
);
6025 /* tlbsx - tlbsx. */
6026 static void gen_tlbsx_booke206(DisasContext
*ctx
)
6028 #if defined(CONFIG_USER_ONLY)
6029 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6032 if (unlikely(!ctx
->mem_idx
)) {
6033 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6037 if (rA(ctx
->opcode
)) {
6038 t0
= tcg_temp_new();
6039 tcg_gen_mov_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)]);
6041 t0
= tcg_const_tl(0);
6044 tcg_gen_add_tl(t0
, t0
, cpu_gpr
[rB(ctx
->opcode
)]);
6045 gen_helper_booke206_tlbsx(cpu_env
, t0
);
6050 static void gen_tlbwe_booke206(DisasContext
*ctx
)
6052 #if defined(CONFIG_USER_ONLY)
6053 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6055 if (unlikely(!ctx
->mem_idx
)) {
6056 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6059 gen_update_nip(ctx
, ctx
->nip
- 4);
6060 gen_helper_booke206_tlbwe(cpu_env
);
6064 static void gen_tlbivax_booke206(DisasContext
*ctx
)
6066 #if defined(CONFIG_USER_ONLY)
6067 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6070 if (unlikely(!ctx
->mem_idx
)) {
6071 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6075 t0
= tcg_temp_new();
6076 gen_addr_reg_index(ctx
, t0
);
6078 gen_helper_booke206_tlbivax(cpu_env
, t0
);
6082 static void gen_tlbilx_booke206(DisasContext
*ctx
)
6084 #if defined(CONFIG_USER_ONLY)
6085 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6088 if (unlikely(!ctx
->mem_idx
)) {
6089 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6093 t0
= tcg_temp_new();
6094 gen_addr_reg_index(ctx
, t0
);
6096 switch((ctx
->opcode
>> 21) & 0x3) {
6098 gen_helper_booke206_tlbilx0(cpu_env
, t0
);
6101 gen_helper_booke206_tlbilx1(cpu_env
, t0
);
6104 gen_helper_booke206_tlbilx3(cpu_env
, t0
);
6107 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6117 static void gen_wrtee(DisasContext
*ctx
)
6119 #if defined(CONFIG_USER_ONLY)
6120 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6123 if (unlikely(!ctx
->mem_idx
)) {
6124 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6127 t0
= tcg_temp_new();
6128 tcg_gen_andi_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)], (1 << MSR_EE
));
6129 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6130 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
6132 /* Stop translation to have a chance to raise an exception
6133 * if we just set msr_ee to 1
6135 gen_stop_exception(ctx
);
6140 static void gen_wrteei(DisasContext
*ctx
)
6142 #if defined(CONFIG_USER_ONLY)
6143 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6145 if (unlikely(!ctx
->mem_idx
)) {
6146 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6149 if (ctx
->opcode
& 0x00008000) {
6150 tcg_gen_ori_tl(cpu_msr
, cpu_msr
, (1 << MSR_EE
));
6151 /* Stop translation to have a chance to raise an exception */
6152 gen_stop_exception(ctx
);
6154 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6159 /* PowerPC 440 specific instructions */
6162 static void gen_dlmzb(DisasContext
*ctx
)
6164 TCGv_i32 t0
= tcg_const_i32(Rc(ctx
->opcode
));
6165 gen_helper_dlmzb(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
6166 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
6167 tcg_temp_free_i32(t0
);
6170 /* mbar replaces eieio on 440 */
6171 static void gen_mbar(DisasContext
*ctx
)
6173 /* interpreted as no-op */
6176 /* msync replaces sync on 440 */
6177 static void gen_msync_4xx(DisasContext
*ctx
)
6179 /* interpreted as no-op */
6183 static void gen_icbt_440(DisasContext
*ctx
)
6185 /* interpreted as no-op */
6186 /* XXX: specification say this is treated as a load by the MMU
6187 * but does not generate any exception
6191 /* Embedded.Processor Control */
6193 static void gen_msgclr(DisasContext
*ctx
)
6195 #if defined(CONFIG_USER_ONLY)
6196 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6198 if (unlikely(ctx
->mem_idx
== 0)) {
6199 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6203 gen_helper_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6207 static void gen_msgsnd(DisasContext
*ctx
)
6209 #if defined(CONFIG_USER_ONLY)
6210 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6212 if (unlikely(ctx
->mem_idx
== 0)) {
6213 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6217 gen_helper_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
6221 /*** Altivec vector extension ***/
6222 /* Altivec registers moves */
6224 static inline TCGv_ptr
gen_avr_ptr(int reg
)
6226 TCGv_ptr r
= tcg_temp_new_ptr();
6227 tcg_gen_addi_ptr(r
, cpu_env
, offsetof(CPUPPCState
, avr
[reg
]));
6231 #define GEN_VR_LDX(name, opc2, opc3) \
6232 static void glue(gen_, name)(DisasContext *ctx) \
6235 if (unlikely(!ctx->altivec_enabled)) { \
6236 gen_exception(ctx, POWERPC_EXCP_VPU); \
6239 gen_set_access_type(ctx, ACCESS_INT); \
6240 EA = tcg_temp_new(); \
6241 gen_addr_reg_index(ctx, EA); \
6242 tcg_gen_andi_tl(EA, EA, ~0xf); \
6243 if (ctx->le_mode) { \
6244 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6245 tcg_gen_addi_tl(EA, EA, 8); \
6246 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6248 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6249 tcg_gen_addi_tl(EA, EA, 8); \
6250 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6252 tcg_temp_free(EA); \
6255 #define GEN_VR_STX(name, opc2, opc3) \
6256 static void gen_st##name(DisasContext *ctx) \
6259 if (unlikely(!ctx->altivec_enabled)) { \
6260 gen_exception(ctx, POWERPC_EXCP_VPU); \
6263 gen_set_access_type(ctx, ACCESS_INT); \
6264 EA = tcg_temp_new(); \
6265 gen_addr_reg_index(ctx, EA); \
6266 tcg_gen_andi_tl(EA, EA, ~0xf); \
6267 if (ctx->le_mode) { \
6268 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6269 tcg_gen_addi_tl(EA, EA, 8); \
6270 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6272 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6273 tcg_gen_addi_tl(EA, EA, 8); \
6274 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6276 tcg_temp_free(EA); \
6279 #define GEN_VR_LVE(name, opc2, opc3) \
6280 static void gen_lve##name(DisasContext *ctx) \
6284 if (unlikely(!ctx->altivec_enabled)) { \
6285 gen_exception(ctx, POWERPC_EXCP_VPU); \
6288 gen_set_access_type(ctx, ACCESS_INT); \
6289 EA = tcg_temp_new(); \
6290 gen_addr_reg_index(ctx, EA); \
6291 rs = gen_avr_ptr(rS(ctx->opcode)); \
6292 gen_helper_lve##name(cpu_env, rs, EA); \
6293 tcg_temp_free(EA); \
6294 tcg_temp_free_ptr(rs); \
6297 #define GEN_VR_STVE(name, opc2, opc3) \
6298 static void gen_stve##name(DisasContext *ctx) \
6302 if (unlikely(!ctx->altivec_enabled)) { \
6303 gen_exception(ctx, POWERPC_EXCP_VPU); \
6306 gen_set_access_type(ctx, ACCESS_INT); \
6307 EA = tcg_temp_new(); \
6308 gen_addr_reg_index(ctx, EA); \
6309 rs = gen_avr_ptr(rS(ctx->opcode)); \
6310 gen_helper_stve##name(cpu_env, rs, EA); \
6311 tcg_temp_free(EA); \
6312 tcg_temp_free_ptr(rs); \
6315 GEN_VR_LDX(lvx
, 0x07, 0x03);
6316 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6317 GEN_VR_LDX(lvxl
, 0x07, 0x0B);
6319 GEN_VR_LVE(bx
, 0x07, 0x00);
6320 GEN_VR_LVE(hx
, 0x07, 0x01);
6321 GEN_VR_LVE(wx
, 0x07, 0x02);
6323 GEN_VR_STX(svx
, 0x07, 0x07);
6324 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6325 GEN_VR_STX(svxl
, 0x07, 0x0F);
6327 GEN_VR_STVE(bx
, 0x07, 0x04);
6328 GEN_VR_STVE(hx
, 0x07, 0x05);
6329 GEN_VR_STVE(wx
, 0x07, 0x06);
6331 static void gen_lvsl(DisasContext
*ctx
)
6335 if (unlikely(!ctx
->altivec_enabled
)) {
6336 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6339 EA
= tcg_temp_new();
6340 gen_addr_reg_index(ctx
, EA
);
6341 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6342 gen_helper_lvsl(rd
, EA
);
6344 tcg_temp_free_ptr(rd
);
6347 static void gen_lvsr(DisasContext
*ctx
)
6351 if (unlikely(!ctx
->altivec_enabled
)) {
6352 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6355 EA
= tcg_temp_new();
6356 gen_addr_reg_index(ctx
, EA
);
6357 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6358 gen_helper_lvsr(rd
, EA
);
6360 tcg_temp_free_ptr(rd
);
6363 static void gen_mfvscr(DisasContext
*ctx
)
6366 if (unlikely(!ctx
->altivec_enabled
)) {
6367 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6370 tcg_gen_movi_i64(cpu_avrh
[rD(ctx
->opcode
)], 0);
6371 t
= tcg_temp_new_i32();
6372 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUPPCState
, vscr
));
6373 tcg_gen_extu_i32_i64(cpu_avrl
[rD(ctx
->opcode
)], t
);
6374 tcg_temp_free_i32(t
);
6377 static void gen_mtvscr(DisasContext
*ctx
)
6380 if (unlikely(!ctx
->altivec_enabled
)) {
6381 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6384 p
= gen_avr_ptr(rD(ctx
->opcode
));
6385 gen_helper_mtvscr(cpu_env
, p
);
6386 tcg_temp_free_ptr(p
);
6389 /* Logical operations */
6390 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6391 static void glue(gen_, name)(DisasContext *ctx) \
6393 if (unlikely(!ctx->altivec_enabled)) { \
6394 gen_exception(ctx, POWERPC_EXCP_VPU); \
6397 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6398 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6401 GEN_VX_LOGICAL(vand
, tcg_gen_and_i64
, 2, 16);
6402 GEN_VX_LOGICAL(vandc
, tcg_gen_andc_i64
, 2, 17);
6403 GEN_VX_LOGICAL(vor
, tcg_gen_or_i64
, 2, 18);
6404 GEN_VX_LOGICAL(vxor
, tcg_gen_xor_i64
, 2, 19);
6405 GEN_VX_LOGICAL(vnor
, tcg_gen_nor_i64
, 2, 20);
6407 #define GEN_VXFORM(name, opc2, opc3) \
6408 static void glue(gen_, name)(DisasContext *ctx) \
6410 TCGv_ptr ra, rb, rd; \
6411 if (unlikely(!ctx->altivec_enabled)) { \
6412 gen_exception(ctx, POWERPC_EXCP_VPU); \
6415 ra = gen_avr_ptr(rA(ctx->opcode)); \
6416 rb = gen_avr_ptr(rB(ctx->opcode)); \
6417 rd = gen_avr_ptr(rD(ctx->opcode)); \
6418 gen_helper_##name (rd, ra, rb); \
6419 tcg_temp_free_ptr(ra); \
6420 tcg_temp_free_ptr(rb); \
6421 tcg_temp_free_ptr(rd); \
6424 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6425 static void glue(gen_, name)(DisasContext *ctx) \
6427 TCGv_ptr ra, rb, rd; \
6428 if (unlikely(!ctx->altivec_enabled)) { \
6429 gen_exception(ctx, POWERPC_EXCP_VPU); \
6432 ra = gen_avr_ptr(rA(ctx->opcode)); \
6433 rb = gen_avr_ptr(rB(ctx->opcode)); \
6434 rd = gen_avr_ptr(rD(ctx->opcode)); \
6435 gen_helper_##name(cpu_env, rd, ra, rb); \
6436 tcg_temp_free_ptr(ra); \
6437 tcg_temp_free_ptr(rb); \
6438 tcg_temp_free_ptr(rd); \
6441 GEN_VXFORM(vaddubm
, 0, 0);
6442 GEN_VXFORM(vadduhm
, 0, 1);
6443 GEN_VXFORM(vadduwm
, 0, 2);
6444 GEN_VXFORM(vsububm
, 0, 16);
6445 GEN_VXFORM(vsubuhm
, 0, 17);
6446 GEN_VXFORM(vsubuwm
, 0, 18);
6447 GEN_VXFORM(vmaxub
, 1, 0);
6448 GEN_VXFORM(vmaxuh
, 1, 1);
6449 GEN_VXFORM(vmaxuw
, 1, 2);
6450 GEN_VXFORM(vmaxsb
, 1, 4);
6451 GEN_VXFORM(vmaxsh
, 1, 5);
6452 GEN_VXFORM(vmaxsw
, 1, 6);
6453 GEN_VXFORM(vminub
, 1, 8);
6454 GEN_VXFORM(vminuh
, 1, 9);
6455 GEN_VXFORM(vminuw
, 1, 10);
6456 GEN_VXFORM(vminsb
, 1, 12);
6457 GEN_VXFORM(vminsh
, 1, 13);
6458 GEN_VXFORM(vminsw
, 1, 14);
6459 GEN_VXFORM(vavgub
, 1, 16);
6460 GEN_VXFORM(vavguh
, 1, 17);
6461 GEN_VXFORM(vavguw
, 1, 18);
6462 GEN_VXFORM(vavgsb
, 1, 20);
6463 GEN_VXFORM(vavgsh
, 1, 21);
6464 GEN_VXFORM(vavgsw
, 1, 22);
6465 GEN_VXFORM(vmrghb
, 6, 0);
6466 GEN_VXFORM(vmrghh
, 6, 1);
6467 GEN_VXFORM(vmrghw
, 6, 2);
6468 GEN_VXFORM(vmrglb
, 6, 4);
6469 GEN_VXFORM(vmrglh
, 6, 5);
6470 GEN_VXFORM(vmrglw
, 6, 6);
6471 GEN_VXFORM(vmuloub
, 4, 0);
6472 GEN_VXFORM(vmulouh
, 4, 1);
6473 GEN_VXFORM(vmulosb
, 4, 4);
6474 GEN_VXFORM(vmulosh
, 4, 5);
6475 GEN_VXFORM(vmuleub
, 4, 8);
6476 GEN_VXFORM(vmuleuh
, 4, 9);
6477 GEN_VXFORM(vmulesb
, 4, 12);
6478 GEN_VXFORM(vmulesh
, 4, 13);
6479 GEN_VXFORM(vslb
, 2, 4);
6480 GEN_VXFORM(vslh
, 2, 5);
6481 GEN_VXFORM(vslw
, 2, 6);
6482 GEN_VXFORM(vsrb
, 2, 8);
6483 GEN_VXFORM(vsrh
, 2, 9);
6484 GEN_VXFORM(vsrw
, 2, 10);
6485 GEN_VXFORM(vsrab
, 2, 12);
6486 GEN_VXFORM(vsrah
, 2, 13);
6487 GEN_VXFORM(vsraw
, 2, 14);
6488 GEN_VXFORM(vslo
, 6, 16);
6489 GEN_VXFORM(vsro
, 6, 17);
6490 GEN_VXFORM(vaddcuw
, 0, 6);
6491 GEN_VXFORM(vsubcuw
, 0, 22);
6492 GEN_VXFORM_ENV(vaddubs
, 0, 8);
6493 GEN_VXFORM_ENV(vadduhs
, 0, 9);
6494 GEN_VXFORM_ENV(vadduws
, 0, 10);
6495 GEN_VXFORM_ENV(vaddsbs
, 0, 12);
6496 GEN_VXFORM_ENV(vaddshs
, 0, 13);
6497 GEN_VXFORM_ENV(vaddsws
, 0, 14);
6498 GEN_VXFORM_ENV(vsububs
, 0, 24);
6499 GEN_VXFORM_ENV(vsubuhs
, 0, 25);
6500 GEN_VXFORM_ENV(vsubuws
, 0, 26);
6501 GEN_VXFORM_ENV(vsubsbs
, 0, 28);
6502 GEN_VXFORM_ENV(vsubshs
, 0, 29);
6503 GEN_VXFORM_ENV(vsubsws
, 0, 30);
6504 GEN_VXFORM(vrlb
, 2, 0);
6505 GEN_VXFORM(vrlh
, 2, 1);
6506 GEN_VXFORM(vrlw
, 2, 2);
6507 GEN_VXFORM(vsl
, 2, 7);
6508 GEN_VXFORM(vsr
, 2, 11);
6509 GEN_VXFORM_ENV(vpkuhum
, 7, 0);
6510 GEN_VXFORM_ENV(vpkuwum
, 7, 1);
6511 GEN_VXFORM_ENV(vpkuhus
, 7, 2);
6512 GEN_VXFORM_ENV(vpkuwus
, 7, 3);
6513 GEN_VXFORM_ENV(vpkshus
, 7, 4);
6514 GEN_VXFORM_ENV(vpkswus
, 7, 5);
6515 GEN_VXFORM_ENV(vpkshss
, 7, 6);
6516 GEN_VXFORM_ENV(vpkswss
, 7, 7);
6517 GEN_VXFORM(vpkpx
, 7, 12);
6518 GEN_VXFORM_ENV(vsum4ubs
, 4, 24);
6519 GEN_VXFORM_ENV(vsum4sbs
, 4, 28);
6520 GEN_VXFORM_ENV(vsum4shs
, 4, 25);
6521 GEN_VXFORM_ENV(vsum2sws
, 4, 26);
6522 GEN_VXFORM_ENV(vsumsws
, 4, 30);
6523 GEN_VXFORM_ENV(vaddfp
, 5, 0);
6524 GEN_VXFORM_ENV(vsubfp
, 5, 1);
6525 GEN_VXFORM_ENV(vmaxfp
, 5, 16);
6526 GEN_VXFORM_ENV(vminfp
, 5, 17);
6528 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6529 static void glue(gen_, name)(DisasContext *ctx) \
6531 TCGv_ptr ra, rb, rd; \
6532 if (unlikely(!ctx->altivec_enabled)) { \
6533 gen_exception(ctx, POWERPC_EXCP_VPU); \
6536 ra = gen_avr_ptr(rA(ctx->opcode)); \
6537 rb = gen_avr_ptr(rB(ctx->opcode)); \
6538 rd = gen_avr_ptr(rD(ctx->opcode)); \
6539 gen_helper_##opname(cpu_env, rd, ra, rb); \
6540 tcg_temp_free_ptr(ra); \
6541 tcg_temp_free_ptr(rb); \
6542 tcg_temp_free_ptr(rd); \
6545 #define GEN_VXRFORM(name, opc2, opc3) \
6546 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6547 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6549 GEN_VXRFORM(vcmpequb
, 3, 0)
6550 GEN_VXRFORM(vcmpequh
, 3, 1)
6551 GEN_VXRFORM(vcmpequw
, 3, 2)
6552 GEN_VXRFORM(vcmpgtsb
, 3, 12)
6553 GEN_VXRFORM(vcmpgtsh
, 3, 13)
6554 GEN_VXRFORM(vcmpgtsw
, 3, 14)
6555 GEN_VXRFORM(vcmpgtub
, 3, 8)
6556 GEN_VXRFORM(vcmpgtuh
, 3, 9)
6557 GEN_VXRFORM(vcmpgtuw
, 3, 10)
6558 GEN_VXRFORM(vcmpeqfp
, 3, 3)
6559 GEN_VXRFORM(vcmpgefp
, 3, 7)
6560 GEN_VXRFORM(vcmpgtfp
, 3, 11)
6561 GEN_VXRFORM(vcmpbfp
, 3, 15)
6563 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6564 static void glue(gen_, name)(DisasContext *ctx) \
6568 if (unlikely(!ctx->altivec_enabled)) { \
6569 gen_exception(ctx, POWERPC_EXCP_VPU); \
6572 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6573 rd = gen_avr_ptr(rD(ctx->opcode)); \
6574 gen_helper_##name (rd, simm); \
6575 tcg_temp_free_i32(simm); \
6576 tcg_temp_free_ptr(rd); \
6579 GEN_VXFORM_SIMM(vspltisb
, 6, 12);
6580 GEN_VXFORM_SIMM(vspltish
, 6, 13);
6581 GEN_VXFORM_SIMM(vspltisw
, 6, 14);
6583 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6584 static void glue(gen_, name)(DisasContext *ctx) \
6587 if (unlikely(!ctx->altivec_enabled)) { \
6588 gen_exception(ctx, POWERPC_EXCP_VPU); \
6591 rb = gen_avr_ptr(rB(ctx->opcode)); \
6592 rd = gen_avr_ptr(rD(ctx->opcode)); \
6593 gen_helper_##name (rd, rb); \
6594 tcg_temp_free_ptr(rb); \
6595 tcg_temp_free_ptr(rd); \
6598 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6599 static void glue(gen_, name)(DisasContext *ctx) \
6603 if (unlikely(!ctx->altivec_enabled)) { \
6604 gen_exception(ctx, POWERPC_EXCP_VPU); \
6607 rb = gen_avr_ptr(rB(ctx->opcode)); \
6608 rd = gen_avr_ptr(rD(ctx->opcode)); \
6609 gen_helper_##name(cpu_env, rd, rb); \
6610 tcg_temp_free_ptr(rb); \
6611 tcg_temp_free_ptr(rd); \
6614 GEN_VXFORM_NOA(vupkhsb
, 7, 8);
6615 GEN_VXFORM_NOA(vupkhsh
, 7, 9);
6616 GEN_VXFORM_NOA(vupklsb
, 7, 10);
6617 GEN_VXFORM_NOA(vupklsh
, 7, 11);
6618 GEN_VXFORM_NOA(vupkhpx
, 7, 13);
6619 GEN_VXFORM_NOA(vupklpx
, 7, 15);
6620 GEN_VXFORM_NOA_ENV(vrefp
, 5, 4);
6621 GEN_VXFORM_NOA_ENV(vrsqrtefp
, 5, 5);
6622 GEN_VXFORM_NOA_ENV(vexptefp
, 5, 6);
6623 GEN_VXFORM_NOA_ENV(vlogefp
, 5, 7);
6624 GEN_VXFORM_NOA_ENV(vrfim
, 5, 8);
6625 GEN_VXFORM_NOA_ENV(vrfin
, 5, 9);
6626 GEN_VXFORM_NOA_ENV(vrfip
, 5, 10);
6627 GEN_VXFORM_NOA_ENV(vrfiz
, 5, 11);
6629 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6630 static void glue(gen_, name)(DisasContext *ctx) \
6634 if (unlikely(!ctx->altivec_enabled)) { \
6635 gen_exception(ctx, POWERPC_EXCP_VPU); \
6638 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6639 rd = gen_avr_ptr(rD(ctx->opcode)); \
6640 gen_helper_##name (rd, simm); \
6641 tcg_temp_free_i32(simm); \
6642 tcg_temp_free_ptr(rd); \
6645 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6646 static void glue(gen_, name)(DisasContext *ctx) \
6650 if (unlikely(!ctx->altivec_enabled)) { \
6651 gen_exception(ctx, POWERPC_EXCP_VPU); \
6654 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6655 rb = gen_avr_ptr(rB(ctx->opcode)); \
6656 rd = gen_avr_ptr(rD(ctx->opcode)); \
6657 gen_helper_##name (rd, rb, uimm); \
6658 tcg_temp_free_i32(uimm); \
6659 tcg_temp_free_ptr(rb); \
6660 tcg_temp_free_ptr(rd); \
6663 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6664 static void glue(gen_, name)(DisasContext *ctx) \
6669 if (unlikely(!ctx->altivec_enabled)) { \
6670 gen_exception(ctx, POWERPC_EXCP_VPU); \
6673 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6674 rb = gen_avr_ptr(rB(ctx->opcode)); \
6675 rd = gen_avr_ptr(rD(ctx->opcode)); \
6676 gen_helper_##name(cpu_env, rd, rb, uimm); \
6677 tcg_temp_free_i32(uimm); \
6678 tcg_temp_free_ptr(rb); \
6679 tcg_temp_free_ptr(rd); \
6682 GEN_VXFORM_UIMM(vspltb
, 6, 8);
6683 GEN_VXFORM_UIMM(vsplth
, 6, 9);
6684 GEN_VXFORM_UIMM(vspltw
, 6, 10);
6685 GEN_VXFORM_UIMM_ENV(vcfux
, 5, 12);
6686 GEN_VXFORM_UIMM_ENV(vcfsx
, 5, 13);
6687 GEN_VXFORM_UIMM_ENV(vctuxs
, 5, 14);
6688 GEN_VXFORM_UIMM_ENV(vctsxs
, 5, 15);
6690 static void gen_vsldoi(DisasContext
*ctx
)
6692 TCGv_ptr ra
, rb
, rd
;
6694 if (unlikely(!ctx
->altivec_enabled
)) {
6695 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6698 ra
= gen_avr_ptr(rA(ctx
->opcode
));
6699 rb
= gen_avr_ptr(rB(ctx
->opcode
));
6700 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6701 sh
= tcg_const_i32(VSH(ctx
->opcode
));
6702 gen_helper_vsldoi (rd
, ra
, rb
, sh
);
6703 tcg_temp_free_ptr(ra
);
6704 tcg_temp_free_ptr(rb
);
6705 tcg_temp_free_ptr(rd
);
6706 tcg_temp_free_i32(sh
);
6709 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6710 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6712 TCGv_ptr ra, rb, rc, rd; \
6713 if (unlikely(!ctx->altivec_enabled)) { \
6714 gen_exception(ctx, POWERPC_EXCP_VPU); \
6717 ra = gen_avr_ptr(rA(ctx->opcode)); \
6718 rb = gen_avr_ptr(rB(ctx->opcode)); \
6719 rc = gen_avr_ptr(rC(ctx->opcode)); \
6720 rd = gen_avr_ptr(rD(ctx->opcode)); \
6721 if (Rc(ctx->opcode)) { \
6722 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6724 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6726 tcg_temp_free_ptr(ra); \
6727 tcg_temp_free_ptr(rb); \
6728 tcg_temp_free_ptr(rc); \
6729 tcg_temp_free_ptr(rd); \
6732 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16)
6734 static void gen_vmladduhm(DisasContext
*ctx
)
6736 TCGv_ptr ra
, rb
, rc
, rd
;
6737 if (unlikely(!ctx
->altivec_enabled
)) {
6738 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6741 ra
= gen_avr_ptr(rA(ctx
->opcode
));
6742 rb
= gen_avr_ptr(rB(ctx
->opcode
));
6743 rc
= gen_avr_ptr(rC(ctx
->opcode
));
6744 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6745 gen_helper_vmladduhm(rd
, ra
, rb
, rc
);
6746 tcg_temp_free_ptr(ra
);
6747 tcg_temp_free_ptr(rb
);
6748 tcg_temp_free_ptr(rc
);
6749 tcg_temp_free_ptr(rd
);
6752 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18)
6753 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19)
6754 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20)
6755 GEN_VAFORM_PAIRED(vsel
, vperm
, 21)
6756 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23)
6758 /*** SPE extension ***/
6759 /* Register moves */
6762 static inline void gen_evmra(DisasContext
*ctx
)
6765 if (unlikely(!ctx
->spe_enabled
)) {
6766 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
6770 #if defined(TARGET_PPC64)
6772 tcg_gen_mov_i64(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
6775 tcg_gen_st_i64(cpu_gpr
[rA(ctx
->opcode
)],
6777 offsetof(CPUPPCState
, spe_acc
));
6779 TCGv_i64 tmp
= tcg_temp_new_i64();
6781 /* tmp := rA_lo + rA_hi << 32 */
6782 tcg_gen_concat_i32_i64(tmp
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
6784 /* spe_acc := tmp */
6785 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
6786 tcg_temp_free_i64(tmp
);
6789 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
6790 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
6794 static inline void gen_load_gpr64(TCGv_i64 t
, int reg
)
6796 #if defined(TARGET_PPC64)
6797 tcg_gen_mov_i64(t
, cpu_gpr
[reg
]);
6799 tcg_gen_concat_i32_i64(t
, cpu_gpr
[reg
], cpu_gprh
[reg
]);
6803 static inline void gen_store_gpr64(int reg
, TCGv_i64 t
)
6805 #if defined(TARGET_PPC64)
6806 tcg_gen_mov_i64(cpu_gpr
[reg
], t
);
6808 TCGv_i64 tmp
= tcg_temp_new_i64();
6809 tcg_gen_trunc_i64_i32(cpu_gpr
[reg
], t
);
6810 tcg_gen_shri_i64(tmp
, t
, 32);
6811 tcg_gen_trunc_i64_i32(cpu_gprh
[reg
], tmp
);
6812 tcg_temp_free_i64(tmp
);
6816 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6817 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6819 if (Rc(ctx->opcode)) \
6825 /* Handler for undefined SPE opcodes */
6826 static inline void gen_speundef(DisasContext
*ctx
)
6828 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6832 #if defined(TARGET_PPC64)
6833 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6834 static inline void gen_##name(DisasContext *ctx) \
6836 if (unlikely(!ctx->spe_enabled)) { \
6837 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6840 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6841 cpu_gpr[rB(ctx->opcode)]); \
6844 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6845 static inline void gen_##name(DisasContext *ctx) \
6847 if (unlikely(!ctx->spe_enabled)) { \
6848 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6851 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6852 cpu_gpr[rB(ctx->opcode)]); \
6853 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6854 cpu_gprh[rB(ctx->opcode)]); \
6858 GEN_SPEOP_LOGIC2(evand
, tcg_gen_and_tl
);
6859 GEN_SPEOP_LOGIC2(evandc
, tcg_gen_andc_tl
);
6860 GEN_SPEOP_LOGIC2(evxor
, tcg_gen_xor_tl
);
6861 GEN_SPEOP_LOGIC2(evor
, tcg_gen_or_tl
);
6862 GEN_SPEOP_LOGIC2(evnor
, tcg_gen_nor_tl
);
6863 GEN_SPEOP_LOGIC2(eveqv
, tcg_gen_eqv_tl
);
6864 GEN_SPEOP_LOGIC2(evorc
, tcg_gen_orc_tl
);
6865 GEN_SPEOP_LOGIC2(evnand
, tcg_gen_nand_tl
);
6867 /* SPE logic immediate */
6868 #if defined(TARGET_PPC64)
6869 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6870 static inline void gen_##name(DisasContext *ctx) \
6872 if (unlikely(!ctx->spe_enabled)) { \
6873 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6876 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6877 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6878 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6879 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6880 tcg_opi(t0, t0, rB(ctx->opcode)); \
6881 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6882 tcg_gen_trunc_i64_i32(t1, t2); \
6883 tcg_temp_free_i64(t2); \
6884 tcg_opi(t1, t1, rB(ctx->opcode)); \
6885 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6886 tcg_temp_free_i32(t0); \
6887 tcg_temp_free_i32(t1); \
6890 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6891 static inline void gen_##name(DisasContext *ctx) \
6893 if (unlikely(!ctx->spe_enabled)) { \
6894 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6897 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6899 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6903 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi
, tcg_gen_shli_i32
);
6904 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu
, tcg_gen_shri_i32
);
6905 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis
, tcg_gen_sari_i32
);
6906 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi
, tcg_gen_rotli_i32
);
6908 /* SPE arithmetic */
6909 #if defined(TARGET_PPC64)
6910 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6911 static inline void gen_##name(DisasContext *ctx) \
6913 if (unlikely(!ctx->spe_enabled)) { \
6914 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6917 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6918 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6919 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6920 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6922 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6923 tcg_gen_trunc_i64_i32(t1, t2); \
6924 tcg_temp_free_i64(t2); \
6926 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6927 tcg_temp_free_i32(t0); \
6928 tcg_temp_free_i32(t1); \
6931 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6932 static inline void gen_##name(DisasContext *ctx) \
6934 if (unlikely(!ctx->spe_enabled)) { \
6935 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6938 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6939 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6943 static inline void gen_op_evabs(TCGv_i32 ret
, TCGv_i32 arg1
)
6945 int l1
= gen_new_label();
6946 int l2
= gen_new_label();
6948 tcg_gen_brcondi_i32(TCG_COND_GE
, arg1
, 0, l1
);
6949 tcg_gen_neg_i32(ret
, arg1
);
6952 tcg_gen_mov_i32(ret
, arg1
);
6955 GEN_SPEOP_ARITH1(evabs
, gen_op_evabs
);
6956 GEN_SPEOP_ARITH1(evneg
, tcg_gen_neg_i32
);
6957 GEN_SPEOP_ARITH1(evextsb
, tcg_gen_ext8s_i32
);
6958 GEN_SPEOP_ARITH1(evextsh
, tcg_gen_ext16s_i32
);
6959 static inline void gen_op_evrndw(TCGv_i32 ret
, TCGv_i32 arg1
)
6961 tcg_gen_addi_i32(ret
, arg1
, 0x8000);
6962 tcg_gen_ext16u_i32(ret
, ret
);
6964 GEN_SPEOP_ARITH1(evrndw
, gen_op_evrndw
);
6965 GEN_SPEOP_ARITH1(evcntlsw
, gen_helper_cntlsw32
);
6966 GEN_SPEOP_ARITH1(evcntlzw
, gen_helper_cntlzw32
);
6968 #if defined(TARGET_PPC64)
6969 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6970 static inline void gen_##name(DisasContext *ctx) \
6972 if (unlikely(!ctx->spe_enabled)) { \
6973 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6976 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6977 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6978 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6979 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6980 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6981 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6982 tcg_op(t0, t0, t2); \
6983 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6984 tcg_gen_trunc_i64_i32(t1, t3); \
6985 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6986 tcg_gen_trunc_i64_i32(t2, t3); \
6987 tcg_temp_free_i64(t3); \
6988 tcg_op(t1, t1, t2); \
6989 tcg_temp_free_i32(t2); \
6990 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6991 tcg_temp_free_i32(t0); \
6992 tcg_temp_free_i32(t1); \
6995 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6996 static inline void gen_##name(DisasContext *ctx) \
6998 if (unlikely(!ctx->spe_enabled)) { \
6999 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7002 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7003 cpu_gpr[rB(ctx->opcode)]); \
7004 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7005 cpu_gprh[rB(ctx->opcode)]); \
7009 static inline void gen_op_evsrwu(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7014 l1
= gen_new_label();
7015 l2
= gen_new_label();
7016 t0
= tcg_temp_local_new_i32();
7017 /* No error here: 6 bits are used */
7018 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
7019 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
7020 tcg_gen_shr_i32(ret
, arg1
, t0
);
7023 tcg_gen_movi_i32(ret
, 0);
7025 tcg_temp_free_i32(t0
);
7027 GEN_SPEOP_ARITH2(evsrwu
, gen_op_evsrwu
);
7028 static inline void gen_op_evsrws(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7033 l1
= gen_new_label();
7034 l2
= gen_new_label();
7035 t0
= tcg_temp_local_new_i32();
7036 /* No error here: 6 bits are used */
7037 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
7038 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
7039 tcg_gen_sar_i32(ret
, arg1
, t0
);
7042 tcg_gen_movi_i32(ret
, 0);
7044 tcg_temp_free_i32(t0
);
7046 GEN_SPEOP_ARITH2(evsrws
, gen_op_evsrws
);
7047 static inline void gen_op_evslw(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7052 l1
= gen_new_label();
7053 l2
= gen_new_label();
7054 t0
= tcg_temp_local_new_i32();
7055 /* No error here: 6 bits are used */
7056 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
7057 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
7058 tcg_gen_shl_i32(ret
, arg1
, t0
);
7061 tcg_gen_movi_i32(ret
, 0);
7063 tcg_temp_free_i32(t0
);
7065 GEN_SPEOP_ARITH2(evslw
, gen_op_evslw
);
7066 static inline void gen_op_evrlw(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7068 TCGv_i32 t0
= tcg_temp_new_i32();
7069 tcg_gen_andi_i32(t0
, arg2
, 0x1F);
7070 tcg_gen_rotl_i32(ret
, arg1
, t0
);
7071 tcg_temp_free_i32(t0
);
7073 GEN_SPEOP_ARITH2(evrlw
, gen_op_evrlw
);
7074 static inline void gen_evmergehi(DisasContext
*ctx
)
7076 if (unlikely(!ctx
->spe_enabled
)) {
7077 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7080 #if defined(TARGET_PPC64)
7081 TCGv t0
= tcg_temp_new();
7082 TCGv t1
= tcg_temp_new();
7083 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 32);
7084 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 0xFFFFFFFF0000000ULL
);
7085 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7089 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
7090 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
7093 GEN_SPEOP_ARITH2(evaddw
, tcg_gen_add_i32
);
7094 static inline void gen_op_evsubf(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7096 tcg_gen_sub_i32(ret
, arg2
, arg1
);
7098 GEN_SPEOP_ARITH2(evsubfw
, gen_op_evsubf
);
7100 /* SPE arithmetic immediate */
7101 #if defined(TARGET_PPC64)
7102 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7103 static inline void gen_##name(DisasContext *ctx) \
7105 if (unlikely(!ctx->spe_enabled)) { \
7106 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7109 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7110 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7111 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7112 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7113 tcg_op(t0, t0, rA(ctx->opcode)); \
7114 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7115 tcg_gen_trunc_i64_i32(t1, t2); \
7116 tcg_temp_free_i64(t2); \
7117 tcg_op(t1, t1, rA(ctx->opcode)); \
7118 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7119 tcg_temp_free_i32(t0); \
7120 tcg_temp_free_i32(t1); \
7123 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7124 static inline void gen_##name(DisasContext *ctx) \
7126 if (unlikely(!ctx->spe_enabled)) { \
7127 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7130 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7132 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7136 GEN_SPEOP_ARITH_IMM2(evaddiw
, tcg_gen_addi_i32
);
7137 GEN_SPEOP_ARITH_IMM2(evsubifw
, tcg_gen_subi_i32
);
7139 /* SPE comparison */
7140 #if defined(TARGET_PPC64)
7141 #define GEN_SPEOP_COMP(name, tcg_cond) \
7142 static inline void gen_##name(DisasContext *ctx) \
7144 if (unlikely(!ctx->spe_enabled)) { \
7145 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7148 int l1 = gen_new_label(); \
7149 int l2 = gen_new_label(); \
7150 int l3 = gen_new_label(); \
7151 int l4 = gen_new_label(); \
7152 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7153 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7154 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7155 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7156 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7157 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7158 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7160 gen_set_label(l1); \
7161 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7162 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7163 gen_set_label(l2); \
7164 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7165 tcg_gen_trunc_i64_i32(t0, t2); \
7166 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7167 tcg_gen_trunc_i64_i32(t1, t2); \
7168 tcg_temp_free_i64(t2); \
7169 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7170 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7171 ~(CRF_CH | CRF_CH_AND_CL)); \
7173 gen_set_label(l3); \
7174 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7175 CRF_CH | CRF_CH_OR_CL); \
7176 gen_set_label(l4); \
7177 tcg_temp_free_i32(t0); \
7178 tcg_temp_free_i32(t1); \
7181 #define GEN_SPEOP_COMP(name, tcg_cond) \
7182 static inline void gen_##name(DisasContext *ctx) \
7184 if (unlikely(!ctx->spe_enabled)) { \
7185 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7188 int l1 = gen_new_label(); \
7189 int l2 = gen_new_label(); \
7190 int l3 = gen_new_label(); \
7191 int l4 = gen_new_label(); \
7193 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7194 cpu_gpr[rB(ctx->opcode)], l1); \
7195 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7197 gen_set_label(l1); \
7198 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7199 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7200 gen_set_label(l2); \
7201 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7202 cpu_gprh[rB(ctx->opcode)], l3); \
7203 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7204 ~(CRF_CH | CRF_CH_AND_CL)); \
7206 gen_set_label(l3); \
7207 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7208 CRF_CH | CRF_CH_OR_CL); \
7209 gen_set_label(l4); \
7212 GEN_SPEOP_COMP(evcmpgtu
, TCG_COND_GTU
);
7213 GEN_SPEOP_COMP(evcmpgts
, TCG_COND_GT
);
7214 GEN_SPEOP_COMP(evcmpltu
, TCG_COND_LTU
);
7215 GEN_SPEOP_COMP(evcmplts
, TCG_COND_LT
);
7216 GEN_SPEOP_COMP(evcmpeq
, TCG_COND_EQ
);
7219 static inline void gen_brinc(DisasContext
*ctx
)
7221 /* Note: brinc is usable even if SPE is disabled */
7222 gen_helper_brinc(cpu_gpr
[rD(ctx
->opcode
)],
7223 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7225 static inline void gen_evmergelo(DisasContext
*ctx
)
7227 if (unlikely(!ctx
->spe_enabled
)) {
7228 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7231 #if defined(TARGET_PPC64)
7232 TCGv t0
= tcg_temp_new();
7233 TCGv t1
= tcg_temp_new();
7234 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
7235 tcg_gen_shli_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 32);
7236 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7240 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
7241 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7244 static inline void gen_evmergehilo(DisasContext
*ctx
)
7246 if (unlikely(!ctx
->spe_enabled
)) {
7247 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7250 #if defined(TARGET_PPC64)
7251 TCGv t0
= tcg_temp_new();
7252 TCGv t1
= tcg_temp_new();
7253 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
7254 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 0xFFFFFFFF0000000ULL
);
7255 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7259 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7260 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
7263 static inline void gen_evmergelohi(DisasContext
*ctx
)
7265 if (unlikely(!ctx
->spe_enabled
)) {
7266 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7269 #if defined(TARGET_PPC64)
7270 TCGv t0
= tcg_temp_new();
7271 TCGv t1
= tcg_temp_new();
7272 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 32);
7273 tcg_gen_shli_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 32);
7274 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7278 if (rD(ctx
->opcode
) == rA(ctx
->opcode
)) {
7279 TCGv_i32 tmp
= tcg_temp_new_i32();
7280 tcg_gen_mov_i32(tmp
, cpu_gpr
[rA(ctx
->opcode
)]);
7281 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
7282 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], tmp
);
7283 tcg_temp_free_i32(tmp
);
7285 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
7286 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
7290 static inline void gen_evsplati(DisasContext
*ctx
)
7292 uint64_t imm
= ((int32_t)(rA(ctx
->opcode
) << 27)) >> 27;
7294 #if defined(TARGET_PPC64)
7295 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], (imm
<< 32) | imm
);
7297 tcg_gen_movi_i32(cpu_gpr
[rD(ctx
->opcode
)], imm
);
7298 tcg_gen_movi_i32(cpu_gprh
[rD(ctx
->opcode
)], imm
);
7301 static inline void gen_evsplatfi(DisasContext
*ctx
)
7303 uint64_t imm
= rA(ctx
->opcode
) << 27;
7305 #if defined(TARGET_PPC64)
7306 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], (imm
<< 32) | imm
);
7308 tcg_gen_movi_i32(cpu_gpr
[rD(ctx
->opcode
)], imm
);
7309 tcg_gen_movi_i32(cpu_gprh
[rD(ctx
->opcode
)], imm
);
7313 static inline void gen_evsel(DisasContext
*ctx
)
7315 int l1
= gen_new_label();
7316 int l2
= gen_new_label();
7317 int l3
= gen_new_label();
7318 int l4
= gen_new_label();
7319 TCGv_i32 t0
= tcg_temp_local_new_i32();
7320 #if defined(TARGET_PPC64)
7321 TCGv t1
= tcg_temp_local_new();
7322 TCGv t2
= tcg_temp_local_new();
7324 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 3);
7325 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
7326 #if defined(TARGET_PPC64)
7327 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 0xFFFFFFFF00000000ULL
);
7329 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
7333 #if defined(TARGET_PPC64)
7334 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0xFFFFFFFF00000000ULL
);
7336 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
7339 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 2);
7340 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l3
);
7341 #if defined(TARGET_PPC64)
7342 tcg_gen_ext32u_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)]);
7344 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
7348 #if defined(TARGET_PPC64)
7349 tcg_gen_ext32u_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)]);
7351 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7354 tcg_temp_free_i32(t0
);
7355 #if defined(TARGET_PPC64)
7356 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
, t2
);
7362 static void gen_evsel0(DisasContext
*ctx
)
7367 static void gen_evsel1(DisasContext
*ctx
)
7372 static void gen_evsel2(DisasContext
*ctx
)
7377 static void gen_evsel3(DisasContext
*ctx
)
7384 static inline void gen_evmwumi(DisasContext
*ctx
)
7388 if (unlikely(!ctx
->spe_enabled
)) {
7389 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7393 t0
= tcg_temp_new_i64();
7394 t1
= tcg_temp_new_i64();
7396 /* t0 := rA; t1 := rB */
7397 #if defined(TARGET_PPC64)
7398 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
7399 tcg_gen_ext32u_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
7401 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
7402 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
7405 tcg_gen_mul_i64(t0
, t0
, t1
); /* t0 := rA * rB */
7407 gen_store_gpr64(rD(ctx
->opcode
), t0
); /* rD := t0 */
7409 tcg_temp_free_i64(t0
);
7410 tcg_temp_free_i64(t1
);
7413 static inline void gen_evmwumia(DisasContext
*ctx
)
7417 if (unlikely(!ctx
->spe_enabled
)) {
7418 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7422 gen_evmwumi(ctx
); /* rD := rA * rB */
7424 tmp
= tcg_temp_new_i64();
7427 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
7428 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7429 tcg_temp_free_i64(tmp
);
7432 static inline void gen_evmwumiaa(DisasContext
*ctx
)
7437 if (unlikely(!ctx
->spe_enabled
)) {
7438 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7442 gen_evmwumi(ctx
); /* rD := rA * rB */
7444 acc
= tcg_temp_new_i64();
7445 tmp
= tcg_temp_new_i64();
7448 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
7451 tcg_gen_ld_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7453 /* acc := tmp + acc */
7454 tcg_gen_add_i64(acc
, acc
, tmp
);
7457 tcg_gen_st_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7460 gen_store_gpr64(rD(ctx
->opcode
), acc
);
7462 tcg_temp_free_i64(acc
);
7463 tcg_temp_free_i64(tmp
);
7466 static inline void gen_evmwsmi(DisasContext
*ctx
)
7470 if (unlikely(!ctx
->spe_enabled
)) {
7471 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7475 t0
= tcg_temp_new_i64();
7476 t1
= tcg_temp_new_i64();
7478 /* t0 := rA; t1 := rB */
7479 #if defined(TARGET_PPC64)
7480 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
7481 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
7483 tcg_gen_ext_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
7484 tcg_gen_ext_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
7487 tcg_gen_mul_i64(t0
, t0
, t1
); /* t0 := rA * rB */
7489 gen_store_gpr64(rD(ctx
->opcode
), t0
); /* rD := t0 */
7491 tcg_temp_free_i64(t0
);
7492 tcg_temp_free_i64(t1
);
7495 static inline void gen_evmwsmia(DisasContext
*ctx
)
7499 gen_evmwsmi(ctx
); /* rD := rA * rB */
7501 tmp
= tcg_temp_new_i64();
7504 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
7505 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7507 tcg_temp_free_i64(tmp
);
7510 static inline void gen_evmwsmiaa(DisasContext
*ctx
)
7512 TCGv_i64 acc
= tcg_temp_new_i64();
7513 TCGv_i64 tmp
= tcg_temp_new_i64();
7515 gen_evmwsmi(ctx
); /* rD := rA * rB */
7517 acc
= tcg_temp_new_i64();
7518 tmp
= tcg_temp_new_i64();
7521 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
7524 tcg_gen_ld_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7526 /* acc := tmp + acc */
7527 tcg_gen_add_i64(acc
, acc
, tmp
);
7530 tcg_gen_st_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7533 gen_store_gpr64(rD(ctx
->opcode
), acc
);
7535 tcg_temp_free_i64(acc
);
7536 tcg_temp_free_i64(tmp
);
7539 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
7540 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
7541 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
7542 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
7543 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
7544 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
7545 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
7546 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE
); //
7547 GEN_SPE(evmra
, speundef
, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE
);
7548 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
); ////
7549 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
7550 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
7551 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
7552 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
7553 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
7554 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
7555 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
); ////
7556 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
7557 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
7558 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE
);
7559 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
7560 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
7561 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE
); //
7562 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE
);
7563 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
7564 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
7565 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE
); ////
7566 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE
); ////
7567 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE
); ////
7569 /* SPE load and stores */
7570 static inline void gen_addr_spe_imm_index(DisasContext
*ctx
, TCGv EA
, int sh
)
7572 target_ulong uimm
= rB(ctx
->opcode
);
7574 if (rA(ctx
->opcode
) == 0) {
7575 tcg_gen_movi_tl(EA
, uimm
<< sh
);
7577 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], uimm
<< sh
);
7578 #if defined(TARGET_PPC64)
7579 if (!ctx
->sf_mode
) {
7580 tcg_gen_ext32u_tl(EA
, EA
);
7586 static inline void gen_op_evldd(DisasContext
*ctx
, TCGv addr
)
7588 #if defined(TARGET_PPC64)
7589 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7591 TCGv_i64 t0
= tcg_temp_new_i64();
7592 gen_qemu_ld64(ctx
, t0
, addr
);
7593 tcg_gen_trunc_i64_i32(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7594 tcg_gen_shri_i64(t0
, t0
, 32);
7595 tcg_gen_trunc_i64_i32(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7596 tcg_temp_free_i64(t0
);
7600 static inline void gen_op_evldw(DisasContext
*ctx
, TCGv addr
)
7602 #if defined(TARGET_PPC64)
7603 TCGv t0
= tcg_temp_new();
7604 gen_qemu_ld32u(ctx
, t0
, addr
);
7605 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7606 gen_addr_add(ctx
, addr
, addr
, 4);
7607 gen_qemu_ld32u(ctx
, t0
, addr
);
7608 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7611 gen_qemu_ld32u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
7612 gen_addr_add(ctx
, addr
, addr
, 4);
7613 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7617 static inline void gen_op_evldh(DisasContext
*ctx
, TCGv addr
)
7619 TCGv t0
= tcg_temp_new();
7620 #if defined(TARGET_PPC64)
7621 gen_qemu_ld16u(ctx
, t0
, addr
);
7622 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7623 gen_addr_add(ctx
, addr
, addr
, 2);
7624 gen_qemu_ld16u(ctx
, t0
, addr
);
7625 tcg_gen_shli_tl(t0
, t0
, 32);
7626 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7627 gen_addr_add(ctx
, addr
, addr
, 2);
7628 gen_qemu_ld16u(ctx
, t0
, addr
);
7629 tcg_gen_shli_tl(t0
, t0
, 16);
7630 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7631 gen_addr_add(ctx
, addr
, addr
, 2);
7632 gen_qemu_ld16u(ctx
, t0
, addr
);
7633 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7635 gen_qemu_ld16u(ctx
, t0
, addr
);
7636 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7637 gen_addr_add(ctx
, addr
, addr
, 2);
7638 gen_qemu_ld16u(ctx
, t0
, addr
);
7639 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
7640 gen_addr_add(ctx
, addr
, addr
, 2);
7641 gen_qemu_ld16u(ctx
, t0
, addr
);
7642 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7643 gen_addr_add(ctx
, addr
, addr
, 2);
7644 gen_qemu_ld16u(ctx
, t0
, addr
);
7645 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7650 static inline void gen_op_evlhhesplat(DisasContext
*ctx
, TCGv addr
)
7652 TCGv t0
= tcg_temp_new();
7653 gen_qemu_ld16u(ctx
, t0
, addr
);
7654 #if defined(TARGET_PPC64)
7655 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7656 tcg_gen_shli_tl(t0
, t0
, 16);
7657 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7659 tcg_gen_shli_tl(t0
, t0
, 16);
7660 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7661 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7666 static inline void gen_op_evlhhousplat(DisasContext
*ctx
, TCGv addr
)
7668 TCGv t0
= tcg_temp_new();
7669 gen_qemu_ld16u(ctx
, t0
, addr
);
7670 #if defined(TARGET_PPC64)
7671 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7672 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7674 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7675 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7680 static inline void gen_op_evlhhossplat(DisasContext
*ctx
, TCGv addr
)
7682 TCGv t0
= tcg_temp_new();
7683 gen_qemu_ld16s(ctx
, t0
, addr
);
7684 #if defined(TARGET_PPC64)
7685 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7686 tcg_gen_ext32u_tl(t0
, t0
);
7687 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7689 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7690 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7695 static inline void gen_op_evlwhe(DisasContext
*ctx
, TCGv addr
)
7697 TCGv t0
= tcg_temp_new();
7698 #if defined(TARGET_PPC64)
7699 gen_qemu_ld16u(ctx
, t0
, addr
);
7700 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7701 gen_addr_add(ctx
, addr
, addr
, 2);
7702 gen_qemu_ld16u(ctx
, t0
, addr
);
7703 tcg_gen_shli_tl(t0
, t0
, 16);
7704 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7706 gen_qemu_ld16u(ctx
, t0
, addr
);
7707 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7708 gen_addr_add(ctx
, addr
, addr
, 2);
7709 gen_qemu_ld16u(ctx
, t0
, addr
);
7710 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
7715 static inline void gen_op_evlwhou(DisasContext
*ctx
, TCGv addr
)
7717 #if defined(TARGET_PPC64)
7718 TCGv t0
= tcg_temp_new();
7719 gen_qemu_ld16u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7720 gen_addr_add(ctx
, addr
, addr
, 2);
7721 gen_qemu_ld16u(ctx
, t0
, addr
);
7722 tcg_gen_shli_tl(t0
, t0
, 32);
7723 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7726 gen_qemu_ld16u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
7727 gen_addr_add(ctx
, addr
, addr
, 2);
7728 gen_qemu_ld16u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7732 static inline void gen_op_evlwhos(DisasContext
*ctx
, TCGv addr
)
7734 #if defined(TARGET_PPC64)
7735 TCGv t0
= tcg_temp_new();
7736 gen_qemu_ld16s(ctx
, t0
, addr
);
7737 tcg_gen_ext32u_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7738 gen_addr_add(ctx
, addr
, addr
, 2);
7739 gen_qemu_ld16s(ctx
, t0
, addr
);
7740 tcg_gen_shli_tl(t0
, t0
, 32);
7741 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7744 gen_qemu_ld16s(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
7745 gen_addr_add(ctx
, addr
, addr
, 2);
7746 gen_qemu_ld16s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7750 static inline void gen_op_evlwwsplat(DisasContext
*ctx
, TCGv addr
)
7752 TCGv t0
= tcg_temp_new();
7753 gen_qemu_ld32u(ctx
, t0
, addr
);
7754 #if defined(TARGET_PPC64)
7755 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7756 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7758 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7759 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7764 static inline void gen_op_evlwhsplat(DisasContext
*ctx
, TCGv addr
)
7766 TCGv t0
= tcg_temp_new();
7767 #if defined(TARGET_PPC64)
7768 gen_qemu_ld16u(ctx
, t0
, addr
);
7769 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7770 tcg_gen_shli_tl(t0
, t0
, 32);
7771 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7772 gen_addr_add(ctx
, addr
, addr
, 2);
7773 gen_qemu_ld16u(ctx
, t0
, addr
);
7774 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7775 tcg_gen_shli_tl(t0
, t0
, 16);
7776 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7778 gen_qemu_ld16u(ctx
, t0
, addr
);
7779 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7780 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
7781 gen_addr_add(ctx
, addr
, addr
, 2);
7782 gen_qemu_ld16u(ctx
, t0
, addr
);
7783 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
7784 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
7789 static inline void gen_op_evstdd(DisasContext
*ctx
, TCGv addr
)
7791 #if defined(TARGET_PPC64)
7792 gen_qemu_st64(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7794 TCGv_i64 t0
= tcg_temp_new_i64();
7795 tcg_gen_concat_i32_i64(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gprh
[rS(ctx
->opcode
)]);
7796 gen_qemu_st64(ctx
, t0
, addr
);
7797 tcg_temp_free_i64(t0
);
7801 static inline void gen_op_evstdw(DisasContext
*ctx
, TCGv addr
)
7803 #if defined(TARGET_PPC64)
7804 TCGv t0
= tcg_temp_new();
7805 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7806 gen_qemu_st32(ctx
, t0
, addr
);
7809 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7811 gen_addr_add(ctx
, addr
, addr
, 4);
7812 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7815 static inline void gen_op_evstdh(DisasContext
*ctx
, TCGv addr
)
7817 TCGv t0
= tcg_temp_new();
7818 #if defined(TARGET_PPC64)
7819 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 48);
7821 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
7823 gen_qemu_st16(ctx
, t0
, addr
);
7824 gen_addr_add(ctx
, addr
, addr
, 2);
7825 #if defined(TARGET_PPC64)
7826 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7827 gen_qemu_st16(ctx
, t0
, addr
);
7829 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7831 gen_addr_add(ctx
, addr
, addr
, 2);
7832 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
7833 gen_qemu_st16(ctx
, t0
, addr
);
7835 gen_addr_add(ctx
, addr
, addr
, 2);
7836 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7839 static inline void gen_op_evstwhe(DisasContext
*ctx
, TCGv addr
)
7841 TCGv t0
= tcg_temp_new();
7842 #if defined(TARGET_PPC64)
7843 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 48);
7845 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
7847 gen_qemu_st16(ctx
, t0
, addr
);
7848 gen_addr_add(ctx
, addr
, addr
, 2);
7849 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
7850 gen_qemu_st16(ctx
, t0
, addr
);
7854 static inline void gen_op_evstwho(DisasContext
*ctx
, TCGv addr
)
7856 #if defined(TARGET_PPC64)
7857 TCGv t0
= tcg_temp_new();
7858 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7859 gen_qemu_st16(ctx
, t0
, addr
);
7862 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7864 gen_addr_add(ctx
, addr
, addr
, 2);
7865 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7868 static inline void gen_op_evstwwe(DisasContext
*ctx
, TCGv addr
)
7870 #if defined(TARGET_PPC64)
7871 TCGv t0
= tcg_temp_new();
7872 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7873 gen_qemu_st32(ctx
, t0
, addr
);
7876 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7880 static inline void gen_op_evstwwo(DisasContext
*ctx
, TCGv addr
)
7882 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7885 #define GEN_SPEOP_LDST(name, opc2, sh) \
7886 static void glue(gen_, name)(DisasContext *ctx) \
7889 if (unlikely(!ctx->spe_enabled)) { \
7890 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7893 gen_set_access_type(ctx, ACCESS_INT); \
7894 t0 = tcg_temp_new(); \
7895 if (Rc(ctx->opcode)) { \
7896 gen_addr_spe_imm_index(ctx, t0, sh); \
7898 gen_addr_reg_index(ctx, t0); \
7900 gen_op_##name(ctx, t0); \
7901 tcg_temp_free(t0); \
7904 GEN_SPEOP_LDST(evldd
, 0x00, 3);
7905 GEN_SPEOP_LDST(evldw
, 0x01, 3);
7906 GEN_SPEOP_LDST(evldh
, 0x02, 3);
7907 GEN_SPEOP_LDST(evlhhesplat
, 0x04, 1);
7908 GEN_SPEOP_LDST(evlhhousplat
, 0x06, 1);
7909 GEN_SPEOP_LDST(evlhhossplat
, 0x07, 1);
7910 GEN_SPEOP_LDST(evlwhe
, 0x08, 2);
7911 GEN_SPEOP_LDST(evlwhou
, 0x0A, 2);
7912 GEN_SPEOP_LDST(evlwhos
, 0x0B, 2);
7913 GEN_SPEOP_LDST(evlwwsplat
, 0x0C, 2);
7914 GEN_SPEOP_LDST(evlwhsplat
, 0x0E, 2);
7916 GEN_SPEOP_LDST(evstdd
, 0x10, 3);
7917 GEN_SPEOP_LDST(evstdw
, 0x11, 3);
7918 GEN_SPEOP_LDST(evstdh
, 0x12, 3);
7919 GEN_SPEOP_LDST(evstwhe
, 0x18, 2);
7920 GEN_SPEOP_LDST(evstwho
, 0x1A, 2);
7921 GEN_SPEOP_LDST(evstwwe
, 0x1C, 2);
7922 GEN_SPEOP_LDST(evstwwo
, 0x1E, 2);
7924 /* Multiply and add - TODO */
7926 GEN_SPE(speundef
, evmhessf
, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);//
7927 GEN_SPE(speundef
, evmhossf
, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7928 GEN_SPE(evmheumi
, evmhesmi
, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
7929 GEN_SPE(speundef
, evmhesmf
, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7930 GEN_SPE(evmhoumi
, evmhosmi
, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
7931 GEN_SPE(speundef
, evmhosmf
, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7932 GEN_SPE(speundef
, evmhessfa
, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7933 GEN_SPE(speundef
, evmhossfa
, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7934 GEN_SPE(evmheumia
, evmhesmia
, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
7935 GEN_SPE(speundef
, evmhesmfa
, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7936 GEN_SPE(evmhoumia
, evmhosmia
, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
7937 GEN_SPE(speundef
, evmhosmfa
, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7939 GEN_SPE(speundef
, evmwhssf
, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7940 GEN_SPE(evmwlumi
, speundef
, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
7941 GEN_SPE(evmwhumi
, evmwhsmi
, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
7942 GEN_SPE(speundef
, evmwhsmf
, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7943 GEN_SPE(speundef
, evmwssf
, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7944 GEN_SPE(speundef
, evmwsmf
, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7945 GEN_SPE(speundef
, evmwhssfa
, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7946 GEN_SPE(evmwlumia
, speundef
, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
7947 GEN_SPE(evmwhumia
, evmwhsmia
, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
7948 GEN_SPE(speundef
, evmwhsmfa
, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7949 GEN_SPE(speundef
, evmwssfa
, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7950 GEN_SPE(speundef
, evmwsmfa
, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7952 GEN_SPE(evadduiaaw
, evaddsiaaw
, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
7953 GEN_SPE(evsubfusiaaw
, evsubfssiaaw
, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
7954 GEN_SPE(evaddumiaaw
, evaddsmiaaw
, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
7955 GEN_SPE(evsubfumiaaw
, evsubfsmiaaw
, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
7956 GEN_SPE(evdivws
, evdivwu
, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE
);
7958 GEN_SPE(evmheusiaaw
, evmhessiaaw
, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
7959 GEN_SPE(speundef
, evmhessfaaw
, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7960 GEN_SPE(evmhousiaaw
, evmhossiaaw
, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
7961 GEN_SPE(speundef
, evmhossfaaw
, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7962 GEN_SPE(evmheumiaaw
, evmhesmiaaw
, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
7963 GEN_SPE(speundef
, evmhesmfaaw
, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7964 GEN_SPE(evmhoumiaaw
, evmhosmiaaw
, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
7965 GEN_SPE(speundef
, evmhosmfaaw
, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7966 GEN_SPE(evmhegumiaa
, evmhegsmiaa
, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
7967 GEN_SPE(speundef
, evmhegsmfaa
, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7968 GEN_SPE(evmhogumiaa
, evmhogsmiaa
, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
7969 GEN_SPE(speundef
, evmhogsmfaa
, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7971 GEN_SPE(evmwlusiaaw
, evmwlssiaaw
, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
7972 GEN_SPE(evmwlumiaaw
, evmwlsmiaaw
, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
7973 GEN_SPE(speundef
, evmwssfaa
, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7974 GEN_SPE(speundef
, evmwsmfaa
, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7976 GEN_SPE(evmheusianw
, evmhessianw
, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
7977 GEN_SPE(speundef
, evmhessfanw
, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7978 GEN_SPE(evmhousianw
, evmhossianw
, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
7979 GEN_SPE(speundef
, evmhossfanw
, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7980 GEN_SPE(evmheumianw
, evmhesmianw
, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
7981 GEN_SPE(speundef
, evmhesmfanw
, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7982 GEN_SPE(evmhoumianw
, evmhosmianw
, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
7983 GEN_SPE(speundef
, evmhosmfanw
, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7984 GEN_SPE(evmhegumian
, evmhegsmian
, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
7985 GEN_SPE(speundef
, evmhegsmfan
, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7986 GEN_SPE(evmhigumian
, evmhigsmian
, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
7987 GEN_SPE(speundef
, evmhogsmfan
, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7989 GEN_SPE(evmwlusianw
, evmwlssianw
, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
7990 GEN_SPE(evmwlumianw
, evmwlsmianw
, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
7991 GEN_SPE(speundef
, evmwssfan
, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7992 GEN_SPE(evmwumian
, evmwsmian
, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
7993 GEN_SPE(speundef
, evmwsmfan
, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
7996 /*** SPE floating-point extension ***/
7997 #if defined(TARGET_PPC64)
7998 #define GEN_SPEFPUOP_CONV_32_32(name) \
7999 static inline void gen_##name(DisasContext *ctx) \
8003 t0 = tcg_temp_new_i32(); \
8004 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8005 gen_helper_##name(t0, cpu_env, t0); \
8006 t1 = tcg_temp_new(); \
8007 tcg_gen_extu_i32_tl(t1, t0); \
8008 tcg_temp_free_i32(t0); \
8009 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8010 0xFFFFFFFF00000000ULL); \
8011 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8012 tcg_temp_free(t1); \
8014 #define GEN_SPEFPUOP_CONV_32_64(name) \
8015 static inline void gen_##name(DisasContext *ctx) \
8019 t0 = tcg_temp_new_i32(); \
8020 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8021 t1 = tcg_temp_new(); \
8022 tcg_gen_extu_i32_tl(t1, t0); \
8023 tcg_temp_free_i32(t0); \
8024 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8025 0xFFFFFFFF00000000ULL); \
8026 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8027 tcg_temp_free(t1); \
8029 #define GEN_SPEFPUOP_CONV_64_32(name) \
8030 static inline void gen_##name(DisasContext *ctx) \
8032 TCGv_i32 t0 = tcg_temp_new_i32(); \
8033 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8034 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8035 tcg_temp_free_i32(t0); \
8037 #define GEN_SPEFPUOP_CONV_64_64(name) \
8038 static inline void gen_##name(DisasContext *ctx) \
8040 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8041 cpu_gpr[rB(ctx->opcode)]); \
8043 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8044 static inline void gen_##name(DisasContext *ctx) \
8048 if (unlikely(!ctx->spe_enabled)) { \
8049 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8052 t0 = tcg_temp_new_i32(); \
8053 t1 = tcg_temp_new_i32(); \
8054 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8055 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8056 gen_helper_##name(t0, cpu_env, t0, t1); \
8057 tcg_temp_free_i32(t1); \
8058 t2 = tcg_temp_new(); \
8059 tcg_gen_extu_i32_tl(t2, t0); \
8060 tcg_temp_free_i32(t0); \
8061 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8062 0xFFFFFFFF00000000ULL); \
8063 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8064 tcg_temp_free(t2); \
8066 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8067 static inline void gen_##name(DisasContext *ctx) \
8069 if (unlikely(!ctx->spe_enabled)) { \
8070 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8073 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8074 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8076 #define GEN_SPEFPUOP_COMP_32(name) \
8077 static inline void gen_##name(DisasContext *ctx) \
8080 if (unlikely(!ctx->spe_enabled)) { \
8081 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8084 t0 = tcg_temp_new_i32(); \
8085 t1 = tcg_temp_new_i32(); \
8086 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8087 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8088 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8089 tcg_temp_free_i32(t0); \
8090 tcg_temp_free_i32(t1); \
8092 #define GEN_SPEFPUOP_COMP_64(name) \
8093 static inline void gen_##name(DisasContext *ctx) \
8095 if (unlikely(!ctx->spe_enabled)) { \
8096 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8099 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8100 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8103 #define GEN_SPEFPUOP_CONV_32_32(name) \
8104 static inline void gen_##name(DisasContext *ctx) \
8106 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8107 cpu_gpr[rB(ctx->opcode)]); \
8109 #define GEN_SPEFPUOP_CONV_32_64(name) \
8110 static inline void gen_##name(DisasContext *ctx) \
8112 TCGv_i64 t0 = tcg_temp_new_i64(); \
8113 gen_load_gpr64(t0, rB(ctx->opcode)); \
8114 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8115 tcg_temp_free_i64(t0); \
8117 #define GEN_SPEFPUOP_CONV_64_32(name) \
8118 static inline void gen_##name(DisasContext *ctx) \
8120 TCGv_i64 t0 = tcg_temp_new_i64(); \
8121 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8122 gen_store_gpr64(rD(ctx->opcode), t0); \
8123 tcg_temp_free_i64(t0); \
8125 #define GEN_SPEFPUOP_CONV_64_64(name) \
8126 static inline void gen_##name(DisasContext *ctx) \
8128 TCGv_i64 t0 = tcg_temp_new_i64(); \
8129 gen_load_gpr64(t0, rB(ctx->opcode)); \
8130 gen_helper_##name(t0, cpu_env, t0); \
8131 gen_store_gpr64(rD(ctx->opcode), t0); \
8132 tcg_temp_free_i64(t0); \
8134 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8135 static inline void gen_##name(DisasContext *ctx) \
8137 if (unlikely(!ctx->spe_enabled)) { \
8138 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8141 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8142 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8144 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8145 static inline void gen_##name(DisasContext *ctx) \
8148 if (unlikely(!ctx->spe_enabled)) { \
8149 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8152 t0 = tcg_temp_new_i64(); \
8153 t1 = tcg_temp_new_i64(); \
8154 gen_load_gpr64(t0, rA(ctx->opcode)); \
8155 gen_load_gpr64(t1, rB(ctx->opcode)); \
8156 gen_helper_##name(t0, cpu_env, t0, t1); \
8157 gen_store_gpr64(rD(ctx->opcode), t0); \
8158 tcg_temp_free_i64(t0); \
8159 tcg_temp_free_i64(t1); \
8161 #define GEN_SPEFPUOP_COMP_32(name) \
8162 static inline void gen_##name(DisasContext *ctx) \
8164 if (unlikely(!ctx->spe_enabled)) { \
8165 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8168 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8169 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8171 #define GEN_SPEFPUOP_COMP_64(name) \
8172 static inline void gen_##name(DisasContext *ctx) \
8175 if (unlikely(!ctx->spe_enabled)) { \
8176 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8179 t0 = tcg_temp_new_i64(); \
8180 t1 = tcg_temp_new_i64(); \
8181 gen_load_gpr64(t0, rA(ctx->opcode)); \
8182 gen_load_gpr64(t1, rB(ctx->opcode)); \
8183 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8184 tcg_temp_free_i64(t0); \
8185 tcg_temp_free_i64(t1); \
8189 /* Single precision floating-point vectors operations */
8191 GEN_SPEFPUOP_ARITH2_64_64(evfsadd
);
8192 GEN_SPEFPUOP_ARITH2_64_64(evfssub
);
8193 GEN_SPEFPUOP_ARITH2_64_64(evfsmul
);
8194 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv
);
8195 static inline void gen_evfsabs(DisasContext
*ctx
)
8197 if (unlikely(!ctx
->spe_enabled
)) {
8198 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8201 #if defined(TARGET_PPC64)
8202 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~0x8000000080000000LL
);
8204 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~0x80000000);
8205 tcg_gen_andi_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], ~0x80000000);
8208 static inline void gen_evfsnabs(DisasContext
*ctx
)
8210 if (unlikely(!ctx
->spe_enabled
)) {
8211 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8214 #if defined(TARGET_PPC64)
8215 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000080000000LL
);
8217 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8218 tcg_gen_ori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8221 static inline void gen_evfsneg(DisasContext
*ctx
)
8223 if (unlikely(!ctx
->spe_enabled
)) {
8224 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8227 #if defined(TARGET_PPC64)
8228 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000080000000LL
);
8230 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8231 tcg_gen_xori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8236 GEN_SPEFPUOP_CONV_64_64(evfscfui
);
8237 GEN_SPEFPUOP_CONV_64_64(evfscfsi
);
8238 GEN_SPEFPUOP_CONV_64_64(evfscfuf
);
8239 GEN_SPEFPUOP_CONV_64_64(evfscfsf
);
8240 GEN_SPEFPUOP_CONV_64_64(evfsctui
);
8241 GEN_SPEFPUOP_CONV_64_64(evfsctsi
);
8242 GEN_SPEFPUOP_CONV_64_64(evfsctuf
);
8243 GEN_SPEFPUOP_CONV_64_64(evfsctsf
);
8244 GEN_SPEFPUOP_CONV_64_64(evfsctuiz
);
8245 GEN_SPEFPUOP_CONV_64_64(evfsctsiz
);
8248 GEN_SPEFPUOP_COMP_64(evfscmpgt
);
8249 GEN_SPEFPUOP_COMP_64(evfscmplt
);
8250 GEN_SPEFPUOP_COMP_64(evfscmpeq
);
8251 GEN_SPEFPUOP_COMP_64(evfststgt
);
8252 GEN_SPEFPUOP_COMP_64(evfststlt
);
8253 GEN_SPEFPUOP_COMP_64(evfststeq
);
8255 /* Opcodes definitions */
8256 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
8257 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
); //
8258 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8259 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
8260 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
8261 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8262 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8263 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8264 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8265 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8266 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8267 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8268 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
8269 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8271 /* Single precision floating-point operations */
8273 GEN_SPEFPUOP_ARITH2_32_32(efsadd
);
8274 GEN_SPEFPUOP_ARITH2_32_32(efssub
);
8275 GEN_SPEFPUOP_ARITH2_32_32(efsmul
);
8276 GEN_SPEFPUOP_ARITH2_32_32(efsdiv
);
8277 static inline void gen_efsabs(DisasContext
*ctx
)
8279 if (unlikely(!ctx
->spe_enabled
)) {
8280 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8283 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], (target_long
)~0x80000000LL
);
8285 static inline void gen_efsnabs(DisasContext
*ctx
)
8287 if (unlikely(!ctx
->spe_enabled
)) {
8288 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8291 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8293 static inline void gen_efsneg(DisasContext
*ctx
)
8295 if (unlikely(!ctx
->spe_enabled
)) {
8296 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8299 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8303 GEN_SPEFPUOP_CONV_32_32(efscfui
);
8304 GEN_SPEFPUOP_CONV_32_32(efscfsi
);
8305 GEN_SPEFPUOP_CONV_32_32(efscfuf
);
8306 GEN_SPEFPUOP_CONV_32_32(efscfsf
);
8307 GEN_SPEFPUOP_CONV_32_32(efsctui
);
8308 GEN_SPEFPUOP_CONV_32_32(efsctsi
);
8309 GEN_SPEFPUOP_CONV_32_32(efsctuf
);
8310 GEN_SPEFPUOP_CONV_32_32(efsctsf
);
8311 GEN_SPEFPUOP_CONV_32_32(efsctuiz
);
8312 GEN_SPEFPUOP_CONV_32_32(efsctsiz
);
8313 GEN_SPEFPUOP_CONV_32_64(efscfd
);
8316 GEN_SPEFPUOP_COMP_32(efscmpgt
);
8317 GEN_SPEFPUOP_COMP_32(efscmplt
);
8318 GEN_SPEFPUOP_COMP_32(efscmpeq
);
8319 GEN_SPEFPUOP_COMP_32(efststgt
);
8320 GEN_SPEFPUOP_COMP_32(efststlt
);
8321 GEN_SPEFPUOP_COMP_32(efststeq
);
8323 /* Opcodes definitions */
8324 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
8325 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
); //
8326 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8327 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
8328 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
8329 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE
); //
8330 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8331 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8332 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8333 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8334 GEN_SPE(efsctuiz
, speundef
, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8335 GEN_SPE(efsctsiz
, speundef
, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8336 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
8337 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8339 /* Double precision floating-point operations */
8341 GEN_SPEFPUOP_ARITH2_64_64(efdadd
);
8342 GEN_SPEFPUOP_ARITH2_64_64(efdsub
);
8343 GEN_SPEFPUOP_ARITH2_64_64(efdmul
);
8344 GEN_SPEFPUOP_ARITH2_64_64(efddiv
);
8345 static inline void gen_efdabs(DisasContext
*ctx
)
8347 if (unlikely(!ctx
->spe_enabled
)) {
8348 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8351 #if defined(TARGET_PPC64)
8352 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~0x8000000000000000LL
);
8354 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8355 tcg_gen_andi_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], ~0x80000000);
8358 static inline void gen_efdnabs(DisasContext
*ctx
)
8360 if (unlikely(!ctx
->spe_enabled
)) {
8361 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8364 #if defined(TARGET_PPC64)
8365 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000000000000LL
);
8367 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8368 tcg_gen_ori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8371 static inline void gen_efdneg(DisasContext
*ctx
)
8373 if (unlikely(!ctx
->spe_enabled
)) {
8374 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8377 #if defined(TARGET_PPC64)
8378 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000000000000LL
);
8380 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8381 tcg_gen_xori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8386 GEN_SPEFPUOP_CONV_64_32(efdcfui
);
8387 GEN_SPEFPUOP_CONV_64_32(efdcfsi
);
8388 GEN_SPEFPUOP_CONV_64_32(efdcfuf
);
8389 GEN_SPEFPUOP_CONV_64_32(efdcfsf
);
8390 GEN_SPEFPUOP_CONV_32_64(efdctui
);
8391 GEN_SPEFPUOP_CONV_32_64(efdctsi
);
8392 GEN_SPEFPUOP_CONV_32_64(efdctuf
);
8393 GEN_SPEFPUOP_CONV_32_64(efdctsf
);
8394 GEN_SPEFPUOP_CONV_32_64(efdctuiz
);
8395 GEN_SPEFPUOP_CONV_32_64(efdctsiz
);
8396 GEN_SPEFPUOP_CONV_64_32(efdcfs
);
8397 GEN_SPEFPUOP_CONV_64_64(efdcfuid
);
8398 GEN_SPEFPUOP_CONV_64_64(efdcfsid
);
8399 GEN_SPEFPUOP_CONV_64_64(efdctuidz
);
8400 GEN_SPEFPUOP_CONV_64_64(efdctsidz
);
8403 GEN_SPEFPUOP_COMP_64(efdcmpgt
);
8404 GEN_SPEFPUOP_COMP_64(efdcmplt
);
8405 GEN_SPEFPUOP_COMP_64(efdcmpeq
);
8406 GEN_SPEFPUOP_COMP_64(efdtstgt
);
8407 GEN_SPEFPUOP_COMP_64(efdtstlt
);
8408 GEN_SPEFPUOP_COMP_64(efdtsteq
);
8410 /* Opcodes definitions */
8411 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
); //
8412 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8413 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE
); //
8414 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
8415 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
); //
8416 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8417 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
); //
8418 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE
); //
8419 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8420 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8421 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8422 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8423 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
8424 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
8425 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
); //
8426 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
8428 static opcode_t opcodes
[] = {
8429 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
),
8430 GEN_HANDLER(cmp
, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER
),
8431 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
8432 GEN_HANDLER(cmpl
, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER
),
8433 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
8434 GEN_HANDLER(isel
, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL
),
8435 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8436 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8437 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8438 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8439 GEN_HANDLER(mulhw
, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER
),
8440 GEN_HANDLER(mulhwu
, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER
),
8441 GEN_HANDLER(mullw
, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER
),
8442 GEN_HANDLER(mullwo
, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER
),
8443 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8444 #if defined(TARGET_PPC64)
8445 GEN_HANDLER(mulld
, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B
),
8447 GEN_HANDLER(neg
, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER
),
8448 GEN_HANDLER(nego
, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER
),
8449 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8450 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8451 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8452 GEN_HANDLER(cntlzw
, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER
),
8453 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
),
8454 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
),
8455 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8456 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8457 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8458 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8459 GEN_HANDLER(popcntb
, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB
),
8460 GEN_HANDLER(popcntw
, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD
),
8461 #if defined(TARGET_PPC64)
8462 GEN_HANDLER(popcntd
, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD
),
8463 GEN_HANDLER(cntlzd
, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B
),
8465 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8466 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8467 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8468 GEN_HANDLER(slw
, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER
),
8469 GEN_HANDLER(sraw
, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER
),
8470 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
),
8471 GEN_HANDLER(srw
, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER
),
8472 #if defined(TARGET_PPC64)
8473 GEN_HANDLER(sld
, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B
),
8474 GEN_HANDLER(srad
, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B
),
8475 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
),
8476 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
),
8477 GEN_HANDLER(srd
, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B
),
8479 GEN_HANDLER(frsqrtes
, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES
),
8480 GEN_HANDLER(fsqrt
, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
),
8481 GEN_HANDLER(fsqrts
, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
),
8482 GEN_HANDLER(fcmpo
, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT
),
8483 GEN_HANDLER(fcmpu
, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT
),
8484 GEN_HANDLER(fmr
, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT
),
8485 GEN_HANDLER(mcrfs
, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT
),
8486 GEN_HANDLER(mffs
, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT
),
8487 GEN_HANDLER(mtfsb0
, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT
),
8488 GEN_HANDLER(mtfsb1
, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT
),
8489 GEN_HANDLER(mtfsf
, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT
),
8490 GEN_HANDLER(mtfsfi
, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT
),
8491 #if defined(TARGET_PPC64)
8492 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
),
8493 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
),
8494 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
),
8496 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8497 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8498 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING
),
8499 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING
),
8500 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING
),
8501 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING
),
8502 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO
),
8503 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
),
8504 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES
),
8505 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
),
8506 #if defined(TARGET_PPC64)
8507 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B
),
8508 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
),
8510 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
),
8511 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
),
8512 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
8513 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
8514 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
),
8515 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
),
8516 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
),
8517 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
),
8518 #if defined(TARGET_PPC64)
8519 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
),
8520 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H
),
8522 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
),
8523 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
),
8524 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
8525 #if defined(TARGET_PPC64)
8526 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
),
8527 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
),
8529 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
),
8530 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
),
8531 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
),
8532 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
),
8533 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
),
8534 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
),
8535 #if defined(TARGET_PPC64)
8536 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
),
8538 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC
),
8539 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC
),
8540 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
),
8541 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
),
8542 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
),
8543 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE
),
8544 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE
),
8545 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ
),
8546 GEN_HANDLER(dst
, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC
),
8547 GEN_HANDLER(dstst
, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC
),
8548 GEN_HANDLER(dss
, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC
),
8549 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
),
8550 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
),
8551 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
),
8552 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
),
8553 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
),
8554 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
),
8555 #if defined(TARGET_PPC64)
8556 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
),
8557 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8559 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
),
8560 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8562 GEN_HANDLER2(slbmte
, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B
),
8563 GEN_HANDLER2(slbmfee
, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B
),
8564 GEN_HANDLER2(slbmfev
, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B
),
8566 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
),
8567 GEN_HANDLER(tlbiel
, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE
),
8568 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE
),
8569 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
),
8570 #if defined(TARGET_PPC64)
8571 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI
),
8572 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
),
8574 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
),
8575 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
),
8576 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
),
8577 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
),
8578 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
),
8579 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
),
8580 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
),
8581 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
),
8582 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
),
8583 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
),
8584 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
),
8585 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
8586 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
),
8587 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
),
8588 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
),
8589 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
),
8590 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
),
8591 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
),
8592 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
),
8593 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
8594 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
),
8595 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
),
8596 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
),
8597 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
),
8598 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
),
8599 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
),
8600 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
),
8601 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
),
8602 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
),
8603 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
),
8604 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
),
8605 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
),
8606 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
),
8607 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
),
8608 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
),
8609 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
),
8610 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
),
8611 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
),
8612 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
),
8613 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
),
8614 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
),
8615 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
),
8616 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
),
8617 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
),
8618 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
),
8619 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
),
8620 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
),
8621 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
),
8622 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
),
8623 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
8624 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
8625 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
),
8626 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
),
8627 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
8628 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
8629 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
),
8630 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
),
8631 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI
),
8632 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA
),
8633 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR
),
8634 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR
),
8635 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX
),
8636 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX
),
8637 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
),
8638 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
),
8639 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
),
8640 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
),
8641 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
),
8642 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
),
8643 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
),
8644 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
),
8645 GEN_HANDLER_E(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
, PPC2_BOOKE206
),
8646 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI
),
8647 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
),
8648 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
),
8649 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
),
8650 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
),
8651 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
),
8652 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
),
8653 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
),
8654 GEN_HANDLER2_E(tlbre_booke206
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8655 PPC_NONE
, PPC2_BOOKE206
),
8656 GEN_HANDLER2_E(tlbsx_booke206
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8657 PPC_NONE
, PPC2_BOOKE206
),
8658 GEN_HANDLER2_E(tlbwe_booke206
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8659 PPC_NONE
, PPC2_BOOKE206
),
8660 GEN_HANDLER2_E(tlbivax_booke206
, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8661 PPC_NONE
, PPC2_BOOKE206
),
8662 GEN_HANDLER2_E(tlbilx_booke206
, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8663 PPC_NONE
, PPC2_BOOKE206
),
8664 GEN_HANDLER2_E(msgsnd
, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8665 PPC_NONE
, PPC2_PRCNTL
),
8666 GEN_HANDLER2_E(msgclr
, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8667 PPC_NONE
, PPC2_PRCNTL
),
8668 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE
),
8669 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE
),
8670 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
),
8671 GEN_HANDLER_E(mbar
, 0x1F, 0x16, 0x1a, 0x001FF801,
8672 PPC_BOOKE
, PPC2_BOOKE206
),
8673 GEN_HANDLER(msync_4xx
, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE
),
8674 GEN_HANDLER2_E(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8675 PPC_BOOKE
, PPC2_BOOKE206
),
8676 GEN_HANDLER(lvsl
, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC
),
8677 GEN_HANDLER(lvsr
, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC
),
8678 GEN_HANDLER(mfvscr
, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC
),
8679 GEN_HANDLER(mtvscr
, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC
),
8680 GEN_HANDLER(vsldoi
, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC
),
8681 GEN_HANDLER(vmladduhm
, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC
),
8682 GEN_HANDLER2(evsel0
, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE
),
8683 GEN_HANDLER2(evsel1
, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE
),
8684 GEN_HANDLER2(evsel2
, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE
),
8685 GEN_HANDLER2(evsel3
, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE
),
8687 #undef GEN_INT_ARITH_ADD
8688 #undef GEN_INT_ARITH_ADD_CONST
8689 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8690 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8691 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8692 add_ca, compute_ca, compute_ov) \
8693 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8694 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
8695 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
8696 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
8697 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
8698 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
8699 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
8700 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
8701 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
8702 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
8703 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
8705 #undef GEN_INT_ARITH_DIVW
8706 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8707 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8708 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0),
8709 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1),
8710 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0),
8711 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1),
8713 #if defined(TARGET_PPC64)
8714 #undef GEN_INT_ARITH_DIVD
8715 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8716 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8717 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0),
8718 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1),
8719 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0),
8720 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1),
8722 #undef GEN_INT_ARITH_MUL_HELPER
8723 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8724 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8725 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00),
8726 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02),
8727 GEN_INT_ARITH_MUL_HELPER(mulldo
, 0x17),
8730 #undef GEN_INT_ARITH_SUBF
8731 #undef GEN_INT_ARITH_SUBF_CONST
8732 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8733 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8734 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8735 add_ca, compute_ca, compute_ov) \
8736 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8737 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
8738 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
8739 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
8740 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
8741 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
8742 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
8743 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
8744 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
8745 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
8746 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
8750 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8751 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8752 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8753 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8754 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
),
8755 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
),
8756 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
),
8757 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
),
8758 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
),
8759 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
),
8760 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
),
8761 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
),
8762 #if defined(TARGET_PPC64)
8763 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
),
8766 #if defined(TARGET_PPC64)
8769 #define GEN_PPC64_R2(name, opc1, opc2) \
8770 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8771 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8773 #define GEN_PPC64_R4(name, opc1, opc2) \
8774 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8775 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8777 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8779 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8781 GEN_PPC64_R4(rldicl
, 0x1E, 0x00),
8782 GEN_PPC64_R4(rldicr
, 0x1E, 0x02),
8783 GEN_PPC64_R4(rldic
, 0x1E, 0x04),
8784 GEN_PPC64_R2(rldcl
, 0x1E, 0x08),
8785 GEN_PPC64_R2(rldcr
, 0x1E, 0x09),
8786 GEN_PPC64_R4(rldimi
, 0x1E, 0x06),
8789 #undef _GEN_FLOAT_ACB
8790 #undef GEN_FLOAT_ACB
8791 #undef _GEN_FLOAT_AB
8793 #undef _GEN_FLOAT_AC
8797 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8798 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8799 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8800 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8801 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8802 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8803 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8804 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8805 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8806 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8807 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8808 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8809 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8810 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8811 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8812 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8813 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8814 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8815 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8817 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
),
8818 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
),
8819 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
),
8820 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
),
8821 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
),
8822 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
),
8823 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
),
8824 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
),
8825 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
),
8826 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
),
8827 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
),
8828 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
),
8829 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
),
8830 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
),
8831 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
),
8832 #if defined(TARGET_PPC64)
8833 GEN_FLOAT_B(cfid
, 0x0E, 0x1A, 1, PPC_64B
),
8834 GEN_FLOAT_B(ctid
, 0x0E, 0x19, 0, PPC_64B
),
8835 GEN_FLOAT_B(ctidz
, 0x0F, 0x19, 0, PPC_64B
),
8837 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
),
8838 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
),
8839 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
),
8840 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
),
8841 GEN_FLOAT_B(abs
, 0x08, 0x08, 0, PPC_FLOAT
),
8842 GEN_FLOAT_B(nabs
, 0x08, 0x04, 0, PPC_FLOAT
),
8843 GEN_FLOAT_B(neg
, 0x08, 0x01, 0, PPC_FLOAT
),
8850 #define GEN_LD(name, ldop, opc, type) \
8851 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8852 #define GEN_LDU(name, ldop, opc, type) \
8853 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8854 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8855 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8856 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8857 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8858 #define GEN_LDS(name, ldop, op, type) \
8859 GEN_LD(name, ldop, op | 0x20, type) \
8860 GEN_LDU(name, ldop, op | 0x21, type) \
8861 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8862 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8864 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
)
8865 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
)
8866 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
)
8867 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
)
8868 #if defined(TARGET_PPC64)
8869 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
)
8870 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
)
8871 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
)
8872 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
)
8873 GEN_LDX_E(ldbr
, ld64ur
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
)
8875 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
)
8876 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
)
8883 #define GEN_ST(name, stop, opc, type) \
8884 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8885 #define GEN_STU(name, stop, opc, type) \
8886 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8887 #define GEN_STUX(name, stop, opc2, opc3, type) \
8888 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8889 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
8890 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8891 #define GEN_STS(name, stop, op, type) \
8892 GEN_ST(name, stop, op | 0x20, type) \
8893 GEN_STU(name, stop, op | 0x21, type) \
8894 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8895 GEN_STX(name, stop, 0x17, op | 0x00, type)
8897 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
)
8898 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
)
8899 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
)
8900 #if defined(TARGET_PPC64)
8901 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
)
8902 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
)
8903 GEN_STX_E(stdbr
, st64r
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
)
8905 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
)
8906 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
)
8913 #define GEN_LDF(name, ldop, opc, type) \
8914 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8915 #define GEN_LDUF(name, ldop, opc, type) \
8916 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8917 #define GEN_LDUXF(name, ldop, opc, type) \
8918 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8919 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
8920 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8921 #define GEN_LDFS(name, ldop, op, type) \
8922 GEN_LDF(name, ldop, op | 0x20, type) \
8923 GEN_LDUF(name, ldop, op | 0x21, type) \
8924 GEN_LDUXF(name, ldop, op | 0x01, type) \
8925 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
8927 GEN_LDFS(lfd
, ld64
, 0x12, PPC_FLOAT
)
8928 GEN_LDFS(lfs
, ld32fs
, 0x10, PPC_FLOAT
)
8935 #define GEN_STF(name, stop, opc, type) \
8936 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8937 #define GEN_STUF(name, stop, opc, type) \
8938 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8939 #define GEN_STUXF(name, stop, opc, type) \
8940 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8941 #define GEN_STXF(name, stop, opc2, opc3, type) \
8942 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8943 #define GEN_STFS(name, stop, op, type) \
8944 GEN_STF(name, stop, op | 0x20, type) \
8945 GEN_STUF(name, stop, op | 0x21, type) \
8946 GEN_STUXF(name, stop, op | 0x01, type) \
8947 GEN_STXF(name, stop, 0x17, op | 0x00, type)
8949 GEN_STFS(stfd
, st64
, 0x16, PPC_FLOAT
)
8950 GEN_STFS(stfs
, st32fs
, 0x14, PPC_FLOAT
)
8951 GEN_STXF(stfiw
, st32fiw
, 0x17, 0x1E, PPC_FLOAT_STFIWX
)
8954 #define GEN_CRLOGIC(name, tcg_op, opc) \
8955 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8956 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08),
8957 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04),
8958 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09),
8959 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07),
8960 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01),
8961 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E),
8962 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D),
8963 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06),
8965 #undef GEN_MAC_HANDLER
8966 #define GEN_MAC_HANDLER(name, opc2, opc3) \
8967 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8968 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05),
8969 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15),
8970 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07),
8971 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17),
8972 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06),
8973 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16),
8974 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04),
8975 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14),
8976 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01),
8977 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11),
8978 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03),
8979 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13),
8980 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02),
8981 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12),
8982 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00),
8983 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10),
8984 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D),
8985 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D),
8986 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F),
8987 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F),
8988 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C),
8989 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C),
8990 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E),
8991 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E),
8992 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05),
8993 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15),
8994 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07),
8995 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17),
8996 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01),
8997 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11),
8998 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03),
8999 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13),
9000 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D),
9001 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D),
9002 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F),
9003 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F),
9004 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05),
9005 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04),
9006 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01),
9007 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00),
9008 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D),
9009 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C),
9015 #define GEN_VR_LDX(name, opc2, opc3) \
9016 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9017 #define GEN_VR_STX(name, opc2, opc3) \
9018 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9019 #define GEN_VR_LVE(name, opc2, opc3) \
9020 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9021 #define GEN_VR_STVE(name, opc2, opc3) \
9022 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9023 GEN_VR_LDX(lvx
, 0x07, 0x03),
9024 GEN_VR_LDX(lvxl
, 0x07, 0x0B),
9025 GEN_VR_LVE(bx
, 0x07, 0x00),
9026 GEN_VR_LVE(hx
, 0x07, 0x01),
9027 GEN_VR_LVE(wx
, 0x07, 0x02),
9028 GEN_VR_STX(svx
, 0x07, 0x07),
9029 GEN_VR_STX(svxl
, 0x07, 0x0F),
9030 GEN_VR_STVE(bx
, 0x07, 0x04),
9031 GEN_VR_STVE(hx
, 0x07, 0x05),
9032 GEN_VR_STVE(wx
, 0x07, 0x06),
9034 #undef GEN_VX_LOGICAL
9035 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9036 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9037 GEN_VX_LOGICAL(vand
, tcg_gen_and_i64
, 2, 16),
9038 GEN_VX_LOGICAL(vandc
, tcg_gen_andc_i64
, 2, 17),
9039 GEN_VX_LOGICAL(vor
, tcg_gen_or_i64
, 2, 18),
9040 GEN_VX_LOGICAL(vxor
, tcg_gen_xor_i64
, 2, 19),
9041 GEN_VX_LOGICAL(vnor
, tcg_gen_nor_i64
, 2, 20),
9044 #define GEN_VXFORM(name, opc2, opc3) \
9045 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9046 GEN_VXFORM(vaddubm
, 0, 0),
9047 GEN_VXFORM(vadduhm
, 0, 1),
9048 GEN_VXFORM(vadduwm
, 0, 2),
9049 GEN_VXFORM(vsububm
, 0, 16),
9050 GEN_VXFORM(vsubuhm
, 0, 17),
9051 GEN_VXFORM(vsubuwm
, 0, 18),
9052 GEN_VXFORM(vmaxub
, 1, 0),
9053 GEN_VXFORM(vmaxuh
, 1, 1),
9054 GEN_VXFORM(vmaxuw
, 1, 2),
9055 GEN_VXFORM(vmaxsb
, 1, 4),
9056 GEN_VXFORM(vmaxsh
, 1, 5),
9057 GEN_VXFORM(vmaxsw
, 1, 6),
9058 GEN_VXFORM(vminub
, 1, 8),
9059 GEN_VXFORM(vminuh
, 1, 9),
9060 GEN_VXFORM(vminuw
, 1, 10),
9061 GEN_VXFORM(vminsb
, 1, 12),
9062 GEN_VXFORM(vminsh
, 1, 13),
9063 GEN_VXFORM(vminsw
, 1, 14),
9064 GEN_VXFORM(vavgub
, 1, 16),
9065 GEN_VXFORM(vavguh
, 1, 17),
9066 GEN_VXFORM(vavguw
, 1, 18),
9067 GEN_VXFORM(vavgsb
, 1, 20),
9068 GEN_VXFORM(vavgsh
, 1, 21),
9069 GEN_VXFORM(vavgsw
, 1, 22),
9070 GEN_VXFORM(vmrghb
, 6, 0),
9071 GEN_VXFORM(vmrghh
, 6, 1),
9072 GEN_VXFORM(vmrghw
, 6, 2),
9073 GEN_VXFORM(vmrglb
, 6, 4),
9074 GEN_VXFORM(vmrglh
, 6, 5),
9075 GEN_VXFORM(vmrglw
, 6, 6),
9076 GEN_VXFORM(vmuloub
, 4, 0),
9077 GEN_VXFORM(vmulouh
, 4, 1),
9078 GEN_VXFORM(vmulosb
, 4, 4),
9079 GEN_VXFORM(vmulosh
, 4, 5),
9080 GEN_VXFORM(vmuleub
, 4, 8),
9081 GEN_VXFORM(vmuleuh
, 4, 9),
9082 GEN_VXFORM(vmulesb
, 4, 12),
9083 GEN_VXFORM(vmulesh
, 4, 13),
9084 GEN_VXFORM(vslb
, 2, 4),
9085 GEN_VXFORM(vslh
, 2, 5),
9086 GEN_VXFORM(vslw
, 2, 6),
9087 GEN_VXFORM(vsrb
, 2, 8),
9088 GEN_VXFORM(vsrh
, 2, 9),
9089 GEN_VXFORM(vsrw
, 2, 10),
9090 GEN_VXFORM(vsrab
, 2, 12),
9091 GEN_VXFORM(vsrah
, 2, 13),
9092 GEN_VXFORM(vsraw
, 2, 14),
9093 GEN_VXFORM(vslo
, 6, 16),
9094 GEN_VXFORM(vsro
, 6, 17),
9095 GEN_VXFORM(vaddcuw
, 0, 6),
9096 GEN_VXFORM(vsubcuw
, 0, 22),
9097 GEN_VXFORM(vaddubs
, 0, 8),
9098 GEN_VXFORM(vadduhs
, 0, 9),
9099 GEN_VXFORM(vadduws
, 0, 10),
9100 GEN_VXFORM(vaddsbs
, 0, 12),
9101 GEN_VXFORM(vaddshs
, 0, 13),
9102 GEN_VXFORM(vaddsws
, 0, 14),
9103 GEN_VXFORM(vsububs
, 0, 24),
9104 GEN_VXFORM(vsubuhs
, 0, 25),
9105 GEN_VXFORM(vsubuws
, 0, 26),
9106 GEN_VXFORM(vsubsbs
, 0, 28),
9107 GEN_VXFORM(vsubshs
, 0, 29),
9108 GEN_VXFORM(vsubsws
, 0, 30),
9109 GEN_VXFORM(vrlb
, 2, 0),
9110 GEN_VXFORM(vrlh
, 2, 1),
9111 GEN_VXFORM(vrlw
, 2, 2),
9112 GEN_VXFORM(vsl
, 2, 7),
9113 GEN_VXFORM(vsr
, 2, 11),
9114 GEN_VXFORM(vpkuhum
, 7, 0),
9115 GEN_VXFORM(vpkuwum
, 7, 1),
9116 GEN_VXFORM(vpkuhus
, 7, 2),
9117 GEN_VXFORM(vpkuwus
, 7, 3),
9118 GEN_VXFORM(vpkshus
, 7, 4),
9119 GEN_VXFORM(vpkswus
, 7, 5),
9120 GEN_VXFORM(vpkshss
, 7, 6),
9121 GEN_VXFORM(vpkswss
, 7, 7),
9122 GEN_VXFORM(vpkpx
, 7, 12),
9123 GEN_VXFORM(vsum4ubs
, 4, 24),
9124 GEN_VXFORM(vsum4sbs
, 4, 28),
9125 GEN_VXFORM(vsum4shs
, 4, 25),
9126 GEN_VXFORM(vsum2sws
, 4, 26),
9127 GEN_VXFORM(vsumsws
, 4, 30),
9128 GEN_VXFORM(vaddfp
, 5, 0),
9129 GEN_VXFORM(vsubfp
, 5, 1),
9130 GEN_VXFORM(vmaxfp
, 5, 16),
9131 GEN_VXFORM(vminfp
, 5, 17),
9135 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9136 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9137 #define GEN_VXRFORM(name, opc2, opc3) \
9138 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9139 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9140 GEN_VXRFORM(vcmpequb
, 3, 0)
9141 GEN_VXRFORM(vcmpequh
, 3, 1)
9142 GEN_VXRFORM(vcmpequw
, 3, 2)
9143 GEN_VXRFORM(vcmpgtsb
, 3, 12)
9144 GEN_VXRFORM(vcmpgtsh
, 3, 13)
9145 GEN_VXRFORM(vcmpgtsw
, 3, 14)
9146 GEN_VXRFORM(vcmpgtub
, 3, 8)
9147 GEN_VXRFORM(vcmpgtuh
, 3, 9)
9148 GEN_VXRFORM(vcmpgtuw
, 3, 10)
9149 GEN_VXRFORM(vcmpeqfp
, 3, 3)
9150 GEN_VXRFORM(vcmpgefp
, 3, 7)
9151 GEN_VXRFORM(vcmpgtfp
, 3, 11)
9152 GEN_VXRFORM(vcmpbfp
, 3, 15)
9154 #undef GEN_VXFORM_SIMM
9155 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9156 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9157 GEN_VXFORM_SIMM(vspltisb
, 6, 12),
9158 GEN_VXFORM_SIMM(vspltish
, 6, 13),
9159 GEN_VXFORM_SIMM(vspltisw
, 6, 14),
9161 #undef GEN_VXFORM_NOA
9162 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9163 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9164 GEN_VXFORM_NOA(vupkhsb
, 7, 8),
9165 GEN_VXFORM_NOA(vupkhsh
, 7, 9),
9166 GEN_VXFORM_NOA(vupklsb
, 7, 10),
9167 GEN_VXFORM_NOA(vupklsh
, 7, 11),
9168 GEN_VXFORM_NOA(vupkhpx
, 7, 13),
9169 GEN_VXFORM_NOA(vupklpx
, 7, 15),
9170 GEN_VXFORM_NOA(vrefp
, 5, 4),
9171 GEN_VXFORM_NOA(vrsqrtefp
, 5, 5),
9172 GEN_VXFORM_NOA(vexptefp
, 5, 6),
9173 GEN_VXFORM_NOA(vlogefp
, 5, 7),
9174 GEN_VXFORM_NOA(vrfim
, 5, 8),
9175 GEN_VXFORM_NOA(vrfin
, 5, 9),
9176 GEN_VXFORM_NOA(vrfip
, 5, 10),
9177 GEN_VXFORM_NOA(vrfiz
, 5, 11),
9179 #undef GEN_VXFORM_UIMM
9180 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9181 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9182 GEN_VXFORM_UIMM(vspltb
, 6, 8),
9183 GEN_VXFORM_UIMM(vsplth
, 6, 9),
9184 GEN_VXFORM_UIMM(vspltw
, 6, 10),
9185 GEN_VXFORM_UIMM(vcfux
, 5, 12),
9186 GEN_VXFORM_UIMM(vcfsx
, 5, 13),
9187 GEN_VXFORM_UIMM(vctuxs
, 5, 14),
9188 GEN_VXFORM_UIMM(vctsxs
, 5, 15),
9190 #undef GEN_VAFORM_PAIRED
9191 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9192 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9193 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16),
9194 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18),
9195 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19),
9196 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20),
9197 GEN_VAFORM_PAIRED(vsel
, vperm
, 21),
9198 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23),
9201 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9202 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9203 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9204 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9205 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9206 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9207 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
9208 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
9209 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
9210 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE
),
9211 GEN_SPE(evmra
, speundef
, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE
),
9212 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
),
9213 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9214 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9215 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9216 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE
),
9217 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE
),
9218 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE
),
9219 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
),
9220 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9221 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9222 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9223 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9224 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9225 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE
),
9226 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE
),
9227 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9228 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9229 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE
),
9230 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE
),
9231 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE
),
9233 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
9234 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
),
9235 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9236 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
9237 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
9238 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9239 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9240 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9241 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9242 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9243 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9244 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9245 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
9246 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9248 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
9249 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
),
9250 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9251 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
9252 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
9253 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE
),
9254 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9255 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9256 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9257 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9258 GEN_SPE(efsctuiz
, speundef
, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9259 GEN_SPE(efsctsiz
, speundef
, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9260 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
9261 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9263 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
),
9264 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9265 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE
),
9266 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
9267 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
),
9268 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9269 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
),
9270 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE
),
9271 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9272 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9273 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9274 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9275 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
9276 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
9277 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
),
9278 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
9280 #undef GEN_SPEOP_LDST
9281 #define GEN_SPEOP_LDST(name, opc2, sh) \
9282 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9283 GEN_SPEOP_LDST(evldd
, 0x00, 3),
9284 GEN_SPEOP_LDST(evldw
, 0x01, 3),
9285 GEN_SPEOP_LDST(evldh
, 0x02, 3),
9286 GEN_SPEOP_LDST(evlhhesplat
, 0x04, 1),
9287 GEN_SPEOP_LDST(evlhhousplat
, 0x06, 1),
9288 GEN_SPEOP_LDST(evlhhossplat
, 0x07, 1),
9289 GEN_SPEOP_LDST(evlwhe
, 0x08, 2),
9290 GEN_SPEOP_LDST(evlwhou
, 0x0A, 2),
9291 GEN_SPEOP_LDST(evlwhos
, 0x0B, 2),
9292 GEN_SPEOP_LDST(evlwwsplat
, 0x0C, 2),
9293 GEN_SPEOP_LDST(evlwhsplat
, 0x0E, 2),
9295 GEN_SPEOP_LDST(evstdd
, 0x10, 3),
9296 GEN_SPEOP_LDST(evstdw
, 0x11, 3),
9297 GEN_SPEOP_LDST(evstdh
, 0x12, 3),
9298 GEN_SPEOP_LDST(evstwhe
, 0x18, 2),
9299 GEN_SPEOP_LDST(evstwho
, 0x1A, 2),
9300 GEN_SPEOP_LDST(evstwwe
, 0x1C, 2),
9301 GEN_SPEOP_LDST(evstwwo
, 0x1E, 2),
9304 #include "helper_regs.h"
9305 #include "translate_init.c"
9307 /*****************************************************************************/
9308 /* Misc PowerPC helpers */
9309 void cpu_dump_state (CPUPPCState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
9317 cpu_synchronize_state(env
);
9319 cpu_fprintf(f
, "NIP " TARGET_FMT_lx
" LR " TARGET_FMT_lx
" CTR "
9320 TARGET_FMT_lx
" XER " TARGET_FMT_lx
"\n",
9321 env
->nip
, env
->lr
, env
->ctr
, cpu_read_xer(env
));
9322 cpu_fprintf(f
, "MSR " TARGET_FMT_lx
" HID0 " TARGET_FMT_lx
" HF "
9323 TARGET_FMT_lx
" idx %d\n", env
->msr
, env
->spr
[SPR_HID0
],
9324 env
->hflags
, env
->mmu_idx
);
9325 #if !defined(NO_TIMER_DUMP)
9326 cpu_fprintf(f
, "TB %08" PRIu32
" %08" PRIu64
9327 #if !defined(CONFIG_USER_ONLY)
9331 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
9332 #if !defined(CONFIG_USER_ONLY)
9333 , cpu_ppc_load_decr(env
)
9337 for (i
= 0; i
< 32; i
++) {
9338 if ((i
& (RGPL
- 1)) == 0)
9339 cpu_fprintf(f
, "GPR%02d", i
);
9340 cpu_fprintf(f
, " %016" PRIx64
, ppc_dump_gpr(env
, i
));
9341 if ((i
& (RGPL
- 1)) == (RGPL
- 1))
9342 cpu_fprintf(f
, "\n");
9344 cpu_fprintf(f
, "CR ");
9345 for (i
= 0; i
< 8; i
++)
9346 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
9347 cpu_fprintf(f
, " [");
9348 for (i
= 0; i
< 8; i
++) {
9350 if (env
->crf
[i
] & 0x08)
9352 else if (env
->crf
[i
] & 0x04)
9354 else if (env
->crf
[i
] & 0x02)
9356 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
9358 cpu_fprintf(f
, " ] RES " TARGET_FMT_lx
"\n",
9360 for (i
= 0; i
< 32; i
++) {
9361 if ((i
& (RFPL
- 1)) == 0)
9362 cpu_fprintf(f
, "FPR%02d", i
);
9363 cpu_fprintf(f
, " %016" PRIx64
, *((uint64_t *)&env
->fpr
[i
]));
9364 if ((i
& (RFPL
- 1)) == (RFPL
- 1))
9365 cpu_fprintf(f
, "\n");
9367 cpu_fprintf(f
, "FPSCR " TARGET_FMT_lx
"\n", env
->fpscr
);
9368 #if !defined(CONFIG_USER_ONLY)
9369 cpu_fprintf(f
, " SRR0 " TARGET_FMT_lx
" SRR1 " TARGET_FMT_lx
9370 " PVR " TARGET_FMT_lx
" VRSAVE " TARGET_FMT_lx
"\n",
9371 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
9372 env
->spr
[SPR_PVR
], env
->spr
[SPR_VRSAVE
]);
9374 cpu_fprintf(f
, "SPRG0 " TARGET_FMT_lx
" SPRG1 " TARGET_FMT_lx
9375 " SPRG2 " TARGET_FMT_lx
" SPRG3 " TARGET_FMT_lx
"\n",
9376 env
->spr
[SPR_SPRG0
], env
->spr
[SPR_SPRG1
],
9377 env
->spr
[SPR_SPRG2
], env
->spr
[SPR_SPRG3
]);
9379 cpu_fprintf(f
, "SPRG4 " TARGET_FMT_lx
" SPRG5 " TARGET_FMT_lx
9380 " SPRG6 " TARGET_FMT_lx
" SPRG7 " TARGET_FMT_lx
"\n",
9381 env
->spr
[SPR_SPRG4
], env
->spr
[SPR_SPRG5
],
9382 env
->spr
[SPR_SPRG6
], env
->spr
[SPR_SPRG7
]);
9384 if (env
->excp_model
== POWERPC_EXCP_BOOKE
) {
9385 cpu_fprintf(f
, "CSRR0 " TARGET_FMT_lx
" CSRR1 " TARGET_FMT_lx
9386 " MCSRR0 " TARGET_FMT_lx
" MCSRR1 " TARGET_FMT_lx
"\n",
9387 env
->spr
[SPR_BOOKE_CSRR0
], env
->spr
[SPR_BOOKE_CSRR1
],
9388 env
->spr
[SPR_BOOKE_MCSRR0
], env
->spr
[SPR_BOOKE_MCSRR1
]);
9390 cpu_fprintf(f
, " TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
9391 " ESR " TARGET_FMT_lx
" DEAR " TARGET_FMT_lx
"\n",
9392 env
->spr
[SPR_BOOKE_TCR
], env
->spr
[SPR_BOOKE_TSR
],
9393 env
->spr
[SPR_BOOKE_ESR
], env
->spr
[SPR_BOOKE_DEAR
]);
9395 cpu_fprintf(f
, " PIR " TARGET_FMT_lx
" DECAR " TARGET_FMT_lx
9396 " IVPR " TARGET_FMT_lx
" EPCR " TARGET_FMT_lx
"\n",
9397 env
->spr
[SPR_BOOKE_PIR
], env
->spr
[SPR_BOOKE_DECAR
],
9398 env
->spr
[SPR_BOOKE_IVPR
], env
->spr
[SPR_BOOKE_EPCR
]);
9400 cpu_fprintf(f
, " MCSR " TARGET_FMT_lx
" SPRG8 " TARGET_FMT_lx
9401 " EPR " TARGET_FMT_lx
"\n",
9402 env
->spr
[SPR_BOOKE_MCSR
], env
->spr
[SPR_BOOKE_SPRG8
],
9403 env
->spr
[SPR_BOOKE_EPR
]);
9406 cpu_fprintf(f
, " MCAR " TARGET_FMT_lx
" PID1 " TARGET_FMT_lx
9407 " PID2 " TARGET_FMT_lx
" SVR " TARGET_FMT_lx
"\n",
9408 env
->spr
[SPR_Exxx_MCAR
], env
->spr
[SPR_BOOKE_PID1
],
9409 env
->spr
[SPR_BOOKE_PID2
], env
->spr
[SPR_E500_SVR
]);
9412 * IVORs are left out as they are large and do not change often --
9413 * they can be read with "p $ivor0", "p $ivor1", etc.
9417 #if defined(TARGET_PPC64)
9418 if (env
->flags
& POWERPC_FLAG_CFAR
) {
9419 cpu_fprintf(f
, " CFAR " TARGET_FMT_lx
"\n", env
->cfar
);
9423 switch (env
->mmu_model
) {
9424 case POWERPC_MMU_32B
:
9425 case POWERPC_MMU_601
:
9426 case POWERPC_MMU_SOFT_6xx
:
9427 case POWERPC_MMU_SOFT_74xx
:
9428 #if defined(TARGET_PPC64)
9429 case POWERPC_MMU_620
:
9430 case POWERPC_MMU_64B
:
9432 cpu_fprintf(f
, " SDR1 " TARGET_FMT_lx
"\n", env
->spr
[SPR_SDR1
]);
9434 case POWERPC_MMU_BOOKE206
:
9435 cpu_fprintf(f
, " MAS0 " TARGET_FMT_lx
" MAS1 " TARGET_FMT_lx
9436 " MAS2 " TARGET_FMT_lx
" MAS3 " TARGET_FMT_lx
"\n",
9437 env
->spr
[SPR_BOOKE_MAS0
], env
->spr
[SPR_BOOKE_MAS1
],
9438 env
->spr
[SPR_BOOKE_MAS2
], env
->spr
[SPR_BOOKE_MAS3
]);
9440 cpu_fprintf(f
, " MAS4 " TARGET_FMT_lx
" MAS6 " TARGET_FMT_lx
9441 " MAS7 " TARGET_FMT_lx
" PID " TARGET_FMT_lx
"\n",
9442 env
->spr
[SPR_BOOKE_MAS4
], env
->spr
[SPR_BOOKE_MAS6
],
9443 env
->spr
[SPR_BOOKE_MAS7
], env
->spr
[SPR_BOOKE_PID
]);
9445 cpu_fprintf(f
, "MMUCFG " TARGET_FMT_lx
" TLB0CFG " TARGET_FMT_lx
9446 " TLB1CFG " TARGET_FMT_lx
"\n",
9447 env
->spr
[SPR_MMUCFG
], env
->spr
[SPR_BOOKE_TLB0CFG
],
9448 env
->spr
[SPR_BOOKE_TLB1CFG
]);
9459 void cpu_dump_statistics (CPUPPCState
*env
, FILE*f
, fprintf_function cpu_fprintf
,
9462 #if defined(DO_PPC_STATISTICS)
9463 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
9467 for (op1
= 0; op1
< 64; op1
++) {
9469 if (is_indirect_opcode(handler
)) {
9470 t2
= ind_table(handler
);
9471 for (op2
= 0; op2
< 32; op2
++) {
9473 if (is_indirect_opcode(handler
)) {
9474 t3
= ind_table(handler
);
9475 for (op3
= 0; op3
< 32; op3
++) {
9477 if (handler
->count
== 0)
9479 cpu_fprintf(f
, "%02x %02x %02x (%02x %04d) %16s: "
9480 "%016" PRIx64
" %" PRId64
"\n",
9481 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
9483 handler
->count
, handler
->count
);
9486 if (handler
->count
== 0)
9488 cpu_fprintf(f
, "%02x %02x (%02x %04d) %16s: "
9489 "%016" PRIx64
" %" PRId64
"\n",
9490 op1
, op2
, op1
, op2
, handler
->oname
,
9491 handler
->count
, handler
->count
);
9495 if (handler
->count
== 0)
9497 cpu_fprintf(f
, "%02x (%02x ) %16s: %016" PRIx64
9499 op1
, op1
, handler
->oname
,
9500 handler
->count
, handler
->count
);
9506 /*****************************************************************************/
9507 static inline void gen_intermediate_code_internal(CPUPPCState
*env
,
9508 TranslationBlock
*tb
,
9511 DisasContext ctx
, *ctxp
= &ctx
;
9512 opc_handler_t
**table
, *handler
;
9513 target_ulong pc_start
;
9514 uint16_t *gen_opc_end
;
9521 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
9524 ctx
.exception
= POWERPC_EXCP_NONE
;
9525 ctx
.spr_cb
= env
->spr_cb
;
9526 ctx
.mem_idx
= env
->mmu_idx
;
9527 ctx
.access_type
= -1;
9528 ctx
.le_mode
= env
->hflags
& (1 << MSR_LE
) ? 1 : 0;
9529 #if defined(TARGET_PPC64)
9530 ctx
.sf_mode
= msr_is_64bit(env
, env
->msr
);
9531 ctx
.has_cfar
= !!(env
->flags
& POWERPC_FLAG_CFAR
);
9533 ctx
.fpu_enabled
= msr_fp
;
9534 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
)
9535 ctx
.spe_enabled
= msr_spe
;
9537 ctx
.spe_enabled
= 0;
9538 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
)
9539 ctx
.altivec_enabled
= msr_vr
;
9541 ctx
.altivec_enabled
= 0;
9542 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
)
9543 ctx
.singlestep_enabled
= CPU_SINGLE_STEP
;
9545 ctx
.singlestep_enabled
= 0;
9546 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
)
9547 ctx
.singlestep_enabled
|= CPU_BRANCH_STEP
;
9548 if (unlikely(env
->singlestep_enabled
))
9549 ctx
.singlestep_enabled
|= GDBSTUB_SINGLE_STEP
;
9550 #if defined (DO_SINGLE_STEP) && 0
9551 /* Single step trace mode */
9555 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
9557 max_insns
= CF_COUNT_MASK
;
9560 /* Set env in case of segfault during code fetch */
9561 while (ctx
.exception
== POWERPC_EXCP_NONE
9562 && tcg_ctx
.gen_opc_ptr
< gen_opc_end
) {
9563 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
9564 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
9565 if (bp
->pc
== ctx
.nip
) {
9566 gen_debug_exception(ctxp
);
9571 if (unlikely(search_pc
)) {
9572 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
9576 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
9578 tcg_ctx
.gen_opc_pc
[lj
] = ctx
.nip
;
9579 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
9580 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
9582 LOG_DISAS("----------------\n");
9583 LOG_DISAS("nip=" TARGET_FMT_lx
" super=%d ir=%d\n",
9584 ctx
.nip
, ctx
.mem_idx
, (int)msr_ir
);
9585 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
9587 if (unlikely(ctx
.le_mode
)) {
9588 ctx
.opcode
= bswap32(cpu_ldl_code(env
, ctx
.nip
));
9590 ctx
.opcode
= cpu_ldl_code(env
, ctx
.nip
);
9592 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9593 ctx
.opcode
, opc1(ctx
.opcode
), opc2(ctx
.opcode
),
9594 opc3(ctx
.opcode
), ctx
.le_mode
? "little" : "big");
9595 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
9596 tcg_gen_debug_insn_start(ctx
.nip
);
9599 table
= env
->opcodes
;
9601 handler
= table
[opc1(ctx
.opcode
)];
9602 if (is_indirect_opcode(handler
)) {
9603 table
= ind_table(handler
);
9604 handler
= table
[opc2(ctx
.opcode
)];
9605 if (is_indirect_opcode(handler
)) {
9606 table
= ind_table(handler
);
9607 handler
= table
[opc3(ctx
.opcode
)];
9610 /* Is opcode *REALLY* valid ? */
9611 if (unlikely(handler
->handler
== &gen_invalid
)) {
9612 if (qemu_log_enabled()) {
9613 qemu_log("invalid/unsupported opcode: "
9614 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx
" %d\n",
9615 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
9616 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
9621 if (unlikely(handler
->type
& (PPC_SPE
| PPC_SPE_SINGLE
| PPC_SPE_DOUBLE
) && Rc(ctx
.opcode
))) {
9622 inval
= handler
->inval2
;
9624 inval
= handler
->inval1
;
9627 if (unlikely((ctx
.opcode
& inval
) != 0)) {
9628 if (qemu_log_enabled()) {
9629 qemu_log("invalid bits: %08x for opcode: "
9630 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx
"\n",
9631 ctx
.opcode
& inval
, opc1(ctx
.opcode
),
9632 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
9633 ctx
.opcode
, ctx
.nip
- 4);
9635 gen_inval_exception(ctxp
, POWERPC_EXCP_INVAL_INVAL
);
9639 (*(handler
->handler
))(&ctx
);
9640 #if defined(DO_PPC_STATISTICS)
9643 /* Check trace mode exceptions */
9644 if (unlikely(ctx
.singlestep_enabled
& CPU_SINGLE_STEP
&&
9645 (ctx
.nip
<= 0x100 || ctx
.nip
> 0xF00) &&
9646 ctx
.exception
!= POWERPC_SYSCALL
&&
9647 ctx
.exception
!= POWERPC_EXCP_TRAP
&&
9648 ctx
.exception
!= POWERPC_EXCP_BRANCH
)) {
9649 gen_exception(ctxp
, POWERPC_EXCP_TRACE
);
9650 } else if (unlikely(((ctx
.nip
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
9651 (env
->singlestep_enabled
) ||
9653 num_insns
>= max_insns
)) {
9654 /* if we reach a page boundary or are single stepping, stop
9660 if (tb
->cflags
& CF_LAST_IO
)
9662 if (ctx
.exception
== POWERPC_EXCP_NONE
) {
9663 gen_goto_tb(&ctx
, 0, ctx
.nip
);
9664 } else if (ctx
.exception
!= POWERPC_EXCP_BRANCH
) {
9665 if (unlikely(env
->singlestep_enabled
)) {
9666 gen_debug_exception(ctxp
);
9668 /* Generate the return instruction */
9671 gen_icount_end(tb
, num_insns
);
9672 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
9673 if (unlikely(search_pc
)) {
9674 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
9677 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
9679 tb
->size
= ctx
.nip
- pc_start
;
9680 tb
->icount
= num_insns
;
9682 #if defined(DEBUG_DISAS)
9683 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
9685 flags
= env
->bfd_mach
;
9686 flags
|= ctx
.le_mode
<< 16;
9687 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
9688 log_target_disas(env
, pc_start
, ctx
.nip
- pc_start
, flags
);
9694 void gen_intermediate_code (CPUPPCState
*env
, struct TranslationBlock
*tb
)
9696 gen_intermediate_code_internal(env
, tb
, 0);
9699 void gen_intermediate_code_pc (CPUPPCState
*env
, struct TranslationBlock
*tb
)
9701 gen_intermediate_code_internal(env
, tb
, 1);
9704 void restore_state_to_opc(CPUPPCState
*env
, TranslationBlock
*tb
, int pc_pos
)
9706 env
->nip
= tcg_ctx
.gen_opc_pc
[pc_pos
];