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Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.6-20160324' into staging
[mirror_qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "tcg-op.h"
25 #include "qemu/host-utils.h"
26 #include "exec/cpu_ldst.h"
27
28 #include "exec/helper-proto.h"
29 #include "exec/helper-gen.h"
30
31 #include "trace-tcg.h"
32 #include "exec/log.h"
33
34
35 #define CPU_SINGLE_STEP 0x1
36 #define CPU_BRANCH_STEP 0x2
37 #define GDBSTUB_SINGLE_STEP 0x4
38
39 /* Include definitions for instructions classes and implementations flags */
40 //#define PPC_DEBUG_DISAS
41 //#define DO_PPC_STATISTICS
42
43 #ifdef PPC_DEBUG_DISAS
44 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
45 #else
46 # define LOG_DISAS(...) do { } while (0)
47 #endif
48 /*****************************************************************************/
49 /* Code translation helpers */
50
51 /* global register indexes */
52 static TCGv_env cpu_env;
53 static char cpu_reg_names[10*3 + 22*4 /* GPR */
54 + 10*4 + 22*5 /* SPE GPRh */
55 + 10*4 + 22*5 /* FPR */
56 + 2*(10*6 + 22*7) /* AVRh, AVRl */
57 + 10*5 + 22*6 /* VSR */
58 + 8*5 /* CRF */];
59 static TCGv cpu_gpr[32];
60 static TCGv cpu_gprh[32];
61 static TCGv_i64 cpu_fpr[32];
62 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
63 static TCGv_i64 cpu_vsr[32];
64 static TCGv_i32 cpu_crf[8];
65 static TCGv cpu_nip;
66 static TCGv cpu_msr;
67 static TCGv cpu_ctr;
68 static TCGv cpu_lr;
69 #if defined(TARGET_PPC64)
70 static TCGv cpu_cfar;
71 #endif
72 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
73 static TCGv cpu_reserve;
74 static TCGv cpu_fpscr;
75 static TCGv_i32 cpu_access_type;
76
77 #include "exec/gen-icount.h"
78
79 void ppc_translate_init(void)
80 {
81 int i;
82 char* p;
83 size_t cpu_reg_names_size;
84 static int done_init = 0;
85
86 if (done_init)
87 return;
88
89 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
90
91 p = cpu_reg_names;
92 cpu_reg_names_size = sizeof(cpu_reg_names);
93
94 for (i = 0; i < 8; i++) {
95 snprintf(p, cpu_reg_names_size, "crf%d", i);
96 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
97 offsetof(CPUPPCState, crf[i]), p);
98 p += 5;
99 cpu_reg_names_size -= 5;
100 }
101
102 for (i = 0; i < 32; i++) {
103 snprintf(p, cpu_reg_names_size, "r%d", i);
104 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
105 offsetof(CPUPPCState, gpr[i]), p);
106 p += (i < 10) ? 3 : 4;
107 cpu_reg_names_size -= (i < 10) ? 3 : 4;
108 snprintf(p, cpu_reg_names_size, "r%dH", i);
109 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
110 offsetof(CPUPPCState, gprh[i]), p);
111 p += (i < 10) ? 4 : 5;
112 cpu_reg_names_size -= (i < 10) ? 4 : 5;
113
114 snprintf(p, cpu_reg_names_size, "fp%d", i);
115 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
116 offsetof(CPUPPCState, fpr[i]), p);
117 p += (i < 10) ? 4 : 5;
118 cpu_reg_names_size -= (i < 10) ? 4 : 5;
119
120 snprintf(p, cpu_reg_names_size, "avr%dH", i);
121 #ifdef HOST_WORDS_BIGENDIAN
122 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
123 offsetof(CPUPPCState, avr[i].u64[0]), p);
124 #else
125 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
126 offsetof(CPUPPCState, avr[i].u64[1]), p);
127 #endif
128 p += (i < 10) ? 6 : 7;
129 cpu_reg_names_size -= (i < 10) ? 6 : 7;
130
131 snprintf(p, cpu_reg_names_size, "avr%dL", i);
132 #ifdef HOST_WORDS_BIGENDIAN
133 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
134 offsetof(CPUPPCState, avr[i].u64[1]), p);
135 #else
136 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
137 offsetof(CPUPPCState, avr[i].u64[0]), p);
138 #endif
139 p += (i < 10) ? 6 : 7;
140 cpu_reg_names_size -= (i < 10) ? 6 : 7;
141 snprintf(p, cpu_reg_names_size, "vsr%d", i);
142 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
143 offsetof(CPUPPCState, vsr[i]), p);
144 p += (i < 10) ? 5 : 6;
145 cpu_reg_names_size -= (i < 10) ? 5 : 6;
146 }
147
148 cpu_nip = tcg_global_mem_new(cpu_env,
149 offsetof(CPUPPCState, nip), "nip");
150
151 cpu_msr = tcg_global_mem_new(cpu_env,
152 offsetof(CPUPPCState, msr), "msr");
153
154 cpu_ctr = tcg_global_mem_new(cpu_env,
155 offsetof(CPUPPCState, ctr), "ctr");
156
157 cpu_lr = tcg_global_mem_new(cpu_env,
158 offsetof(CPUPPCState, lr), "lr");
159
160 #if defined(TARGET_PPC64)
161 cpu_cfar = tcg_global_mem_new(cpu_env,
162 offsetof(CPUPPCState, cfar), "cfar");
163 #endif
164
165 cpu_xer = tcg_global_mem_new(cpu_env,
166 offsetof(CPUPPCState, xer), "xer");
167 cpu_so = tcg_global_mem_new(cpu_env,
168 offsetof(CPUPPCState, so), "SO");
169 cpu_ov = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, ov), "OV");
171 cpu_ca = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, ca), "CA");
173
174 cpu_reserve = tcg_global_mem_new(cpu_env,
175 offsetof(CPUPPCState, reserve_addr),
176 "reserve_addr");
177
178 cpu_fpscr = tcg_global_mem_new(cpu_env,
179 offsetof(CPUPPCState, fpscr), "fpscr");
180
181 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
182 offsetof(CPUPPCState, access_type), "access_type");
183
184 done_init = 1;
185 }
186
187 /* internal defines */
188 struct DisasContext {
189 struct TranslationBlock *tb;
190 target_ulong nip;
191 uint32_t opcode;
192 uint32_t exception;
193 /* Routine used to access memory */
194 bool pr, hv;
195 int mem_idx;
196 int access_type;
197 /* Translation flags */
198 int le_mode;
199 TCGMemOp default_tcg_memop_mask;
200 #if defined(TARGET_PPC64)
201 int sf_mode;
202 int has_cfar;
203 #endif
204 int fpu_enabled;
205 int altivec_enabled;
206 int vsx_enabled;
207 int spe_enabled;
208 int tm_enabled;
209 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
210 int singlestep_enabled;
211 uint64_t insns_flags;
212 uint64_t insns_flags2;
213 };
214
215 /* Return true iff byteswap is needed in a scalar memop */
216 static inline bool need_byteswap(const DisasContext *ctx)
217 {
218 #if defined(TARGET_WORDS_BIGENDIAN)
219 return ctx->le_mode;
220 #else
221 return !ctx->le_mode;
222 #endif
223 }
224
225 /* True when active word size < size of target_long. */
226 #ifdef TARGET_PPC64
227 # define NARROW_MODE(C) (!(C)->sf_mode)
228 #else
229 # define NARROW_MODE(C) 0
230 #endif
231
232 struct opc_handler_t {
233 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
234 uint32_t inval1;
235 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
236 uint32_t inval2;
237 /* instruction type */
238 uint64_t type;
239 /* extended instruction type */
240 uint64_t type2;
241 /* handler */
242 void (*handler)(DisasContext *ctx);
243 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
244 const char *oname;
245 #endif
246 #if defined(DO_PPC_STATISTICS)
247 uint64_t count;
248 #endif
249 };
250
251 static inline void gen_reset_fpstatus(void)
252 {
253 gen_helper_reset_fpstatus(cpu_env);
254 }
255
256 static inline void gen_compute_fprf(TCGv_i64 arg)
257 {
258 gen_helper_compute_fprf(cpu_env, arg);
259 gen_helper_float_check_status(cpu_env);
260 }
261
262 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
263 {
264 if (ctx->access_type != access_type) {
265 tcg_gen_movi_i32(cpu_access_type, access_type);
266 ctx->access_type = access_type;
267 }
268 }
269
270 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
271 {
272 if (NARROW_MODE(ctx)) {
273 nip = (uint32_t)nip;
274 }
275 tcg_gen_movi_tl(cpu_nip, nip);
276 }
277
278 void gen_update_current_nip(void *opaque)
279 {
280 DisasContext *ctx = opaque;
281
282 tcg_gen_movi_tl(cpu_nip, ctx->nip);
283 }
284
285 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
286 {
287 TCGv_i32 t0, t1;
288 if (ctx->exception == POWERPC_EXCP_NONE) {
289 gen_update_nip(ctx, ctx->nip);
290 }
291 t0 = tcg_const_i32(excp);
292 t1 = tcg_const_i32(error);
293 gen_helper_raise_exception_err(cpu_env, t0, t1);
294 tcg_temp_free_i32(t0);
295 tcg_temp_free_i32(t1);
296 ctx->exception = (excp);
297 }
298
299 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
300 {
301 TCGv_i32 t0;
302 if (ctx->exception == POWERPC_EXCP_NONE) {
303 gen_update_nip(ctx, ctx->nip);
304 }
305 t0 = tcg_const_i32(excp);
306 gen_helper_raise_exception(cpu_env, t0);
307 tcg_temp_free_i32(t0);
308 ctx->exception = (excp);
309 }
310
311 static inline void gen_debug_exception(DisasContext *ctx)
312 {
313 TCGv_i32 t0;
314
315 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
316 (ctx->exception != POWERPC_EXCP_SYNC)) {
317 gen_update_nip(ctx, ctx->nip);
318 }
319 t0 = tcg_const_i32(EXCP_DEBUG);
320 gen_helper_raise_exception(cpu_env, t0);
321 tcg_temp_free_i32(t0);
322 }
323
324 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
325 {
326 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
327 }
328
329 /* Stop translation */
330 static inline void gen_stop_exception(DisasContext *ctx)
331 {
332 gen_update_nip(ctx, ctx->nip);
333 ctx->exception = POWERPC_EXCP_STOP;
334 }
335
336 #ifndef CONFIG_USER_ONLY
337 /* No need to update nip here, as execution flow will change */
338 static inline void gen_sync_exception(DisasContext *ctx)
339 {
340 ctx->exception = POWERPC_EXCP_SYNC;
341 }
342 #endif
343
344 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
345 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
346
347 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
348 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
349
350 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
351 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
352
353 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
354 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
355
356 typedef struct opcode_t {
357 unsigned char opc1, opc2, opc3;
358 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
359 unsigned char pad[5];
360 #else
361 unsigned char pad[1];
362 #endif
363 opc_handler_t handler;
364 const char *oname;
365 } opcode_t;
366
367 /*****************************************************************************/
368 /*** Instruction decoding ***/
369 #define EXTRACT_HELPER(name, shift, nb) \
370 static inline uint32_t name(uint32_t opcode) \
371 { \
372 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
373 }
374
375 #define EXTRACT_SHELPER(name, shift, nb) \
376 static inline int32_t name(uint32_t opcode) \
377 { \
378 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
379 }
380
381 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
382 static inline uint32_t name(uint32_t opcode) \
383 { \
384 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
385 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
386 }
387 /* Opcode part 1 */
388 EXTRACT_HELPER(opc1, 26, 6);
389 /* Opcode part 2 */
390 EXTRACT_HELPER(opc2, 1, 5);
391 /* Opcode part 3 */
392 EXTRACT_HELPER(opc3, 6, 5);
393 /* Update Cr0 flags */
394 EXTRACT_HELPER(Rc, 0, 1);
395 /* Update Cr6 flags (Altivec) */
396 EXTRACT_HELPER(Rc21, 10, 1);
397 /* Destination */
398 EXTRACT_HELPER(rD, 21, 5);
399 /* Source */
400 EXTRACT_HELPER(rS, 21, 5);
401 /* First operand */
402 EXTRACT_HELPER(rA, 16, 5);
403 /* Second operand */
404 EXTRACT_HELPER(rB, 11, 5);
405 /* Third operand */
406 EXTRACT_HELPER(rC, 6, 5);
407 /*** Get CRn ***/
408 EXTRACT_HELPER(crfD, 23, 3);
409 EXTRACT_HELPER(crfS, 18, 3);
410 EXTRACT_HELPER(crbD, 21, 5);
411 EXTRACT_HELPER(crbA, 16, 5);
412 EXTRACT_HELPER(crbB, 11, 5);
413 /* SPR / TBL */
414 EXTRACT_HELPER(_SPR, 11, 10);
415 static inline uint32_t SPR(uint32_t opcode)
416 {
417 uint32_t sprn = _SPR(opcode);
418
419 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
420 }
421 /*** Get constants ***/
422 /* 16 bits signed immediate value */
423 EXTRACT_SHELPER(SIMM, 0, 16);
424 /* 16 bits unsigned immediate value */
425 EXTRACT_HELPER(UIMM, 0, 16);
426 /* 5 bits signed immediate value */
427 EXTRACT_HELPER(SIMM5, 16, 5);
428 /* 5 bits signed immediate value */
429 EXTRACT_HELPER(UIMM5, 16, 5);
430 /* Bit count */
431 EXTRACT_HELPER(NB, 11, 5);
432 /* Shift count */
433 EXTRACT_HELPER(SH, 11, 5);
434 /* Vector shift count */
435 EXTRACT_HELPER(VSH, 6, 4);
436 /* Mask start */
437 EXTRACT_HELPER(MB, 6, 5);
438 /* Mask end */
439 EXTRACT_HELPER(ME, 1, 5);
440 /* Trap operand */
441 EXTRACT_HELPER(TO, 21, 5);
442
443 EXTRACT_HELPER(CRM, 12, 8);
444
445 #ifndef CONFIG_USER_ONLY
446 EXTRACT_HELPER(SR, 16, 4);
447 #endif
448
449 /* mtfsf/mtfsfi */
450 EXTRACT_HELPER(FPBF, 23, 3);
451 EXTRACT_HELPER(FPIMM, 12, 4);
452 EXTRACT_HELPER(FPL, 25, 1);
453 EXTRACT_HELPER(FPFLM, 17, 8);
454 EXTRACT_HELPER(FPW, 16, 1);
455
456 /*** Jump target decoding ***/
457 /* Immediate address */
458 static inline target_ulong LI(uint32_t opcode)
459 {
460 return (opcode >> 0) & 0x03FFFFFC;
461 }
462
463 static inline uint32_t BD(uint32_t opcode)
464 {
465 return (opcode >> 0) & 0xFFFC;
466 }
467
468 EXTRACT_HELPER(BO, 21, 5);
469 EXTRACT_HELPER(BI, 16, 5);
470 /* Absolute/relative address */
471 EXTRACT_HELPER(AA, 1, 1);
472 /* Link */
473 EXTRACT_HELPER(LK, 0, 1);
474
475 /* DFP Z22-form */
476 EXTRACT_HELPER(DCM, 10, 6)
477
478 /* DFP Z23-form */
479 EXTRACT_HELPER(RMC, 9, 2)
480
481 /* Create a mask between <start> and <end> bits */
482 static inline target_ulong MASK(uint32_t start, uint32_t end)
483 {
484 target_ulong ret;
485
486 #if defined(TARGET_PPC64)
487 if (likely(start == 0)) {
488 ret = UINT64_MAX << (63 - end);
489 } else if (likely(end == 63)) {
490 ret = UINT64_MAX >> start;
491 }
492 #else
493 if (likely(start == 0)) {
494 ret = UINT32_MAX << (31 - end);
495 } else if (likely(end == 31)) {
496 ret = UINT32_MAX >> start;
497 }
498 #endif
499 else {
500 ret = (((target_ulong)(-1ULL)) >> (start)) ^
501 (((target_ulong)(-1ULL) >> (end)) >> 1);
502 if (unlikely(start > end))
503 return ~ret;
504 }
505
506 return ret;
507 }
508
509 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
510 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
511 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
512 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
513 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
514 EXTRACT_HELPER(DM, 8, 2);
515 EXTRACT_HELPER(UIM, 16, 2);
516 EXTRACT_HELPER(SHW, 8, 2);
517 EXTRACT_HELPER(SP, 19, 2);
518 /*****************************************************************************/
519 /* PowerPC instructions table */
520
521 #if defined(DO_PPC_STATISTICS)
522 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
523 { \
524 .opc1 = op1, \
525 .opc2 = op2, \
526 .opc3 = op3, \
527 .pad = { 0, }, \
528 .handler = { \
529 .inval1 = invl, \
530 .type = _typ, \
531 .type2 = _typ2, \
532 .handler = &gen_##name, \
533 .oname = stringify(name), \
534 }, \
535 .oname = stringify(name), \
536 }
537 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
538 { \
539 .opc1 = op1, \
540 .opc2 = op2, \
541 .opc3 = op3, \
542 .pad = { 0, }, \
543 .handler = { \
544 .inval1 = invl1, \
545 .inval2 = invl2, \
546 .type = _typ, \
547 .type2 = _typ2, \
548 .handler = &gen_##name, \
549 .oname = stringify(name), \
550 }, \
551 .oname = stringify(name), \
552 }
553 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
554 { \
555 .opc1 = op1, \
556 .opc2 = op2, \
557 .opc3 = op3, \
558 .pad = { 0, }, \
559 .handler = { \
560 .inval1 = invl, \
561 .type = _typ, \
562 .type2 = _typ2, \
563 .handler = &gen_##name, \
564 .oname = onam, \
565 }, \
566 .oname = onam, \
567 }
568 #else
569 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
570 { \
571 .opc1 = op1, \
572 .opc2 = op2, \
573 .opc3 = op3, \
574 .pad = { 0, }, \
575 .handler = { \
576 .inval1 = invl, \
577 .type = _typ, \
578 .type2 = _typ2, \
579 .handler = &gen_##name, \
580 }, \
581 .oname = stringify(name), \
582 }
583 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
584 { \
585 .opc1 = op1, \
586 .opc2 = op2, \
587 .opc3 = op3, \
588 .pad = { 0, }, \
589 .handler = { \
590 .inval1 = invl1, \
591 .inval2 = invl2, \
592 .type = _typ, \
593 .type2 = _typ2, \
594 .handler = &gen_##name, \
595 }, \
596 .oname = stringify(name), \
597 }
598 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
599 { \
600 .opc1 = op1, \
601 .opc2 = op2, \
602 .opc3 = op3, \
603 .pad = { 0, }, \
604 .handler = { \
605 .inval1 = invl, \
606 .type = _typ, \
607 .type2 = _typ2, \
608 .handler = &gen_##name, \
609 }, \
610 .oname = onam, \
611 }
612 #endif
613
614 /* SPR load/store helpers */
615 static inline void gen_load_spr(TCGv t, int reg)
616 {
617 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
618 }
619
620 static inline void gen_store_spr(int reg, TCGv t)
621 {
622 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
623 }
624
625 /* Invalid instruction */
626 static void gen_invalid(DisasContext *ctx)
627 {
628 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
629 }
630
631 static opc_handler_t invalid_handler = {
632 .inval1 = 0xFFFFFFFF,
633 .inval2 = 0xFFFFFFFF,
634 .type = PPC_NONE,
635 .type2 = PPC_NONE,
636 .handler = gen_invalid,
637 };
638
639 /*** Integer comparison ***/
640
641 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
642 {
643 TCGv t0 = tcg_temp_new();
644 TCGv_i32 t1 = tcg_temp_new_i32();
645
646 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
647
648 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
649 tcg_gen_trunc_tl_i32(t1, t0);
650 tcg_gen_shli_i32(t1, t1, CRF_LT);
651 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
652
653 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
654 tcg_gen_trunc_tl_i32(t1, t0);
655 tcg_gen_shli_i32(t1, t1, CRF_GT);
656 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
657
658 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
659 tcg_gen_trunc_tl_i32(t1, t0);
660 tcg_gen_shli_i32(t1, t1, CRF_EQ);
661 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
662
663 tcg_temp_free(t0);
664 tcg_temp_free_i32(t1);
665 }
666
667 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
668 {
669 TCGv t0 = tcg_const_tl(arg1);
670 gen_op_cmp(arg0, t0, s, crf);
671 tcg_temp_free(t0);
672 }
673
674 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
675 {
676 TCGv t0, t1;
677 t0 = tcg_temp_new();
678 t1 = tcg_temp_new();
679 if (s) {
680 tcg_gen_ext32s_tl(t0, arg0);
681 tcg_gen_ext32s_tl(t1, arg1);
682 } else {
683 tcg_gen_ext32u_tl(t0, arg0);
684 tcg_gen_ext32u_tl(t1, arg1);
685 }
686 gen_op_cmp(t0, t1, s, crf);
687 tcg_temp_free(t1);
688 tcg_temp_free(t0);
689 }
690
691 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
692 {
693 TCGv t0 = tcg_const_tl(arg1);
694 gen_op_cmp32(arg0, t0, s, crf);
695 tcg_temp_free(t0);
696 }
697
698 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
699 {
700 if (NARROW_MODE(ctx)) {
701 gen_op_cmpi32(reg, 0, 1, 0);
702 } else {
703 gen_op_cmpi(reg, 0, 1, 0);
704 }
705 }
706
707 /* cmp */
708 static void gen_cmp(DisasContext *ctx)
709 {
710 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
711 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
712 1, crfD(ctx->opcode));
713 } else {
714 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
715 1, crfD(ctx->opcode));
716 }
717 }
718
719 /* cmpi */
720 static void gen_cmpi(DisasContext *ctx)
721 {
722 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
723 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
724 1, crfD(ctx->opcode));
725 } else {
726 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
727 1, crfD(ctx->opcode));
728 }
729 }
730
731 /* cmpl */
732 static void gen_cmpl(DisasContext *ctx)
733 {
734 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
735 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
736 0, crfD(ctx->opcode));
737 } else {
738 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
739 0, crfD(ctx->opcode));
740 }
741 }
742
743 /* cmpli */
744 static void gen_cmpli(DisasContext *ctx)
745 {
746 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
747 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
748 0, crfD(ctx->opcode));
749 } else {
750 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
751 0, crfD(ctx->opcode));
752 }
753 }
754
755 /* isel (PowerPC 2.03 specification) */
756 static void gen_isel(DisasContext *ctx)
757 {
758 TCGLabel *l1, *l2;
759 uint32_t bi = rC(ctx->opcode);
760 uint32_t mask;
761 TCGv_i32 t0;
762
763 l1 = gen_new_label();
764 l2 = gen_new_label();
765
766 mask = 0x08 >> (bi & 0x03);
767 t0 = tcg_temp_new_i32();
768 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
769 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
770 if (rA(ctx->opcode) == 0)
771 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
772 else
773 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
774 tcg_gen_br(l2);
775 gen_set_label(l1);
776 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
777 gen_set_label(l2);
778 tcg_temp_free_i32(t0);
779 }
780
781 /* cmpb: PowerPC 2.05 specification */
782 static void gen_cmpb(DisasContext *ctx)
783 {
784 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
785 cpu_gpr[rB(ctx->opcode)]);
786 }
787
788 /*** Integer arithmetic ***/
789
790 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
791 TCGv arg1, TCGv arg2, int sub)
792 {
793 TCGv t0 = tcg_temp_new();
794
795 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
796 tcg_gen_xor_tl(t0, arg1, arg2);
797 if (sub) {
798 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
799 } else {
800 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
801 }
802 tcg_temp_free(t0);
803 if (NARROW_MODE(ctx)) {
804 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
805 }
806 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
807 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
808 }
809
810 /* Common add function */
811 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
812 TCGv arg2, bool add_ca, bool compute_ca,
813 bool compute_ov, bool compute_rc0)
814 {
815 TCGv t0 = ret;
816
817 if (compute_ca || compute_ov) {
818 t0 = tcg_temp_new();
819 }
820
821 if (compute_ca) {
822 if (NARROW_MODE(ctx)) {
823 /* Caution: a non-obvious corner case of the spec is that we
824 must produce the *entire* 64-bit addition, but produce the
825 carry into bit 32. */
826 TCGv t1 = tcg_temp_new();
827 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
828 tcg_gen_add_tl(t0, arg1, arg2);
829 if (add_ca) {
830 tcg_gen_add_tl(t0, t0, cpu_ca);
831 }
832 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
833 tcg_temp_free(t1);
834 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
835 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
836 } else {
837 TCGv zero = tcg_const_tl(0);
838 if (add_ca) {
839 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
840 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
841 } else {
842 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
843 }
844 tcg_temp_free(zero);
845 }
846 } else {
847 tcg_gen_add_tl(t0, arg1, arg2);
848 if (add_ca) {
849 tcg_gen_add_tl(t0, t0, cpu_ca);
850 }
851 }
852
853 if (compute_ov) {
854 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
855 }
856 if (unlikely(compute_rc0)) {
857 gen_set_Rc0(ctx, t0);
858 }
859
860 if (!TCGV_EQUAL(t0, ret)) {
861 tcg_gen_mov_tl(ret, t0);
862 tcg_temp_free(t0);
863 }
864 }
865 /* Add functions with two operands */
866 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
867 static void glue(gen_, name)(DisasContext *ctx) \
868 { \
869 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
870 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
871 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
872 }
873 /* Add functions with one operand and one immediate */
874 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
875 add_ca, compute_ca, compute_ov) \
876 static void glue(gen_, name)(DisasContext *ctx) \
877 { \
878 TCGv t0 = tcg_const_tl(const_val); \
879 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
880 cpu_gpr[rA(ctx->opcode)], t0, \
881 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
882 tcg_temp_free(t0); \
883 }
884
885 /* add add. addo addo. */
886 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
887 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
888 /* addc addc. addco addco. */
889 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
890 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
891 /* adde adde. addeo addeo. */
892 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
893 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
894 /* addme addme. addmeo addmeo. */
895 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
896 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
897 /* addze addze. addzeo addzeo.*/
898 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
899 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
900 /* addi */
901 static void gen_addi(DisasContext *ctx)
902 {
903 target_long simm = SIMM(ctx->opcode);
904
905 if (rA(ctx->opcode) == 0) {
906 /* li case */
907 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
908 } else {
909 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
910 cpu_gpr[rA(ctx->opcode)], simm);
911 }
912 }
913 /* addic addic.*/
914 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
915 {
916 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
917 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
918 c, 0, 1, 0, compute_rc0);
919 tcg_temp_free(c);
920 }
921
922 static void gen_addic(DisasContext *ctx)
923 {
924 gen_op_addic(ctx, 0);
925 }
926
927 static void gen_addic_(DisasContext *ctx)
928 {
929 gen_op_addic(ctx, 1);
930 }
931
932 /* addis */
933 static void gen_addis(DisasContext *ctx)
934 {
935 target_long simm = SIMM(ctx->opcode);
936
937 if (rA(ctx->opcode) == 0) {
938 /* lis case */
939 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
940 } else {
941 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
942 cpu_gpr[rA(ctx->opcode)], simm << 16);
943 }
944 }
945
946 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
947 TCGv arg2, int sign, int compute_ov)
948 {
949 TCGLabel *l1 = gen_new_label();
950 TCGLabel *l2 = gen_new_label();
951 TCGv_i32 t0 = tcg_temp_local_new_i32();
952 TCGv_i32 t1 = tcg_temp_local_new_i32();
953
954 tcg_gen_trunc_tl_i32(t0, arg1);
955 tcg_gen_trunc_tl_i32(t1, arg2);
956 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
957 if (sign) {
958 TCGLabel *l3 = gen_new_label();
959 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
960 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
961 gen_set_label(l3);
962 tcg_gen_div_i32(t0, t0, t1);
963 } else {
964 tcg_gen_divu_i32(t0, t0, t1);
965 }
966 if (compute_ov) {
967 tcg_gen_movi_tl(cpu_ov, 0);
968 }
969 tcg_gen_br(l2);
970 gen_set_label(l1);
971 if (sign) {
972 tcg_gen_sari_i32(t0, t0, 31);
973 } else {
974 tcg_gen_movi_i32(t0, 0);
975 }
976 if (compute_ov) {
977 tcg_gen_movi_tl(cpu_ov, 1);
978 tcg_gen_movi_tl(cpu_so, 1);
979 }
980 gen_set_label(l2);
981 tcg_gen_extu_i32_tl(ret, t0);
982 tcg_temp_free_i32(t0);
983 tcg_temp_free_i32(t1);
984 if (unlikely(Rc(ctx->opcode) != 0))
985 gen_set_Rc0(ctx, ret);
986 }
987 /* Div functions */
988 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
989 static void glue(gen_, name)(DisasContext *ctx) \
990 { \
991 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
992 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
993 sign, compute_ov); \
994 }
995 /* divwu divwu. divwuo divwuo. */
996 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
997 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
998 /* divw divw. divwo divwo. */
999 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1000 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1001
1002 /* div[wd]eu[o][.] */
1003 #define GEN_DIVE(name, hlpr, compute_ov) \
1004 static void gen_##name(DisasContext *ctx) \
1005 { \
1006 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1007 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1008 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1009 tcg_temp_free_i32(t0); \
1010 if (unlikely(Rc(ctx->opcode) != 0)) { \
1011 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1012 } \
1013 }
1014
1015 GEN_DIVE(divweu, divweu, 0);
1016 GEN_DIVE(divweuo, divweu, 1);
1017 GEN_DIVE(divwe, divwe, 0);
1018 GEN_DIVE(divweo, divwe, 1);
1019
1020 #if defined(TARGET_PPC64)
1021 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1022 TCGv arg2, int sign, int compute_ov)
1023 {
1024 TCGLabel *l1 = gen_new_label();
1025 TCGLabel *l2 = gen_new_label();
1026
1027 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1028 if (sign) {
1029 TCGLabel *l3 = gen_new_label();
1030 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1031 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1032 gen_set_label(l3);
1033 tcg_gen_div_i64(ret, arg1, arg2);
1034 } else {
1035 tcg_gen_divu_i64(ret, arg1, arg2);
1036 }
1037 if (compute_ov) {
1038 tcg_gen_movi_tl(cpu_ov, 0);
1039 }
1040 tcg_gen_br(l2);
1041 gen_set_label(l1);
1042 if (sign) {
1043 tcg_gen_sari_i64(ret, arg1, 63);
1044 } else {
1045 tcg_gen_movi_i64(ret, 0);
1046 }
1047 if (compute_ov) {
1048 tcg_gen_movi_tl(cpu_ov, 1);
1049 tcg_gen_movi_tl(cpu_so, 1);
1050 }
1051 gen_set_label(l2);
1052 if (unlikely(Rc(ctx->opcode) != 0))
1053 gen_set_Rc0(ctx, ret);
1054 }
1055 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1056 static void glue(gen_, name)(DisasContext *ctx) \
1057 { \
1058 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1059 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1060 sign, compute_ov); \
1061 }
1062 /* divwu divwu. divwuo divwuo. */
1063 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1064 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1065 /* divw divw. divwo divwo. */
1066 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1067 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1068
1069 GEN_DIVE(divdeu, divdeu, 0);
1070 GEN_DIVE(divdeuo, divdeu, 1);
1071 GEN_DIVE(divde, divde, 0);
1072 GEN_DIVE(divdeo, divde, 1);
1073 #endif
1074
1075 /* mulhw mulhw. */
1076 static void gen_mulhw(DisasContext *ctx)
1077 {
1078 TCGv_i32 t0 = tcg_temp_new_i32();
1079 TCGv_i32 t1 = tcg_temp_new_i32();
1080
1081 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1082 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1083 tcg_gen_muls2_i32(t0, t1, t0, t1);
1084 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1085 tcg_temp_free_i32(t0);
1086 tcg_temp_free_i32(t1);
1087 if (unlikely(Rc(ctx->opcode) != 0))
1088 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1089 }
1090
1091 /* mulhwu mulhwu. */
1092 static void gen_mulhwu(DisasContext *ctx)
1093 {
1094 TCGv_i32 t0 = tcg_temp_new_i32();
1095 TCGv_i32 t1 = tcg_temp_new_i32();
1096
1097 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1098 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1099 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1100 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1101 tcg_temp_free_i32(t0);
1102 tcg_temp_free_i32(t1);
1103 if (unlikely(Rc(ctx->opcode) != 0))
1104 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1105 }
1106
1107 /* mullw mullw. */
1108 static void gen_mullw(DisasContext *ctx)
1109 {
1110 #if defined(TARGET_PPC64)
1111 TCGv_i64 t0, t1;
1112 t0 = tcg_temp_new_i64();
1113 t1 = tcg_temp_new_i64();
1114 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1115 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1116 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1117 tcg_temp_free(t0);
1118 tcg_temp_free(t1);
1119 #else
1120 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1121 cpu_gpr[rB(ctx->opcode)]);
1122 #endif
1123 if (unlikely(Rc(ctx->opcode) != 0))
1124 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1125 }
1126
1127 /* mullwo mullwo. */
1128 static void gen_mullwo(DisasContext *ctx)
1129 {
1130 TCGv_i32 t0 = tcg_temp_new_i32();
1131 TCGv_i32 t1 = tcg_temp_new_i32();
1132
1133 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1134 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1135 tcg_gen_muls2_i32(t0, t1, t0, t1);
1136 #if defined(TARGET_PPC64)
1137 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1138 #else
1139 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1140 #endif
1141
1142 tcg_gen_sari_i32(t0, t0, 31);
1143 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1144 tcg_gen_extu_i32_tl(cpu_ov, t0);
1145 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1146
1147 tcg_temp_free_i32(t0);
1148 tcg_temp_free_i32(t1);
1149 if (unlikely(Rc(ctx->opcode) != 0))
1150 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1151 }
1152
1153 /* mulli */
1154 static void gen_mulli(DisasContext *ctx)
1155 {
1156 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1157 SIMM(ctx->opcode));
1158 }
1159
1160 #if defined(TARGET_PPC64)
1161 /* mulhd mulhd. */
1162 static void gen_mulhd(DisasContext *ctx)
1163 {
1164 TCGv lo = tcg_temp_new();
1165 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1166 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1167 tcg_temp_free(lo);
1168 if (unlikely(Rc(ctx->opcode) != 0)) {
1169 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1170 }
1171 }
1172
1173 /* mulhdu mulhdu. */
1174 static void gen_mulhdu(DisasContext *ctx)
1175 {
1176 TCGv lo = tcg_temp_new();
1177 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1178 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1179 tcg_temp_free(lo);
1180 if (unlikely(Rc(ctx->opcode) != 0)) {
1181 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1182 }
1183 }
1184
1185 /* mulld mulld. */
1186 static void gen_mulld(DisasContext *ctx)
1187 {
1188 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1189 cpu_gpr[rB(ctx->opcode)]);
1190 if (unlikely(Rc(ctx->opcode) != 0))
1191 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1192 }
1193
1194 /* mulldo mulldo. */
1195 static void gen_mulldo(DisasContext *ctx)
1196 {
1197 TCGv_i64 t0 = tcg_temp_new_i64();
1198 TCGv_i64 t1 = tcg_temp_new_i64();
1199
1200 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1201 cpu_gpr[rB(ctx->opcode)]);
1202 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1203
1204 tcg_gen_sari_i64(t0, t0, 63);
1205 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1206 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1207
1208 tcg_temp_free_i64(t0);
1209 tcg_temp_free_i64(t1);
1210
1211 if (unlikely(Rc(ctx->opcode) != 0)) {
1212 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1213 }
1214 }
1215 #endif
1216
1217 /* Common subf function */
1218 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1219 TCGv arg2, bool add_ca, bool compute_ca,
1220 bool compute_ov, bool compute_rc0)
1221 {
1222 TCGv t0 = ret;
1223
1224 if (compute_ca || compute_ov) {
1225 t0 = tcg_temp_new();
1226 }
1227
1228 if (compute_ca) {
1229 /* dest = ~arg1 + arg2 [+ ca]. */
1230 if (NARROW_MODE(ctx)) {
1231 /* Caution: a non-obvious corner case of the spec is that we
1232 must produce the *entire* 64-bit addition, but produce the
1233 carry into bit 32. */
1234 TCGv inv1 = tcg_temp_new();
1235 TCGv t1 = tcg_temp_new();
1236 tcg_gen_not_tl(inv1, arg1);
1237 if (add_ca) {
1238 tcg_gen_add_tl(t0, arg2, cpu_ca);
1239 } else {
1240 tcg_gen_addi_tl(t0, arg2, 1);
1241 }
1242 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1243 tcg_gen_add_tl(t0, t0, inv1);
1244 tcg_temp_free(inv1);
1245 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1246 tcg_temp_free(t1);
1247 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1248 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1249 } else if (add_ca) {
1250 TCGv zero, inv1 = tcg_temp_new();
1251 tcg_gen_not_tl(inv1, arg1);
1252 zero = tcg_const_tl(0);
1253 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1254 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1255 tcg_temp_free(zero);
1256 tcg_temp_free(inv1);
1257 } else {
1258 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1259 tcg_gen_sub_tl(t0, arg2, arg1);
1260 }
1261 } else if (add_ca) {
1262 /* Since we're ignoring carry-out, we can simplify the
1263 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1264 tcg_gen_sub_tl(t0, arg2, arg1);
1265 tcg_gen_add_tl(t0, t0, cpu_ca);
1266 tcg_gen_subi_tl(t0, t0, 1);
1267 } else {
1268 tcg_gen_sub_tl(t0, arg2, arg1);
1269 }
1270
1271 if (compute_ov) {
1272 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1273 }
1274 if (unlikely(compute_rc0)) {
1275 gen_set_Rc0(ctx, t0);
1276 }
1277
1278 if (!TCGV_EQUAL(t0, ret)) {
1279 tcg_gen_mov_tl(ret, t0);
1280 tcg_temp_free(t0);
1281 }
1282 }
1283 /* Sub functions with Two operands functions */
1284 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1285 static void glue(gen_, name)(DisasContext *ctx) \
1286 { \
1287 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1288 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1289 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1290 }
1291 /* Sub functions with one operand and one immediate */
1292 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1293 add_ca, compute_ca, compute_ov) \
1294 static void glue(gen_, name)(DisasContext *ctx) \
1295 { \
1296 TCGv t0 = tcg_const_tl(const_val); \
1297 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1298 cpu_gpr[rA(ctx->opcode)], t0, \
1299 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1300 tcg_temp_free(t0); \
1301 }
1302 /* subf subf. subfo subfo. */
1303 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1304 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1305 /* subfc subfc. subfco subfco. */
1306 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1307 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1308 /* subfe subfe. subfeo subfo. */
1309 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1310 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1311 /* subfme subfme. subfmeo subfmeo. */
1312 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1313 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1314 /* subfze subfze. subfzeo subfzeo.*/
1315 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1316 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1317
1318 /* subfic */
1319 static void gen_subfic(DisasContext *ctx)
1320 {
1321 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1322 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1323 c, 0, 1, 0, 0);
1324 tcg_temp_free(c);
1325 }
1326
1327 /* neg neg. nego nego. */
1328 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1329 {
1330 TCGv zero = tcg_const_tl(0);
1331 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1332 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1333 tcg_temp_free(zero);
1334 }
1335
1336 static void gen_neg(DisasContext *ctx)
1337 {
1338 gen_op_arith_neg(ctx, 0);
1339 }
1340
1341 static void gen_nego(DisasContext *ctx)
1342 {
1343 gen_op_arith_neg(ctx, 1);
1344 }
1345
1346 /*** Integer logical ***/
1347 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1348 static void glue(gen_, name)(DisasContext *ctx) \
1349 { \
1350 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1351 cpu_gpr[rB(ctx->opcode)]); \
1352 if (unlikely(Rc(ctx->opcode) != 0)) \
1353 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1354 }
1355
1356 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1357 static void glue(gen_, name)(DisasContext *ctx) \
1358 { \
1359 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1360 if (unlikely(Rc(ctx->opcode) != 0)) \
1361 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1362 }
1363
1364 /* and & and. */
1365 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1366 /* andc & andc. */
1367 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1368
1369 /* andi. */
1370 static void gen_andi_(DisasContext *ctx)
1371 {
1372 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1373 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1374 }
1375
1376 /* andis. */
1377 static void gen_andis_(DisasContext *ctx)
1378 {
1379 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1380 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1381 }
1382
1383 /* cntlzw */
1384 static void gen_cntlzw(DisasContext *ctx)
1385 {
1386 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1387 if (unlikely(Rc(ctx->opcode) != 0))
1388 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1389 }
1390 /* eqv & eqv. */
1391 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1392 /* extsb & extsb. */
1393 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1394 /* extsh & extsh. */
1395 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1396 /* nand & nand. */
1397 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1398 /* nor & nor. */
1399 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1400
1401 /* or & or. */
1402 static void gen_or(DisasContext *ctx)
1403 {
1404 int rs, ra, rb;
1405
1406 rs = rS(ctx->opcode);
1407 ra = rA(ctx->opcode);
1408 rb = rB(ctx->opcode);
1409 /* Optimisation for mr. ri case */
1410 if (rs != ra || rs != rb) {
1411 if (rs != rb)
1412 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1413 else
1414 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1415 if (unlikely(Rc(ctx->opcode) != 0))
1416 gen_set_Rc0(ctx, cpu_gpr[ra]);
1417 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1418 gen_set_Rc0(ctx, cpu_gpr[rs]);
1419 #if defined(TARGET_PPC64)
1420 } else {
1421 int prio = 0;
1422
1423 switch (rs) {
1424 case 1:
1425 /* Set process priority to low */
1426 prio = 2;
1427 break;
1428 case 6:
1429 /* Set process priority to medium-low */
1430 prio = 3;
1431 break;
1432 case 2:
1433 /* Set process priority to normal */
1434 prio = 4;
1435 break;
1436 #if !defined(CONFIG_USER_ONLY)
1437 case 31:
1438 if (!ctx->pr) {
1439 /* Set process priority to very low */
1440 prio = 1;
1441 }
1442 break;
1443 case 5:
1444 if (!ctx->pr) {
1445 /* Set process priority to medium-hight */
1446 prio = 5;
1447 }
1448 break;
1449 case 3:
1450 if (!ctx->pr) {
1451 /* Set process priority to high */
1452 prio = 6;
1453 }
1454 break;
1455 case 7:
1456 if (ctx->hv) {
1457 /* Set process priority to very high */
1458 prio = 7;
1459 }
1460 break;
1461 #endif
1462 default:
1463 /* nop */
1464 break;
1465 }
1466 if (prio) {
1467 TCGv t0 = tcg_temp_new();
1468 gen_load_spr(t0, SPR_PPR);
1469 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1470 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1471 gen_store_spr(SPR_PPR, t0);
1472 tcg_temp_free(t0);
1473 }
1474 #endif
1475 }
1476 }
1477 /* orc & orc. */
1478 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1479
1480 /* xor & xor. */
1481 static void gen_xor(DisasContext *ctx)
1482 {
1483 /* Optimisation for "set to zero" case */
1484 if (rS(ctx->opcode) != rB(ctx->opcode))
1485 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1486 else
1487 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1488 if (unlikely(Rc(ctx->opcode) != 0))
1489 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1490 }
1491
1492 /* ori */
1493 static void gen_ori(DisasContext *ctx)
1494 {
1495 target_ulong uimm = UIMM(ctx->opcode);
1496
1497 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1498 /* NOP */
1499 /* XXX: should handle special NOPs for POWER series */
1500 return;
1501 }
1502 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1503 }
1504
1505 /* oris */
1506 static void gen_oris(DisasContext *ctx)
1507 {
1508 target_ulong uimm = UIMM(ctx->opcode);
1509
1510 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1511 /* NOP */
1512 return;
1513 }
1514 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1515 }
1516
1517 /* xori */
1518 static void gen_xori(DisasContext *ctx)
1519 {
1520 target_ulong uimm = UIMM(ctx->opcode);
1521
1522 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1523 /* NOP */
1524 return;
1525 }
1526 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1527 }
1528
1529 /* xoris */
1530 static void gen_xoris(DisasContext *ctx)
1531 {
1532 target_ulong uimm = UIMM(ctx->opcode);
1533
1534 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1535 /* NOP */
1536 return;
1537 }
1538 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1539 }
1540
1541 /* popcntb : PowerPC 2.03 specification */
1542 static void gen_popcntb(DisasContext *ctx)
1543 {
1544 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1545 }
1546
1547 static void gen_popcntw(DisasContext *ctx)
1548 {
1549 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1550 }
1551
1552 #if defined(TARGET_PPC64)
1553 /* popcntd: PowerPC 2.06 specification */
1554 static void gen_popcntd(DisasContext *ctx)
1555 {
1556 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1557 }
1558 #endif
1559
1560 /* prtyw: PowerPC 2.05 specification */
1561 static void gen_prtyw(DisasContext *ctx)
1562 {
1563 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1564 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1565 TCGv t0 = tcg_temp_new();
1566 tcg_gen_shri_tl(t0, rs, 16);
1567 tcg_gen_xor_tl(ra, rs, t0);
1568 tcg_gen_shri_tl(t0, ra, 8);
1569 tcg_gen_xor_tl(ra, ra, t0);
1570 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1571 tcg_temp_free(t0);
1572 }
1573
1574 #if defined(TARGET_PPC64)
1575 /* prtyd: PowerPC 2.05 specification */
1576 static void gen_prtyd(DisasContext *ctx)
1577 {
1578 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1579 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1580 TCGv t0 = tcg_temp_new();
1581 tcg_gen_shri_tl(t0, rs, 32);
1582 tcg_gen_xor_tl(ra, rs, t0);
1583 tcg_gen_shri_tl(t0, ra, 16);
1584 tcg_gen_xor_tl(ra, ra, t0);
1585 tcg_gen_shri_tl(t0, ra, 8);
1586 tcg_gen_xor_tl(ra, ra, t0);
1587 tcg_gen_andi_tl(ra, ra, 1);
1588 tcg_temp_free(t0);
1589 }
1590 #endif
1591
1592 #if defined(TARGET_PPC64)
1593 /* bpermd */
1594 static void gen_bpermd(DisasContext *ctx)
1595 {
1596 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1597 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1598 }
1599 #endif
1600
1601 #if defined(TARGET_PPC64)
1602 /* extsw & extsw. */
1603 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1604
1605 /* cntlzd */
1606 static void gen_cntlzd(DisasContext *ctx)
1607 {
1608 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1609 if (unlikely(Rc(ctx->opcode) != 0))
1610 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1611 }
1612 #endif
1613
1614 /*** Integer rotate ***/
1615
1616 /* rlwimi & rlwimi. */
1617 static void gen_rlwimi(DisasContext *ctx)
1618 {
1619 uint32_t mb, me, sh;
1620
1621 mb = MB(ctx->opcode);
1622 me = ME(ctx->opcode);
1623 sh = SH(ctx->opcode);
1624 if (likely(sh == (31-me) && mb <= me)) {
1625 tcg_gen_deposit_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1626 cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1);
1627 } else {
1628 target_ulong mask;
1629 TCGv t1;
1630 TCGv t0 = tcg_temp_new();
1631 #if defined(TARGET_PPC64)
1632 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1633 cpu_gpr[rS(ctx->opcode)], 32, 32);
1634 tcg_gen_rotli_i64(t0, t0, sh);
1635 #else
1636 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1637 #endif
1638 #if defined(TARGET_PPC64)
1639 mb += 32;
1640 me += 32;
1641 #endif
1642 mask = MASK(mb, me);
1643 t1 = tcg_temp_new();
1644 tcg_gen_andi_tl(t0, t0, mask);
1645 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1646 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1647 tcg_temp_free(t0);
1648 tcg_temp_free(t1);
1649 }
1650 if (unlikely(Rc(ctx->opcode) != 0))
1651 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1652 }
1653
1654 /* rlwinm & rlwinm. */
1655 static void gen_rlwinm(DisasContext *ctx)
1656 {
1657 uint32_t mb, me, sh;
1658
1659 sh = SH(ctx->opcode);
1660 mb = MB(ctx->opcode);
1661 me = ME(ctx->opcode);
1662
1663 if (likely(mb == 0 && me == (31 - sh))) {
1664 if (likely(sh == 0)) {
1665 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1666 } else {
1667 TCGv t0 = tcg_temp_new();
1668 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1669 tcg_gen_shli_tl(t0, t0, sh);
1670 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1671 tcg_temp_free(t0);
1672 }
1673 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1674 TCGv t0 = tcg_temp_new();
1675 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1676 tcg_gen_shri_tl(t0, t0, mb);
1677 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1678 tcg_temp_free(t0);
1679 } else if (likely(mb == 0 && me == 31)) {
1680 TCGv_i32 t0 = tcg_temp_new_i32();
1681 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rS(ctx->opcode)]);
1682 tcg_gen_rotli_i32(t0, t0, sh);
1683 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t0);
1684 tcg_temp_free_i32(t0);
1685 } else {
1686 TCGv t0 = tcg_temp_new();
1687 #if defined(TARGET_PPC64)
1688 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1689 cpu_gpr[rS(ctx->opcode)], 32, 32);
1690 tcg_gen_rotli_i64(t0, t0, sh);
1691 #else
1692 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1693 #endif
1694 #if defined(TARGET_PPC64)
1695 mb += 32;
1696 me += 32;
1697 #endif
1698 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1699 tcg_temp_free(t0);
1700 }
1701 if (unlikely(Rc(ctx->opcode) != 0))
1702 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1703 }
1704
1705 /* rlwnm & rlwnm. */
1706 static void gen_rlwnm(DisasContext *ctx)
1707 {
1708 uint32_t mb, me;
1709 mb = MB(ctx->opcode);
1710 me = ME(ctx->opcode);
1711
1712 if (likely(mb == 0 && me == 31)) {
1713 TCGv_i32 t0, t1;
1714 t0 = tcg_temp_new_i32();
1715 t1 = tcg_temp_new_i32();
1716 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]);
1717 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1718 tcg_gen_andi_i32(t0, t0, 0x1f);
1719 tcg_gen_rotl_i32(t1, t1, t0);
1720 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t1);
1721 tcg_temp_free_i32(t0);
1722 tcg_temp_free_i32(t1);
1723 } else {
1724 TCGv t0;
1725 #if defined(TARGET_PPC64)
1726 TCGv t1;
1727 #endif
1728
1729 t0 = tcg_temp_new();
1730 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1731 #if defined(TARGET_PPC64)
1732 t1 = tcg_temp_new_i64();
1733 tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)],
1734 cpu_gpr[rS(ctx->opcode)], 32, 32);
1735 tcg_gen_rotl_i64(t0, t1, t0);
1736 tcg_temp_free_i64(t1);
1737 #else
1738 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1739 #endif
1740 if (unlikely(mb != 0 || me != 31)) {
1741 #if defined(TARGET_PPC64)
1742 mb += 32;
1743 me += 32;
1744 #endif
1745 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1746 } else {
1747 tcg_gen_andi_tl(t0, t0, MASK(32, 63));
1748 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1749 }
1750 tcg_temp_free(t0);
1751 }
1752 if (unlikely(Rc(ctx->opcode) != 0))
1753 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1754 }
1755
1756 #if defined(TARGET_PPC64)
1757 #define GEN_PPC64_R2(name, opc1, opc2) \
1758 static void glue(gen_, name##0)(DisasContext *ctx) \
1759 { \
1760 gen_##name(ctx, 0); \
1761 } \
1762 \
1763 static void glue(gen_, name##1)(DisasContext *ctx) \
1764 { \
1765 gen_##name(ctx, 1); \
1766 }
1767 #define GEN_PPC64_R4(name, opc1, opc2) \
1768 static void glue(gen_, name##0)(DisasContext *ctx) \
1769 { \
1770 gen_##name(ctx, 0, 0); \
1771 } \
1772 \
1773 static void glue(gen_, name##1)(DisasContext *ctx) \
1774 { \
1775 gen_##name(ctx, 0, 1); \
1776 } \
1777 \
1778 static void glue(gen_, name##2)(DisasContext *ctx) \
1779 { \
1780 gen_##name(ctx, 1, 0); \
1781 } \
1782 \
1783 static void glue(gen_, name##3)(DisasContext *ctx) \
1784 { \
1785 gen_##name(ctx, 1, 1); \
1786 }
1787
1788 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1789 uint32_t sh)
1790 {
1791 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1792 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1793 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1794 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1795 } else {
1796 TCGv t0 = tcg_temp_new();
1797 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1798 if (likely(mb == 0 && me == 63)) {
1799 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1800 } else {
1801 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1802 }
1803 tcg_temp_free(t0);
1804 }
1805 if (unlikely(Rc(ctx->opcode) != 0))
1806 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1807 }
1808 /* rldicl - rldicl. */
1809 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1810 {
1811 uint32_t sh, mb;
1812
1813 sh = SH(ctx->opcode) | (shn << 5);
1814 mb = MB(ctx->opcode) | (mbn << 5);
1815 gen_rldinm(ctx, mb, 63, sh);
1816 }
1817 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1818 /* rldicr - rldicr. */
1819 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1820 {
1821 uint32_t sh, me;
1822
1823 sh = SH(ctx->opcode) | (shn << 5);
1824 me = MB(ctx->opcode) | (men << 5);
1825 gen_rldinm(ctx, 0, me, sh);
1826 }
1827 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1828 /* rldic - rldic. */
1829 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1830 {
1831 uint32_t sh, mb;
1832
1833 sh = SH(ctx->opcode) | (shn << 5);
1834 mb = MB(ctx->opcode) | (mbn << 5);
1835 gen_rldinm(ctx, mb, 63 - sh, sh);
1836 }
1837 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1838
1839 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1840 {
1841 TCGv t0;
1842
1843 t0 = tcg_temp_new();
1844 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1845 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1846 if (unlikely(mb != 0 || me != 63)) {
1847 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1848 } else {
1849 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1850 }
1851 tcg_temp_free(t0);
1852 if (unlikely(Rc(ctx->opcode) != 0))
1853 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1854 }
1855
1856 /* rldcl - rldcl. */
1857 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1858 {
1859 uint32_t mb;
1860
1861 mb = MB(ctx->opcode) | (mbn << 5);
1862 gen_rldnm(ctx, mb, 63);
1863 }
1864 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1865 /* rldcr - rldcr. */
1866 static inline void gen_rldcr(DisasContext *ctx, int men)
1867 {
1868 uint32_t me;
1869
1870 me = MB(ctx->opcode) | (men << 5);
1871 gen_rldnm(ctx, 0, me);
1872 }
1873 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1874 /* rldimi - rldimi. */
1875 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1876 {
1877 uint32_t sh, mb, me;
1878
1879 sh = SH(ctx->opcode) | (shn << 5);
1880 mb = MB(ctx->opcode) | (mbn << 5);
1881 me = 63 - sh;
1882 if (unlikely(sh == 0 && mb == 0)) {
1883 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1884 } else {
1885 TCGv t0, t1;
1886 target_ulong mask;
1887
1888 t0 = tcg_temp_new();
1889 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1890 t1 = tcg_temp_new();
1891 mask = MASK(mb, me);
1892 tcg_gen_andi_tl(t0, t0, mask);
1893 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1894 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1895 tcg_temp_free(t0);
1896 tcg_temp_free(t1);
1897 }
1898 if (unlikely(Rc(ctx->opcode) != 0))
1899 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1900 }
1901 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1902 #endif
1903
1904 /*** Integer shift ***/
1905
1906 /* slw & slw. */
1907 static void gen_slw(DisasContext *ctx)
1908 {
1909 TCGv t0, t1;
1910
1911 t0 = tcg_temp_new();
1912 /* AND rS with a mask that is 0 when rB >= 0x20 */
1913 #if defined(TARGET_PPC64)
1914 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1915 tcg_gen_sari_tl(t0, t0, 0x3f);
1916 #else
1917 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1918 tcg_gen_sari_tl(t0, t0, 0x1f);
1919 #endif
1920 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1921 t1 = tcg_temp_new();
1922 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1923 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1924 tcg_temp_free(t1);
1925 tcg_temp_free(t0);
1926 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1927 if (unlikely(Rc(ctx->opcode) != 0))
1928 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1929 }
1930
1931 /* sraw & sraw. */
1932 static void gen_sraw(DisasContext *ctx)
1933 {
1934 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1935 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1936 if (unlikely(Rc(ctx->opcode) != 0))
1937 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1938 }
1939
1940 /* srawi & srawi. */
1941 static void gen_srawi(DisasContext *ctx)
1942 {
1943 int sh = SH(ctx->opcode);
1944 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1945 TCGv src = cpu_gpr[rS(ctx->opcode)];
1946 if (sh == 0) {
1947 tcg_gen_ext32s_tl(dst, src);
1948 tcg_gen_movi_tl(cpu_ca, 0);
1949 } else {
1950 TCGv t0;
1951 tcg_gen_ext32s_tl(dst, src);
1952 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1953 t0 = tcg_temp_new();
1954 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1955 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1956 tcg_temp_free(t0);
1957 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1958 tcg_gen_sari_tl(dst, dst, sh);
1959 }
1960 if (unlikely(Rc(ctx->opcode) != 0)) {
1961 gen_set_Rc0(ctx, dst);
1962 }
1963 }
1964
1965 /* srw & srw. */
1966 static void gen_srw(DisasContext *ctx)
1967 {
1968 TCGv t0, t1;
1969
1970 t0 = tcg_temp_new();
1971 /* AND rS with a mask that is 0 when rB >= 0x20 */
1972 #if defined(TARGET_PPC64)
1973 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1974 tcg_gen_sari_tl(t0, t0, 0x3f);
1975 #else
1976 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1977 tcg_gen_sari_tl(t0, t0, 0x1f);
1978 #endif
1979 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1980 tcg_gen_ext32u_tl(t0, t0);
1981 t1 = tcg_temp_new();
1982 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1983 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1984 tcg_temp_free(t1);
1985 tcg_temp_free(t0);
1986 if (unlikely(Rc(ctx->opcode) != 0))
1987 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1988 }
1989
1990 #if defined(TARGET_PPC64)
1991 /* sld & sld. */
1992 static void gen_sld(DisasContext *ctx)
1993 {
1994 TCGv t0, t1;
1995
1996 t0 = tcg_temp_new();
1997 /* AND rS with a mask that is 0 when rB >= 0x40 */
1998 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1999 tcg_gen_sari_tl(t0, t0, 0x3f);
2000 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2001 t1 = tcg_temp_new();
2002 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2003 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2004 tcg_temp_free(t1);
2005 tcg_temp_free(t0);
2006 if (unlikely(Rc(ctx->opcode) != 0))
2007 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2008 }
2009
2010 /* srad & srad. */
2011 static void gen_srad(DisasContext *ctx)
2012 {
2013 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2014 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2015 if (unlikely(Rc(ctx->opcode) != 0))
2016 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2017 }
2018 /* sradi & sradi. */
2019 static inline void gen_sradi(DisasContext *ctx, int n)
2020 {
2021 int sh = SH(ctx->opcode) + (n << 5);
2022 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2023 TCGv src = cpu_gpr[rS(ctx->opcode)];
2024 if (sh == 0) {
2025 tcg_gen_mov_tl(dst, src);
2026 tcg_gen_movi_tl(cpu_ca, 0);
2027 } else {
2028 TCGv t0;
2029 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2030 t0 = tcg_temp_new();
2031 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2032 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2033 tcg_temp_free(t0);
2034 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2035 tcg_gen_sari_tl(dst, src, sh);
2036 }
2037 if (unlikely(Rc(ctx->opcode) != 0)) {
2038 gen_set_Rc0(ctx, dst);
2039 }
2040 }
2041
2042 static void gen_sradi0(DisasContext *ctx)
2043 {
2044 gen_sradi(ctx, 0);
2045 }
2046
2047 static void gen_sradi1(DisasContext *ctx)
2048 {
2049 gen_sradi(ctx, 1);
2050 }
2051
2052 /* srd & srd. */
2053 static void gen_srd(DisasContext *ctx)
2054 {
2055 TCGv t0, t1;
2056
2057 t0 = tcg_temp_new();
2058 /* AND rS with a mask that is 0 when rB >= 0x40 */
2059 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2060 tcg_gen_sari_tl(t0, t0, 0x3f);
2061 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2062 t1 = tcg_temp_new();
2063 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2064 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2065 tcg_temp_free(t1);
2066 tcg_temp_free(t0);
2067 if (unlikely(Rc(ctx->opcode) != 0))
2068 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2069 }
2070 #endif
2071
2072 #if defined(TARGET_PPC64)
2073 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2074 {
2075 TCGv_i32 tmp = tcg_temp_new_i32();
2076 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2077 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2078 tcg_temp_free_i32(tmp);
2079 }
2080 #else
2081 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2082 {
2083 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2084 }
2085 #endif
2086
2087 /*** Floating-Point arithmetic ***/
2088 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2089 static void gen_f##name(DisasContext *ctx) \
2090 { \
2091 if (unlikely(!ctx->fpu_enabled)) { \
2092 gen_exception(ctx, POWERPC_EXCP_FPU); \
2093 return; \
2094 } \
2095 /* NIP cannot be restored if the memory exception comes from an helper */ \
2096 gen_update_nip(ctx, ctx->nip - 4); \
2097 gen_reset_fpstatus(); \
2098 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2099 cpu_fpr[rA(ctx->opcode)], \
2100 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2101 if (isfloat) { \
2102 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2103 cpu_fpr[rD(ctx->opcode)]); \
2104 } \
2105 if (set_fprf) { \
2106 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2107 } \
2108 if (unlikely(Rc(ctx->opcode) != 0)) { \
2109 gen_set_cr1_from_fpscr(ctx); \
2110 } \
2111 }
2112
2113 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2114 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2115 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2116
2117 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2118 static void gen_f##name(DisasContext *ctx) \
2119 { \
2120 if (unlikely(!ctx->fpu_enabled)) { \
2121 gen_exception(ctx, POWERPC_EXCP_FPU); \
2122 return; \
2123 } \
2124 /* NIP cannot be restored if the memory exception comes from an helper */ \
2125 gen_update_nip(ctx, ctx->nip - 4); \
2126 gen_reset_fpstatus(); \
2127 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2128 cpu_fpr[rA(ctx->opcode)], \
2129 cpu_fpr[rB(ctx->opcode)]); \
2130 if (isfloat) { \
2131 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2132 cpu_fpr[rD(ctx->opcode)]); \
2133 } \
2134 if (set_fprf) { \
2135 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2136 } \
2137 if (unlikely(Rc(ctx->opcode) != 0)) { \
2138 gen_set_cr1_from_fpscr(ctx); \
2139 } \
2140 }
2141 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2142 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2143 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2144
2145 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2146 static void gen_f##name(DisasContext *ctx) \
2147 { \
2148 if (unlikely(!ctx->fpu_enabled)) { \
2149 gen_exception(ctx, POWERPC_EXCP_FPU); \
2150 return; \
2151 } \
2152 /* NIP cannot be restored if the memory exception comes from an helper */ \
2153 gen_update_nip(ctx, ctx->nip - 4); \
2154 gen_reset_fpstatus(); \
2155 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2156 cpu_fpr[rA(ctx->opcode)], \
2157 cpu_fpr[rC(ctx->opcode)]); \
2158 if (isfloat) { \
2159 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2160 cpu_fpr[rD(ctx->opcode)]); \
2161 } \
2162 if (set_fprf) { \
2163 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2164 } \
2165 if (unlikely(Rc(ctx->opcode) != 0)) { \
2166 gen_set_cr1_from_fpscr(ctx); \
2167 } \
2168 }
2169 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2170 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2171 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2172
2173 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2174 static void gen_f##name(DisasContext *ctx) \
2175 { \
2176 if (unlikely(!ctx->fpu_enabled)) { \
2177 gen_exception(ctx, POWERPC_EXCP_FPU); \
2178 return; \
2179 } \
2180 /* NIP cannot be restored if the memory exception comes from an helper */ \
2181 gen_update_nip(ctx, ctx->nip - 4); \
2182 gen_reset_fpstatus(); \
2183 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2184 cpu_fpr[rB(ctx->opcode)]); \
2185 if (set_fprf) { \
2186 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2187 } \
2188 if (unlikely(Rc(ctx->opcode) != 0)) { \
2189 gen_set_cr1_from_fpscr(ctx); \
2190 } \
2191 }
2192
2193 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2194 static void gen_f##name(DisasContext *ctx) \
2195 { \
2196 if (unlikely(!ctx->fpu_enabled)) { \
2197 gen_exception(ctx, POWERPC_EXCP_FPU); \
2198 return; \
2199 } \
2200 /* NIP cannot be restored if the memory exception comes from an helper */ \
2201 gen_update_nip(ctx, ctx->nip - 4); \
2202 gen_reset_fpstatus(); \
2203 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2204 cpu_fpr[rB(ctx->opcode)]); \
2205 if (set_fprf) { \
2206 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2207 } \
2208 if (unlikely(Rc(ctx->opcode) != 0)) { \
2209 gen_set_cr1_from_fpscr(ctx); \
2210 } \
2211 }
2212
2213 /* fadd - fadds */
2214 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2215 /* fdiv - fdivs */
2216 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2217 /* fmul - fmuls */
2218 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2219
2220 /* fre */
2221 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2222
2223 /* fres */
2224 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2225
2226 /* frsqrte */
2227 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2228
2229 /* frsqrtes */
2230 static void gen_frsqrtes(DisasContext *ctx)
2231 {
2232 if (unlikely(!ctx->fpu_enabled)) {
2233 gen_exception(ctx, POWERPC_EXCP_FPU);
2234 return;
2235 }
2236 /* NIP cannot be restored if the memory exception comes from an helper */
2237 gen_update_nip(ctx, ctx->nip - 4);
2238 gen_reset_fpstatus();
2239 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2240 cpu_fpr[rB(ctx->opcode)]);
2241 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2242 cpu_fpr[rD(ctx->opcode)]);
2243 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2244 if (unlikely(Rc(ctx->opcode) != 0)) {
2245 gen_set_cr1_from_fpscr(ctx);
2246 }
2247 }
2248
2249 /* fsel */
2250 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2251 /* fsub - fsubs */
2252 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2253 /* Optional: */
2254
2255 /* fsqrt */
2256 static void gen_fsqrt(DisasContext *ctx)
2257 {
2258 if (unlikely(!ctx->fpu_enabled)) {
2259 gen_exception(ctx, POWERPC_EXCP_FPU);
2260 return;
2261 }
2262 /* NIP cannot be restored if the memory exception comes from an helper */
2263 gen_update_nip(ctx, ctx->nip - 4);
2264 gen_reset_fpstatus();
2265 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2266 cpu_fpr[rB(ctx->opcode)]);
2267 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2268 if (unlikely(Rc(ctx->opcode) != 0)) {
2269 gen_set_cr1_from_fpscr(ctx);
2270 }
2271 }
2272
2273 static void gen_fsqrts(DisasContext *ctx)
2274 {
2275 if (unlikely(!ctx->fpu_enabled)) {
2276 gen_exception(ctx, POWERPC_EXCP_FPU);
2277 return;
2278 }
2279 /* NIP cannot be restored if the memory exception comes from an helper */
2280 gen_update_nip(ctx, ctx->nip - 4);
2281 gen_reset_fpstatus();
2282 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2283 cpu_fpr[rB(ctx->opcode)]);
2284 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2285 cpu_fpr[rD(ctx->opcode)]);
2286 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2287 if (unlikely(Rc(ctx->opcode) != 0)) {
2288 gen_set_cr1_from_fpscr(ctx);
2289 }
2290 }
2291
2292 /*** Floating-Point multiply-and-add ***/
2293 /* fmadd - fmadds */
2294 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2295 /* fmsub - fmsubs */
2296 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2297 /* fnmadd - fnmadds */
2298 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2299 /* fnmsub - fnmsubs */
2300 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2301
2302 /*** Floating-Point round & convert ***/
2303 /* fctiw */
2304 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2305 /* fctiwu */
2306 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2307 /* fctiwz */
2308 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2309 /* fctiwuz */
2310 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2311 /* frsp */
2312 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2313 /* fcfid */
2314 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
2315 /* fcfids */
2316 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2317 /* fcfidu */
2318 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2319 /* fcfidus */
2320 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2321 /* fctid */
2322 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
2323 /* fctidu */
2324 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2325 /* fctidz */
2326 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
2327 /* fctidu */
2328 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2329
2330 /* frin */
2331 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2332 /* friz */
2333 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2334 /* frip */
2335 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2336 /* frim */
2337 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2338
2339 static void gen_ftdiv(DisasContext *ctx)
2340 {
2341 if (unlikely(!ctx->fpu_enabled)) {
2342 gen_exception(ctx, POWERPC_EXCP_FPU);
2343 return;
2344 }
2345 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2346 cpu_fpr[rB(ctx->opcode)]);
2347 }
2348
2349 static void gen_ftsqrt(DisasContext *ctx)
2350 {
2351 if (unlikely(!ctx->fpu_enabled)) {
2352 gen_exception(ctx, POWERPC_EXCP_FPU);
2353 return;
2354 }
2355 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2356 }
2357
2358
2359
2360 /*** Floating-Point compare ***/
2361
2362 /* fcmpo */
2363 static void gen_fcmpo(DisasContext *ctx)
2364 {
2365 TCGv_i32 crf;
2366 if (unlikely(!ctx->fpu_enabled)) {
2367 gen_exception(ctx, POWERPC_EXCP_FPU);
2368 return;
2369 }
2370 /* NIP cannot be restored if the memory exception comes from an helper */
2371 gen_update_nip(ctx, ctx->nip - 4);
2372 gen_reset_fpstatus();
2373 crf = tcg_const_i32(crfD(ctx->opcode));
2374 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2375 cpu_fpr[rB(ctx->opcode)], crf);
2376 tcg_temp_free_i32(crf);
2377 gen_helper_float_check_status(cpu_env);
2378 }
2379
2380 /* fcmpu */
2381 static void gen_fcmpu(DisasContext *ctx)
2382 {
2383 TCGv_i32 crf;
2384 if (unlikely(!ctx->fpu_enabled)) {
2385 gen_exception(ctx, POWERPC_EXCP_FPU);
2386 return;
2387 }
2388 /* NIP cannot be restored if the memory exception comes from an helper */
2389 gen_update_nip(ctx, ctx->nip - 4);
2390 gen_reset_fpstatus();
2391 crf = tcg_const_i32(crfD(ctx->opcode));
2392 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2393 cpu_fpr[rB(ctx->opcode)], crf);
2394 tcg_temp_free_i32(crf);
2395 gen_helper_float_check_status(cpu_env);
2396 }
2397
2398 /*** Floating-point move ***/
2399 /* fabs */
2400 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2401 static void gen_fabs(DisasContext *ctx)
2402 {
2403 if (unlikely(!ctx->fpu_enabled)) {
2404 gen_exception(ctx, POWERPC_EXCP_FPU);
2405 return;
2406 }
2407 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2408 ~(1ULL << 63));
2409 if (unlikely(Rc(ctx->opcode))) {
2410 gen_set_cr1_from_fpscr(ctx);
2411 }
2412 }
2413
2414 /* fmr - fmr. */
2415 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2416 static void gen_fmr(DisasContext *ctx)
2417 {
2418 if (unlikely(!ctx->fpu_enabled)) {
2419 gen_exception(ctx, POWERPC_EXCP_FPU);
2420 return;
2421 }
2422 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2423 if (unlikely(Rc(ctx->opcode))) {
2424 gen_set_cr1_from_fpscr(ctx);
2425 }
2426 }
2427
2428 /* fnabs */
2429 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2430 static void gen_fnabs(DisasContext *ctx)
2431 {
2432 if (unlikely(!ctx->fpu_enabled)) {
2433 gen_exception(ctx, POWERPC_EXCP_FPU);
2434 return;
2435 }
2436 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2437 1ULL << 63);
2438 if (unlikely(Rc(ctx->opcode))) {
2439 gen_set_cr1_from_fpscr(ctx);
2440 }
2441 }
2442
2443 /* fneg */
2444 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2445 static void gen_fneg(DisasContext *ctx)
2446 {
2447 if (unlikely(!ctx->fpu_enabled)) {
2448 gen_exception(ctx, POWERPC_EXCP_FPU);
2449 return;
2450 }
2451 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2452 1ULL << 63);
2453 if (unlikely(Rc(ctx->opcode))) {
2454 gen_set_cr1_from_fpscr(ctx);
2455 }
2456 }
2457
2458 /* fcpsgn: PowerPC 2.05 specification */
2459 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2460 static void gen_fcpsgn(DisasContext *ctx)
2461 {
2462 if (unlikely(!ctx->fpu_enabled)) {
2463 gen_exception(ctx, POWERPC_EXCP_FPU);
2464 return;
2465 }
2466 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2467 cpu_fpr[rB(ctx->opcode)], 0, 63);
2468 if (unlikely(Rc(ctx->opcode))) {
2469 gen_set_cr1_from_fpscr(ctx);
2470 }
2471 }
2472
2473 static void gen_fmrgew(DisasContext *ctx)
2474 {
2475 TCGv_i64 b0;
2476 if (unlikely(!ctx->fpu_enabled)) {
2477 gen_exception(ctx, POWERPC_EXCP_FPU);
2478 return;
2479 }
2480 b0 = tcg_temp_new_i64();
2481 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2482 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2483 b0, 0, 32);
2484 tcg_temp_free_i64(b0);
2485 }
2486
2487 static void gen_fmrgow(DisasContext *ctx)
2488 {
2489 if (unlikely(!ctx->fpu_enabled)) {
2490 gen_exception(ctx, POWERPC_EXCP_FPU);
2491 return;
2492 }
2493 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2494 cpu_fpr[rB(ctx->opcode)],
2495 cpu_fpr[rA(ctx->opcode)],
2496 32, 32);
2497 }
2498
2499 /*** Floating-Point status & ctrl register ***/
2500
2501 /* mcrfs */
2502 static void gen_mcrfs(DisasContext *ctx)
2503 {
2504 TCGv tmp = tcg_temp_new();
2505 TCGv_i32 tmask;
2506 TCGv_i64 tnew_fpscr = tcg_temp_new_i64();
2507 int bfa;
2508 int nibble;
2509 int shift;
2510
2511 if (unlikely(!ctx->fpu_enabled)) {
2512 gen_exception(ctx, POWERPC_EXCP_FPU);
2513 return;
2514 }
2515 bfa = crfS(ctx->opcode);
2516 nibble = 7 - bfa;
2517 shift = 4 * nibble;
2518 tcg_gen_shri_tl(tmp, cpu_fpscr, shift);
2519 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2520 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2521 tcg_temp_free(tmp);
2522 tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
2523 /* Only the exception bits (including FX) should be cleared if read */
2524 tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, ~((0xF << shift) & FP_EX_CLEAR_BITS));
2525 /* FEX and VX need to be updated, so don't set fpscr directly */
2526 tmask = tcg_const_i32(1 << nibble);
2527 gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
2528 tcg_temp_free_i32(tmask);
2529 tcg_temp_free_i64(tnew_fpscr);
2530 }
2531
2532 /* mffs */
2533 static void gen_mffs(DisasContext *ctx)
2534 {
2535 if (unlikely(!ctx->fpu_enabled)) {
2536 gen_exception(ctx, POWERPC_EXCP_FPU);
2537 return;
2538 }
2539 gen_reset_fpstatus();
2540 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2541 if (unlikely(Rc(ctx->opcode))) {
2542 gen_set_cr1_from_fpscr(ctx);
2543 }
2544 }
2545
2546 /* mtfsb0 */
2547 static void gen_mtfsb0(DisasContext *ctx)
2548 {
2549 uint8_t crb;
2550
2551 if (unlikely(!ctx->fpu_enabled)) {
2552 gen_exception(ctx, POWERPC_EXCP_FPU);
2553 return;
2554 }
2555 crb = 31 - crbD(ctx->opcode);
2556 gen_reset_fpstatus();
2557 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2558 TCGv_i32 t0;
2559 /* NIP cannot be restored if the memory exception comes from an helper */
2560 gen_update_nip(ctx, ctx->nip - 4);
2561 t0 = tcg_const_i32(crb);
2562 gen_helper_fpscr_clrbit(cpu_env, t0);
2563 tcg_temp_free_i32(t0);
2564 }
2565 if (unlikely(Rc(ctx->opcode) != 0)) {
2566 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2567 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2568 }
2569 }
2570
2571 /* mtfsb1 */
2572 static void gen_mtfsb1(DisasContext *ctx)
2573 {
2574 uint8_t crb;
2575
2576 if (unlikely(!ctx->fpu_enabled)) {
2577 gen_exception(ctx, POWERPC_EXCP_FPU);
2578 return;
2579 }
2580 crb = 31 - crbD(ctx->opcode);
2581 gen_reset_fpstatus();
2582 /* XXX: we pretend we can only do IEEE floating-point computations */
2583 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2584 TCGv_i32 t0;
2585 /* NIP cannot be restored if the memory exception comes from an helper */
2586 gen_update_nip(ctx, ctx->nip - 4);
2587 t0 = tcg_const_i32(crb);
2588 gen_helper_fpscr_setbit(cpu_env, t0);
2589 tcg_temp_free_i32(t0);
2590 }
2591 if (unlikely(Rc(ctx->opcode) != 0)) {
2592 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2593 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2594 }
2595 /* We can raise a differed exception */
2596 gen_helper_float_check_status(cpu_env);
2597 }
2598
2599 /* mtfsf */
2600 static void gen_mtfsf(DisasContext *ctx)
2601 {
2602 TCGv_i32 t0;
2603 int flm, l, w;
2604
2605 if (unlikely(!ctx->fpu_enabled)) {
2606 gen_exception(ctx, POWERPC_EXCP_FPU);
2607 return;
2608 }
2609 flm = FPFLM(ctx->opcode);
2610 l = FPL(ctx->opcode);
2611 w = FPW(ctx->opcode);
2612 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2613 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2614 return;
2615 }
2616 /* NIP cannot be restored if the memory exception comes from an helper */
2617 gen_update_nip(ctx, ctx->nip - 4);
2618 gen_reset_fpstatus();
2619 if (l) {
2620 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2621 } else {
2622 t0 = tcg_const_i32(flm << (w * 8));
2623 }
2624 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2625 tcg_temp_free_i32(t0);
2626 if (unlikely(Rc(ctx->opcode) != 0)) {
2627 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2628 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2629 }
2630 /* We can raise a differed exception */
2631 gen_helper_float_check_status(cpu_env);
2632 }
2633
2634 /* mtfsfi */
2635 static void gen_mtfsfi(DisasContext *ctx)
2636 {
2637 int bf, sh, w;
2638 TCGv_i64 t0;
2639 TCGv_i32 t1;
2640
2641 if (unlikely(!ctx->fpu_enabled)) {
2642 gen_exception(ctx, POWERPC_EXCP_FPU);
2643 return;
2644 }
2645 w = FPW(ctx->opcode);
2646 bf = FPBF(ctx->opcode);
2647 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2648 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2649 return;
2650 }
2651 sh = (8 * w) + 7 - bf;
2652 /* NIP cannot be restored if the memory exception comes from an helper */
2653 gen_update_nip(ctx, ctx->nip - 4);
2654 gen_reset_fpstatus();
2655 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2656 t1 = tcg_const_i32(1 << sh);
2657 gen_helper_store_fpscr(cpu_env, t0, t1);
2658 tcg_temp_free_i64(t0);
2659 tcg_temp_free_i32(t1);
2660 if (unlikely(Rc(ctx->opcode) != 0)) {
2661 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2662 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2663 }
2664 /* We can raise a differed exception */
2665 gen_helper_float_check_status(cpu_env);
2666 }
2667
2668 /*** Addressing modes ***/
2669 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2670 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2671 target_long maskl)
2672 {
2673 target_long simm = SIMM(ctx->opcode);
2674
2675 simm &= ~maskl;
2676 if (rA(ctx->opcode) == 0) {
2677 if (NARROW_MODE(ctx)) {
2678 simm = (uint32_t)simm;
2679 }
2680 tcg_gen_movi_tl(EA, simm);
2681 } else if (likely(simm != 0)) {
2682 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2683 if (NARROW_MODE(ctx)) {
2684 tcg_gen_ext32u_tl(EA, EA);
2685 }
2686 } else {
2687 if (NARROW_MODE(ctx)) {
2688 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2689 } else {
2690 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2691 }
2692 }
2693 }
2694
2695 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2696 {
2697 if (rA(ctx->opcode) == 0) {
2698 if (NARROW_MODE(ctx)) {
2699 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2700 } else {
2701 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2702 }
2703 } else {
2704 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2705 if (NARROW_MODE(ctx)) {
2706 tcg_gen_ext32u_tl(EA, EA);
2707 }
2708 }
2709 }
2710
2711 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2712 {
2713 if (rA(ctx->opcode) == 0) {
2714 tcg_gen_movi_tl(EA, 0);
2715 } else if (NARROW_MODE(ctx)) {
2716 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2717 } else {
2718 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2719 }
2720 }
2721
2722 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2723 target_long val)
2724 {
2725 tcg_gen_addi_tl(ret, arg1, val);
2726 if (NARROW_MODE(ctx)) {
2727 tcg_gen_ext32u_tl(ret, ret);
2728 }
2729 }
2730
2731 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2732 {
2733 TCGLabel *l1 = gen_new_label();
2734 TCGv t0 = tcg_temp_new();
2735 TCGv_i32 t1, t2;
2736 /* NIP cannot be restored if the memory exception comes from an helper */
2737 gen_update_nip(ctx, ctx->nip - 4);
2738 tcg_gen_andi_tl(t0, EA, mask);
2739 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2740 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2741 t2 = tcg_const_i32(0);
2742 gen_helper_raise_exception_err(cpu_env, t1, t2);
2743 tcg_temp_free_i32(t1);
2744 tcg_temp_free_i32(t2);
2745 gen_set_label(l1);
2746 tcg_temp_free(t0);
2747 }
2748
2749 /*** Integer load ***/
2750 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2751 {
2752 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2753 }
2754
2755 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2756 {
2757 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2758 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2759 }
2760
2761 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2762 {
2763 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2764 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2765 }
2766
2767 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2768 {
2769 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2770 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2771 }
2772
2773 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2774 {
2775 TCGv tmp = tcg_temp_new();
2776 gen_qemu_ld32u(ctx, tmp, addr);
2777 tcg_gen_extu_tl_i64(val, tmp);
2778 tcg_temp_free(tmp);
2779 }
2780
2781 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2782 {
2783 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2784 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2785 }
2786
2787 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2788 {
2789 TCGv tmp = tcg_temp_new();
2790 gen_qemu_ld32s(ctx, tmp, addr);
2791 tcg_gen_ext_tl_i64(val, tmp);
2792 tcg_temp_free(tmp);
2793 }
2794
2795 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2796 {
2797 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2798 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2799 }
2800
2801 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2802 {
2803 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2804 }
2805
2806 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2807 {
2808 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2809 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2810 }
2811
2812 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2813 {
2814 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2815 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2816 }
2817
2818 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2819 {
2820 TCGv tmp = tcg_temp_new();
2821 tcg_gen_trunc_i64_tl(tmp, val);
2822 gen_qemu_st32(ctx, tmp, addr);
2823 tcg_temp_free(tmp);
2824 }
2825
2826 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2827 {
2828 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2829 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2830 }
2831
2832 #define GEN_LD(name, ldop, opc, type) \
2833 static void glue(gen_, name)(DisasContext *ctx) \
2834 { \
2835 TCGv EA; \
2836 gen_set_access_type(ctx, ACCESS_INT); \
2837 EA = tcg_temp_new(); \
2838 gen_addr_imm_index(ctx, EA, 0); \
2839 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2840 tcg_temp_free(EA); \
2841 }
2842
2843 #define GEN_LDU(name, ldop, opc, type) \
2844 static void glue(gen_, name##u)(DisasContext *ctx) \
2845 { \
2846 TCGv EA; \
2847 if (unlikely(rA(ctx->opcode) == 0 || \
2848 rA(ctx->opcode) == rD(ctx->opcode))) { \
2849 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2850 return; \
2851 } \
2852 gen_set_access_type(ctx, ACCESS_INT); \
2853 EA = tcg_temp_new(); \
2854 if (type == PPC_64B) \
2855 gen_addr_imm_index(ctx, EA, 0x03); \
2856 else \
2857 gen_addr_imm_index(ctx, EA, 0); \
2858 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2859 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2860 tcg_temp_free(EA); \
2861 }
2862
2863 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2864 static void glue(gen_, name##ux)(DisasContext *ctx) \
2865 { \
2866 TCGv EA; \
2867 if (unlikely(rA(ctx->opcode) == 0 || \
2868 rA(ctx->opcode) == rD(ctx->opcode))) { \
2869 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2870 return; \
2871 } \
2872 gen_set_access_type(ctx, ACCESS_INT); \
2873 EA = tcg_temp_new(); \
2874 gen_addr_reg_index(ctx, EA); \
2875 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2876 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2877 tcg_temp_free(EA); \
2878 }
2879
2880 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2881 static void glue(gen_, name##x)(DisasContext *ctx) \
2882 { \
2883 TCGv EA; \
2884 gen_set_access_type(ctx, ACCESS_INT); \
2885 EA = tcg_temp_new(); \
2886 gen_addr_reg_index(ctx, EA); \
2887 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2888 tcg_temp_free(EA); \
2889 }
2890 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2891 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2892
2893 #define GEN_LDS(name, ldop, op, type) \
2894 GEN_LD(name, ldop, op | 0x20, type); \
2895 GEN_LDU(name, ldop, op | 0x21, type); \
2896 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2897 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2898
2899 /* lbz lbzu lbzux lbzx */
2900 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2901 /* lha lhau lhaux lhax */
2902 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2903 /* lhz lhzu lhzux lhzx */
2904 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2905 /* lwz lwzu lwzux lwzx */
2906 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2907 #if defined(TARGET_PPC64)
2908 /* lwaux */
2909 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2910 /* lwax */
2911 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2912 /* ldux */
2913 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2914 /* ldx */
2915 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2916
2917 static void gen_ld(DisasContext *ctx)
2918 {
2919 TCGv EA;
2920 if (Rc(ctx->opcode)) {
2921 if (unlikely(rA(ctx->opcode) == 0 ||
2922 rA(ctx->opcode) == rD(ctx->opcode))) {
2923 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2924 return;
2925 }
2926 }
2927 gen_set_access_type(ctx, ACCESS_INT);
2928 EA = tcg_temp_new();
2929 gen_addr_imm_index(ctx, EA, 0x03);
2930 if (ctx->opcode & 0x02) {
2931 /* lwa (lwau is undefined) */
2932 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2933 } else {
2934 /* ld - ldu */
2935 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2936 }
2937 if (Rc(ctx->opcode))
2938 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2939 tcg_temp_free(EA);
2940 }
2941
2942 /* lq */
2943 static void gen_lq(DisasContext *ctx)
2944 {
2945 int ra, rd;
2946 TCGv EA;
2947
2948 /* lq is a legal user mode instruction starting in ISA 2.07 */
2949 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2950 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2951
2952 if (!legal_in_user_mode && ctx->pr) {
2953 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2954 return;
2955 }
2956
2957 if (!le_is_supported && ctx->le_mode) {
2958 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2959 return;
2960 }
2961
2962 ra = rA(ctx->opcode);
2963 rd = rD(ctx->opcode);
2964 if (unlikely((rd & 1) || rd == ra)) {
2965 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2966 return;
2967 }
2968
2969 gen_set_access_type(ctx, ACCESS_INT);
2970 EA = tcg_temp_new();
2971 gen_addr_imm_index(ctx, EA, 0x0F);
2972
2973 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2974 64-bit byteswap already. */
2975 if (unlikely(ctx->le_mode)) {
2976 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2977 gen_addr_add(ctx, EA, EA, 8);
2978 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2979 } else {
2980 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2981 gen_addr_add(ctx, EA, EA, 8);
2982 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2983 }
2984 tcg_temp_free(EA);
2985 }
2986 #endif
2987
2988 /*** Integer store ***/
2989 #define GEN_ST(name, stop, opc, type) \
2990 static void glue(gen_, name)(DisasContext *ctx) \
2991 { \
2992 TCGv EA; \
2993 gen_set_access_type(ctx, ACCESS_INT); \
2994 EA = tcg_temp_new(); \
2995 gen_addr_imm_index(ctx, EA, 0); \
2996 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2997 tcg_temp_free(EA); \
2998 }
2999
3000 #define GEN_STU(name, stop, opc, type) \
3001 static void glue(gen_, stop##u)(DisasContext *ctx) \
3002 { \
3003 TCGv EA; \
3004 if (unlikely(rA(ctx->opcode) == 0)) { \
3005 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3006 return; \
3007 } \
3008 gen_set_access_type(ctx, ACCESS_INT); \
3009 EA = tcg_temp_new(); \
3010 if (type == PPC_64B) \
3011 gen_addr_imm_index(ctx, EA, 0x03); \
3012 else \
3013 gen_addr_imm_index(ctx, EA, 0); \
3014 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3015 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3016 tcg_temp_free(EA); \
3017 }
3018
3019 #define GEN_STUX(name, stop, opc2, opc3, type) \
3020 static void glue(gen_, name##ux)(DisasContext *ctx) \
3021 { \
3022 TCGv EA; \
3023 if (unlikely(rA(ctx->opcode) == 0)) { \
3024 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3025 return; \
3026 } \
3027 gen_set_access_type(ctx, ACCESS_INT); \
3028 EA = tcg_temp_new(); \
3029 gen_addr_reg_index(ctx, EA); \
3030 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3031 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3032 tcg_temp_free(EA); \
3033 }
3034
3035 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
3036 static void glue(gen_, name##x)(DisasContext *ctx) \
3037 { \
3038 TCGv EA; \
3039 gen_set_access_type(ctx, ACCESS_INT); \
3040 EA = tcg_temp_new(); \
3041 gen_addr_reg_index(ctx, EA); \
3042 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3043 tcg_temp_free(EA); \
3044 }
3045 #define GEN_STX(name, stop, opc2, opc3, type) \
3046 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
3047
3048 #define GEN_STS(name, stop, op, type) \
3049 GEN_ST(name, stop, op | 0x20, type); \
3050 GEN_STU(name, stop, op | 0x21, type); \
3051 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3052 GEN_STX(name, stop, 0x17, op | 0x00, type)
3053
3054 /* stb stbu stbux stbx */
3055 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3056 /* sth sthu sthux sthx */
3057 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3058 /* stw stwu stwux stwx */
3059 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3060 #if defined(TARGET_PPC64)
3061 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3062 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
3063
3064 static void gen_std(DisasContext *ctx)
3065 {
3066 int rs;
3067 TCGv EA;
3068
3069 rs = rS(ctx->opcode);
3070 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3071
3072 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3073 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3074
3075 if (!legal_in_user_mode && ctx->pr) {
3076 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3077 return;
3078 }
3079
3080 if (!le_is_supported && ctx->le_mode) {
3081 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3082 return;
3083 }
3084
3085 if (unlikely(rs & 1)) {
3086 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3087 return;
3088 }
3089 gen_set_access_type(ctx, ACCESS_INT);
3090 EA = tcg_temp_new();
3091 gen_addr_imm_index(ctx, EA, 0x03);
3092
3093 /* We only need to swap high and low halves. gen_qemu_st64 does
3094 necessary 64-bit byteswap already. */
3095 if (unlikely(ctx->le_mode)) {
3096 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3097 gen_addr_add(ctx, EA, EA, 8);
3098 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3099 } else {
3100 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3101 gen_addr_add(ctx, EA, EA, 8);
3102 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3103 }
3104 tcg_temp_free(EA);
3105 } else {
3106 /* std / stdu*/
3107 if (Rc(ctx->opcode)) {
3108 if (unlikely(rA(ctx->opcode) == 0)) {
3109 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3110 return;
3111 }
3112 }
3113 gen_set_access_type(ctx, ACCESS_INT);
3114 EA = tcg_temp_new();
3115 gen_addr_imm_index(ctx, EA, 0x03);
3116 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3117 if (Rc(ctx->opcode))
3118 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3119 tcg_temp_free(EA);
3120 }
3121 }
3122 #endif
3123 /*** Integer load and store with byte reverse ***/
3124
3125 /* lhbrx */
3126 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3127 {
3128 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3129 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3130 }
3131 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3132
3133 /* lwbrx */
3134 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3135 {
3136 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3137 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3138 }
3139 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3140
3141 #if defined(TARGET_PPC64)
3142 /* ldbrx */
3143 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3144 {
3145 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3146 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3147 }
3148 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3149 #endif /* TARGET_PPC64 */
3150
3151 /* sthbrx */
3152 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3153 {
3154 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3155 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3156 }
3157 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3158
3159 /* stwbrx */
3160 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3161 {
3162 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3163 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3164 }
3165 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3166
3167 #if defined(TARGET_PPC64)
3168 /* stdbrx */
3169 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3170 {
3171 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3172 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3173 }
3174 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3175 #endif /* TARGET_PPC64 */
3176
3177 /*** Integer load and store multiple ***/
3178
3179 /* lmw */
3180 static void gen_lmw(DisasContext *ctx)
3181 {
3182 TCGv t0;
3183 TCGv_i32 t1;
3184 gen_set_access_type(ctx, ACCESS_INT);
3185 /* NIP cannot be restored if the memory exception comes from an helper */
3186 gen_update_nip(ctx, ctx->nip - 4);
3187 t0 = tcg_temp_new();
3188 t1 = tcg_const_i32(rD(ctx->opcode));
3189 gen_addr_imm_index(ctx, t0, 0);
3190 gen_helper_lmw(cpu_env, t0, t1);
3191 tcg_temp_free(t0);
3192 tcg_temp_free_i32(t1);
3193 }
3194
3195 /* stmw */
3196 static void gen_stmw(DisasContext *ctx)
3197 {
3198 TCGv t0;
3199 TCGv_i32 t1;
3200 gen_set_access_type(ctx, ACCESS_INT);
3201 /* NIP cannot be restored if the memory exception comes from an helper */
3202 gen_update_nip(ctx, ctx->nip - 4);
3203 t0 = tcg_temp_new();
3204 t1 = tcg_const_i32(rS(ctx->opcode));
3205 gen_addr_imm_index(ctx, t0, 0);
3206 gen_helper_stmw(cpu_env, t0, t1);
3207 tcg_temp_free(t0);
3208 tcg_temp_free_i32(t1);
3209 }
3210
3211 /*** Integer load and store strings ***/
3212
3213 /* lswi */
3214 /* PowerPC32 specification says we must generate an exception if
3215 * rA is in the range of registers to be loaded.
3216 * In an other hand, IBM says this is valid, but rA won't be loaded.
3217 * For now, I'll follow the spec...
3218 */
3219 static void gen_lswi(DisasContext *ctx)
3220 {
3221 TCGv t0;
3222 TCGv_i32 t1, t2;
3223 int nb = NB(ctx->opcode);
3224 int start = rD(ctx->opcode);
3225 int ra = rA(ctx->opcode);
3226 int nr;
3227
3228 if (nb == 0)
3229 nb = 32;
3230 nr = nb / 4;
3231 if (unlikely(((start + nr) > 32 &&
3232 start <= ra && (start + nr - 32) > ra) ||
3233 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3234 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3235 return;
3236 }
3237 gen_set_access_type(ctx, ACCESS_INT);
3238 /* NIP cannot be restored if the memory exception comes from an helper */
3239 gen_update_nip(ctx, ctx->nip - 4);
3240 t0 = tcg_temp_new();
3241 gen_addr_register(ctx, t0);
3242 t1 = tcg_const_i32(nb);
3243 t2 = tcg_const_i32(start);
3244 gen_helper_lsw(cpu_env, t0, t1, t2);
3245 tcg_temp_free(t0);
3246 tcg_temp_free_i32(t1);
3247 tcg_temp_free_i32(t2);
3248 }
3249
3250 /* lswx */
3251 static void gen_lswx(DisasContext *ctx)
3252 {
3253 TCGv t0;
3254 TCGv_i32 t1, t2, t3;
3255 gen_set_access_type(ctx, ACCESS_INT);
3256 /* NIP cannot be restored if the memory exception comes from an helper */
3257 gen_update_nip(ctx, ctx->nip - 4);
3258 t0 = tcg_temp_new();
3259 gen_addr_reg_index(ctx, t0);
3260 t1 = tcg_const_i32(rD(ctx->opcode));
3261 t2 = tcg_const_i32(rA(ctx->opcode));
3262 t3 = tcg_const_i32(rB(ctx->opcode));
3263 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3264 tcg_temp_free(t0);
3265 tcg_temp_free_i32(t1);
3266 tcg_temp_free_i32(t2);
3267 tcg_temp_free_i32(t3);
3268 }
3269
3270 /* stswi */
3271 static void gen_stswi(DisasContext *ctx)
3272 {
3273 TCGv t0;
3274 TCGv_i32 t1, t2;
3275 int nb = NB(ctx->opcode);
3276 gen_set_access_type(ctx, ACCESS_INT);
3277 /* NIP cannot be restored if the memory exception comes from an helper */
3278 gen_update_nip(ctx, ctx->nip - 4);
3279 t0 = tcg_temp_new();
3280 gen_addr_register(ctx, t0);
3281 if (nb == 0)
3282 nb = 32;
3283 t1 = tcg_const_i32(nb);
3284 t2 = tcg_const_i32(rS(ctx->opcode));
3285 gen_helper_stsw(cpu_env, t0, t1, t2);
3286 tcg_temp_free(t0);
3287 tcg_temp_free_i32(t1);
3288 tcg_temp_free_i32(t2);
3289 }
3290
3291 /* stswx */
3292 static void gen_stswx(DisasContext *ctx)
3293 {
3294 TCGv t0;
3295 TCGv_i32 t1, t2;
3296 gen_set_access_type(ctx, ACCESS_INT);
3297 /* NIP cannot be restored if the memory exception comes from an helper */
3298 gen_update_nip(ctx, ctx->nip - 4);
3299 t0 = tcg_temp_new();
3300 gen_addr_reg_index(ctx, t0);
3301 t1 = tcg_temp_new_i32();
3302 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3303 tcg_gen_andi_i32(t1, t1, 0x7F);
3304 t2 = tcg_const_i32(rS(ctx->opcode));
3305 gen_helper_stsw(cpu_env, t0, t1, t2);
3306 tcg_temp_free(t0);
3307 tcg_temp_free_i32(t1);
3308 tcg_temp_free_i32(t2);
3309 }
3310
3311 /*** Memory synchronisation ***/
3312 /* eieio */
3313 static void gen_eieio(DisasContext *ctx)
3314 {
3315 }
3316
3317 /* isync */
3318 static void gen_isync(DisasContext *ctx)
3319 {
3320 gen_stop_exception(ctx);
3321 }
3322
3323 #define LARX(name, len, loadop) \
3324 static void gen_##name(DisasContext *ctx) \
3325 { \
3326 TCGv t0; \
3327 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3328 gen_set_access_type(ctx, ACCESS_RES); \
3329 t0 = tcg_temp_local_new(); \
3330 gen_addr_reg_index(ctx, t0); \
3331 if ((len) > 1) { \
3332 gen_check_align(ctx, t0, (len)-1); \
3333 } \
3334 gen_qemu_##loadop(ctx, gpr, t0); \
3335 tcg_gen_mov_tl(cpu_reserve, t0); \
3336 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3337 tcg_temp_free(t0); \
3338 }
3339
3340 /* lwarx */
3341 LARX(lbarx, 1, ld8u);
3342 LARX(lharx, 2, ld16u);
3343 LARX(lwarx, 4, ld32u);
3344
3345
3346 #if defined(CONFIG_USER_ONLY)
3347 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3348 int reg, int size)
3349 {
3350 TCGv t0 = tcg_temp_new();
3351 uint32_t save_exception = ctx->exception;
3352
3353 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3354 tcg_gen_movi_tl(t0, (size << 5) | reg);
3355 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3356 tcg_temp_free(t0);
3357 gen_update_nip(ctx, ctx->nip-4);
3358 ctx->exception = POWERPC_EXCP_BRANCH;
3359 gen_exception(ctx, POWERPC_EXCP_STCX);
3360 ctx->exception = save_exception;
3361 }
3362 #else
3363 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3364 int reg, int size)
3365 {
3366 TCGLabel *l1;
3367
3368 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3369 l1 = gen_new_label();
3370 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3371 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3372 #if defined(TARGET_PPC64)
3373 if (size == 8) {
3374 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3375 } else
3376 #endif
3377 if (size == 4) {
3378 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3379 } else if (size == 2) {
3380 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3381 #if defined(TARGET_PPC64)
3382 } else if (size == 16) {
3383 TCGv gpr1, gpr2 , EA8;
3384 if (unlikely(ctx->le_mode)) {
3385 gpr1 = cpu_gpr[reg+1];
3386 gpr2 = cpu_gpr[reg];
3387 } else {
3388 gpr1 = cpu_gpr[reg];
3389 gpr2 = cpu_gpr[reg+1];
3390 }
3391 gen_qemu_st64(ctx, gpr1, EA);
3392 EA8 = tcg_temp_local_new();
3393 gen_addr_add(ctx, EA8, EA, 8);
3394 gen_qemu_st64(ctx, gpr2, EA8);
3395 tcg_temp_free(EA8);
3396 #endif
3397 } else {
3398 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3399 }
3400 gen_set_label(l1);
3401 tcg_gen_movi_tl(cpu_reserve, -1);
3402 }
3403 #endif
3404
3405 #define STCX(name, len) \
3406 static void gen_##name(DisasContext *ctx) \
3407 { \
3408 TCGv t0; \
3409 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3410 gen_inval_exception(ctx, \
3411 POWERPC_EXCP_INVAL_INVAL); \
3412 return; \
3413 } \
3414 gen_set_access_type(ctx, ACCESS_RES); \
3415 t0 = tcg_temp_local_new(); \
3416 gen_addr_reg_index(ctx, t0); \
3417 if (len > 1) { \
3418 gen_check_align(ctx, t0, (len)-1); \
3419 } \
3420 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3421 tcg_temp_free(t0); \
3422 }
3423
3424 STCX(stbcx_, 1);
3425 STCX(sthcx_, 2);
3426 STCX(stwcx_, 4);
3427
3428 #if defined(TARGET_PPC64)
3429 /* ldarx */
3430 LARX(ldarx, 8, ld64);
3431
3432 /* lqarx */
3433 static void gen_lqarx(DisasContext *ctx)
3434 {
3435 TCGv EA;
3436 int rd = rD(ctx->opcode);
3437 TCGv gpr1, gpr2;
3438
3439 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3440 (rd == rB(ctx->opcode)))) {
3441 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3442 return;
3443 }
3444
3445 gen_set_access_type(ctx, ACCESS_RES);
3446 EA = tcg_temp_local_new();
3447 gen_addr_reg_index(ctx, EA);
3448 gen_check_align(ctx, EA, 15);
3449 if (unlikely(ctx->le_mode)) {
3450 gpr1 = cpu_gpr[rd+1];
3451 gpr2 = cpu_gpr[rd];
3452 } else {
3453 gpr1 = cpu_gpr[rd];
3454 gpr2 = cpu_gpr[rd+1];
3455 }
3456 gen_qemu_ld64(ctx, gpr1, EA);
3457 tcg_gen_mov_tl(cpu_reserve, EA);
3458
3459 gen_addr_add(ctx, EA, EA, 8);
3460 gen_qemu_ld64(ctx, gpr2, EA);
3461
3462 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3463 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3464
3465 tcg_temp_free(EA);
3466 }
3467
3468 /* stdcx. */
3469 STCX(stdcx_, 8);
3470 STCX(stqcx_, 16);
3471 #endif /* defined(TARGET_PPC64) */
3472
3473 /* sync */
3474 static void gen_sync(DisasContext *ctx)
3475 {
3476 }
3477
3478 /* wait */
3479 static void gen_wait(DisasContext *ctx)
3480 {
3481 TCGv_i32 t0 = tcg_temp_new_i32();
3482 tcg_gen_st_i32(t0, cpu_env,
3483 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3484 tcg_temp_free_i32(t0);
3485 /* Stop translation, as the CPU is supposed to sleep from now */
3486 gen_exception_err(ctx, EXCP_HLT, 1);
3487 }
3488
3489 /*** Floating-point load ***/
3490 #define GEN_LDF(name, ldop, opc, type) \
3491 static void glue(gen_, name)(DisasContext *ctx) \
3492 { \
3493 TCGv EA; \
3494 if (unlikely(!ctx->fpu_enabled)) { \
3495 gen_exception(ctx, POWERPC_EXCP_FPU); \
3496 return; \
3497 } \
3498 gen_set_access_type(ctx, ACCESS_FLOAT); \
3499 EA = tcg_temp_new(); \
3500 gen_addr_imm_index(ctx, EA, 0); \
3501 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3502 tcg_temp_free(EA); \
3503 }
3504
3505 #define GEN_LDUF(name, ldop, opc, type) \
3506 static void glue(gen_, name##u)(DisasContext *ctx) \
3507 { \
3508 TCGv EA; \
3509 if (unlikely(!ctx->fpu_enabled)) { \
3510 gen_exception(ctx, POWERPC_EXCP_FPU); \
3511 return; \
3512 } \
3513 if (unlikely(rA(ctx->opcode) == 0)) { \
3514 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3515 return; \
3516 } \
3517 gen_set_access_type(ctx, ACCESS_FLOAT); \
3518 EA = tcg_temp_new(); \
3519 gen_addr_imm_index(ctx, EA, 0); \
3520 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3521 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3522 tcg_temp_free(EA); \
3523 }
3524
3525 #define GEN_LDUXF(name, ldop, opc, type) \
3526 static void glue(gen_, name##ux)(DisasContext *ctx) \
3527 { \
3528 TCGv EA; \
3529 if (unlikely(!ctx->fpu_enabled)) { \
3530 gen_exception(ctx, POWERPC_EXCP_FPU); \
3531 return; \
3532 } \
3533 if (unlikely(rA(ctx->opcode) == 0)) { \
3534 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3535 return; \
3536 } \
3537 gen_set_access_type(ctx, ACCESS_FLOAT); \
3538 EA = tcg_temp_new(); \
3539 gen_addr_reg_index(ctx, EA); \
3540 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3541 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3542 tcg_temp_free(EA); \
3543 }
3544
3545 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3546 static void glue(gen_, name##x)(DisasContext *ctx) \
3547 { \
3548 TCGv EA; \
3549 if (unlikely(!ctx->fpu_enabled)) { \
3550 gen_exception(ctx, POWERPC_EXCP_FPU); \
3551 return; \
3552 } \
3553 gen_set_access_type(ctx, ACCESS_FLOAT); \
3554 EA = tcg_temp_new(); \
3555 gen_addr_reg_index(ctx, EA); \
3556 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3557 tcg_temp_free(EA); \
3558 }
3559
3560 #define GEN_LDFS(name, ldop, op, type) \
3561 GEN_LDF(name, ldop, op | 0x20, type); \
3562 GEN_LDUF(name, ldop, op | 0x21, type); \
3563 GEN_LDUXF(name, ldop, op | 0x01, type); \
3564 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3565
3566 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3567 {
3568 TCGv t0 = tcg_temp_new();
3569 TCGv_i32 t1 = tcg_temp_new_i32();
3570 gen_qemu_ld32u(ctx, t0, arg2);
3571 tcg_gen_trunc_tl_i32(t1, t0);
3572 tcg_temp_free(t0);
3573 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3574 tcg_temp_free_i32(t1);
3575 }
3576
3577 /* lfd lfdu lfdux lfdx */
3578 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3579 /* lfs lfsu lfsux lfsx */
3580 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3581
3582 /* lfdp */
3583 static void gen_lfdp(DisasContext *ctx)
3584 {
3585 TCGv EA;
3586 if (unlikely(!ctx->fpu_enabled)) {
3587 gen_exception(ctx, POWERPC_EXCP_FPU);
3588 return;
3589 }
3590 gen_set_access_type(ctx, ACCESS_FLOAT);
3591 EA = tcg_temp_new();
3592 gen_addr_imm_index(ctx, EA, 0);
3593 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3594 64-bit byteswap already. */
3595 if (unlikely(ctx->le_mode)) {
3596 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3597 tcg_gen_addi_tl(EA, EA, 8);
3598 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3599 } else {
3600 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3601 tcg_gen_addi_tl(EA, EA, 8);
3602 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3603 }
3604 tcg_temp_free(EA);
3605 }
3606
3607 /* lfdpx */
3608 static void gen_lfdpx(DisasContext *ctx)
3609 {
3610 TCGv EA;
3611 if (unlikely(!ctx->fpu_enabled)) {
3612 gen_exception(ctx, POWERPC_EXCP_FPU);
3613 return;
3614 }
3615 gen_set_access_type(ctx, ACCESS_FLOAT);
3616 EA = tcg_temp_new();
3617 gen_addr_reg_index(ctx, EA);
3618 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3619 64-bit byteswap already. */
3620 if (unlikely(ctx->le_mode)) {
3621 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3622 tcg_gen_addi_tl(EA, EA, 8);
3623 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3624 } else {
3625 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3626 tcg_gen_addi_tl(EA, EA, 8);
3627 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3628 }
3629 tcg_temp_free(EA);
3630 }
3631
3632 /* lfiwax */
3633 static void gen_lfiwax(DisasContext *ctx)
3634 {
3635 TCGv EA;
3636 TCGv t0;
3637 if (unlikely(!ctx->fpu_enabled)) {
3638 gen_exception(ctx, POWERPC_EXCP_FPU);
3639 return;
3640 }
3641 gen_set_access_type(ctx, ACCESS_FLOAT);
3642 EA = tcg_temp_new();
3643 t0 = tcg_temp_new();
3644 gen_addr_reg_index(ctx, EA);
3645 gen_qemu_ld32s(ctx, t0, EA);
3646 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3647 tcg_temp_free(EA);
3648 tcg_temp_free(t0);
3649 }
3650
3651 /* lfiwzx */
3652 static void gen_lfiwzx(DisasContext *ctx)
3653 {
3654 TCGv EA;
3655 if (unlikely(!ctx->fpu_enabled)) {
3656 gen_exception(ctx, POWERPC_EXCP_FPU);
3657 return;
3658 }
3659 gen_set_access_type(ctx, ACCESS_FLOAT);
3660 EA = tcg_temp_new();
3661 gen_addr_reg_index(ctx, EA);
3662 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3663 tcg_temp_free(EA);
3664 }
3665 /*** Floating-point store ***/
3666 #define GEN_STF(name, stop, opc, type) \
3667 static void glue(gen_, name)(DisasContext *ctx) \
3668 { \
3669 TCGv EA; \
3670 if (unlikely(!ctx->fpu_enabled)) { \
3671 gen_exception(ctx, POWERPC_EXCP_FPU); \
3672 return; \
3673 } \
3674 gen_set_access_type(ctx, ACCESS_FLOAT); \
3675 EA = tcg_temp_new(); \
3676 gen_addr_imm_index(ctx, EA, 0); \
3677 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3678 tcg_temp_free(EA); \
3679 }
3680
3681 #define GEN_STUF(name, stop, opc, type) \
3682 static void glue(gen_, name##u)(DisasContext *ctx) \
3683 { \
3684 TCGv EA; \
3685 if (unlikely(!ctx->fpu_enabled)) { \
3686 gen_exception(ctx, POWERPC_EXCP_FPU); \
3687 return; \
3688 } \
3689 if (unlikely(rA(ctx->opcode) == 0)) { \
3690 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3691 return; \
3692 } \
3693 gen_set_access_type(ctx, ACCESS_FLOAT); \
3694 EA = tcg_temp_new(); \
3695 gen_addr_imm_index(ctx, EA, 0); \
3696 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3697 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3698 tcg_temp_free(EA); \
3699 }
3700
3701 #define GEN_STUXF(name, stop, opc, type) \
3702 static void glue(gen_, name##ux)(DisasContext *ctx) \
3703 { \
3704 TCGv EA; \
3705 if (unlikely(!ctx->fpu_enabled)) { \
3706 gen_exception(ctx, POWERPC_EXCP_FPU); \
3707 return; \
3708 } \
3709 if (unlikely(rA(ctx->opcode) == 0)) { \
3710 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3711 return; \
3712 } \
3713 gen_set_access_type(ctx, ACCESS_FLOAT); \
3714 EA = tcg_temp_new(); \
3715 gen_addr_reg_index(ctx, EA); \
3716 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3717 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3718 tcg_temp_free(EA); \
3719 }
3720
3721 #define GEN_STXF(name, stop, opc2, opc3, type) \
3722 static void glue(gen_, name##x)(DisasContext *ctx) \
3723 { \
3724 TCGv EA; \
3725 if (unlikely(!ctx->fpu_enabled)) { \
3726 gen_exception(ctx, POWERPC_EXCP_FPU); \
3727 return; \
3728 } \
3729 gen_set_access_type(ctx, ACCESS_FLOAT); \
3730 EA = tcg_temp_new(); \
3731 gen_addr_reg_index(ctx, EA); \
3732 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3733 tcg_temp_free(EA); \
3734 }
3735
3736 #define GEN_STFS(name, stop, op, type) \
3737 GEN_STF(name, stop, op | 0x20, type); \
3738 GEN_STUF(name, stop, op | 0x21, type); \
3739 GEN_STUXF(name, stop, op | 0x01, type); \
3740 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3741
3742 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3743 {
3744 TCGv_i32 t0 = tcg_temp_new_i32();
3745 TCGv t1 = tcg_temp_new();
3746 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3747 tcg_gen_extu_i32_tl(t1, t0);
3748 tcg_temp_free_i32(t0);
3749 gen_qemu_st32(ctx, t1, arg2);
3750 tcg_temp_free(t1);
3751 }
3752
3753 /* stfd stfdu stfdux stfdx */
3754 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3755 /* stfs stfsu stfsux stfsx */
3756 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3757
3758 /* stfdp */
3759 static void gen_stfdp(DisasContext *ctx)
3760 {
3761 TCGv EA;
3762 if (unlikely(!ctx->fpu_enabled)) {
3763 gen_exception(ctx, POWERPC_EXCP_FPU);
3764 return;
3765 }
3766 gen_set_access_type(ctx, ACCESS_FLOAT);
3767 EA = tcg_temp_new();
3768 gen_addr_imm_index(ctx, EA, 0);
3769 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3770 64-bit byteswap already. */
3771 if (unlikely(ctx->le_mode)) {
3772 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3773 tcg_gen_addi_tl(EA, EA, 8);
3774 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3775 } else {
3776 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3777 tcg_gen_addi_tl(EA, EA, 8);
3778 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3779 }
3780 tcg_temp_free(EA);
3781 }
3782
3783 /* stfdpx */
3784 static void gen_stfdpx(DisasContext *ctx)
3785 {
3786 TCGv EA;
3787 if (unlikely(!ctx->fpu_enabled)) {
3788 gen_exception(ctx, POWERPC_EXCP_FPU);
3789 return;
3790 }
3791 gen_set_access_type(ctx, ACCESS_FLOAT);
3792 EA = tcg_temp_new();
3793 gen_addr_reg_index(ctx, EA);
3794 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3795 64-bit byteswap already. */
3796 if (unlikely(ctx->le_mode)) {
3797 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3798 tcg_gen_addi_tl(EA, EA, 8);
3799 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3800 } else {
3801 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3802 tcg_gen_addi_tl(EA, EA, 8);
3803 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3804 }
3805 tcg_temp_free(EA);
3806 }
3807
3808 /* Optional: */
3809 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3810 {
3811 TCGv t0 = tcg_temp_new();
3812 tcg_gen_trunc_i64_tl(t0, arg1),
3813 gen_qemu_st32(ctx, t0, arg2);
3814 tcg_temp_free(t0);
3815 }
3816 /* stfiwx */
3817 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3818
3819 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3820 {
3821 #if defined(TARGET_PPC64)
3822 if (ctx->has_cfar)
3823 tcg_gen_movi_tl(cpu_cfar, nip);
3824 #endif
3825 }
3826
3827 /*** Branch ***/
3828 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3829 {
3830 TranslationBlock *tb;
3831 tb = ctx->tb;
3832 if (NARROW_MODE(ctx)) {
3833 dest = (uint32_t) dest;
3834 }
3835 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3836 likely(!ctx->singlestep_enabled)) {
3837 tcg_gen_goto_tb(n);
3838 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3839 tcg_gen_exit_tb((uintptr_t)tb + n);
3840 } else {
3841 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3842 if (unlikely(ctx->singlestep_enabled)) {
3843 if ((ctx->singlestep_enabled &
3844 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3845 (ctx->exception == POWERPC_EXCP_BRANCH ||
3846 ctx->exception == POWERPC_EXCP_TRACE)) {
3847 target_ulong tmp = ctx->nip;
3848 ctx->nip = dest;
3849 gen_exception(ctx, POWERPC_EXCP_TRACE);
3850 ctx->nip = tmp;
3851 }
3852 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3853 gen_debug_exception(ctx);
3854 }
3855 }
3856 tcg_gen_exit_tb(0);
3857 }
3858 }
3859
3860 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3861 {
3862 if (NARROW_MODE(ctx)) {
3863 nip = (uint32_t)nip;
3864 }
3865 tcg_gen_movi_tl(cpu_lr, nip);
3866 }
3867
3868 /* b ba bl bla */
3869 static void gen_b(DisasContext *ctx)
3870 {
3871 target_ulong li, target;
3872
3873 ctx->exception = POWERPC_EXCP_BRANCH;
3874 /* sign extend LI */
3875 li = LI(ctx->opcode);
3876 li = (li ^ 0x02000000) - 0x02000000;
3877 if (likely(AA(ctx->opcode) == 0)) {
3878 target = ctx->nip + li - 4;
3879 } else {
3880 target = li;
3881 }
3882 if (LK(ctx->opcode)) {
3883 gen_setlr(ctx, ctx->nip);
3884 }
3885 gen_update_cfar(ctx, ctx->nip);
3886 gen_goto_tb(ctx, 0, target);
3887 }
3888
3889 #define BCOND_IM 0
3890 #define BCOND_LR 1
3891 #define BCOND_CTR 2
3892 #define BCOND_TAR 3
3893
3894 static inline void gen_bcond(DisasContext *ctx, int type)
3895 {
3896 uint32_t bo = BO(ctx->opcode);
3897 TCGLabel *l1;
3898 TCGv target;
3899
3900 ctx->exception = POWERPC_EXCP_BRANCH;
3901 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3902 target = tcg_temp_local_new();
3903 if (type == BCOND_CTR)
3904 tcg_gen_mov_tl(target, cpu_ctr);
3905 else if (type == BCOND_TAR)
3906 gen_load_spr(target, SPR_TAR);
3907 else
3908 tcg_gen_mov_tl(target, cpu_lr);
3909 } else {
3910 TCGV_UNUSED(target);
3911 }
3912 if (LK(ctx->opcode))
3913 gen_setlr(ctx, ctx->nip);
3914 l1 = gen_new_label();
3915 if ((bo & 0x4) == 0) {
3916 /* Decrement and test CTR */
3917 TCGv temp = tcg_temp_new();
3918 if (unlikely(type == BCOND_CTR)) {
3919 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3920 return;
3921 }
3922 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3923 if (NARROW_MODE(ctx)) {
3924 tcg_gen_ext32u_tl(temp, cpu_ctr);
3925 } else {
3926 tcg_gen_mov_tl(temp, cpu_ctr);
3927 }
3928 if (bo & 0x2) {
3929 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3930 } else {
3931 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3932 }
3933 tcg_temp_free(temp);
3934 }
3935 if ((bo & 0x10) == 0) {
3936 /* Test CR */
3937 uint32_t bi = BI(ctx->opcode);
3938 uint32_t mask = 0x08 >> (bi & 0x03);
3939 TCGv_i32 temp = tcg_temp_new_i32();
3940
3941 if (bo & 0x8) {
3942 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3943 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3944 } else {
3945 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3946 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3947 }
3948 tcg_temp_free_i32(temp);
3949 }
3950 gen_update_cfar(ctx, ctx->nip);
3951 if (type == BCOND_IM) {
3952 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3953 if (likely(AA(ctx->opcode) == 0)) {
3954 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3955 } else {
3956 gen_goto_tb(ctx, 0, li);
3957 }
3958 gen_set_label(l1);
3959 gen_goto_tb(ctx, 1, ctx->nip);
3960 } else {
3961 if (NARROW_MODE(ctx)) {
3962 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3963 } else {
3964 tcg_gen_andi_tl(cpu_nip, target, ~3);
3965 }
3966 tcg_gen_exit_tb(0);
3967 gen_set_label(l1);
3968 gen_update_nip(ctx, ctx->nip);
3969 tcg_gen_exit_tb(0);
3970 }
3971 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3972 tcg_temp_free(target);
3973 }
3974 }
3975
3976 static void gen_bc(DisasContext *ctx)
3977 {
3978 gen_bcond(ctx, BCOND_IM);
3979 }
3980
3981 static void gen_bcctr(DisasContext *ctx)
3982 {
3983 gen_bcond(ctx, BCOND_CTR);
3984 }
3985
3986 static void gen_bclr(DisasContext *ctx)
3987 {
3988 gen_bcond(ctx, BCOND_LR);
3989 }
3990
3991 static void gen_bctar(DisasContext *ctx)
3992 {
3993 gen_bcond(ctx, BCOND_TAR);
3994 }
3995
3996 /*** Condition register logical ***/
3997 #define GEN_CRLOGIC(name, tcg_op, opc) \
3998 static void glue(gen_, name)(DisasContext *ctx) \
3999 { \
4000 uint8_t bitmask; \
4001 int sh; \
4002 TCGv_i32 t0, t1; \
4003 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
4004 t0 = tcg_temp_new_i32(); \
4005 if (sh > 0) \
4006 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
4007 else if (sh < 0) \
4008 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
4009 else \
4010 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
4011 t1 = tcg_temp_new_i32(); \
4012 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4013 if (sh > 0) \
4014 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4015 else if (sh < 0) \
4016 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4017 else \
4018 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4019 tcg_op(t0, t0, t1); \
4020 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4021 tcg_gen_andi_i32(t0, t0, bitmask); \
4022 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4023 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4024 tcg_temp_free_i32(t0); \
4025 tcg_temp_free_i32(t1); \
4026 }
4027
4028 /* crand */
4029 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4030 /* crandc */
4031 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4032 /* creqv */
4033 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4034 /* crnand */
4035 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4036 /* crnor */
4037 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
4038 /* cror */
4039 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
4040 /* crorc */
4041 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
4042 /* crxor */
4043 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
4044
4045 /* mcrf */
4046 static void gen_mcrf(DisasContext *ctx)
4047 {
4048 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4049 }
4050
4051 /*** System linkage ***/
4052
4053 /* rfi (supervisor only) */
4054 static void gen_rfi(DisasContext *ctx)
4055 {
4056 #if defined(CONFIG_USER_ONLY)
4057 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4058 #else
4059 /* Restore CPU state */
4060 if (unlikely(ctx->pr)) {
4061 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4062 return;
4063 }
4064 gen_update_cfar(ctx, ctx->nip);
4065 gen_helper_rfi(cpu_env);
4066 gen_sync_exception(ctx);
4067 #endif
4068 }
4069
4070 #if defined(TARGET_PPC64)
4071 static void gen_rfid(DisasContext *ctx)
4072 {
4073 #if defined(CONFIG_USER_ONLY)
4074 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4075 #else
4076 /* Restore CPU state */
4077 if (unlikely(ctx->pr)) {
4078 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4079 return;
4080 }
4081 gen_update_cfar(ctx, ctx->nip);
4082 gen_helper_rfid(cpu_env);
4083 gen_sync_exception(ctx);
4084 #endif
4085 }
4086
4087 static void gen_hrfid(DisasContext *ctx)
4088 {
4089 #if defined(CONFIG_USER_ONLY)
4090 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4091 #else
4092 /* Restore CPU state */
4093 if (unlikely(!ctx->hv)) {
4094 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4095 return;
4096 }
4097 gen_helper_hrfid(cpu_env);
4098 gen_sync_exception(ctx);
4099 #endif
4100 }
4101 #endif
4102
4103 /* sc */
4104 #if defined(CONFIG_USER_ONLY)
4105 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4106 #else
4107 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4108 #endif
4109 static void gen_sc(DisasContext *ctx)
4110 {
4111 uint32_t lev;
4112
4113 lev = (ctx->opcode >> 5) & 0x7F;
4114 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4115 }
4116
4117 /*** Trap ***/
4118
4119 /* tw */
4120 static void gen_tw(DisasContext *ctx)
4121 {
4122 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4123 /* Update the nip since this might generate a trap exception */
4124 gen_update_nip(ctx, ctx->nip);
4125 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4126 t0);
4127 tcg_temp_free_i32(t0);
4128 }
4129
4130 /* twi */
4131 static void gen_twi(DisasContext *ctx)
4132 {
4133 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4134 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4135 /* Update the nip since this might generate a trap exception */
4136 gen_update_nip(ctx, ctx->nip);
4137 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4138 tcg_temp_free(t0);
4139 tcg_temp_free_i32(t1);
4140 }
4141
4142 #if defined(TARGET_PPC64)
4143 /* td */
4144 static void gen_td(DisasContext *ctx)
4145 {
4146 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4147 /* Update the nip since this might generate a trap exception */
4148 gen_update_nip(ctx, ctx->nip);
4149 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4150 t0);
4151 tcg_temp_free_i32(t0);
4152 }
4153
4154 /* tdi */
4155 static void gen_tdi(DisasContext *ctx)
4156 {
4157 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4158 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4159 /* Update the nip since this might generate a trap exception */
4160 gen_update_nip(ctx, ctx->nip);
4161 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4162 tcg_temp_free(t0);
4163 tcg_temp_free_i32(t1);
4164 }
4165 #endif
4166
4167 /*** Processor control ***/
4168
4169 static void gen_read_xer(TCGv dst)
4170 {
4171 TCGv t0 = tcg_temp_new();
4172 TCGv t1 = tcg_temp_new();
4173 TCGv t2 = tcg_temp_new();
4174 tcg_gen_mov_tl(dst, cpu_xer);
4175 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4176 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4177 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4178 tcg_gen_or_tl(t0, t0, t1);
4179 tcg_gen_or_tl(dst, dst, t2);
4180 tcg_gen_or_tl(dst, dst, t0);
4181 tcg_temp_free(t0);
4182 tcg_temp_free(t1);
4183 tcg_temp_free(t2);
4184 }
4185
4186 static void gen_write_xer(TCGv src)
4187 {
4188 tcg_gen_andi_tl(cpu_xer, src,
4189 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4190 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4191 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4192 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4193 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4194 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4195 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4196 }
4197
4198 /* mcrxr */
4199 static void gen_mcrxr(DisasContext *ctx)
4200 {
4201 TCGv_i32 t0 = tcg_temp_new_i32();
4202 TCGv_i32 t1 = tcg_temp_new_i32();
4203 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4204
4205 tcg_gen_trunc_tl_i32(t0, cpu_so);
4206 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4207 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4208 tcg_gen_shli_i32(t0, t0, 3);
4209 tcg_gen_shli_i32(t1, t1, 2);
4210 tcg_gen_shli_i32(dst, dst, 1);
4211 tcg_gen_or_i32(dst, dst, t0);
4212 tcg_gen_or_i32(dst, dst, t1);
4213 tcg_temp_free_i32(t0);
4214 tcg_temp_free_i32(t1);
4215
4216 tcg_gen_movi_tl(cpu_so, 0);
4217 tcg_gen_movi_tl(cpu_ov, 0);
4218 tcg_gen_movi_tl(cpu_ca, 0);
4219 }
4220
4221 /* mfcr mfocrf */
4222 static void gen_mfcr(DisasContext *ctx)
4223 {
4224 uint32_t crm, crn;
4225
4226 if (likely(ctx->opcode & 0x00100000)) {
4227 crm = CRM(ctx->opcode);
4228 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4229 crn = ctz32 (crm);
4230 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4231 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4232 cpu_gpr[rD(ctx->opcode)], crn * 4);
4233 }
4234 } else {
4235 TCGv_i32 t0 = tcg_temp_new_i32();
4236 tcg_gen_mov_i32(t0, cpu_crf[0]);
4237 tcg_gen_shli_i32(t0, t0, 4);
4238 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4239 tcg_gen_shli_i32(t0, t0, 4);
4240 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4241 tcg_gen_shli_i32(t0, t0, 4);
4242 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4243 tcg_gen_shli_i32(t0, t0, 4);
4244 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4245 tcg_gen_shli_i32(t0, t0, 4);
4246 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4247 tcg_gen_shli_i32(t0, t0, 4);
4248 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4249 tcg_gen_shli_i32(t0, t0, 4);
4250 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4251 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4252 tcg_temp_free_i32(t0);
4253 }
4254 }
4255
4256 /* mfmsr */
4257 static void gen_mfmsr(DisasContext *ctx)
4258 {
4259 #if defined(CONFIG_USER_ONLY)
4260 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4261 #else
4262 if (unlikely(ctx->pr)) {
4263 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4264 return;
4265 }
4266 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4267 #endif
4268 }
4269
4270 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
4271 {
4272 #if 0
4273 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4274 printf("ERROR: try to access SPR %d !\n", sprn);
4275 #endif
4276 }
4277 #define SPR_NOACCESS (&spr_noaccess)
4278
4279 /* mfspr */
4280 static inline void gen_op_mfspr(DisasContext *ctx)
4281 {
4282 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4283 uint32_t sprn = SPR(ctx->opcode);
4284
4285 #if defined(CONFIG_USER_ONLY)
4286 read_cb = ctx->spr_cb[sprn].uea_read;
4287 #else
4288 if (ctx->pr) {
4289 read_cb = ctx->spr_cb[sprn].uea_read;
4290 } else if (ctx->hv) {
4291 read_cb = ctx->spr_cb[sprn].hea_read;
4292 } else {
4293 read_cb = ctx->spr_cb[sprn].oea_read;
4294 }
4295 #endif
4296 if (likely(read_cb != NULL)) {
4297 if (likely(read_cb != SPR_NOACCESS)) {
4298 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4299 } else {
4300 /* Privilege exception */
4301 /* This is a hack to avoid warnings when running Linux:
4302 * this OS breaks the PowerPC virtualisation model,
4303 * allowing userland application to read the PVR
4304 */
4305 if (sprn != SPR_PVR) {
4306 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
4307 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4308 if (qemu_log_separate()) {
4309 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4310 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4311 }
4312 }
4313 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4314 }
4315 } else {
4316 /* Not defined */
4317 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
4318 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4319 if (qemu_log_separate()) {
4320 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4321 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4322 }
4323 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4324 }
4325 }
4326
4327 static void gen_mfspr(DisasContext *ctx)
4328 {
4329 gen_op_mfspr(ctx);
4330 }
4331
4332 /* mftb */
4333 static void gen_mftb(DisasContext *ctx)
4334 {
4335 gen_op_mfspr(ctx);
4336 }
4337
4338 /* mtcrf mtocrf*/
4339 static void gen_mtcrf(DisasContext *ctx)
4340 {
4341 uint32_t crm, crn;
4342
4343 crm = CRM(ctx->opcode);
4344 if (likely((ctx->opcode & 0x00100000))) {
4345 if (crm && ((crm & (crm - 1)) == 0)) {
4346 TCGv_i32 temp = tcg_temp_new_i32();
4347 crn = ctz32 (crm);
4348 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4349 tcg_gen_shri_i32(temp, temp, crn * 4);
4350 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4351 tcg_temp_free_i32(temp);
4352 }
4353 } else {
4354 TCGv_i32 temp = tcg_temp_new_i32();
4355 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4356 for (crn = 0 ; crn < 8 ; crn++) {
4357 if (crm & (1 << crn)) {
4358 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4359 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4360 }
4361 }
4362 tcg_temp_free_i32(temp);
4363 }
4364 }
4365
4366 /* mtmsr */
4367 #if defined(TARGET_PPC64)
4368 static void gen_mtmsrd(DisasContext *ctx)
4369 {
4370 #if defined(CONFIG_USER_ONLY)
4371 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4372 #else
4373 if (unlikely(ctx->pr)) {
4374 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4375 return;
4376 }
4377 if (ctx->opcode & 0x00010000) {
4378 /* Special form that does not need any synchronisation */
4379 TCGv t0 = tcg_temp_new();
4380 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4381 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4382 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4383 tcg_temp_free(t0);
4384 } else {
4385 /* XXX: we need to update nip before the store
4386 * if we enter power saving mode, we will exit the loop
4387 * directly from ppc_store_msr
4388 */
4389 gen_update_nip(ctx, ctx->nip);
4390 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4391 /* Must stop the translation as machine state (may have) changed */
4392 /* Note that mtmsr is not always defined as context-synchronizing */
4393 gen_stop_exception(ctx);
4394 }
4395 #endif
4396 }
4397 #endif
4398
4399 static void gen_mtmsr(DisasContext *ctx)
4400 {
4401 #if defined(CONFIG_USER_ONLY)
4402 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4403 #else
4404 if (unlikely(ctx->pr)) {
4405 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4406 return;
4407 }
4408 if (ctx->opcode & 0x00010000) {
4409 /* Special form that does not need any synchronisation */
4410 TCGv t0 = tcg_temp_new();
4411 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4412 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4413 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4414 tcg_temp_free(t0);
4415 } else {
4416 TCGv msr = tcg_temp_new();
4417
4418 /* XXX: we need to update nip before the store
4419 * if we enter power saving mode, we will exit the loop
4420 * directly from ppc_store_msr
4421 */
4422 gen_update_nip(ctx, ctx->nip);
4423 #if defined(TARGET_PPC64)
4424 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4425 #else
4426 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4427 #endif
4428 gen_helper_store_msr(cpu_env, msr);
4429 tcg_temp_free(msr);
4430 /* Must stop the translation as machine state (may have) changed */
4431 /* Note that mtmsr is not always defined as context-synchronizing */
4432 gen_stop_exception(ctx);
4433 }
4434 #endif
4435 }
4436
4437 /* mtspr */
4438 static void gen_mtspr(DisasContext *ctx)
4439 {
4440 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4441 uint32_t sprn = SPR(ctx->opcode);
4442
4443 #if defined(CONFIG_USER_ONLY)
4444 write_cb = ctx->spr_cb[sprn].uea_write;
4445 #else
4446 if (ctx->pr) {
4447 write_cb = ctx->spr_cb[sprn].uea_write;
4448 } else if (ctx->hv) {
4449 write_cb = ctx->spr_cb[sprn].hea_write;
4450 } else {
4451 write_cb = ctx->spr_cb[sprn].oea_write;
4452 }
4453 #endif
4454 if (likely(write_cb != NULL)) {
4455 if (likely(write_cb != SPR_NOACCESS)) {
4456 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4457 } else {
4458 /* Privilege exception */
4459 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4460 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4461 if (qemu_log_separate()) {
4462 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4463 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4464 }
4465 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4466 }
4467 } else {
4468 /* Not defined */
4469 if (qemu_log_separate()) {
4470 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4471 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4472 }
4473 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4474 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4475 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4476 }
4477 }
4478
4479 /*** Cache management ***/
4480
4481 /* dcbf */
4482 static void gen_dcbf(DisasContext *ctx)
4483 {
4484 /* XXX: specification says this is treated as a load by the MMU */
4485 TCGv t0;
4486 gen_set_access_type(ctx, ACCESS_CACHE);
4487 t0 = tcg_temp_new();
4488 gen_addr_reg_index(ctx, t0);
4489 gen_qemu_ld8u(ctx, t0, t0);
4490 tcg_temp_free(t0);
4491 }
4492
4493 /* dcbi (Supervisor only) */
4494 static void gen_dcbi(DisasContext *ctx)
4495 {
4496 #if defined(CONFIG_USER_ONLY)
4497 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4498 #else
4499 TCGv EA, val;
4500 if (unlikely(ctx->pr)) {
4501 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4502 return;
4503 }
4504 EA = tcg_temp_new();
4505 gen_set_access_type(ctx, ACCESS_CACHE);
4506 gen_addr_reg_index(ctx, EA);
4507 val = tcg_temp_new();
4508 /* XXX: specification says this should be treated as a store by the MMU */
4509 gen_qemu_ld8u(ctx, val, EA);
4510 gen_qemu_st8(ctx, val, EA);
4511 tcg_temp_free(val);
4512 tcg_temp_free(EA);
4513 #endif
4514 }
4515
4516 /* dcdst */
4517 static void gen_dcbst(DisasContext *ctx)
4518 {
4519 /* XXX: specification say this is treated as a load by the MMU */
4520 TCGv t0;
4521 gen_set_access_type(ctx, ACCESS_CACHE);
4522 t0 = tcg_temp_new();
4523 gen_addr_reg_index(ctx, t0);
4524 gen_qemu_ld8u(ctx, t0, t0);
4525 tcg_temp_free(t0);
4526 }
4527
4528 /* dcbt */
4529 static void gen_dcbt(DisasContext *ctx)
4530 {
4531 /* interpreted as no-op */
4532 /* XXX: specification say this is treated as a load by the MMU
4533 * but does not generate any exception
4534 */
4535 }
4536
4537 /* dcbtst */
4538 static void gen_dcbtst(DisasContext *ctx)
4539 {
4540 /* interpreted as no-op */
4541 /* XXX: specification say this is treated as a load by the MMU
4542 * but does not generate any exception
4543 */
4544 }
4545
4546 /* dcbtls */
4547 static void gen_dcbtls(DisasContext *ctx)
4548 {
4549 /* Always fails locking the cache */
4550 TCGv t0 = tcg_temp_new();
4551 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4552 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4553 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4554 tcg_temp_free(t0);
4555 }
4556
4557 /* dcbz */
4558 static void gen_dcbz(DisasContext *ctx)
4559 {
4560 TCGv tcgv_addr;
4561 TCGv_i32 tcgv_is_dcbzl;
4562 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4563
4564 gen_set_access_type(ctx, ACCESS_CACHE);
4565 /* NIP cannot be restored if the memory exception comes from an helper */
4566 gen_update_nip(ctx, ctx->nip - 4);
4567 tcgv_addr = tcg_temp_new();
4568 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4569
4570 gen_addr_reg_index(ctx, tcgv_addr);
4571 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4572
4573 tcg_temp_free(tcgv_addr);
4574 tcg_temp_free_i32(tcgv_is_dcbzl);
4575 }
4576
4577 /* dst / dstt */
4578 static void gen_dst(DisasContext *ctx)
4579 {
4580 if (rA(ctx->opcode) == 0) {
4581 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4582 } else {
4583 /* interpreted as no-op */
4584 }
4585 }
4586
4587 /* dstst /dststt */
4588 static void gen_dstst(DisasContext *ctx)
4589 {
4590 if (rA(ctx->opcode) == 0) {
4591 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4592 } else {
4593 /* interpreted as no-op */
4594 }
4595
4596 }
4597
4598 /* dss / dssall */
4599 static void gen_dss(DisasContext *ctx)
4600 {
4601 /* interpreted as no-op */
4602 }
4603
4604 /* icbi */
4605 static void gen_icbi(DisasContext *ctx)
4606 {
4607 TCGv t0;
4608 gen_set_access_type(ctx, ACCESS_CACHE);
4609 /* NIP cannot be restored if the memory exception comes from an helper */
4610 gen_update_nip(ctx, ctx->nip - 4);
4611 t0 = tcg_temp_new();
4612 gen_addr_reg_index(ctx, t0);
4613 gen_helper_icbi(cpu_env, t0);
4614 tcg_temp_free(t0);
4615 }
4616
4617 /* Optional: */
4618 /* dcba */
4619 static void gen_dcba(DisasContext *ctx)
4620 {
4621 /* interpreted as no-op */
4622 /* XXX: specification say this is treated as a store by the MMU
4623 * but does not generate any exception
4624 */
4625 }
4626
4627 /*** Segment register manipulation ***/
4628 /* Supervisor only: */
4629
4630 /* mfsr */
4631 static void gen_mfsr(DisasContext *ctx)
4632 {
4633 #if defined(CONFIG_USER_ONLY)
4634 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4635 #else
4636 TCGv t0;
4637 if (unlikely(ctx->pr)) {
4638 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4639 return;
4640 }
4641 t0 = tcg_const_tl(SR(ctx->opcode));
4642 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4643 tcg_temp_free(t0);
4644 #endif
4645 }
4646
4647 /* mfsrin */
4648 static void gen_mfsrin(DisasContext *ctx)
4649 {
4650 #if defined(CONFIG_USER_ONLY)
4651 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4652 #else
4653 TCGv t0;
4654 if (unlikely(ctx->pr)) {
4655 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4656 return;
4657 }
4658 t0 = tcg_temp_new();
4659 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4660 tcg_gen_andi_tl(t0, t0, 0xF);
4661 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4662 tcg_temp_free(t0);
4663 #endif
4664 }
4665
4666 /* mtsr */
4667 static void gen_mtsr(DisasContext *ctx)
4668 {
4669 #if defined(CONFIG_USER_ONLY)
4670 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4671 #else
4672 TCGv t0;
4673 if (unlikely(ctx->pr)) {
4674 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4675 return;
4676 }
4677 t0 = tcg_const_tl(SR(ctx->opcode));
4678 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4679 tcg_temp_free(t0);
4680 #endif
4681 }
4682
4683 /* mtsrin */
4684 static void gen_mtsrin(DisasContext *ctx)
4685 {
4686 #if defined(CONFIG_USER_ONLY)
4687 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4688 #else
4689 TCGv t0;
4690 if (unlikely(ctx->pr)) {
4691 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4692 return;
4693 }
4694 t0 = tcg_temp_new();
4695 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4696 tcg_gen_andi_tl(t0, t0, 0xF);
4697 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4698 tcg_temp_free(t0);
4699 #endif
4700 }
4701
4702 #if defined(TARGET_PPC64)
4703 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4704
4705 /* mfsr */
4706 static void gen_mfsr_64b(DisasContext *ctx)
4707 {
4708 #if defined(CONFIG_USER_ONLY)
4709 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4710 #else
4711 TCGv t0;
4712 if (unlikely(ctx->pr)) {
4713 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4714 return;
4715 }
4716 t0 = tcg_const_tl(SR(ctx->opcode));
4717 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4718 tcg_temp_free(t0);
4719 #endif
4720 }
4721
4722 /* mfsrin */
4723 static void gen_mfsrin_64b(DisasContext *ctx)
4724 {
4725 #if defined(CONFIG_USER_ONLY)
4726 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4727 #else
4728 TCGv t0;
4729 if (unlikely(ctx->pr)) {
4730 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4731 return;
4732 }
4733 t0 = tcg_temp_new();
4734 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4735 tcg_gen_andi_tl(t0, t0, 0xF);
4736 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4737 tcg_temp_free(t0);
4738 #endif
4739 }
4740
4741 /* mtsr */
4742 static void gen_mtsr_64b(DisasContext *ctx)
4743 {
4744 #if defined(CONFIG_USER_ONLY)
4745 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4746 #else
4747 TCGv t0;
4748 if (unlikely(ctx->pr)) {
4749 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4750 return;
4751 }
4752 t0 = tcg_const_tl(SR(ctx->opcode));
4753 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4754 tcg_temp_free(t0);
4755 #endif
4756 }
4757
4758 /* mtsrin */
4759 static void gen_mtsrin_64b(DisasContext *ctx)
4760 {
4761 #if defined(CONFIG_USER_ONLY)
4762 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4763 #else
4764 TCGv t0;
4765 if (unlikely(ctx->pr)) {
4766 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4767 return;
4768 }
4769 t0 = tcg_temp_new();
4770 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4771 tcg_gen_andi_tl(t0, t0, 0xF);
4772 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4773 tcg_temp_free(t0);
4774 #endif
4775 }
4776
4777 /* slbmte */
4778 static void gen_slbmte(DisasContext *ctx)
4779 {
4780 #if defined(CONFIG_USER_ONLY)
4781 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4782 #else
4783 if (unlikely(ctx->pr)) {
4784 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4785 return;
4786 }
4787 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4788 cpu_gpr[rS(ctx->opcode)]);
4789 #endif
4790 }
4791
4792 static void gen_slbmfee(DisasContext *ctx)
4793 {
4794 #if defined(CONFIG_USER_ONLY)
4795 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4796 #else
4797 if (unlikely(ctx->pr)) {
4798 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4799 return;
4800 }
4801 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4802 cpu_gpr[rB(ctx->opcode)]);
4803 #endif
4804 }
4805
4806 static void gen_slbmfev(DisasContext *ctx)
4807 {
4808 #if defined(CONFIG_USER_ONLY)
4809 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4810 #else
4811 if (unlikely(ctx->pr)) {
4812 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4813 return;
4814 }
4815 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4816 cpu_gpr[rB(ctx->opcode)]);
4817 #endif
4818 }
4819 #endif /* defined(TARGET_PPC64) */
4820
4821 /*** Lookaside buffer management ***/
4822 /* Optional & supervisor only: */
4823
4824 /* tlbia */
4825 static void gen_tlbia(DisasContext *ctx)
4826 {
4827 #if defined(CONFIG_USER_ONLY)
4828 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4829 #else
4830 if (unlikely(ctx->pr)) {
4831 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4832 return;
4833 }
4834 gen_helper_tlbia(cpu_env);
4835 #endif
4836 }
4837
4838 /* tlbiel */
4839 static void gen_tlbiel(DisasContext *ctx)
4840 {
4841 #if defined(CONFIG_USER_ONLY)
4842 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4843 #else
4844 if (unlikely(ctx->pr)) {
4845 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4846 return;
4847 }
4848 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4849 #endif
4850 }
4851
4852 /* tlbie */
4853 static void gen_tlbie(DisasContext *ctx)
4854 {
4855 #if defined(CONFIG_USER_ONLY)
4856 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4857 #else
4858 if (unlikely(ctx->pr)) {
4859 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4860 return;
4861 }
4862 if (NARROW_MODE(ctx)) {
4863 TCGv t0 = tcg_temp_new();
4864 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4865 gen_helper_tlbie(cpu_env, t0);
4866 tcg_temp_free(t0);
4867 } else {
4868 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4869 }
4870 #endif
4871 }
4872
4873 /* tlbsync */
4874 static void gen_tlbsync(DisasContext *ctx)
4875 {
4876 #if defined(CONFIG_USER_ONLY)
4877 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4878 #else
4879 if (unlikely(ctx->pr)) {
4880 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4881 return;
4882 }
4883 /* This has no effect: it should ensure that all previous
4884 * tlbie have completed
4885 */
4886 gen_stop_exception(ctx);
4887 #endif
4888 }
4889
4890 #if defined(TARGET_PPC64)
4891 /* slbia */
4892 static void gen_slbia(DisasContext *ctx)
4893 {
4894 #if defined(CONFIG_USER_ONLY)
4895 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4896 #else
4897 if (unlikely(ctx->pr)) {
4898 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4899 return;
4900 }
4901 gen_helper_slbia(cpu_env);
4902 #endif
4903 }
4904
4905 /* slbie */
4906 static void gen_slbie(DisasContext *ctx)
4907 {
4908 #if defined(CONFIG_USER_ONLY)
4909 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4910 #else
4911 if (unlikely(ctx->pr)) {
4912 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4913 return;
4914 }
4915 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4916 #endif
4917 }
4918 #endif
4919
4920 /*** External control ***/
4921 /* Optional: */
4922
4923 /* eciwx */
4924 static void gen_eciwx(DisasContext *ctx)
4925 {
4926 TCGv t0;
4927 /* Should check EAR[E] ! */
4928 gen_set_access_type(ctx, ACCESS_EXT);
4929 t0 = tcg_temp_new();
4930 gen_addr_reg_index(ctx, t0);
4931 gen_check_align(ctx, t0, 0x03);
4932 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4933 tcg_temp_free(t0);
4934 }
4935
4936 /* ecowx */
4937 static void gen_ecowx(DisasContext *ctx)
4938 {
4939 TCGv t0;
4940 /* Should check EAR[E] ! */
4941 gen_set_access_type(ctx, ACCESS_EXT);
4942 t0 = tcg_temp_new();
4943 gen_addr_reg_index(ctx, t0);
4944 gen_check_align(ctx, t0, 0x03);
4945 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4946 tcg_temp_free(t0);
4947 }
4948
4949 /* PowerPC 601 specific instructions */
4950
4951 /* abs - abs. */
4952 static void gen_abs(DisasContext *ctx)
4953 {
4954 TCGLabel *l1 = gen_new_label();
4955 TCGLabel *l2 = gen_new_label();
4956 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4957 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4958 tcg_gen_br(l2);
4959 gen_set_label(l1);
4960 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4961 gen_set_label(l2);
4962 if (unlikely(Rc(ctx->opcode) != 0))
4963 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4964 }
4965
4966 /* abso - abso. */
4967 static void gen_abso(DisasContext *ctx)
4968 {
4969 TCGLabel *l1 = gen_new_label();
4970 TCGLabel *l2 = gen_new_label();
4971 TCGLabel *l3 = gen_new_label();
4972 /* Start with XER OV disabled, the most likely case */
4973 tcg_gen_movi_tl(cpu_ov, 0);
4974 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4975 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4976 tcg_gen_movi_tl(cpu_ov, 1);
4977 tcg_gen_movi_tl(cpu_so, 1);
4978 tcg_gen_br(l2);
4979 gen_set_label(l1);
4980 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4981 tcg_gen_br(l3);
4982 gen_set_label(l2);
4983 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4984 gen_set_label(l3);
4985 if (unlikely(Rc(ctx->opcode) != 0))
4986 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4987 }
4988
4989 /* clcs */
4990 static void gen_clcs(DisasContext *ctx)
4991 {
4992 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4993 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4994 tcg_temp_free_i32(t0);
4995 /* Rc=1 sets CR0 to an undefined state */
4996 }
4997
4998 /* div - div. */
4999 static void gen_div(DisasContext *ctx)
5000 {
5001 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5002 cpu_gpr[rB(ctx->opcode)]);
5003 if (unlikely(Rc(ctx->opcode) != 0))
5004 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5005 }
5006
5007 /* divo - divo. */
5008 static void gen_divo(DisasContext *ctx)
5009 {
5010 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5011 cpu_gpr[rB(ctx->opcode)]);
5012 if (unlikely(Rc(ctx->opcode) != 0))
5013 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5014 }
5015
5016 /* divs - divs. */
5017 static void gen_divs(DisasContext *ctx)
5018 {
5019 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5020 cpu_gpr[rB(ctx->opcode)]);
5021 if (unlikely(Rc(ctx->opcode) != 0))
5022 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5023 }
5024
5025 /* divso - divso. */
5026 static void gen_divso(DisasContext *ctx)
5027 {
5028 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5029 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5030 if (unlikely(Rc(ctx->opcode) != 0))
5031 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5032 }
5033
5034 /* doz - doz. */
5035 static void gen_doz(DisasContext *ctx)
5036 {
5037 TCGLabel *l1 = gen_new_label();
5038 TCGLabel *l2 = gen_new_label();
5039 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5040 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5041 tcg_gen_br(l2);
5042 gen_set_label(l1);
5043 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5044 gen_set_label(l2);
5045 if (unlikely(Rc(ctx->opcode) != 0))
5046 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5047 }
5048
5049 /* dozo - dozo. */
5050 static void gen_dozo(DisasContext *ctx)
5051 {
5052 TCGLabel *l1 = gen_new_label();
5053 TCGLabel *l2 = gen_new_label();
5054 TCGv t0 = tcg_temp_new();
5055 TCGv t1 = tcg_temp_new();
5056 TCGv t2 = tcg_temp_new();
5057 /* Start with XER OV disabled, the most likely case */
5058 tcg_gen_movi_tl(cpu_ov, 0);
5059 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5060 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5061 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5062 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5063 tcg_gen_andc_tl(t1, t1, t2);
5064 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5065 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5066 tcg_gen_movi_tl(cpu_ov, 1);
5067 tcg_gen_movi_tl(cpu_so, 1);
5068 tcg_gen_br(l2);
5069 gen_set_label(l1);
5070 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5071 gen_set_label(l2);
5072 tcg_temp_free(t0);
5073 tcg_temp_free(t1);
5074 tcg_temp_free(t2);
5075 if (unlikely(Rc(ctx->opcode) != 0))
5076 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5077 }
5078
5079 /* dozi */
5080 static void gen_dozi(DisasContext *ctx)
5081 {
5082 target_long simm = SIMM(ctx->opcode);
5083 TCGLabel *l1 = gen_new_label();
5084 TCGLabel *l2 = gen_new_label();
5085 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5086 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5087 tcg_gen_br(l2);
5088 gen_set_label(l1);
5089 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5090 gen_set_label(l2);
5091 if (unlikely(Rc(ctx->opcode) != 0))
5092 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5093 }
5094
5095 /* lscbx - lscbx. */
5096 static void gen_lscbx(DisasContext *ctx)
5097 {
5098 TCGv t0 = tcg_temp_new();
5099 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5100 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5101 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5102
5103 gen_addr_reg_index(ctx, t0);
5104 /* NIP cannot be restored if the memory exception comes from an helper */
5105 gen_update_nip(ctx, ctx->nip - 4);
5106 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5107 tcg_temp_free_i32(t1);
5108 tcg_temp_free_i32(t2);
5109 tcg_temp_free_i32(t3);
5110 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5111 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5112 if (unlikely(Rc(ctx->opcode) != 0))
5113 gen_set_Rc0(ctx, t0);
5114 tcg_temp_free(t0);
5115 }
5116
5117 /* maskg - maskg. */
5118 static void gen_maskg(DisasContext *ctx)
5119 {
5120 TCGLabel *l1 = gen_new_label();
5121 TCGv t0 = tcg_temp_new();
5122 TCGv t1 = tcg_temp_new();
5123 TCGv t2 = tcg_temp_new();
5124 TCGv t3 = tcg_temp_new();
5125 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5126 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5127 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5128 tcg_gen_addi_tl(t2, t0, 1);
5129 tcg_gen_shr_tl(t2, t3, t2);
5130 tcg_gen_shr_tl(t3, t3, t1);
5131 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5132 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5133 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5134 gen_set_label(l1);
5135 tcg_temp_free(t0);
5136 tcg_temp_free(t1);
5137 tcg_temp_free(t2);
5138 tcg_temp_free(t3);
5139 if (unlikely(Rc(ctx->opcode) != 0))
5140 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5141 }
5142
5143 /* maskir - maskir. */
5144 static void gen_maskir(DisasContext *ctx)
5145 {
5146 TCGv t0 = tcg_temp_new();
5147 TCGv t1 = tcg_temp_new();
5148 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5149 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5150 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5151 tcg_temp_free(t0);
5152 tcg_temp_free(t1);
5153 if (unlikely(Rc(ctx->opcode) != 0))
5154 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5155 }
5156
5157 /* mul - mul. */
5158 static void gen_mul(DisasContext *ctx)
5159 {
5160 TCGv_i64 t0 = tcg_temp_new_i64();
5161 TCGv_i64 t1 = tcg_temp_new_i64();
5162 TCGv t2 = tcg_temp_new();
5163 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5164 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5165 tcg_gen_mul_i64(t0, t0, t1);
5166 tcg_gen_trunc_i64_tl(t2, t0);
5167 gen_store_spr(SPR_MQ, t2);
5168 tcg_gen_shri_i64(t1, t0, 32);
5169 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5170 tcg_temp_free_i64(t0);
5171 tcg_temp_free_i64(t1);
5172 tcg_temp_free(t2);
5173 if (unlikely(Rc(ctx->opcode) != 0))
5174 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5175 }
5176
5177 /* mulo - mulo. */
5178 static void gen_mulo(DisasContext *ctx)
5179 {
5180 TCGLabel *l1 = gen_new_label();
5181 TCGv_i64 t0 = tcg_temp_new_i64();
5182 TCGv_i64 t1 = tcg_temp_new_i64();
5183 TCGv t2 = tcg_temp_new();
5184 /* Start with XER OV disabled, the most likely case */
5185 tcg_gen_movi_tl(cpu_ov, 0);
5186 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5187 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5188 tcg_gen_mul_i64(t0, t0, t1);
5189 tcg_gen_trunc_i64_tl(t2, t0);
5190 gen_store_spr(SPR_MQ, t2);
5191 tcg_gen_shri_i64(t1, t0, 32);
5192 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5193 tcg_gen_ext32s_i64(t1, t0);
5194 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5195 tcg_gen_movi_tl(cpu_ov, 1);
5196 tcg_gen_movi_tl(cpu_so, 1);
5197 gen_set_label(l1);
5198 tcg_temp_free_i64(t0);
5199 tcg_temp_free_i64(t1);
5200 tcg_temp_free(t2);
5201 if (unlikely(Rc(ctx->opcode) != 0))
5202 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5203 }
5204
5205 /* nabs - nabs. */
5206 static void gen_nabs(DisasContext *ctx)
5207 {
5208 TCGLabel *l1 = gen_new_label();
5209 TCGLabel *l2 = gen_new_label();
5210 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5211 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5212 tcg_gen_br(l2);
5213 gen_set_label(l1);
5214 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5215 gen_set_label(l2);
5216 if (unlikely(Rc(ctx->opcode) != 0))
5217 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5218 }
5219
5220 /* nabso - nabso. */
5221 static void gen_nabso(DisasContext *ctx)
5222 {
5223 TCGLabel *l1 = gen_new_label();
5224 TCGLabel *l2 = gen_new_label();
5225 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5226 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5227 tcg_gen_br(l2);
5228 gen_set_label(l1);
5229 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5230 gen_set_label(l2);
5231 /* nabs never overflows */
5232 tcg_gen_movi_tl(cpu_ov, 0);
5233 if (unlikely(Rc(ctx->opcode) != 0))
5234 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5235 }
5236
5237 /* rlmi - rlmi. */
5238 static void gen_rlmi(DisasContext *ctx)
5239 {
5240 uint32_t mb = MB(ctx->opcode);
5241 uint32_t me = ME(ctx->opcode);
5242 TCGv t0 = tcg_temp_new();
5243 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5244 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5245 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5246 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5247 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5248 tcg_temp_free(t0);
5249 if (unlikely(Rc(ctx->opcode) != 0))
5250 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5251 }
5252
5253 /* rrib - rrib. */
5254 static void gen_rrib(DisasContext *ctx)
5255 {
5256 TCGv t0 = tcg_temp_new();
5257 TCGv t1 = tcg_temp_new();
5258 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5259 tcg_gen_movi_tl(t1, 0x80000000);
5260 tcg_gen_shr_tl(t1, t1, t0);
5261 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5262 tcg_gen_and_tl(t0, t0, t1);
5263 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5264 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5265 tcg_temp_free(t0);
5266 tcg_temp_free(t1);
5267 if (unlikely(Rc(ctx->opcode) != 0))
5268 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5269 }
5270
5271 /* sle - sle. */
5272 static void gen_sle(DisasContext *ctx)
5273 {
5274 TCGv t0 = tcg_temp_new();
5275 TCGv t1 = tcg_temp_new();
5276 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5277 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5278 tcg_gen_subfi_tl(t1, 32, t1);
5279 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5280 tcg_gen_or_tl(t1, t0, t1);
5281 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5282 gen_store_spr(SPR_MQ, t1);
5283 tcg_temp_free(t0);
5284 tcg_temp_free(t1);
5285 if (unlikely(Rc(ctx->opcode) != 0))
5286 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5287 }
5288
5289 /* sleq - sleq. */
5290 static void gen_sleq(DisasContext *ctx)
5291 {
5292 TCGv t0 = tcg_temp_new();
5293 TCGv t1 = tcg_temp_new();
5294 TCGv t2 = tcg_temp_new();
5295 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5296 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5297 tcg_gen_shl_tl(t2, t2, t0);
5298 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5299 gen_load_spr(t1, SPR_MQ);
5300 gen_store_spr(SPR_MQ, t0);
5301 tcg_gen_and_tl(t0, t0, t2);
5302 tcg_gen_andc_tl(t1, t1, t2);
5303 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5304 tcg_temp_free(t0);
5305 tcg_temp_free(t1);
5306 tcg_temp_free(t2);
5307 if (unlikely(Rc(ctx->opcode) != 0))
5308 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5309 }
5310
5311 /* sliq - sliq. */
5312 static void gen_sliq(DisasContext *ctx)
5313 {
5314 int sh = SH(ctx->opcode);
5315 TCGv t0 = tcg_temp_new();
5316 TCGv t1 = tcg_temp_new();
5317 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5318 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5319 tcg_gen_or_tl(t1, t0, t1);
5320 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5321 gen_store_spr(SPR_MQ, t1);
5322 tcg_temp_free(t0);
5323 tcg_temp_free(t1);
5324 if (unlikely(Rc(ctx->opcode) != 0))
5325 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5326 }
5327
5328 /* slliq - slliq. */
5329 static void gen_slliq(DisasContext *ctx)
5330 {
5331 int sh = SH(ctx->opcode);
5332 TCGv t0 = tcg_temp_new();
5333 TCGv t1 = tcg_temp_new();
5334 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5335 gen_load_spr(t1, SPR_MQ);
5336 gen_store_spr(SPR_MQ, t0);
5337 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5338 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5339 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5340 tcg_temp_free(t0);
5341 tcg_temp_free(t1);
5342 if (unlikely(Rc(ctx->opcode) != 0))
5343 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5344 }
5345
5346 /* sllq - sllq. */
5347 static void gen_sllq(DisasContext *ctx)
5348 {
5349 TCGLabel *l1 = gen_new_label();
5350 TCGLabel *l2 = gen_new_label();
5351 TCGv t0 = tcg_temp_local_new();
5352 TCGv t1 = tcg_temp_local_new();
5353 TCGv t2 = tcg_temp_local_new();
5354 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5355 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5356 tcg_gen_shl_tl(t1, t1, t2);
5357 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5358 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5359 gen_load_spr(t0, SPR_MQ);
5360 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5361 tcg_gen_br(l2);
5362 gen_set_label(l1);
5363 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5364 gen_load_spr(t2, SPR_MQ);
5365 tcg_gen_andc_tl(t1, t2, t1);
5366 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5367 gen_set_label(l2);
5368 tcg_temp_free(t0);
5369 tcg_temp_free(t1);
5370 tcg_temp_free(t2);
5371 if (unlikely(Rc(ctx->opcode) != 0))
5372 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5373 }
5374
5375 /* slq - slq. */
5376 static void gen_slq(DisasContext *ctx)
5377 {
5378 TCGLabel *l1 = gen_new_label();
5379 TCGv t0 = tcg_temp_new();
5380 TCGv t1 = tcg_temp_new();
5381 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5382 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5383 tcg_gen_subfi_tl(t1, 32, t1);
5384 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5385 tcg_gen_or_tl(t1, t0, t1);
5386 gen_store_spr(SPR_MQ, t1);
5387 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5388 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5389 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5390 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5391 gen_set_label(l1);
5392 tcg_temp_free(t0);
5393 tcg_temp_free(t1);
5394 if (unlikely(Rc(ctx->opcode) != 0))
5395 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5396 }
5397
5398 /* sraiq - sraiq. */
5399 static void gen_sraiq(DisasContext *ctx)
5400 {
5401 int sh = SH(ctx->opcode);
5402 TCGLabel *l1 = gen_new_label();
5403 TCGv t0 = tcg_temp_new();
5404 TCGv t1 = tcg_temp_new();
5405 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5406 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5407 tcg_gen_or_tl(t0, t0, t1);
5408 gen_store_spr(SPR_MQ, t0);
5409 tcg_gen_movi_tl(cpu_ca, 0);
5410 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5411 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5412 tcg_gen_movi_tl(cpu_ca, 1);
5413 gen_set_label(l1);
5414 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5415 tcg_temp_free(t0);
5416 tcg_temp_free(t1);
5417 if (unlikely(Rc(ctx->opcode) != 0))
5418 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5419 }
5420
5421 /* sraq - sraq. */
5422 static void gen_sraq(DisasContext *ctx)
5423 {
5424 TCGLabel *l1 = gen_new_label();
5425 TCGLabel *l2 = gen_new_label();
5426 TCGv t0 = tcg_temp_new();
5427 TCGv t1 = tcg_temp_local_new();
5428 TCGv t2 = tcg_temp_local_new();
5429 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5430 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5431 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5432 tcg_gen_subfi_tl(t2, 32, t2);
5433 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5434 tcg_gen_or_tl(t0, t0, t2);
5435 gen_store_spr(SPR_MQ, t0);
5436 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5437 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5438 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5439 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5440 gen_set_label(l1);
5441 tcg_temp_free(t0);
5442 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5443 tcg_gen_movi_tl(cpu_ca, 0);
5444 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5445 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5446 tcg_gen_movi_tl(cpu_ca, 1);
5447 gen_set_label(l2);
5448 tcg_temp_free(t1);
5449 tcg_temp_free(t2);
5450 if (unlikely(Rc(ctx->opcode) != 0))
5451 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5452 }
5453
5454 /* sre - sre. */
5455 static void gen_sre(DisasContext *ctx)
5456 {
5457 TCGv t0 = tcg_temp_new();
5458 TCGv t1 = tcg_temp_new();
5459 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5460 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5461 tcg_gen_subfi_tl(t1, 32, t1);
5462 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5463 tcg_gen_or_tl(t1, t0, t1);
5464 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5465 gen_store_spr(SPR_MQ, t1);
5466 tcg_temp_free(t0);
5467 tcg_temp_free(t1);
5468 if (unlikely(Rc(ctx->opcode) != 0))
5469 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5470 }
5471
5472 /* srea - srea. */
5473 static void gen_srea(DisasContext *ctx)
5474 {
5475 TCGv t0 = tcg_temp_new();
5476 TCGv t1 = tcg_temp_new();
5477 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5478 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5479 gen_store_spr(SPR_MQ, t0);
5480 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5481 tcg_temp_free(t0);
5482 tcg_temp_free(t1);
5483 if (unlikely(Rc(ctx->opcode) != 0))
5484 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5485 }
5486
5487 /* sreq */
5488 static void gen_sreq(DisasContext *ctx)
5489 {
5490 TCGv t0 = tcg_temp_new();
5491 TCGv t1 = tcg_temp_new();
5492 TCGv t2 = tcg_temp_new();
5493 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5494 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5495 tcg_gen_shr_tl(t1, t1, t0);
5496 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5497 gen_load_spr(t2, SPR_MQ);
5498 gen_store_spr(SPR_MQ, t0);
5499 tcg_gen_and_tl(t0, t0, t1);
5500 tcg_gen_andc_tl(t2, t2, t1);
5501 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5502 tcg_temp_free(t0);
5503 tcg_temp_free(t1);
5504 tcg_temp_free(t2);
5505 if (unlikely(Rc(ctx->opcode) != 0))
5506 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5507 }
5508
5509 /* sriq */
5510 static void gen_sriq(DisasContext *ctx)
5511 {
5512 int sh = SH(ctx->opcode);
5513 TCGv t0 = tcg_temp_new();
5514 TCGv t1 = tcg_temp_new();
5515 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5516 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5517 tcg_gen_or_tl(t1, t0, t1);
5518 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5519 gen_store_spr(SPR_MQ, t1);
5520 tcg_temp_free(t0);
5521 tcg_temp_free(t1);
5522 if (unlikely(Rc(ctx->opcode) != 0))
5523 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5524 }
5525
5526 /* srliq */
5527 static void gen_srliq(DisasContext *ctx)
5528 {
5529 int sh = SH(ctx->opcode);
5530 TCGv t0 = tcg_temp_new();
5531 TCGv t1 = tcg_temp_new();
5532 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5533 gen_load_spr(t1, SPR_MQ);
5534 gen_store_spr(SPR_MQ, t0);
5535 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5536 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5537 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5538 tcg_temp_free(t0);
5539 tcg_temp_free(t1);
5540 if (unlikely(Rc(ctx->opcode) != 0))
5541 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5542 }
5543
5544 /* srlq */
5545 static void gen_srlq(DisasContext *ctx)
5546 {
5547 TCGLabel *l1 = gen_new_label();
5548 TCGLabel *l2 = gen_new_label();
5549 TCGv t0 = tcg_temp_local_new();
5550 TCGv t1 = tcg_temp_local_new();
5551 TCGv t2 = tcg_temp_local_new();
5552 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5553 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5554 tcg_gen_shr_tl(t2, t1, t2);
5555 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5556 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5557 gen_load_spr(t0, SPR_MQ);
5558 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5559 tcg_gen_br(l2);
5560 gen_set_label(l1);
5561 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5562 tcg_gen_and_tl(t0, t0, t2);
5563 gen_load_spr(t1, SPR_MQ);
5564 tcg_gen_andc_tl(t1, t1, t2);
5565 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5566 gen_set_label(l2);
5567 tcg_temp_free(t0);
5568 tcg_temp_free(t1);
5569 tcg_temp_free(t2);
5570 if (unlikely(Rc(ctx->opcode) != 0))
5571 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5572 }
5573
5574 /* srq */
5575 static void gen_srq(DisasContext *ctx)
5576 {
5577 TCGLabel *l1 = gen_new_label();
5578 TCGv t0 = tcg_temp_new();
5579 TCGv t1 = tcg_temp_new();
5580 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5581 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5582 tcg_gen_subfi_tl(t1, 32, t1);
5583 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5584 tcg_gen_or_tl(t1, t0, t1);
5585 gen_store_spr(SPR_MQ, t1);
5586 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5587 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5588 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5589 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5590 gen_set_label(l1);
5591 tcg_temp_free(t0);
5592 tcg_temp_free(t1);
5593 if (unlikely(Rc(ctx->opcode) != 0))
5594 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5595 }
5596
5597 /* PowerPC 602 specific instructions */
5598
5599 /* dsa */
5600 static void gen_dsa(DisasContext *ctx)
5601 {
5602 /* XXX: TODO */
5603 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5604 }
5605
5606 /* esa */
5607 static void gen_esa(DisasContext *ctx)
5608 {
5609 /* XXX: TODO */
5610 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5611 }
5612
5613 /* mfrom */
5614 static void gen_mfrom(DisasContext *ctx)
5615 {
5616 #if defined(CONFIG_USER_ONLY)
5617 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5618 #else
5619 if (unlikely(ctx->pr)) {
5620 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5621 return;
5622 }
5623 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5624 #endif
5625 }
5626
5627 /* 602 - 603 - G2 TLB management */
5628
5629 /* tlbld */
5630 static void gen_tlbld_6xx(DisasContext *ctx)
5631 {
5632 #if defined(CONFIG_USER_ONLY)
5633 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5634 #else
5635 if (unlikely(ctx->pr)) {
5636 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5637 return;
5638 }
5639 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5640 #endif
5641 }
5642
5643 /* tlbli */
5644 static void gen_tlbli_6xx(DisasContext *ctx)
5645 {
5646 #if defined(CONFIG_USER_ONLY)
5647 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5648 #else
5649 if (unlikely(ctx->pr)) {
5650 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5651 return;
5652 }
5653 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5654 #endif
5655 }
5656
5657 /* 74xx TLB management */
5658
5659 /* tlbld */
5660 static void gen_tlbld_74xx(DisasContext *ctx)
5661 {
5662 #if defined(CONFIG_USER_ONLY)
5663 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5664 #else
5665 if (unlikely(ctx->pr)) {
5666 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5667 return;
5668 }
5669 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5670 #endif
5671 }
5672
5673 /* tlbli */
5674 static void gen_tlbli_74xx(DisasContext *ctx)
5675 {
5676 #if defined(CONFIG_USER_ONLY)
5677 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5678 #else
5679 if (unlikely(ctx->pr)) {
5680 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5681 return;
5682 }
5683 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5684 #endif
5685 }
5686
5687 /* POWER instructions not in PowerPC 601 */
5688
5689 /* clf */
5690 static void gen_clf(DisasContext *ctx)
5691 {
5692 /* Cache line flush: implemented as no-op */
5693 }
5694
5695 /* cli */
5696 static void gen_cli(DisasContext *ctx)
5697 {
5698 /* Cache line invalidate: privileged and treated as no-op */
5699 #if defined(CONFIG_USER_ONLY)
5700 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5701 #else
5702 if (unlikely(ctx->pr)) {
5703 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5704 return;
5705 }
5706 #endif
5707 }
5708
5709 /* dclst */
5710 static void gen_dclst(DisasContext *ctx)
5711 {
5712 /* Data cache line store: treated as no-op */
5713 }
5714
5715 static void gen_mfsri(DisasContext *ctx)
5716 {
5717 #if defined(CONFIG_USER_ONLY)
5718 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5719 #else
5720 int ra = rA(ctx->opcode);
5721 int rd = rD(ctx->opcode);
5722 TCGv t0;
5723 if (unlikely(ctx->pr)) {
5724 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5725 return;
5726 }
5727 t0 = tcg_temp_new();
5728 gen_addr_reg_index(ctx, t0);
5729 tcg_gen_shri_tl(t0, t0, 28);
5730 tcg_gen_andi_tl(t0, t0, 0xF);
5731 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5732 tcg_temp_free(t0);
5733 if (ra != 0 && ra != rd)
5734 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5735 #endif
5736 }
5737
5738 static void gen_rac(DisasContext *ctx)
5739 {
5740 #if defined(CONFIG_USER_ONLY)
5741 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5742 #else
5743 TCGv t0;
5744 if (unlikely(ctx->pr)) {
5745 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5746 return;
5747 }
5748 t0 = tcg_temp_new();
5749 gen_addr_reg_index(ctx, t0);
5750 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5751 tcg_temp_free(t0);
5752 #endif
5753 }
5754
5755 static void gen_rfsvc(DisasContext *ctx)
5756 {
5757 #if defined(CONFIG_USER_ONLY)
5758 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5759 #else
5760 if (unlikely(ctx->pr)) {
5761 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5762 return;
5763 }
5764 gen_helper_rfsvc(cpu_env);
5765 gen_sync_exception(ctx);
5766 #endif
5767 }
5768
5769 /* svc is not implemented for now */
5770
5771 /* POWER2 specific instructions */
5772 /* Quad manipulation (load/store two floats at a time) */
5773
5774 /* lfq */
5775 static void gen_lfq(DisasContext *ctx)
5776 {
5777 int rd = rD(ctx->opcode);
5778 TCGv t0;
5779 gen_set_access_type(ctx, ACCESS_FLOAT);
5780 t0 = tcg_temp_new();
5781 gen_addr_imm_index(ctx, t0, 0);
5782 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5783 gen_addr_add(ctx, t0, t0, 8);
5784 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5785 tcg_temp_free(t0);
5786 }
5787
5788 /* lfqu */
5789 static void gen_lfqu(DisasContext *ctx)
5790 {
5791 int ra = rA(ctx->opcode);
5792 int rd = rD(ctx->opcode);
5793 TCGv t0, t1;
5794 gen_set_access_type(ctx, ACCESS_FLOAT);
5795 t0 = tcg_temp_new();
5796 t1 = tcg_temp_new();
5797 gen_addr_imm_index(ctx, t0, 0);
5798 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5799 gen_addr_add(ctx, t1, t0, 8);
5800 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5801 if (ra != 0)
5802 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5803 tcg_temp_free(t0);
5804 tcg_temp_free(t1);
5805 }
5806
5807 /* lfqux */
5808 static void gen_lfqux(DisasContext *ctx)
5809 {
5810 int ra = rA(ctx->opcode);
5811 int rd = rD(ctx->opcode);
5812 gen_set_access_type(ctx, ACCESS_FLOAT);
5813 TCGv t0, t1;
5814 t0 = tcg_temp_new();
5815 gen_addr_reg_index(ctx, t0);
5816 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5817 t1 = tcg_temp_new();
5818 gen_addr_add(ctx, t1, t0, 8);
5819 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5820 tcg_temp_free(t1);
5821 if (ra != 0)
5822 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5823 tcg_temp_free(t0);
5824 }
5825
5826 /* lfqx */
5827 static void gen_lfqx(DisasContext *ctx)
5828 {
5829 int rd = rD(ctx->opcode);
5830 TCGv t0;
5831 gen_set_access_type(ctx, ACCESS_FLOAT);
5832 t0 = tcg_temp_new();
5833 gen_addr_reg_index(ctx, t0);
5834 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5835 gen_addr_add(ctx, t0, t0, 8);
5836 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5837 tcg_temp_free(t0);
5838 }
5839
5840 /* stfq */
5841 static void gen_stfq(DisasContext *ctx)
5842 {
5843 int rd = rD(ctx->opcode);
5844 TCGv t0;
5845 gen_set_access_type(ctx, ACCESS_FLOAT);
5846 t0 = tcg_temp_new();
5847 gen_addr_imm_index(ctx, t0, 0);
5848 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5849 gen_addr_add(ctx, t0, t0, 8);
5850 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5851 tcg_temp_free(t0);
5852 }
5853
5854 /* stfqu */
5855 static void gen_stfqu(DisasContext *ctx)
5856 {
5857 int ra = rA(ctx->opcode);
5858 int rd = rD(ctx->opcode);
5859 TCGv t0, t1;
5860 gen_set_access_type(ctx, ACCESS_FLOAT);
5861 t0 = tcg_temp_new();
5862 gen_addr_imm_index(ctx, t0, 0);
5863 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5864 t1 = tcg_temp_new();
5865 gen_addr_add(ctx, t1, t0, 8);
5866 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5867 tcg_temp_free(t1);
5868 if (ra != 0)
5869 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5870 tcg_temp_free(t0);
5871 }
5872
5873 /* stfqux */
5874 static void gen_stfqux(DisasContext *ctx)
5875 {
5876 int ra = rA(ctx->opcode);
5877 int rd = rD(ctx->opcode);
5878 TCGv t0, t1;
5879 gen_set_access_type(ctx, ACCESS_FLOAT);
5880 t0 = tcg_temp_new();
5881 gen_addr_reg_index(ctx, t0);
5882 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5883 t1 = tcg_temp_new();
5884 gen_addr_add(ctx, t1, t0, 8);
5885 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5886 tcg_temp_free(t1);
5887 if (ra != 0)
5888 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5889 tcg_temp_free(t0);
5890 }
5891
5892 /* stfqx */
5893 static void gen_stfqx(DisasContext *ctx)
5894 {
5895 int rd = rD(ctx->opcode);
5896 TCGv t0;
5897 gen_set_access_type(ctx, ACCESS_FLOAT);
5898 t0 = tcg_temp_new();
5899 gen_addr_reg_index(ctx, t0);
5900 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5901 gen_addr_add(ctx, t0, t0, 8);
5902 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5903 tcg_temp_free(t0);
5904 }
5905
5906 /* BookE specific instructions */
5907
5908 /* XXX: not implemented on 440 ? */
5909 static void gen_mfapidi(DisasContext *ctx)
5910 {
5911 /* XXX: TODO */
5912 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5913 }
5914
5915 /* XXX: not implemented on 440 ? */
5916 static void gen_tlbiva(DisasContext *ctx)
5917 {
5918 #if defined(CONFIG_USER_ONLY)
5919 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5920 #else
5921 TCGv t0;
5922 if (unlikely(ctx->pr)) {
5923 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5924 return;
5925 }
5926 t0 = tcg_temp_new();
5927 gen_addr_reg_index(ctx, t0);
5928 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5929 tcg_temp_free(t0);
5930 #endif
5931 }
5932
5933 /* All 405 MAC instructions are translated here */
5934 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5935 int ra, int rb, int rt, int Rc)
5936 {
5937 TCGv t0, t1;
5938
5939 t0 = tcg_temp_local_new();
5940 t1 = tcg_temp_local_new();
5941
5942 switch (opc3 & 0x0D) {
5943 case 0x05:
5944 /* macchw - macchw. - macchwo - macchwo. */
5945 /* macchws - macchws. - macchwso - macchwso. */
5946 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5947 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5948 /* mulchw - mulchw. */
5949 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5950 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5951 tcg_gen_ext16s_tl(t1, t1);
5952 break;
5953 case 0x04:
5954 /* macchwu - macchwu. - macchwuo - macchwuo. */
5955 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5956 /* mulchwu - mulchwu. */
5957 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5958 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5959 tcg_gen_ext16u_tl(t1, t1);
5960 break;
5961 case 0x01:
5962 /* machhw - machhw. - machhwo - machhwo. */
5963 /* machhws - machhws. - machhwso - machhwso. */
5964 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5965 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5966 /* mulhhw - mulhhw. */
5967 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5968 tcg_gen_ext16s_tl(t0, t0);
5969 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5970 tcg_gen_ext16s_tl(t1, t1);
5971 break;
5972 case 0x00:
5973 /* machhwu - machhwu. - machhwuo - machhwuo. */
5974 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5975 /* mulhhwu - mulhhwu. */
5976 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5977 tcg_gen_ext16u_tl(t0, t0);
5978 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5979 tcg_gen_ext16u_tl(t1, t1);
5980 break;
5981 case 0x0D:
5982 /* maclhw - maclhw. - maclhwo - maclhwo. */
5983 /* maclhws - maclhws. - maclhwso - maclhwso. */
5984 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5985 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5986 /* mullhw - mullhw. */
5987 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5988 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5989 break;
5990 case 0x0C:
5991 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5992 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5993 /* mullhwu - mullhwu. */
5994 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5995 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5996 break;
5997 }
5998 if (opc2 & 0x04) {
5999 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
6000 tcg_gen_mul_tl(t1, t0, t1);
6001 if (opc2 & 0x02) {
6002 /* nmultiply-and-accumulate (0x0E) */
6003 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
6004 } else {
6005 /* multiply-and-accumulate (0x0C) */
6006 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
6007 }
6008
6009 if (opc3 & 0x12) {
6010 /* Check overflow and/or saturate */
6011 TCGLabel *l1 = gen_new_label();
6012
6013 if (opc3 & 0x10) {
6014 /* Start with XER OV disabled, the most likely case */
6015 tcg_gen_movi_tl(cpu_ov, 0);
6016 }
6017 if (opc3 & 0x01) {
6018 /* Signed */
6019 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
6020 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
6021 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
6022 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
6023 if (opc3 & 0x02) {
6024 /* Saturate */
6025 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
6026 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
6027 }
6028 } else {
6029 /* Unsigned */
6030 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
6031 if (opc3 & 0x02) {
6032 /* Saturate */
6033 tcg_gen_movi_tl(t0, UINT32_MAX);
6034 }
6035 }
6036 if (opc3 & 0x10) {
6037 /* Check overflow */
6038 tcg_gen_movi_tl(cpu_ov, 1);
6039 tcg_gen_movi_tl(cpu_so, 1);
6040 }
6041 gen_set_label(l1);
6042 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6043 }
6044 } else {
6045 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
6046 }
6047 tcg_temp_free(t0);
6048 tcg_temp_free(t1);
6049 if (unlikely(Rc) != 0) {
6050 /* Update Rc0 */
6051 gen_set_Rc0(ctx, cpu_gpr[rt]);
6052 }
6053 }
6054
6055 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6056 static void glue(gen_, name)(DisasContext *ctx) \
6057 { \
6058 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6059 rD(ctx->opcode), Rc(ctx->opcode)); \
6060 }
6061
6062 /* macchw - macchw. */
6063 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
6064 /* macchwo - macchwo. */
6065 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
6066 /* macchws - macchws. */
6067 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
6068 /* macchwso - macchwso. */
6069 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
6070 /* macchwsu - macchwsu. */
6071 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
6072 /* macchwsuo - macchwsuo. */
6073 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
6074 /* macchwu - macchwu. */
6075 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
6076 /* macchwuo - macchwuo. */
6077 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
6078 /* machhw - machhw. */
6079 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
6080 /* machhwo - machhwo. */
6081 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
6082 /* machhws - machhws. */
6083 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
6084 /* machhwso - machhwso. */
6085 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6086 /* machhwsu - machhwsu. */
6087 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6088 /* machhwsuo - machhwsuo. */
6089 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6090 /* machhwu - machhwu. */
6091 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6092 /* machhwuo - machhwuo. */
6093 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6094 /* maclhw - maclhw. */
6095 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6096 /* maclhwo - maclhwo. */
6097 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6098 /* maclhws - maclhws. */
6099 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6100 /* maclhwso - maclhwso. */
6101 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6102 /* maclhwu - maclhwu. */
6103 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6104 /* maclhwuo - maclhwuo. */
6105 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6106 /* maclhwsu - maclhwsu. */
6107 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6108 /* maclhwsuo - maclhwsuo. */
6109 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6110 /* nmacchw - nmacchw. */
6111 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6112 /* nmacchwo - nmacchwo. */
6113 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6114 /* nmacchws - nmacchws. */
6115 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6116 /* nmacchwso - nmacchwso. */
6117 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6118 /* nmachhw - nmachhw. */
6119 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6120 /* nmachhwo - nmachhwo. */
6121 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6122 /* nmachhws - nmachhws. */
6123 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6124 /* nmachhwso - nmachhwso. */
6125 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6126 /* nmaclhw - nmaclhw. */
6127 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6128 /* nmaclhwo - nmaclhwo. */
6129 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6130 /* nmaclhws - nmaclhws. */
6131 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6132 /* nmaclhwso - nmaclhwso. */
6133 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6134
6135 /* mulchw - mulchw. */
6136 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6137 /* mulchwu - mulchwu. */
6138 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6139 /* mulhhw - mulhhw. */
6140 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6141 /* mulhhwu - mulhhwu. */
6142 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6143 /* mullhw - mullhw. */
6144 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6145 /* mullhwu - mullhwu. */
6146 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6147
6148 /* mfdcr */
6149 static void gen_mfdcr(DisasContext *ctx)
6150 {
6151 #if defined(CONFIG_USER_ONLY)
6152 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6153 #else
6154 TCGv dcrn;
6155 if (unlikely(ctx->pr)) {
6156 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6157 return;
6158 }
6159 /* NIP cannot be restored if the memory exception comes from an helper */
6160 gen_update_nip(ctx, ctx->nip - 4);
6161 dcrn = tcg_const_tl(SPR(ctx->opcode));
6162 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6163 tcg_temp_free(dcrn);
6164 #endif
6165 }
6166
6167 /* mtdcr */
6168 static void gen_mtdcr(DisasContext *ctx)
6169 {
6170 #if defined(CONFIG_USER_ONLY)
6171 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6172 #else
6173 TCGv dcrn;
6174 if (unlikely(ctx->pr)) {
6175 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6176 return;
6177 }
6178 /* NIP cannot be restored if the memory exception comes from an helper */
6179 gen_update_nip(ctx, ctx->nip - 4);
6180 dcrn = tcg_const_tl(SPR(ctx->opcode));
6181 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6182 tcg_temp_free(dcrn);
6183 #endif
6184 }
6185
6186 /* mfdcrx */
6187 /* XXX: not implemented on 440 ? */
6188 static void gen_mfdcrx(DisasContext *ctx)
6189 {
6190 #if defined(CONFIG_USER_ONLY)
6191 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6192 #else
6193 if (unlikely(ctx->pr)) {
6194 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6195 return;
6196 }
6197 /* NIP cannot be restored if the memory exception comes from an helper */
6198 gen_update_nip(ctx, ctx->nip - 4);
6199 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6200 cpu_gpr[rA(ctx->opcode)]);
6201 /* Note: Rc update flag set leads to undefined state of Rc0 */
6202 #endif
6203 }
6204
6205 /* mtdcrx */
6206 /* XXX: not implemented on 440 ? */
6207 static void gen_mtdcrx(DisasContext *ctx)
6208 {
6209 #if defined(CONFIG_USER_ONLY)
6210 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6211 #else
6212 if (unlikely(ctx->pr)) {
6213 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6214 return;
6215 }
6216 /* NIP cannot be restored if the memory exception comes from an helper */
6217 gen_update_nip(ctx, ctx->nip - 4);
6218 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6219 cpu_gpr[rS(ctx->opcode)]);
6220 /* Note: Rc update flag set leads to undefined state of Rc0 */
6221 #endif
6222 }
6223
6224 /* mfdcrux (PPC 460) : user-mode access to DCR */
6225 static void gen_mfdcrux(DisasContext *ctx)
6226 {
6227 /* NIP cannot be restored if the memory exception comes from an helper */
6228 gen_update_nip(ctx, ctx->nip - 4);
6229 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6230 cpu_gpr[rA(ctx->opcode)]);
6231 /* Note: Rc update flag set leads to undefined state of Rc0 */
6232 }
6233
6234 /* mtdcrux (PPC 460) : user-mode access to DCR */
6235 static void gen_mtdcrux(DisasContext *ctx)
6236 {
6237 /* NIP cannot be restored if the memory exception comes from an helper */
6238 gen_update_nip(ctx, ctx->nip - 4);
6239 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6240 cpu_gpr[rS(ctx->opcode)]);
6241 /* Note: Rc update flag set leads to undefined state of Rc0 */
6242 }
6243
6244 /* dccci */
6245 static void gen_dccci(DisasContext *ctx)
6246 {
6247 #if defined(CONFIG_USER_ONLY)
6248 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6249 #else
6250 if (unlikely(ctx->pr)) {
6251 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6252 return;
6253 }
6254 /* interpreted as no-op */
6255 #endif
6256 }
6257
6258 /* dcread */
6259 static void gen_dcread(DisasContext *ctx)
6260 {
6261 #if defined(CONFIG_USER_ONLY)
6262 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6263 #else
6264 TCGv EA, val;
6265 if (unlikely(ctx->pr)) {
6266 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6267 return;
6268 }
6269 gen_set_access_type(ctx, ACCESS_CACHE);
6270 EA = tcg_temp_new();
6271 gen_addr_reg_index(ctx, EA);
6272 val = tcg_temp_new();
6273 gen_qemu_ld32u(ctx, val, EA);
6274 tcg_temp_free(val);
6275 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6276 tcg_temp_free(EA);
6277 #endif
6278 }
6279
6280 /* icbt */
6281 static void gen_icbt_40x(DisasContext *ctx)
6282 {
6283 /* interpreted as no-op */
6284 /* XXX: specification say this is treated as a load by the MMU
6285 * but does not generate any exception
6286 */
6287 }
6288
6289 /* iccci */
6290 static void gen_iccci(DisasContext *ctx)
6291 {
6292 #if defined(CONFIG_USER_ONLY)
6293 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6294 #else
6295 if (unlikely(ctx->pr)) {
6296 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6297 return;
6298 }
6299 /* interpreted as no-op */
6300 #endif
6301 }
6302
6303 /* icread */
6304 static void gen_icread(DisasContext *ctx)
6305 {
6306 #if defined(CONFIG_USER_ONLY)
6307 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6308 #else
6309 if (unlikely(ctx->pr)) {
6310 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6311 return;
6312 }
6313 /* interpreted as no-op */
6314 #endif
6315 }
6316
6317 /* rfci (supervisor only) */
6318 static void gen_rfci_40x(DisasContext *ctx)
6319 {
6320 #if defined(CONFIG_USER_ONLY)
6321 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6322 #else
6323 if (unlikely(ctx->pr)) {
6324 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6325 return;
6326 }
6327 /* Restore CPU state */
6328 gen_helper_40x_rfci(cpu_env);
6329 gen_sync_exception(ctx);
6330 #endif
6331 }
6332
6333 static void gen_rfci(DisasContext *ctx)
6334 {
6335 #if defined(CONFIG_USER_ONLY)
6336 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6337 #else
6338 if (unlikely(ctx->pr)) {
6339 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6340 return;
6341 }
6342 /* Restore CPU state */
6343 gen_helper_rfci(cpu_env);
6344 gen_sync_exception(ctx);
6345 #endif
6346 }
6347
6348 /* BookE specific */
6349
6350 /* XXX: not implemented on 440 ? */
6351 static void gen_rfdi(DisasContext *ctx)
6352 {
6353 #if defined(CONFIG_USER_ONLY)
6354 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6355 #else
6356 if (unlikely(ctx->pr)) {
6357 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6358 return;
6359 }
6360 /* Restore CPU state */
6361 gen_helper_rfdi(cpu_env);
6362 gen_sync_exception(ctx);
6363 #endif
6364 }
6365
6366 /* XXX: not implemented on 440 ? */
6367 static void gen_rfmci(DisasContext *ctx)
6368 {
6369 #if defined(CONFIG_USER_ONLY)
6370 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6371 #else
6372 if (unlikely(ctx->pr)) {
6373 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6374 return;
6375 }
6376 /* Restore CPU state */
6377 gen_helper_rfmci(cpu_env);
6378 gen_sync_exception(ctx);
6379 #endif
6380 }
6381
6382 /* TLB management - PowerPC 405 implementation */
6383
6384 /* tlbre */
6385 static void gen_tlbre_40x(DisasContext *ctx)
6386 {
6387 #if defined(CONFIG_USER_ONLY)
6388 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6389 #else
6390 if (unlikely(ctx->pr)) {
6391 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6392 return;
6393 }
6394 switch (rB(ctx->opcode)) {
6395 case 0:
6396 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6397 cpu_gpr[rA(ctx->opcode)]);
6398 break;
6399 case 1:
6400 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6401 cpu_gpr[rA(ctx->opcode)]);
6402 break;
6403 default:
6404 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6405 break;
6406 }
6407 #endif
6408 }
6409
6410 /* tlbsx - tlbsx. */
6411 static void gen_tlbsx_40x(DisasContext *ctx)
6412 {
6413 #if defined(CONFIG_USER_ONLY)
6414 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6415 #else
6416 TCGv t0;
6417 if (unlikely(ctx->pr)) {
6418 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6419 return;
6420 }
6421 t0 = tcg_temp_new();
6422 gen_addr_reg_index(ctx, t0);
6423 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6424 tcg_temp_free(t0);
6425 if (Rc(ctx->opcode)) {
6426 TCGLabel *l1 = gen_new_label();
6427 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6428 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6429 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6430 gen_set_label(l1);
6431 }
6432 #endif
6433 }
6434
6435 /* tlbwe */
6436 static void gen_tlbwe_40x(DisasContext *ctx)
6437 {
6438 #if defined(CONFIG_USER_ONLY)
6439 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6440 #else
6441 if (unlikely(ctx->pr)) {
6442 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6443 return;
6444 }
6445 switch (rB(ctx->opcode)) {
6446 case 0:
6447 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6448 cpu_gpr[rS(ctx->opcode)]);
6449 break;
6450 case 1:
6451 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6452 cpu_gpr[rS(ctx->opcode)]);
6453 break;
6454 default:
6455 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6456 break;
6457 }
6458 #endif
6459 }
6460
6461 /* TLB management - PowerPC 440 implementation */
6462
6463 /* tlbre */
6464 static void gen_tlbre_440(DisasContext *ctx)
6465 {
6466 #if defined(CONFIG_USER_ONLY)
6467 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6468 #else
6469 if (unlikely(ctx->pr)) {
6470 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6471 return;
6472 }
6473 switch (rB(ctx->opcode)) {
6474 case 0:
6475 case 1:
6476 case 2:
6477 {
6478 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6479 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6480 t0, cpu_gpr[rA(ctx->opcode)]);
6481 tcg_temp_free_i32(t0);
6482 }
6483 break;
6484 default:
6485 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6486 break;
6487 }
6488 #endif
6489 }
6490
6491 /* tlbsx - tlbsx. */
6492 static void gen_tlbsx_440(DisasContext *ctx)
6493 {
6494 #if defined(CONFIG_USER_ONLY)
6495 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6496 #else
6497 TCGv t0;
6498 if (unlikely(ctx->pr)) {
6499 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6500 return;
6501 }
6502 t0 = tcg_temp_new();
6503 gen_addr_reg_index(ctx, t0);
6504 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6505 tcg_temp_free(t0);
6506 if (Rc(ctx->opcode)) {
6507 TCGLabel *l1 = gen_new_label();
6508 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6509 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6510 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6511 gen_set_label(l1);
6512 }
6513 #endif
6514 }
6515
6516 /* tlbwe */
6517 static void gen_tlbwe_440(DisasContext *ctx)
6518 {
6519 #if defined(CONFIG_USER_ONLY)
6520 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6521 #else
6522 if (unlikely(ctx->pr)) {
6523 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6524 return;
6525 }
6526 switch (rB(ctx->opcode)) {
6527 case 0:
6528 case 1:
6529 case 2:
6530 {
6531 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6532 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6533 cpu_gpr[rS(ctx->opcode)]);
6534 tcg_temp_free_i32(t0);
6535 }
6536 break;
6537 default:
6538 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6539 break;
6540 }
6541 #endif
6542 }
6543
6544 /* TLB management - PowerPC BookE 2.06 implementation */
6545
6546 /* tlbre */
6547 static void gen_tlbre_booke206(DisasContext *ctx)
6548 {
6549 #if defined(CONFIG_USER_ONLY)
6550 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6551 #else
6552 if (unlikely(ctx->pr)) {
6553 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6554 return;
6555 }
6556
6557 gen_helper_booke206_tlbre(cpu_env);
6558 #endif
6559 }
6560
6561 /* tlbsx - tlbsx. */
6562 static void gen_tlbsx_booke206(DisasContext *ctx)
6563 {
6564 #if defined(CONFIG_USER_ONLY)
6565 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6566 #else
6567 TCGv t0;
6568 if (unlikely(ctx->pr)) {
6569 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6570 return;
6571 }
6572
6573 if (rA(ctx->opcode)) {
6574 t0 = tcg_temp_new();
6575 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6576 } else {
6577 t0 = tcg_const_tl(0);
6578 }
6579
6580 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6581 gen_helper_booke206_tlbsx(cpu_env, t0);
6582 tcg_temp_free(t0);
6583 #endif
6584 }
6585
6586 /* tlbwe */
6587 static void gen_tlbwe_booke206(DisasContext *ctx)
6588 {
6589 #if defined(CONFIG_USER_ONLY)
6590 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6591 #else
6592 if (unlikely(ctx->pr)) {
6593 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6594 return;
6595 }
6596 gen_update_nip(ctx, ctx->nip - 4);
6597 gen_helper_booke206_tlbwe(cpu_env);
6598 #endif
6599 }
6600
6601 static void gen_tlbivax_booke206(DisasContext *ctx)
6602 {
6603 #if defined(CONFIG_USER_ONLY)
6604 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6605 #else
6606 TCGv t0;
6607 if (unlikely(ctx->pr)) {
6608 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6609 return;
6610 }
6611
6612 t0 = tcg_temp_new();
6613 gen_addr_reg_index(ctx, t0);
6614
6615 gen_helper_booke206_tlbivax(cpu_env, t0);
6616 tcg_temp_free(t0);
6617 #endif
6618 }
6619
6620 static void gen_tlbilx_booke206(DisasContext *ctx)
6621 {
6622 #if defined(CONFIG_USER_ONLY)
6623 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6624 #else
6625 TCGv t0;
6626 if (unlikely(ctx->pr)) {
6627 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6628 return;
6629 }
6630
6631 t0 = tcg_temp_new();
6632 gen_addr_reg_index(ctx, t0);
6633
6634 switch((ctx->opcode >> 21) & 0x3) {
6635 case 0:
6636 gen_helper_booke206_tlbilx0(cpu_env, t0);
6637 break;
6638 case 1:
6639 gen_helper_booke206_tlbilx1(cpu_env, t0);
6640 break;
6641 case 3:
6642 gen_helper_booke206_tlbilx3(cpu_env, t0);
6643 break;
6644 default:
6645 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6646 break;
6647 }
6648
6649 tcg_temp_free(t0);
6650 #endif
6651 }
6652
6653
6654 /* wrtee */
6655 static void gen_wrtee(DisasContext *ctx)
6656 {
6657 #if defined(CONFIG_USER_ONLY)
6658 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6659 #else
6660 TCGv t0;
6661 if (unlikely(ctx->pr)) {
6662 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6663 return;
6664 }
6665 t0 = tcg_temp_new();
6666 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6667 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6668 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6669 tcg_temp_free(t0);
6670 /* Stop translation to have a chance to raise an exception
6671 * if we just set msr_ee to 1
6672 */
6673 gen_stop_exception(ctx);
6674 #endif
6675 }
6676
6677 /* wrteei */
6678 static void gen_wrteei(DisasContext *ctx)
6679 {
6680 #if defined(CONFIG_USER_ONLY)
6681 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6682 #else
6683 if (unlikely(ctx->pr)) {
6684 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6685 return;
6686 }
6687 if (ctx->opcode & 0x00008000) {
6688 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6689 /* Stop translation to have a chance to raise an exception */
6690 gen_stop_exception(ctx);
6691 } else {
6692 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6693 }
6694 #endif
6695 }
6696
6697 /* PowerPC 440 specific instructions */
6698
6699 /* dlmzb */
6700 static void gen_dlmzb(DisasContext *ctx)
6701 {
6702 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6703 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6704 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6705 tcg_temp_free_i32(t0);
6706 }
6707
6708 /* mbar replaces eieio on 440 */
6709 static void gen_mbar(DisasContext *ctx)
6710 {
6711 /* interpreted as no-op */
6712 }
6713
6714 /* msync replaces sync on 440 */
6715 static void gen_msync_4xx(DisasContext *ctx)
6716 {
6717 /* interpreted as no-op */
6718 }
6719
6720 /* icbt */
6721 static void gen_icbt_440(DisasContext *ctx)
6722 {
6723 /* interpreted as no-op */
6724 /* XXX: specification say this is treated as a load by the MMU
6725 * but does not generate any exception
6726 */
6727 }
6728
6729 /* Embedded.Processor Control */
6730
6731 static void gen_msgclr(DisasContext *ctx)
6732 {
6733 #if defined(CONFIG_USER_ONLY)
6734 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6735 #else
6736 if (unlikely(ctx->pr)) {
6737 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6738 return;
6739 }
6740
6741 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6742 #endif
6743 }
6744
6745 static void gen_msgsnd(DisasContext *ctx)
6746 {
6747 #if defined(CONFIG_USER_ONLY)
6748 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6749 #else
6750 if (unlikely(ctx->pr)) {
6751 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6752 return;
6753 }
6754
6755 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6756 #endif
6757 }
6758
6759 /*** Altivec vector extension ***/
6760 /* Altivec registers moves */
6761
6762 static inline TCGv_ptr gen_avr_ptr(int reg)
6763 {
6764 TCGv_ptr r = tcg_temp_new_ptr();
6765 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6766 return r;
6767 }
6768
6769 #define GEN_VR_LDX(name, opc2, opc3) \
6770 static void glue(gen_, name)(DisasContext *ctx) \
6771 { \
6772 TCGv EA; \
6773 if (unlikely(!ctx->altivec_enabled)) { \
6774 gen_exception(ctx, POWERPC_EXCP_VPU); \
6775 return; \
6776 } \
6777 gen_set_access_type(ctx, ACCESS_INT); \
6778 EA = tcg_temp_new(); \
6779 gen_addr_reg_index(ctx, EA); \
6780 tcg_gen_andi_tl(EA, EA, ~0xf); \
6781 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6782 64-bit byteswap already. */ \
6783 if (ctx->le_mode) { \
6784 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6785 tcg_gen_addi_tl(EA, EA, 8); \
6786 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6787 } else { \
6788 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6789 tcg_gen_addi_tl(EA, EA, 8); \
6790 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6791 } \
6792 tcg_temp_free(EA); \
6793 }
6794
6795 #define GEN_VR_STX(name, opc2, opc3) \
6796 static void gen_st##name(DisasContext *ctx) \
6797 { \
6798 TCGv EA; \
6799 if (unlikely(!ctx->altivec_enabled)) { \
6800 gen_exception(ctx, POWERPC_EXCP_VPU); \
6801 return; \
6802 } \
6803 gen_set_access_type(ctx, ACCESS_INT); \
6804 EA = tcg_temp_new(); \
6805 gen_addr_reg_index(ctx, EA); \
6806 tcg_gen_andi_tl(EA, EA, ~0xf); \
6807 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6808 64-bit byteswap already. */ \
6809 if (ctx->le_mode) { \
6810 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6811 tcg_gen_addi_tl(EA, EA, 8); \
6812 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6813 } else { \
6814 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6815 tcg_gen_addi_tl(EA, EA, 8); \
6816 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6817 } \
6818 tcg_temp_free(EA); \
6819 }
6820
6821 #define GEN_VR_LVE(name, opc2, opc3, size) \
6822 static void gen_lve##name(DisasContext *ctx) \
6823 { \
6824 TCGv EA; \
6825 TCGv_ptr rs; \
6826 if (unlikely(!ctx->altivec_enabled)) { \
6827 gen_exception(ctx, POWERPC_EXCP_VPU); \
6828 return; \
6829 } \
6830 gen_set_access_type(ctx, ACCESS_INT); \
6831 EA = tcg_temp_new(); \
6832 gen_addr_reg_index(ctx, EA); \
6833 if (size > 1) { \
6834 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6835 } \
6836 rs = gen_avr_ptr(rS(ctx->opcode)); \
6837 gen_helper_lve##name(cpu_env, rs, EA); \
6838 tcg_temp_free(EA); \
6839 tcg_temp_free_ptr(rs); \
6840 }
6841
6842 #define GEN_VR_STVE(name, opc2, opc3, size) \
6843 static void gen_stve##name(DisasContext *ctx) \
6844 { \
6845 TCGv EA; \
6846 TCGv_ptr rs; \
6847 if (unlikely(!ctx->altivec_enabled)) { \
6848 gen_exception(ctx, POWERPC_EXCP_VPU); \
6849 return; \
6850 } \
6851 gen_set_access_type(ctx, ACCESS_INT); \
6852 EA = tcg_temp_new(); \
6853 gen_addr_reg_index(ctx, EA); \
6854 if (size > 1) { \
6855 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6856 } \
6857 rs = gen_avr_ptr(rS(ctx->opcode)); \
6858 gen_helper_stve##name(cpu_env, rs, EA); \
6859 tcg_temp_free(EA); \
6860 tcg_temp_free_ptr(rs); \
6861 }
6862
6863 GEN_VR_LDX(lvx, 0x07, 0x03);
6864 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6865 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6866
6867 GEN_VR_LVE(bx, 0x07, 0x00, 1);
6868 GEN_VR_LVE(hx, 0x07, 0x01, 2);
6869 GEN_VR_LVE(wx, 0x07, 0x02, 4);
6870
6871 GEN_VR_STX(svx, 0x07, 0x07);
6872 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6873 GEN_VR_STX(svxl, 0x07, 0x0F);
6874
6875 GEN_VR_STVE(bx, 0x07, 0x04, 1);
6876 GEN_VR_STVE(hx, 0x07, 0x05, 2);
6877 GEN_VR_STVE(wx, 0x07, 0x06, 4);
6878
6879 static void gen_lvsl(DisasContext *ctx)
6880 {
6881 TCGv_ptr rd;
6882 TCGv EA;
6883 if (unlikely(!ctx->altivec_enabled)) {
6884 gen_exception(ctx, POWERPC_EXCP_VPU);
6885 return;
6886 }
6887 EA = tcg_temp_new();
6888 gen_addr_reg_index(ctx, EA);
6889 rd = gen_avr_ptr(rD(ctx->opcode));
6890 gen_helper_lvsl(rd, EA);
6891 tcg_temp_free(EA);
6892 tcg_temp_free_ptr(rd);
6893 }
6894
6895 static void gen_lvsr(DisasContext *ctx)
6896 {
6897 TCGv_ptr rd;
6898 TCGv EA;
6899 if (unlikely(!ctx->altivec_enabled)) {
6900 gen_exception(ctx, POWERPC_EXCP_VPU);
6901 return;
6902 }
6903 EA = tcg_temp_new();
6904 gen_addr_reg_index(ctx, EA);
6905 rd = gen_avr_ptr(rD(ctx->opcode));
6906 gen_helper_lvsr(rd, EA);
6907 tcg_temp_free(EA);
6908 tcg_temp_free_ptr(rd);
6909 }
6910
6911 static void gen_mfvscr(DisasContext *ctx)
6912 {
6913 TCGv_i32 t;
6914 if (unlikely(!ctx->altivec_enabled)) {
6915 gen_exception(ctx, POWERPC_EXCP_VPU);
6916 return;
6917 }
6918 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6919 t = tcg_temp_new_i32();
6920 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6921 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6922 tcg_temp_free_i32(t);
6923 }
6924
6925 static void gen_mtvscr(DisasContext *ctx)
6926 {
6927 TCGv_ptr p;
6928 if (unlikely(!ctx->altivec_enabled)) {
6929 gen_exception(ctx, POWERPC_EXCP_VPU);
6930 return;
6931 }
6932 p = gen_avr_ptr(rB(ctx->opcode));
6933 gen_helper_mtvscr(cpu_env, p);
6934 tcg_temp_free_ptr(p);
6935 }
6936
6937 /* Logical operations */
6938 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6939 static void glue(gen_, name)(DisasContext *ctx) \
6940 { \
6941 if (unlikely(!ctx->altivec_enabled)) { \
6942 gen_exception(ctx, POWERPC_EXCP_VPU); \
6943 return; \
6944 } \
6945 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6946 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6947 }
6948
6949 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6950 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6951 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6952 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6953 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6954 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6955 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6956 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
6957
6958 #define GEN_VXFORM(name, opc2, opc3) \
6959 static void glue(gen_, name)(DisasContext *ctx) \
6960 { \
6961 TCGv_ptr ra, rb, rd; \
6962 if (unlikely(!ctx->altivec_enabled)) { \
6963 gen_exception(ctx, POWERPC_EXCP_VPU); \
6964 return; \
6965 } \
6966 ra = gen_avr_ptr(rA(ctx->opcode)); \
6967 rb = gen_avr_ptr(rB(ctx->opcode)); \
6968 rd = gen_avr_ptr(rD(ctx->opcode)); \
6969 gen_helper_##name (rd, ra, rb); \
6970 tcg_temp_free_ptr(ra); \
6971 tcg_temp_free_ptr(rb); \
6972 tcg_temp_free_ptr(rd); \
6973 }
6974
6975 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6976 static void glue(gen_, name)(DisasContext *ctx) \
6977 { \
6978 TCGv_ptr ra, rb, rd; \
6979 if (unlikely(!ctx->altivec_enabled)) { \
6980 gen_exception(ctx, POWERPC_EXCP_VPU); \
6981 return; \
6982 } \
6983 ra = gen_avr_ptr(rA(ctx->opcode)); \
6984 rb = gen_avr_ptr(rB(ctx->opcode)); \
6985 rd = gen_avr_ptr(rD(ctx->opcode)); \
6986 gen_helper_##name(cpu_env, rd, ra, rb); \
6987 tcg_temp_free_ptr(ra); \
6988 tcg_temp_free_ptr(rb); \
6989 tcg_temp_free_ptr(rd); \
6990 }
6991
6992 #define GEN_VXFORM3(name, opc2, opc3) \
6993 static void glue(gen_, name)(DisasContext *ctx) \
6994 { \
6995 TCGv_ptr ra, rb, rc, rd; \
6996 if (unlikely(!ctx->altivec_enabled)) { \
6997 gen_exception(ctx, POWERPC_EXCP_VPU); \
6998 return; \
6999 } \
7000 ra = gen_avr_ptr(rA(ctx->opcode)); \
7001 rb = gen_avr_ptr(rB(ctx->opcode)); \
7002 rc = gen_avr_ptr(rC(ctx->opcode)); \
7003 rd = gen_avr_ptr(rD(ctx->opcode)); \
7004 gen_helper_##name(rd, ra, rb, rc); \
7005 tcg_temp_free_ptr(ra); \
7006 tcg_temp_free_ptr(rb); \
7007 tcg_temp_free_ptr(rc); \
7008 tcg_temp_free_ptr(rd); \
7009 }
7010
7011 /*
7012 * Support for Altivec instruction pairs that use bit 31 (Rc) as
7013 * an opcode bit. In general, these pairs come from different
7014 * versions of the ISA, so we must also support a pair of flags for
7015 * each instruction.
7016 */
7017 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7018 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7019 { \
7020 if ((Rc(ctx->opcode) == 0) && \
7021 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7022 gen_##name0(ctx); \
7023 } else if ((Rc(ctx->opcode) == 1) && \
7024 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7025 gen_##name1(ctx); \
7026 } else { \
7027 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7028 } \
7029 }
7030
7031 GEN_VXFORM(vaddubm, 0, 0);
7032 GEN_VXFORM(vadduhm, 0, 1);
7033 GEN_VXFORM(vadduwm, 0, 2);
7034 GEN_VXFORM(vaddudm, 0, 3);
7035 GEN_VXFORM(vsububm, 0, 16);
7036 GEN_VXFORM(vsubuhm, 0, 17);
7037 GEN_VXFORM(vsubuwm, 0, 18);
7038 GEN_VXFORM(vsubudm, 0, 19);
7039 GEN_VXFORM(vmaxub, 1, 0);
7040 GEN_VXFORM(vmaxuh, 1, 1);
7041 GEN_VXFORM(vmaxuw, 1, 2);
7042 GEN_VXFORM(vmaxud, 1, 3);
7043 GEN_VXFORM(vmaxsb, 1, 4);
7044 GEN_VXFORM(vmaxsh, 1, 5);
7045 GEN_VXFORM(vmaxsw, 1, 6);
7046 GEN_VXFORM(vmaxsd, 1, 7);
7047 GEN_VXFORM(vminub, 1, 8);
7048 GEN_VXFORM(vminuh, 1, 9);
7049 GEN_VXFORM(vminuw, 1, 10);
7050 GEN_VXFORM(vminud, 1, 11);
7051 GEN_VXFORM(vminsb, 1, 12);
7052 GEN_VXFORM(vminsh, 1, 13);
7053 GEN_VXFORM(vminsw, 1, 14);
7054 GEN_VXFORM(vminsd, 1, 15);
7055 GEN_VXFORM(vavgub, 1, 16);
7056 GEN_VXFORM(vavguh, 1, 17);
7057 GEN_VXFORM(vavguw, 1, 18);
7058 GEN_VXFORM(vavgsb, 1, 20);
7059 GEN_VXFORM(vavgsh, 1, 21);
7060 GEN_VXFORM(vavgsw, 1, 22);
7061 GEN_VXFORM(vmrghb, 6, 0);
7062 GEN_VXFORM(vmrghh, 6, 1);
7063 GEN_VXFORM(vmrghw, 6, 2);
7064 GEN_VXFORM(vmrglb, 6, 4);
7065 GEN_VXFORM(vmrglh, 6, 5);
7066 GEN_VXFORM(vmrglw, 6, 6);
7067
7068 static void gen_vmrgew(DisasContext *ctx)
7069 {
7070 TCGv_i64 tmp;
7071 int VT, VA, VB;
7072 if (unlikely(!ctx->altivec_enabled)) {
7073 gen_exception(ctx, POWERPC_EXCP_VPU);
7074 return;
7075 }
7076 VT = rD(ctx->opcode);
7077 VA = rA(ctx->opcode);
7078 VB = rB(ctx->opcode);
7079 tmp = tcg_temp_new_i64();
7080 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7081 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7082 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7083 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7084 tcg_temp_free_i64(tmp);
7085 }
7086
7087 static void gen_vmrgow(DisasContext *ctx)
7088 {
7089 int VT, VA, VB;
7090 if (unlikely(!ctx->altivec_enabled)) {
7091 gen_exception(ctx, POWERPC_EXCP_VPU);
7092 return;
7093 }
7094 VT = rD(ctx->opcode);
7095 VA = rA(ctx->opcode);
7096 VB = rB(ctx->opcode);
7097
7098 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7099 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7100 }
7101
7102 GEN_VXFORM(vmuloub, 4, 0);
7103 GEN_VXFORM(vmulouh, 4, 1);
7104 GEN_VXFORM(vmulouw, 4, 2);
7105 GEN_VXFORM(vmuluwm, 4, 2);
7106 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7107 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7108 GEN_VXFORM(vmulosb, 4, 4);
7109 GEN_VXFORM(vmulosh, 4, 5);
7110 GEN_VXFORM(vmulosw, 4, 6);
7111 GEN_VXFORM(vmuleub, 4, 8);
7112 GEN_VXFORM(vmuleuh, 4, 9);
7113 GEN_VXFORM(vmuleuw, 4, 10);
7114 GEN_VXFORM(vmulesb, 4, 12);
7115 GEN_VXFORM(vmulesh, 4, 13);
7116 GEN_VXFORM(vmulesw, 4, 14);
7117 GEN_VXFORM(vslb, 2, 4);
7118 GEN_VXFORM(vslh, 2, 5);
7119 GEN_VXFORM(vslw, 2, 6);
7120 GEN_VXFORM(vsld, 2, 23);
7121 GEN_VXFORM(vsrb, 2, 8);
7122 GEN_VXFORM(vsrh, 2, 9);
7123 GEN_VXFORM(vsrw, 2, 10);
7124 GEN_VXFORM(vsrd, 2, 27);
7125 GEN_VXFORM(vsrab, 2, 12);
7126 GEN_VXFORM(vsrah, 2, 13);
7127 GEN_VXFORM(vsraw, 2, 14);
7128 GEN_VXFORM(vsrad, 2, 15);
7129 GEN_VXFORM(vslo, 6, 16);
7130 GEN_VXFORM(vsro, 6, 17);
7131 GEN_VXFORM(vaddcuw, 0, 6);
7132 GEN_VXFORM(vsubcuw, 0, 22);
7133 GEN_VXFORM_ENV(vaddubs, 0, 8);
7134 GEN_VXFORM_ENV(vadduhs, 0, 9);
7135 GEN_VXFORM_ENV(vadduws, 0, 10);
7136 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7137 GEN_VXFORM_ENV(vaddshs, 0, 13);
7138 GEN_VXFORM_ENV(vaddsws, 0, 14);
7139 GEN_VXFORM_ENV(vsububs, 0, 24);
7140 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7141 GEN_VXFORM_ENV(vsubuws, 0, 26);
7142 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7143 GEN_VXFORM_ENV(vsubshs, 0, 29);
7144 GEN_VXFORM_ENV(vsubsws, 0, 30);
7145 GEN_VXFORM(vadduqm, 0, 4);
7146 GEN_VXFORM(vaddcuq, 0, 5);
7147 GEN_VXFORM3(vaddeuqm, 30, 0);
7148 GEN_VXFORM3(vaddecuq, 30, 0);
7149 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7150 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7151 GEN_VXFORM(vsubuqm, 0, 20);
7152 GEN_VXFORM(vsubcuq, 0, 21);
7153 GEN_VXFORM3(vsubeuqm, 31, 0);
7154 GEN_VXFORM3(vsubecuq, 31, 0);
7155 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7156 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7157 GEN_VXFORM(vrlb, 2, 0);
7158 GEN_VXFORM(vrlh, 2, 1);
7159 GEN_VXFORM(vrlw, 2, 2);
7160 GEN_VXFORM(vrld, 2, 3);
7161 GEN_VXFORM(vsl, 2, 7);
7162 GEN_VXFORM(vsr, 2, 11);
7163 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7164 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7165 GEN_VXFORM_ENV(vpkudum, 7, 17);
7166 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7167 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7168 GEN_VXFORM_ENV(vpkudus, 7, 19);
7169 GEN_VXFORM_ENV(vpkshus, 7, 4);
7170 GEN_VXFORM_ENV(vpkswus, 7, 5);
7171 GEN_VXFORM_ENV(vpksdus, 7, 21);
7172 GEN_VXFORM_ENV(vpkshss, 7, 6);
7173 GEN_VXFORM_ENV(vpkswss, 7, 7);
7174 GEN_VXFORM_ENV(vpksdss, 7, 23);
7175 GEN_VXFORM(vpkpx, 7, 12);
7176 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7177 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7178 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7179 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7180 GEN_VXFORM_ENV(vsumsws, 4, 30);
7181 GEN_VXFORM_ENV(vaddfp, 5, 0);
7182 GEN_VXFORM_ENV(vsubfp, 5, 1);
7183 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7184 GEN_VXFORM_ENV(vminfp, 5, 17);
7185
7186 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7187 static void glue(gen_, name)(DisasContext *ctx) \
7188 { \
7189 TCGv_ptr ra, rb, rd; \
7190 if (unlikely(!ctx->altivec_enabled)) { \
7191 gen_exception(ctx, POWERPC_EXCP_VPU); \
7192 return; \
7193 } \
7194 ra = gen_avr_ptr(rA(ctx->opcode)); \
7195 rb = gen_avr_ptr(rB(ctx->opcode)); \
7196 rd = gen_avr_ptr(rD(ctx->opcode)); \
7197 gen_helper_##opname(cpu_env, rd, ra, rb); \
7198 tcg_temp_free_ptr(ra); \
7199 tcg_temp_free_ptr(rb); \
7200 tcg_temp_free_ptr(rd); \
7201 }
7202
7203 #define GEN_VXRFORM(name, opc2, opc3) \
7204 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7205 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7206
7207 /*
7208 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7209 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7210 * come from different versions of the ISA, so we must also support a
7211 * pair of flags for each instruction.
7212 */
7213 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7214 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7215 { \
7216 if ((Rc(ctx->opcode) == 0) && \
7217 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7218 if (Rc21(ctx->opcode) == 0) { \
7219 gen_##name0(ctx); \
7220 } else { \
7221 gen_##name0##_(ctx); \
7222 } \
7223 } else if ((Rc(ctx->opcode) == 1) && \
7224 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7225 if (Rc21(ctx->opcode) == 0) { \
7226 gen_##name1(ctx); \
7227 } else { \
7228 gen_##name1##_(ctx); \
7229 } \
7230 } else { \
7231 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7232 } \
7233 }
7234
7235 GEN_VXRFORM(vcmpequb, 3, 0)
7236 GEN_VXRFORM(vcmpequh, 3, 1)
7237 GEN_VXRFORM(vcmpequw, 3, 2)
7238 GEN_VXRFORM(vcmpequd, 3, 3)
7239 GEN_VXRFORM(vcmpgtsb, 3, 12)
7240 GEN_VXRFORM(vcmpgtsh, 3, 13)
7241 GEN_VXRFORM(vcmpgtsw, 3, 14)
7242 GEN_VXRFORM(vcmpgtsd, 3, 15)
7243 GEN_VXRFORM(vcmpgtub, 3, 8)
7244 GEN_VXRFORM(vcmpgtuh, 3, 9)
7245 GEN_VXRFORM(vcmpgtuw, 3, 10)
7246 GEN_VXRFORM(vcmpgtud, 3, 11)
7247 GEN_VXRFORM(vcmpeqfp, 3, 3)
7248 GEN_VXRFORM(vcmpgefp, 3, 7)
7249 GEN_VXRFORM(vcmpgtfp, 3, 11)
7250 GEN_VXRFORM(vcmpbfp, 3, 15)
7251
7252 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7253 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7254 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7255 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7256 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7257 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7258
7259 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7260 static void glue(gen_, name)(DisasContext *ctx) \
7261 { \
7262 TCGv_ptr rd; \
7263 TCGv_i32 simm; \
7264 if (unlikely(!ctx->altivec_enabled)) { \
7265 gen_exception(ctx, POWERPC_EXCP_VPU); \
7266 return; \
7267 } \
7268 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7269 rd = gen_avr_ptr(rD(ctx->opcode)); \
7270 gen_helper_##name (rd, simm); \
7271 tcg_temp_free_i32(simm); \
7272 tcg_temp_free_ptr(rd); \
7273 }
7274
7275 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7276 GEN_VXFORM_SIMM(vspltish, 6, 13);
7277 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7278
7279 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7280 static void glue(gen_, name)(DisasContext *ctx) \
7281 { \
7282 TCGv_ptr rb, rd; \
7283 if (unlikely(!ctx->altivec_enabled)) { \
7284 gen_exception(ctx, POWERPC_EXCP_VPU); \
7285 return; \
7286 } \
7287 rb = gen_avr_ptr(rB(ctx->opcode)); \
7288 rd = gen_avr_ptr(rD(ctx->opcode)); \
7289 gen_helper_##name (rd, rb); \
7290 tcg_temp_free_ptr(rb); \
7291 tcg_temp_free_ptr(rd); \
7292 }
7293
7294 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7295 static void glue(gen_, name)(DisasContext *ctx) \
7296 { \
7297 TCGv_ptr rb, rd; \
7298 \
7299 if (unlikely(!ctx->altivec_enabled)) { \
7300 gen_exception(ctx, POWERPC_EXCP_VPU); \
7301 return; \
7302 } \
7303 rb = gen_avr_ptr(rB(ctx->opcode)); \
7304 rd = gen_avr_ptr(rD(ctx->opcode)); \
7305 gen_helper_##name(cpu_env, rd, rb); \
7306 tcg_temp_free_ptr(rb); \
7307 tcg_temp_free_ptr(rd); \
7308 }
7309
7310 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7311 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7312 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7313 GEN_VXFORM_NOA(vupklsb, 7, 10);
7314 GEN_VXFORM_NOA(vupklsh, 7, 11);
7315 GEN_VXFORM_NOA(vupklsw, 7, 27);
7316 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7317 GEN_VXFORM_NOA(vupklpx, 7, 15);
7318 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7319 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7320 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7321 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7322 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7323 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
7324 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7325 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
7326
7327 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7328 static void glue(gen_, name)(DisasContext *ctx) \
7329 { \
7330 TCGv_ptr rd; \
7331 TCGv_i32 simm; \
7332 if (unlikely(!ctx->altivec_enabled)) { \
7333 gen_exception(ctx, POWERPC_EXCP_VPU); \
7334 return; \
7335 } \
7336 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7337 rd = gen_avr_ptr(rD(ctx->opcode)); \
7338 gen_helper_##name (rd, simm); \
7339 tcg_temp_free_i32(simm); \
7340 tcg_temp_free_ptr(rd); \
7341 }
7342
7343 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7344 static void glue(gen_, name)(DisasContext *ctx) \
7345 { \
7346 TCGv_ptr rb, rd; \
7347 TCGv_i32 uimm; \
7348 if (unlikely(!ctx->altivec_enabled)) { \
7349 gen_exception(ctx, POWERPC_EXCP_VPU); \
7350 return; \
7351 } \
7352 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7353 rb = gen_avr_ptr(rB(ctx->opcode)); \
7354 rd = gen_avr_ptr(rD(ctx->opcode)); \
7355 gen_helper_##name (rd, rb, uimm); \
7356 tcg_temp_free_i32(uimm); \
7357 tcg_temp_free_ptr(rb); \
7358 tcg_temp_free_ptr(rd); \
7359 }
7360
7361 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7362 static void glue(gen_, name)(DisasContext *ctx) \
7363 { \
7364 TCGv_ptr rb, rd; \
7365 TCGv_i32 uimm; \
7366 \
7367 if (unlikely(!ctx->altivec_enabled)) { \
7368 gen_exception(ctx, POWERPC_EXCP_VPU); \
7369 return; \
7370 } \
7371 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7372 rb = gen_avr_ptr(rB(ctx->opcode)); \
7373 rd = gen_avr_ptr(rD(ctx->opcode)); \
7374 gen_helper_##name(cpu_env, rd, rb, uimm); \
7375 tcg_temp_free_i32(uimm); \
7376 tcg_temp_free_ptr(rb); \
7377 tcg_temp_free_ptr(rd); \
7378 }
7379
7380 GEN_VXFORM_UIMM(vspltb, 6, 8);
7381 GEN_VXFORM_UIMM(vsplth, 6, 9);
7382 GEN_VXFORM_UIMM(vspltw, 6, 10);
7383 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7384 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7385 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7386 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7387
7388 static void gen_vsldoi(DisasContext *ctx)
7389 {
7390 TCGv_ptr ra, rb, rd;
7391 TCGv_i32 sh;
7392 if (unlikely(!ctx->altivec_enabled)) {
7393 gen_exception(ctx, POWERPC_EXCP_VPU);
7394 return;
7395 }
7396 ra = gen_avr_ptr(rA(ctx->opcode));
7397 rb = gen_avr_ptr(rB(ctx->opcode));
7398 rd = gen_avr_ptr(rD(ctx->opcode));
7399 sh = tcg_const_i32(VSH(ctx->opcode));
7400 gen_helper_vsldoi (rd, ra, rb, sh);
7401 tcg_temp_free_ptr(ra);
7402 tcg_temp_free_ptr(rb);
7403 tcg_temp_free_ptr(rd);
7404 tcg_temp_free_i32(sh);
7405 }
7406
7407 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7408 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7409 { \
7410 TCGv_ptr ra, rb, rc, rd; \
7411 if (unlikely(!ctx->altivec_enabled)) { \
7412 gen_exception(ctx, POWERPC_EXCP_VPU); \
7413 return; \
7414 } \
7415 ra = gen_avr_ptr(rA(ctx->opcode)); \
7416 rb = gen_avr_ptr(rB(ctx->opcode)); \
7417 rc = gen_avr_ptr(rC(ctx->opcode)); \
7418 rd = gen_avr_ptr(rD(ctx->opcode)); \
7419 if (Rc(ctx->opcode)) { \
7420 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7421 } else { \
7422 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7423 } \
7424 tcg_temp_free_ptr(ra); \
7425 tcg_temp_free_ptr(rb); \
7426 tcg_temp_free_ptr(rc); \
7427 tcg_temp_free_ptr(rd); \
7428 }
7429
7430 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7431
7432 static void gen_vmladduhm(DisasContext *ctx)
7433 {
7434 TCGv_ptr ra, rb, rc, rd;
7435 if (unlikely(!ctx->altivec_enabled)) {
7436 gen_exception(ctx, POWERPC_EXCP_VPU);
7437 return;
7438 }
7439 ra = gen_avr_ptr(rA(ctx->opcode));
7440 rb = gen_avr_ptr(rB(ctx->opcode));
7441 rc = gen_avr_ptr(rC(ctx->opcode));
7442 rd = gen_avr_ptr(rD(ctx->opcode));
7443 gen_helper_vmladduhm(rd, ra, rb, rc);
7444 tcg_temp_free_ptr(ra);
7445 tcg_temp_free_ptr(rb);
7446 tcg_temp_free_ptr(rc);
7447 tcg_temp_free_ptr(rd);
7448 }
7449
7450 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7451 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7452 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7453 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7454 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7455
7456 GEN_VXFORM_NOA(vclzb, 1, 28)
7457 GEN_VXFORM_NOA(vclzh, 1, 29)
7458 GEN_VXFORM_NOA(vclzw, 1, 30)
7459 GEN_VXFORM_NOA(vclzd, 1, 31)
7460 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7461 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7462 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7463 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7464 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7465 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7466 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7467 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7468 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7469 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7470 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7471 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7472 GEN_VXFORM(vbpermq, 6, 21);
7473 GEN_VXFORM_NOA(vgbbd, 6, 20);
7474 GEN_VXFORM(vpmsumb, 4, 16)
7475 GEN_VXFORM(vpmsumh, 4, 17)
7476 GEN_VXFORM(vpmsumw, 4, 18)
7477 GEN_VXFORM(vpmsumd, 4, 19)
7478
7479 #define GEN_BCD(op) \
7480 static void gen_##op(DisasContext *ctx) \
7481 { \
7482 TCGv_ptr ra, rb, rd; \
7483 TCGv_i32 ps; \
7484 \
7485 if (unlikely(!ctx->altivec_enabled)) { \
7486 gen_exception(ctx, POWERPC_EXCP_VPU); \
7487 return; \
7488 } \
7489 \
7490 ra = gen_avr_ptr(rA(ctx->opcode)); \
7491 rb = gen_avr_ptr(rB(ctx->opcode)); \
7492 rd = gen_avr_ptr(rD(ctx->opcode)); \
7493 \
7494 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7495 \
7496 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7497 \
7498 tcg_temp_free_ptr(ra); \
7499 tcg_temp_free_ptr(rb); \
7500 tcg_temp_free_ptr(rd); \
7501 tcg_temp_free_i32(ps); \
7502 }
7503
7504 GEN_BCD(bcdadd)
7505 GEN_BCD(bcdsub)
7506
7507 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7508 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7509 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7510 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7511 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7512 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7513 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7514 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7515
7516 static void gen_vsbox(DisasContext *ctx)
7517 {
7518 TCGv_ptr ra, rd;
7519 if (unlikely(!ctx->altivec_enabled)) {
7520 gen_exception(ctx, POWERPC_EXCP_VPU);
7521 return;
7522 }
7523 ra = gen_avr_ptr(rA(ctx->opcode));
7524 rd = gen_avr_ptr(rD(ctx->opcode));
7525 gen_helper_vsbox(rd, ra);
7526 tcg_temp_free_ptr(ra);
7527 tcg_temp_free_ptr(rd);
7528 }
7529
7530 GEN_VXFORM(vcipher, 4, 20)
7531 GEN_VXFORM(vcipherlast, 4, 20)
7532 GEN_VXFORM(vncipher, 4, 21)
7533 GEN_VXFORM(vncipherlast, 4, 21)
7534
7535 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7536 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7537 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7538 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7539
7540 #define VSHASIGMA(op) \
7541 static void gen_##op(DisasContext *ctx) \
7542 { \
7543 TCGv_ptr ra, rd; \
7544 TCGv_i32 st_six; \
7545 if (unlikely(!ctx->altivec_enabled)) { \
7546 gen_exception(ctx, POWERPC_EXCP_VPU); \
7547 return; \
7548 } \
7549 ra = gen_avr_ptr(rA(ctx->opcode)); \
7550 rd = gen_avr_ptr(rD(ctx->opcode)); \
7551 st_six = tcg_const_i32(rB(ctx->opcode)); \
7552 gen_helper_##op(rd, ra, st_six); \
7553 tcg_temp_free_ptr(ra); \
7554 tcg_temp_free_ptr(rd); \
7555 tcg_temp_free_i32(st_six); \
7556 }
7557
7558 VSHASIGMA(vshasigmaw)
7559 VSHASIGMA(vshasigmad)
7560
7561 GEN_VXFORM3(vpermxor, 22, 0xFF)
7562 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7563 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7564
7565 /*** VSX extension ***/
7566
7567 static inline TCGv_i64 cpu_vsrh(int n)
7568 {
7569 if (n < 32) {
7570 return cpu_fpr[n];
7571 } else {
7572 return cpu_avrh[n-32];
7573 }
7574 }
7575
7576 static inline TCGv_i64 cpu_vsrl(int n)
7577 {
7578 if (n < 32) {
7579 return cpu_vsr[n];
7580 } else {
7581 return cpu_avrl[n-32];
7582 }
7583 }
7584
7585 #define VSX_LOAD_SCALAR(name, operation) \
7586 static void gen_##name(DisasContext *ctx) \
7587 { \
7588 TCGv EA; \
7589 if (unlikely(!ctx->vsx_enabled)) { \
7590 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7591 return; \
7592 } \
7593 gen_set_access_type(ctx, ACCESS_INT); \
7594 EA = tcg_temp_new(); \
7595 gen_addr_reg_index(ctx, EA); \
7596 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7597 /* NOTE: cpu_vsrl is undefined */ \
7598 tcg_temp_free(EA); \
7599 }
7600
7601 VSX_LOAD_SCALAR(lxsdx, ld64)
7602 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7603 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7604 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7605
7606 static void gen_lxvd2x(DisasContext *ctx)
7607 {
7608 TCGv EA;
7609 if (unlikely(!ctx->vsx_enabled)) {
7610 gen_exception(ctx, POWERPC_EXCP_VSXU);
7611 return;
7612 }
7613 gen_set_access_type(ctx, ACCESS_INT);
7614 EA = tcg_temp_new();
7615 gen_addr_reg_index(ctx, EA);
7616 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7617 tcg_gen_addi_tl(EA, EA, 8);
7618 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7619 tcg_temp_free(EA);
7620 }
7621
7622 static void gen_lxvdsx(DisasContext *ctx)
7623 {
7624 TCGv EA;
7625 if (unlikely(!ctx->vsx_enabled)) {
7626 gen_exception(ctx, POWERPC_EXCP_VSXU);
7627 return;
7628 }
7629 gen_set_access_type(ctx, ACCESS_INT);
7630 EA = tcg_temp_new();
7631 gen_addr_reg_index(ctx, EA);
7632 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7633 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7634 tcg_temp_free(EA);
7635 }
7636
7637 static void gen_lxvw4x(DisasContext *ctx)
7638 {
7639 TCGv EA;
7640 TCGv_i64 tmp;
7641 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7642 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7643 if (unlikely(!ctx->vsx_enabled)) {
7644 gen_exception(ctx, POWERPC_EXCP_VSXU);
7645 return;
7646 }
7647 gen_set_access_type(ctx, ACCESS_INT);
7648 EA = tcg_temp_new();
7649 tmp = tcg_temp_new_i64();
7650
7651 gen_addr_reg_index(ctx, EA);
7652 gen_qemu_ld32u_i64(ctx, tmp, EA);
7653 tcg_gen_addi_tl(EA, EA, 4);
7654 gen_qemu_ld32u_i64(ctx, xth, EA);
7655 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7656
7657 tcg_gen_addi_tl(EA, EA, 4);
7658 gen_qemu_ld32u_i64(ctx, tmp, EA);
7659 tcg_gen_addi_tl(EA, EA, 4);
7660 gen_qemu_ld32u_i64(ctx, xtl, EA);
7661 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7662
7663 tcg_temp_free(EA);
7664 tcg_temp_free_i64(tmp);
7665 }
7666
7667 #define VSX_STORE_SCALAR(name, operation) \
7668 static void gen_##name(DisasContext *ctx) \
7669 { \
7670 TCGv EA; \
7671 if (unlikely(!ctx->vsx_enabled)) { \
7672 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7673 return; \
7674 } \
7675 gen_set_access_type(ctx, ACCESS_INT); \
7676 EA = tcg_temp_new(); \
7677 gen_addr_reg_index(ctx, EA); \
7678 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7679 tcg_temp_free(EA); \
7680 }
7681
7682 VSX_STORE_SCALAR(stxsdx, st64)
7683 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7684 VSX_STORE_SCALAR(stxsspx, st32fs)
7685
7686 static void gen_stxvd2x(DisasContext *ctx)
7687 {
7688 TCGv EA;
7689 if (unlikely(!ctx->vsx_enabled)) {
7690 gen_exception(ctx, POWERPC_EXCP_VSXU);
7691 return;
7692 }
7693 gen_set_access_type(ctx, ACCESS_INT);
7694 EA = tcg_temp_new();
7695 gen_addr_reg_index(ctx, EA);
7696 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7697 tcg_gen_addi_tl(EA, EA, 8);
7698 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7699 tcg_temp_free(EA);
7700 }
7701
7702 static void gen_stxvw4x(DisasContext *ctx)
7703 {
7704 TCGv_i64 tmp;
7705 TCGv EA;
7706 if (unlikely(!ctx->vsx_enabled)) {
7707 gen_exception(ctx, POWERPC_EXCP_VSXU);
7708 return;
7709 }
7710 gen_set_access_type(ctx, ACCESS_INT);
7711 EA = tcg_temp_new();
7712 gen_addr_reg_index(ctx, EA);
7713 tmp = tcg_temp_new_i64();
7714
7715 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7716 gen_qemu_st32_i64(ctx, tmp, EA);
7717 tcg_gen_addi_tl(EA, EA, 4);
7718 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7719
7720 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7721 tcg_gen_addi_tl(EA, EA, 4);
7722 gen_qemu_st32_i64(ctx, tmp, EA);
7723 tcg_gen_addi_tl(EA, EA, 4);
7724 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7725
7726 tcg_temp_free(EA);
7727 tcg_temp_free_i64(tmp);
7728 }
7729
7730 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7731 static void gen_##name(DisasContext *ctx) \
7732 { \
7733 if (xS(ctx->opcode) < 32) { \
7734 if (unlikely(!ctx->fpu_enabled)) { \
7735 gen_exception(ctx, POWERPC_EXCP_FPU); \
7736 return; \
7737 } \
7738 } else { \
7739 if (unlikely(!ctx->altivec_enabled)) { \
7740 gen_exception(ctx, POWERPC_EXCP_VPU); \
7741 return; \
7742 } \
7743 } \
7744 TCGv_i64 tmp = tcg_temp_new_i64(); \
7745 tcg_gen_##tcgop1(tmp, source); \
7746 tcg_gen_##tcgop2(target, tmp); \
7747 tcg_temp_free_i64(tmp); \
7748 }
7749
7750
7751 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7752 cpu_vsrh(xS(ctx->opcode)))
7753 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7754 cpu_gpr[rA(ctx->opcode)])
7755 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7756 cpu_gpr[rA(ctx->opcode)])
7757
7758 #if defined(TARGET_PPC64)
7759 #define MV_VSRD(name, target, source) \
7760 static void gen_##name(DisasContext *ctx) \
7761 { \
7762 if (xS(ctx->opcode) < 32) { \
7763 if (unlikely(!ctx->fpu_enabled)) { \
7764 gen_exception(ctx, POWERPC_EXCP_FPU); \
7765 return; \
7766 } \
7767 } else { \
7768 if (unlikely(!ctx->altivec_enabled)) { \
7769 gen_exception(ctx, POWERPC_EXCP_VPU); \
7770 return; \
7771 } \
7772 } \
7773 tcg_gen_mov_i64(target, source); \
7774 }
7775
7776 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7777 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7778
7779 #endif
7780
7781 static void gen_xxpermdi(DisasContext *ctx)
7782 {
7783 if (unlikely(!ctx->vsx_enabled)) {
7784 gen_exception(ctx, POWERPC_EXCP_VSXU);
7785 return;
7786 }
7787
7788 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7789 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7790 TCGv_i64 xh, xl;
7791
7792 xh = tcg_temp_new_i64();
7793 xl = tcg_temp_new_i64();
7794
7795 if ((DM(ctx->opcode) & 2) == 0) {
7796 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7797 } else {
7798 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7799 }
7800 if ((DM(ctx->opcode) & 1) == 0) {
7801 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7802 } else {
7803 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7804 }
7805
7806 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7807 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7808
7809 tcg_temp_free_i64(xh);
7810 tcg_temp_free_i64(xl);
7811 } else {
7812 if ((DM(ctx->opcode) & 2) == 0) {
7813 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7814 } else {
7815 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7816 }
7817 if ((DM(ctx->opcode) & 1) == 0) {
7818 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7819 } else {
7820 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7821 }
7822 }
7823 }
7824
7825 #define OP_ABS 1
7826 #define OP_NABS 2
7827 #define OP_NEG 3
7828 #define OP_CPSGN 4
7829 #define SGN_MASK_DP 0x8000000000000000ull
7830 #define SGN_MASK_SP 0x8000000080000000ull
7831
7832 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7833 static void glue(gen_, name)(DisasContext * ctx) \
7834 { \
7835 TCGv_i64 xb, sgm; \
7836 if (unlikely(!ctx->vsx_enabled)) { \
7837 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7838 return; \
7839 } \
7840 xb = tcg_temp_new_i64(); \
7841 sgm = tcg_temp_new_i64(); \
7842 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7843 tcg_gen_movi_i64(sgm, sgn_mask); \
7844 switch (op) { \
7845 case OP_ABS: { \
7846 tcg_gen_andc_i64(xb, xb, sgm); \
7847 break; \
7848 } \
7849 case OP_NABS: { \
7850 tcg_gen_or_i64(xb, xb, sgm); \
7851 break; \
7852 } \
7853 case OP_NEG: { \
7854 tcg_gen_xor_i64(xb, xb, sgm); \
7855 break; \
7856 } \
7857 case OP_CPSGN: { \
7858 TCGv_i64 xa = tcg_temp_new_i64(); \
7859 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7860 tcg_gen_and_i64(xa, xa, sgm); \
7861 tcg_gen_andc_i64(xb, xb, sgm); \
7862 tcg_gen_or_i64(xb, xb, xa); \
7863 tcg_temp_free_i64(xa); \
7864 break; \
7865 } \
7866 } \
7867 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7868 tcg_temp_free_i64(xb); \
7869 tcg_temp_free_i64(sgm); \
7870 }
7871
7872 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7873 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7874 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7875 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7876
7877 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7878 static void glue(gen_, name)(DisasContext * ctx) \
7879 { \
7880 TCGv_i64 xbh, xbl, sgm; \
7881 if (unlikely(!ctx->vsx_enabled)) { \
7882 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7883 return; \
7884 } \
7885 xbh = tcg_temp_new_i64(); \
7886 xbl = tcg_temp_new_i64(); \
7887 sgm = tcg_temp_new_i64(); \
7888 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7889 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7890 tcg_gen_movi_i64(sgm, sgn_mask); \
7891 switch (op) { \
7892 case OP_ABS: { \
7893 tcg_gen_andc_i64(xbh, xbh, sgm); \
7894 tcg_gen_andc_i64(xbl, xbl, sgm); \
7895 break; \
7896 } \
7897 case OP_NABS: { \
7898 tcg_gen_or_i64(xbh, xbh, sgm); \
7899 tcg_gen_or_i64(xbl, xbl, sgm); \
7900 break; \
7901 } \
7902 case OP_NEG: { \
7903 tcg_gen_xor_i64(xbh, xbh, sgm); \
7904 tcg_gen_xor_i64(xbl, xbl, sgm); \
7905 break; \
7906 } \
7907 case OP_CPSGN: { \
7908 TCGv_i64 xah = tcg_temp_new_i64(); \
7909 TCGv_i64 xal = tcg_temp_new_i64(); \
7910 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7911 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7912 tcg_gen_and_i64(xah, xah, sgm); \
7913 tcg_gen_and_i64(xal, xal, sgm); \
7914 tcg_gen_andc_i64(xbh, xbh, sgm); \
7915 tcg_gen_andc_i64(xbl, xbl, sgm); \
7916 tcg_gen_or_i64(xbh, xbh, xah); \
7917 tcg_gen_or_i64(xbl, xbl, xal); \
7918 tcg_temp_free_i64(xah); \
7919 tcg_temp_free_i64(xal); \
7920 break; \
7921 } \
7922 } \
7923 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7924 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7925 tcg_temp_free_i64(xbh); \
7926 tcg_temp_free_i64(xbl); \
7927 tcg_temp_free_i64(sgm); \
7928 }
7929
7930 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7931 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7932 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7933 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7934 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7935 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7936 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7937 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7938
7939 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7940 static void gen_##name(DisasContext * ctx) \
7941 { \
7942 TCGv_i32 opc; \
7943 if (unlikely(!ctx->vsx_enabled)) { \
7944 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7945 return; \
7946 } \
7947 /* NIP cannot be restored if the memory exception comes from an helper */ \
7948 gen_update_nip(ctx, ctx->nip - 4); \
7949 opc = tcg_const_i32(ctx->opcode); \
7950 gen_helper_##name(cpu_env, opc); \
7951 tcg_temp_free_i32(opc); \
7952 }
7953
7954 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7955 static void gen_##name(DisasContext * ctx) \
7956 { \
7957 if (unlikely(!ctx->vsx_enabled)) { \
7958 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7959 return; \
7960 } \
7961 /* NIP cannot be restored if the exception comes */ \
7962 /* from a helper. */ \
7963 gen_update_nip(ctx, ctx->nip - 4); \
7964 \
7965 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7966 cpu_vsrh(xB(ctx->opcode))); \
7967 }
7968
7969 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7970 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7971 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7972 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7973 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7974 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7975 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7976 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7977 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7978 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7979 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7980 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7981 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7982 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7983 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7984 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7985 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7986 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7987 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7988 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7989 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7990 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7991 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
7992 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7993 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
7994 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7995 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7996 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7997 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7998 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7999 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
8000 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
8001 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
8002 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
8003 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
8004 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
8005 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
8006
8007 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
8008 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
8009 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
8010 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
8011 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
8012 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
8013 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
8014 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
8015 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
8016 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
8017 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
8018 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
8019 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
8020 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
8021 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
8022 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
8023 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
8024
8025 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
8026 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
8027 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
8028 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
8029 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
8030 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
8031 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
8032 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
8033 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
8034 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8035 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8036 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8037 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8038 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8039 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8040 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8041 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
8042 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8043 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
8044 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8045 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8046 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
8047 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
8048 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8049 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8050 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8051 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8052 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8053 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8054 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8055 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
8056 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8057 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8058 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8059 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8060 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
8061
8062 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8063 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
8064 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
8065 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
8066 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
8067 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
8068 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
8069 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
8070 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
8071 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8072 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8073 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8074 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8075 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8076 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8077 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8078 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
8079 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8080 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
8081 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8082 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8083 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
8084 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
8085 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8086 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8087 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8088 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8089 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8090 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8091 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8092 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
8093 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8094 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8095 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8096 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8097 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
8098
8099 #define VSX_LOGICAL(name, tcg_op) \
8100 static void glue(gen_, name)(DisasContext * ctx) \
8101 { \
8102 if (unlikely(!ctx->vsx_enabled)) { \
8103 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8104 return; \
8105 } \
8106 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8107 cpu_vsrh(xB(ctx->opcode))); \
8108 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8109 cpu_vsrl(xB(ctx->opcode))); \
8110 }
8111
8112 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8113 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8114 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8115 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8116 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8117 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8118 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8119 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8120
8121 #define VSX_XXMRG(name, high) \
8122 static void glue(gen_, name)(DisasContext * ctx) \
8123 { \
8124 TCGv_i64 a0, a1, b0, b1; \
8125 if (unlikely(!ctx->vsx_enabled)) { \
8126 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8127 return; \
8128 } \
8129 a0 = tcg_temp_new_i64(); \
8130 a1 = tcg_temp_new_i64(); \
8131 b0 = tcg_temp_new_i64(); \
8132 b1 = tcg_temp_new_i64(); \
8133 if (high) { \
8134 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8135 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8136 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8137 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8138 } else { \
8139 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8140 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8141 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8142 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8143 } \
8144 tcg_gen_shri_i64(a0, a0, 32); \
8145 tcg_gen_shri_i64(b0, b0, 32); \
8146 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8147 b0, a0, 32, 32); \
8148 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8149 b1, a1, 32, 32); \
8150 tcg_temp_free_i64(a0); \
8151 tcg_temp_free_i64(a1); \
8152 tcg_temp_free_i64(b0); \
8153 tcg_temp_free_i64(b1); \
8154 }
8155
8156 VSX_XXMRG(xxmrghw, 1)
8157 VSX_XXMRG(xxmrglw, 0)
8158
8159 static void gen_xxsel(DisasContext * ctx)
8160 {
8161 TCGv_i64 a, b, c;
8162 if (unlikely(!ctx->vsx_enabled)) {
8163 gen_exception(ctx, POWERPC_EXCP_VSXU);
8164 return;
8165 }
8166 a = tcg_temp_new_i64();
8167 b = tcg_temp_new_i64();
8168 c = tcg_temp_new_i64();
8169
8170 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8171 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8172 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8173
8174 tcg_gen_and_i64(b, b, c);
8175 tcg_gen_andc_i64(a, a, c);
8176 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8177
8178 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8179 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8180 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8181
8182 tcg_gen_and_i64(b, b, c);
8183 tcg_gen_andc_i64(a, a, c);
8184 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8185
8186 tcg_temp_free_i64(a);
8187 tcg_temp_free_i64(b);
8188 tcg_temp_free_i64(c);
8189 }
8190
8191 static void gen_xxspltw(DisasContext *ctx)
8192 {
8193 TCGv_i64 b, b2;
8194 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8195 cpu_vsrl(xB(ctx->opcode)) :
8196 cpu_vsrh(xB(ctx->opcode));
8197
8198 if (unlikely(!ctx->vsx_enabled)) {
8199 gen_exception(ctx, POWERPC_EXCP_VSXU);
8200 return;
8201 }
8202
8203 b = tcg_temp_new_i64();
8204 b2 = tcg_temp_new_i64();
8205
8206 if (UIM(ctx->opcode) & 1) {
8207 tcg_gen_ext32u_i64(b, vsr);
8208 } else {
8209 tcg_gen_shri_i64(b, vsr, 32);
8210 }
8211
8212 tcg_gen_shli_i64(b2, b, 32);
8213 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8214 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8215
8216 tcg_temp_free_i64(b);
8217 tcg_temp_free_i64(b2);
8218 }
8219
8220 static void gen_xxsldwi(DisasContext *ctx)
8221 {
8222 TCGv_i64 xth, xtl;
8223 if (unlikely(!ctx->vsx_enabled)) {
8224 gen_exception(ctx, POWERPC_EXCP_VSXU);
8225 return;
8226 }
8227 xth = tcg_temp_new_i64();
8228 xtl = tcg_temp_new_i64();
8229
8230 switch (SHW(ctx->opcode)) {
8231 case 0: {
8232 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8233 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8234 break;
8235 }
8236 case 1: {
8237 TCGv_i64 t0 = tcg_temp_new_i64();
8238 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8239 tcg_gen_shli_i64(xth, xth, 32);
8240 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8241 tcg_gen_shri_i64(t0, t0, 32);
8242 tcg_gen_or_i64(xth, xth, t0);
8243 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8244 tcg_gen_shli_i64(xtl, xtl, 32);
8245 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8246 tcg_gen_shri_i64(t0, t0, 32);
8247 tcg_gen_or_i64(xtl, xtl, t0);
8248 tcg_temp_free_i64(t0);
8249 break;
8250 }
8251 case 2: {
8252 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8253 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8254 break;
8255 }
8256 case 3: {
8257 TCGv_i64 t0 = tcg_temp_new_i64();
8258 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8259 tcg_gen_shli_i64(xth, xth, 32);
8260 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8261 tcg_gen_shri_i64(t0, t0, 32);
8262 tcg_gen_or_i64(xth, xth, t0);
8263 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8264 tcg_gen_shli_i64(xtl, xtl, 32);
8265 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8266 tcg_gen_shri_i64(t0, t0, 32);
8267 tcg_gen_or_i64(xtl, xtl, t0);
8268 tcg_temp_free_i64(t0);
8269 break;
8270 }
8271 }
8272
8273 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8274 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8275
8276 tcg_temp_free_i64(xth);
8277 tcg_temp_free_i64(xtl);
8278 }
8279
8280 /*** Decimal Floating Point ***/
8281
8282 static inline TCGv_ptr gen_fprp_ptr(int reg)
8283 {
8284 TCGv_ptr r = tcg_temp_new_ptr();
8285 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8286 return r;
8287 }
8288
8289 #define GEN_DFP_T_A_B_Rc(name) \
8290 static void gen_##name(DisasContext *ctx) \
8291 { \
8292 TCGv_ptr rd, ra, rb; \
8293 if (unlikely(!ctx->fpu_enabled)) { \
8294 gen_exception(ctx, POWERPC_EXCP_FPU); \
8295 return; \
8296 } \
8297 gen_update_nip(ctx, ctx->nip - 4); \
8298 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8299 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8300 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8301 gen_helper_##name(cpu_env, rd, ra, rb); \
8302 if (unlikely(Rc(ctx->opcode) != 0)) { \
8303 gen_set_cr1_from_fpscr(ctx); \
8304 } \
8305 tcg_temp_free_ptr(rd); \
8306 tcg_temp_free_ptr(ra); \
8307 tcg_temp_free_ptr(rb); \
8308 }
8309
8310 #define GEN_DFP_BF_A_B(name) \
8311 static void gen_##name(DisasContext *ctx) \
8312 { \
8313 TCGv_ptr ra, rb; \
8314 if (unlikely(!ctx->fpu_enabled)) { \
8315 gen_exception(ctx, POWERPC_EXCP_FPU); \
8316 return; \
8317 } \
8318 gen_update_nip(ctx, ctx->nip - 4); \
8319 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8320 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8321 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8322 cpu_env, ra, rb); \
8323 tcg_temp_free_ptr(ra); \
8324 tcg_temp_free_ptr(rb); \
8325 }
8326
8327 #define GEN_DFP_BF_A_DCM(name) \
8328 static void gen_##name(DisasContext *ctx) \
8329 { \
8330 TCGv_ptr ra; \
8331 TCGv_i32 dcm; \
8332 if (unlikely(!ctx->fpu_enabled)) { \
8333 gen_exception(ctx, POWERPC_EXCP_FPU); \
8334 return; \
8335 } \
8336 gen_update_nip(ctx, ctx->nip - 4); \
8337 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8338 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8339 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8340 cpu_env, ra, dcm); \
8341 tcg_temp_free_ptr(ra); \
8342 tcg_temp_free_i32(dcm); \
8343 }
8344
8345 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8346 static void gen_##name(DisasContext *ctx) \
8347 { \
8348 TCGv_ptr rt, rb; \
8349 TCGv_i32 u32_1, u32_2; \
8350 if (unlikely(!ctx->fpu_enabled)) { \
8351 gen_exception(ctx, POWERPC_EXCP_FPU); \
8352 return; \
8353 } \
8354 gen_update_nip(ctx, ctx->nip - 4); \
8355 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8356 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8357 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8358 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8359 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8360 if (unlikely(Rc(ctx->opcode) != 0)) { \
8361 gen_set_cr1_from_fpscr(ctx); \
8362 } \
8363 tcg_temp_free_ptr(rt); \
8364 tcg_temp_free_ptr(rb); \
8365 tcg_temp_free_i32(u32_1); \
8366 tcg_temp_free_i32(u32_2); \
8367 }
8368
8369 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8370 static void gen_##name(DisasContext *ctx) \
8371 { \
8372 TCGv_ptr rt, ra, rb; \
8373 TCGv_i32 i32; \
8374 if (unlikely(!ctx->fpu_enabled)) { \
8375 gen_exception(ctx, POWERPC_EXCP_FPU); \
8376 return; \
8377 } \
8378 gen_update_nip(ctx, ctx->nip - 4); \
8379 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8380 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8381 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8382 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8383 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8384 if (unlikely(Rc(ctx->opcode) != 0)) { \
8385 gen_set_cr1_from_fpscr(ctx); \
8386 } \
8387 tcg_temp_free_ptr(rt); \
8388 tcg_temp_free_ptr(rb); \
8389 tcg_temp_free_ptr(ra); \
8390 tcg_temp_free_i32(i32); \
8391 }
8392
8393 #define GEN_DFP_T_B_Rc(name) \
8394 static void gen_##name(DisasContext *ctx) \
8395 { \
8396 TCGv_ptr rt, rb; \
8397 if (unlikely(!ctx->fpu_enabled)) { \
8398 gen_exception(ctx, POWERPC_EXCP_FPU); \
8399 return; \
8400 } \
8401 gen_update_nip(ctx, ctx->nip - 4); \
8402 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8403 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8404 gen_helper_##name(cpu_env, rt, rb); \
8405 if (unlikely(Rc(ctx->opcode) != 0)) { \
8406 gen_set_cr1_from_fpscr(ctx); \
8407 } \
8408 tcg_temp_free_ptr(rt); \
8409 tcg_temp_free_ptr(rb); \
8410 }
8411
8412 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8413 static void gen_##name(DisasContext *ctx) \
8414 { \
8415 TCGv_ptr rt, rs; \
8416 TCGv_i32 i32; \
8417 if (unlikely(!ctx->fpu_enabled)) { \
8418 gen_exception(ctx, POWERPC_EXCP_FPU); \
8419 return; \
8420 } \
8421 gen_update_nip(ctx, ctx->nip - 4); \
8422 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8423 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8424 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8425 gen_helper_##name(cpu_env, rt, rs, i32); \
8426 if (unlikely(Rc(ctx->opcode) != 0)) { \
8427 gen_set_cr1_from_fpscr(ctx); \
8428 } \
8429 tcg_temp_free_ptr(rt); \
8430 tcg_temp_free_ptr(rs); \
8431 tcg_temp_free_i32(i32); \
8432 }
8433
8434 GEN_DFP_T_A_B_Rc(dadd)
8435 GEN_DFP_T_A_B_Rc(daddq)
8436 GEN_DFP_T_A_B_Rc(dsub)
8437 GEN_DFP_T_A_B_Rc(dsubq)
8438 GEN_DFP_T_A_B_Rc(dmul)
8439 GEN_DFP_T_A_B_Rc(dmulq)
8440 GEN_DFP_T_A_B_Rc(ddiv)
8441 GEN_DFP_T_A_B_Rc(ddivq)
8442 GEN_DFP_BF_A_B(dcmpu)
8443 GEN_DFP_BF_A_B(dcmpuq)
8444 GEN_DFP_BF_A_B(dcmpo)
8445 GEN_DFP_BF_A_B(dcmpoq)
8446 GEN_DFP_BF_A_DCM(dtstdc)
8447 GEN_DFP_BF_A_DCM(dtstdcq)
8448 GEN_DFP_BF_A_DCM(dtstdg)
8449 GEN_DFP_BF_A_DCM(dtstdgq)
8450 GEN_DFP_BF_A_B(dtstex)
8451 GEN_DFP_BF_A_B(dtstexq)
8452 GEN_DFP_BF_A_B(dtstsf)
8453 GEN_DFP_BF_A_B(dtstsfq)
8454 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8455 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8456 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8457 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8458 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8459 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8460 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8461 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8462 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8463 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8464 GEN_DFP_T_B_Rc(dctdp)
8465 GEN_DFP_T_B_Rc(dctqpq)
8466 GEN_DFP_T_B_Rc(drsp)
8467 GEN_DFP_T_B_Rc(drdpq)
8468 GEN_DFP_T_B_Rc(dcffix)
8469 GEN_DFP_T_B_Rc(dcffixq)
8470 GEN_DFP_T_B_Rc(dctfix)
8471 GEN_DFP_T_B_Rc(dctfixq)
8472 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8473 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8474 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8475 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8476 GEN_DFP_T_B_Rc(dxex)
8477 GEN_DFP_T_B_Rc(dxexq)
8478 GEN_DFP_T_A_B_Rc(diex)
8479 GEN_DFP_T_A_B_Rc(diexq)
8480 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8481 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8482 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8483 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8484
8485 /*** SPE extension ***/
8486 /* Register moves */
8487
8488 static inline void gen_evmra(DisasContext *ctx)
8489 {
8490
8491 if (unlikely(!ctx->spe_enabled)) {
8492 gen_exception(ctx, POWERPC_EXCP_SPEU);
8493 return;
8494 }
8495
8496 TCGv_i64 tmp = tcg_temp_new_i64();
8497
8498 /* tmp := rA_lo + rA_hi << 32 */
8499 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8500
8501 /* spe_acc := tmp */
8502 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8503 tcg_temp_free_i64(tmp);
8504
8505 /* rD := rA */
8506 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8507 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8508 }
8509
8510 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8511 {
8512 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8513 }
8514
8515 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8516 {
8517 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8518 }
8519
8520 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8521 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8522 { \
8523 if (Rc(ctx->opcode)) \
8524 gen_##name1(ctx); \
8525 else \
8526 gen_##name0(ctx); \
8527 }
8528
8529 /* Handler for undefined SPE opcodes */
8530 static inline void gen_speundef(DisasContext *ctx)
8531 {
8532 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8533 }
8534
8535 /* SPE logic */
8536 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8537 static inline void gen_##name(DisasContext *ctx) \
8538 { \
8539 if (unlikely(!ctx->spe_enabled)) { \
8540 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8541 return; \
8542 } \
8543 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8544 cpu_gpr[rB(ctx->opcode)]); \
8545 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8546 cpu_gprh[rB(ctx->opcode)]); \
8547 }
8548
8549 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8550 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8551 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8552 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8553 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8554 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8555 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8556 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8557
8558 /* SPE logic immediate */
8559 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8560 static inline void gen_##name(DisasContext *ctx) \
8561 { \
8562 TCGv_i32 t0; \
8563 if (unlikely(!ctx->spe_enabled)) { \
8564 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8565 return; \
8566 } \
8567 t0 = tcg_temp_new_i32(); \
8568 \
8569 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8570 tcg_opi(t0, t0, rB(ctx->opcode)); \
8571 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8572 \
8573 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8574 tcg_opi(t0, t0, rB(ctx->opcode)); \
8575 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8576 \
8577 tcg_temp_free_i32(t0); \
8578 }
8579 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8580 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8581 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8582 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8583
8584 /* SPE arithmetic */
8585 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8586 static inline void gen_##name(DisasContext *ctx) \
8587 { \
8588 TCGv_i32 t0; \
8589 if (unlikely(!ctx->spe_enabled)) { \
8590 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8591 return; \
8592 } \
8593 t0 = tcg_temp_new_i32(); \
8594 \
8595 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8596 tcg_op(t0, t0); \
8597 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8598 \
8599 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8600 tcg_op(t0, t0); \
8601 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8602 \
8603 tcg_temp_free_i32(t0); \
8604 }
8605
8606 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8607 {
8608 TCGLabel *l1 = gen_new_label();
8609 TCGLabel *l2 = gen_new_label();
8610
8611 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8612 tcg_gen_neg_i32(ret, arg1);
8613 tcg_gen_br(l2);
8614 gen_set_label(l1);
8615 tcg_gen_mov_i32(ret, arg1);
8616 gen_set_label(l2);
8617 }
8618 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8619 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8620 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8621 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8622 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8623 {
8624 tcg_gen_addi_i32(ret, arg1, 0x8000);
8625 tcg_gen_ext16u_i32(ret, ret);
8626 }
8627 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8628 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8629 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8630
8631 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8632 static inline void gen_##name(DisasContext *ctx) \
8633 { \
8634 TCGv_i32 t0, t1; \
8635 if (unlikely(!ctx->spe_enabled)) { \
8636 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8637 return; \
8638 } \
8639 t0 = tcg_temp_new_i32(); \
8640 t1 = tcg_temp_new_i32(); \
8641 \
8642 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8643 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8644 tcg_op(t0, t0, t1); \
8645 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8646 \
8647 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8648 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8649 tcg_op(t0, t0, t1); \
8650 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8651 \
8652 tcg_temp_free_i32(t0); \
8653 tcg_temp_free_i32(t1); \
8654 }
8655
8656 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8657 {
8658 TCGLabel *l1 = gen_new_label();
8659 TCGLabel *l2 = gen_new_label();
8660 TCGv_i32 t0 = tcg_temp_local_new_i32();
8661
8662 /* No error here: 6 bits are used */
8663 tcg_gen_andi_i32(t0, arg2, 0x3F);
8664 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8665 tcg_gen_shr_i32(ret, arg1, t0);
8666 tcg_gen_br(l2);
8667 gen_set_label(l1);
8668 tcg_gen_movi_i32(ret, 0);
8669 gen_set_label(l2);
8670 tcg_temp_free_i32(t0);
8671 }
8672 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8673 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8674 {
8675 TCGLabel *l1 = gen_new_label();
8676 TCGLabel *l2 = gen_new_label();
8677 TCGv_i32 t0 = tcg_temp_local_new_i32();
8678
8679 /* No error here: 6 bits are used */
8680 tcg_gen_andi_i32(t0, arg2, 0x3F);
8681 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8682 tcg_gen_sar_i32(ret, arg1, t0);
8683 tcg_gen_br(l2);
8684 gen_set_label(l1);
8685 tcg_gen_movi_i32(ret, 0);
8686 gen_set_label(l2);
8687 tcg_temp_free_i32(t0);
8688 }
8689 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8690 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8691 {
8692 TCGLabel *l1 = gen_new_label();
8693 TCGLabel *l2 = gen_new_label();
8694 TCGv_i32 t0 = tcg_temp_local_new_i32();
8695
8696 /* No error here: 6 bits are used */
8697 tcg_gen_andi_i32(t0, arg2, 0x3F);
8698 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8699 tcg_gen_shl_i32(ret, arg1, t0);
8700 tcg_gen_br(l2);
8701 gen_set_label(l1);
8702 tcg_gen_movi_i32(ret, 0);
8703 gen_set_label(l2);
8704 tcg_temp_free_i32(t0);
8705 }
8706 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8707 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8708 {
8709 TCGv_i32 t0 = tcg_temp_new_i32();
8710 tcg_gen_andi_i32(t0, arg2, 0x1F);
8711 tcg_gen_rotl_i32(ret, arg1, t0);
8712 tcg_temp_free_i32(t0);
8713 }
8714 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8715 static inline void gen_evmergehi(DisasContext *ctx)
8716 {
8717 if (unlikely(!ctx->spe_enabled)) {
8718 gen_exception(ctx, POWERPC_EXCP_SPEU);
8719 return;
8720 }
8721 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8722 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8723 }
8724 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8725 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8726 {
8727 tcg_gen_sub_i32(ret, arg2, arg1);
8728 }
8729 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8730
8731 /* SPE arithmetic immediate */
8732 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8733 static inline void gen_##name(DisasContext *ctx) \
8734 { \
8735 TCGv_i32 t0; \
8736 if (unlikely(!ctx->spe_enabled)) { \
8737 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8738 return; \
8739 } \
8740 t0 = tcg_temp_new_i32(); \
8741 \
8742 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8743 tcg_op(t0, t0, rA(ctx->opcode)); \
8744 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8745 \
8746 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8747 tcg_op(t0, t0, rA(ctx->opcode)); \
8748 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8749 \
8750 tcg_temp_free_i32(t0); \
8751 }
8752 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8753 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8754
8755 /* SPE comparison */
8756 #define GEN_SPEOP_COMP(name, tcg_cond) \
8757 static inline void gen_##name(DisasContext *ctx) \
8758 { \
8759 if (unlikely(!ctx->spe_enabled)) { \
8760 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8761 return; \
8762 } \
8763 TCGLabel *l1 = gen_new_label(); \
8764 TCGLabel *l2 = gen_new_label(); \
8765 TCGLabel *l3 = gen_new_label(); \
8766 TCGLabel *l4 = gen_new_label(); \
8767 \
8768 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8769 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8770 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8771 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8772 \
8773 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8774 cpu_gpr[rB(ctx->opcode)], l1); \
8775 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8776 tcg_gen_br(l2); \
8777 gen_set_label(l1); \
8778 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8779 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8780 gen_set_label(l2); \
8781 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8782 cpu_gprh[rB(ctx->opcode)], l3); \
8783 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8784 ~(CRF_CH | CRF_CH_AND_CL)); \
8785 tcg_gen_br(l4); \
8786 gen_set_label(l3); \
8787 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8788 CRF_CH | CRF_CH_OR_CL); \
8789 gen_set_label(l4); \
8790 }
8791 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8792 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8793 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8794 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8795 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8796
8797 /* SPE misc */
8798 static inline void gen_brinc(DisasContext *ctx)
8799 {
8800 /* Note: brinc is usable even if SPE is disabled */
8801 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8802 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8803 }
8804 static inline void gen_evmergelo(DisasContext *ctx)
8805 {
8806 if (unlikely(!ctx->spe_enabled)) {
8807 gen_exception(ctx, POWERPC_EXCP_SPEU);
8808 return;
8809 }
8810 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8811 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8812 }
8813 static inline void gen_evmergehilo(DisasContext *ctx)
8814 {
8815 if (unlikely(!ctx->spe_enabled)) {
8816 gen_exception(ctx, POWERPC_EXCP_SPEU);
8817 return;
8818 }
8819 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8820 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8821 }
8822 static inline void gen_evmergelohi(DisasContext *ctx)
8823 {
8824 if (unlikely(!ctx->spe_enabled)) {
8825 gen_exception(ctx, POWERPC_EXCP_SPEU);
8826 return;
8827 }
8828 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8829 TCGv tmp = tcg_temp_new();
8830 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8831 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8832 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8833 tcg_temp_free(tmp);
8834 } else {
8835 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8836 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8837 }
8838 }
8839 static inline void gen_evsplati(DisasContext *ctx)
8840 {
8841 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8842
8843 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8844 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8845 }
8846 static inline void gen_evsplatfi(DisasContext *ctx)
8847 {
8848 uint64_t imm = rA(ctx->opcode) << 27;
8849
8850 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8851 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8852 }
8853
8854 static inline void gen_evsel(DisasContext *ctx)
8855 {
8856 TCGLabel *l1 = gen_new_label();
8857 TCGLabel *l2 = gen_new_label();
8858 TCGLabel *l3 = gen_new_label();
8859 TCGLabel *l4 = gen_new_label();
8860 TCGv_i32 t0 = tcg_temp_local_new_i32();
8861
8862 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8863 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8864 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8865 tcg_gen_br(l2);
8866 gen_set_label(l1);
8867 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8868 gen_set_label(l2);
8869 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8870 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8871 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8872 tcg_gen_br(l4);
8873 gen_set_label(l3);
8874 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8875 gen_set_label(l4);
8876 tcg_temp_free_i32(t0);
8877 }
8878
8879 static void gen_evsel0(DisasContext *ctx)
8880 {
8881 gen_evsel(ctx);
8882 }
8883
8884 static void gen_evsel1(DisasContext *ctx)
8885 {
8886 gen_evsel(ctx);
8887 }
8888
8889 static void gen_evsel2(DisasContext *ctx)
8890 {
8891 gen_evsel(ctx);
8892 }
8893
8894 static void gen_evsel3(DisasContext *ctx)
8895 {
8896 gen_evsel(ctx);
8897 }
8898
8899 /* Multiply */
8900
8901 static inline void gen_evmwumi(DisasContext *ctx)
8902 {
8903 TCGv_i64 t0, t1;
8904
8905 if (unlikely(!ctx->spe_enabled)) {
8906 gen_exception(ctx, POWERPC_EXCP_SPEU);
8907 return;
8908 }
8909
8910 t0 = tcg_temp_new_i64();
8911 t1 = tcg_temp_new_i64();
8912
8913 /* t0 := rA; t1 := rB */
8914 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8915 tcg_gen_ext32u_i64(t0, t0);
8916 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8917 tcg_gen_ext32u_i64(t1, t1);
8918
8919 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8920
8921 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8922
8923 tcg_temp_free_i64(t0);
8924 tcg_temp_free_i64(t1);
8925 }
8926
8927 static inline void gen_evmwumia(DisasContext *ctx)
8928 {
8929 TCGv_i64 tmp;
8930
8931 if (unlikely(!ctx->spe_enabled)) {
8932 gen_exception(ctx, POWERPC_EXCP_SPEU);
8933 return;
8934 }
8935
8936 gen_evmwumi(ctx); /* rD := rA * rB */
8937
8938 tmp = tcg_temp_new_i64();
8939
8940 /* acc := rD */
8941 gen_load_gpr64(tmp, rD(ctx->opcode));
8942 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8943 tcg_temp_free_i64(tmp);
8944 }
8945
8946 static inline void gen_evmwumiaa(DisasContext *ctx)
8947 {
8948 TCGv_i64 acc;
8949 TCGv_i64 tmp;
8950
8951 if (unlikely(!ctx->spe_enabled)) {
8952 gen_exception(ctx, POWERPC_EXCP_SPEU);
8953 return;
8954 }
8955
8956 gen_evmwumi(ctx); /* rD := rA * rB */
8957
8958 acc = tcg_temp_new_i64();
8959 tmp = tcg_temp_new_i64();
8960
8961 /* tmp := rD */
8962 gen_load_gpr64(tmp, rD(ctx->opcode));
8963
8964 /* Load acc */
8965 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8966
8967 /* acc := tmp + acc */
8968 tcg_gen_add_i64(acc, acc, tmp);
8969
8970 /* Store acc */
8971 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8972
8973 /* rD := acc */
8974 gen_store_gpr64(rD(ctx->opcode), acc);
8975
8976 tcg_temp_free_i64(acc);
8977 tcg_temp_free_i64(tmp);
8978 }
8979
8980 static inline void gen_evmwsmi(DisasContext *ctx)
8981 {
8982 TCGv_i64 t0, t1;
8983
8984 if (unlikely(!ctx->spe_enabled)) {
8985 gen_exception(ctx, POWERPC_EXCP_SPEU);
8986 return;
8987 }
8988
8989 t0 = tcg_temp_new_i64();
8990 t1 = tcg_temp_new_i64();
8991
8992 /* t0 := rA; t1 := rB */
8993 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8994 tcg_gen_ext32s_i64(t0, t0);
8995 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8996 tcg_gen_ext32s_i64(t1, t1);
8997
8998 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8999
9000 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9001
9002 tcg_temp_free_i64(t0);
9003 tcg_temp_free_i64(t1);
9004 }
9005
9006 static inline void gen_evmwsmia(DisasContext *ctx)
9007 {
9008 TCGv_i64 tmp;
9009
9010 gen_evmwsmi(ctx); /* rD := rA * rB */
9011
9012 tmp = tcg_temp_new_i64();
9013
9014 /* acc := rD */
9015 gen_load_gpr64(tmp, rD(ctx->opcode));
9016 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
9017
9018 tcg_temp_free_i64(tmp);
9019 }
9020
9021 static inline void gen_evmwsmiaa(DisasContext *ctx)
9022 {
9023 TCGv_i64 acc = tcg_temp_new_i64();
9024 TCGv_i64 tmp = tcg_temp_new_i64();
9025
9026 gen_evmwsmi(ctx); /* rD := rA * rB */
9027
9028 acc = tcg_temp_new_i64();
9029 tmp = tcg_temp_new_i64();
9030
9031 /* tmp := rD */
9032 gen_load_gpr64(tmp, rD(ctx->opcode));
9033
9034 /* Load acc */
9035 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9036
9037 /* acc := tmp + acc */
9038 tcg_gen_add_i64(acc, acc, tmp);
9039
9040 /* Store acc */
9041 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9042
9043 /* rD := acc */
9044 gen_store_gpr64(rD(ctx->opcode), acc);
9045
9046 tcg_temp_free_i64(acc);
9047 tcg_temp_free_i64(tmp);
9048 }
9049
9050 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9051 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9052 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9053 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9054 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9055 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9056 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9057 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9058 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9059 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9060 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9061 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9062 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9063 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9064 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9065 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9066 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9067 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9068 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9069 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9070 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9071 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9072 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9073 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9074 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9075 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9076 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9077 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9078 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
9079
9080 /* SPE load and stores */
9081 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
9082 {
9083 target_ulong uimm = rB(ctx->opcode);
9084
9085 if (rA(ctx->opcode) == 0) {
9086 tcg_gen_movi_tl(EA, uimm << sh);
9087 } else {
9088 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9089 if (NARROW_MODE(ctx)) {
9090 tcg_gen_ext32u_tl(EA, EA);
9091 }
9092 }
9093 }
9094
9095 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9096 {
9097 TCGv_i64 t0 = tcg_temp_new_i64();
9098 gen_qemu_ld64(ctx, t0, addr);
9099 gen_store_gpr64(rD(ctx->opcode), t0);
9100 tcg_temp_free_i64(t0);
9101 }
9102
9103 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9104 {
9105 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9106 gen_addr_add(ctx, addr, addr, 4);
9107 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9108 }
9109
9110 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9111 {
9112 TCGv t0 = tcg_temp_new();
9113 gen_qemu_ld16u(ctx, t0, addr);
9114 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9115 gen_addr_add(ctx, addr, addr, 2);
9116 gen_qemu_ld16u(ctx, t0, addr);
9117 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9118 gen_addr_add(ctx, addr, addr, 2);
9119 gen_qemu_ld16u(ctx, t0, addr);
9120 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9121 gen_addr_add(ctx, addr, addr, 2);
9122 gen_qemu_ld16u(ctx, t0, addr);
9123 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9124 tcg_temp_free(t0);
9125 }
9126
9127 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9128 {
9129 TCGv t0 = tcg_temp_new();
9130 gen_qemu_ld16u(ctx, t0, addr);
9131 tcg_gen_shli_tl(t0, t0, 16);
9132 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9133 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9134 tcg_temp_free(t0);
9135 }
9136
9137 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9138 {
9139 TCGv t0 = tcg_temp_new();
9140 gen_qemu_ld16u(ctx, t0, addr);
9141 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9142 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9143 tcg_temp_free(t0);
9144 }
9145
9146 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9147 {
9148 TCGv t0 = tcg_temp_new();
9149 gen_qemu_ld16s(ctx, t0, addr);
9150 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9151 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9152 tcg_temp_free(t0);
9153 }
9154
9155 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9156 {
9157 TCGv t0 = tcg_temp_new();
9158 gen_qemu_ld16u(ctx, t0, addr);
9159 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9160 gen_addr_add(ctx, addr, addr, 2);
9161 gen_qemu_ld16u(ctx, t0, addr);
9162 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9163 tcg_temp_free(t0);
9164 }
9165
9166 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9167 {
9168 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9169 gen_addr_add(ctx, addr, addr, 2);
9170 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9171 }
9172
9173 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9174 {
9175 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9176 gen_addr_add(ctx, addr, addr, 2);
9177 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9178 }
9179
9180 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9181 {
9182 TCGv t0 = tcg_temp_new();
9183 gen_qemu_ld32u(ctx, t0, addr);
9184 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9185 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9186 tcg_temp_free(t0);
9187 }
9188
9189 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9190 {
9191 TCGv t0 = tcg_temp_new();
9192 gen_qemu_ld16u(ctx, t0, addr);
9193 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9194 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9195 gen_addr_add(ctx, addr, addr, 2);
9196 gen_qemu_ld16u(ctx, t0, addr);
9197 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9198 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9199 tcg_temp_free(t0);
9200 }
9201
9202 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9203 {
9204 TCGv_i64 t0 = tcg_temp_new_i64();
9205 gen_load_gpr64(t0, rS(ctx->opcode));
9206 gen_qemu_st64(ctx, t0, addr);
9207 tcg_temp_free_i64(t0);
9208 }
9209
9210 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9211 {
9212 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9213 gen_addr_add(ctx, addr, addr, 4);
9214 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9215 }
9216
9217 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9218 {
9219 TCGv t0 = tcg_temp_new();
9220 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9221 gen_qemu_st16(ctx, t0, addr);
9222 gen_addr_add(ctx, addr, addr, 2);
9223 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9224 gen_addr_add(ctx, addr, addr, 2);
9225 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9226 gen_qemu_st16(ctx, t0, addr);
9227 tcg_temp_free(t0);
9228 gen_addr_add(ctx, addr, addr, 2);
9229 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9230 }
9231
9232 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9233 {
9234 TCGv t0 = tcg_temp_new();
9235 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9236 gen_qemu_st16(ctx, t0, addr);
9237 gen_addr_add(ctx, addr, addr, 2);
9238 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9239 gen_qemu_st16(ctx, t0, addr);
9240 tcg_temp_free(t0);
9241 }
9242
9243 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9244 {
9245 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9246 gen_addr_add(ctx, addr, addr, 2);
9247 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9248 }
9249
9250 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9251 {
9252 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9253 }
9254
9255 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9256 {
9257 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9258 }
9259
9260 #define GEN_SPEOP_LDST(name, opc2, sh) \
9261 static void glue(gen_, name)(DisasContext *ctx) \
9262 { \
9263 TCGv t0; \
9264 if (unlikely(!ctx->spe_enabled)) { \
9265 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9266 return; \
9267 } \
9268 gen_set_access_type(ctx, ACCESS_INT); \
9269 t0 = tcg_temp_new(); \
9270 if (Rc(ctx->opcode)) { \
9271 gen_addr_spe_imm_index(ctx, t0, sh); \
9272 } else { \
9273 gen_addr_reg_index(ctx, t0); \
9274 } \
9275 gen_op_##name(ctx, t0); \
9276 tcg_temp_free(t0); \
9277 }
9278
9279 GEN_SPEOP_LDST(evldd, 0x00, 3);
9280 GEN_SPEOP_LDST(evldw, 0x01, 3);
9281 GEN_SPEOP_LDST(evldh, 0x02, 3);
9282 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9283 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9284 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9285 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9286 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9287 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9288 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9289 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9290
9291 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9292 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9293 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9294 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9295 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9296 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9297 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9298
9299 /* Multiply and add - TODO */
9300 #if 0
9301 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9302 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9303 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9304 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9305 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9306 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9307 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9308 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9309 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9310 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9311 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9312 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9313
9314 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9315 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9316 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9317 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9318 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9319 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9320 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9321 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9322 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9323 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9324 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9325 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9326
9327 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9328 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9329 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9330 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9331 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9332
9333 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9334 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9335 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9336 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9337 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9338 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9339 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9340 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9341 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9342 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9343 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9344 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9345
9346 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9347 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9348 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9349 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9350
9351 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9352 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9353 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9354 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9355 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9356 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9357 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9358 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9359 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9360 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9361 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9362 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9363
9364 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9365 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9366 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9367 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9368 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9369 #endif
9370
9371 /*** SPE floating-point extension ***/
9372 #define GEN_SPEFPUOP_CONV_32_32(name) \
9373 static inline void gen_##name(DisasContext *ctx) \
9374 { \
9375 TCGv_i32 t0 = tcg_temp_new_i32(); \
9376 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9377 gen_helper_##name(t0, cpu_env, t0); \
9378 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9379 tcg_temp_free_i32(t0); \
9380 }
9381 #define GEN_SPEFPUOP_CONV_32_64(name) \
9382 static inline void gen_##name(DisasContext *ctx) \
9383 { \
9384 TCGv_i64 t0 = tcg_temp_new_i64(); \
9385 TCGv_i32 t1 = tcg_temp_new_i32(); \
9386 gen_load_gpr64(t0, rB(ctx->opcode)); \
9387 gen_helper_##name(t1, cpu_env, t0); \
9388 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9389 tcg_temp_free_i64(t0); \
9390 tcg_temp_free_i32(t1); \
9391 }
9392 #define GEN_SPEFPUOP_CONV_64_32(name) \
9393 static inline void gen_##name(DisasContext *ctx) \
9394 { \
9395 TCGv_i64 t0 = tcg_temp_new_i64(); \
9396 TCGv_i32 t1 = tcg_temp_new_i32(); \
9397 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9398 gen_helper_##name(t0, cpu_env, t1); \
9399 gen_store_gpr64(rD(ctx->opcode), t0); \
9400 tcg_temp_free_i64(t0); \
9401 tcg_temp_free_i32(t1); \
9402 }
9403 #define GEN_SPEFPUOP_CONV_64_64(name) \
9404 static inline void gen_##name(DisasContext *ctx) \
9405 { \
9406 TCGv_i64 t0 = tcg_temp_new_i64(); \
9407 gen_load_gpr64(t0, rB(ctx->opcode)); \
9408 gen_helper_##name(t0, cpu_env, t0); \
9409 gen_store_gpr64(rD(ctx->opcode), t0); \
9410 tcg_temp_free_i64(t0); \
9411 }
9412 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9413 static inline void gen_##name(DisasContext *ctx) \
9414 { \
9415 TCGv_i32 t0, t1; \
9416 if (unlikely(!ctx->spe_enabled)) { \
9417 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9418 return; \
9419 } \
9420 t0 = tcg_temp_new_i32(); \
9421 t1 = tcg_temp_new_i32(); \
9422 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9423 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9424 gen_helper_##name(t0, cpu_env, t0, t1); \
9425 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9426 \
9427 tcg_temp_free_i32(t0); \
9428 tcg_temp_free_i32(t1); \
9429 }
9430 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9431 static inline void gen_##name(DisasContext *ctx) \
9432 { \
9433 TCGv_i64 t0, t1; \
9434 if (unlikely(!ctx->spe_enabled)) { \
9435 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9436 return; \
9437 } \
9438 t0 = tcg_temp_new_i64(); \
9439 t1 = tcg_temp_new_i64(); \
9440 gen_load_gpr64(t0, rA(ctx->opcode)); \
9441 gen_load_gpr64(t1, rB(ctx->opcode)); \
9442 gen_helper_##name(t0, cpu_env, t0, t1); \
9443 gen_store_gpr64(rD(ctx->opcode), t0); \
9444 tcg_temp_free_i64(t0); \
9445 tcg_temp_free_i64(t1); \
9446 }
9447 #define GEN_SPEFPUOP_COMP_32(name) \
9448 static inline void gen_##name(DisasContext *ctx) \
9449 { \
9450 TCGv_i32 t0, t1; \
9451 if (unlikely(!ctx->spe_enabled)) { \
9452 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9453 return; \
9454 } \
9455 t0 = tcg_temp_new_i32(); \
9456 t1 = tcg_temp_new_i32(); \
9457 \
9458 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9459 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9460 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9461 \
9462 tcg_temp_free_i32(t0); \
9463 tcg_temp_free_i32(t1); \
9464 }
9465 #define GEN_SPEFPUOP_COMP_64(name) \
9466 static inline void gen_##name(DisasContext *ctx) \
9467 { \
9468 TCGv_i64 t0, t1; \
9469 if (unlikely(!ctx->spe_enabled)) { \
9470 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9471 return; \
9472 } \
9473 t0 = tcg_temp_new_i64(); \
9474 t1 = tcg_temp_new_i64(); \
9475 gen_load_gpr64(t0, rA(ctx->opcode)); \
9476 gen_load_gpr64(t1, rB(ctx->opcode)); \
9477 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9478 tcg_temp_free_i64(t0); \
9479 tcg_temp_free_i64(t1); \
9480 }
9481
9482 /* Single precision floating-point vectors operations */
9483 /* Arithmetic */
9484 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9485 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9486 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9487 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9488 static inline void gen_evfsabs(DisasContext *ctx)
9489 {
9490 if (unlikely(!ctx->spe_enabled)) {
9491 gen_exception(ctx, POWERPC_EXCP_SPEU);
9492 return;
9493 }
9494 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9495 ~0x80000000);
9496 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9497 ~0x80000000);
9498 }
9499 static inline void gen_evfsnabs(DisasContext *ctx)
9500 {
9501 if (unlikely(!ctx->spe_enabled)) {
9502 gen_exception(ctx, POWERPC_EXCP_SPEU);
9503 return;
9504 }
9505 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9506 0x80000000);
9507 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9508 0x80000000);
9509 }
9510 static inline void gen_evfsneg(DisasContext *ctx)
9511 {
9512 if (unlikely(!ctx->spe_enabled)) {
9513 gen_exception(ctx, POWERPC_EXCP_SPEU);
9514 return;
9515 }
9516 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9517 0x80000000);
9518 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9519 0x80000000);
9520 }
9521
9522 /* Conversion */
9523 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9524 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9525 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9526 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9527 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9528 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9529 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9530 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9531 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9532 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9533
9534 /* Comparison */
9535 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9536 GEN_SPEFPUOP_COMP_64(evfscmplt);
9537 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9538 GEN_SPEFPUOP_COMP_64(evfststgt);
9539 GEN_SPEFPUOP_COMP_64(evfststlt);
9540 GEN_SPEFPUOP_COMP_64(evfststeq);
9541
9542 /* Opcodes definitions */
9543 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9544 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9545 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9546 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9547 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9548 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9549 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9550 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9551 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9552 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9553 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9554 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9555 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9556 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9557
9558 /* Single precision floating-point operations */
9559 /* Arithmetic */
9560 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9561 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9562 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9563 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9564 static inline void gen_efsabs(DisasContext *ctx)
9565 {
9566 if (unlikely(!ctx->spe_enabled)) {
9567 gen_exception(ctx, POWERPC_EXCP_SPEU);
9568 return;
9569 }
9570 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9571 }
9572 static inline void gen_efsnabs(DisasContext *ctx)
9573 {
9574 if (unlikely(!ctx->spe_enabled)) {
9575 gen_exception(ctx, POWERPC_EXCP_SPEU);
9576 return;
9577 }
9578 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9579 }
9580 static inline void gen_efsneg(DisasContext *ctx)
9581 {
9582 if (unlikely(!ctx->spe_enabled)) {
9583 gen_exception(ctx, POWERPC_EXCP_SPEU);
9584 return;
9585 }
9586 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9587 }
9588
9589 /* Conversion */
9590 GEN_SPEFPUOP_CONV_32_32(efscfui);
9591 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9592 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9593 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9594 GEN_SPEFPUOP_CONV_32_32(efsctui);
9595 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9596 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9597 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9598 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9599 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9600 GEN_SPEFPUOP_CONV_32_64(efscfd);
9601
9602 /* Comparison */
9603 GEN_SPEFPUOP_COMP_32(efscmpgt);
9604 GEN_SPEFPUOP_COMP_32(efscmplt);
9605 GEN_SPEFPUOP_COMP_32(efscmpeq);
9606 GEN_SPEFPUOP_COMP_32(efststgt);
9607 GEN_SPEFPUOP_COMP_32(efststlt);
9608 GEN_SPEFPUOP_COMP_32(efststeq);
9609
9610 /* Opcodes definitions */
9611 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9612 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9613 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9614 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9615 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9616 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9617 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9618 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9619 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9620 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9621 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9622 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9623 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9624 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9625
9626 /* Double precision floating-point operations */
9627 /* Arithmetic */
9628 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9629 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9630 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9631 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9632 static inline void gen_efdabs(DisasContext *ctx)
9633 {
9634 if (unlikely(!ctx->spe_enabled)) {
9635 gen_exception(ctx, POWERPC_EXCP_SPEU);
9636 return;
9637 }
9638 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9639 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9640 ~0x80000000);
9641 }
9642 static inline void gen_efdnabs(DisasContext *ctx)
9643 {
9644 if (unlikely(!ctx->spe_enabled)) {
9645 gen_exception(ctx, POWERPC_EXCP_SPEU);
9646 return;
9647 }
9648 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9649 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9650 0x80000000);
9651 }
9652 static inline void gen_efdneg(DisasContext *ctx)
9653 {
9654 if (unlikely(!ctx->spe_enabled)) {
9655 gen_exception(ctx, POWERPC_EXCP_SPEU);
9656 return;
9657 }
9658 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9659 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9660 0x80000000);
9661 }
9662
9663 /* Conversion */
9664 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9665 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9666 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9667 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9668 GEN_SPEFPUOP_CONV_32_64(efdctui);
9669 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9670 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9671 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9672 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9673 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9674 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9675 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9676 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9677 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9678 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9679
9680 /* Comparison */
9681 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9682 GEN_SPEFPUOP_COMP_64(efdcmplt);
9683 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9684 GEN_SPEFPUOP_COMP_64(efdtstgt);
9685 GEN_SPEFPUOP_COMP_64(efdtstlt);
9686 GEN_SPEFPUOP_COMP_64(efdtsteq);
9687
9688 /* Opcodes definitions */
9689 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9690 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9691 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9692 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9693 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9694 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9695 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9696 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9697 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9698 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9699 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9700 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9701 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9702 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9703 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9704 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9705
9706 static void gen_tbegin(DisasContext *ctx)
9707 {
9708 if (unlikely(!ctx->tm_enabled)) {
9709 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9710 return;
9711 }
9712 gen_helper_tbegin(cpu_env);
9713 }
9714
9715 #define GEN_TM_NOOP(name) \
9716 static inline void gen_##name(DisasContext *ctx) \
9717 { \
9718 if (unlikely(!ctx->tm_enabled)) { \
9719 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9720 return; \
9721 } \
9722 /* Because tbegin always fails in QEMU, these user \
9723 * space instructions all have a simple implementation: \
9724 * \
9725 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9726 * = 0b0 || 0b00 || 0b0 \
9727 */ \
9728 tcg_gen_movi_i32(cpu_crf[0], 0); \
9729 }
9730
9731 GEN_TM_NOOP(tend);
9732 GEN_TM_NOOP(tabort);
9733 GEN_TM_NOOP(tabortwc);
9734 GEN_TM_NOOP(tabortwci);
9735 GEN_TM_NOOP(tabortdc);
9736 GEN_TM_NOOP(tabortdci);
9737 GEN_TM_NOOP(tsr);
9738
9739 static void gen_tcheck(DisasContext *ctx)
9740 {
9741 if (unlikely(!ctx->tm_enabled)) {
9742 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9743 return;
9744 }
9745 /* Because tbegin always fails, the tcheck implementation
9746 * is simple:
9747 *
9748 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9749 * = 0b1 || 0b00 || 0b0
9750 */
9751 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
9752 }
9753
9754 #if defined(CONFIG_USER_ONLY)
9755 #define GEN_TM_PRIV_NOOP(name) \
9756 static inline void gen_##name(DisasContext *ctx) \
9757 { \
9758 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9759 }
9760
9761 #else
9762
9763 #define GEN_TM_PRIV_NOOP(name) \
9764 static inline void gen_##name(DisasContext *ctx) \
9765 { \
9766 if (unlikely(ctx->pr)) { \
9767 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9768 return; \
9769 } \
9770 if (unlikely(!ctx->tm_enabled)) { \
9771 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9772 return; \
9773 } \
9774 /* Because tbegin always fails, the implementation is \
9775 * simple: \
9776 * \
9777 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9778 * = 0b0 || 0b00 | 0b0 \
9779 */ \
9780 tcg_gen_movi_i32(cpu_crf[0], 0); \
9781 }
9782
9783 #endif
9784
9785 GEN_TM_PRIV_NOOP(treclaim);
9786 GEN_TM_PRIV_NOOP(trechkpt);
9787
9788 static opcode_t opcodes[] = {
9789 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9790 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9791 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9792 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9793 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9794 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9795 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9796 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9797 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9798 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9799 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9800 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9801 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9802 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9803 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9804 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9805 #if defined(TARGET_PPC64)
9806 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9807 #endif
9808 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9809 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9810 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9811 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9812 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9813 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9814 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9815 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9816 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9817 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9818 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9819 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9820 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
9821 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9822 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9823 #if defined(TARGET_PPC64)
9824 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9825 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9826 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9827 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9828 #endif
9829 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9830 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9831 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9832 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9833 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9834 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9835 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9836 #if defined(TARGET_PPC64)
9837 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9838 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9839 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9840 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9841 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9842 #endif
9843 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9844 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9845 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9846 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9847 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9848 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9849 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9850 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9851 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9852 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9853 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9854 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9855 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9856 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9857 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9858 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9859 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9860 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9861 #if defined(TARGET_PPC64)
9862 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9863 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9864 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9865 #endif
9866 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9867 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9868 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9869 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9870 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9871 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9872 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9873 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9874 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9875 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9876 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9877 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9878 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9879 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9880 #if defined(TARGET_PPC64)
9881 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9882 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9883 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9884 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9885 #endif
9886 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9887 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9888 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9889 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9890 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9891 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9892 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9893 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9894 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9895 #if defined(TARGET_PPC64)
9896 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9897 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9898 #endif
9899 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9900 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9901 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9902 #if defined(TARGET_PPC64)
9903 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9904 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9905 #endif
9906 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9907 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9908 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9909 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9910 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9911 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9912 #if defined(TARGET_PPC64)
9913 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9914 #endif
9915 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9916 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
9917 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9918 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9919 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9920 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9921 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9922 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
9923 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9924 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9925 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9926 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9927 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9928 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9929 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9930 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9931 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9932 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9933 #if defined(TARGET_PPC64)
9934 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9935 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9936 PPC_SEGMENT_64B),
9937 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9938 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9939 PPC_SEGMENT_64B),
9940 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9941 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9942 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9943 #endif
9944 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9945 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9946 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9947 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9948 #if defined(TARGET_PPC64)
9949 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9950 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9951 #endif
9952 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9953 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9954 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9955 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9956 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9957 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9958 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9959 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9960 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9961 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9962 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9963 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9964 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9965 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9966 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9967 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9968 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9969 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9970 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9971 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9972 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9973 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9974 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9975 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9976 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9977 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9978 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9979 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9980 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9981 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9982 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9983 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9984 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9985 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9986 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9987 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9988 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9989 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9990 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9991 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
9992 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
9993 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
9994 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
9995 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
9996 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
9997 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
9998 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
9999 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
10000 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
10001 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10002 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10003 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
10004 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
10005 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10006 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10007 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
10008 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
10009 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
10010 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
10011 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
10012 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
10013 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
10014 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
10015 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
10016 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
10017 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
10018 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
10019 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
10020 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
10021 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
10022 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
10023 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
10024 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
10025 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
10026 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
10027 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
10028 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10029 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10030 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10031 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
10032 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10033 PPC_NONE, PPC2_BOOKE206),
10034 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10035 PPC_NONE, PPC2_BOOKE206),
10036 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10037 PPC_NONE, PPC2_BOOKE206),
10038 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10039 PPC_NONE, PPC2_BOOKE206),
10040 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10041 PPC_NONE, PPC2_BOOKE206),
10042 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10043 PPC_NONE, PPC2_PRCNTL),
10044 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10045 PPC_NONE, PPC2_PRCNTL),
10046 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
10047 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
10048 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
10049 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10050 PPC_BOOKE, PPC2_BOOKE206),
10051 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
10052 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10053 PPC_BOOKE, PPC2_BOOKE206),
10054 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10055 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10056 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10057 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
10058 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10059 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10060 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10061 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10062 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10063
10064 #undef GEN_INT_ARITH_ADD
10065 #undef GEN_INT_ARITH_ADD_CONST
10066 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10067 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10068 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10069 add_ca, compute_ca, compute_ov) \
10070 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10071 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10072 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10073 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10074 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10075 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10076 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10077 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10078 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10079 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10080 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10081
10082 #undef GEN_INT_ARITH_DIVW
10083 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10084 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10085 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10086 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10087 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10088 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
10089 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10090 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10091 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10092 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10093
10094 #if defined(TARGET_PPC64)
10095 #undef GEN_INT_ARITH_DIVD
10096 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10097 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10098 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10099 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10100 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10101 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10102
10103 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10104 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10105 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10106 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10107
10108 #undef GEN_INT_ARITH_MUL_HELPER
10109 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10110 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10111 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10112 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10113 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10114 #endif
10115
10116 #undef GEN_INT_ARITH_SUBF
10117 #undef GEN_INT_ARITH_SUBF_CONST
10118 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10119 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10120 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10121 add_ca, compute_ca, compute_ov) \
10122 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10123 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10124 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10125 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10126 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10127 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10128 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10129 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10130 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10131 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10132 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10133
10134 #undef GEN_LOGICAL1
10135 #undef GEN_LOGICAL2
10136 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10137 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10138 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10139 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10140 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10141 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10142 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10143 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10144 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10145 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10146 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10147 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10148 #if defined(TARGET_PPC64)
10149 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10150 #endif
10151
10152 #if defined(TARGET_PPC64)
10153 #undef GEN_PPC64_R2
10154 #undef GEN_PPC64_R4
10155 #define GEN_PPC64_R2(name, opc1, opc2) \
10156 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10157 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10158 PPC_64B)
10159 #define GEN_PPC64_R4(name, opc1, opc2) \
10160 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10161 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10162 PPC_64B), \
10163 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10164 PPC_64B), \
10165 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10166 PPC_64B)
10167 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10168 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10169 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10170 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10171 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10172 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10173 #endif
10174
10175 #undef _GEN_FLOAT_ACB
10176 #undef GEN_FLOAT_ACB
10177 #undef _GEN_FLOAT_AB
10178 #undef GEN_FLOAT_AB
10179 #undef _GEN_FLOAT_AC
10180 #undef GEN_FLOAT_AC
10181 #undef GEN_FLOAT_B
10182 #undef GEN_FLOAT_BS
10183 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10184 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10185 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10186 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10187 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10188 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10189 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10190 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10191 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10192 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10193 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10194 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10195 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10196 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10197 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10198 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10199 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10200 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10201 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10202
10203 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10204 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10205 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10206 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10207 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10208 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10209 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10210 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10211 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10212 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10213 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10214 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10215 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10216 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10217 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10218 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10219 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10220 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10221 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10222 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10223 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10224 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10225 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10226 GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10227 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10228 GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10229 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10230 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10231 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10232 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10233 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10234
10235 #undef GEN_LD
10236 #undef GEN_LDU
10237 #undef GEN_LDUX
10238 #undef GEN_LDX_E
10239 #undef GEN_LDS
10240 #define GEN_LD(name, ldop, opc, type) \
10241 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10242 #define GEN_LDU(name, ldop, opc, type) \
10243 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10244 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10245 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10246 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10247 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10248 #define GEN_LDS(name, ldop, op, type) \
10249 GEN_LD(name, ldop, op | 0x20, type) \
10250 GEN_LDU(name, ldop, op | 0x21, type) \
10251 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10252 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10253
10254 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10255 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10256 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10257 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10258 #if defined(TARGET_PPC64)
10259 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10260 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10261 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10262 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10263 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10264 #endif
10265 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10266 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10267
10268 #undef GEN_ST
10269 #undef GEN_STU
10270 #undef GEN_STUX
10271 #undef GEN_STX_E
10272 #undef GEN_STS
10273 #define GEN_ST(name, stop, opc, type) \
10274 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10275 #define GEN_STU(name, stop, opc, type) \
10276 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10277 #define GEN_STUX(name, stop, opc2, opc3, type) \
10278 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10279 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10280 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10281 #define GEN_STS(name, stop, op, type) \
10282 GEN_ST(name, stop, op | 0x20, type) \
10283 GEN_STU(name, stop, op | 0x21, type) \
10284 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10285 GEN_STX(name, stop, 0x17, op | 0x00, type)
10286
10287 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10288 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10289 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10290 #if defined(TARGET_PPC64)
10291 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10292 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10293 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10294 #endif
10295 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10296 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10297
10298 #undef GEN_LDF
10299 #undef GEN_LDUF
10300 #undef GEN_LDUXF
10301 #undef GEN_LDXF
10302 #undef GEN_LDFS
10303 #define GEN_LDF(name, ldop, opc, type) \
10304 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10305 #define GEN_LDUF(name, ldop, opc, type) \
10306 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10307 #define GEN_LDUXF(name, ldop, opc, type) \
10308 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10309 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10310 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10311 #define GEN_LDFS(name, ldop, op, type) \
10312 GEN_LDF(name, ldop, op | 0x20, type) \
10313 GEN_LDUF(name, ldop, op | 0x21, type) \
10314 GEN_LDUXF(name, ldop, op | 0x01, type) \
10315 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10316
10317 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10318 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10319 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10320 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10321 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10322 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10323
10324 #undef GEN_STF
10325 #undef GEN_STUF
10326 #undef GEN_STUXF
10327 #undef GEN_STXF
10328 #undef GEN_STFS
10329 #define GEN_STF(name, stop, opc, type) \
10330 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10331 #define GEN_STUF(name, stop, opc, type) \
10332 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10333 #define GEN_STUXF(name, stop, opc, type) \
10334 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10335 #define GEN_STXF(name, stop, opc2, opc3, type) \
10336 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10337 #define GEN_STFS(name, stop, op, type) \
10338 GEN_STF(name, stop, op | 0x20, type) \
10339 GEN_STUF(name, stop, op | 0x21, type) \
10340 GEN_STUXF(name, stop, op | 0x01, type) \
10341 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10342
10343 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10344 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10345 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10346 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10347 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10348
10349 #undef GEN_CRLOGIC
10350 #define GEN_CRLOGIC(name, tcg_op, opc) \
10351 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10352 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10353 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10354 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10355 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10356 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10357 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10358 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10359 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10360
10361 #undef GEN_MAC_HANDLER
10362 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10363 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10364 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10365 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10366 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10367 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10368 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10369 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10370 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10371 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10372 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10373 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10374 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10375 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10376 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10377 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10378 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10379 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10380 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10381 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10382 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10383 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10384 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10385 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10386 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10387 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10388 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10389 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10390 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10391 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10392 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10393 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10394 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10395 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10396 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10397 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10398 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10399 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10400 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10401 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10402 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10403 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10404 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10405 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10406
10407 #undef GEN_VR_LDX
10408 #undef GEN_VR_STX
10409 #undef GEN_VR_LVE
10410 #undef GEN_VR_STVE
10411 #define GEN_VR_LDX(name, opc2, opc3) \
10412 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10413 #define GEN_VR_STX(name, opc2, opc3) \
10414 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10415 #define GEN_VR_LVE(name, opc2, opc3) \
10416 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10417 #define GEN_VR_STVE(name, opc2, opc3) \
10418 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10419 GEN_VR_LDX(lvx, 0x07, 0x03),
10420 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10421 GEN_VR_LVE(bx, 0x07, 0x00),
10422 GEN_VR_LVE(hx, 0x07, 0x01),
10423 GEN_VR_LVE(wx, 0x07, 0x02),
10424 GEN_VR_STX(svx, 0x07, 0x07),
10425 GEN_VR_STX(svxl, 0x07, 0x0F),
10426 GEN_VR_STVE(bx, 0x07, 0x04),
10427 GEN_VR_STVE(hx, 0x07, 0x05),
10428 GEN_VR_STVE(wx, 0x07, 0x06),
10429
10430 #undef GEN_VX_LOGICAL
10431 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10432 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10433
10434 #undef GEN_VX_LOGICAL_207
10435 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10436 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10437
10438 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10439 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10440 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10441 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10442 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10443 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10444 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10445 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10446
10447 #undef GEN_VXFORM
10448 #define GEN_VXFORM(name, opc2, opc3) \
10449 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10450
10451 #undef GEN_VXFORM_207
10452 #define GEN_VXFORM_207(name, opc2, opc3) \
10453 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10454
10455 #undef GEN_VXFORM_DUAL
10456 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10457 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10458
10459 #undef GEN_VXRFORM_DUAL
10460 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10461 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10462 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10463
10464 GEN_VXFORM(vaddubm, 0, 0),
10465 GEN_VXFORM(vadduhm, 0, 1),
10466 GEN_VXFORM(vadduwm, 0, 2),
10467 GEN_VXFORM_207(vaddudm, 0, 3),
10468 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10469 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10470 GEN_VXFORM(vsubuwm, 0, 18),
10471 GEN_VXFORM_207(vsubudm, 0, 19),
10472 GEN_VXFORM(vmaxub, 1, 0),
10473 GEN_VXFORM(vmaxuh, 1, 1),
10474 GEN_VXFORM(vmaxuw, 1, 2),
10475 GEN_VXFORM_207(vmaxud, 1, 3),
10476 GEN_VXFORM(vmaxsb, 1, 4),
10477 GEN_VXFORM(vmaxsh, 1, 5),
10478 GEN_VXFORM(vmaxsw, 1, 6),
10479 GEN_VXFORM_207(vmaxsd, 1, 7),
10480 GEN_VXFORM(vminub, 1, 8),
10481 GEN_VXFORM(vminuh, 1, 9),
10482 GEN_VXFORM(vminuw, 1, 10),
10483 GEN_VXFORM_207(vminud, 1, 11),
10484 GEN_VXFORM(vminsb, 1, 12),
10485 GEN_VXFORM(vminsh, 1, 13),
10486 GEN_VXFORM(vminsw, 1, 14),
10487 GEN_VXFORM_207(vminsd, 1, 15),
10488 GEN_VXFORM(vavgub, 1, 16),
10489 GEN_VXFORM(vavguh, 1, 17),
10490 GEN_VXFORM(vavguw, 1, 18),
10491 GEN_VXFORM(vavgsb, 1, 20),
10492 GEN_VXFORM(vavgsh, 1, 21),
10493 GEN_VXFORM(vavgsw, 1, 22),
10494 GEN_VXFORM(vmrghb, 6, 0),
10495 GEN_VXFORM(vmrghh, 6, 1),
10496 GEN_VXFORM(vmrghw, 6, 2),
10497 GEN_VXFORM(vmrglb, 6, 4),
10498 GEN_VXFORM(vmrglh, 6, 5),
10499 GEN_VXFORM(vmrglw, 6, 6),
10500 GEN_VXFORM_207(vmrgew, 6, 30),
10501 GEN_VXFORM_207(vmrgow, 6, 26),
10502 GEN_VXFORM(vmuloub, 4, 0),
10503 GEN_VXFORM(vmulouh, 4, 1),
10504 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10505 GEN_VXFORM(vmulosb, 4, 4),
10506 GEN_VXFORM(vmulosh, 4, 5),
10507 GEN_VXFORM_207(vmulosw, 4, 6),
10508 GEN_VXFORM(vmuleub, 4, 8),
10509 GEN_VXFORM(vmuleuh, 4, 9),
10510 GEN_VXFORM_207(vmuleuw, 4, 10),
10511 GEN_VXFORM(vmulesb, 4, 12),
10512 GEN_VXFORM(vmulesh, 4, 13),
10513 GEN_VXFORM_207(vmulesw, 4, 14),
10514 GEN_VXFORM(vslb, 2, 4),
10515 GEN_VXFORM(vslh, 2, 5),
10516 GEN_VXFORM(vslw, 2, 6),
10517 GEN_VXFORM_207(vsld, 2, 23),
10518 GEN_VXFORM(vsrb, 2, 8),
10519 GEN_VXFORM(vsrh, 2, 9),
10520 GEN_VXFORM(vsrw, 2, 10),
10521 GEN_VXFORM_207(vsrd, 2, 27),
10522 GEN_VXFORM(vsrab, 2, 12),
10523 GEN_VXFORM(vsrah, 2, 13),
10524 GEN_VXFORM(vsraw, 2, 14),
10525 GEN_VXFORM_207(vsrad, 2, 15),
10526 GEN_VXFORM(vslo, 6, 16),
10527 GEN_VXFORM(vsro, 6, 17),
10528 GEN_VXFORM(vaddcuw, 0, 6),
10529 GEN_VXFORM(vsubcuw, 0, 22),
10530 GEN_VXFORM(vaddubs, 0, 8),
10531 GEN_VXFORM(vadduhs, 0, 9),
10532 GEN_VXFORM(vadduws, 0, 10),
10533 GEN_VXFORM(vaddsbs, 0, 12),
10534 GEN_VXFORM(vaddshs, 0, 13),
10535 GEN_VXFORM(vaddsws, 0, 14),
10536 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10537 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10538 GEN_VXFORM(vsubuws, 0, 26),
10539 GEN_VXFORM(vsubsbs, 0, 28),
10540 GEN_VXFORM(vsubshs, 0, 29),
10541 GEN_VXFORM(vsubsws, 0, 30),
10542 GEN_VXFORM_207(vadduqm, 0, 4),
10543 GEN_VXFORM_207(vaddcuq, 0, 5),
10544 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10545 GEN_VXFORM_207(vsubuqm, 0, 20),
10546 GEN_VXFORM_207(vsubcuq, 0, 21),
10547 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10548 GEN_VXFORM(vrlb, 2, 0),
10549 GEN_VXFORM(vrlh, 2, 1),
10550 GEN_VXFORM(vrlw, 2, 2),
10551 GEN_VXFORM_207(vrld, 2, 3),
10552 GEN_VXFORM(vsl, 2, 7),
10553 GEN_VXFORM(vsr, 2, 11),
10554 GEN_VXFORM(vpkuhum, 7, 0),
10555 GEN_VXFORM(vpkuwum, 7, 1),
10556 GEN_VXFORM_207(vpkudum, 7, 17),
10557 GEN_VXFORM(vpkuhus, 7, 2),
10558 GEN_VXFORM(vpkuwus, 7, 3),
10559 GEN_VXFORM_207(vpkudus, 7, 19),
10560 GEN_VXFORM(vpkshus, 7, 4),
10561 GEN_VXFORM(vpkswus, 7, 5),
10562 GEN_VXFORM_207(vpksdus, 7, 21),
10563 GEN_VXFORM(vpkshss, 7, 6),
10564 GEN_VXFORM(vpkswss, 7, 7),
10565 GEN_VXFORM_207(vpksdss, 7, 23),
10566 GEN_VXFORM(vpkpx, 7, 12),
10567 GEN_VXFORM(vsum4ubs, 4, 24),
10568 GEN_VXFORM(vsum4sbs, 4, 28),
10569 GEN_VXFORM(vsum4shs, 4, 25),
10570 GEN_VXFORM(vsum2sws, 4, 26),
10571 GEN_VXFORM(vsumsws, 4, 30),
10572 GEN_VXFORM(vaddfp, 5, 0),
10573 GEN_VXFORM(vsubfp, 5, 1),
10574 GEN_VXFORM(vmaxfp, 5, 16),
10575 GEN_VXFORM(vminfp, 5, 17),
10576
10577 #undef GEN_VXRFORM1
10578 #undef GEN_VXRFORM
10579 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10580 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10581 #define GEN_VXRFORM(name, opc2, opc3) \
10582 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10583 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10584 GEN_VXRFORM(vcmpequb, 3, 0)
10585 GEN_VXRFORM(vcmpequh, 3, 1)
10586 GEN_VXRFORM(vcmpequw, 3, 2)
10587 GEN_VXRFORM(vcmpgtsb, 3, 12)
10588 GEN_VXRFORM(vcmpgtsh, 3, 13)
10589 GEN_VXRFORM(vcmpgtsw, 3, 14)
10590 GEN_VXRFORM(vcmpgtub, 3, 8)
10591 GEN_VXRFORM(vcmpgtuh, 3, 9)
10592 GEN_VXRFORM(vcmpgtuw, 3, 10)
10593 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10594 GEN_VXRFORM(vcmpgefp, 3, 7)
10595 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10596 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10597
10598 #undef GEN_VXFORM_SIMM
10599 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10600 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10601 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10602 GEN_VXFORM_SIMM(vspltish, 6, 13),
10603 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10604
10605 #undef GEN_VXFORM_NOA
10606 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10607 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10608 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10609 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10610 GEN_VXFORM_207(vupkhsw, 7, 25),
10611 GEN_VXFORM_NOA(vupklsb, 7, 10),
10612 GEN_VXFORM_NOA(vupklsh, 7, 11),
10613 GEN_VXFORM_207(vupklsw, 7, 27),
10614 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10615 GEN_VXFORM_NOA(vupklpx, 7, 15),
10616 GEN_VXFORM_NOA(vrefp, 5, 4),
10617 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10618 GEN_VXFORM_NOA(vexptefp, 5, 6),
10619 GEN_VXFORM_NOA(vlogefp, 5, 7),
10620 GEN_VXFORM_NOA(vrfim, 5, 11),
10621 GEN_VXFORM_NOA(vrfin, 5, 8),
10622 GEN_VXFORM_NOA(vrfip, 5, 10),
10623 GEN_VXFORM_NOA(vrfiz, 5, 9),
10624
10625 #undef GEN_VXFORM_UIMM
10626 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10627 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10628 GEN_VXFORM_UIMM(vspltb, 6, 8),
10629 GEN_VXFORM_UIMM(vsplth, 6, 9),
10630 GEN_VXFORM_UIMM(vspltw, 6, 10),
10631 GEN_VXFORM_UIMM(vcfux, 5, 12),
10632 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10633 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10634 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10635
10636 #undef GEN_VAFORM_PAIRED
10637 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10638 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10639 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10640 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10641 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10642 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10643 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10644 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10645
10646 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10647 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10648 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10649 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10650
10651 GEN_VXFORM_207(vbpermq, 6, 21),
10652 GEN_VXFORM_207(vgbbd, 6, 20),
10653 GEN_VXFORM_207(vpmsumb, 4, 16),
10654 GEN_VXFORM_207(vpmsumh, 4, 17),
10655 GEN_VXFORM_207(vpmsumw, 4, 18),
10656 GEN_VXFORM_207(vpmsumd, 4, 19),
10657
10658 GEN_VXFORM_207(vsbox, 4, 23),
10659
10660 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10661 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10662
10663 GEN_VXFORM_207(vshasigmaw, 1, 26),
10664 GEN_VXFORM_207(vshasigmad, 1, 27),
10665
10666 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10667
10668 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10669 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10670 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10671 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10672 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10673 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10674 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10675
10676 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10677 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10678 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10679 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10680 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10681
10682 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10683 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10684 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10685 #if defined(TARGET_PPC64)
10686 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10687 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10688 #endif
10689
10690 #undef GEN_XX2FORM
10691 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10692 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10693 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10694
10695 #undef GEN_XX3FORM
10696 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10697 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10698 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10699 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10700 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10701
10702 #undef GEN_XX2IFORM
10703 #define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10704 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10705 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10706 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10707 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10708
10709 #undef GEN_XX3_RC_FORM
10710 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10711 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10712 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10713 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10714 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10715 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10716 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10717 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10718 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10719
10720 #undef GEN_XX3FORM_DM
10721 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10722 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10723 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10724 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10725 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10726 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10727 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10728 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10729 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10730 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10731 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10732 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10733 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10734 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10735 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10736 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10737 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10738
10739 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10740 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10741 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10742 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10743
10744 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10745 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10746 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10747 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10748 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10749 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10750 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10751 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10752
10753 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10754 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10755 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10756 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10757 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10758 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10759 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10760 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10761 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10762 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10763 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10764 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10765 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10766 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10767 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10768 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10769 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10770 GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10771 GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10772 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10773 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10774 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10775 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10776 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10777 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10778 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10779 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10780 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10781 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10782 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10783 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10784 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10785 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10786 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10787 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10788 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10789
10790 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10791 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10792 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10793 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10794 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10795 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10796 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10797 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10798 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10799 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10800 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10801 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10802 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10803 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10804 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10805 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10806 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10807 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10808
10809 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10810 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10811 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10812 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10813 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10814 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10815 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10816 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10817 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10818 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10819 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10820 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10821 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10822 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10823 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10824 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10825 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10826 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10827 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10828 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10829 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10830 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10831 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10832 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10833 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10834 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10835 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10836 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10837 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10838 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10839 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10840 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10841 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10842 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10843 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10844 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10845
10846 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10847 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10848 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10849 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10850 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10851 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10852 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10853 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10854 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10855 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10856 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10857 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10858 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10859 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10860 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10861 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10862 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10863 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10864 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10865 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10866 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10867 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10868 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10869 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10870 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10871 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10872 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10873 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10874 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10875 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10876 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10877 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10878 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10879 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10880 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10881 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10882
10883 #undef VSX_LOGICAL
10884 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10885 GEN_XX3FORM(name, opc2, opc3, fl2)
10886
10887 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10888 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10889 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10890 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10891 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10892 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10893 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10894 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10895 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10896 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10897 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10898 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10899
10900 #define GEN_XXSEL_ROW(opc3) \
10901 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10902 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10903 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10904 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10905 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10906 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10907 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10908 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10909
10910 GEN_XXSEL_ROW(0x00)
10911 GEN_XXSEL_ROW(0x01)
10912 GEN_XXSEL_ROW(0x02)
10913 GEN_XXSEL_ROW(0x03)
10914 GEN_XXSEL_ROW(0x04)
10915 GEN_XXSEL_ROW(0x05)
10916 GEN_XXSEL_ROW(0x06)
10917 GEN_XXSEL_ROW(0x07)
10918 GEN_XXSEL_ROW(0x08)
10919 GEN_XXSEL_ROW(0x09)
10920 GEN_XXSEL_ROW(0x0A)
10921 GEN_XXSEL_ROW(0x0B)
10922 GEN_XXSEL_ROW(0x0C)
10923 GEN_XXSEL_ROW(0x0D)
10924 GEN_XXSEL_ROW(0x0E)
10925 GEN_XXSEL_ROW(0x0F)
10926 GEN_XXSEL_ROW(0x10)
10927 GEN_XXSEL_ROW(0x11)
10928 GEN_XXSEL_ROW(0x12)
10929 GEN_XXSEL_ROW(0x13)
10930 GEN_XXSEL_ROW(0x14)
10931 GEN_XXSEL_ROW(0x15)
10932 GEN_XXSEL_ROW(0x16)
10933 GEN_XXSEL_ROW(0x17)
10934 GEN_XXSEL_ROW(0x18)
10935 GEN_XXSEL_ROW(0x19)
10936 GEN_XXSEL_ROW(0x1A)
10937 GEN_XXSEL_ROW(0x1B)
10938 GEN_XXSEL_ROW(0x1C)
10939 GEN_XXSEL_ROW(0x1D)
10940 GEN_XXSEL_ROW(0x1E)
10941 GEN_XXSEL_ROW(0x1F)
10942
10943 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10944
10945 #undef GEN_DFP_T_A_B_Rc
10946 #undef GEN_DFP_BF_A_B
10947 #undef GEN_DFP_BF_A_DCM
10948 #undef GEN_DFP_T_B_U32_U32_Rc
10949 #undef GEN_DFP_T_A_B_I32_Rc
10950 #undef GEN_DFP_T_B_Rc
10951 #undef GEN_DFP_T_FPR_I32_Rc
10952
10953 #define _GEN_DFP_LONG(name, op1, op2, mask) \
10954 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10955
10956 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10957 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10958 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10959
10960 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10961 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10962 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10963 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10964 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10965
10966 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
10967 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10968
10969 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10970 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10971 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10972
10973 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10974 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10975 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10976 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10977 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10978
10979 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10980 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
10981
10982 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10983 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10984
10985 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10986 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10987
10988 #define GEN_DFP_T_B_Rc(name, op1, op2) \
10989 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10990
10991 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
10992 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
10993
10994 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
10995 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
10996
10997 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
10998 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
10999
11000 #define GEN_DFP_BF_A_B(name, op1, op2) \
11001 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
11002
11003 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
11004 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
11005
11006 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
11007 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
11008
11009 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
11010 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
11011
11012 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
11013 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
11014
11015 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
11016 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11017
11018 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
11019 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
11020
11021 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
11022 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
11023
11024 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
11025 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11026
11027 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
11028 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11029
11030 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11031 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11032
11033 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11034 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11035
11036 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11037 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
11038
11039 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11040 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11041
11042 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11043 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11044
11045 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11046 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11047
11048 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11049 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11050
11051 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11052 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11053
11054 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11055 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
11056 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11057 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
11058 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11059 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
11060 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11061 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
11062 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11063 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11064 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11065 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
11066 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11067 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
11068 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11069 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
11070 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11071 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
11072 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11073 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
11074 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11075 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11076 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11077 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
11078 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11079 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
11080 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11081 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11082 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11083 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
11084 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11085 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
11086 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11087 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
11088 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11089 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
11090 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11091 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
11092 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11093 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
11094 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11095 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
11096 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11097 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
11098 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11099 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
11100 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11101 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11102 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11103 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11104
11105 #undef GEN_SPE
11106 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11107 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11108 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11109 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11110 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11111 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11112 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11113 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11114 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11115 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11116 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11117 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11118 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11119 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11120 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11121 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11122 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11123 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11124 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11125 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11126 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11127 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11128 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11129 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11130 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11131 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11132 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11133 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11134 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11135 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11136 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11137
11138 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11139 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11140 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11141 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11142 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11143 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11144 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11145 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11146 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11147 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11148 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11149 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11150 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11151 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11152
11153 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11154 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11155 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11156 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11157 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11158 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11159 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11160 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11161 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11162 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11163 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11164 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11165 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11166 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11167
11168 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11169 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11170 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11171 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11172 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11173 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11174 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11175 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11176 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11177 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11178 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11179 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11180 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11181 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11182 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11183 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11184
11185 #undef GEN_SPEOP_LDST
11186 #define GEN_SPEOP_LDST(name, opc2, sh) \
11187 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11188 GEN_SPEOP_LDST(evldd, 0x00, 3),
11189 GEN_SPEOP_LDST(evldw, 0x01, 3),
11190 GEN_SPEOP_LDST(evldh, 0x02, 3),
11191 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11192 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11193 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11194 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11195 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11196 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11197 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11198 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11199
11200 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11201 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11202 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11203 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11204 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11205 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11206 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11207
11208 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11209 PPC_NONE, PPC2_TM),
11210 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11211 PPC_NONE, PPC2_TM),
11212 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11213 PPC_NONE, PPC2_TM),
11214 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11215 PPC_NONE, PPC2_TM),
11216 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11217 PPC_NONE, PPC2_TM),
11218 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11219 PPC_NONE, PPC2_TM),
11220 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11221 PPC_NONE, PPC2_TM),
11222 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11223 PPC_NONE, PPC2_TM),
11224 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11225 PPC_NONE, PPC2_TM),
11226 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11227 PPC_NONE, PPC2_TM),
11228 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11229 PPC_NONE, PPC2_TM),
11230 };
11231
11232 #include "helper_regs.h"
11233 #include "translate_init.c"
11234
11235 /*****************************************************************************/
11236 /* Misc PowerPC helpers */
11237 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11238 int flags)
11239 {
11240 #define RGPL 4
11241 #define RFPL 4
11242
11243 PowerPCCPU *cpu = POWERPC_CPU(cs);
11244 CPUPPCState *env = &cpu->env;
11245 int i;
11246
11247 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11248 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
11249 env->nip, env->lr, env->ctr, cpu_read_xer(env),
11250 cs->cpu_index);
11251 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11252 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
11253 env->hflags, env->mmu_idx);
11254 #if !defined(NO_TIMER_DUMP)
11255 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11256 #if !defined(CONFIG_USER_ONLY)
11257 " DECR %08" PRIu32
11258 #endif
11259 "\n",
11260 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11261 #if !defined(CONFIG_USER_ONLY)
11262 , cpu_ppc_load_decr(env)
11263 #endif
11264 );
11265 #endif
11266 for (i = 0; i < 32; i++) {
11267 if ((i & (RGPL - 1)) == 0)
11268 cpu_fprintf(f, "GPR%02d", i);
11269 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11270 if ((i & (RGPL - 1)) == (RGPL - 1))
11271 cpu_fprintf(f, "\n");
11272 }
11273 cpu_fprintf(f, "CR ");
11274 for (i = 0; i < 8; i++)
11275 cpu_fprintf(f, "%01x", env->crf[i]);
11276 cpu_fprintf(f, " [");
11277 for (i = 0; i < 8; i++) {
11278 char a = '-';
11279 if (env->crf[i] & 0x08)
11280 a = 'L';
11281 else if (env->crf[i] & 0x04)
11282 a = 'G';
11283 else if (env->crf[i] & 0x02)
11284 a = 'E';
11285 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11286 }
11287 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11288 env->reserve_addr);
11289 for (i = 0; i < 32; i++) {
11290 if ((i & (RFPL - 1)) == 0)
11291 cpu_fprintf(f, "FPR%02d", i);
11292 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11293 if ((i & (RFPL - 1)) == (RFPL - 1))
11294 cpu_fprintf(f, "\n");
11295 }
11296 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11297 #if !defined(CONFIG_USER_ONLY)
11298 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11299 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11300 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11301 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11302
11303 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11304 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11305 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11306 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11307
11308 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11309 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11310 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11311 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11312
11313 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11314 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11315 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11316 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11317 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11318
11319 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11320 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11321 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11322 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11323
11324 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11325 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11326 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11327 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11328
11329 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11330 " EPR " TARGET_FMT_lx "\n",
11331 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11332 env->spr[SPR_BOOKE_EPR]);
11333
11334 /* FSL-specific */
11335 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11336 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11337 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11338 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11339
11340 /*
11341 * IVORs are left out as they are large and do not change often --
11342 * they can be read with "p $ivor0", "p $ivor1", etc.
11343 */
11344 }
11345
11346 #if defined(TARGET_PPC64)
11347 if (env->flags & POWERPC_FLAG_CFAR) {
11348 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11349 }
11350 #endif
11351
11352 switch (env->mmu_model) {
11353 case POWERPC_MMU_32B:
11354 case POWERPC_MMU_601:
11355 case POWERPC_MMU_SOFT_6xx:
11356 case POWERPC_MMU_SOFT_74xx:
11357 #if defined(TARGET_PPC64)
11358 case POWERPC_MMU_64B:
11359 case POWERPC_MMU_2_03:
11360 case POWERPC_MMU_2_06:
11361 case POWERPC_MMU_2_06a:
11362 case POWERPC_MMU_2_07:
11363 case POWERPC_MMU_2_07a:
11364 #endif
11365 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11366 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11367 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11368 break;
11369 case POWERPC_MMU_BOOKE206:
11370 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11371 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11372 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11373 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11374
11375 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11376 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11377 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11378 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11379
11380 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11381 " TLB1CFG " TARGET_FMT_lx "\n",
11382 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11383 env->spr[SPR_BOOKE_TLB1CFG]);
11384 break;
11385 default:
11386 break;
11387 }
11388 #endif
11389
11390 #undef RGPL
11391 #undef RFPL
11392 }
11393
11394 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11395 fprintf_function cpu_fprintf, int flags)
11396 {
11397 #if defined(DO_PPC_STATISTICS)
11398 PowerPCCPU *cpu = POWERPC_CPU(cs);
11399 opc_handler_t **t1, **t2, **t3, *handler;
11400 int op1, op2, op3;
11401
11402 t1 = cpu->env.opcodes;
11403 for (op1 = 0; op1 < 64; op1++) {
11404 handler = t1[op1];
11405 if (is_indirect_opcode(handler)) {
11406 t2 = ind_table(handler);
11407 for (op2 = 0; op2 < 32; op2++) {
11408 handler = t2[op2];
11409 if (is_indirect_opcode(handler)) {
11410 t3 = ind_table(handler);
11411 for (op3 = 0; op3 < 32; op3++) {
11412 handler = t3[op3];
11413 if (handler->count == 0)
11414 continue;
11415 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11416 "%016" PRIx64 " %" PRId64 "\n",
11417 op1, op2, op3, op1, (op3 << 5) | op2,
11418 handler->oname,
11419 handler->count, handler->count);
11420 }
11421 } else {
11422 if (handler->count == 0)
11423 continue;
11424 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11425 "%016" PRIx64 " %" PRId64 "\n",
11426 op1, op2, op1, op2, handler->oname,
11427 handler->count, handler->count);
11428 }
11429 }
11430 } else {
11431 if (handler->count == 0)
11432 continue;
11433 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11434 " %" PRId64 "\n",
11435 op1, op1, handler->oname,
11436 handler->count, handler->count);
11437 }
11438 }
11439 #endif
11440 }
11441
11442 /*****************************************************************************/
11443 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
11444 {
11445 PowerPCCPU *cpu = ppc_env_get_cpu(env);
11446 CPUState *cs = CPU(cpu);
11447 DisasContext ctx, *ctxp = &ctx;
11448 opc_handler_t **table, *handler;
11449 target_ulong pc_start;
11450 int num_insns;
11451 int max_insns;
11452
11453 pc_start = tb->pc;
11454 ctx.nip = pc_start;
11455 ctx.tb = tb;
11456 ctx.exception = POWERPC_EXCP_NONE;
11457 ctx.spr_cb = env->spr_cb;
11458 ctx.pr = msr_pr;
11459 ctx.hv = !msr_pr && msr_hv;
11460 ctx.mem_idx = env->mmu_idx;
11461 ctx.insns_flags = env->insns_flags;
11462 ctx.insns_flags2 = env->insns_flags2;
11463 ctx.access_type = -1;
11464 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11465 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11466 #if defined(TARGET_PPC64)
11467 ctx.sf_mode = msr_is_64bit(env, env->msr);
11468 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11469 #endif
11470 ctx.fpu_enabled = msr_fp;
11471 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11472 ctx.spe_enabled = msr_spe;
11473 else
11474 ctx.spe_enabled = 0;
11475 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11476 ctx.altivec_enabled = msr_vr;
11477 else
11478 ctx.altivec_enabled = 0;
11479 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11480 ctx.vsx_enabled = msr_vsx;
11481 } else {
11482 ctx.vsx_enabled = 0;
11483 }
11484 #if defined(TARGET_PPC64)
11485 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11486 ctx.tm_enabled = msr_tm;
11487 } else {
11488 ctx.tm_enabled = 0;
11489 }
11490 #endif
11491 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11492 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11493 else
11494 ctx.singlestep_enabled = 0;
11495 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11496 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11497 if (unlikely(cs->singlestep_enabled)) {
11498 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11499 }
11500 #if defined (DO_SINGLE_STEP) && 0
11501 /* Single step trace mode */
11502 msr_se = 1;
11503 #endif
11504 num_insns = 0;
11505 max_insns = tb->cflags & CF_COUNT_MASK;
11506 if (max_insns == 0) {
11507 max_insns = CF_COUNT_MASK;
11508 }
11509 if (max_insns > TCG_MAX_INSNS) {
11510 max_insns = TCG_MAX_INSNS;
11511 }
11512
11513 gen_tb_start(tb);
11514 tcg_clear_temp_count();
11515 /* Set env in case of segfault during code fetch */
11516 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
11517 tcg_gen_insn_start(ctx.nip);
11518 num_insns++;
11519
11520 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
11521 gen_debug_exception(ctxp);
11522 /* The address covered by the breakpoint must be included in
11523 [tb->pc, tb->pc + tb->size) in order to for it to be
11524 properly cleared -- thus we increment the PC here so that
11525 the logic setting tb->size below does the right thing. */
11526 ctx.nip += 4;
11527 break;
11528 }
11529
11530 LOG_DISAS("----------------\n");
11531 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11532 ctx.nip, ctx.mem_idx, (int)msr_ir);
11533 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
11534 gen_io_start();
11535 if (unlikely(need_byteswap(&ctx))) {
11536 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11537 } else {
11538 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11539 }
11540 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11541 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11542 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11543 ctx.nip += 4;
11544 table = env->opcodes;
11545 handler = table[opc1(ctx.opcode)];
11546 if (is_indirect_opcode(handler)) {
11547 table = ind_table(handler);
11548 handler = table[opc2(ctx.opcode)];
11549 if (is_indirect_opcode(handler)) {
11550 table = ind_table(handler);
11551 handler = table[opc3(ctx.opcode)];
11552 }
11553 }
11554 /* Is opcode *REALLY* valid ? */
11555 if (unlikely(handler->handler == &gen_invalid)) {
11556 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
11557 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11558 opc1(ctx.opcode), opc2(ctx.opcode),
11559 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11560 } else {
11561 uint32_t inval;
11562
11563 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11564 inval = handler->inval2;
11565 } else {
11566 inval = handler->inval1;
11567 }
11568
11569 if (unlikely((ctx.opcode & inval) != 0)) {
11570 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
11571 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11572 ctx.opcode & inval, opc1(ctx.opcode),
11573 opc2(ctx.opcode), opc3(ctx.opcode),
11574 ctx.opcode, ctx.nip - 4);
11575 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11576 break;
11577 }
11578 }
11579 (*(handler->handler))(&ctx);
11580 #if defined(DO_PPC_STATISTICS)
11581 handler->count++;
11582 #endif
11583 /* Check trace mode exceptions */
11584 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11585 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11586 ctx.exception != POWERPC_SYSCALL &&
11587 ctx.exception != POWERPC_EXCP_TRAP &&
11588 ctx.exception != POWERPC_EXCP_BRANCH)) {
11589 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11590 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11591 (cs->singlestep_enabled) ||
11592 singlestep ||
11593 num_insns >= max_insns)) {
11594 /* if we reach a page boundary or are single stepping, stop
11595 * generation
11596 */
11597 break;
11598 }
11599 if (tcg_check_temp_count()) {
11600 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11601 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11602 ctx.opcode);
11603 exit(1);
11604 }
11605 }
11606 if (tb->cflags & CF_LAST_IO)
11607 gen_io_end();
11608 if (ctx.exception == POWERPC_EXCP_NONE) {
11609 gen_goto_tb(&ctx, 0, ctx.nip);
11610 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11611 if (unlikely(cs->singlestep_enabled)) {
11612 gen_debug_exception(ctxp);
11613 }
11614 /* Generate the return instruction */
11615 tcg_gen_exit_tb(0);
11616 }
11617 gen_tb_end(tb, num_insns);
11618
11619 tb->size = ctx.nip - pc_start;
11620 tb->icount = num_insns;
11621
11622 #if defined(DEBUG_DISAS)
11623 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11624 int flags;
11625 flags = env->bfd_mach;
11626 flags |= ctx.le_mode << 16;
11627 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11628 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
11629 qemu_log("\n");
11630 }
11631 #endif
11632 }
11633
11634 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
11635 target_ulong *data)
11636 {
11637 env->nip = data[0];
11638 }
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