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target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions
[mirror_qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 10*5 + 22*6 /* VSR */
55 + 8*5 /* CRF */];
56 static TCGv cpu_gpr[32];
57 #if !defined(TARGET_PPC64)
58 static TCGv cpu_gprh[32];
59 #endif
60 static TCGv_i64 cpu_fpr[32];
61 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
62 static TCGv_i64 cpu_vsr[32];
63 static TCGv_i32 cpu_crf[8];
64 static TCGv cpu_nip;
65 static TCGv cpu_msr;
66 static TCGv cpu_ctr;
67 static TCGv cpu_lr;
68 #if defined(TARGET_PPC64)
69 static TCGv cpu_cfar;
70 #endif
71 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
72 static TCGv cpu_reserve;
73 static TCGv cpu_fpscr;
74 static TCGv_i32 cpu_access_type;
75
76 #include "exec/gen-icount.h"
77
78 void ppc_translate_init(void)
79 {
80 int i;
81 char* p;
82 size_t cpu_reg_names_size;
83 static int done_init = 0;
84
85 if (done_init)
86 return;
87
88 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
89
90 p = cpu_reg_names;
91 cpu_reg_names_size = sizeof(cpu_reg_names);
92
93 for (i = 0; i < 8; i++) {
94 snprintf(p, cpu_reg_names_size, "crf%d", i);
95 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
96 offsetof(CPUPPCState, crf[i]), p);
97 p += 5;
98 cpu_reg_names_size -= 5;
99 }
100
101 for (i = 0; i < 32; i++) {
102 snprintf(p, cpu_reg_names_size, "r%d", i);
103 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
104 offsetof(CPUPPCState, gpr[i]), p);
105 p += (i < 10) ? 3 : 4;
106 cpu_reg_names_size -= (i < 10) ? 3 : 4;
107 #if !defined(TARGET_PPC64)
108 snprintf(p, cpu_reg_names_size, "r%dH", i);
109 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
110 offsetof(CPUPPCState, gprh[i]), p);
111 p += (i < 10) ? 4 : 5;
112 cpu_reg_names_size -= (i < 10) ? 4 : 5;
113 #endif
114
115 snprintf(p, cpu_reg_names_size, "fp%d", i);
116 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
117 offsetof(CPUPPCState, fpr[i]), p);
118 p += (i < 10) ? 4 : 5;
119 cpu_reg_names_size -= (i < 10) ? 4 : 5;
120
121 snprintf(p, cpu_reg_names_size, "avr%dH", i);
122 #ifdef HOST_WORDS_BIGENDIAN
123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
124 offsetof(CPUPPCState, avr[i].u64[0]), p);
125 #else
126 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
127 offsetof(CPUPPCState, avr[i].u64[1]), p);
128 #endif
129 p += (i < 10) ? 6 : 7;
130 cpu_reg_names_size -= (i < 10) ? 6 : 7;
131
132 snprintf(p, cpu_reg_names_size, "avr%dL", i);
133 #ifdef HOST_WORDS_BIGENDIAN
134 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
135 offsetof(CPUPPCState, avr[i].u64[1]), p);
136 #else
137 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
138 offsetof(CPUPPCState, avr[i].u64[0]), p);
139 #endif
140 p += (i < 10) ? 6 : 7;
141 cpu_reg_names_size -= (i < 10) ? 6 : 7;
142 snprintf(p, cpu_reg_names_size, "vsr%d", i);
143 cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
144 offsetof(CPUPPCState, vsr[i]), p);
145 p += (i < 10) ? 5 : 6;
146 cpu_reg_names_size -= (i < 10) ? 5 : 6;
147 }
148
149 cpu_nip = tcg_global_mem_new(TCG_AREG0,
150 offsetof(CPUPPCState, nip), "nip");
151
152 cpu_msr = tcg_global_mem_new(TCG_AREG0,
153 offsetof(CPUPPCState, msr), "msr");
154
155 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, ctr), "ctr");
157
158 cpu_lr = tcg_global_mem_new(TCG_AREG0,
159 offsetof(CPUPPCState, lr), "lr");
160
161 #if defined(TARGET_PPC64)
162 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
163 offsetof(CPUPPCState, cfar), "cfar");
164 #endif
165
166 cpu_xer = tcg_global_mem_new(TCG_AREG0,
167 offsetof(CPUPPCState, xer), "xer");
168 cpu_so = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, so), "SO");
170 cpu_ov = tcg_global_mem_new(TCG_AREG0,
171 offsetof(CPUPPCState, ov), "OV");
172 cpu_ca = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, ca), "CA");
174
175 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
176 offsetof(CPUPPCState, reserve_addr),
177 "reserve_addr");
178
179 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
180 offsetof(CPUPPCState, fpscr), "fpscr");
181
182 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
183 offsetof(CPUPPCState, access_type), "access_type");
184
185 done_init = 1;
186 }
187
188 /* internal defines */
189 typedef struct DisasContext {
190 struct TranslationBlock *tb;
191 target_ulong nip;
192 uint32_t opcode;
193 uint32_t exception;
194 /* Routine used to access memory */
195 int mem_idx;
196 int access_type;
197 /* Translation flags */
198 int le_mode;
199 #if defined(TARGET_PPC64)
200 int sf_mode;
201 int has_cfar;
202 #endif
203 int fpu_enabled;
204 int altivec_enabled;
205 int vsx_enabled;
206 int spe_enabled;
207 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
208 int singlestep_enabled;
209 uint64_t insns_flags;
210 uint64_t insns_flags2;
211 } DisasContext;
212
213 /* True when active word size < size of target_long. */
214 #ifdef TARGET_PPC64
215 # define NARROW_MODE(C) (!(C)->sf_mode)
216 #else
217 # define NARROW_MODE(C) 0
218 #endif
219
220 struct opc_handler_t {
221 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
222 uint32_t inval1;
223 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
224 uint32_t inval2;
225 /* instruction type */
226 uint64_t type;
227 /* extended instruction type */
228 uint64_t type2;
229 /* handler */
230 void (*handler)(DisasContext *ctx);
231 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
232 const char *oname;
233 #endif
234 #if defined(DO_PPC_STATISTICS)
235 uint64_t count;
236 #endif
237 };
238
239 static inline void gen_reset_fpstatus(void)
240 {
241 gen_helper_reset_fpstatus(cpu_env);
242 }
243
244 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
245 {
246 TCGv_i32 t0 = tcg_temp_new_i32();
247
248 if (set_fprf != 0) {
249 /* This case might be optimized later */
250 tcg_gen_movi_i32(t0, 1);
251 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
252 if (unlikely(set_rc)) {
253 tcg_gen_mov_i32(cpu_crf[1], t0);
254 }
255 gen_helper_float_check_status(cpu_env);
256 } else if (unlikely(set_rc)) {
257 /* We always need to compute fpcc */
258 tcg_gen_movi_i32(t0, 0);
259 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
260 tcg_gen_mov_i32(cpu_crf[1], t0);
261 }
262
263 tcg_temp_free_i32(t0);
264 }
265
266 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
267 {
268 if (ctx->access_type != access_type) {
269 tcg_gen_movi_i32(cpu_access_type, access_type);
270 ctx->access_type = access_type;
271 }
272 }
273
274 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
275 {
276 if (NARROW_MODE(ctx)) {
277 nip = (uint32_t)nip;
278 }
279 tcg_gen_movi_tl(cpu_nip, nip);
280 }
281
282 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
283 {
284 TCGv_i32 t0, t1;
285 if (ctx->exception == POWERPC_EXCP_NONE) {
286 gen_update_nip(ctx, ctx->nip);
287 }
288 t0 = tcg_const_i32(excp);
289 t1 = tcg_const_i32(error);
290 gen_helper_raise_exception_err(cpu_env, t0, t1);
291 tcg_temp_free_i32(t0);
292 tcg_temp_free_i32(t1);
293 ctx->exception = (excp);
294 }
295
296 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
297 {
298 TCGv_i32 t0;
299 if (ctx->exception == POWERPC_EXCP_NONE) {
300 gen_update_nip(ctx, ctx->nip);
301 }
302 t0 = tcg_const_i32(excp);
303 gen_helper_raise_exception(cpu_env, t0);
304 tcg_temp_free_i32(t0);
305 ctx->exception = (excp);
306 }
307
308 static inline void gen_debug_exception(DisasContext *ctx)
309 {
310 TCGv_i32 t0;
311
312 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
313 (ctx->exception != POWERPC_EXCP_SYNC)) {
314 gen_update_nip(ctx, ctx->nip);
315 }
316 t0 = tcg_const_i32(EXCP_DEBUG);
317 gen_helper_raise_exception(cpu_env, t0);
318 tcg_temp_free_i32(t0);
319 }
320
321 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
322 {
323 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
324 }
325
326 /* Stop translation */
327 static inline void gen_stop_exception(DisasContext *ctx)
328 {
329 gen_update_nip(ctx, ctx->nip);
330 ctx->exception = POWERPC_EXCP_STOP;
331 }
332
333 /* No need to update nip here, as execution flow will change */
334 static inline void gen_sync_exception(DisasContext *ctx)
335 {
336 ctx->exception = POWERPC_EXCP_SYNC;
337 }
338
339 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
340 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
341
342 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
343 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
344
345 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
346 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
347
348 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
349 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
350
351 typedef struct opcode_t {
352 unsigned char opc1, opc2, opc3;
353 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
354 unsigned char pad[5];
355 #else
356 unsigned char pad[1];
357 #endif
358 opc_handler_t handler;
359 const char *oname;
360 } opcode_t;
361
362 /*****************************************************************************/
363 /*** Instruction decoding ***/
364 #define EXTRACT_HELPER(name, shift, nb) \
365 static inline uint32_t name(uint32_t opcode) \
366 { \
367 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
368 }
369
370 #define EXTRACT_SHELPER(name, shift, nb) \
371 static inline int32_t name(uint32_t opcode) \
372 { \
373 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
374 }
375
376 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
377 static inline uint32_t name(uint32_t opcode) \
378 { \
379 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
380 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
381 }
382 /* Opcode part 1 */
383 EXTRACT_HELPER(opc1, 26, 6);
384 /* Opcode part 2 */
385 EXTRACT_HELPER(opc2, 1, 5);
386 /* Opcode part 3 */
387 EXTRACT_HELPER(opc3, 6, 5);
388 /* Update Cr0 flags */
389 EXTRACT_HELPER(Rc, 0, 1);
390 /* Destination */
391 EXTRACT_HELPER(rD, 21, 5);
392 /* Source */
393 EXTRACT_HELPER(rS, 21, 5);
394 /* First operand */
395 EXTRACT_HELPER(rA, 16, 5);
396 /* Second operand */
397 EXTRACT_HELPER(rB, 11, 5);
398 /* Third operand */
399 EXTRACT_HELPER(rC, 6, 5);
400 /*** Get CRn ***/
401 EXTRACT_HELPER(crfD, 23, 3);
402 EXTRACT_HELPER(crfS, 18, 3);
403 EXTRACT_HELPER(crbD, 21, 5);
404 EXTRACT_HELPER(crbA, 16, 5);
405 EXTRACT_HELPER(crbB, 11, 5);
406 /* SPR / TBL */
407 EXTRACT_HELPER(_SPR, 11, 10);
408 static inline uint32_t SPR(uint32_t opcode)
409 {
410 uint32_t sprn = _SPR(opcode);
411
412 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
413 }
414 /*** Get constants ***/
415 EXTRACT_HELPER(IMM, 12, 8);
416 /* 16 bits signed immediate value */
417 EXTRACT_SHELPER(SIMM, 0, 16);
418 /* 16 bits unsigned immediate value */
419 EXTRACT_HELPER(UIMM, 0, 16);
420 /* 5 bits signed immediate value */
421 EXTRACT_HELPER(SIMM5, 16, 5);
422 /* 5 bits signed immediate value */
423 EXTRACT_HELPER(UIMM5, 16, 5);
424 /* Bit count */
425 EXTRACT_HELPER(NB, 11, 5);
426 /* Shift count */
427 EXTRACT_HELPER(SH, 11, 5);
428 /* Vector shift count */
429 EXTRACT_HELPER(VSH, 6, 4);
430 /* Mask start */
431 EXTRACT_HELPER(MB, 6, 5);
432 /* Mask end */
433 EXTRACT_HELPER(ME, 1, 5);
434 /* Trap operand */
435 EXTRACT_HELPER(TO, 21, 5);
436
437 EXTRACT_HELPER(CRM, 12, 8);
438 EXTRACT_HELPER(SR, 16, 4);
439
440 /* mtfsf/mtfsfi */
441 EXTRACT_HELPER(FPBF, 23, 3);
442 EXTRACT_HELPER(FPIMM, 12, 4);
443 EXTRACT_HELPER(FPL, 25, 1);
444 EXTRACT_HELPER(FPFLM, 17, 8);
445 EXTRACT_HELPER(FPW, 16, 1);
446
447 /*** Jump target decoding ***/
448 /* Displacement */
449 EXTRACT_SHELPER(d, 0, 16);
450 /* Immediate address */
451 static inline target_ulong LI(uint32_t opcode)
452 {
453 return (opcode >> 0) & 0x03FFFFFC;
454 }
455
456 static inline uint32_t BD(uint32_t opcode)
457 {
458 return (opcode >> 0) & 0xFFFC;
459 }
460
461 EXTRACT_HELPER(BO, 21, 5);
462 EXTRACT_HELPER(BI, 16, 5);
463 /* Absolute/relative address */
464 EXTRACT_HELPER(AA, 1, 1);
465 /* Link */
466 EXTRACT_HELPER(LK, 0, 1);
467
468 /* Create a mask between <start> and <end> bits */
469 static inline target_ulong MASK(uint32_t start, uint32_t end)
470 {
471 target_ulong ret;
472
473 #if defined(TARGET_PPC64)
474 if (likely(start == 0)) {
475 ret = UINT64_MAX << (63 - end);
476 } else if (likely(end == 63)) {
477 ret = UINT64_MAX >> start;
478 }
479 #else
480 if (likely(start == 0)) {
481 ret = UINT32_MAX << (31 - end);
482 } else if (likely(end == 31)) {
483 ret = UINT32_MAX >> start;
484 }
485 #endif
486 else {
487 ret = (((target_ulong)(-1ULL)) >> (start)) ^
488 (((target_ulong)(-1ULL) >> (end)) >> 1);
489 if (unlikely(start > end))
490 return ~ret;
491 }
492
493 return ret;
494 }
495
496 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
497 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
498 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
499 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
500 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
501 EXTRACT_HELPER(DM, 8, 2);
502 EXTRACT_HELPER(UIM, 16, 2);
503 EXTRACT_HELPER(SHW, 8, 2);
504 /*****************************************************************************/
505 /* PowerPC instructions table */
506
507 #if defined(DO_PPC_STATISTICS)
508 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
509 { \
510 .opc1 = op1, \
511 .opc2 = op2, \
512 .opc3 = op3, \
513 .pad = { 0, }, \
514 .handler = { \
515 .inval1 = invl, \
516 .type = _typ, \
517 .type2 = _typ2, \
518 .handler = &gen_##name, \
519 .oname = stringify(name), \
520 }, \
521 .oname = stringify(name), \
522 }
523 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
524 { \
525 .opc1 = op1, \
526 .opc2 = op2, \
527 .opc3 = op3, \
528 .pad = { 0, }, \
529 .handler = { \
530 .inval1 = invl1, \
531 .inval2 = invl2, \
532 .type = _typ, \
533 .type2 = _typ2, \
534 .handler = &gen_##name, \
535 .oname = stringify(name), \
536 }, \
537 .oname = stringify(name), \
538 }
539 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
540 { \
541 .opc1 = op1, \
542 .opc2 = op2, \
543 .opc3 = op3, \
544 .pad = { 0, }, \
545 .handler = { \
546 .inval1 = invl, \
547 .type = _typ, \
548 .type2 = _typ2, \
549 .handler = &gen_##name, \
550 .oname = onam, \
551 }, \
552 .oname = onam, \
553 }
554 #else
555 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
556 { \
557 .opc1 = op1, \
558 .opc2 = op2, \
559 .opc3 = op3, \
560 .pad = { 0, }, \
561 .handler = { \
562 .inval1 = invl, \
563 .type = _typ, \
564 .type2 = _typ2, \
565 .handler = &gen_##name, \
566 }, \
567 .oname = stringify(name), \
568 }
569 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
570 { \
571 .opc1 = op1, \
572 .opc2 = op2, \
573 .opc3 = op3, \
574 .pad = { 0, }, \
575 .handler = { \
576 .inval1 = invl1, \
577 .inval2 = invl2, \
578 .type = _typ, \
579 .type2 = _typ2, \
580 .handler = &gen_##name, \
581 }, \
582 .oname = stringify(name), \
583 }
584 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
585 { \
586 .opc1 = op1, \
587 .opc2 = op2, \
588 .opc3 = op3, \
589 .pad = { 0, }, \
590 .handler = { \
591 .inval1 = invl, \
592 .type = _typ, \
593 .type2 = _typ2, \
594 .handler = &gen_##name, \
595 }, \
596 .oname = onam, \
597 }
598 #endif
599
600 /* SPR load/store helpers */
601 static inline void gen_load_spr(TCGv t, int reg)
602 {
603 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
604 }
605
606 static inline void gen_store_spr(int reg, TCGv t)
607 {
608 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
609 }
610
611 /* Invalid instruction */
612 static void gen_invalid(DisasContext *ctx)
613 {
614 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
615 }
616
617 static opc_handler_t invalid_handler = {
618 .inval1 = 0xFFFFFFFF,
619 .inval2 = 0xFFFFFFFF,
620 .type = PPC_NONE,
621 .type2 = PPC_NONE,
622 .handler = gen_invalid,
623 };
624
625 /*** Integer comparison ***/
626
627 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
628 {
629 TCGv t0 = tcg_temp_new();
630 TCGv_i32 t1 = tcg_temp_new_i32();
631
632 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
633
634 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
635 tcg_gen_trunc_tl_i32(t1, t0);
636 tcg_gen_shli_i32(t1, t1, CRF_LT);
637 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
638
639 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
640 tcg_gen_trunc_tl_i32(t1, t0);
641 tcg_gen_shli_i32(t1, t1, CRF_GT);
642 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
643
644 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
645 tcg_gen_trunc_tl_i32(t1, t0);
646 tcg_gen_shli_i32(t1, t1, CRF_EQ);
647 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
648
649 tcg_temp_free(t0);
650 tcg_temp_free_i32(t1);
651 }
652
653 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
654 {
655 TCGv t0 = tcg_const_tl(arg1);
656 gen_op_cmp(arg0, t0, s, crf);
657 tcg_temp_free(t0);
658 }
659
660 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
661 {
662 TCGv t0, t1;
663 t0 = tcg_temp_new();
664 t1 = tcg_temp_new();
665 if (s) {
666 tcg_gen_ext32s_tl(t0, arg0);
667 tcg_gen_ext32s_tl(t1, arg1);
668 } else {
669 tcg_gen_ext32u_tl(t0, arg0);
670 tcg_gen_ext32u_tl(t1, arg1);
671 }
672 gen_op_cmp(t0, t1, s, crf);
673 tcg_temp_free(t1);
674 tcg_temp_free(t0);
675 }
676
677 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
678 {
679 TCGv t0 = tcg_const_tl(arg1);
680 gen_op_cmp32(arg0, t0, s, crf);
681 tcg_temp_free(t0);
682 }
683
684 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
685 {
686 if (NARROW_MODE(ctx)) {
687 gen_op_cmpi32(reg, 0, 1, 0);
688 } else {
689 gen_op_cmpi(reg, 0, 1, 0);
690 }
691 }
692
693 /* cmp */
694 static void gen_cmp(DisasContext *ctx)
695 {
696 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
697 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
698 1, crfD(ctx->opcode));
699 } else {
700 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
701 1, crfD(ctx->opcode));
702 }
703 }
704
705 /* cmpi */
706 static void gen_cmpi(DisasContext *ctx)
707 {
708 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
709 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
710 1, crfD(ctx->opcode));
711 } else {
712 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
713 1, crfD(ctx->opcode));
714 }
715 }
716
717 /* cmpl */
718 static void gen_cmpl(DisasContext *ctx)
719 {
720 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
721 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
722 0, crfD(ctx->opcode));
723 } else {
724 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
725 0, crfD(ctx->opcode));
726 }
727 }
728
729 /* cmpli */
730 static void gen_cmpli(DisasContext *ctx)
731 {
732 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
733 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
734 0, crfD(ctx->opcode));
735 } else {
736 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
737 0, crfD(ctx->opcode));
738 }
739 }
740
741 /* isel (PowerPC 2.03 specification) */
742 static void gen_isel(DisasContext *ctx)
743 {
744 int l1, l2;
745 uint32_t bi = rC(ctx->opcode);
746 uint32_t mask;
747 TCGv_i32 t0;
748
749 l1 = gen_new_label();
750 l2 = gen_new_label();
751
752 mask = 1 << (3 - (bi & 0x03));
753 t0 = tcg_temp_new_i32();
754 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
755 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
756 if (rA(ctx->opcode) == 0)
757 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
758 else
759 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
760 tcg_gen_br(l2);
761 gen_set_label(l1);
762 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
763 gen_set_label(l2);
764 tcg_temp_free_i32(t0);
765 }
766
767 /* cmpb: PowerPC 2.05 specification */
768 static void gen_cmpb(DisasContext *ctx)
769 {
770 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
771 cpu_gpr[rB(ctx->opcode)]);
772 }
773
774 /*** Integer arithmetic ***/
775
776 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
777 TCGv arg1, TCGv arg2, int sub)
778 {
779 TCGv t0 = tcg_temp_new();
780
781 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
782 tcg_gen_xor_tl(t0, arg1, arg2);
783 if (sub) {
784 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
785 } else {
786 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
787 }
788 tcg_temp_free(t0);
789 if (NARROW_MODE(ctx)) {
790 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
791 }
792 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
793 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
794 }
795
796 /* Common add function */
797 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
798 TCGv arg2, bool add_ca, bool compute_ca,
799 bool compute_ov, bool compute_rc0)
800 {
801 TCGv t0 = ret;
802
803 if (compute_ca || compute_ov) {
804 t0 = tcg_temp_new();
805 }
806
807 if (compute_ca) {
808 if (NARROW_MODE(ctx)) {
809 /* Caution: a non-obvious corner case of the spec is that we
810 must produce the *entire* 64-bit addition, but produce the
811 carry into bit 32. */
812 TCGv t1 = tcg_temp_new();
813 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
814 tcg_gen_add_tl(t0, arg1, arg2);
815 if (add_ca) {
816 tcg_gen_add_tl(t0, t0, cpu_ca);
817 }
818 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
819 tcg_temp_free(t1);
820 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
821 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
822 } else {
823 TCGv zero = tcg_const_tl(0);
824 if (add_ca) {
825 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
826 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
827 } else {
828 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
829 }
830 tcg_temp_free(zero);
831 }
832 } else {
833 tcg_gen_add_tl(t0, arg1, arg2);
834 if (add_ca) {
835 tcg_gen_add_tl(t0, t0, cpu_ca);
836 }
837 }
838
839 if (compute_ov) {
840 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
841 }
842 if (unlikely(compute_rc0)) {
843 gen_set_Rc0(ctx, t0);
844 }
845
846 if (!TCGV_EQUAL(t0, ret)) {
847 tcg_gen_mov_tl(ret, t0);
848 tcg_temp_free(t0);
849 }
850 }
851 /* Add functions with two operands */
852 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
853 static void glue(gen_, name)(DisasContext *ctx) \
854 { \
855 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
856 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
857 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
858 }
859 /* Add functions with one operand and one immediate */
860 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
861 add_ca, compute_ca, compute_ov) \
862 static void glue(gen_, name)(DisasContext *ctx) \
863 { \
864 TCGv t0 = tcg_const_tl(const_val); \
865 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
866 cpu_gpr[rA(ctx->opcode)], t0, \
867 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
868 tcg_temp_free(t0); \
869 }
870
871 /* add add. addo addo. */
872 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
873 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
874 /* addc addc. addco addco. */
875 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
876 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
877 /* adde adde. addeo addeo. */
878 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
879 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
880 /* addme addme. addmeo addmeo. */
881 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
882 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
883 /* addze addze. addzeo addzeo.*/
884 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
885 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
886 /* addi */
887 static void gen_addi(DisasContext *ctx)
888 {
889 target_long simm = SIMM(ctx->opcode);
890
891 if (rA(ctx->opcode) == 0) {
892 /* li case */
893 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
894 } else {
895 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
896 cpu_gpr[rA(ctx->opcode)], simm);
897 }
898 }
899 /* addic addic.*/
900 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
901 {
902 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
903 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
904 c, 0, 1, 0, compute_rc0);
905 tcg_temp_free(c);
906 }
907
908 static void gen_addic(DisasContext *ctx)
909 {
910 gen_op_addic(ctx, 0);
911 }
912
913 static void gen_addic_(DisasContext *ctx)
914 {
915 gen_op_addic(ctx, 1);
916 }
917
918 /* addis */
919 static void gen_addis(DisasContext *ctx)
920 {
921 target_long simm = SIMM(ctx->opcode);
922
923 if (rA(ctx->opcode) == 0) {
924 /* lis case */
925 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
926 } else {
927 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
928 cpu_gpr[rA(ctx->opcode)], simm << 16);
929 }
930 }
931
932 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
933 TCGv arg2, int sign, int compute_ov)
934 {
935 int l1 = gen_new_label();
936 int l2 = gen_new_label();
937 TCGv_i32 t0 = tcg_temp_local_new_i32();
938 TCGv_i32 t1 = tcg_temp_local_new_i32();
939
940 tcg_gen_trunc_tl_i32(t0, arg1);
941 tcg_gen_trunc_tl_i32(t1, arg2);
942 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
943 if (sign) {
944 int l3 = gen_new_label();
945 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
946 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
947 gen_set_label(l3);
948 tcg_gen_div_i32(t0, t0, t1);
949 } else {
950 tcg_gen_divu_i32(t0, t0, t1);
951 }
952 if (compute_ov) {
953 tcg_gen_movi_tl(cpu_ov, 0);
954 }
955 tcg_gen_br(l2);
956 gen_set_label(l1);
957 if (sign) {
958 tcg_gen_sari_i32(t0, t0, 31);
959 } else {
960 tcg_gen_movi_i32(t0, 0);
961 }
962 if (compute_ov) {
963 tcg_gen_movi_tl(cpu_ov, 1);
964 tcg_gen_movi_tl(cpu_so, 1);
965 }
966 gen_set_label(l2);
967 tcg_gen_extu_i32_tl(ret, t0);
968 tcg_temp_free_i32(t0);
969 tcg_temp_free_i32(t1);
970 if (unlikely(Rc(ctx->opcode) != 0))
971 gen_set_Rc0(ctx, ret);
972 }
973 /* Div functions */
974 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
975 static void glue(gen_, name)(DisasContext *ctx) \
976 { \
977 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
978 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
979 sign, compute_ov); \
980 }
981 /* divwu divwu. divwuo divwuo. */
982 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
983 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
984 /* divw divw. divwo divwo. */
985 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
986 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
987
988 /* div[wd]eu[o][.] */
989 #define GEN_DIVE(name, hlpr, compute_ov) \
990 static void gen_##name(DisasContext *ctx) \
991 { \
992 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
993 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
994 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
995 tcg_temp_free_i32(t0); \
996 if (unlikely(Rc(ctx->opcode) != 0)) { \
997 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
998 } \
999 }
1000
1001 GEN_DIVE(divweu, divweu, 0);
1002 GEN_DIVE(divweuo, divweu, 1);
1003 GEN_DIVE(divwe, divwe, 0);
1004 GEN_DIVE(divweo, divwe, 1);
1005
1006 #if defined(TARGET_PPC64)
1007 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1008 TCGv arg2, int sign, int compute_ov)
1009 {
1010 int l1 = gen_new_label();
1011 int l2 = gen_new_label();
1012
1013 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1014 if (sign) {
1015 int l3 = gen_new_label();
1016 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1017 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1018 gen_set_label(l3);
1019 tcg_gen_div_i64(ret, arg1, arg2);
1020 } else {
1021 tcg_gen_divu_i64(ret, arg1, arg2);
1022 }
1023 if (compute_ov) {
1024 tcg_gen_movi_tl(cpu_ov, 0);
1025 }
1026 tcg_gen_br(l2);
1027 gen_set_label(l1);
1028 if (sign) {
1029 tcg_gen_sari_i64(ret, arg1, 63);
1030 } else {
1031 tcg_gen_movi_i64(ret, 0);
1032 }
1033 if (compute_ov) {
1034 tcg_gen_movi_tl(cpu_ov, 1);
1035 tcg_gen_movi_tl(cpu_so, 1);
1036 }
1037 gen_set_label(l2);
1038 if (unlikely(Rc(ctx->opcode) != 0))
1039 gen_set_Rc0(ctx, ret);
1040 }
1041 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1042 static void glue(gen_, name)(DisasContext *ctx) \
1043 { \
1044 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1045 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1046 sign, compute_ov); \
1047 }
1048 /* divwu divwu. divwuo divwuo. */
1049 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1050 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1051 /* divw divw. divwo divwo. */
1052 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1053 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1054
1055 GEN_DIVE(divdeu, divdeu, 0);
1056 GEN_DIVE(divdeuo, divdeu, 1);
1057 GEN_DIVE(divde, divde, 0);
1058 GEN_DIVE(divdeo, divde, 1);
1059 #endif
1060
1061 /* mulhw mulhw. */
1062 static void gen_mulhw(DisasContext *ctx)
1063 {
1064 TCGv_i32 t0 = tcg_temp_new_i32();
1065 TCGv_i32 t1 = tcg_temp_new_i32();
1066
1067 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1068 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1069 tcg_gen_muls2_i32(t0, t1, t0, t1);
1070 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1071 tcg_temp_free_i32(t0);
1072 tcg_temp_free_i32(t1);
1073 if (unlikely(Rc(ctx->opcode) != 0))
1074 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1075 }
1076
1077 /* mulhwu mulhwu. */
1078 static void gen_mulhwu(DisasContext *ctx)
1079 {
1080 TCGv_i32 t0 = tcg_temp_new_i32();
1081 TCGv_i32 t1 = tcg_temp_new_i32();
1082
1083 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1084 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1085 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1086 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1087 tcg_temp_free_i32(t0);
1088 tcg_temp_free_i32(t1);
1089 if (unlikely(Rc(ctx->opcode) != 0))
1090 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1091 }
1092
1093 /* mullw mullw. */
1094 static void gen_mullw(DisasContext *ctx)
1095 {
1096 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1097 cpu_gpr[rB(ctx->opcode)]);
1098 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1099 if (unlikely(Rc(ctx->opcode) != 0))
1100 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1101 }
1102
1103 /* mullwo mullwo. */
1104 static void gen_mullwo(DisasContext *ctx)
1105 {
1106 TCGv_i32 t0 = tcg_temp_new_i32();
1107 TCGv_i32 t1 = tcg_temp_new_i32();
1108
1109 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1110 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1111 tcg_gen_muls2_i32(t0, t1, t0, t1);
1112 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1113
1114 tcg_gen_sari_i32(t0, t0, 31);
1115 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1116 tcg_gen_extu_i32_tl(cpu_ov, t0);
1117 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1118
1119 tcg_temp_free_i32(t0);
1120 tcg_temp_free_i32(t1);
1121 if (unlikely(Rc(ctx->opcode) != 0))
1122 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1123 }
1124
1125 /* mulli */
1126 static void gen_mulli(DisasContext *ctx)
1127 {
1128 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1129 SIMM(ctx->opcode));
1130 }
1131
1132 #if defined(TARGET_PPC64)
1133 /* mulhd mulhd. */
1134 static void gen_mulhd(DisasContext *ctx)
1135 {
1136 TCGv lo = tcg_temp_new();
1137 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1138 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1139 tcg_temp_free(lo);
1140 if (unlikely(Rc(ctx->opcode) != 0)) {
1141 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1142 }
1143 }
1144
1145 /* mulhdu mulhdu. */
1146 static void gen_mulhdu(DisasContext *ctx)
1147 {
1148 TCGv lo = tcg_temp_new();
1149 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1150 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1151 tcg_temp_free(lo);
1152 if (unlikely(Rc(ctx->opcode) != 0)) {
1153 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1154 }
1155 }
1156
1157 /* mulld mulld. */
1158 static void gen_mulld(DisasContext *ctx)
1159 {
1160 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1161 cpu_gpr[rB(ctx->opcode)]);
1162 if (unlikely(Rc(ctx->opcode) != 0))
1163 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1164 }
1165
1166 /* mulldo mulldo. */
1167 static void gen_mulldo(DisasContext *ctx)
1168 {
1169 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1170 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1171 if (unlikely(Rc(ctx->opcode) != 0)) {
1172 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1173 }
1174 }
1175 #endif
1176
1177 /* Common subf function */
1178 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1179 TCGv arg2, bool add_ca, bool compute_ca,
1180 bool compute_ov, bool compute_rc0)
1181 {
1182 TCGv t0 = ret;
1183
1184 if (compute_ca || compute_ov) {
1185 t0 = tcg_temp_new();
1186 }
1187
1188 if (compute_ca) {
1189 /* dest = ~arg1 + arg2 [+ ca]. */
1190 if (NARROW_MODE(ctx)) {
1191 /* Caution: a non-obvious corner case of the spec is that we
1192 must produce the *entire* 64-bit addition, but produce the
1193 carry into bit 32. */
1194 TCGv inv1 = tcg_temp_new();
1195 TCGv t1 = tcg_temp_new();
1196 tcg_gen_not_tl(inv1, arg1);
1197 if (add_ca) {
1198 tcg_gen_add_tl(t0, arg2, cpu_ca);
1199 } else {
1200 tcg_gen_addi_tl(t0, arg2, 1);
1201 }
1202 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1203 tcg_gen_add_tl(t0, t0, inv1);
1204 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1205 tcg_temp_free(t1);
1206 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1207 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1208 } else if (add_ca) {
1209 TCGv zero, inv1 = tcg_temp_new();
1210 tcg_gen_not_tl(inv1, arg1);
1211 zero = tcg_const_tl(0);
1212 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1213 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1214 tcg_temp_free(zero);
1215 tcg_temp_free(inv1);
1216 } else {
1217 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1218 tcg_gen_sub_tl(t0, arg2, arg1);
1219 }
1220 } else if (add_ca) {
1221 /* Since we're ignoring carry-out, we can simplify the
1222 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1223 tcg_gen_sub_tl(t0, arg2, arg1);
1224 tcg_gen_add_tl(t0, t0, cpu_ca);
1225 tcg_gen_subi_tl(t0, t0, 1);
1226 } else {
1227 tcg_gen_sub_tl(t0, arg2, arg1);
1228 }
1229
1230 if (compute_ov) {
1231 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1232 }
1233 if (unlikely(compute_rc0)) {
1234 gen_set_Rc0(ctx, t0);
1235 }
1236
1237 if (!TCGV_EQUAL(t0, ret)) {
1238 tcg_gen_mov_tl(ret, t0);
1239 tcg_temp_free(t0);
1240 }
1241 }
1242 /* Sub functions with Two operands functions */
1243 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1244 static void glue(gen_, name)(DisasContext *ctx) \
1245 { \
1246 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1247 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1248 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1249 }
1250 /* Sub functions with one operand and one immediate */
1251 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1252 add_ca, compute_ca, compute_ov) \
1253 static void glue(gen_, name)(DisasContext *ctx) \
1254 { \
1255 TCGv t0 = tcg_const_tl(const_val); \
1256 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1257 cpu_gpr[rA(ctx->opcode)], t0, \
1258 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1259 tcg_temp_free(t0); \
1260 }
1261 /* subf subf. subfo subfo. */
1262 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1263 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1264 /* subfc subfc. subfco subfco. */
1265 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1266 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1267 /* subfe subfe. subfeo subfo. */
1268 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1269 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1270 /* subfme subfme. subfmeo subfmeo. */
1271 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1272 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1273 /* subfze subfze. subfzeo subfzeo.*/
1274 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1275 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1276
1277 /* subfic */
1278 static void gen_subfic(DisasContext *ctx)
1279 {
1280 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1281 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1282 c, 0, 1, 0, 0);
1283 tcg_temp_free(c);
1284 }
1285
1286 /* neg neg. nego nego. */
1287 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1288 {
1289 TCGv zero = tcg_const_tl(0);
1290 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1291 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1292 tcg_temp_free(zero);
1293 }
1294
1295 static void gen_neg(DisasContext *ctx)
1296 {
1297 gen_op_arith_neg(ctx, 0);
1298 }
1299
1300 static void gen_nego(DisasContext *ctx)
1301 {
1302 gen_op_arith_neg(ctx, 1);
1303 }
1304
1305 /*** Integer logical ***/
1306 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1307 static void glue(gen_, name)(DisasContext *ctx) \
1308 { \
1309 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1310 cpu_gpr[rB(ctx->opcode)]); \
1311 if (unlikely(Rc(ctx->opcode) != 0)) \
1312 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1313 }
1314
1315 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1316 static void glue(gen_, name)(DisasContext *ctx) \
1317 { \
1318 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1319 if (unlikely(Rc(ctx->opcode) != 0)) \
1320 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1321 }
1322
1323 /* and & and. */
1324 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1325 /* andc & andc. */
1326 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1327
1328 /* andi. */
1329 static void gen_andi_(DisasContext *ctx)
1330 {
1331 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1332 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1333 }
1334
1335 /* andis. */
1336 static void gen_andis_(DisasContext *ctx)
1337 {
1338 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1339 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1340 }
1341
1342 /* cntlzw */
1343 static void gen_cntlzw(DisasContext *ctx)
1344 {
1345 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1346 if (unlikely(Rc(ctx->opcode) != 0))
1347 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1348 }
1349 /* eqv & eqv. */
1350 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1351 /* extsb & extsb. */
1352 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1353 /* extsh & extsh. */
1354 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1355 /* nand & nand. */
1356 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1357 /* nor & nor. */
1358 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1359
1360 /* or & or. */
1361 static void gen_or(DisasContext *ctx)
1362 {
1363 int rs, ra, rb;
1364
1365 rs = rS(ctx->opcode);
1366 ra = rA(ctx->opcode);
1367 rb = rB(ctx->opcode);
1368 /* Optimisation for mr. ri case */
1369 if (rs != ra || rs != rb) {
1370 if (rs != rb)
1371 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1372 else
1373 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1374 if (unlikely(Rc(ctx->opcode) != 0))
1375 gen_set_Rc0(ctx, cpu_gpr[ra]);
1376 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1377 gen_set_Rc0(ctx, cpu_gpr[rs]);
1378 #if defined(TARGET_PPC64)
1379 } else {
1380 int prio = 0;
1381
1382 switch (rs) {
1383 case 1:
1384 /* Set process priority to low */
1385 prio = 2;
1386 break;
1387 case 6:
1388 /* Set process priority to medium-low */
1389 prio = 3;
1390 break;
1391 case 2:
1392 /* Set process priority to normal */
1393 prio = 4;
1394 break;
1395 #if !defined(CONFIG_USER_ONLY)
1396 case 31:
1397 if (ctx->mem_idx > 0) {
1398 /* Set process priority to very low */
1399 prio = 1;
1400 }
1401 break;
1402 case 5:
1403 if (ctx->mem_idx > 0) {
1404 /* Set process priority to medium-hight */
1405 prio = 5;
1406 }
1407 break;
1408 case 3:
1409 if (ctx->mem_idx > 0) {
1410 /* Set process priority to high */
1411 prio = 6;
1412 }
1413 break;
1414 case 7:
1415 if (ctx->mem_idx > 1) {
1416 /* Set process priority to very high */
1417 prio = 7;
1418 }
1419 break;
1420 #endif
1421 default:
1422 /* nop */
1423 break;
1424 }
1425 if (prio) {
1426 TCGv t0 = tcg_temp_new();
1427 gen_load_spr(t0, SPR_PPR);
1428 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1429 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1430 gen_store_spr(SPR_PPR, t0);
1431 tcg_temp_free(t0);
1432 }
1433 #endif
1434 }
1435 }
1436 /* orc & orc. */
1437 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1438
1439 /* xor & xor. */
1440 static void gen_xor(DisasContext *ctx)
1441 {
1442 /* Optimisation for "set to zero" case */
1443 if (rS(ctx->opcode) != rB(ctx->opcode))
1444 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1445 else
1446 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1447 if (unlikely(Rc(ctx->opcode) != 0))
1448 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1449 }
1450
1451 /* ori */
1452 static void gen_ori(DisasContext *ctx)
1453 {
1454 target_ulong uimm = UIMM(ctx->opcode);
1455
1456 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1457 /* NOP */
1458 /* XXX: should handle special NOPs for POWER series */
1459 return;
1460 }
1461 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1462 }
1463
1464 /* oris */
1465 static void gen_oris(DisasContext *ctx)
1466 {
1467 target_ulong uimm = UIMM(ctx->opcode);
1468
1469 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1470 /* NOP */
1471 return;
1472 }
1473 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1474 }
1475
1476 /* xori */
1477 static void gen_xori(DisasContext *ctx)
1478 {
1479 target_ulong uimm = UIMM(ctx->opcode);
1480
1481 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1482 /* NOP */
1483 return;
1484 }
1485 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1486 }
1487
1488 /* xoris */
1489 static void gen_xoris(DisasContext *ctx)
1490 {
1491 target_ulong uimm = UIMM(ctx->opcode);
1492
1493 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1494 /* NOP */
1495 return;
1496 }
1497 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1498 }
1499
1500 /* popcntb : PowerPC 2.03 specification */
1501 static void gen_popcntb(DisasContext *ctx)
1502 {
1503 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1504 }
1505
1506 static void gen_popcntw(DisasContext *ctx)
1507 {
1508 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1509 }
1510
1511 #if defined(TARGET_PPC64)
1512 /* popcntd: PowerPC 2.06 specification */
1513 static void gen_popcntd(DisasContext *ctx)
1514 {
1515 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1516 }
1517 #endif
1518
1519 /* prtyw: PowerPC 2.05 specification */
1520 static void gen_prtyw(DisasContext *ctx)
1521 {
1522 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1523 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1524 TCGv t0 = tcg_temp_new();
1525 tcg_gen_shri_tl(t0, rs, 16);
1526 tcg_gen_xor_tl(ra, rs, t0);
1527 tcg_gen_shri_tl(t0, ra, 8);
1528 tcg_gen_xor_tl(ra, ra, t0);
1529 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1530 tcg_temp_free(t0);
1531 }
1532
1533 #if defined(TARGET_PPC64)
1534 /* prtyd: PowerPC 2.05 specification */
1535 static void gen_prtyd(DisasContext *ctx)
1536 {
1537 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1538 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1539 TCGv t0 = tcg_temp_new();
1540 tcg_gen_shri_tl(t0, rs, 32);
1541 tcg_gen_xor_tl(ra, rs, t0);
1542 tcg_gen_shri_tl(t0, ra, 16);
1543 tcg_gen_xor_tl(ra, ra, t0);
1544 tcg_gen_shri_tl(t0, ra, 8);
1545 tcg_gen_xor_tl(ra, ra, t0);
1546 tcg_gen_andi_tl(ra, ra, 1);
1547 tcg_temp_free(t0);
1548 }
1549 #endif
1550
1551 #if defined(TARGET_PPC64)
1552 /* bpermd */
1553 static void gen_bpermd(DisasContext *ctx)
1554 {
1555 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1556 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1557 }
1558 #endif
1559
1560 #if defined(TARGET_PPC64)
1561 /* extsw & extsw. */
1562 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1563
1564 /* cntlzd */
1565 static void gen_cntlzd(DisasContext *ctx)
1566 {
1567 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1568 if (unlikely(Rc(ctx->opcode) != 0))
1569 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1570 }
1571 #endif
1572
1573 /*** Integer rotate ***/
1574
1575 /* rlwimi & rlwimi. */
1576 static void gen_rlwimi(DisasContext *ctx)
1577 {
1578 uint32_t mb, me, sh;
1579
1580 mb = MB(ctx->opcode);
1581 me = ME(ctx->opcode);
1582 sh = SH(ctx->opcode);
1583 if (likely(sh == 0 && mb == 0 && me == 31)) {
1584 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1585 } else {
1586 target_ulong mask;
1587 TCGv t1;
1588 TCGv t0 = tcg_temp_new();
1589 #if defined(TARGET_PPC64)
1590 TCGv_i32 t2 = tcg_temp_new_i32();
1591 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1592 tcg_gen_rotli_i32(t2, t2, sh);
1593 tcg_gen_extu_i32_i64(t0, t2);
1594 tcg_temp_free_i32(t2);
1595 #else
1596 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1597 #endif
1598 #if defined(TARGET_PPC64)
1599 mb += 32;
1600 me += 32;
1601 #endif
1602 mask = MASK(mb, me);
1603 t1 = tcg_temp_new();
1604 tcg_gen_andi_tl(t0, t0, mask);
1605 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1606 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1607 tcg_temp_free(t0);
1608 tcg_temp_free(t1);
1609 }
1610 if (unlikely(Rc(ctx->opcode) != 0))
1611 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1612 }
1613
1614 /* rlwinm & rlwinm. */
1615 static void gen_rlwinm(DisasContext *ctx)
1616 {
1617 uint32_t mb, me, sh;
1618
1619 sh = SH(ctx->opcode);
1620 mb = MB(ctx->opcode);
1621 me = ME(ctx->opcode);
1622
1623 if (likely(mb == 0 && me == (31 - sh))) {
1624 if (likely(sh == 0)) {
1625 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1626 } else {
1627 TCGv t0 = tcg_temp_new();
1628 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1629 tcg_gen_shli_tl(t0, t0, sh);
1630 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1631 tcg_temp_free(t0);
1632 }
1633 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1634 TCGv t0 = tcg_temp_new();
1635 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1636 tcg_gen_shri_tl(t0, t0, mb);
1637 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1638 tcg_temp_free(t0);
1639 } else {
1640 TCGv t0 = tcg_temp_new();
1641 #if defined(TARGET_PPC64)
1642 TCGv_i32 t1 = tcg_temp_new_i32();
1643 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1644 tcg_gen_rotli_i32(t1, t1, sh);
1645 tcg_gen_extu_i32_i64(t0, t1);
1646 tcg_temp_free_i32(t1);
1647 #else
1648 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1649 #endif
1650 #if defined(TARGET_PPC64)
1651 mb += 32;
1652 me += 32;
1653 #endif
1654 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1655 tcg_temp_free(t0);
1656 }
1657 if (unlikely(Rc(ctx->opcode) != 0))
1658 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1659 }
1660
1661 /* rlwnm & rlwnm. */
1662 static void gen_rlwnm(DisasContext *ctx)
1663 {
1664 uint32_t mb, me;
1665 TCGv t0;
1666 #if defined(TARGET_PPC64)
1667 TCGv_i32 t1, t2;
1668 #endif
1669
1670 mb = MB(ctx->opcode);
1671 me = ME(ctx->opcode);
1672 t0 = tcg_temp_new();
1673 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1674 #if defined(TARGET_PPC64)
1675 t1 = tcg_temp_new_i32();
1676 t2 = tcg_temp_new_i32();
1677 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1678 tcg_gen_trunc_i64_i32(t2, t0);
1679 tcg_gen_rotl_i32(t1, t1, t2);
1680 tcg_gen_extu_i32_i64(t0, t1);
1681 tcg_temp_free_i32(t1);
1682 tcg_temp_free_i32(t2);
1683 #else
1684 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1685 #endif
1686 if (unlikely(mb != 0 || me != 31)) {
1687 #if defined(TARGET_PPC64)
1688 mb += 32;
1689 me += 32;
1690 #endif
1691 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1692 } else {
1693 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1694 }
1695 tcg_temp_free(t0);
1696 if (unlikely(Rc(ctx->opcode) != 0))
1697 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1698 }
1699
1700 #if defined(TARGET_PPC64)
1701 #define GEN_PPC64_R2(name, opc1, opc2) \
1702 static void glue(gen_, name##0)(DisasContext *ctx) \
1703 { \
1704 gen_##name(ctx, 0); \
1705 } \
1706 \
1707 static void glue(gen_, name##1)(DisasContext *ctx) \
1708 { \
1709 gen_##name(ctx, 1); \
1710 }
1711 #define GEN_PPC64_R4(name, opc1, opc2) \
1712 static void glue(gen_, name##0)(DisasContext *ctx) \
1713 { \
1714 gen_##name(ctx, 0, 0); \
1715 } \
1716 \
1717 static void glue(gen_, name##1)(DisasContext *ctx) \
1718 { \
1719 gen_##name(ctx, 0, 1); \
1720 } \
1721 \
1722 static void glue(gen_, name##2)(DisasContext *ctx) \
1723 { \
1724 gen_##name(ctx, 1, 0); \
1725 } \
1726 \
1727 static void glue(gen_, name##3)(DisasContext *ctx) \
1728 { \
1729 gen_##name(ctx, 1, 1); \
1730 }
1731
1732 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1733 uint32_t sh)
1734 {
1735 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1736 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1737 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1738 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1739 } else {
1740 TCGv t0 = tcg_temp_new();
1741 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1742 if (likely(mb == 0 && me == 63)) {
1743 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1744 } else {
1745 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1746 }
1747 tcg_temp_free(t0);
1748 }
1749 if (unlikely(Rc(ctx->opcode) != 0))
1750 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1751 }
1752 /* rldicl - rldicl. */
1753 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1754 {
1755 uint32_t sh, mb;
1756
1757 sh = SH(ctx->opcode) | (shn << 5);
1758 mb = MB(ctx->opcode) | (mbn << 5);
1759 gen_rldinm(ctx, mb, 63, sh);
1760 }
1761 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1762 /* rldicr - rldicr. */
1763 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1764 {
1765 uint32_t sh, me;
1766
1767 sh = SH(ctx->opcode) | (shn << 5);
1768 me = MB(ctx->opcode) | (men << 5);
1769 gen_rldinm(ctx, 0, me, sh);
1770 }
1771 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1772 /* rldic - rldic. */
1773 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1774 {
1775 uint32_t sh, mb;
1776
1777 sh = SH(ctx->opcode) | (shn << 5);
1778 mb = MB(ctx->opcode) | (mbn << 5);
1779 gen_rldinm(ctx, mb, 63 - sh, sh);
1780 }
1781 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1782
1783 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1784 {
1785 TCGv t0;
1786
1787 t0 = tcg_temp_new();
1788 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1789 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1790 if (unlikely(mb != 0 || me != 63)) {
1791 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1792 } else {
1793 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1794 }
1795 tcg_temp_free(t0);
1796 if (unlikely(Rc(ctx->opcode) != 0))
1797 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1798 }
1799
1800 /* rldcl - rldcl. */
1801 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1802 {
1803 uint32_t mb;
1804
1805 mb = MB(ctx->opcode) | (mbn << 5);
1806 gen_rldnm(ctx, mb, 63);
1807 }
1808 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1809 /* rldcr - rldcr. */
1810 static inline void gen_rldcr(DisasContext *ctx, int men)
1811 {
1812 uint32_t me;
1813
1814 me = MB(ctx->opcode) | (men << 5);
1815 gen_rldnm(ctx, 0, me);
1816 }
1817 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1818 /* rldimi - rldimi. */
1819 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1820 {
1821 uint32_t sh, mb, me;
1822
1823 sh = SH(ctx->opcode) | (shn << 5);
1824 mb = MB(ctx->opcode) | (mbn << 5);
1825 me = 63 - sh;
1826 if (unlikely(sh == 0 && mb == 0)) {
1827 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1828 } else {
1829 TCGv t0, t1;
1830 target_ulong mask;
1831
1832 t0 = tcg_temp_new();
1833 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1834 t1 = tcg_temp_new();
1835 mask = MASK(mb, me);
1836 tcg_gen_andi_tl(t0, t0, mask);
1837 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1838 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1839 tcg_temp_free(t0);
1840 tcg_temp_free(t1);
1841 }
1842 if (unlikely(Rc(ctx->opcode) != 0))
1843 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1844 }
1845 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1846 #endif
1847
1848 /*** Integer shift ***/
1849
1850 /* slw & slw. */
1851 static void gen_slw(DisasContext *ctx)
1852 {
1853 TCGv t0, t1;
1854
1855 t0 = tcg_temp_new();
1856 /* AND rS with a mask that is 0 when rB >= 0x20 */
1857 #if defined(TARGET_PPC64)
1858 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1859 tcg_gen_sari_tl(t0, t0, 0x3f);
1860 #else
1861 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1862 tcg_gen_sari_tl(t0, t0, 0x1f);
1863 #endif
1864 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1865 t1 = tcg_temp_new();
1866 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1867 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1868 tcg_temp_free(t1);
1869 tcg_temp_free(t0);
1870 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1871 if (unlikely(Rc(ctx->opcode) != 0))
1872 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1873 }
1874
1875 /* sraw & sraw. */
1876 static void gen_sraw(DisasContext *ctx)
1877 {
1878 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1879 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1880 if (unlikely(Rc(ctx->opcode) != 0))
1881 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1882 }
1883
1884 /* srawi & srawi. */
1885 static void gen_srawi(DisasContext *ctx)
1886 {
1887 int sh = SH(ctx->opcode);
1888 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1889 TCGv src = cpu_gpr[rS(ctx->opcode)];
1890 if (sh == 0) {
1891 tcg_gen_mov_tl(dst, src);
1892 tcg_gen_movi_tl(cpu_ca, 0);
1893 } else {
1894 TCGv t0;
1895 tcg_gen_ext32s_tl(dst, src);
1896 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1897 t0 = tcg_temp_new();
1898 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1899 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1900 tcg_temp_free(t0);
1901 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1902 tcg_gen_sari_tl(dst, dst, sh);
1903 }
1904 if (unlikely(Rc(ctx->opcode) != 0)) {
1905 gen_set_Rc0(ctx, dst);
1906 }
1907 }
1908
1909 /* srw & srw. */
1910 static void gen_srw(DisasContext *ctx)
1911 {
1912 TCGv t0, t1;
1913
1914 t0 = tcg_temp_new();
1915 /* AND rS with a mask that is 0 when rB >= 0x20 */
1916 #if defined(TARGET_PPC64)
1917 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1918 tcg_gen_sari_tl(t0, t0, 0x3f);
1919 #else
1920 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1921 tcg_gen_sari_tl(t0, t0, 0x1f);
1922 #endif
1923 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1924 tcg_gen_ext32u_tl(t0, t0);
1925 t1 = tcg_temp_new();
1926 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1927 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1928 tcg_temp_free(t1);
1929 tcg_temp_free(t0);
1930 if (unlikely(Rc(ctx->opcode) != 0))
1931 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1932 }
1933
1934 #if defined(TARGET_PPC64)
1935 /* sld & sld. */
1936 static void gen_sld(DisasContext *ctx)
1937 {
1938 TCGv t0, t1;
1939
1940 t0 = tcg_temp_new();
1941 /* AND rS with a mask that is 0 when rB >= 0x40 */
1942 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1943 tcg_gen_sari_tl(t0, t0, 0x3f);
1944 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1945 t1 = tcg_temp_new();
1946 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1947 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1948 tcg_temp_free(t1);
1949 tcg_temp_free(t0);
1950 if (unlikely(Rc(ctx->opcode) != 0))
1951 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1952 }
1953
1954 /* srad & srad. */
1955 static void gen_srad(DisasContext *ctx)
1956 {
1957 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1958 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1959 if (unlikely(Rc(ctx->opcode) != 0))
1960 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1961 }
1962 /* sradi & sradi. */
1963 static inline void gen_sradi(DisasContext *ctx, int n)
1964 {
1965 int sh = SH(ctx->opcode) + (n << 5);
1966 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1967 TCGv src = cpu_gpr[rS(ctx->opcode)];
1968 if (sh == 0) {
1969 tcg_gen_mov_tl(dst, src);
1970 tcg_gen_movi_tl(cpu_ca, 0);
1971 } else {
1972 TCGv t0;
1973 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1974 t0 = tcg_temp_new();
1975 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1976 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1977 tcg_temp_free(t0);
1978 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1979 tcg_gen_sari_tl(dst, src, sh);
1980 }
1981 if (unlikely(Rc(ctx->opcode) != 0)) {
1982 gen_set_Rc0(ctx, dst);
1983 }
1984 }
1985
1986 static void gen_sradi0(DisasContext *ctx)
1987 {
1988 gen_sradi(ctx, 0);
1989 }
1990
1991 static void gen_sradi1(DisasContext *ctx)
1992 {
1993 gen_sradi(ctx, 1);
1994 }
1995
1996 /* srd & srd. */
1997 static void gen_srd(DisasContext *ctx)
1998 {
1999 TCGv t0, t1;
2000
2001 t0 = tcg_temp_new();
2002 /* AND rS with a mask that is 0 when rB >= 0x40 */
2003 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2004 tcg_gen_sari_tl(t0, t0, 0x3f);
2005 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2006 t1 = tcg_temp_new();
2007 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2008 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2009 tcg_temp_free(t1);
2010 tcg_temp_free(t0);
2011 if (unlikely(Rc(ctx->opcode) != 0))
2012 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2013 }
2014 #endif
2015
2016 /*** Floating-Point arithmetic ***/
2017 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2018 static void gen_f##name(DisasContext *ctx) \
2019 { \
2020 if (unlikely(!ctx->fpu_enabled)) { \
2021 gen_exception(ctx, POWERPC_EXCP_FPU); \
2022 return; \
2023 } \
2024 /* NIP cannot be restored if the memory exception comes from an helper */ \
2025 gen_update_nip(ctx, ctx->nip - 4); \
2026 gen_reset_fpstatus(); \
2027 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2028 cpu_fpr[rA(ctx->opcode)], \
2029 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2030 if (isfloat) { \
2031 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2032 cpu_fpr[rD(ctx->opcode)]); \
2033 } \
2034 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2035 Rc(ctx->opcode) != 0); \
2036 }
2037
2038 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2039 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2040 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2041
2042 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2043 static void gen_f##name(DisasContext *ctx) \
2044 { \
2045 if (unlikely(!ctx->fpu_enabled)) { \
2046 gen_exception(ctx, POWERPC_EXCP_FPU); \
2047 return; \
2048 } \
2049 /* NIP cannot be restored if the memory exception comes from an helper */ \
2050 gen_update_nip(ctx, ctx->nip - 4); \
2051 gen_reset_fpstatus(); \
2052 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2053 cpu_fpr[rA(ctx->opcode)], \
2054 cpu_fpr[rB(ctx->opcode)]); \
2055 if (isfloat) { \
2056 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2057 cpu_fpr[rD(ctx->opcode)]); \
2058 } \
2059 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2060 set_fprf, Rc(ctx->opcode) != 0); \
2061 }
2062 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2063 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2064 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2065
2066 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2067 static void gen_f##name(DisasContext *ctx) \
2068 { \
2069 if (unlikely(!ctx->fpu_enabled)) { \
2070 gen_exception(ctx, POWERPC_EXCP_FPU); \
2071 return; \
2072 } \
2073 /* NIP cannot be restored if the memory exception comes from an helper */ \
2074 gen_update_nip(ctx, ctx->nip - 4); \
2075 gen_reset_fpstatus(); \
2076 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2077 cpu_fpr[rA(ctx->opcode)], \
2078 cpu_fpr[rC(ctx->opcode)]); \
2079 if (isfloat) { \
2080 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2081 cpu_fpr[rD(ctx->opcode)]); \
2082 } \
2083 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2084 set_fprf, Rc(ctx->opcode) != 0); \
2085 }
2086 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2087 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2088 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2089
2090 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2091 static void gen_f##name(DisasContext *ctx) \
2092 { \
2093 if (unlikely(!ctx->fpu_enabled)) { \
2094 gen_exception(ctx, POWERPC_EXCP_FPU); \
2095 return; \
2096 } \
2097 /* NIP cannot be restored if the memory exception comes from an helper */ \
2098 gen_update_nip(ctx, ctx->nip - 4); \
2099 gen_reset_fpstatus(); \
2100 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2101 cpu_fpr[rB(ctx->opcode)]); \
2102 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2103 set_fprf, Rc(ctx->opcode) != 0); \
2104 }
2105
2106 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2107 static void gen_f##name(DisasContext *ctx) \
2108 { \
2109 if (unlikely(!ctx->fpu_enabled)) { \
2110 gen_exception(ctx, POWERPC_EXCP_FPU); \
2111 return; \
2112 } \
2113 /* NIP cannot be restored if the memory exception comes from an helper */ \
2114 gen_update_nip(ctx, ctx->nip - 4); \
2115 gen_reset_fpstatus(); \
2116 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2117 cpu_fpr[rB(ctx->opcode)]); \
2118 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2119 set_fprf, Rc(ctx->opcode) != 0); \
2120 }
2121
2122 /* fadd - fadds */
2123 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2124 /* fdiv - fdivs */
2125 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2126 /* fmul - fmuls */
2127 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2128
2129 /* fre */
2130 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2131
2132 /* fres */
2133 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2134
2135 /* frsqrte */
2136 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2137
2138 /* frsqrtes */
2139 static void gen_frsqrtes(DisasContext *ctx)
2140 {
2141 if (unlikely(!ctx->fpu_enabled)) {
2142 gen_exception(ctx, POWERPC_EXCP_FPU);
2143 return;
2144 }
2145 /* NIP cannot be restored if the memory exception comes from an helper */
2146 gen_update_nip(ctx, ctx->nip - 4);
2147 gen_reset_fpstatus();
2148 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2149 cpu_fpr[rB(ctx->opcode)]);
2150 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2151 cpu_fpr[rD(ctx->opcode)]);
2152 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2153 }
2154
2155 /* fsel */
2156 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2157 /* fsub - fsubs */
2158 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2159 /* Optional: */
2160
2161 /* fsqrt */
2162 static void gen_fsqrt(DisasContext *ctx)
2163 {
2164 if (unlikely(!ctx->fpu_enabled)) {
2165 gen_exception(ctx, POWERPC_EXCP_FPU);
2166 return;
2167 }
2168 /* NIP cannot be restored if the memory exception comes from an helper */
2169 gen_update_nip(ctx, ctx->nip - 4);
2170 gen_reset_fpstatus();
2171 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2172 cpu_fpr[rB(ctx->opcode)]);
2173 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2174 }
2175
2176 static void gen_fsqrts(DisasContext *ctx)
2177 {
2178 if (unlikely(!ctx->fpu_enabled)) {
2179 gen_exception(ctx, POWERPC_EXCP_FPU);
2180 return;
2181 }
2182 /* NIP cannot be restored if the memory exception comes from an helper */
2183 gen_update_nip(ctx, ctx->nip - 4);
2184 gen_reset_fpstatus();
2185 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2186 cpu_fpr[rB(ctx->opcode)]);
2187 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2188 cpu_fpr[rD(ctx->opcode)]);
2189 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2190 }
2191
2192 /*** Floating-Point multiply-and-add ***/
2193 /* fmadd - fmadds */
2194 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2195 /* fmsub - fmsubs */
2196 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2197 /* fnmadd - fnmadds */
2198 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2199 /* fnmsub - fnmsubs */
2200 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2201
2202 /*** Floating-Point round & convert ***/
2203 /* fctiw */
2204 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2205 /* fctiwz */
2206 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2207 /* frsp */
2208 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2209 #if defined(TARGET_PPC64)
2210 /* fcfid */
2211 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2212 /* fctid */
2213 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2214 /* fctidz */
2215 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2216 #endif
2217
2218 /* frin */
2219 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2220 /* friz */
2221 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2222 /* frip */
2223 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2224 /* frim */
2225 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2226
2227 /*** Floating-Point compare ***/
2228
2229 /* fcmpo */
2230 static void gen_fcmpo(DisasContext *ctx)
2231 {
2232 TCGv_i32 crf;
2233 if (unlikely(!ctx->fpu_enabled)) {
2234 gen_exception(ctx, POWERPC_EXCP_FPU);
2235 return;
2236 }
2237 /* NIP cannot be restored if the memory exception comes from an helper */
2238 gen_update_nip(ctx, ctx->nip - 4);
2239 gen_reset_fpstatus();
2240 crf = tcg_const_i32(crfD(ctx->opcode));
2241 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2242 cpu_fpr[rB(ctx->opcode)], crf);
2243 tcg_temp_free_i32(crf);
2244 gen_helper_float_check_status(cpu_env);
2245 }
2246
2247 /* fcmpu */
2248 static void gen_fcmpu(DisasContext *ctx)
2249 {
2250 TCGv_i32 crf;
2251 if (unlikely(!ctx->fpu_enabled)) {
2252 gen_exception(ctx, POWERPC_EXCP_FPU);
2253 return;
2254 }
2255 /* NIP cannot be restored if the memory exception comes from an helper */
2256 gen_update_nip(ctx, ctx->nip - 4);
2257 gen_reset_fpstatus();
2258 crf = tcg_const_i32(crfD(ctx->opcode));
2259 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2260 cpu_fpr[rB(ctx->opcode)], crf);
2261 tcg_temp_free_i32(crf);
2262 gen_helper_float_check_status(cpu_env);
2263 }
2264
2265 /*** Floating-point move ***/
2266 /* fabs */
2267 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2268 static void gen_fabs(DisasContext *ctx)
2269 {
2270 if (unlikely(!ctx->fpu_enabled)) {
2271 gen_exception(ctx, POWERPC_EXCP_FPU);
2272 return;
2273 }
2274 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2275 ~(1ULL << 63));
2276 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2277 }
2278
2279 /* fmr - fmr. */
2280 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2281 static void gen_fmr(DisasContext *ctx)
2282 {
2283 if (unlikely(!ctx->fpu_enabled)) {
2284 gen_exception(ctx, POWERPC_EXCP_FPU);
2285 return;
2286 }
2287 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2288 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2289 }
2290
2291 /* fnabs */
2292 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2293 static void gen_fnabs(DisasContext *ctx)
2294 {
2295 if (unlikely(!ctx->fpu_enabled)) {
2296 gen_exception(ctx, POWERPC_EXCP_FPU);
2297 return;
2298 }
2299 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2300 1ULL << 63);
2301 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2302 }
2303
2304 /* fneg */
2305 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2306 static void gen_fneg(DisasContext *ctx)
2307 {
2308 if (unlikely(!ctx->fpu_enabled)) {
2309 gen_exception(ctx, POWERPC_EXCP_FPU);
2310 return;
2311 }
2312 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2313 1ULL << 63);
2314 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2315 }
2316
2317 /* fcpsgn: PowerPC 2.05 specification */
2318 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2319 static void gen_fcpsgn(DisasContext *ctx)
2320 {
2321 if (unlikely(!ctx->fpu_enabled)) {
2322 gen_exception(ctx, POWERPC_EXCP_FPU);
2323 return;
2324 }
2325 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2326 cpu_fpr[rB(ctx->opcode)], 0, 63);
2327 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2328 }
2329
2330 static void gen_fmrgew(DisasContext *ctx)
2331 {
2332 TCGv_i64 b0;
2333 if (unlikely(!ctx->fpu_enabled)) {
2334 gen_exception(ctx, POWERPC_EXCP_FPU);
2335 return;
2336 }
2337 b0 = tcg_temp_new_i64();
2338 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2339 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2340 b0, 0, 32);
2341 tcg_temp_free_i64(b0);
2342 }
2343
2344 static void gen_fmrgow(DisasContext *ctx)
2345 {
2346 if (unlikely(!ctx->fpu_enabled)) {
2347 gen_exception(ctx, POWERPC_EXCP_FPU);
2348 return;
2349 }
2350 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2351 cpu_fpr[rB(ctx->opcode)],
2352 cpu_fpr[rA(ctx->opcode)],
2353 32, 32);
2354 }
2355
2356 /*** Floating-Point status & ctrl register ***/
2357
2358 /* mcrfs */
2359 static void gen_mcrfs(DisasContext *ctx)
2360 {
2361 TCGv tmp = tcg_temp_new();
2362 int bfa;
2363
2364 if (unlikely(!ctx->fpu_enabled)) {
2365 gen_exception(ctx, POWERPC_EXCP_FPU);
2366 return;
2367 }
2368 bfa = 4 * (7 - crfS(ctx->opcode));
2369 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2370 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2371 tcg_temp_free(tmp);
2372 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2373 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2374 }
2375
2376 /* mffs */
2377 static void gen_mffs(DisasContext *ctx)
2378 {
2379 if (unlikely(!ctx->fpu_enabled)) {
2380 gen_exception(ctx, POWERPC_EXCP_FPU);
2381 return;
2382 }
2383 gen_reset_fpstatus();
2384 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2385 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2386 }
2387
2388 /* mtfsb0 */
2389 static void gen_mtfsb0(DisasContext *ctx)
2390 {
2391 uint8_t crb;
2392
2393 if (unlikely(!ctx->fpu_enabled)) {
2394 gen_exception(ctx, POWERPC_EXCP_FPU);
2395 return;
2396 }
2397 crb = 31 - crbD(ctx->opcode);
2398 gen_reset_fpstatus();
2399 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2400 TCGv_i32 t0;
2401 /* NIP cannot be restored if the memory exception comes from an helper */
2402 gen_update_nip(ctx, ctx->nip - 4);
2403 t0 = tcg_const_i32(crb);
2404 gen_helper_fpscr_clrbit(cpu_env, t0);
2405 tcg_temp_free_i32(t0);
2406 }
2407 if (unlikely(Rc(ctx->opcode) != 0)) {
2408 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2409 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2410 }
2411 }
2412
2413 /* mtfsb1 */
2414 static void gen_mtfsb1(DisasContext *ctx)
2415 {
2416 uint8_t crb;
2417
2418 if (unlikely(!ctx->fpu_enabled)) {
2419 gen_exception(ctx, POWERPC_EXCP_FPU);
2420 return;
2421 }
2422 crb = 31 - crbD(ctx->opcode);
2423 gen_reset_fpstatus();
2424 /* XXX: we pretend we can only do IEEE floating-point computations */
2425 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2426 TCGv_i32 t0;
2427 /* NIP cannot be restored if the memory exception comes from an helper */
2428 gen_update_nip(ctx, ctx->nip - 4);
2429 t0 = tcg_const_i32(crb);
2430 gen_helper_fpscr_setbit(cpu_env, t0);
2431 tcg_temp_free_i32(t0);
2432 }
2433 if (unlikely(Rc(ctx->opcode) != 0)) {
2434 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2435 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2436 }
2437 /* We can raise a differed exception */
2438 gen_helper_float_check_status(cpu_env);
2439 }
2440
2441 /* mtfsf */
2442 static void gen_mtfsf(DisasContext *ctx)
2443 {
2444 TCGv_i32 t0;
2445 int flm, l, w;
2446
2447 if (unlikely(!ctx->fpu_enabled)) {
2448 gen_exception(ctx, POWERPC_EXCP_FPU);
2449 return;
2450 }
2451 flm = FPFLM(ctx->opcode);
2452 l = FPL(ctx->opcode);
2453 w = FPW(ctx->opcode);
2454 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2455 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2456 return;
2457 }
2458 /* NIP cannot be restored if the memory exception comes from an helper */
2459 gen_update_nip(ctx, ctx->nip - 4);
2460 gen_reset_fpstatus();
2461 if (l) {
2462 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2463 } else {
2464 t0 = tcg_const_i32(flm << (w * 8));
2465 }
2466 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2467 tcg_temp_free_i32(t0);
2468 if (unlikely(Rc(ctx->opcode) != 0)) {
2469 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2470 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2471 }
2472 /* We can raise a differed exception */
2473 gen_helper_float_check_status(cpu_env);
2474 }
2475
2476 /* mtfsfi */
2477 static void gen_mtfsfi(DisasContext *ctx)
2478 {
2479 int bf, sh, w;
2480 TCGv_i64 t0;
2481 TCGv_i32 t1;
2482
2483 if (unlikely(!ctx->fpu_enabled)) {
2484 gen_exception(ctx, POWERPC_EXCP_FPU);
2485 return;
2486 }
2487 w = FPW(ctx->opcode);
2488 bf = FPBF(ctx->opcode);
2489 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2490 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2491 return;
2492 }
2493 sh = (8 * w) + 7 - bf;
2494 /* NIP cannot be restored if the memory exception comes from an helper */
2495 gen_update_nip(ctx, ctx->nip - 4);
2496 gen_reset_fpstatus();
2497 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2498 t1 = tcg_const_i32(1 << sh);
2499 gen_helper_store_fpscr(cpu_env, t0, t1);
2500 tcg_temp_free_i64(t0);
2501 tcg_temp_free_i32(t1);
2502 if (unlikely(Rc(ctx->opcode) != 0)) {
2503 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2504 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2505 }
2506 /* We can raise a differed exception */
2507 gen_helper_float_check_status(cpu_env);
2508 }
2509
2510 /*** Addressing modes ***/
2511 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2512 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2513 target_long maskl)
2514 {
2515 target_long simm = SIMM(ctx->opcode);
2516
2517 simm &= ~maskl;
2518 if (rA(ctx->opcode) == 0) {
2519 if (NARROW_MODE(ctx)) {
2520 simm = (uint32_t)simm;
2521 }
2522 tcg_gen_movi_tl(EA, simm);
2523 } else if (likely(simm != 0)) {
2524 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2525 if (NARROW_MODE(ctx)) {
2526 tcg_gen_ext32u_tl(EA, EA);
2527 }
2528 } else {
2529 if (NARROW_MODE(ctx)) {
2530 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2531 } else {
2532 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2533 }
2534 }
2535 }
2536
2537 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2538 {
2539 if (rA(ctx->opcode) == 0) {
2540 if (NARROW_MODE(ctx)) {
2541 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2542 } else {
2543 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2544 }
2545 } else {
2546 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2547 if (NARROW_MODE(ctx)) {
2548 tcg_gen_ext32u_tl(EA, EA);
2549 }
2550 }
2551 }
2552
2553 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2554 {
2555 if (rA(ctx->opcode) == 0) {
2556 tcg_gen_movi_tl(EA, 0);
2557 } else if (NARROW_MODE(ctx)) {
2558 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2559 } else {
2560 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2561 }
2562 }
2563
2564 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2565 target_long val)
2566 {
2567 tcg_gen_addi_tl(ret, arg1, val);
2568 if (NARROW_MODE(ctx)) {
2569 tcg_gen_ext32u_tl(ret, ret);
2570 }
2571 }
2572
2573 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2574 {
2575 int l1 = gen_new_label();
2576 TCGv t0 = tcg_temp_new();
2577 TCGv_i32 t1, t2;
2578 /* NIP cannot be restored if the memory exception comes from an helper */
2579 gen_update_nip(ctx, ctx->nip - 4);
2580 tcg_gen_andi_tl(t0, EA, mask);
2581 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2582 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2583 t2 = tcg_const_i32(0);
2584 gen_helper_raise_exception_err(cpu_env, t1, t2);
2585 tcg_temp_free_i32(t1);
2586 tcg_temp_free_i32(t2);
2587 gen_set_label(l1);
2588 tcg_temp_free(t0);
2589 }
2590
2591 /*** Integer load ***/
2592 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2593 {
2594 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2595 }
2596
2597 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2598 {
2599 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2600 }
2601
2602 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2603 {
2604 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2605 if (unlikely(ctx->le_mode)) {
2606 tcg_gen_bswap16_tl(arg1, arg1);
2607 }
2608 }
2609
2610 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2611 {
2612 if (unlikely(ctx->le_mode)) {
2613 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2614 tcg_gen_bswap16_tl(arg1, arg1);
2615 tcg_gen_ext16s_tl(arg1, arg1);
2616 } else {
2617 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2618 }
2619 }
2620
2621 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2622 {
2623 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2624 if (unlikely(ctx->le_mode)) {
2625 tcg_gen_bswap32_tl(arg1, arg1);
2626 }
2627 }
2628
2629 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2630 {
2631 TCGv tmp = tcg_temp_new();
2632 gen_qemu_ld32u(ctx, tmp, addr);
2633 tcg_gen_extu_tl_i64(val, tmp);
2634 tcg_temp_free(tmp);
2635 }
2636
2637 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2638 {
2639 if (unlikely(ctx->le_mode)) {
2640 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2641 tcg_gen_bswap32_tl(arg1, arg1);
2642 tcg_gen_ext32s_tl(arg1, arg1);
2643 } else
2644 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2645 }
2646
2647 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2648 {
2649 TCGv tmp = tcg_temp_new();
2650 gen_qemu_ld32s(ctx, tmp, addr);
2651 tcg_gen_ext_tl_i64(val, tmp);
2652 tcg_temp_free(tmp);
2653 }
2654
2655 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2656 {
2657 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2658 if (unlikely(ctx->le_mode)) {
2659 tcg_gen_bswap64_i64(arg1, arg1);
2660 }
2661 }
2662
2663 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2664 {
2665 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2666 }
2667
2668 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2669 {
2670 if (unlikely(ctx->le_mode)) {
2671 TCGv t0 = tcg_temp_new();
2672 tcg_gen_ext16u_tl(t0, arg1);
2673 tcg_gen_bswap16_tl(t0, t0);
2674 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2675 tcg_temp_free(t0);
2676 } else {
2677 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2678 }
2679 }
2680
2681 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2682 {
2683 if (unlikely(ctx->le_mode)) {
2684 TCGv t0 = tcg_temp_new();
2685 tcg_gen_ext32u_tl(t0, arg1);
2686 tcg_gen_bswap32_tl(t0, t0);
2687 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2688 tcg_temp_free(t0);
2689 } else {
2690 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2691 }
2692 }
2693
2694 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2695 {
2696 TCGv tmp = tcg_temp_new();
2697 tcg_gen_trunc_i64_tl(tmp, val);
2698 gen_qemu_st32(ctx, tmp, addr);
2699 tcg_temp_free(tmp);
2700 }
2701
2702 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2703 {
2704 if (unlikely(ctx->le_mode)) {
2705 TCGv_i64 t0 = tcg_temp_new_i64();
2706 tcg_gen_bswap64_i64(t0, arg1);
2707 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2708 tcg_temp_free_i64(t0);
2709 } else
2710 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2711 }
2712
2713 #define GEN_LD(name, ldop, opc, type) \
2714 static void glue(gen_, name)(DisasContext *ctx) \
2715 { \
2716 TCGv EA; \
2717 gen_set_access_type(ctx, ACCESS_INT); \
2718 EA = tcg_temp_new(); \
2719 gen_addr_imm_index(ctx, EA, 0); \
2720 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2721 tcg_temp_free(EA); \
2722 }
2723
2724 #define GEN_LDU(name, ldop, opc, type) \
2725 static void glue(gen_, name##u)(DisasContext *ctx) \
2726 { \
2727 TCGv EA; \
2728 if (unlikely(rA(ctx->opcode) == 0 || \
2729 rA(ctx->opcode) == rD(ctx->opcode))) { \
2730 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2731 return; \
2732 } \
2733 gen_set_access_type(ctx, ACCESS_INT); \
2734 EA = tcg_temp_new(); \
2735 if (type == PPC_64B) \
2736 gen_addr_imm_index(ctx, EA, 0x03); \
2737 else \
2738 gen_addr_imm_index(ctx, EA, 0); \
2739 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2740 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2741 tcg_temp_free(EA); \
2742 }
2743
2744 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2745 static void glue(gen_, name##ux)(DisasContext *ctx) \
2746 { \
2747 TCGv EA; \
2748 if (unlikely(rA(ctx->opcode) == 0 || \
2749 rA(ctx->opcode) == rD(ctx->opcode))) { \
2750 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2751 return; \
2752 } \
2753 gen_set_access_type(ctx, ACCESS_INT); \
2754 EA = tcg_temp_new(); \
2755 gen_addr_reg_index(ctx, EA); \
2756 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2757 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2758 tcg_temp_free(EA); \
2759 }
2760
2761 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2762 static void glue(gen_, name##x)(DisasContext *ctx) \
2763 { \
2764 TCGv EA; \
2765 gen_set_access_type(ctx, ACCESS_INT); \
2766 EA = tcg_temp_new(); \
2767 gen_addr_reg_index(ctx, EA); \
2768 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2769 tcg_temp_free(EA); \
2770 }
2771 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2772 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2773
2774 #define GEN_LDS(name, ldop, op, type) \
2775 GEN_LD(name, ldop, op | 0x20, type); \
2776 GEN_LDU(name, ldop, op | 0x21, type); \
2777 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2778 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2779
2780 /* lbz lbzu lbzux lbzx */
2781 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2782 /* lha lhau lhaux lhax */
2783 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2784 /* lhz lhzu lhzux lhzx */
2785 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2786 /* lwz lwzu lwzux lwzx */
2787 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2788 #if defined(TARGET_PPC64)
2789 /* lwaux */
2790 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2791 /* lwax */
2792 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2793 /* ldux */
2794 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2795 /* ldx */
2796 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2797
2798 static void gen_ld(DisasContext *ctx)
2799 {
2800 TCGv EA;
2801 if (Rc(ctx->opcode)) {
2802 if (unlikely(rA(ctx->opcode) == 0 ||
2803 rA(ctx->opcode) == rD(ctx->opcode))) {
2804 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2805 return;
2806 }
2807 }
2808 gen_set_access_type(ctx, ACCESS_INT);
2809 EA = tcg_temp_new();
2810 gen_addr_imm_index(ctx, EA, 0x03);
2811 if (ctx->opcode & 0x02) {
2812 /* lwa (lwau is undefined) */
2813 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2814 } else {
2815 /* ld - ldu */
2816 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2817 }
2818 if (Rc(ctx->opcode))
2819 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2820 tcg_temp_free(EA);
2821 }
2822
2823 /* lq */
2824 static void gen_lq(DisasContext *ctx)
2825 {
2826 #if defined(CONFIG_USER_ONLY)
2827 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2828 #else
2829 int ra, rd;
2830 TCGv EA;
2831
2832 /* Restore CPU state */
2833 if (unlikely(ctx->mem_idx == 0)) {
2834 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2835 return;
2836 }
2837 ra = rA(ctx->opcode);
2838 rd = rD(ctx->opcode);
2839 if (unlikely((rd & 1) || rd == ra)) {
2840 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2841 return;
2842 }
2843 if (unlikely(ctx->le_mode)) {
2844 /* Little-endian mode is not handled */
2845 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2846 return;
2847 }
2848 gen_set_access_type(ctx, ACCESS_INT);
2849 EA = tcg_temp_new();
2850 gen_addr_imm_index(ctx, EA, 0x0F);
2851 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2852 gen_addr_add(ctx, EA, EA, 8);
2853 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2854 tcg_temp_free(EA);
2855 #endif
2856 }
2857 #endif
2858
2859 /*** Integer store ***/
2860 #define GEN_ST(name, stop, opc, type) \
2861 static void glue(gen_, name)(DisasContext *ctx) \
2862 { \
2863 TCGv EA; \
2864 gen_set_access_type(ctx, ACCESS_INT); \
2865 EA = tcg_temp_new(); \
2866 gen_addr_imm_index(ctx, EA, 0); \
2867 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2868 tcg_temp_free(EA); \
2869 }
2870
2871 #define GEN_STU(name, stop, opc, type) \
2872 static void glue(gen_, stop##u)(DisasContext *ctx) \
2873 { \
2874 TCGv EA; \
2875 if (unlikely(rA(ctx->opcode) == 0)) { \
2876 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2877 return; \
2878 } \
2879 gen_set_access_type(ctx, ACCESS_INT); \
2880 EA = tcg_temp_new(); \
2881 if (type == PPC_64B) \
2882 gen_addr_imm_index(ctx, EA, 0x03); \
2883 else \
2884 gen_addr_imm_index(ctx, EA, 0); \
2885 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2886 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2887 tcg_temp_free(EA); \
2888 }
2889
2890 #define GEN_STUX(name, stop, opc2, opc3, type) \
2891 static void glue(gen_, name##ux)(DisasContext *ctx) \
2892 { \
2893 TCGv EA; \
2894 if (unlikely(rA(ctx->opcode) == 0)) { \
2895 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2896 return; \
2897 } \
2898 gen_set_access_type(ctx, ACCESS_INT); \
2899 EA = tcg_temp_new(); \
2900 gen_addr_reg_index(ctx, EA); \
2901 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2902 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2903 tcg_temp_free(EA); \
2904 }
2905
2906 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2907 static void glue(gen_, name##x)(DisasContext *ctx) \
2908 { \
2909 TCGv EA; \
2910 gen_set_access_type(ctx, ACCESS_INT); \
2911 EA = tcg_temp_new(); \
2912 gen_addr_reg_index(ctx, EA); \
2913 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2914 tcg_temp_free(EA); \
2915 }
2916 #define GEN_STX(name, stop, opc2, opc3, type) \
2917 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2918
2919 #define GEN_STS(name, stop, op, type) \
2920 GEN_ST(name, stop, op | 0x20, type); \
2921 GEN_STU(name, stop, op | 0x21, type); \
2922 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2923 GEN_STX(name, stop, 0x17, op | 0x00, type)
2924
2925 /* stb stbu stbux stbx */
2926 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2927 /* sth sthu sthux sthx */
2928 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2929 /* stw stwu stwux stwx */
2930 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2931 #if defined(TARGET_PPC64)
2932 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2933 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2934
2935 static void gen_std(DisasContext *ctx)
2936 {
2937 int rs;
2938 TCGv EA;
2939
2940 rs = rS(ctx->opcode);
2941 if ((ctx->opcode & 0x3) == 0x2) {
2942 #if defined(CONFIG_USER_ONLY)
2943 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2944 #else
2945 /* stq */
2946 if (unlikely(ctx->mem_idx == 0)) {
2947 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2948 return;
2949 }
2950 if (unlikely(rs & 1)) {
2951 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2952 return;
2953 }
2954 if (unlikely(ctx->le_mode)) {
2955 /* Little-endian mode is not handled */
2956 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2957 return;
2958 }
2959 gen_set_access_type(ctx, ACCESS_INT);
2960 EA = tcg_temp_new();
2961 gen_addr_imm_index(ctx, EA, 0x03);
2962 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2963 gen_addr_add(ctx, EA, EA, 8);
2964 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2965 tcg_temp_free(EA);
2966 #endif
2967 } else {
2968 /* std / stdu */
2969 if (Rc(ctx->opcode)) {
2970 if (unlikely(rA(ctx->opcode) == 0)) {
2971 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2972 return;
2973 }
2974 }
2975 gen_set_access_type(ctx, ACCESS_INT);
2976 EA = tcg_temp_new();
2977 gen_addr_imm_index(ctx, EA, 0x03);
2978 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2979 if (Rc(ctx->opcode))
2980 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2981 tcg_temp_free(EA);
2982 }
2983 }
2984 #endif
2985 /*** Integer load and store with byte reverse ***/
2986 /* lhbrx */
2987 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2988 {
2989 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2990 if (likely(!ctx->le_mode)) {
2991 tcg_gen_bswap16_tl(arg1, arg1);
2992 }
2993 }
2994 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2995
2996 /* lwbrx */
2997 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2998 {
2999 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
3000 if (likely(!ctx->le_mode)) {
3001 tcg_gen_bswap32_tl(arg1, arg1);
3002 }
3003 }
3004 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3005
3006 #if defined(TARGET_PPC64)
3007 /* ldbrx */
3008 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3009 {
3010 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
3011 if (likely(!ctx->le_mode)) {
3012 tcg_gen_bswap64_tl(arg1, arg1);
3013 }
3014 }
3015 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3016 #endif /* TARGET_PPC64 */
3017
3018 /* sthbrx */
3019 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3020 {
3021 if (likely(!ctx->le_mode)) {
3022 TCGv t0 = tcg_temp_new();
3023 tcg_gen_ext16u_tl(t0, arg1);
3024 tcg_gen_bswap16_tl(t0, t0);
3025 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3026 tcg_temp_free(t0);
3027 } else {
3028 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3029 }
3030 }
3031 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3032
3033 /* stwbrx */
3034 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3035 {
3036 if (likely(!ctx->le_mode)) {
3037 TCGv t0 = tcg_temp_new();
3038 tcg_gen_ext32u_tl(t0, arg1);
3039 tcg_gen_bswap32_tl(t0, t0);
3040 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3041 tcg_temp_free(t0);
3042 } else {
3043 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3044 }
3045 }
3046 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3047
3048 #if defined(TARGET_PPC64)
3049 /* stdbrx */
3050 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3051 {
3052 if (likely(!ctx->le_mode)) {
3053 TCGv t0 = tcg_temp_new();
3054 tcg_gen_bswap64_tl(t0, arg1);
3055 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
3056 tcg_temp_free(t0);
3057 } else {
3058 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
3059 }
3060 }
3061 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3062 #endif /* TARGET_PPC64 */
3063
3064 /*** Integer load and store multiple ***/
3065
3066 /* lmw */
3067 static void gen_lmw(DisasContext *ctx)
3068 {
3069 TCGv t0;
3070 TCGv_i32 t1;
3071 gen_set_access_type(ctx, ACCESS_INT);
3072 /* NIP cannot be restored if the memory exception comes from an helper */
3073 gen_update_nip(ctx, ctx->nip - 4);
3074 t0 = tcg_temp_new();
3075 t1 = tcg_const_i32(rD(ctx->opcode));
3076 gen_addr_imm_index(ctx, t0, 0);
3077 gen_helper_lmw(cpu_env, t0, t1);
3078 tcg_temp_free(t0);
3079 tcg_temp_free_i32(t1);
3080 }
3081
3082 /* stmw */
3083 static void gen_stmw(DisasContext *ctx)
3084 {
3085 TCGv t0;
3086 TCGv_i32 t1;
3087 gen_set_access_type(ctx, ACCESS_INT);
3088 /* NIP cannot be restored if the memory exception comes from an helper */
3089 gen_update_nip(ctx, ctx->nip - 4);
3090 t0 = tcg_temp_new();
3091 t1 = tcg_const_i32(rS(ctx->opcode));
3092 gen_addr_imm_index(ctx, t0, 0);
3093 gen_helper_stmw(cpu_env, t0, t1);
3094 tcg_temp_free(t0);
3095 tcg_temp_free_i32(t1);
3096 }
3097
3098 /*** Integer load and store strings ***/
3099
3100 /* lswi */
3101 /* PowerPC32 specification says we must generate an exception if
3102 * rA is in the range of registers to be loaded.
3103 * In an other hand, IBM says this is valid, but rA won't be loaded.
3104 * For now, I'll follow the spec...
3105 */
3106 static void gen_lswi(DisasContext *ctx)
3107 {
3108 TCGv t0;
3109 TCGv_i32 t1, t2;
3110 int nb = NB(ctx->opcode);
3111 int start = rD(ctx->opcode);
3112 int ra = rA(ctx->opcode);
3113 int nr;
3114
3115 if (nb == 0)
3116 nb = 32;
3117 nr = nb / 4;
3118 if (unlikely(((start + nr) > 32 &&
3119 start <= ra && (start + nr - 32) > ra) ||
3120 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3121 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3122 return;
3123 }
3124 gen_set_access_type(ctx, ACCESS_INT);
3125 /* NIP cannot be restored if the memory exception comes from an helper */
3126 gen_update_nip(ctx, ctx->nip - 4);
3127 t0 = tcg_temp_new();
3128 gen_addr_register(ctx, t0);
3129 t1 = tcg_const_i32(nb);
3130 t2 = tcg_const_i32(start);
3131 gen_helper_lsw(cpu_env, t0, t1, t2);
3132 tcg_temp_free(t0);
3133 tcg_temp_free_i32(t1);
3134 tcg_temp_free_i32(t2);
3135 }
3136
3137 /* lswx */
3138 static void gen_lswx(DisasContext *ctx)
3139 {
3140 TCGv t0;
3141 TCGv_i32 t1, t2, t3;
3142 gen_set_access_type(ctx, ACCESS_INT);
3143 /* NIP cannot be restored if the memory exception comes from an helper */
3144 gen_update_nip(ctx, ctx->nip - 4);
3145 t0 = tcg_temp_new();
3146 gen_addr_reg_index(ctx, t0);
3147 t1 = tcg_const_i32(rD(ctx->opcode));
3148 t2 = tcg_const_i32(rA(ctx->opcode));
3149 t3 = tcg_const_i32(rB(ctx->opcode));
3150 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3151 tcg_temp_free(t0);
3152 tcg_temp_free_i32(t1);
3153 tcg_temp_free_i32(t2);
3154 tcg_temp_free_i32(t3);
3155 }
3156
3157 /* stswi */
3158 static void gen_stswi(DisasContext *ctx)
3159 {
3160 TCGv t0;
3161 TCGv_i32 t1, t2;
3162 int nb = NB(ctx->opcode);
3163 gen_set_access_type(ctx, ACCESS_INT);
3164 /* NIP cannot be restored if the memory exception comes from an helper */
3165 gen_update_nip(ctx, ctx->nip - 4);
3166 t0 = tcg_temp_new();
3167 gen_addr_register(ctx, t0);
3168 if (nb == 0)
3169 nb = 32;
3170 t1 = tcg_const_i32(nb);
3171 t2 = tcg_const_i32(rS(ctx->opcode));
3172 gen_helper_stsw(cpu_env, t0, t1, t2);
3173 tcg_temp_free(t0);
3174 tcg_temp_free_i32(t1);
3175 tcg_temp_free_i32(t2);
3176 }
3177
3178 /* stswx */
3179 static void gen_stswx(DisasContext *ctx)
3180 {
3181 TCGv t0;
3182 TCGv_i32 t1, t2;
3183 gen_set_access_type(ctx, ACCESS_INT);
3184 /* NIP cannot be restored if the memory exception comes from an helper */
3185 gen_update_nip(ctx, ctx->nip - 4);
3186 t0 = tcg_temp_new();
3187 gen_addr_reg_index(ctx, t0);
3188 t1 = tcg_temp_new_i32();
3189 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3190 tcg_gen_andi_i32(t1, t1, 0x7F);
3191 t2 = tcg_const_i32(rS(ctx->opcode));
3192 gen_helper_stsw(cpu_env, t0, t1, t2);
3193 tcg_temp_free(t0);
3194 tcg_temp_free_i32(t1);
3195 tcg_temp_free_i32(t2);
3196 }
3197
3198 /*** Memory synchronisation ***/
3199 /* eieio */
3200 static void gen_eieio(DisasContext *ctx)
3201 {
3202 }
3203
3204 /* isync */
3205 static void gen_isync(DisasContext *ctx)
3206 {
3207 gen_stop_exception(ctx);
3208 }
3209
3210 #define LARX(name, len, loadop) \
3211 static void gen_##name(DisasContext *ctx) \
3212 { \
3213 TCGv t0; \
3214 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3215 gen_set_access_type(ctx, ACCESS_RES); \
3216 t0 = tcg_temp_local_new(); \
3217 gen_addr_reg_index(ctx, t0); \
3218 if ((len) > 1) { \
3219 gen_check_align(ctx, t0, (len)-1); \
3220 } \
3221 gen_qemu_##loadop(ctx, gpr, t0); \
3222 tcg_gen_mov_tl(cpu_reserve, t0); \
3223 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3224 tcg_temp_free(t0); \
3225 }
3226
3227 /* lwarx */
3228 LARX(lbarx, 1, ld8u);
3229 LARX(lharx, 2, ld16u);
3230 LARX(lwarx, 4, ld32u);
3231
3232
3233 #if defined(CONFIG_USER_ONLY)
3234 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3235 int reg, int size)
3236 {
3237 TCGv t0 = tcg_temp_new();
3238 uint32_t save_exception = ctx->exception;
3239
3240 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3241 tcg_gen_movi_tl(t0, (size << 5) | reg);
3242 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3243 tcg_temp_free(t0);
3244 gen_update_nip(ctx, ctx->nip-4);
3245 ctx->exception = POWERPC_EXCP_BRANCH;
3246 gen_exception(ctx, POWERPC_EXCP_STCX);
3247 ctx->exception = save_exception;
3248 }
3249 #else
3250 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3251 int reg, int size)
3252 {
3253 int l1;
3254
3255 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3256 l1 = gen_new_label();
3257 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3258 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3259 #if defined(TARGET_PPC64)
3260 if (size == 8) {
3261 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3262 } else
3263 #endif
3264 if (size == 4) {
3265 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3266 } else if (size == 2) {
3267 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3268 } else {
3269 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3270 }
3271 gen_set_label(l1);
3272 tcg_gen_movi_tl(cpu_reserve, -1);
3273 }
3274 #endif
3275
3276 #define STCX(name, len) \
3277 static void gen_##name(DisasContext *ctx) \
3278 { \
3279 TCGv t0; \
3280 gen_set_access_type(ctx, ACCESS_RES); \
3281 t0 = tcg_temp_local_new(); \
3282 gen_addr_reg_index(ctx, t0); \
3283 if (len > 1) { \
3284 gen_check_align(ctx, t0, (len)-1); \
3285 } \
3286 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3287 tcg_temp_free(t0); \
3288 }
3289
3290 STCX(stbcx_, 1);
3291 STCX(sthcx_, 2);
3292 STCX(stwcx_, 4);
3293
3294 #if defined(TARGET_PPC64)
3295 /* ldarx */
3296 LARX(ldarx, 8, ld64);
3297
3298 /* stdcx. */
3299 STCX(stdcx_, 8);
3300 #endif /* defined(TARGET_PPC64) */
3301
3302 /* sync */
3303 static void gen_sync(DisasContext *ctx)
3304 {
3305 }
3306
3307 /* wait */
3308 static void gen_wait(DisasContext *ctx)
3309 {
3310 TCGv_i32 t0 = tcg_temp_new_i32();
3311 tcg_gen_st_i32(t0, cpu_env,
3312 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3313 tcg_temp_free_i32(t0);
3314 /* Stop translation, as the CPU is supposed to sleep from now */
3315 gen_exception_err(ctx, EXCP_HLT, 1);
3316 }
3317
3318 /*** Floating-point load ***/
3319 #define GEN_LDF(name, ldop, opc, type) \
3320 static void glue(gen_, name)(DisasContext *ctx) \
3321 { \
3322 TCGv EA; \
3323 if (unlikely(!ctx->fpu_enabled)) { \
3324 gen_exception(ctx, POWERPC_EXCP_FPU); \
3325 return; \
3326 } \
3327 gen_set_access_type(ctx, ACCESS_FLOAT); \
3328 EA = tcg_temp_new(); \
3329 gen_addr_imm_index(ctx, EA, 0); \
3330 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3331 tcg_temp_free(EA); \
3332 }
3333
3334 #define GEN_LDUF(name, ldop, opc, type) \
3335 static void glue(gen_, name##u)(DisasContext *ctx) \
3336 { \
3337 TCGv EA; \
3338 if (unlikely(!ctx->fpu_enabled)) { \
3339 gen_exception(ctx, POWERPC_EXCP_FPU); \
3340 return; \
3341 } \
3342 if (unlikely(rA(ctx->opcode) == 0)) { \
3343 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3344 return; \
3345 } \
3346 gen_set_access_type(ctx, ACCESS_FLOAT); \
3347 EA = tcg_temp_new(); \
3348 gen_addr_imm_index(ctx, EA, 0); \
3349 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3350 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3351 tcg_temp_free(EA); \
3352 }
3353
3354 #define GEN_LDUXF(name, ldop, opc, type) \
3355 static void glue(gen_, name##ux)(DisasContext *ctx) \
3356 { \
3357 TCGv EA; \
3358 if (unlikely(!ctx->fpu_enabled)) { \
3359 gen_exception(ctx, POWERPC_EXCP_FPU); \
3360 return; \
3361 } \
3362 if (unlikely(rA(ctx->opcode) == 0)) { \
3363 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3364 return; \
3365 } \
3366 gen_set_access_type(ctx, ACCESS_FLOAT); \
3367 EA = tcg_temp_new(); \
3368 gen_addr_reg_index(ctx, EA); \
3369 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3370 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3371 tcg_temp_free(EA); \
3372 }
3373
3374 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3375 static void glue(gen_, name##x)(DisasContext *ctx) \
3376 { \
3377 TCGv EA; \
3378 if (unlikely(!ctx->fpu_enabled)) { \
3379 gen_exception(ctx, POWERPC_EXCP_FPU); \
3380 return; \
3381 } \
3382 gen_set_access_type(ctx, ACCESS_FLOAT); \
3383 EA = tcg_temp_new(); \
3384 gen_addr_reg_index(ctx, EA); \
3385 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3386 tcg_temp_free(EA); \
3387 }
3388
3389 #define GEN_LDFS(name, ldop, op, type) \
3390 GEN_LDF(name, ldop, op | 0x20, type); \
3391 GEN_LDUF(name, ldop, op | 0x21, type); \
3392 GEN_LDUXF(name, ldop, op | 0x01, type); \
3393 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3394
3395 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3396 {
3397 TCGv t0 = tcg_temp_new();
3398 TCGv_i32 t1 = tcg_temp_new_i32();
3399 gen_qemu_ld32u(ctx, t0, arg2);
3400 tcg_gen_trunc_tl_i32(t1, t0);
3401 tcg_temp_free(t0);
3402 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3403 tcg_temp_free_i32(t1);
3404 }
3405
3406 /* lfd lfdu lfdux lfdx */
3407 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3408 /* lfs lfsu lfsux lfsx */
3409 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3410
3411 /* lfdp */
3412 static void gen_lfdp(DisasContext *ctx)
3413 {
3414 TCGv EA;
3415 if (unlikely(!ctx->fpu_enabled)) {
3416 gen_exception(ctx, POWERPC_EXCP_FPU);
3417 return;
3418 }
3419 gen_set_access_type(ctx, ACCESS_FLOAT);
3420 EA = tcg_temp_new();
3421 gen_addr_imm_index(ctx, EA, 0); \
3422 if (unlikely(ctx->le_mode)) {
3423 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3424 tcg_gen_addi_tl(EA, EA, 8);
3425 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3426 } else {
3427 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3428 tcg_gen_addi_tl(EA, EA, 8);
3429 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3430 }
3431 tcg_temp_free(EA);
3432 }
3433
3434 /* lfdpx */
3435 static void gen_lfdpx(DisasContext *ctx)
3436 {
3437 TCGv EA;
3438 if (unlikely(!ctx->fpu_enabled)) {
3439 gen_exception(ctx, POWERPC_EXCP_FPU);
3440 return;
3441 }
3442 gen_set_access_type(ctx, ACCESS_FLOAT);
3443 EA = tcg_temp_new();
3444 gen_addr_reg_index(ctx, EA);
3445 if (unlikely(ctx->le_mode)) {
3446 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3447 tcg_gen_addi_tl(EA, EA, 8);
3448 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3449 } else {
3450 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3451 tcg_gen_addi_tl(EA, EA, 8);
3452 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3453 }
3454 tcg_temp_free(EA);
3455 }
3456
3457 /* lfiwax */
3458 static void gen_lfiwax(DisasContext *ctx)
3459 {
3460 TCGv EA;
3461 TCGv t0;
3462 if (unlikely(!ctx->fpu_enabled)) {
3463 gen_exception(ctx, POWERPC_EXCP_FPU);
3464 return;
3465 }
3466 gen_set_access_type(ctx, ACCESS_FLOAT);
3467 EA = tcg_temp_new();
3468 t0 = tcg_temp_new();
3469 gen_addr_reg_index(ctx, EA);
3470 gen_qemu_ld32s(ctx, t0, EA);
3471 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3472 tcg_temp_free(EA);
3473 tcg_temp_free(t0);
3474 }
3475
3476 /*** Floating-point store ***/
3477 #define GEN_STF(name, stop, opc, type) \
3478 static void glue(gen_, name)(DisasContext *ctx) \
3479 { \
3480 TCGv EA; \
3481 if (unlikely(!ctx->fpu_enabled)) { \
3482 gen_exception(ctx, POWERPC_EXCP_FPU); \
3483 return; \
3484 } \
3485 gen_set_access_type(ctx, ACCESS_FLOAT); \
3486 EA = tcg_temp_new(); \
3487 gen_addr_imm_index(ctx, EA, 0); \
3488 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3489 tcg_temp_free(EA); \
3490 }
3491
3492 #define GEN_STUF(name, stop, opc, type) \
3493 static void glue(gen_, name##u)(DisasContext *ctx) \
3494 { \
3495 TCGv EA; \
3496 if (unlikely(!ctx->fpu_enabled)) { \
3497 gen_exception(ctx, POWERPC_EXCP_FPU); \
3498 return; \
3499 } \
3500 if (unlikely(rA(ctx->opcode) == 0)) { \
3501 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3502 return; \
3503 } \
3504 gen_set_access_type(ctx, ACCESS_FLOAT); \
3505 EA = tcg_temp_new(); \
3506 gen_addr_imm_index(ctx, EA, 0); \
3507 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3508 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3509 tcg_temp_free(EA); \
3510 }
3511
3512 #define GEN_STUXF(name, stop, opc, type) \
3513 static void glue(gen_, name##ux)(DisasContext *ctx) \
3514 { \
3515 TCGv EA; \
3516 if (unlikely(!ctx->fpu_enabled)) { \
3517 gen_exception(ctx, POWERPC_EXCP_FPU); \
3518 return; \
3519 } \
3520 if (unlikely(rA(ctx->opcode) == 0)) { \
3521 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3522 return; \
3523 } \
3524 gen_set_access_type(ctx, ACCESS_FLOAT); \
3525 EA = tcg_temp_new(); \
3526 gen_addr_reg_index(ctx, EA); \
3527 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3528 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3529 tcg_temp_free(EA); \
3530 }
3531
3532 #define GEN_STXF(name, stop, opc2, opc3, type) \
3533 static void glue(gen_, name##x)(DisasContext *ctx) \
3534 { \
3535 TCGv EA; \
3536 if (unlikely(!ctx->fpu_enabled)) { \
3537 gen_exception(ctx, POWERPC_EXCP_FPU); \
3538 return; \
3539 } \
3540 gen_set_access_type(ctx, ACCESS_FLOAT); \
3541 EA = tcg_temp_new(); \
3542 gen_addr_reg_index(ctx, EA); \
3543 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3544 tcg_temp_free(EA); \
3545 }
3546
3547 #define GEN_STFS(name, stop, op, type) \
3548 GEN_STF(name, stop, op | 0x20, type); \
3549 GEN_STUF(name, stop, op | 0x21, type); \
3550 GEN_STUXF(name, stop, op | 0x01, type); \
3551 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3552
3553 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3554 {
3555 TCGv_i32 t0 = tcg_temp_new_i32();
3556 TCGv t1 = tcg_temp_new();
3557 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3558 tcg_gen_extu_i32_tl(t1, t0);
3559 tcg_temp_free_i32(t0);
3560 gen_qemu_st32(ctx, t1, arg2);
3561 tcg_temp_free(t1);
3562 }
3563
3564 /* stfd stfdu stfdux stfdx */
3565 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3566 /* stfs stfsu stfsux stfsx */
3567 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3568
3569 /* stfdp */
3570 static void gen_stfdp(DisasContext *ctx)
3571 {
3572 TCGv EA;
3573 if (unlikely(!ctx->fpu_enabled)) {
3574 gen_exception(ctx, POWERPC_EXCP_FPU);
3575 return;
3576 }
3577 gen_set_access_type(ctx, ACCESS_FLOAT);
3578 EA = tcg_temp_new();
3579 gen_addr_imm_index(ctx, EA, 0); \
3580 if (unlikely(ctx->le_mode)) {
3581 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3582 tcg_gen_addi_tl(EA, EA, 8);
3583 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3584 } else {
3585 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3586 tcg_gen_addi_tl(EA, EA, 8);
3587 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3588 }
3589 tcg_temp_free(EA);
3590 }
3591
3592 /* stfdpx */
3593 static void gen_stfdpx(DisasContext *ctx)
3594 {
3595 TCGv EA;
3596 if (unlikely(!ctx->fpu_enabled)) {
3597 gen_exception(ctx, POWERPC_EXCP_FPU);
3598 return;
3599 }
3600 gen_set_access_type(ctx, ACCESS_FLOAT);
3601 EA = tcg_temp_new();
3602 gen_addr_reg_index(ctx, EA);
3603 if (unlikely(ctx->le_mode)) {
3604 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3605 tcg_gen_addi_tl(EA, EA, 8);
3606 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3607 } else {
3608 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3609 tcg_gen_addi_tl(EA, EA, 8);
3610 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3611 }
3612 tcg_temp_free(EA);
3613 }
3614
3615 /* Optional: */
3616 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3617 {
3618 TCGv t0 = tcg_temp_new();
3619 tcg_gen_trunc_i64_tl(t0, arg1),
3620 gen_qemu_st32(ctx, t0, arg2);
3621 tcg_temp_free(t0);
3622 }
3623 /* stfiwx */
3624 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3625
3626 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3627 {
3628 #if defined(TARGET_PPC64)
3629 if (ctx->has_cfar)
3630 tcg_gen_movi_tl(cpu_cfar, nip);
3631 #endif
3632 }
3633
3634 /*** Branch ***/
3635 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3636 {
3637 TranslationBlock *tb;
3638 tb = ctx->tb;
3639 if (NARROW_MODE(ctx)) {
3640 dest = (uint32_t) dest;
3641 }
3642 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3643 likely(!ctx->singlestep_enabled)) {
3644 tcg_gen_goto_tb(n);
3645 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3646 tcg_gen_exit_tb((uintptr_t)tb + n);
3647 } else {
3648 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3649 if (unlikely(ctx->singlestep_enabled)) {
3650 if ((ctx->singlestep_enabled &
3651 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3652 (ctx->exception == POWERPC_EXCP_BRANCH ||
3653 ctx->exception == POWERPC_EXCP_TRACE)) {
3654 target_ulong tmp = ctx->nip;
3655 ctx->nip = dest;
3656 gen_exception(ctx, POWERPC_EXCP_TRACE);
3657 ctx->nip = tmp;
3658 }
3659 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3660 gen_debug_exception(ctx);
3661 }
3662 }
3663 tcg_gen_exit_tb(0);
3664 }
3665 }
3666
3667 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3668 {
3669 if (NARROW_MODE(ctx)) {
3670 nip = (uint32_t)nip;
3671 }
3672 tcg_gen_movi_tl(cpu_lr, nip);
3673 }
3674
3675 /* b ba bl bla */
3676 static void gen_b(DisasContext *ctx)
3677 {
3678 target_ulong li, target;
3679
3680 ctx->exception = POWERPC_EXCP_BRANCH;
3681 /* sign extend LI */
3682 li = LI(ctx->opcode);
3683 li = (li ^ 0x02000000) - 0x02000000;
3684 if (likely(AA(ctx->opcode) == 0)) {
3685 target = ctx->nip + li - 4;
3686 } else {
3687 target = li;
3688 }
3689 if (LK(ctx->opcode)) {
3690 gen_setlr(ctx, ctx->nip);
3691 }
3692 gen_update_cfar(ctx, ctx->nip);
3693 gen_goto_tb(ctx, 0, target);
3694 }
3695
3696 #define BCOND_IM 0
3697 #define BCOND_LR 1
3698 #define BCOND_CTR 2
3699
3700 static inline void gen_bcond(DisasContext *ctx, int type)
3701 {
3702 uint32_t bo = BO(ctx->opcode);
3703 int l1;
3704 TCGv target;
3705
3706 ctx->exception = POWERPC_EXCP_BRANCH;
3707 if (type == BCOND_LR || type == BCOND_CTR) {
3708 target = tcg_temp_local_new();
3709 if (type == BCOND_CTR)
3710 tcg_gen_mov_tl(target, cpu_ctr);
3711 else
3712 tcg_gen_mov_tl(target, cpu_lr);
3713 } else {
3714 TCGV_UNUSED(target);
3715 }
3716 if (LK(ctx->opcode))
3717 gen_setlr(ctx, ctx->nip);
3718 l1 = gen_new_label();
3719 if ((bo & 0x4) == 0) {
3720 /* Decrement and test CTR */
3721 TCGv temp = tcg_temp_new();
3722 if (unlikely(type == BCOND_CTR)) {
3723 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3724 return;
3725 }
3726 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3727 if (NARROW_MODE(ctx)) {
3728 tcg_gen_ext32u_tl(temp, cpu_ctr);
3729 } else {
3730 tcg_gen_mov_tl(temp, cpu_ctr);
3731 }
3732 if (bo & 0x2) {
3733 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3734 } else {
3735 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3736 }
3737 tcg_temp_free(temp);
3738 }
3739 if ((bo & 0x10) == 0) {
3740 /* Test CR */
3741 uint32_t bi = BI(ctx->opcode);
3742 uint32_t mask = 1 << (3 - (bi & 0x03));
3743 TCGv_i32 temp = tcg_temp_new_i32();
3744
3745 if (bo & 0x8) {
3746 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3747 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3748 } else {
3749 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3750 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3751 }
3752 tcg_temp_free_i32(temp);
3753 }
3754 gen_update_cfar(ctx, ctx->nip);
3755 if (type == BCOND_IM) {
3756 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3757 if (likely(AA(ctx->opcode) == 0)) {
3758 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3759 } else {
3760 gen_goto_tb(ctx, 0, li);
3761 }
3762 gen_set_label(l1);
3763 gen_goto_tb(ctx, 1, ctx->nip);
3764 } else {
3765 if (NARROW_MODE(ctx)) {
3766 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3767 } else {
3768 tcg_gen_andi_tl(cpu_nip, target, ~3);
3769 }
3770 tcg_gen_exit_tb(0);
3771 gen_set_label(l1);
3772 gen_update_nip(ctx, ctx->nip);
3773 tcg_gen_exit_tb(0);
3774 }
3775 }
3776
3777 static void gen_bc(DisasContext *ctx)
3778 {
3779 gen_bcond(ctx, BCOND_IM);
3780 }
3781
3782 static void gen_bcctr(DisasContext *ctx)
3783 {
3784 gen_bcond(ctx, BCOND_CTR);
3785 }
3786
3787 static void gen_bclr(DisasContext *ctx)
3788 {
3789 gen_bcond(ctx, BCOND_LR);
3790 }
3791
3792 /*** Condition register logical ***/
3793 #define GEN_CRLOGIC(name, tcg_op, opc) \
3794 static void glue(gen_, name)(DisasContext *ctx) \
3795 { \
3796 uint8_t bitmask; \
3797 int sh; \
3798 TCGv_i32 t0, t1; \
3799 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3800 t0 = tcg_temp_new_i32(); \
3801 if (sh > 0) \
3802 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3803 else if (sh < 0) \
3804 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3805 else \
3806 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3807 t1 = tcg_temp_new_i32(); \
3808 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3809 if (sh > 0) \
3810 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3811 else if (sh < 0) \
3812 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3813 else \
3814 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3815 tcg_op(t0, t0, t1); \
3816 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3817 tcg_gen_andi_i32(t0, t0, bitmask); \
3818 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3819 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3820 tcg_temp_free_i32(t0); \
3821 tcg_temp_free_i32(t1); \
3822 }
3823
3824 /* crand */
3825 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3826 /* crandc */
3827 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3828 /* creqv */
3829 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3830 /* crnand */
3831 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3832 /* crnor */
3833 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3834 /* cror */
3835 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3836 /* crorc */
3837 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3838 /* crxor */
3839 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3840
3841 /* mcrf */
3842 static void gen_mcrf(DisasContext *ctx)
3843 {
3844 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3845 }
3846
3847 /*** System linkage ***/
3848
3849 /* rfi (mem_idx only) */
3850 static void gen_rfi(DisasContext *ctx)
3851 {
3852 #if defined(CONFIG_USER_ONLY)
3853 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3854 #else
3855 /* Restore CPU state */
3856 if (unlikely(!ctx->mem_idx)) {
3857 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3858 return;
3859 }
3860 gen_update_cfar(ctx, ctx->nip);
3861 gen_helper_rfi(cpu_env);
3862 gen_sync_exception(ctx);
3863 #endif
3864 }
3865
3866 #if defined(TARGET_PPC64)
3867 static void gen_rfid(DisasContext *ctx)
3868 {
3869 #if defined(CONFIG_USER_ONLY)
3870 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3871 #else
3872 /* Restore CPU state */
3873 if (unlikely(!ctx->mem_idx)) {
3874 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3875 return;
3876 }
3877 gen_update_cfar(ctx, ctx->nip);
3878 gen_helper_rfid(cpu_env);
3879 gen_sync_exception(ctx);
3880 #endif
3881 }
3882
3883 static void gen_hrfid(DisasContext *ctx)
3884 {
3885 #if defined(CONFIG_USER_ONLY)
3886 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3887 #else
3888 /* Restore CPU state */
3889 if (unlikely(ctx->mem_idx <= 1)) {
3890 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3891 return;
3892 }
3893 gen_helper_hrfid(cpu_env);
3894 gen_sync_exception(ctx);
3895 #endif
3896 }
3897 #endif
3898
3899 /* sc */
3900 #if defined(CONFIG_USER_ONLY)
3901 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3902 #else
3903 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3904 #endif
3905 static void gen_sc(DisasContext *ctx)
3906 {
3907 uint32_t lev;
3908
3909 lev = (ctx->opcode >> 5) & 0x7F;
3910 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3911 }
3912
3913 /*** Trap ***/
3914
3915 /* tw */
3916 static void gen_tw(DisasContext *ctx)
3917 {
3918 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3919 /* Update the nip since this might generate a trap exception */
3920 gen_update_nip(ctx, ctx->nip);
3921 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3922 t0);
3923 tcg_temp_free_i32(t0);
3924 }
3925
3926 /* twi */
3927 static void gen_twi(DisasContext *ctx)
3928 {
3929 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3930 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3931 /* Update the nip since this might generate a trap exception */
3932 gen_update_nip(ctx, ctx->nip);
3933 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3934 tcg_temp_free(t0);
3935 tcg_temp_free_i32(t1);
3936 }
3937
3938 #if defined(TARGET_PPC64)
3939 /* td */
3940 static void gen_td(DisasContext *ctx)
3941 {
3942 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3943 /* Update the nip since this might generate a trap exception */
3944 gen_update_nip(ctx, ctx->nip);
3945 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3946 t0);
3947 tcg_temp_free_i32(t0);
3948 }
3949
3950 /* tdi */
3951 static void gen_tdi(DisasContext *ctx)
3952 {
3953 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3954 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3955 /* Update the nip since this might generate a trap exception */
3956 gen_update_nip(ctx, ctx->nip);
3957 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3958 tcg_temp_free(t0);
3959 tcg_temp_free_i32(t1);
3960 }
3961 #endif
3962
3963 /*** Processor control ***/
3964
3965 static void gen_read_xer(TCGv dst)
3966 {
3967 TCGv t0 = tcg_temp_new();
3968 TCGv t1 = tcg_temp_new();
3969 TCGv t2 = tcg_temp_new();
3970 tcg_gen_mov_tl(dst, cpu_xer);
3971 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3972 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3973 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3974 tcg_gen_or_tl(t0, t0, t1);
3975 tcg_gen_or_tl(dst, dst, t2);
3976 tcg_gen_or_tl(dst, dst, t0);
3977 tcg_temp_free(t0);
3978 tcg_temp_free(t1);
3979 tcg_temp_free(t2);
3980 }
3981
3982 static void gen_write_xer(TCGv src)
3983 {
3984 tcg_gen_andi_tl(cpu_xer, src,
3985 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3986 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3987 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3988 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3989 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3990 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3991 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3992 }
3993
3994 /* mcrxr */
3995 static void gen_mcrxr(DisasContext *ctx)
3996 {
3997 TCGv_i32 t0 = tcg_temp_new_i32();
3998 TCGv_i32 t1 = tcg_temp_new_i32();
3999 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4000
4001 tcg_gen_trunc_tl_i32(t0, cpu_so);
4002 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4003 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4004 tcg_gen_shri_i32(t0, t0, 2);
4005 tcg_gen_shri_i32(t1, t1, 1);
4006 tcg_gen_or_i32(dst, dst, t0);
4007 tcg_gen_or_i32(dst, dst, t1);
4008 tcg_temp_free_i32(t0);
4009 tcg_temp_free_i32(t1);
4010
4011 tcg_gen_movi_tl(cpu_so, 0);
4012 tcg_gen_movi_tl(cpu_ov, 0);
4013 tcg_gen_movi_tl(cpu_ca, 0);
4014 }
4015
4016 /* mfcr mfocrf */
4017 static void gen_mfcr(DisasContext *ctx)
4018 {
4019 uint32_t crm, crn;
4020
4021 if (likely(ctx->opcode & 0x00100000)) {
4022 crm = CRM(ctx->opcode);
4023 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4024 crn = ctz32 (crm);
4025 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4026 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4027 cpu_gpr[rD(ctx->opcode)], crn * 4);
4028 }
4029 } else {
4030 TCGv_i32 t0 = tcg_temp_new_i32();
4031 tcg_gen_mov_i32(t0, cpu_crf[0]);
4032 tcg_gen_shli_i32(t0, t0, 4);
4033 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4034 tcg_gen_shli_i32(t0, t0, 4);
4035 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4036 tcg_gen_shli_i32(t0, t0, 4);
4037 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4038 tcg_gen_shli_i32(t0, t0, 4);
4039 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4040 tcg_gen_shli_i32(t0, t0, 4);
4041 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4042 tcg_gen_shli_i32(t0, t0, 4);
4043 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4044 tcg_gen_shli_i32(t0, t0, 4);
4045 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4046 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4047 tcg_temp_free_i32(t0);
4048 }
4049 }
4050
4051 /* mfmsr */
4052 static void gen_mfmsr(DisasContext *ctx)
4053 {
4054 #if defined(CONFIG_USER_ONLY)
4055 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4056 #else
4057 if (unlikely(!ctx->mem_idx)) {
4058 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4059 return;
4060 }
4061 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4062 #endif
4063 }
4064
4065 static void spr_noaccess(void *opaque, int gprn, int sprn)
4066 {
4067 #if 0
4068 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4069 printf("ERROR: try to access SPR %d !\n", sprn);
4070 #endif
4071 }
4072 #define SPR_NOACCESS (&spr_noaccess)
4073
4074 /* mfspr */
4075 static inline void gen_op_mfspr(DisasContext *ctx)
4076 {
4077 void (*read_cb)(void *opaque, int gprn, int sprn);
4078 uint32_t sprn = SPR(ctx->opcode);
4079
4080 #if !defined(CONFIG_USER_ONLY)
4081 if (ctx->mem_idx == 2)
4082 read_cb = ctx->spr_cb[sprn].hea_read;
4083 else if (ctx->mem_idx)
4084 read_cb = ctx->spr_cb[sprn].oea_read;
4085 else
4086 #endif
4087 read_cb = ctx->spr_cb[sprn].uea_read;
4088 if (likely(read_cb != NULL)) {
4089 if (likely(read_cb != SPR_NOACCESS)) {
4090 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4091 } else {
4092 /* Privilege exception */
4093 /* This is a hack to avoid warnings when running Linux:
4094 * this OS breaks the PowerPC virtualisation model,
4095 * allowing userland application to read the PVR
4096 */
4097 if (sprn != SPR_PVR) {
4098 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4099 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4100 printf("Trying to read privileged spr %d (0x%03x) at "
4101 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4102 }
4103 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4104 }
4105 } else {
4106 /* Not defined */
4107 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4108 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4109 printf("Trying to read invalid spr %d (0x%03x) at "
4110 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4111 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4112 }
4113 }
4114
4115 static void gen_mfspr(DisasContext *ctx)
4116 {
4117 gen_op_mfspr(ctx);
4118 }
4119
4120 /* mftb */
4121 static void gen_mftb(DisasContext *ctx)
4122 {
4123 gen_op_mfspr(ctx);
4124 }
4125
4126 /* mtcrf mtocrf*/
4127 static void gen_mtcrf(DisasContext *ctx)
4128 {
4129 uint32_t crm, crn;
4130
4131 crm = CRM(ctx->opcode);
4132 if (likely((ctx->opcode & 0x00100000))) {
4133 if (crm && ((crm & (crm - 1)) == 0)) {
4134 TCGv_i32 temp = tcg_temp_new_i32();
4135 crn = ctz32 (crm);
4136 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4137 tcg_gen_shri_i32(temp, temp, crn * 4);
4138 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4139 tcg_temp_free_i32(temp);
4140 }
4141 } else {
4142 TCGv_i32 temp = tcg_temp_new_i32();
4143 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4144 for (crn = 0 ; crn < 8 ; crn++) {
4145 if (crm & (1 << crn)) {
4146 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4147 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4148 }
4149 }
4150 tcg_temp_free_i32(temp);
4151 }
4152 }
4153
4154 /* mtmsr */
4155 #if defined(TARGET_PPC64)
4156 static void gen_mtmsrd(DisasContext *ctx)
4157 {
4158 #if defined(CONFIG_USER_ONLY)
4159 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4160 #else
4161 if (unlikely(!ctx->mem_idx)) {
4162 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4163 return;
4164 }
4165 if (ctx->opcode & 0x00010000) {
4166 /* Special form that does not need any synchronisation */
4167 TCGv t0 = tcg_temp_new();
4168 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4169 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4170 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4171 tcg_temp_free(t0);
4172 } else {
4173 /* XXX: we need to update nip before the store
4174 * if we enter power saving mode, we will exit the loop
4175 * directly from ppc_store_msr
4176 */
4177 gen_update_nip(ctx, ctx->nip);
4178 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4179 /* Must stop the translation as machine state (may have) changed */
4180 /* Note that mtmsr is not always defined as context-synchronizing */
4181 gen_stop_exception(ctx);
4182 }
4183 #endif
4184 }
4185 #endif
4186
4187 static void gen_mtmsr(DisasContext *ctx)
4188 {
4189 #if defined(CONFIG_USER_ONLY)
4190 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4191 #else
4192 if (unlikely(!ctx->mem_idx)) {
4193 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4194 return;
4195 }
4196 if (ctx->opcode & 0x00010000) {
4197 /* Special form that does not need any synchronisation */
4198 TCGv t0 = tcg_temp_new();
4199 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4200 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4201 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4202 tcg_temp_free(t0);
4203 } else {
4204 TCGv msr = tcg_temp_new();
4205
4206 /* XXX: we need to update nip before the store
4207 * if we enter power saving mode, we will exit the loop
4208 * directly from ppc_store_msr
4209 */
4210 gen_update_nip(ctx, ctx->nip);
4211 #if defined(TARGET_PPC64)
4212 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4213 #else
4214 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4215 #endif
4216 gen_helper_store_msr(cpu_env, msr);
4217 /* Must stop the translation as machine state (may have) changed */
4218 /* Note that mtmsr is not always defined as context-synchronizing */
4219 gen_stop_exception(ctx);
4220 }
4221 #endif
4222 }
4223
4224 /* mtspr */
4225 static void gen_mtspr(DisasContext *ctx)
4226 {
4227 void (*write_cb)(void *opaque, int sprn, int gprn);
4228 uint32_t sprn = SPR(ctx->opcode);
4229
4230 #if !defined(CONFIG_USER_ONLY)
4231 if (ctx->mem_idx == 2)
4232 write_cb = ctx->spr_cb[sprn].hea_write;
4233 else if (ctx->mem_idx)
4234 write_cb = ctx->spr_cb[sprn].oea_write;
4235 else
4236 #endif
4237 write_cb = ctx->spr_cb[sprn].uea_write;
4238 if (likely(write_cb != NULL)) {
4239 if (likely(write_cb != SPR_NOACCESS)) {
4240 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4241 } else {
4242 /* Privilege exception */
4243 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4244 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4245 printf("Trying to write privileged spr %d (0x%03x) at "
4246 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4247 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4248 }
4249 } else {
4250 /* Not defined */
4251 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4252 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4253 printf("Trying to write invalid spr %d (0x%03x) at "
4254 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4255 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4256 }
4257 }
4258
4259 /*** Cache management ***/
4260
4261 /* dcbf */
4262 static void gen_dcbf(DisasContext *ctx)
4263 {
4264 /* XXX: specification says this is treated as a load by the MMU */
4265 TCGv t0;
4266 gen_set_access_type(ctx, ACCESS_CACHE);
4267 t0 = tcg_temp_new();
4268 gen_addr_reg_index(ctx, t0);
4269 gen_qemu_ld8u(ctx, t0, t0);
4270 tcg_temp_free(t0);
4271 }
4272
4273 /* dcbi (Supervisor only) */
4274 static void gen_dcbi(DisasContext *ctx)
4275 {
4276 #if defined(CONFIG_USER_ONLY)
4277 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4278 #else
4279 TCGv EA, val;
4280 if (unlikely(!ctx->mem_idx)) {
4281 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4282 return;
4283 }
4284 EA = tcg_temp_new();
4285 gen_set_access_type(ctx, ACCESS_CACHE);
4286 gen_addr_reg_index(ctx, EA);
4287 val = tcg_temp_new();
4288 /* XXX: specification says this should be treated as a store by the MMU */
4289 gen_qemu_ld8u(ctx, val, EA);
4290 gen_qemu_st8(ctx, val, EA);
4291 tcg_temp_free(val);
4292 tcg_temp_free(EA);
4293 #endif
4294 }
4295
4296 /* dcdst */
4297 static void gen_dcbst(DisasContext *ctx)
4298 {
4299 /* XXX: specification say this is treated as a load by the MMU */
4300 TCGv t0;
4301 gen_set_access_type(ctx, ACCESS_CACHE);
4302 t0 = tcg_temp_new();
4303 gen_addr_reg_index(ctx, t0);
4304 gen_qemu_ld8u(ctx, t0, t0);
4305 tcg_temp_free(t0);
4306 }
4307
4308 /* dcbt */
4309 static void gen_dcbt(DisasContext *ctx)
4310 {
4311 /* interpreted as no-op */
4312 /* XXX: specification say this is treated as a load by the MMU
4313 * but does not generate any exception
4314 */
4315 }
4316
4317 /* dcbtst */
4318 static void gen_dcbtst(DisasContext *ctx)
4319 {
4320 /* interpreted as no-op */
4321 /* XXX: specification say this is treated as a load by the MMU
4322 * but does not generate any exception
4323 */
4324 }
4325
4326 /* dcbz */
4327 static void gen_dcbz(DisasContext *ctx)
4328 {
4329 TCGv tcgv_addr;
4330 TCGv_i32 tcgv_is_dcbzl;
4331 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4332
4333 gen_set_access_type(ctx, ACCESS_CACHE);
4334 /* NIP cannot be restored if the memory exception comes from an helper */
4335 gen_update_nip(ctx, ctx->nip - 4);
4336 tcgv_addr = tcg_temp_new();
4337 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4338
4339 gen_addr_reg_index(ctx, tcgv_addr);
4340 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4341
4342 tcg_temp_free(tcgv_addr);
4343 tcg_temp_free_i32(tcgv_is_dcbzl);
4344 }
4345
4346 /* dst / dstt */
4347 static void gen_dst(DisasContext *ctx)
4348 {
4349 if (rA(ctx->opcode) == 0) {
4350 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4351 } else {
4352 /* interpreted as no-op */
4353 }
4354 }
4355
4356 /* dstst /dststt */
4357 static void gen_dstst(DisasContext *ctx)
4358 {
4359 if (rA(ctx->opcode) == 0) {
4360 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4361 } else {
4362 /* interpreted as no-op */
4363 }
4364
4365 }
4366
4367 /* dss / dssall */
4368 static void gen_dss(DisasContext *ctx)
4369 {
4370 /* interpreted as no-op */
4371 }
4372
4373 /* icbi */
4374 static void gen_icbi(DisasContext *ctx)
4375 {
4376 TCGv t0;
4377 gen_set_access_type(ctx, ACCESS_CACHE);
4378 /* NIP cannot be restored if the memory exception comes from an helper */
4379 gen_update_nip(ctx, ctx->nip - 4);
4380 t0 = tcg_temp_new();
4381 gen_addr_reg_index(ctx, t0);
4382 gen_helper_icbi(cpu_env, t0);
4383 tcg_temp_free(t0);
4384 }
4385
4386 /* Optional: */
4387 /* dcba */
4388 static void gen_dcba(DisasContext *ctx)
4389 {
4390 /* interpreted as no-op */
4391 /* XXX: specification say this is treated as a store by the MMU
4392 * but does not generate any exception
4393 */
4394 }
4395
4396 /*** Segment register manipulation ***/
4397 /* Supervisor only: */
4398
4399 /* mfsr */
4400 static void gen_mfsr(DisasContext *ctx)
4401 {
4402 #if defined(CONFIG_USER_ONLY)
4403 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4404 #else
4405 TCGv t0;
4406 if (unlikely(!ctx->mem_idx)) {
4407 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4408 return;
4409 }
4410 t0 = tcg_const_tl(SR(ctx->opcode));
4411 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4412 tcg_temp_free(t0);
4413 #endif
4414 }
4415
4416 /* mfsrin */
4417 static void gen_mfsrin(DisasContext *ctx)
4418 {
4419 #if defined(CONFIG_USER_ONLY)
4420 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4421 #else
4422 TCGv t0;
4423 if (unlikely(!ctx->mem_idx)) {
4424 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4425 return;
4426 }
4427 t0 = tcg_temp_new();
4428 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4429 tcg_gen_andi_tl(t0, t0, 0xF);
4430 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4431 tcg_temp_free(t0);
4432 #endif
4433 }
4434
4435 /* mtsr */
4436 static void gen_mtsr(DisasContext *ctx)
4437 {
4438 #if defined(CONFIG_USER_ONLY)
4439 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4440 #else
4441 TCGv t0;
4442 if (unlikely(!ctx->mem_idx)) {
4443 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4444 return;
4445 }
4446 t0 = tcg_const_tl(SR(ctx->opcode));
4447 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4448 tcg_temp_free(t0);
4449 #endif
4450 }
4451
4452 /* mtsrin */
4453 static void gen_mtsrin(DisasContext *ctx)
4454 {
4455 #if defined(CONFIG_USER_ONLY)
4456 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4457 #else
4458 TCGv t0;
4459 if (unlikely(!ctx->mem_idx)) {
4460 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4461 return;
4462 }
4463 t0 = tcg_temp_new();
4464 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4465 tcg_gen_andi_tl(t0, t0, 0xF);
4466 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4467 tcg_temp_free(t0);
4468 #endif
4469 }
4470
4471 #if defined(TARGET_PPC64)
4472 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4473
4474 /* mfsr */
4475 static void gen_mfsr_64b(DisasContext *ctx)
4476 {
4477 #if defined(CONFIG_USER_ONLY)
4478 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4479 #else
4480 TCGv t0;
4481 if (unlikely(!ctx->mem_idx)) {
4482 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4483 return;
4484 }
4485 t0 = tcg_const_tl(SR(ctx->opcode));
4486 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4487 tcg_temp_free(t0);
4488 #endif
4489 }
4490
4491 /* mfsrin */
4492 static void gen_mfsrin_64b(DisasContext *ctx)
4493 {
4494 #if defined(CONFIG_USER_ONLY)
4495 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4496 #else
4497 TCGv t0;
4498 if (unlikely(!ctx->mem_idx)) {
4499 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4500 return;
4501 }
4502 t0 = tcg_temp_new();
4503 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4504 tcg_gen_andi_tl(t0, t0, 0xF);
4505 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4506 tcg_temp_free(t0);
4507 #endif
4508 }
4509
4510 /* mtsr */
4511 static void gen_mtsr_64b(DisasContext *ctx)
4512 {
4513 #if defined(CONFIG_USER_ONLY)
4514 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4515 #else
4516 TCGv t0;
4517 if (unlikely(!ctx->mem_idx)) {
4518 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4519 return;
4520 }
4521 t0 = tcg_const_tl(SR(ctx->opcode));
4522 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4523 tcg_temp_free(t0);
4524 #endif
4525 }
4526
4527 /* mtsrin */
4528 static void gen_mtsrin_64b(DisasContext *ctx)
4529 {
4530 #if defined(CONFIG_USER_ONLY)
4531 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4532 #else
4533 TCGv t0;
4534 if (unlikely(!ctx->mem_idx)) {
4535 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4536 return;
4537 }
4538 t0 = tcg_temp_new();
4539 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4540 tcg_gen_andi_tl(t0, t0, 0xF);
4541 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4542 tcg_temp_free(t0);
4543 #endif
4544 }
4545
4546 /* slbmte */
4547 static void gen_slbmte(DisasContext *ctx)
4548 {
4549 #if defined(CONFIG_USER_ONLY)
4550 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4551 #else
4552 if (unlikely(!ctx->mem_idx)) {
4553 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4554 return;
4555 }
4556 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4557 cpu_gpr[rS(ctx->opcode)]);
4558 #endif
4559 }
4560
4561 static void gen_slbmfee(DisasContext *ctx)
4562 {
4563 #if defined(CONFIG_USER_ONLY)
4564 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4565 #else
4566 if (unlikely(!ctx->mem_idx)) {
4567 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4568 return;
4569 }
4570 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4571 cpu_gpr[rB(ctx->opcode)]);
4572 #endif
4573 }
4574
4575 static void gen_slbmfev(DisasContext *ctx)
4576 {
4577 #if defined(CONFIG_USER_ONLY)
4578 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4579 #else
4580 if (unlikely(!ctx->mem_idx)) {
4581 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4582 return;
4583 }
4584 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4585 cpu_gpr[rB(ctx->opcode)]);
4586 #endif
4587 }
4588 #endif /* defined(TARGET_PPC64) */
4589
4590 /*** Lookaside buffer management ***/
4591 /* Optional & mem_idx only: */
4592
4593 /* tlbia */
4594 static void gen_tlbia(DisasContext *ctx)
4595 {
4596 #if defined(CONFIG_USER_ONLY)
4597 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4598 #else
4599 if (unlikely(!ctx->mem_idx)) {
4600 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4601 return;
4602 }
4603 gen_helper_tlbia(cpu_env);
4604 #endif
4605 }
4606
4607 /* tlbiel */
4608 static void gen_tlbiel(DisasContext *ctx)
4609 {
4610 #if defined(CONFIG_USER_ONLY)
4611 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4612 #else
4613 if (unlikely(!ctx->mem_idx)) {
4614 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4615 return;
4616 }
4617 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4618 #endif
4619 }
4620
4621 /* tlbie */
4622 static void gen_tlbie(DisasContext *ctx)
4623 {
4624 #if defined(CONFIG_USER_ONLY)
4625 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4626 #else
4627 if (unlikely(!ctx->mem_idx)) {
4628 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4629 return;
4630 }
4631 if (NARROW_MODE(ctx)) {
4632 TCGv t0 = tcg_temp_new();
4633 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4634 gen_helper_tlbie(cpu_env, t0);
4635 tcg_temp_free(t0);
4636 } else {
4637 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4638 }
4639 #endif
4640 }
4641
4642 /* tlbsync */
4643 static void gen_tlbsync(DisasContext *ctx)
4644 {
4645 #if defined(CONFIG_USER_ONLY)
4646 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4647 #else
4648 if (unlikely(!ctx->mem_idx)) {
4649 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4650 return;
4651 }
4652 /* This has no effect: it should ensure that all previous
4653 * tlbie have completed
4654 */
4655 gen_stop_exception(ctx);
4656 #endif
4657 }
4658
4659 #if defined(TARGET_PPC64)
4660 /* slbia */
4661 static void gen_slbia(DisasContext *ctx)
4662 {
4663 #if defined(CONFIG_USER_ONLY)
4664 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4665 #else
4666 if (unlikely(!ctx->mem_idx)) {
4667 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4668 return;
4669 }
4670 gen_helper_slbia(cpu_env);
4671 #endif
4672 }
4673
4674 /* slbie */
4675 static void gen_slbie(DisasContext *ctx)
4676 {
4677 #if defined(CONFIG_USER_ONLY)
4678 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4679 #else
4680 if (unlikely(!ctx->mem_idx)) {
4681 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4682 return;
4683 }
4684 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4685 #endif
4686 }
4687 #endif
4688
4689 /*** External control ***/
4690 /* Optional: */
4691
4692 /* eciwx */
4693 static void gen_eciwx(DisasContext *ctx)
4694 {
4695 TCGv t0;
4696 /* Should check EAR[E] ! */
4697 gen_set_access_type(ctx, ACCESS_EXT);
4698 t0 = tcg_temp_new();
4699 gen_addr_reg_index(ctx, t0);
4700 gen_check_align(ctx, t0, 0x03);
4701 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4702 tcg_temp_free(t0);
4703 }
4704
4705 /* ecowx */
4706 static void gen_ecowx(DisasContext *ctx)
4707 {
4708 TCGv t0;
4709 /* Should check EAR[E] ! */
4710 gen_set_access_type(ctx, ACCESS_EXT);
4711 t0 = tcg_temp_new();
4712 gen_addr_reg_index(ctx, t0);
4713 gen_check_align(ctx, t0, 0x03);
4714 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4715 tcg_temp_free(t0);
4716 }
4717
4718 /* PowerPC 601 specific instructions */
4719
4720 /* abs - abs. */
4721 static void gen_abs(DisasContext *ctx)
4722 {
4723 int l1 = gen_new_label();
4724 int l2 = gen_new_label();
4725 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4726 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4727 tcg_gen_br(l2);
4728 gen_set_label(l1);
4729 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4730 gen_set_label(l2);
4731 if (unlikely(Rc(ctx->opcode) != 0))
4732 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4733 }
4734
4735 /* abso - abso. */
4736 static void gen_abso(DisasContext *ctx)
4737 {
4738 int l1 = gen_new_label();
4739 int l2 = gen_new_label();
4740 int l3 = gen_new_label();
4741 /* Start with XER OV disabled, the most likely case */
4742 tcg_gen_movi_tl(cpu_ov, 0);
4743 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4744 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4745 tcg_gen_movi_tl(cpu_ov, 1);
4746 tcg_gen_movi_tl(cpu_so, 1);
4747 tcg_gen_br(l2);
4748 gen_set_label(l1);
4749 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4750 tcg_gen_br(l3);
4751 gen_set_label(l2);
4752 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4753 gen_set_label(l3);
4754 if (unlikely(Rc(ctx->opcode) != 0))
4755 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4756 }
4757
4758 /* clcs */
4759 static void gen_clcs(DisasContext *ctx)
4760 {
4761 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4762 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4763 tcg_temp_free_i32(t0);
4764 /* Rc=1 sets CR0 to an undefined state */
4765 }
4766
4767 /* div - div. */
4768 static void gen_div(DisasContext *ctx)
4769 {
4770 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4771 cpu_gpr[rB(ctx->opcode)]);
4772 if (unlikely(Rc(ctx->opcode) != 0))
4773 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4774 }
4775
4776 /* divo - divo. */
4777 static void gen_divo(DisasContext *ctx)
4778 {
4779 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4780 cpu_gpr[rB(ctx->opcode)]);
4781 if (unlikely(Rc(ctx->opcode) != 0))
4782 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4783 }
4784
4785 /* divs - divs. */
4786 static void gen_divs(DisasContext *ctx)
4787 {
4788 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4789 cpu_gpr[rB(ctx->opcode)]);
4790 if (unlikely(Rc(ctx->opcode) != 0))
4791 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4792 }
4793
4794 /* divso - divso. */
4795 static void gen_divso(DisasContext *ctx)
4796 {
4797 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4798 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4799 if (unlikely(Rc(ctx->opcode) != 0))
4800 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4801 }
4802
4803 /* doz - doz. */
4804 static void gen_doz(DisasContext *ctx)
4805 {
4806 int l1 = gen_new_label();
4807 int l2 = gen_new_label();
4808 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4809 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4810 tcg_gen_br(l2);
4811 gen_set_label(l1);
4812 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4813 gen_set_label(l2);
4814 if (unlikely(Rc(ctx->opcode) != 0))
4815 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4816 }
4817
4818 /* dozo - dozo. */
4819 static void gen_dozo(DisasContext *ctx)
4820 {
4821 int l1 = gen_new_label();
4822 int l2 = gen_new_label();
4823 TCGv t0 = tcg_temp_new();
4824 TCGv t1 = tcg_temp_new();
4825 TCGv t2 = tcg_temp_new();
4826 /* Start with XER OV disabled, the most likely case */
4827 tcg_gen_movi_tl(cpu_ov, 0);
4828 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4829 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4830 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4831 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4832 tcg_gen_andc_tl(t1, t1, t2);
4833 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4834 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4835 tcg_gen_movi_tl(cpu_ov, 1);
4836 tcg_gen_movi_tl(cpu_so, 1);
4837 tcg_gen_br(l2);
4838 gen_set_label(l1);
4839 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4840 gen_set_label(l2);
4841 tcg_temp_free(t0);
4842 tcg_temp_free(t1);
4843 tcg_temp_free(t2);
4844 if (unlikely(Rc(ctx->opcode) != 0))
4845 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4846 }
4847
4848 /* dozi */
4849 static void gen_dozi(DisasContext *ctx)
4850 {
4851 target_long simm = SIMM(ctx->opcode);
4852 int l1 = gen_new_label();
4853 int l2 = gen_new_label();
4854 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4855 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4856 tcg_gen_br(l2);
4857 gen_set_label(l1);
4858 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4859 gen_set_label(l2);
4860 if (unlikely(Rc(ctx->opcode) != 0))
4861 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4862 }
4863
4864 /* lscbx - lscbx. */
4865 static void gen_lscbx(DisasContext *ctx)
4866 {
4867 TCGv t0 = tcg_temp_new();
4868 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4869 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4870 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4871
4872 gen_addr_reg_index(ctx, t0);
4873 /* NIP cannot be restored if the memory exception comes from an helper */
4874 gen_update_nip(ctx, ctx->nip - 4);
4875 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4876 tcg_temp_free_i32(t1);
4877 tcg_temp_free_i32(t2);
4878 tcg_temp_free_i32(t3);
4879 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4880 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4881 if (unlikely(Rc(ctx->opcode) != 0))
4882 gen_set_Rc0(ctx, t0);
4883 tcg_temp_free(t0);
4884 }
4885
4886 /* maskg - maskg. */
4887 static void gen_maskg(DisasContext *ctx)
4888 {
4889 int l1 = gen_new_label();
4890 TCGv t0 = tcg_temp_new();
4891 TCGv t1 = tcg_temp_new();
4892 TCGv t2 = tcg_temp_new();
4893 TCGv t3 = tcg_temp_new();
4894 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4895 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4896 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4897 tcg_gen_addi_tl(t2, t0, 1);
4898 tcg_gen_shr_tl(t2, t3, t2);
4899 tcg_gen_shr_tl(t3, t3, t1);
4900 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4901 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4902 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4903 gen_set_label(l1);
4904 tcg_temp_free(t0);
4905 tcg_temp_free(t1);
4906 tcg_temp_free(t2);
4907 tcg_temp_free(t3);
4908 if (unlikely(Rc(ctx->opcode) != 0))
4909 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4910 }
4911
4912 /* maskir - maskir. */
4913 static void gen_maskir(DisasContext *ctx)
4914 {
4915 TCGv t0 = tcg_temp_new();
4916 TCGv t1 = tcg_temp_new();
4917 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4918 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4919 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4920 tcg_temp_free(t0);
4921 tcg_temp_free(t1);
4922 if (unlikely(Rc(ctx->opcode) != 0))
4923 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4924 }
4925
4926 /* mul - mul. */
4927 static void gen_mul(DisasContext *ctx)
4928 {
4929 TCGv_i64 t0 = tcg_temp_new_i64();
4930 TCGv_i64 t1 = tcg_temp_new_i64();
4931 TCGv t2 = tcg_temp_new();
4932 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4933 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4934 tcg_gen_mul_i64(t0, t0, t1);
4935 tcg_gen_trunc_i64_tl(t2, t0);
4936 gen_store_spr(SPR_MQ, t2);
4937 tcg_gen_shri_i64(t1, t0, 32);
4938 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4939 tcg_temp_free_i64(t0);
4940 tcg_temp_free_i64(t1);
4941 tcg_temp_free(t2);
4942 if (unlikely(Rc(ctx->opcode) != 0))
4943 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4944 }
4945
4946 /* mulo - mulo. */
4947 static void gen_mulo(DisasContext *ctx)
4948 {
4949 int l1 = gen_new_label();
4950 TCGv_i64 t0 = tcg_temp_new_i64();
4951 TCGv_i64 t1 = tcg_temp_new_i64();
4952 TCGv t2 = tcg_temp_new();
4953 /* Start with XER OV disabled, the most likely case */
4954 tcg_gen_movi_tl(cpu_ov, 0);
4955 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4956 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4957 tcg_gen_mul_i64(t0, t0, t1);
4958 tcg_gen_trunc_i64_tl(t2, t0);
4959 gen_store_spr(SPR_MQ, t2);
4960 tcg_gen_shri_i64(t1, t0, 32);
4961 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4962 tcg_gen_ext32s_i64(t1, t0);
4963 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4964 tcg_gen_movi_tl(cpu_ov, 1);
4965 tcg_gen_movi_tl(cpu_so, 1);
4966 gen_set_label(l1);
4967 tcg_temp_free_i64(t0);
4968 tcg_temp_free_i64(t1);
4969 tcg_temp_free(t2);
4970 if (unlikely(Rc(ctx->opcode) != 0))
4971 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4972 }
4973
4974 /* nabs - nabs. */
4975 static void gen_nabs(DisasContext *ctx)
4976 {
4977 int l1 = gen_new_label();
4978 int l2 = gen_new_label();
4979 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4980 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4981 tcg_gen_br(l2);
4982 gen_set_label(l1);
4983 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4984 gen_set_label(l2);
4985 if (unlikely(Rc(ctx->opcode) != 0))
4986 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4987 }
4988
4989 /* nabso - nabso. */
4990 static void gen_nabso(DisasContext *ctx)
4991 {
4992 int l1 = gen_new_label();
4993 int l2 = gen_new_label();
4994 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4995 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4996 tcg_gen_br(l2);
4997 gen_set_label(l1);
4998 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4999 gen_set_label(l2);
5000 /* nabs never overflows */
5001 tcg_gen_movi_tl(cpu_ov, 0);
5002 if (unlikely(Rc(ctx->opcode) != 0))
5003 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5004 }
5005
5006 /* rlmi - rlmi. */
5007 static void gen_rlmi(DisasContext *ctx)
5008 {
5009 uint32_t mb = MB(ctx->opcode);
5010 uint32_t me = ME(ctx->opcode);
5011 TCGv t0 = tcg_temp_new();
5012 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5013 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5014 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5015 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5016 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5017 tcg_temp_free(t0);
5018 if (unlikely(Rc(ctx->opcode) != 0))
5019 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5020 }
5021
5022 /* rrib - rrib. */
5023 static void gen_rrib(DisasContext *ctx)
5024 {
5025 TCGv t0 = tcg_temp_new();
5026 TCGv t1 = tcg_temp_new();
5027 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5028 tcg_gen_movi_tl(t1, 0x80000000);
5029 tcg_gen_shr_tl(t1, t1, t0);
5030 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5031 tcg_gen_and_tl(t0, t0, t1);
5032 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5033 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5034 tcg_temp_free(t0);
5035 tcg_temp_free(t1);
5036 if (unlikely(Rc(ctx->opcode) != 0))
5037 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5038 }
5039
5040 /* sle - sle. */
5041 static void gen_sle(DisasContext *ctx)
5042 {
5043 TCGv t0 = tcg_temp_new();
5044 TCGv t1 = tcg_temp_new();
5045 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5046 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5047 tcg_gen_subfi_tl(t1, 32, t1);
5048 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5049 tcg_gen_or_tl(t1, t0, t1);
5050 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5051 gen_store_spr(SPR_MQ, t1);
5052 tcg_temp_free(t0);
5053 tcg_temp_free(t1);
5054 if (unlikely(Rc(ctx->opcode) != 0))
5055 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5056 }
5057
5058 /* sleq - sleq. */
5059 static void gen_sleq(DisasContext *ctx)
5060 {
5061 TCGv t0 = tcg_temp_new();
5062 TCGv t1 = tcg_temp_new();
5063 TCGv t2 = tcg_temp_new();
5064 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5065 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5066 tcg_gen_shl_tl(t2, t2, t0);
5067 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5068 gen_load_spr(t1, SPR_MQ);
5069 gen_store_spr(SPR_MQ, t0);
5070 tcg_gen_and_tl(t0, t0, t2);
5071 tcg_gen_andc_tl(t1, t1, t2);
5072 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5073 tcg_temp_free(t0);
5074 tcg_temp_free(t1);
5075 tcg_temp_free(t2);
5076 if (unlikely(Rc(ctx->opcode) != 0))
5077 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5078 }
5079
5080 /* sliq - sliq. */
5081 static void gen_sliq(DisasContext *ctx)
5082 {
5083 int sh = SH(ctx->opcode);
5084 TCGv t0 = tcg_temp_new();
5085 TCGv t1 = tcg_temp_new();
5086 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5087 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5088 tcg_gen_or_tl(t1, t0, t1);
5089 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5090 gen_store_spr(SPR_MQ, t1);
5091 tcg_temp_free(t0);
5092 tcg_temp_free(t1);
5093 if (unlikely(Rc(ctx->opcode) != 0))
5094 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5095 }
5096
5097 /* slliq - slliq. */
5098 static void gen_slliq(DisasContext *ctx)
5099 {
5100 int sh = SH(ctx->opcode);
5101 TCGv t0 = tcg_temp_new();
5102 TCGv t1 = tcg_temp_new();
5103 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5104 gen_load_spr(t1, SPR_MQ);
5105 gen_store_spr(SPR_MQ, t0);
5106 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5107 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5108 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5109 tcg_temp_free(t0);
5110 tcg_temp_free(t1);
5111 if (unlikely(Rc(ctx->opcode) != 0))
5112 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5113 }
5114
5115 /* sllq - sllq. */
5116 static void gen_sllq(DisasContext *ctx)
5117 {
5118 int l1 = gen_new_label();
5119 int l2 = gen_new_label();
5120 TCGv t0 = tcg_temp_local_new();
5121 TCGv t1 = tcg_temp_local_new();
5122 TCGv t2 = tcg_temp_local_new();
5123 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5124 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5125 tcg_gen_shl_tl(t1, t1, t2);
5126 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5127 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5128 gen_load_spr(t0, SPR_MQ);
5129 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5130 tcg_gen_br(l2);
5131 gen_set_label(l1);
5132 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5133 gen_load_spr(t2, SPR_MQ);
5134 tcg_gen_andc_tl(t1, t2, t1);
5135 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5136 gen_set_label(l2);
5137 tcg_temp_free(t0);
5138 tcg_temp_free(t1);
5139 tcg_temp_free(t2);
5140 if (unlikely(Rc(ctx->opcode) != 0))
5141 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5142 }
5143
5144 /* slq - slq. */
5145 static void gen_slq(DisasContext *ctx)
5146 {
5147 int l1 = gen_new_label();
5148 TCGv t0 = tcg_temp_new();
5149 TCGv t1 = tcg_temp_new();
5150 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5151 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5152 tcg_gen_subfi_tl(t1, 32, t1);
5153 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5154 tcg_gen_or_tl(t1, t0, t1);
5155 gen_store_spr(SPR_MQ, t1);
5156 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5157 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5158 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5159 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5160 gen_set_label(l1);
5161 tcg_temp_free(t0);
5162 tcg_temp_free(t1);
5163 if (unlikely(Rc(ctx->opcode) != 0))
5164 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5165 }
5166
5167 /* sraiq - sraiq. */
5168 static void gen_sraiq(DisasContext *ctx)
5169 {
5170 int sh = SH(ctx->opcode);
5171 int l1 = gen_new_label();
5172 TCGv t0 = tcg_temp_new();
5173 TCGv t1 = tcg_temp_new();
5174 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5175 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5176 tcg_gen_or_tl(t0, t0, t1);
5177 gen_store_spr(SPR_MQ, t0);
5178 tcg_gen_movi_tl(cpu_ca, 0);
5179 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5180 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5181 tcg_gen_movi_tl(cpu_ca, 1);
5182 gen_set_label(l1);
5183 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5184 tcg_temp_free(t0);
5185 tcg_temp_free(t1);
5186 if (unlikely(Rc(ctx->opcode) != 0))
5187 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5188 }
5189
5190 /* sraq - sraq. */
5191 static void gen_sraq(DisasContext *ctx)
5192 {
5193 int l1 = gen_new_label();
5194 int l2 = gen_new_label();
5195 TCGv t0 = tcg_temp_new();
5196 TCGv t1 = tcg_temp_local_new();
5197 TCGv t2 = tcg_temp_local_new();
5198 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5199 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5200 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5201 tcg_gen_subfi_tl(t2, 32, t2);
5202 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5203 tcg_gen_or_tl(t0, t0, t2);
5204 gen_store_spr(SPR_MQ, t0);
5205 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5206 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5207 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5208 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5209 gen_set_label(l1);
5210 tcg_temp_free(t0);
5211 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5212 tcg_gen_movi_tl(cpu_ca, 0);
5213 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5214 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5215 tcg_gen_movi_tl(cpu_ca, 1);
5216 gen_set_label(l2);
5217 tcg_temp_free(t1);
5218 tcg_temp_free(t2);
5219 if (unlikely(Rc(ctx->opcode) != 0))
5220 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5221 }
5222
5223 /* sre - sre. */
5224 static void gen_sre(DisasContext *ctx)
5225 {
5226 TCGv t0 = tcg_temp_new();
5227 TCGv t1 = tcg_temp_new();
5228 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5229 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5230 tcg_gen_subfi_tl(t1, 32, t1);
5231 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5232 tcg_gen_or_tl(t1, t0, t1);
5233 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5234 gen_store_spr(SPR_MQ, t1);
5235 tcg_temp_free(t0);
5236 tcg_temp_free(t1);
5237 if (unlikely(Rc(ctx->opcode) != 0))
5238 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5239 }
5240
5241 /* srea - srea. */
5242 static void gen_srea(DisasContext *ctx)
5243 {
5244 TCGv t0 = tcg_temp_new();
5245 TCGv t1 = tcg_temp_new();
5246 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5247 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5248 gen_store_spr(SPR_MQ, t0);
5249 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5250 tcg_temp_free(t0);
5251 tcg_temp_free(t1);
5252 if (unlikely(Rc(ctx->opcode) != 0))
5253 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5254 }
5255
5256 /* sreq */
5257 static void gen_sreq(DisasContext *ctx)
5258 {
5259 TCGv t0 = tcg_temp_new();
5260 TCGv t1 = tcg_temp_new();
5261 TCGv t2 = tcg_temp_new();
5262 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5263 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5264 tcg_gen_shr_tl(t1, t1, t0);
5265 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5266 gen_load_spr(t2, SPR_MQ);
5267 gen_store_spr(SPR_MQ, t0);
5268 tcg_gen_and_tl(t0, t0, t1);
5269 tcg_gen_andc_tl(t2, t2, t1);
5270 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5271 tcg_temp_free(t0);
5272 tcg_temp_free(t1);
5273 tcg_temp_free(t2);
5274 if (unlikely(Rc(ctx->opcode) != 0))
5275 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5276 }
5277
5278 /* sriq */
5279 static void gen_sriq(DisasContext *ctx)
5280 {
5281 int sh = SH(ctx->opcode);
5282 TCGv t0 = tcg_temp_new();
5283 TCGv t1 = tcg_temp_new();
5284 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5285 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5286 tcg_gen_or_tl(t1, t0, t1);
5287 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5288 gen_store_spr(SPR_MQ, t1);
5289 tcg_temp_free(t0);
5290 tcg_temp_free(t1);
5291 if (unlikely(Rc(ctx->opcode) != 0))
5292 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5293 }
5294
5295 /* srliq */
5296 static void gen_srliq(DisasContext *ctx)
5297 {
5298 int sh = SH(ctx->opcode);
5299 TCGv t0 = tcg_temp_new();
5300 TCGv t1 = tcg_temp_new();
5301 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5302 gen_load_spr(t1, SPR_MQ);
5303 gen_store_spr(SPR_MQ, t0);
5304 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5305 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5306 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5307 tcg_temp_free(t0);
5308 tcg_temp_free(t1);
5309 if (unlikely(Rc(ctx->opcode) != 0))
5310 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5311 }
5312
5313 /* srlq */
5314 static void gen_srlq(DisasContext *ctx)
5315 {
5316 int l1 = gen_new_label();
5317 int l2 = gen_new_label();
5318 TCGv t0 = tcg_temp_local_new();
5319 TCGv t1 = tcg_temp_local_new();
5320 TCGv t2 = tcg_temp_local_new();
5321 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5322 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5323 tcg_gen_shr_tl(t2, t1, t2);
5324 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5325 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5326 gen_load_spr(t0, SPR_MQ);
5327 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5328 tcg_gen_br(l2);
5329 gen_set_label(l1);
5330 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5331 tcg_gen_and_tl(t0, t0, t2);
5332 gen_load_spr(t1, SPR_MQ);
5333 tcg_gen_andc_tl(t1, t1, t2);
5334 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5335 gen_set_label(l2);
5336 tcg_temp_free(t0);
5337 tcg_temp_free(t1);
5338 tcg_temp_free(t2);
5339 if (unlikely(Rc(ctx->opcode) != 0))
5340 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5341 }
5342
5343 /* srq */
5344 static void gen_srq(DisasContext *ctx)
5345 {
5346 int l1 = gen_new_label();
5347 TCGv t0 = tcg_temp_new();
5348 TCGv t1 = tcg_temp_new();
5349 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5350 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5351 tcg_gen_subfi_tl(t1, 32, t1);
5352 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5353 tcg_gen_or_tl(t1, t0, t1);
5354 gen_store_spr(SPR_MQ, t1);
5355 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5356 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5357 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5358 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5359 gen_set_label(l1);
5360 tcg_temp_free(t0);
5361 tcg_temp_free(t1);
5362 if (unlikely(Rc(ctx->opcode) != 0))
5363 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5364 }
5365
5366 /* PowerPC 602 specific instructions */
5367
5368 /* dsa */
5369 static void gen_dsa(DisasContext *ctx)
5370 {
5371 /* XXX: TODO */
5372 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5373 }
5374
5375 /* esa */
5376 static void gen_esa(DisasContext *ctx)
5377 {
5378 /* XXX: TODO */
5379 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5380 }
5381
5382 /* mfrom */
5383 static void gen_mfrom(DisasContext *ctx)
5384 {
5385 #if defined(CONFIG_USER_ONLY)
5386 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5387 #else
5388 if (unlikely(!ctx->mem_idx)) {
5389 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5390 return;
5391 }
5392 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5393 #endif
5394 }
5395
5396 /* 602 - 603 - G2 TLB management */
5397
5398 /* tlbld */
5399 static void gen_tlbld_6xx(DisasContext *ctx)
5400 {
5401 #if defined(CONFIG_USER_ONLY)
5402 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5403 #else
5404 if (unlikely(!ctx->mem_idx)) {
5405 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5406 return;
5407 }
5408 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5409 #endif
5410 }
5411
5412 /* tlbli */
5413 static void gen_tlbli_6xx(DisasContext *ctx)
5414 {
5415 #if defined(CONFIG_USER_ONLY)
5416 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5417 #else
5418 if (unlikely(!ctx->mem_idx)) {
5419 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5420 return;
5421 }
5422 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5423 #endif
5424 }
5425
5426 /* 74xx TLB management */
5427
5428 /* tlbld */
5429 static void gen_tlbld_74xx(DisasContext *ctx)
5430 {
5431 #if defined(CONFIG_USER_ONLY)
5432 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5433 #else
5434 if (unlikely(!ctx->mem_idx)) {
5435 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5436 return;
5437 }
5438 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5439 #endif
5440 }
5441
5442 /* tlbli */
5443 static void gen_tlbli_74xx(DisasContext *ctx)
5444 {
5445 #if defined(CONFIG_USER_ONLY)
5446 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5447 #else
5448 if (unlikely(!ctx->mem_idx)) {
5449 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5450 return;
5451 }
5452 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5453 #endif
5454 }
5455
5456 /* POWER instructions not in PowerPC 601 */
5457
5458 /* clf */
5459 static void gen_clf(DisasContext *ctx)
5460 {
5461 /* Cache line flush: implemented as no-op */
5462 }
5463
5464 /* cli */
5465 static void gen_cli(DisasContext *ctx)
5466 {
5467 /* Cache line invalidate: privileged and treated as no-op */
5468 #if defined(CONFIG_USER_ONLY)
5469 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5470 #else
5471 if (unlikely(!ctx->mem_idx)) {
5472 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5473 return;
5474 }
5475 #endif
5476 }
5477
5478 /* dclst */
5479 static void gen_dclst(DisasContext *ctx)
5480 {
5481 /* Data cache line store: treated as no-op */
5482 }
5483
5484 static void gen_mfsri(DisasContext *ctx)
5485 {
5486 #if defined(CONFIG_USER_ONLY)
5487 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5488 #else
5489 int ra = rA(ctx->opcode);
5490 int rd = rD(ctx->opcode);
5491 TCGv t0;
5492 if (unlikely(!ctx->mem_idx)) {
5493 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5494 return;
5495 }
5496 t0 = tcg_temp_new();
5497 gen_addr_reg_index(ctx, t0);
5498 tcg_gen_shri_tl(t0, t0, 28);
5499 tcg_gen_andi_tl(t0, t0, 0xF);
5500 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5501 tcg_temp_free(t0);
5502 if (ra != 0 && ra != rd)
5503 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5504 #endif
5505 }
5506
5507 static void gen_rac(DisasContext *ctx)
5508 {
5509 #if defined(CONFIG_USER_ONLY)
5510 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5511 #else
5512 TCGv t0;
5513 if (unlikely(!ctx->mem_idx)) {
5514 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5515 return;
5516 }
5517 t0 = tcg_temp_new();
5518 gen_addr_reg_index(ctx, t0);
5519 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5520 tcg_temp_free(t0);
5521 #endif
5522 }
5523
5524 static void gen_rfsvc(DisasContext *ctx)
5525 {
5526 #if defined(CONFIG_USER_ONLY)
5527 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5528 #else
5529 if (unlikely(!ctx->mem_idx)) {
5530 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5531 return;
5532 }
5533 gen_helper_rfsvc(cpu_env);
5534 gen_sync_exception(ctx);
5535 #endif
5536 }
5537
5538 /* svc is not implemented for now */
5539
5540 /* POWER2 specific instructions */
5541 /* Quad manipulation (load/store two floats at a time) */
5542
5543 /* lfq */
5544 static void gen_lfq(DisasContext *ctx)
5545 {
5546 int rd = rD(ctx->opcode);
5547 TCGv t0;
5548 gen_set_access_type(ctx, ACCESS_FLOAT);
5549 t0 = tcg_temp_new();
5550 gen_addr_imm_index(ctx, t0, 0);
5551 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5552 gen_addr_add(ctx, t0, t0, 8);
5553 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5554 tcg_temp_free(t0);
5555 }
5556
5557 /* lfqu */
5558 static void gen_lfqu(DisasContext *ctx)
5559 {
5560 int ra = rA(ctx->opcode);
5561 int rd = rD(ctx->opcode);
5562 TCGv t0, t1;
5563 gen_set_access_type(ctx, ACCESS_FLOAT);
5564 t0 = tcg_temp_new();
5565 t1 = tcg_temp_new();
5566 gen_addr_imm_index(ctx, t0, 0);
5567 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5568 gen_addr_add(ctx, t1, t0, 8);
5569 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5570 if (ra != 0)
5571 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5572 tcg_temp_free(t0);
5573 tcg_temp_free(t1);
5574 }
5575
5576 /* lfqux */
5577 static void gen_lfqux(DisasContext *ctx)
5578 {
5579 int ra = rA(ctx->opcode);
5580 int rd = rD(ctx->opcode);
5581 gen_set_access_type(ctx, ACCESS_FLOAT);
5582 TCGv t0, t1;
5583 t0 = tcg_temp_new();
5584 gen_addr_reg_index(ctx, t0);
5585 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5586 t1 = tcg_temp_new();
5587 gen_addr_add(ctx, t1, t0, 8);
5588 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5589 tcg_temp_free(t1);
5590 if (ra != 0)
5591 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5592 tcg_temp_free(t0);
5593 }
5594
5595 /* lfqx */
5596 static void gen_lfqx(DisasContext *ctx)
5597 {
5598 int rd = rD(ctx->opcode);
5599 TCGv t0;
5600 gen_set_access_type(ctx, ACCESS_FLOAT);
5601 t0 = tcg_temp_new();
5602 gen_addr_reg_index(ctx, t0);
5603 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5604 gen_addr_add(ctx, t0, t0, 8);
5605 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5606 tcg_temp_free(t0);
5607 }
5608
5609 /* stfq */
5610 static void gen_stfq(DisasContext *ctx)
5611 {
5612 int rd = rD(ctx->opcode);
5613 TCGv t0;
5614 gen_set_access_type(ctx, ACCESS_FLOAT);
5615 t0 = tcg_temp_new();
5616 gen_addr_imm_index(ctx, t0, 0);
5617 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5618 gen_addr_add(ctx, t0, t0, 8);
5619 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5620 tcg_temp_free(t0);
5621 }
5622
5623 /* stfqu */
5624 static void gen_stfqu(DisasContext *ctx)
5625 {
5626 int ra = rA(ctx->opcode);
5627 int rd = rD(ctx->opcode);
5628 TCGv t0, t1;
5629 gen_set_access_type(ctx, ACCESS_FLOAT);
5630 t0 = tcg_temp_new();
5631 gen_addr_imm_index(ctx, t0, 0);
5632 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5633 t1 = tcg_temp_new();
5634 gen_addr_add(ctx, t1, t0, 8);
5635 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5636 tcg_temp_free(t1);
5637 if (ra != 0)
5638 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5639 tcg_temp_free(t0);
5640 }
5641
5642 /* stfqux */
5643 static void gen_stfqux(DisasContext *ctx)
5644 {
5645 int ra = rA(ctx->opcode);
5646 int rd = rD(ctx->opcode);
5647 TCGv t0, t1;
5648 gen_set_access_type(ctx, ACCESS_FLOAT);
5649 t0 = tcg_temp_new();
5650 gen_addr_reg_index(ctx, t0);
5651 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5652 t1 = tcg_temp_new();
5653 gen_addr_add(ctx, t1, t0, 8);
5654 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5655 tcg_temp_free(t1);
5656 if (ra != 0)
5657 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5658 tcg_temp_free(t0);
5659 }
5660
5661 /* stfqx */
5662 static void gen_stfqx(DisasContext *ctx)
5663 {
5664 int rd = rD(ctx->opcode);
5665 TCGv t0;
5666 gen_set_access_type(ctx, ACCESS_FLOAT);
5667 t0 = tcg_temp_new();
5668 gen_addr_reg_index(ctx, t0);
5669 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5670 gen_addr_add(ctx, t0, t0, 8);
5671 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5672 tcg_temp_free(t0);
5673 }
5674
5675 /* BookE specific instructions */
5676
5677 /* XXX: not implemented on 440 ? */
5678 static void gen_mfapidi(DisasContext *ctx)
5679 {
5680 /* XXX: TODO */
5681 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5682 }
5683
5684 /* XXX: not implemented on 440 ? */
5685 static void gen_tlbiva(DisasContext *ctx)
5686 {
5687 #if defined(CONFIG_USER_ONLY)
5688 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5689 #else
5690 TCGv t0;
5691 if (unlikely(!ctx->mem_idx)) {
5692 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5693 return;
5694 }
5695 t0 = tcg_temp_new();
5696 gen_addr_reg_index(ctx, t0);
5697 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5698 tcg_temp_free(t0);
5699 #endif
5700 }
5701
5702 /* All 405 MAC instructions are translated here */
5703 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5704 int ra, int rb, int rt, int Rc)
5705 {
5706 TCGv t0, t1;
5707
5708 t0 = tcg_temp_local_new();
5709 t1 = tcg_temp_local_new();
5710
5711 switch (opc3 & 0x0D) {
5712 case 0x05:
5713 /* macchw - macchw. - macchwo - macchwo. */
5714 /* macchws - macchws. - macchwso - macchwso. */
5715 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5716 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5717 /* mulchw - mulchw. */
5718 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5719 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5720 tcg_gen_ext16s_tl(t1, t1);
5721 break;
5722 case 0x04:
5723 /* macchwu - macchwu. - macchwuo - macchwuo. */
5724 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5725 /* mulchwu - mulchwu. */
5726 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5727 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5728 tcg_gen_ext16u_tl(t1, t1);
5729 break;
5730 case 0x01:
5731 /* machhw - machhw. - machhwo - machhwo. */
5732 /* machhws - machhws. - machhwso - machhwso. */
5733 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5734 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5735 /* mulhhw - mulhhw. */
5736 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5737 tcg_gen_ext16s_tl(t0, t0);
5738 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5739 tcg_gen_ext16s_tl(t1, t1);
5740 break;
5741 case 0x00:
5742 /* machhwu - machhwu. - machhwuo - machhwuo. */
5743 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5744 /* mulhhwu - mulhhwu. */
5745 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5746 tcg_gen_ext16u_tl(t0, t0);
5747 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5748 tcg_gen_ext16u_tl(t1, t1);
5749 break;
5750 case 0x0D:
5751 /* maclhw - maclhw. - maclhwo - maclhwo. */
5752 /* maclhws - maclhws. - maclhwso - maclhwso. */
5753 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5754 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5755 /* mullhw - mullhw. */
5756 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5757 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5758 break;
5759 case 0x0C:
5760 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5761 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5762 /* mullhwu - mullhwu. */
5763 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5764 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5765 break;
5766 }
5767 if (opc2 & 0x04) {
5768 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5769 tcg_gen_mul_tl(t1, t0, t1);
5770 if (opc2 & 0x02) {
5771 /* nmultiply-and-accumulate (0x0E) */
5772 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5773 } else {
5774 /* multiply-and-accumulate (0x0C) */
5775 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5776 }
5777
5778 if (opc3 & 0x12) {
5779 /* Check overflow and/or saturate */
5780 int l1 = gen_new_label();
5781
5782 if (opc3 & 0x10) {
5783 /* Start with XER OV disabled, the most likely case */
5784 tcg_gen_movi_tl(cpu_ov, 0);
5785 }
5786 if (opc3 & 0x01) {
5787 /* Signed */
5788 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5789 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5790 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5791 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5792 if (opc3 & 0x02) {
5793 /* Saturate */
5794 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5795 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5796 }
5797 } else {
5798 /* Unsigned */
5799 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5800 if (opc3 & 0x02) {
5801 /* Saturate */
5802 tcg_gen_movi_tl(t0, UINT32_MAX);
5803 }
5804 }
5805 if (opc3 & 0x10) {
5806 /* Check overflow */
5807 tcg_gen_movi_tl(cpu_ov, 1);
5808 tcg_gen_movi_tl(cpu_so, 1);
5809 }
5810 gen_set_label(l1);
5811 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5812 }
5813 } else {
5814 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5815 }
5816 tcg_temp_free(t0);
5817 tcg_temp_free(t1);
5818 if (unlikely(Rc) != 0) {
5819 /* Update Rc0 */
5820 gen_set_Rc0(ctx, cpu_gpr[rt]);
5821 }
5822 }
5823
5824 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5825 static void glue(gen_, name)(DisasContext *ctx) \
5826 { \
5827 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5828 rD(ctx->opcode), Rc(ctx->opcode)); \
5829 }
5830
5831 /* macchw - macchw. */
5832 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5833 /* macchwo - macchwo. */
5834 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5835 /* macchws - macchws. */
5836 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5837 /* macchwso - macchwso. */
5838 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5839 /* macchwsu - macchwsu. */
5840 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5841 /* macchwsuo - macchwsuo. */
5842 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5843 /* macchwu - macchwu. */
5844 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5845 /* macchwuo - macchwuo. */
5846 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5847 /* machhw - machhw. */
5848 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5849 /* machhwo - machhwo. */
5850 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5851 /* machhws - machhws. */
5852 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5853 /* machhwso - machhwso. */
5854 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5855 /* machhwsu - machhwsu. */
5856 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5857 /* machhwsuo - machhwsuo. */
5858 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5859 /* machhwu - machhwu. */
5860 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5861 /* machhwuo - machhwuo. */
5862 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5863 /* maclhw - maclhw. */
5864 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5865 /* maclhwo - maclhwo. */
5866 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5867 /* maclhws - maclhws. */
5868 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5869 /* maclhwso - maclhwso. */
5870 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5871 /* maclhwu - maclhwu. */
5872 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5873 /* maclhwuo - maclhwuo. */
5874 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5875 /* maclhwsu - maclhwsu. */
5876 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5877 /* maclhwsuo - maclhwsuo. */
5878 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5879 /* nmacchw - nmacchw. */
5880 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5881 /* nmacchwo - nmacchwo. */
5882 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5883 /* nmacchws - nmacchws. */
5884 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5885 /* nmacchwso - nmacchwso. */
5886 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5887 /* nmachhw - nmachhw. */
5888 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5889 /* nmachhwo - nmachhwo. */
5890 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5891 /* nmachhws - nmachhws. */
5892 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5893 /* nmachhwso - nmachhwso. */
5894 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5895 /* nmaclhw - nmaclhw. */
5896 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5897 /* nmaclhwo - nmaclhwo. */
5898 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5899 /* nmaclhws - nmaclhws. */
5900 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5901 /* nmaclhwso - nmaclhwso. */
5902 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5903
5904 /* mulchw - mulchw. */
5905 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5906 /* mulchwu - mulchwu. */
5907 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5908 /* mulhhw - mulhhw. */
5909 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5910 /* mulhhwu - mulhhwu. */
5911 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5912 /* mullhw - mullhw. */
5913 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5914 /* mullhwu - mullhwu. */
5915 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5916
5917 /* mfdcr */
5918 static void gen_mfdcr(DisasContext *ctx)
5919 {
5920 #if defined(CONFIG_USER_ONLY)
5921 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5922 #else
5923 TCGv dcrn;
5924 if (unlikely(!ctx->mem_idx)) {
5925 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5926 return;
5927 }
5928 /* NIP cannot be restored if the memory exception comes from an helper */
5929 gen_update_nip(ctx, ctx->nip - 4);
5930 dcrn = tcg_const_tl(SPR(ctx->opcode));
5931 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5932 tcg_temp_free(dcrn);
5933 #endif
5934 }
5935
5936 /* mtdcr */
5937 static void gen_mtdcr(DisasContext *ctx)
5938 {
5939 #if defined(CONFIG_USER_ONLY)
5940 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5941 #else
5942 TCGv dcrn;
5943 if (unlikely(!ctx->mem_idx)) {
5944 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5945 return;
5946 }
5947 /* NIP cannot be restored if the memory exception comes from an helper */
5948 gen_update_nip(ctx, ctx->nip - 4);
5949 dcrn = tcg_const_tl(SPR(ctx->opcode));
5950 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5951 tcg_temp_free(dcrn);
5952 #endif
5953 }
5954
5955 /* mfdcrx */
5956 /* XXX: not implemented on 440 ? */
5957 static void gen_mfdcrx(DisasContext *ctx)
5958 {
5959 #if defined(CONFIG_USER_ONLY)
5960 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5961 #else
5962 if (unlikely(!ctx->mem_idx)) {
5963 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5964 return;
5965 }
5966 /* NIP cannot be restored if the memory exception comes from an helper */
5967 gen_update_nip(ctx, ctx->nip - 4);
5968 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5969 cpu_gpr[rA(ctx->opcode)]);
5970 /* Note: Rc update flag set leads to undefined state of Rc0 */
5971 #endif
5972 }
5973
5974 /* mtdcrx */
5975 /* XXX: not implemented on 440 ? */
5976 static void gen_mtdcrx(DisasContext *ctx)
5977 {
5978 #if defined(CONFIG_USER_ONLY)
5979 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5980 #else
5981 if (unlikely(!ctx->mem_idx)) {
5982 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5983 return;
5984 }
5985 /* NIP cannot be restored if the memory exception comes from an helper */
5986 gen_update_nip(ctx, ctx->nip - 4);
5987 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5988 cpu_gpr[rS(ctx->opcode)]);
5989 /* Note: Rc update flag set leads to undefined state of Rc0 */
5990 #endif
5991 }
5992
5993 /* mfdcrux (PPC 460) : user-mode access to DCR */
5994 static void gen_mfdcrux(DisasContext *ctx)
5995 {
5996 /* NIP cannot be restored if the memory exception comes from an helper */
5997 gen_update_nip(ctx, ctx->nip - 4);
5998 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5999 cpu_gpr[rA(ctx->opcode)]);
6000 /* Note: Rc update flag set leads to undefined state of Rc0 */
6001 }
6002
6003 /* mtdcrux (PPC 460) : user-mode access to DCR */
6004 static void gen_mtdcrux(DisasContext *ctx)
6005 {
6006 /* NIP cannot be restored if the memory exception comes from an helper */
6007 gen_update_nip(ctx, ctx->nip - 4);
6008 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6009 cpu_gpr[rS(ctx->opcode)]);
6010 /* Note: Rc update flag set leads to undefined state of Rc0 */
6011 }
6012
6013 /* dccci */
6014 static void gen_dccci(DisasContext *ctx)
6015 {
6016 #if defined(CONFIG_USER_ONLY)
6017 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6018 #else
6019 if (unlikely(!ctx->mem_idx)) {
6020 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6021 return;
6022 }
6023 /* interpreted as no-op */
6024 #endif
6025 }
6026
6027 /* dcread */
6028 static void gen_dcread(DisasContext *ctx)
6029 {
6030 #if defined(CONFIG_USER_ONLY)
6031 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6032 #else
6033 TCGv EA, val;
6034 if (unlikely(!ctx->mem_idx)) {
6035 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6036 return;
6037 }
6038 gen_set_access_type(ctx, ACCESS_CACHE);
6039 EA = tcg_temp_new();
6040 gen_addr_reg_index(ctx, EA);
6041 val = tcg_temp_new();
6042 gen_qemu_ld32u(ctx, val, EA);
6043 tcg_temp_free(val);
6044 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6045 tcg_temp_free(EA);
6046 #endif
6047 }
6048
6049 /* icbt */
6050 static void gen_icbt_40x(DisasContext *ctx)
6051 {
6052 /* interpreted as no-op */
6053 /* XXX: specification say this is treated as a load by the MMU
6054 * but does not generate any exception
6055 */
6056 }
6057
6058 /* iccci */
6059 static void gen_iccci(DisasContext *ctx)
6060 {
6061 #if defined(CONFIG_USER_ONLY)
6062 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6063 #else
6064 if (unlikely(!ctx->mem_idx)) {
6065 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6066 return;
6067 }
6068 /* interpreted as no-op */
6069 #endif
6070 }
6071
6072 /* icread */
6073 static void gen_icread(DisasContext *ctx)
6074 {
6075 #if defined(CONFIG_USER_ONLY)
6076 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6077 #else
6078 if (unlikely(!ctx->mem_idx)) {
6079 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6080 return;
6081 }
6082 /* interpreted as no-op */
6083 #endif
6084 }
6085
6086 /* rfci (mem_idx only) */
6087 static void gen_rfci_40x(DisasContext *ctx)
6088 {
6089 #if defined(CONFIG_USER_ONLY)
6090 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6091 #else
6092 if (unlikely(!ctx->mem_idx)) {
6093 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6094 return;
6095 }
6096 /* Restore CPU state */
6097 gen_helper_40x_rfci(cpu_env);
6098 gen_sync_exception(ctx);
6099 #endif
6100 }
6101
6102 static void gen_rfci(DisasContext *ctx)
6103 {
6104 #if defined(CONFIG_USER_ONLY)
6105 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6106 #else
6107 if (unlikely(!ctx->mem_idx)) {
6108 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6109 return;
6110 }
6111 /* Restore CPU state */
6112 gen_helper_rfci(cpu_env);
6113 gen_sync_exception(ctx);
6114 #endif
6115 }
6116
6117 /* BookE specific */
6118
6119 /* XXX: not implemented on 440 ? */
6120 static void gen_rfdi(DisasContext *ctx)
6121 {
6122 #if defined(CONFIG_USER_ONLY)
6123 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6124 #else
6125 if (unlikely(!ctx->mem_idx)) {
6126 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6127 return;
6128 }
6129 /* Restore CPU state */
6130 gen_helper_rfdi(cpu_env);
6131 gen_sync_exception(ctx);
6132 #endif
6133 }
6134
6135 /* XXX: not implemented on 440 ? */
6136 static void gen_rfmci(DisasContext *ctx)
6137 {
6138 #if defined(CONFIG_USER_ONLY)
6139 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6140 #else
6141 if (unlikely(!ctx->mem_idx)) {
6142 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6143 return;
6144 }
6145 /* Restore CPU state */
6146 gen_helper_rfmci(cpu_env);
6147 gen_sync_exception(ctx);
6148 #endif
6149 }
6150
6151 /* TLB management - PowerPC 405 implementation */
6152
6153 /* tlbre */
6154 static void gen_tlbre_40x(DisasContext *ctx)
6155 {
6156 #if defined(CONFIG_USER_ONLY)
6157 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6158 #else
6159 if (unlikely(!ctx->mem_idx)) {
6160 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6161 return;
6162 }
6163 switch (rB(ctx->opcode)) {
6164 case 0:
6165 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6166 cpu_gpr[rA(ctx->opcode)]);
6167 break;
6168 case 1:
6169 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6170 cpu_gpr[rA(ctx->opcode)]);
6171 break;
6172 default:
6173 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6174 break;
6175 }
6176 #endif
6177 }
6178
6179 /* tlbsx - tlbsx. */
6180 static void gen_tlbsx_40x(DisasContext *ctx)
6181 {
6182 #if defined(CONFIG_USER_ONLY)
6183 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6184 #else
6185 TCGv t0;
6186 if (unlikely(!ctx->mem_idx)) {
6187 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6188 return;
6189 }
6190 t0 = tcg_temp_new();
6191 gen_addr_reg_index(ctx, t0);
6192 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6193 tcg_temp_free(t0);
6194 if (Rc(ctx->opcode)) {
6195 int l1 = gen_new_label();
6196 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6197 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6198 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6199 gen_set_label(l1);
6200 }
6201 #endif
6202 }
6203
6204 /* tlbwe */
6205 static void gen_tlbwe_40x(DisasContext *ctx)
6206 {
6207 #if defined(CONFIG_USER_ONLY)
6208 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6209 #else
6210 if (unlikely(!ctx->mem_idx)) {
6211 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6212 return;
6213 }
6214 switch (rB(ctx->opcode)) {
6215 case 0:
6216 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6217 cpu_gpr[rS(ctx->opcode)]);
6218 break;
6219 case 1:
6220 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6221 cpu_gpr[rS(ctx->opcode)]);
6222 break;
6223 default:
6224 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6225 break;
6226 }
6227 #endif
6228 }
6229
6230 /* TLB management - PowerPC 440 implementation */
6231
6232 /* tlbre */
6233 static void gen_tlbre_440(DisasContext *ctx)
6234 {
6235 #if defined(CONFIG_USER_ONLY)
6236 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6237 #else
6238 if (unlikely(!ctx->mem_idx)) {
6239 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6240 return;
6241 }
6242 switch (rB(ctx->opcode)) {
6243 case 0:
6244 case 1:
6245 case 2:
6246 {
6247 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6248 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6249 t0, cpu_gpr[rA(ctx->opcode)]);
6250 tcg_temp_free_i32(t0);
6251 }
6252 break;
6253 default:
6254 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6255 break;
6256 }
6257 #endif
6258 }
6259
6260 /* tlbsx - tlbsx. */
6261 static void gen_tlbsx_440(DisasContext *ctx)
6262 {
6263 #if defined(CONFIG_USER_ONLY)
6264 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6265 #else
6266 TCGv t0;
6267 if (unlikely(!ctx->mem_idx)) {
6268 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6269 return;
6270 }
6271 t0 = tcg_temp_new();
6272 gen_addr_reg_index(ctx, t0);
6273 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6274 tcg_temp_free(t0);
6275 if (Rc(ctx->opcode)) {
6276 int l1 = gen_new_label();
6277 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6278 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6279 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6280 gen_set_label(l1);
6281 }
6282 #endif
6283 }
6284
6285 /* tlbwe */
6286 static void gen_tlbwe_440(DisasContext *ctx)
6287 {
6288 #if defined(CONFIG_USER_ONLY)
6289 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6290 #else
6291 if (unlikely(!ctx->mem_idx)) {
6292 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6293 return;
6294 }
6295 switch (rB(ctx->opcode)) {
6296 case 0:
6297 case 1:
6298 case 2:
6299 {
6300 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6301 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6302 cpu_gpr[rS(ctx->opcode)]);
6303 tcg_temp_free_i32(t0);
6304 }
6305 break;
6306 default:
6307 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6308 break;
6309 }
6310 #endif
6311 }
6312
6313 /* TLB management - PowerPC BookE 2.06 implementation */
6314
6315 /* tlbre */
6316 static void gen_tlbre_booke206(DisasContext *ctx)
6317 {
6318 #if defined(CONFIG_USER_ONLY)
6319 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6320 #else
6321 if (unlikely(!ctx->mem_idx)) {
6322 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6323 return;
6324 }
6325
6326 gen_helper_booke206_tlbre(cpu_env);
6327 #endif
6328 }
6329
6330 /* tlbsx - tlbsx. */
6331 static void gen_tlbsx_booke206(DisasContext *ctx)
6332 {
6333 #if defined(CONFIG_USER_ONLY)
6334 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6335 #else
6336 TCGv t0;
6337 if (unlikely(!ctx->mem_idx)) {
6338 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6339 return;
6340 }
6341
6342 if (rA(ctx->opcode)) {
6343 t0 = tcg_temp_new();
6344 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6345 } else {
6346 t0 = tcg_const_tl(0);
6347 }
6348
6349 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6350 gen_helper_booke206_tlbsx(cpu_env, t0);
6351 #endif
6352 }
6353
6354 /* tlbwe */
6355 static void gen_tlbwe_booke206(DisasContext *ctx)
6356 {
6357 #if defined(CONFIG_USER_ONLY)
6358 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6359 #else
6360 if (unlikely(!ctx->mem_idx)) {
6361 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6362 return;
6363 }
6364 gen_update_nip(ctx, ctx->nip - 4);
6365 gen_helper_booke206_tlbwe(cpu_env);
6366 #endif
6367 }
6368
6369 static void gen_tlbivax_booke206(DisasContext *ctx)
6370 {
6371 #if defined(CONFIG_USER_ONLY)
6372 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6373 #else
6374 TCGv t0;
6375 if (unlikely(!ctx->mem_idx)) {
6376 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6377 return;
6378 }
6379
6380 t0 = tcg_temp_new();
6381 gen_addr_reg_index(ctx, t0);
6382
6383 gen_helper_booke206_tlbivax(cpu_env, t0);
6384 #endif
6385 }
6386
6387 static void gen_tlbilx_booke206(DisasContext *ctx)
6388 {
6389 #if defined(CONFIG_USER_ONLY)
6390 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6391 #else
6392 TCGv t0;
6393 if (unlikely(!ctx->mem_idx)) {
6394 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6395 return;
6396 }
6397
6398 t0 = tcg_temp_new();
6399 gen_addr_reg_index(ctx, t0);
6400
6401 switch((ctx->opcode >> 21) & 0x3) {
6402 case 0:
6403 gen_helper_booke206_tlbilx0(cpu_env, t0);
6404 break;
6405 case 1:
6406 gen_helper_booke206_tlbilx1(cpu_env, t0);
6407 break;
6408 case 3:
6409 gen_helper_booke206_tlbilx3(cpu_env, t0);
6410 break;
6411 default:
6412 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6413 break;
6414 }
6415
6416 tcg_temp_free(t0);
6417 #endif
6418 }
6419
6420
6421 /* wrtee */
6422 static void gen_wrtee(DisasContext *ctx)
6423 {
6424 #if defined(CONFIG_USER_ONLY)
6425 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6426 #else
6427 TCGv t0;
6428 if (unlikely(!ctx->mem_idx)) {
6429 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6430 return;
6431 }
6432 t0 = tcg_temp_new();
6433 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6434 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6435 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6436 tcg_temp_free(t0);
6437 /* Stop translation to have a chance to raise an exception
6438 * if we just set msr_ee to 1
6439 */
6440 gen_stop_exception(ctx);
6441 #endif
6442 }
6443
6444 /* wrteei */
6445 static void gen_wrteei(DisasContext *ctx)
6446 {
6447 #if defined(CONFIG_USER_ONLY)
6448 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6449 #else
6450 if (unlikely(!ctx->mem_idx)) {
6451 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6452 return;
6453 }
6454 if (ctx->opcode & 0x00008000) {
6455 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6456 /* Stop translation to have a chance to raise an exception */
6457 gen_stop_exception(ctx);
6458 } else {
6459 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6460 }
6461 #endif
6462 }
6463
6464 /* PowerPC 440 specific instructions */
6465
6466 /* dlmzb */
6467 static void gen_dlmzb(DisasContext *ctx)
6468 {
6469 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6470 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6471 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6472 tcg_temp_free_i32(t0);
6473 }
6474
6475 /* mbar replaces eieio on 440 */
6476 static void gen_mbar(DisasContext *ctx)
6477 {
6478 /* interpreted as no-op */
6479 }
6480
6481 /* msync replaces sync on 440 */
6482 static void gen_msync_4xx(DisasContext *ctx)
6483 {
6484 /* interpreted as no-op */
6485 }
6486
6487 /* icbt */
6488 static void gen_icbt_440(DisasContext *ctx)
6489 {
6490 /* interpreted as no-op */
6491 /* XXX: specification say this is treated as a load by the MMU
6492 * but does not generate any exception
6493 */
6494 }
6495
6496 /* Embedded.Processor Control */
6497
6498 static void gen_msgclr(DisasContext *ctx)
6499 {
6500 #if defined(CONFIG_USER_ONLY)
6501 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6502 #else
6503 if (unlikely(ctx->mem_idx == 0)) {
6504 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6505 return;
6506 }
6507
6508 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6509 #endif
6510 }
6511
6512 static void gen_msgsnd(DisasContext *ctx)
6513 {
6514 #if defined(CONFIG_USER_ONLY)
6515 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6516 #else
6517 if (unlikely(ctx->mem_idx == 0)) {
6518 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6519 return;
6520 }
6521
6522 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6523 #endif
6524 }
6525
6526 /*** Altivec vector extension ***/
6527 /* Altivec registers moves */
6528
6529 static inline TCGv_ptr gen_avr_ptr(int reg)
6530 {
6531 TCGv_ptr r = tcg_temp_new_ptr();
6532 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6533 return r;
6534 }
6535
6536 #define GEN_VR_LDX(name, opc2, opc3) \
6537 static void glue(gen_, name)(DisasContext *ctx) \
6538 { \
6539 TCGv EA; \
6540 if (unlikely(!ctx->altivec_enabled)) { \
6541 gen_exception(ctx, POWERPC_EXCP_VPU); \
6542 return; \
6543 } \
6544 gen_set_access_type(ctx, ACCESS_INT); \
6545 EA = tcg_temp_new(); \
6546 gen_addr_reg_index(ctx, EA); \
6547 tcg_gen_andi_tl(EA, EA, ~0xf); \
6548 if (ctx->le_mode) { \
6549 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6550 tcg_gen_addi_tl(EA, EA, 8); \
6551 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6552 } else { \
6553 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6554 tcg_gen_addi_tl(EA, EA, 8); \
6555 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6556 } \
6557 tcg_temp_free(EA); \
6558 }
6559
6560 #define GEN_VR_STX(name, opc2, opc3) \
6561 static void gen_st##name(DisasContext *ctx) \
6562 { \
6563 TCGv EA; \
6564 if (unlikely(!ctx->altivec_enabled)) { \
6565 gen_exception(ctx, POWERPC_EXCP_VPU); \
6566 return; \
6567 } \
6568 gen_set_access_type(ctx, ACCESS_INT); \
6569 EA = tcg_temp_new(); \
6570 gen_addr_reg_index(ctx, EA); \
6571 tcg_gen_andi_tl(EA, EA, ~0xf); \
6572 if (ctx->le_mode) { \
6573 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6574 tcg_gen_addi_tl(EA, EA, 8); \
6575 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6576 } else { \
6577 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6578 tcg_gen_addi_tl(EA, EA, 8); \
6579 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6580 } \
6581 tcg_temp_free(EA); \
6582 }
6583
6584 #define GEN_VR_LVE(name, opc2, opc3) \
6585 static void gen_lve##name(DisasContext *ctx) \
6586 { \
6587 TCGv EA; \
6588 TCGv_ptr rs; \
6589 if (unlikely(!ctx->altivec_enabled)) { \
6590 gen_exception(ctx, POWERPC_EXCP_VPU); \
6591 return; \
6592 } \
6593 gen_set_access_type(ctx, ACCESS_INT); \
6594 EA = tcg_temp_new(); \
6595 gen_addr_reg_index(ctx, EA); \
6596 rs = gen_avr_ptr(rS(ctx->opcode)); \
6597 gen_helper_lve##name(cpu_env, rs, EA); \
6598 tcg_temp_free(EA); \
6599 tcg_temp_free_ptr(rs); \
6600 }
6601
6602 #define GEN_VR_STVE(name, opc2, opc3) \
6603 static void gen_stve##name(DisasContext *ctx) \
6604 { \
6605 TCGv EA; \
6606 TCGv_ptr rs; \
6607 if (unlikely(!ctx->altivec_enabled)) { \
6608 gen_exception(ctx, POWERPC_EXCP_VPU); \
6609 return; \
6610 } \
6611 gen_set_access_type(ctx, ACCESS_INT); \
6612 EA = tcg_temp_new(); \
6613 gen_addr_reg_index(ctx, EA); \
6614 rs = gen_avr_ptr(rS(ctx->opcode)); \
6615 gen_helper_stve##name(cpu_env, rs, EA); \
6616 tcg_temp_free(EA); \
6617 tcg_temp_free_ptr(rs); \
6618 }
6619
6620 GEN_VR_LDX(lvx, 0x07, 0x03);
6621 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6622 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6623
6624 GEN_VR_LVE(bx, 0x07, 0x00);
6625 GEN_VR_LVE(hx, 0x07, 0x01);
6626 GEN_VR_LVE(wx, 0x07, 0x02);
6627
6628 GEN_VR_STX(svx, 0x07, 0x07);
6629 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6630 GEN_VR_STX(svxl, 0x07, 0x0F);
6631
6632 GEN_VR_STVE(bx, 0x07, 0x04);
6633 GEN_VR_STVE(hx, 0x07, 0x05);
6634 GEN_VR_STVE(wx, 0x07, 0x06);
6635
6636 static void gen_lvsl(DisasContext *ctx)
6637 {
6638 TCGv_ptr rd;
6639 TCGv EA;
6640 if (unlikely(!ctx->altivec_enabled)) {
6641 gen_exception(ctx, POWERPC_EXCP_VPU);
6642 return;
6643 }
6644 EA = tcg_temp_new();
6645 gen_addr_reg_index(ctx, EA);
6646 rd = gen_avr_ptr(rD(ctx->opcode));
6647 gen_helper_lvsl(rd, EA);
6648 tcg_temp_free(EA);
6649 tcg_temp_free_ptr(rd);
6650 }
6651
6652 static void gen_lvsr(DisasContext *ctx)
6653 {
6654 TCGv_ptr rd;
6655 TCGv EA;
6656 if (unlikely(!ctx->altivec_enabled)) {
6657 gen_exception(ctx, POWERPC_EXCP_VPU);
6658 return;
6659 }
6660 EA = tcg_temp_new();
6661 gen_addr_reg_index(ctx, EA);
6662 rd = gen_avr_ptr(rD(ctx->opcode));
6663 gen_helper_lvsr(rd, EA);
6664 tcg_temp_free(EA);
6665 tcg_temp_free_ptr(rd);
6666 }
6667
6668 static void gen_mfvscr(DisasContext *ctx)
6669 {
6670 TCGv_i32 t;
6671 if (unlikely(!ctx->altivec_enabled)) {
6672 gen_exception(ctx, POWERPC_EXCP_VPU);
6673 return;
6674 }
6675 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6676 t = tcg_temp_new_i32();
6677 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6678 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6679 tcg_temp_free_i32(t);
6680 }
6681
6682 static void gen_mtvscr(DisasContext *ctx)
6683 {
6684 TCGv_ptr p;
6685 if (unlikely(!ctx->altivec_enabled)) {
6686 gen_exception(ctx, POWERPC_EXCP_VPU);
6687 return;
6688 }
6689 p = gen_avr_ptr(rD(ctx->opcode));
6690 gen_helper_mtvscr(cpu_env, p);
6691 tcg_temp_free_ptr(p);
6692 }
6693
6694 /* Logical operations */
6695 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6696 static void glue(gen_, name)(DisasContext *ctx) \
6697 { \
6698 if (unlikely(!ctx->altivec_enabled)) { \
6699 gen_exception(ctx, POWERPC_EXCP_VPU); \
6700 return; \
6701 } \
6702 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6703 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6704 }
6705
6706 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6707 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6708 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6709 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6710 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6711
6712 #define GEN_VXFORM(name, opc2, opc3) \
6713 static void glue(gen_, name)(DisasContext *ctx) \
6714 { \
6715 TCGv_ptr ra, rb, rd; \
6716 if (unlikely(!ctx->altivec_enabled)) { \
6717 gen_exception(ctx, POWERPC_EXCP_VPU); \
6718 return; \
6719 } \
6720 ra = gen_avr_ptr(rA(ctx->opcode)); \
6721 rb = gen_avr_ptr(rB(ctx->opcode)); \
6722 rd = gen_avr_ptr(rD(ctx->opcode)); \
6723 gen_helper_##name (rd, ra, rb); \
6724 tcg_temp_free_ptr(ra); \
6725 tcg_temp_free_ptr(rb); \
6726 tcg_temp_free_ptr(rd); \
6727 }
6728
6729 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6730 static void glue(gen_, name)(DisasContext *ctx) \
6731 { \
6732 TCGv_ptr ra, rb, rd; \
6733 if (unlikely(!ctx->altivec_enabled)) { \
6734 gen_exception(ctx, POWERPC_EXCP_VPU); \
6735 return; \
6736 } \
6737 ra = gen_avr_ptr(rA(ctx->opcode)); \
6738 rb = gen_avr_ptr(rB(ctx->opcode)); \
6739 rd = gen_avr_ptr(rD(ctx->opcode)); \
6740 gen_helper_##name(cpu_env, rd, ra, rb); \
6741 tcg_temp_free_ptr(ra); \
6742 tcg_temp_free_ptr(rb); \
6743 tcg_temp_free_ptr(rd); \
6744 }
6745
6746 GEN_VXFORM(vaddubm, 0, 0);
6747 GEN_VXFORM(vadduhm, 0, 1);
6748 GEN_VXFORM(vadduwm, 0, 2);
6749 GEN_VXFORM(vsububm, 0, 16);
6750 GEN_VXFORM(vsubuhm, 0, 17);
6751 GEN_VXFORM(vsubuwm, 0, 18);
6752 GEN_VXFORM(vmaxub, 1, 0);
6753 GEN_VXFORM(vmaxuh, 1, 1);
6754 GEN_VXFORM(vmaxuw, 1, 2);
6755 GEN_VXFORM(vmaxsb, 1, 4);
6756 GEN_VXFORM(vmaxsh, 1, 5);
6757 GEN_VXFORM(vmaxsw, 1, 6);
6758 GEN_VXFORM(vminub, 1, 8);
6759 GEN_VXFORM(vminuh, 1, 9);
6760 GEN_VXFORM(vminuw, 1, 10);
6761 GEN_VXFORM(vminsb, 1, 12);
6762 GEN_VXFORM(vminsh, 1, 13);
6763 GEN_VXFORM(vminsw, 1, 14);
6764 GEN_VXFORM(vavgub, 1, 16);
6765 GEN_VXFORM(vavguh, 1, 17);
6766 GEN_VXFORM(vavguw, 1, 18);
6767 GEN_VXFORM(vavgsb, 1, 20);
6768 GEN_VXFORM(vavgsh, 1, 21);
6769 GEN_VXFORM(vavgsw, 1, 22);
6770 GEN_VXFORM(vmrghb, 6, 0);
6771 GEN_VXFORM(vmrghh, 6, 1);
6772 GEN_VXFORM(vmrghw, 6, 2);
6773 GEN_VXFORM(vmrglb, 6, 4);
6774 GEN_VXFORM(vmrglh, 6, 5);
6775 GEN_VXFORM(vmrglw, 6, 6);
6776 GEN_VXFORM(vmuloub, 4, 0);
6777 GEN_VXFORM(vmulouh, 4, 1);
6778 GEN_VXFORM(vmulosb, 4, 4);
6779 GEN_VXFORM(vmulosh, 4, 5);
6780 GEN_VXFORM(vmuleub, 4, 8);
6781 GEN_VXFORM(vmuleuh, 4, 9);
6782 GEN_VXFORM(vmulesb, 4, 12);
6783 GEN_VXFORM(vmulesh, 4, 13);
6784 GEN_VXFORM(vslb, 2, 4);
6785 GEN_VXFORM(vslh, 2, 5);
6786 GEN_VXFORM(vslw, 2, 6);
6787 GEN_VXFORM(vsrb, 2, 8);
6788 GEN_VXFORM(vsrh, 2, 9);
6789 GEN_VXFORM(vsrw, 2, 10);
6790 GEN_VXFORM(vsrab, 2, 12);
6791 GEN_VXFORM(vsrah, 2, 13);
6792 GEN_VXFORM(vsraw, 2, 14);
6793 GEN_VXFORM(vslo, 6, 16);
6794 GEN_VXFORM(vsro, 6, 17);
6795 GEN_VXFORM(vaddcuw, 0, 6);
6796 GEN_VXFORM(vsubcuw, 0, 22);
6797 GEN_VXFORM_ENV(vaddubs, 0, 8);
6798 GEN_VXFORM_ENV(vadduhs, 0, 9);
6799 GEN_VXFORM_ENV(vadduws, 0, 10);
6800 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6801 GEN_VXFORM_ENV(vaddshs, 0, 13);
6802 GEN_VXFORM_ENV(vaddsws, 0, 14);
6803 GEN_VXFORM_ENV(vsububs, 0, 24);
6804 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6805 GEN_VXFORM_ENV(vsubuws, 0, 26);
6806 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6807 GEN_VXFORM_ENV(vsubshs, 0, 29);
6808 GEN_VXFORM_ENV(vsubsws, 0, 30);
6809 GEN_VXFORM(vrlb, 2, 0);
6810 GEN_VXFORM(vrlh, 2, 1);
6811 GEN_VXFORM(vrlw, 2, 2);
6812 GEN_VXFORM(vsl, 2, 7);
6813 GEN_VXFORM(vsr, 2, 11);
6814 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6815 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6816 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6817 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6818 GEN_VXFORM_ENV(vpkshus, 7, 4);
6819 GEN_VXFORM_ENV(vpkswus, 7, 5);
6820 GEN_VXFORM_ENV(vpkshss, 7, 6);
6821 GEN_VXFORM_ENV(vpkswss, 7, 7);
6822 GEN_VXFORM(vpkpx, 7, 12);
6823 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6824 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6825 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6826 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6827 GEN_VXFORM_ENV(vsumsws, 4, 30);
6828 GEN_VXFORM_ENV(vaddfp, 5, 0);
6829 GEN_VXFORM_ENV(vsubfp, 5, 1);
6830 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6831 GEN_VXFORM_ENV(vminfp, 5, 17);
6832
6833 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6834 static void glue(gen_, name)(DisasContext *ctx) \
6835 { \
6836 TCGv_ptr ra, rb, rd; \
6837 if (unlikely(!ctx->altivec_enabled)) { \
6838 gen_exception(ctx, POWERPC_EXCP_VPU); \
6839 return; \
6840 } \
6841 ra = gen_avr_ptr(rA(ctx->opcode)); \
6842 rb = gen_avr_ptr(rB(ctx->opcode)); \
6843 rd = gen_avr_ptr(rD(ctx->opcode)); \
6844 gen_helper_##opname(cpu_env, rd, ra, rb); \
6845 tcg_temp_free_ptr(ra); \
6846 tcg_temp_free_ptr(rb); \
6847 tcg_temp_free_ptr(rd); \
6848 }
6849
6850 #define GEN_VXRFORM(name, opc2, opc3) \
6851 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6852 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6853
6854 GEN_VXRFORM(vcmpequb, 3, 0)
6855 GEN_VXRFORM(vcmpequh, 3, 1)
6856 GEN_VXRFORM(vcmpequw, 3, 2)
6857 GEN_VXRFORM(vcmpgtsb, 3, 12)
6858 GEN_VXRFORM(vcmpgtsh, 3, 13)
6859 GEN_VXRFORM(vcmpgtsw, 3, 14)
6860 GEN_VXRFORM(vcmpgtub, 3, 8)
6861 GEN_VXRFORM(vcmpgtuh, 3, 9)
6862 GEN_VXRFORM(vcmpgtuw, 3, 10)
6863 GEN_VXRFORM(vcmpeqfp, 3, 3)
6864 GEN_VXRFORM(vcmpgefp, 3, 7)
6865 GEN_VXRFORM(vcmpgtfp, 3, 11)
6866 GEN_VXRFORM(vcmpbfp, 3, 15)
6867
6868 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6869 static void glue(gen_, name)(DisasContext *ctx) \
6870 { \
6871 TCGv_ptr rd; \
6872 TCGv_i32 simm; \
6873 if (unlikely(!ctx->altivec_enabled)) { \
6874 gen_exception(ctx, POWERPC_EXCP_VPU); \
6875 return; \
6876 } \
6877 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6878 rd = gen_avr_ptr(rD(ctx->opcode)); \
6879 gen_helper_##name (rd, simm); \
6880 tcg_temp_free_i32(simm); \
6881 tcg_temp_free_ptr(rd); \
6882 }
6883
6884 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6885 GEN_VXFORM_SIMM(vspltish, 6, 13);
6886 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6887
6888 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6889 static void glue(gen_, name)(DisasContext *ctx) \
6890 { \
6891 TCGv_ptr rb, rd; \
6892 if (unlikely(!ctx->altivec_enabled)) { \
6893 gen_exception(ctx, POWERPC_EXCP_VPU); \
6894 return; \
6895 } \
6896 rb = gen_avr_ptr(rB(ctx->opcode)); \
6897 rd = gen_avr_ptr(rD(ctx->opcode)); \
6898 gen_helper_##name (rd, rb); \
6899 tcg_temp_free_ptr(rb); \
6900 tcg_temp_free_ptr(rd); \
6901 }
6902
6903 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6904 static void glue(gen_, name)(DisasContext *ctx) \
6905 { \
6906 TCGv_ptr rb, rd; \
6907 \
6908 if (unlikely(!ctx->altivec_enabled)) { \
6909 gen_exception(ctx, POWERPC_EXCP_VPU); \
6910 return; \
6911 } \
6912 rb = gen_avr_ptr(rB(ctx->opcode)); \
6913 rd = gen_avr_ptr(rD(ctx->opcode)); \
6914 gen_helper_##name(cpu_env, rd, rb); \
6915 tcg_temp_free_ptr(rb); \
6916 tcg_temp_free_ptr(rd); \
6917 }
6918
6919 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6920 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6921 GEN_VXFORM_NOA(vupklsb, 7, 10);
6922 GEN_VXFORM_NOA(vupklsh, 7, 11);
6923 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6924 GEN_VXFORM_NOA(vupklpx, 7, 15);
6925 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6926 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6927 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6928 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6929 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6930 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6931 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6932 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6933
6934 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6935 static void glue(gen_, name)(DisasContext *ctx) \
6936 { \
6937 TCGv_ptr rd; \
6938 TCGv_i32 simm; \
6939 if (unlikely(!ctx->altivec_enabled)) { \
6940 gen_exception(ctx, POWERPC_EXCP_VPU); \
6941 return; \
6942 } \
6943 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6944 rd = gen_avr_ptr(rD(ctx->opcode)); \
6945 gen_helper_##name (rd, simm); \
6946 tcg_temp_free_i32(simm); \
6947 tcg_temp_free_ptr(rd); \
6948 }
6949
6950 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6951 static void glue(gen_, name)(DisasContext *ctx) \
6952 { \
6953 TCGv_ptr rb, rd; \
6954 TCGv_i32 uimm; \
6955 if (unlikely(!ctx->altivec_enabled)) { \
6956 gen_exception(ctx, POWERPC_EXCP_VPU); \
6957 return; \
6958 } \
6959 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6960 rb = gen_avr_ptr(rB(ctx->opcode)); \
6961 rd = gen_avr_ptr(rD(ctx->opcode)); \
6962 gen_helper_##name (rd, rb, uimm); \
6963 tcg_temp_free_i32(uimm); \
6964 tcg_temp_free_ptr(rb); \
6965 tcg_temp_free_ptr(rd); \
6966 }
6967
6968 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6969 static void glue(gen_, name)(DisasContext *ctx) \
6970 { \
6971 TCGv_ptr rb, rd; \
6972 TCGv_i32 uimm; \
6973 \
6974 if (unlikely(!ctx->altivec_enabled)) { \
6975 gen_exception(ctx, POWERPC_EXCP_VPU); \
6976 return; \
6977 } \
6978 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6979 rb = gen_avr_ptr(rB(ctx->opcode)); \
6980 rd = gen_avr_ptr(rD(ctx->opcode)); \
6981 gen_helper_##name(cpu_env, rd, rb, uimm); \
6982 tcg_temp_free_i32(uimm); \
6983 tcg_temp_free_ptr(rb); \
6984 tcg_temp_free_ptr(rd); \
6985 }
6986
6987 GEN_VXFORM_UIMM(vspltb, 6, 8);
6988 GEN_VXFORM_UIMM(vsplth, 6, 9);
6989 GEN_VXFORM_UIMM(vspltw, 6, 10);
6990 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6991 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6992 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6993 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6994
6995 static void gen_vsldoi(DisasContext *ctx)
6996 {
6997 TCGv_ptr ra, rb, rd;
6998 TCGv_i32 sh;
6999 if (unlikely(!ctx->altivec_enabled)) {
7000 gen_exception(ctx, POWERPC_EXCP_VPU);
7001 return;
7002 }
7003 ra = gen_avr_ptr(rA(ctx->opcode));
7004 rb = gen_avr_ptr(rB(ctx->opcode));
7005 rd = gen_avr_ptr(rD(ctx->opcode));
7006 sh = tcg_const_i32(VSH(ctx->opcode));
7007 gen_helper_vsldoi (rd, ra, rb, sh);
7008 tcg_temp_free_ptr(ra);
7009 tcg_temp_free_ptr(rb);
7010 tcg_temp_free_ptr(rd);
7011 tcg_temp_free_i32(sh);
7012 }
7013
7014 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7015 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7016 { \
7017 TCGv_ptr ra, rb, rc, rd; \
7018 if (unlikely(!ctx->altivec_enabled)) { \
7019 gen_exception(ctx, POWERPC_EXCP_VPU); \
7020 return; \
7021 } \
7022 ra = gen_avr_ptr(rA(ctx->opcode)); \
7023 rb = gen_avr_ptr(rB(ctx->opcode)); \
7024 rc = gen_avr_ptr(rC(ctx->opcode)); \
7025 rd = gen_avr_ptr(rD(ctx->opcode)); \
7026 if (Rc(ctx->opcode)) { \
7027 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7028 } else { \
7029 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7030 } \
7031 tcg_temp_free_ptr(ra); \
7032 tcg_temp_free_ptr(rb); \
7033 tcg_temp_free_ptr(rc); \
7034 tcg_temp_free_ptr(rd); \
7035 }
7036
7037 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7038
7039 static void gen_vmladduhm(DisasContext *ctx)
7040 {
7041 TCGv_ptr ra, rb, rc, rd;
7042 if (unlikely(!ctx->altivec_enabled)) {
7043 gen_exception(ctx, POWERPC_EXCP_VPU);
7044 return;
7045 }
7046 ra = gen_avr_ptr(rA(ctx->opcode));
7047 rb = gen_avr_ptr(rB(ctx->opcode));
7048 rc = gen_avr_ptr(rC(ctx->opcode));
7049 rd = gen_avr_ptr(rD(ctx->opcode));
7050 gen_helper_vmladduhm(rd, ra, rb, rc);
7051 tcg_temp_free_ptr(ra);
7052 tcg_temp_free_ptr(rb);
7053 tcg_temp_free_ptr(rc);
7054 tcg_temp_free_ptr(rd);
7055 }
7056
7057 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7058 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7059 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7060 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7061 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7062
7063 /*** VSX extension ***/
7064
7065 static inline TCGv_i64 cpu_vsrh(int n)
7066 {
7067 if (n < 32) {
7068 return cpu_fpr[n];
7069 } else {
7070 return cpu_avrh[n-32];
7071 }
7072 }
7073
7074 static inline TCGv_i64 cpu_vsrl(int n)
7075 {
7076 if (n < 32) {
7077 return cpu_vsr[n];
7078 } else {
7079 return cpu_avrl[n-32];
7080 }
7081 }
7082
7083 #define VSX_LOAD_SCALAR(name, operation) \
7084 static void gen_##name(DisasContext *ctx) \
7085 { \
7086 TCGv EA; \
7087 if (unlikely(!ctx->vsx_enabled)) { \
7088 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7089 return; \
7090 } \
7091 gen_set_access_type(ctx, ACCESS_INT); \
7092 EA = tcg_temp_new(); \
7093 gen_addr_reg_index(ctx, EA); \
7094 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7095 /* NOTE: cpu_vsrl is undefined */ \
7096 tcg_temp_free(EA); \
7097 }
7098
7099 VSX_LOAD_SCALAR(lxsdx, ld64)
7100 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7101 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7102 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7103
7104 static void gen_lxvd2x(DisasContext *ctx)
7105 {
7106 TCGv EA;
7107 if (unlikely(!ctx->vsx_enabled)) {
7108 gen_exception(ctx, POWERPC_EXCP_VSXU);
7109 return;
7110 }
7111 gen_set_access_type(ctx, ACCESS_INT);
7112 EA = tcg_temp_new();
7113 gen_addr_reg_index(ctx, EA);
7114 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7115 tcg_gen_addi_tl(EA, EA, 8);
7116 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7117 tcg_temp_free(EA);
7118 }
7119
7120 static void gen_lxvdsx(DisasContext *ctx)
7121 {
7122 TCGv EA;
7123 if (unlikely(!ctx->vsx_enabled)) {
7124 gen_exception(ctx, POWERPC_EXCP_VSXU);
7125 return;
7126 }
7127 gen_set_access_type(ctx, ACCESS_INT);
7128 EA = tcg_temp_new();
7129 gen_addr_reg_index(ctx, EA);
7130 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7131 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7132 tcg_temp_free(EA);
7133 }
7134
7135 static void gen_lxvw4x(DisasContext *ctx)
7136 {
7137 TCGv EA;
7138 TCGv_i64 tmp;
7139 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7140 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7141 if (unlikely(!ctx->vsx_enabled)) {
7142 gen_exception(ctx, POWERPC_EXCP_VSXU);
7143 return;
7144 }
7145 gen_set_access_type(ctx, ACCESS_INT);
7146 EA = tcg_temp_new();
7147 tmp = tcg_temp_new_i64();
7148
7149 gen_addr_reg_index(ctx, EA);
7150 gen_qemu_ld32u_i64(ctx, tmp, EA);
7151 tcg_gen_addi_tl(EA, EA, 4);
7152 gen_qemu_ld32u_i64(ctx, xth, EA);
7153 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7154
7155 tcg_gen_addi_tl(EA, EA, 4);
7156 gen_qemu_ld32u_i64(ctx, tmp, EA);
7157 tcg_gen_addi_tl(EA, EA, 4);
7158 gen_qemu_ld32u_i64(ctx, xtl, EA);
7159 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7160
7161 tcg_temp_free(EA);
7162 tcg_temp_free_i64(tmp);
7163 }
7164
7165 #define VSX_STORE_SCALAR(name, operation) \
7166 static void gen_##name(DisasContext *ctx) \
7167 { \
7168 TCGv EA; \
7169 if (unlikely(!ctx->vsx_enabled)) { \
7170 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7171 return; \
7172 } \
7173 gen_set_access_type(ctx, ACCESS_INT); \
7174 EA = tcg_temp_new(); \
7175 gen_addr_reg_index(ctx, EA); \
7176 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7177 tcg_temp_free(EA); \
7178 }
7179
7180 VSX_STORE_SCALAR(stxsdx, st64)
7181 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7182 VSX_STORE_SCALAR(stxsspx, st32fs)
7183
7184 static void gen_stxvd2x(DisasContext *ctx)
7185 {
7186 TCGv EA;
7187 if (unlikely(!ctx->vsx_enabled)) {
7188 gen_exception(ctx, POWERPC_EXCP_VSXU);
7189 return;
7190 }
7191 gen_set_access_type(ctx, ACCESS_INT);
7192 EA = tcg_temp_new();
7193 gen_addr_reg_index(ctx, EA);
7194 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7195 tcg_gen_addi_tl(EA, EA, 8);
7196 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7197 tcg_temp_free(EA);
7198 }
7199
7200 static void gen_stxvw4x(DisasContext *ctx)
7201 {
7202 TCGv_i64 tmp;
7203 TCGv EA;
7204 if (unlikely(!ctx->vsx_enabled)) {
7205 gen_exception(ctx, POWERPC_EXCP_VSXU);
7206 return;
7207 }
7208 gen_set_access_type(ctx, ACCESS_INT);
7209 EA = tcg_temp_new();
7210 gen_addr_reg_index(ctx, EA);
7211 tmp = tcg_temp_new_i64();
7212
7213 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7214 gen_qemu_st32_i64(ctx, tmp, EA);
7215 tcg_gen_addi_tl(EA, EA, 4);
7216 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7217
7218 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7219 tcg_gen_addi_tl(EA, EA, 4);
7220 gen_qemu_st32_i64(ctx, tmp, EA);
7221 tcg_gen_addi_tl(EA, EA, 4);
7222 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7223
7224 tcg_temp_free(EA);
7225 tcg_temp_free_i64(tmp);
7226 }
7227
7228 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7229 static void gen_##name(DisasContext *ctx) \
7230 { \
7231 if (xS(ctx->opcode) < 32) { \
7232 if (unlikely(!ctx->fpu_enabled)) { \
7233 gen_exception(ctx, POWERPC_EXCP_FPU); \
7234 return; \
7235 } \
7236 } else { \
7237 if (unlikely(!ctx->altivec_enabled)) { \
7238 gen_exception(ctx, POWERPC_EXCP_VPU); \
7239 return; \
7240 } \
7241 } \
7242 TCGv_i64 tmp = tcg_temp_new_i64(); \
7243 tcg_gen_##tcgop1(tmp, source); \
7244 tcg_gen_##tcgop2(target, tmp); \
7245 tcg_temp_free_i64(tmp); \
7246 }
7247
7248
7249 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7250 cpu_vsrh(xS(ctx->opcode)))
7251 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7252 cpu_gpr[rA(ctx->opcode)])
7253 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7254 cpu_gpr[rA(ctx->opcode)])
7255
7256 #if defined(TARGET_PPC64)
7257 #define MV_VSRD(name, target, source) \
7258 static void gen_##name(DisasContext *ctx) \
7259 { \
7260 if (xS(ctx->opcode) < 32) { \
7261 if (unlikely(!ctx->fpu_enabled)) { \
7262 gen_exception(ctx, POWERPC_EXCP_FPU); \
7263 return; \
7264 } \
7265 } else { \
7266 if (unlikely(!ctx->altivec_enabled)) { \
7267 gen_exception(ctx, POWERPC_EXCP_VPU); \
7268 return; \
7269 } \
7270 } \
7271 tcg_gen_mov_i64(target, source); \
7272 }
7273
7274 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7275 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7276
7277 #endif
7278
7279 static void gen_xxpermdi(DisasContext *ctx)
7280 {
7281 if (unlikely(!ctx->vsx_enabled)) {
7282 gen_exception(ctx, POWERPC_EXCP_VSXU);
7283 return;
7284 }
7285
7286 if ((DM(ctx->opcode) & 2) == 0) {
7287 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7288 } else {
7289 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7290 }
7291 if ((DM(ctx->opcode) & 1) == 0) {
7292 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7293 } else {
7294 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7295 }
7296 }
7297
7298 #define OP_ABS 1
7299 #define OP_NABS 2
7300 #define OP_NEG 3
7301 #define OP_CPSGN 4
7302 #define SGN_MASK_DP 0x8000000000000000ul
7303 #define SGN_MASK_SP 0x8000000080000000ul
7304
7305 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7306 static void glue(gen_, name)(DisasContext * ctx) \
7307 { \
7308 TCGv_i64 xb, sgm; \
7309 if (unlikely(!ctx->vsx_enabled)) { \
7310 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7311 return; \
7312 } \
7313 xb = tcg_temp_new_i64(); \
7314 sgm = tcg_temp_new_i64(); \
7315 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7316 tcg_gen_movi_i64(sgm, sgn_mask); \
7317 switch (op) { \
7318 case OP_ABS: { \
7319 tcg_gen_andc_i64(xb, xb, sgm); \
7320 break; \
7321 } \
7322 case OP_NABS: { \
7323 tcg_gen_or_i64(xb, xb, sgm); \
7324 break; \
7325 } \
7326 case OP_NEG: { \
7327 tcg_gen_xor_i64(xb, xb, sgm); \
7328 break; \
7329 } \
7330 case OP_CPSGN: { \
7331 TCGv_i64 xa = tcg_temp_new_i64(); \
7332 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7333 tcg_gen_and_i64(xa, xa, sgm); \
7334 tcg_gen_andc_i64(xb, xb, sgm); \
7335 tcg_gen_or_i64(xb, xb, xa); \
7336 tcg_temp_free_i64(xa); \
7337 break; \
7338 } \
7339 } \
7340 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7341 tcg_temp_free_i64(xb); \
7342 tcg_temp_free_i64(sgm); \
7343 }
7344
7345 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7346 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7347 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7348 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7349
7350 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7351 static void glue(gen_, name)(DisasContext * ctx) \
7352 { \
7353 TCGv_i64 xbh, xbl, sgm; \
7354 if (unlikely(!ctx->vsx_enabled)) { \
7355 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7356 return; \
7357 } \
7358 xbh = tcg_temp_new_i64(); \
7359 xbl = tcg_temp_new_i64(); \
7360 sgm = tcg_temp_new_i64(); \
7361 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7362 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7363 tcg_gen_movi_i64(sgm, sgn_mask); \
7364 switch (op) { \
7365 case OP_ABS: { \
7366 tcg_gen_andc_i64(xbh, xbh, sgm); \
7367 tcg_gen_andc_i64(xbl, xbl, sgm); \
7368 break; \
7369 } \
7370 case OP_NABS: { \
7371 tcg_gen_or_i64(xbh, xbh, sgm); \
7372 tcg_gen_or_i64(xbl, xbl, sgm); \
7373 break; \
7374 } \
7375 case OP_NEG: { \
7376 tcg_gen_xor_i64(xbh, xbh, sgm); \
7377 tcg_gen_xor_i64(xbl, xbl, sgm); \
7378 break; \
7379 } \
7380 case OP_CPSGN: { \
7381 TCGv_i64 xah = tcg_temp_new_i64(); \
7382 TCGv_i64 xal = tcg_temp_new_i64(); \
7383 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7384 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7385 tcg_gen_and_i64(xah, xah, sgm); \
7386 tcg_gen_and_i64(xal, xal, sgm); \
7387 tcg_gen_andc_i64(xbh, xbh, sgm); \
7388 tcg_gen_andc_i64(xbl, xbl, sgm); \
7389 tcg_gen_or_i64(xbh, xbh, xah); \
7390 tcg_gen_or_i64(xbl, xbl, xal); \
7391 tcg_temp_free_i64(xah); \
7392 tcg_temp_free_i64(xal); \
7393 break; \
7394 } \
7395 } \
7396 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7397 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7398 tcg_temp_free_i64(xbh); \
7399 tcg_temp_free_i64(xbl); \
7400 tcg_temp_free_i64(sgm); \
7401 }
7402
7403 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7404 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7405 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7406 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7407 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7408 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7409 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7410 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7411
7412 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7413 static void gen_##name(DisasContext * ctx) \
7414 { \
7415 TCGv_i32 opc; \
7416 if (unlikely(!ctx->vsx_enabled)) { \
7417 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7418 return; \
7419 } \
7420 /* NIP cannot be restored if the memory exception comes from an helper */ \
7421 gen_update_nip(ctx, ctx->nip - 4); \
7422 opc = tcg_const_i32(ctx->opcode); \
7423 gen_helper_##name(cpu_env, opc); \
7424 tcg_temp_free_i32(opc); \
7425 }
7426
7427 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7428 static void gen_##name(DisasContext * ctx) \
7429 { \
7430 if (unlikely(!ctx->vsx_enabled)) { \
7431 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7432 return; \
7433 } \
7434 /* NIP cannot be restored if the exception comes */ \
7435 /* from a helper. */ \
7436 gen_update_nip(ctx, ctx->nip - 4); \
7437 \
7438 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7439 cpu_vsrh(xB(ctx->opcode))); \
7440 }
7441
7442 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7443 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7444 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7445 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7446 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7447 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7448 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7449 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7450 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7451 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7452 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7453 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7454 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7455 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7456 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7457 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7458 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7459 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7460 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7461 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7462 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7463 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7464 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
7465 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7466 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
7467 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7468 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7469 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7470 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7471 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7472 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
7473 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7474 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7475 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7476 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7477 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
7478 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
7479
7480 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
7481 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
7482 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
7483 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
7484 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
7485 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
7486 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
7487 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
7488 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
7489 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
7490 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
7491 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
7492 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
7493 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
7494 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
7495 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
7496 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
7497
7498 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
7499 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
7500 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
7501 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
7502 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
7503 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
7504 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
7505 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
7506 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
7507 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
7508 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
7509 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
7510 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
7511 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
7512 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
7513 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
7514 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
7515 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
7516 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
7517 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
7518 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
7519 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
7520 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
7521 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
7522 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
7523 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
7524 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
7525 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
7526 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
7527 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
7528 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
7529 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
7530 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
7531 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
7532 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
7533 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
7534
7535 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
7536 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
7537 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
7538 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
7539 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
7540 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
7541 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
7542 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
7543 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
7544 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
7545 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
7546 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
7547 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
7548 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
7549 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
7550 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
7551 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
7552 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
7553 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
7554 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
7555 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
7556 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
7557 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
7558 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
7559 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
7560 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
7561 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
7562 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
7563 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
7564 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
7565 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
7566 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
7567 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
7568 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
7569 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
7570 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
7571
7572 #define VSX_LOGICAL(name, tcg_op) \
7573 static void glue(gen_, name)(DisasContext * ctx) \
7574 { \
7575 if (unlikely(!ctx->vsx_enabled)) { \
7576 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7577 return; \
7578 } \
7579 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
7580 cpu_vsrh(xB(ctx->opcode))); \
7581 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
7582 cpu_vsrl(xB(ctx->opcode))); \
7583 }
7584
7585 VSX_LOGICAL(xxland, tcg_gen_and_i64)
7586 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
7587 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
7588 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
7589 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
7590 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
7591 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
7592 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
7593
7594 #define VSX_XXMRG(name, high) \
7595 static void glue(gen_, name)(DisasContext * ctx) \
7596 { \
7597 TCGv_i64 a0, a1, b0, b1; \
7598 if (unlikely(!ctx->vsx_enabled)) { \
7599 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7600 return; \
7601 } \
7602 a0 = tcg_temp_new_i64(); \
7603 a1 = tcg_temp_new_i64(); \
7604 b0 = tcg_temp_new_i64(); \
7605 b1 = tcg_temp_new_i64(); \
7606 if (high) { \
7607 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
7608 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
7609 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
7610 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
7611 } else { \
7612 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
7613 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
7614 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
7615 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
7616 } \
7617 tcg_gen_shri_i64(a0, a0, 32); \
7618 tcg_gen_shri_i64(b0, b0, 32); \
7619 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
7620 b0, a0, 32, 32); \
7621 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
7622 b1, a1, 32, 32); \
7623 tcg_temp_free_i64(a0); \
7624 tcg_temp_free_i64(a1); \
7625 tcg_temp_free_i64(b0); \
7626 tcg_temp_free_i64(b1); \
7627 }
7628
7629 VSX_XXMRG(xxmrghw, 1)
7630 VSX_XXMRG(xxmrglw, 0)
7631
7632 static void gen_xxsel(DisasContext * ctx)
7633 {
7634 TCGv_i64 a, b, c;
7635 if (unlikely(!ctx->vsx_enabled)) {
7636 gen_exception(ctx, POWERPC_EXCP_VSXU);
7637 return;
7638 }
7639 a = tcg_temp_new_i64();
7640 b = tcg_temp_new_i64();
7641 c = tcg_temp_new_i64();
7642
7643 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
7644 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
7645 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
7646
7647 tcg_gen_and_i64(b, b, c);
7648 tcg_gen_andc_i64(a, a, c);
7649 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
7650
7651 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
7652 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
7653 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
7654
7655 tcg_gen_and_i64(b, b, c);
7656 tcg_gen_andc_i64(a, a, c);
7657 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
7658
7659 tcg_temp_free_i64(a);
7660 tcg_temp_free_i64(b);
7661 tcg_temp_free_i64(c);
7662 }
7663
7664 static void gen_xxspltw(DisasContext *ctx)
7665 {
7666 TCGv_i64 b, b2;
7667 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
7668 cpu_vsrl(xB(ctx->opcode)) :
7669 cpu_vsrh(xB(ctx->opcode));
7670
7671 if (unlikely(!ctx->vsx_enabled)) {
7672 gen_exception(ctx, POWERPC_EXCP_VSXU);
7673 return;
7674 }
7675
7676 b = tcg_temp_new_i64();
7677 b2 = tcg_temp_new_i64();
7678
7679 if (UIM(ctx->opcode) & 1) {
7680 tcg_gen_ext32u_i64(b, vsr);
7681 } else {
7682 tcg_gen_shri_i64(b, vsr, 32);
7683 }
7684
7685 tcg_gen_shli_i64(b2, b, 32);
7686 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
7687 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7688
7689 tcg_temp_free_i64(b);
7690 tcg_temp_free_i64(b2);
7691 }
7692
7693 static void gen_xxsldwi(DisasContext *ctx)
7694 {
7695 TCGv_i64 xth, xtl;
7696 if (unlikely(!ctx->vsx_enabled)) {
7697 gen_exception(ctx, POWERPC_EXCP_VSXU);
7698 return;
7699 }
7700 xth = tcg_temp_new_i64();
7701 xtl = tcg_temp_new_i64();
7702
7703 switch (SHW(ctx->opcode)) {
7704 case 0: {
7705 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
7706 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
7707 break;
7708 }
7709 case 1: {
7710 TCGv_i64 t0 = tcg_temp_new_i64();
7711 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
7712 tcg_gen_shli_i64(xth, xth, 32);
7713 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
7714 tcg_gen_shri_i64(t0, t0, 32);
7715 tcg_gen_or_i64(xth, xth, t0);
7716 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
7717 tcg_gen_shli_i64(xtl, xtl, 32);
7718 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
7719 tcg_gen_shri_i64(t0, t0, 32);
7720 tcg_gen_or_i64(xtl, xtl, t0);
7721 tcg_temp_free_i64(t0);
7722 break;
7723 }
7724 case 2: {
7725 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
7726 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
7727 break;
7728 }
7729 case 3: {
7730 TCGv_i64 t0 = tcg_temp_new_i64();
7731 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
7732 tcg_gen_shli_i64(xth, xth, 32);
7733 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
7734 tcg_gen_shri_i64(t0, t0, 32);
7735 tcg_gen_or_i64(xth, xth, t0);
7736 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
7737 tcg_gen_shli_i64(xtl, xtl, 32);
7738 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
7739 tcg_gen_shri_i64(t0, t0, 32);
7740 tcg_gen_or_i64(xtl, xtl, t0);
7741 tcg_temp_free_i64(t0);
7742 break;
7743 }
7744 }
7745
7746 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
7747 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
7748
7749 tcg_temp_free_i64(xth);
7750 tcg_temp_free_i64(xtl);
7751 }
7752
7753
7754 /*** SPE extension ***/
7755 /* Register moves */
7756
7757 static inline void gen_evmra(DisasContext *ctx)
7758 {
7759
7760 if (unlikely(!ctx->spe_enabled)) {
7761 gen_exception(ctx, POWERPC_EXCP_SPEU);
7762 return;
7763 }
7764
7765 #if defined(TARGET_PPC64)
7766 /* rD := rA */
7767 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7768
7769 /* spe_acc := rA */
7770 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
7771 cpu_env,
7772 offsetof(CPUPPCState, spe_acc));
7773 #else
7774 TCGv_i64 tmp = tcg_temp_new_i64();
7775
7776 /* tmp := rA_lo + rA_hi << 32 */
7777 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7778
7779 /* spe_acc := tmp */
7780 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7781 tcg_temp_free_i64(tmp);
7782
7783 /* rD := rA */
7784 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7785 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7786 #endif
7787 }
7788
7789 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
7790 {
7791 #if defined(TARGET_PPC64)
7792 tcg_gen_mov_i64(t, cpu_gpr[reg]);
7793 #else
7794 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
7795 #endif
7796 }
7797
7798 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
7799 {
7800 #if defined(TARGET_PPC64)
7801 tcg_gen_mov_i64(cpu_gpr[reg], t);
7802 #else
7803 TCGv_i64 tmp = tcg_temp_new_i64();
7804 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
7805 tcg_gen_shri_i64(tmp, t, 32);
7806 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
7807 tcg_temp_free_i64(tmp);
7808 #endif
7809 }
7810
7811 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
7812 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7813 { \
7814 if (Rc(ctx->opcode)) \
7815 gen_##name1(ctx); \
7816 else \
7817 gen_##name0(ctx); \
7818 }
7819
7820 /* Handler for undefined SPE opcodes */
7821 static inline void gen_speundef(DisasContext *ctx)
7822 {
7823 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7824 }
7825
7826 /* SPE logic */
7827 #if defined(TARGET_PPC64)
7828 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
7829 static inline void gen_##name(DisasContext *ctx) \
7830 { \
7831 if (unlikely(!ctx->spe_enabled)) { \
7832 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7833 return; \
7834 } \
7835 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7836 cpu_gpr[rB(ctx->opcode)]); \
7837 }
7838 #else
7839 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
7840 static inline void gen_##name(DisasContext *ctx) \
7841 { \
7842 if (unlikely(!ctx->spe_enabled)) { \
7843 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7844 return; \
7845 } \
7846 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7847 cpu_gpr[rB(ctx->opcode)]); \
7848 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7849 cpu_gprh[rB(ctx->opcode)]); \
7850 }
7851 #endif
7852
7853 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
7854 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
7855 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
7856 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
7857 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
7858 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
7859 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
7860 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
7861
7862 /* SPE logic immediate */
7863 #if defined(TARGET_PPC64)
7864 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
7865 static inline void gen_##name(DisasContext *ctx) \
7866 { \
7867 if (unlikely(!ctx->spe_enabled)) { \
7868 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7869 return; \
7870 } \
7871 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7872 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7873 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7874 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7875 tcg_opi(t0, t0, rB(ctx->opcode)); \
7876 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7877 tcg_gen_trunc_i64_i32(t1, t2); \
7878 tcg_temp_free_i64(t2); \
7879 tcg_opi(t1, t1, rB(ctx->opcode)); \
7880 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7881 tcg_temp_free_i32(t0); \
7882 tcg_temp_free_i32(t1); \
7883 }
7884 #else
7885 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
7886 static inline void gen_##name(DisasContext *ctx) \
7887 { \
7888 if (unlikely(!ctx->spe_enabled)) { \
7889 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7890 return; \
7891 } \
7892 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7893 rB(ctx->opcode)); \
7894 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7895 rB(ctx->opcode)); \
7896 }
7897 #endif
7898 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
7899 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
7900 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
7901 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
7902
7903 /* SPE arithmetic */
7904 #if defined(TARGET_PPC64)
7905 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7906 static inline void gen_##name(DisasContext *ctx) \
7907 { \
7908 if (unlikely(!ctx->spe_enabled)) { \
7909 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7910 return; \
7911 } \
7912 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7913 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7914 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7915 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7916 tcg_op(t0, t0); \
7917 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7918 tcg_gen_trunc_i64_i32(t1, t2); \
7919 tcg_temp_free_i64(t2); \
7920 tcg_op(t1, t1); \
7921 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7922 tcg_temp_free_i32(t0); \
7923 tcg_temp_free_i32(t1); \
7924 }
7925 #else
7926 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7927 static inline void gen_##name(DisasContext *ctx) \
7928 { \
7929 if (unlikely(!ctx->spe_enabled)) { \
7930 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7931 return; \
7932 } \
7933 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
7934 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
7935 }
7936 #endif
7937
7938 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
7939 {
7940 int l1 = gen_new_label();
7941 int l2 = gen_new_label();
7942
7943 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
7944 tcg_gen_neg_i32(ret, arg1);
7945 tcg_gen_br(l2);
7946 gen_set_label(l1);
7947 tcg_gen_mov_i32(ret, arg1);
7948 gen_set_label(l2);
7949 }
7950 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
7951 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
7952 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
7953 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
7954 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
7955 {
7956 tcg_gen_addi_i32(ret, arg1, 0x8000);
7957 tcg_gen_ext16u_i32(ret, ret);
7958 }
7959 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
7960 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
7961 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
7962
7963 #if defined(TARGET_PPC64)
7964 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7965 static inline void gen_##name(DisasContext *ctx) \
7966 { \
7967 if (unlikely(!ctx->spe_enabled)) { \
7968 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7969 return; \
7970 } \
7971 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7972 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7973 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
7974 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
7975 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7976 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
7977 tcg_op(t0, t0, t2); \
7978 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
7979 tcg_gen_trunc_i64_i32(t1, t3); \
7980 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
7981 tcg_gen_trunc_i64_i32(t2, t3); \
7982 tcg_temp_free_i64(t3); \
7983 tcg_op(t1, t1, t2); \
7984 tcg_temp_free_i32(t2); \
7985 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7986 tcg_temp_free_i32(t0); \
7987 tcg_temp_free_i32(t1); \
7988 }
7989 #else
7990 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7991 static inline void gen_##name(DisasContext *ctx) \
7992 { \
7993 if (unlikely(!ctx->spe_enabled)) { \
7994 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7995 return; \
7996 } \
7997 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7998 cpu_gpr[rB(ctx->opcode)]); \
7999 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8000 cpu_gprh[rB(ctx->opcode)]); \
8001 }
8002 #endif
8003
8004 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8005 {
8006 TCGv_i32 t0;
8007 int l1, l2;
8008
8009 l1 = gen_new_label();
8010 l2 = gen_new_label();
8011 t0 = tcg_temp_local_new_i32();
8012 /* No error here: 6 bits are used */
8013 tcg_gen_andi_i32(t0, arg2, 0x3F);
8014 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8015 tcg_gen_shr_i32(ret, arg1, t0);
8016 tcg_gen_br(l2);
8017 gen_set_label(l1);
8018 tcg_gen_movi_i32(ret, 0);
8019 gen_set_label(l2);
8020 tcg_temp_free_i32(t0);
8021 }
8022 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8023 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8024 {
8025 TCGv_i32 t0;
8026 int l1, l2;
8027
8028 l1 = gen_new_label();
8029 l2 = gen_new_label();
8030 t0 = tcg_temp_local_new_i32();
8031 /* No error here: 6 bits are used */
8032 tcg_gen_andi_i32(t0, arg2, 0x3F);
8033 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8034 tcg_gen_sar_i32(ret, arg1, t0);
8035 tcg_gen_br(l2);
8036 gen_set_label(l1);
8037 tcg_gen_movi_i32(ret, 0);
8038 gen_set_label(l2);
8039 tcg_temp_free_i32(t0);
8040 }
8041 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8042 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8043 {
8044 TCGv_i32 t0;
8045 int l1, l2;
8046
8047 l1 = gen_new_label();
8048 l2 = gen_new_label();
8049 t0 = tcg_temp_local_new_i32();
8050 /* No error here: 6 bits are used */
8051 tcg_gen_andi_i32(t0, arg2, 0x3F);
8052 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8053 tcg_gen_shl_i32(ret, arg1, t0);
8054 tcg_gen_br(l2);
8055 gen_set_label(l1);
8056 tcg_gen_movi_i32(ret, 0);
8057 gen_set_label(l2);
8058 tcg_temp_free_i32(t0);
8059 }
8060 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8061 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8062 {
8063 TCGv_i32 t0 = tcg_temp_new_i32();
8064 tcg_gen_andi_i32(t0, arg2, 0x1F);
8065 tcg_gen_rotl_i32(ret, arg1, t0);
8066 tcg_temp_free_i32(t0);
8067 }
8068 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8069 static inline void gen_evmergehi(DisasContext *ctx)
8070 {
8071 if (unlikely(!ctx->spe_enabled)) {
8072 gen_exception(ctx, POWERPC_EXCP_SPEU);
8073 return;
8074 }
8075 #if defined(TARGET_PPC64)
8076 TCGv t0 = tcg_temp_new();
8077 TCGv t1 = tcg_temp_new();
8078 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
8079 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
8080 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8081 tcg_temp_free(t0);
8082 tcg_temp_free(t1);
8083 #else
8084 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8085 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8086 #endif
8087 }
8088 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8089 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8090 {
8091 tcg_gen_sub_i32(ret, arg2, arg1);
8092 }
8093 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8094
8095 /* SPE arithmetic immediate */
8096 #if defined(TARGET_PPC64)
8097 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8098 static inline void gen_##name(DisasContext *ctx) \
8099 { \
8100 if (unlikely(!ctx->spe_enabled)) { \
8101 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8102 return; \
8103 } \
8104 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8105 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8106 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8107 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8108 tcg_op(t0, t0, rA(ctx->opcode)); \
8109 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
8110 tcg_gen_trunc_i64_i32(t1, t2); \
8111 tcg_temp_free_i64(t2); \
8112 tcg_op(t1, t1, rA(ctx->opcode)); \
8113 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
8114 tcg_temp_free_i32(t0); \
8115 tcg_temp_free_i32(t1); \
8116 }
8117 #else
8118 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8119 static inline void gen_##name(DisasContext *ctx) \
8120 { \
8121 if (unlikely(!ctx->spe_enabled)) { \
8122 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8123 return; \
8124 } \
8125 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
8126 rA(ctx->opcode)); \
8127 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
8128 rA(ctx->opcode)); \
8129 }
8130 #endif
8131 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8132 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8133
8134 /* SPE comparison */
8135 #if defined(TARGET_PPC64)
8136 #define GEN_SPEOP_COMP(name, tcg_cond) \
8137 static inline void gen_##name(DisasContext *ctx) \
8138 { \
8139 if (unlikely(!ctx->spe_enabled)) { \
8140 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8141 return; \
8142 } \
8143 int l1 = gen_new_label(); \
8144 int l2 = gen_new_label(); \
8145 int l3 = gen_new_label(); \
8146 int l4 = gen_new_label(); \
8147 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8148 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8149 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8150 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8151 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8152 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
8153 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8154 tcg_gen_br(l2); \
8155 gen_set_label(l1); \
8156 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8157 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8158 gen_set_label(l2); \
8159 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
8160 tcg_gen_trunc_i64_i32(t0, t2); \
8161 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
8162 tcg_gen_trunc_i64_i32(t1, t2); \
8163 tcg_temp_free_i64(t2); \
8164 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
8165 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8166 ~(CRF_CH | CRF_CH_AND_CL)); \
8167 tcg_gen_br(l4); \
8168 gen_set_label(l3); \
8169 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8170 CRF_CH | CRF_CH_OR_CL); \
8171 gen_set_label(l4); \
8172 tcg_temp_free_i32(t0); \
8173 tcg_temp_free_i32(t1); \
8174 }
8175 #else
8176 #define GEN_SPEOP_COMP(name, tcg_cond) \
8177 static inline void gen_##name(DisasContext *ctx) \
8178 { \
8179 if (unlikely(!ctx->spe_enabled)) { \
8180 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8181 return; \
8182 } \
8183 int l1 = gen_new_label(); \
8184 int l2 = gen_new_label(); \
8185 int l3 = gen_new_label(); \
8186 int l4 = gen_new_label(); \
8187 \
8188 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8189 cpu_gpr[rB(ctx->opcode)], l1); \
8190 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
8191 tcg_gen_br(l2); \
8192 gen_set_label(l1); \
8193 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8194 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8195 gen_set_label(l2); \
8196 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8197 cpu_gprh[rB(ctx->opcode)], l3); \
8198 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8199 ~(CRF_CH | CRF_CH_AND_CL)); \
8200 tcg_gen_br(l4); \
8201 gen_set_label(l3); \
8202 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8203 CRF_CH | CRF_CH_OR_CL); \
8204 gen_set_label(l4); \
8205 }
8206 #endif
8207 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8208 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8209 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8210 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8211 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8212
8213 /* SPE misc */
8214 static inline void gen_brinc(DisasContext *ctx)
8215 {
8216 /* Note: brinc is usable even if SPE is disabled */
8217 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8218 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8219 }
8220 static inline void gen_evmergelo(DisasContext *ctx)
8221 {
8222 if (unlikely(!ctx->spe_enabled)) {
8223 gen_exception(ctx, POWERPC_EXCP_SPEU);
8224 return;
8225 }
8226 #if defined(TARGET_PPC64)
8227 TCGv t0 = tcg_temp_new();
8228 TCGv t1 = tcg_temp_new();
8229 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
8230 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
8231 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8232 tcg_temp_free(t0);
8233 tcg_temp_free(t1);
8234 #else
8235 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8236 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8237 #endif
8238 }
8239 static inline void gen_evmergehilo(DisasContext *ctx)
8240 {
8241 if (unlikely(!ctx->spe_enabled)) {
8242 gen_exception(ctx, POWERPC_EXCP_SPEU);
8243 return;
8244 }
8245 #if defined(TARGET_PPC64)
8246 TCGv t0 = tcg_temp_new();
8247 TCGv t1 = tcg_temp_new();
8248 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
8249 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
8250 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8251 tcg_temp_free(t0);
8252 tcg_temp_free(t1);
8253 #else
8254 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8255 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8256 #endif
8257 }
8258 static inline void gen_evmergelohi(DisasContext *ctx)
8259 {
8260 if (unlikely(!ctx->spe_enabled)) {
8261 gen_exception(ctx, POWERPC_EXCP_SPEU);
8262 return;
8263 }
8264 #if defined(TARGET_PPC64)
8265 TCGv t0 = tcg_temp_new();
8266 TCGv t1 = tcg_temp_new();
8267 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
8268 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
8269 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8270 tcg_temp_free(t0);
8271 tcg_temp_free(t1);
8272 #else
8273 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8274 TCGv_i32 tmp = tcg_temp_new_i32();
8275 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
8276 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8277 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
8278 tcg_temp_free_i32(tmp);
8279 } else {
8280 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8281 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8282 }
8283 #endif
8284 }
8285 static inline void gen_evsplati(DisasContext *ctx)
8286 {
8287 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8288
8289 #if defined(TARGET_PPC64)
8290 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
8291 #else
8292 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
8293 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
8294 #endif
8295 }
8296 static inline void gen_evsplatfi(DisasContext *ctx)
8297 {
8298 uint64_t imm = rA(ctx->opcode) << 27;
8299
8300 #if defined(TARGET_PPC64)
8301 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
8302 #else
8303 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
8304 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
8305 #endif
8306 }
8307
8308 static inline void gen_evsel(DisasContext *ctx)
8309 {
8310 int l1 = gen_new_label();
8311 int l2 = gen_new_label();
8312 int l3 = gen_new_label();
8313 int l4 = gen_new_label();
8314 TCGv_i32 t0 = tcg_temp_local_new_i32();
8315 #if defined(TARGET_PPC64)
8316 TCGv t1 = tcg_temp_local_new();
8317 TCGv t2 = tcg_temp_local_new();
8318 #endif
8319 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8320 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8321 #if defined(TARGET_PPC64)
8322 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
8323 #else
8324 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8325 #endif
8326 tcg_gen_br(l2);
8327 gen_set_label(l1);
8328 #if defined(TARGET_PPC64)
8329 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
8330 #else
8331 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8332 #endif
8333 gen_set_label(l2);
8334 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8335 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8336 #if defined(TARGET_PPC64)
8337 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
8338 #else
8339 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8340 #endif
8341 tcg_gen_br(l4);
8342 gen_set_label(l3);
8343 #if defined(TARGET_PPC64)
8344 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
8345 #else
8346 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8347 #endif
8348 gen_set_label(l4);
8349 tcg_temp_free_i32(t0);
8350 #if defined(TARGET_PPC64)
8351 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
8352 tcg_temp_free(t1);
8353 tcg_temp_free(t2);
8354 #endif
8355 }
8356
8357 static void gen_evsel0(DisasContext *ctx)
8358 {
8359 gen_evsel(ctx);
8360 }
8361
8362 static void gen_evsel1(DisasContext *ctx)
8363 {
8364 gen_evsel(ctx);
8365 }
8366
8367 static void gen_evsel2(DisasContext *ctx)
8368 {
8369 gen_evsel(ctx);
8370 }
8371
8372 static void gen_evsel3(DisasContext *ctx)
8373 {
8374 gen_evsel(ctx);
8375 }
8376
8377 /* Multiply */
8378
8379 static inline void gen_evmwumi(DisasContext *ctx)
8380 {
8381 TCGv_i64 t0, t1;
8382
8383 if (unlikely(!ctx->spe_enabled)) {
8384 gen_exception(ctx, POWERPC_EXCP_SPEU);
8385 return;
8386 }
8387
8388 t0 = tcg_temp_new_i64();
8389 t1 = tcg_temp_new_i64();
8390
8391 /* t0 := rA; t1 := rB */
8392 #if defined(TARGET_PPC64)
8393 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
8394 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
8395 #else
8396 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8397 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8398 #endif
8399
8400 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8401
8402 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8403
8404 tcg_temp_free_i64(t0);
8405 tcg_temp_free_i64(t1);
8406 }
8407
8408 static inline void gen_evmwumia(DisasContext *ctx)
8409 {
8410 TCGv_i64 tmp;
8411
8412 if (unlikely(!ctx->spe_enabled)) {
8413 gen_exception(ctx, POWERPC_EXCP_SPEU);
8414 return;
8415 }
8416
8417 gen_evmwumi(ctx); /* rD := rA * rB */
8418
8419 tmp = tcg_temp_new_i64();
8420
8421 /* acc := rD */
8422 gen_load_gpr64(tmp, rD(ctx->opcode));
8423 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8424 tcg_temp_free_i64(tmp);
8425 }
8426
8427 static inline void gen_evmwumiaa(DisasContext *ctx)
8428 {
8429 TCGv_i64 acc;
8430 TCGv_i64 tmp;
8431
8432 if (unlikely(!ctx->spe_enabled)) {
8433 gen_exception(ctx, POWERPC_EXCP_SPEU);
8434 return;
8435 }
8436
8437 gen_evmwumi(ctx); /* rD := rA * rB */
8438
8439 acc = tcg_temp_new_i64();
8440 tmp = tcg_temp_new_i64();
8441
8442 /* tmp := rD */
8443 gen_load_gpr64(tmp, rD(ctx->opcode));
8444
8445 /* Load acc */
8446 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8447
8448 /* acc := tmp + acc */
8449 tcg_gen_add_i64(acc, acc, tmp);
8450
8451 /* Store acc */
8452 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8453
8454 /* rD := acc */
8455 gen_store_gpr64(rD(ctx->opcode), acc);
8456
8457 tcg_temp_free_i64(acc);
8458 tcg_temp_free_i64(tmp);
8459 }
8460
8461 static inline void gen_evmwsmi(DisasContext *ctx)
8462 {
8463 TCGv_i64 t0, t1;
8464
8465 if (unlikely(!ctx->spe_enabled)) {
8466 gen_exception(ctx, POWERPC_EXCP_SPEU);
8467 return;
8468 }
8469
8470 t0 = tcg_temp_new_i64();
8471 t1 = tcg_temp_new_i64();
8472
8473 /* t0 := rA; t1 := rB */
8474 #if defined(TARGET_PPC64)
8475 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
8476 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
8477 #else
8478 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8479 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8480 #endif
8481
8482 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8483
8484 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8485
8486 tcg_temp_free_i64(t0);
8487 tcg_temp_free_i64(t1);
8488 }
8489
8490 static inline void gen_evmwsmia(DisasContext *ctx)
8491 {
8492 TCGv_i64 tmp;
8493
8494 gen_evmwsmi(ctx); /* rD := rA * rB */
8495
8496 tmp = tcg_temp_new_i64();
8497
8498 /* acc := rD */
8499 gen_load_gpr64(tmp, rD(ctx->opcode));
8500 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8501
8502 tcg_temp_free_i64(tmp);
8503 }
8504
8505 static inline void gen_evmwsmiaa(DisasContext *ctx)
8506 {
8507 TCGv_i64 acc = tcg_temp_new_i64();
8508 TCGv_i64 tmp = tcg_temp_new_i64();
8509
8510 gen_evmwsmi(ctx); /* rD := rA * rB */
8511
8512 acc = tcg_temp_new_i64();
8513 tmp = tcg_temp_new_i64();
8514
8515 /* tmp := rD */
8516 gen_load_gpr64(tmp, rD(ctx->opcode));
8517
8518 /* Load acc */
8519 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8520
8521 /* acc := tmp + acc */
8522 tcg_gen_add_i64(acc, acc, tmp);
8523
8524 /* Store acc */
8525 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8526
8527 /* rD := acc */
8528 gen_store_gpr64(rD(ctx->opcode), acc);
8529
8530 tcg_temp_free_i64(acc);
8531 tcg_temp_free_i64(tmp);
8532 }
8533
8534 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8535 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8536 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8537 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8538 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8539 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8540 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8541 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
8542 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
8543 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8544 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8545 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8546 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8547 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8548 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8549 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8550 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8551 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8552 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8553 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
8554 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8555 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8556 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
8557 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
8558 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8559 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8560 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8561 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8562 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
8563
8564 /* SPE load and stores */
8565 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
8566 {
8567 target_ulong uimm = rB(ctx->opcode);
8568
8569 if (rA(ctx->opcode) == 0) {
8570 tcg_gen_movi_tl(EA, uimm << sh);
8571 } else {
8572 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
8573 if (NARROW_MODE(ctx)) {
8574 tcg_gen_ext32u_tl(EA, EA);
8575 }
8576 }
8577 }
8578
8579 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
8580 {
8581 #if defined(TARGET_PPC64)
8582 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8583 #else
8584 TCGv_i64 t0 = tcg_temp_new_i64();
8585 gen_qemu_ld64(ctx, t0, addr);
8586 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
8587 tcg_gen_shri_i64(t0, t0, 32);
8588 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
8589 tcg_temp_free_i64(t0);
8590 #endif
8591 }
8592
8593 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
8594 {
8595 #if defined(TARGET_PPC64)
8596 TCGv t0 = tcg_temp_new();
8597 gen_qemu_ld32u(ctx, t0, addr);
8598 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8599 gen_addr_add(ctx, addr, addr, 4);
8600 gen_qemu_ld32u(ctx, t0, addr);
8601 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8602 tcg_temp_free(t0);
8603 #else
8604 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
8605 gen_addr_add(ctx, addr, addr, 4);
8606 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8607 #endif
8608 }
8609
8610 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
8611 {
8612 TCGv t0 = tcg_temp_new();
8613 #if defined(TARGET_PPC64)
8614 gen_qemu_ld16u(ctx, t0, addr);
8615 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8616 gen_addr_add(ctx, addr, addr, 2);
8617 gen_qemu_ld16u(ctx, t0, addr);
8618 tcg_gen_shli_tl(t0, t0, 32);
8619 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8620 gen_addr_add(ctx, addr, addr, 2);
8621 gen_qemu_ld16u(ctx, t0, addr);
8622 tcg_gen_shli_tl(t0, t0, 16);
8623 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8624 gen_addr_add(ctx, addr, addr, 2);
8625 gen_qemu_ld16u(ctx, t0, addr);
8626 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8627 #else
8628 gen_qemu_ld16u(ctx, t0, addr);
8629 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8630 gen_addr_add(ctx, addr, addr, 2);
8631 gen_qemu_ld16u(ctx, t0, addr);
8632 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
8633 gen_addr_add(ctx, addr, addr, 2);
8634 gen_qemu_ld16u(ctx, t0, addr);
8635 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8636 gen_addr_add(ctx, addr, addr, 2);
8637 gen_qemu_ld16u(ctx, t0, addr);
8638 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8639 #endif
8640 tcg_temp_free(t0);
8641 }
8642
8643 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
8644 {
8645 TCGv t0 = tcg_temp_new();
8646 gen_qemu_ld16u(ctx, t0, addr);
8647 #if defined(TARGET_PPC64)
8648 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8649 tcg_gen_shli_tl(t0, t0, 16);
8650 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8651 #else
8652 tcg_gen_shli_tl(t0, t0, 16);
8653 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8654 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8655 #endif
8656 tcg_temp_free(t0);
8657 }
8658
8659 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
8660 {
8661 TCGv t0 = tcg_temp_new();
8662 gen_qemu_ld16u(ctx, t0, addr);
8663 #if defined(TARGET_PPC64)
8664 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8665 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8666 #else
8667 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8668 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8669 #endif
8670 tcg_temp_free(t0);
8671 }
8672
8673 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
8674 {
8675 TCGv t0 = tcg_temp_new();
8676 gen_qemu_ld16s(ctx, t0, addr);
8677 #if defined(TARGET_PPC64)
8678 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8679 tcg_gen_ext32u_tl(t0, t0);
8680 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8681 #else
8682 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8683 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8684 #endif
8685 tcg_temp_free(t0);
8686 }
8687
8688 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
8689 {
8690 TCGv t0 = tcg_temp_new();
8691 #if defined(TARGET_PPC64)
8692 gen_qemu_ld16u(ctx, t0, addr);
8693 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8694 gen_addr_add(ctx, addr, addr, 2);
8695 gen_qemu_ld16u(ctx, t0, addr);
8696 tcg_gen_shli_tl(t0, t0, 16);
8697 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8698 #else
8699 gen_qemu_ld16u(ctx, t0, addr);
8700 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8701 gen_addr_add(ctx, addr, addr, 2);
8702 gen_qemu_ld16u(ctx, t0, addr);
8703 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
8704 #endif
8705 tcg_temp_free(t0);
8706 }
8707
8708 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
8709 {
8710 #if defined(TARGET_PPC64)
8711 TCGv t0 = tcg_temp_new();
8712 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8713 gen_addr_add(ctx, addr, addr, 2);
8714 gen_qemu_ld16u(ctx, t0, addr);
8715 tcg_gen_shli_tl(t0, t0, 32);
8716 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8717 tcg_temp_free(t0);
8718 #else
8719 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
8720 gen_addr_add(ctx, addr, addr, 2);
8721 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8722 #endif
8723 }
8724
8725 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
8726 {
8727 #if defined(TARGET_PPC64)
8728 TCGv t0 = tcg_temp_new();
8729 gen_qemu_ld16s(ctx, t0, addr);
8730 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
8731 gen_addr_add(ctx, addr, addr, 2);
8732 gen_qemu_ld16s(ctx, t0, addr);
8733 tcg_gen_shli_tl(t0, t0, 32);
8734 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8735 tcg_temp_free(t0);
8736 #else
8737 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
8738 gen_addr_add(ctx, addr, addr, 2);
8739 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8740 #endif
8741 }
8742
8743 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
8744 {
8745 TCGv t0 = tcg_temp_new();
8746 gen_qemu_ld32u(ctx, t0, addr);
8747 #if defined(TARGET_PPC64)
8748 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8749 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8750 #else
8751 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8752 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8753 #endif
8754 tcg_temp_free(t0);
8755 }
8756
8757 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
8758 {
8759 TCGv t0 = tcg_temp_new();
8760 #if defined(TARGET_PPC64)
8761 gen_qemu_ld16u(ctx, t0, addr);
8762 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8763 tcg_gen_shli_tl(t0, t0, 32);
8764 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8765 gen_addr_add(ctx, addr, addr, 2);
8766 gen_qemu_ld16u(ctx, t0, addr);
8767 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8768 tcg_gen_shli_tl(t0, t0, 16);
8769 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8770 #else
8771 gen_qemu_ld16u(ctx, t0, addr);
8772 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8773 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
8774 gen_addr_add(ctx, addr, addr, 2);
8775 gen_qemu_ld16u(ctx, t0, addr);
8776 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
8777 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
8778 #endif
8779 tcg_temp_free(t0);
8780 }
8781
8782 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
8783 {
8784 #if defined(TARGET_PPC64)
8785 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8786 #else
8787 TCGv_i64 t0 = tcg_temp_new_i64();
8788 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
8789 gen_qemu_st64(ctx, t0, addr);
8790 tcg_temp_free_i64(t0);
8791 #endif
8792 }
8793
8794 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
8795 {
8796 #if defined(TARGET_PPC64)
8797 TCGv t0 = tcg_temp_new();
8798 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8799 gen_qemu_st32(ctx, t0, addr);
8800 tcg_temp_free(t0);
8801 #else
8802 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8803 #endif
8804 gen_addr_add(ctx, addr, addr, 4);
8805 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8806 }
8807
8808 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
8809 {
8810 TCGv t0 = tcg_temp_new();
8811 #if defined(TARGET_PPC64)
8812 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
8813 #else
8814 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
8815 #endif
8816 gen_qemu_st16(ctx, t0, addr);
8817 gen_addr_add(ctx, addr, addr, 2);
8818 #if defined(TARGET_PPC64)
8819 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8820 gen_qemu_st16(ctx, t0, addr);
8821 #else
8822 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8823 #endif
8824 gen_addr_add(ctx, addr, addr, 2);
8825 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
8826 gen_qemu_st16(ctx, t0, addr);
8827 tcg_temp_free(t0);
8828 gen_addr_add(ctx, addr, addr, 2);
8829 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8830 }
8831
8832 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
8833 {
8834 TCGv t0 = tcg_temp_new();
8835 #if defined(TARGET_PPC64)
8836 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
8837 #else
8838 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
8839 #endif
8840 gen_qemu_st16(ctx, t0, addr);
8841 gen_addr_add(ctx, addr, addr, 2);
8842 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
8843 gen_qemu_st16(ctx, t0, addr);
8844 tcg_temp_free(t0);
8845 }
8846
8847 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
8848 {
8849 #if defined(TARGET_PPC64)
8850 TCGv t0 = tcg_temp_new();
8851 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8852 gen_qemu_st16(ctx, t0, addr);
8853 tcg_temp_free(t0);
8854 #else
8855 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8856 #endif
8857 gen_addr_add(ctx, addr, addr, 2);
8858 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8859 }
8860
8861 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
8862 {
8863 #if defined(TARGET_PPC64)
8864 TCGv t0 = tcg_temp_new();
8865 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8866 gen_qemu_st32(ctx, t0, addr);
8867 tcg_temp_free(t0);
8868 #else
8869 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8870 #endif
8871 }
8872
8873 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
8874 {
8875 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8876 }
8877
8878 #define GEN_SPEOP_LDST(name, opc2, sh) \
8879 static void glue(gen_, name)(DisasContext *ctx) \
8880 { \
8881 TCGv t0; \
8882 if (unlikely(!ctx->spe_enabled)) { \
8883 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8884 return; \
8885 } \
8886 gen_set_access_type(ctx, ACCESS_INT); \
8887 t0 = tcg_temp_new(); \
8888 if (Rc(ctx->opcode)) { \
8889 gen_addr_spe_imm_index(ctx, t0, sh); \
8890 } else { \
8891 gen_addr_reg_index(ctx, t0); \
8892 } \
8893 gen_op_##name(ctx, t0); \
8894 tcg_temp_free(t0); \
8895 }
8896
8897 GEN_SPEOP_LDST(evldd, 0x00, 3);
8898 GEN_SPEOP_LDST(evldw, 0x01, 3);
8899 GEN_SPEOP_LDST(evldh, 0x02, 3);
8900 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
8901 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
8902 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
8903 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
8904 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
8905 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
8906 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
8907 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
8908
8909 GEN_SPEOP_LDST(evstdd, 0x10, 3);
8910 GEN_SPEOP_LDST(evstdw, 0x11, 3);
8911 GEN_SPEOP_LDST(evstdh, 0x12, 3);
8912 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
8913 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
8914 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
8915 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
8916
8917 /* Multiply and add - TODO */
8918 #if 0
8919 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
8920 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8921 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8922 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8923 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8924 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8925 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8926 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8927 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8928 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8929 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8930 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8931
8932 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8933 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8934 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8935 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8936 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8937 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8938 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8939 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8940 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8941 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8942 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8943 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8944
8945 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8946 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8947 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8948 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8949 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
8950
8951 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8952 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8953 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8954 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8955 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8956 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8957 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8958 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8959 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8960 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8961 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8962 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8963
8964 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8965 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8966 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8967 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8968
8969 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8970 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8971 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8972 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8973 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8974 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8975 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8976 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8977 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8978 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8979 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8980 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8981
8982 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8983 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8984 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8985 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8986 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8987 #endif
8988
8989 /*** SPE floating-point extension ***/
8990 #if defined(TARGET_PPC64)
8991 #define GEN_SPEFPUOP_CONV_32_32(name) \
8992 static inline void gen_##name(DisasContext *ctx) \
8993 { \
8994 TCGv_i32 t0; \
8995 TCGv t1; \
8996 t0 = tcg_temp_new_i32(); \
8997 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8998 gen_helper_##name(t0, cpu_env, t0); \
8999 t1 = tcg_temp_new(); \
9000 tcg_gen_extu_i32_tl(t1, t0); \
9001 tcg_temp_free_i32(t0); \
9002 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9003 0xFFFFFFFF00000000ULL); \
9004 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
9005 tcg_temp_free(t1); \
9006 }
9007 #define GEN_SPEFPUOP_CONV_32_64(name) \
9008 static inline void gen_##name(DisasContext *ctx) \
9009 { \
9010 TCGv_i32 t0; \
9011 TCGv t1; \
9012 t0 = tcg_temp_new_i32(); \
9013 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
9014 t1 = tcg_temp_new(); \
9015 tcg_gen_extu_i32_tl(t1, t0); \
9016 tcg_temp_free_i32(t0); \
9017 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9018 0xFFFFFFFF00000000ULL); \
9019 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
9020 tcg_temp_free(t1); \
9021 }
9022 #define GEN_SPEFPUOP_CONV_64_32(name) \
9023 static inline void gen_##name(DisasContext *ctx) \
9024 { \
9025 TCGv_i32 t0 = tcg_temp_new_i32(); \
9026 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9027 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
9028 tcg_temp_free_i32(t0); \
9029 }
9030 #define GEN_SPEFPUOP_CONV_64_64(name) \
9031 static inline void gen_##name(DisasContext *ctx) \
9032 { \
9033 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9034 cpu_gpr[rB(ctx->opcode)]); \
9035 }
9036 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9037 static inline void gen_##name(DisasContext *ctx) \
9038 { \
9039 TCGv_i32 t0, t1; \
9040 TCGv_i64 t2; \
9041 if (unlikely(!ctx->spe_enabled)) { \
9042 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9043 return; \
9044 } \
9045 t0 = tcg_temp_new_i32(); \
9046 t1 = tcg_temp_new_i32(); \
9047 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9048 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9049 gen_helper_##name(t0, cpu_env, t0, t1); \
9050 tcg_temp_free_i32(t1); \
9051 t2 = tcg_temp_new(); \
9052 tcg_gen_extu_i32_tl(t2, t0); \
9053 tcg_temp_free_i32(t0); \
9054 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9055 0xFFFFFFFF00000000ULL); \
9056 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
9057 tcg_temp_free(t2); \
9058 }
9059 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9060 static inline void gen_##name(DisasContext *ctx) \
9061 { \
9062 if (unlikely(!ctx->spe_enabled)) { \
9063 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9064 return; \
9065 } \
9066 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9067 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9068 }
9069 #define GEN_SPEFPUOP_COMP_32(name) \
9070 static inline void gen_##name(DisasContext *ctx) \
9071 { \
9072 TCGv_i32 t0, t1; \
9073 if (unlikely(!ctx->spe_enabled)) { \
9074 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9075 return; \
9076 } \
9077 t0 = tcg_temp_new_i32(); \
9078 t1 = tcg_temp_new_i32(); \
9079 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9080 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9081 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9082 tcg_temp_free_i32(t0); \
9083 tcg_temp_free_i32(t1); \
9084 }
9085 #define GEN_SPEFPUOP_COMP_64(name) \
9086 static inline void gen_##name(DisasContext *ctx) \
9087 { \
9088 if (unlikely(!ctx->spe_enabled)) { \
9089 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9090 return; \
9091 } \
9092 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
9093 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9094 }
9095 #else
9096 #define GEN_SPEFPUOP_CONV_32_32(name) \
9097 static inline void gen_##name(DisasContext *ctx) \
9098 { \
9099 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9100 cpu_gpr[rB(ctx->opcode)]); \
9101 }
9102 #define GEN_SPEFPUOP_CONV_32_64(name) \
9103 static inline void gen_##name(DisasContext *ctx) \
9104 { \
9105 TCGv_i64 t0 = tcg_temp_new_i64(); \
9106 gen_load_gpr64(t0, rB(ctx->opcode)); \
9107 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
9108 tcg_temp_free_i64(t0); \
9109 }
9110 #define GEN_SPEFPUOP_CONV_64_32(name) \
9111 static inline void gen_##name(DisasContext *ctx) \
9112 { \
9113 TCGv_i64 t0 = tcg_temp_new_i64(); \
9114 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
9115 gen_store_gpr64(rD(ctx->opcode), t0); \
9116 tcg_temp_free_i64(t0); \
9117 }
9118 #define GEN_SPEFPUOP_CONV_64_64(name) \
9119 static inline void gen_##name(DisasContext *ctx) \
9120 { \
9121 TCGv_i64 t0 = tcg_temp_new_i64(); \
9122 gen_load_gpr64(t0, rB(ctx->opcode)); \
9123 gen_helper_##name(t0, cpu_env, t0); \
9124 gen_store_gpr64(rD(ctx->opcode), t0); \
9125 tcg_temp_free_i64(t0); \
9126 }
9127 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9128 static inline void gen_##name(DisasContext *ctx) \
9129 { \
9130 if (unlikely(!ctx->spe_enabled)) { \
9131 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9132 return; \
9133 } \
9134 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9135 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9136 }
9137 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9138 static inline void gen_##name(DisasContext *ctx) \
9139 { \
9140 TCGv_i64 t0, t1; \
9141 if (unlikely(!ctx->spe_enabled)) { \
9142 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9143 return; \
9144 } \
9145 t0 = tcg_temp_new_i64(); \
9146 t1 = tcg_temp_new_i64(); \
9147 gen_load_gpr64(t0, rA(ctx->opcode)); \
9148 gen_load_gpr64(t1, rB(ctx->opcode)); \
9149 gen_helper_##name(t0, cpu_env, t0, t1); \
9150 gen_store_gpr64(rD(ctx->opcode), t0); \
9151 tcg_temp_free_i64(t0); \
9152 tcg_temp_free_i64(t1); \
9153 }
9154 #define GEN_SPEFPUOP_COMP_32(name) \
9155 static inline void gen_##name(DisasContext *ctx) \
9156 { \
9157 if (unlikely(!ctx->spe_enabled)) { \
9158 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9159 return; \
9160 } \
9161 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
9162 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9163 }
9164 #define GEN_SPEFPUOP_COMP_64(name) \
9165 static inline void gen_##name(DisasContext *ctx) \
9166 { \
9167 TCGv_i64 t0, t1; \
9168 if (unlikely(!ctx->spe_enabled)) { \
9169 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9170 return; \
9171 } \
9172 t0 = tcg_temp_new_i64(); \
9173 t1 = tcg_temp_new_i64(); \
9174 gen_load_gpr64(t0, rA(ctx->opcode)); \
9175 gen_load_gpr64(t1, rB(ctx->opcode)); \
9176 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9177 tcg_temp_free_i64(t0); \
9178 tcg_temp_free_i64(t1); \
9179 }
9180 #endif
9181
9182 /* Single precision floating-point vectors operations */
9183 /* Arithmetic */
9184 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9185 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9186 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9187 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9188 static inline void gen_evfsabs(DisasContext *ctx)
9189 {
9190 if (unlikely(!ctx->spe_enabled)) {
9191 gen_exception(ctx, POWERPC_EXCP_SPEU);
9192 return;
9193 }
9194 #if defined(TARGET_PPC64)
9195 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
9196 #else
9197 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
9198 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
9199 #endif
9200 }
9201 static inline void gen_evfsnabs(DisasContext *ctx)
9202 {
9203 if (unlikely(!ctx->spe_enabled)) {
9204 gen_exception(ctx, POWERPC_EXCP_SPEU);
9205 return;
9206 }
9207 #if defined(TARGET_PPC64)
9208 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
9209 #else
9210 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9211 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9212 #endif
9213 }
9214 static inline void gen_evfsneg(DisasContext *ctx)
9215 {
9216 if (unlikely(!ctx->spe_enabled)) {
9217 gen_exception(ctx, POWERPC_EXCP_SPEU);
9218 return;
9219 }
9220 #if defined(TARGET_PPC64)
9221 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
9222 #else
9223 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9224 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9225 #endif
9226 }
9227
9228 /* Conversion */
9229 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9230 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9231 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9232 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9233 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9234 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9235 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9236 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9237 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9238 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9239
9240 /* Comparison */
9241 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9242 GEN_SPEFPUOP_COMP_64(evfscmplt);
9243 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9244 GEN_SPEFPUOP_COMP_64(evfststgt);
9245 GEN_SPEFPUOP_COMP_64(evfststlt);
9246 GEN_SPEFPUOP_COMP_64(evfststeq);
9247
9248 /* Opcodes definitions */
9249 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9250 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9251 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9252 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9253 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9254 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9255 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9256 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9257 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9258 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9259 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9260 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9261 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9262 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9263
9264 /* Single precision floating-point operations */
9265 /* Arithmetic */
9266 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9267 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9268 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9269 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9270 static inline void gen_efsabs(DisasContext *ctx)
9271 {
9272 if (unlikely(!ctx->spe_enabled)) {
9273 gen_exception(ctx, POWERPC_EXCP_SPEU);
9274 return;
9275 }
9276 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9277 }
9278 static inline void gen_efsnabs(DisasContext *ctx)
9279 {
9280 if (unlikely(!ctx->spe_enabled)) {
9281 gen_exception(ctx, POWERPC_EXCP_SPEU);
9282 return;
9283 }
9284 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9285 }
9286 static inline void gen_efsneg(DisasContext *ctx)
9287 {
9288 if (unlikely(!ctx->spe_enabled)) {
9289 gen_exception(ctx, POWERPC_EXCP_SPEU);
9290 return;
9291 }
9292 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9293 }
9294
9295 /* Conversion */
9296 GEN_SPEFPUOP_CONV_32_32(efscfui);
9297 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9298 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9299 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9300 GEN_SPEFPUOP_CONV_32_32(efsctui);
9301 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9302 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9303 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9304 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9305 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9306 GEN_SPEFPUOP_CONV_32_64(efscfd);
9307
9308 /* Comparison */
9309 GEN_SPEFPUOP_COMP_32(efscmpgt);
9310 GEN_SPEFPUOP_COMP_32(efscmplt);
9311 GEN_SPEFPUOP_COMP_32(efscmpeq);
9312 GEN_SPEFPUOP_COMP_32(efststgt);
9313 GEN_SPEFPUOP_COMP_32(efststlt);
9314 GEN_SPEFPUOP_COMP_32(efststeq);
9315
9316 /* Opcodes definitions */
9317 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9318 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9319 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9320 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9321 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9322 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9323 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9324 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9325 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9326 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9327 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9328 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9329 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9330 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9331
9332 /* Double precision floating-point operations */
9333 /* Arithmetic */
9334 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9335 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9336 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9337 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9338 static inline void gen_efdabs(DisasContext *ctx)
9339 {
9340 if (unlikely(!ctx->spe_enabled)) {
9341 gen_exception(ctx, POWERPC_EXCP_SPEU);
9342 return;
9343 }
9344 #if defined(TARGET_PPC64)
9345 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
9346 #else
9347 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9348 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
9349 #endif
9350 }
9351 static inline void gen_efdnabs(DisasContext *ctx)
9352 {
9353 if (unlikely(!ctx->spe_enabled)) {
9354 gen_exception(ctx, POWERPC_EXCP_SPEU);
9355 return;
9356 }
9357 #if defined(TARGET_PPC64)
9358 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
9359 #else
9360 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9361 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9362 #endif
9363 }
9364 static inline void gen_efdneg(DisasContext *ctx)
9365 {
9366 if (unlikely(!ctx->spe_enabled)) {
9367 gen_exception(ctx, POWERPC_EXCP_SPEU);
9368 return;
9369 }
9370 #if defined(TARGET_PPC64)
9371 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
9372 #else
9373 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9374 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9375 #endif
9376 }
9377
9378 /* Conversion */
9379 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9380 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9381 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9382 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9383 GEN_SPEFPUOP_CONV_32_64(efdctui);
9384 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9385 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9386 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9387 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9388 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9389 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9390 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9391 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9392 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9393 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9394
9395 /* Comparison */
9396 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9397 GEN_SPEFPUOP_COMP_64(efdcmplt);
9398 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9399 GEN_SPEFPUOP_COMP_64(efdtstgt);
9400 GEN_SPEFPUOP_COMP_64(efdtstlt);
9401 GEN_SPEFPUOP_COMP_64(efdtsteq);
9402
9403 /* Opcodes definitions */
9404 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9405 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9406 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9407 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9408 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9409 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9410 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9411 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9412 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9413 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9414 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9415 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9416 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9417 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9418 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9419 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9420
9421 static opcode_t opcodes[] = {
9422 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9423 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9424 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9425 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9426 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9427 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9428 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9429 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9430 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9431 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9432 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9433 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9434 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9435 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9436 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9437 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9438 #if defined(TARGET_PPC64)
9439 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9440 #endif
9441 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9442 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9443 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9444 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9445 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9446 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9447 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9448 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9449 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9450 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9451 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9452 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9453 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
9454 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9455 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9456 #if defined(TARGET_PPC64)
9457 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9458 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9459 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9460 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9461 #endif
9462 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9463 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9464 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9465 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9466 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9467 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9468 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9469 #if defined(TARGET_PPC64)
9470 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9471 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9472 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9473 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9474 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9475 #endif
9476 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9477 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9478 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9479 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9480 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9481 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9482 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9483 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9484 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9485 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9486 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9487 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9488 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9489 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9490 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9491 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9492 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9493 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9494 #if defined(TARGET_PPC64)
9495 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9496 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9497 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9498 #endif
9499 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9500 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9501 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9502 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9503 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9504 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9505 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9506 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9507 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9508 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9509 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9510 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9511 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9512 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9513 #if defined(TARGET_PPC64)
9514 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9515 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9516 #endif
9517 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9518 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9519 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9520 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9521 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9522 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9523 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9524 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9525 #if defined(TARGET_PPC64)
9526 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9527 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9528 #endif
9529 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9530 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9531 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9532 #if defined(TARGET_PPC64)
9533 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9534 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9535 #endif
9536 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9537 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9538 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9539 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9540 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9541 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9542 #if defined(TARGET_PPC64)
9543 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9544 #endif
9545 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9546 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
9547 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9548 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9549 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9550 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
9551 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
9552 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9553 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9554 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9555 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9556 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9557 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9558 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9559 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9560 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9561 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9562 #if defined(TARGET_PPC64)
9563 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9564 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9565 PPC_SEGMENT_64B),
9566 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9567 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9568 PPC_SEGMENT_64B),
9569 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9570 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9571 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9572 #endif
9573 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9574 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9575 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9576 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9577 #if defined(TARGET_PPC64)
9578 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9579 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9580 #endif
9581 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9582 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9583 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9584 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9585 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9586 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9587 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9588 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9589 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9590 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9591 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9592 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9593 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9594 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9595 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9596 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9597 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9598 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9599 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9600 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9601 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9602 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9603 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9604 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9605 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9606 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9607 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9608 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9609 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9610 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9611 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9612 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9613 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9614 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9615 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9616 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9617 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9618 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9619 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9620 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
9621 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
9622 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
9623 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
9624 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
9625 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
9626 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
9627 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
9628 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
9629 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
9630 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9631 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9632 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
9633 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
9634 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9635 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9636 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
9637 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
9638 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
9639 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
9640 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
9641 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
9642 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
9643 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
9644 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
9645 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
9646 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
9647 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
9648 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
9649 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
9650 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
9651 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
9652 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
9653 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
9654 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
9655 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
9656 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
9657 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
9658 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
9659 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
9660 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
9661 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
9662 PPC_NONE, PPC2_BOOKE206),
9663 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
9664 PPC_NONE, PPC2_BOOKE206),
9665 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
9666 PPC_NONE, PPC2_BOOKE206),
9667 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
9668 PPC_NONE, PPC2_BOOKE206),
9669 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
9670 PPC_NONE, PPC2_BOOKE206),
9671 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
9672 PPC_NONE, PPC2_PRCNTL),
9673 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
9674 PPC_NONE, PPC2_PRCNTL),
9675 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
9676 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
9677 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
9678 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
9679 PPC_BOOKE, PPC2_BOOKE206),
9680 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
9681 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
9682 PPC_BOOKE, PPC2_BOOKE206),
9683 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
9684 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
9685 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
9686 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
9687 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
9688 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
9689 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
9690 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
9691 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
9692 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
9693
9694 #undef GEN_INT_ARITH_ADD
9695 #undef GEN_INT_ARITH_ADD_CONST
9696 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
9697 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
9698 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
9699 add_ca, compute_ca, compute_ov) \
9700 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
9701 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
9702 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
9703 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
9704 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
9705 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
9706 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
9707 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
9708 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
9709 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
9710 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
9711
9712 #undef GEN_INT_ARITH_DIVW
9713 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
9714 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
9715 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
9716 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
9717 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
9718 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
9719 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9720 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9721 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9722 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9723
9724 #if defined(TARGET_PPC64)
9725 #undef GEN_INT_ARITH_DIVD
9726 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
9727 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9728 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
9729 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
9730 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
9731 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
9732
9733 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9734 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9735 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9736 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9737
9738 #undef GEN_INT_ARITH_MUL_HELPER
9739 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
9740 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9741 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
9742 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
9743 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
9744 #endif
9745
9746 #undef GEN_INT_ARITH_SUBF
9747 #undef GEN_INT_ARITH_SUBF_CONST
9748 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
9749 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
9750 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
9751 add_ca, compute_ca, compute_ov) \
9752 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
9753 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
9754 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
9755 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
9756 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
9757 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
9758 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
9759 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
9760 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
9761 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
9762 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
9763
9764 #undef GEN_LOGICAL1
9765 #undef GEN_LOGICAL2
9766 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
9767 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
9768 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
9769 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
9770 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
9771 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
9772 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
9773 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
9774 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
9775 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
9776 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
9777 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
9778 #if defined(TARGET_PPC64)
9779 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
9780 #endif
9781
9782 #if defined(TARGET_PPC64)
9783 #undef GEN_PPC64_R2
9784 #undef GEN_PPC64_R4
9785 #define GEN_PPC64_R2(name, opc1, opc2) \
9786 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9787 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9788 PPC_64B)
9789 #define GEN_PPC64_R4(name, opc1, opc2) \
9790 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9791 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
9792 PPC_64B), \
9793 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9794 PPC_64B), \
9795 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
9796 PPC_64B)
9797 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
9798 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
9799 GEN_PPC64_R4(rldic, 0x1E, 0x04),
9800 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
9801 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
9802 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
9803 #endif
9804
9805 #undef _GEN_FLOAT_ACB
9806 #undef GEN_FLOAT_ACB
9807 #undef _GEN_FLOAT_AB
9808 #undef GEN_FLOAT_AB
9809 #undef _GEN_FLOAT_AC
9810 #undef GEN_FLOAT_AC
9811 #undef GEN_FLOAT_B
9812 #undef GEN_FLOAT_BS
9813 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
9814 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
9815 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
9816 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
9817 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
9818 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
9819 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
9820 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
9821 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
9822 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
9823 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
9824 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
9825 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
9826 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
9827 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
9828 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
9829 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
9830 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
9831 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
9832
9833 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
9834 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
9835 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
9836 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
9837 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
9838 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
9839 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
9840 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
9841 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
9842 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
9843 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
9844 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
9845 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
9846 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
9847 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
9848 #if defined(TARGET_PPC64)
9849 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
9850 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
9851 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
9852 #endif
9853 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
9854 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
9855 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
9856 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
9857
9858 #undef GEN_LD
9859 #undef GEN_LDU
9860 #undef GEN_LDUX
9861 #undef GEN_LDX_E
9862 #undef GEN_LDS
9863 #define GEN_LD(name, ldop, opc, type) \
9864 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9865 #define GEN_LDU(name, ldop, opc, type) \
9866 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9867 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
9868 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
9869 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
9870 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
9871 #define GEN_LDS(name, ldop, op, type) \
9872 GEN_LD(name, ldop, op | 0x20, type) \
9873 GEN_LDU(name, ldop, op | 0x21, type) \
9874 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
9875 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
9876
9877 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
9878 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
9879 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
9880 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
9881 #if defined(TARGET_PPC64)
9882 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
9883 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
9884 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
9885 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
9886 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
9887 #endif
9888 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
9889 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
9890
9891 #undef GEN_ST
9892 #undef GEN_STU
9893 #undef GEN_STUX
9894 #undef GEN_STX_E
9895 #undef GEN_STS
9896 #define GEN_ST(name, stop, opc, type) \
9897 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9898 #define GEN_STU(name, stop, opc, type) \
9899 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
9900 #define GEN_STUX(name, stop, opc2, opc3, type) \
9901 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
9902 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
9903 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
9904 #define GEN_STS(name, stop, op, type) \
9905 GEN_ST(name, stop, op | 0x20, type) \
9906 GEN_STU(name, stop, op | 0x21, type) \
9907 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
9908 GEN_STX(name, stop, 0x17, op | 0x00, type)
9909
9910 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
9911 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
9912 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
9913 #if defined(TARGET_PPC64)
9914 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
9915 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
9916 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
9917 #endif
9918 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
9919 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
9920
9921 #undef GEN_LDF
9922 #undef GEN_LDUF
9923 #undef GEN_LDUXF
9924 #undef GEN_LDXF
9925 #undef GEN_LDFS
9926 #define GEN_LDF(name, ldop, opc, type) \
9927 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9928 #define GEN_LDUF(name, ldop, opc, type) \
9929 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9930 #define GEN_LDUXF(name, ldop, opc, type) \
9931 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9932 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
9933 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9934 #define GEN_LDFS(name, ldop, op, type) \
9935 GEN_LDF(name, ldop, op | 0x20, type) \
9936 GEN_LDUF(name, ldop, op | 0x21, type) \
9937 GEN_LDUXF(name, ldop, op | 0x01, type) \
9938 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
9939
9940 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
9941 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
9942 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
9943 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
9944 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
9945
9946 #undef GEN_STF
9947 #undef GEN_STUF
9948 #undef GEN_STUXF
9949 #undef GEN_STXF
9950 #undef GEN_STFS
9951 #define GEN_STF(name, stop, opc, type) \
9952 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9953 #define GEN_STUF(name, stop, opc, type) \
9954 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9955 #define GEN_STUXF(name, stop, opc, type) \
9956 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9957 #define GEN_STXF(name, stop, opc2, opc3, type) \
9958 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9959 #define GEN_STFS(name, stop, op, type) \
9960 GEN_STF(name, stop, op | 0x20, type) \
9961 GEN_STUF(name, stop, op | 0x21, type) \
9962 GEN_STUXF(name, stop, op | 0x01, type) \
9963 GEN_STXF(name, stop, 0x17, op | 0x00, type)
9964
9965 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
9966 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
9967 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
9968 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
9969 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
9970
9971 #undef GEN_CRLOGIC
9972 #define GEN_CRLOGIC(name, tcg_op, opc) \
9973 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
9974 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
9975 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
9976 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
9977 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
9978 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
9979 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
9980 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
9981 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
9982
9983 #undef GEN_MAC_HANDLER
9984 #define GEN_MAC_HANDLER(name, opc2, opc3) \
9985 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
9986 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
9987 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
9988 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
9989 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
9990 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
9991 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
9992 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
9993 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
9994 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
9995 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
9996 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
9997 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
9998 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
9999 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10000 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10001 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10002 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10003 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10004 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10005 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10006 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10007 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10008 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10009 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10010 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10011 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10012 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10013 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10014 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10015 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10016 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10017 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10018 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10019 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10020 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10021 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10022 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10023 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10024 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10025 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10026 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10027 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10028
10029 #undef GEN_VR_LDX
10030 #undef GEN_VR_STX
10031 #undef GEN_VR_LVE
10032 #undef GEN_VR_STVE
10033 #define GEN_VR_LDX(name, opc2, opc3) \
10034 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10035 #define GEN_VR_STX(name, opc2, opc3) \
10036 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10037 #define GEN_VR_LVE(name, opc2, opc3) \
10038 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10039 #define GEN_VR_STVE(name, opc2, opc3) \
10040 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10041 GEN_VR_LDX(lvx, 0x07, 0x03),
10042 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10043 GEN_VR_LVE(bx, 0x07, 0x00),
10044 GEN_VR_LVE(hx, 0x07, 0x01),
10045 GEN_VR_LVE(wx, 0x07, 0x02),
10046 GEN_VR_STX(svx, 0x07, 0x07),
10047 GEN_VR_STX(svxl, 0x07, 0x0F),
10048 GEN_VR_STVE(bx, 0x07, 0x04),
10049 GEN_VR_STVE(hx, 0x07, 0x05),
10050 GEN_VR_STVE(wx, 0x07, 0x06),
10051
10052 #undef GEN_VX_LOGICAL
10053 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10054 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10055 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10056 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10057 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10058 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10059 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10060
10061 #undef GEN_VXFORM
10062 #define GEN_VXFORM(name, opc2, opc3) \
10063 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10064 GEN_VXFORM(vaddubm, 0, 0),
10065 GEN_VXFORM(vadduhm, 0, 1),
10066 GEN_VXFORM(vadduwm, 0, 2),
10067 GEN_VXFORM(vsububm, 0, 16),
10068 GEN_VXFORM(vsubuhm, 0, 17),
10069 GEN_VXFORM(vsubuwm, 0, 18),
10070 GEN_VXFORM(vmaxub, 1, 0),
10071 GEN_VXFORM(vmaxuh, 1, 1),
10072 GEN_VXFORM(vmaxuw, 1, 2),
10073 GEN_VXFORM(vmaxsb, 1, 4),
10074 GEN_VXFORM(vmaxsh, 1, 5),
10075 GEN_VXFORM(vmaxsw, 1, 6),
10076 GEN_VXFORM(vminub, 1, 8),
10077 GEN_VXFORM(vminuh, 1, 9),
10078 GEN_VXFORM(vminuw, 1, 10),
10079 GEN_VXFORM(vminsb, 1, 12),
10080 GEN_VXFORM(vminsh, 1, 13),
10081 GEN_VXFORM(vminsw, 1, 14),
10082 GEN_VXFORM(vavgub, 1, 16),
10083 GEN_VXFORM(vavguh, 1, 17),
10084 GEN_VXFORM(vavguw, 1, 18),
10085 GEN_VXFORM(vavgsb, 1, 20),
10086 GEN_VXFORM(vavgsh, 1, 21),
10087 GEN_VXFORM(vavgsw, 1, 22),
10088 GEN_VXFORM(vmrghb, 6, 0),
10089 GEN_VXFORM(vmrghh, 6, 1),
10090 GEN_VXFORM(vmrghw, 6, 2),
10091 GEN_VXFORM(vmrglb, 6, 4),
10092 GEN_VXFORM(vmrglh, 6, 5),
10093 GEN_VXFORM(vmrglw, 6, 6),
10094 GEN_VXFORM(vmuloub, 4, 0),
10095 GEN_VXFORM(vmulouh, 4, 1),
10096 GEN_VXFORM(vmulosb, 4, 4),
10097 GEN_VXFORM(vmulosh, 4, 5),
10098 GEN_VXFORM(vmuleub, 4, 8),
10099 GEN_VXFORM(vmuleuh, 4, 9),
10100 GEN_VXFORM(vmulesb, 4, 12),
10101 GEN_VXFORM(vmulesh, 4, 13),
10102 GEN_VXFORM(vslb, 2, 4),
10103 GEN_VXFORM(vslh, 2, 5),
10104 GEN_VXFORM(vslw, 2, 6),
10105 GEN_VXFORM(vsrb, 2, 8),
10106 GEN_VXFORM(vsrh, 2, 9),
10107 GEN_VXFORM(vsrw, 2, 10),
10108 GEN_VXFORM(vsrab, 2, 12),
10109 GEN_VXFORM(vsrah, 2, 13),
10110 GEN_VXFORM(vsraw, 2, 14),
10111 GEN_VXFORM(vslo, 6, 16),
10112 GEN_VXFORM(vsro, 6, 17),
10113 GEN_VXFORM(vaddcuw, 0, 6),
10114 GEN_VXFORM(vsubcuw, 0, 22),
10115 GEN_VXFORM(vaddubs, 0, 8),
10116 GEN_VXFORM(vadduhs, 0, 9),
10117 GEN_VXFORM(vadduws, 0, 10),
10118 GEN_VXFORM(vaddsbs, 0, 12),
10119 GEN_VXFORM(vaddshs, 0, 13),
10120 GEN_VXFORM(vaddsws, 0, 14),
10121 GEN_VXFORM(vsububs, 0, 24),
10122 GEN_VXFORM(vsubuhs, 0, 25),
10123 GEN_VXFORM(vsubuws, 0, 26),
10124 GEN_VXFORM(vsubsbs, 0, 28),
10125 GEN_VXFORM(vsubshs, 0, 29),
10126 GEN_VXFORM(vsubsws, 0, 30),
10127 GEN_VXFORM(vrlb, 2, 0),
10128 GEN_VXFORM(vrlh, 2, 1),
10129 GEN_VXFORM(vrlw, 2, 2),
10130 GEN_VXFORM(vsl, 2, 7),
10131 GEN_VXFORM(vsr, 2, 11),
10132 GEN_VXFORM(vpkuhum, 7, 0),
10133 GEN_VXFORM(vpkuwum, 7, 1),
10134 GEN_VXFORM(vpkuhus, 7, 2),
10135 GEN_VXFORM(vpkuwus, 7, 3),
10136 GEN_VXFORM(vpkshus, 7, 4),
10137 GEN_VXFORM(vpkswus, 7, 5),
10138 GEN_VXFORM(vpkshss, 7, 6),
10139 GEN_VXFORM(vpkswss, 7, 7),
10140 GEN_VXFORM(vpkpx, 7, 12),
10141 GEN_VXFORM(vsum4ubs, 4, 24),
10142 GEN_VXFORM(vsum4sbs, 4, 28),
10143 GEN_VXFORM(vsum4shs, 4, 25),
10144 GEN_VXFORM(vsum2sws, 4, 26),
10145 GEN_VXFORM(vsumsws, 4, 30),
10146 GEN_VXFORM(vaddfp, 5, 0),
10147 GEN_VXFORM(vsubfp, 5, 1),
10148 GEN_VXFORM(vmaxfp, 5, 16),
10149 GEN_VXFORM(vminfp, 5, 17),
10150
10151 #undef GEN_VXRFORM1
10152 #undef GEN_VXRFORM
10153 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10154 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10155 #define GEN_VXRFORM(name, opc2, opc3) \
10156 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10157 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10158 GEN_VXRFORM(vcmpequb, 3, 0)
10159 GEN_VXRFORM(vcmpequh, 3, 1)
10160 GEN_VXRFORM(vcmpequw, 3, 2)
10161 GEN_VXRFORM(vcmpgtsb, 3, 12)
10162 GEN_VXRFORM(vcmpgtsh, 3, 13)
10163 GEN_VXRFORM(vcmpgtsw, 3, 14)
10164 GEN_VXRFORM(vcmpgtub, 3, 8)
10165 GEN_VXRFORM(vcmpgtuh, 3, 9)
10166 GEN_VXRFORM(vcmpgtuw, 3, 10)
10167 GEN_VXRFORM(vcmpeqfp, 3, 3)
10168 GEN_VXRFORM(vcmpgefp, 3, 7)
10169 GEN_VXRFORM(vcmpgtfp, 3, 11)
10170 GEN_VXRFORM(vcmpbfp, 3, 15)
10171
10172 #undef GEN_VXFORM_SIMM
10173 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10174 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10175 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10176 GEN_VXFORM_SIMM(vspltish, 6, 13),
10177 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10178
10179 #undef GEN_VXFORM_NOA
10180 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10181 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10182 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10183 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10184 GEN_VXFORM_NOA(vupklsb, 7, 10),
10185 GEN_VXFORM_NOA(vupklsh, 7, 11),
10186 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10187 GEN_VXFORM_NOA(vupklpx, 7, 15),
10188 GEN_VXFORM_NOA(vrefp, 5, 4),
10189 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10190 GEN_VXFORM_NOA(vexptefp, 5, 6),
10191 GEN_VXFORM_NOA(vlogefp, 5, 7),
10192 GEN_VXFORM_NOA(vrfim, 5, 8),
10193 GEN_VXFORM_NOA(vrfin, 5, 9),
10194 GEN_VXFORM_NOA(vrfip, 5, 10),
10195 GEN_VXFORM_NOA(vrfiz, 5, 11),
10196
10197 #undef GEN_VXFORM_UIMM
10198 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10199 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10200 GEN_VXFORM_UIMM(vspltb, 6, 8),
10201 GEN_VXFORM_UIMM(vsplth, 6, 9),
10202 GEN_VXFORM_UIMM(vspltw, 6, 10),
10203 GEN_VXFORM_UIMM(vcfux, 5, 12),
10204 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10205 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10206 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10207
10208 #undef GEN_VAFORM_PAIRED
10209 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10210 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10211 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10212 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10213 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10214 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10215 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10216 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10217
10218 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10219 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10220 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10221 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10222 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10223 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10224 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10225
10226 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10227 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10228 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10229 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10230 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10231
10232 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10233 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10234 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10235 #if defined(TARGET_PPC64)
10236 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10237 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10238 #endif
10239
10240 #undef GEN_XX2FORM
10241 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10242 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10243 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10244
10245 #undef GEN_XX3FORM
10246 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10247 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10248 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10249 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10250 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10251
10252 #undef GEN_XX3_RC_FORM
10253 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10254 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10255 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10256 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10257 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10258 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10259 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10260 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10261 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10262
10263 #undef GEN_XX3FORM_DM
10264 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10265 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10266 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10267 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10268 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10269 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10270 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10271 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10272 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10273 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10274 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10275 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10276 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10277 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10278 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10279 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10280 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10281
10282 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10283 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10284 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10285 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10286
10287 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10288 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10289 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10290 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10291 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10292 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10293 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10294 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10295
10296 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10297 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10298 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10299 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10300 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10301 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10302 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10303 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10304 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10305 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10306 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10307 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10308 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10309 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10310 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10311 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10312 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10313 GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10314 GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10315 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10316 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10317 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10318 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10319 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10320 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10321 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10322 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10323 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10324 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10325 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10326 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10327 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10328 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10329 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10330 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10331 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10332
10333 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10334 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10335 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10336 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10337 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10338 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10339 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10340 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10341 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10342 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10343 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10344 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10345 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10346 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10347 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10348 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10349 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10350 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10351
10352 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10353 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10354 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10355 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10356 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10357 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10358 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10359 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10360 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10361 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10362 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10363 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10364 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10365 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10366 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10367 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10368 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10369 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10370 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10371 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10372 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10373 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10374 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10375 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10376 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10377 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10378 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10379 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10380 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10381 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10382 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10383 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10384 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10385 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10386 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10387 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10388
10389 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10390 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10391 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10392 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10393 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10394 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10395 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10396 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10397 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10398 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10399 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10400 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10401 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10402 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10403 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10404 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10405 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10406 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10407 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10408 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10409 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10410 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10411 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10412 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10413 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10414 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10415 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10416 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10417 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10418 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10419 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10420 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10421 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10422 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10423 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10424 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10425
10426 #undef VSX_LOGICAL
10427 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10428 GEN_XX3FORM(name, opc2, opc3, fl2)
10429
10430 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10431 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10432 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10433 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10434 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10435 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10436 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10437 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10438 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10439 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10440 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10441 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10442
10443 #define GEN_XXSEL_ROW(opc3) \
10444 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10445 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10446 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10447 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10448 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10449 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10450 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10451 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10452
10453 GEN_XXSEL_ROW(0x00)
10454 GEN_XXSEL_ROW(0x01)
10455 GEN_XXSEL_ROW(0x02)
10456 GEN_XXSEL_ROW(0x03)
10457 GEN_XXSEL_ROW(0x04)
10458 GEN_XXSEL_ROW(0x05)
10459 GEN_XXSEL_ROW(0x06)
10460 GEN_XXSEL_ROW(0x07)
10461 GEN_XXSEL_ROW(0x08)
10462 GEN_XXSEL_ROW(0x09)
10463 GEN_XXSEL_ROW(0x0A)
10464 GEN_XXSEL_ROW(0x0B)
10465 GEN_XXSEL_ROW(0x0C)
10466 GEN_XXSEL_ROW(0x0D)
10467 GEN_XXSEL_ROW(0x0E)
10468 GEN_XXSEL_ROW(0x0F)
10469 GEN_XXSEL_ROW(0x10)
10470 GEN_XXSEL_ROW(0x11)
10471 GEN_XXSEL_ROW(0x12)
10472 GEN_XXSEL_ROW(0x13)
10473 GEN_XXSEL_ROW(0x14)
10474 GEN_XXSEL_ROW(0x15)
10475 GEN_XXSEL_ROW(0x16)
10476 GEN_XXSEL_ROW(0x17)
10477 GEN_XXSEL_ROW(0x18)
10478 GEN_XXSEL_ROW(0x19)
10479 GEN_XXSEL_ROW(0x1A)
10480 GEN_XXSEL_ROW(0x1B)
10481 GEN_XXSEL_ROW(0x1C)
10482 GEN_XXSEL_ROW(0x1D)
10483 GEN_XXSEL_ROW(0x1E)
10484 GEN_XXSEL_ROW(0x1F)
10485
10486 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10487
10488 #undef GEN_SPE
10489 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
10490 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
10491 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10492 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10493 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10494 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10495 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10496 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10497 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10498 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
10499 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
10500 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10501 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10502 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10503 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10504 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10505 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10506 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
10507 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10508 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10509 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10510 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10511 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10512 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10513 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10514 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10515 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10516 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10517 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10518 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10519 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
10520
10521 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10522 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10523 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10524 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10525 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10526 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10527 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10528 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10529 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10530 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10531 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10532 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10533 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10534 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10535
10536 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10537 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10538 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10539 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10540 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10541 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
10542 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10543 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10544 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10545 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10546 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10547 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10548 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10549 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10550
10551 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
10552 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10553 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
10554 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10555 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
10556 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10557 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
10558 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
10559 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10560 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10561 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10562 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10563 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10564 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10565 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
10566 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10567
10568 #undef GEN_SPEOP_LDST
10569 #define GEN_SPEOP_LDST(name, opc2, sh) \
10570 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
10571 GEN_SPEOP_LDST(evldd, 0x00, 3),
10572 GEN_SPEOP_LDST(evldw, 0x01, 3),
10573 GEN_SPEOP_LDST(evldh, 0x02, 3),
10574 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
10575 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
10576 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
10577 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
10578 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
10579 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
10580 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
10581 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
10582
10583 GEN_SPEOP_LDST(evstdd, 0x10, 3),
10584 GEN_SPEOP_LDST(evstdw, 0x11, 3),
10585 GEN_SPEOP_LDST(evstdh, 0x12, 3),
10586 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
10587 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
10588 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
10589 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
10590 };
10591
10592 #include "helper_regs.h"
10593 #include "translate_init.c"
10594
10595 /*****************************************************************************/
10596 /* Misc PowerPC helpers */
10597 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
10598 int flags)
10599 {
10600 #define RGPL 4
10601 #define RFPL 4
10602
10603 PowerPCCPU *cpu = POWERPC_CPU(cs);
10604 CPUPPCState *env = &cpu->env;
10605 int i;
10606
10607 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
10608 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
10609 env->nip, env->lr, env->ctr, cpu_read_xer(env));
10610 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
10611 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
10612 env->hflags, env->mmu_idx);
10613 #if !defined(NO_TIMER_DUMP)
10614 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
10615 #if !defined(CONFIG_USER_ONLY)
10616 " DECR %08" PRIu32
10617 #endif
10618 "\n",
10619 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
10620 #if !defined(CONFIG_USER_ONLY)
10621 , cpu_ppc_load_decr(env)
10622 #endif
10623 );
10624 #endif
10625 for (i = 0; i < 32; i++) {
10626 if ((i & (RGPL - 1)) == 0)
10627 cpu_fprintf(f, "GPR%02d", i);
10628 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
10629 if ((i & (RGPL - 1)) == (RGPL - 1))
10630 cpu_fprintf(f, "\n");
10631 }
10632 cpu_fprintf(f, "CR ");
10633 for (i = 0; i < 8; i++)
10634 cpu_fprintf(f, "%01x", env->crf[i]);
10635 cpu_fprintf(f, " [");
10636 for (i = 0; i < 8; i++) {
10637 char a = '-';
10638 if (env->crf[i] & 0x08)
10639 a = 'L';
10640 else if (env->crf[i] & 0x04)
10641 a = 'G';
10642 else if (env->crf[i] & 0x02)
10643 a = 'E';
10644 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
10645 }
10646 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
10647 env->reserve_addr);
10648 for (i = 0; i < 32; i++) {
10649 if ((i & (RFPL - 1)) == 0)
10650 cpu_fprintf(f, "FPR%02d", i);
10651 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
10652 if ((i & (RFPL - 1)) == (RFPL - 1))
10653 cpu_fprintf(f, "\n");
10654 }
10655 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
10656 #if !defined(CONFIG_USER_ONLY)
10657 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
10658 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
10659 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
10660 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
10661
10662 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
10663 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
10664 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
10665 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
10666
10667 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
10668 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
10669 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
10670 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
10671
10672 if (env->excp_model == POWERPC_EXCP_BOOKE) {
10673 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
10674 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
10675 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
10676 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
10677
10678 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
10679 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
10680 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
10681 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
10682
10683 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
10684 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
10685 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
10686 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
10687
10688 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
10689 " EPR " TARGET_FMT_lx "\n",
10690 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
10691 env->spr[SPR_BOOKE_EPR]);
10692
10693 /* FSL-specific */
10694 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
10695 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
10696 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
10697 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
10698
10699 /*
10700 * IVORs are left out as they are large and do not change often --
10701 * they can be read with "p $ivor0", "p $ivor1", etc.
10702 */
10703 }
10704
10705 #if defined(TARGET_PPC64)
10706 if (env->flags & POWERPC_FLAG_CFAR) {
10707 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
10708 }
10709 #endif
10710
10711 switch (env->mmu_model) {
10712 case POWERPC_MMU_32B:
10713 case POWERPC_MMU_601:
10714 case POWERPC_MMU_SOFT_6xx:
10715 case POWERPC_MMU_SOFT_74xx:
10716 #if defined(TARGET_PPC64)
10717 case POWERPC_MMU_64B:
10718 case POWERPC_MMU_2_06:
10719 case POWERPC_MMU_2_06a:
10720 case POWERPC_MMU_2_06d:
10721 #endif
10722 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
10723 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
10724 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
10725 break;
10726 case POWERPC_MMU_BOOKE206:
10727 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
10728 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
10729 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
10730 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
10731
10732 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
10733 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
10734 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
10735 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
10736
10737 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
10738 " TLB1CFG " TARGET_FMT_lx "\n",
10739 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
10740 env->spr[SPR_BOOKE_TLB1CFG]);
10741 break;
10742 default:
10743 break;
10744 }
10745 #endif
10746
10747 #undef RGPL
10748 #undef RFPL
10749 }
10750
10751 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
10752 fprintf_function cpu_fprintf, int flags)
10753 {
10754 #if defined(DO_PPC_STATISTICS)
10755 PowerPCCPU *cpu = POWERPC_CPU(cs);
10756 opc_handler_t **t1, **t2, **t3, *handler;
10757 int op1, op2, op3;
10758
10759 t1 = cpu->env.opcodes;
10760 for (op1 = 0; op1 < 64; op1++) {
10761 handler = t1[op1];
10762 if (is_indirect_opcode(handler)) {
10763 t2 = ind_table(handler);
10764 for (op2 = 0; op2 < 32; op2++) {
10765 handler = t2[op2];
10766 if (is_indirect_opcode(handler)) {
10767 t3 = ind_table(handler);
10768 for (op3 = 0; op3 < 32; op3++) {
10769 handler = t3[op3];
10770 if (handler->count == 0)
10771 continue;
10772 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
10773 "%016" PRIx64 " %" PRId64 "\n",
10774 op1, op2, op3, op1, (op3 << 5) | op2,
10775 handler->oname,
10776 handler->count, handler->count);
10777 }
10778 } else {
10779 if (handler->count == 0)
10780 continue;
10781 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
10782 "%016" PRIx64 " %" PRId64 "\n",
10783 op1, op2, op1, op2, handler->oname,
10784 handler->count, handler->count);
10785 }
10786 }
10787 } else {
10788 if (handler->count == 0)
10789 continue;
10790 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
10791 " %" PRId64 "\n",
10792 op1, op1, handler->oname,
10793 handler->count, handler->count);
10794 }
10795 }
10796 #endif
10797 }
10798
10799 /*****************************************************************************/
10800 static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
10801 TranslationBlock *tb,
10802 bool search_pc)
10803 {
10804 CPUState *cs = CPU(cpu);
10805 CPUPPCState *env = &cpu->env;
10806 DisasContext ctx, *ctxp = &ctx;
10807 opc_handler_t **table, *handler;
10808 target_ulong pc_start;
10809 uint16_t *gen_opc_end;
10810 CPUBreakpoint *bp;
10811 int j, lj = -1;
10812 int num_insns;
10813 int max_insns;
10814
10815 pc_start = tb->pc;
10816 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
10817 ctx.nip = pc_start;
10818 ctx.tb = tb;
10819 ctx.exception = POWERPC_EXCP_NONE;
10820 ctx.spr_cb = env->spr_cb;
10821 ctx.mem_idx = env->mmu_idx;
10822 ctx.insns_flags = env->insns_flags;
10823 ctx.insns_flags2 = env->insns_flags2;
10824 ctx.access_type = -1;
10825 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
10826 #if defined(TARGET_PPC64)
10827 ctx.sf_mode = msr_is_64bit(env, env->msr);
10828 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
10829 #endif
10830 ctx.fpu_enabled = msr_fp;
10831 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
10832 ctx.spe_enabled = msr_spe;
10833 else
10834 ctx.spe_enabled = 0;
10835 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
10836 ctx.altivec_enabled = msr_vr;
10837 else
10838 ctx.altivec_enabled = 0;
10839 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
10840 ctx.vsx_enabled = msr_vsx;
10841 } else {
10842 ctx.vsx_enabled = 0;
10843 }
10844 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
10845 ctx.singlestep_enabled = CPU_SINGLE_STEP;
10846 else
10847 ctx.singlestep_enabled = 0;
10848 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
10849 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
10850 if (unlikely(cs->singlestep_enabled)) {
10851 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
10852 }
10853 #if defined (DO_SINGLE_STEP) && 0
10854 /* Single step trace mode */
10855 msr_se = 1;
10856 #endif
10857 num_insns = 0;
10858 max_insns = tb->cflags & CF_COUNT_MASK;
10859 if (max_insns == 0)
10860 max_insns = CF_COUNT_MASK;
10861
10862 gen_tb_start();
10863 /* Set env in case of segfault during code fetch */
10864 while (ctx.exception == POWERPC_EXCP_NONE
10865 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
10866 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
10867 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
10868 if (bp->pc == ctx.nip) {
10869 gen_debug_exception(ctxp);
10870 break;
10871 }
10872 }
10873 }
10874 if (unlikely(search_pc)) {
10875 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
10876 if (lj < j) {
10877 lj++;
10878 while (lj < j)
10879 tcg_ctx.gen_opc_instr_start[lj++] = 0;
10880 }
10881 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
10882 tcg_ctx.gen_opc_instr_start[lj] = 1;
10883 tcg_ctx.gen_opc_icount[lj] = num_insns;
10884 }
10885 LOG_DISAS("----------------\n");
10886 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
10887 ctx.nip, ctx.mem_idx, (int)msr_ir);
10888 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
10889 gen_io_start();
10890 if (unlikely(ctx.le_mode)) {
10891 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
10892 } else {
10893 ctx.opcode = cpu_ldl_code(env, ctx.nip);
10894 }
10895 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
10896 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
10897 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
10898 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
10899 tcg_gen_debug_insn_start(ctx.nip);
10900 }
10901 ctx.nip += 4;
10902 table = env->opcodes;
10903 num_insns++;
10904 handler = table[opc1(ctx.opcode)];
10905 if (is_indirect_opcode(handler)) {
10906 table = ind_table(handler);
10907 handler = table[opc2(ctx.opcode)];
10908 if (is_indirect_opcode(handler)) {
10909 table = ind_table(handler);
10910 handler = table[opc3(ctx.opcode)];
10911 }
10912 }
10913 /* Is opcode *REALLY* valid ? */
10914 if (unlikely(handler->handler == &gen_invalid)) {
10915 if (qemu_log_enabled()) {
10916 qemu_log("invalid/unsupported opcode: "
10917 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
10918 opc1(ctx.opcode), opc2(ctx.opcode),
10919 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
10920 }
10921 } else {
10922 uint32_t inval;
10923
10924 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
10925 inval = handler->inval2;
10926 } else {
10927 inval = handler->inval1;
10928 }
10929
10930 if (unlikely((ctx.opcode & inval) != 0)) {
10931 if (qemu_log_enabled()) {
10932 qemu_log("invalid bits: %08x for opcode: "
10933 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
10934 ctx.opcode & inval, opc1(ctx.opcode),
10935 opc2(ctx.opcode), opc3(ctx.opcode),
10936 ctx.opcode, ctx.nip - 4);
10937 }
10938 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
10939 break;
10940 }
10941 }
10942 (*(handler->handler))(&ctx);
10943 #if defined(DO_PPC_STATISTICS)
10944 handler->count++;
10945 #endif
10946 /* Check trace mode exceptions */
10947 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
10948 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
10949 ctx.exception != POWERPC_SYSCALL &&
10950 ctx.exception != POWERPC_EXCP_TRAP &&
10951 ctx.exception != POWERPC_EXCP_BRANCH)) {
10952 gen_exception(ctxp, POWERPC_EXCP_TRACE);
10953 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
10954 (cs->singlestep_enabled) ||
10955 singlestep ||
10956 num_insns >= max_insns)) {
10957 /* if we reach a page boundary or are single stepping, stop
10958 * generation
10959 */
10960 break;
10961 }
10962 }
10963 if (tb->cflags & CF_LAST_IO)
10964 gen_io_end();
10965 if (ctx.exception == POWERPC_EXCP_NONE) {
10966 gen_goto_tb(&ctx, 0, ctx.nip);
10967 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
10968 if (unlikely(cs->singlestep_enabled)) {
10969 gen_debug_exception(ctxp);
10970 }
10971 /* Generate the return instruction */
10972 tcg_gen_exit_tb(0);
10973 }
10974 gen_tb_end(tb, num_insns);
10975 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
10976 if (unlikely(search_pc)) {
10977 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
10978 lj++;
10979 while (lj <= j)
10980 tcg_ctx.gen_opc_instr_start[lj++] = 0;
10981 } else {
10982 tb->size = ctx.nip - pc_start;
10983 tb->icount = num_insns;
10984 }
10985 #if defined(DEBUG_DISAS)
10986 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
10987 int flags;
10988 flags = env->bfd_mach;
10989 flags |= ctx.le_mode << 16;
10990 qemu_log("IN: %s\n", lookup_symbol(pc_start));
10991 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
10992 qemu_log("\n");
10993 }
10994 #endif
10995 }
10996
10997 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
10998 {
10999 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false);
11000 }
11001
11002 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
11003 {
11004 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true);
11005 }
11006
11007 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
11008 {
11009 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
11010 }
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