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Merge remote-tracking branch 'afaerber/qom-cpu.v5' into staging
[mirror_qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas.h"
23 #include "tcg-op.h"
24 #include "host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i32 cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_msr;
64 static TCGv cpu_ctr;
65 static TCGv cpu_lr;
66 #if defined(TARGET_PPC64)
67 static TCGv cpu_cfar;
68 #endif
69 static TCGv cpu_xer;
70 static TCGv cpu_reserve;
71 static TCGv_i32 cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111 #endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154 #if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157 #endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161
162 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
163 offsetof(CPUPPCState, reserve_addr),
164 "reserve_addr");
165
166 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
167 offsetof(CPUPPCState, fpscr), "fpscr");
168
169 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
170 offsetof(CPUPPCState, access_type), "access_type");
171
172 /* register helpers */
173 #define GEN_HELPER 2
174 #include "helper.h"
175
176 done_init = 1;
177 }
178
179 /* internal defines */
180 typedef struct DisasContext {
181 struct TranslationBlock *tb;
182 target_ulong nip;
183 uint32_t opcode;
184 uint32_t exception;
185 /* Routine used to access memory */
186 int mem_idx;
187 int access_type;
188 /* Translation flags */
189 int le_mode;
190 #if defined(TARGET_PPC64)
191 int sf_mode;
192 int has_cfar;
193 #endif
194 int fpu_enabled;
195 int altivec_enabled;
196 int spe_enabled;
197 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
198 int singlestep_enabled;
199 } DisasContext;
200
201 struct opc_handler_t {
202 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
203 uint32_t inval1;
204 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
205 uint32_t inval2;
206 /* instruction type */
207 uint64_t type;
208 /* extended instruction type */
209 uint64_t type2;
210 /* handler */
211 void (*handler)(DisasContext *ctx);
212 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
213 const char *oname;
214 #endif
215 #if defined(DO_PPC_STATISTICS)
216 uint64_t count;
217 #endif
218 };
219
220 static inline void gen_reset_fpstatus(void)
221 {
222 gen_helper_reset_fpstatus();
223 }
224
225 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
226 {
227 TCGv_i32 t0 = tcg_temp_new_i32();
228
229 if (set_fprf != 0) {
230 /* This case might be optimized later */
231 tcg_gen_movi_i32(t0, 1);
232 gen_helper_compute_fprf(t0, arg, t0);
233 if (unlikely(set_rc)) {
234 tcg_gen_mov_i32(cpu_crf[1], t0);
235 }
236 gen_helper_float_check_status();
237 } else if (unlikely(set_rc)) {
238 /* We always need to compute fpcc */
239 tcg_gen_movi_i32(t0, 0);
240 gen_helper_compute_fprf(t0, arg, t0);
241 tcg_gen_mov_i32(cpu_crf[1], t0);
242 }
243
244 tcg_temp_free_i32(t0);
245 }
246
247 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
248 {
249 if (ctx->access_type != access_type) {
250 tcg_gen_movi_i32(cpu_access_type, access_type);
251 ctx->access_type = access_type;
252 }
253 }
254
255 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
256 {
257 #if defined(TARGET_PPC64)
258 if (ctx->sf_mode)
259 tcg_gen_movi_tl(cpu_nip, nip);
260 else
261 #endif
262 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
263 }
264
265 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
266 {
267 TCGv_i32 t0, t1;
268 if (ctx->exception == POWERPC_EXCP_NONE) {
269 gen_update_nip(ctx, ctx->nip);
270 }
271 t0 = tcg_const_i32(excp);
272 t1 = tcg_const_i32(error);
273 gen_helper_raise_exception_err(t0, t1);
274 tcg_temp_free_i32(t0);
275 tcg_temp_free_i32(t1);
276 ctx->exception = (excp);
277 }
278
279 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
280 {
281 TCGv_i32 t0;
282 if (ctx->exception == POWERPC_EXCP_NONE) {
283 gen_update_nip(ctx, ctx->nip);
284 }
285 t0 = tcg_const_i32(excp);
286 gen_helper_raise_exception(t0);
287 tcg_temp_free_i32(t0);
288 ctx->exception = (excp);
289 }
290
291 static inline void gen_debug_exception(DisasContext *ctx)
292 {
293 TCGv_i32 t0;
294
295 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
296 (ctx->exception != POWERPC_EXCP_SYNC)) {
297 gen_update_nip(ctx, ctx->nip);
298 }
299 t0 = tcg_const_i32(EXCP_DEBUG);
300 gen_helper_raise_exception(t0);
301 tcg_temp_free_i32(t0);
302 }
303
304 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
305 {
306 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
307 }
308
309 /* Stop translation */
310 static inline void gen_stop_exception(DisasContext *ctx)
311 {
312 gen_update_nip(ctx, ctx->nip);
313 ctx->exception = POWERPC_EXCP_STOP;
314 }
315
316 /* No need to update nip here, as execution flow will change */
317 static inline void gen_sync_exception(DisasContext *ctx)
318 {
319 ctx->exception = POWERPC_EXCP_SYNC;
320 }
321
322 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
323 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
324
325 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
326 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
327
328 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
329 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
330
331 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
332 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
333
334 typedef struct opcode_t {
335 unsigned char opc1, opc2, opc3;
336 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
337 unsigned char pad[5];
338 #else
339 unsigned char pad[1];
340 #endif
341 opc_handler_t handler;
342 const char *oname;
343 } opcode_t;
344
345 /*****************************************************************************/
346 /*** Instruction decoding ***/
347 #define EXTRACT_HELPER(name, shift, nb) \
348 static inline uint32_t name(uint32_t opcode) \
349 { \
350 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
351 }
352
353 #define EXTRACT_SHELPER(name, shift, nb) \
354 static inline int32_t name(uint32_t opcode) \
355 { \
356 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
357 }
358
359 /* Opcode part 1 */
360 EXTRACT_HELPER(opc1, 26, 6);
361 /* Opcode part 2 */
362 EXTRACT_HELPER(opc2, 1, 5);
363 /* Opcode part 3 */
364 EXTRACT_HELPER(opc3, 6, 5);
365 /* Update Cr0 flags */
366 EXTRACT_HELPER(Rc, 0, 1);
367 /* Destination */
368 EXTRACT_HELPER(rD, 21, 5);
369 /* Source */
370 EXTRACT_HELPER(rS, 21, 5);
371 /* First operand */
372 EXTRACT_HELPER(rA, 16, 5);
373 /* Second operand */
374 EXTRACT_HELPER(rB, 11, 5);
375 /* Third operand */
376 EXTRACT_HELPER(rC, 6, 5);
377 /*** Get CRn ***/
378 EXTRACT_HELPER(crfD, 23, 3);
379 EXTRACT_HELPER(crfS, 18, 3);
380 EXTRACT_HELPER(crbD, 21, 5);
381 EXTRACT_HELPER(crbA, 16, 5);
382 EXTRACT_HELPER(crbB, 11, 5);
383 /* SPR / TBL */
384 EXTRACT_HELPER(_SPR, 11, 10);
385 static inline uint32_t SPR(uint32_t opcode)
386 {
387 uint32_t sprn = _SPR(opcode);
388
389 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
390 }
391 /*** Get constants ***/
392 EXTRACT_HELPER(IMM, 12, 8);
393 /* 16 bits signed immediate value */
394 EXTRACT_SHELPER(SIMM, 0, 16);
395 /* 16 bits unsigned immediate value */
396 EXTRACT_HELPER(UIMM, 0, 16);
397 /* 5 bits signed immediate value */
398 EXTRACT_HELPER(SIMM5, 16, 5);
399 /* 5 bits signed immediate value */
400 EXTRACT_HELPER(UIMM5, 16, 5);
401 /* Bit count */
402 EXTRACT_HELPER(NB, 11, 5);
403 /* Shift count */
404 EXTRACT_HELPER(SH, 11, 5);
405 /* Vector shift count */
406 EXTRACT_HELPER(VSH, 6, 4);
407 /* Mask start */
408 EXTRACT_HELPER(MB, 6, 5);
409 /* Mask end */
410 EXTRACT_HELPER(ME, 1, 5);
411 /* Trap operand */
412 EXTRACT_HELPER(TO, 21, 5);
413
414 EXTRACT_HELPER(CRM, 12, 8);
415 EXTRACT_HELPER(FM, 17, 8);
416 EXTRACT_HELPER(SR, 16, 4);
417 EXTRACT_HELPER(FPIMM, 12, 4);
418
419 /*** Jump target decoding ***/
420 /* Displacement */
421 EXTRACT_SHELPER(d, 0, 16);
422 /* Immediate address */
423 static inline target_ulong LI(uint32_t opcode)
424 {
425 return (opcode >> 0) & 0x03FFFFFC;
426 }
427
428 static inline uint32_t BD(uint32_t opcode)
429 {
430 return (opcode >> 0) & 0xFFFC;
431 }
432
433 EXTRACT_HELPER(BO, 21, 5);
434 EXTRACT_HELPER(BI, 16, 5);
435 /* Absolute/relative address */
436 EXTRACT_HELPER(AA, 1, 1);
437 /* Link */
438 EXTRACT_HELPER(LK, 0, 1);
439
440 /* Create a mask between <start> and <end> bits */
441 static inline target_ulong MASK(uint32_t start, uint32_t end)
442 {
443 target_ulong ret;
444
445 #if defined(TARGET_PPC64)
446 if (likely(start == 0)) {
447 ret = UINT64_MAX << (63 - end);
448 } else if (likely(end == 63)) {
449 ret = UINT64_MAX >> start;
450 }
451 #else
452 if (likely(start == 0)) {
453 ret = UINT32_MAX << (31 - end);
454 } else if (likely(end == 31)) {
455 ret = UINT32_MAX >> start;
456 }
457 #endif
458 else {
459 ret = (((target_ulong)(-1ULL)) >> (start)) ^
460 (((target_ulong)(-1ULL) >> (end)) >> 1);
461 if (unlikely(start > end))
462 return ~ret;
463 }
464
465 return ret;
466 }
467
468 /*****************************************************************************/
469 /* PowerPC instructions table */
470
471 #if defined(DO_PPC_STATISTICS)
472 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
473 { \
474 .opc1 = op1, \
475 .opc2 = op2, \
476 .opc3 = op3, \
477 .pad = { 0, }, \
478 .handler = { \
479 .inval1 = invl, \
480 .type = _typ, \
481 .type2 = _typ2, \
482 .handler = &gen_##name, \
483 .oname = stringify(name), \
484 }, \
485 .oname = stringify(name), \
486 }
487 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
488 { \
489 .opc1 = op1, \
490 .opc2 = op2, \
491 .opc3 = op3, \
492 .pad = { 0, }, \
493 .handler = { \
494 .inval1 = invl1, \
495 .inval2 = invl2, \
496 .type = _typ, \
497 .type2 = _typ2, \
498 .handler = &gen_##name, \
499 .oname = stringify(name), \
500 }, \
501 .oname = stringify(name), \
502 }
503 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
504 { \
505 .opc1 = op1, \
506 .opc2 = op2, \
507 .opc3 = op3, \
508 .pad = { 0, }, \
509 .handler = { \
510 .inval1 = invl, \
511 .type = _typ, \
512 .type2 = _typ2, \
513 .handler = &gen_##name, \
514 .oname = onam, \
515 }, \
516 .oname = onam, \
517 }
518 #else
519 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
520 { \
521 .opc1 = op1, \
522 .opc2 = op2, \
523 .opc3 = op3, \
524 .pad = { 0, }, \
525 .handler = { \
526 .inval1 = invl, \
527 .type = _typ, \
528 .type2 = _typ2, \
529 .handler = &gen_##name, \
530 }, \
531 .oname = stringify(name), \
532 }
533 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
534 { \
535 .opc1 = op1, \
536 .opc2 = op2, \
537 .opc3 = op3, \
538 .pad = { 0, }, \
539 .handler = { \
540 .inval1 = invl1, \
541 .inval2 = invl2, \
542 .type = _typ, \
543 .type2 = _typ2, \
544 .handler = &gen_##name, \
545 }, \
546 .oname = stringify(name), \
547 }
548 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
549 { \
550 .opc1 = op1, \
551 .opc2 = op2, \
552 .opc3 = op3, \
553 .pad = { 0, }, \
554 .handler = { \
555 .inval1 = invl, \
556 .type = _typ, \
557 .type2 = _typ2, \
558 .handler = &gen_##name, \
559 }, \
560 .oname = onam, \
561 }
562 #endif
563
564 /* SPR load/store helpers */
565 static inline void gen_load_spr(TCGv t, int reg)
566 {
567 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
568 }
569
570 static inline void gen_store_spr(int reg, TCGv t)
571 {
572 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
573 }
574
575 /* Invalid instruction */
576 static void gen_invalid(DisasContext *ctx)
577 {
578 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
579 }
580
581 static opc_handler_t invalid_handler = {
582 .inval1 = 0xFFFFFFFF,
583 .inval2 = 0xFFFFFFFF,
584 .type = PPC_NONE,
585 .type2 = PPC_NONE,
586 .handler = gen_invalid,
587 };
588
589 /*** Integer comparison ***/
590
591 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
592 {
593 int l1, l2, l3;
594
595 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
596 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
597 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
598
599 l1 = gen_new_label();
600 l2 = gen_new_label();
601 l3 = gen_new_label();
602 if (s) {
603 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
604 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
605 } else {
606 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
607 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
608 }
609 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
610 tcg_gen_br(l3);
611 gen_set_label(l1);
612 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
613 tcg_gen_br(l3);
614 gen_set_label(l2);
615 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
616 gen_set_label(l3);
617 }
618
619 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
620 {
621 TCGv t0 = tcg_const_local_tl(arg1);
622 gen_op_cmp(arg0, t0, s, crf);
623 tcg_temp_free(t0);
624 }
625
626 #if defined(TARGET_PPC64)
627 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
628 {
629 TCGv t0, t1;
630 t0 = tcg_temp_local_new();
631 t1 = tcg_temp_local_new();
632 if (s) {
633 tcg_gen_ext32s_tl(t0, arg0);
634 tcg_gen_ext32s_tl(t1, arg1);
635 } else {
636 tcg_gen_ext32u_tl(t0, arg0);
637 tcg_gen_ext32u_tl(t1, arg1);
638 }
639 gen_op_cmp(t0, t1, s, crf);
640 tcg_temp_free(t1);
641 tcg_temp_free(t0);
642 }
643
644 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
645 {
646 TCGv t0 = tcg_const_local_tl(arg1);
647 gen_op_cmp32(arg0, t0, s, crf);
648 tcg_temp_free(t0);
649 }
650 #endif
651
652 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
653 {
654 #if defined(TARGET_PPC64)
655 if (!(ctx->sf_mode))
656 gen_op_cmpi32(reg, 0, 1, 0);
657 else
658 #endif
659 gen_op_cmpi(reg, 0, 1, 0);
660 }
661
662 /* cmp */
663 static void gen_cmp(DisasContext *ctx)
664 {
665 #if defined(TARGET_PPC64)
666 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
667 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
668 1, crfD(ctx->opcode));
669 else
670 #endif
671 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
672 1, crfD(ctx->opcode));
673 }
674
675 /* cmpi */
676 static void gen_cmpi(DisasContext *ctx)
677 {
678 #if defined(TARGET_PPC64)
679 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
680 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
681 1, crfD(ctx->opcode));
682 else
683 #endif
684 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
685 1, crfD(ctx->opcode));
686 }
687
688 /* cmpl */
689 static void gen_cmpl(DisasContext *ctx)
690 {
691 #if defined(TARGET_PPC64)
692 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
693 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
694 0, crfD(ctx->opcode));
695 else
696 #endif
697 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
698 0, crfD(ctx->opcode));
699 }
700
701 /* cmpli */
702 static void gen_cmpli(DisasContext *ctx)
703 {
704 #if defined(TARGET_PPC64)
705 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
706 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
707 0, crfD(ctx->opcode));
708 else
709 #endif
710 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
711 0, crfD(ctx->opcode));
712 }
713
714 /* isel (PowerPC 2.03 specification) */
715 static void gen_isel(DisasContext *ctx)
716 {
717 int l1, l2;
718 uint32_t bi = rC(ctx->opcode);
719 uint32_t mask;
720 TCGv_i32 t0;
721
722 l1 = gen_new_label();
723 l2 = gen_new_label();
724
725 mask = 1 << (3 - (bi & 0x03));
726 t0 = tcg_temp_new_i32();
727 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
728 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
729 if (rA(ctx->opcode) == 0)
730 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
731 else
732 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
733 tcg_gen_br(l2);
734 gen_set_label(l1);
735 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
736 gen_set_label(l2);
737 tcg_temp_free_i32(t0);
738 }
739
740 /*** Integer arithmetic ***/
741
742 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
743 TCGv arg1, TCGv arg2, int sub)
744 {
745 int l1;
746 TCGv t0;
747
748 l1 = gen_new_label();
749 /* Start with XER OV disabled, the most likely case */
750 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
751 t0 = tcg_temp_local_new();
752 tcg_gen_xor_tl(t0, arg0, arg1);
753 #if defined(TARGET_PPC64)
754 if (!ctx->sf_mode)
755 tcg_gen_ext32s_tl(t0, t0);
756 #endif
757 if (sub)
758 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
759 else
760 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
761 tcg_gen_xor_tl(t0, arg1, arg2);
762 #if defined(TARGET_PPC64)
763 if (!ctx->sf_mode)
764 tcg_gen_ext32s_tl(t0, t0);
765 #endif
766 if (sub)
767 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
768 else
769 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
770 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
771 gen_set_label(l1);
772 tcg_temp_free(t0);
773 }
774
775 static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1,
776 TCGv arg2, int sub)
777 {
778 int l1 = gen_new_label();
779
780 #if defined(TARGET_PPC64)
781 if (!(ctx->sf_mode)) {
782 TCGv t0, t1;
783 t0 = tcg_temp_new();
784 t1 = tcg_temp_new();
785
786 tcg_gen_ext32u_tl(t0, arg1);
787 tcg_gen_ext32u_tl(t1, arg2);
788 if (sub) {
789 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
790 } else {
791 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
792 }
793 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
794 gen_set_label(l1);
795 tcg_temp_free(t0);
796 tcg_temp_free(t1);
797 } else
798 #endif
799 {
800 if (sub) {
801 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
802 } else {
803 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
804 }
805 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
806 gen_set_label(l1);
807 }
808 }
809
810 /* Common add function */
811 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
812 TCGv arg2, int add_ca, int compute_ca,
813 int compute_ov)
814 {
815 TCGv t0, t1;
816
817 if ((!compute_ca && !compute_ov) ||
818 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
819 t0 = ret;
820 } else {
821 t0 = tcg_temp_local_new();
822 }
823
824 if (add_ca) {
825 t1 = tcg_temp_local_new();
826 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
827 tcg_gen_shri_tl(t1, t1, XER_CA);
828 } else {
829 TCGV_UNUSED(t1);
830 }
831
832 if (compute_ca && compute_ov) {
833 /* Start with XER CA and OV disabled, the most likely case */
834 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
835 } else if (compute_ca) {
836 /* Start with XER CA disabled, the most likely case */
837 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
838 } else if (compute_ov) {
839 /* Start with XER OV disabled, the most likely case */
840 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
841 }
842
843 tcg_gen_add_tl(t0, arg1, arg2);
844
845 if (compute_ca) {
846 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
847 }
848 if (add_ca) {
849 tcg_gen_add_tl(t0, t0, t1);
850 gen_op_arith_compute_ca(ctx, t0, t1, 0);
851 tcg_temp_free(t1);
852 }
853 if (compute_ov) {
854 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
855 }
856
857 if (unlikely(Rc(ctx->opcode) != 0))
858 gen_set_Rc0(ctx, t0);
859
860 if (!TCGV_EQUAL(t0, ret)) {
861 tcg_gen_mov_tl(ret, t0);
862 tcg_temp_free(t0);
863 }
864 }
865 /* Add functions with two operands */
866 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
867 static void glue(gen_, name)(DisasContext *ctx) \
868 { \
869 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
870 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
871 add_ca, compute_ca, compute_ov); \
872 }
873 /* Add functions with one operand and one immediate */
874 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
875 add_ca, compute_ca, compute_ov) \
876 static void glue(gen_, name)(DisasContext *ctx) \
877 { \
878 TCGv t0 = tcg_const_local_tl(const_val); \
879 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
880 cpu_gpr[rA(ctx->opcode)], t0, \
881 add_ca, compute_ca, compute_ov); \
882 tcg_temp_free(t0); \
883 }
884
885 /* add add. addo addo. */
886 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
887 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
888 /* addc addc. addco addco. */
889 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
890 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
891 /* adde adde. addeo addeo. */
892 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
893 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
894 /* addme addme. addmeo addmeo. */
895 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
896 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
897 /* addze addze. addzeo addzeo.*/
898 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
899 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
900 /* addi */
901 static void gen_addi(DisasContext *ctx)
902 {
903 target_long simm = SIMM(ctx->opcode);
904
905 if (rA(ctx->opcode) == 0) {
906 /* li case */
907 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
908 } else {
909 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
910 }
911 }
912 /* addic addic.*/
913 static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1,
914 int compute_Rc0)
915 {
916 target_long simm = SIMM(ctx->opcode);
917
918 /* Start with XER CA and OV disabled, the most likely case */
919 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
920
921 if (likely(simm != 0)) {
922 TCGv t0 = tcg_temp_local_new();
923 tcg_gen_addi_tl(t0, arg1, simm);
924 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
925 tcg_gen_mov_tl(ret, t0);
926 tcg_temp_free(t0);
927 } else {
928 tcg_gen_mov_tl(ret, arg1);
929 }
930 if (compute_Rc0) {
931 gen_set_Rc0(ctx, ret);
932 }
933 }
934
935 static void gen_addic(DisasContext *ctx)
936 {
937 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
938 }
939
940 static void gen_addic_(DisasContext *ctx)
941 {
942 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
943 }
944
945 /* addis */
946 static void gen_addis(DisasContext *ctx)
947 {
948 target_long simm = SIMM(ctx->opcode);
949
950 if (rA(ctx->opcode) == 0) {
951 /* lis case */
952 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
953 } else {
954 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
955 }
956 }
957
958 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
959 TCGv arg2, int sign, int compute_ov)
960 {
961 int l1 = gen_new_label();
962 int l2 = gen_new_label();
963 TCGv_i32 t0 = tcg_temp_local_new_i32();
964 TCGv_i32 t1 = tcg_temp_local_new_i32();
965
966 tcg_gen_trunc_tl_i32(t0, arg1);
967 tcg_gen_trunc_tl_i32(t1, arg2);
968 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
969 if (sign) {
970 int l3 = gen_new_label();
971 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
972 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
973 gen_set_label(l3);
974 tcg_gen_div_i32(t0, t0, t1);
975 } else {
976 tcg_gen_divu_i32(t0, t0, t1);
977 }
978 if (compute_ov) {
979 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
980 }
981 tcg_gen_br(l2);
982 gen_set_label(l1);
983 if (sign) {
984 tcg_gen_sari_i32(t0, t0, 31);
985 } else {
986 tcg_gen_movi_i32(t0, 0);
987 }
988 if (compute_ov) {
989 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
990 }
991 gen_set_label(l2);
992 tcg_gen_extu_i32_tl(ret, t0);
993 tcg_temp_free_i32(t0);
994 tcg_temp_free_i32(t1);
995 if (unlikely(Rc(ctx->opcode) != 0))
996 gen_set_Rc0(ctx, ret);
997 }
998 /* Div functions */
999 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1000 static void glue(gen_, name)(DisasContext *ctx) \
1001 { \
1002 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1003 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1004 sign, compute_ov); \
1005 }
1006 /* divwu divwu. divwuo divwuo. */
1007 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1008 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1009 /* divw divw. divwo divwo. */
1010 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1011 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1012 #if defined(TARGET_PPC64)
1013 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1014 TCGv arg2, int sign, int compute_ov)
1015 {
1016 int l1 = gen_new_label();
1017 int l2 = gen_new_label();
1018
1019 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1020 if (sign) {
1021 int l3 = gen_new_label();
1022 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1023 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1024 gen_set_label(l3);
1025 tcg_gen_div_i64(ret, arg1, arg2);
1026 } else {
1027 tcg_gen_divu_i64(ret, arg1, arg2);
1028 }
1029 if (compute_ov) {
1030 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1031 }
1032 tcg_gen_br(l2);
1033 gen_set_label(l1);
1034 if (sign) {
1035 tcg_gen_sari_i64(ret, arg1, 63);
1036 } else {
1037 tcg_gen_movi_i64(ret, 0);
1038 }
1039 if (compute_ov) {
1040 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1041 }
1042 gen_set_label(l2);
1043 if (unlikely(Rc(ctx->opcode) != 0))
1044 gen_set_Rc0(ctx, ret);
1045 }
1046 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1047 static void glue(gen_, name)(DisasContext *ctx) \
1048 { \
1049 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1050 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1051 sign, compute_ov); \
1052 }
1053 /* divwu divwu. divwuo divwuo. */
1054 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1055 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1056 /* divw divw. divwo divwo. */
1057 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1058 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1059 #endif
1060
1061 /* mulhw mulhw. */
1062 static void gen_mulhw(DisasContext *ctx)
1063 {
1064 TCGv_i64 t0, t1;
1065
1066 t0 = tcg_temp_new_i64();
1067 t1 = tcg_temp_new_i64();
1068 #if defined(TARGET_PPC64)
1069 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1070 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1071 tcg_gen_mul_i64(t0, t0, t1);
1072 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1073 #else
1074 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1075 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1076 tcg_gen_mul_i64(t0, t0, t1);
1077 tcg_gen_shri_i64(t0, t0, 32);
1078 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1079 #endif
1080 tcg_temp_free_i64(t0);
1081 tcg_temp_free_i64(t1);
1082 if (unlikely(Rc(ctx->opcode) != 0))
1083 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1084 }
1085
1086 /* mulhwu mulhwu. */
1087 static void gen_mulhwu(DisasContext *ctx)
1088 {
1089 TCGv_i64 t0, t1;
1090
1091 t0 = tcg_temp_new_i64();
1092 t1 = tcg_temp_new_i64();
1093 #if defined(TARGET_PPC64)
1094 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1095 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1096 tcg_gen_mul_i64(t0, t0, t1);
1097 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1098 #else
1099 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1100 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1101 tcg_gen_mul_i64(t0, t0, t1);
1102 tcg_gen_shri_i64(t0, t0, 32);
1103 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1104 #endif
1105 tcg_temp_free_i64(t0);
1106 tcg_temp_free_i64(t1);
1107 if (unlikely(Rc(ctx->opcode) != 0))
1108 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1109 }
1110
1111 /* mullw mullw. */
1112 static void gen_mullw(DisasContext *ctx)
1113 {
1114 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1115 cpu_gpr[rB(ctx->opcode)]);
1116 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1117 if (unlikely(Rc(ctx->opcode) != 0))
1118 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1119 }
1120
1121 /* mullwo mullwo. */
1122 static void gen_mullwo(DisasContext *ctx)
1123 {
1124 int l1;
1125 TCGv_i64 t0, t1;
1126
1127 t0 = tcg_temp_new_i64();
1128 t1 = tcg_temp_new_i64();
1129 l1 = gen_new_label();
1130 /* Start with XER OV disabled, the most likely case */
1131 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1132 #if defined(TARGET_PPC64)
1133 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1134 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1135 #else
1136 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1137 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1138 #endif
1139 tcg_gen_mul_i64(t0, t0, t1);
1140 #if defined(TARGET_PPC64)
1141 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1142 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1143 #else
1144 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1145 tcg_gen_ext32s_i64(t1, t0);
1146 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1147 #endif
1148 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1149 gen_set_label(l1);
1150 tcg_temp_free_i64(t0);
1151 tcg_temp_free_i64(t1);
1152 if (unlikely(Rc(ctx->opcode) != 0))
1153 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1154 }
1155
1156 /* mulli */
1157 static void gen_mulli(DisasContext *ctx)
1158 {
1159 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1160 SIMM(ctx->opcode));
1161 }
1162 #if defined(TARGET_PPC64)
1163 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1164 static void glue(gen_, name)(DisasContext *ctx) \
1165 { \
1166 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1167 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1168 if (unlikely(Rc(ctx->opcode) != 0)) \
1169 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1170 }
1171 /* mulhd mulhd. */
1172 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1173 /* mulhdu mulhdu. */
1174 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1175
1176 /* mulld mulld. */
1177 static void gen_mulld(DisasContext *ctx)
1178 {
1179 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1180 cpu_gpr[rB(ctx->opcode)]);
1181 if (unlikely(Rc(ctx->opcode) != 0))
1182 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1183 }
1184 /* mulldo mulldo. */
1185 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1186 #endif
1187
1188 /* neg neg. nego nego. */
1189 static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1,
1190 int ov_check)
1191 {
1192 int l1 = gen_new_label();
1193 int l2 = gen_new_label();
1194 TCGv t0 = tcg_temp_local_new();
1195 #if defined(TARGET_PPC64)
1196 if (ctx->sf_mode) {
1197 tcg_gen_mov_tl(t0, arg1);
1198 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1199 } else
1200 #endif
1201 {
1202 tcg_gen_ext32s_tl(t0, arg1);
1203 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1204 }
1205 tcg_gen_neg_tl(ret, arg1);
1206 if (ov_check) {
1207 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1208 }
1209 tcg_gen_br(l2);
1210 gen_set_label(l1);
1211 tcg_gen_mov_tl(ret, t0);
1212 if (ov_check) {
1213 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1214 }
1215 gen_set_label(l2);
1216 tcg_temp_free(t0);
1217 if (unlikely(Rc(ctx->opcode) != 0))
1218 gen_set_Rc0(ctx, ret);
1219 }
1220
1221 static void gen_neg(DisasContext *ctx)
1222 {
1223 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1224 }
1225
1226 static void gen_nego(DisasContext *ctx)
1227 {
1228 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1229 }
1230
1231 /* Common subf function */
1232 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1233 TCGv arg2, int add_ca, int compute_ca,
1234 int compute_ov)
1235 {
1236 TCGv t0, t1;
1237
1238 if ((!compute_ca && !compute_ov) ||
1239 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1240 t0 = ret;
1241 } else {
1242 t0 = tcg_temp_local_new();
1243 }
1244
1245 if (add_ca) {
1246 t1 = tcg_temp_local_new();
1247 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1248 tcg_gen_shri_tl(t1, t1, XER_CA);
1249 } else {
1250 TCGV_UNUSED(t1);
1251 }
1252
1253 if (compute_ca && compute_ov) {
1254 /* Start with XER CA and OV disabled, the most likely case */
1255 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1256 } else if (compute_ca) {
1257 /* Start with XER CA disabled, the most likely case */
1258 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1259 } else if (compute_ov) {
1260 /* Start with XER OV disabled, the most likely case */
1261 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1262 }
1263
1264 if (add_ca) {
1265 tcg_gen_not_tl(t0, arg1);
1266 tcg_gen_add_tl(t0, t0, arg2);
1267 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1268 tcg_gen_add_tl(t0, t0, t1);
1269 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1270 tcg_temp_free(t1);
1271 } else {
1272 tcg_gen_sub_tl(t0, arg2, arg1);
1273 if (compute_ca) {
1274 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1275 }
1276 }
1277 if (compute_ov) {
1278 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1279 }
1280
1281 if (unlikely(Rc(ctx->opcode) != 0))
1282 gen_set_Rc0(ctx, t0);
1283
1284 if (!TCGV_EQUAL(t0, ret)) {
1285 tcg_gen_mov_tl(ret, t0);
1286 tcg_temp_free(t0);
1287 }
1288 }
1289 /* Sub functions with Two operands functions */
1290 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1291 static void glue(gen_, name)(DisasContext *ctx) \
1292 { \
1293 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1294 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1295 add_ca, compute_ca, compute_ov); \
1296 }
1297 /* Sub functions with one operand and one immediate */
1298 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1299 add_ca, compute_ca, compute_ov) \
1300 static void glue(gen_, name)(DisasContext *ctx) \
1301 { \
1302 TCGv t0 = tcg_const_local_tl(const_val); \
1303 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1304 cpu_gpr[rA(ctx->opcode)], t0, \
1305 add_ca, compute_ca, compute_ov); \
1306 tcg_temp_free(t0); \
1307 }
1308 /* subf subf. subfo subfo. */
1309 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1310 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1311 /* subfc subfc. subfco subfco. */
1312 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1313 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1314 /* subfe subfe. subfeo subfo. */
1315 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1316 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1317 /* subfme subfme. subfmeo subfmeo. */
1318 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1319 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1320 /* subfze subfze. subfzeo subfzeo.*/
1321 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1322 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1323
1324 /* subfic */
1325 static void gen_subfic(DisasContext *ctx)
1326 {
1327 /* Start with XER CA and OV disabled, the most likely case */
1328 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1329 TCGv t0 = tcg_temp_local_new();
1330 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1331 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1332 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1333 tcg_temp_free(t1);
1334 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1335 tcg_temp_free(t0);
1336 }
1337
1338 /*** Integer logical ***/
1339 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1340 static void glue(gen_, name)(DisasContext *ctx) \
1341 { \
1342 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1343 cpu_gpr[rB(ctx->opcode)]); \
1344 if (unlikely(Rc(ctx->opcode) != 0)) \
1345 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1346 }
1347
1348 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1349 static void glue(gen_, name)(DisasContext *ctx) \
1350 { \
1351 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1352 if (unlikely(Rc(ctx->opcode) != 0)) \
1353 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1354 }
1355
1356 /* and & and. */
1357 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1358 /* andc & andc. */
1359 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1360
1361 /* andi. */
1362 static void gen_andi_(DisasContext *ctx)
1363 {
1364 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1365 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1366 }
1367
1368 /* andis. */
1369 static void gen_andis_(DisasContext *ctx)
1370 {
1371 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1372 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1373 }
1374
1375 /* cntlzw */
1376 static void gen_cntlzw(DisasContext *ctx)
1377 {
1378 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1379 if (unlikely(Rc(ctx->opcode) != 0))
1380 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1381 }
1382 /* eqv & eqv. */
1383 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1384 /* extsb & extsb. */
1385 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1386 /* extsh & extsh. */
1387 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1388 /* nand & nand. */
1389 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1390 /* nor & nor. */
1391 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1392
1393 /* or & or. */
1394 static void gen_or(DisasContext *ctx)
1395 {
1396 int rs, ra, rb;
1397
1398 rs = rS(ctx->opcode);
1399 ra = rA(ctx->opcode);
1400 rb = rB(ctx->opcode);
1401 /* Optimisation for mr. ri case */
1402 if (rs != ra || rs != rb) {
1403 if (rs != rb)
1404 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1405 else
1406 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1407 if (unlikely(Rc(ctx->opcode) != 0))
1408 gen_set_Rc0(ctx, cpu_gpr[ra]);
1409 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1410 gen_set_Rc0(ctx, cpu_gpr[rs]);
1411 #if defined(TARGET_PPC64)
1412 } else {
1413 int prio = 0;
1414
1415 switch (rs) {
1416 case 1:
1417 /* Set process priority to low */
1418 prio = 2;
1419 break;
1420 case 6:
1421 /* Set process priority to medium-low */
1422 prio = 3;
1423 break;
1424 case 2:
1425 /* Set process priority to normal */
1426 prio = 4;
1427 break;
1428 #if !defined(CONFIG_USER_ONLY)
1429 case 31:
1430 if (ctx->mem_idx > 0) {
1431 /* Set process priority to very low */
1432 prio = 1;
1433 }
1434 break;
1435 case 5:
1436 if (ctx->mem_idx > 0) {
1437 /* Set process priority to medium-hight */
1438 prio = 5;
1439 }
1440 break;
1441 case 3:
1442 if (ctx->mem_idx > 0) {
1443 /* Set process priority to high */
1444 prio = 6;
1445 }
1446 break;
1447 case 7:
1448 if (ctx->mem_idx > 1) {
1449 /* Set process priority to very high */
1450 prio = 7;
1451 }
1452 break;
1453 #endif
1454 default:
1455 /* nop */
1456 break;
1457 }
1458 if (prio) {
1459 TCGv t0 = tcg_temp_new();
1460 gen_load_spr(t0, SPR_PPR);
1461 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1462 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1463 gen_store_spr(SPR_PPR, t0);
1464 tcg_temp_free(t0);
1465 }
1466 #endif
1467 }
1468 }
1469 /* orc & orc. */
1470 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1471
1472 /* xor & xor. */
1473 static void gen_xor(DisasContext *ctx)
1474 {
1475 /* Optimisation for "set to zero" case */
1476 if (rS(ctx->opcode) != rB(ctx->opcode))
1477 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1478 else
1479 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1480 if (unlikely(Rc(ctx->opcode) != 0))
1481 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1482 }
1483
1484 /* ori */
1485 static void gen_ori(DisasContext *ctx)
1486 {
1487 target_ulong uimm = UIMM(ctx->opcode);
1488
1489 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1490 /* NOP */
1491 /* XXX: should handle special NOPs for POWER series */
1492 return;
1493 }
1494 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1495 }
1496
1497 /* oris */
1498 static void gen_oris(DisasContext *ctx)
1499 {
1500 target_ulong uimm = UIMM(ctx->opcode);
1501
1502 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1503 /* NOP */
1504 return;
1505 }
1506 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1507 }
1508
1509 /* xori */
1510 static void gen_xori(DisasContext *ctx)
1511 {
1512 target_ulong uimm = UIMM(ctx->opcode);
1513
1514 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1515 /* NOP */
1516 return;
1517 }
1518 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1519 }
1520
1521 /* xoris */
1522 static void gen_xoris(DisasContext *ctx)
1523 {
1524 target_ulong uimm = UIMM(ctx->opcode);
1525
1526 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1527 /* NOP */
1528 return;
1529 }
1530 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1531 }
1532
1533 /* popcntb : PowerPC 2.03 specification */
1534 static void gen_popcntb(DisasContext *ctx)
1535 {
1536 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1537 }
1538
1539 static void gen_popcntw(DisasContext *ctx)
1540 {
1541 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1542 }
1543
1544 #if defined(TARGET_PPC64)
1545 /* popcntd: PowerPC 2.06 specification */
1546 static void gen_popcntd(DisasContext *ctx)
1547 {
1548 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1549 }
1550 #endif
1551
1552 #if defined(TARGET_PPC64)
1553 /* extsw & extsw. */
1554 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1555
1556 /* cntlzd */
1557 static void gen_cntlzd(DisasContext *ctx)
1558 {
1559 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1560 if (unlikely(Rc(ctx->opcode) != 0))
1561 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1562 }
1563 #endif
1564
1565 /*** Integer rotate ***/
1566
1567 /* rlwimi & rlwimi. */
1568 static void gen_rlwimi(DisasContext *ctx)
1569 {
1570 uint32_t mb, me, sh;
1571
1572 mb = MB(ctx->opcode);
1573 me = ME(ctx->opcode);
1574 sh = SH(ctx->opcode);
1575 if (likely(sh == 0 && mb == 0 && me == 31)) {
1576 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1577 } else {
1578 target_ulong mask;
1579 TCGv t1;
1580 TCGv t0 = tcg_temp_new();
1581 #if defined(TARGET_PPC64)
1582 TCGv_i32 t2 = tcg_temp_new_i32();
1583 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1584 tcg_gen_rotli_i32(t2, t2, sh);
1585 tcg_gen_extu_i32_i64(t0, t2);
1586 tcg_temp_free_i32(t2);
1587 #else
1588 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1589 #endif
1590 #if defined(TARGET_PPC64)
1591 mb += 32;
1592 me += 32;
1593 #endif
1594 mask = MASK(mb, me);
1595 t1 = tcg_temp_new();
1596 tcg_gen_andi_tl(t0, t0, mask);
1597 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1598 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1599 tcg_temp_free(t0);
1600 tcg_temp_free(t1);
1601 }
1602 if (unlikely(Rc(ctx->opcode) != 0))
1603 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1604 }
1605
1606 /* rlwinm & rlwinm. */
1607 static void gen_rlwinm(DisasContext *ctx)
1608 {
1609 uint32_t mb, me, sh;
1610
1611 sh = SH(ctx->opcode);
1612 mb = MB(ctx->opcode);
1613 me = ME(ctx->opcode);
1614
1615 if (likely(mb == 0 && me == (31 - sh))) {
1616 if (likely(sh == 0)) {
1617 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1618 } else {
1619 TCGv t0 = tcg_temp_new();
1620 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1621 tcg_gen_shli_tl(t0, t0, sh);
1622 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1623 tcg_temp_free(t0);
1624 }
1625 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1626 TCGv t0 = tcg_temp_new();
1627 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1628 tcg_gen_shri_tl(t0, t0, mb);
1629 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1630 tcg_temp_free(t0);
1631 } else {
1632 TCGv t0 = tcg_temp_new();
1633 #if defined(TARGET_PPC64)
1634 TCGv_i32 t1 = tcg_temp_new_i32();
1635 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1636 tcg_gen_rotli_i32(t1, t1, sh);
1637 tcg_gen_extu_i32_i64(t0, t1);
1638 tcg_temp_free_i32(t1);
1639 #else
1640 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1641 #endif
1642 #if defined(TARGET_PPC64)
1643 mb += 32;
1644 me += 32;
1645 #endif
1646 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1647 tcg_temp_free(t0);
1648 }
1649 if (unlikely(Rc(ctx->opcode) != 0))
1650 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1651 }
1652
1653 /* rlwnm & rlwnm. */
1654 static void gen_rlwnm(DisasContext *ctx)
1655 {
1656 uint32_t mb, me;
1657 TCGv t0;
1658 #if defined(TARGET_PPC64)
1659 TCGv_i32 t1, t2;
1660 #endif
1661
1662 mb = MB(ctx->opcode);
1663 me = ME(ctx->opcode);
1664 t0 = tcg_temp_new();
1665 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1666 #if defined(TARGET_PPC64)
1667 t1 = tcg_temp_new_i32();
1668 t2 = tcg_temp_new_i32();
1669 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1670 tcg_gen_trunc_i64_i32(t2, t0);
1671 tcg_gen_rotl_i32(t1, t1, t2);
1672 tcg_gen_extu_i32_i64(t0, t1);
1673 tcg_temp_free_i32(t1);
1674 tcg_temp_free_i32(t2);
1675 #else
1676 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1677 #endif
1678 if (unlikely(mb != 0 || me != 31)) {
1679 #if defined(TARGET_PPC64)
1680 mb += 32;
1681 me += 32;
1682 #endif
1683 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1684 } else {
1685 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1686 }
1687 tcg_temp_free(t0);
1688 if (unlikely(Rc(ctx->opcode) != 0))
1689 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1690 }
1691
1692 #if defined(TARGET_PPC64)
1693 #define GEN_PPC64_R2(name, opc1, opc2) \
1694 static void glue(gen_, name##0)(DisasContext *ctx) \
1695 { \
1696 gen_##name(ctx, 0); \
1697 } \
1698 \
1699 static void glue(gen_, name##1)(DisasContext *ctx) \
1700 { \
1701 gen_##name(ctx, 1); \
1702 }
1703 #define GEN_PPC64_R4(name, opc1, opc2) \
1704 static void glue(gen_, name##0)(DisasContext *ctx) \
1705 { \
1706 gen_##name(ctx, 0, 0); \
1707 } \
1708 \
1709 static void glue(gen_, name##1)(DisasContext *ctx) \
1710 { \
1711 gen_##name(ctx, 0, 1); \
1712 } \
1713 \
1714 static void glue(gen_, name##2)(DisasContext *ctx) \
1715 { \
1716 gen_##name(ctx, 1, 0); \
1717 } \
1718 \
1719 static void glue(gen_, name##3)(DisasContext *ctx) \
1720 { \
1721 gen_##name(ctx, 1, 1); \
1722 }
1723
1724 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1725 uint32_t sh)
1726 {
1727 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1728 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1729 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1730 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1731 } else {
1732 TCGv t0 = tcg_temp_new();
1733 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1734 if (likely(mb == 0 && me == 63)) {
1735 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1736 } else {
1737 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1738 }
1739 tcg_temp_free(t0);
1740 }
1741 if (unlikely(Rc(ctx->opcode) != 0))
1742 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1743 }
1744 /* rldicl - rldicl. */
1745 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1746 {
1747 uint32_t sh, mb;
1748
1749 sh = SH(ctx->opcode) | (shn << 5);
1750 mb = MB(ctx->opcode) | (mbn << 5);
1751 gen_rldinm(ctx, mb, 63, sh);
1752 }
1753 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1754 /* rldicr - rldicr. */
1755 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1756 {
1757 uint32_t sh, me;
1758
1759 sh = SH(ctx->opcode) | (shn << 5);
1760 me = MB(ctx->opcode) | (men << 5);
1761 gen_rldinm(ctx, 0, me, sh);
1762 }
1763 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1764 /* rldic - rldic. */
1765 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1766 {
1767 uint32_t sh, mb;
1768
1769 sh = SH(ctx->opcode) | (shn << 5);
1770 mb = MB(ctx->opcode) | (mbn << 5);
1771 gen_rldinm(ctx, mb, 63 - sh, sh);
1772 }
1773 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1774
1775 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1776 {
1777 TCGv t0;
1778
1779 mb = MB(ctx->opcode);
1780 me = ME(ctx->opcode);
1781 t0 = tcg_temp_new();
1782 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1783 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1784 if (unlikely(mb != 0 || me != 63)) {
1785 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1786 } else {
1787 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1788 }
1789 tcg_temp_free(t0);
1790 if (unlikely(Rc(ctx->opcode) != 0))
1791 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1792 }
1793
1794 /* rldcl - rldcl. */
1795 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1796 {
1797 uint32_t mb;
1798
1799 mb = MB(ctx->opcode) | (mbn << 5);
1800 gen_rldnm(ctx, mb, 63);
1801 }
1802 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1803 /* rldcr - rldcr. */
1804 static inline void gen_rldcr(DisasContext *ctx, int men)
1805 {
1806 uint32_t me;
1807
1808 me = MB(ctx->opcode) | (men << 5);
1809 gen_rldnm(ctx, 0, me);
1810 }
1811 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1812 /* rldimi - rldimi. */
1813 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1814 {
1815 uint32_t sh, mb, me;
1816
1817 sh = SH(ctx->opcode) | (shn << 5);
1818 mb = MB(ctx->opcode) | (mbn << 5);
1819 me = 63 - sh;
1820 if (unlikely(sh == 0 && mb == 0)) {
1821 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1822 } else {
1823 TCGv t0, t1;
1824 target_ulong mask;
1825
1826 t0 = tcg_temp_new();
1827 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1828 t1 = tcg_temp_new();
1829 mask = MASK(mb, me);
1830 tcg_gen_andi_tl(t0, t0, mask);
1831 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1832 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1833 tcg_temp_free(t0);
1834 tcg_temp_free(t1);
1835 }
1836 if (unlikely(Rc(ctx->opcode) != 0))
1837 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1838 }
1839 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1840 #endif
1841
1842 /*** Integer shift ***/
1843
1844 /* slw & slw. */
1845 static void gen_slw(DisasContext *ctx)
1846 {
1847 TCGv t0, t1;
1848
1849 t0 = tcg_temp_new();
1850 /* AND rS with a mask that is 0 when rB >= 0x20 */
1851 #if defined(TARGET_PPC64)
1852 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1853 tcg_gen_sari_tl(t0, t0, 0x3f);
1854 #else
1855 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1856 tcg_gen_sari_tl(t0, t0, 0x1f);
1857 #endif
1858 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1859 t1 = tcg_temp_new();
1860 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1861 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1862 tcg_temp_free(t1);
1863 tcg_temp_free(t0);
1864 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1865 if (unlikely(Rc(ctx->opcode) != 0))
1866 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1867 }
1868
1869 /* sraw & sraw. */
1870 static void gen_sraw(DisasContext *ctx)
1871 {
1872 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1873 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1874 if (unlikely(Rc(ctx->opcode) != 0))
1875 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1876 }
1877
1878 /* srawi & srawi. */
1879 static void gen_srawi(DisasContext *ctx)
1880 {
1881 int sh = SH(ctx->opcode);
1882 if (sh != 0) {
1883 int l1, l2;
1884 TCGv t0;
1885 l1 = gen_new_label();
1886 l2 = gen_new_label();
1887 t0 = tcg_temp_local_new();
1888 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1889 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1890 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1891 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1892 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1893 tcg_gen_br(l2);
1894 gen_set_label(l1);
1895 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1896 gen_set_label(l2);
1897 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1898 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1899 tcg_temp_free(t0);
1900 } else {
1901 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1902 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1903 }
1904 if (unlikely(Rc(ctx->opcode) != 0))
1905 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1906 }
1907
1908 /* srw & srw. */
1909 static void gen_srw(DisasContext *ctx)
1910 {
1911 TCGv t0, t1;
1912
1913 t0 = tcg_temp_new();
1914 /* AND rS with a mask that is 0 when rB >= 0x20 */
1915 #if defined(TARGET_PPC64)
1916 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1917 tcg_gen_sari_tl(t0, t0, 0x3f);
1918 #else
1919 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1920 tcg_gen_sari_tl(t0, t0, 0x1f);
1921 #endif
1922 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1923 tcg_gen_ext32u_tl(t0, t0);
1924 t1 = tcg_temp_new();
1925 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1926 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1927 tcg_temp_free(t1);
1928 tcg_temp_free(t0);
1929 if (unlikely(Rc(ctx->opcode) != 0))
1930 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1931 }
1932
1933 #if defined(TARGET_PPC64)
1934 /* sld & sld. */
1935 static void gen_sld(DisasContext *ctx)
1936 {
1937 TCGv t0, t1;
1938
1939 t0 = tcg_temp_new();
1940 /* AND rS with a mask that is 0 when rB >= 0x40 */
1941 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1942 tcg_gen_sari_tl(t0, t0, 0x3f);
1943 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1944 t1 = tcg_temp_new();
1945 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1946 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1947 tcg_temp_free(t1);
1948 tcg_temp_free(t0);
1949 if (unlikely(Rc(ctx->opcode) != 0))
1950 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1951 }
1952
1953 /* srad & srad. */
1954 static void gen_srad(DisasContext *ctx)
1955 {
1956 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
1957 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1958 if (unlikely(Rc(ctx->opcode) != 0))
1959 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1960 }
1961 /* sradi & sradi. */
1962 static inline void gen_sradi(DisasContext *ctx, int n)
1963 {
1964 int sh = SH(ctx->opcode) + (n << 5);
1965 if (sh != 0) {
1966 int l1, l2;
1967 TCGv t0;
1968 l1 = gen_new_label();
1969 l2 = gen_new_label();
1970 t0 = tcg_temp_local_new();
1971 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
1972 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1973 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1974 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1975 tcg_gen_br(l2);
1976 gen_set_label(l1);
1977 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1978 gen_set_label(l2);
1979 tcg_temp_free(t0);
1980 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1981 } else {
1982 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1983 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1984 }
1985 if (unlikely(Rc(ctx->opcode) != 0))
1986 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1987 }
1988
1989 static void gen_sradi0(DisasContext *ctx)
1990 {
1991 gen_sradi(ctx, 0);
1992 }
1993
1994 static void gen_sradi1(DisasContext *ctx)
1995 {
1996 gen_sradi(ctx, 1);
1997 }
1998
1999 /* srd & srd. */
2000 static void gen_srd(DisasContext *ctx)
2001 {
2002 TCGv t0, t1;
2003
2004 t0 = tcg_temp_new();
2005 /* AND rS with a mask that is 0 when rB >= 0x40 */
2006 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2007 tcg_gen_sari_tl(t0, t0, 0x3f);
2008 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2009 t1 = tcg_temp_new();
2010 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2011 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2012 tcg_temp_free(t1);
2013 tcg_temp_free(t0);
2014 if (unlikely(Rc(ctx->opcode) != 0))
2015 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2016 }
2017 #endif
2018
2019 /*** Floating-Point arithmetic ***/
2020 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2021 static void gen_f##name(DisasContext *ctx) \
2022 { \
2023 if (unlikely(!ctx->fpu_enabled)) { \
2024 gen_exception(ctx, POWERPC_EXCP_FPU); \
2025 return; \
2026 } \
2027 /* NIP cannot be restored if the memory exception comes from an helper */ \
2028 gen_update_nip(ctx, ctx->nip - 4); \
2029 gen_reset_fpstatus(); \
2030 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2031 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2032 if (isfloat) { \
2033 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2034 } \
2035 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2036 Rc(ctx->opcode) != 0); \
2037 }
2038
2039 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2040 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2041 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2042
2043 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2044 static void gen_f##name(DisasContext *ctx) \
2045 { \
2046 if (unlikely(!ctx->fpu_enabled)) { \
2047 gen_exception(ctx, POWERPC_EXCP_FPU); \
2048 return; \
2049 } \
2050 /* NIP cannot be restored if the memory exception comes from an helper */ \
2051 gen_update_nip(ctx, ctx->nip - 4); \
2052 gen_reset_fpstatus(); \
2053 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2054 cpu_fpr[rB(ctx->opcode)]); \
2055 if (isfloat) { \
2056 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2057 } \
2058 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2059 set_fprf, Rc(ctx->opcode) != 0); \
2060 }
2061 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2062 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2063 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2064
2065 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2066 static void gen_f##name(DisasContext *ctx) \
2067 { \
2068 if (unlikely(!ctx->fpu_enabled)) { \
2069 gen_exception(ctx, POWERPC_EXCP_FPU); \
2070 return; \
2071 } \
2072 /* NIP cannot be restored if the memory exception comes from an helper */ \
2073 gen_update_nip(ctx, ctx->nip - 4); \
2074 gen_reset_fpstatus(); \
2075 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2076 cpu_fpr[rC(ctx->opcode)]); \
2077 if (isfloat) { \
2078 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2079 } \
2080 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2081 set_fprf, Rc(ctx->opcode) != 0); \
2082 }
2083 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2084 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2085 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2086
2087 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2088 static void gen_f##name(DisasContext *ctx) \
2089 { \
2090 if (unlikely(!ctx->fpu_enabled)) { \
2091 gen_exception(ctx, POWERPC_EXCP_FPU); \
2092 return; \
2093 } \
2094 /* NIP cannot be restored if the memory exception comes from an helper */ \
2095 gen_update_nip(ctx, ctx->nip - 4); \
2096 gen_reset_fpstatus(); \
2097 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2098 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2099 set_fprf, Rc(ctx->opcode) != 0); \
2100 }
2101
2102 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2103 static void gen_f##name(DisasContext *ctx) \
2104 { \
2105 if (unlikely(!ctx->fpu_enabled)) { \
2106 gen_exception(ctx, POWERPC_EXCP_FPU); \
2107 return; \
2108 } \
2109 /* NIP cannot be restored if the memory exception comes from an helper */ \
2110 gen_update_nip(ctx, ctx->nip - 4); \
2111 gen_reset_fpstatus(); \
2112 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2113 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2114 set_fprf, Rc(ctx->opcode) != 0); \
2115 }
2116
2117 /* fadd - fadds */
2118 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2119 /* fdiv - fdivs */
2120 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2121 /* fmul - fmuls */
2122 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2123
2124 /* fre */
2125 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2126
2127 /* fres */
2128 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2129
2130 /* frsqrte */
2131 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2132
2133 /* frsqrtes */
2134 static void gen_frsqrtes(DisasContext *ctx)
2135 {
2136 if (unlikely(!ctx->fpu_enabled)) {
2137 gen_exception(ctx, POWERPC_EXCP_FPU);
2138 return;
2139 }
2140 /* NIP cannot be restored if the memory exception comes from an helper */
2141 gen_update_nip(ctx, ctx->nip - 4);
2142 gen_reset_fpstatus();
2143 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2144 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2145 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2146 }
2147
2148 /* fsel */
2149 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2150 /* fsub - fsubs */
2151 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2152 /* Optional: */
2153
2154 /* fsqrt */
2155 static void gen_fsqrt(DisasContext *ctx)
2156 {
2157 if (unlikely(!ctx->fpu_enabled)) {
2158 gen_exception(ctx, POWERPC_EXCP_FPU);
2159 return;
2160 }
2161 /* NIP cannot be restored if the memory exception comes from an helper */
2162 gen_update_nip(ctx, ctx->nip - 4);
2163 gen_reset_fpstatus();
2164 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2165 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2166 }
2167
2168 static void gen_fsqrts(DisasContext *ctx)
2169 {
2170 if (unlikely(!ctx->fpu_enabled)) {
2171 gen_exception(ctx, POWERPC_EXCP_FPU);
2172 return;
2173 }
2174 /* NIP cannot be restored if the memory exception comes from an helper */
2175 gen_update_nip(ctx, ctx->nip - 4);
2176 gen_reset_fpstatus();
2177 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2178 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2179 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2180 }
2181
2182 /*** Floating-Point multiply-and-add ***/
2183 /* fmadd - fmadds */
2184 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2185 /* fmsub - fmsubs */
2186 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2187 /* fnmadd - fnmadds */
2188 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2189 /* fnmsub - fnmsubs */
2190 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2191
2192 /*** Floating-Point round & convert ***/
2193 /* fctiw */
2194 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2195 /* fctiwz */
2196 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2197 /* frsp */
2198 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2199 #if defined(TARGET_PPC64)
2200 /* fcfid */
2201 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2202 /* fctid */
2203 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2204 /* fctidz */
2205 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2206 #endif
2207
2208 /* frin */
2209 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2210 /* friz */
2211 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2212 /* frip */
2213 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2214 /* frim */
2215 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2216
2217 /*** Floating-Point compare ***/
2218
2219 /* fcmpo */
2220 static void gen_fcmpo(DisasContext *ctx)
2221 {
2222 TCGv_i32 crf;
2223 if (unlikely(!ctx->fpu_enabled)) {
2224 gen_exception(ctx, POWERPC_EXCP_FPU);
2225 return;
2226 }
2227 /* NIP cannot be restored if the memory exception comes from an helper */
2228 gen_update_nip(ctx, ctx->nip - 4);
2229 gen_reset_fpstatus();
2230 crf = tcg_const_i32(crfD(ctx->opcode));
2231 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2232 tcg_temp_free_i32(crf);
2233 gen_helper_float_check_status();
2234 }
2235
2236 /* fcmpu */
2237 static void gen_fcmpu(DisasContext *ctx)
2238 {
2239 TCGv_i32 crf;
2240 if (unlikely(!ctx->fpu_enabled)) {
2241 gen_exception(ctx, POWERPC_EXCP_FPU);
2242 return;
2243 }
2244 /* NIP cannot be restored if the memory exception comes from an helper */
2245 gen_update_nip(ctx, ctx->nip - 4);
2246 gen_reset_fpstatus();
2247 crf = tcg_const_i32(crfD(ctx->opcode));
2248 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2249 tcg_temp_free_i32(crf);
2250 gen_helper_float_check_status();
2251 }
2252
2253 /*** Floating-point move ***/
2254 /* fabs */
2255 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2256 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2257
2258 /* fmr - fmr. */
2259 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2260 static void gen_fmr(DisasContext *ctx)
2261 {
2262 if (unlikely(!ctx->fpu_enabled)) {
2263 gen_exception(ctx, POWERPC_EXCP_FPU);
2264 return;
2265 }
2266 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2267 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2268 }
2269
2270 /* fnabs */
2271 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2272 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2273 /* fneg */
2274 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2275 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2276
2277 /*** Floating-Point status & ctrl register ***/
2278
2279 /* mcrfs */
2280 static void gen_mcrfs(DisasContext *ctx)
2281 {
2282 int bfa;
2283
2284 if (unlikely(!ctx->fpu_enabled)) {
2285 gen_exception(ctx, POWERPC_EXCP_FPU);
2286 return;
2287 }
2288 bfa = 4 * (7 - crfS(ctx->opcode));
2289 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2290 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2291 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2292 }
2293
2294 /* mffs */
2295 static void gen_mffs(DisasContext *ctx)
2296 {
2297 if (unlikely(!ctx->fpu_enabled)) {
2298 gen_exception(ctx, POWERPC_EXCP_FPU);
2299 return;
2300 }
2301 gen_reset_fpstatus();
2302 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2303 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2304 }
2305
2306 /* mtfsb0 */
2307 static void gen_mtfsb0(DisasContext *ctx)
2308 {
2309 uint8_t crb;
2310
2311 if (unlikely(!ctx->fpu_enabled)) {
2312 gen_exception(ctx, POWERPC_EXCP_FPU);
2313 return;
2314 }
2315 crb = 31 - crbD(ctx->opcode);
2316 gen_reset_fpstatus();
2317 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2318 TCGv_i32 t0;
2319 /* NIP cannot be restored if the memory exception comes from an helper */
2320 gen_update_nip(ctx, ctx->nip - 4);
2321 t0 = tcg_const_i32(crb);
2322 gen_helper_fpscr_clrbit(t0);
2323 tcg_temp_free_i32(t0);
2324 }
2325 if (unlikely(Rc(ctx->opcode) != 0)) {
2326 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2327 }
2328 }
2329
2330 /* mtfsb1 */
2331 static void gen_mtfsb1(DisasContext *ctx)
2332 {
2333 uint8_t crb;
2334
2335 if (unlikely(!ctx->fpu_enabled)) {
2336 gen_exception(ctx, POWERPC_EXCP_FPU);
2337 return;
2338 }
2339 crb = 31 - crbD(ctx->opcode);
2340 gen_reset_fpstatus();
2341 /* XXX: we pretend we can only do IEEE floating-point computations */
2342 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2343 TCGv_i32 t0;
2344 /* NIP cannot be restored if the memory exception comes from an helper */
2345 gen_update_nip(ctx, ctx->nip - 4);
2346 t0 = tcg_const_i32(crb);
2347 gen_helper_fpscr_setbit(t0);
2348 tcg_temp_free_i32(t0);
2349 }
2350 if (unlikely(Rc(ctx->opcode) != 0)) {
2351 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2352 }
2353 /* We can raise a differed exception */
2354 gen_helper_float_check_status();
2355 }
2356
2357 /* mtfsf */
2358 static void gen_mtfsf(DisasContext *ctx)
2359 {
2360 TCGv_i32 t0;
2361 int L = ctx->opcode & 0x02000000;
2362
2363 if (unlikely(!ctx->fpu_enabled)) {
2364 gen_exception(ctx, POWERPC_EXCP_FPU);
2365 return;
2366 }
2367 /* NIP cannot be restored if the memory exception comes from an helper */
2368 gen_update_nip(ctx, ctx->nip - 4);
2369 gen_reset_fpstatus();
2370 if (L)
2371 t0 = tcg_const_i32(0xff);
2372 else
2373 t0 = tcg_const_i32(FM(ctx->opcode));
2374 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2375 tcg_temp_free_i32(t0);
2376 if (unlikely(Rc(ctx->opcode) != 0)) {
2377 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2378 }
2379 /* We can raise a differed exception */
2380 gen_helper_float_check_status();
2381 }
2382
2383 /* mtfsfi */
2384 static void gen_mtfsfi(DisasContext *ctx)
2385 {
2386 int bf, sh;
2387 TCGv_i64 t0;
2388 TCGv_i32 t1;
2389
2390 if (unlikely(!ctx->fpu_enabled)) {
2391 gen_exception(ctx, POWERPC_EXCP_FPU);
2392 return;
2393 }
2394 bf = crbD(ctx->opcode) >> 2;
2395 sh = 7 - bf;
2396 /* NIP cannot be restored if the memory exception comes from an helper */
2397 gen_update_nip(ctx, ctx->nip - 4);
2398 gen_reset_fpstatus();
2399 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2400 t1 = tcg_const_i32(1 << sh);
2401 gen_helper_store_fpscr(t0, t1);
2402 tcg_temp_free_i64(t0);
2403 tcg_temp_free_i32(t1);
2404 if (unlikely(Rc(ctx->opcode) != 0)) {
2405 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2406 }
2407 /* We can raise a differed exception */
2408 gen_helper_float_check_status();
2409 }
2410
2411 /*** Addressing modes ***/
2412 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2413 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2414 target_long maskl)
2415 {
2416 target_long simm = SIMM(ctx->opcode);
2417
2418 simm &= ~maskl;
2419 if (rA(ctx->opcode) == 0) {
2420 #if defined(TARGET_PPC64)
2421 if (!ctx->sf_mode) {
2422 tcg_gen_movi_tl(EA, (uint32_t)simm);
2423 } else
2424 #endif
2425 tcg_gen_movi_tl(EA, simm);
2426 } else if (likely(simm != 0)) {
2427 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2428 #if defined(TARGET_PPC64)
2429 if (!ctx->sf_mode) {
2430 tcg_gen_ext32u_tl(EA, EA);
2431 }
2432 #endif
2433 } else {
2434 #if defined(TARGET_PPC64)
2435 if (!ctx->sf_mode) {
2436 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2437 } else
2438 #endif
2439 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2440 }
2441 }
2442
2443 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2444 {
2445 if (rA(ctx->opcode) == 0) {
2446 #if defined(TARGET_PPC64)
2447 if (!ctx->sf_mode) {
2448 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2449 } else
2450 #endif
2451 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2452 } else {
2453 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2454 #if defined(TARGET_PPC64)
2455 if (!ctx->sf_mode) {
2456 tcg_gen_ext32u_tl(EA, EA);
2457 }
2458 #endif
2459 }
2460 }
2461
2462 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2463 {
2464 if (rA(ctx->opcode) == 0) {
2465 tcg_gen_movi_tl(EA, 0);
2466 } else {
2467 #if defined(TARGET_PPC64)
2468 if (!ctx->sf_mode) {
2469 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2470 } else
2471 #endif
2472 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2473 }
2474 }
2475
2476 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2477 target_long val)
2478 {
2479 tcg_gen_addi_tl(ret, arg1, val);
2480 #if defined(TARGET_PPC64)
2481 if (!ctx->sf_mode) {
2482 tcg_gen_ext32u_tl(ret, ret);
2483 }
2484 #endif
2485 }
2486
2487 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2488 {
2489 int l1 = gen_new_label();
2490 TCGv t0 = tcg_temp_new();
2491 TCGv_i32 t1, t2;
2492 /* NIP cannot be restored if the memory exception comes from an helper */
2493 gen_update_nip(ctx, ctx->nip - 4);
2494 tcg_gen_andi_tl(t0, EA, mask);
2495 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2496 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2497 t2 = tcg_const_i32(0);
2498 gen_helper_raise_exception_err(t1, t2);
2499 tcg_temp_free_i32(t1);
2500 tcg_temp_free_i32(t2);
2501 gen_set_label(l1);
2502 tcg_temp_free(t0);
2503 }
2504
2505 /*** Integer load ***/
2506 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2507 {
2508 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2509 }
2510
2511 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2512 {
2513 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2514 }
2515
2516 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2517 {
2518 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2519 if (unlikely(ctx->le_mode)) {
2520 tcg_gen_bswap16_tl(arg1, arg1);
2521 }
2522 }
2523
2524 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2525 {
2526 if (unlikely(ctx->le_mode)) {
2527 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2528 tcg_gen_bswap16_tl(arg1, arg1);
2529 tcg_gen_ext16s_tl(arg1, arg1);
2530 } else {
2531 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2532 }
2533 }
2534
2535 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2536 {
2537 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2538 if (unlikely(ctx->le_mode)) {
2539 tcg_gen_bswap32_tl(arg1, arg1);
2540 }
2541 }
2542
2543 #if defined(TARGET_PPC64)
2544 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2545 {
2546 if (unlikely(ctx->le_mode)) {
2547 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2548 tcg_gen_bswap32_tl(arg1, arg1);
2549 tcg_gen_ext32s_tl(arg1, arg1);
2550 } else
2551 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2552 }
2553 #endif
2554
2555 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2556 {
2557 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2558 if (unlikely(ctx->le_mode)) {
2559 tcg_gen_bswap64_i64(arg1, arg1);
2560 }
2561 }
2562
2563 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2564 {
2565 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2566 }
2567
2568 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2569 {
2570 if (unlikely(ctx->le_mode)) {
2571 TCGv t0 = tcg_temp_new();
2572 tcg_gen_ext16u_tl(t0, arg1);
2573 tcg_gen_bswap16_tl(t0, t0);
2574 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2575 tcg_temp_free(t0);
2576 } else {
2577 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2578 }
2579 }
2580
2581 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2582 {
2583 if (unlikely(ctx->le_mode)) {
2584 TCGv t0 = tcg_temp_new();
2585 tcg_gen_ext32u_tl(t0, arg1);
2586 tcg_gen_bswap32_tl(t0, t0);
2587 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2588 tcg_temp_free(t0);
2589 } else {
2590 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2591 }
2592 }
2593
2594 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2595 {
2596 if (unlikely(ctx->le_mode)) {
2597 TCGv_i64 t0 = tcg_temp_new_i64();
2598 tcg_gen_bswap64_i64(t0, arg1);
2599 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2600 tcg_temp_free_i64(t0);
2601 } else
2602 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2603 }
2604
2605 #define GEN_LD(name, ldop, opc, type) \
2606 static void glue(gen_, name)(DisasContext *ctx) \
2607 { \
2608 TCGv EA; \
2609 gen_set_access_type(ctx, ACCESS_INT); \
2610 EA = tcg_temp_new(); \
2611 gen_addr_imm_index(ctx, EA, 0); \
2612 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2613 tcg_temp_free(EA); \
2614 }
2615
2616 #define GEN_LDU(name, ldop, opc, type) \
2617 static void glue(gen_, name##u)(DisasContext *ctx) \
2618 { \
2619 TCGv EA; \
2620 if (unlikely(rA(ctx->opcode) == 0 || \
2621 rA(ctx->opcode) == rD(ctx->opcode))) { \
2622 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2623 return; \
2624 } \
2625 gen_set_access_type(ctx, ACCESS_INT); \
2626 EA = tcg_temp_new(); \
2627 if (type == PPC_64B) \
2628 gen_addr_imm_index(ctx, EA, 0x03); \
2629 else \
2630 gen_addr_imm_index(ctx, EA, 0); \
2631 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2632 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2633 tcg_temp_free(EA); \
2634 }
2635
2636 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2637 static void glue(gen_, name##ux)(DisasContext *ctx) \
2638 { \
2639 TCGv EA; \
2640 if (unlikely(rA(ctx->opcode) == 0 || \
2641 rA(ctx->opcode) == rD(ctx->opcode))) { \
2642 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2643 return; \
2644 } \
2645 gen_set_access_type(ctx, ACCESS_INT); \
2646 EA = tcg_temp_new(); \
2647 gen_addr_reg_index(ctx, EA); \
2648 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2649 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2650 tcg_temp_free(EA); \
2651 }
2652
2653 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2654 static void glue(gen_, name##x)(DisasContext *ctx) \
2655 { \
2656 TCGv EA; \
2657 gen_set_access_type(ctx, ACCESS_INT); \
2658 EA = tcg_temp_new(); \
2659 gen_addr_reg_index(ctx, EA); \
2660 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2661 tcg_temp_free(EA); \
2662 }
2663
2664 #define GEN_LDS(name, ldop, op, type) \
2665 GEN_LD(name, ldop, op | 0x20, type); \
2666 GEN_LDU(name, ldop, op | 0x21, type); \
2667 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2668 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2669
2670 /* lbz lbzu lbzux lbzx */
2671 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2672 /* lha lhau lhaux lhax */
2673 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2674 /* lhz lhzu lhzux lhzx */
2675 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2676 /* lwz lwzu lwzux lwzx */
2677 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2678 #if defined(TARGET_PPC64)
2679 /* lwaux */
2680 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2681 /* lwax */
2682 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2683 /* ldux */
2684 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2685 /* ldx */
2686 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2687
2688 static void gen_ld(DisasContext *ctx)
2689 {
2690 TCGv EA;
2691 if (Rc(ctx->opcode)) {
2692 if (unlikely(rA(ctx->opcode) == 0 ||
2693 rA(ctx->opcode) == rD(ctx->opcode))) {
2694 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2695 return;
2696 }
2697 }
2698 gen_set_access_type(ctx, ACCESS_INT);
2699 EA = tcg_temp_new();
2700 gen_addr_imm_index(ctx, EA, 0x03);
2701 if (ctx->opcode & 0x02) {
2702 /* lwa (lwau is undefined) */
2703 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2704 } else {
2705 /* ld - ldu */
2706 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2707 }
2708 if (Rc(ctx->opcode))
2709 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2710 tcg_temp_free(EA);
2711 }
2712
2713 /* lq */
2714 static void gen_lq(DisasContext *ctx)
2715 {
2716 #if defined(CONFIG_USER_ONLY)
2717 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2718 #else
2719 int ra, rd;
2720 TCGv EA;
2721
2722 /* Restore CPU state */
2723 if (unlikely(ctx->mem_idx == 0)) {
2724 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2725 return;
2726 }
2727 ra = rA(ctx->opcode);
2728 rd = rD(ctx->opcode);
2729 if (unlikely((rd & 1) || rd == ra)) {
2730 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2731 return;
2732 }
2733 if (unlikely(ctx->le_mode)) {
2734 /* Little-endian mode is not handled */
2735 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2736 return;
2737 }
2738 gen_set_access_type(ctx, ACCESS_INT);
2739 EA = tcg_temp_new();
2740 gen_addr_imm_index(ctx, EA, 0x0F);
2741 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2742 gen_addr_add(ctx, EA, EA, 8);
2743 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2744 tcg_temp_free(EA);
2745 #endif
2746 }
2747 #endif
2748
2749 /*** Integer store ***/
2750 #define GEN_ST(name, stop, opc, type) \
2751 static void glue(gen_, name)(DisasContext *ctx) \
2752 { \
2753 TCGv EA; \
2754 gen_set_access_type(ctx, ACCESS_INT); \
2755 EA = tcg_temp_new(); \
2756 gen_addr_imm_index(ctx, EA, 0); \
2757 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2758 tcg_temp_free(EA); \
2759 }
2760
2761 #define GEN_STU(name, stop, opc, type) \
2762 static void glue(gen_, stop##u)(DisasContext *ctx) \
2763 { \
2764 TCGv EA; \
2765 if (unlikely(rA(ctx->opcode) == 0)) { \
2766 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2767 return; \
2768 } \
2769 gen_set_access_type(ctx, ACCESS_INT); \
2770 EA = tcg_temp_new(); \
2771 if (type == PPC_64B) \
2772 gen_addr_imm_index(ctx, EA, 0x03); \
2773 else \
2774 gen_addr_imm_index(ctx, EA, 0); \
2775 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2776 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2777 tcg_temp_free(EA); \
2778 }
2779
2780 #define GEN_STUX(name, stop, opc2, opc3, type) \
2781 static void glue(gen_, name##ux)(DisasContext *ctx) \
2782 { \
2783 TCGv EA; \
2784 if (unlikely(rA(ctx->opcode) == 0)) { \
2785 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2786 return; \
2787 } \
2788 gen_set_access_type(ctx, ACCESS_INT); \
2789 EA = tcg_temp_new(); \
2790 gen_addr_reg_index(ctx, EA); \
2791 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2792 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2793 tcg_temp_free(EA); \
2794 }
2795
2796 #define GEN_STX(name, stop, opc2, opc3, type) \
2797 static void glue(gen_, name##x)(DisasContext *ctx) \
2798 { \
2799 TCGv EA; \
2800 gen_set_access_type(ctx, ACCESS_INT); \
2801 EA = tcg_temp_new(); \
2802 gen_addr_reg_index(ctx, EA); \
2803 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2804 tcg_temp_free(EA); \
2805 }
2806
2807 #define GEN_STS(name, stop, op, type) \
2808 GEN_ST(name, stop, op | 0x20, type); \
2809 GEN_STU(name, stop, op | 0x21, type); \
2810 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2811 GEN_STX(name, stop, 0x17, op | 0x00, type)
2812
2813 /* stb stbu stbux stbx */
2814 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2815 /* sth sthu sthux sthx */
2816 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2817 /* stw stwu stwux stwx */
2818 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2819 #if defined(TARGET_PPC64)
2820 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2821 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2822
2823 static void gen_std(DisasContext *ctx)
2824 {
2825 int rs;
2826 TCGv EA;
2827
2828 rs = rS(ctx->opcode);
2829 if ((ctx->opcode & 0x3) == 0x2) {
2830 #if defined(CONFIG_USER_ONLY)
2831 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2832 #else
2833 /* stq */
2834 if (unlikely(ctx->mem_idx == 0)) {
2835 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2836 return;
2837 }
2838 if (unlikely(rs & 1)) {
2839 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2840 return;
2841 }
2842 if (unlikely(ctx->le_mode)) {
2843 /* Little-endian mode is not handled */
2844 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2845 return;
2846 }
2847 gen_set_access_type(ctx, ACCESS_INT);
2848 EA = tcg_temp_new();
2849 gen_addr_imm_index(ctx, EA, 0x03);
2850 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2851 gen_addr_add(ctx, EA, EA, 8);
2852 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2853 tcg_temp_free(EA);
2854 #endif
2855 } else {
2856 /* std / stdu */
2857 if (Rc(ctx->opcode)) {
2858 if (unlikely(rA(ctx->opcode) == 0)) {
2859 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2860 return;
2861 }
2862 }
2863 gen_set_access_type(ctx, ACCESS_INT);
2864 EA = tcg_temp_new();
2865 gen_addr_imm_index(ctx, EA, 0x03);
2866 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2867 if (Rc(ctx->opcode))
2868 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2869 tcg_temp_free(EA);
2870 }
2871 }
2872 #endif
2873 /*** Integer load and store with byte reverse ***/
2874 /* lhbrx */
2875 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2876 {
2877 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2878 if (likely(!ctx->le_mode)) {
2879 tcg_gen_bswap16_tl(arg1, arg1);
2880 }
2881 }
2882 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2883
2884 /* lwbrx */
2885 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2886 {
2887 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2888 if (likely(!ctx->le_mode)) {
2889 tcg_gen_bswap32_tl(arg1, arg1);
2890 }
2891 }
2892 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2893
2894 /* sthbrx */
2895 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2896 {
2897 if (likely(!ctx->le_mode)) {
2898 TCGv t0 = tcg_temp_new();
2899 tcg_gen_ext16u_tl(t0, arg1);
2900 tcg_gen_bswap16_tl(t0, t0);
2901 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2902 tcg_temp_free(t0);
2903 } else {
2904 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2905 }
2906 }
2907 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2908
2909 /* stwbrx */
2910 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2911 {
2912 if (likely(!ctx->le_mode)) {
2913 TCGv t0 = tcg_temp_new();
2914 tcg_gen_ext32u_tl(t0, arg1);
2915 tcg_gen_bswap32_tl(t0, t0);
2916 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2917 tcg_temp_free(t0);
2918 } else {
2919 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2920 }
2921 }
2922 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2923
2924 /*** Integer load and store multiple ***/
2925
2926 /* lmw */
2927 static void gen_lmw(DisasContext *ctx)
2928 {
2929 TCGv t0;
2930 TCGv_i32 t1;
2931 gen_set_access_type(ctx, ACCESS_INT);
2932 /* NIP cannot be restored if the memory exception comes from an helper */
2933 gen_update_nip(ctx, ctx->nip - 4);
2934 t0 = tcg_temp_new();
2935 t1 = tcg_const_i32(rD(ctx->opcode));
2936 gen_addr_imm_index(ctx, t0, 0);
2937 gen_helper_lmw(t0, t1);
2938 tcg_temp_free(t0);
2939 tcg_temp_free_i32(t1);
2940 }
2941
2942 /* stmw */
2943 static void gen_stmw(DisasContext *ctx)
2944 {
2945 TCGv t0;
2946 TCGv_i32 t1;
2947 gen_set_access_type(ctx, ACCESS_INT);
2948 /* NIP cannot be restored if the memory exception comes from an helper */
2949 gen_update_nip(ctx, ctx->nip - 4);
2950 t0 = tcg_temp_new();
2951 t1 = tcg_const_i32(rS(ctx->opcode));
2952 gen_addr_imm_index(ctx, t0, 0);
2953 gen_helper_stmw(t0, t1);
2954 tcg_temp_free(t0);
2955 tcg_temp_free_i32(t1);
2956 }
2957
2958 /*** Integer load and store strings ***/
2959
2960 /* lswi */
2961 /* PowerPC32 specification says we must generate an exception if
2962 * rA is in the range of registers to be loaded.
2963 * In an other hand, IBM says this is valid, but rA won't be loaded.
2964 * For now, I'll follow the spec...
2965 */
2966 static void gen_lswi(DisasContext *ctx)
2967 {
2968 TCGv t0;
2969 TCGv_i32 t1, t2;
2970 int nb = NB(ctx->opcode);
2971 int start = rD(ctx->opcode);
2972 int ra = rA(ctx->opcode);
2973 int nr;
2974
2975 if (nb == 0)
2976 nb = 32;
2977 nr = nb / 4;
2978 if (unlikely(((start + nr) > 32 &&
2979 start <= ra && (start + nr - 32) > ra) ||
2980 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2981 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2982 return;
2983 }
2984 gen_set_access_type(ctx, ACCESS_INT);
2985 /* NIP cannot be restored if the memory exception comes from an helper */
2986 gen_update_nip(ctx, ctx->nip - 4);
2987 t0 = tcg_temp_new();
2988 gen_addr_register(ctx, t0);
2989 t1 = tcg_const_i32(nb);
2990 t2 = tcg_const_i32(start);
2991 gen_helper_lsw(t0, t1, t2);
2992 tcg_temp_free(t0);
2993 tcg_temp_free_i32(t1);
2994 tcg_temp_free_i32(t2);
2995 }
2996
2997 /* lswx */
2998 static void gen_lswx(DisasContext *ctx)
2999 {
3000 TCGv t0;
3001 TCGv_i32 t1, t2, t3;
3002 gen_set_access_type(ctx, ACCESS_INT);
3003 /* NIP cannot be restored if the memory exception comes from an helper */
3004 gen_update_nip(ctx, ctx->nip - 4);
3005 t0 = tcg_temp_new();
3006 gen_addr_reg_index(ctx, t0);
3007 t1 = tcg_const_i32(rD(ctx->opcode));
3008 t2 = tcg_const_i32(rA(ctx->opcode));
3009 t3 = tcg_const_i32(rB(ctx->opcode));
3010 gen_helper_lswx(t0, t1, t2, t3);
3011 tcg_temp_free(t0);
3012 tcg_temp_free_i32(t1);
3013 tcg_temp_free_i32(t2);
3014 tcg_temp_free_i32(t3);
3015 }
3016
3017 /* stswi */
3018 static void gen_stswi(DisasContext *ctx)
3019 {
3020 TCGv t0;
3021 TCGv_i32 t1, t2;
3022 int nb = NB(ctx->opcode);
3023 gen_set_access_type(ctx, ACCESS_INT);
3024 /* NIP cannot be restored if the memory exception comes from an helper */
3025 gen_update_nip(ctx, ctx->nip - 4);
3026 t0 = tcg_temp_new();
3027 gen_addr_register(ctx, t0);
3028 if (nb == 0)
3029 nb = 32;
3030 t1 = tcg_const_i32(nb);
3031 t2 = tcg_const_i32(rS(ctx->opcode));
3032 gen_helper_stsw(t0, t1, t2);
3033 tcg_temp_free(t0);
3034 tcg_temp_free_i32(t1);
3035 tcg_temp_free_i32(t2);
3036 }
3037
3038 /* stswx */
3039 static void gen_stswx(DisasContext *ctx)
3040 {
3041 TCGv t0;
3042 TCGv_i32 t1, t2;
3043 gen_set_access_type(ctx, ACCESS_INT);
3044 /* NIP cannot be restored if the memory exception comes from an helper */
3045 gen_update_nip(ctx, ctx->nip - 4);
3046 t0 = tcg_temp_new();
3047 gen_addr_reg_index(ctx, t0);
3048 t1 = tcg_temp_new_i32();
3049 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3050 tcg_gen_andi_i32(t1, t1, 0x7F);
3051 t2 = tcg_const_i32(rS(ctx->opcode));
3052 gen_helper_stsw(t0, t1, t2);
3053 tcg_temp_free(t0);
3054 tcg_temp_free_i32(t1);
3055 tcg_temp_free_i32(t2);
3056 }
3057
3058 /*** Memory synchronisation ***/
3059 /* eieio */
3060 static void gen_eieio(DisasContext *ctx)
3061 {
3062 }
3063
3064 /* isync */
3065 static void gen_isync(DisasContext *ctx)
3066 {
3067 gen_stop_exception(ctx);
3068 }
3069
3070 /* lwarx */
3071 static void gen_lwarx(DisasContext *ctx)
3072 {
3073 TCGv t0;
3074 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3075 gen_set_access_type(ctx, ACCESS_RES);
3076 t0 = tcg_temp_local_new();
3077 gen_addr_reg_index(ctx, t0);
3078 gen_check_align(ctx, t0, 0x03);
3079 gen_qemu_ld32u(ctx, gpr, t0);
3080 tcg_gen_mov_tl(cpu_reserve, t0);
3081 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3082 tcg_temp_free(t0);
3083 }
3084
3085 #if defined(CONFIG_USER_ONLY)
3086 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3087 int reg, int size)
3088 {
3089 TCGv t0 = tcg_temp_new();
3090 uint32_t save_exception = ctx->exception;
3091
3092 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3093 tcg_gen_movi_tl(t0, (size << 5) | reg);
3094 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3095 tcg_temp_free(t0);
3096 gen_update_nip(ctx, ctx->nip-4);
3097 ctx->exception = POWERPC_EXCP_BRANCH;
3098 gen_exception(ctx, POWERPC_EXCP_STCX);
3099 ctx->exception = save_exception;
3100 }
3101 #endif
3102
3103 /* stwcx. */
3104 static void gen_stwcx_(DisasContext *ctx)
3105 {
3106 TCGv t0;
3107 gen_set_access_type(ctx, ACCESS_RES);
3108 t0 = tcg_temp_local_new();
3109 gen_addr_reg_index(ctx, t0);
3110 gen_check_align(ctx, t0, 0x03);
3111 #if defined(CONFIG_USER_ONLY)
3112 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3113 #else
3114 {
3115 int l1;
3116
3117 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3118 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3119 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3120 l1 = gen_new_label();
3121 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3122 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3123 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3124 gen_set_label(l1);
3125 tcg_gen_movi_tl(cpu_reserve, -1);
3126 }
3127 #endif
3128 tcg_temp_free(t0);
3129 }
3130
3131 #if defined(TARGET_PPC64)
3132 /* ldarx */
3133 static void gen_ldarx(DisasContext *ctx)
3134 {
3135 TCGv t0;
3136 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3137 gen_set_access_type(ctx, ACCESS_RES);
3138 t0 = tcg_temp_local_new();
3139 gen_addr_reg_index(ctx, t0);
3140 gen_check_align(ctx, t0, 0x07);
3141 gen_qemu_ld64(ctx, gpr, t0);
3142 tcg_gen_mov_tl(cpu_reserve, t0);
3143 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3144 tcg_temp_free(t0);
3145 }
3146
3147 /* stdcx. */
3148 static void gen_stdcx_(DisasContext *ctx)
3149 {
3150 TCGv t0;
3151 gen_set_access_type(ctx, ACCESS_RES);
3152 t0 = tcg_temp_local_new();
3153 gen_addr_reg_index(ctx, t0);
3154 gen_check_align(ctx, t0, 0x07);
3155 #if defined(CONFIG_USER_ONLY)
3156 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3157 #else
3158 {
3159 int l1;
3160 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3161 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3162 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3163 l1 = gen_new_label();
3164 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3165 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3166 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3167 gen_set_label(l1);
3168 tcg_gen_movi_tl(cpu_reserve, -1);
3169 }
3170 #endif
3171 tcg_temp_free(t0);
3172 }
3173 #endif /* defined(TARGET_PPC64) */
3174
3175 /* sync */
3176 static void gen_sync(DisasContext *ctx)
3177 {
3178 }
3179
3180 /* wait */
3181 static void gen_wait(DisasContext *ctx)
3182 {
3183 TCGv_i32 t0 = tcg_temp_new_i32();
3184 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, halted));
3185 tcg_temp_free_i32(t0);
3186 /* Stop translation, as the CPU is supposed to sleep from now */
3187 gen_exception_err(ctx, EXCP_HLT, 1);
3188 }
3189
3190 /*** Floating-point load ***/
3191 #define GEN_LDF(name, ldop, opc, type) \
3192 static void glue(gen_, name)(DisasContext *ctx) \
3193 { \
3194 TCGv EA; \
3195 if (unlikely(!ctx->fpu_enabled)) { \
3196 gen_exception(ctx, POWERPC_EXCP_FPU); \
3197 return; \
3198 } \
3199 gen_set_access_type(ctx, ACCESS_FLOAT); \
3200 EA = tcg_temp_new(); \
3201 gen_addr_imm_index(ctx, EA, 0); \
3202 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3203 tcg_temp_free(EA); \
3204 }
3205
3206 #define GEN_LDUF(name, ldop, opc, type) \
3207 static void glue(gen_, name##u)(DisasContext *ctx) \
3208 { \
3209 TCGv EA; \
3210 if (unlikely(!ctx->fpu_enabled)) { \
3211 gen_exception(ctx, POWERPC_EXCP_FPU); \
3212 return; \
3213 } \
3214 if (unlikely(rA(ctx->opcode) == 0)) { \
3215 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3216 return; \
3217 } \
3218 gen_set_access_type(ctx, ACCESS_FLOAT); \
3219 EA = tcg_temp_new(); \
3220 gen_addr_imm_index(ctx, EA, 0); \
3221 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3222 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3223 tcg_temp_free(EA); \
3224 }
3225
3226 #define GEN_LDUXF(name, ldop, opc, type) \
3227 static void glue(gen_, name##ux)(DisasContext *ctx) \
3228 { \
3229 TCGv EA; \
3230 if (unlikely(!ctx->fpu_enabled)) { \
3231 gen_exception(ctx, POWERPC_EXCP_FPU); \
3232 return; \
3233 } \
3234 if (unlikely(rA(ctx->opcode) == 0)) { \
3235 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3236 return; \
3237 } \
3238 gen_set_access_type(ctx, ACCESS_FLOAT); \
3239 EA = tcg_temp_new(); \
3240 gen_addr_reg_index(ctx, EA); \
3241 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3242 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3243 tcg_temp_free(EA); \
3244 }
3245
3246 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3247 static void glue(gen_, name##x)(DisasContext *ctx) \
3248 { \
3249 TCGv EA; \
3250 if (unlikely(!ctx->fpu_enabled)) { \
3251 gen_exception(ctx, POWERPC_EXCP_FPU); \
3252 return; \
3253 } \
3254 gen_set_access_type(ctx, ACCESS_FLOAT); \
3255 EA = tcg_temp_new(); \
3256 gen_addr_reg_index(ctx, EA); \
3257 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3258 tcg_temp_free(EA); \
3259 }
3260
3261 #define GEN_LDFS(name, ldop, op, type) \
3262 GEN_LDF(name, ldop, op | 0x20, type); \
3263 GEN_LDUF(name, ldop, op | 0x21, type); \
3264 GEN_LDUXF(name, ldop, op | 0x01, type); \
3265 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3266
3267 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3268 {
3269 TCGv t0 = tcg_temp_new();
3270 TCGv_i32 t1 = tcg_temp_new_i32();
3271 gen_qemu_ld32u(ctx, t0, arg2);
3272 tcg_gen_trunc_tl_i32(t1, t0);
3273 tcg_temp_free(t0);
3274 gen_helper_float32_to_float64(arg1, t1);
3275 tcg_temp_free_i32(t1);
3276 }
3277
3278 /* lfd lfdu lfdux lfdx */
3279 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3280 /* lfs lfsu lfsux lfsx */
3281 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3282
3283 /*** Floating-point store ***/
3284 #define GEN_STF(name, stop, opc, type) \
3285 static void glue(gen_, name)(DisasContext *ctx) \
3286 { \
3287 TCGv EA; \
3288 if (unlikely(!ctx->fpu_enabled)) { \
3289 gen_exception(ctx, POWERPC_EXCP_FPU); \
3290 return; \
3291 } \
3292 gen_set_access_type(ctx, ACCESS_FLOAT); \
3293 EA = tcg_temp_new(); \
3294 gen_addr_imm_index(ctx, EA, 0); \
3295 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3296 tcg_temp_free(EA); \
3297 }
3298
3299 #define GEN_STUF(name, stop, opc, type) \
3300 static void glue(gen_, name##u)(DisasContext *ctx) \
3301 { \
3302 TCGv EA; \
3303 if (unlikely(!ctx->fpu_enabled)) { \
3304 gen_exception(ctx, POWERPC_EXCP_FPU); \
3305 return; \
3306 } \
3307 if (unlikely(rA(ctx->opcode) == 0)) { \
3308 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3309 return; \
3310 } \
3311 gen_set_access_type(ctx, ACCESS_FLOAT); \
3312 EA = tcg_temp_new(); \
3313 gen_addr_imm_index(ctx, EA, 0); \
3314 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3315 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3316 tcg_temp_free(EA); \
3317 }
3318
3319 #define GEN_STUXF(name, stop, opc, type) \
3320 static void glue(gen_, name##ux)(DisasContext *ctx) \
3321 { \
3322 TCGv EA; \
3323 if (unlikely(!ctx->fpu_enabled)) { \
3324 gen_exception(ctx, POWERPC_EXCP_FPU); \
3325 return; \
3326 } \
3327 if (unlikely(rA(ctx->opcode) == 0)) { \
3328 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3329 return; \
3330 } \
3331 gen_set_access_type(ctx, ACCESS_FLOAT); \
3332 EA = tcg_temp_new(); \
3333 gen_addr_reg_index(ctx, EA); \
3334 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3335 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3336 tcg_temp_free(EA); \
3337 }
3338
3339 #define GEN_STXF(name, stop, opc2, opc3, type) \
3340 static void glue(gen_, name##x)(DisasContext *ctx) \
3341 { \
3342 TCGv EA; \
3343 if (unlikely(!ctx->fpu_enabled)) { \
3344 gen_exception(ctx, POWERPC_EXCP_FPU); \
3345 return; \
3346 } \
3347 gen_set_access_type(ctx, ACCESS_FLOAT); \
3348 EA = tcg_temp_new(); \
3349 gen_addr_reg_index(ctx, EA); \
3350 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3351 tcg_temp_free(EA); \
3352 }
3353
3354 #define GEN_STFS(name, stop, op, type) \
3355 GEN_STF(name, stop, op | 0x20, type); \
3356 GEN_STUF(name, stop, op | 0x21, type); \
3357 GEN_STUXF(name, stop, op | 0x01, type); \
3358 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3359
3360 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3361 {
3362 TCGv_i32 t0 = tcg_temp_new_i32();
3363 TCGv t1 = tcg_temp_new();
3364 gen_helper_float64_to_float32(t0, arg1);
3365 tcg_gen_extu_i32_tl(t1, t0);
3366 tcg_temp_free_i32(t0);
3367 gen_qemu_st32(ctx, t1, arg2);
3368 tcg_temp_free(t1);
3369 }
3370
3371 /* stfd stfdu stfdux stfdx */
3372 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3373 /* stfs stfsu stfsux stfsx */
3374 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3375
3376 /* Optional: */
3377 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3378 {
3379 TCGv t0 = tcg_temp_new();
3380 tcg_gen_trunc_i64_tl(t0, arg1),
3381 gen_qemu_st32(ctx, t0, arg2);
3382 tcg_temp_free(t0);
3383 }
3384 /* stfiwx */
3385 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3386
3387 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3388 {
3389 #if defined(TARGET_PPC64)
3390 if (ctx->has_cfar)
3391 tcg_gen_movi_tl(cpu_cfar, nip);
3392 #endif
3393 }
3394
3395 /*** Branch ***/
3396 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3397 {
3398 TranslationBlock *tb;
3399 tb = ctx->tb;
3400 #if defined(TARGET_PPC64)
3401 if (!ctx->sf_mode)
3402 dest = (uint32_t) dest;
3403 #endif
3404 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3405 likely(!ctx->singlestep_enabled)) {
3406 tcg_gen_goto_tb(n);
3407 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3408 tcg_gen_exit_tb((tcg_target_long)tb + n);
3409 } else {
3410 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3411 if (unlikely(ctx->singlestep_enabled)) {
3412 if ((ctx->singlestep_enabled &
3413 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3414 ctx->exception == POWERPC_EXCP_BRANCH) {
3415 target_ulong tmp = ctx->nip;
3416 ctx->nip = dest;
3417 gen_exception(ctx, POWERPC_EXCP_TRACE);
3418 ctx->nip = tmp;
3419 }
3420 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3421 gen_debug_exception(ctx);
3422 }
3423 }
3424 tcg_gen_exit_tb(0);
3425 }
3426 }
3427
3428 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3429 {
3430 #if defined(TARGET_PPC64)
3431 if (ctx->sf_mode == 0)
3432 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3433 else
3434 #endif
3435 tcg_gen_movi_tl(cpu_lr, nip);
3436 }
3437
3438 /* b ba bl bla */
3439 static void gen_b(DisasContext *ctx)
3440 {
3441 target_ulong li, target;
3442
3443 ctx->exception = POWERPC_EXCP_BRANCH;
3444 /* sign extend LI */
3445 #if defined(TARGET_PPC64)
3446 if (ctx->sf_mode)
3447 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3448 else
3449 #endif
3450 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3451 if (likely(AA(ctx->opcode) == 0))
3452 target = ctx->nip + li - 4;
3453 else
3454 target = li;
3455 if (LK(ctx->opcode))
3456 gen_setlr(ctx, ctx->nip);
3457 gen_update_cfar(ctx, ctx->nip);
3458 gen_goto_tb(ctx, 0, target);
3459 }
3460
3461 #define BCOND_IM 0
3462 #define BCOND_LR 1
3463 #define BCOND_CTR 2
3464
3465 static inline void gen_bcond(DisasContext *ctx, int type)
3466 {
3467 uint32_t bo = BO(ctx->opcode);
3468 int l1;
3469 TCGv target;
3470
3471 ctx->exception = POWERPC_EXCP_BRANCH;
3472 if (type == BCOND_LR || type == BCOND_CTR) {
3473 target = tcg_temp_local_new();
3474 if (type == BCOND_CTR)
3475 tcg_gen_mov_tl(target, cpu_ctr);
3476 else
3477 tcg_gen_mov_tl(target, cpu_lr);
3478 } else {
3479 TCGV_UNUSED(target);
3480 }
3481 if (LK(ctx->opcode))
3482 gen_setlr(ctx, ctx->nip);
3483 l1 = gen_new_label();
3484 if ((bo & 0x4) == 0) {
3485 /* Decrement and test CTR */
3486 TCGv temp = tcg_temp_new();
3487 if (unlikely(type == BCOND_CTR)) {
3488 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3489 return;
3490 }
3491 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3492 #if defined(TARGET_PPC64)
3493 if (!ctx->sf_mode)
3494 tcg_gen_ext32u_tl(temp, cpu_ctr);
3495 else
3496 #endif
3497 tcg_gen_mov_tl(temp, cpu_ctr);
3498 if (bo & 0x2) {
3499 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3500 } else {
3501 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3502 }
3503 tcg_temp_free(temp);
3504 }
3505 if ((bo & 0x10) == 0) {
3506 /* Test CR */
3507 uint32_t bi = BI(ctx->opcode);
3508 uint32_t mask = 1 << (3 - (bi & 0x03));
3509 TCGv_i32 temp = tcg_temp_new_i32();
3510
3511 if (bo & 0x8) {
3512 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3513 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3514 } else {
3515 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3516 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3517 }
3518 tcg_temp_free_i32(temp);
3519 }
3520 gen_update_cfar(ctx, ctx->nip);
3521 if (type == BCOND_IM) {
3522 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3523 if (likely(AA(ctx->opcode) == 0)) {
3524 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3525 } else {
3526 gen_goto_tb(ctx, 0, li);
3527 }
3528 gen_set_label(l1);
3529 gen_goto_tb(ctx, 1, ctx->nip);
3530 } else {
3531 #if defined(TARGET_PPC64)
3532 if (!(ctx->sf_mode))
3533 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3534 else
3535 #endif
3536 tcg_gen_andi_tl(cpu_nip, target, ~3);
3537 tcg_gen_exit_tb(0);
3538 gen_set_label(l1);
3539 #if defined(TARGET_PPC64)
3540 if (!(ctx->sf_mode))
3541 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3542 else
3543 #endif
3544 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3545 tcg_gen_exit_tb(0);
3546 }
3547 }
3548
3549 static void gen_bc(DisasContext *ctx)
3550 {
3551 gen_bcond(ctx, BCOND_IM);
3552 }
3553
3554 static void gen_bcctr(DisasContext *ctx)
3555 {
3556 gen_bcond(ctx, BCOND_CTR);
3557 }
3558
3559 static void gen_bclr(DisasContext *ctx)
3560 {
3561 gen_bcond(ctx, BCOND_LR);
3562 }
3563
3564 /*** Condition register logical ***/
3565 #define GEN_CRLOGIC(name, tcg_op, opc) \
3566 static void glue(gen_, name)(DisasContext *ctx) \
3567 { \
3568 uint8_t bitmask; \
3569 int sh; \
3570 TCGv_i32 t0, t1; \
3571 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3572 t0 = tcg_temp_new_i32(); \
3573 if (sh > 0) \
3574 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3575 else if (sh < 0) \
3576 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3577 else \
3578 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3579 t1 = tcg_temp_new_i32(); \
3580 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3581 if (sh > 0) \
3582 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3583 else if (sh < 0) \
3584 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3585 else \
3586 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3587 tcg_op(t0, t0, t1); \
3588 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3589 tcg_gen_andi_i32(t0, t0, bitmask); \
3590 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3591 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3592 tcg_temp_free_i32(t0); \
3593 tcg_temp_free_i32(t1); \
3594 }
3595
3596 /* crand */
3597 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3598 /* crandc */
3599 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3600 /* creqv */
3601 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3602 /* crnand */
3603 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3604 /* crnor */
3605 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3606 /* cror */
3607 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3608 /* crorc */
3609 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3610 /* crxor */
3611 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3612
3613 /* mcrf */
3614 static void gen_mcrf(DisasContext *ctx)
3615 {
3616 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3617 }
3618
3619 /*** System linkage ***/
3620
3621 /* rfi (mem_idx only) */
3622 static void gen_rfi(DisasContext *ctx)
3623 {
3624 #if defined(CONFIG_USER_ONLY)
3625 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3626 #else
3627 /* Restore CPU state */
3628 if (unlikely(!ctx->mem_idx)) {
3629 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3630 return;
3631 }
3632 gen_update_cfar(ctx, ctx->nip);
3633 gen_helper_rfi();
3634 gen_sync_exception(ctx);
3635 #endif
3636 }
3637
3638 #if defined(TARGET_PPC64)
3639 static void gen_rfid(DisasContext *ctx)
3640 {
3641 #if defined(CONFIG_USER_ONLY)
3642 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3643 #else
3644 /* Restore CPU state */
3645 if (unlikely(!ctx->mem_idx)) {
3646 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3647 return;
3648 }
3649 gen_update_cfar(ctx, ctx->nip);
3650 gen_helper_rfid();
3651 gen_sync_exception(ctx);
3652 #endif
3653 }
3654
3655 static void gen_hrfid(DisasContext *ctx)
3656 {
3657 #if defined(CONFIG_USER_ONLY)
3658 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3659 #else
3660 /* Restore CPU state */
3661 if (unlikely(ctx->mem_idx <= 1)) {
3662 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3663 return;
3664 }
3665 gen_helper_hrfid();
3666 gen_sync_exception(ctx);
3667 #endif
3668 }
3669 #endif
3670
3671 /* sc */
3672 #if defined(CONFIG_USER_ONLY)
3673 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3674 #else
3675 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3676 #endif
3677 static void gen_sc(DisasContext *ctx)
3678 {
3679 uint32_t lev;
3680
3681 lev = (ctx->opcode >> 5) & 0x7F;
3682 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3683 }
3684
3685 /*** Trap ***/
3686
3687 /* tw */
3688 static void gen_tw(DisasContext *ctx)
3689 {
3690 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3691 /* Update the nip since this might generate a trap exception */
3692 gen_update_nip(ctx, ctx->nip);
3693 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3694 tcg_temp_free_i32(t0);
3695 }
3696
3697 /* twi */
3698 static void gen_twi(DisasContext *ctx)
3699 {
3700 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3701 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3702 /* Update the nip since this might generate a trap exception */
3703 gen_update_nip(ctx, ctx->nip);
3704 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3705 tcg_temp_free(t0);
3706 tcg_temp_free_i32(t1);
3707 }
3708
3709 #if defined(TARGET_PPC64)
3710 /* td */
3711 static void gen_td(DisasContext *ctx)
3712 {
3713 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3714 /* Update the nip since this might generate a trap exception */
3715 gen_update_nip(ctx, ctx->nip);
3716 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3717 tcg_temp_free_i32(t0);
3718 }
3719
3720 /* tdi */
3721 static void gen_tdi(DisasContext *ctx)
3722 {
3723 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3724 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3725 /* Update the nip since this might generate a trap exception */
3726 gen_update_nip(ctx, ctx->nip);
3727 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3728 tcg_temp_free(t0);
3729 tcg_temp_free_i32(t1);
3730 }
3731 #endif
3732
3733 /*** Processor control ***/
3734
3735 /* mcrxr */
3736 static void gen_mcrxr(DisasContext *ctx)
3737 {
3738 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3739 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3740 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3741 }
3742
3743 /* mfcr mfocrf */
3744 static void gen_mfcr(DisasContext *ctx)
3745 {
3746 uint32_t crm, crn;
3747
3748 if (likely(ctx->opcode & 0x00100000)) {
3749 crm = CRM(ctx->opcode);
3750 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3751 crn = ctz32 (crm);
3752 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3753 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3754 cpu_gpr[rD(ctx->opcode)], crn * 4);
3755 }
3756 } else {
3757 TCGv_i32 t0 = tcg_temp_new_i32();
3758 tcg_gen_mov_i32(t0, cpu_crf[0]);
3759 tcg_gen_shli_i32(t0, t0, 4);
3760 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3761 tcg_gen_shli_i32(t0, t0, 4);
3762 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3763 tcg_gen_shli_i32(t0, t0, 4);
3764 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3765 tcg_gen_shli_i32(t0, t0, 4);
3766 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3767 tcg_gen_shli_i32(t0, t0, 4);
3768 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3769 tcg_gen_shli_i32(t0, t0, 4);
3770 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3771 tcg_gen_shli_i32(t0, t0, 4);
3772 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3773 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3774 tcg_temp_free_i32(t0);
3775 }
3776 }
3777
3778 /* mfmsr */
3779 static void gen_mfmsr(DisasContext *ctx)
3780 {
3781 #if defined(CONFIG_USER_ONLY)
3782 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3783 #else
3784 if (unlikely(!ctx->mem_idx)) {
3785 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3786 return;
3787 }
3788 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3789 #endif
3790 }
3791
3792 static void spr_noaccess(void *opaque, int gprn, int sprn)
3793 {
3794 #if 0
3795 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3796 printf("ERROR: try to access SPR %d !\n", sprn);
3797 #endif
3798 }
3799 #define SPR_NOACCESS (&spr_noaccess)
3800
3801 /* mfspr */
3802 static inline void gen_op_mfspr(DisasContext *ctx)
3803 {
3804 void (*read_cb)(void *opaque, int gprn, int sprn);
3805 uint32_t sprn = SPR(ctx->opcode);
3806
3807 #if !defined(CONFIG_USER_ONLY)
3808 if (ctx->mem_idx == 2)
3809 read_cb = ctx->spr_cb[sprn].hea_read;
3810 else if (ctx->mem_idx)
3811 read_cb = ctx->spr_cb[sprn].oea_read;
3812 else
3813 #endif
3814 read_cb = ctx->spr_cb[sprn].uea_read;
3815 if (likely(read_cb != NULL)) {
3816 if (likely(read_cb != SPR_NOACCESS)) {
3817 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3818 } else {
3819 /* Privilege exception */
3820 /* This is a hack to avoid warnings when running Linux:
3821 * this OS breaks the PowerPC virtualisation model,
3822 * allowing userland application to read the PVR
3823 */
3824 if (sprn != SPR_PVR) {
3825 qemu_log("Trying to read privileged spr %d %03x at "
3826 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3827 printf("Trying to read privileged spr %d %03x at "
3828 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3829 }
3830 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3831 }
3832 } else {
3833 /* Not defined */
3834 qemu_log("Trying to read invalid spr %d %03x at "
3835 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3836 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3837 sprn, sprn, ctx->nip);
3838 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3839 }
3840 }
3841
3842 static void gen_mfspr(DisasContext *ctx)
3843 {
3844 gen_op_mfspr(ctx);
3845 }
3846
3847 /* mftb */
3848 static void gen_mftb(DisasContext *ctx)
3849 {
3850 gen_op_mfspr(ctx);
3851 }
3852
3853 /* mtcrf mtocrf*/
3854 static void gen_mtcrf(DisasContext *ctx)
3855 {
3856 uint32_t crm, crn;
3857
3858 crm = CRM(ctx->opcode);
3859 if (likely((ctx->opcode & 0x00100000))) {
3860 if (crm && ((crm & (crm - 1)) == 0)) {
3861 TCGv_i32 temp = tcg_temp_new_i32();
3862 crn = ctz32 (crm);
3863 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3864 tcg_gen_shri_i32(temp, temp, crn * 4);
3865 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3866 tcg_temp_free_i32(temp);
3867 }
3868 } else {
3869 TCGv_i32 temp = tcg_temp_new_i32();
3870 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3871 for (crn = 0 ; crn < 8 ; crn++) {
3872 if (crm & (1 << crn)) {
3873 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3874 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3875 }
3876 }
3877 tcg_temp_free_i32(temp);
3878 }
3879 }
3880
3881 /* mtmsr */
3882 #if defined(TARGET_PPC64)
3883 static void gen_mtmsrd(DisasContext *ctx)
3884 {
3885 #if defined(CONFIG_USER_ONLY)
3886 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3887 #else
3888 if (unlikely(!ctx->mem_idx)) {
3889 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3890 return;
3891 }
3892 if (ctx->opcode & 0x00010000) {
3893 /* Special form that does not need any synchronisation */
3894 TCGv t0 = tcg_temp_new();
3895 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3896 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3897 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3898 tcg_temp_free(t0);
3899 } else {
3900 /* XXX: we need to update nip before the store
3901 * if we enter power saving mode, we will exit the loop
3902 * directly from ppc_store_msr
3903 */
3904 gen_update_nip(ctx, ctx->nip);
3905 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3906 /* Must stop the translation as machine state (may have) changed */
3907 /* Note that mtmsr is not always defined as context-synchronizing */
3908 gen_stop_exception(ctx);
3909 }
3910 #endif
3911 }
3912 #endif
3913
3914 static void gen_mtmsr(DisasContext *ctx)
3915 {
3916 #if defined(CONFIG_USER_ONLY)
3917 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3918 #else
3919 if (unlikely(!ctx->mem_idx)) {
3920 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3921 return;
3922 }
3923 if (ctx->opcode & 0x00010000) {
3924 /* Special form that does not need any synchronisation */
3925 TCGv t0 = tcg_temp_new();
3926 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3927 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3928 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3929 tcg_temp_free(t0);
3930 } else {
3931 TCGv msr = tcg_temp_new();
3932
3933 /* XXX: we need to update nip before the store
3934 * if we enter power saving mode, we will exit the loop
3935 * directly from ppc_store_msr
3936 */
3937 gen_update_nip(ctx, ctx->nip);
3938 #if defined(TARGET_PPC64)
3939 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3940 #else
3941 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3942 #endif
3943 gen_helper_store_msr(msr);
3944 /* Must stop the translation as machine state (may have) changed */
3945 /* Note that mtmsr is not always defined as context-synchronizing */
3946 gen_stop_exception(ctx);
3947 }
3948 #endif
3949 }
3950
3951 /* mtspr */
3952 static void gen_mtspr(DisasContext *ctx)
3953 {
3954 void (*write_cb)(void *opaque, int sprn, int gprn);
3955 uint32_t sprn = SPR(ctx->opcode);
3956
3957 #if !defined(CONFIG_USER_ONLY)
3958 if (ctx->mem_idx == 2)
3959 write_cb = ctx->spr_cb[sprn].hea_write;
3960 else if (ctx->mem_idx)
3961 write_cb = ctx->spr_cb[sprn].oea_write;
3962 else
3963 #endif
3964 write_cb = ctx->spr_cb[sprn].uea_write;
3965 if (likely(write_cb != NULL)) {
3966 if (likely(write_cb != SPR_NOACCESS)) {
3967 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3968 } else {
3969 /* Privilege exception */
3970 qemu_log("Trying to write privileged spr %d %03x at "
3971 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3972 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
3973 "\n", sprn, sprn, ctx->nip);
3974 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3975 }
3976 } else {
3977 /* Not defined */
3978 qemu_log("Trying to write invalid spr %d %03x at "
3979 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3980 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
3981 sprn, sprn, ctx->nip);
3982 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3983 }
3984 }
3985
3986 /*** Cache management ***/
3987
3988 /* dcbf */
3989 static void gen_dcbf(DisasContext *ctx)
3990 {
3991 /* XXX: specification says this is treated as a load by the MMU */
3992 TCGv t0;
3993 gen_set_access_type(ctx, ACCESS_CACHE);
3994 t0 = tcg_temp_new();
3995 gen_addr_reg_index(ctx, t0);
3996 gen_qemu_ld8u(ctx, t0, t0);
3997 tcg_temp_free(t0);
3998 }
3999
4000 /* dcbi (Supervisor only) */
4001 static void gen_dcbi(DisasContext *ctx)
4002 {
4003 #if defined(CONFIG_USER_ONLY)
4004 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4005 #else
4006 TCGv EA, val;
4007 if (unlikely(!ctx->mem_idx)) {
4008 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4009 return;
4010 }
4011 EA = tcg_temp_new();
4012 gen_set_access_type(ctx, ACCESS_CACHE);
4013 gen_addr_reg_index(ctx, EA);
4014 val = tcg_temp_new();
4015 /* XXX: specification says this should be treated as a store by the MMU */
4016 gen_qemu_ld8u(ctx, val, EA);
4017 gen_qemu_st8(ctx, val, EA);
4018 tcg_temp_free(val);
4019 tcg_temp_free(EA);
4020 #endif
4021 }
4022
4023 /* dcdst */
4024 static void gen_dcbst(DisasContext *ctx)
4025 {
4026 /* XXX: specification say this is treated as a load by the MMU */
4027 TCGv t0;
4028 gen_set_access_type(ctx, ACCESS_CACHE);
4029 t0 = tcg_temp_new();
4030 gen_addr_reg_index(ctx, t0);
4031 gen_qemu_ld8u(ctx, t0, t0);
4032 tcg_temp_free(t0);
4033 }
4034
4035 /* dcbt */
4036 static void gen_dcbt(DisasContext *ctx)
4037 {
4038 /* interpreted as no-op */
4039 /* XXX: specification say this is treated as a load by the MMU
4040 * but does not generate any exception
4041 */
4042 }
4043
4044 /* dcbtst */
4045 static void gen_dcbtst(DisasContext *ctx)
4046 {
4047 /* interpreted as no-op */
4048 /* XXX: specification say this is treated as a load by the MMU
4049 * but does not generate any exception
4050 */
4051 }
4052
4053 /* dcbz */
4054 static void gen_dcbz(DisasContext *ctx)
4055 {
4056 TCGv t0;
4057 gen_set_access_type(ctx, ACCESS_CACHE);
4058 /* NIP cannot be restored if the memory exception comes from an helper */
4059 gen_update_nip(ctx, ctx->nip - 4);
4060 t0 = tcg_temp_new();
4061 gen_addr_reg_index(ctx, t0);
4062 gen_helper_dcbz(t0);
4063 tcg_temp_free(t0);
4064 }
4065
4066 static void gen_dcbz_970(DisasContext *ctx)
4067 {
4068 TCGv t0;
4069 gen_set_access_type(ctx, ACCESS_CACHE);
4070 /* NIP cannot be restored if the memory exception comes from an helper */
4071 gen_update_nip(ctx, ctx->nip - 4);
4072 t0 = tcg_temp_new();
4073 gen_addr_reg_index(ctx, t0);
4074 if (ctx->opcode & 0x00200000)
4075 gen_helper_dcbz(t0);
4076 else
4077 gen_helper_dcbz_970(t0);
4078 tcg_temp_free(t0);
4079 }
4080
4081 /* dst / dstt */
4082 static void gen_dst(DisasContext *ctx)
4083 {
4084 if (rA(ctx->opcode) == 0) {
4085 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4086 } else {
4087 /* interpreted as no-op */
4088 }
4089 }
4090
4091 /* dstst /dststt */
4092 static void gen_dstst(DisasContext *ctx)
4093 {
4094 if (rA(ctx->opcode) == 0) {
4095 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4096 } else {
4097 /* interpreted as no-op */
4098 }
4099
4100 }
4101
4102 /* dss / dssall */
4103 static void gen_dss(DisasContext *ctx)
4104 {
4105 /* interpreted as no-op */
4106 }
4107
4108 /* icbi */
4109 static void gen_icbi(DisasContext *ctx)
4110 {
4111 TCGv t0;
4112 gen_set_access_type(ctx, ACCESS_CACHE);
4113 /* NIP cannot be restored if the memory exception comes from an helper */
4114 gen_update_nip(ctx, ctx->nip - 4);
4115 t0 = tcg_temp_new();
4116 gen_addr_reg_index(ctx, t0);
4117 gen_helper_icbi(t0);
4118 tcg_temp_free(t0);
4119 }
4120
4121 /* Optional: */
4122 /* dcba */
4123 static void gen_dcba(DisasContext *ctx)
4124 {
4125 /* interpreted as no-op */
4126 /* XXX: specification say this is treated as a store by the MMU
4127 * but does not generate any exception
4128 */
4129 }
4130
4131 /*** Segment register manipulation ***/
4132 /* Supervisor only: */
4133
4134 /* mfsr */
4135 static void gen_mfsr(DisasContext *ctx)
4136 {
4137 #if defined(CONFIG_USER_ONLY)
4138 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4139 #else
4140 TCGv t0;
4141 if (unlikely(!ctx->mem_idx)) {
4142 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4143 return;
4144 }
4145 t0 = tcg_const_tl(SR(ctx->opcode));
4146 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4147 tcg_temp_free(t0);
4148 #endif
4149 }
4150
4151 /* mfsrin */
4152 static void gen_mfsrin(DisasContext *ctx)
4153 {
4154 #if defined(CONFIG_USER_ONLY)
4155 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4156 #else
4157 TCGv t0;
4158 if (unlikely(!ctx->mem_idx)) {
4159 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4160 return;
4161 }
4162 t0 = tcg_temp_new();
4163 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4164 tcg_gen_andi_tl(t0, t0, 0xF);
4165 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4166 tcg_temp_free(t0);
4167 #endif
4168 }
4169
4170 /* mtsr */
4171 static void gen_mtsr(DisasContext *ctx)
4172 {
4173 #if defined(CONFIG_USER_ONLY)
4174 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4175 #else
4176 TCGv t0;
4177 if (unlikely(!ctx->mem_idx)) {
4178 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4179 return;
4180 }
4181 t0 = tcg_const_tl(SR(ctx->opcode));
4182 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4183 tcg_temp_free(t0);
4184 #endif
4185 }
4186
4187 /* mtsrin */
4188 static void gen_mtsrin(DisasContext *ctx)
4189 {
4190 #if defined(CONFIG_USER_ONLY)
4191 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4192 #else
4193 TCGv t0;
4194 if (unlikely(!ctx->mem_idx)) {
4195 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4196 return;
4197 }
4198 t0 = tcg_temp_new();
4199 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4200 tcg_gen_andi_tl(t0, t0, 0xF);
4201 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4202 tcg_temp_free(t0);
4203 #endif
4204 }
4205
4206 #if defined(TARGET_PPC64)
4207 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4208
4209 /* mfsr */
4210 static void gen_mfsr_64b(DisasContext *ctx)
4211 {
4212 #if defined(CONFIG_USER_ONLY)
4213 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4214 #else
4215 TCGv t0;
4216 if (unlikely(!ctx->mem_idx)) {
4217 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4218 return;
4219 }
4220 t0 = tcg_const_tl(SR(ctx->opcode));
4221 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4222 tcg_temp_free(t0);
4223 #endif
4224 }
4225
4226 /* mfsrin */
4227 static void gen_mfsrin_64b(DisasContext *ctx)
4228 {
4229 #if defined(CONFIG_USER_ONLY)
4230 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4231 #else
4232 TCGv t0;
4233 if (unlikely(!ctx->mem_idx)) {
4234 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4235 return;
4236 }
4237 t0 = tcg_temp_new();
4238 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4239 tcg_gen_andi_tl(t0, t0, 0xF);
4240 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4241 tcg_temp_free(t0);
4242 #endif
4243 }
4244
4245 /* mtsr */
4246 static void gen_mtsr_64b(DisasContext *ctx)
4247 {
4248 #if defined(CONFIG_USER_ONLY)
4249 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4250 #else
4251 TCGv t0;
4252 if (unlikely(!ctx->mem_idx)) {
4253 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4254 return;
4255 }
4256 t0 = tcg_const_tl(SR(ctx->opcode));
4257 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4258 tcg_temp_free(t0);
4259 #endif
4260 }
4261
4262 /* mtsrin */
4263 static void gen_mtsrin_64b(DisasContext *ctx)
4264 {
4265 #if defined(CONFIG_USER_ONLY)
4266 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4267 #else
4268 TCGv t0;
4269 if (unlikely(!ctx->mem_idx)) {
4270 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4271 return;
4272 }
4273 t0 = tcg_temp_new();
4274 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4275 tcg_gen_andi_tl(t0, t0, 0xF);
4276 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4277 tcg_temp_free(t0);
4278 #endif
4279 }
4280
4281 /* slbmte */
4282 static void gen_slbmte(DisasContext *ctx)
4283 {
4284 #if defined(CONFIG_USER_ONLY)
4285 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4286 #else
4287 if (unlikely(!ctx->mem_idx)) {
4288 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4289 return;
4290 }
4291 gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
4292 #endif
4293 }
4294
4295 static void gen_slbmfee(DisasContext *ctx)
4296 {
4297 #if defined(CONFIG_USER_ONLY)
4298 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4299 #else
4300 if (unlikely(!ctx->mem_idx)) {
4301 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4302 return;
4303 }
4304 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)],
4305 cpu_gpr[rB(ctx->opcode)]);
4306 #endif
4307 }
4308
4309 static void gen_slbmfev(DisasContext *ctx)
4310 {
4311 #if defined(CONFIG_USER_ONLY)
4312 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4313 #else
4314 if (unlikely(!ctx->mem_idx)) {
4315 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4316 return;
4317 }
4318 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)],
4319 cpu_gpr[rB(ctx->opcode)]);
4320 #endif
4321 }
4322 #endif /* defined(TARGET_PPC64) */
4323
4324 /*** Lookaside buffer management ***/
4325 /* Optional & mem_idx only: */
4326
4327 /* tlbia */
4328 static void gen_tlbia(DisasContext *ctx)
4329 {
4330 #if defined(CONFIG_USER_ONLY)
4331 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4332 #else
4333 if (unlikely(!ctx->mem_idx)) {
4334 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4335 return;
4336 }
4337 gen_helper_tlbia();
4338 #endif
4339 }
4340
4341 /* tlbiel */
4342 static void gen_tlbiel(DisasContext *ctx)
4343 {
4344 #if defined(CONFIG_USER_ONLY)
4345 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4346 #else
4347 if (unlikely(!ctx->mem_idx)) {
4348 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4349 return;
4350 }
4351 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4352 #endif
4353 }
4354
4355 /* tlbie */
4356 static void gen_tlbie(DisasContext *ctx)
4357 {
4358 #if defined(CONFIG_USER_ONLY)
4359 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4360 #else
4361 if (unlikely(!ctx->mem_idx)) {
4362 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4363 return;
4364 }
4365 #if defined(TARGET_PPC64)
4366 if (!ctx->sf_mode) {
4367 TCGv t0 = tcg_temp_new();
4368 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4369 gen_helper_tlbie(t0);
4370 tcg_temp_free(t0);
4371 } else
4372 #endif
4373 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4374 #endif
4375 }
4376
4377 /* tlbsync */
4378 static void gen_tlbsync(DisasContext *ctx)
4379 {
4380 #if defined(CONFIG_USER_ONLY)
4381 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4382 #else
4383 if (unlikely(!ctx->mem_idx)) {
4384 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4385 return;
4386 }
4387 /* This has no effect: it should ensure that all previous
4388 * tlbie have completed
4389 */
4390 gen_stop_exception(ctx);
4391 #endif
4392 }
4393
4394 #if defined(TARGET_PPC64)
4395 /* slbia */
4396 static void gen_slbia(DisasContext *ctx)
4397 {
4398 #if defined(CONFIG_USER_ONLY)
4399 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4400 #else
4401 if (unlikely(!ctx->mem_idx)) {
4402 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4403 return;
4404 }
4405 gen_helper_slbia();
4406 #endif
4407 }
4408
4409 /* slbie */
4410 static void gen_slbie(DisasContext *ctx)
4411 {
4412 #if defined(CONFIG_USER_ONLY)
4413 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4414 #else
4415 if (unlikely(!ctx->mem_idx)) {
4416 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4417 return;
4418 }
4419 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
4420 #endif
4421 }
4422 #endif
4423
4424 /*** External control ***/
4425 /* Optional: */
4426
4427 /* eciwx */
4428 static void gen_eciwx(DisasContext *ctx)
4429 {
4430 TCGv t0;
4431 /* Should check EAR[E] ! */
4432 gen_set_access_type(ctx, ACCESS_EXT);
4433 t0 = tcg_temp_new();
4434 gen_addr_reg_index(ctx, t0);
4435 gen_check_align(ctx, t0, 0x03);
4436 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4437 tcg_temp_free(t0);
4438 }
4439
4440 /* ecowx */
4441 static void gen_ecowx(DisasContext *ctx)
4442 {
4443 TCGv t0;
4444 /* Should check EAR[E] ! */
4445 gen_set_access_type(ctx, ACCESS_EXT);
4446 t0 = tcg_temp_new();
4447 gen_addr_reg_index(ctx, t0);
4448 gen_check_align(ctx, t0, 0x03);
4449 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4450 tcg_temp_free(t0);
4451 }
4452
4453 /* PowerPC 601 specific instructions */
4454
4455 /* abs - abs. */
4456 static void gen_abs(DisasContext *ctx)
4457 {
4458 int l1 = gen_new_label();
4459 int l2 = gen_new_label();
4460 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4461 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4462 tcg_gen_br(l2);
4463 gen_set_label(l1);
4464 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4465 gen_set_label(l2);
4466 if (unlikely(Rc(ctx->opcode) != 0))
4467 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4468 }
4469
4470 /* abso - abso. */
4471 static void gen_abso(DisasContext *ctx)
4472 {
4473 int l1 = gen_new_label();
4474 int l2 = gen_new_label();
4475 int l3 = gen_new_label();
4476 /* Start with XER OV disabled, the most likely case */
4477 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4478 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4479 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4480 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4481 tcg_gen_br(l2);
4482 gen_set_label(l1);
4483 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4484 tcg_gen_br(l3);
4485 gen_set_label(l2);
4486 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4487 gen_set_label(l3);
4488 if (unlikely(Rc(ctx->opcode) != 0))
4489 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4490 }
4491
4492 /* clcs */
4493 static void gen_clcs(DisasContext *ctx)
4494 {
4495 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4496 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4497 tcg_temp_free_i32(t0);
4498 /* Rc=1 sets CR0 to an undefined state */
4499 }
4500
4501 /* div - div. */
4502 static void gen_div(DisasContext *ctx)
4503 {
4504 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4505 if (unlikely(Rc(ctx->opcode) != 0))
4506 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4507 }
4508
4509 /* divo - divo. */
4510 static void gen_divo(DisasContext *ctx)
4511 {
4512 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4513 if (unlikely(Rc(ctx->opcode) != 0))
4514 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4515 }
4516
4517 /* divs - divs. */
4518 static void gen_divs(DisasContext *ctx)
4519 {
4520 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4521 if (unlikely(Rc(ctx->opcode) != 0))
4522 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4523 }
4524
4525 /* divso - divso. */
4526 static void gen_divso(DisasContext *ctx)
4527 {
4528 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4529 if (unlikely(Rc(ctx->opcode) != 0))
4530 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4531 }
4532
4533 /* doz - doz. */
4534 static void gen_doz(DisasContext *ctx)
4535 {
4536 int l1 = gen_new_label();
4537 int l2 = gen_new_label();
4538 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4539 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4540 tcg_gen_br(l2);
4541 gen_set_label(l1);
4542 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4543 gen_set_label(l2);
4544 if (unlikely(Rc(ctx->opcode) != 0))
4545 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4546 }
4547
4548 /* dozo - dozo. */
4549 static void gen_dozo(DisasContext *ctx)
4550 {
4551 int l1 = gen_new_label();
4552 int l2 = gen_new_label();
4553 TCGv t0 = tcg_temp_new();
4554 TCGv t1 = tcg_temp_new();
4555 TCGv t2 = tcg_temp_new();
4556 /* Start with XER OV disabled, the most likely case */
4557 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4558 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4559 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4560 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4561 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4562 tcg_gen_andc_tl(t1, t1, t2);
4563 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4564 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4565 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4566 tcg_gen_br(l2);
4567 gen_set_label(l1);
4568 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4569 gen_set_label(l2);
4570 tcg_temp_free(t0);
4571 tcg_temp_free(t1);
4572 tcg_temp_free(t2);
4573 if (unlikely(Rc(ctx->opcode) != 0))
4574 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4575 }
4576
4577 /* dozi */
4578 static void gen_dozi(DisasContext *ctx)
4579 {
4580 target_long simm = SIMM(ctx->opcode);
4581 int l1 = gen_new_label();
4582 int l2 = gen_new_label();
4583 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4584 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4585 tcg_gen_br(l2);
4586 gen_set_label(l1);
4587 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4588 gen_set_label(l2);
4589 if (unlikely(Rc(ctx->opcode) != 0))
4590 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4591 }
4592
4593 /* lscbx - lscbx. */
4594 static void gen_lscbx(DisasContext *ctx)
4595 {
4596 TCGv t0 = tcg_temp_new();
4597 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4598 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4599 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4600
4601 gen_addr_reg_index(ctx, t0);
4602 /* NIP cannot be restored if the memory exception comes from an helper */
4603 gen_update_nip(ctx, ctx->nip - 4);
4604 gen_helper_lscbx(t0, t0, t1, t2, t3);
4605 tcg_temp_free_i32(t1);
4606 tcg_temp_free_i32(t2);
4607 tcg_temp_free_i32(t3);
4608 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4609 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4610 if (unlikely(Rc(ctx->opcode) != 0))
4611 gen_set_Rc0(ctx, t0);
4612 tcg_temp_free(t0);
4613 }
4614
4615 /* maskg - maskg. */
4616 static void gen_maskg(DisasContext *ctx)
4617 {
4618 int l1 = gen_new_label();
4619 TCGv t0 = tcg_temp_new();
4620 TCGv t1 = tcg_temp_new();
4621 TCGv t2 = tcg_temp_new();
4622 TCGv t3 = tcg_temp_new();
4623 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4624 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4625 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4626 tcg_gen_addi_tl(t2, t0, 1);
4627 tcg_gen_shr_tl(t2, t3, t2);
4628 tcg_gen_shr_tl(t3, t3, t1);
4629 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4630 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4631 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4632 gen_set_label(l1);
4633 tcg_temp_free(t0);
4634 tcg_temp_free(t1);
4635 tcg_temp_free(t2);
4636 tcg_temp_free(t3);
4637 if (unlikely(Rc(ctx->opcode) != 0))
4638 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4639 }
4640
4641 /* maskir - maskir. */
4642 static void gen_maskir(DisasContext *ctx)
4643 {
4644 TCGv t0 = tcg_temp_new();
4645 TCGv t1 = tcg_temp_new();
4646 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4647 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4648 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4649 tcg_temp_free(t0);
4650 tcg_temp_free(t1);
4651 if (unlikely(Rc(ctx->opcode) != 0))
4652 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4653 }
4654
4655 /* mul - mul. */
4656 static void gen_mul(DisasContext *ctx)
4657 {
4658 TCGv_i64 t0 = tcg_temp_new_i64();
4659 TCGv_i64 t1 = tcg_temp_new_i64();
4660 TCGv t2 = tcg_temp_new();
4661 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4662 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4663 tcg_gen_mul_i64(t0, t0, t1);
4664 tcg_gen_trunc_i64_tl(t2, t0);
4665 gen_store_spr(SPR_MQ, t2);
4666 tcg_gen_shri_i64(t1, t0, 32);
4667 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4668 tcg_temp_free_i64(t0);
4669 tcg_temp_free_i64(t1);
4670 tcg_temp_free(t2);
4671 if (unlikely(Rc(ctx->opcode) != 0))
4672 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4673 }
4674
4675 /* mulo - mulo. */
4676 static void gen_mulo(DisasContext *ctx)
4677 {
4678 int l1 = gen_new_label();
4679 TCGv_i64 t0 = tcg_temp_new_i64();
4680 TCGv_i64 t1 = tcg_temp_new_i64();
4681 TCGv t2 = tcg_temp_new();
4682 /* Start with XER OV disabled, the most likely case */
4683 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4684 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4685 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4686 tcg_gen_mul_i64(t0, t0, t1);
4687 tcg_gen_trunc_i64_tl(t2, t0);
4688 gen_store_spr(SPR_MQ, t2);
4689 tcg_gen_shri_i64(t1, t0, 32);
4690 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4691 tcg_gen_ext32s_i64(t1, t0);
4692 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4693 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4694 gen_set_label(l1);
4695 tcg_temp_free_i64(t0);
4696 tcg_temp_free_i64(t1);
4697 tcg_temp_free(t2);
4698 if (unlikely(Rc(ctx->opcode) != 0))
4699 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4700 }
4701
4702 /* nabs - nabs. */
4703 static void gen_nabs(DisasContext *ctx)
4704 {
4705 int l1 = gen_new_label();
4706 int l2 = gen_new_label();
4707 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4708 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4709 tcg_gen_br(l2);
4710 gen_set_label(l1);
4711 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4712 gen_set_label(l2);
4713 if (unlikely(Rc(ctx->opcode) != 0))
4714 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4715 }
4716
4717 /* nabso - nabso. */
4718 static void gen_nabso(DisasContext *ctx)
4719 {
4720 int l1 = gen_new_label();
4721 int l2 = gen_new_label();
4722 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4723 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4724 tcg_gen_br(l2);
4725 gen_set_label(l1);
4726 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4727 gen_set_label(l2);
4728 /* nabs never overflows */
4729 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4730 if (unlikely(Rc(ctx->opcode) != 0))
4731 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4732 }
4733
4734 /* rlmi - rlmi. */
4735 static void gen_rlmi(DisasContext *ctx)
4736 {
4737 uint32_t mb = MB(ctx->opcode);
4738 uint32_t me = ME(ctx->opcode);
4739 TCGv t0 = tcg_temp_new();
4740 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4741 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4742 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4743 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4744 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4745 tcg_temp_free(t0);
4746 if (unlikely(Rc(ctx->opcode) != 0))
4747 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4748 }
4749
4750 /* rrib - rrib. */
4751 static void gen_rrib(DisasContext *ctx)
4752 {
4753 TCGv t0 = tcg_temp_new();
4754 TCGv t1 = tcg_temp_new();
4755 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4756 tcg_gen_movi_tl(t1, 0x80000000);
4757 tcg_gen_shr_tl(t1, t1, t0);
4758 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4759 tcg_gen_and_tl(t0, t0, t1);
4760 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4761 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4762 tcg_temp_free(t0);
4763 tcg_temp_free(t1);
4764 if (unlikely(Rc(ctx->opcode) != 0))
4765 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4766 }
4767
4768 /* sle - sle. */
4769 static void gen_sle(DisasContext *ctx)
4770 {
4771 TCGv t0 = tcg_temp_new();
4772 TCGv t1 = tcg_temp_new();
4773 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4774 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4775 tcg_gen_subfi_tl(t1, 32, t1);
4776 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4777 tcg_gen_or_tl(t1, t0, t1);
4778 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4779 gen_store_spr(SPR_MQ, t1);
4780 tcg_temp_free(t0);
4781 tcg_temp_free(t1);
4782 if (unlikely(Rc(ctx->opcode) != 0))
4783 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4784 }
4785
4786 /* sleq - sleq. */
4787 static void gen_sleq(DisasContext *ctx)
4788 {
4789 TCGv t0 = tcg_temp_new();
4790 TCGv t1 = tcg_temp_new();
4791 TCGv t2 = tcg_temp_new();
4792 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4793 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4794 tcg_gen_shl_tl(t2, t2, t0);
4795 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4796 gen_load_spr(t1, SPR_MQ);
4797 gen_store_spr(SPR_MQ, t0);
4798 tcg_gen_and_tl(t0, t0, t2);
4799 tcg_gen_andc_tl(t1, t1, t2);
4800 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4801 tcg_temp_free(t0);
4802 tcg_temp_free(t1);
4803 tcg_temp_free(t2);
4804 if (unlikely(Rc(ctx->opcode) != 0))
4805 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4806 }
4807
4808 /* sliq - sliq. */
4809 static void gen_sliq(DisasContext *ctx)
4810 {
4811 int sh = SH(ctx->opcode);
4812 TCGv t0 = tcg_temp_new();
4813 TCGv t1 = tcg_temp_new();
4814 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4815 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4816 tcg_gen_or_tl(t1, t0, t1);
4817 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4818 gen_store_spr(SPR_MQ, t1);
4819 tcg_temp_free(t0);
4820 tcg_temp_free(t1);
4821 if (unlikely(Rc(ctx->opcode) != 0))
4822 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4823 }
4824
4825 /* slliq - slliq. */
4826 static void gen_slliq(DisasContext *ctx)
4827 {
4828 int sh = SH(ctx->opcode);
4829 TCGv t0 = tcg_temp_new();
4830 TCGv t1 = tcg_temp_new();
4831 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4832 gen_load_spr(t1, SPR_MQ);
4833 gen_store_spr(SPR_MQ, t0);
4834 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4835 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4836 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4837 tcg_temp_free(t0);
4838 tcg_temp_free(t1);
4839 if (unlikely(Rc(ctx->opcode) != 0))
4840 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4841 }
4842
4843 /* sllq - sllq. */
4844 static void gen_sllq(DisasContext *ctx)
4845 {
4846 int l1 = gen_new_label();
4847 int l2 = gen_new_label();
4848 TCGv t0 = tcg_temp_local_new();
4849 TCGv t1 = tcg_temp_local_new();
4850 TCGv t2 = tcg_temp_local_new();
4851 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4852 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4853 tcg_gen_shl_tl(t1, t1, t2);
4854 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4855 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4856 gen_load_spr(t0, SPR_MQ);
4857 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4858 tcg_gen_br(l2);
4859 gen_set_label(l1);
4860 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4861 gen_load_spr(t2, SPR_MQ);
4862 tcg_gen_andc_tl(t1, t2, t1);
4863 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4864 gen_set_label(l2);
4865 tcg_temp_free(t0);
4866 tcg_temp_free(t1);
4867 tcg_temp_free(t2);
4868 if (unlikely(Rc(ctx->opcode) != 0))
4869 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4870 }
4871
4872 /* slq - slq. */
4873 static void gen_slq(DisasContext *ctx)
4874 {
4875 int l1 = gen_new_label();
4876 TCGv t0 = tcg_temp_new();
4877 TCGv t1 = tcg_temp_new();
4878 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4879 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4880 tcg_gen_subfi_tl(t1, 32, t1);
4881 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4882 tcg_gen_or_tl(t1, t0, t1);
4883 gen_store_spr(SPR_MQ, t1);
4884 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4885 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4886 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4887 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4888 gen_set_label(l1);
4889 tcg_temp_free(t0);
4890 tcg_temp_free(t1);
4891 if (unlikely(Rc(ctx->opcode) != 0))
4892 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4893 }
4894
4895 /* sraiq - sraiq. */
4896 static void gen_sraiq(DisasContext *ctx)
4897 {
4898 int sh = SH(ctx->opcode);
4899 int l1 = gen_new_label();
4900 TCGv t0 = tcg_temp_new();
4901 TCGv t1 = tcg_temp_new();
4902 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4903 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4904 tcg_gen_or_tl(t0, t0, t1);
4905 gen_store_spr(SPR_MQ, t0);
4906 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4907 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4908 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4909 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4910 gen_set_label(l1);
4911 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4912 tcg_temp_free(t0);
4913 tcg_temp_free(t1);
4914 if (unlikely(Rc(ctx->opcode) != 0))
4915 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4916 }
4917
4918 /* sraq - sraq. */
4919 static void gen_sraq(DisasContext *ctx)
4920 {
4921 int l1 = gen_new_label();
4922 int l2 = gen_new_label();
4923 TCGv t0 = tcg_temp_new();
4924 TCGv t1 = tcg_temp_local_new();
4925 TCGv t2 = tcg_temp_local_new();
4926 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4927 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4928 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4929 tcg_gen_subfi_tl(t2, 32, t2);
4930 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4931 tcg_gen_or_tl(t0, t0, t2);
4932 gen_store_spr(SPR_MQ, t0);
4933 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4934 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4935 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4936 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4937 gen_set_label(l1);
4938 tcg_temp_free(t0);
4939 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4940 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4941 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4942 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4943 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4944 gen_set_label(l2);
4945 tcg_temp_free(t1);
4946 tcg_temp_free(t2);
4947 if (unlikely(Rc(ctx->opcode) != 0))
4948 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4949 }
4950
4951 /* sre - sre. */
4952 static void gen_sre(DisasContext *ctx)
4953 {
4954 TCGv t0 = tcg_temp_new();
4955 TCGv t1 = tcg_temp_new();
4956 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4957 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4958 tcg_gen_subfi_tl(t1, 32, t1);
4959 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4960 tcg_gen_or_tl(t1, t0, t1);
4961 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4962 gen_store_spr(SPR_MQ, t1);
4963 tcg_temp_free(t0);
4964 tcg_temp_free(t1);
4965 if (unlikely(Rc(ctx->opcode) != 0))
4966 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4967 }
4968
4969 /* srea - srea. */
4970 static void gen_srea(DisasContext *ctx)
4971 {
4972 TCGv t0 = tcg_temp_new();
4973 TCGv t1 = tcg_temp_new();
4974 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4975 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4976 gen_store_spr(SPR_MQ, t0);
4977 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4978 tcg_temp_free(t0);
4979 tcg_temp_free(t1);
4980 if (unlikely(Rc(ctx->opcode) != 0))
4981 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4982 }
4983
4984 /* sreq */
4985 static void gen_sreq(DisasContext *ctx)
4986 {
4987 TCGv t0 = tcg_temp_new();
4988 TCGv t1 = tcg_temp_new();
4989 TCGv t2 = tcg_temp_new();
4990 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4991 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4992 tcg_gen_shr_tl(t1, t1, t0);
4993 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4994 gen_load_spr(t2, SPR_MQ);
4995 gen_store_spr(SPR_MQ, t0);
4996 tcg_gen_and_tl(t0, t0, t1);
4997 tcg_gen_andc_tl(t2, t2, t1);
4998 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4999 tcg_temp_free(t0);
5000 tcg_temp_free(t1);
5001 tcg_temp_free(t2);
5002 if (unlikely(Rc(ctx->opcode) != 0))
5003 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5004 }
5005
5006 /* sriq */
5007 static void gen_sriq(DisasContext *ctx)
5008 {
5009 int sh = SH(ctx->opcode);
5010 TCGv t0 = tcg_temp_new();
5011 TCGv t1 = tcg_temp_new();
5012 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5013 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5014 tcg_gen_or_tl(t1, t0, t1);
5015 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5016 gen_store_spr(SPR_MQ, t1);
5017 tcg_temp_free(t0);
5018 tcg_temp_free(t1);
5019 if (unlikely(Rc(ctx->opcode) != 0))
5020 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5021 }
5022
5023 /* srliq */
5024 static void gen_srliq(DisasContext *ctx)
5025 {
5026 int sh = SH(ctx->opcode);
5027 TCGv t0 = tcg_temp_new();
5028 TCGv t1 = tcg_temp_new();
5029 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5030 gen_load_spr(t1, SPR_MQ);
5031 gen_store_spr(SPR_MQ, t0);
5032 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5033 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5034 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5035 tcg_temp_free(t0);
5036 tcg_temp_free(t1);
5037 if (unlikely(Rc(ctx->opcode) != 0))
5038 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5039 }
5040
5041 /* srlq */
5042 static void gen_srlq(DisasContext *ctx)
5043 {
5044 int l1 = gen_new_label();
5045 int l2 = gen_new_label();
5046 TCGv t0 = tcg_temp_local_new();
5047 TCGv t1 = tcg_temp_local_new();
5048 TCGv t2 = tcg_temp_local_new();
5049 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5050 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5051 tcg_gen_shr_tl(t2, t1, t2);
5052 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5053 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5054 gen_load_spr(t0, SPR_MQ);
5055 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5056 tcg_gen_br(l2);
5057 gen_set_label(l1);
5058 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5059 tcg_gen_and_tl(t0, t0, t2);
5060 gen_load_spr(t1, SPR_MQ);
5061 tcg_gen_andc_tl(t1, t1, t2);
5062 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5063 gen_set_label(l2);
5064 tcg_temp_free(t0);
5065 tcg_temp_free(t1);
5066 tcg_temp_free(t2);
5067 if (unlikely(Rc(ctx->opcode) != 0))
5068 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5069 }
5070
5071 /* srq */
5072 static void gen_srq(DisasContext *ctx)
5073 {
5074 int l1 = gen_new_label();
5075 TCGv t0 = tcg_temp_new();
5076 TCGv t1 = tcg_temp_new();
5077 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5078 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5079 tcg_gen_subfi_tl(t1, 32, t1);
5080 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5081 tcg_gen_or_tl(t1, t0, t1);
5082 gen_store_spr(SPR_MQ, t1);
5083 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5084 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5085 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5086 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5087 gen_set_label(l1);
5088 tcg_temp_free(t0);
5089 tcg_temp_free(t1);
5090 if (unlikely(Rc(ctx->opcode) != 0))
5091 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5092 }
5093
5094 /* PowerPC 602 specific instructions */
5095
5096 /* dsa */
5097 static void gen_dsa(DisasContext *ctx)
5098 {
5099 /* XXX: TODO */
5100 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5101 }
5102
5103 /* esa */
5104 static void gen_esa(DisasContext *ctx)
5105 {
5106 /* XXX: TODO */
5107 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5108 }
5109
5110 /* mfrom */
5111 static void gen_mfrom(DisasContext *ctx)
5112 {
5113 #if defined(CONFIG_USER_ONLY)
5114 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5115 #else
5116 if (unlikely(!ctx->mem_idx)) {
5117 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5118 return;
5119 }
5120 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5121 #endif
5122 }
5123
5124 /* 602 - 603 - G2 TLB management */
5125
5126 /* tlbld */
5127 static void gen_tlbld_6xx(DisasContext *ctx)
5128 {
5129 #if defined(CONFIG_USER_ONLY)
5130 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5131 #else
5132 if (unlikely(!ctx->mem_idx)) {
5133 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5134 return;
5135 }
5136 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5137 #endif
5138 }
5139
5140 /* tlbli */
5141 static void gen_tlbli_6xx(DisasContext *ctx)
5142 {
5143 #if defined(CONFIG_USER_ONLY)
5144 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5145 #else
5146 if (unlikely(!ctx->mem_idx)) {
5147 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5148 return;
5149 }
5150 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5151 #endif
5152 }
5153
5154 /* 74xx TLB management */
5155
5156 /* tlbld */
5157 static void gen_tlbld_74xx(DisasContext *ctx)
5158 {
5159 #if defined(CONFIG_USER_ONLY)
5160 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5161 #else
5162 if (unlikely(!ctx->mem_idx)) {
5163 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5164 return;
5165 }
5166 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5167 #endif
5168 }
5169
5170 /* tlbli */
5171 static void gen_tlbli_74xx(DisasContext *ctx)
5172 {
5173 #if defined(CONFIG_USER_ONLY)
5174 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5175 #else
5176 if (unlikely(!ctx->mem_idx)) {
5177 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5178 return;
5179 }
5180 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5181 #endif
5182 }
5183
5184 /* POWER instructions not in PowerPC 601 */
5185
5186 /* clf */
5187 static void gen_clf(DisasContext *ctx)
5188 {
5189 /* Cache line flush: implemented as no-op */
5190 }
5191
5192 /* cli */
5193 static void gen_cli(DisasContext *ctx)
5194 {
5195 /* Cache line invalidate: privileged and treated as no-op */
5196 #if defined(CONFIG_USER_ONLY)
5197 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5198 #else
5199 if (unlikely(!ctx->mem_idx)) {
5200 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5201 return;
5202 }
5203 #endif
5204 }
5205
5206 /* dclst */
5207 static void gen_dclst(DisasContext *ctx)
5208 {
5209 /* Data cache line store: treated as no-op */
5210 }
5211
5212 static void gen_mfsri(DisasContext *ctx)
5213 {
5214 #if defined(CONFIG_USER_ONLY)
5215 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5216 #else
5217 int ra = rA(ctx->opcode);
5218 int rd = rD(ctx->opcode);
5219 TCGv t0;
5220 if (unlikely(!ctx->mem_idx)) {
5221 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5222 return;
5223 }
5224 t0 = tcg_temp_new();
5225 gen_addr_reg_index(ctx, t0);
5226 tcg_gen_shri_tl(t0, t0, 28);
5227 tcg_gen_andi_tl(t0, t0, 0xF);
5228 gen_helper_load_sr(cpu_gpr[rd], t0);
5229 tcg_temp_free(t0);
5230 if (ra != 0 && ra != rd)
5231 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5232 #endif
5233 }
5234
5235 static void gen_rac(DisasContext *ctx)
5236 {
5237 #if defined(CONFIG_USER_ONLY)
5238 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5239 #else
5240 TCGv t0;
5241 if (unlikely(!ctx->mem_idx)) {
5242 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5243 return;
5244 }
5245 t0 = tcg_temp_new();
5246 gen_addr_reg_index(ctx, t0);
5247 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5248 tcg_temp_free(t0);
5249 #endif
5250 }
5251
5252 static void gen_rfsvc(DisasContext *ctx)
5253 {
5254 #if defined(CONFIG_USER_ONLY)
5255 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5256 #else
5257 if (unlikely(!ctx->mem_idx)) {
5258 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5259 return;
5260 }
5261 gen_helper_rfsvc();
5262 gen_sync_exception(ctx);
5263 #endif
5264 }
5265
5266 /* svc is not implemented for now */
5267
5268 /* POWER2 specific instructions */
5269 /* Quad manipulation (load/store two floats at a time) */
5270
5271 /* lfq */
5272 static void gen_lfq(DisasContext *ctx)
5273 {
5274 int rd = rD(ctx->opcode);
5275 TCGv t0;
5276 gen_set_access_type(ctx, ACCESS_FLOAT);
5277 t0 = tcg_temp_new();
5278 gen_addr_imm_index(ctx, t0, 0);
5279 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5280 gen_addr_add(ctx, t0, t0, 8);
5281 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5282 tcg_temp_free(t0);
5283 }
5284
5285 /* lfqu */
5286 static void gen_lfqu(DisasContext *ctx)
5287 {
5288 int ra = rA(ctx->opcode);
5289 int rd = rD(ctx->opcode);
5290 TCGv t0, t1;
5291 gen_set_access_type(ctx, ACCESS_FLOAT);
5292 t0 = tcg_temp_new();
5293 t1 = tcg_temp_new();
5294 gen_addr_imm_index(ctx, t0, 0);
5295 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5296 gen_addr_add(ctx, t1, t0, 8);
5297 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5298 if (ra != 0)
5299 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5300 tcg_temp_free(t0);
5301 tcg_temp_free(t1);
5302 }
5303
5304 /* lfqux */
5305 static void gen_lfqux(DisasContext *ctx)
5306 {
5307 int ra = rA(ctx->opcode);
5308 int rd = rD(ctx->opcode);
5309 gen_set_access_type(ctx, ACCESS_FLOAT);
5310 TCGv t0, t1;
5311 t0 = tcg_temp_new();
5312 gen_addr_reg_index(ctx, t0);
5313 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5314 t1 = tcg_temp_new();
5315 gen_addr_add(ctx, t1, t0, 8);
5316 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5317 tcg_temp_free(t1);
5318 if (ra != 0)
5319 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5320 tcg_temp_free(t0);
5321 }
5322
5323 /* lfqx */
5324 static void gen_lfqx(DisasContext *ctx)
5325 {
5326 int rd = rD(ctx->opcode);
5327 TCGv t0;
5328 gen_set_access_type(ctx, ACCESS_FLOAT);
5329 t0 = tcg_temp_new();
5330 gen_addr_reg_index(ctx, t0);
5331 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5332 gen_addr_add(ctx, t0, t0, 8);
5333 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5334 tcg_temp_free(t0);
5335 }
5336
5337 /* stfq */
5338 static void gen_stfq(DisasContext *ctx)
5339 {
5340 int rd = rD(ctx->opcode);
5341 TCGv t0;
5342 gen_set_access_type(ctx, ACCESS_FLOAT);
5343 t0 = tcg_temp_new();
5344 gen_addr_imm_index(ctx, t0, 0);
5345 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5346 gen_addr_add(ctx, t0, t0, 8);
5347 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5348 tcg_temp_free(t0);
5349 }
5350
5351 /* stfqu */
5352 static void gen_stfqu(DisasContext *ctx)
5353 {
5354 int ra = rA(ctx->opcode);
5355 int rd = rD(ctx->opcode);
5356 TCGv t0, t1;
5357 gen_set_access_type(ctx, ACCESS_FLOAT);
5358 t0 = tcg_temp_new();
5359 gen_addr_imm_index(ctx, t0, 0);
5360 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5361 t1 = tcg_temp_new();
5362 gen_addr_add(ctx, t1, t0, 8);
5363 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5364 tcg_temp_free(t1);
5365 if (ra != 0)
5366 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5367 tcg_temp_free(t0);
5368 }
5369
5370 /* stfqux */
5371 static void gen_stfqux(DisasContext *ctx)
5372 {
5373 int ra = rA(ctx->opcode);
5374 int rd = rD(ctx->opcode);
5375 TCGv t0, t1;
5376 gen_set_access_type(ctx, ACCESS_FLOAT);
5377 t0 = tcg_temp_new();
5378 gen_addr_reg_index(ctx, t0);
5379 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5380 t1 = tcg_temp_new();
5381 gen_addr_add(ctx, t1, t0, 8);
5382 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5383 tcg_temp_free(t1);
5384 if (ra != 0)
5385 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5386 tcg_temp_free(t0);
5387 }
5388
5389 /* stfqx */
5390 static void gen_stfqx(DisasContext *ctx)
5391 {
5392 int rd = rD(ctx->opcode);
5393 TCGv t0;
5394 gen_set_access_type(ctx, ACCESS_FLOAT);
5395 t0 = tcg_temp_new();
5396 gen_addr_reg_index(ctx, t0);
5397 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5398 gen_addr_add(ctx, t0, t0, 8);
5399 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5400 tcg_temp_free(t0);
5401 }
5402
5403 /* BookE specific instructions */
5404
5405 /* XXX: not implemented on 440 ? */
5406 static void gen_mfapidi(DisasContext *ctx)
5407 {
5408 /* XXX: TODO */
5409 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5410 }
5411
5412 /* XXX: not implemented on 440 ? */
5413 static void gen_tlbiva(DisasContext *ctx)
5414 {
5415 #if defined(CONFIG_USER_ONLY)
5416 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5417 #else
5418 TCGv t0;
5419 if (unlikely(!ctx->mem_idx)) {
5420 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5421 return;
5422 }
5423 t0 = tcg_temp_new();
5424 gen_addr_reg_index(ctx, t0);
5425 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5426 tcg_temp_free(t0);
5427 #endif
5428 }
5429
5430 /* All 405 MAC instructions are translated here */
5431 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5432 int ra, int rb, int rt, int Rc)
5433 {
5434 TCGv t0, t1;
5435
5436 t0 = tcg_temp_local_new();
5437 t1 = tcg_temp_local_new();
5438
5439 switch (opc3 & 0x0D) {
5440 case 0x05:
5441 /* macchw - macchw. - macchwo - macchwo. */
5442 /* macchws - macchws. - macchwso - macchwso. */
5443 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5444 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5445 /* mulchw - mulchw. */
5446 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5447 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5448 tcg_gen_ext16s_tl(t1, t1);
5449 break;
5450 case 0x04:
5451 /* macchwu - macchwu. - macchwuo - macchwuo. */
5452 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5453 /* mulchwu - mulchwu. */
5454 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5455 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5456 tcg_gen_ext16u_tl(t1, t1);
5457 break;
5458 case 0x01:
5459 /* machhw - machhw. - machhwo - machhwo. */
5460 /* machhws - machhws. - machhwso - machhwso. */
5461 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5462 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5463 /* mulhhw - mulhhw. */
5464 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5465 tcg_gen_ext16s_tl(t0, t0);
5466 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5467 tcg_gen_ext16s_tl(t1, t1);
5468 break;
5469 case 0x00:
5470 /* machhwu - machhwu. - machhwuo - machhwuo. */
5471 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5472 /* mulhhwu - mulhhwu. */
5473 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5474 tcg_gen_ext16u_tl(t0, t0);
5475 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5476 tcg_gen_ext16u_tl(t1, t1);
5477 break;
5478 case 0x0D:
5479 /* maclhw - maclhw. - maclhwo - maclhwo. */
5480 /* maclhws - maclhws. - maclhwso - maclhwso. */
5481 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5482 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5483 /* mullhw - mullhw. */
5484 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5485 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5486 break;
5487 case 0x0C:
5488 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5489 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5490 /* mullhwu - mullhwu. */
5491 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5492 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5493 break;
5494 }
5495 if (opc2 & 0x04) {
5496 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5497 tcg_gen_mul_tl(t1, t0, t1);
5498 if (opc2 & 0x02) {
5499 /* nmultiply-and-accumulate (0x0E) */
5500 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5501 } else {
5502 /* multiply-and-accumulate (0x0C) */
5503 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5504 }
5505
5506 if (opc3 & 0x12) {
5507 /* Check overflow and/or saturate */
5508 int l1 = gen_new_label();
5509
5510 if (opc3 & 0x10) {
5511 /* Start with XER OV disabled, the most likely case */
5512 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5513 }
5514 if (opc3 & 0x01) {
5515 /* Signed */
5516 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5517 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5518 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5519 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5520 if (opc3 & 0x02) {
5521 /* Saturate */
5522 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5523 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5524 }
5525 } else {
5526 /* Unsigned */
5527 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5528 if (opc3 & 0x02) {
5529 /* Saturate */
5530 tcg_gen_movi_tl(t0, UINT32_MAX);
5531 }
5532 }
5533 if (opc3 & 0x10) {
5534 /* Check overflow */
5535 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5536 }
5537 gen_set_label(l1);
5538 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5539 }
5540 } else {
5541 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5542 }
5543 tcg_temp_free(t0);
5544 tcg_temp_free(t1);
5545 if (unlikely(Rc) != 0) {
5546 /* Update Rc0 */
5547 gen_set_Rc0(ctx, cpu_gpr[rt]);
5548 }
5549 }
5550
5551 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5552 static void glue(gen_, name)(DisasContext *ctx) \
5553 { \
5554 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5555 rD(ctx->opcode), Rc(ctx->opcode)); \
5556 }
5557
5558 /* macchw - macchw. */
5559 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5560 /* macchwo - macchwo. */
5561 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5562 /* macchws - macchws. */
5563 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5564 /* macchwso - macchwso. */
5565 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5566 /* macchwsu - macchwsu. */
5567 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5568 /* macchwsuo - macchwsuo. */
5569 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5570 /* macchwu - macchwu. */
5571 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5572 /* macchwuo - macchwuo. */
5573 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5574 /* machhw - machhw. */
5575 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5576 /* machhwo - machhwo. */
5577 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5578 /* machhws - machhws. */
5579 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5580 /* machhwso - machhwso. */
5581 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5582 /* machhwsu - machhwsu. */
5583 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5584 /* machhwsuo - machhwsuo. */
5585 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5586 /* machhwu - machhwu. */
5587 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5588 /* machhwuo - machhwuo. */
5589 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5590 /* maclhw - maclhw. */
5591 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5592 /* maclhwo - maclhwo. */
5593 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5594 /* maclhws - maclhws. */
5595 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5596 /* maclhwso - maclhwso. */
5597 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5598 /* maclhwu - maclhwu. */
5599 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5600 /* maclhwuo - maclhwuo. */
5601 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5602 /* maclhwsu - maclhwsu. */
5603 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5604 /* maclhwsuo - maclhwsuo. */
5605 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5606 /* nmacchw - nmacchw. */
5607 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5608 /* nmacchwo - nmacchwo. */
5609 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5610 /* nmacchws - nmacchws. */
5611 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5612 /* nmacchwso - nmacchwso. */
5613 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5614 /* nmachhw - nmachhw. */
5615 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5616 /* nmachhwo - nmachhwo. */
5617 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5618 /* nmachhws - nmachhws. */
5619 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5620 /* nmachhwso - nmachhwso. */
5621 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5622 /* nmaclhw - nmaclhw. */
5623 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5624 /* nmaclhwo - nmaclhwo. */
5625 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5626 /* nmaclhws - nmaclhws. */
5627 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5628 /* nmaclhwso - nmaclhwso. */
5629 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5630
5631 /* mulchw - mulchw. */
5632 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5633 /* mulchwu - mulchwu. */
5634 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5635 /* mulhhw - mulhhw. */
5636 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5637 /* mulhhwu - mulhhwu. */
5638 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5639 /* mullhw - mullhw. */
5640 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5641 /* mullhwu - mullhwu. */
5642 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5643
5644 /* mfdcr */
5645 static void gen_mfdcr(DisasContext *ctx)
5646 {
5647 #if defined(CONFIG_USER_ONLY)
5648 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5649 #else
5650 TCGv dcrn;
5651 if (unlikely(!ctx->mem_idx)) {
5652 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5653 return;
5654 }
5655 /* NIP cannot be restored if the memory exception comes from an helper */
5656 gen_update_nip(ctx, ctx->nip - 4);
5657 dcrn = tcg_const_tl(SPR(ctx->opcode));
5658 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5659 tcg_temp_free(dcrn);
5660 #endif
5661 }
5662
5663 /* mtdcr */
5664 static void gen_mtdcr(DisasContext *ctx)
5665 {
5666 #if defined(CONFIG_USER_ONLY)
5667 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5668 #else
5669 TCGv dcrn;
5670 if (unlikely(!ctx->mem_idx)) {
5671 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5672 return;
5673 }
5674 /* NIP cannot be restored if the memory exception comes from an helper */
5675 gen_update_nip(ctx, ctx->nip - 4);
5676 dcrn = tcg_const_tl(SPR(ctx->opcode));
5677 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5678 tcg_temp_free(dcrn);
5679 #endif
5680 }
5681
5682 /* mfdcrx */
5683 /* XXX: not implemented on 440 ? */
5684 static void gen_mfdcrx(DisasContext *ctx)
5685 {
5686 #if defined(CONFIG_USER_ONLY)
5687 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5688 #else
5689 if (unlikely(!ctx->mem_idx)) {
5690 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5691 return;
5692 }
5693 /* NIP cannot be restored if the memory exception comes from an helper */
5694 gen_update_nip(ctx, ctx->nip - 4);
5695 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5696 /* Note: Rc update flag set leads to undefined state of Rc0 */
5697 #endif
5698 }
5699
5700 /* mtdcrx */
5701 /* XXX: not implemented on 440 ? */
5702 static void gen_mtdcrx(DisasContext *ctx)
5703 {
5704 #if defined(CONFIG_USER_ONLY)
5705 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5706 #else
5707 if (unlikely(!ctx->mem_idx)) {
5708 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5709 return;
5710 }
5711 /* NIP cannot be restored if the memory exception comes from an helper */
5712 gen_update_nip(ctx, ctx->nip - 4);
5713 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5714 /* Note: Rc update flag set leads to undefined state of Rc0 */
5715 #endif
5716 }
5717
5718 /* mfdcrux (PPC 460) : user-mode access to DCR */
5719 static void gen_mfdcrux(DisasContext *ctx)
5720 {
5721 /* NIP cannot be restored if the memory exception comes from an helper */
5722 gen_update_nip(ctx, ctx->nip - 4);
5723 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5724 /* Note: Rc update flag set leads to undefined state of Rc0 */
5725 }
5726
5727 /* mtdcrux (PPC 460) : user-mode access to DCR */
5728 static void gen_mtdcrux(DisasContext *ctx)
5729 {
5730 /* NIP cannot be restored if the memory exception comes from an helper */
5731 gen_update_nip(ctx, ctx->nip - 4);
5732 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5733 /* Note: Rc update flag set leads to undefined state of Rc0 */
5734 }
5735
5736 /* dccci */
5737 static void gen_dccci(DisasContext *ctx)
5738 {
5739 #if defined(CONFIG_USER_ONLY)
5740 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5741 #else
5742 if (unlikely(!ctx->mem_idx)) {
5743 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5744 return;
5745 }
5746 /* interpreted as no-op */
5747 #endif
5748 }
5749
5750 /* dcread */
5751 static void gen_dcread(DisasContext *ctx)
5752 {
5753 #if defined(CONFIG_USER_ONLY)
5754 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5755 #else
5756 TCGv EA, val;
5757 if (unlikely(!ctx->mem_idx)) {
5758 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5759 return;
5760 }
5761 gen_set_access_type(ctx, ACCESS_CACHE);
5762 EA = tcg_temp_new();
5763 gen_addr_reg_index(ctx, EA);
5764 val = tcg_temp_new();
5765 gen_qemu_ld32u(ctx, val, EA);
5766 tcg_temp_free(val);
5767 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5768 tcg_temp_free(EA);
5769 #endif
5770 }
5771
5772 /* icbt */
5773 static void gen_icbt_40x(DisasContext *ctx)
5774 {
5775 /* interpreted as no-op */
5776 /* XXX: specification say this is treated as a load by the MMU
5777 * but does not generate any exception
5778 */
5779 }
5780
5781 /* iccci */
5782 static void gen_iccci(DisasContext *ctx)
5783 {
5784 #if defined(CONFIG_USER_ONLY)
5785 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5786 #else
5787 if (unlikely(!ctx->mem_idx)) {
5788 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5789 return;
5790 }
5791 /* interpreted as no-op */
5792 #endif
5793 }
5794
5795 /* icread */
5796 static void gen_icread(DisasContext *ctx)
5797 {
5798 #if defined(CONFIG_USER_ONLY)
5799 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5800 #else
5801 if (unlikely(!ctx->mem_idx)) {
5802 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5803 return;
5804 }
5805 /* interpreted as no-op */
5806 #endif
5807 }
5808
5809 /* rfci (mem_idx only) */
5810 static void gen_rfci_40x(DisasContext *ctx)
5811 {
5812 #if defined(CONFIG_USER_ONLY)
5813 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5814 #else
5815 if (unlikely(!ctx->mem_idx)) {
5816 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5817 return;
5818 }
5819 /* Restore CPU state */
5820 gen_helper_40x_rfci();
5821 gen_sync_exception(ctx);
5822 #endif
5823 }
5824
5825 static void gen_rfci(DisasContext *ctx)
5826 {
5827 #if defined(CONFIG_USER_ONLY)
5828 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5829 #else
5830 if (unlikely(!ctx->mem_idx)) {
5831 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5832 return;
5833 }
5834 /* Restore CPU state */
5835 gen_helper_rfci();
5836 gen_sync_exception(ctx);
5837 #endif
5838 }
5839
5840 /* BookE specific */
5841
5842 /* XXX: not implemented on 440 ? */
5843 static void gen_rfdi(DisasContext *ctx)
5844 {
5845 #if defined(CONFIG_USER_ONLY)
5846 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5847 #else
5848 if (unlikely(!ctx->mem_idx)) {
5849 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5850 return;
5851 }
5852 /* Restore CPU state */
5853 gen_helper_rfdi();
5854 gen_sync_exception(ctx);
5855 #endif
5856 }
5857
5858 /* XXX: not implemented on 440 ? */
5859 static void gen_rfmci(DisasContext *ctx)
5860 {
5861 #if defined(CONFIG_USER_ONLY)
5862 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5863 #else
5864 if (unlikely(!ctx->mem_idx)) {
5865 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5866 return;
5867 }
5868 /* Restore CPU state */
5869 gen_helper_rfmci();
5870 gen_sync_exception(ctx);
5871 #endif
5872 }
5873
5874 /* TLB management - PowerPC 405 implementation */
5875
5876 /* tlbre */
5877 static void gen_tlbre_40x(DisasContext *ctx)
5878 {
5879 #if defined(CONFIG_USER_ONLY)
5880 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5881 #else
5882 if (unlikely(!ctx->mem_idx)) {
5883 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5884 return;
5885 }
5886 switch (rB(ctx->opcode)) {
5887 case 0:
5888 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5889 break;
5890 case 1:
5891 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5892 break;
5893 default:
5894 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5895 break;
5896 }
5897 #endif
5898 }
5899
5900 /* tlbsx - tlbsx. */
5901 static void gen_tlbsx_40x(DisasContext *ctx)
5902 {
5903 #if defined(CONFIG_USER_ONLY)
5904 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5905 #else
5906 TCGv t0;
5907 if (unlikely(!ctx->mem_idx)) {
5908 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5909 return;
5910 }
5911 t0 = tcg_temp_new();
5912 gen_addr_reg_index(ctx, t0);
5913 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5914 tcg_temp_free(t0);
5915 if (Rc(ctx->opcode)) {
5916 int l1 = gen_new_label();
5917 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5918 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5919 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5920 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5921 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5922 gen_set_label(l1);
5923 }
5924 #endif
5925 }
5926
5927 /* tlbwe */
5928 static void gen_tlbwe_40x(DisasContext *ctx)
5929 {
5930 #if defined(CONFIG_USER_ONLY)
5931 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5932 #else
5933 if (unlikely(!ctx->mem_idx)) {
5934 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5935 return;
5936 }
5937 switch (rB(ctx->opcode)) {
5938 case 0:
5939 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5940 break;
5941 case 1:
5942 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5943 break;
5944 default:
5945 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5946 break;
5947 }
5948 #endif
5949 }
5950
5951 /* TLB management - PowerPC 440 implementation */
5952
5953 /* tlbre */
5954 static void gen_tlbre_440(DisasContext *ctx)
5955 {
5956 #if defined(CONFIG_USER_ONLY)
5957 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5958 #else
5959 if (unlikely(!ctx->mem_idx)) {
5960 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5961 return;
5962 }
5963 switch (rB(ctx->opcode)) {
5964 case 0:
5965 case 1:
5966 case 2:
5967 {
5968 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5969 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], t0, cpu_gpr[rA(ctx->opcode)]);
5970 tcg_temp_free_i32(t0);
5971 }
5972 break;
5973 default:
5974 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5975 break;
5976 }
5977 #endif
5978 }
5979
5980 /* tlbsx - tlbsx. */
5981 static void gen_tlbsx_440(DisasContext *ctx)
5982 {
5983 #if defined(CONFIG_USER_ONLY)
5984 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5985 #else
5986 TCGv t0;
5987 if (unlikely(!ctx->mem_idx)) {
5988 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5989 return;
5990 }
5991 t0 = tcg_temp_new();
5992 gen_addr_reg_index(ctx, t0);
5993 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5994 tcg_temp_free(t0);
5995 if (Rc(ctx->opcode)) {
5996 int l1 = gen_new_label();
5997 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5998 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5999 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
6000 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6001 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6002 gen_set_label(l1);
6003 }
6004 #endif
6005 }
6006
6007 /* tlbwe */
6008 static void gen_tlbwe_440(DisasContext *ctx)
6009 {
6010 #if defined(CONFIG_USER_ONLY)
6011 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6012 #else
6013 if (unlikely(!ctx->mem_idx)) {
6014 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6015 return;
6016 }
6017 switch (rB(ctx->opcode)) {
6018 case 0:
6019 case 1:
6020 case 2:
6021 {
6022 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6023 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6024 tcg_temp_free_i32(t0);
6025 }
6026 break;
6027 default:
6028 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6029 break;
6030 }
6031 #endif
6032 }
6033
6034 /* TLB management - PowerPC BookE 2.06 implementation */
6035
6036 /* tlbre */
6037 static void gen_tlbre_booke206(DisasContext *ctx)
6038 {
6039 #if defined(CONFIG_USER_ONLY)
6040 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6041 #else
6042 if (unlikely(!ctx->mem_idx)) {
6043 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6044 return;
6045 }
6046
6047 gen_helper_booke206_tlbre();
6048 #endif
6049 }
6050
6051 /* tlbsx - tlbsx. */
6052 static void gen_tlbsx_booke206(DisasContext *ctx)
6053 {
6054 #if defined(CONFIG_USER_ONLY)
6055 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6056 #else
6057 TCGv t0;
6058 if (unlikely(!ctx->mem_idx)) {
6059 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6060 return;
6061 }
6062
6063 if (rA(ctx->opcode)) {
6064 t0 = tcg_temp_new();
6065 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6066 } else {
6067 t0 = tcg_const_tl(0);
6068 }
6069
6070 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6071 gen_helper_booke206_tlbsx(t0);
6072 #endif
6073 }
6074
6075 /* tlbwe */
6076 static void gen_tlbwe_booke206(DisasContext *ctx)
6077 {
6078 #if defined(CONFIG_USER_ONLY)
6079 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6080 #else
6081 if (unlikely(!ctx->mem_idx)) {
6082 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6083 return;
6084 }
6085 gen_update_nip(ctx, ctx->nip - 4);
6086 gen_helper_booke206_tlbwe();
6087 #endif
6088 }
6089
6090 static void gen_tlbivax_booke206(DisasContext *ctx)
6091 {
6092 #if defined(CONFIG_USER_ONLY)
6093 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6094 #else
6095 TCGv t0;
6096 if (unlikely(!ctx->mem_idx)) {
6097 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6098 return;
6099 }
6100
6101 t0 = tcg_temp_new();
6102 gen_addr_reg_index(ctx, t0);
6103
6104 gen_helper_booke206_tlbivax(t0);
6105 #endif
6106 }
6107
6108 static void gen_tlbilx_booke206(DisasContext *ctx)
6109 {
6110 #if defined(CONFIG_USER_ONLY)
6111 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6112 #else
6113 TCGv t0;
6114 if (unlikely(!ctx->mem_idx)) {
6115 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6116 return;
6117 }
6118
6119 t0 = tcg_temp_new();
6120 gen_addr_reg_index(ctx, t0);
6121
6122 switch((ctx->opcode >> 21) & 0x3) {
6123 case 0:
6124 gen_helper_booke206_tlbilx0(t0);
6125 break;
6126 case 1:
6127 gen_helper_booke206_tlbilx1(t0);
6128 break;
6129 case 3:
6130 gen_helper_booke206_tlbilx3(t0);
6131 break;
6132 default:
6133 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6134 break;
6135 }
6136
6137 tcg_temp_free(t0);
6138 #endif
6139 }
6140
6141
6142 /* wrtee */
6143 static void gen_wrtee(DisasContext *ctx)
6144 {
6145 #if defined(CONFIG_USER_ONLY)
6146 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6147 #else
6148 TCGv t0;
6149 if (unlikely(!ctx->mem_idx)) {
6150 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6151 return;
6152 }
6153 t0 = tcg_temp_new();
6154 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6155 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6156 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6157 tcg_temp_free(t0);
6158 /* Stop translation to have a chance to raise an exception
6159 * if we just set msr_ee to 1
6160 */
6161 gen_stop_exception(ctx);
6162 #endif
6163 }
6164
6165 /* wrteei */
6166 static void gen_wrteei(DisasContext *ctx)
6167 {
6168 #if defined(CONFIG_USER_ONLY)
6169 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6170 #else
6171 if (unlikely(!ctx->mem_idx)) {
6172 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6173 return;
6174 }
6175 if (ctx->opcode & 0x00008000) {
6176 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6177 /* Stop translation to have a chance to raise an exception */
6178 gen_stop_exception(ctx);
6179 } else {
6180 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6181 }
6182 #endif
6183 }
6184
6185 /* PowerPC 440 specific instructions */
6186
6187 /* dlmzb */
6188 static void gen_dlmzb(DisasContext *ctx)
6189 {
6190 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6191 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6192 cpu_gpr[rB(ctx->opcode)], t0);
6193 tcg_temp_free_i32(t0);
6194 }
6195
6196 /* mbar replaces eieio on 440 */
6197 static void gen_mbar(DisasContext *ctx)
6198 {
6199 /* interpreted as no-op */
6200 }
6201
6202 /* msync replaces sync on 440 */
6203 static void gen_msync_4xx(DisasContext *ctx)
6204 {
6205 /* interpreted as no-op */
6206 }
6207
6208 /* icbt */
6209 static void gen_icbt_440(DisasContext *ctx)
6210 {
6211 /* interpreted as no-op */
6212 /* XXX: specification say this is treated as a load by the MMU
6213 * but does not generate any exception
6214 */
6215 }
6216
6217 /* Embedded.Processor Control */
6218
6219 static void gen_msgclr(DisasContext *ctx)
6220 {
6221 #if defined(CONFIG_USER_ONLY)
6222 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6223 #else
6224 if (unlikely(ctx->mem_idx == 0)) {
6225 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6226 return;
6227 }
6228
6229 gen_helper_msgclr(cpu_gpr[rB(ctx->opcode)]);
6230 #endif
6231 }
6232
6233 static void gen_msgsnd(DisasContext *ctx)
6234 {
6235 #if defined(CONFIG_USER_ONLY)
6236 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6237 #else
6238 if (unlikely(ctx->mem_idx == 0)) {
6239 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6240 return;
6241 }
6242
6243 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6244 #endif
6245 }
6246
6247 /*** Altivec vector extension ***/
6248 /* Altivec registers moves */
6249
6250 static inline TCGv_ptr gen_avr_ptr(int reg)
6251 {
6252 TCGv_ptr r = tcg_temp_new_ptr();
6253 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6254 return r;
6255 }
6256
6257 #define GEN_VR_LDX(name, opc2, opc3) \
6258 static void glue(gen_, name)(DisasContext *ctx) \
6259 { \
6260 TCGv EA; \
6261 if (unlikely(!ctx->altivec_enabled)) { \
6262 gen_exception(ctx, POWERPC_EXCP_VPU); \
6263 return; \
6264 } \
6265 gen_set_access_type(ctx, ACCESS_INT); \
6266 EA = tcg_temp_new(); \
6267 gen_addr_reg_index(ctx, EA); \
6268 tcg_gen_andi_tl(EA, EA, ~0xf); \
6269 if (ctx->le_mode) { \
6270 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6271 tcg_gen_addi_tl(EA, EA, 8); \
6272 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6273 } else { \
6274 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6275 tcg_gen_addi_tl(EA, EA, 8); \
6276 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6277 } \
6278 tcg_temp_free(EA); \
6279 }
6280
6281 #define GEN_VR_STX(name, opc2, opc3) \
6282 static void gen_st##name(DisasContext *ctx) \
6283 { \
6284 TCGv EA; \
6285 if (unlikely(!ctx->altivec_enabled)) { \
6286 gen_exception(ctx, POWERPC_EXCP_VPU); \
6287 return; \
6288 } \
6289 gen_set_access_type(ctx, ACCESS_INT); \
6290 EA = tcg_temp_new(); \
6291 gen_addr_reg_index(ctx, EA); \
6292 tcg_gen_andi_tl(EA, EA, ~0xf); \
6293 if (ctx->le_mode) { \
6294 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6295 tcg_gen_addi_tl(EA, EA, 8); \
6296 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6297 } else { \
6298 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6299 tcg_gen_addi_tl(EA, EA, 8); \
6300 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6301 } \
6302 tcg_temp_free(EA); \
6303 }
6304
6305 #define GEN_VR_LVE(name, opc2, opc3) \
6306 static void gen_lve##name(DisasContext *ctx) \
6307 { \
6308 TCGv EA; \
6309 TCGv_ptr rs; \
6310 if (unlikely(!ctx->altivec_enabled)) { \
6311 gen_exception(ctx, POWERPC_EXCP_VPU); \
6312 return; \
6313 } \
6314 gen_set_access_type(ctx, ACCESS_INT); \
6315 EA = tcg_temp_new(); \
6316 gen_addr_reg_index(ctx, EA); \
6317 rs = gen_avr_ptr(rS(ctx->opcode)); \
6318 gen_helper_lve##name (rs, EA); \
6319 tcg_temp_free(EA); \
6320 tcg_temp_free_ptr(rs); \
6321 }
6322
6323 #define GEN_VR_STVE(name, opc2, opc3) \
6324 static void gen_stve##name(DisasContext *ctx) \
6325 { \
6326 TCGv EA; \
6327 TCGv_ptr rs; \
6328 if (unlikely(!ctx->altivec_enabled)) { \
6329 gen_exception(ctx, POWERPC_EXCP_VPU); \
6330 return; \
6331 } \
6332 gen_set_access_type(ctx, ACCESS_INT); \
6333 EA = tcg_temp_new(); \
6334 gen_addr_reg_index(ctx, EA); \
6335 rs = gen_avr_ptr(rS(ctx->opcode)); \
6336 gen_helper_stve##name (rs, EA); \
6337 tcg_temp_free(EA); \
6338 tcg_temp_free_ptr(rs); \
6339 }
6340
6341 GEN_VR_LDX(lvx, 0x07, 0x03);
6342 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6343 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6344
6345 GEN_VR_LVE(bx, 0x07, 0x00);
6346 GEN_VR_LVE(hx, 0x07, 0x01);
6347 GEN_VR_LVE(wx, 0x07, 0x02);
6348
6349 GEN_VR_STX(svx, 0x07, 0x07);
6350 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6351 GEN_VR_STX(svxl, 0x07, 0x0F);
6352
6353 GEN_VR_STVE(bx, 0x07, 0x04);
6354 GEN_VR_STVE(hx, 0x07, 0x05);
6355 GEN_VR_STVE(wx, 0x07, 0x06);
6356
6357 static void gen_lvsl(DisasContext *ctx)
6358 {
6359 TCGv_ptr rd;
6360 TCGv EA;
6361 if (unlikely(!ctx->altivec_enabled)) {
6362 gen_exception(ctx, POWERPC_EXCP_VPU);
6363 return;
6364 }
6365 EA = tcg_temp_new();
6366 gen_addr_reg_index(ctx, EA);
6367 rd = gen_avr_ptr(rD(ctx->opcode));
6368 gen_helper_lvsl(rd, EA);
6369 tcg_temp_free(EA);
6370 tcg_temp_free_ptr(rd);
6371 }
6372
6373 static void gen_lvsr(DisasContext *ctx)
6374 {
6375 TCGv_ptr rd;
6376 TCGv EA;
6377 if (unlikely(!ctx->altivec_enabled)) {
6378 gen_exception(ctx, POWERPC_EXCP_VPU);
6379 return;
6380 }
6381 EA = tcg_temp_new();
6382 gen_addr_reg_index(ctx, EA);
6383 rd = gen_avr_ptr(rD(ctx->opcode));
6384 gen_helper_lvsr(rd, EA);
6385 tcg_temp_free(EA);
6386 tcg_temp_free_ptr(rd);
6387 }
6388
6389 static void gen_mfvscr(DisasContext *ctx)
6390 {
6391 TCGv_i32 t;
6392 if (unlikely(!ctx->altivec_enabled)) {
6393 gen_exception(ctx, POWERPC_EXCP_VPU);
6394 return;
6395 }
6396 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6397 t = tcg_temp_new_i32();
6398 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6399 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6400 tcg_temp_free_i32(t);
6401 }
6402
6403 static void gen_mtvscr(DisasContext *ctx)
6404 {
6405 TCGv_ptr p;
6406 if (unlikely(!ctx->altivec_enabled)) {
6407 gen_exception(ctx, POWERPC_EXCP_VPU);
6408 return;
6409 }
6410 p = gen_avr_ptr(rD(ctx->opcode));
6411 gen_helper_mtvscr(p);
6412 tcg_temp_free_ptr(p);
6413 }
6414
6415 /* Logical operations */
6416 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6417 static void glue(gen_, name)(DisasContext *ctx) \
6418 { \
6419 if (unlikely(!ctx->altivec_enabled)) { \
6420 gen_exception(ctx, POWERPC_EXCP_VPU); \
6421 return; \
6422 } \
6423 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6424 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6425 }
6426
6427 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6428 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6429 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6430 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6431 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6432
6433 #define GEN_VXFORM(name, opc2, opc3) \
6434 static void glue(gen_, name)(DisasContext *ctx) \
6435 { \
6436 TCGv_ptr ra, rb, rd; \
6437 if (unlikely(!ctx->altivec_enabled)) { \
6438 gen_exception(ctx, POWERPC_EXCP_VPU); \
6439 return; \
6440 } \
6441 ra = gen_avr_ptr(rA(ctx->opcode)); \
6442 rb = gen_avr_ptr(rB(ctx->opcode)); \
6443 rd = gen_avr_ptr(rD(ctx->opcode)); \
6444 gen_helper_##name (rd, ra, rb); \
6445 tcg_temp_free_ptr(ra); \
6446 tcg_temp_free_ptr(rb); \
6447 tcg_temp_free_ptr(rd); \
6448 }
6449
6450 GEN_VXFORM(vaddubm, 0, 0);
6451 GEN_VXFORM(vadduhm, 0, 1);
6452 GEN_VXFORM(vadduwm, 0, 2);
6453 GEN_VXFORM(vsububm, 0, 16);
6454 GEN_VXFORM(vsubuhm, 0, 17);
6455 GEN_VXFORM(vsubuwm, 0, 18);
6456 GEN_VXFORM(vmaxub, 1, 0);
6457 GEN_VXFORM(vmaxuh, 1, 1);
6458 GEN_VXFORM(vmaxuw, 1, 2);
6459 GEN_VXFORM(vmaxsb, 1, 4);
6460 GEN_VXFORM(vmaxsh, 1, 5);
6461 GEN_VXFORM(vmaxsw, 1, 6);
6462 GEN_VXFORM(vminub, 1, 8);
6463 GEN_VXFORM(vminuh, 1, 9);
6464 GEN_VXFORM(vminuw, 1, 10);
6465 GEN_VXFORM(vminsb, 1, 12);
6466 GEN_VXFORM(vminsh, 1, 13);
6467 GEN_VXFORM(vminsw, 1, 14);
6468 GEN_VXFORM(vavgub, 1, 16);
6469 GEN_VXFORM(vavguh, 1, 17);
6470 GEN_VXFORM(vavguw, 1, 18);
6471 GEN_VXFORM(vavgsb, 1, 20);
6472 GEN_VXFORM(vavgsh, 1, 21);
6473 GEN_VXFORM(vavgsw, 1, 22);
6474 GEN_VXFORM(vmrghb, 6, 0);
6475 GEN_VXFORM(vmrghh, 6, 1);
6476 GEN_VXFORM(vmrghw, 6, 2);
6477 GEN_VXFORM(vmrglb, 6, 4);
6478 GEN_VXFORM(vmrglh, 6, 5);
6479 GEN_VXFORM(vmrglw, 6, 6);
6480 GEN_VXFORM(vmuloub, 4, 0);
6481 GEN_VXFORM(vmulouh, 4, 1);
6482 GEN_VXFORM(vmulosb, 4, 4);
6483 GEN_VXFORM(vmulosh, 4, 5);
6484 GEN_VXFORM(vmuleub, 4, 8);
6485 GEN_VXFORM(vmuleuh, 4, 9);
6486 GEN_VXFORM(vmulesb, 4, 12);
6487 GEN_VXFORM(vmulesh, 4, 13);
6488 GEN_VXFORM(vslb, 2, 4);
6489 GEN_VXFORM(vslh, 2, 5);
6490 GEN_VXFORM(vslw, 2, 6);
6491 GEN_VXFORM(vsrb, 2, 8);
6492 GEN_VXFORM(vsrh, 2, 9);
6493 GEN_VXFORM(vsrw, 2, 10);
6494 GEN_VXFORM(vsrab, 2, 12);
6495 GEN_VXFORM(vsrah, 2, 13);
6496 GEN_VXFORM(vsraw, 2, 14);
6497 GEN_VXFORM(vslo, 6, 16);
6498 GEN_VXFORM(vsro, 6, 17);
6499 GEN_VXFORM(vaddcuw, 0, 6);
6500 GEN_VXFORM(vsubcuw, 0, 22);
6501 GEN_VXFORM(vaddubs, 0, 8);
6502 GEN_VXFORM(vadduhs, 0, 9);
6503 GEN_VXFORM(vadduws, 0, 10);
6504 GEN_VXFORM(vaddsbs, 0, 12);
6505 GEN_VXFORM(vaddshs, 0, 13);
6506 GEN_VXFORM(vaddsws, 0, 14);
6507 GEN_VXFORM(vsububs, 0, 24);
6508 GEN_VXFORM(vsubuhs, 0, 25);
6509 GEN_VXFORM(vsubuws, 0, 26);
6510 GEN_VXFORM(vsubsbs, 0, 28);
6511 GEN_VXFORM(vsubshs, 0, 29);
6512 GEN_VXFORM(vsubsws, 0, 30);
6513 GEN_VXFORM(vrlb, 2, 0);
6514 GEN_VXFORM(vrlh, 2, 1);
6515 GEN_VXFORM(vrlw, 2, 2);
6516 GEN_VXFORM(vsl, 2, 7);
6517 GEN_VXFORM(vsr, 2, 11);
6518 GEN_VXFORM(vpkuhum, 7, 0);
6519 GEN_VXFORM(vpkuwum, 7, 1);
6520 GEN_VXFORM(vpkuhus, 7, 2);
6521 GEN_VXFORM(vpkuwus, 7, 3);
6522 GEN_VXFORM(vpkshus, 7, 4);
6523 GEN_VXFORM(vpkswus, 7, 5);
6524 GEN_VXFORM(vpkshss, 7, 6);
6525 GEN_VXFORM(vpkswss, 7, 7);
6526 GEN_VXFORM(vpkpx, 7, 12);
6527 GEN_VXFORM(vsum4ubs, 4, 24);
6528 GEN_VXFORM(vsum4sbs, 4, 28);
6529 GEN_VXFORM(vsum4shs, 4, 25);
6530 GEN_VXFORM(vsum2sws, 4, 26);
6531 GEN_VXFORM(vsumsws, 4, 30);
6532 GEN_VXFORM(vaddfp, 5, 0);
6533 GEN_VXFORM(vsubfp, 5, 1);
6534 GEN_VXFORM(vmaxfp, 5, 16);
6535 GEN_VXFORM(vminfp, 5, 17);
6536
6537 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6538 static void glue(gen_, name)(DisasContext *ctx) \
6539 { \
6540 TCGv_ptr ra, rb, rd; \
6541 if (unlikely(!ctx->altivec_enabled)) { \
6542 gen_exception(ctx, POWERPC_EXCP_VPU); \
6543 return; \
6544 } \
6545 ra = gen_avr_ptr(rA(ctx->opcode)); \
6546 rb = gen_avr_ptr(rB(ctx->opcode)); \
6547 rd = gen_avr_ptr(rD(ctx->opcode)); \
6548 gen_helper_##opname (rd, ra, rb); \
6549 tcg_temp_free_ptr(ra); \
6550 tcg_temp_free_ptr(rb); \
6551 tcg_temp_free_ptr(rd); \
6552 }
6553
6554 #define GEN_VXRFORM(name, opc2, opc3) \
6555 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6556 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6557
6558 GEN_VXRFORM(vcmpequb, 3, 0)
6559 GEN_VXRFORM(vcmpequh, 3, 1)
6560 GEN_VXRFORM(vcmpequw, 3, 2)
6561 GEN_VXRFORM(vcmpgtsb, 3, 12)
6562 GEN_VXRFORM(vcmpgtsh, 3, 13)
6563 GEN_VXRFORM(vcmpgtsw, 3, 14)
6564 GEN_VXRFORM(vcmpgtub, 3, 8)
6565 GEN_VXRFORM(vcmpgtuh, 3, 9)
6566 GEN_VXRFORM(vcmpgtuw, 3, 10)
6567 GEN_VXRFORM(vcmpeqfp, 3, 3)
6568 GEN_VXRFORM(vcmpgefp, 3, 7)
6569 GEN_VXRFORM(vcmpgtfp, 3, 11)
6570 GEN_VXRFORM(vcmpbfp, 3, 15)
6571
6572 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6573 static void glue(gen_, name)(DisasContext *ctx) \
6574 { \
6575 TCGv_ptr rd; \
6576 TCGv_i32 simm; \
6577 if (unlikely(!ctx->altivec_enabled)) { \
6578 gen_exception(ctx, POWERPC_EXCP_VPU); \
6579 return; \
6580 } \
6581 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6582 rd = gen_avr_ptr(rD(ctx->opcode)); \
6583 gen_helper_##name (rd, simm); \
6584 tcg_temp_free_i32(simm); \
6585 tcg_temp_free_ptr(rd); \
6586 }
6587
6588 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6589 GEN_VXFORM_SIMM(vspltish, 6, 13);
6590 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6591
6592 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6593 static void glue(gen_, name)(DisasContext *ctx) \
6594 { \
6595 TCGv_ptr rb, rd; \
6596 if (unlikely(!ctx->altivec_enabled)) { \
6597 gen_exception(ctx, POWERPC_EXCP_VPU); \
6598 return; \
6599 } \
6600 rb = gen_avr_ptr(rB(ctx->opcode)); \
6601 rd = gen_avr_ptr(rD(ctx->opcode)); \
6602 gen_helper_##name (rd, rb); \
6603 tcg_temp_free_ptr(rb); \
6604 tcg_temp_free_ptr(rd); \
6605 }
6606
6607 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6608 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6609 GEN_VXFORM_NOA(vupklsb, 7, 10);
6610 GEN_VXFORM_NOA(vupklsh, 7, 11);
6611 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6612 GEN_VXFORM_NOA(vupklpx, 7, 15);
6613 GEN_VXFORM_NOA(vrefp, 5, 4);
6614 GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
6615 GEN_VXFORM_NOA(vexptefp, 5, 6);
6616 GEN_VXFORM_NOA(vlogefp, 5, 7);
6617 GEN_VXFORM_NOA(vrfim, 5, 8);
6618 GEN_VXFORM_NOA(vrfin, 5, 9);
6619 GEN_VXFORM_NOA(vrfip, 5, 10);
6620 GEN_VXFORM_NOA(vrfiz, 5, 11);
6621
6622 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6623 static void glue(gen_, name)(DisasContext *ctx) \
6624 { \
6625 TCGv_ptr rd; \
6626 TCGv_i32 simm; \
6627 if (unlikely(!ctx->altivec_enabled)) { \
6628 gen_exception(ctx, POWERPC_EXCP_VPU); \
6629 return; \
6630 } \
6631 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6632 rd = gen_avr_ptr(rD(ctx->opcode)); \
6633 gen_helper_##name (rd, simm); \
6634 tcg_temp_free_i32(simm); \
6635 tcg_temp_free_ptr(rd); \
6636 }
6637
6638 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6639 static void glue(gen_, name)(DisasContext *ctx) \
6640 { \
6641 TCGv_ptr rb, rd; \
6642 TCGv_i32 uimm; \
6643 if (unlikely(!ctx->altivec_enabled)) { \
6644 gen_exception(ctx, POWERPC_EXCP_VPU); \
6645 return; \
6646 } \
6647 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6648 rb = gen_avr_ptr(rB(ctx->opcode)); \
6649 rd = gen_avr_ptr(rD(ctx->opcode)); \
6650 gen_helper_##name (rd, rb, uimm); \
6651 tcg_temp_free_i32(uimm); \
6652 tcg_temp_free_ptr(rb); \
6653 tcg_temp_free_ptr(rd); \
6654 }
6655
6656 GEN_VXFORM_UIMM(vspltb, 6, 8);
6657 GEN_VXFORM_UIMM(vsplth, 6, 9);
6658 GEN_VXFORM_UIMM(vspltw, 6, 10);
6659 GEN_VXFORM_UIMM(vcfux, 5, 12);
6660 GEN_VXFORM_UIMM(vcfsx, 5, 13);
6661 GEN_VXFORM_UIMM(vctuxs, 5, 14);
6662 GEN_VXFORM_UIMM(vctsxs, 5, 15);
6663
6664 static void gen_vsldoi(DisasContext *ctx)
6665 {
6666 TCGv_ptr ra, rb, rd;
6667 TCGv_i32 sh;
6668 if (unlikely(!ctx->altivec_enabled)) {
6669 gen_exception(ctx, POWERPC_EXCP_VPU);
6670 return;
6671 }
6672 ra = gen_avr_ptr(rA(ctx->opcode));
6673 rb = gen_avr_ptr(rB(ctx->opcode));
6674 rd = gen_avr_ptr(rD(ctx->opcode));
6675 sh = tcg_const_i32(VSH(ctx->opcode));
6676 gen_helper_vsldoi (rd, ra, rb, sh);
6677 tcg_temp_free_ptr(ra);
6678 tcg_temp_free_ptr(rb);
6679 tcg_temp_free_ptr(rd);
6680 tcg_temp_free_i32(sh);
6681 }
6682
6683 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6684 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6685 { \
6686 TCGv_ptr ra, rb, rc, rd; \
6687 if (unlikely(!ctx->altivec_enabled)) { \
6688 gen_exception(ctx, POWERPC_EXCP_VPU); \
6689 return; \
6690 } \
6691 ra = gen_avr_ptr(rA(ctx->opcode)); \
6692 rb = gen_avr_ptr(rB(ctx->opcode)); \
6693 rc = gen_avr_ptr(rC(ctx->opcode)); \
6694 rd = gen_avr_ptr(rD(ctx->opcode)); \
6695 if (Rc(ctx->opcode)) { \
6696 gen_helper_##name1 (rd, ra, rb, rc); \
6697 } else { \
6698 gen_helper_##name0 (rd, ra, rb, rc); \
6699 } \
6700 tcg_temp_free_ptr(ra); \
6701 tcg_temp_free_ptr(rb); \
6702 tcg_temp_free_ptr(rc); \
6703 tcg_temp_free_ptr(rd); \
6704 }
6705
6706 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6707
6708 static void gen_vmladduhm(DisasContext *ctx)
6709 {
6710 TCGv_ptr ra, rb, rc, rd;
6711 if (unlikely(!ctx->altivec_enabled)) {
6712 gen_exception(ctx, POWERPC_EXCP_VPU);
6713 return;
6714 }
6715 ra = gen_avr_ptr(rA(ctx->opcode));
6716 rb = gen_avr_ptr(rB(ctx->opcode));
6717 rc = gen_avr_ptr(rC(ctx->opcode));
6718 rd = gen_avr_ptr(rD(ctx->opcode));
6719 gen_helper_vmladduhm(rd, ra, rb, rc);
6720 tcg_temp_free_ptr(ra);
6721 tcg_temp_free_ptr(rb);
6722 tcg_temp_free_ptr(rc);
6723 tcg_temp_free_ptr(rd);
6724 }
6725
6726 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6727 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6728 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6729 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6730 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6731
6732 /*** SPE extension ***/
6733 /* Register moves */
6734
6735
6736 static inline void gen_evmra(DisasContext *ctx)
6737 {
6738
6739 if (unlikely(!ctx->spe_enabled)) {
6740 gen_exception(ctx, POWERPC_EXCP_SPEU);
6741 return;
6742 }
6743
6744 #if defined(TARGET_PPC64)
6745 /* rD := rA */
6746 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6747
6748 /* spe_acc := rA */
6749 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6750 cpu_env,
6751 offsetof(CPUPPCState, spe_acc));
6752 #else
6753 TCGv_i64 tmp = tcg_temp_new_i64();
6754
6755 /* tmp := rA_lo + rA_hi << 32 */
6756 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6757
6758 /* spe_acc := tmp */
6759 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6760 tcg_temp_free_i64(tmp);
6761
6762 /* rD := rA */
6763 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6764 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6765 #endif
6766 }
6767
6768 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6769 {
6770 #if defined(TARGET_PPC64)
6771 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6772 #else
6773 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6774 #endif
6775 }
6776
6777 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6778 {
6779 #if defined(TARGET_PPC64)
6780 tcg_gen_mov_i64(cpu_gpr[reg], t);
6781 #else
6782 TCGv_i64 tmp = tcg_temp_new_i64();
6783 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6784 tcg_gen_shri_i64(tmp, t, 32);
6785 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6786 tcg_temp_free_i64(tmp);
6787 #endif
6788 }
6789
6790 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6791 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6792 { \
6793 if (Rc(ctx->opcode)) \
6794 gen_##name1(ctx); \
6795 else \
6796 gen_##name0(ctx); \
6797 }
6798
6799 /* Handler for undefined SPE opcodes */
6800 static inline void gen_speundef(DisasContext *ctx)
6801 {
6802 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6803 }
6804
6805 /* SPE logic */
6806 #if defined(TARGET_PPC64)
6807 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6808 static inline void gen_##name(DisasContext *ctx) \
6809 { \
6810 if (unlikely(!ctx->spe_enabled)) { \
6811 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6812 return; \
6813 } \
6814 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6815 cpu_gpr[rB(ctx->opcode)]); \
6816 }
6817 #else
6818 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6819 static inline void gen_##name(DisasContext *ctx) \
6820 { \
6821 if (unlikely(!ctx->spe_enabled)) { \
6822 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6823 return; \
6824 } \
6825 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6826 cpu_gpr[rB(ctx->opcode)]); \
6827 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6828 cpu_gprh[rB(ctx->opcode)]); \
6829 }
6830 #endif
6831
6832 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6833 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6834 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6835 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6836 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6837 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6838 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6839 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6840
6841 /* SPE logic immediate */
6842 #if defined(TARGET_PPC64)
6843 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6844 static inline void gen_##name(DisasContext *ctx) \
6845 { \
6846 if (unlikely(!ctx->spe_enabled)) { \
6847 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6848 return; \
6849 } \
6850 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6851 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6852 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6853 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6854 tcg_opi(t0, t0, rB(ctx->opcode)); \
6855 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6856 tcg_gen_trunc_i64_i32(t1, t2); \
6857 tcg_temp_free_i64(t2); \
6858 tcg_opi(t1, t1, rB(ctx->opcode)); \
6859 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6860 tcg_temp_free_i32(t0); \
6861 tcg_temp_free_i32(t1); \
6862 }
6863 #else
6864 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6865 static inline void gen_##name(DisasContext *ctx) \
6866 { \
6867 if (unlikely(!ctx->spe_enabled)) { \
6868 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6869 return; \
6870 } \
6871 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6872 rB(ctx->opcode)); \
6873 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6874 rB(ctx->opcode)); \
6875 }
6876 #endif
6877 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6878 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6879 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6880 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6881
6882 /* SPE arithmetic */
6883 #if defined(TARGET_PPC64)
6884 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6885 static inline void gen_##name(DisasContext *ctx) \
6886 { \
6887 if (unlikely(!ctx->spe_enabled)) { \
6888 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6889 return; \
6890 } \
6891 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6892 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6893 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6894 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6895 tcg_op(t0, t0); \
6896 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6897 tcg_gen_trunc_i64_i32(t1, t2); \
6898 tcg_temp_free_i64(t2); \
6899 tcg_op(t1, t1); \
6900 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6901 tcg_temp_free_i32(t0); \
6902 tcg_temp_free_i32(t1); \
6903 }
6904 #else
6905 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6906 static inline void gen_##name(DisasContext *ctx) \
6907 { \
6908 if (unlikely(!ctx->spe_enabled)) { \
6909 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6910 return; \
6911 } \
6912 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6913 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6914 }
6915 #endif
6916
6917 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
6918 {
6919 int l1 = gen_new_label();
6920 int l2 = gen_new_label();
6921
6922 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6923 tcg_gen_neg_i32(ret, arg1);
6924 tcg_gen_br(l2);
6925 gen_set_label(l1);
6926 tcg_gen_mov_i32(ret, arg1);
6927 gen_set_label(l2);
6928 }
6929 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6930 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6931 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6932 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6933 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
6934 {
6935 tcg_gen_addi_i32(ret, arg1, 0x8000);
6936 tcg_gen_ext16u_i32(ret, ret);
6937 }
6938 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6939 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6940 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6941
6942 #if defined(TARGET_PPC64)
6943 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6944 static inline void gen_##name(DisasContext *ctx) \
6945 { \
6946 if (unlikely(!ctx->spe_enabled)) { \
6947 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6948 return; \
6949 } \
6950 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6951 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6952 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6953 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6954 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6955 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6956 tcg_op(t0, t0, t2); \
6957 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6958 tcg_gen_trunc_i64_i32(t1, t3); \
6959 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6960 tcg_gen_trunc_i64_i32(t2, t3); \
6961 tcg_temp_free_i64(t3); \
6962 tcg_op(t1, t1, t2); \
6963 tcg_temp_free_i32(t2); \
6964 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6965 tcg_temp_free_i32(t0); \
6966 tcg_temp_free_i32(t1); \
6967 }
6968 #else
6969 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6970 static inline void gen_##name(DisasContext *ctx) \
6971 { \
6972 if (unlikely(!ctx->spe_enabled)) { \
6973 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6974 return; \
6975 } \
6976 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6977 cpu_gpr[rB(ctx->opcode)]); \
6978 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6979 cpu_gprh[rB(ctx->opcode)]); \
6980 }
6981 #endif
6982
6983 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6984 {
6985 TCGv_i32 t0;
6986 int l1, l2;
6987
6988 l1 = gen_new_label();
6989 l2 = gen_new_label();
6990 t0 = tcg_temp_local_new_i32();
6991 /* No error here: 6 bits are used */
6992 tcg_gen_andi_i32(t0, arg2, 0x3F);
6993 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6994 tcg_gen_shr_i32(ret, arg1, t0);
6995 tcg_gen_br(l2);
6996 gen_set_label(l1);
6997 tcg_gen_movi_i32(ret, 0);
6998 gen_set_label(l2);
6999 tcg_temp_free_i32(t0);
7000 }
7001 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7002 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7003 {
7004 TCGv_i32 t0;
7005 int l1, l2;
7006
7007 l1 = gen_new_label();
7008 l2 = gen_new_label();
7009 t0 = tcg_temp_local_new_i32();
7010 /* No error here: 6 bits are used */
7011 tcg_gen_andi_i32(t0, arg2, 0x3F);
7012 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7013 tcg_gen_sar_i32(ret, arg1, t0);
7014 tcg_gen_br(l2);
7015 gen_set_label(l1);
7016 tcg_gen_movi_i32(ret, 0);
7017 gen_set_label(l2);
7018 tcg_temp_free_i32(t0);
7019 }
7020 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7021 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7022 {
7023 TCGv_i32 t0;
7024 int l1, l2;
7025
7026 l1 = gen_new_label();
7027 l2 = gen_new_label();
7028 t0 = tcg_temp_local_new_i32();
7029 /* No error here: 6 bits are used */
7030 tcg_gen_andi_i32(t0, arg2, 0x3F);
7031 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7032 tcg_gen_shl_i32(ret, arg1, t0);
7033 tcg_gen_br(l2);
7034 gen_set_label(l1);
7035 tcg_gen_movi_i32(ret, 0);
7036 gen_set_label(l2);
7037 tcg_temp_free_i32(t0);
7038 }
7039 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7040 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7041 {
7042 TCGv_i32 t0 = tcg_temp_new_i32();
7043 tcg_gen_andi_i32(t0, arg2, 0x1F);
7044 tcg_gen_rotl_i32(ret, arg1, t0);
7045 tcg_temp_free_i32(t0);
7046 }
7047 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7048 static inline void gen_evmergehi(DisasContext *ctx)
7049 {
7050 if (unlikely(!ctx->spe_enabled)) {
7051 gen_exception(ctx, POWERPC_EXCP_SPEU);
7052 return;
7053 }
7054 #if defined(TARGET_PPC64)
7055 TCGv t0 = tcg_temp_new();
7056 TCGv t1 = tcg_temp_new();
7057 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7058 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7059 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7060 tcg_temp_free(t0);
7061 tcg_temp_free(t1);
7062 #else
7063 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7064 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7065 #endif
7066 }
7067 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7068 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7069 {
7070 tcg_gen_sub_i32(ret, arg2, arg1);
7071 }
7072 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7073
7074 /* SPE arithmetic immediate */
7075 #if defined(TARGET_PPC64)
7076 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7077 static inline void gen_##name(DisasContext *ctx) \
7078 { \
7079 if (unlikely(!ctx->spe_enabled)) { \
7080 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7081 return; \
7082 } \
7083 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7084 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7085 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7086 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7087 tcg_op(t0, t0, rA(ctx->opcode)); \
7088 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7089 tcg_gen_trunc_i64_i32(t1, t2); \
7090 tcg_temp_free_i64(t2); \
7091 tcg_op(t1, t1, rA(ctx->opcode)); \
7092 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7093 tcg_temp_free_i32(t0); \
7094 tcg_temp_free_i32(t1); \
7095 }
7096 #else
7097 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7098 static inline void gen_##name(DisasContext *ctx) \
7099 { \
7100 if (unlikely(!ctx->spe_enabled)) { \
7101 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7102 return; \
7103 } \
7104 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7105 rA(ctx->opcode)); \
7106 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7107 rA(ctx->opcode)); \
7108 }
7109 #endif
7110 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7111 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7112
7113 /* SPE comparison */
7114 #if defined(TARGET_PPC64)
7115 #define GEN_SPEOP_COMP(name, tcg_cond) \
7116 static inline void gen_##name(DisasContext *ctx) \
7117 { \
7118 if (unlikely(!ctx->spe_enabled)) { \
7119 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7120 return; \
7121 } \
7122 int l1 = gen_new_label(); \
7123 int l2 = gen_new_label(); \
7124 int l3 = gen_new_label(); \
7125 int l4 = gen_new_label(); \
7126 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7127 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7128 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7129 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7130 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7131 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7132 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7133 tcg_gen_br(l2); \
7134 gen_set_label(l1); \
7135 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7136 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7137 gen_set_label(l2); \
7138 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7139 tcg_gen_trunc_i64_i32(t0, t2); \
7140 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7141 tcg_gen_trunc_i64_i32(t1, t2); \
7142 tcg_temp_free_i64(t2); \
7143 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7144 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7145 ~(CRF_CH | CRF_CH_AND_CL)); \
7146 tcg_gen_br(l4); \
7147 gen_set_label(l3); \
7148 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7149 CRF_CH | CRF_CH_OR_CL); \
7150 gen_set_label(l4); \
7151 tcg_temp_free_i32(t0); \
7152 tcg_temp_free_i32(t1); \
7153 }
7154 #else
7155 #define GEN_SPEOP_COMP(name, tcg_cond) \
7156 static inline void gen_##name(DisasContext *ctx) \
7157 { \
7158 if (unlikely(!ctx->spe_enabled)) { \
7159 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7160 return; \
7161 } \
7162 int l1 = gen_new_label(); \
7163 int l2 = gen_new_label(); \
7164 int l3 = gen_new_label(); \
7165 int l4 = gen_new_label(); \
7166 \
7167 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7168 cpu_gpr[rB(ctx->opcode)], l1); \
7169 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7170 tcg_gen_br(l2); \
7171 gen_set_label(l1); \
7172 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7173 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7174 gen_set_label(l2); \
7175 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7176 cpu_gprh[rB(ctx->opcode)], l3); \
7177 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7178 ~(CRF_CH | CRF_CH_AND_CL)); \
7179 tcg_gen_br(l4); \
7180 gen_set_label(l3); \
7181 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7182 CRF_CH | CRF_CH_OR_CL); \
7183 gen_set_label(l4); \
7184 }
7185 #endif
7186 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7187 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7188 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7189 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7190 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7191
7192 /* SPE misc */
7193 static inline void gen_brinc(DisasContext *ctx)
7194 {
7195 /* Note: brinc is usable even if SPE is disabled */
7196 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7197 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7198 }
7199 static inline void gen_evmergelo(DisasContext *ctx)
7200 {
7201 if (unlikely(!ctx->spe_enabled)) {
7202 gen_exception(ctx, POWERPC_EXCP_SPEU);
7203 return;
7204 }
7205 #if defined(TARGET_PPC64)
7206 TCGv t0 = tcg_temp_new();
7207 TCGv t1 = tcg_temp_new();
7208 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7209 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7210 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7211 tcg_temp_free(t0);
7212 tcg_temp_free(t1);
7213 #else
7214 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7215 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7216 #endif
7217 }
7218 static inline void gen_evmergehilo(DisasContext *ctx)
7219 {
7220 if (unlikely(!ctx->spe_enabled)) {
7221 gen_exception(ctx, POWERPC_EXCP_SPEU);
7222 return;
7223 }
7224 #if defined(TARGET_PPC64)
7225 TCGv t0 = tcg_temp_new();
7226 TCGv t1 = tcg_temp_new();
7227 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7228 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7229 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7230 tcg_temp_free(t0);
7231 tcg_temp_free(t1);
7232 #else
7233 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7234 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7235 #endif
7236 }
7237 static inline void gen_evmergelohi(DisasContext *ctx)
7238 {
7239 if (unlikely(!ctx->spe_enabled)) {
7240 gen_exception(ctx, POWERPC_EXCP_SPEU);
7241 return;
7242 }
7243 #if defined(TARGET_PPC64)
7244 TCGv t0 = tcg_temp_new();
7245 TCGv t1 = tcg_temp_new();
7246 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7247 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7248 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7249 tcg_temp_free(t0);
7250 tcg_temp_free(t1);
7251 #else
7252 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7253 TCGv_i32 tmp = tcg_temp_new_i32();
7254 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7255 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7256 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7257 tcg_temp_free_i32(tmp);
7258 } else {
7259 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7260 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7261 }
7262 #endif
7263 }
7264 static inline void gen_evsplati(DisasContext *ctx)
7265 {
7266 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7267
7268 #if defined(TARGET_PPC64)
7269 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7270 #else
7271 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7272 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7273 #endif
7274 }
7275 static inline void gen_evsplatfi(DisasContext *ctx)
7276 {
7277 uint64_t imm = rA(ctx->opcode) << 27;
7278
7279 #if defined(TARGET_PPC64)
7280 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7281 #else
7282 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7283 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7284 #endif
7285 }
7286
7287 static inline void gen_evsel(DisasContext *ctx)
7288 {
7289 int l1 = gen_new_label();
7290 int l2 = gen_new_label();
7291 int l3 = gen_new_label();
7292 int l4 = gen_new_label();
7293 TCGv_i32 t0 = tcg_temp_local_new_i32();
7294 #if defined(TARGET_PPC64)
7295 TCGv t1 = tcg_temp_local_new();
7296 TCGv t2 = tcg_temp_local_new();
7297 #endif
7298 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7299 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7300 #if defined(TARGET_PPC64)
7301 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7302 #else
7303 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7304 #endif
7305 tcg_gen_br(l2);
7306 gen_set_label(l1);
7307 #if defined(TARGET_PPC64)
7308 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7309 #else
7310 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7311 #endif
7312 gen_set_label(l2);
7313 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7314 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7315 #if defined(TARGET_PPC64)
7316 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7317 #else
7318 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7319 #endif
7320 tcg_gen_br(l4);
7321 gen_set_label(l3);
7322 #if defined(TARGET_PPC64)
7323 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7324 #else
7325 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7326 #endif
7327 gen_set_label(l4);
7328 tcg_temp_free_i32(t0);
7329 #if defined(TARGET_PPC64)
7330 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7331 tcg_temp_free(t1);
7332 tcg_temp_free(t2);
7333 #endif
7334 }
7335
7336 static void gen_evsel0(DisasContext *ctx)
7337 {
7338 gen_evsel(ctx);
7339 }
7340
7341 static void gen_evsel1(DisasContext *ctx)
7342 {
7343 gen_evsel(ctx);
7344 }
7345
7346 static void gen_evsel2(DisasContext *ctx)
7347 {
7348 gen_evsel(ctx);
7349 }
7350
7351 static void gen_evsel3(DisasContext *ctx)
7352 {
7353 gen_evsel(ctx);
7354 }
7355
7356 /* Multiply */
7357
7358 static inline void gen_evmwumi(DisasContext *ctx)
7359 {
7360 TCGv_i64 t0, t1;
7361
7362 if (unlikely(!ctx->spe_enabled)) {
7363 gen_exception(ctx, POWERPC_EXCP_SPEU);
7364 return;
7365 }
7366
7367 t0 = tcg_temp_new_i64();
7368 t1 = tcg_temp_new_i64();
7369
7370 /* t0 := rA; t1 := rB */
7371 #if defined(TARGET_PPC64)
7372 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7373 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7374 #else
7375 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7376 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7377 #endif
7378
7379 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7380
7381 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7382
7383 tcg_temp_free_i64(t0);
7384 tcg_temp_free_i64(t1);
7385 }
7386
7387 static inline void gen_evmwumia(DisasContext *ctx)
7388 {
7389 TCGv_i64 tmp;
7390
7391 if (unlikely(!ctx->spe_enabled)) {
7392 gen_exception(ctx, POWERPC_EXCP_SPEU);
7393 return;
7394 }
7395
7396 gen_evmwumi(ctx); /* rD := rA * rB */
7397
7398 tmp = tcg_temp_new_i64();
7399
7400 /* acc := rD */
7401 gen_load_gpr64(tmp, rD(ctx->opcode));
7402 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7403 tcg_temp_free_i64(tmp);
7404 }
7405
7406 static inline void gen_evmwumiaa(DisasContext *ctx)
7407 {
7408 TCGv_i64 acc;
7409 TCGv_i64 tmp;
7410
7411 if (unlikely(!ctx->spe_enabled)) {
7412 gen_exception(ctx, POWERPC_EXCP_SPEU);
7413 return;
7414 }
7415
7416 gen_evmwumi(ctx); /* rD := rA * rB */
7417
7418 acc = tcg_temp_new_i64();
7419 tmp = tcg_temp_new_i64();
7420
7421 /* tmp := rD */
7422 gen_load_gpr64(tmp, rD(ctx->opcode));
7423
7424 /* Load acc */
7425 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7426
7427 /* acc := tmp + acc */
7428 tcg_gen_add_i64(acc, acc, tmp);
7429
7430 /* Store acc */
7431 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7432
7433 /* rD := acc */
7434 gen_store_gpr64(rD(ctx->opcode), acc);
7435
7436 tcg_temp_free_i64(acc);
7437 tcg_temp_free_i64(tmp);
7438 }
7439
7440 static inline void gen_evmwsmi(DisasContext *ctx)
7441 {
7442 TCGv_i64 t0, t1;
7443
7444 if (unlikely(!ctx->spe_enabled)) {
7445 gen_exception(ctx, POWERPC_EXCP_SPEU);
7446 return;
7447 }
7448
7449 t0 = tcg_temp_new_i64();
7450 t1 = tcg_temp_new_i64();
7451
7452 /* t0 := rA; t1 := rB */
7453 #if defined(TARGET_PPC64)
7454 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7455 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7456 #else
7457 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7458 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7459 #endif
7460
7461 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7462
7463 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7464
7465 tcg_temp_free_i64(t0);
7466 tcg_temp_free_i64(t1);
7467 }
7468
7469 static inline void gen_evmwsmia(DisasContext *ctx)
7470 {
7471 TCGv_i64 tmp;
7472
7473 gen_evmwsmi(ctx); /* rD := rA * rB */
7474
7475 tmp = tcg_temp_new_i64();
7476
7477 /* acc := rD */
7478 gen_load_gpr64(tmp, rD(ctx->opcode));
7479 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7480
7481 tcg_temp_free_i64(tmp);
7482 }
7483
7484 static inline void gen_evmwsmiaa(DisasContext *ctx)
7485 {
7486 TCGv_i64 acc = tcg_temp_new_i64();
7487 TCGv_i64 tmp = tcg_temp_new_i64();
7488
7489 gen_evmwsmi(ctx); /* rD := rA * rB */
7490
7491 acc = tcg_temp_new_i64();
7492 tmp = tcg_temp_new_i64();
7493
7494 /* tmp := rD */
7495 gen_load_gpr64(tmp, rD(ctx->opcode));
7496
7497 /* Load acc */
7498 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7499
7500 /* acc := tmp + acc */
7501 tcg_gen_add_i64(acc, acc, tmp);
7502
7503 /* Store acc */
7504 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7505
7506 /* rD := acc */
7507 gen_store_gpr64(rD(ctx->opcode), acc);
7508
7509 tcg_temp_free_i64(acc);
7510 tcg_temp_free_i64(tmp);
7511 }
7512
7513 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7514 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7515 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7516 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7517 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7518 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7519 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7520 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7521 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7522 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7523 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7524 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7525 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7526 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7527 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7528 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7529 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7530 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7531 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7532 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7533 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7534 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7535 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7536 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7537 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7538 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7539 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7540 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7541 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7542
7543 /* SPE load and stores */
7544 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7545 {
7546 target_ulong uimm = rB(ctx->opcode);
7547
7548 if (rA(ctx->opcode) == 0) {
7549 tcg_gen_movi_tl(EA, uimm << sh);
7550 } else {
7551 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7552 #if defined(TARGET_PPC64)
7553 if (!ctx->sf_mode) {
7554 tcg_gen_ext32u_tl(EA, EA);
7555 }
7556 #endif
7557 }
7558 }
7559
7560 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7561 {
7562 #if defined(TARGET_PPC64)
7563 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7564 #else
7565 TCGv_i64 t0 = tcg_temp_new_i64();
7566 gen_qemu_ld64(ctx, t0, addr);
7567 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7568 tcg_gen_shri_i64(t0, t0, 32);
7569 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7570 tcg_temp_free_i64(t0);
7571 #endif
7572 }
7573
7574 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7575 {
7576 #if defined(TARGET_PPC64)
7577 TCGv t0 = tcg_temp_new();
7578 gen_qemu_ld32u(ctx, t0, addr);
7579 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7580 gen_addr_add(ctx, addr, addr, 4);
7581 gen_qemu_ld32u(ctx, t0, addr);
7582 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7583 tcg_temp_free(t0);
7584 #else
7585 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7586 gen_addr_add(ctx, addr, addr, 4);
7587 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7588 #endif
7589 }
7590
7591 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7592 {
7593 TCGv t0 = tcg_temp_new();
7594 #if defined(TARGET_PPC64)
7595 gen_qemu_ld16u(ctx, t0, addr);
7596 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7597 gen_addr_add(ctx, addr, addr, 2);
7598 gen_qemu_ld16u(ctx, t0, addr);
7599 tcg_gen_shli_tl(t0, t0, 32);
7600 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7601 gen_addr_add(ctx, addr, addr, 2);
7602 gen_qemu_ld16u(ctx, t0, addr);
7603 tcg_gen_shli_tl(t0, t0, 16);
7604 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7605 gen_addr_add(ctx, addr, addr, 2);
7606 gen_qemu_ld16u(ctx, t0, addr);
7607 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7608 #else
7609 gen_qemu_ld16u(ctx, t0, addr);
7610 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7611 gen_addr_add(ctx, addr, addr, 2);
7612 gen_qemu_ld16u(ctx, t0, addr);
7613 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7614 gen_addr_add(ctx, addr, addr, 2);
7615 gen_qemu_ld16u(ctx, t0, addr);
7616 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7617 gen_addr_add(ctx, addr, addr, 2);
7618 gen_qemu_ld16u(ctx, t0, addr);
7619 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7620 #endif
7621 tcg_temp_free(t0);
7622 }
7623
7624 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7625 {
7626 TCGv t0 = tcg_temp_new();
7627 gen_qemu_ld16u(ctx, t0, addr);
7628 #if defined(TARGET_PPC64)
7629 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7630 tcg_gen_shli_tl(t0, t0, 16);
7631 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7632 #else
7633 tcg_gen_shli_tl(t0, t0, 16);
7634 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7635 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7636 #endif
7637 tcg_temp_free(t0);
7638 }
7639
7640 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7641 {
7642 TCGv t0 = tcg_temp_new();
7643 gen_qemu_ld16u(ctx, t0, addr);
7644 #if defined(TARGET_PPC64)
7645 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7646 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7647 #else
7648 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7649 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7650 #endif
7651 tcg_temp_free(t0);
7652 }
7653
7654 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7655 {
7656 TCGv t0 = tcg_temp_new();
7657 gen_qemu_ld16s(ctx, t0, addr);
7658 #if defined(TARGET_PPC64)
7659 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7660 tcg_gen_ext32u_tl(t0, t0);
7661 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7662 #else
7663 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7664 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7665 #endif
7666 tcg_temp_free(t0);
7667 }
7668
7669 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7670 {
7671 TCGv t0 = tcg_temp_new();
7672 #if defined(TARGET_PPC64)
7673 gen_qemu_ld16u(ctx, t0, addr);
7674 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7675 gen_addr_add(ctx, addr, addr, 2);
7676 gen_qemu_ld16u(ctx, t0, addr);
7677 tcg_gen_shli_tl(t0, t0, 16);
7678 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7679 #else
7680 gen_qemu_ld16u(ctx, t0, addr);
7681 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7682 gen_addr_add(ctx, addr, addr, 2);
7683 gen_qemu_ld16u(ctx, t0, addr);
7684 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7685 #endif
7686 tcg_temp_free(t0);
7687 }
7688
7689 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7690 {
7691 #if defined(TARGET_PPC64)
7692 TCGv t0 = tcg_temp_new();
7693 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7694 gen_addr_add(ctx, addr, addr, 2);
7695 gen_qemu_ld16u(ctx, t0, addr);
7696 tcg_gen_shli_tl(t0, t0, 32);
7697 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7698 tcg_temp_free(t0);
7699 #else
7700 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7701 gen_addr_add(ctx, addr, addr, 2);
7702 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7703 #endif
7704 }
7705
7706 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7707 {
7708 #if defined(TARGET_PPC64)
7709 TCGv t0 = tcg_temp_new();
7710 gen_qemu_ld16s(ctx, t0, addr);
7711 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7712 gen_addr_add(ctx, addr, addr, 2);
7713 gen_qemu_ld16s(ctx, t0, addr);
7714 tcg_gen_shli_tl(t0, t0, 32);
7715 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7716 tcg_temp_free(t0);
7717 #else
7718 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7719 gen_addr_add(ctx, addr, addr, 2);
7720 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7721 #endif
7722 }
7723
7724 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7725 {
7726 TCGv t0 = tcg_temp_new();
7727 gen_qemu_ld32u(ctx, t0, addr);
7728 #if defined(TARGET_PPC64)
7729 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7730 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7731 #else
7732 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7733 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7734 #endif
7735 tcg_temp_free(t0);
7736 }
7737
7738 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7739 {
7740 TCGv t0 = tcg_temp_new();
7741 #if defined(TARGET_PPC64)
7742 gen_qemu_ld16u(ctx, t0, addr);
7743 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7744 tcg_gen_shli_tl(t0, t0, 32);
7745 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7746 gen_addr_add(ctx, addr, addr, 2);
7747 gen_qemu_ld16u(ctx, t0, addr);
7748 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7749 tcg_gen_shli_tl(t0, t0, 16);
7750 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7751 #else
7752 gen_qemu_ld16u(ctx, t0, addr);
7753 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7754 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7755 gen_addr_add(ctx, addr, addr, 2);
7756 gen_qemu_ld16u(ctx, t0, addr);
7757 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7758 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7759 #endif
7760 tcg_temp_free(t0);
7761 }
7762
7763 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7764 {
7765 #if defined(TARGET_PPC64)
7766 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7767 #else
7768 TCGv_i64 t0 = tcg_temp_new_i64();
7769 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7770 gen_qemu_st64(ctx, t0, addr);
7771 tcg_temp_free_i64(t0);
7772 #endif
7773 }
7774
7775 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7776 {
7777 #if defined(TARGET_PPC64)
7778 TCGv t0 = tcg_temp_new();
7779 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7780 gen_qemu_st32(ctx, t0, addr);
7781 tcg_temp_free(t0);
7782 #else
7783 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7784 #endif
7785 gen_addr_add(ctx, addr, addr, 4);
7786 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7787 }
7788
7789 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7790 {
7791 TCGv t0 = tcg_temp_new();
7792 #if defined(TARGET_PPC64)
7793 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7794 #else
7795 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7796 #endif
7797 gen_qemu_st16(ctx, t0, addr);
7798 gen_addr_add(ctx, addr, addr, 2);
7799 #if defined(TARGET_PPC64)
7800 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7801 gen_qemu_st16(ctx, t0, addr);
7802 #else
7803 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7804 #endif
7805 gen_addr_add(ctx, addr, addr, 2);
7806 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7807 gen_qemu_st16(ctx, t0, addr);
7808 tcg_temp_free(t0);
7809 gen_addr_add(ctx, addr, addr, 2);
7810 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7811 }
7812
7813 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7814 {
7815 TCGv t0 = tcg_temp_new();
7816 #if defined(TARGET_PPC64)
7817 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7818 #else
7819 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7820 #endif
7821 gen_qemu_st16(ctx, t0, addr);
7822 gen_addr_add(ctx, addr, addr, 2);
7823 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7824 gen_qemu_st16(ctx, t0, addr);
7825 tcg_temp_free(t0);
7826 }
7827
7828 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7829 {
7830 #if defined(TARGET_PPC64)
7831 TCGv t0 = tcg_temp_new();
7832 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7833 gen_qemu_st16(ctx, t0, addr);
7834 tcg_temp_free(t0);
7835 #else
7836 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7837 #endif
7838 gen_addr_add(ctx, addr, addr, 2);
7839 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7840 }
7841
7842 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7843 {
7844 #if defined(TARGET_PPC64)
7845 TCGv t0 = tcg_temp_new();
7846 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7847 gen_qemu_st32(ctx, t0, addr);
7848 tcg_temp_free(t0);
7849 #else
7850 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7851 #endif
7852 }
7853
7854 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7855 {
7856 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7857 }
7858
7859 #define GEN_SPEOP_LDST(name, opc2, sh) \
7860 static void glue(gen_, name)(DisasContext *ctx) \
7861 { \
7862 TCGv t0; \
7863 if (unlikely(!ctx->spe_enabled)) { \
7864 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7865 return; \
7866 } \
7867 gen_set_access_type(ctx, ACCESS_INT); \
7868 t0 = tcg_temp_new(); \
7869 if (Rc(ctx->opcode)) { \
7870 gen_addr_spe_imm_index(ctx, t0, sh); \
7871 } else { \
7872 gen_addr_reg_index(ctx, t0); \
7873 } \
7874 gen_op_##name(ctx, t0); \
7875 tcg_temp_free(t0); \
7876 }
7877
7878 GEN_SPEOP_LDST(evldd, 0x00, 3);
7879 GEN_SPEOP_LDST(evldw, 0x01, 3);
7880 GEN_SPEOP_LDST(evldh, 0x02, 3);
7881 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7882 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7883 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7884 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7885 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7886 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7887 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7888 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7889
7890 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7891 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7892 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7893 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7894 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7895 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7896 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7897
7898 /* Multiply and add - TODO */
7899 #if 0
7900 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
7901 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7902 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7903 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7904 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7905 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7906 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7907 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7908 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7909 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7910 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7911 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7912
7913 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7914 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7915 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7916 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7917 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7918 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7919 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7920 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7921 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7922 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7923 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7924 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7925
7926 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7927 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7928 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7929 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7930 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
7931
7932 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7933 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7934 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7935 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7936 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7937 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7938 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7939 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7940 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7941 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7942 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7943 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7944
7945 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7946 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7947 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7948 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7949
7950 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7951 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7952 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7953 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7954 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7955 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7956 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7957 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7958 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7959 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7960 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7961 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7962
7963 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7964 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7965 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7966 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7967 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7968 #endif
7969
7970 /*** SPE floating-point extension ***/
7971 #if defined(TARGET_PPC64)
7972 #define GEN_SPEFPUOP_CONV_32_32(name) \
7973 static inline void gen_##name(DisasContext *ctx) \
7974 { \
7975 TCGv_i32 t0; \
7976 TCGv t1; \
7977 t0 = tcg_temp_new_i32(); \
7978 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7979 gen_helper_##name(t0, t0); \
7980 t1 = tcg_temp_new(); \
7981 tcg_gen_extu_i32_tl(t1, t0); \
7982 tcg_temp_free_i32(t0); \
7983 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7984 0xFFFFFFFF00000000ULL); \
7985 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7986 tcg_temp_free(t1); \
7987 }
7988 #define GEN_SPEFPUOP_CONV_32_64(name) \
7989 static inline void gen_##name(DisasContext *ctx) \
7990 { \
7991 TCGv_i32 t0; \
7992 TCGv t1; \
7993 t0 = tcg_temp_new_i32(); \
7994 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7995 t1 = tcg_temp_new(); \
7996 tcg_gen_extu_i32_tl(t1, t0); \
7997 tcg_temp_free_i32(t0); \
7998 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7999 0xFFFFFFFF00000000ULL); \
8000 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8001 tcg_temp_free(t1); \
8002 }
8003 #define GEN_SPEFPUOP_CONV_64_32(name) \
8004 static inline void gen_##name(DisasContext *ctx) \
8005 { \
8006 TCGv_i32 t0 = tcg_temp_new_i32(); \
8007 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8008 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
8009 tcg_temp_free_i32(t0); \
8010 }
8011 #define GEN_SPEFPUOP_CONV_64_64(name) \
8012 static inline void gen_##name(DisasContext *ctx) \
8013 { \
8014 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8015 }
8016 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8017 static inline void gen_##name(DisasContext *ctx) \
8018 { \
8019 TCGv_i32 t0, t1; \
8020 TCGv_i64 t2; \
8021 if (unlikely(!ctx->spe_enabled)) { \
8022 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8023 return; \
8024 } \
8025 t0 = tcg_temp_new_i32(); \
8026 t1 = tcg_temp_new_i32(); \
8027 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8028 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8029 gen_helper_##name(t0, t0, t1); \
8030 tcg_temp_free_i32(t1); \
8031 t2 = tcg_temp_new(); \
8032 tcg_gen_extu_i32_tl(t2, t0); \
8033 tcg_temp_free_i32(t0); \
8034 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8035 0xFFFFFFFF00000000ULL); \
8036 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8037 tcg_temp_free(t2); \
8038 }
8039 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8040 static inline void gen_##name(DisasContext *ctx) \
8041 { \
8042 if (unlikely(!ctx->spe_enabled)) { \
8043 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8044 return; \
8045 } \
8046 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8047 cpu_gpr[rB(ctx->opcode)]); \
8048 }
8049 #define GEN_SPEFPUOP_COMP_32(name) \
8050 static inline void gen_##name(DisasContext *ctx) \
8051 { \
8052 TCGv_i32 t0, t1; \
8053 if (unlikely(!ctx->spe_enabled)) { \
8054 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8055 return; \
8056 } \
8057 t0 = tcg_temp_new_i32(); \
8058 t1 = tcg_temp_new_i32(); \
8059 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8060 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8061 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
8062 tcg_temp_free_i32(t0); \
8063 tcg_temp_free_i32(t1); \
8064 }
8065 #define GEN_SPEFPUOP_COMP_64(name) \
8066 static inline void gen_##name(DisasContext *ctx) \
8067 { \
8068 if (unlikely(!ctx->spe_enabled)) { \
8069 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8070 return; \
8071 } \
8072 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8073 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8074 }
8075 #else
8076 #define GEN_SPEFPUOP_CONV_32_32(name) \
8077 static inline void gen_##name(DisasContext *ctx) \
8078 { \
8079 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8080 }
8081 #define GEN_SPEFPUOP_CONV_32_64(name) \
8082 static inline void gen_##name(DisasContext *ctx) \
8083 { \
8084 TCGv_i64 t0 = tcg_temp_new_i64(); \
8085 gen_load_gpr64(t0, rB(ctx->opcode)); \
8086 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
8087 tcg_temp_free_i64(t0); \
8088 }
8089 #define GEN_SPEFPUOP_CONV_64_32(name) \
8090 static inline void gen_##name(DisasContext *ctx) \
8091 { \
8092 TCGv_i64 t0 = tcg_temp_new_i64(); \
8093 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
8094 gen_store_gpr64(rD(ctx->opcode), t0); \
8095 tcg_temp_free_i64(t0); \
8096 }
8097 #define GEN_SPEFPUOP_CONV_64_64(name) \
8098 static inline void gen_##name(DisasContext *ctx) \
8099 { \
8100 TCGv_i64 t0 = tcg_temp_new_i64(); \
8101 gen_load_gpr64(t0, rB(ctx->opcode)); \
8102 gen_helper_##name(t0, t0); \
8103 gen_store_gpr64(rD(ctx->opcode), t0); \
8104 tcg_temp_free_i64(t0); \
8105 }
8106 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8107 static inline void gen_##name(DisasContext *ctx) \
8108 { \
8109 if (unlikely(!ctx->spe_enabled)) { \
8110 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8111 return; \
8112 } \
8113 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
8114 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8115 }
8116 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8117 static inline void gen_##name(DisasContext *ctx) \
8118 { \
8119 TCGv_i64 t0, t1; \
8120 if (unlikely(!ctx->spe_enabled)) { \
8121 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8122 return; \
8123 } \
8124 t0 = tcg_temp_new_i64(); \
8125 t1 = tcg_temp_new_i64(); \
8126 gen_load_gpr64(t0, rA(ctx->opcode)); \
8127 gen_load_gpr64(t1, rB(ctx->opcode)); \
8128 gen_helper_##name(t0, t0, t1); \
8129 gen_store_gpr64(rD(ctx->opcode), t0); \
8130 tcg_temp_free_i64(t0); \
8131 tcg_temp_free_i64(t1); \
8132 }
8133 #define GEN_SPEFPUOP_COMP_32(name) \
8134 static inline void gen_##name(DisasContext *ctx) \
8135 { \
8136 if (unlikely(!ctx->spe_enabled)) { \
8137 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8138 return; \
8139 } \
8140 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8141 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8142 }
8143 #define GEN_SPEFPUOP_COMP_64(name) \
8144 static inline void gen_##name(DisasContext *ctx) \
8145 { \
8146 TCGv_i64 t0, t1; \
8147 if (unlikely(!ctx->spe_enabled)) { \
8148 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8149 return; \
8150 } \
8151 t0 = tcg_temp_new_i64(); \
8152 t1 = tcg_temp_new_i64(); \
8153 gen_load_gpr64(t0, rA(ctx->opcode)); \
8154 gen_load_gpr64(t1, rB(ctx->opcode)); \
8155 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
8156 tcg_temp_free_i64(t0); \
8157 tcg_temp_free_i64(t1); \
8158 }
8159 #endif
8160
8161 /* Single precision floating-point vectors operations */
8162 /* Arithmetic */
8163 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8164 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8165 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8166 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8167 static inline void gen_evfsabs(DisasContext *ctx)
8168 {
8169 if (unlikely(!ctx->spe_enabled)) {
8170 gen_exception(ctx, POWERPC_EXCP_SPEU);
8171 return;
8172 }
8173 #if defined(TARGET_PPC64)
8174 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8175 #else
8176 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8177 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8178 #endif
8179 }
8180 static inline void gen_evfsnabs(DisasContext *ctx)
8181 {
8182 if (unlikely(!ctx->spe_enabled)) {
8183 gen_exception(ctx, POWERPC_EXCP_SPEU);
8184 return;
8185 }
8186 #if defined(TARGET_PPC64)
8187 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8188 #else
8189 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8190 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8191 #endif
8192 }
8193 static inline void gen_evfsneg(DisasContext *ctx)
8194 {
8195 if (unlikely(!ctx->spe_enabled)) {
8196 gen_exception(ctx, POWERPC_EXCP_SPEU);
8197 return;
8198 }
8199 #if defined(TARGET_PPC64)
8200 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8201 #else
8202 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8203 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8204 #endif
8205 }
8206
8207 /* Conversion */
8208 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8209 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8210 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8211 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8212 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8213 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8214 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8215 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8216 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8217 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8218
8219 /* Comparison */
8220 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8221 GEN_SPEFPUOP_COMP_64(evfscmplt);
8222 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8223 GEN_SPEFPUOP_COMP_64(evfststgt);
8224 GEN_SPEFPUOP_COMP_64(evfststlt);
8225 GEN_SPEFPUOP_COMP_64(evfststeq);
8226
8227 /* Opcodes definitions */
8228 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8229 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8230 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8231 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8232 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8233 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8234 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8235 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8236 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8237 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8238 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8239 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8240 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8241 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8242
8243 /* Single precision floating-point operations */
8244 /* Arithmetic */
8245 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8246 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8247 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8248 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8249 static inline void gen_efsabs(DisasContext *ctx)
8250 {
8251 if (unlikely(!ctx->spe_enabled)) {
8252 gen_exception(ctx, POWERPC_EXCP_SPEU);
8253 return;
8254 }
8255 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8256 }
8257 static inline void gen_efsnabs(DisasContext *ctx)
8258 {
8259 if (unlikely(!ctx->spe_enabled)) {
8260 gen_exception(ctx, POWERPC_EXCP_SPEU);
8261 return;
8262 }
8263 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8264 }
8265 static inline void gen_efsneg(DisasContext *ctx)
8266 {
8267 if (unlikely(!ctx->spe_enabled)) {
8268 gen_exception(ctx, POWERPC_EXCP_SPEU);
8269 return;
8270 }
8271 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8272 }
8273
8274 /* Conversion */
8275 GEN_SPEFPUOP_CONV_32_32(efscfui);
8276 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8277 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8278 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8279 GEN_SPEFPUOP_CONV_32_32(efsctui);
8280 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8281 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8282 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8283 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8284 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8285 GEN_SPEFPUOP_CONV_32_64(efscfd);
8286
8287 /* Comparison */
8288 GEN_SPEFPUOP_COMP_32(efscmpgt);
8289 GEN_SPEFPUOP_COMP_32(efscmplt);
8290 GEN_SPEFPUOP_COMP_32(efscmpeq);
8291 GEN_SPEFPUOP_COMP_32(efststgt);
8292 GEN_SPEFPUOP_COMP_32(efststlt);
8293 GEN_SPEFPUOP_COMP_32(efststeq);
8294
8295 /* Opcodes definitions */
8296 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8297 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8298 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8299 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8300 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8301 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8302 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8303 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8304 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8305 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8306 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8307 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8308 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8309 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8310
8311 /* Double precision floating-point operations */
8312 /* Arithmetic */
8313 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8314 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8315 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8316 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8317 static inline void gen_efdabs(DisasContext *ctx)
8318 {
8319 if (unlikely(!ctx->spe_enabled)) {
8320 gen_exception(ctx, POWERPC_EXCP_SPEU);
8321 return;
8322 }
8323 #if defined(TARGET_PPC64)
8324 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8325 #else
8326 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8327 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8328 #endif
8329 }
8330 static inline void gen_efdnabs(DisasContext *ctx)
8331 {
8332 if (unlikely(!ctx->spe_enabled)) {
8333 gen_exception(ctx, POWERPC_EXCP_SPEU);
8334 return;
8335 }
8336 #if defined(TARGET_PPC64)
8337 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8338 #else
8339 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8340 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8341 #endif
8342 }
8343 static inline void gen_efdneg(DisasContext *ctx)
8344 {
8345 if (unlikely(!ctx->spe_enabled)) {
8346 gen_exception(ctx, POWERPC_EXCP_SPEU);
8347 return;
8348 }
8349 #if defined(TARGET_PPC64)
8350 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8351 #else
8352 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8353 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8354 #endif
8355 }
8356
8357 /* Conversion */
8358 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8359 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8360 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8361 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8362 GEN_SPEFPUOP_CONV_32_64(efdctui);
8363 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8364 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8365 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8366 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8367 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8368 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8369 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8370 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8371 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8372 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8373
8374 /* Comparison */
8375 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8376 GEN_SPEFPUOP_COMP_64(efdcmplt);
8377 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8378 GEN_SPEFPUOP_COMP_64(efdtstgt);
8379 GEN_SPEFPUOP_COMP_64(efdtstlt);
8380 GEN_SPEFPUOP_COMP_64(efdtsteq);
8381
8382 /* Opcodes definitions */
8383 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8384 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8385 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8386 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8387 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8388 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8389 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8390 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8391 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8392 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8393 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8394 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8395 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8396 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8397 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8398 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8399
8400 static opcode_t opcodes[] = {
8401 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8402 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8403 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8404 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8405 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8406 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8407 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8408 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8409 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8410 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8411 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8412 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8413 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8414 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8415 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8416 #if defined(TARGET_PPC64)
8417 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8418 #endif
8419 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8420 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8421 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8422 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8423 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8424 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8425 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8426 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8427 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8428 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8429 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8430 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8431 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8432 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8433 #if defined(TARGET_PPC64)
8434 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8435 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8436 #endif
8437 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8438 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8439 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8440 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8441 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8442 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8443 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8444 #if defined(TARGET_PPC64)
8445 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8446 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8447 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8448 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8449 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8450 #endif
8451 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8452 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8453 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8454 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8455 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8456 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8457 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8458 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8459 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8460 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8461 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8462 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8463 #if defined(TARGET_PPC64)
8464 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8465 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8466 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8467 #endif
8468 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8469 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8470 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8471 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8472 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8473 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8474 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8475 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8476 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8477 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8478 #if defined(TARGET_PPC64)
8479 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8480 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8481 #endif
8482 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8483 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8484 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8485 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8486 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8487 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8488 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8489 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8490 #if defined(TARGET_PPC64)
8491 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8492 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8493 #endif
8494 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8495 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8496 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8497 #if defined(TARGET_PPC64)
8498 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8499 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8500 #endif
8501 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8502 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8503 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8504 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8505 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8506 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8507 #if defined(TARGET_PPC64)
8508 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8509 #endif
8510 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8511 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8512 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8513 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8514 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8515 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8516 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8517 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ),
8518 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT),
8519 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8520 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8521 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8522 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8523 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8524 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8525 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8526 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8527 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8528 #if defined(TARGET_PPC64)
8529 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8530 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8531 PPC_SEGMENT_64B),
8532 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8533 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8534 PPC_SEGMENT_64B),
8535 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8536 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8537 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8538 #endif
8539 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8540 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8541 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8542 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8543 #if defined(TARGET_PPC64)
8544 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8545 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8546 #endif
8547 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8548 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8549 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8550 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8551 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8552 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8553 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8554 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8555 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8556 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8557 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8558 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8559 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8560 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8561 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8562 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8563 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8564 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8565 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8566 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8567 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8568 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8569 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8570 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8571 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8572 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8573 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8574 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8575 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8576 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8577 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8578 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8579 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8580 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8581 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8582 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8583 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8584 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8585 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8586 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8587 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8588 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8589 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8590 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8591 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8592 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8593 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8594 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8595 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8596 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8597 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8598 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8599 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8600 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8601 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8602 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8603 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8604 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8605 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8606 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8607 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8608 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8609 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8610 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8611 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8612 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8613 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8614 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8615 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8616 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8617 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8618 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8619 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8620 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8621 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8622 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8623 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8624 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8625 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8626 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8627 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8628 PPC_NONE, PPC2_BOOKE206),
8629 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8630 PPC_NONE, PPC2_BOOKE206),
8631 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8632 PPC_NONE, PPC2_BOOKE206),
8633 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8634 PPC_NONE, PPC2_BOOKE206),
8635 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8636 PPC_NONE, PPC2_BOOKE206),
8637 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8638 PPC_NONE, PPC2_PRCNTL),
8639 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8640 PPC_NONE, PPC2_PRCNTL),
8641 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8642 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8643 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8644 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8645 PPC_BOOKE, PPC2_BOOKE206),
8646 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8647 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8648 PPC_BOOKE, PPC2_BOOKE206),
8649 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8650 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8651 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8652 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8653 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8654 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8655 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8656 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8657 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8658 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8659
8660 #undef GEN_INT_ARITH_ADD
8661 #undef GEN_INT_ARITH_ADD_CONST
8662 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8663 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8664 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8665 add_ca, compute_ca, compute_ov) \
8666 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8667 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8668 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8669 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8670 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8671 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8672 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8673 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8674 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8675 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8676 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8677
8678 #undef GEN_INT_ARITH_DIVW
8679 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8680 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8681 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8682 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8683 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8684 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8685
8686 #if defined(TARGET_PPC64)
8687 #undef GEN_INT_ARITH_DIVD
8688 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8689 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8690 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8691 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8692 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8693 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8694
8695 #undef GEN_INT_ARITH_MUL_HELPER
8696 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8697 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8698 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8699 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8700 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8701 #endif
8702
8703 #undef GEN_INT_ARITH_SUBF
8704 #undef GEN_INT_ARITH_SUBF_CONST
8705 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8706 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8707 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8708 add_ca, compute_ca, compute_ov) \
8709 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8710 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8711 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8712 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8713 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8714 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8715 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8716 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8717 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8718 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8719 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8720
8721 #undef GEN_LOGICAL1
8722 #undef GEN_LOGICAL2
8723 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8724 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8725 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8726 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8727 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8728 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8729 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8730 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8731 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8732 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8733 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8734 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8735 #if defined(TARGET_PPC64)
8736 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8737 #endif
8738
8739 #if defined(TARGET_PPC64)
8740 #undef GEN_PPC64_R2
8741 #undef GEN_PPC64_R4
8742 #define GEN_PPC64_R2(name, opc1, opc2) \
8743 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8744 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8745 PPC_64B)
8746 #define GEN_PPC64_R4(name, opc1, opc2) \
8747 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8748 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8749 PPC_64B), \
8750 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8751 PPC_64B), \
8752 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8753 PPC_64B)
8754 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8755 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8756 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8757 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8758 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8759 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8760 #endif
8761
8762 #undef _GEN_FLOAT_ACB
8763 #undef GEN_FLOAT_ACB
8764 #undef _GEN_FLOAT_AB
8765 #undef GEN_FLOAT_AB
8766 #undef _GEN_FLOAT_AC
8767 #undef GEN_FLOAT_AC
8768 #undef GEN_FLOAT_B
8769 #undef GEN_FLOAT_BS
8770 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8771 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8772 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8773 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8774 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8775 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8776 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8777 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8778 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8779 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8780 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8781 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8782 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8783 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8784 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8785 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8786 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8787 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8788 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8789
8790 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8791 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8792 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8793 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8794 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8795 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8796 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8797 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8798 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8799 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8800 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8801 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8802 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8803 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8804 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8805 #if defined(TARGET_PPC64)
8806 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8807 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8808 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8809 #endif
8810 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8811 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8812 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8813 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8814 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8815 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8816 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8817
8818 #undef GEN_LD
8819 #undef GEN_LDU
8820 #undef GEN_LDUX
8821 #undef GEN_LDX
8822 #undef GEN_LDS
8823 #define GEN_LD(name, ldop, opc, type) \
8824 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8825 #define GEN_LDU(name, ldop, opc, type) \
8826 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8827 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8828 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8829 #define GEN_LDX(name, ldop, opc2, opc3, type) \
8830 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8831 #define GEN_LDS(name, ldop, op, type) \
8832 GEN_LD(name, ldop, op | 0x20, type) \
8833 GEN_LDU(name, ldop, op | 0x21, type) \
8834 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8835 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8836
8837 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8838 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8839 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8840 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8841 #if defined(TARGET_PPC64)
8842 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8843 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8844 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8845 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8846 #endif
8847 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8848 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8849
8850 #undef GEN_ST
8851 #undef GEN_STU
8852 #undef GEN_STUX
8853 #undef GEN_STX
8854 #undef GEN_STS
8855 #define GEN_ST(name, stop, opc, type) \
8856 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8857 #define GEN_STU(name, stop, opc, type) \
8858 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8859 #define GEN_STUX(name, stop, opc2, opc3, type) \
8860 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8861 #define GEN_STX(name, stop, opc2, opc3, type) \
8862 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8863 #define GEN_STS(name, stop, op, type) \
8864 GEN_ST(name, stop, op | 0x20, type) \
8865 GEN_STU(name, stop, op | 0x21, type) \
8866 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8867 GEN_STX(name, stop, 0x17, op | 0x00, type)
8868
8869 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8870 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8871 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8872 #if defined(TARGET_PPC64)
8873 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8874 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8875 #endif
8876 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8877 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8878
8879 #undef GEN_LDF
8880 #undef GEN_LDUF
8881 #undef GEN_LDUXF
8882 #undef GEN_LDXF
8883 #undef GEN_LDFS
8884 #define GEN_LDF(name, ldop, opc, type) \
8885 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8886 #define GEN_LDUF(name, ldop, opc, type) \
8887 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8888 #define GEN_LDUXF(name, ldop, opc, type) \
8889 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8890 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
8891 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8892 #define GEN_LDFS(name, ldop, op, type) \
8893 GEN_LDF(name, ldop, op | 0x20, type) \
8894 GEN_LDUF(name, ldop, op | 0x21, type) \
8895 GEN_LDUXF(name, ldop, op | 0x01, type) \
8896 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
8897
8898 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
8899 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
8900
8901 #undef GEN_STF
8902 #undef GEN_STUF
8903 #undef GEN_STUXF
8904 #undef GEN_STXF
8905 #undef GEN_STFS
8906 #define GEN_STF(name, stop, opc, type) \
8907 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8908 #define GEN_STUF(name, stop, opc, type) \
8909 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8910 #define GEN_STUXF(name, stop, opc, type) \
8911 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8912 #define GEN_STXF(name, stop, opc2, opc3, type) \
8913 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8914 #define GEN_STFS(name, stop, op, type) \
8915 GEN_STF(name, stop, op | 0x20, type) \
8916 GEN_STUF(name, stop, op | 0x21, type) \
8917 GEN_STUXF(name, stop, op | 0x01, type) \
8918 GEN_STXF(name, stop, 0x17, op | 0x00, type)
8919
8920 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
8921 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
8922 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
8923
8924 #undef GEN_CRLOGIC
8925 #define GEN_CRLOGIC(name, tcg_op, opc) \
8926 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8927 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8928 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8929 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8930 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
8931 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
8932 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
8933 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
8934 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
8935
8936 #undef GEN_MAC_HANDLER
8937 #define GEN_MAC_HANDLER(name, opc2, opc3) \
8938 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8939 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
8940 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
8941 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
8942 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
8943 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
8944 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
8945 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
8946 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
8947 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
8948 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
8949 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
8950 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
8951 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
8952 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
8953 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
8954 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
8955 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
8956 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
8957 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
8958 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
8959 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
8960 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
8961 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
8962 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
8963 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
8964 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
8965 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
8966 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
8967 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
8968 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
8969 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
8970 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
8971 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
8972 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
8973 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
8974 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
8975 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
8976 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
8977 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
8978 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
8979 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
8980 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
8981
8982 #undef GEN_VR_LDX
8983 #undef GEN_VR_STX
8984 #undef GEN_VR_LVE
8985 #undef GEN_VR_STVE
8986 #define GEN_VR_LDX(name, opc2, opc3) \
8987 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8988 #define GEN_VR_STX(name, opc2, opc3) \
8989 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8990 #define GEN_VR_LVE(name, opc2, opc3) \
8991 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8992 #define GEN_VR_STVE(name, opc2, opc3) \
8993 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8994 GEN_VR_LDX(lvx, 0x07, 0x03),
8995 GEN_VR_LDX(lvxl, 0x07, 0x0B),
8996 GEN_VR_LVE(bx, 0x07, 0x00),
8997 GEN_VR_LVE(hx, 0x07, 0x01),
8998 GEN_VR_LVE(wx, 0x07, 0x02),
8999 GEN_VR_STX(svx, 0x07, 0x07),
9000 GEN_VR_STX(svxl, 0x07, 0x0F),
9001 GEN_VR_STVE(bx, 0x07, 0x04),
9002 GEN_VR_STVE(hx, 0x07, 0x05),
9003 GEN_VR_STVE(wx, 0x07, 0x06),
9004
9005 #undef GEN_VX_LOGICAL
9006 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9007 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9008 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9009 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9010 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9011 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9012 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9013
9014 #undef GEN_VXFORM
9015 #define GEN_VXFORM(name, opc2, opc3) \
9016 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9017 GEN_VXFORM(vaddubm, 0, 0),
9018 GEN_VXFORM(vadduhm, 0, 1),
9019 GEN_VXFORM(vadduwm, 0, 2),
9020 GEN_VXFORM(vsububm, 0, 16),
9021 GEN_VXFORM(vsubuhm, 0, 17),
9022 GEN_VXFORM(vsubuwm, 0, 18),
9023 GEN_VXFORM(vmaxub, 1, 0),
9024 GEN_VXFORM(vmaxuh, 1, 1),
9025 GEN_VXFORM(vmaxuw, 1, 2),
9026 GEN_VXFORM(vmaxsb, 1, 4),
9027 GEN_VXFORM(vmaxsh, 1, 5),
9028 GEN_VXFORM(vmaxsw, 1, 6),
9029 GEN_VXFORM(vminub, 1, 8),
9030 GEN_VXFORM(vminuh, 1, 9),
9031 GEN_VXFORM(vminuw, 1, 10),
9032 GEN_VXFORM(vminsb, 1, 12),
9033 GEN_VXFORM(vminsh, 1, 13),
9034 GEN_VXFORM(vminsw, 1, 14),
9035 GEN_VXFORM(vavgub, 1, 16),
9036 GEN_VXFORM(vavguh, 1, 17),
9037 GEN_VXFORM(vavguw, 1, 18),
9038 GEN_VXFORM(vavgsb, 1, 20),
9039 GEN_VXFORM(vavgsh, 1, 21),
9040 GEN_VXFORM(vavgsw, 1, 22),
9041 GEN_VXFORM(vmrghb, 6, 0),
9042 GEN_VXFORM(vmrghh, 6, 1),
9043 GEN_VXFORM(vmrghw, 6, 2),
9044 GEN_VXFORM(vmrglb, 6, 4),
9045 GEN_VXFORM(vmrglh, 6, 5),
9046 GEN_VXFORM(vmrglw, 6, 6),
9047 GEN_VXFORM(vmuloub, 4, 0),
9048 GEN_VXFORM(vmulouh, 4, 1),
9049 GEN_VXFORM(vmulosb, 4, 4),
9050 GEN_VXFORM(vmulosh, 4, 5),
9051 GEN_VXFORM(vmuleub, 4, 8),
9052 GEN_VXFORM(vmuleuh, 4, 9),
9053 GEN_VXFORM(vmulesb, 4, 12),
9054 GEN_VXFORM(vmulesh, 4, 13),
9055 GEN_VXFORM(vslb, 2, 4),
9056 GEN_VXFORM(vslh, 2, 5),
9057 GEN_VXFORM(vslw, 2, 6),
9058 GEN_VXFORM(vsrb, 2, 8),
9059 GEN_VXFORM(vsrh, 2, 9),
9060 GEN_VXFORM(vsrw, 2, 10),
9061 GEN_VXFORM(vsrab, 2, 12),
9062 GEN_VXFORM(vsrah, 2, 13),
9063 GEN_VXFORM(vsraw, 2, 14),
9064 GEN_VXFORM(vslo, 6, 16),
9065 GEN_VXFORM(vsro, 6, 17),
9066 GEN_VXFORM(vaddcuw, 0, 6),
9067 GEN_VXFORM(vsubcuw, 0, 22),
9068 GEN_VXFORM(vaddubs, 0, 8),
9069 GEN_VXFORM(vadduhs, 0, 9),
9070 GEN_VXFORM(vadduws, 0, 10),
9071 GEN_VXFORM(vaddsbs, 0, 12),
9072 GEN_VXFORM(vaddshs, 0, 13),
9073 GEN_VXFORM(vaddsws, 0, 14),
9074 GEN_VXFORM(vsububs, 0, 24),
9075 GEN_VXFORM(vsubuhs, 0, 25),
9076 GEN_VXFORM(vsubuws, 0, 26),
9077 GEN_VXFORM(vsubsbs, 0, 28),
9078 GEN_VXFORM(vsubshs, 0, 29),
9079 GEN_VXFORM(vsubsws, 0, 30),
9080 GEN_VXFORM(vrlb, 2, 0),
9081 GEN_VXFORM(vrlh, 2, 1),
9082 GEN_VXFORM(vrlw, 2, 2),
9083 GEN_VXFORM(vsl, 2, 7),
9084 GEN_VXFORM(vsr, 2, 11),
9085 GEN_VXFORM(vpkuhum, 7, 0),
9086 GEN_VXFORM(vpkuwum, 7, 1),
9087 GEN_VXFORM(vpkuhus, 7, 2),
9088 GEN_VXFORM(vpkuwus, 7, 3),
9089 GEN_VXFORM(vpkshus, 7, 4),
9090 GEN_VXFORM(vpkswus, 7, 5),
9091 GEN_VXFORM(vpkshss, 7, 6),
9092 GEN_VXFORM(vpkswss, 7, 7),
9093 GEN_VXFORM(vpkpx, 7, 12),
9094 GEN_VXFORM(vsum4ubs, 4, 24),
9095 GEN_VXFORM(vsum4sbs, 4, 28),
9096 GEN_VXFORM(vsum4shs, 4, 25),
9097 GEN_VXFORM(vsum2sws, 4, 26),
9098 GEN_VXFORM(vsumsws, 4, 30),
9099 GEN_VXFORM(vaddfp, 5, 0),
9100 GEN_VXFORM(vsubfp, 5, 1),
9101 GEN_VXFORM(vmaxfp, 5, 16),
9102 GEN_VXFORM(vminfp, 5, 17),
9103
9104 #undef GEN_VXRFORM1
9105 #undef GEN_VXRFORM
9106 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9107 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9108 #define GEN_VXRFORM(name, opc2, opc3) \
9109 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9110 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9111 GEN_VXRFORM(vcmpequb, 3, 0)
9112 GEN_VXRFORM(vcmpequh, 3, 1)
9113 GEN_VXRFORM(vcmpequw, 3, 2)
9114 GEN_VXRFORM(vcmpgtsb, 3, 12)
9115 GEN_VXRFORM(vcmpgtsh, 3, 13)
9116 GEN_VXRFORM(vcmpgtsw, 3, 14)
9117 GEN_VXRFORM(vcmpgtub, 3, 8)
9118 GEN_VXRFORM(vcmpgtuh, 3, 9)
9119 GEN_VXRFORM(vcmpgtuw, 3, 10)
9120 GEN_VXRFORM(vcmpeqfp, 3, 3)
9121 GEN_VXRFORM(vcmpgefp, 3, 7)
9122 GEN_VXRFORM(vcmpgtfp, 3, 11)
9123 GEN_VXRFORM(vcmpbfp, 3, 15)
9124
9125 #undef GEN_VXFORM_SIMM
9126 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9127 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9128 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9129 GEN_VXFORM_SIMM(vspltish, 6, 13),
9130 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9131
9132 #undef GEN_VXFORM_NOA
9133 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9134 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9135 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9136 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9137 GEN_VXFORM_NOA(vupklsb, 7, 10),
9138 GEN_VXFORM_NOA(vupklsh, 7, 11),
9139 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9140 GEN_VXFORM_NOA(vupklpx, 7, 15),
9141 GEN_VXFORM_NOA(vrefp, 5, 4),
9142 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9143 GEN_VXFORM_NOA(vexptefp, 5, 6),
9144 GEN_VXFORM_NOA(vlogefp, 5, 7),
9145 GEN_VXFORM_NOA(vrfim, 5, 8),
9146 GEN_VXFORM_NOA(vrfin, 5, 9),
9147 GEN_VXFORM_NOA(vrfip, 5, 10),
9148 GEN_VXFORM_NOA(vrfiz, 5, 11),
9149
9150 #undef GEN_VXFORM_UIMM
9151 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9152 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9153 GEN_VXFORM_UIMM(vspltb, 6, 8),
9154 GEN_VXFORM_UIMM(vsplth, 6, 9),
9155 GEN_VXFORM_UIMM(vspltw, 6, 10),
9156 GEN_VXFORM_UIMM(vcfux, 5, 12),
9157 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9158 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9159 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9160
9161 #undef GEN_VAFORM_PAIRED
9162 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9163 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9164 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9165 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9166 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9167 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9168 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9169 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9170
9171 #undef GEN_SPE
9172 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9173 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9174 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9175 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9176 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9177 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9178 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9179 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9180 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9181 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9182 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9183 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9184 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9185 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9186 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9187 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9188 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9189 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9190 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9191 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9192 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9193 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9194 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9195 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9196 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9197 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9198 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9199 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9200 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9201 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9202 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9203
9204 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9205 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9206 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9207 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9208 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9209 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9210 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9211 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9212 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9213 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9214 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9215 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9216 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9217 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9218
9219 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9220 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9221 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9222 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9223 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9224 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9225 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9226 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9227 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9228 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9229 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9230 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9231 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9232 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9233
9234 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9235 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9236 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9237 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9238 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9239 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9240 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9241 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9242 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9243 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9244 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9245 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9246 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9247 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9248 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9249 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9250
9251 #undef GEN_SPEOP_LDST
9252 #define GEN_SPEOP_LDST(name, opc2, sh) \
9253 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9254 GEN_SPEOP_LDST(evldd, 0x00, 3),
9255 GEN_SPEOP_LDST(evldw, 0x01, 3),
9256 GEN_SPEOP_LDST(evldh, 0x02, 3),
9257 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9258 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9259 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9260 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9261 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9262 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9263 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9264 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9265
9266 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9267 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9268 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9269 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9270 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9271 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9272 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9273 };
9274
9275 #include "translate_init.c"
9276 #include "helper_regs.h"
9277
9278 /*****************************************************************************/
9279 /* Misc PowerPC helpers */
9280 void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
9281 int flags)
9282 {
9283 #define RGPL 4
9284 #define RFPL 4
9285
9286 int i;
9287
9288 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9289 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9290 env->nip, env->lr, env->ctr, env->xer);
9291 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9292 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9293 env->hflags, env->mmu_idx);
9294 #if !defined(NO_TIMER_DUMP)
9295 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9296 #if !defined(CONFIG_USER_ONLY)
9297 " DECR %08" PRIu32
9298 #endif
9299 "\n",
9300 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9301 #if !defined(CONFIG_USER_ONLY)
9302 , cpu_ppc_load_decr(env)
9303 #endif
9304 );
9305 #endif
9306 for (i = 0; i < 32; i++) {
9307 if ((i & (RGPL - 1)) == 0)
9308 cpu_fprintf(f, "GPR%02d", i);
9309 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9310 if ((i & (RGPL - 1)) == (RGPL - 1))
9311 cpu_fprintf(f, "\n");
9312 }
9313 cpu_fprintf(f, "CR ");
9314 for (i = 0; i < 8; i++)
9315 cpu_fprintf(f, "%01x", env->crf[i]);
9316 cpu_fprintf(f, " [");
9317 for (i = 0; i < 8; i++) {
9318 char a = '-';
9319 if (env->crf[i] & 0x08)
9320 a = 'L';
9321 else if (env->crf[i] & 0x04)
9322 a = 'G';
9323 else if (env->crf[i] & 0x02)
9324 a = 'E';
9325 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9326 }
9327 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9328 env->reserve_addr);
9329 for (i = 0; i < 32; i++) {
9330 if ((i & (RFPL - 1)) == 0)
9331 cpu_fprintf(f, "FPR%02d", i);
9332 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9333 if ((i & (RFPL - 1)) == (RFPL - 1))
9334 cpu_fprintf(f, "\n");
9335 }
9336 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
9337 #if !defined(CONFIG_USER_ONLY)
9338 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9339 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9340 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9341 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9342
9343 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9344 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9345 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9346 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9347
9348 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9349 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9350 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9351 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9352
9353 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9354 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9355 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9356 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9357 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9358
9359 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9360 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9361 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9362 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9363
9364 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9365 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9366 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9367 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9368
9369 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9370 " EPR " TARGET_FMT_lx "\n",
9371 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9372 env->spr[SPR_BOOKE_EPR]);
9373
9374 /* FSL-specific */
9375 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9376 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9377 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9378 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9379
9380 /*
9381 * IVORs are left out as they are large and do not change often --
9382 * they can be read with "p $ivor0", "p $ivor1", etc.
9383 */
9384 }
9385
9386 #if defined(TARGET_PPC64)
9387 if (env->flags & POWERPC_FLAG_CFAR) {
9388 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9389 }
9390 #endif
9391
9392 switch (env->mmu_model) {
9393 case POWERPC_MMU_32B:
9394 case POWERPC_MMU_601:
9395 case POWERPC_MMU_SOFT_6xx:
9396 case POWERPC_MMU_SOFT_74xx:
9397 #if defined(TARGET_PPC64)
9398 case POWERPC_MMU_620:
9399 case POWERPC_MMU_64B:
9400 #endif
9401 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9402 break;
9403 case POWERPC_MMU_BOOKE206:
9404 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9405 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9406 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9407 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9408
9409 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9410 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9411 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9412 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9413
9414 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9415 " TLB1CFG " TARGET_FMT_lx "\n",
9416 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9417 env->spr[SPR_BOOKE_TLB1CFG]);
9418 break;
9419 default:
9420 break;
9421 }
9422 #endif
9423
9424 #undef RGPL
9425 #undef RFPL
9426 }
9427
9428 void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
9429 int flags)
9430 {
9431 #if defined(DO_PPC_STATISTICS)
9432 opc_handler_t **t1, **t2, **t3, *handler;
9433 int op1, op2, op3;
9434
9435 t1 = env->opcodes;
9436 for (op1 = 0; op1 < 64; op1++) {
9437 handler = t1[op1];
9438 if (is_indirect_opcode(handler)) {
9439 t2 = ind_table(handler);
9440 for (op2 = 0; op2 < 32; op2++) {
9441 handler = t2[op2];
9442 if (is_indirect_opcode(handler)) {
9443 t3 = ind_table(handler);
9444 for (op3 = 0; op3 < 32; op3++) {
9445 handler = t3[op3];
9446 if (handler->count == 0)
9447 continue;
9448 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9449 "%016" PRIx64 " %" PRId64 "\n",
9450 op1, op2, op3, op1, (op3 << 5) | op2,
9451 handler->oname,
9452 handler->count, handler->count);
9453 }
9454 } else {
9455 if (handler->count == 0)
9456 continue;
9457 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9458 "%016" PRIx64 " %" PRId64 "\n",
9459 op1, op2, op1, op2, handler->oname,
9460 handler->count, handler->count);
9461 }
9462 }
9463 } else {
9464 if (handler->count == 0)
9465 continue;
9466 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9467 " %" PRId64 "\n",
9468 op1, op1, handler->oname,
9469 handler->count, handler->count);
9470 }
9471 }
9472 #endif
9473 }
9474
9475 /*****************************************************************************/
9476 static inline void gen_intermediate_code_internal(CPUPPCState *env,
9477 TranslationBlock *tb,
9478 int search_pc)
9479 {
9480 DisasContext ctx, *ctxp = &ctx;
9481 opc_handler_t **table, *handler;
9482 target_ulong pc_start;
9483 uint16_t *gen_opc_end;
9484 CPUBreakpoint *bp;
9485 int j, lj = -1;
9486 int num_insns;
9487 int max_insns;
9488
9489 pc_start = tb->pc;
9490 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
9491 ctx.nip = pc_start;
9492 ctx.tb = tb;
9493 ctx.exception = POWERPC_EXCP_NONE;
9494 ctx.spr_cb = env->spr_cb;
9495 ctx.mem_idx = env->mmu_idx;
9496 ctx.access_type = -1;
9497 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9498 #if defined(TARGET_PPC64)
9499 ctx.sf_mode = msr_sf;
9500 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9501 #endif
9502 ctx.fpu_enabled = msr_fp;
9503 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9504 ctx.spe_enabled = msr_spe;
9505 else
9506 ctx.spe_enabled = 0;
9507 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9508 ctx.altivec_enabled = msr_vr;
9509 else
9510 ctx.altivec_enabled = 0;
9511 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9512 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9513 else
9514 ctx.singlestep_enabled = 0;
9515 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9516 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9517 if (unlikely(env->singlestep_enabled))
9518 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9519 #if defined (DO_SINGLE_STEP) && 0
9520 /* Single step trace mode */
9521 msr_se = 1;
9522 #endif
9523 num_insns = 0;
9524 max_insns = tb->cflags & CF_COUNT_MASK;
9525 if (max_insns == 0)
9526 max_insns = CF_COUNT_MASK;
9527
9528 gen_icount_start();
9529 /* Set env in case of segfault during code fetch */
9530 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
9531 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9532 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9533 if (bp->pc == ctx.nip) {
9534 gen_debug_exception(ctxp);
9535 break;
9536 }
9537 }
9538 }
9539 if (unlikely(search_pc)) {
9540 j = gen_opc_ptr - gen_opc_buf;
9541 if (lj < j) {
9542 lj++;
9543 while (lj < j)
9544 gen_opc_instr_start[lj++] = 0;
9545 }
9546 gen_opc_pc[lj] = ctx.nip;
9547 gen_opc_instr_start[lj] = 1;
9548 gen_opc_icount[lj] = num_insns;
9549 }
9550 LOG_DISAS("----------------\n");
9551 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9552 ctx.nip, ctx.mem_idx, (int)msr_ir);
9553 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9554 gen_io_start();
9555 if (unlikely(ctx.le_mode)) {
9556 ctx.opcode = bswap32(ldl_code(ctx.nip));
9557 } else {
9558 ctx.opcode = ldl_code(ctx.nip);
9559 }
9560 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9561 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9562 opc3(ctx.opcode), little_endian ? "little" : "big");
9563 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
9564 tcg_gen_debug_insn_start(ctx.nip);
9565 ctx.nip += 4;
9566 table = env->opcodes;
9567 num_insns++;
9568 handler = table[opc1(ctx.opcode)];
9569 if (is_indirect_opcode(handler)) {
9570 table = ind_table(handler);
9571 handler = table[opc2(ctx.opcode)];
9572 if (is_indirect_opcode(handler)) {
9573 table = ind_table(handler);
9574 handler = table[opc3(ctx.opcode)];
9575 }
9576 }
9577 /* Is opcode *REALLY* valid ? */
9578 if (unlikely(handler->handler == &gen_invalid)) {
9579 if (qemu_log_enabled()) {
9580 qemu_log("invalid/unsupported opcode: "
9581 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9582 opc1(ctx.opcode), opc2(ctx.opcode),
9583 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9584 }
9585 } else {
9586 uint32_t inval;
9587
9588 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9589 inval = handler->inval2;
9590 } else {
9591 inval = handler->inval1;
9592 }
9593
9594 if (unlikely((ctx.opcode & inval) != 0)) {
9595 if (qemu_log_enabled()) {
9596 qemu_log("invalid bits: %08x for opcode: "
9597 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9598 ctx.opcode & inval, opc1(ctx.opcode),
9599 opc2(ctx.opcode), opc3(ctx.opcode),
9600 ctx.opcode, ctx.nip - 4);
9601 }
9602 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9603 break;
9604 }
9605 }
9606 (*(handler->handler))(&ctx);
9607 #if defined(DO_PPC_STATISTICS)
9608 handler->count++;
9609 #endif
9610 /* Check trace mode exceptions */
9611 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9612 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9613 ctx.exception != POWERPC_SYSCALL &&
9614 ctx.exception != POWERPC_EXCP_TRAP &&
9615 ctx.exception != POWERPC_EXCP_BRANCH)) {
9616 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9617 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9618 (env->singlestep_enabled) ||
9619 singlestep ||
9620 num_insns >= max_insns)) {
9621 /* if we reach a page boundary or are single stepping, stop
9622 * generation
9623 */
9624 break;
9625 }
9626 }
9627 if (tb->cflags & CF_LAST_IO)
9628 gen_io_end();
9629 if (ctx.exception == POWERPC_EXCP_NONE) {
9630 gen_goto_tb(&ctx, 0, ctx.nip);
9631 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9632 if (unlikely(env->singlestep_enabled)) {
9633 gen_debug_exception(ctxp);
9634 }
9635 /* Generate the return instruction */
9636 tcg_gen_exit_tb(0);
9637 }
9638 gen_icount_end(tb, num_insns);
9639 *gen_opc_ptr = INDEX_op_end;
9640 if (unlikely(search_pc)) {
9641 j = gen_opc_ptr - gen_opc_buf;
9642 lj++;
9643 while (lj <= j)
9644 gen_opc_instr_start[lj++] = 0;
9645 } else {
9646 tb->size = ctx.nip - pc_start;
9647 tb->icount = num_insns;
9648 }
9649 #if defined(DEBUG_DISAS)
9650 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9651 int flags;
9652 flags = env->bfd_mach;
9653 flags |= ctx.le_mode << 16;
9654 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9655 log_target_disas(pc_start, ctx.nip - pc_start, flags);
9656 qemu_log("\n");
9657 }
9658 #endif
9659 }
9660
9661 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9662 {
9663 gen_intermediate_code_internal(env, tb, 0);
9664 }
9665
9666 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9667 {
9668 gen_intermediate_code_internal(env, tb, 1);
9669 }
9670
9671 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9672 {
9673 env->nip = gen_opc_pc[pc_pos];
9674 }
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