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target-ppc: Altivec 2.07: Quadword Addition and Subtracation
[mirror_qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 10*5 + 22*6 /* VSR */
55 + 8*5 /* CRF */];
56 static TCGv cpu_gpr[32];
57 #if !defined(TARGET_PPC64)
58 static TCGv cpu_gprh[32];
59 #endif
60 static TCGv_i64 cpu_fpr[32];
61 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
62 static TCGv_i64 cpu_vsr[32];
63 static TCGv_i32 cpu_crf[8];
64 static TCGv cpu_nip;
65 static TCGv cpu_msr;
66 static TCGv cpu_ctr;
67 static TCGv cpu_lr;
68 #if defined(TARGET_PPC64)
69 static TCGv cpu_cfar;
70 #endif
71 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
72 static TCGv cpu_reserve;
73 static TCGv cpu_fpscr;
74 static TCGv_i32 cpu_access_type;
75
76 #include "exec/gen-icount.h"
77
78 void ppc_translate_init(void)
79 {
80 int i;
81 char* p;
82 size_t cpu_reg_names_size;
83 static int done_init = 0;
84
85 if (done_init)
86 return;
87
88 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
89
90 p = cpu_reg_names;
91 cpu_reg_names_size = sizeof(cpu_reg_names);
92
93 for (i = 0; i < 8; i++) {
94 snprintf(p, cpu_reg_names_size, "crf%d", i);
95 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
96 offsetof(CPUPPCState, crf[i]), p);
97 p += 5;
98 cpu_reg_names_size -= 5;
99 }
100
101 for (i = 0; i < 32; i++) {
102 snprintf(p, cpu_reg_names_size, "r%d", i);
103 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
104 offsetof(CPUPPCState, gpr[i]), p);
105 p += (i < 10) ? 3 : 4;
106 cpu_reg_names_size -= (i < 10) ? 3 : 4;
107 #if !defined(TARGET_PPC64)
108 snprintf(p, cpu_reg_names_size, "r%dH", i);
109 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
110 offsetof(CPUPPCState, gprh[i]), p);
111 p += (i < 10) ? 4 : 5;
112 cpu_reg_names_size -= (i < 10) ? 4 : 5;
113 #endif
114
115 snprintf(p, cpu_reg_names_size, "fp%d", i);
116 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
117 offsetof(CPUPPCState, fpr[i]), p);
118 p += (i < 10) ? 4 : 5;
119 cpu_reg_names_size -= (i < 10) ? 4 : 5;
120
121 snprintf(p, cpu_reg_names_size, "avr%dH", i);
122 #ifdef HOST_WORDS_BIGENDIAN
123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
124 offsetof(CPUPPCState, avr[i].u64[0]), p);
125 #else
126 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
127 offsetof(CPUPPCState, avr[i].u64[1]), p);
128 #endif
129 p += (i < 10) ? 6 : 7;
130 cpu_reg_names_size -= (i < 10) ? 6 : 7;
131
132 snprintf(p, cpu_reg_names_size, "avr%dL", i);
133 #ifdef HOST_WORDS_BIGENDIAN
134 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
135 offsetof(CPUPPCState, avr[i].u64[1]), p);
136 #else
137 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
138 offsetof(CPUPPCState, avr[i].u64[0]), p);
139 #endif
140 p += (i < 10) ? 6 : 7;
141 cpu_reg_names_size -= (i < 10) ? 6 : 7;
142 snprintf(p, cpu_reg_names_size, "vsr%d", i);
143 cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
144 offsetof(CPUPPCState, vsr[i]), p);
145 p += (i < 10) ? 5 : 6;
146 cpu_reg_names_size -= (i < 10) ? 5 : 6;
147 }
148
149 cpu_nip = tcg_global_mem_new(TCG_AREG0,
150 offsetof(CPUPPCState, nip), "nip");
151
152 cpu_msr = tcg_global_mem_new(TCG_AREG0,
153 offsetof(CPUPPCState, msr), "msr");
154
155 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, ctr), "ctr");
157
158 cpu_lr = tcg_global_mem_new(TCG_AREG0,
159 offsetof(CPUPPCState, lr), "lr");
160
161 #if defined(TARGET_PPC64)
162 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
163 offsetof(CPUPPCState, cfar), "cfar");
164 #endif
165
166 cpu_xer = tcg_global_mem_new(TCG_AREG0,
167 offsetof(CPUPPCState, xer), "xer");
168 cpu_so = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, so), "SO");
170 cpu_ov = tcg_global_mem_new(TCG_AREG0,
171 offsetof(CPUPPCState, ov), "OV");
172 cpu_ca = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, ca), "CA");
174
175 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
176 offsetof(CPUPPCState, reserve_addr),
177 "reserve_addr");
178
179 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
180 offsetof(CPUPPCState, fpscr), "fpscr");
181
182 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
183 offsetof(CPUPPCState, access_type), "access_type");
184
185 done_init = 1;
186 }
187
188 /* internal defines */
189 typedef struct DisasContext {
190 struct TranslationBlock *tb;
191 target_ulong nip;
192 uint32_t opcode;
193 uint32_t exception;
194 /* Routine used to access memory */
195 int mem_idx;
196 int access_type;
197 /* Translation flags */
198 int le_mode;
199 #if defined(TARGET_PPC64)
200 int sf_mode;
201 int has_cfar;
202 #endif
203 int fpu_enabled;
204 int altivec_enabled;
205 int vsx_enabled;
206 int spe_enabled;
207 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
208 int singlestep_enabled;
209 uint64_t insns_flags;
210 uint64_t insns_flags2;
211 } DisasContext;
212
213 /* True when active word size < size of target_long. */
214 #ifdef TARGET_PPC64
215 # define NARROW_MODE(C) (!(C)->sf_mode)
216 #else
217 # define NARROW_MODE(C) 0
218 #endif
219
220 struct opc_handler_t {
221 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
222 uint32_t inval1;
223 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
224 uint32_t inval2;
225 /* instruction type */
226 uint64_t type;
227 /* extended instruction type */
228 uint64_t type2;
229 /* handler */
230 void (*handler)(DisasContext *ctx);
231 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
232 const char *oname;
233 #endif
234 #if defined(DO_PPC_STATISTICS)
235 uint64_t count;
236 #endif
237 };
238
239 static inline void gen_reset_fpstatus(void)
240 {
241 gen_helper_reset_fpstatus(cpu_env);
242 }
243
244 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
245 {
246 TCGv_i32 t0 = tcg_temp_new_i32();
247
248 if (set_fprf != 0) {
249 /* This case might be optimized later */
250 tcg_gen_movi_i32(t0, 1);
251 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
252 if (unlikely(set_rc)) {
253 tcg_gen_mov_i32(cpu_crf[1], t0);
254 }
255 gen_helper_float_check_status(cpu_env);
256 } else if (unlikely(set_rc)) {
257 /* We always need to compute fpcc */
258 tcg_gen_movi_i32(t0, 0);
259 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
260 tcg_gen_mov_i32(cpu_crf[1], t0);
261 }
262
263 tcg_temp_free_i32(t0);
264 }
265
266 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
267 {
268 if (ctx->access_type != access_type) {
269 tcg_gen_movi_i32(cpu_access_type, access_type);
270 ctx->access_type = access_type;
271 }
272 }
273
274 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
275 {
276 if (NARROW_MODE(ctx)) {
277 nip = (uint32_t)nip;
278 }
279 tcg_gen_movi_tl(cpu_nip, nip);
280 }
281
282 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
283 {
284 TCGv_i32 t0, t1;
285 if (ctx->exception == POWERPC_EXCP_NONE) {
286 gen_update_nip(ctx, ctx->nip);
287 }
288 t0 = tcg_const_i32(excp);
289 t1 = tcg_const_i32(error);
290 gen_helper_raise_exception_err(cpu_env, t0, t1);
291 tcg_temp_free_i32(t0);
292 tcg_temp_free_i32(t1);
293 ctx->exception = (excp);
294 }
295
296 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
297 {
298 TCGv_i32 t0;
299 if (ctx->exception == POWERPC_EXCP_NONE) {
300 gen_update_nip(ctx, ctx->nip);
301 }
302 t0 = tcg_const_i32(excp);
303 gen_helper_raise_exception(cpu_env, t0);
304 tcg_temp_free_i32(t0);
305 ctx->exception = (excp);
306 }
307
308 static inline void gen_debug_exception(DisasContext *ctx)
309 {
310 TCGv_i32 t0;
311
312 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
313 (ctx->exception != POWERPC_EXCP_SYNC)) {
314 gen_update_nip(ctx, ctx->nip);
315 }
316 t0 = tcg_const_i32(EXCP_DEBUG);
317 gen_helper_raise_exception(cpu_env, t0);
318 tcg_temp_free_i32(t0);
319 }
320
321 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
322 {
323 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
324 }
325
326 /* Stop translation */
327 static inline void gen_stop_exception(DisasContext *ctx)
328 {
329 gen_update_nip(ctx, ctx->nip);
330 ctx->exception = POWERPC_EXCP_STOP;
331 }
332
333 /* No need to update nip here, as execution flow will change */
334 static inline void gen_sync_exception(DisasContext *ctx)
335 {
336 ctx->exception = POWERPC_EXCP_SYNC;
337 }
338
339 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
340 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
341
342 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
343 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
344
345 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
346 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
347
348 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
349 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
350
351 typedef struct opcode_t {
352 unsigned char opc1, opc2, opc3;
353 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
354 unsigned char pad[5];
355 #else
356 unsigned char pad[1];
357 #endif
358 opc_handler_t handler;
359 const char *oname;
360 } opcode_t;
361
362 /*****************************************************************************/
363 /*** Instruction decoding ***/
364 #define EXTRACT_HELPER(name, shift, nb) \
365 static inline uint32_t name(uint32_t opcode) \
366 { \
367 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
368 }
369
370 #define EXTRACT_SHELPER(name, shift, nb) \
371 static inline int32_t name(uint32_t opcode) \
372 { \
373 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
374 }
375
376 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
377 static inline uint32_t name(uint32_t opcode) \
378 { \
379 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
380 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
381 }
382 /* Opcode part 1 */
383 EXTRACT_HELPER(opc1, 26, 6);
384 /* Opcode part 2 */
385 EXTRACT_HELPER(opc2, 1, 5);
386 /* Opcode part 3 */
387 EXTRACT_HELPER(opc3, 6, 5);
388 /* Update Cr0 flags */
389 EXTRACT_HELPER(Rc, 0, 1);
390 /* Update Cr6 flags (Altivec) */
391 EXTRACT_HELPER(Rc21, 10, 1);
392 /* Destination */
393 EXTRACT_HELPER(rD, 21, 5);
394 /* Source */
395 EXTRACT_HELPER(rS, 21, 5);
396 /* First operand */
397 EXTRACT_HELPER(rA, 16, 5);
398 /* Second operand */
399 EXTRACT_HELPER(rB, 11, 5);
400 /* Third operand */
401 EXTRACT_HELPER(rC, 6, 5);
402 /*** Get CRn ***/
403 EXTRACT_HELPER(crfD, 23, 3);
404 EXTRACT_HELPER(crfS, 18, 3);
405 EXTRACT_HELPER(crbD, 21, 5);
406 EXTRACT_HELPER(crbA, 16, 5);
407 EXTRACT_HELPER(crbB, 11, 5);
408 /* SPR / TBL */
409 EXTRACT_HELPER(_SPR, 11, 10);
410 static inline uint32_t SPR(uint32_t opcode)
411 {
412 uint32_t sprn = _SPR(opcode);
413
414 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
415 }
416 /*** Get constants ***/
417 EXTRACT_HELPER(IMM, 12, 8);
418 /* 16 bits signed immediate value */
419 EXTRACT_SHELPER(SIMM, 0, 16);
420 /* 16 bits unsigned immediate value */
421 EXTRACT_HELPER(UIMM, 0, 16);
422 /* 5 bits signed immediate value */
423 EXTRACT_HELPER(SIMM5, 16, 5);
424 /* 5 bits signed immediate value */
425 EXTRACT_HELPER(UIMM5, 16, 5);
426 /* Bit count */
427 EXTRACT_HELPER(NB, 11, 5);
428 /* Shift count */
429 EXTRACT_HELPER(SH, 11, 5);
430 /* Vector shift count */
431 EXTRACT_HELPER(VSH, 6, 4);
432 /* Mask start */
433 EXTRACT_HELPER(MB, 6, 5);
434 /* Mask end */
435 EXTRACT_HELPER(ME, 1, 5);
436 /* Trap operand */
437 EXTRACT_HELPER(TO, 21, 5);
438
439 EXTRACT_HELPER(CRM, 12, 8);
440 EXTRACT_HELPER(SR, 16, 4);
441
442 /* mtfsf/mtfsfi */
443 EXTRACT_HELPER(FPBF, 23, 3);
444 EXTRACT_HELPER(FPIMM, 12, 4);
445 EXTRACT_HELPER(FPL, 25, 1);
446 EXTRACT_HELPER(FPFLM, 17, 8);
447 EXTRACT_HELPER(FPW, 16, 1);
448
449 /*** Jump target decoding ***/
450 /* Displacement */
451 EXTRACT_SHELPER(d, 0, 16);
452 /* Immediate address */
453 static inline target_ulong LI(uint32_t opcode)
454 {
455 return (opcode >> 0) & 0x03FFFFFC;
456 }
457
458 static inline uint32_t BD(uint32_t opcode)
459 {
460 return (opcode >> 0) & 0xFFFC;
461 }
462
463 EXTRACT_HELPER(BO, 21, 5);
464 EXTRACT_HELPER(BI, 16, 5);
465 /* Absolute/relative address */
466 EXTRACT_HELPER(AA, 1, 1);
467 /* Link */
468 EXTRACT_HELPER(LK, 0, 1);
469
470 /* Create a mask between <start> and <end> bits */
471 static inline target_ulong MASK(uint32_t start, uint32_t end)
472 {
473 target_ulong ret;
474
475 #if defined(TARGET_PPC64)
476 if (likely(start == 0)) {
477 ret = UINT64_MAX << (63 - end);
478 } else if (likely(end == 63)) {
479 ret = UINT64_MAX >> start;
480 }
481 #else
482 if (likely(start == 0)) {
483 ret = UINT32_MAX << (31 - end);
484 } else if (likely(end == 31)) {
485 ret = UINT32_MAX >> start;
486 }
487 #endif
488 else {
489 ret = (((target_ulong)(-1ULL)) >> (start)) ^
490 (((target_ulong)(-1ULL) >> (end)) >> 1);
491 if (unlikely(start > end))
492 return ~ret;
493 }
494
495 return ret;
496 }
497
498 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
499 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
500 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
501 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
502 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
503 EXTRACT_HELPER(DM, 8, 2);
504 EXTRACT_HELPER(UIM, 16, 2);
505 EXTRACT_HELPER(SHW, 8, 2);
506 /*****************************************************************************/
507 /* PowerPC instructions table */
508
509 #if defined(DO_PPC_STATISTICS)
510 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
511 { \
512 .opc1 = op1, \
513 .opc2 = op2, \
514 .opc3 = op3, \
515 .pad = { 0, }, \
516 .handler = { \
517 .inval1 = invl, \
518 .type = _typ, \
519 .type2 = _typ2, \
520 .handler = &gen_##name, \
521 .oname = stringify(name), \
522 }, \
523 .oname = stringify(name), \
524 }
525 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
526 { \
527 .opc1 = op1, \
528 .opc2 = op2, \
529 .opc3 = op3, \
530 .pad = { 0, }, \
531 .handler = { \
532 .inval1 = invl1, \
533 .inval2 = invl2, \
534 .type = _typ, \
535 .type2 = _typ2, \
536 .handler = &gen_##name, \
537 .oname = stringify(name), \
538 }, \
539 .oname = stringify(name), \
540 }
541 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
542 { \
543 .opc1 = op1, \
544 .opc2 = op2, \
545 .opc3 = op3, \
546 .pad = { 0, }, \
547 .handler = { \
548 .inval1 = invl, \
549 .type = _typ, \
550 .type2 = _typ2, \
551 .handler = &gen_##name, \
552 .oname = onam, \
553 }, \
554 .oname = onam, \
555 }
556 #else
557 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
558 { \
559 .opc1 = op1, \
560 .opc2 = op2, \
561 .opc3 = op3, \
562 .pad = { 0, }, \
563 .handler = { \
564 .inval1 = invl, \
565 .type = _typ, \
566 .type2 = _typ2, \
567 .handler = &gen_##name, \
568 }, \
569 .oname = stringify(name), \
570 }
571 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
572 { \
573 .opc1 = op1, \
574 .opc2 = op2, \
575 .opc3 = op3, \
576 .pad = { 0, }, \
577 .handler = { \
578 .inval1 = invl1, \
579 .inval2 = invl2, \
580 .type = _typ, \
581 .type2 = _typ2, \
582 .handler = &gen_##name, \
583 }, \
584 .oname = stringify(name), \
585 }
586 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
587 { \
588 .opc1 = op1, \
589 .opc2 = op2, \
590 .opc3 = op3, \
591 .pad = { 0, }, \
592 .handler = { \
593 .inval1 = invl, \
594 .type = _typ, \
595 .type2 = _typ2, \
596 .handler = &gen_##name, \
597 }, \
598 .oname = onam, \
599 }
600 #endif
601
602 /* SPR load/store helpers */
603 static inline void gen_load_spr(TCGv t, int reg)
604 {
605 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
606 }
607
608 static inline void gen_store_spr(int reg, TCGv t)
609 {
610 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
611 }
612
613 /* Invalid instruction */
614 static void gen_invalid(DisasContext *ctx)
615 {
616 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
617 }
618
619 static opc_handler_t invalid_handler = {
620 .inval1 = 0xFFFFFFFF,
621 .inval2 = 0xFFFFFFFF,
622 .type = PPC_NONE,
623 .type2 = PPC_NONE,
624 .handler = gen_invalid,
625 };
626
627 #if defined(TARGET_PPC64)
628 /* NOTE: as this time, the only use of is_user_mode() is in 64 bit code. And */
629 /* so the function is wrapped in the standard 64-bit ifdef in order to */
630 /* avoid compiler warnings in 32-bit implementations. */
631 static bool is_user_mode(DisasContext *ctx)
632 {
633 #if defined(CONFIG_USER_ONLY)
634 return true;
635 #else
636 return ctx->mem_idx == 0;
637 #endif
638 }
639 #endif
640
641 /*** Integer comparison ***/
642
643 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
644 {
645 TCGv t0 = tcg_temp_new();
646 TCGv_i32 t1 = tcg_temp_new_i32();
647
648 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
649
650 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
651 tcg_gen_trunc_tl_i32(t1, t0);
652 tcg_gen_shli_i32(t1, t1, CRF_LT);
653 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
654
655 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
656 tcg_gen_trunc_tl_i32(t1, t0);
657 tcg_gen_shli_i32(t1, t1, CRF_GT);
658 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
659
660 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
661 tcg_gen_trunc_tl_i32(t1, t0);
662 tcg_gen_shli_i32(t1, t1, CRF_EQ);
663 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
664
665 tcg_temp_free(t0);
666 tcg_temp_free_i32(t1);
667 }
668
669 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
670 {
671 TCGv t0 = tcg_const_tl(arg1);
672 gen_op_cmp(arg0, t0, s, crf);
673 tcg_temp_free(t0);
674 }
675
676 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
677 {
678 TCGv t0, t1;
679 t0 = tcg_temp_new();
680 t1 = tcg_temp_new();
681 if (s) {
682 tcg_gen_ext32s_tl(t0, arg0);
683 tcg_gen_ext32s_tl(t1, arg1);
684 } else {
685 tcg_gen_ext32u_tl(t0, arg0);
686 tcg_gen_ext32u_tl(t1, arg1);
687 }
688 gen_op_cmp(t0, t1, s, crf);
689 tcg_temp_free(t1);
690 tcg_temp_free(t0);
691 }
692
693 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
694 {
695 TCGv t0 = tcg_const_tl(arg1);
696 gen_op_cmp32(arg0, t0, s, crf);
697 tcg_temp_free(t0);
698 }
699
700 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
701 {
702 if (NARROW_MODE(ctx)) {
703 gen_op_cmpi32(reg, 0, 1, 0);
704 } else {
705 gen_op_cmpi(reg, 0, 1, 0);
706 }
707 }
708
709 /* cmp */
710 static void gen_cmp(DisasContext *ctx)
711 {
712 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
713 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
714 1, crfD(ctx->opcode));
715 } else {
716 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
717 1, crfD(ctx->opcode));
718 }
719 }
720
721 /* cmpi */
722 static void gen_cmpi(DisasContext *ctx)
723 {
724 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
725 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
726 1, crfD(ctx->opcode));
727 } else {
728 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
729 1, crfD(ctx->opcode));
730 }
731 }
732
733 /* cmpl */
734 static void gen_cmpl(DisasContext *ctx)
735 {
736 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
737 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
738 0, crfD(ctx->opcode));
739 } else {
740 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
741 0, crfD(ctx->opcode));
742 }
743 }
744
745 /* cmpli */
746 static void gen_cmpli(DisasContext *ctx)
747 {
748 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
749 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
750 0, crfD(ctx->opcode));
751 } else {
752 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
753 0, crfD(ctx->opcode));
754 }
755 }
756
757 /* isel (PowerPC 2.03 specification) */
758 static void gen_isel(DisasContext *ctx)
759 {
760 int l1, l2;
761 uint32_t bi = rC(ctx->opcode);
762 uint32_t mask;
763 TCGv_i32 t0;
764
765 l1 = gen_new_label();
766 l2 = gen_new_label();
767
768 mask = 1 << (3 - (bi & 0x03));
769 t0 = tcg_temp_new_i32();
770 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
771 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
772 if (rA(ctx->opcode) == 0)
773 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
774 else
775 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
776 tcg_gen_br(l2);
777 gen_set_label(l1);
778 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
779 gen_set_label(l2);
780 tcg_temp_free_i32(t0);
781 }
782
783 /* cmpb: PowerPC 2.05 specification */
784 static void gen_cmpb(DisasContext *ctx)
785 {
786 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
787 cpu_gpr[rB(ctx->opcode)]);
788 }
789
790 /*** Integer arithmetic ***/
791
792 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
793 TCGv arg1, TCGv arg2, int sub)
794 {
795 TCGv t0 = tcg_temp_new();
796
797 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
798 tcg_gen_xor_tl(t0, arg1, arg2);
799 if (sub) {
800 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
801 } else {
802 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
803 }
804 tcg_temp_free(t0);
805 if (NARROW_MODE(ctx)) {
806 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
807 }
808 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
809 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
810 }
811
812 /* Common add function */
813 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
814 TCGv arg2, bool add_ca, bool compute_ca,
815 bool compute_ov, bool compute_rc0)
816 {
817 TCGv t0 = ret;
818
819 if (compute_ca || compute_ov) {
820 t0 = tcg_temp_new();
821 }
822
823 if (compute_ca) {
824 if (NARROW_MODE(ctx)) {
825 /* Caution: a non-obvious corner case of the spec is that we
826 must produce the *entire* 64-bit addition, but produce the
827 carry into bit 32. */
828 TCGv t1 = tcg_temp_new();
829 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
830 tcg_gen_add_tl(t0, arg1, arg2);
831 if (add_ca) {
832 tcg_gen_add_tl(t0, t0, cpu_ca);
833 }
834 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
835 tcg_temp_free(t1);
836 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
837 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
838 } else {
839 TCGv zero = tcg_const_tl(0);
840 if (add_ca) {
841 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
842 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
843 } else {
844 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
845 }
846 tcg_temp_free(zero);
847 }
848 } else {
849 tcg_gen_add_tl(t0, arg1, arg2);
850 if (add_ca) {
851 tcg_gen_add_tl(t0, t0, cpu_ca);
852 }
853 }
854
855 if (compute_ov) {
856 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
857 }
858 if (unlikely(compute_rc0)) {
859 gen_set_Rc0(ctx, t0);
860 }
861
862 if (!TCGV_EQUAL(t0, ret)) {
863 tcg_gen_mov_tl(ret, t0);
864 tcg_temp_free(t0);
865 }
866 }
867 /* Add functions with two operands */
868 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
869 static void glue(gen_, name)(DisasContext *ctx) \
870 { \
871 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
872 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
873 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
874 }
875 /* Add functions with one operand and one immediate */
876 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
877 add_ca, compute_ca, compute_ov) \
878 static void glue(gen_, name)(DisasContext *ctx) \
879 { \
880 TCGv t0 = tcg_const_tl(const_val); \
881 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
882 cpu_gpr[rA(ctx->opcode)], t0, \
883 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
884 tcg_temp_free(t0); \
885 }
886
887 /* add add. addo addo. */
888 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
889 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
890 /* addc addc. addco addco. */
891 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
892 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
893 /* adde adde. addeo addeo. */
894 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
895 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
896 /* addme addme. addmeo addmeo. */
897 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
898 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
899 /* addze addze. addzeo addzeo.*/
900 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
901 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
902 /* addi */
903 static void gen_addi(DisasContext *ctx)
904 {
905 target_long simm = SIMM(ctx->opcode);
906
907 if (rA(ctx->opcode) == 0) {
908 /* li case */
909 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
910 } else {
911 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
912 cpu_gpr[rA(ctx->opcode)], simm);
913 }
914 }
915 /* addic addic.*/
916 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
917 {
918 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
919 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
920 c, 0, 1, 0, compute_rc0);
921 tcg_temp_free(c);
922 }
923
924 static void gen_addic(DisasContext *ctx)
925 {
926 gen_op_addic(ctx, 0);
927 }
928
929 static void gen_addic_(DisasContext *ctx)
930 {
931 gen_op_addic(ctx, 1);
932 }
933
934 /* addis */
935 static void gen_addis(DisasContext *ctx)
936 {
937 target_long simm = SIMM(ctx->opcode);
938
939 if (rA(ctx->opcode) == 0) {
940 /* lis case */
941 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
942 } else {
943 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
944 cpu_gpr[rA(ctx->opcode)], simm << 16);
945 }
946 }
947
948 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
949 TCGv arg2, int sign, int compute_ov)
950 {
951 int l1 = gen_new_label();
952 int l2 = gen_new_label();
953 TCGv_i32 t0 = tcg_temp_local_new_i32();
954 TCGv_i32 t1 = tcg_temp_local_new_i32();
955
956 tcg_gen_trunc_tl_i32(t0, arg1);
957 tcg_gen_trunc_tl_i32(t1, arg2);
958 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
959 if (sign) {
960 int l3 = gen_new_label();
961 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
962 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
963 gen_set_label(l3);
964 tcg_gen_div_i32(t0, t0, t1);
965 } else {
966 tcg_gen_divu_i32(t0, t0, t1);
967 }
968 if (compute_ov) {
969 tcg_gen_movi_tl(cpu_ov, 0);
970 }
971 tcg_gen_br(l2);
972 gen_set_label(l1);
973 if (sign) {
974 tcg_gen_sari_i32(t0, t0, 31);
975 } else {
976 tcg_gen_movi_i32(t0, 0);
977 }
978 if (compute_ov) {
979 tcg_gen_movi_tl(cpu_ov, 1);
980 tcg_gen_movi_tl(cpu_so, 1);
981 }
982 gen_set_label(l2);
983 tcg_gen_extu_i32_tl(ret, t0);
984 tcg_temp_free_i32(t0);
985 tcg_temp_free_i32(t1);
986 if (unlikely(Rc(ctx->opcode) != 0))
987 gen_set_Rc0(ctx, ret);
988 }
989 /* Div functions */
990 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
991 static void glue(gen_, name)(DisasContext *ctx) \
992 { \
993 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
994 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
995 sign, compute_ov); \
996 }
997 /* divwu divwu. divwuo divwuo. */
998 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
999 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1000 /* divw divw. divwo divwo. */
1001 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1002 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1003
1004 /* div[wd]eu[o][.] */
1005 #define GEN_DIVE(name, hlpr, compute_ov) \
1006 static void gen_##name(DisasContext *ctx) \
1007 { \
1008 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1009 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1010 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1011 tcg_temp_free_i32(t0); \
1012 if (unlikely(Rc(ctx->opcode) != 0)) { \
1013 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1014 } \
1015 }
1016
1017 GEN_DIVE(divweu, divweu, 0);
1018 GEN_DIVE(divweuo, divweu, 1);
1019 GEN_DIVE(divwe, divwe, 0);
1020 GEN_DIVE(divweo, divwe, 1);
1021
1022 #if defined(TARGET_PPC64)
1023 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1024 TCGv arg2, int sign, int compute_ov)
1025 {
1026 int l1 = gen_new_label();
1027 int l2 = gen_new_label();
1028
1029 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1030 if (sign) {
1031 int l3 = gen_new_label();
1032 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1033 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1034 gen_set_label(l3);
1035 tcg_gen_div_i64(ret, arg1, arg2);
1036 } else {
1037 tcg_gen_divu_i64(ret, arg1, arg2);
1038 }
1039 if (compute_ov) {
1040 tcg_gen_movi_tl(cpu_ov, 0);
1041 }
1042 tcg_gen_br(l2);
1043 gen_set_label(l1);
1044 if (sign) {
1045 tcg_gen_sari_i64(ret, arg1, 63);
1046 } else {
1047 tcg_gen_movi_i64(ret, 0);
1048 }
1049 if (compute_ov) {
1050 tcg_gen_movi_tl(cpu_ov, 1);
1051 tcg_gen_movi_tl(cpu_so, 1);
1052 }
1053 gen_set_label(l2);
1054 if (unlikely(Rc(ctx->opcode) != 0))
1055 gen_set_Rc0(ctx, ret);
1056 }
1057 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1058 static void glue(gen_, name)(DisasContext *ctx) \
1059 { \
1060 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1061 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1062 sign, compute_ov); \
1063 }
1064 /* divwu divwu. divwuo divwuo. */
1065 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1066 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1067 /* divw divw. divwo divwo. */
1068 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1069 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1070
1071 GEN_DIVE(divdeu, divdeu, 0);
1072 GEN_DIVE(divdeuo, divdeu, 1);
1073 GEN_DIVE(divde, divde, 0);
1074 GEN_DIVE(divdeo, divde, 1);
1075 #endif
1076
1077 /* mulhw mulhw. */
1078 static void gen_mulhw(DisasContext *ctx)
1079 {
1080 TCGv_i32 t0 = tcg_temp_new_i32();
1081 TCGv_i32 t1 = tcg_temp_new_i32();
1082
1083 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1084 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1085 tcg_gen_muls2_i32(t0, t1, t0, t1);
1086 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1087 tcg_temp_free_i32(t0);
1088 tcg_temp_free_i32(t1);
1089 if (unlikely(Rc(ctx->opcode) != 0))
1090 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1091 }
1092
1093 /* mulhwu mulhwu. */
1094 static void gen_mulhwu(DisasContext *ctx)
1095 {
1096 TCGv_i32 t0 = tcg_temp_new_i32();
1097 TCGv_i32 t1 = tcg_temp_new_i32();
1098
1099 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1100 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1101 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1102 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1103 tcg_temp_free_i32(t0);
1104 tcg_temp_free_i32(t1);
1105 if (unlikely(Rc(ctx->opcode) != 0))
1106 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1107 }
1108
1109 /* mullw mullw. */
1110 static void gen_mullw(DisasContext *ctx)
1111 {
1112 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1113 cpu_gpr[rB(ctx->opcode)]);
1114 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1115 if (unlikely(Rc(ctx->opcode) != 0))
1116 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1117 }
1118
1119 /* mullwo mullwo. */
1120 static void gen_mullwo(DisasContext *ctx)
1121 {
1122 TCGv_i32 t0 = tcg_temp_new_i32();
1123 TCGv_i32 t1 = tcg_temp_new_i32();
1124
1125 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1126 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1127 tcg_gen_muls2_i32(t0, t1, t0, t1);
1128 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1129
1130 tcg_gen_sari_i32(t0, t0, 31);
1131 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1132 tcg_gen_extu_i32_tl(cpu_ov, t0);
1133 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1134
1135 tcg_temp_free_i32(t0);
1136 tcg_temp_free_i32(t1);
1137 if (unlikely(Rc(ctx->opcode) != 0))
1138 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1139 }
1140
1141 /* mulli */
1142 static void gen_mulli(DisasContext *ctx)
1143 {
1144 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1145 SIMM(ctx->opcode));
1146 }
1147
1148 #if defined(TARGET_PPC64)
1149 /* mulhd mulhd. */
1150 static void gen_mulhd(DisasContext *ctx)
1151 {
1152 TCGv lo = tcg_temp_new();
1153 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1154 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1155 tcg_temp_free(lo);
1156 if (unlikely(Rc(ctx->opcode) != 0)) {
1157 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1158 }
1159 }
1160
1161 /* mulhdu mulhdu. */
1162 static void gen_mulhdu(DisasContext *ctx)
1163 {
1164 TCGv lo = tcg_temp_new();
1165 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1166 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1167 tcg_temp_free(lo);
1168 if (unlikely(Rc(ctx->opcode) != 0)) {
1169 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1170 }
1171 }
1172
1173 /* mulld mulld. */
1174 static void gen_mulld(DisasContext *ctx)
1175 {
1176 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1177 cpu_gpr[rB(ctx->opcode)]);
1178 if (unlikely(Rc(ctx->opcode) != 0))
1179 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1180 }
1181
1182 /* mulldo mulldo. */
1183 static void gen_mulldo(DisasContext *ctx)
1184 {
1185 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1186 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1187 if (unlikely(Rc(ctx->opcode) != 0)) {
1188 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1189 }
1190 }
1191 #endif
1192
1193 /* Common subf function */
1194 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1195 TCGv arg2, bool add_ca, bool compute_ca,
1196 bool compute_ov, bool compute_rc0)
1197 {
1198 TCGv t0 = ret;
1199
1200 if (compute_ca || compute_ov) {
1201 t0 = tcg_temp_new();
1202 }
1203
1204 if (compute_ca) {
1205 /* dest = ~arg1 + arg2 [+ ca]. */
1206 if (NARROW_MODE(ctx)) {
1207 /* Caution: a non-obvious corner case of the spec is that we
1208 must produce the *entire* 64-bit addition, but produce the
1209 carry into bit 32. */
1210 TCGv inv1 = tcg_temp_new();
1211 TCGv t1 = tcg_temp_new();
1212 tcg_gen_not_tl(inv1, arg1);
1213 if (add_ca) {
1214 tcg_gen_add_tl(t0, arg2, cpu_ca);
1215 } else {
1216 tcg_gen_addi_tl(t0, arg2, 1);
1217 }
1218 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1219 tcg_gen_add_tl(t0, t0, inv1);
1220 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1221 tcg_temp_free(t1);
1222 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1223 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1224 } else if (add_ca) {
1225 TCGv zero, inv1 = tcg_temp_new();
1226 tcg_gen_not_tl(inv1, arg1);
1227 zero = tcg_const_tl(0);
1228 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1229 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1230 tcg_temp_free(zero);
1231 tcg_temp_free(inv1);
1232 } else {
1233 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1234 tcg_gen_sub_tl(t0, arg2, arg1);
1235 }
1236 } else if (add_ca) {
1237 /* Since we're ignoring carry-out, we can simplify the
1238 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1239 tcg_gen_sub_tl(t0, arg2, arg1);
1240 tcg_gen_add_tl(t0, t0, cpu_ca);
1241 tcg_gen_subi_tl(t0, t0, 1);
1242 } else {
1243 tcg_gen_sub_tl(t0, arg2, arg1);
1244 }
1245
1246 if (compute_ov) {
1247 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1248 }
1249 if (unlikely(compute_rc0)) {
1250 gen_set_Rc0(ctx, t0);
1251 }
1252
1253 if (!TCGV_EQUAL(t0, ret)) {
1254 tcg_gen_mov_tl(ret, t0);
1255 tcg_temp_free(t0);
1256 }
1257 }
1258 /* Sub functions with Two operands functions */
1259 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1260 static void glue(gen_, name)(DisasContext *ctx) \
1261 { \
1262 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1263 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1264 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1265 }
1266 /* Sub functions with one operand and one immediate */
1267 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1268 add_ca, compute_ca, compute_ov) \
1269 static void glue(gen_, name)(DisasContext *ctx) \
1270 { \
1271 TCGv t0 = tcg_const_tl(const_val); \
1272 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1273 cpu_gpr[rA(ctx->opcode)], t0, \
1274 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1275 tcg_temp_free(t0); \
1276 }
1277 /* subf subf. subfo subfo. */
1278 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1279 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1280 /* subfc subfc. subfco subfco. */
1281 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1282 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1283 /* subfe subfe. subfeo subfo. */
1284 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1285 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1286 /* subfme subfme. subfmeo subfmeo. */
1287 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1288 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1289 /* subfze subfze. subfzeo subfzeo.*/
1290 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1291 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1292
1293 /* subfic */
1294 static void gen_subfic(DisasContext *ctx)
1295 {
1296 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1297 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1298 c, 0, 1, 0, 0);
1299 tcg_temp_free(c);
1300 }
1301
1302 /* neg neg. nego nego. */
1303 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1304 {
1305 TCGv zero = tcg_const_tl(0);
1306 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1307 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1308 tcg_temp_free(zero);
1309 }
1310
1311 static void gen_neg(DisasContext *ctx)
1312 {
1313 gen_op_arith_neg(ctx, 0);
1314 }
1315
1316 static void gen_nego(DisasContext *ctx)
1317 {
1318 gen_op_arith_neg(ctx, 1);
1319 }
1320
1321 /*** Integer logical ***/
1322 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1323 static void glue(gen_, name)(DisasContext *ctx) \
1324 { \
1325 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1326 cpu_gpr[rB(ctx->opcode)]); \
1327 if (unlikely(Rc(ctx->opcode) != 0)) \
1328 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1329 }
1330
1331 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1332 static void glue(gen_, name)(DisasContext *ctx) \
1333 { \
1334 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1335 if (unlikely(Rc(ctx->opcode) != 0)) \
1336 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1337 }
1338
1339 /* and & and. */
1340 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1341 /* andc & andc. */
1342 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1343
1344 /* andi. */
1345 static void gen_andi_(DisasContext *ctx)
1346 {
1347 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1348 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1349 }
1350
1351 /* andis. */
1352 static void gen_andis_(DisasContext *ctx)
1353 {
1354 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1355 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1356 }
1357
1358 /* cntlzw */
1359 static void gen_cntlzw(DisasContext *ctx)
1360 {
1361 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1362 if (unlikely(Rc(ctx->opcode) != 0))
1363 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1364 }
1365 /* eqv & eqv. */
1366 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1367 /* extsb & extsb. */
1368 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1369 /* extsh & extsh. */
1370 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1371 /* nand & nand. */
1372 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1373 /* nor & nor. */
1374 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1375
1376 /* or & or. */
1377 static void gen_or(DisasContext *ctx)
1378 {
1379 int rs, ra, rb;
1380
1381 rs = rS(ctx->opcode);
1382 ra = rA(ctx->opcode);
1383 rb = rB(ctx->opcode);
1384 /* Optimisation for mr. ri case */
1385 if (rs != ra || rs != rb) {
1386 if (rs != rb)
1387 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1388 else
1389 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1390 if (unlikely(Rc(ctx->opcode) != 0))
1391 gen_set_Rc0(ctx, cpu_gpr[ra]);
1392 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1393 gen_set_Rc0(ctx, cpu_gpr[rs]);
1394 #if defined(TARGET_PPC64)
1395 } else {
1396 int prio = 0;
1397
1398 switch (rs) {
1399 case 1:
1400 /* Set process priority to low */
1401 prio = 2;
1402 break;
1403 case 6:
1404 /* Set process priority to medium-low */
1405 prio = 3;
1406 break;
1407 case 2:
1408 /* Set process priority to normal */
1409 prio = 4;
1410 break;
1411 #if !defined(CONFIG_USER_ONLY)
1412 case 31:
1413 if (ctx->mem_idx > 0) {
1414 /* Set process priority to very low */
1415 prio = 1;
1416 }
1417 break;
1418 case 5:
1419 if (ctx->mem_idx > 0) {
1420 /* Set process priority to medium-hight */
1421 prio = 5;
1422 }
1423 break;
1424 case 3:
1425 if (ctx->mem_idx > 0) {
1426 /* Set process priority to high */
1427 prio = 6;
1428 }
1429 break;
1430 case 7:
1431 if (ctx->mem_idx > 1) {
1432 /* Set process priority to very high */
1433 prio = 7;
1434 }
1435 break;
1436 #endif
1437 default:
1438 /* nop */
1439 break;
1440 }
1441 if (prio) {
1442 TCGv t0 = tcg_temp_new();
1443 gen_load_spr(t0, SPR_PPR);
1444 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1445 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1446 gen_store_spr(SPR_PPR, t0);
1447 tcg_temp_free(t0);
1448 }
1449 #endif
1450 }
1451 }
1452 /* orc & orc. */
1453 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1454
1455 /* xor & xor. */
1456 static void gen_xor(DisasContext *ctx)
1457 {
1458 /* Optimisation for "set to zero" case */
1459 if (rS(ctx->opcode) != rB(ctx->opcode))
1460 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1461 else
1462 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1463 if (unlikely(Rc(ctx->opcode) != 0))
1464 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1465 }
1466
1467 /* ori */
1468 static void gen_ori(DisasContext *ctx)
1469 {
1470 target_ulong uimm = UIMM(ctx->opcode);
1471
1472 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1473 /* NOP */
1474 /* XXX: should handle special NOPs for POWER series */
1475 return;
1476 }
1477 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1478 }
1479
1480 /* oris */
1481 static void gen_oris(DisasContext *ctx)
1482 {
1483 target_ulong uimm = UIMM(ctx->opcode);
1484
1485 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1486 /* NOP */
1487 return;
1488 }
1489 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1490 }
1491
1492 /* xori */
1493 static void gen_xori(DisasContext *ctx)
1494 {
1495 target_ulong uimm = UIMM(ctx->opcode);
1496
1497 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1498 /* NOP */
1499 return;
1500 }
1501 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1502 }
1503
1504 /* xoris */
1505 static void gen_xoris(DisasContext *ctx)
1506 {
1507 target_ulong uimm = UIMM(ctx->opcode);
1508
1509 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1510 /* NOP */
1511 return;
1512 }
1513 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1514 }
1515
1516 /* popcntb : PowerPC 2.03 specification */
1517 static void gen_popcntb(DisasContext *ctx)
1518 {
1519 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1520 }
1521
1522 static void gen_popcntw(DisasContext *ctx)
1523 {
1524 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1525 }
1526
1527 #if defined(TARGET_PPC64)
1528 /* popcntd: PowerPC 2.06 specification */
1529 static void gen_popcntd(DisasContext *ctx)
1530 {
1531 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1532 }
1533 #endif
1534
1535 /* prtyw: PowerPC 2.05 specification */
1536 static void gen_prtyw(DisasContext *ctx)
1537 {
1538 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1539 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1540 TCGv t0 = tcg_temp_new();
1541 tcg_gen_shri_tl(t0, rs, 16);
1542 tcg_gen_xor_tl(ra, rs, t0);
1543 tcg_gen_shri_tl(t0, ra, 8);
1544 tcg_gen_xor_tl(ra, ra, t0);
1545 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1546 tcg_temp_free(t0);
1547 }
1548
1549 #if defined(TARGET_PPC64)
1550 /* prtyd: PowerPC 2.05 specification */
1551 static void gen_prtyd(DisasContext *ctx)
1552 {
1553 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1554 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1555 TCGv t0 = tcg_temp_new();
1556 tcg_gen_shri_tl(t0, rs, 32);
1557 tcg_gen_xor_tl(ra, rs, t0);
1558 tcg_gen_shri_tl(t0, ra, 16);
1559 tcg_gen_xor_tl(ra, ra, t0);
1560 tcg_gen_shri_tl(t0, ra, 8);
1561 tcg_gen_xor_tl(ra, ra, t0);
1562 tcg_gen_andi_tl(ra, ra, 1);
1563 tcg_temp_free(t0);
1564 }
1565 #endif
1566
1567 #if defined(TARGET_PPC64)
1568 /* bpermd */
1569 static void gen_bpermd(DisasContext *ctx)
1570 {
1571 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1572 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1573 }
1574 #endif
1575
1576 #if defined(TARGET_PPC64)
1577 /* extsw & extsw. */
1578 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1579
1580 /* cntlzd */
1581 static void gen_cntlzd(DisasContext *ctx)
1582 {
1583 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1584 if (unlikely(Rc(ctx->opcode) != 0))
1585 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1586 }
1587 #endif
1588
1589 /*** Integer rotate ***/
1590
1591 /* rlwimi & rlwimi. */
1592 static void gen_rlwimi(DisasContext *ctx)
1593 {
1594 uint32_t mb, me, sh;
1595
1596 mb = MB(ctx->opcode);
1597 me = ME(ctx->opcode);
1598 sh = SH(ctx->opcode);
1599 if (likely(sh == 0 && mb == 0 && me == 31)) {
1600 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1601 } else {
1602 target_ulong mask;
1603 TCGv t1;
1604 TCGv t0 = tcg_temp_new();
1605 #if defined(TARGET_PPC64)
1606 TCGv_i32 t2 = tcg_temp_new_i32();
1607 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1608 tcg_gen_rotli_i32(t2, t2, sh);
1609 tcg_gen_extu_i32_i64(t0, t2);
1610 tcg_temp_free_i32(t2);
1611 #else
1612 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1613 #endif
1614 #if defined(TARGET_PPC64)
1615 mb += 32;
1616 me += 32;
1617 #endif
1618 mask = MASK(mb, me);
1619 t1 = tcg_temp_new();
1620 tcg_gen_andi_tl(t0, t0, mask);
1621 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1622 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1623 tcg_temp_free(t0);
1624 tcg_temp_free(t1);
1625 }
1626 if (unlikely(Rc(ctx->opcode) != 0))
1627 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1628 }
1629
1630 /* rlwinm & rlwinm. */
1631 static void gen_rlwinm(DisasContext *ctx)
1632 {
1633 uint32_t mb, me, sh;
1634
1635 sh = SH(ctx->opcode);
1636 mb = MB(ctx->opcode);
1637 me = ME(ctx->opcode);
1638
1639 if (likely(mb == 0 && me == (31 - sh))) {
1640 if (likely(sh == 0)) {
1641 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1642 } else {
1643 TCGv t0 = tcg_temp_new();
1644 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1645 tcg_gen_shli_tl(t0, t0, sh);
1646 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1647 tcg_temp_free(t0);
1648 }
1649 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1650 TCGv t0 = tcg_temp_new();
1651 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1652 tcg_gen_shri_tl(t0, t0, mb);
1653 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1654 tcg_temp_free(t0);
1655 } else {
1656 TCGv t0 = tcg_temp_new();
1657 #if defined(TARGET_PPC64)
1658 TCGv_i32 t1 = tcg_temp_new_i32();
1659 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1660 tcg_gen_rotli_i32(t1, t1, sh);
1661 tcg_gen_extu_i32_i64(t0, t1);
1662 tcg_temp_free_i32(t1);
1663 #else
1664 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1665 #endif
1666 #if defined(TARGET_PPC64)
1667 mb += 32;
1668 me += 32;
1669 #endif
1670 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1671 tcg_temp_free(t0);
1672 }
1673 if (unlikely(Rc(ctx->opcode) != 0))
1674 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1675 }
1676
1677 /* rlwnm & rlwnm. */
1678 static void gen_rlwnm(DisasContext *ctx)
1679 {
1680 uint32_t mb, me;
1681 TCGv t0;
1682 #if defined(TARGET_PPC64)
1683 TCGv_i32 t1, t2;
1684 #endif
1685
1686 mb = MB(ctx->opcode);
1687 me = ME(ctx->opcode);
1688 t0 = tcg_temp_new();
1689 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1690 #if defined(TARGET_PPC64)
1691 t1 = tcg_temp_new_i32();
1692 t2 = tcg_temp_new_i32();
1693 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1694 tcg_gen_trunc_i64_i32(t2, t0);
1695 tcg_gen_rotl_i32(t1, t1, t2);
1696 tcg_gen_extu_i32_i64(t0, t1);
1697 tcg_temp_free_i32(t1);
1698 tcg_temp_free_i32(t2);
1699 #else
1700 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1701 #endif
1702 if (unlikely(mb != 0 || me != 31)) {
1703 #if defined(TARGET_PPC64)
1704 mb += 32;
1705 me += 32;
1706 #endif
1707 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1708 } else {
1709 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1710 }
1711 tcg_temp_free(t0);
1712 if (unlikely(Rc(ctx->opcode) != 0))
1713 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1714 }
1715
1716 #if defined(TARGET_PPC64)
1717 #define GEN_PPC64_R2(name, opc1, opc2) \
1718 static void glue(gen_, name##0)(DisasContext *ctx) \
1719 { \
1720 gen_##name(ctx, 0); \
1721 } \
1722 \
1723 static void glue(gen_, name##1)(DisasContext *ctx) \
1724 { \
1725 gen_##name(ctx, 1); \
1726 }
1727 #define GEN_PPC64_R4(name, opc1, opc2) \
1728 static void glue(gen_, name##0)(DisasContext *ctx) \
1729 { \
1730 gen_##name(ctx, 0, 0); \
1731 } \
1732 \
1733 static void glue(gen_, name##1)(DisasContext *ctx) \
1734 { \
1735 gen_##name(ctx, 0, 1); \
1736 } \
1737 \
1738 static void glue(gen_, name##2)(DisasContext *ctx) \
1739 { \
1740 gen_##name(ctx, 1, 0); \
1741 } \
1742 \
1743 static void glue(gen_, name##3)(DisasContext *ctx) \
1744 { \
1745 gen_##name(ctx, 1, 1); \
1746 }
1747
1748 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1749 uint32_t sh)
1750 {
1751 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1752 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1753 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1754 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1755 } else {
1756 TCGv t0 = tcg_temp_new();
1757 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1758 if (likely(mb == 0 && me == 63)) {
1759 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1760 } else {
1761 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1762 }
1763 tcg_temp_free(t0);
1764 }
1765 if (unlikely(Rc(ctx->opcode) != 0))
1766 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1767 }
1768 /* rldicl - rldicl. */
1769 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1770 {
1771 uint32_t sh, mb;
1772
1773 sh = SH(ctx->opcode) | (shn << 5);
1774 mb = MB(ctx->opcode) | (mbn << 5);
1775 gen_rldinm(ctx, mb, 63, sh);
1776 }
1777 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1778 /* rldicr - rldicr. */
1779 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1780 {
1781 uint32_t sh, me;
1782
1783 sh = SH(ctx->opcode) | (shn << 5);
1784 me = MB(ctx->opcode) | (men << 5);
1785 gen_rldinm(ctx, 0, me, sh);
1786 }
1787 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1788 /* rldic - rldic. */
1789 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1790 {
1791 uint32_t sh, mb;
1792
1793 sh = SH(ctx->opcode) | (shn << 5);
1794 mb = MB(ctx->opcode) | (mbn << 5);
1795 gen_rldinm(ctx, mb, 63 - sh, sh);
1796 }
1797 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1798
1799 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1800 {
1801 TCGv t0;
1802
1803 t0 = tcg_temp_new();
1804 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1805 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1806 if (unlikely(mb != 0 || me != 63)) {
1807 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1808 } else {
1809 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1810 }
1811 tcg_temp_free(t0);
1812 if (unlikely(Rc(ctx->opcode) != 0))
1813 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1814 }
1815
1816 /* rldcl - rldcl. */
1817 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1818 {
1819 uint32_t mb;
1820
1821 mb = MB(ctx->opcode) | (mbn << 5);
1822 gen_rldnm(ctx, mb, 63);
1823 }
1824 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1825 /* rldcr - rldcr. */
1826 static inline void gen_rldcr(DisasContext *ctx, int men)
1827 {
1828 uint32_t me;
1829
1830 me = MB(ctx->opcode) | (men << 5);
1831 gen_rldnm(ctx, 0, me);
1832 }
1833 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1834 /* rldimi - rldimi. */
1835 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1836 {
1837 uint32_t sh, mb, me;
1838
1839 sh = SH(ctx->opcode) | (shn << 5);
1840 mb = MB(ctx->opcode) | (mbn << 5);
1841 me = 63 - sh;
1842 if (unlikely(sh == 0 && mb == 0)) {
1843 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1844 } else {
1845 TCGv t0, t1;
1846 target_ulong mask;
1847
1848 t0 = tcg_temp_new();
1849 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1850 t1 = tcg_temp_new();
1851 mask = MASK(mb, me);
1852 tcg_gen_andi_tl(t0, t0, mask);
1853 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1854 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1855 tcg_temp_free(t0);
1856 tcg_temp_free(t1);
1857 }
1858 if (unlikely(Rc(ctx->opcode) != 0))
1859 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1860 }
1861 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1862 #endif
1863
1864 /*** Integer shift ***/
1865
1866 /* slw & slw. */
1867 static void gen_slw(DisasContext *ctx)
1868 {
1869 TCGv t0, t1;
1870
1871 t0 = tcg_temp_new();
1872 /* AND rS with a mask that is 0 when rB >= 0x20 */
1873 #if defined(TARGET_PPC64)
1874 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1875 tcg_gen_sari_tl(t0, t0, 0x3f);
1876 #else
1877 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1878 tcg_gen_sari_tl(t0, t0, 0x1f);
1879 #endif
1880 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1881 t1 = tcg_temp_new();
1882 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1883 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1884 tcg_temp_free(t1);
1885 tcg_temp_free(t0);
1886 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1887 if (unlikely(Rc(ctx->opcode) != 0))
1888 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1889 }
1890
1891 /* sraw & sraw. */
1892 static void gen_sraw(DisasContext *ctx)
1893 {
1894 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1895 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1896 if (unlikely(Rc(ctx->opcode) != 0))
1897 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1898 }
1899
1900 /* srawi & srawi. */
1901 static void gen_srawi(DisasContext *ctx)
1902 {
1903 int sh = SH(ctx->opcode);
1904 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1905 TCGv src = cpu_gpr[rS(ctx->opcode)];
1906 if (sh == 0) {
1907 tcg_gen_mov_tl(dst, src);
1908 tcg_gen_movi_tl(cpu_ca, 0);
1909 } else {
1910 TCGv t0;
1911 tcg_gen_ext32s_tl(dst, src);
1912 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1913 t0 = tcg_temp_new();
1914 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1915 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1916 tcg_temp_free(t0);
1917 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1918 tcg_gen_sari_tl(dst, dst, sh);
1919 }
1920 if (unlikely(Rc(ctx->opcode) != 0)) {
1921 gen_set_Rc0(ctx, dst);
1922 }
1923 }
1924
1925 /* srw & srw. */
1926 static void gen_srw(DisasContext *ctx)
1927 {
1928 TCGv t0, t1;
1929
1930 t0 = tcg_temp_new();
1931 /* AND rS with a mask that is 0 when rB >= 0x20 */
1932 #if defined(TARGET_PPC64)
1933 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1934 tcg_gen_sari_tl(t0, t0, 0x3f);
1935 #else
1936 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1937 tcg_gen_sari_tl(t0, t0, 0x1f);
1938 #endif
1939 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1940 tcg_gen_ext32u_tl(t0, t0);
1941 t1 = tcg_temp_new();
1942 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1943 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1944 tcg_temp_free(t1);
1945 tcg_temp_free(t0);
1946 if (unlikely(Rc(ctx->opcode) != 0))
1947 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1948 }
1949
1950 #if defined(TARGET_PPC64)
1951 /* sld & sld. */
1952 static void gen_sld(DisasContext *ctx)
1953 {
1954 TCGv t0, t1;
1955
1956 t0 = tcg_temp_new();
1957 /* AND rS with a mask that is 0 when rB >= 0x40 */
1958 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1959 tcg_gen_sari_tl(t0, t0, 0x3f);
1960 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1961 t1 = tcg_temp_new();
1962 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1963 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1964 tcg_temp_free(t1);
1965 tcg_temp_free(t0);
1966 if (unlikely(Rc(ctx->opcode) != 0))
1967 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1968 }
1969
1970 /* srad & srad. */
1971 static void gen_srad(DisasContext *ctx)
1972 {
1973 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1974 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1975 if (unlikely(Rc(ctx->opcode) != 0))
1976 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1977 }
1978 /* sradi & sradi. */
1979 static inline void gen_sradi(DisasContext *ctx, int n)
1980 {
1981 int sh = SH(ctx->opcode) + (n << 5);
1982 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1983 TCGv src = cpu_gpr[rS(ctx->opcode)];
1984 if (sh == 0) {
1985 tcg_gen_mov_tl(dst, src);
1986 tcg_gen_movi_tl(cpu_ca, 0);
1987 } else {
1988 TCGv t0;
1989 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1990 t0 = tcg_temp_new();
1991 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1992 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1993 tcg_temp_free(t0);
1994 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1995 tcg_gen_sari_tl(dst, src, sh);
1996 }
1997 if (unlikely(Rc(ctx->opcode) != 0)) {
1998 gen_set_Rc0(ctx, dst);
1999 }
2000 }
2001
2002 static void gen_sradi0(DisasContext *ctx)
2003 {
2004 gen_sradi(ctx, 0);
2005 }
2006
2007 static void gen_sradi1(DisasContext *ctx)
2008 {
2009 gen_sradi(ctx, 1);
2010 }
2011
2012 /* srd & srd. */
2013 static void gen_srd(DisasContext *ctx)
2014 {
2015 TCGv t0, t1;
2016
2017 t0 = tcg_temp_new();
2018 /* AND rS with a mask that is 0 when rB >= 0x40 */
2019 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2020 tcg_gen_sari_tl(t0, t0, 0x3f);
2021 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2022 t1 = tcg_temp_new();
2023 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2024 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2025 tcg_temp_free(t1);
2026 tcg_temp_free(t0);
2027 if (unlikely(Rc(ctx->opcode) != 0))
2028 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2029 }
2030 #endif
2031
2032 /*** Floating-Point arithmetic ***/
2033 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2034 static void gen_f##name(DisasContext *ctx) \
2035 { \
2036 if (unlikely(!ctx->fpu_enabled)) { \
2037 gen_exception(ctx, POWERPC_EXCP_FPU); \
2038 return; \
2039 } \
2040 /* NIP cannot be restored if the memory exception comes from an helper */ \
2041 gen_update_nip(ctx, ctx->nip - 4); \
2042 gen_reset_fpstatus(); \
2043 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2044 cpu_fpr[rA(ctx->opcode)], \
2045 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2046 if (isfloat) { \
2047 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2048 cpu_fpr[rD(ctx->opcode)]); \
2049 } \
2050 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2051 Rc(ctx->opcode) != 0); \
2052 }
2053
2054 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2055 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2056 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2057
2058 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2059 static void gen_f##name(DisasContext *ctx) \
2060 { \
2061 if (unlikely(!ctx->fpu_enabled)) { \
2062 gen_exception(ctx, POWERPC_EXCP_FPU); \
2063 return; \
2064 } \
2065 /* NIP cannot be restored if the memory exception comes from an helper */ \
2066 gen_update_nip(ctx, ctx->nip - 4); \
2067 gen_reset_fpstatus(); \
2068 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2069 cpu_fpr[rA(ctx->opcode)], \
2070 cpu_fpr[rB(ctx->opcode)]); \
2071 if (isfloat) { \
2072 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2073 cpu_fpr[rD(ctx->opcode)]); \
2074 } \
2075 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2076 set_fprf, Rc(ctx->opcode) != 0); \
2077 }
2078 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2079 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2080 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2081
2082 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2083 static void gen_f##name(DisasContext *ctx) \
2084 { \
2085 if (unlikely(!ctx->fpu_enabled)) { \
2086 gen_exception(ctx, POWERPC_EXCP_FPU); \
2087 return; \
2088 } \
2089 /* NIP cannot be restored if the memory exception comes from an helper */ \
2090 gen_update_nip(ctx, ctx->nip - 4); \
2091 gen_reset_fpstatus(); \
2092 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2093 cpu_fpr[rA(ctx->opcode)], \
2094 cpu_fpr[rC(ctx->opcode)]); \
2095 if (isfloat) { \
2096 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2097 cpu_fpr[rD(ctx->opcode)]); \
2098 } \
2099 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2100 set_fprf, Rc(ctx->opcode) != 0); \
2101 }
2102 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2103 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2104 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2105
2106 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2107 static void gen_f##name(DisasContext *ctx) \
2108 { \
2109 if (unlikely(!ctx->fpu_enabled)) { \
2110 gen_exception(ctx, POWERPC_EXCP_FPU); \
2111 return; \
2112 } \
2113 /* NIP cannot be restored if the memory exception comes from an helper */ \
2114 gen_update_nip(ctx, ctx->nip - 4); \
2115 gen_reset_fpstatus(); \
2116 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2117 cpu_fpr[rB(ctx->opcode)]); \
2118 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2119 set_fprf, Rc(ctx->opcode) != 0); \
2120 }
2121
2122 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2123 static void gen_f##name(DisasContext *ctx) \
2124 { \
2125 if (unlikely(!ctx->fpu_enabled)) { \
2126 gen_exception(ctx, POWERPC_EXCP_FPU); \
2127 return; \
2128 } \
2129 /* NIP cannot be restored if the memory exception comes from an helper */ \
2130 gen_update_nip(ctx, ctx->nip - 4); \
2131 gen_reset_fpstatus(); \
2132 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2133 cpu_fpr[rB(ctx->opcode)]); \
2134 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2135 set_fprf, Rc(ctx->opcode) != 0); \
2136 }
2137
2138 /* fadd - fadds */
2139 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2140 /* fdiv - fdivs */
2141 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2142 /* fmul - fmuls */
2143 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2144
2145 /* fre */
2146 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2147
2148 /* fres */
2149 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2150
2151 /* frsqrte */
2152 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2153
2154 /* frsqrtes */
2155 static void gen_frsqrtes(DisasContext *ctx)
2156 {
2157 if (unlikely(!ctx->fpu_enabled)) {
2158 gen_exception(ctx, POWERPC_EXCP_FPU);
2159 return;
2160 }
2161 /* NIP cannot be restored if the memory exception comes from an helper */
2162 gen_update_nip(ctx, ctx->nip - 4);
2163 gen_reset_fpstatus();
2164 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2165 cpu_fpr[rB(ctx->opcode)]);
2166 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2167 cpu_fpr[rD(ctx->opcode)]);
2168 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2169 }
2170
2171 /* fsel */
2172 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2173 /* fsub - fsubs */
2174 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2175 /* Optional: */
2176
2177 /* fsqrt */
2178 static void gen_fsqrt(DisasContext *ctx)
2179 {
2180 if (unlikely(!ctx->fpu_enabled)) {
2181 gen_exception(ctx, POWERPC_EXCP_FPU);
2182 return;
2183 }
2184 /* NIP cannot be restored if the memory exception comes from an helper */
2185 gen_update_nip(ctx, ctx->nip - 4);
2186 gen_reset_fpstatus();
2187 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2188 cpu_fpr[rB(ctx->opcode)]);
2189 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2190 }
2191
2192 static void gen_fsqrts(DisasContext *ctx)
2193 {
2194 if (unlikely(!ctx->fpu_enabled)) {
2195 gen_exception(ctx, POWERPC_EXCP_FPU);
2196 return;
2197 }
2198 /* NIP cannot be restored if the memory exception comes from an helper */
2199 gen_update_nip(ctx, ctx->nip - 4);
2200 gen_reset_fpstatus();
2201 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2202 cpu_fpr[rB(ctx->opcode)]);
2203 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2204 cpu_fpr[rD(ctx->opcode)]);
2205 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2206 }
2207
2208 /*** Floating-Point multiply-and-add ***/
2209 /* fmadd - fmadds */
2210 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2211 /* fmsub - fmsubs */
2212 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2213 /* fnmadd - fnmadds */
2214 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2215 /* fnmsub - fnmsubs */
2216 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2217
2218 /*** Floating-Point round & convert ***/
2219 /* fctiw */
2220 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2221 /* fctiwu */
2222 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2223 /* fctiwz */
2224 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2225 /* fctiwuz */
2226 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2227 /* frsp */
2228 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2229 #if defined(TARGET_PPC64)
2230 /* fcfid */
2231 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2232 /* fcfids */
2233 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2234 /* fcfidu */
2235 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2236 /* fcfidus */
2237 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2238 /* fctid */
2239 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2240 /* fctidu */
2241 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2242 /* fctidz */
2243 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2244 /* fctidu */
2245 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2246 #endif
2247
2248 /* frin */
2249 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2250 /* friz */
2251 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2252 /* frip */
2253 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2254 /* frim */
2255 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2256
2257 static void gen_ftdiv(DisasContext *ctx)
2258 {
2259 if (unlikely(!ctx->fpu_enabled)) {
2260 gen_exception(ctx, POWERPC_EXCP_FPU);
2261 return;
2262 }
2263 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2264 cpu_fpr[rB(ctx->opcode)]);
2265 }
2266
2267 static void gen_ftsqrt(DisasContext *ctx)
2268 {
2269 if (unlikely(!ctx->fpu_enabled)) {
2270 gen_exception(ctx, POWERPC_EXCP_FPU);
2271 return;
2272 }
2273 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2274 }
2275
2276
2277
2278 /*** Floating-Point compare ***/
2279
2280 /* fcmpo */
2281 static void gen_fcmpo(DisasContext *ctx)
2282 {
2283 TCGv_i32 crf;
2284 if (unlikely(!ctx->fpu_enabled)) {
2285 gen_exception(ctx, POWERPC_EXCP_FPU);
2286 return;
2287 }
2288 /* NIP cannot be restored if the memory exception comes from an helper */
2289 gen_update_nip(ctx, ctx->nip - 4);
2290 gen_reset_fpstatus();
2291 crf = tcg_const_i32(crfD(ctx->opcode));
2292 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2293 cpu_fpr[rB(ctx->opcode)], crf);
2294 tcg_temp_free_i32(crf);
2295 gen_helper_float_check_status(cpu_env);
2296 }
2297
2298 /* fcmpu */
2299 static void gen_fcmpu(DisasContext *ctx)
2300 {
2301 TCGv_i32 crf;
2302 if (unlikely(!ctx->fpu_enabled)) {
2303 gen_exception(ctx, POWERPC_EXCP_FPU);
2304 return;
2305 }
2306 /* NIP cannot be restored if the memory exception comes from an helper */
2307 gen_update_nip(ctx, ctx->nip - 4);
2308 gen_reset_fpstatus();
2309 crf = tcg_const_i32(crfD(ctx->opcode));
2310 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2311 cpu_fpr[rB(ctx->opcode)], crf);
2312 tcg_temp_free_i32(crf);
2313 gen_helper_float_check_status(cpu_env);
2314 }
2315
2316 /*** Floating-point move ***/
2317 /* fabs */
2318 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2319 static void gen_fabs(DisasContext *ctx)
2320 {
2321 if (unlikely(!ctx->fpu_enabled)) {
2322 gen_exception(ctx, POWERPC_EXCP_FPU);
2323 return;
2324 }
2325 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2326 ~(1ULL << 63));
2327 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2328 }
2329
2330 /* fmr - fmr. */
2331 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2332 static void gen_fmr(DisasContext *ctx)
2333 {
2334 if (unlikely(!ctx->fpu_enabled)) {
2335 gen_exception(ctx, POWERPC_EXCP_FPU);
2336 return;
2337 }
2338 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2339 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2340 }
2341
2342 /* fnabs */
2343 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2344 static void gen_fnabs(DisasContext *ctx)
2345 {
2346 if (unlikely(!ctx->fpu_enabled)) {
2347 gen_exception(ctx, POWERPC_EXCP_FPU);
2348 return;
2349 }
2350 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2351 1ULL << 63);
2352 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2353 }
2354
2355 /* fneg */
2356 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2357 static void gen_fneg(DisasContext *ctx)
2358 {
2359 if (unlikely(!ctx->fpu_enabled)) {
2360 gen_exception(ctx, POWERPC_EXCP_FPU);
2361 return;
2362 }
2363 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2364 1ULL << 63);
2365 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2366 }
2367
2368 /* fcpsgn: PowerPC 2.05 specification */
2369 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2370 static void gen_fcpsgn(DisasContext *ctx)
2371 {
2372 if (unlikely(!ctx->fpu_enabled)) {
2373 gen_exception(ctx, POWERPC_EXCP_FPU);
2374 return;
2375 }
2376 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2377 cpu_fpr[rB(ctx->opcode)], 0, 63);
2378 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2379 }
2380
2381 static void gen_fmrgew(DisasContext *ctx)
2382 {
2383 TCGv_i64 b0;
2384 if (unlikely(!ctx->fpu_enabled)) {
2385 gen_exception(ctx, POWERPC_EXCP_FPU);
2386 return;
2387 }
2388 b0 = tcg_temp_new_i64();
2389 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2390 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2391 b0, 0, 32);
2392 tcg_temp_free_i64(b0);
2393 }
2394
2395 static void gen_fmrgow(DisasContext *ctx)
2396 {
2397 if (unlikely(!ctx->fpu_enabled)) {
2398 gen_exception(ctx, POWERPC_EXCP_FPU);
2399 return;
2400 }
2401 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2402 cpu_fpr[rB(ctx->opcode)],
2403 cpu_fpr[rA(ctx->opcode)],
2404 32, 32);
2405 }
2406
2407 /*** Floating-Point status & ctrl register ***/
2408
2409 /* mcrfs */
2410 static void gen_mcrfs(DisasContext *ctx)
2411 {
2412 TCGv tmp = tcg_temp_new();
2413 int bfa;
2414
2415 if (unlikely(!ctx->fpu_enabled)) {
2416 gen_exception(ctx, POWERPC_EXCP_FPU);
2417 return;
2418 }
2419 bfa = 4 * (7 - crfS(ctx->opcode));
2420 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2421 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2422 tcg_temp_free(tmp);
2423 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2424 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2425 }
2426
2427 /* mffs */
2428 static void gen_mffs(DisasContext *ctx)
2429 {
2430 if (unlikely(!ctx->fpu_enabled)) {
2431 gen_exception(ctx, POWERPC_EXCP_FPU);
2432 return;
2433 }
2434 gen_reset_fpstatus();
2435 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2436 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2437 }
2438
2439 /* mtfsb0 */
2440 static void gen_mtfsb0(DisasContext *ctx)
2441 {
2442 uint8_t crb;
2443
2444 if (unlikely(!ctx->fpu_enabled)) {
2445 gen_exception(ctx, POWERPC_EXCP_FPU);
2446 return;
2447 }
2448 crb = 31 - crbD(ctx->opcode);
2449 gen_reset_fpstatus();
2450 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2451 TCGv_i32 t0;
2452 /* NIP cannot be restored if the memory exception comes from an helper */
2453 gen_update_nip(ctx, ctx->nip - 4);
2454 t0 = tcg_const_i32(crb);
2455 gen_helper_fpscr_clrbit(cpu_env, t0);
2456 tcg_temp_free_i32(t0);
2457 }
2458 if (unlikely(Rc(ctx->opcode) != 0)) {
2459 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2460 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2461 }
2462 }
2463
2464 /* mtfsb1 */
2465 static void gen_mtfsb1(DisasContext *ctx)
2466 {
2467 uint8_t crb;
2468
2469 if (unlikely(!ctx->fpu_enabled)) {
2470 gen_exception(ctx, POWERPC_EXCP_FPU);
2471 return;
2472 }
2473 crb = 31 - crbD(ctx->opcode);
2474 gen_reset_fpstatus();
2475 /* XXX: we pretend we can only do IEEE floating-point computations */
2476 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2477 TCGv_i32 t0;
2478 /* NIP cannot be restored if the memory exception comes from an helper */
2479 gen_update_nip(ctx, ctx->nip - 4);
2480 t0 = tcg_const_i32(crb);
2481 gen_helper_fpscr_setbit(cpu_env, t0);
2482 tcg_temp_free_i32(t0);
2483 }
2484 if (unlikely(Rc(ctx->opcode) != 0)) {
2485 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2486 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2487 }
2488 /* We can raise a differed exception */
2489 gen_helper_float_check_status(cpu_env);
2490 }
2491
2492 /* mtfsf */
2493 static void gen_mtfsf(DisasContext *ctx)
2494 {
2495 TCGv_i32 t0;
2496 int flm, l, w;
2497
2498 if (unlikely(!ctx->fpu_enabled)) {
2499 gen_exception(ctx, POWERPC_EXCP_FPU);
2500 return;
2501 }
2502 flm = FPFLM(ctx->opcode);
2503 l = FPL(ctx->opcode);
2504 w = FPW(ctx->opcode);
2505 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2506 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2507 return;
2508 }
2509 /* NIP cannot be restored if the memory exception comes from an helper */
2510 gen_update_nip(ctx, ctx->nip - 4);
2511 gen_reset_fpstatus();
2512 if (l) {
2513 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2514 } else {
2515 t0 = tcg_const_i32(flm << (w * 8));
2516 }
2517 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2518 tcg_temp_free_i32(t0);
2519 if (unlikely(Rc(ctx->opcode) != 0)) {
2520 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2521 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2522 }
2523 /* We can raise a differed exception */
2524 gen_helper_float_check_status(cpu_env);
2525 }
2526
2527 /* mtfsfi */
2528 static void gen_mtfsfi(DisasContext *ctx)
2529 {
2530 int bf, sh, w;
2531 TCGv_i64 t0;
2532 TCGv_i32 t1;
2533
2534 if (unlikely(!ctx->fpu_enabled)) {
2535 gen_exception(ctx, POWERPC_EXCP_FPU);
2536 return;
2537 }
2538 w = FPW(ctx->opcode);
2539 bf = FPBF(ctx->opcode);
2540 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2541 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2542 return;
2543 }
2544 sh = (8 * w) + 7 - bf;
2545 /* NIP cannot be restored if the memory exception comes from an helper */
2546 gen_update_nip(ctx, ctx->nip - 4);
2547 gen_reset_fpstatus();
2548 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2549 t1 = tcg_const_i32(1 << sh);
2550 gen_helper_store_fpscr(cpu_env, t0, t1);
2551 tcg_temp_free_i64(t0);
2552 tcg_temp_free_i32(t1);
2553 if (unlikely(Rc(ctx->opcode) != 0)) {
2554 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2555 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2556 }
2557 /* We can raise a differed exception */
2558 gen_helper_float_check_status(cpu_env);
2559 }
2560
2561 /*** Addressing modes ***/
2562 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2563 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2564 target_long maskl)
2565 {
2566 target_long simm = SIMM(ctx->opcode);
2567
2568 simm &= ~maskl;
2569 if (rA(ctx->opcode) == 0) {
2570 if (NARROW_MODE(ctx)) {
2571 simm = (uint32_t)simm;
2572 }
2573 tcg_gen_movi_tl(EA, simm);
2574 } else if (likely(simm != 0)) {
2575 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2576 if (NARROW_MODE(ctx)) {
2577 tcg_gen_ext32u_tl(EA, EA);
2578 }
2579 } else {
2580 if (NARROW_MODE(ctx)) {
2581 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2582 } else {
2583 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2584 }
2585 }
2586 }
2587
2588 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2589 {
2590 if (rA(ctx->opcode) == 0) {
2591 if (NARROW_MODE(ctx)) {
2592 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2593 } else {
2594 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2595 }
2596 } else {
2597 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2598 if (NARROW_MODE(ctx)) {
2599 tcg_gen_ext32u_tl(EA, EA);
2600 }
2601 }
2602 }
2603
2604 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2605 {
2606 if (rA(ctx->opcode) == 0) {
2607 tcg_gen_movi_tl(EA, 0);
2608 } else if (NARROW_MODE(ctx)) {
2609 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2610 } else {
2611 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2612 }
2613 }
2614
2615 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2616 target_long val)
2617 {
2618 tcg_gen_addi_tl(ret, arg1, val);
2619 if (NARROW_MODE(ctx)) {
2620 tcg_gen_ext32u_tl(ret, ret);
2621 }
2622 }
2623
2624 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2625 {
2626 int l1 = gen_new_label();
2627 TCGv t0 = tcg_temp_new();
2628 TCGv_i32 t1, t2;
2629 /* NIP cannot be restored if the memory exception comes from an helper */
2630 gen_update_nip(ctx, ctx->nip - 4);
2631 tcg_gen_andi_tl(t0, EA, mask);
2632 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2633 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2634 t2 = tcg_const_i32(0);
2635 gen_helper_raise_exception_err(cpu_env, t1, t2);
2636 tcg_temp_free_i32(t1);
2637 tcg_temp_free_i32(t2);
2638 gen_set_label(l1);
2639 tcg_temp_free(t0);
2640 }
2641
2642 /*** Integer load ***/
2643 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2644 {
2645 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2646 }
2647
2648 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2649 {
2650 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2651 }
2652
2653 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2654 {
2655 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2656 if (unlikely(ctx->le_mode)) {
2657 tcg_gen_bswap16_tl(arg1, arg1);
2658 }
2659 }
2660
2661 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2662 {
2663 if (unlikely(ctx->le_mode)) {
2664 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2665 tcg_gen_bswap16_tl(arg1, arg1);
2666 tcg_gen_ext16s_tl(arg1, arg1);
2667 } else {
2668 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2669 }
2670 }
2671
2672 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2673 {
2674 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2675 if (unlikely(ctx->le_mode)) {
2676 tcg_gen_bswap32_tl(arg1, arg1);
2677 }
2678 }
2679
2680 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2681 {
2682 TCGv tmp = tcg_temp_new();
2683 gen_qemu_ld32u(ctx, tmp, addr);
2684 tcg_gen_extu_tl_i64(val, tmp);
2685 tcg_temp_free(tmp);
2686 }
2687
2688 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2689 {
2690 if (unlikely(ctx->le_mode)) {
2691 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2692 tcg_gen_bswap32_tl(arg1, arg1);
2693 tcg_gen_ext32s_tl(arg1, arg1);
2694 } else
2695 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2696 }
2697
2698 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2699 {
2700 TCGv tmp = tcg_temp_new();
2701 gen_qemu_ld32s(ctx, tmp, addr);
2702 tcg_gen_ext_tl_i64(val, tmp);
2703 tcg_temp_free(tmp);
2704 }
2705
2706 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2707 {
2708 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2709 if (unlikely(ctx->le_mode)) {
2710 tcg_gen_bswap64_i64(arg1, arg1);
2711 }
2712 }
2713
2714 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2715 {
2716 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2717 }
2718
2719 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2720 {
2721 if (unlikely(ctx->le_mode)) {
2722 TCGv t0 = tcg_temp_new();
2723 tcg_gen_ext16u_tl(t0, arg1);
2724 tcg_gen_bswap16_tl(t0, t0);
2725 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2726 tcg_temp_free(t0);
2727 } else {
2728 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2729 }
2730 }
2731
2732 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2733 {
2734 if (unlikely(ctx->le_mode)) {
2735 TCGv t0 = tcg_temp_new();
2736 tcg_gen_ext32u_tl(t0, arg1);
2737 tcg_gen_bswap32_tl(t0, t0);
2738 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2739 tcg_temp_free(t0);
2740 } else {
2741 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2742 }
2743 }
2744
2745 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2746 {
2747 TCGv tmp = tcg_temp_new();
2748 tcg_gen_trunc_i64_tl(tmp, val);
2749 gen_qemu_st32(ctx, tmp, addr);
2750 tcg_temp_free(tmp);
2751 }
2752
2753 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2754 {
2755 if (unlikely(ctx->le_mode)) {
2756 TCGv_i64 t0 = tcg_temp_new_i64();
2757 tcg_gen_bswap64_i64(t0, arg1);
2758 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2759 tcg_temp_free_i64(t0);
2760 } else
2761 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2762 }
2763
2764 #define GEN_LD(name, ldop, opc, type) \
2765 static void glue(gen_, name)(DisasContext *ctx) \
2766 { \
2767 TCGv EA; \
2768 gen_set_access_type(ctx, ACCESS_INT); \
2769 EA = tcg_temp_new(); \
2770 gen_addr_imm_index(ctx, EA, 0); \
2771 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2772 tcg_temp_free(EA); \
2773 }
2774
2775 #define GEN_LDU(name, ldop, opc, type) \
2776 static void glue(gen_, name##u)(DisasContext *ctx) \
2777 { \
2778 TCGv EA; \
2779 if (unlikely(rA(ctx->opcode) == 0 || \
2780 rA(ctx->opcode) == rD(ctx->opcode))) { \
2781 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2782 return; \
2783 } \
2784 gen_set_access_type(ctx, ACCESS_INT); \
2785 EA = tcg_temp_new(); \
2786 if (type == PPC_64B) \
2787 gen_addr_imm_index(ctx, EA, 0x03); \
2788 else \
2789 gen_addr_imm_index(ctx, EA, 0); \
2790 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2791 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2792 tcg_temp_free(EA); \
2793 }
2794
2795 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2796 static void glue(gen_, name##ux)(DisasContext *ctx) \
2797 { \
2798 TCGv EA; \
2799 if (unlikely(rA(ctx->opcode) == 0 || \
2800 rA(ctx->opcode) == rD(ctx->opcode))) { \
2801 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2802 return; \
2803 } \
2804 gen_set_access_type(ctx, ACCESS_INT); \
2805 EA = tcg_temp_new(); \
2806 gen_addr_reg_index(ctx, EA); \
2807 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2808 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2809 tcg_temp_free(EA); \
2810 }
2811
2812 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2813 static void glue(gen_, name##x)(DisasContext *ctx) \
2814 { \
2815 TCGv EA; \
2816 gen_set_access_type(ctx, ACCESS_INT); \
2817 EA = tcg_temp_new(); \
2818 gen_addr_reg_index(ctx, EA); \
2819 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2820 tcg_temp_free(EA); \
2821 }
2822 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2823 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2824
2825 #define GEN_LDS(name, ldop, op, type) \
2826 GEN_LD(name, ldop, op | 0x20, type); \
2827 GEN_LDU(name, ldop, op | 0x21, type); \
2828 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2829 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2830
2831 /* lbz lbzu lbzux lbzx */
2832 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2833 /* lha lhau lhaux lhax */
2834 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2835 /* lhz lhzu lhzux lhzx */
2836 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2837 /* lwz lwzu lwzux lwzx */
2838 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2839 #if defined(TARGET_PPC64)
2840 /* lwaux */
2841 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2842 /* lwax */
2843 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2844 /* ldux */
2845 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2846 /* ldx */
2847 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2848
2849 static void gen_ld(DisasContext *ctx)
2850 {
2851 TCGv EA;
2852 if (Rc(ctx->opcode)) {
2853 if (unlikely(rA(ctx->opcode) == 0 ||
2854 rA(ctx->opcode) == rD(ctx->opcode))) {
2855 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2856 return;
2857 }
2858 }
2859 gen_set_access_type(ctx, ACCESS_INT);
2860 EA = tcg_temp_new();
2861 gen_addr_imm_index(ctx, EA, 0x03);
2862 if (ctx->opcode & 0x02) {
2863 /* lwa (lwau is undefined) */
2864 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2865 } else {
2866 /* ld - ldu */
2867 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2868 }
2869 if (Rc(ctx->opcode))
2870 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2871 tcg_temp_free(EA);
2872 }
2873
2874 /* lq */
2875 static void gen_lq(DisasContext *ctx)
2876 {
2877 int ra, rd;
2878 TCGv EA;
2879
2880 /* lq is a legal user mode instruction starting in ISA 2.07 */
2881 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2882 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2883
2884 if (!legal_in_user_mode && is_user_mode(ctx)) {
2885 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2886 return;
2887 }
2888
2889 if (!le_is_supported && ctx->le_mode) {
2890 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2891 return;
2892 }
2893
2894 ra = rA(ctx->opcode);
2895 rd = rD(ctx->opcode);
2896 if (unlikely((rd & 1) || rd == ra)) {
2897 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2898 return;
2899 }
2900
2901 gen_set_access_type(ctx, ACCESS_INT);
2902 EA = tcg_temp_new();
2903 gen_addr_imm_index(ctx, EA, 0x0F);
2904
2905 if (unlikely(ctx->le_mode)) {
2906 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2907 gen_addr_add(ctx, EA, EA, 8);
2908 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2909 } else {
2910 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2911 gen_addr_add(ctx, EA, EA, 8);
2912 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2913 }
2914 tcg_temp_free(EA);
2915 }
2916 #endif
2917
2918 /*** Integer store ***/
2919 #define GEN_ST(name, stop, opc, type) \
2920 static void glue(gen_, name)(DisasContext *ctx) \
2921 { \
2922 TCGv EA; \
2923 gen_set_access_type(ctx, ACCESS_INT); \
2924 EA = tcg_temp_new(); \
2925 gen_addr_imm_index(ctx, EA, 0); \
2926 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2927 tcg_temp_free(EA); \
2928 }
2929
2930 #define GEN_STU(name, stop, opc, type) \
2931 static void glue(gen_, stop##u)(DisasContext *ctx) \
2932 { \
2933 TCGv EA; \
2934 if (unlikely(rA(ctx->opcode) == 0)) { \
2935 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2936 return; \
2937 } \
2938 gen_set_access_type(ctx, ACCESS_INT); \
2939 EA = tcg_temp_new(); \
2940 if (type == PPC_64B) \
2941 gen_addr_imm_index(ctx, EA, 0x03); \
2942 else \
2943 gen_addr_imm_index(ctx, EA, 0); \
2944 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2945 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2946 tcg_temp_free(EA); \
2947 }
2948
2949 #define GEN_STUX(name, stop, opc2, opc3, type) \
2950 static void glue(gen_, name##ux)(DisasContext *ctx) \
2951 { \
2952 TCGv EA; \
2953 if (unlikely(rA(ctx->opcode) == 0)) { \
2954 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2955 return; \
2956 } \
2957 gen_set_access_type(ctx, ACCESS_INT); \
2958 EA = tcg_temp_new(); \
2959 gen_addr_reg_index(ctx, EA); \
2960 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2961 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2962 tcg_temp_free(EA); \
2963 }
2964
2965 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2966 static void glue(gen_, name##x)(DisasContext *ctx) \
2967 { \
2968 TCGv EA; \
2969 gen_set_access_type(ctx, ACCESS_INT); \
2970 EA = tcg_temp_new(); \
2971 gen_addr_reg_index(ctx, EA); \
2972 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2973 tcg_temp_free(EA); \
2974 }
2975 #define GEN_STX(name, stop, opc2, opc3, type) \
2976 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2977
2978 #define GEN_STS(name, stop, op, type) \
2979 GEN_ST(name, stop, op | 0x20, type); \
2980 GEN_STU(name, stop, op | 0x21, type); \
2981 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2982 GEN_STX(name, stop, 0x17, op | 0x00, type)
2983
2984 /* stb stbu stbux stbx */
2985 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2986 /* sth sthu sthux sthx */
2987 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2988 /* stw stwu stwux stwx */
2989 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2990 #if defined(TARGET_PPC64)
2991 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2992 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2993
2994 static void gen_std(DisasContext *ctx)
2995 {
2996 int rs;
2997 TCGv EA;
2998
2999 rs = rS(ctx->opcode);
3000 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3001
3002 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3003 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3004
3005 if (!legal_in_user_mode && is_user_mode(ctx)) {
3006 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3007 return;
3008 }
3009
3010 if (!le_is_supported && ctx->le_mode) {
3011 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3012 return;
3013 }
3014
3015 if (unlikely(rs & 1)) {
3016 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3017 return;
3018 }
3019 gen_set_access_type(ctx, ACCESS_INT);
3020 EA = tcg_temp_new();
3021 gen_addr_imm_index(ctx, EA, 0x03);
3022
3023 if (unlikely(ctx->le_mode)) {
3024 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3025 gen_addr_add(ctx, EA, EA, 8);
3026 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3027 } else {
3028 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3029 gen_addr_add(ctx, EA, EA, 8);
3030 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3031 }
3032 tcg_temp_free(EA);
3033 } else {
3034 /* std / stdu*/
3035 if (Rc(ctx->opcode)) {
3036 if (unlikely(rA(ctx->opcode) == 0)) {
3037 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3038 return;
3039 }
3040 }
3041 gen_set_access_type(ctx, ACCESS_INT);
3042 EA = tcg_temp_new();
3043 gen_addr_imm_index(ctx, EA, 0x03);
3044 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3045 if (Rc(ctx->opcode))
3046 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3047 tcg_temp_free(EA);
3048 }
3049 }
3050 #endif
3051 /*** Integer load and store with byte reverse ***/
3052 /* lhbrx */
3053 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3054 {
3055 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
3056 if (likely(!ctx->le_mode)) {
3057 tcg_gen_bswap16_tl(arg1, arg1);
3058 }
3059 }
3060 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3061
3062 /* lwbrx */
3063 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3064 {
3065 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
3066 if (likely(!ctx->le_mode)) {
3067 tcg_gen_bswap32_tl(arg1, arg1);
3068 }
3069 }
3070 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3071
3072 #if defined(TARGET_PPC64)
3073 /* ldbrx */
3074 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3075 {
3076 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
3077 if (likely(!ctx->le_mode)) {
3078 tcg_gen_bswap64_tl(arg1, arg1);
3079 }
3080 }
3081 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3082 #endif /* TARGET_PPC64 */
3083
3084 /* sthbrx */
3085 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3086 {
3087 if (likely(!ctx->le_mode)) {
3088 TCGv t0 = tcg_temp_new();
3089 tcg_gen_ext16u_tl(t0, arg1);
3090 tcg_gen_bswap16_tl(t0, t0);
3091 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3092 tcg_temp_free(t0);
3093 } else {
3094 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3095 }
3096 }
3097 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3098
3099 /* stwbrx */
3100 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3101 {
3102 if (likely(!ctx->le_mode)) {
3103 TCGv t0 = tcg_temp_new();
3104 tcg_gen_ext32u_tl(t0, arg1);
3105 tcg_gen_bswap32_tl(t0, t0);
3106 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3107 tcg_temp_free(t0);
3108 } else {
3109 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3110 }
3111 }
3112 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3113
3114 #if defined(TARGET_PPC64)
3115 /* stdbrx */
3116 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3117 {
3118 if (likely(!ctx->le_mode)) {
3119 TCGv t0 = tcg_temp_new();
3120 tcg_gen_bswap64_tl(t0, arg1);
3121 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
3122 tcg_temp_free(t0);
3123 } else {
3124 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
3125 }
3126 }
3127 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3128 #endif /* TARGET_PPC64 */
3129
3130 /*** Integer load and store multiple ***/
3131
3132 /* lmw */
3133 static void gen_lmw(DisasContext *ctx)
3134 {
3135 TCGv t0;
3136 TCGv_i32 t1;
3137 gen_set_access_type(ctx, ACCESS_INT);
3138 /* NIP cannot be restored if the memory exception comes from an helper */
3139 gen_update_nip(ctx, ctx->nip - 4);
3140 t0 = tcg_temp_new();
3141 t1 = tcg_const_i32(rD(ctx->opcode));
3142 gen_addr_imm_index(ctx, t0, 0);
3143 gen_helper_lmw(cpu_env, t0, t1);
3144 tcg_temp_free(t0);
3145 tcg_temp_free_i32(t1);
3146 }
3147
3148 /* stmw */
3149 static void gen_stmw(DisasContext *ctx)
3150 {
3151 TCGv t0;
3152 TCGv_i32 t1;
3153 gen_set_access_type(ctx, ACCESS_INT);
3154 /* NIP cannot be restored if the memory exception comes from an helper */
3155 gen_update_nip(ctx, ctx->nip - 4);
3156 t0 = tcg_temp_new();
3157 t1 = tcg_const_i32(rS(ctx->opcode));
3158 gen_addr_imm_index(ctx, t0, 0);
3159 gen_helper_stmw(cpu_env, t0, t1);
3160 tcg_temp_free(t0);
3161 tcg_temp_free_i32(t1);
3162 }
3163
3164 /*** Integer load and store strings ***/
3165
3166 /* lswi */
3167 /* PowerPC32 specification says we must generate an exception if
3168 * rA is in the range of registers to be loaded.
3169 * In an other hand, IBM says this is valid, but rA won't be loaded.
3170 * For now, I'll follow the spec...
3171 */
3172 static void gen_lswi(DisasContext *ctx)
3173 {
3174 TCGv t0;
3175 TCGv_i32 t1, t2;
3176 int nb = NB(ctx->opcode);
3177 int start = rD(ctx->opcode);
3178 int ra = rA(ctx->opcode);
3179 int nr;
3180
3181 if (nb == 0)
3182 nb = 32;
3183 nr = nb / 4;
3184 if (unlikely(((start + nr) > 32 &&
3185 start <= ra && (start + nr - 32) > ra) ||
3186 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3187 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3188 return;
3189 }
3190 gen_set_access_type(ctx, ACCESS_INT);
3191 /* NIP cannot be restored if the memory exception comes from an helper */
3192 gen_update_nip(ctx, ctx->nip - 4);
3193 t0 = tcg_temp_new();
3194 gen_addr_register(ctx, t0);
3195 t1 = tcg_const_i32(nb);
3196 t2 = tcg_const_i32(start);
3197 gen_helper_lsw(cpu_env, t0, t1, t2);
3198 tcg_temp_free(t0);
3199 tcg_temp_free_i32(t1);
3200 tcg_temp_free_i32(t2);
3201 }
3202
3203 /* lswx */
3204 static void gen_lswx(DisasContext *ctx)
3205 {
3206 TCGv t0;
3207 TCGv_i32 t1, t2, t3;
3208 gen_set_access_type(ctx, ACCESS_INT);
3209 /* NIP cannot be restored if the memory exception comes from an helper */
3210 gen_update_nip(ctx, ctx->nip - 4);
3211 t0 = tcg_temp_new();
3212 gen_addr_reg_index(ctx, t0);
3213 t1 = tcg_const_i32(rD(ctx->opcode));
3214 t2 = tcg_const_i32(rA(ctx->opcode));
3215 t3 = tcg_const_i32(rB(ctx->opcode));
3216 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3217 tcg_temp_free(t0);
3218 tcg_temp_free_i32(t1);
3219 tcg_temp_free_i32(t2);
3220 tcg_temp_free_i32(t3);
3221 }
3222
3223 /* stswi */
3224 static void gen_stswi(DisasContext *ctx)
3225 {
3226 TCGv t0;
3227 TCGv_i32 t1, t2;
3228 int nb = NB(ctx->opcode);
3229 gen_set_access_type(ctx, ACCESS_INT);
3230 /* NIP cannot be restored if the memory exception comes from an helper */
3231 gen_update_nip(ctx, ctx->nip - 4);
3232 t0 = tcg_temp_new();
3233 gen_addr_register(ctx, t0);
3234 if (nb == 0)
3235 nb = 32;
3236 t1 = tcg_const_i32(nb);
3237 t2 = tcg_const_i32(rS(ctx->opcode));
3238 gen_helper_stsw(cpu_env, t0, t1, t2);
3239 tcg_temp_free(t0);
3240 tcg_temp_free_i32(t1);
3241 tcg_temp_free_i32(t2);
3242 }
3243
3244 /* stswx */
3245 static void gen_stswx(DisasContext *ctx)
3246 {
3247 TCGv t0;
3248 TCGv_i32 t1, t2;
3249 gen_set_access_type(ctx, ACCESS_INT);
3250 /* NIP cannot be restored if the memory exception comes from an helper */
3251 gen_update_nip(ctx, ctx->nip - 4);
3252 t0 = tcg_temp_new();
3253 gen_addr_reg_index(ctx, t0);
3254 t1 = tcg_temp_new_i32();
3255 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3256 tcg_gen_andi_i32(t1, t1, 0x7F);
3257 t2 = tcg_const_i32(rS(ctx->opcode));
3258 gen_helper_stsw(cpu_env, t0, t1, t2);
3259 tcg_temp_free(t0);
3260 tcg_temp_free_i32(t1);
3261 tcg_temp_free_i32(t2);
3262 }
3263
3264 /*** Memory synchronisation ***/
3265 /* eieio */
3266 static void gen_eieio(DisasContext *ctx)
3267 {
3268 }
3269
3270 /* isync */
3271 static void gen_isync(DisasContext *ctx)
3272 {
3273 gen_stop_exception(ctx);
3274 }
3275
3276 #define LARX(name, len, loadop) \
3277 static void gen_##name(DisasContext *ctx) \
3278 { \
3279 TCGv t0; \
3280 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3281 gen_set_access_type(ctx, ACCESS_RES); \
3282 t0 = tcg_temp_local_new(); \
3283 gen_addr_reg_index(ctx, t0); \
3284 if ((len) > 1) { \
3285 gen_check_align(ctx, t0, (len)-1); \
3286 } \
3287 gen_qemu_##loadop(ctx, gpr, t0); \
3288 tcg_gen_mov_tl(cpu_reserve, t0); \
3289 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3290 tcg_temp_free(t0); \
3291 }
3292
3293 /* lwarx */
3294 LARX(lbarx, 1, ld8u);
3295 LARX(lharx, 2, ld16u);
3296 LARX(lwarx, 4, ld32u);
3297
3298
3299 #if defined(CONFIG_USER_ONLY)
3300 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3301 int reg, int size)
3302 {
3303 TCGv t0 = tcg_temp_new();
3304 uint32_t save_exception = ctx->exception;
3305
3306 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3307 tcg_gen_movi_tl(t0, (size << 5) | reg);
3308 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3309 tcg_temp_free(t0);
3310 gen_update_nip(ctx, ctx->nip-4);
3311 ctx->exception = POWERPC_EXCP_BRANCH;
3312 gen_exception(ctx, POWERPC_EXCP_STCX);
3313 ctx->exception = save_exception;
3314 }
3315 #else
3316 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3317 int reg, int size)
3318 {
3319 int l1;
3320
3321 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3322 l1 = gen_new_label();
3323 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3324 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3325 #if defined(TARGET_PPC64)
3326 if (size == 8) {
3327 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3328 } else
3329 #endif
3330 if (size == 4) {
3331 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3332 } else if (size == 2) {
3333 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3334 #if defined(TARGET_PPC64)
3335 } else if (size == 16) {
3336 TCGv gpr1, gpr2;
3337 if (unlikely(ctx->le_mode)) {
3338 gpr1 = cpu_gpr[reg+1];
3339 gpr2 = cpu_gpr[reg];
3340 } else {
3341 gpr1 = cpu_gpr[reg];
3342 gpr2 = cpu_gpr[reg+1];
3343 }
3344 gen_qemu_st64(ctx, gpr1, EA);
3345 gen_addr_add(ctx, EA, EA, 8);
3346 gen_qemu_st64(ctx, gpr2, EA);
3347 #endif
3348 } else {
3349 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3350 }
3351 gen_set_label(l1);
3352 tcg_gen_movi_tl(cpu_reserve, -1);
3353 }
3354 #endif
3355
3356 #define STCX(name, len) \
3357 static void gen_##name(DisasContext *ctx) \
3358 { \
3359 TCGv t0; \
3360 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3361 gen_inval_exception(ctx, \
3362 POWERPC_EXCP_INVAL_INVAL); \
3363 return; \
3364 } \
3365 gen_set_access_type(ctx, ACCESS_RES); \
3366 t0 = tcg_temp_local_new(); \
3367 gen_addr_reg_index(ctx, t0); \
3368 if (len > 1) { \
3369 gen_check_align(ctx, t0, (len)-1); \
3370 } \
3371 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3372 tcg_temp_free(t0); \
3373 }
3374
3375 STCX(stbcx_, 1);
3376 STCX(sthcx_, 2);
3377 STCX(stwcx_, 4);
3378
3379 #if defined(TARGET_PPC64)
3380 /* ldarx */
3381 LARX(ldarx, 8, ld64);
3382
3383 /* lqarx */
3384 static void gen_lqarx(DisasContext *ctx)
3385 {
3386 TCGv EA;
3387 int rd = rD(ctx->opcode);
3388 TCGv gpr1, gpr2;
3389
3390 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3391 (rd == rB(ctx->opcode)))) {
3392 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3393 return;
3394 }
3395
3396 gen_set_access_type(ctx, ACCESS_RES);
3397 EA = tcg_temp_local_new();
3398 gen_addr_reg_index(ctx, EA);
3399 gen_check_align(ctx, EA, 15);
3400 if (unlikely(ctx->le_mode)) {
3401 gpr1 = cpu_gpr[rd+1];
3402 gpr2 = cpu_gpr[rd];
3403 } else {
3404 gpr1 = cpu_gpr[rd];
3405 gpr2 = cpu_gpr[rd+1];
3406 }
3407 gen_qemu_ld64(ctx, gpr1, EA);
3408 tcg_gen_mov_tl(cpu_reserve, EA);
3409
3410 gen_addr_add(ctx, EA, EA, 8);
3411 gen_qemu_ld64(ctx, gpr2, EA);
3412
3413 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3414 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3415
3416 tcg_temp_free(EA);
3417 }
3418
3419 /* stdcx. */
3420 STCX(stdcx_, 8);
3421 STCX(stqcx_, 16);
3422 #endif /* defined(TARGET_PPC64) */
3423
3424 /* sync */
3425 static void gen_sync(DisasContext *ctx)
3426 {
3427 }
3428
3429 /* wait */
3430 static void gen_wait(DisasContext *ctx)
3431 {
3432 TCGv_i32 t0 = tcg_temp_new_i32();
3433 tcg_gen_st_i32(t0, cpu_env,
3434 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3435 tcg_temp_free_i32(t0);
3436 /* Stop translation, as the CPU is supposed to sleep from now */
3437 gen_exception_err(ctx, EXCP_HLT, 1);
3438 }
3439
3440 /*** Floating-point load ***/
3441 #define GEN_LDF(name, ldop, opc, type) \
3442 static void glue(gen_, name)(DisasContext *ctx) \
3443 { \
3444 TCGv EA; \
3445 if (unlikely(!ctx->fpu_enabled)) { \
3446 gen_exception(ctx, POWERPC_EXCP_FPU); \
3447 return; \
3448 } \
3449 gen_set_access_type(ctx, ACCESS_FLOAT); \
3450 EA = tcg_temp_new(); \
3451 gen_addr_imm_index(ctx, EA, 0); \
3452 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3453 tcg_temp_free(EA); \
3454 }
3455
3456 #define GEN_LDUF(name, ldop, opc, type) \
3457 static void glue(gen_, name##u)(DisasContext *ctx) \
3458 { \
3459 TCGv EA; \
3460 if (unlikely(!ctx->fpu_enabled)) { \
3461 gen_exception(ctx, POWERPC_EXCP_FPU); \
3462 return; \
3463 } \
3464 if (unlikely(rA(ctx->opcode) == 0)) { \
3465 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3466 return; \
3467 } \
3468 gen_set_access_type(ctx, ACCESS_FLOAT); \
3469 EA = tcg_temp_new(); \
3470 gen_addr_imm_index(ctx, EA, 0); \
3471 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3472 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3473 tcg_temp_free(EA); \
3474 }
3475
3476 #define GEN_LDUXF(name, ldop, opc, type) \
3477 static void glue(gen_, name##ux)(DisasContext *ctx) \
3478 { \
3479 TCGv EA; \
3480 if (unlikely(!ctx->fpu_enabled)) { \
3481 gen_exception(ctx, POWERPC_EXCP_FPU); \
3482 return; \
3483 } \
3484 if (unlikely(rA(ctx->opcode) == 0)) { \
3485 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3486 return; \
3487 } \
3488 gen_set_access_type(ctx, ACCESS_FLOAT); \
3489 EA = tcg_temp_new(); \
3490 gen_addr_reg_index(ctx, EA); \
3491 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3492 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3493 tcg_temp_free(EA); \
3494 }
3495
3496 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3497 static void glue(gen_, name##x)(DisasContext *ctx) \
3498 { \
3499 TCGv EA; \
3500 if (unlikely(!ctx->fpu_enabled)) { \
3501 gen_exception(ctx, POWERPC_EXCP_FPU); \
3502 return; \
3503 } \
3504 gen_set_access_type(ctx, ACCESS_FLOAT); \
3505 EA = tcg_temp_new(); \
3506 gen_addr_reg_index(ctx, EA); \
3507 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3508 tcg_temp_free(EA); \
3509 }
3510
3511 #define GEN_LDFS(name, ldop, op, type) \
3512 GEN_LDF(name, ldop, op | 0x20, type); \
3513 GEN_LDUF(name, ldop, op | 0x21, type); \
3514 GEN_LDUXF(name, ldop, op | 0x01, type); \
3515 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3516
3517 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3518 {
3519 TCGv t0 = tcg_temp_new();
3520 TCGv_i32 t1 = tcg_temp_new_i32();
3521 gen_qemu_ld32u(ctx, t0, arg2);
3522 tcg_gen_trunc_tl_i32(t1, t0);
3523 tcg_temp_free(t0);
3524 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3525 tcg_temp_free_i32(t1);
3526 }
3527
3528 /* lfd lfdu lfdux lfdx */
3529 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3530 /* lfs lfsu lfsux lfsx */
3531 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3532
3533 /* lfdp */
3534 static void gen_lfdp(DisasContext *ctx)
3535 {
3536 TCGv EA;
3537 if (unlikely(!ctx->fpu_enabled)) {
3538 gen_exception(ctx, POWERPC_EXCP_FPU);
3539 return;
3540 }
3541 gen_set_access_type(ctx, ACCESS_FLOAT);
3542 EA = tcg_temp_new();
3543 gen_addr_imm_index(ctx, EA, 0); \
3544 if (unlikely(ctx->le_mode)) {
3545 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3546 tcg_gen_addi_tl(EA, EA, 8);
3547 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3548 } else {
3549 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3550 tcg_gen_addi_tl(EA, EA, 8);
3551 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3552 }
3553 tcg_temp_free(EA);
3554 }
3555
3556 /* lfdpx */
3557 static void gen_lfdpx(DisasContext *ctx)
3558 {
3559 TCGv EA;
3560 if (unlikely(!ctx->fpu_enabled)) {
3561 gen_exception(ctx, POWERPC_EXCP_FPU);
3562 return;
3563 }
3564 gen_set_access_type(ctx, ACCESS_FLOAT);
3565 EA = tcg_temp_new();
3566 gen_addr_reg_index(ctx, EA);
3567 if (unlikely(ctx->le_mode)) {
3568 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3569 tcg_gen_addi_tl(EA, EA, 8);
3570 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3571 } else {
3572 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3573 tcg_gen_addi_tl(EA, EA, 8);
3574 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3575 }
3576 tcg_temp_free(EA);
3577 }
3578
3579 /* lfiwax */
3580 static void gen_lfiwax(DisasContext *ctx)
3581 {
3582 TCGv EA;
3583 TCGv t0;
3584 if (unlikely(!ctx->fpu_enabled)) {
3585 gen_exception(ctx, POWERPC_EXCP_FPU);
3586 return;
3587 }
3588 gen_set_access_type(ctx, ACCESS_FLOAT);
3589 EA = tcg_temp_new();
3590 t0 = tcg_temp_new();
3591 gen_addr_reg_index(ctx, EA);
3592 gen_qemu_ld32s(ctx, t0, EA);
3593 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3594 tcg_temp_free(EA);
3595 tcg_temp_free(t0);
3596 }
3597
3598 /* lfiwzx */
3599 static void gen_lfiwzx(DisasContext *ctx)
3600 {
3601 TCGv EA;
3602 if (unlikely(!ctx->fpu_enabled)) {
3603 gen_exception(ctx, POWERPC_EXCP_FPU);
3604 return;
3605 }
3606 gen_set_access_type(ctx, ACCESS_FLOAT);
3607 EA = tcg_temp_new();
3608 gen_addr_reg_index(ctx, EA);
3609 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3610 tcg_temp_free(EA);
3611 }
3612 /*** Floating-point store ***/
3613 #define GEN_STF(name, stop, opc, type) \
3614 static void glue(gen_, name)(DisasContext *ctx) \
3615 { \
3616 TCGv EA; \
3617 if (unlikely(!ctx->fpu_enabled)) { \
3618 gen_exception(ctx, POWERPC_EXCP_FPU); \
3619 return; \
3620 } \
3621 gen_set_access_type(ctx, ACCESS_FLOAT); \
3622 EA = tcg_temp_new(); \
3623 gen_addr_imm_index(ctx, EA, 0); \
3624 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3625 tcg_temp_free(EA); \
3626 }
3627
3628 #define GEN_STUF(name, stop, opc, type) \
3629 static void glue(gen_, name##u)(DisasContext *ctx) \
3630 { \
3631 TCGv EA; \
3632 if (unlikely(!ctx->fpu_enabled)) { \
3633 gen_exception(ctx, POWERPC_EXCP_FPU); \
3634 return; \
3635 } \
3636 if (unlikely(rA(ctx->opcode) == 0)) { \
3637 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3638 return; \
3639 } \
3640 gen_set_access_type(ctx, ACCESS_FLOAT); \
3641 EA = tcg_temp_new(); \
3642 gen_addr_imm_index(ctx, EA, 0); \
3643 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3644 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3645 tcg_temp_free(EA); \
3646 }
3647
3648 #define GEN_STUXF(name, stop, opc, type) \
3649 static void glue(gen_, name##ux)(DisasContext *ctx) \
3650 { \
3651 TCGv EA; \
3652 if (unlikely(!ctx->fpu_enabled)) { \
3653 gen_exception(ctx, POWERPC_EXCP_FPU); \
3654 return; \
3655 } \
3656 if (unlikely(rA(ctx->opcode) == 0)) { \
3657 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3658 return; \
3659 } \
3660 gen_set_access_type(ctx, ACCESS_FLOAT); \
3661 EA = tcg_temp_new(); \
3662 gen_addr_reg_index(ctx, EA); \
3663 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3664 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3665 tcg_temp_free(EA); \
3666 }
3667
3668 #define GEN_STXF(name, stop, opc2, opc3, type) \
3669 static void glue(gen_, name##x)(DisasContext *ctx) \
3670 { \
3671 TCGv EA; \
3672 if (unlikely(!ctx->fpu_enabled)) { \
3673 gen_exception(ctx, POWERPC_EXCP_FPU); \
3674 return; \
3675 } \
3676 gen_set_access_type(ctx, ACCESS_FLOAT); \
3677 EA = tcg_temp_new(); \
3678 gen_addr_reg_index(ctx, EA); \
3679 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3680 tcg_temp_free(EA); \
3681 }
3682
3683 #define GEN_STFS(name, stop, op, type) \
3684 GEN_STF(name, stop, op | 0x20, type); \
3685 GEN_STUF(name, stop, op | 0x21, type); \
3686 GEN_STUXF(name, stop, op | 0x01, type); \
3687 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3688
3689 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3690 {
3691 TCGv_i32 t0 = tcg_temp_new_i32();
3692 TCGv t1 = tcg_temp_new();
3693 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3694 tcg_gen_extu_i32_tl(t1, t0);
3695 tcg_temp_free_i32(t0);
3696 gen_qemu_st32(ctx, t1, arg2);
3697 tcg_temp_free(t1);
3698 }
3699
3700 /* stfd stfdu stfdux stfdx */
3701 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3702 /* stfs stfsu stfsux stfsx */
3703 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3704
3705 /* stfdp */
3706 static void gen_stfdp(DisasContext *ctx)
3707 {
3708 TCGv EA;
3709 if (unlikely(!ctx->fpu_enabled)) {
3710 gen_exception(ctx, POWERPC_EXCP_FPU);
3711 return;
3712 }
3713 gen_set_access_type(ctx, ACCESS_FLOAT);
3714 EA = tcg_temp_new();
3715 gen_addr_imm_index(ctx, EA, 0); \
3716 if (unlikely(ctx->le_mode)) {
3717 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3718 tcg_gen_addi_tl(EA, EA, 8);
3719 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3720 } else {
3721 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3722 tcg_gen_addi_tl(EA, EA, 8);
3723 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3724 }
3725 tcg_temp_free(EA);
3726 }
3727
3728 /* stfdpx */
3729 static void gen_stfdpx(DisasContext *ctx)
3730 {
3731 TCGv EA;
3732 if (unlikely(!ctx->fpu_enabled)) {
3733 gen_exception(ctx, POWERPC_EXCP_FPU);
3734 return;
3735 }
3736 gen_set_access_type(ctx, ACCESS_FLOAT);
3737 EA = tcg_temp_new();
3738 gen_addr_reg_index(ctx, EA);
3739 if (unlikely(ctx->le_mode)) {
3740 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3741 tcg_gen_addi_tl(EA, EA, 8);
3742 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3743 } else {
3744 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3745 tcg_gen_addi_tl(EA, EA, 8);
3746 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3747 }
3748 tcg_temp_free(EA);
3749 }
3750
3751 /* Optional: */
3752 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3753 {
3754 TCGv t0 = tcg_temp_new();
3755 tcg_gen_trunc_i64_tl(t0, arg1),
3756 gen_qemu_st32(ctx, t0, arg2);
3757 tcg_temp_free(t0);
3758 }
3759 /* stfiwx */
3760 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3761
3762 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3763 {
3764 #if defined(TARGET_PPC64)
3765 if (ctx->has_cfar)
3766 tcg_gen_movi_tl(cpu_cfar, nip);
3767 #endif
3768 }
3769
3770 /*** Branch ***/
3771 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3772 {
3773 TranslationBlock *tb;
3774 tb = ctx->tb;
3775 if (NARROW_MODE(ctx)) {
3776 dest = (uint32_t) dest;
3777 }
3778 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3779 likely(!ctx->singlestep_enabled)) {
3780 tcg_gen_goto_tb(n);
3781 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3782 tcg_gen_exit_tb((uintptr_t)tb + n);
3783 } else {
3784 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3785 if (unlikely(ctx->singlestep_enabled)) {
3786 if ((ctx->singlestep_enabled &
3787 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3788 (ctx->exception == POWERPC_EXCP_BRANCH ||
3789 ctx->exception == POWERPC_EXCP_TRACE)) {
3790 target_ulong tmp = ctx->nip;
3791 ctx->nip = dest;
3792 gen_exception(ctx, POWERPC_EXCP_TRACE);
3793 ctx->nip = tmp;
3794 }
3795 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3796 gen_debug_exception(ctx);
3797 }
3798 }
3799 tcg_gen_exit_tb(0);
3800 }
3801 }
3802
3803 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3804 {
3805 if (NARROW_MODE(ctx)) {
3806 nip = (uint32_t)nip;
3807 }
3808 tcg_gen_movi_tl(cpu_lr, nip);
3809 }
3810
3811 /* b ba bl bla */
3812 static void gen_b(DisasContext *ctx)
3813 {
3814 target_ulong li, target;
3815
3816 ctx->exception = POWERPC_EXCP_BRANCH;
3817 /* sign extend LI */
3818 li = LI(ctx->opcode);
3819 li = (li ^ 0x02000000) - 0x02000000;
3820 if (likely(AA(ctx->opcode) == 0)) {
3821 target = ctx->nip + li - 4;
3822 } else {
3823 target = li;
3824 }
3825 if (LK(ctx->opcode)) {
3826 gen_setlr(ctx, ctx->nip);
3827 }
3828 gen_update_cfar(ctx, ctx->nip);
3829 gen_goto_tb(ctx, 0, target);
3830 }
3831
3832 #define BCOND_IM 0
3833 #define BCOND_LR 1
3834 #define BCOND_CTR 2
3835 #define BCOND_TAR 3
3836
3837 static inline void gen_bcond(DisasContext *ctx, int type)
3838 {
3839 uint32_t bo = BO(ctx->opcode);
3840 int l1;
3841 TCGv target;
3842
3843 ctx->exception = POWERPC_EXCP_BRANCH;
3844 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3845 target = tcg_temp_local_new();
3846 if (type == BCOND_CTR)
3847 tcg_gen_mov_tl(target, cpu_ctr);
3848 else if (type == BCOND_TAR)
3849 gen_load_spr(target, SPR_TAR);
3850 else
3851 tcg_gen_mov_tl(target, cpu_lr);
3852 } else {
3853 TCGV_UNUSED(target);
3854 }
3855 if (LK(ctx->opcode))
3856 gen_setlr(ctx, ctx->nip);
3857 l1 = gen_new_label();
3858 if ((bo & 0x4) == 0) {
3859 /* Decrement and test CTR */
3860 TCGv temp = tcg_temp_new();
3861 if (unlikely(type == BCOND_CTR)) {
3862 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3863 return;
3864 }
3865 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3866 if (NARROW_MODE(ctx)) {
3867 tcg_gen_ext32u_tl(temp, cpu_ctr);
3868 } else {
3869 tcg_gen_mov_tl(temp, cpu_ctr);
3870 }
3871 if (bo & 0x2) {
3872 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3873 } else {
3874 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3875 }
3876 tcg_temp_free(temp);
3877 }
3878 if ((bo & 0x10) == 0) {
3879 /* Test CR */
3880 uint32_t bi = BI(ctx->opcode);
3881 uint32_t mask = 1 << (3 - (bi & 0x03));
3882 TCGv_i32 temp = tcg_temp_new_i32();
3883
3884 if (bo & 0x8) {
3885 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3886 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3887 } else {
3888 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3889 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3890 }
3891 tcg_temp_free_i32(temp);
3892 }
3893 gen_update_cfar(ctx, ctx->nip);
3894 if (type == BCOND_IM) {
3895 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3896 if (likely(AA(ctx->opcode) == 0)) {
3897 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3898 } else {
3899 gen_goto_tb(ctx, 0, li);
3900 }
3901 gen_set_label(l1);
3902 gen_goto_tb(ctx, 1, ctx->nip);
3903 } else {
3904 if (NARROW_MODE(ctx)) {
3905 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3906 } else {
3907 tcg_gen_andi_tl(cpu_nip, target, ~3);
3908 }
3909 tcg_gen_exit_tb(0);
3910 gen_set_label(l1);
3911 gen_update_nip(ctx, ctx->nip);
3912 tcg_gen_exit_tb(0);
3913 }
3914 }
3915
3916 static void gen_bc(DisasContext *ctx)
3917 {
3918 gen_bcond(ctx, BCOND_IM);
3919 }
3920
3921 static void gen_bcctr(DisasContext *ctx)
3922 {
3923 gen_bcond(ctx, BCOND_CTR);
3924 }
3925
3926 static void gen_bclr(DisasContext *ctx)
3927 {
3928 gen_bcond(ctx, BCOND_LR);
3929 }
3930
3931 static void gen_bctar(DisasContext *ctx)
3932 {
3933 gen_bcond(ctx, BCOND_TAR);
3934 }
3935
3936 /*** Condition register logical ***/
3937 #define GEN_CRLOGIC(name, tcg_op, opc) \
3938 static void glue(gen_, name)(DisasContext *ctx) \
3939 { \
3940 uint8_t bitmask; \
3941 int sh; \
3942 TCGv_i32 t0, t1; \
3943 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3944 t0 = tcg_temp_new_i32(); \
3945 if (sh > 0) \
3946 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3947 else if (sh < 0) \
3948 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3949 else \
3950 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3951 t1 = tcg_temp_new_i32(); \
3952 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3953 if (sh > 0) \
3954 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3955 else if (sh < 0) \
3956 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3957 else \
3958 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3959 tcg_op(t0, t0, t1); \
3960 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3961 tcg_gen_andi_i32(t0, t0, bitmask); \
3962 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3963 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3964 tcg_temp_free_i32(t0); \
3965 tcg_temp_free_i32(t1); \
3966 }
3967
3968 /* crand */
3969 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3970 /* crandc */
3971 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3972 /* creqv */
3973 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3974 /* crnand */
3975 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3976 /* crnor */
3977 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3978 /* cror */
3979 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3980 /* crorc */
3981 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3982 /* crxor */
3983 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3984
3985 /* mcrf */
3986 static void gen_mcrf(DisasContext *ctx)
3987 {
3988 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3989 }
3990
3991 /*** System linkage ***/
3992
3993 /* rfi (mem_idx only) */
3994 static void gen_rfi(DisasContext *ctx)
3995 {
3996 #if defined(CONFIG_USER_ONLY)
3997 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3998 #else
3999 /* Restore CPU state */
4000 if (unlikely(!ctx->mem_idx)) {
4001 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4002 return;
4003 }
4004 gen_update_cfar(ctx, ctx->nip);
4005 gen_helper_rfi(cpu_env);
4006 gen_sync_exception(ctx);
4007 #endif
4008 }
4009
4010 #if defined(TARGET_PPC64)
4011 static void gen_rfid(DisasContext *ctx)
4012 {
4013 #if defined(CONFIG_USER_ONLY)
4014 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4015 #else
4016 /* Restore CPU state */
4017 if (unlikely(!ctx->mem_idx)) {
4018 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4019 return;
4020 }
4021 gen_update_cfar(ctx, ctx->nip);
4022 gen_helper_rfid(cpu_env);
4023 gen_sync_exception(ctx);
4024 #endif
4025 }
4026
4027 static void gen_hrfid(DisasContext *ctx)
4028 {
4029 #if defined(CONFIG_USER_ONLY)
4030 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4031 #else
4032 /* Restore CPU state */
4033 if (unlikely(ctx->mem_idx <= 1)) {
4034 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4035 return;
4036 }
4037 gen_helper_hrfid(cpu_env);
4038 gen_sync_exception(ctx);
4039 #endif
4040 }
4041 #endif
4042
4043 /* sc */
4044 #if defined(CONFIG_USER_ONLY)
4045 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4046 #else
4047 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4048 #endif
4049 static void gen_sc(DisasContext *ctx)
4050 {
4051 uint32_t lev;
4052
4053 lev = (ctx->opcode >> 5) & 0x7F;
4054 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4055 }
4056
4057 /*** Trap ***/
4058
4059 /* tw */
4060 static void gen_tw(DisasContext *ctx)
4061 {
4062 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4063 /* Update the nip since this might generate a trap exception */
4064 gen_update_nip(ctx, ctx->nip);
4065 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4066 t0);
4067 tcg_temp_free_i32(t0);
4068 }
4069
4070 /* twi */
4071 static void gen_twi(DisasContext *ctx)
4072 {
4073 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4074 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4075 /* Update the nip since this might generate a trap exception */
4076 gen_update_nip(ctx, ctx->nip);
4077 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4078 tcg_temp_free(t0);
4079 tcg_temp_free_i32(t1);
4080 }
4081
4082 #if defined(TARGET_PPC64)
4083 /* td */
4084 static void gen_td(DisasContext *ctx)
4085 {
4086 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4087 /* Update the nip since this might generate a trap exception */
4088 gen_update_nip(ctx, ctx->nip);
4089 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4090 t0);
4091 tcg_temp_free_i32(t0);
4092 }
4093
4094 /* tdi */
4095 static void gen_tdi(DisasContext *ctx)
4096 {
4097 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4098 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4099 /* Update the nip since this might generate a trap exception */
4100 gen_update_nip(ctx, ctx->nip);
4101 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4102 tcg_temp_free(t0);
4103 tcg_temp_free_i32(t1);
4104 }
4105 #endif
4106
4107 /*** Processor control ***/
4108
4109 static void gen_read_xer(TCGv dst)
4110 {
4111 TCGv t0 = tcg_temp_new();
4112 TCGv t1 = tcg_temp_new();
4113 TCGv t2 = tcg_temp_new();
4114 tcg_gen_mov_tl(dst, cpu_xer);
4115 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4116 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4117 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4118 tcg_gen_or_tl(t0, t0, t1);
4119 tcg_gen_or_tl(dst, dst, t2);
4120 tcg_gen_or_tl(dst, dst, t0);
4121 tcg_temp_free(t0);
4122 tcg_temp_free(t1);
4123 tcg_temp_free(t2);
4124 }
4125
4126 static void gen_write_xer(TCGv src)
4127 {
4128 tcg_gen_andi_tl(cpu_xer, src,
4129 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4130 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4131 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4132 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4133 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4134 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4135 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4136 }
4137
4138 /* mcrxr */
4139 static void gen_mcrxr(DisasContext *ctx)
4140 {
4141 TCGv_i32 t0 = tcg_temp_new_i32();
4142 TCGv_i32 t1 = tcg_temp_new_i32();
4143 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4144
4145 tcg_gen_trunc_tl_i32(t0, cpu_so);
4146 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4147 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4148 tcg_gen_shri_i32(t0, t0, 2);
4149 tcg_gen_shri_i32(t1, t1, 1);
4150 tcg_gen_or_i32(dst, dst, t0);
4151 tcg_gen_or_i32(dst, dst, t1);
4152 tcg_temp_free_i32(t0);
4153 tcg_temp_free_i32(t1);
4154
4155 tcg_gen_movi_tl(cpu_so, 0);
4156 tcg_gen_movi_tl(cpu_ov, 0);
4157 tcg_gen_movi_tl(cpu_ca, 0);
4158 }
4159
4160 /* mfcr mfocrf */
4161 static void gen_mfcr(DisasContext *ctx)
4162 {
4163 uint32_t crm, crn;
4164
4165 if (likely(ctx->opcode & 0x00100000)) {
4166 crm = CRM(ctx->opcode);
4167 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4168 crn = ctz32 (crm);
4169 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4170 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4171 cpu_gpr[rD(ctx->opcode)], crn * 4);
4172 }
4173 } else {
4174 TCGv_i32 t0 = tcg_temp_new_i32();
4175 tcg_gen_mov_i32(t0, cpu_crf[0]);
4176 tcg_gen_shli_i32(t0, t0, 4);
4177 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4178 tcg_gen_shli_i32(t0, t0, 4);
4179 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4180 tcg_gen_shli_i32(t0, t0, 4);
4181 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4182 tcg_gen_shli_i32(t0, t0, 4);
4183 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4184 tcg_gen_shli_i32(t0, t0, 4);
4185 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4186 tcg_gen_shli_i32(t0, t0, 4);
4187 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4188 tcg_gen_shli_i32(t0, t0, 4);
4189 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4190 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4191 tcg_temp_free_i32(t0);
4192 }
4193 }
4194
4195 /* mfmsr */
4196 static void gen_mfmsr(DisasContext *ctx)
4197 {
4198 #if defined(CONFIG_USER_ONLY)
4199 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4200 #else
4201 if (unlikely(!ctx->mem_idx)) {
4202 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4203 return;
4204 }
4205 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4206 #endif
4207 }
4208
4209 static void spr_noaccess(void *opaque, int gprn, int sprn)
4210 {
4211 #if 0
4212 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4213 printf("ERROR: try to access SPR %d !\n", sprn);
4214 #endif
4215 }
4216 #define SPR_NOACCESS (&spr_noaccess)
4217
4218 /* mfspr */
4219 static inline void gen_op_mfspr(DisasContext *ctx)
4220 {
4221 void (*read_cb)(void *opaque, int gprn, int sprn);
4222 uint32_t sprn = SPR(ctx->opcode);
4223
4224 #if !defined(CONFIG_USER_ONLY)
4225 if (ctx->mem_idx == 2)
4226 read_cb = ctx->spr_cb[sprn].hea_read;
4227 else if (ctx->mem_idx)
4228 read_cb = ctx->spr_cb[sprn].oea_read;
4229 else
4230 #endif
4231 read_cb = ctx->spr_cb[sprn].uea_read;
4232 if (likely(read_cb != NULL)) {
4233 if (likely(read_cb != SPR_NOACCESS)) {
4234 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4235 } else {
4236 /* Privilege exception */
4237 /* This is a hack to avoid warnings when running Linux:
4238 * this OS breaks the PowerPC virtualisation model,
4239 * allowing userland application to read the PVR
4240 */
4241 if (sprn != SPR_PVR) {
4242 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4243 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4244 printf("Trying to read privileged spr %d (0x%03x) at "
4245 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4246 }
4247 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4248 }
4249 } else {
4250 /* Not defined */
4251 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4252 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4253 printf("Trying to read invalid spr %d (0x%03x) at "
4254 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4255 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4256 }
4257 }
4258
4259 static void gen_mfspr(DisasContext *ctx)
4260 {
4261 gen_op_mfspr(ctx);
4262 }
4263
4264 /* mftb */
4265 static void gen_mftb(DisasContext *ctx)
4266 {
4267 gen_op_mfspr(ctx);
4268 }
4269
4270 /* mtcrf mtocrf*/
4271 static void gen_mtcrf(DisasContext *ctx)
4272 {
4273 uint32_t crm, crn;
4274
4275 crm = CRM(ctx->opcode);
4276 if (likely((ctx->opcode & 0x00100000))) {
4277 if (crm && ((crm & (crm - 1)) == 0)) {
4278 TCGv_i32 temp = tcg_temp_new_i32();
4279 crn = ctz32 (crm);
4280 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4281 tcg_gen_shri_i32(temp, temp, crn * 4);
4282 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4283 tcg_temp_free_i32(temp);
4284 }
4285 } else {
4286 TCGv_i32 temp = tcg_temp_new_i32();
4287 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4288 for (crn = 0 ; crn < 8 ; crn++) {
4289 if (crm & (1 << crn)) {
4290 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4291 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4292 }
4293 }
4294 tcg_temp_free_i32(temp);
4295 }
4296 }
4297
4298 /* mtmsr */
4299 #if defined(TARGET_PPC64)
4300 static void gen_mtmsrd(DisasContext *ctx)
4301 {
4302 #if defined(CONFIG_USER_ONLY)
4303 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4304 #else
4305 if (unlikely(!ctx->mem_idx)) {
4306 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4307 return;
4308 }
4309 if (ctx->opcode & 0x00010000) {
4310 /* Special form that does not need any synchronisation */
4311 TCGv t0 = tcg_temp_new();
4312 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4313 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4314 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4315 tcg_temp_free(t0);
4316 } else {
4317 /* XXX: we need to update nip before the store
4318 * if we enter power saving mode, we will exit the loop
4319 * directly from ppc_store_msr
4320 */
4321 gen_update_nip(ctx, ctx->nip);
4322 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4323 /* Must stop the translation as machine state (may have) changed */
4324 /* Note that mtmsr is not always defined as context-synchronizing */
4325 gen_stop_exception(ctx);
4326 }
4327 #endif
4328 }
4329 #endif
4330
4331 static void gen_mtmsr(DisasContext *ctx)
4332 {
4333 #if defined(CONFIG_USER_ONLY)
4334 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4335 #else
4336 if (unlikely(!ctx->mem_idx)) {
4337 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4338 return;
4339 }
4340 if (ctx->opcode & 0x00010000) {
4341 /* Special form that does not need any synchronisation */
4342 TCGv t0 = tcg_temp_new();
4343 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4344 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4345 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4346 tcg_temp_free(t0);
4347 } else {
4348 TCGv msr = tcg_temp_new();
4349
4350 /* XXX: we need to update nip before the store
4351 * if we enter power saving mode, we will exit the loop
4352 * directly from ppc_store_msr
4353 */
4354 gen_update_nip(ctx, ctx->nip);
4355 #if defined(TARGET_PPC64)
4356 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4357 #else
4358 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4359 #endif
4360 gen_helper_store_msr(cpu_env, msr);
4361 /* Must stop the translation as machine state (may have) changed */
4362 /* Note that mtmsr is not always defined as context-synchronizing */
4363 gen_stop_exception(ctx);
4364 }
4365 #endif
4366 }
4367
4368 /* mtspr */
4369 static void gen_mtspr(DisasContext *ctx)
4370 {
4371 void (*write_cb)(void *opaque, int sprn, int gprn);
4372 uint32_t sprn = SPR(ctx->opcode);
4373
4374 #if !defined(CONFIG_USER_ONLY)
4375 if (ctx->mem_idx == 2)
4376 write_cb = ctx->spr_cb[sprn].hea_write;
4377 else if (ctx->mem_idx)
4378 write_cb = ctx->spr_cb[sprn].oea_write;
4379 else
4380 #endif
4381 write_cb = ctx->spr_cb[sprn].uea_write;
4382 if (likely(write_cb != NULL)) {
4383 if (likely(write_cb != SPR_NOACCESS)) {
4384 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4385 } else {
4386 /* Privilege exception */
4387 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4388 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4389 printf("Trying to write privileged spr %d (0x%03x) at "
4390 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4391 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4392 }
4393 } else {
4394 /* Not defined */
4395 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4396 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4397 printf("Trying to write invalid spr %d (0x%03x) at "
4398 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4399 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4400 }
4401 }
4402
4403 /*** Cache management ***/
4404
4405 /* dcbf */
4406 static void gen_dcbf(DisasContext *ctx)
4407 {
4408 /* XXX: specification says this is treated as a load by the MMU */
4409 TCGv t0;
4410 gen_set_access_type(ctx, ACCESS_CACHE);
4411 t0 = tcg_temp_new();
4412 gen_addr_reg_index(ctx, t0);
4413 gen_qemu_ld8u(ctx, t0, t0);
4414 tcg_temp_free(t0);
4415 }
4416
4417 /* dcbi (Supervisor only) */
4418 static void gen_dcbi(DisasContext *ctx)
4419 {
4420 #if defined(CONFIG_USER_ONLY)
4421 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4422 #else
4423 TCGv EA, val;
4424 if (unlikely(!ctx->mem_idx)) {
4425 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4426 return;
4427 }
4428 EA = tcg_temp_new();
4429 gen_set_access_type(ctx, ACCESS_CACHE);
4430 gen_addr_reg_index(ctx, EA);
4431 val = tcg_temp_new();
4432 /* XXX: specification says this should be treated as a store by the MMU */
4433 gen_qemu_ld8u(ctx, val, EA);
4434 gen_qemu_st8(ctx, val, EA);
4435 tcg_temp_free(val);
4436 tcg_temp_free(EA);
4437 #endif
4438 }
4439
4440 /* dcdst */
4441 static void gen_dcbst(DisasContext *ctx)
4442 {
4443 /* XXX: specification say this is treated as a load by the MMU */
4444 TCGv t0;
4445 gen_set_access_type(ctx, ACCESS_CACHE);
4446 t0 = tcg_temp_new();
4447 gen_addr_reg_index(ctx, t0);
4448 gen_qemu_ld8u(ctx, t0, t0);
4449 tcg_temp_free(t0);
4450 }
4451
4452 /* dcbt */
4453 static void gen_dcbt(DisasContext *ctx)
4454 {
4455 /* interpreted as no-op */
4456 /* XXX: specification say this is treated as a load by the MMU
4457 * but does not generate any exception
4458 */
4459 }
4460
4461 /* dcbtst */
4462 static void gen_dcbtst(DisasContext *ctx)
4463 {
4464 /* interpreted as no-op */
4465 /* XXX: specification say this is treated as a load by the MMU
4466 * but does not generate any exception
4467 */
4468 }
4469
4470 /* dcbz */
4471 static void gen_dcbz(DisasContext *ctx)
4472 {
4473 TCGv tcgv_addr;
4474 TCGv_i32 tcgv_is_dcbzl;
4475 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4476
4477 gen_set_access_type(ctx, ACCESS_CACHE);
4478 /* NIP cannot be restored if the memory exception comes from an helper */
4479 gen_update_nip(ctx, ctx->nip - 4);
4480 tcgv_addr = tcg_temp_new();
4481 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4482
4483 gen_addr_reg_index(ctx, tcgv_addr);
4484 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4485
4486 tcg_temp_free(tcgv_addr);
4487 tcg_temp_free_i32(tcgv_is_dcbzl);
4488 }
4489
4490 /* dst / dstt */
4491 static void gen_dst(DisasContext *ctx)
4492 {
4493 if (rA(ctx->opcode) == 0) {
4494 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4495 } else {
4496 /* interpreted as no-op */
4497 }
4498 }
4499
4500 /* dstst /dststt */
4501 static void gen_dstst(DisasContext *ctx)
4502 {
4503 if (rA(ctx->opcode) == 0) {
4504 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4505 } else {
4506 /* interpreted as no-op */
4507 }
4508
4509 }
4510
4511 /* dss / dssall */
4512 static void gen_dss(DisasContext *ctx)
4513 {
4514 /* interpreted as no-op */
4515 }
4516
4517 /* icbi */
4518 static void gen_icbi(DisasContext *ctx)
4519 {
4520 TCGv t0;
4521 gen_set_access_type(ctx, ACCESS_CACHE);
4522 /* NIP cannot be restored if the memory exception comes from an helper */
4523 gen_update_nip(ctx, ctx->nip - 4);
4524 t0 = tcg_temp_new();
4525 gen_addr_reg_index(ctx, t0);
4526 gen_helper_icbi(cpu_env, t0);
4527 tcg_temp_free(t0);
4528 }
4529
4530 /* Optional: */
4531 /* dcba */
4532 static void gen_dcba(DisasContext *ctx)
4533 {
4534 /* interpreted as no-op */
4535 /* XXX: specification say this is treated as a store by the MMU
4536 * but does not generate any exception
4537 */
4538 }
4539
4540 /*** Segment register manipulation ***/
4541 /* Supervisor only: */
4542
4543 /* mfsr */
4544 static void gen_mfsr(DisasContext *ctx)
4545 {
4546 #if defined(CONFIG_USER_ONLY)
4547 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4548 #else
4549 TCGv t0;
4550 if (unlikely(!ctx->mem_idx)) {
4551 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4552 return;
4553 }
4554 t0 = tcg_const_tl(SR(ctx->opcode));
4555 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4556 tcg_temp_free(t0);
4557 #endif
4558 }
4559
4560 /* mfsrin */
4561 static void gen_mfsrin(DisasContext *ctx)
4562 {
4563 #if defined(CONFIG_USER_ONLY)
4564 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4565 #else
4566 TCGv t0;
4567 if (unlikely(!ctx->mem_idx)) {
4568 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4569 return;
4570 }
4571 t0 = tcg_temp_new();
4572 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4573 tcg_gen_andi_tl(t0, t0, 0xF);
4574 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4575 tcg_temp_free(t0);
4576 #endif
4577 }
4578
4579 /* mtsr */
4580 static void gen_mtsr(DisasContext *ctx)
4581 {
4582 #if defined(CONFIG_USER_ONLY)
4583 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4584 #else
4585 TCGv t0;
4586 if (unlikely(!ctx->mem_idx)) {
4587 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4588 return;
4589 }
4590 t0 = tcg_const_tl(SR(ctx->opcode));
4591 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4592 tcg_temp_free(t0);
4593 #endif
4594 }
4595
4596 /* mtsrin */
4597 static void gen_mtsrin(DisasContext *ctx)
4598 {
4599 #if defined(CONFIG_USER_ONLY)
4600 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4601 #else
4602 TCGv t0;
4603 if (unlikely(!ctx->mem_idx)) {
4604 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4605 return;
4606 }
4607 t0 = tcg_temp_new();
4608 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4609 tcg_gen_andi_tl(t0, t0, 0xF);
4610 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4611 tcg_temp_free(t0);
4612 #endif
4613 }
4614
4615 #if defined(TARGET_PPC64)
4616 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4617
4618 /* mfsr */
4619 static void gen_mfsr_64b(DisasContext *ctx)
4620 {
4621 #if defined(CONFIG_USER_ONLY)
4622 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4623 #else
4624 TCGv t0;
4625 if (unlikely(!ctx->mem_idx)) {
4626 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4627 return;
4628 }
4629 t0 = tcg_const_tl(SR(ctx->opcode));
4630 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4631 tcg_temp_free(t0);
4632 #endif
4633 }
4634
4635 /* mfsrin */
4636 static void gen_mfsrin_64b(DisasContext *ctx)
4637 {
4638 #if defined(CONFIG_USER_ONLY)
4639 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4640 #else
4641 TCGv t0;
4642 if (unlikely(!ctx->mem_idx)) {
4643 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4644 return;
4645 }
4646 t0 = tcg_temp_new();
4647 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4648 tcg_gen_andi_tl(t0, t0, 0xF);
4649 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4650 tcg_temp_free(t0);
4651 #endif
4652 }
4653
4654 /* mtsr */
4655 static void gen_mtsr_64b(DisasContext *ctx)
4656 {
4657 #if defined(CONFIG_USER_ONLY)
4658 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4659 #else
4660 TCGv t0;
4661 if (unlikely(!ctx->mem_idx)) {
4662 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4663 return;
4664 }
4665 t0 = tcg_const_tl(SR(ctx->opcode));
4666 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4667 tcg_temp_free(t0);
4668 #endif
4669 }
4670
4671 /* mtsrin */
4672 static void gen_mtsrin_64b(DisasContext *ctx)
4673 {
4674 #if defined(CONFIG_USER_ONLY)
4675 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4676 #else
4677 TCGv t0;
4678 if (unlikely(!ctx->mem_idx)) {
4679 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4680 return;
4681 }
4682 t0 = tcg_temp_new();
4683 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4684 tcg_gen_andi_tl(t0, t0, 0xF);
4685 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4686 tcg_temp_free(t0);
4687 #endif
4688 }
4689
4690 /* slbmte */
4691 static void gen_slbmte(DisasContext *ctx)
4692 {
4693 #if defined(CONFIG_USER_ONLY)
4694 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4695 #else
4696 if (unlikely(!ctx->mem_idx)) {
4697 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4698 return;
4699 }
4700 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4701 cpu_gpr[rS(ctx->opcode)]);
4702 #endif
4703 }
4704
4705 static void gen_slbmfee(DisasContext *ctx)
4706 {
4707 #if defined(CONFIG_USER_ONLY)
4708 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4709 #else
4710 if (unlikely(!ctx->mem_idx)) {
4711 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4712 return;
4713 }
4714 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4715 cpu_gpr[rB(ctx->opcode)]);
4716 #endif
4717 }
4718
4719 static void gen_slbmfev(DisasContext *ctx)
4720 {
4721 #if defined(CONFIG_USER_ONLY)
4722 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4723 #else
4724 if (unlikely(!ctx->mem_idx)) {
4725 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4726 return;
4727 }
4728 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4729 cpu_gpr[rB(ctx->opcode)]);
4730 #endif
4731 }
4732 #endif /* defined(TARGET_PPC64) */
4733
4734 /*** Lookaside buffer management ***/
4735 /* Optional & mem_idx only: */
4736
4737 /* tlbia */
4738 static void gen_tlbia(DisasContext *ctx)
4739 {
4740 #if defined(CONFIG_USER_ONLY)
4741 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4742 #else
4743 if (unlikely(!ctx->mem_idx)) {
4744 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4745 return;
4746 }
4747 gen_helper_tlbia(cpu_env);
4748 #endif
4749 }
4750
4751 /* tlbiel */
4752 static void gen_tlbiel(DisasContext *ctx)
4753 {
4754 #if defined(CONFIG_USER_ONLY)
4755 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4756 #else
4757 if (unlikely(!ctx->mem_idx)) {
4758 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4759 return;
4760 }
4761 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4762 #endif
4763 }
4764
4765 /* tlbie */
4766 static void gen_tlbie(DisasContext *ctx)
4767 {
4768 #if defined(CONFIG_USER_ONLY)
4769 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4770 #else
4771 if (unlikely(!ctx->mem_idx)) {
4772 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4773 return;
4774 }
4775 if (NARROW_MODE(ctx)) {
4776 TCGv t0 = tcg_temp_new();
4777 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4778 gen_helper_tlbie(cpu_env, t0);
4779 tcg_temp_free(t0);
4780 } else {
4781 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4782 }
4783 #endif
4784 }
4785
4786 /* tlbsync */
4787 static void gen_tlbsync(DisasContext *ctx)
4788 {
4789 #if defined(CONFIG_USER_ONLY)
4790 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4791 #else
4792 if (unlikely(!ctx->mem_idx)) {
4793 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4794 return;
4795 }
4796 /* This has no effect: it should ensure that all previous
4797 * tlbie have completed
4798 */
4799 gen_stop_exception(ctx);
4800 #endif
4801 }
4802
4803 #if defined(TARGET_PPC64)
4804 /* slbia */
4805 static void gen_slbia(DisasContext *ctx)
4806 {
4807 #if defined(CONFIG_USER_ONLY)
4808 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4809 #else
4810 if (unlikely(!ctx->mem_idx)) {
4811 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4812 return;
4813 }
4814 gen_helper_slbia(cpu_env);
4815 #endif
4816 }
4817
4818 /* slbie */
4819 static void gen_slbie(DisasContext *ctx)
4820 {
4821 #if defined(CONFIG_USER_ONLY)
4822 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4823 #else
4824 if (unlikely(!ctx->mem_idx)) {
4825 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4826 return;
4827 }
4828 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4829 #endif
4830 }
4831 #endif
4832
4833 /*** External control ***/
4834 /* Optional: */
4835
4836 /* eciwx */
4837 static void gen_eciwx(DisasContext *ctx)
4838 {
4839 TCGv t0;
4840 /* Should check EAR[E] ! */
4841 gen_set_access_type(ctx, ACCESS_EXT);
4842 t0 = tcg_temp_new();
4843 gen_addr_reg_index(ctx, t0);
4844 gen_check_align(ctx, t0, 0x03);
4845 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4846 tcg_temp_free(t0);
4847 }
4848
4849 /* ecowx */
4850 static void gen_ecowx(DisasContext *ctx)
4851 {
4852 TCGv t0;
4853 /* Should check EAR[E] ! */
4854 gen_set_access_type(ctx, ACCESS_EXT);
4855 t0 = tcg_temp_new();
4856 gen_addr_reg_index(ctx, t0);
4857 gen_check_align(ctx, t0, 0x03);
4858 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4859 tcg_temp_free(t0);
4860 }
4861
4862 /* PowerPC 601 specific instructions */
4863
4864 /* abs - abs. */
4865 static void gen_abs(DisasContext *ctx)
4866 {
4867 int l1 = gen_new_label();
4868 int l2 = gen_new_label();
4869 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4870 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4871 tcg_gen_br(l2);
4872 gen_set_label(l1);
4873 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4874 gen_set_label(l2);
4875 if (unlikely(Rc(ctx->opcode) != 0))
4876 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4877 }
4878
4879 /* abso - abso. */
4880 static void gen_abso(DisasContext *ctx)
4881 {
4882 int l1 = gen_new_label();
4883 int l2 = gen_new_label();
4884 int l3 = gen_new_label();
4885 /* Start with XER OV disabled, the most likely case */
4886 tcg_gen_movi_tl(cpu_ov, 0);
4887 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4888 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4889 tcg_gen_movi_tl(cpu_ov, 1);
4890 tcg_gen_movi_tl(cpu_so, 1);
4891 tcg_gen_br(l2);
4892 gen_set_label(l1);
4893 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4894 tcg_gen_br(l3);
4895 gen_set_label(l2);
4896 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4897 gen_set_label(l3);
4898 if (unlikely(Rc(ctx->opcode) != 0))
4899 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4900 }
4901
4902 /* clcs */
4903 static void gen_clcs(DisasContext *ctx)
4904 {
4905 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4906 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4907 tcg_temp_free_i32(t0);
4908 /* Rc=1 sets CR0 to an undefined state */
4909 }
4910
4911 /* div - div. */
4912 static void gen_div(DisasContext *ctx)
4913 {
4914 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4915 cpu_gpr[rB(ctx->opcode)]);
4916 if (unlikely(Rc(ctx->opcode) != 0))
4917 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4918 }
4919
4920 /* divo - divo. */
4921 static void gen_divo(DisasContext *ctx)
4922 {
4923 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4924 cpu_gpr[rB(ctx->opcode)]);
4925 if (unlikely(Rc(ctx->opcode) != 0))
4926 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4927 }
4928
4929 /* divs - divs. */
4930 static void gen_divs(DisasContext *ctx)
4931 {
4932 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4933 cpu_gpr[rB(ctx->opcode)]);
4934 if (unlikely(Rc(ctx->opcode) != 0))
4935 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4936 }
4937
4938 /* divso - divso. */
4939 static void gen_divso(DisasContext *ctx)
4940 {
4941 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4942 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4943 if (unlikely(Rc(ctx->opcode) != 0))
4944 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4945 }
4946
4947 /* doz - doz. */
4948 static void gen_doz(DisasContext *ctx)
4949 {
4950 int l1 = gen_new_label();
4951 int l2 = gen_new_label();
4952 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4953 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4954 tcg_gen_br(l2);
4955 gen_set_label(l1);
4956 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4957 gen_set_label(l2);
4958 if (unlikely(Rc(ctx->opcode) != 0))
4959 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4960 }
4961
4962 /* dozo - dozo. */
4963 static void gen_dozo(DisasContext *ctx)
4964 {
4965 int l1 = gen_new_label();
4966 int l2 = gen_new_label();
4967 TCGv t0 = tcg_temp_new();
4968 TCGv t1 = tcg_temp_new();
4969 TCGv t2 = tcg_temp_new();
4970 /* Start with XER OV disabled, the most likely case */
4971 tcg_gen_movi_tl(cpu_ov, 0);
4972 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4973 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4974 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4975 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4976 tcg_gen_andc_tl(t1, t1, t2);
4977 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4978 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4979 tcg_gen_movi_tl(cpu_ov, 1);
4980 tcg_gen_movi_tl(cpu_so, 1);
4981 tcg_gen_br(l2);
4982 gen_set_label(l1);
4983 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4984 gen_set_label(l2);
4985 tcg_temp_free(t0);
4986 tcg_temp_free(t1);
4987 tcg_temp_free(t2);
4988 if (unlikely(Rc(ctx->opcode) != 0))
4989 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4990 }
4991
4992 /* dozi */
4993 static void gen_dozi(DisasContext *ctx)
4994 {
4995 target_long simm = SIMM(ctx->opcode);
4996 int l1 = gen_new_label();
4997 int l2 = gen_new_label();
4998 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4999 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5000 tcg_gen_br(l2);
5001 gen_set_label(l1);
5002 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5003 gen_set_label(l2);
5004 if (unlikely(Rc(ctx->opcode) != 0))
5005 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5006 }
5007
5008 /* lscbx - lscbx. */
5009 static void gen_lscbx(DisasContext *ctx)
5010 {
5011 TCGv t0 = tcg_temp_new();
5012 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5013 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5014 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5015
5016 gen_addr_reg_index(ctx, t0);
5017 /* NIP cannot be restored if the memory exception comes from an helper */
5018 gen_update_nip(ctx, ctx->nip - 4);
5019 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5020 tcg_temp_free_i32(t1);
5021 tcg_temp_free_i32(t2);
5022 tcg_temp_free_i32(t3);
5023 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5024 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5025 if (unlikely(Rc(ctx->opcode) != 0))
5026 gen_set_Rc0(ctx, t0);
5027 tcg_temp_free(t0);
5028 }
5029
5030 /* maskg - maskg. */
5031 static void gen_maskg(DisasContext *ctx)
5032 {
5033 int l1 = gen_new_label();
5034 TCGv t0 = tcg_temp_new();
5035 TCGv t1 = tcg_temp_new();
5036 TCGv t2 = tcg_temp_new();
5037 TCGv t3 = tcg_temp_new();
5038 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5039 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5040 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5041 tcg_gen_addi_tl(t2, t0, 1);
5042 tcg_gen_shr_tl(t2, t3, t2);
5043 tcg_gen_shr_tl(t3, t3, t1);
5044 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5045 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5046 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5047 gen_set_label(l1);
5048 tcg_temp_free(t0);
5049 tcg_temp_free(t1);
5050 tcg_temp_free(t2);
5051 tcg_temp_free(t3);
5052 if (unlikely(Rc(ctx->opcode) != 0))
5053 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5054 }
5055
5056 /* maskir - maskir. */
5057 static void gen_maskir(DisasContext *ctx)
5058 {
5059 TCGv t0 = tcg_temp_new();
5060 TCGv t1 = tcg_temp_new();
5061 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5062 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5063 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5064 tcg_temp_free(t0);
5065 tcg_temp_free(t1);
5066 if (unlikely(Rc(ctx->opcode) != 0))
5067 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5068 }
5069
5070 /* mul - mul. */
5071 static void gen_mul(DisasContext *ctx)
5072 {
5073 TCGv_i64 t0 = tcg_temp_new_i64();
5074 TCGv_i64 t1 = tcg_temp_new_i64();
5075 TCGv t2 = tcg_temp_new();
5076 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5077 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5078 tcg_gen_mul_i64(t0, t0, t1);
5079 tcg_gen_trunc_i64_tl(t2, t0);
5080 gen_store_spr(SPR_MQ, t2);
5081 tcg_gen_shri_i64(t1, t0, 32);
5082 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5083 tcg_temp_free_i64(t0);
5084 tcg_temp_free_i64(t1);
5085 tcg_temp_free(t2);
5086 if (unlikely(Rc(ctx->opcode) != 0))
5087 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5088 }
5089
5090 /* mulo - mulo. */
5091 static void gen_mulo(DisasContext *ctx)
5092 {
5093 int l1 = gen_new_label();
5094 TCGv_i64 t0 = tcg_temp_new_i64();
5095 TCGv_i64 t1 = tcg_temp_new_i64();
5096 TCGv t2 = tcg_temp_new();
5097 /* Start with XER OV disabled, the most likely case */
5098 tcg_gen_movi_tl(cpu_ov, 0);
5099 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5100 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5101 tcg_gen_mul_i64(t0, t0, t1);
5102 tcg_gen_trunc_i64_tl(t2, t0);
5103 gen_store_spr(SPR_MQ, t2);
5104 tcg_gen_shri_i64(t1, t0, 32);
5105 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5106 tcg_gen_ext32s_i64(t1, t0);
5107 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5108 tcg_gen_movi_tl(cpu_ov, 1);
5109 tcg_gen_movi_tl(cpu_so, 1);
5110 gen_set_label(l1);
5111 tcg_temp_free_i64(t0);
5112 tcg_temp_free_i64(t1);
5113 tcg_temp_free(t2);
5114 if (unlikely(Rc(ctx->opcode) != 0))
5115 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5116 }
5117
5118 /* nabs - nabs. */
5119 static void gen_nabs(DisasContext *ctx)
5120 {
5121 int l1 = gen_new_label();
5122 int l2 = gen_new_label();
5123 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5124 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5125 tcg_gen_br(l2);
5126 gen_set_label(l1);
5127 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5128 gen_set_label(l2);
5129 if (unlikely(Rc(ctx->opcode) != 0))
5130 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5131 }
5132
5133 /* nabso - nabso. */
5134 static void gen_nabso(DisasContext *ctx)
5135 {
5136 int l1 = gen_new_label();
5137 int l2 = gen_new_label();
5138 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5139 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5140 tcg_gen_br(l2);
5141 gen_set_label(l1);
5142 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5143 gen_set_label(l2);
5144 /* nabs never overflows */
5145 tcg_gen_movi_tl(cpu_ov, 0);
5146 if (unlikely(Rc(ctx->opcode) != 0))
5147 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5148 }
5149
5150 /* rlmi - rlmi. */
5151 static void gen_rlmi(DisasContext *ctx)
5152 {
5153 uint32_t mb = MB(ctx->opcode);
5154 uint32_t me = ME(ctx->opcode);
5155 TCGv t0 = tcg_temp_new();
5156 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5157 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5158 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5159 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5160 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5161 tcg_temp_free(t0);
5162 if (unlikely(Rc(ctx->opcode) != 0))
5163 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5164 }
5165
5166 /* rrib - rrib. */
5167 static void gen_rrib(DisasContext *ctx)
5168 {
5169 TCGv t0 = tcg_temp_new();
5170 TCGv t1 = tcg_temp_new();
5171 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5172 tcg_gen_movi_tl(t1, 0x80000000);
5173 tcg_gen_shr_tl(t1, t1, t0);
5174 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5175 tcg_gen_and_tl(t0, t0, t1);
5176 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5177 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5178 tcg_temp_free(t0);
5179 tcg_temp_free(t1);
5180 if (unlikely(Rc(ctx->opcode) != 0))
5181 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5182 }
5183
5184 /* sle - sle. */
5185 static void gen_sle(DisasContext *ctx)
5186 {
5187 TCGv t0 = tcg_temp_new();
5188 TCGv t1 = tcg_temp_new();
5189 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5190 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5191 tcg_gen_subfi_tl(t1, 32, t1);
5192 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5193 tcg_gen_or_tl(t1, t0, t1);
5194 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5195 gen_store_spr(SPR_MQ, t1);
5196 tcg_temp_free(t0);
5197 tcg_temp_free(t1);
5198 if (unlikely(Rc(ctx->opcode) != 0))
5199 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5200 }
5201
5202 /* sleq - sleq. */
5203 static void gen_sleq(DisasContext *ctx)
5204 {
5205 TCGv t0 = tcg_temp_new();
5206 TCGv t1 = tcg_temp_new();
5207 TCGv t2 = tcg_temp_new();
5208 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5209 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5210 tcg_gen_shl_tl(t2, t2, t0);
5211 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5212 gen_load_spr(t1, SPR_MQ);
5213 gen_store_spr(SPR_MQ, t0);
5214 tcg_gen_and_tl(t0, t0, t2);
5215 tcg_gen_andc_tl(t1, t1, t2);
5216 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5217 tcg_temp_free(t0);
5218 tcg_temp_free(t1);
5219 tcg_temp_free(t2);
5220 if (unlikely(Rc(ctx->opcode) != 0))
5221 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5222 }
5223
5224 /* sliq - sliq. */
5225 static void gen_sliq(DisasContext *ctx)
5226 {
5227 int sh = SH(ctx->opcode);
5228 TCGv t0 = tcg_temp_new();
5229 TCGv t1 = tcg_temp_new();
5230 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5231 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5232 tcg_gen_or_tl(t1, t0, t1);
5233 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5234 gen_store_spr(SPR_MQ, t1);
5235 tcg_temp_free(t0);
5236 tcg_temp_free(t1);
5237 if (unlikely(Rc(ctx->opcode) != 0))
5238 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5239 }
5240
5241 /* slliq - slliq. */
5242 static void gen_slliq(DisasContext *ctx)
5243 {
5244 int sh = SH(ctx->opcode);
5245 TCGv t0 = tcg_temp_new();
5246 TCGv t1 = tcg_temp_new();
5247 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5248 gen_load_spr(t1, SPR_MQ);
5249 gen_store_spr(SPR_MQ, t0);
5250 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5251 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5252 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5253 tcg_temp_free(t0);
5254 tcg_temp_free(t1);
5255 if (unlikely(Rc(ctx->opcode) != 0))
5256 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5257 }
5258
5259 /* sllq - sllq. */
5260 static void gen_sllq(DisasContext *ctx)
5261 {
5262 int l1 = gen_new_label();
5263 int l2 = gen_new_label();
5264 TCGv t0 = tcg_temp_local_new();
5265 TCGv t1 = tcg_temp_local_new();
5266 TCGv t2 = tcg_temp_local_new();
5267 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5268 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5269 tcg_gen_shl_tl(t1, t1, t2);
5270 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5271 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5272 gen_load_spr(t0, SPR_MQ);
5273 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5274 tcg_gen_br(l2);
5275 gen_set_label(l1);
5276 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5277 gen_load_spr(t2, SPR_MQ);
5278 tcg_gen_andc_tl(t1, t2, t1);
5279 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5280 gen_set_label(l2);
5281 tcg_temp_free(t0);
5282 tcg_temp_free(t1);
5283 tcg_temp_free(t2);
5284 if (unlikely(Rc(ctx->opcode) != 0))
5285 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5286 }
5287
5288 /* slq - slq. */
5289 static void gen_slq(DisasContext *ctx)
5290 {
5291 int l1 = gen_new_label();
5292 TCGv t0 = tcg_temp_new();
5293 TCGv t1 = tcg_temp_new();
5294 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5295 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5296 tcg_gen_subfi_tl(t1, 32, t1);
5297 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5298 tcg_gen_or_tl(t1, t0, t1);
5299 gen_store_spr(SPR_MQ, t1);
5300 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5301 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5302 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5303 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5304 gen_set_label(l1);
5305 tcg_temp_free(t0);
5306 tcg_temp_free(t1);
5307 if (unlikely(Rc(ctx->opcode) != 0))
5308 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5309 }
5310
5311 /* sraiq - sraiq. */
5312 static void gen_sraiq(DisasContext *ctx)
5313 {
5314 int sh = SH(ctx->opcode);
5315 int l1 = gen_new_label();
5316 TCGv t0 = tcg_temp_new();
5317 TCGv t1 = tcg_temp_new();
5318 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5319 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5320 tcg_gen_or_tl(t0, t0, t1);
5321 gen_store_spr(SPR_MQ, t0);
5322 tcg_gen_movi_tl(cpu_ca, 0);
5323 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5324 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5325 tcg_gen_movi_tl(cpu_ca, 1);
5326 gen_set_label(l1);
5327 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5328 tcg_temp_free(t0);
5329 tcg_temp_free(t1);
5330 if (unlikely(Rc(ctx->opcode) != 0))
5331 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5332 }
5333
5334 /* sraq - sraq. */
5335 static void gen_sraq(DisasContext *ctx)
5336 {
5337 int l1 = gen_new_label();
5338 int l2 = gen_new_label();
5339 TCGv t0 = tcg_temp_new();
5340 TCGv t1 = tcg_temp_local_new();
5341 TCGv t2 = tcg_temp_local_new();
5342 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5343 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5344 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5345 tcg_gen_subfi_tl(t2, 32, t2);
5346 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5347 tcg_gen_or_tl(t0, t0, t2);
5348 gen_store_spr(SPR_MQ, t0);
5349 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5350 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5351 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5352 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5353 gen_set_label(l1);
5354 tcg_temp_free(t0);
5355 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5356 tcg_gen_movi_tl(cpu_ca, 0);
5357 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5358 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5359 tcg_gen_movi_tl(cpu_ca, 1);
5360 gen_set_label(l2);
5361 tcg_temp_free(t1);
5362 tcg_temp_free(t2);
5363 if (unlikely(Rc(ctx->opcode) != 0))
5364 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5365 }
5366
5367 /* sre - sre. */
5368 static void gen_sre(DisasContext *ctx)
5369 {
5370 TCGv t0 = tcg_temp_new();
5371 TCGv t1 = tcg_temp_new();
5372 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5373 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5374 tcg_gen_subfi_tl(t1, 32, t1);
5375 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5376 tcg_gen_or_tl(t1, t0, t1);
5377 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5378 gen_store_spr(SPR_MQ, t1);
5379 tcg_temp_free(t0);
5380 tcg_temp_free(t1);
5381 if (unlikely(Rc(ctx->opcode) != 0))
5382 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5383 }
5384
5385 /* srea - srea. */
5386 static void gen_srea(DisasContext *ctx)
5387 {
5388 TCGv t0 = tcg_temp_new();
5389 TCGv t1 = tcg_temp_new();
5390 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5391 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5392 gen_store_spr(SPR_MQ, t0);
5393 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5394 tcg_temp_free(t0);
5395 tcg_temp_free(t1);
5396 if (unlikely(Rc(ctx->opcode) != 0))
5397 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5398 }
5399
5400 /* sreq */
5401 static void gen_sreq(DisasContext *ctx)
5402 {
5403 TCGv t0 = tcg_temp_new();
5404 TCGv t1 = tcg_temp_new();
5405 TCGv t2 = tcg_temp_new();
5406 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5407 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5408 tcg_gen_shr_tl(t1, t1, t0);
5409 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5410 gen_load_spr(t2, SPR_MQ);
5411 gen_store_spr(SPR_MQ, t0);
5412 tcg_gen_and_tl(t0, t0, t1);
5413 tcg_gen_andc_tl(t2, t2, t1);
5414 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5415 tcg_temp_free(t0);
5416 tcg_temp_free(t1);
5417 tcg_temp_free(t2);
5418 if (unlikely(Rc(ctx->opcode) != 0))
5419 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5420 }
5421
5422 /* sriq */
5423 static void gen_sriq(DisasContext *ctx)
5424 {
5425 int sh = SH(ctx->opcode);
5426 TCGv t0 = tcg_temp_new();
5427 TCGv t1 = tcg_temp_new();
5428 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5429 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5430 tcg_gen_or_tl(t1, t0, t1);
5431 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5432 gen_store_spr(SPR_MQ, t1);
5433 tcg_temp_free(t0);
5434 tcg_temp_free(t1);
5435 if (unlikely(Rc(ctx->opcode) != 0))
5436 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5437 }
5438
5439 /* srliq */
5440 static void gen_srliq(DisasContext *ctx)
5441 {
5442 int sh = SH(ctx->opcode);
5443 TCGv t0 = tcg_temp_new();
5444 TCGv t1 = tcg_temp_new();
5445 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5446 gen_load_spr(t1, SPR_MQ);
5447 gen_store_spr(SPR_MQ, t0);
5448 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5449 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5450 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5451 tcg_temp_free(t0);
5452 tcg_temp_free(t1);
5453 if (unlikely(Rc(ctx->opcode) != 0))
5454 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5455 }
5456
5457 /* srlq */
5458 static void gen_srlq(DisasContext *ctx)
5459 {
5460 int l1 = gen_new_label();
5461 int l2 = gen_new_label();
5462 TCGv t0 = tcg_temp_local_new();
5463 TCGv t1 = tcg_temp_local_new();
5464 TCGv t2 = tcg_temp_local_new();
5465 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5466 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5467 tcg_gen_shr_tl(t2, t1, t2);
5468 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5469 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5470 gen_load_spr(t0, SPR_MQ);
5471 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5472 tcg_gen_br(l2);
5473 gen_set_label(l1);
5474 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5475 tcg_gen_and_tl(t0, t0, t2);
5476 gen_load_spr(t1, SPR_MQ);
5477 tcg_gen_andc_tl(t1, t1, t2);
5478 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5479 gen_set_label(l2);
5480 tcg_temp_free(t0);
5481 tcg_temp_free(t1);
5482 tcg_temp_free(t2);
5483 if (unlikely(Rc(ctx->opcode) != 0))
5484 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5485 }
5486
5487 /* srq */
5488 static void gen_srq(DisasContext *ctx)
5489 {
5490 int l1 = gen_new_label();
5491 TCGv t0 = tcg_temp_new();
5492 TCGv t1 = tcg_temp_new();
5493 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5494 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5495 tcg_gen_subfi_tl(t1, 32, t1);
5496 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5497 tcg_gen_or_tl(t1, t0, t1);
5498 gen_store_spr(SPR_MQ, t1);
5499 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5500 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5501 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5502 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5503 gen_set_label(l1);
5504 tcg_temp_free(t0);
5505 tcg_temp_free(t1);
5506 if (unlikely(Rc(ctx->opcode) != 0))
5507 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5508 }
5509
5510 /* PowerPC 602 specific instructions */
5511
5512 /* dsa */
5513 static void gen_dsa(DisasContext *ctx)
5514 {
5515 /* XXX: TODO */
5516 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5517 }
5518
5519 /* esa */
5520 static void gen_esa(DisasContext *ctx)
5521 {
5522 /* XXX: TODO */
5523 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5524 }
5525
5526 /* mfrom */
5527 static void gen_mfrom(DisasContext *ctx)
5528 {
5529 #if defined(CONFIG_USER_ONLY)
5530 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5531 #else
5532 if (unlikely(!ctx->mem_idx)) {
5533 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5534 return;
5535 }
5536 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5537 #endif
5538 }
5539
5540 /* 602 - 603 - G2 TLB management */
5541
5542 /* tlbld */
5543 static void gen_tlbld_6xx(DisasContext *ctx)
5544 {
5545 #if defined(CONFIG_USER_ONLY)
5546 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5547 #else
5548 if (unlikely(!ctx->mem_idx)) {
5549 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5550 return;
5551 }
5552 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5553 #endif
5554 }
5555
5556 /* tlbli */
5557 static void gen_tlbli_6xx(DisasContext *ctx)
5558 {
5559 #if defined(CONFIG_USER_ONLY)
5560 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5561 #else
5562 if (unlikely(!ctx->mem_idx)) {
5563 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5564 return;
5565 }
5566 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5567 #endif
5568 }
5569
5570 /* 74xx TLB management */
5571
5572 /* tlbld */
5573 static void gen_tlbld_74xx(DisasContext *ctx)
5574 {
5575 #if defined(CONFIG_USER_ONLY)
5576 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5577 #else
5578 if (unlikely(!ctx->mem_idx)) {
5579 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5580 return;
5581 }
5582 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5583 #endif
5584 }
5585
5586 /* tlbli */
5587 static void gen_tlbli_74xx(DisasContext *ctx)
5588 {
5589 #if defined(CONFIG_USER_ONLY)
5590 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5591 #else
5592 if (unlikely(!ctx->mem_idx)) {
5593 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5594 return;
5595 }
5596 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5597 #endif
5598 }
5599
5600 /* POWER instructions not in PowerPC 601 */
5601
5602 /* clf */
5603 static void gen_clf(DisasContext *ctx)
5604 {
5605 /* Cache line flush: implemented as no-op */
5606 }
5607
5608 /* cli */
5609 static void gen_cli(DisasContext *ctx)
5610 {
5611 /* Cache line invalidate: privileged and treated as no-op */
5612 #if defined(CONFIG_USER_ONLY)
5613 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5614 #else
5615 if (unlikely(!ctx->mem_idx)) {
5616 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5617 return;
5618 }
5619 #endif
5620 }
5621
5622 /* dclst */
5623 static void gen_dclst(DisasContext *ctx)
5624 {
5625 /* Data cache line store: treated as no-op */
5626 }
5627
5628 static void gen_mfsri(DisasContext *ctx)
5629 {
5630 #if defined(CONFIG_USER_ONLY)
5631 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5632 #else
5633 int ra = rA(ctx->opcode);
5634 int rd = rD(ctx->opcode);
5635 TCGv t0;
5636 if (unlikely(!ctx->mem_idx)) {
5637 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5638 return;
5639 }
5640 t0 = tcg_temp_new();
5641 gen_addr_reg_index(ctx, t0);
5642 tcg_gen_shri_tl(t0, t0, 28);
5643 tcg_gen_andi_tl(t0, t0, 0xF);
5644 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5645 tcg_temp_free(t0);
5646 if (ra != 0 && ra != rd)
5647 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5648 #endif
5649 }
5650
5651 static void gen_rac(DisasContext *ctx)
5652 {
5653 #if defined(CONFIG_USER_ONLY)
5654 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5655 #else
5656 TCGv t0;
5657 if (unlikely(!ctx->mem_idx)) {
5658 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5659 return;
5660 }
5661 t0 = tcg_temp_new();
5662 gen_addr_reg_index(ctx, t0);
5663 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5664 tcg_temp_free(t0);
5665 #endif
5666 }
5667
5668 static void gen_rfsvc(DisasContext *ctx)
5669 {
5670 #if defined(CONFIG_USER_ONLY)
5671 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5672 #else
5673 if (unlikely(!ctx->mem_idx)) {
5674 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5675 return;
5676 }
5677 gen_helper_rfsvc(cpu_env);
5678 gen_sync_exception(ctx);
5679 #endif
5680 }
5681
5682 /* svc is not implemented for now */
5683
5684 /* POWER2 specific instructions */
5685 /* Quad manipulation (load/store two floats at a time) */
5686
5687 /* lfq */
5688 static void gen_lfq(DisasContext *ctx)
5689 {
5690 int rd = rD(ctx->opcode);
5691 TCGv t0;
5692 gen_set_access_type(ctx, ACCESS_FLOAT);
5693 t0 = tcg_temp_new();
5694 gen_addr_imm_index(ctx, t0, 0);
5695 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5696 gen_addr_add(ctx, t0, t0, 8);
5697 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5698 tcg_temp_free(t0);
5699 }
5700
5701 /* lfqu */
5702 static void gen_lfqu(DisasContext *ctx)
5703 {
5704 int ra = rA(ctx->opcode);
5705 int rd = rD(ctx->opcode);
5706 TCGv t0, t1;
5707 gen_set_access_type(ctx, ACCESS_FLOAT);
5708 t0 = tcg_temp_new();
5709 t1 = tcg_temp_new();
5710 gen_addr_imm_index(ctx, t0, 0);
5711 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5712 gen_addr_add(ctx, t1, t0, 8);
5713 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5714 if (ra != 0)
5715 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5716 tcg_temp_free(t0);
5717 tcg_temp_free(t1);
5718 }
5719
5720 /* lfqux */
5721 static void gen_lfqux(DisasContext *ctx)
5722 {
5723 int ra = rA(ctx->opcode);
5724 int rd = rD(ctx->opcode);
5725 gen_set_access_type(ctx, ACCESS_FLOAT);
5726 TCGv t0, t1;
5727 t0 = tcg_temp_new();
5728 gen_addr_reg_index(ctx, t0);
5729 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5730 t1 = tcg_temp_new();
5731 gen_addr_add(ctx, t1, t0, 8);
5732 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5733 tcg_temp_free(t1);
5734 if (ra != 0)
5735 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5736 tcg_temp_free(t0);
5737 }
5738
5739 /* lfqx */
5740 static void gen_lfqx(DisasContext *ctx)
5741 {
5742 int rd = rD(ctx->opcode);
5743 TCGv t0;
5744 gen_set_access_type(ctx, ACCESS_FLOAT);
5745 t0 = tcg_temp_new();
5746 gen_addr_reg_index(ctx, t0);
5747 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5748 gen_addr_add(ctx, t0, t0, 8);
5749 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5750 tcg_temp_free(t0);
5751 }
5752
5753 /* stfq */
5754 static void gen_stfq(DisasContext *ctx)
5755 {
5756 int rd = rD(ctx->opcode);
5757 TCGv t0;
5758 gen_set_access_type(ctx, ACCESS_FLOAT);
5759 t0 = tcg_temp_new();
5760 gen_addr_imm_index(ctx, t0, 0);
5761 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5762 gen_addr_add(ctx, t0, t0, 8);
5763 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5764 tcg_temp_free(t0);
5765 }
5766
5767 /* stfqu */
5768 static void gen_stfqu(DisasContext *ctx)
5769 {
5770 int ra = rA(ctx->opcode);
5771 int rd = rD(ctx->opcode);
5772 TCGv t0, t1;
5773 gen_set_access_type(ctx, ACCESS_FLOAT);
5774 t0 = tcg_temp_new();
5775 gen_addr_imm_index(ctx, t0, 0);
5776 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5777 t1 = tcg_temp_new();
5778 gen_addr_add(ctx, t1, t0, 8);
5779 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5780 tcg_temp_free(t1);
5781 if (ra != 0)
5782 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5783 tcg_temp_free(t0);
5784 }
5785
5786 /* stfqux */
5787 static void gen_stfqux(DisasContext *ctx)
5788 {
5789 int ra = rA(ctx->opcode);
5790 int rd = rD(ctx->opcode);
5791 TCGv t0, t1;
5792 gen_set_access_type(ctx, ACCESS_FLOAT);
5793 t0 = tcg_temp_new();
5794 gen_addr_reg_index(ctx, t0);
5795 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5796 t1 = tcg_temp_new();
5797 gen_addr_add(ctx, t1, t0, 8);
5798 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5799 tcg_temp_free(t1);
5800 if (ra != 0)
5801 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5802 tcg_temp_free(t0);
5803 }
5804
5805 /* stfqx */
5806 static void gen_stfqx(DisasContext *ctx)
5807 {
5808 int rd = rD(ctx->opcode);
5809 TCGv t0;
5810 gen_set_access_type(ctx, ACCESS_FLOAT);
5811 t0 = tcg_temp_new();
5812 gen_addr_reg_index(ctx, t0);
5813 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5814 gen_addr_add(ctx, t0, t0, 8);
5815 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5816 tcg_temp_free(t0);
5817 }
5818
5819 /* BookE specific instructions */
5820
5821 /* XXX: not implemented on 440 ? */
5822 static void gen_mfapidi(DisasContext *ctx)
5823 {
5824 /* XXX: TODO */
5825 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5826 }
5827
5828 /* XXX: not implemented on 440 ? */
5829 static void gen_tlbiva(DisasContext *ctx)
5830 {
5831 #if defined(CONFIG_USER_ONLY)
5832 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5833 #else
5834 TCGv t0;
5835 if (unlikely(!ctx->mem_idx)) {
5836 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5837 return;
5838 }
5839 t0 = tcg_temp_new();
5840 gen_addr_reg_index(ctx, t0);
5841 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5842 tcg_temp_free(t0);
5843 #endif
5844 }
5845
5846 /* All 405 MAC instructions are translated here */
5847 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5848 int ra, int rb, int rt, int Rc)
5849 {
5850 TCGv t0, t1;
5851
5852 t0 = tcg_temp_local_new();
5853 t1 = tcg_temp_local_new();
5854
5855 switch (opc3 & 0x0D) {
5856 case 0x05:
5857 /* macchw - macchw. - macchwo - macchwo. */
5858 /* macchws - macchws. - macchwso - macchwso. */
5859 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5860 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5861 /* mulchw - mulchw. */
5862 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5863 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5864 tcg_gen_ext16s_tl(t1, t1);
5865 break;
5866 case 0x04:
5867 /* macchwu - macchwu. - macchwuo - macchwuo. */
5868 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5869 /* mulchwu - mulchwu. */
5870 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5871 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5872 tcg_gen_ext16u_tl(t1, t1);
5873 break;
5874 case 0x01:
5875 /* machhw - machhw. - machhwo - machhwo. */
5876 /* machhws - machhws. - machhwso - machhwso. */
5877 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5878 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5879 /* mulhhw - mulhhw. */
5880 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5881 tcg_gen_ext16s_tl(t0, t0);
5882 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5883 tcg_gen_ext16s_tl(t1, t1);
5884 break;
5885 case 0x00:
5886 /* machhwu - machhwu. - machhwuo - machhwuo. */
5887 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5888 /* mulhhwu - mulhhwu. */
5889 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5890 tcg_gen_ext16u_tl(t0, t0);
5891 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5892 tcg_gen_ext16u_tl(t1, t1);
5893 break;
5894 case 0x0D:
5895 /* maclhw - maclhw. - maclhwo - maclhwo. */
5896 /* maclhws - maclhws. - maclhwso - maclhwso. */
5897 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5898 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5899 /* mullhw - mullhw. */
5900 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5901 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5902 break;
5903 case 0x0C:
5904 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5905 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5906 /* mullhwu - mullhwu. */
5907 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5908 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5909 break;
5910 }
5911 if (opc2 & 0x04) {
5912 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5913 tcg_gen_mul_tl(t1, t0, t1);
5914 if (opc2 & 0x02) {
5915 /* nmultiply-and-accumulate (0x0E) */
5916 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5917 } else {
5918 /* multiply-and-accumulate (0x0C) */
5919 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5920 }
5921
5922 if (opc3 & 0x12) {
5923 /* Check overflow and/or saturate */
5924 int l1 = gen_new_label();
5925
5926 if (opc3 & 0x10) {
5927 /* Start with XER OV disabled, the most likely case */
5928 tcg_gen_movi_tl(cpu_ov, 0);
5929 }
5930 if (opc3 & 0x01) {
5931 /* Signed */
5932 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5933 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5934 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5935 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5936 if (opc3 & 0x02) {
5937 /* Saturate */
5938 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5939 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5940 }
5941 } else {
5942 /* Unsigned */
5943 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5944 if (opc3 & 0x02) {
5945 /* Saturate */
5946 tcg_gen_movi_tl(t0, UINT32_MAX);
5947 }
5948 }
5949 if (opc3 & 0x10) {
5950 /* Check overflow */
5951 tcg_gen_movi_tl(cpu_ov, 1);
5952 tcg_gen_movi_tl(cpu_so, 1);
5953 }
5954 gen_set_label(l1);
5955 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5956 }
5957 } else {
5958 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5959 }
5960 tcg_temp_free(t0);
5961 tcg_temp_free(t1);
5962 if (unlikely(Rc) != 0) {
5963 /* Update Rc0 */
5964 gen_set_Rc0(ctx, cpu_gpr[rt]);
5965 }
5966 }
5967
5968 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5969 static void glue(gen_, name)(DisasContext *ctx) \
5970 { \
5971 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5972 rD(ctx->opcode), Rc(ctx->opcode)); \
5973 }
5974
5975 /* macchw - macchw. */
5976 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5977 /* macchwo - macchwo. */
5978 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5979 /* macchws - macchws. */
5980 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5981 /* macchwso - macchwso. */
5982 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5983 /* macchwsu - macchwsu. */
5984 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5985 /* macchwsuo - macchwsuo. */
5986 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5987 /* macchwu - macchwu. */
5988 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5989 /* macchwuo - macchwuo. */
5990 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5991 /* machhw - machhw. */
5992 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5993 /* machhwo - machhwo. */
5994 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5995 /* machhws - machhws. */
5996 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5997 /* machhwso - machhwso. */
5998 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5999 /* machhwsu - machhwsu. */
6000 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6001 /* machhwsuo - machhwsuo. */
6002 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6003 /* machhwu - machhwu. */
6004 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6005 /* machhwuo - machhwuo. */
6006 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6007 /* maclhw - maclhw. */
6008 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6009 /* maclhwo - maclhwo. */
6010 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6011 /* maclhws - maclhws. */
6012 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6013 /* maclhwso - maclhwso. */
6014 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6015 /* maclhwu - maclhwu. */
6016 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6017 /* maclhwuo - maclhwuo. */
6018 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6019 /* maclhwsu - maclhwsu. */
6020 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6021 /* maclhwsuo - maclhwsuo. */
6022 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6023 /* nmacchw - nmacchw. */
6024 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6025 /* nmacchwo - nmacchwo. */
6026 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6027 /* nmacchws - nmacchws. */
6028 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6029 /* nmacchwso - nmacchwso. */
6030 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6031 /* nmachhw - nmachhw. */
6032 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6033 /* nmachhwo - nmachhwo. */
6034 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6035 /* nmachhws - nmachhws. */
6036 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6037 /* nmachhwso - nmachhwso. */
6038 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6039 /* nmaclhw - nmaclhw. */
6040 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6041 /* nmaclhwo - nmaclhwo. */
6042 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6043 /* nmaclhws - nmaclhws. */
6044 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6045 /* nmaclhwso - nmaclhwso. */
6046 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6047
6048 /* mulchw - mulchw. */
6049 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6050 /* mulchwu - mulchwu. */
6051 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6052 /* mulhhw - mulhhw. */
6053 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6054 /* mulhhwu - mulhhwu. */
6055 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6056 /* mullhw - mullhw. */
6057 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6058 /* mullhwu - mullhwu. */
6059 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6060
6061 /* mfdcr */
6062 static void gen_mfdcr(DisasContext *ctx)
6063 {
6064 #if defined(CONFIG_USER_ONLY)
6065 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6066 #else
6067 TCGv dcrn;
6068 if (unlikely(!ctx->mem_idx)) {
6069 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6070 return;
6071 }
6072 /* NIP cannot be restored if the memory exception comes from an helper */
6073 gen_update_nip(ctx, ctx->nip - 4);
6074 dcrn = tcg_const_tl(SPR(ctx->opcode));
6075 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6076 tcg_temp_free(dcrn);
6077 #endif
6078 }
6079
6080 /* mtdcr */
6081 static void gen_mtdcr(DisasContext *ctx)
6082 {
6083 #if defined(CONFIG_USER_ONLY)
6084 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6085 #else
6086 TCGv dcrn;
6087 if (unlikely(!ctx->mem_idx)) {
6088 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6089 return;
6090 }
6091 /* NIP cannot be restored if the memory exception comes from an helper */
6092 gen_update_nip(ctx, ctx->nip - 4);
6093 dcrn = tcg_const_tl(SPR(ctx->opcode));
6094 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6095 tcg_temp_free(dcrn);
6096 #endif
6097 }
6098
6099 /* mfdcrx */
6100 /* XXX: not implemented on 440 ? */
6101 static void gen_mfdcrx(DisasContext *ctx)
6102 {
6103 #if defined(CONFIG_USER_ONLY)
6104 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6105 #else
6106 if (unlikely(!ctx->mem_idx)) {
6107 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6108 return;
6109 }
6110 /* NIP cannot be restored if the memory exception comes from an helper */
6111 gen_update_nip(ctx, ctx->nip - 4);
6112 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6113 cpu_gpr[rA(ctx->opcode)]);
6114 /* Note: Rc update flag set leads to undefined state of Rc0 */
6115 #endif
6116 }
6117
6118 /* mtdcrx */
6119 /* XXX: not implemented on 440 ? */
6120 static void gen_mtdcrx(DisasContext *ctx)
6121 {
6122 #if defined(CONFIG_USER_ONLY)
6123 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6124 #else
6125 if (unlikely(!ctx->mem_idx)) {
6126 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6127 return;
6128 }
6129 /* NIP cannot be restored if the memory exception comes from an helper */
6130 gen_update_nip(ctx, ctx->nip - 4);
6131 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6132 cpu_gpr[rS(ctx->opcode)]);
6133 /* Note: Rc update flag set leads to undefined state of Rc0 */
6134 #endif
6135 }
6136
6137 /* mfdcrux (PPC 460) : user-mode access to DCR */
6138 static void gen_mfdcrux(DisasContext *ctx)
6139 {
6140 /* NIP cannot be restored if the memory exception comes from an helper */
6141 gen_update_nip(ctx, ctx->nip - 4);
6142 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6143 cpu_gpr[rA(ctx->opcode)]);
6144 /* Note: Rc update flag set leads to undefined state of Rc0 */
6145 }
6146
6147 /* mtdcrux (PPC 460) : user-mode access to DCR */
6148 static void gen_mtdcrux(DisasContext *ctx)
6149 {
6150 /* NIP cannot be restored if the memory exception comes from an helper */
6151 gen_update_nip(ctx, ctx->nip - 4);
6152 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6153 cpu_gpr[rS(ctx->opcode)]);
6154 /* Note: Rc update flag set leads to undefined state of Rc0 */
6155 }
6156
6157 /* dccci */
6158 static void gen_dccci(DisasContext *ctx)
6159 {
6160 #if defined(CONFIG_USER_ONLY)
6161 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6162 #else
6163 if (unlikely(!ctx->mem_idx)) {
6164 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6165 return;
6166 }
6167 /* interpreted as no-op */
6168 #endif
6169 }
6170
6171 /* dcread */
6172 static void gen_dcread(DisasContext *ctx)
6173 {
6174 #if defined(CONFIG_USER_ONLY)
6175 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6176 #else
6177 TCGv EA, val;
6178 if (unlikely(!ctx->mem_idx)) {
6179 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6180 return;
6181 }
6182 gen_set_access_type(ctx, ACCESS_CACHE);
6183 EA = tcg_temp_new();
6184 gen_addr_reg_index(ctx, EA);
6185 val = tcg_temp_new();
6186 gen_qemu_ld32u(ctx, val, EA);
6187 tcg_temp_free(val);
6188 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6189 tcg_temp_free(EA);
6190 #endif
6191 }
6192
6193 /* icbt */
6194 static void gen_icbt_40x(DisasContext *ctx)
6195 {
6196 /* interpreted as no-op */
6197 /* XXX: specification say this is treated as a load by the MMU
6198 * but does not generate any exception
6199 */
6200 }
6201
6202 /* iccci */
6203 static void gen_iccci(DisasContext *ctx)
6204 {
6205 #if defined(CONFIG_USER_ONLY)
6206 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6207 #else
6208 if (unlikely(!ctx->mem_idx)) {
6209 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6210 return;
6211 }
6212 /* interpreted as no-op */
6213 #endif
6214 }
6215
6216 /* icread */
6217 static void gen_icread(DisasContext *ctx)
6218 {
6219 #if defined(CONFIG_USER_ONLY)
6220 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6221 #else
6222 if (unlikely(!ctx->mem_idx)) {
6223 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6224 return;
6225 }
6226 /* interpreted as no-op */
6227 #endif
6228 }
6229
6230 /* rfci (mem_idx only) */
6231 static void gen_rfci_40x(DisasContext *ctx)
6232 {
6233 #if defined(CONFIG_USER_ONLY)
6234 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6235 #else
6236 if (unlikely(!ctx->mem_idx)) {
6237 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6238 return;
6239 }
6240 /* Restore CPU state */
6241 gen_helper_40x_rfci(cpu_env);
6242 gen_sync_exception(ctx);
6243 #endif
6244 }
6245
6246 static void gen_rfci(DisasContext *ctx)
6247 {
6248 #if defined(CONFIG_USER_ONLY)
6249 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6250 #else
6251 if (unlikely(!ctx->mem_idx)) {
6252 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6253 return;
6254 }
6255 /* Restore CPU state */
6256 gen_helper_rfci(cpu_env);
6257 gen_sync_exception(ctx);
6258 #endif
6259 }
6260
6261 /* BookE specific */
6262
6263 /* XXX: not implemented on 440 ? */
6264 static void gen_rfdi(DisasContext *ctx)
6265 {
6266 #if defined(CONFIG_USER_ONLY)
6267 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6268 #else
6269 if (unlikely(!ctx->mem_idx)) {
6270 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6271 return;
6272 }
6273 /* Restore CPU state */
6274 gen_helper_rfdi(cpu_env);
6275 gen_sync_exception(ctx);
6276 #endif
6277 }
6278
6279 /* XXX: not implemented on 440 ? */
6280 static void gen_rfmci(DisasContext *ctx)
6281 {
6282 #if defined(CONFIG_USER_ONLY)
6283 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6284 #else
6285 if (unlikely(!ctx->mem_idx)) {
6286 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6287 return;
6288 }
6289 /* Restore CPU state */
6290 gen_helper_rfmci(cpu_env);
6291 gen_sync_exception(ctx);
6292 #endif
6293 }
6294
6295 /* TLB management - PowerPC 405 implementation */
6296
6297 /* tlbre */
6298 static void gen_tlbre_40x(DisasContext *ctx)
6299 {
6300 #if defined(CONFIG_USER_ONLY)
6301 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6302 #else
6303 if (unlikely(!ctx->mem_idx)) {
6304 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6305 return;
6306 }
6307 switch (rB(ctx->opcode)) {
6308 case 0:
6309 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6310 cpu_gpr[rA(ctx->opcode)]);
6311 break;
6312 case 1:
6313 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6314 cpu_gpr[rA(ctx->opcode)]);
6315 break;
6316 default:
6317 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6318 break;
6319 }
6320 #endif
6321 }
6322
6323 /* tlbsx - tlbsx. */
6324 static void gen_tlbsx_40x(DisasContext *ctx)
6325 {
6326 #if defined(CONFIG_USER_ONLY)
6327 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6328 #else
6329 TCGv t0;
6330 if (unlikely(!ctx->mem_idx)) {
6331 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6332 return;
6333 }
6334 t0 = tcg_temp_new();
6335 gen_addr_reg_index(ctx, t0);
6336 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6337 tcg_temp_free(t0);
6338 if (Rc(ctx->opcode)) {
6339 int l1 = gen_new_label();
6340 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6341 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6342 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6343 gen_set_label(l1);
6344 }
6345 #endif
6346 }
6347
6348 /* tlbwe */
6349 static void gen_tlbwe_40x(DisasContext *ctx)
6350 {
6351 #if defined(CONFIG_USER_ONLY)
6352 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6353 #else
6354 if (unlikely(!ctx->mem_idx)) {
6355 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6356 return;
6357 }
6358 switch (rB(ctx->opcode)) {
6359 case 0:
6360 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6361 cpu_gpr[rS(ctx->opcode)]);
6362 break;
6363 case 1:
6364 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6365 cpu_gpr[rS(ctx->opcode)]);
6366 break;
6367 default:
6368 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6369 break;
6370 }
6371 #endif
6372 }
6373
6374 /* TLB management - PowerPC 440 implementation */
6375
6376 /* tlbre */
6377 static void gen_tlbre_440(DisasContext *ctx)
6378 {
6379 #if defined(CONFIG_USER_ONLY)
6380 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6381 #else
6382 if (unlikely(!ctx->mem_idx)) {
6383 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6384 return;
6385 }
6386 switch (rB(ctx->opcode)) {
6387 case 0:
6388 case 1:
6389 case 2:
6390 {
6391 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6392 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6393 t0, cpu_gpr[rA(ctx->opcode)]);
6394 tcg_temp_free_i32(t0);
6395 }
6396 break;
6397 default:
6398 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6399 break;
6400 }
6401 #endif
6402 }
6403
6404 /* tlbsx - tlbsx. */
6405 static void gen_tlbsx_440(DisasContext *ctx)
6406 {
6407 #if defined(CONFIG_USER_ONLY)
6408 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6409 #else
6410 TCGv t0;
6411 if (unlikely(!ctx->mem_idx)) {
6412 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6413 return;
6414 }
6415 t0 = tcg_temp_new();
6416 gen_addr_reg_index(ctx, t0);
6417 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6418 tcg_temp_free(t0);
6419 if (Rc(ctx->opcode)) {
6420 int l1 = gen_new_label();
6421 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6422 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6423 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6424 gen_set_label(l1);
6425 }
6426 #endif
6427 }
6428
6429 /* tlbwe */
6430 static void gen_tlbwe_440(DisasContext *ctx)
6431 {
6432 #if defined(CONFIG_USER_ONLY)
6433 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6434 #else
6435 if (unlikely(!ctx->mem_idx)) {
6436 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6437 return;
6438 }
6439 switch (rB(ctx->opcode)) {
6440 case 0:
6441 case 1:
6442 case 2:
6443 {
6444 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6445 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6446 cpu_gpr[rS(ctx->opcode)]);
6447 tcg_temp_free_i32(t0);
6448 }
6449 break;
6450 default:
6451 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6452 break;
6453 }
6454 #endif
6455 }
6456
6457 /* TLB management - PowerPC BookE 2.06 implementation */
6458
6459 /* tlbre */
6460 static void gen_tlbre_booke206(DisasContext *ctx)
6461 {
6462 #if defined(CONFIG_USER_ONLY)
6463 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6464 #else
6465 if (unlikely(!ctx->mem_idx)) {
6466 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6467 return;
6468 }
6469
6470 gen_helper_booke206_tlbre(cpu_env);
6471 #endif
6472 }
6473
6474 /* tlbsx - tlbsx. */
6475 static void gen_tlbsx_booke206(DisasContext *ctx)
6476 {
6477 #if defined(CONFIG_USER_ONLY)
6478 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6479 #else
6480 TCGv t0;
6481 if (unlikely(!ctx->mem_idx)) {
6482 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6483 return;
6484 }
6485
6486 if (rA(ctx->opcode)) {
6487 t0 = tcg_temp_new();
6488 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6489 } else {
6490 t0 = tcg_const_tl(0);
6491 }
6492
6493 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6494 gen_helper_booke206_tlbsx(cpu_env, t0);
6495 #endif
6496 }
6497
6498 /* tlbwe */
6499 static void gen_tlbwe_booke206(DisasContext *ctx)
6500 {
6501 #if defined(CONFIG_USER_ONLY)
6502 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6503 #else
6504 if (unlikely(!ctx->mem_idx)) {
6505 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6506 return;
6507 }
6508 gen_update_nip(ctx, ctx->nip - 4);
6509 gen_helper_booke206_tlbwe(cpu_env);
6510 #endif
6511 }
6512
6513 static void gen_tlbivax_booke206(DisasContext *ctx)
6514 {
6515 #if defined(CONFIG_USER_ONLY)
6516 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6517 #else
6518 TCGv t0;
6519 if (unlikely(!ctx->mem_idx)) {
6520 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6521 return;
6522 }
6523
6524 t0 = tcg_temp_new();
6525 gen_addr_reg_index(ctx, t0);
6526
6527 gen_helper_booke206_tlbivax(cpu_env, t0);
6528 #endif
6529 }
6530
6531 static void gen_tlbilx_booke206(DisasContext *ctx)
6532 {
6533 #if defined(CONFIG_USER_ONLY)
6534 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6535 #else
6536 TCGv t0;
6537 if (unlikely(!ctx->mem_idx)) {
6538 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6539 return;
6540 }
6541
6542 t0 = tcg_temp_new();
6543 gen_addr_reg_index(ctx, t0);
6544
6545 switch((ctx->opcode >> 21) & 0x3) {
6546 case 0:
6547 gen_helper_booke206_tlbilx0(cpu_env, t0);
6548 break;
6549 case 1:
6550 gen_helper_booke206_tlbilx1(cpu_env, t0);
6551 break;
6552 case 3:
6553 gen_helper_booke206_tlbilx3(cpu_env, t0);
6554 break;
6555 default:
6556 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6557 break;
6558 }
6559
6560 tcg_temp_free(t0);
6561 #endif
6562 }
6563
6564
6565 /* wrtee */
6566 static void gen_wrtee(DisasContext *ctx)
6567 {
6568 #if defined(CONFIG_USER_ONLY)
6569 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6570 #else
6571 TCGv t0;
6572 if (unlikely(!ctx->mem_idx)) {
6573 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6574 return;
6575 }
6576 t0 = tcg_temp_new();
6577 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6578 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6579 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6580 tcg_temp_free(t0);
6581 /* Stop translation to have a chance to raise an exception
6582 * if we just set msr_ee to 1
6583 */
6584 gen_stop_exception(ctx);
6585 #endif
6586 }
6587
6588 /* wrteei */
6589 static void gen_wrteei(DisasContext *ctx)
6590 {
6591 #if defined(CONFIG_USER_ONLY)
6592 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6593 #else
6594 if (unlikely(!ctx->mem_idx)) {
6595 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6596 return;
6597 }
6598 if (ctx->opcode & 0x00008000) {
6599 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6600 /* Stop translation to have a chance to raise an exception */
6601 gen_stop_exception(ctx);
6602 } else {
6603 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6604 }
6605 #endif
6606 }
6607
6608 /* PowerPC 440 specific instructions */
6609
6610 /* dlmzb */
6611 static void gen_dlmzb(DisasContext *ctx)
6612 {
6613 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6614 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6615 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6616 tcg_temp_free_i32(t0);
6617 }
6618
6619 /* mbar replaces eieio on 440 */
6620 static void gen_mbar(DisasContext *ctx)
6621 {
6622 /* interpreted as no-op */
6623 }
6624
6625 /* msync replaces sync on 440 */
6626 static void gen_msync_4xx(DisasContext *ctx)
6627 {
6628 /* interpreted as no-op */
6629 }
6630
6631 /* icbt */
6632 static void gen_icbt_440(DisasContext *ctx)
6633 {
6634 /* interpreted as no-op */
6635 /* XXX: specification say this is treated as a load by the MMU
6636 * but does not generate any exception
6637 */
6638 }
6639
6640 /* Embedded.Processor Control */
6641
6642 static void gen_msgclr(DisasContext *ctx)
6643 {
6644 #if defined(CONFIG_USER_ONLY)
6645 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6646 #else
6647 if (unlikely(ctx->mem_idx == 0)) {
6648 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6649 return;
6650 }
6651
6652 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6653 #endif
6654 }
6655
6656 static void gen_msgsnd(DisasContext *ctx)
6657 {
6658 #if defined(CONFIG_USER_ONLY)
6659 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6660 #else
6661 if (unlikely(ctx->mem_idx == 0)) {
6662 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6663 return;
6664 }
6665
6666 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6667 #endif
6668 }
6669
6670 /*** Altivec vector extension ***/
6671 /* Altivec registers moves */
6672
6673 static inline TCGv_ptr gen_avr_ptr(int reg)
6674 {
6675 TCGv_ptr r = tcg_temp_new_ptr();
6676 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6677 return r;
6678 }
6679
6680 #define GEN_VR_LDX(name, opc2, opc3) \
6681 static void glue(gen_, name)(DisasContext *ctx) \
6682 { \
6683 TCGv EA; \
6684 if (unlikely(!ctx->altivec_enabled)) { \
6685 gen_exception(ctx, POWERPC_EXCP_VPU); \
6686 return; \
6687 } \
6688 gen_set_access_type(ctx, ACCESS_INT); \
6689 EA = tcg_temp_new(); \
6690 gen_addr_reg_index(ctx, EA); \
6691 tcg_gen_andi_tl(EA, EA, ~0xf); \
6692 if (ctx->le_mode) { \
6693 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6694 tcg_gen_addi_tl(EA, EA, 8); \
6695 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6696 } else { \
6697 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6698 tcg_gen_addi_tl(EA, EA, 8); \
6699 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6700 } \
6701 tcg_temp_free(EA); \
6702 }
6703
6704 #define GEN_VR_STX(name, opc2, opc3) \
6705 static void gen_st##name(DisasContext *ctx) \
6706 { \
6707 TCGv EA; \
6708 if (unlikely(!ctx->altivec_enabled)) { \
6709 gen_exception(ctx, POWERPC_EXCP_VPU); \
6710 return; \
6711 } \
6712 gen_set_access_type(ctx, ACCESS_INT); \
6713 EA = tcg_temp_new(); \
6714 gen_addr_reg_index(ctx, EA); \
6715 tcg_gen_andi_tl(EA, EA, ~0xf); \
6716 if (ctx->le_mode) { \
6717 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6718 tcg_gen_addi_tl(EA, EA, 8); \
6719 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6720 } else { \
6721 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6722 tcg_gen_addi_tl(EA, EA, 8); \
6723 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6724 } \
6725 tcg_temp_free(EA); \
6726 }
6727
6728 #define GEN_VR_LVE(name, opc2, opc3) \
6729 static void gen_lve##name(DisasContext *ctx) \
6730 { \
6731 TCGv EA; \
6732 TCGv_ptr rs; \
6733 if (unlikely(!ctx->altivec_enabled)) { \
6734 gen_exception(ctx, POWERPC_EXCP_VPU); \
6735 return; \
6736 } \
6737 gen_set_access_type(ctx, ACCESS_INT); \
6738 EA = tcg_temp_new(); \
6739 gen_addr_reg_index(ctx, EA); \
6740 rs = gen_avr_ptr(rS(ctx->opcode)); \
6741 gen_helper_lve##name(cpu_env, rs, EA); \
6742 tcg_temp_free(EA); \
6743 tcg_temp_free_ptr(rs); \
6744 }
6745
6746 #define GEN_VR_STVE(name, opc2, opc3) \
6747 static void gen_stve##name(DisasContext *ctx) \
6748 { \
6749 TCGv EA; \
6750 TCGv_ptr rs; \
6751 if (unlikely(!ctx->altivec_enabled)) { \
6752 gen_exception(ctx, POWERPC_EXCP_VPU); \
6753 return; \
6754 } \
6755 gen_set_access_type(ctx, ACCESS_INT); \
6756 EA = tcg_temp_new(); \
6757 gen_addr_reg_index(ctx, EA); \
6758 rs = gen_avr_ptr(rS(ctx->opcode)); \
6759 gen_helper_stve##name(cpu_env, rs, EA); \
6760 tcg_temp_free(EA); \
6761 tcg_temp_free_ptr(rs); \
6762 }
6763
6764 GEN_VR_LDX(lvx, 0x07, 0x03);
6765 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6766 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6767
6768 GEN_VR_LVE(bx, 0x07, 0x00);
6769 GEN_VR_LVE(hx, 0x07, 0x01);
6770 GEN_VR_LVE(wx, 0x07, 0x02);
6771
6772 GEN_VR_STX(svx, 0x07, 0x07);
6773 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6774 GEN_VR_STX(svxl, 0x07, 0x0F);
6775
6776 GEN_VR_STVE(bx, 0x07, 0x04);
6777 GEN_VR_STVE(hx, 0x07, 0x05);
6778 GEN_VR_STVE(wx, 0x07, 0x06);
6779
6780 static void gen_lvsl(DisasContext *ctx)
6781 {
6782 TCGv_ptr rd;
6783 TCGv EA;
6784 if (unlikely(!ctx->altivec_enabled)) {
6785 gen_exception(ctx, POWERPC_EXCP_VPU);
6786 return;
6787 }
6788 EA = tcg_temp_new();
6789 gen_addr_reg_index(ctx, EA);
6790 rd = gen_avr_ptr(rD(ctx->opcode));
6791 gen_helper_lvsl(rd, EA);
6792 tcg_temp_free(EA);
6793 tcg_temp_free_ptr(rd);
6794 }
6795
6796 static void gen_lvsr(DisasContext *ctx)
6797 {
6798 TCGv_ptr rd;
6799 TCGv EA;
6800 if (unlikely(!ctx->altivec_enabled)) {
6801 gen_exception(ctx, POWERPC_EXCP_VPU);
6802 return;
6803 }
6804 EA = tcg_temp_new();
6805 gen_addr_reg_index(ctx, EA);
6806 rd = gen_avr_ptr(rD(ctx->opcode));
6807 gen_helper_lvsr(rd, EA);
6808 tcg_temp_free(EA);
6809 tcg_temp_free_ptr(rd);
6810 }
6811
6812 static void gen_mfvscr(DisasContext *ctx)
6813 {
6814 TCGv_i32 t;
6815 if (unlikely(!ctx->altivec_enabled)) {
6816 gen_exception(ctx, POWERPC_EXCP_VPU);
6817 return;
6818 }
6819 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6820 t = tcg_temp_new_i32();
6821 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6822 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6823 tcg_temp_free_i32(t);
6824 }
6825
6826 static void gen_mtvscr(DisasContext *ctx)
6827 {
6828 TCGv_ptr p;
6829 if (unlikely(!ctx->altivec_enabled)) {
6830 gen_exception(ctx, POWERPC_EXCP_VPU);
6831 return;
6832 }
6833 p = gen_avr_ptr(rD(ctx->opcode));
6834 gen_helper_mtvscr(cpu_env, p);
6835 tcg_temp_free_ptr(p);
6836 }
6837
6838 /* Logical operations */
6839 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6840 static void glue(gen_, name)(DisasContext *ctx) \
6841 { \
6842 if (unlikely(!ctx->altivec_enabled)) { \
6843 gen_exception(ctx, POWERPC_EXCP_VPU); \
6844 return; \
6845 } \
6846 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6847 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6848 }
6849
6850 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6851 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6852 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6853 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6854 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6855 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6856 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6857 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
6858
6859 #define GEN_VXFORM(name, opc2, opc3) \
6860 static void glue(gen_, name)(DisasContext *ctx) \
6861 { \
6862 TCGv_ptr ra, rb, rd; \
6863 if (unlikely(!ctx->altivec_enabled)) { \
6864 gen_exception(ctx, POWERPC_EXCP_VPU); \
6865 return; \
6866 } \
6867 ra = gen_avr_ptr(rA(ctx->opcode)); \
6868 rb = gen_avr_ptr(rB(ctx->opcode)); \
6869 rd = gen_avr_ptr(rD(ctx->opcode)); \
6870 gen_helper_##name (rd, ra, rb); \
6871 tcg_temp_free_ptr(ra); \
6872 tcg_temp_free_ptr(rb); \
6873 tcg_temp_free_ptr(rd); \
6874 }
6875
6876 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6877 static void glue(gen_, name)(DisasContext *ctx) \
6878 { \
6879 TCGv_ptr ra, rb, rd; \
6880 if (unlikely(!ctx->altivec_enabled)) { \
6881 gen_exception(ctx, POWERPC_EXCP_VPU); \
6882 return; \
6883 } \
6884 ra = gen_avr_ptr(rA(ctx->opcode)); \
6885 rb = gen_avr_ptr(rB(ctx->opcode)); \
6886 rd = gen_avr_ptr(rD(ctx->opcode)); \
6887 gen_helper_##name(cpu_env, rd, ra, rb); \
6888 tcg_temp_free_ptr(ra); \
6889 tcg_temp_free_ptr(rb); \
6890 tcg_temp_free_ptr(rd); \
6891 }
6892
6893 #define GEN_VXFORM3(name, opc2, opc3) \
6894 static void glue(gen_, name)(DisasContext *ctx) \
6895 { \
6896 TCGv_ptr ra, rb, rc, rd; \
6897 if (unlikely(!ctx->altivec_enabled)) { \
6898 gen_exception(ctx, POWERPC_EXCP_VPU); \
6899 return; \
6900 } \
6901 ra = gen_avr_ptr(rA(ctx->opcode)); \
6902 rb = gen_avr_ptr(rB(ctx->opcode)); \
6903 rc = gen_avr_ptr(rC(ctx->opcode)); \
6904 rd = gen_avr_ptr(rD(ctx->opcode)); \
6905 gen_helper_##name(rd, ra, rb, rc); \
6906 tcg_temp_free_ptr(ra); \
6907 tcg_temp_free_ptr(rb); \
6908 tcg_temp_free_ptr(rc); \
6909 tcg_temp_free_ptr(rd); \
6910 }
6911
6912 /*
6913 * Support for Altivec instruction pairs that use bit 31 (Rc) as
6914 * an opcode bit. In general, these pairs come from different
6915 * versions of the ISA, so we must also support a pair of flags for
6916 * each instruction.
6917 */
6918 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
6919 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6920 { \
6921 if ((Rc(ctx->opcode) == 0) && \
6922 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
6923 gen_##name0(ctx); \
6924 } else if ((Rc(ctx->opcode) == 1) && \
6925 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
6926 gen_##name1(ctx); \
6927 } else { \
6928 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
6929 } \
6930 }
6931
6932 GEN_VXFORM(vaddubm, 0, 0);
6933 GEN_VXFORM(vadduhm, 0, 1);
6934 GEN_VXFORM(vadduwm, 0, 2);
6935 GEN_VXFORM(vaddudm, 0, 3);
6936 GEN_VXFORM(vsububm, 0, 16);
6937 GEN_VXFORM(vsubuhm, 0, 17);
6938 GEN_VXFORM(vsubuwm, 0, 18);
6939 GEN_VXFORM(vsubudm, 0, 19);
6940 GEN_VXFORM(vmaxub, 1, 0);
6941 GEN_VXFORM(vmaxuh, 1, 1);
6942 GEN_VXFORM(vmaxuw, 1, 2);
6943 GEN_VXFORM(vmaxud, 1, 3);
6944 GEN_VXFORM(vmaxsb, 1, 4);
6945 GEN_VXFORM(vmaxsh, 1, 5);
6946 GEN_VXFORM(vmaxsw, 1, 6);
6947 GEN_VXFORM(vmaxsd, 1, 7);
6948 GEN_VXFORM(vminub, 1, 8);
6949 GEN_VXFORM(vminuh, 1, 9);
6950 GEN_VXFORM(vminuw, 1, 10);
6951 GEN_VXFORM(vminud, 1, 11);
6952 GEN_VXFORM(vminsb, 1, 12);
6953 GEN_VXFORM(vminsh, 1, 13);
6954 GEN_VXFORM(vminsw, 1, 14);
6955 GEN_VXFORM(vminsd, 1, 15);
6956 GEN_VXFORM(vavgub, 1, 16);
6957 GEN_VXFORM(vavguh, 1, 17);
6958 GEN_VXFORM(vavguw, 1, 18);
6959 GEN_VXFORM(vavgsb, 1, 20);
6960 GEN_VXFORM(vavgsh, 1, 21);
6961 GEN_VXFORM(vavgsw, 1, 22);
6962 GEN_VXFORM(vmrghb, 6, 0);
6963 GEN_VXFORM(vmrghh, 6, 1);
6964 GEN_VXFORM(vmrghw, 6, 2);
6965 GEN_VXFORM(vmrglb, 6, 4);
6966 GEN_VXFORM(vmrglh, 6, 5);
6967 GEN_VXFORM(vmrglw, 6, 6);
6968
6969 static void gen_vmrgew(DisasContext *ctx)
6970 {
6971 TCGv_i64 tmp;
6972 int VT, VA, VB;
6973 if (unlikely(!ctx->altivec_enabled)) {
6974 gen_exception(ctx, POWERPC_EXCP_VPU);
6975 return;
6976 }
6977 VT = rD(ctx->opcode);
6978 VA = rA(ctx->opcode);
6979 VB = rB(ctx->opcode);
6980 tmp = tcg_temp_new_i64();
6981 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
6982 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
6983 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
6984 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
6985 tcg_temp_free_i64(tmp);
6986 }
6987
6988 static void gen_vmrgow(DisasContext *ctx)
6989 {
6990 int VT, VA, VB;
6991 if (unlikely(!ctx->altivec_enabled)) {
6992 gen_exception(ctx, POWERPC_EXCP_VPU);
6993 return;
6994 }
6995 VT = rD(ctx->opcode);
6996 VA = rA(ctx->opcode);
6997 VB = rB(ctx->opcode);
6998
6999 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7000 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7001 }
7002
7003 GEN_VXFORM(vmuloub, 4, 0);
7004 GEN_VXFORM(vmulouh, 4, 1);
7005 GEN_VXFORM(vmulouw, 4, 2);
7006 GEN_VXFORM(vmuluwm, 4, 2);
7007 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7008 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7009 GEN_VXFORM(vmulosb, 4, 4);
7010 GEN_VXFORM(vmulosh, 4, 5);
7011 GEN_VXFORM(vmulosw, 4, 6);
7012 GEN_VXFORM(vmuleub, 4, 8);
7013 GEN_VXFORM(vmuleuh, 4, 9);
7014 GEN_VXFORM(vmuleuw, 4, 10);
7015 GEN_VXFORM(vmulesb, 4, 12);
7016 GEN_VXFORM(vmulesh, 4, 13);
7017 GEN_VXFORM(vmulesw, 4, 14);
7018 GEN_VXFORM(vslb, 2, 4);
7019 GEN_VXFORM(vslh, 2, 5);
7020 GEN_VXFORM(vslw, 2, 6);
7021 GEN_VXFORM(vsld, 2, 23);
7022 GEN_VXFORM(vsrb, 2, 8);
7023 GEN_VXFORM(vsrh, 2, 9);
7024 GEN_VXFORM(vsrw, 2, 10);
7025 GEN_VXFORM(vsrd, 2, 27);
7026 GEN_VXFORM(vsrab, 2, 12);
7027 GEN_VXFORM(vsrah, 2, 13);
7028 GEN_VXFORM(vsraw, 2, 14);
7029 GEN_VXFORM(vsrad, 2, 15);
7030 GEN_VXFORM(vslo, 6, 16);
7031 GEN_VXFORM(vsro, 6, 17);
7032 GEN_VXFORM(vaddcuw, 0, 6);
7033 GEN_VXFORM(vsubcuw, 0, 22);
7034 GEN_VXFORM_ENV(vaddubs, 0, 8);
7035 GEN_VXFORM_ENV(vadduhs, 0, 9);
7036 GEN_VXFORM_ENV(vadduws, 0, 10);
7037 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7038 GEN_VXFORM_ENV(vaddshs, 0, 13);
7039 GEN_VXFORM_ENV(vaddsws, 0, 14);
7040 GEN_VXFORM_ENV(vsububs, 0, 24);
7041 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7042 GEN_VXFORM_ENV(vsubuws, 0, 26);
7043 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7044 GEN_VXFORM_ENV(vsubshs, 0, 29);
7045 GEN_VXFORM_ENV(vsubsws, 0, 30);
7046 GEN_VXFORM(vadduqm, 0, 4);
7047 GEN_VXFORM(vaddcuq, 0, 5);
7048 GEN_VXFORM3(vaddeuqm, 30, 0);
7049 GEN_VXFORM3(vaddecuq, 30, 0);
7050 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7051 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7052 GEN_VXFORM(vsubuqm, 0, 20);
7053 GEN_VXFORM(vsubcuq, 0, 21);
7054 GEN_VXFORM3(vsubeuqm, 31, 0);
7055 GEN_VXFORM3(vsubecuq, 31, 0);
7056 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7057 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7058 GEN_VXFORM(vrlb, 2, 0);
7059 GEN_VXFORM(vrlh, 2, 1);
7060 GEN_VXFORM(vrlw, 2, 2);
7061 GEN_VXFORM(vrld, 2, 3);
7062 GEN_VXFORM(vsl, 2, 7);
7063 GEN_VXFORM(vsr, 2, 11);
7064 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7065 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7066 GEN_VXFORM_ENV(vpkudum, 7, 17);
7067 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7068 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7069 GEN_VXFORM_ENV(vpkudus, 7, 19);
7070 GEN_VXFORM_ENV(vpkshus, 7, 4);
7071 GEN_VXFORM_ENV(vpkswus, 7, 5);
7072 GEN_VXFORM_ENV(vpksdus, 7, 21);
7073 GEN_VXFORM_ENV(vpkshss, 7, 6);
7074 GEN_VXFORM_ENV(vpkswss, 7, 7);
7075 GEN_VXFORM_ENV(vpksdss, 7, 23);
7076 GEN_VXFORM(vpkpx, 7, 12);
7077 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7078 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7079 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7080 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7081 GEN_VXFORM_ENV(vsumsws, 4, 30);
7082 GEN_VXFORM_ENV(vaddfp, 5, 0);
7083 GEN_VXFORM_ENV(vsubfp, 5, 1);
7084 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7085 GEN_VXFORM_ENV(vminfp, 5, 17);
7086
7087 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7088 static void glue(gen_, name)(DisasContext *ctx) \
7089 { \
7090 TCGv_ptr ra, rb, rd; \
7091 if (unlikely(!ctx->altivec_enabled)) { \
7092 gen_exception(ctx, POWERPC_EXCP_VPU); \
7093 return; \
7094 } \
7095 ra = gen_avr_ptr(rA(ctx->opcode)); \
7096 rb = gen_avr_ptr(rB(ctx->opcode)); \
7097 rd = gen_avr_ptr(rD(ctx->opcode)); \
7098 gen_helper_##opname(cpu_env, rd, ra, rb); \
7099 tcg_temp_free_ptr(ra); \
7100 tcg_temp_free_ptr(rb); \
7101 tcg_temp_free_ptr(rd); \
7102 }
7103
7104 #define GEN_VXRFORM(name, opc2, opc3) \
7105 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7106 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7107
7108 /*
7109 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7110 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7111 * come from different versions of the ISA, so we must also support a
7112 * pair of flags for each instruction.
7113 */
7114 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7115 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7116 { \
7117 if ((Rc(ctx->opcode) == 0) && \
7118 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7119 if (Rc21(ctx->opcode) == 0) { \
7120 gen_##name0(ctx); \
7121 } else { \
7122 gen_##name0##_(ctx); \
7123 } \
7124 } else if ((Rc(ctx->opcode) == 1) && \
7125 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7126 if (Rc21(ctx->opcode) == 0) { \
7127 gen_##name1(ctx); \
7128 } else { \
7129 gen_##name1##_(ctx); \
7130 } \
7131 } else { \
7132 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7133 } \
7134 }
7135
7136 GEN_VXRFORM(vcmpequb, 3, 0)
7137 GEN_VXRFORM(vcmpequh, 3, 1)
7138 GEN_VXRFORM(vcmpequw, 3, 2)
7139 GEN_VXRFORM(vcmpgtsb, 3, 12)
7140 GEN_VXRFORM(vcmpgtsh, 3, 13)
7141 GEN_VXRFORM(vcmpgtsw, 3, 14)
7142 GEN_VXRFORM(vcmpgtub, 3, 8)
7143 GEN_VXRFORM(vcmpgtuh, 3, 9)
7144 GEN_VXRFORM(vcmpgtuw, 3, 10)
7145 GEN_VXRFORM(vcmpeqfp, 3, 3)
7146 GEN_VXRFORM(vcmpgefp, 3, 7)
7147 GEN_VXRFORM(vcmpgtfp, 3, 11)
7148 GEN_VXRFORM(vcmpbfp, 3, 15)
7149
7150 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7151 static void glue(gen_, name)(DisasContext *ctx) \
7152 { \
7153 TCGv_ptr rd; \
7154 TCGv_i32 simm; \
7155 if (unlikely(!ctx->altivec_enabled)) { \
7156 gen_exception(ctx, POWERPC_EXCP_VPU); \
7157 return; \
7158 } \
7159 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7160 rd = gen_avr_ptr(rD(ctx->opcode)); \
7161 gen_helper_##name (rd, simm); \
7162 tcg_temp_free_i32(simm); \
7163 tcg_temp_free_ptr(rd); \
7164 }
7165
7166 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7167 GEN_VXFORM_SIMM(vspltish, 6, 13);
7168 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7169
7170 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7171 static void glue(gen_, name)(DisasContext *ctx) \
7172 { \
7173 TCGv_ptr rb, rd; \
7174 if (unlikely(!ctx->altivec_enabled)) { \
7175 gen_exception(ctx, POWERPC_EXCP_VPU); \
7176 return; \
7177 } \
7178 rb = gen_avr_ptr(rB(ctx->opcode)); \
7179 rd = gen_avr_ptr(rD(ctx->opcode)); \
7180 gen_helper_##name (rd, rb); \
7181 tcg_temp_free_ptr(rb); \
7182 tcg_temp_free_ptr(rd); \
7183 }
7184
7185 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7186 static void glue(gen_, name)(DisasContext *ctx) \
7187 { \
7188 TCGv_ptr rb, rd; \
7189 \
7190 if (unlikely(!ctx->altivec_enabled)) { \
7191 gen_exception(ctx, POWERPC_EXCP_VPU); \
7192 return; \
7193 } \
7194 rb = gen_avr_ptr(rB(ctx->opcode)); \
7195 rd = gen_avr_ptr(rD(ctx->opcode)); \
7196 gen_helper_##name(cpu_env, rd, rb); \
7197 tcg_temp_free_ptr(rb); \
7198 tcg_temp_free_ptr(rd); \
7199 }
7200
7201 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7202 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7203 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7204 GEN_VXFORM_NOA(vupklsb, 7, 10);
7205 GEN_VXFORM_NOA(vupklsh, 7, 11);
7206 GEN_VXFORM_NOA(vupklsw, 7, 27);
7207 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7208 GEN_VXFORM_NOA(vupklpx, 7, 15);
7209 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7210 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7211 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7212 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7213 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
7214 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
7215 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7216 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
7217
7218 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7219 static void glue(gen_, name)(DisasContext *ctx) \
7220 { \
7221 TCGv_ptr rd; \
7222 TCGv_i32 simm; \
7223 if (unlikely(!ctx->altivec_enabled)) { \
7224 gen_exception(ctx, POWERPC_EXCP_VPU); \
7225 return; \
7226 } \
7227 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7228 rd = gen_avr_ptr(rD(ctx->opcode)); \
7229 gen_helper_##name (rd, simm); \
7230 tcg_temp_free_i32(simm); \
7231 tcg_temp_free_ptr(rd); \
7232 }
7233
7234 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7235 static void glue(gen_, name)(DisasContext *ctx) \
7236 { \
7237 TCGv_ptr rb, rd; \
7238 TCGv_i32 uimm; \
7239 if (unlikely(!ctx->altivec_enabled)) { \
7240 gen_exception(ctx, POWERPC_EXCP_VPU); \
7241 return; \
7242 } \
7243 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7244 rb = gen_avr_ptr(rB(ctx->opcode)); \
7245 rd = gen_avr_ptr(rD(ctx->opcode)); \
7246 gen_helper_##name (rd, rb, uimm); \
7247 tcg_temp_free_i32(uimm); \
7248 tcg_temp_free_ptr(rb); \
7249 tcg_temp_free_ptr(rd); \
7250 }
7251
7252 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7253 static void glue(gen_, name)(DisasContext *ctx) \
7254 { \
7255 TCGv_ptr rb, rd; \
7256 TCGv_i32 uimm; \
7257 \
7258 if (unlikely(!ctx->altivec_enabled)) { \
7259 gen_exception(ctx, POWERPC_EXCP_VPU); \
7260 return; \
7261 } \
7262 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7263 rb = gen_avr_ptr(rB(ctx->opcode)); \
7264 rd = gen_avr_ptr(rD(ctx->opcode)); \
7265 gen_helper_##name(cpu_env, rd, rb, uimm); \
7266 tcg_temp_free_i32(uimm); \
7267 tcg_temp_free_ptr(rb); \
7268 tcg_temp_free_ptr(rd); \
7269 }
7270
7271 GEN_VXFORM_UIMM(vspltb, 6, 8);
7272 GEN_VXFORM_UIMM(vsplth, 6, 9);
7273 GEN_VXFORM_UIMM(vspltw, 6, 10);
7274 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7275 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7276 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7277 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7278
7279 static void gen_vsldoi(DisasContext *ctx)
7280 {
7281 TCGv_ptr ra, rb, rd;
7282 TCGv_i32 sh;
7283 if (unlikely(!ctx->altivec_enabled)) {
7284 gen_exception(ctx, POWERPC_EXCP_VPU);
7285 return;
7286 }
7287 ra = gen_avr_ptr(rA(ctx->opcode));
7288 rb = gen_avr_ptr(rB(ctx->opcode));
7289 rd = gen_avr_ptr(rD(ctx->opcode));
7290 sh = tcg_const_i32(VSH(ctx->opcode));
7291 gen_helper_vsldoi (rd, ra, rb, sh);
7292 tcg_temp_free_ptr(ra);
7293 tcg_temp_free_ptr(rb);
7294 tcg_temp_free_ptr(rd);
7295 tcg_temp_free_i32(sh);
7296 }
7297
7298 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7299 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7300 { \
7301 TCGv_ptr ra, rb, rc, rd; \
7302 if (unlikely(!ctx->altivec_enabled)) { \
7303 gen_exception(ctx, POWERPC_EXCP_VPU); \
7304 return; \
7305 } \
7306 ra = gen_avr_ptr(rA(ctx->opcode)); \
7307 rb = gen_avr_ptr(rB(ctx->opcode)); \
7308 rc = gen_avr_ptr(rC(ctx->opcode)); \
7309 rd = gen_avr_ptr(rD(ctx->opcode)); \
7310 if (Rc(ctx->opcode)) { \
7311 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7312 } else { \
7313 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7314 } \
7315 tcg_temp_free_ptr(ra); \
7316 tcg_temp_free_ptr(rb); \
7317 tcg_temp_free_ptr(rc); \
7318 tcg_temp_free_ptr(rd); \
7319 }
7320
7321 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7322
7323 static void gen_vmladduhm(DisasContext *ctx)
7324 {
7325 TCGv_ptr ra, rb, rc, rd;
7326 if (unlikely(!ctx->altivec_enabled)) {
7327 gen_exception(ctx, POWERPC_EXCP_VPU);
7328 return;
7329 }
7330 ra = gen_avr_ptr(rA(ctx->opcode));
7331 rb = gen_avr_ptr(rB(ctx->opcode));
7332 rc = gen_avr_ptr(rC(ctx->opcode));
7333 rd = gen_avr_ptr(rD(ctx->opcode));
7334 gen_helper_vmladduhm(rd, ra, rb, rc);
7335 tcg_temp_free_ptr(ra);
7336 tcg_temp_free_ptr(rb);
7337 tcg_temp_free_ptr(rc);
7338 tcg_temp_free_ptr(rd);
7339 }
7340
7341 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7342 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7343 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7344 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7345 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7346
7347 GEN_VXFORM_NOA(vclzb, 1, 28)
7348 GEN_VXFORM_NOA(vclzh, 1, 29)
7349 GEN_VXFORM_NOA(vclzw, 1, 30)
7350 GEN_VXFORM_NOA(vclzd, 1, 31)
7351 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7352 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7353 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7354 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7355 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7356 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7357 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7358 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7359 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7360 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7361 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7362 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7363
7364 /*** VSX extension ***/
7365
7366 static inline TCGv_i64 cpu_vsrh(int n)
7367 {
7368 if (n < 32) {
7369 return cpu_fpr[n];
7370 } else {
7371 return cpu_avrh[n-32];
7372 }
7373 }
7374
7375 static inline TCGv_i64 cpu_vsrl(int n)
7376 {
7377 if (n < 32) {
7378 return cpu_vsr[n];
7379 } else {
7380 return cpu_avrl[n-32];
7381 }
7382 }
7383
7384 #define VSX_LOAD_SCALAR(name, operation) \
7385 static void gen_##name(DisasContext *ctx) \
7386 { \
7387 TCGv EA; \
7388 if (unlikely(!ctx->vsx_enabled)) { \
7389 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7390 return; \
7391 } \
7392 gen_set_access_type(ctx, ACCESS_INT); \
7393 EA = tcg_temp_new(); \
7394 gen_addr_reg_index(ctx, EA); \
7395 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7396 /* NOTE: cpu_vsrl is undefined */ \
7397 tcg_temp_free(EA); \
7398 }
7399
7400 VSX_LOAD_SCALAR(lxsdx, ld64)
7401 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7402 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7403 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7404
7405 static void gen_lxvd2x(DisasContext *ctx)
7406 {
7407 TCGv EA;
7408 if (unlikely(!ctx->vsx_enabled)) {
7409 gen_exception(ctx, POWERPC_EXCP_VSXU);
7410 return;
7411 }
7412 gen_set_access_type(ctx, ACCESS_INT);
7413 EA = tcg_temp_new();
7414 gen_addr_reg_index(ctx, EA);
7415 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7416 tcg_gen_addi_tl(EA, EA, 8);
7417 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7418 tcg_temp_free(EA);
7419 }
7420
7421 static void gen_lxvdsx(DisasContext *ctx)
7422 {
7423 TCGv EA;
7424 if (unlikely(!ctx->vsx_enabled)) {
7425 gen_exception(ctx, POWERPC_EXCP_VSXU);
7426 return;
7427 }
7428 gen_set_access_type(ctx, ACCESS_INT);
7429 EA = tcg_temp_new();
7430 gen_addr_reg_index(ctx, EA);
7431 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7432 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7433 tcg_temp_free(EA);
7434 }
7435
7436 static void gen_lxvw4x(DisasContext *ctx)
7437 {
7438 TCGv EA;
7439 TCGv_i64 tmp;
7440 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7441 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7442 if (unlikely(!ctx->vsx_enabled)) {
7443 gen_exception(ctx, POWERPC_EXCP_VSXU);
7444 return;
7445 }
7446 gen_set_access_type(ctx, ACCESS_INT);
7447 EA = tcg_temp_new();
7448 tmp = tcg_temp_new_i64();
7449
7450 gen_addr_reg_index(ctx, EA);
7451 gen_qemu_ld32u_i64(ctx, tmp, EA);
7452 tcg_gen_addi_tl(EA, EA, 4);
7453 gen_qemu_ld32u_i64(ctx, xth, EA);
7454 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7455
7456 tcg_gen_addi_tl(EA, EA, 4);
7457 gen_qemu_ld32u_i64(ctx, tmp, EA);
7458 tcg_gen_addi_tl(EA, EA, 4);
7459 gen_qemu_ld32u_i64(ctx, xtl, EA);
7460 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7461
7462 tcg_temp_free(EA);
7463 tcg_temp_free_i64(tmp);
7464 }
7465
7466 #define VSX_STORE_SCALAR(name, operation) \
7467 static void gen_##name(DisasContext *ctx) \
7468 { \
7469 TCGv EA; \
7470 if (unlikely(!ctx->vsx_enabled)) { \
7471 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7472 return; \
7473 } \
7474 gen_set_access_type(ctx, ACCESS_INT); \
7475 EA = tcg_temp_new(); \
7476 gen_addr_reg_index(ctx, EA); \
7477 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7478 tcg_temp_free(EA); \
7479 }
7480
7481 VSX_STORE_SCALAR(stxsdx, st64)
7482 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7483 VSX_STORE_SCALAR(stxsspx, st32fs)
7484
7485 static void gen_stxvd2x(DisasContext *ctx)
7486 {
7487 TCGv EA;
7488 if (unlikely(!ctx->vsx_enabled)) {
7489 gen_exception(ctx, POWERPC_EXCP_VSXU);
7490 return;
7491 }
7492 gen_set_access_type(ctx, ACCESS_INT);
7493 EA = tcg_temp_new();
7494 gen_addr_reg_index(ctx, EA);
7495 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7496 tcg_gen_addi_tl(EA, EA, 8);
7497 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7498 tcg_temp_free(EA);
7499 }
7500
7501 static void gen_stxvw4x(DisasContext *ctx)
7502 {
7503 TCGv_i64 tmp;
7504 TCGv EA;
7505 if (unlikely(!ctx->vsx_enabled)) {
7506 gen_exception(ctx, POWERPC_EXCP_VSXU);
7507 return;
7508 }
7509 gen_set_access_type(ctx, ACCESS_INT);
7510 EA = tcg_temp_new();
7511 gen_addr_reg_index(ctx, EA);
7512 tmp = tcg_temp_new_i64();
7513
7514 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7515 gen_qemu_st32_i64(ctx, tmp, EA);
7516 tcg_gen_addi_tl(EA, EA, 4);
7517 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7518
7519 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7520 tcg_gen_addi_tl(EA, EA, 4);
7521 gen_qemu_st32_i64(ctx, tmp, EA);
7522 tcg_gen_addi_tl(EA, EA, 4);
7523 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7524
7525 tcg_temp_free(EA);
7526 tcg_temp_free_i64(tmp);
7527 }
7528
7529 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7530 static void gen_##name(DisasContext *ctx) \
7531 { \
7532 if (xS(ctx->opcode) < 32) { \
7533 if (unlikely(!ctx->fpu_enabled)) { \
7534 gen_exception(ctx, POWERPC_EXCP_FPU); \
7535 return; \
7536 } \
7537 } else { \
7538 if (unlikely(!ctx->altivec_enabled)) { \
7539 gen_exception(ctx, POWERPC_EXCP_VPU); \
7540 return; \
7541 } \
7542 } \
7543 TCGv_i64 tmp = tcg_temp_new_i64(); \
7544 tcg_gen_##tcgop1(tmp, source); \
7545 tcg_gen_##tcgop2(target, tmp); \
7546 tcg_temp_free_i64(tmp); \
7547 }
7548
7549
7550 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7551 cpu_vsrh(xS(ctx->opcode)))
7552 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7553 cpu_gpr[rA(ctx->opcode)])
7554 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7555 cpu_gpr[rA(ctx->opcode)])
7556
7557 #if defined(TARGET_PPC64)
7558 #define MV_VSRD(name, target, source) \
7559 static void gen_##name(DisasContext *ctx) \
7560 { \
7561 if (xS(ctx->opcode) < 32) { \
7562 if (unlikely(!ctx->fpu_enabled)) { \
7563 gen_exception(ctx, POWERPC_EXCP_FPU); \
7564 return; \
7565 } \
7566 } else { \
7567 if (unlikely(!ctx->altivec_enabled)) { \
7568 gen_exception(ctx, POWERPC_EXCP_VPU); \
7569 return; \
7570 } \
7571 } \
7572 tcg_gen_mov_i64(target, source); \
7573 }
7574
7575 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7576 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7577
7578 #endif
7579
7580 static void gen_xxpermdi(DisasContext *ctx)
7581 {
7582 if (unlikely(!ctx->vsx_enabled)) {
7583 gen_exception(ctx, POWERPC_EXCP_VSXU);
7584 return;
7585 }
7586
7587 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7588 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7589 TCGv_i64 xh, xl;
7590
7591 xh = tcg_temp_new_i64();
7592 xl = tcg_temp_new_i64();
7593
7594 if ((DM(ctx->opcode) & 2) == 0) {
7595 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7596 } else {
7597 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7598 }
7599 if ((DM(ctx->opcode) & 1) == 0) {
7600 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7601 } else {
7602 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7603 }
7604
7605 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7606 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7607
7608 tcg_temp_free_i64(xh);
7609 tcg_temp_free_i64(xl);
7610 } else {
7611 if ((DM(ctx->opcode) & 2) == 0) {
7612 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7613 } else {
7614 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7615 }
7616 if ((DM(ctx->opcode) & 1) == 0) {
7617 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7618 } else {
7619 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7620 }
7621 }
7622 }
7623
7624 #define OP_ABS 1
7625 #define OP_NABS 2
7626 #define OP_NEG 3
7627 #define OP_CPSGN 4
7628 #define SGN_MASK_DP 0x8000000000000000ul
7629 #define SGN_MASK_SP 0x8000000080000000ul
7630
7631 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7632 static void glue(gen_, name)(DisasContext * ctx) \
7633 { \
7634 TCGv_i64 xb, sgm; \
7635 if (unlikely(!ctx->vsx_enabled)) { \
7636 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7637 return; \
7638 } \
7639 xb = tcg_temp_new_i64(); \
7640 sgm = tcg_temp_new_i64(); \
7641 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7642 tcg_gen_movi_i64(sgm, sgn_mask); \
7643 switch (op) { \
7644 case OP_ABS: { \
7645 tcg_gen_andc_i64(xb, xb, sgm); \
7646 break; \
7647 } \
7648 case OP_NABS: { \
7649 tcg_gen_or_i64(xb, xb, sgm); \
7650 break; \
7651 } \
7652 case OP_NEG: { \
7653 tcg_gen_xor_i64(xb, xb, sgm); \
7654 break; \
7655 } \
7656 case OP_CPSGN: { \
7657 TCGv_i64 xa = tcg_temp_new_i64(); \
7658 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7659 tcg_gen_and_i64(xa, xa, sgm); \
7660 tcg_gen_andc_i64(xb, xb, sgm); \
7661 tcg_gen_or_i64(xb, xb, xa); \
7662 tcg_temp_free_i64(xa); \
7663 break; \
7664 } \
7665 } \
7666 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7667 tcg_temp_free_i64(xb); \
7668 tcg_temp_free_i64(sgm); \
7669 }
7670
7671 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7672 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7673 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7674 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7675
7676 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7677 static void glue(gen_, name)(DisasContext * ctx) \
7678 { \
7679 TCGv_i64 xbh, xbl, sgm; \
7680 if (unlikely(!ctx->vsx_enabled)) { \
7681 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7682 return; \
7683 } \
7684 xbh = tcg_temp_new_i64(); \
7685 xbl = tcg_temp_new_i64(); \
7686 sgm = tcg_temp_new_i64(); \
7687 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7688 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7689 tcg_gen_movi_i64(sgm, sgn_mask); \
7690 switch (op) { \
7691 case OP_ABS: { \
7692 tcg_gen_andc_i64(xbh, xbh, sgm); \
7693 tcg_gen_andc_i64(xbl, xbl, sgm); \
7694 break; \
7695 } \
7696 case OP_NABS: { \
7697 tcg_gen_or_i64(xbh, xbh, sgm); \
7698 tcg_gen_or_i64(xbl, xbl, sgm); \
7699 break; \
7700 } \
7701 case OP_NEG: { \
7702 tcg_gen_xor_i64(xbh, xbh, sgm); \
7703 tcg_gen_xor_i64(xbl, xbl, sgm); \
7704 break; \
7705 } \
7706 case OP_CPSGN: { \
7707 TCGv_i64 xah = tcg_temp_new_i64(); \
7708 TCGv_i64 xal = tcg_temp_new_i64(); \
7709 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7710 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7711 tcg_gen_and_i64(xah, xah, sgm); \
7712 tcg_gen_and_i64(xal, xal, sgm); \
7713 tcg_gen_andc_i64(xbh, xbh, sgm); \
7714 tcg_gen_andc_i64(xbl, xbl, sgm); \
7715 tcg_gen_or_i64(xbh, xbh, xah); \
7716 tcg_gen_or_i64(xbl, xbl, xal); \
7717 tcg_temp_free_i64(xah); \
7718 tcg_temp_free_i64(xal); \
7719 break; \
7720 } \
7721 } \
7722 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7723 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7724 tcg_temp_free_i64(xbh); \
7725 tcg_temp_free_i64(xbl); \
7726 tcg_temp_free_i64(sgm); \
7727 }
7728
7729 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7730 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7731 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7732 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7733 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7734 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7735 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7736 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7737
7738 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7739 static void gen_##name(DisasContext * ctx) \
7740 { \
7741 TCGv_i32 opc; \
7742 if (unlikely(!ctx->vsx_enabled)) { \
7743 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7744 return; \
7745 } \
7746 /* NIP cannot be restored if the memory exception comes from an helper */ \
7747 gen_update_nip(ctx, ctx->nip - 4); \
7748 opc = tcg_const_i32(ctx->opcode); \
7749 gen_helper_##name(cpu_env, opc); \
7750 tcg_temp_free_i32(opc); \
7751 }
7752
7753 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7754 static void gen_##name(DisasContext * ctx) \
7755 { \
7756 if (unlikely(!ctx->vsx_enabled)) { \
7757 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7758 return; \
7759 } \
7760 /* NIP cannot be restored if the exception comes */ \
7761 /* from a helper. */ \
7762 gen_update_nip(ctx, ctx->nip - 4); \
7763 \
7764 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7765 cpu_vsrh(xB(ctx->opcode))); \
7766 }
7767
7768 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7769 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7770 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7771 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7772 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7773 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7774 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7775 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7776 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7777 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7778 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7779 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7780 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7781 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7782 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7783 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7784 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7785 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7786 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7787 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7788 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7789 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7790 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
7791 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7792 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
7793 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7794 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7795 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7796 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7797 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7798 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
7799 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7800 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7801 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7802 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7803 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
7804 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
7805
7806 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
7807 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
7808 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
7809 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
7810 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
7811 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
7812 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
7813 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
7814 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
7815 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
7816 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
7817 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
7818 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
7819 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
7820 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
7821 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
7822 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
7823
7824 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
7825 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
7826 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
7827 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
7828 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
7829 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
7830 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
7831 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
7832 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
7833 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
7834 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
7835 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
7836 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
7837 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
7838 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
7839 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
7840 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
7841 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
7842 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
7843 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
7844 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
7845 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
7846 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
7847 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
7848 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
7849 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
7850 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
7851 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
7852 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
7853 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
7854 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
7855 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
7856 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
7857 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
7858 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
7859 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
7860
7861 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
7862 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
7863 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
7864 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
7865 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
7866 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
7867 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
7868 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
7869 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
7870 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
7871 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
7872 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
7873 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
7874 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
7875 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
7876 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
7877 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
7878 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
7879 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
7880 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
7881 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
7882 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
7883 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
7884 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
7885 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
7886 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
7887 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
7888 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
7889 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
7890 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
7891 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
7892 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
7893 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
7894 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
7895 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
7896 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
7897
7898 #define VSX_LOGICAL(name, tcg_op) \
7899 static void glue(gen_, name)(DisasContext * ctx) \
7900 { \
7901 if (unlikely(!ctx->vsx_enabled)) { \
7902 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7903 return; \
7904 } \
7905 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
7906 cpu_vsrh(xB(ctx->opcode))); \
7907 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
7908 cpu_vsrl(xB(ctx->opcode))); \
7909 }
7910
7911 VSX_LOGICAL(xxland, tcg_gen_and_i64)
7912 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
7913 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
7914 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
7915 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
7916 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
7917 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
7918 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
7919
7920 #define VSX_XXMRG(name, high) \
7921 static void glue(gen_, name)(DisasContext * ctx) \
7922 { \
7923 TCGv_i64 a0, a1, b0, b1; \
7924 if (unlikely(!ctx->vsx_enabled)) { \
7925 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7926 return; \
7927 } \
7928 a0 = tcg_temp_new_i64(); \
7929 a1 = tcg_temp_new_i64(); \
7930 b0 = tcg_temp_new_i64(); \
7931 b1 = tcg_temp_new_i64(); \
7932 if (high) { \
7933 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
7934 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
7935 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
7936 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
7937 } else { \
7938 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
7939 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
7940 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
7941 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
7942 } \
7943 tcg_gen_shri_i64(a0, a0, 32); \
7944 tcg_gen_shri_i64(b0, b0, 32); \
7945 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
7946 b0, a0, 32, 32); \
7947 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
7948 b1, a1, 32, 32); \
7949 tcg_temp_free_i64(a0); \
7950 tcg_temp_free_i64(a1); \
7951 tcg_temp_free_i64(b0); \
7952 tcg_temp_free_i64(b1); \
7953 }
7954
7955 VSX_XXMRG(xxmrghw, 1)
7956 VSX_XXMRG(xxmrglw, 0)
7957
7958 static void gen_xxsel(DisasContext * ctx)
7959 {
7960 TCGv_i64 a, b, c;
7961 if (unlikely(!ctx->vsx_enabled)) {
7962 gen_exception(ctx, POWERPC_EXCP_VSXU);
7963 return;
7964 }
7965 a = tcg_temp_new_i64();
7966 b = tcg_temp_new_i64();
7967 c = tcg_temp_new_i64();
7968
7969 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
7970 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
7971 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
7972
7973 tcg_gen_and_i64(b, b, c);
7974 tcg_gen_andc_i64(a, a, c);
7975 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
7976
7977 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
7978 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
7979 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
7980
7981 tcg_gen_and_i64(b, b, c);
7982 tcg_gen_andc_i64(a, a, c);
7983 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
7984
7985 tcg_temp_free_i64(a);
7986 tcg_temp_free_i64(b);
7987 tcg_temp_free_i64(c);
7988 }
7989
7990 static void gen_xxspltw(DisasContext *ctx)
7991 {
7992 TCGv_i64 b, b2;
7993 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
7994 cpu_vsrl(xB(ctx->opcode)) :
7995 cpu_vsrh(xB(ctx->opcode));
7996
7997 if (unlikely(!ctx->vsx_enabled)) {
7998 gen_exception(ctx, POWERPC_EXCP_VSXU);
7999 return;
8000 }
8001
8002 b = tcg_temp_new_i64();
8003 b2 = tcg_temp_new_i64();
8004
8005 if (UIM(ctx->opcode) & 1) {
8006 tcg_gen_ext32u_i64(b, vsr);
8007 } else {
8008 tcg_gen_shri_i64(b, vsr, 32);
8009 }
8010
8011 tcg_gen_shli_i64(b2, b, 32);
8012 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8013 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8014
8015 tcg_temp_free_i64(b);
8016 tcg_temp_free_i64(b2);
8017 }
8018
8019 static void gen_xxsldwi(DisasContext *ctx)
8020 {
8021 TCGv_i64 xth, xtl;
8022 if (unlikely(!ctx->vsx_enabled)) {
8023 gen_exception(ctx, POWERPC_EXCP_VSXU);
8024 return;
8025 }
8026 xth = tcg_temp_new_i64();
8027 xtl = tcg_temp_new_i64();
8028
8029 switch (SHW(ctx->opcode)) {
8030 case 0: {
8031 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8032 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8033 break;
8034 }
8035 case 1: {
8036 TCGv_i64 t0 = tcg_temp_new_i64();
8037 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8038 tcg_gen_shli_i64(xth, xth, 32);
8039 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8040 tcg_gen_shri_i64(t0, t0, 32);
8041 tcg_gen_or_i64(xth, xth, t0);
8042 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8043 tcg_gen_shli_i64(xtl, xtl, 32);
8044 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8045 tcg_gen_shri_i64(t0, t0, 32);
8046 tcg_gen_or_i64(xtl, xtl, t0);
8047 tcg_temp_free_i64(t0);
8048 break;
8049 }
8050 case 2: {
8051 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8052 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8053 break;
8054 }
8055 case 3: {
8056 TCGv_i64 t0 = tcg_temp_new_i64();
8057 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8058 tcg_gen_shli_i64(xth, xth, 32);
8059 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8060 tcg_gen_shri_i64(t0, t0, 32);
8061 tcg_gen_or_i64(xth, xth, t0);
8062 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8063 tcg_gen_shli_i64(xtl, xtl, 32);
8064 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8065 tcg_gen_shri_i64(t0, t0, 32);
8066 tcg_gen_or_i64(xtl, xtl, t0);
8067 tcg_temp_free_i64(t0);
8068 break;
8069 }
8070 }
8071
8072 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8073 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8074
8075 tcg_temp_free_i64(xth);
8076 tcg_temp_free_i64(xtl);
8077 }
8078
8079
8080 /*** SPE extension ***/
8081 /* Register moves */
8082
8083 static inline void gen_evmra(DisasContext *ctx)
8084 {
8085
8086 if (unlikely(!ctx->spe_enabled)) {
8087 gen_exception(ctx, POWERPC_EXCP_SPEU);
8088 return;
8089 }
8090
8091 #if defined(TARGET_PPC64)
8092 /* rD := rA */
8093 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8094
8095 /* spe_acc := rA */
8096 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
8097 cpu_env,
8098 offsetof(CPUPPCState, spe_acc));
8099 #else
8100 TCGv_i64 tmp = tcg_temp_new_i64();
8101
8102 /* tmp := rA_lo + rA_hi << 32 */
8103 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8104
8105 /* spe_acc := tmp */
8106 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8107 tcg_temp_free_i64(tmp);
8108
8109 /* rD := rA */
8110 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8111 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8112 #endif
8113 }
8114
8115 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8116 {
8117 #if defined(TARGET_PPC64)
8118 tcg_gen_mov_i64(t, cpu_gpr[reg]);
8119 #else
8120 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8121 #endif
8122 }
8123
8124 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8125 {
8126 #if defined(TARGET_PPC64)
8127 tcg_gen_mov_i64(cpu_gpr[reg], t);
8128 #else
8129 TCGv_i64 tmp = tcg_temp_new_i64();
8130 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
8131 tcg_gen_shri_i64(tmp, t, 32);
8132 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
8133 tcg_temp_free_i64(tmp);
8134 #endif
8135 }
8136
8137 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8138 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8139 { \
8140 if (Rc(ctx->opcode)) \
8141 gen_##name1(ctx); \
8142 else \
8143 gen_##name0(ctx); \
8144 }
8145
8146 /* Handler for undefined SPE opcodes */
8147 static inline void gen_speundef(DisasContext *ctx)
8148 {
8149 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8150 }
8151
8152 /* SPE logic */
8153 #if defined(TARGET_PPC64)
8154 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8155 static inline void gen_##name(DisasContext *ctx) \
8156 { \
8157 if (unlikely(!ctx->spe_enabled)) { \
8158 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8159 return; \
8160 } \
8161 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8162 cpu_gpr[rB(ctx->opcode)]); \
8163 }
8164 #else
8165 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8166 static inline void gen_##name(DisasContext *ctx) \
8167 { \
8168 if (unlikely(!ctx->spe_enabled)) { \
8169 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8170 return; \
8171 } \
8172 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8173 cpu_gpr[rB(ctx->opcode)]); \
8174 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8175 cpu_gprh[rB(ctx->opcode)]); \
8176 }
8177 #endif
8178
8179 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8180 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8181 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8182 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8183 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8184 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8185 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8186 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8187
8188 /* SPE logic immediate */
8189 #if defined(TARGET_PPC64)
8190 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8191 static inline void gen_##name(DisasContext *ctx) \
8192 { \
8193 if (unlikely(!ctx->spe_enabled)) { \
8194 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8195 return; \
8196 } \
8197 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8198 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8199 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8200 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8201 tcg_opi(t0, t0, rB(ctx->opcode)); \
8202 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
8203 tcg_gen_trunc_i64_i32(t1, t2); \
8204 tcg_temp_free_i64(t2); \
8205 tcg_opi(t1, t1, rB(ctx->opcode)); \
8206 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
8207 tcg_temp_free_i32(t0); \
8208 tcg_temp_free_i32(t1); \
8209 }
8210 #else
8211 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8212 static inline void gen_##name(DisasContext *ctx) \
8213 { \
8214 if (unlikely(!ctx->spe_enabled)) { \
8215 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8216 return; \
8217 } \
8218 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8219 rB(ctx->opcode)); \
8220 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8221 rB(ctx->opcode)); \
8222 }
8223 #endif
8224 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8225 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8226 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8227 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8228
8229 /* SPE arithmetic */
8230 #if defined(TARGET_PPC64)
8231 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8232 static inline void gen_##name(DisasContext *ctx) \
8233 { \
8234 if (unlikely(!ctx->spe_enabled)) { \
8235 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8236 return; \
8237 } \
8238 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8239 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8240 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8241 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8242 tcg_op(t0, t0); \
8243 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
8244 tcg_gen_trunc_i64_i32(t1, t2); \
8245 tcg_temp_free_i64(t2); \
8246 tcg_op(t1, t1); \
8247 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
8248 tcg_temp_free_i32(t0); \
8249 tcg_temp_free_i32(t1); \
8250 }
8251 #else
8252 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8253 static inline void gen_##name(DisasContext *ctx) \
8254 { \
8255 if (unlikely(!ctx->spe_enabled)) { \
8256 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8257 return; \
8258 } \
8259 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8260 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8261 }
8262 #endif
8263
8264 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8265 {
8266 int l1 = gen_new_label();
8267 int l2 = gen_new_label();
8268
8269 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8270 tcg_gen_neg_i32(ret, arg1);
8271 tcg_gen_br(l2);
8272 gen_set_label(l1);
8273 tcg_gen_mov_i32(ret, arg1);
8274 gen_set_label(l2);
8275 }
8276 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8277 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8278 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8279 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8280 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8281 {
8282 tcg_gen_addi_i32(ret, arg1, 0x8000);
8283 tcg_gen_ext16u_i32(ret, ret);
8284 }
8285 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8286 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8287 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8288
8289 #if defined(TARGET_PPC64)
8290 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8291 static inline void gen_##name(DisasContext *ctx) \
8292 { \
8293 if (unlikely(!ctx->spe_enabled)) { \
8294 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8295 return; \
8296 } \
8297 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8298 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8299 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
8300 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
8301 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8302 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
8303 tcg_op(t0, t0, t2); \
8304 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
8305 tcg_gen_trunc_i64_i32(t1, t3); \
8306 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
8307 tcg_gen_trunc_i64_i32(t2, t3); \
8308 tcg_temp_free_i64(t3); \
8309 tcg_op(t1, t1, t2); \
8310 tcg_temp_free_i32(t2); \
8311 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
8312 tcg_temp_free_i32(t0); \
8313 tcg_temp_free_i32(t1); \
8314 }
8315 #else
8316 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8317 static inline void gen_##name(DisasContext *ctx) \
8318 { \
8319 if (unlikely(!ctx->spe_enabled)) { \
8320 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8321 return; \
8322 } \
8323 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8324 cpu_gpr[rB(ctx->opcode)]); \
8325 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8326 cpu_gprh[rB(ctx->opcode)]); \
8327 }
8328 #endif
8329
8330 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8331 {
8332 TCGv_i32 t0;
8333 int l1, l2;
8334
8335 l1 = gen_new_label();
8336 l2 = gen_new_label();
8337 t0 = tcg_temp_local_new_i32();
8338 /* No error here: 6 bits are used */
8339 tcg_gen_andi_i32(t0, arg2, 0x3F);
8340 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8341 tcg_gen_shr_i32(ret, arg1, t0);
8342 tcg_gen_br(l2);
8343 gen_set_label(l1);
8344 tcg_gen_movi_i32(ret, 0);
8345 gen_set_label(l2);
8346 tcg_temp_free_i32(t0);
8347 }
8348 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8349 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8350 {
8351 TCGv_i32 t0;
8352 int l1, l2;
8353
8354 l1 = gen_new_label();
8355 l2 = gen_new_label();
8356 t0 = tcg_temp_local_new_i32();
8357 /* No error here: 6 bits are used */
8358 tcg_gen_andi_i32(t0, arg2, 0x3F);
8359 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8360 tcg_gen_sar_i32(ret, arg1, t0);
8361 tcg_gen_br(l2);
8362 gen_set_label(l1);
8363 tcg_gen_movi_i32(ret, 0);
8364 gen_set_label(l2);
8365 tcg_temp_free_i32(t0);
8366 }
8367 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8368 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8369 {
8370 TCGv_i32 t0;
8371 int l1, l2;
8372
8373 l1 = gen_new_label();
8374 l2 = gen_new_label();
8375 t0 = tcg_temp_local_new_i32();
8376 /* No error here: 6 bits are used */
8377 tcg_gen_andi_i32(t0, arg2, 0x3F);
8378 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8379 tcg_gen_shl_i32(ret, arg1, t0);
8380 tcg_gen_br(l2);
8381 gen_set_label(l1);
8382 tcg_gen_movi_i32(ret, 0);
8383 gen_set_label(l2);
8384 tcg_temp_free_i32(t0);
8385 }
8386 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8387 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8388 {
8389 TCGv_i32 t0 = tcg_temp_new_i32();
8390 tcg_gen_andi_i32(t0, arg2, 0x1F);
8391 tcg_gen_rotl_i32(ret, arg1, t0);
8392 tcg_temp_free_i32(t0);
8393 }
8394 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8395 static inline void gen_evmergehi(DisasContext *ctx)
8396 {
8397 if (unlikely(!ctx->spe_enabled)) {
8398 gen_exception(ctx, POWERPC_EXCP_SPEU);
8399 return;
8400 }
8401 #if defined(TARGET_PPC64)
8402 TCGv t0 = tcg_temp_new();
8403 TCGv t1 = tcg_temp_new();
8404 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
8405 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
8406 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8407 tcg_temp_free(t0);
8408 tcg_temp_free(t1);
8409 #else
8410 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8411 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8412 #endif
8413 }
8414 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8415 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8416 {
8417 tcg_gen_sub_i32(ret, arg2, arg1);
8418 }
8419 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8420
8421 /* SPE arithmetic immediate */
8422 #if defined(TARGET_PPC64)
8423 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8424 static inline void gen_##name(DisasContext *ctx) \
8425 { \
8426 if (unlikely(!ctx->spe_enabled)) { \
8427 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8428 return; \
8429 } \
8430 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8431 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8432 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8433 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8434 tcg_op(t0, t0, rA(ctx->opcode)); \
8435 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
8436 tcg_gen_trunc_i64_i32(t1, t2); \
8437 tcg_temp_free_i64(t2); \
8438 tcg_op(t1, t1, rA(ctx->opcode)); \
8439 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
8440 tcg_temp_free_i32(t0); \
8441 tcg_temp_free_i32(t1); \
8442 }
8443 #else
8444 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8445 static inline void gen_##name(DisasContext *ctx) \
8446 { \
8447 if (unlikely(!ctx->spe_enabled)) { \
8448 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8449 return; \
8450 } \
8451 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
8452 rA(ctx->opcode)); \
8453 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
8454 rA(ctx->opcode)); \
8455 }
8456 #endif
8457 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8458 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8459
8460 /* SPE comparison */
8461 #if defined(TARGET_PPC64)
8462 #define GEN_SPEOP_COMP(name, tcg_cond) \
8463 static inline void gen_##name(DisasContext *ctx) \
8464 { \
8465 if (unlikely(!ctx->spe_enabled)) { \
8466 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8467 return; \
8468 } \
8469 int l1 = gen_new_label(); \
8470 int l2 = gen_new_label(); \
8471 int l3 = gen_new_label(); \
8472 int l4 = gen_new_label(); \
8473 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8474 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8475 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8476 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8477 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8478 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
8479 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8480 tcg_gen_br(l2); \
8481 gen_set_label(l1); \
8482 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8483 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8484 gen_set_label(l2); \
8485 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
8486 tcg_gen_trunc_i64_i32(t0, t2); \
8487 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
8488 tcg_gen_trunc_i64_i32(t1, t2); \
8489 tcg_temp_free_i64(t2); \
8490 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
8491 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8492 ~(CRF_CH | CRF_CH_AND_CL)); \
8493 tcg_gen_br(l4); \
8494 gen_set_label(l3); \
8495 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8496 CRF_CH | CRF_CH_OR_CL); \
8497 gen_set_label(l4); \
8498 tcg_temp_free_i32(t0); \
8499 tcg_temp_free_i32(t1); \
8500 }
8501 #else
8502 #define GEN_SPEOP_COMP(name, tcg_cond) \
8503 static inline void gen_##name(DisasContext *ctx) \
8504 { \
8505 if (unlikely(!ctx->spe_enabled)) { \
8506 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8507 return; \
8508 } \
8509 int l1 = gen_new_label(); \
8510 int l2 = gen_new_label(); \
8511 int l3 = gen_new_label(); \
8512 int l4 = gen_new_label(); \
8513 \
8514 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8515 cpu_gpr[rB(ctx->opcode)], l1); \
8516 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
8517 tcg_gen_br(l2); \
8518 gen_set_label(l1); \
8519 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8520 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8521 gen_set_label(l2); \
8522 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8523 cpu_gprh[rB(ctx->opcode)], l3); \
8524 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8525 ~(CRF_CH | CRF_CH_AND_CL)); \
8526 tcg_gen_br(l4); \
8527 gen_set_label(l3); \
8528 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8529 CRF_CH | CRF_CH_OR_CL); \
8530 gen_set_label(l4); \
8531 }
8532 #endif
8533 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8534 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8535 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8536 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8537 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8538
8539 /* SPE misc */
8540 static inline void gen_brinc(DisasContext *ctx)
8541 {
8542 /* Note: brinc is usable even if SPE is disabled */
8543 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8544 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8545 }
8546 static inline void gen_evmergelo(DisasContext *ctx)
8547 {
8548 if (unlikely(!ctx->spe_enabled)) {
8549 gen_exception(ctx, POWERPC_EXCP_SPEU);
8550 return;
8551 }
8552 #if defined(TARGET_PPC64)
8553 TCGv t0 = tcg_temp_new();
8554 TCGv t1 = tcg_temp_new();
8555 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
8556 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
8557 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8558 tcg_temp_free(t0);
8559 tcg_temp_free(t1);
8560 #else
8561 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8562 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8563 #endif
8564 }
8565 static inline void gen_evmergehilo(DisasContext *ctx)
8566 {
8567 if (unlikely(!ctx->spe_enabled)) {
8568 gen_exception(ctx, POWERPC_EXCP_SPEU);
8569 return;
8570 }
8571 #if defined(TARGET_PPC64)
8572 TCGv t0 = tcg_temp_new();
8573 TCGv t1 = tcg_temp_new();
8574 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
8575 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
8576 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8577 tcg_temp_free(t0);
8578 tcg_temp_free(t1);
8579 #else
8580 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8581 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8582 #endif
8583 }
8584 static inline void gen_evmergelohi(DisasContext *ctx)
8585 {
8586 if (unlikely(!ctx->spe_enabled)) {
8587 gen_exception(ctx, POWERPC_EXCP_SPEU);
8588 return;
8589 }
8590 #if defined(TARGET_PPC64)
8591 TCGv t0 = tcg_temp_new();
8592 TCGv t1 = tcg_temp_new();
8593 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
8594 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
8595 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8596 tcg_temp_free(t0);
8597 tcg_temp_free(t1);
8598 #else
8599 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8600 TCGv_i32 tmp = tcg_temp_new_i32();
8601 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
8602 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8603 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
8604 tcg_temp_free_i32(tmp);
8605 } else {
8606 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8607 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8608 }
8609 #endif
8610 }
8611 static inline void gen_evsplati(DisasContext *ctx)
8612 {
8613 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8614
8615 #if defined(TARGET_PPC64)
8616 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
8617 #else
8618 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
8619 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
8620 #endif
8621 }
8622 static inline void gen_evsplatfi(DisasContext *ctx)
8623 {
8624 uint64_t imm = rA(ctx->opcode) << 27;
8625
8626 #if defined(TARGET_PPC64)
8627 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
8628 #else
8629 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
8630 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
8631 #endif
8632 }
8633
8634 static inline void gen_evsel(DisasContext *ctx)
8635 {
8636 int l1 = gen_new_label();
8637 int l2 = gen_new_label();
8638 int l3 = gen_new_label();
8639 int l4 = gen_new_label();
8640 TCGv_i32 t0 = tcg_temp_local_new_i32();
8641 #if defined(TARGET_PPC64)
8642 TCGv t1 = tcg_temp_local_new();
8643 TCGv t2 = tcg_temp_local_new();
8644 #endif
8645 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8646 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8647 #if defined(TARGET_PPC64)
8648 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
8649 #else
8650 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8651 #endif
8652 tcg_gen_br(l2);
8653 gen_set_label(l1);
8654 #if defined(TARGET_PPC64)
8655 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
8656 #else
8657 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8658 #endif
8659 gen_set_label(l2);
8660 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8661 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8662 #if defined(TARGET_PPC64)
8663 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
8664 #else
8665 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8666 #endif
8667 tcg_gen_br(l4);
8668 gen_set_label(l3);
8669 #if defined(TARGET_PPC64)
8670 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
8671 #else
8672 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8673 #endif
8674 gen_set_label(l4);
8675 tcg_temp_free_i32(t0);
8676 #if defined(TARGET_PPC64)
8677 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
8678 tcg_temp_free(t1);
8679 tcg_temp_free(t2);
8680 #endif
8681 }
8682
8683 static void gen_evsel0(DisasContext *ctx)
8684 {
8685 gen_evsel(ctx);
8686 }
8687
8688 static void gen_evsel1(DisasContext *ctx)
8689 {
8690 gen_evsel(ctx);
8691 }
8692
8693 static void gen_evsel2(DisasContext *ctx)
8694 {
8695 gen_evsel(ctx);
8696 }
8697
8698 static void gen_evsel3(DisasContext *ctx)
8699 {
8700 gen_evsel(ctx);
8701 }
8702
8703 /* Multiply */
8704
8705 static inline void gen_evmwumi(DisasContext *ctx)
8706 {
8707 TCGv_i64 t0, t1;
8708
8709 if (unlikely(!ctx->spe_enabled)) {
8710 gen_exception(ctx, POWERPC_EXCP_SPEU);
8711 return;
8712 }
8713
8714 t0 = tcg_temp_new_i64();
8715 t1 = tcg_temp_new_i64();
8716
8717 /* t0 := rA; t1 := rB */
8718 #if defined(TARGET_PPC64)
8719 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
8720 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
8721 #else
8722 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8723 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8724 #endif
8725
8726 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8727
8728 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8729
8730 tcg_temp_free_i64(t0);
8731 tcg_temp_free_i64(t1);
8732 }
8733
8734 static inline void gen_evmwumia(DisasContext *ctx)
8735 {
8736 TCGv_i64 tmp;
8737
8738 if (unlikely(!ctx->spe_enabled)) {
8739 gen_exception(ctx, POWERPC_EXCP_SPEU);
8740 return;
8741 }
8742
8743 gen_evmwumi(ctx); /* rD := rA * rB */
8744
8745 tmp = tcg_temp_new_i64();
8746
8747 /* acc := rD */
8748 gen_load_gpr64(tmp, rD(ctx->opcode));
8749 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8750 tcg_temp_free_i64(tmp);
8751 }
8752
8753 static inline void gen_evmwumiaa(DisasContext *ctx)
8754 {
8755 TCGv_i64 acc;
8756 TCGv_i64 tmp;
8757
8758 if (unlikely(!ctx->spe_enabled)) {
8759 gen_exception(ctx, POWERPC_EXCP_SPEU);
8760 return;
8761 }
8762
8763 gen_evmwumi(ctx); /* rD := rA * rB */
8764
8765 acc = tcg_temp_new_i64();
8766 tmp = tcg_temp_new_i64();
8767
8768 /* tmp := rD */
8769 gen_load_gpr64(tmp, rD(ctx->opcode));
8770
8771 /* Load acc */
8772 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8773
8774 /* acc := tmp + acc */
8775 tcg_gen_add_i64(acc, acc, tmp);
8776
8777 /* Store acc */
8778 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8779
8780 /* rD := acc */
8781 gen_store_gpr64(rD(ctx->opcode), acc);
8782
8783 tcg_temp_free_i64(acc);
8784 tcg_temp_free_i64(tmp);
8785 }
8786
8787 static inline void gen_evmwsmi(DisasContext *ctx)
8788 {
8789 TCGv_i64 t0, t1;
8790
8791 if (unlikely(!ctx->spe_enabled)) {
8792 gen_exception(ctx, POWERPC_EXCP_SPEU);
8793 return;
8794 }
8795
8796 t0 = tcg_temp_new_i64();
8797 t1 = tcg_temp_new_i64();
8798
8799 /* t0 := rA; t1 := rB */
8800 #if defined(TARGET_PPC64)
8801 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
8802 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
8803 #else
8804 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8805 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8806 #endif
8807
8808 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8809
8810 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8811
8812 tcg_temp_free_i64(t0);
8813 tcg_temp_free_i64(t1);
8814 }
8815
8816 static inline void gen_evmwsmia(DisasContext *ctx)
8817 {
8818 TCGv_i64 tmp;
8819
8820 gen_evmwsmi(ctx); /* rD := rA * rB */
8821
8822 tmp = tcg_temp_new_i64();
8823
8824 /* acc := rD */
8825 gen_load_gpr64(tmp, rD(ctx->opcode));
8826 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8827
8828 tcg_temp_free_i64(tmp);
8829 }
8830
8831 static inline void gen_evmwsmiaa(DisasContext *ctx)
8832 {
8833 TCGv_i64 acc = tcg_temp_new_i64();
8834 TCGv_i64 tmp = tcg_temp_new_i64();
8835
8836 gen_evmwsmi(ctx); /* rD := rA * rB */
8837
8838 acc = tcg_temp_new_i64();
8839 tmp = tcg_temp_new_i64();
8840
8841 /* tmp := rD */
8842 gen_load_gpr64(tmp, rD(ctx->opcode));
8843
8844 /* Load acc */
8845 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8846
8847 /* acc := tmp + acc */
8848 tcg_gen_add_i64(acc, acc, tmp);
8849
8850 /* Store acc */
8851 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8852
8853 /* rD := acc */
8854 gen_store_gpr64(rD(ctx->opcode), acc);
8855
8856 tcg_temp_free_i64(acc);
8857 tcg_temp_free_i64(tmp);
8858 }
8859
8860 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8861 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8862 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8863 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8864 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8865 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8866 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8867 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
8868 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
8869 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8870 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8871 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8872 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8873 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8874 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8875 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8876 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8877 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8878 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8879 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
8880 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8881 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8882 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
8883 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
8884 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8885 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8886 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8887 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8888 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
8889
8890 /* SPE load and stores */
8891 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
8892 {
8893 target_ulong uimm = rB(ctx->opcode);
8894
8895 if (rA(ctx->opcode) == 0) {
8896 tcg_gen_movi_tl(EA, uimm << sh);
8897 } else {
8898 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
8899 if (NARROW_MODE(ctx)) {
8900 tcg_gen_ext32u_tl(EA, EA);
8901 }
8902 }
8903 }
8904
8905 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
8906 {
8907 #if defined(TARGET_PPC64)
8908 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8909 #else
8910 TCGv_i64 t0 = tcg_temp_new_i64();
8911 gen_qemu_ld64(ctx, t0, addr);
8912 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
8913 tcg_gen_shri_i64(t0, t0, 32);
8914 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
8915 tcg_temp_free_i64(t0);
8916 #endif
8917 }
8918
8919 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
8920 {
8921 #if defined(TARGET_PPC64)
8922 TCGv t0 = tcg_temp_new();
8923 gen_qemu_ld32u(ctx, t0, addr);
8924 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8925 gen_addr_add(ctx, addr, addr, 4);
8926 gen_qemu_ld32u(ctx, t0, addr);
8927 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8928 tcg_temp_free(t0);
8929 #else
8930 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
8931 gen_addr_add(ctx, addr, addr, 4);
8932 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8933 #endif
8934 }
8935
8936 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
8937 {
8938 TCGv t0 = tcg_temp_new();
8939 #if defined(TARGET_PPC64)
8940 gen_qemu_ld16u(ctx, t0, addr);
8941 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8942 gen_addr_add(ctx, addr, addr, 2);
8943 gen_qemu_ld16u(ctx, t0, addr);
8944 tcg_gen_shli_tl(t0, t0, 32);
8945 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8946 gen_addr_add(ctx, addr, addr, 2);
8947 gen_qemu_ld16u(ctx, t0, addr);
8948 tcg_gen_shli_tl(t0, t0, 16);
8949 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8950 gen_addr_add(ctx, addr, addr, 2);
8951 gen_qemu_ld16u(ctx, t0, addr);
8952 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8953 #else
8954 gen_qemu_ld16u(ctx, t0, addr);
8955 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8956 gen_addr_add(ctx, addr, addr, 2);
8957 gen_qemu_ld16u(ctx, t0, addr);
8958 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
8959 gen_addr_add(ctx, addr, addr, 2);
8960 gen_qemu_ld16u(ctx, t0, addr);
8961 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8962 gen_addr_add(ctx, addr, addr, 2);
8963 gen_qemu_ld16u(ctx, t0, addr);
8964 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8965 #endif
8966 tcg_temp_free(t0);
8967 }
8968
8969 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
8970 {
8971 TCGv t0 = tcg_temp_new();
8972 gen_qemu_ld16u(ctx, t0, addr);
8973 #if defined(TARGET_PPC64)
8974 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8975 tcg_gen_shli_tl(t0, t0, 16);
8976 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8977 #else
8978 tcg_gen_shli_tl(t0, t0, 16);
8979 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8980 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8981 #endif
8982 tcg_temp_free(t0);
8983 }
8984
8985 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
8986 {
8987 TCGv t0 = tcg_temp_new();
8988 gen_qemu_ld16u(ctx, t0, addr);
8989 #if defined(TARGET_PPC64)
8990 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8991 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8992 #else
8993 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8994 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8995 #endif
8996 tcg_temp_free(t0);
8997 }
8998
8999 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9000 {
9001 TCGv t0 = tcg_temp_new();
9002 gen_qemu_ld16s(ctx, t0, addr);
9003 #if defined(TARGET_PPC64)
9004 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
9005 tcg_gen_ext32u_tl(t0, t0);
9006 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9007 #else
9008 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9009 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9010 #endif
9011 tcg_temp_free(t0);
9012 }
9013
9014 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9015 {
9016 TCGv t0 = tcg_temp_new();
9017 #if defined(TARGET_PPC64)
9018 gen_qemu_ld16u(ctx, t0, addr);
9019 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
9020 gen_addr_add(ctx, addr, addr, 2);
9021 gen_qemu_ld16u(ctx, t0, addr);
9022 tcg_gen_shli_tl(t0, t0, 16);
9023 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9024 #else
9025 gen_qemu_ld16u(ctx, t0, addr);
9026 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9027 gen_addr_add(ctx, addr, addr, 2);
9028 gen_qemu_ld16u(ctx, t0, addr);
9029 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9030 #endif
9031 tcg_temp_free(t0);
9032 }
9033
9034 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9035 {
9036 #if defined(TARGET_PPC64)
9037 TCGv t0 = tcg_temp_new();
9038 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9039 gen_addr_add(ctx, addr, addr, 2);
9040 gen_qemu_ld16u(ctx, t0, addr);
9041 tcg_gen_shli_tl(t0, t0, 32);
9042 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9043 tcg_temp_free(t0);
9044 #else
9045 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9046 gen_addr_add(ctx, addr, addr, 2);
9047 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9048 #endif
9049 }
9050
9051 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9052 {
9053 #if defined(TARGET_PPC64)
9054 TCGv t0 = tcg_temp_new();
9055 gen_qemu_ld16s(ctx, t0, addr);
9056 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
9057 gen_addr_add(ctx, addr, addr, 2);
9058 gen_qemu_ld16s(ctx, t0, addr);
9059 tcg_gen_shli_tl(t0, t0, 32);
9060 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9061 tcg_temp_free(t0);
9062 #else
9063 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9064 gen_addr_add(ctx, addr, addr, 2);
9065 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9066 #endif
9067 }
9068
9069 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9070 {
9071 TCGv t0 = tcg_temp_new();
9072 gen_qemu_ld32u(ctx, t0, addr);
9073 #if defined(TARGET_PPC64)
9074 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
9075 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9076 #else
9077 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9078 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9079 #endif
9080 tcg_temp_free(t0);
9081 }
9082
9083 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9084 {
9085 TCGv t0 = tcg_temp_new();
9086 #if defined(TARGET_PPC64)
9087 gen_qemu_ld16u(ctx, t0, addr);
9088 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
9089 tcg_gen_shli_tl(t0, t0, 32);
9090 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9091 gen_addr_add(ctx, addr, addr, 2);
9092 gen_qemu_ld16u(ctx, t0, addr);
9093 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9094 tcg_gen_shli_tl(t0, t0, 16);
9095 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9096 #else
9097 gen_qemu_ld16u(ctx, t0, addr);
9098 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9099 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9100 gen_addr_add(ctx, addr, addr, 2);
9101 gen_qemu_ld16u(ctx, t0, addr);
9102 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9103 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9104 #endif
9105 tcg_temp_free(t0);
9106 }
9107
9108 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9109 {
9110 #if defined(TARGET_PPC64)
9111 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9112 #else
9113 TCGv_i64 t0 = tcg_temp_new_i64();
9114 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
9115 gen_qemu_st64(ctx, t0, addr);
9116 tcg_temp_free_i64(t0);
9117 #endif
9118 }
9119
9120 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9121 {
9122 #if defined(TARGET_PPC64)
9123 TCGv t0 = tcg_temp_new();
9124 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
9125 gen_qemu_st32(ctx, t0, addr);
9126 tcg_temp_free(t0);
9127 #else
9128 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9129 #endif
9130 gen_addr_add(ctx, addr, addr, 4);
9131 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9132 }
9133
9134 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9135 {
9136 TCGv t0 = tcg_temp_new();
9137 #if defined(TARGET_PPC64)
9138 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
9139 #else
9140 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9141 #endif
9142 gen_qemu_st16(ctx, t0, addr);
9143 gen_addr_add(ctx, addr, addr, 2);
9144 #if defined(TARGET_PPC64)
9145 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
9146 gen_qemu_st16(ctx, t0, addr);
9147 #else
9148 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9149 #endif
9150 gen_addr_add(ctx, addr, addr, 2);
9151 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9152 gen_qemu_st16(ctx, t0, addr);
9153 tcg_temp_free(t0);
9154 gen_addr_add(ctx, addr, addr, 2);
9155 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9156 }
9157
9158 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9159 {
9160 TCGv t0 = tcg_temp_new();
9161 #if defined(TARGET_PPC64)
9162 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
9163 #else
9164 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9165 #endif
9166 gen_qemu_st16(ctx, t0, addr);
9167 gen_addr_add(ctx, addr, addr, 2);
9168 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9169 gen_qemu_st16(ctx, t0, addr);
9170 tcg_temp_free(t0);
9171 }
9172
9173 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9174 {
9175 #if defined(TARGET_PPC64)
9176 TCGv t0 = tcg_temp_new();
9177 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
9178 gen_qemu_st16(ctx, t0, addr);
9179 tcg_temp_free(t0);
9180 #else
9181 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9182 #endif
9183 gen_addr_add(ctx, addr, addr, 2);
9184 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9185 }
9186
9187 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9188 {
9189 #if defined(TARGET_PPC64)
9190 TCGv t0 = tcg_temp_new();
9191 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
9192 gen_qemu_st32(ctx, t0, addr);
9193 tcg_temp_free(t0);
9194 #else
9195 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9196 #endif
9197 }
9198
9199 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9200 {
9201 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9202 }
9203
9204 #define GEN_SPEOP_LDST(name, opc2, sh) \
9205 static void glue(gen_, name)(DisasContext *ctx) \
9206 { \
9207 TCGv t0; \
9208 if (unlikely(!ctx->spe_enabled)) { \
9209 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9210 return; \
9211 } \
9212 gen_set_access_type(ctx, ACCESS_INT); \
9213 t0 = tcg_temp_new(); \
9214 if (Rc(ctx->opcode)) { \
9215 gen_addr_spe_imm_index(ctx, t0, sh); \
9216 } else { \
9217 gen_addr_reg_index(ctx, t0); \
9218 } \
9219 gen_op_##name(ctx, t0); \
9220 tcg_temp_free(t0); \
9221 }
9222
9223 GEN_SPEOP_LDST(evldd, 0x00, 3);
9224 GEN_SPEOP_LDST(evldw, 0x01, 3);
9225 GEN_SPEOP_LDST(evldh, 0x02, 3);
9226 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9227 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9228 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9229 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9230 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9231 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9232 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9233 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9234
9235 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9236 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9237 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9238 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9239 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9240 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9241 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9242
9243 /* Multiply and add - TODO */
9244 #if 0
9245 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9246 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9247 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9248 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9249 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9250 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9251 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9252 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9253 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9254 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9255 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9256 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9257
9258 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9259 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9260 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9261 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9262 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9263 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9264 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9265 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9266 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9267 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9268 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9269 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9270
9271 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9272 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9273 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9274 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9275 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9276
9277 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9278 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9279 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9280 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9281 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9282 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9283 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9284 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9285 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9286 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9287 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9288 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9289
9290 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9291 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9292 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9293 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9294
9295 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9296 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9297 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9298 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9299 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9300 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9301 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9302 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9303 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9304 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9305 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9306 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9307
9308 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9309 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9310 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9311 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9312 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9313 #endif
9314
9315 /*** SPE floating-point extension ***/
9316 #if defined(TARGET_PPC64)
9317 #define GEN_SPEFPUOP_CONV_32_32(name) \
9318 static inline void gen_##name(DisasContext *ctx) \
9319 { \
9320 TCGv_i32 t0; \
9321 TCGv t1; \
9322 t0 = tcg_temp_new_i32(); \
9323 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9324 gen_helper_##name(t0, cpu_env, t0); \
9325 t1 = tcg_temp_new(); \
9326 tcg_gen_extu_i32_tl(t1, t0); \
9327 tcg_temp_free_i32(t0); \
9328 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9329 0xFFFFFFFF00000000ULL); \
9330 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
9331 tcg_temp_free(t1); \
9332 }
9333 #define GEN_SPEFPUOP_CONV_32_64(name) \
9334 static inline void gen_##name(DisasContext *ctx) \
9335 { \
9336 TCGv_i32 t0; \
9337 TCGv t1; \
9338 t0 = tcg_temp_new_i32(); \
9339 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
9340 t1 = tcg_temp_new(); \
9341 tcg_gen_extu_i32_tl(t1, t0); \
9342 tcg_temp_free_i32(t0); \
9343 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9344 0xFFFFFFFF00000000ULL); \
9345 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
9346 tcg_temp_free(t1); \
9347 }
9348 #define GEN_SPEFPUOP_CONV_64_32(name) \
9349 static inline void gen_##name(DisasContext *ctx) \
9350 { \
9351 TCGv_i32 t0 = tcg_temp_new_i32(); \
9352 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9353 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
9354 tcg_temp_free_i32(t0); \
9355 }
9356 #define GEN_SPEFPUOP_CONV_64_64(name) \
9357 static inline void gen_##name(DisasContext *ctx) \
9358 { \
9359 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9360 cpu_gpr[rB(ctx->opcode)]); \
9361 }
9362 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9363 static inline void gen_##name(DisasContext *ctx) \
9364 { \
9365 TCGv_i32 t0, t1; \
9366 TCGv_i64 t2; \
9367 if (unlikely(!ctx->spe_enabled)) { \
9368 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9369 return; \
9370 } \
9371 t0 = tcg_temp_new_i32(); \
9372 t1 = tcg_temp_new_i32(); \
9373 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9374 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9375 gen_helper_##name(t0, cpu_env, t0, t1); \
9376 tcg_temp_free_i32(t1); \
9377 t2 = tcg_temp_new(); \
9378 tcg_gen_extu_i32_tl(t2, t0); \
9379 tcg_temp_free_i32(t0); \
9380 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9381 0xFFFFFFFF00000000ULL); \
9382 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
9383 tcg_temp_free(t2); \
9384 }
9385 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9386 static inline void gen_##name(DisasContext *ctx) \
9387 { \
9388 if (unlikely(!ctx->spe_enabled)) { \
9389 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9390 return; \
9391 } \
9392 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9393 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9394 }
9395 #define GEN_SPEFPUOP_COMP_32(name) \
9396 static inline void gen_##name(DisasContext *ctx) \
9397 { \
9398 TCGv_i32 t0, t1; \
9399 if (unlikely(!ctx->spe_enabled)) { \
9400 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9401 return; \
9402 } \
9403 t0 = tcg_temp_new_i32(); \
9404 t1 = tcg_temp_new_i32(); \
9405 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9406 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9407 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9408 tcg_temp_free_i32(t0); \
9409 tcg_temp_free_i32(t1); \
9410 }
9411 #define GEN_SPEFPUOP_COMP_64(name) \
9412 static inline void gen_##name(DisasContext *ctx) \
9413 { \
9414 if (unlikely(!ctx->spe_enabled)) { \
9415 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9416 return; \
9417 } \
9418 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
9419 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9420 }
9421 #else
9422 #define GEN_SPEFPUOP_CONV_32_32(name) \
9423 static inline void gen_##name(DisasContext *ctx) \
9424 { \
9425 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9426 cpu_gpr[rB(ctx->opcode)]); \
9427 }
9428 #define GEN_SPEFPUOP_CONV_32_64(name) \
9429 static inline void gen_##name(DisasContext *ctx) \
9430 { \
9431 TCGv_i64 t0 = tcg_temp_new_i64(); \
9432 gen_load_gpr64(t0, rB(ctx->opcode)); \
9433 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
9434 tcg_temp_free_i64(t0); \
9435 }
9436 #define GEN_SPEFPUOP_CONV_64_32(name) \
9437 static inline void gen_##name(DisasContext *ctx) \
9438 { \
9439 TCGv_i64 t0 = tcg_temp_new_i64(); \
9440 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
9441 gen_store_gpr64(rD(ctx->opcode), t0); \
9442 tcg_temp_free_i64(t0); \
9443 }
9444 #define GEN_SPEFPUOP_CONV_64_64(name) \
9445 static inline void gen_##name(DisasContext *ctx) \
9446 { \
9447 TCGv_i64 t0 = tcg_temp_new_i64(); \
9448 gen_load_gpr64(t0, rB(ctx->opcode)); \
9449 gen_helper_##name(t0, cpu_env, t0); \
9450 gen_store_gpr64(rD(ctx->opcode), t0); \
9451 tcg_temp_free_i64(t0); \
9452 }
9453 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9454 static inline void gen_##name(DisasContext *ctx) \
9455 { \
9456 if (unlikely(!ctx->spe_enabled)) { \
9457 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9458 return; \
9459 } \
9460 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9461 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9462 }
9463 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9464 static inline void gen_##name(DisasContext *ctx) \
9465 { \
9466 TCGv_i64 t0, t1; \
9467 if (unlikely(!ctx->spe_enabled)) { \
9468 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9469 return; \
9470 } \
9471 t0 = tcg_temp_new_i64(); \
9472 t1 = tcg_temp_new_i64(); \
9473 gen_load_gpr64(t0, rA(ctx->opcode)); \
9474 gen_load_gpr64(t1, rB(ctx->opcode)); \
9475 gen_helper_##name(t0, cpu_env, t0, t1); \
9476 gen_store_gpr64(rD(ctx->opcode), t0); \
9477 tcg_temp_free_i64(t0); \
9478 tcg_temp_free_i64(t1); \
9479 }
9480 #define GEN_SPEFPUOP_COMP_32(name) \
9481 static inline void gen_##name(DisasContext *ctx) \
9482 { \
9483 if (unlikely(!ctx->spe_enabled)) { \
9484 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9485 return; \
9486 } \
9487 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
9488 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9489 }
9490 #define GEN_SPEFPUOP_COMP_64(name) \
9491 static inline void gen_##name(DisasContext *ctx) \
9492 { \
9493 TCGv_i64 t0, t1; \
9494 if (unlikely(!ctx->spe_enabled)) { \
9495 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9496 return; \
9497 } \
9498 t0 = tcg_temp_new_i64(); \
9499 t1 = tcg_temp_new_i64(); \
9500 gen_load_gpr64(t0, rA(ctx->opcode)); \
9501 gen_load_gpr64(t1, rB(ctx->opcode)); \
9502 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9503 tcg_temp_free_i64(t0); \
9504 tcg_temp_free_i64(t1); \
9505 }
9506 #endif
9507
9508 /* Single precision floating-point vectors operations */
9509 /* Arithmetic */
9510 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9511 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9512 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9513 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9514 static inline void gen_evfsabs(DisasContext *ctx)
9515 {
9516 if (unlikely(!ctx->spe_enabled)) {
9517 gen_exception(ctx, POWERPC_EXCP_SPEU);
9518 return;
9519 }
9520 #if defined(TARGET_PPC64)
9521 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
9522 #else
9523 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
9524 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
9525 #endif
9526 }
9527 static inline void gen_evfsnabs(DisasContext *ctx)
9528 {
9529 if (unlikely(!ctx->spe_enabled)) {
9530 gen_exception(ctx, POWERPC_EXCP_SPEU);
9531 return;
9532 }
9533 #if defined(TARGET_PPC64)
9534 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
9535 #else
9536 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9537 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9538 #endif
9539 }
9540 static inline void gen_evfsneg(DisasContext *ctx)
9541 {
9542 if (unlikely(!ctx->spe_enabled)) {
9543 gen_exception(ctx, POWERPC_EXCP_SPEU);
9544 return;
9545 }
9546 #if defined(TARGET_PPC64)
9547 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
9548 #else
9549 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9550 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9551 #endif
9552 }
9553
9554 /* Conversion */
9555 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9556 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9557 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9558 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9559 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9560 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9561 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9562 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9563 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9564 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9565
9566 /* Comparison */
9567 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9568 GEN_SPEFPUOP_COMP_64(evfscmplt);
9569 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9570 GEN_SPEFPUOP_COMP_64(evfststgt);
9571 GEN_SPEFPUOP_COMP_64(evfststlt);
9572 GEN_SPEFPUOP_COMP_64(evfststeq);
9573
9574 /* Opcodes definitions */
9575 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9576 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9577 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9578 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9579 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9580 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9581 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9582 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9583 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9584 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9585 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9586 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9587 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9588 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9589
9590 /* Single precision floating-point operations */
9591 /* Arithmetic */
9592 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9593 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9594 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9595 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9596 static inline void gen_efsabs(DisasContext *ctx)
9597 {
9598 if (unlikely(!ctx->spe_enabled)) {
9599 gen_exception(ctx, POWERPC_EXCP_SPEU);
9600 return;
9601 }
9602 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9603 }
9604 static inline void gen_efsnabs(DisasContext *ctx)
9605 {
9606 if (unlikely(!ctx->spe_enabled)) {
9607 gen_exception(ctx, POWERPC_EXCP_SPEU);
9608 return;
9609 }
9610 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9611 }
9612 static inline void gen_efsneg(DisasContext *ctx)
9613 {
9614 if (unlikely(!ctx->spe_enabled)) {
9615 gen_exception(ctx, POWERPC_EXCP_SPEU);
9616 return;
9617 }
9618 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9619 }
9620
9621 /* Conversion */
9622 GEN_SPEFPUOP_CONV_32_32(efscfui);
9623 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9624 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9625 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9626 GEN_SPEFPUOP_CONV_32_32(efsctui);
9627 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9628 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9629 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9630 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9631 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9632 GEN_SPEFPUOP_CONV_32_64(efscfd);
9633
9634 /* Comparison */
9635 GEN_SPEFPUOP_COMP_32(efscmpgt);
9636 GEN_SPEFPUOP_COMP_32(efscmplt);
9637 GEN_SPEFPUOP_COMP_32(efscmpeq);
9638 GEN_SPEFPUOP_COMP_32(efststgt);
9639 GEN_SPEFPUOP_COMP_32(efststlt);
9640 GEN_SPEFPUOP_COMP_32(efststeq);
9641
9642 /* Opcodes definitions */
9643 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9644 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9645 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9646 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9647 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9648 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9649 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9650 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9651 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9652 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9653 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9654 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9655 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9656 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9657
9658 /* Double precision floating-point operations */
9659 /* Arithmetic */
9660 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9661 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9662 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9663 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9664 static inline void gen_efdabs(DisasContext *ctx)
9665 {
9666 if (unlikely(!ctx->spe_enabled)) {
9667 gen_exception(ctx, POWERPC_EXCP_SPEU);
9668 return;
9669 }
9670 #if defined(TARGET_PPC64)
9671 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
9672 #else
9673 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9674 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
9675 #endif
9676 }
9677 static inline void gen_efdnabs(DisasContext *ctx)
9678 {
9679 if (unlikely(!ctx->spe_enabled)) {
9680 gen_exception(ctx, POWERPC_EXCP_SPEU);
9681 return;
9682 }
9683 #if defined(TARGET_PPC64)
9684 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
9685 #else
9686 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9687 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9688 #endif
9689 }
9690 static inline void gen_efdneg(DisasContext *ctx)
9691 {
9692 if (unlikely(!ctx->spe_enabled)) {
9693 gen_exception(ctx, POWERPC_EXCP_SPEU);
9694 return;
9695 }
9696 #if defined(TARGET_PPC64)
9697 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
9698 #else
9699 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9700 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9701 #endif
9702 }
9703
9704 /* Conversion */
9705 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9706 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9707 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9708 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9709 GEN_SPEFPUOP_CONV_32_64(efdctui);
9710 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9711 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9712 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9713 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9714 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9715 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9716 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9717 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9718 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9719 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9720
9721 /* Comparison */
9722 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9723 GEN_SPEFPUOP_COMP_64(efdcmplt);
9724 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9725 GEN_SPEFPUOP_COMP_64(efdtstgt);
9726 GEN_SPEFPUOP_COMP_64(efdtstlt);
9727 GEN_SPEFPUOP_COMP_64(efdtsteq);
9728
9729 /* Opcodes definitions */
9730 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9731 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9732 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9733 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9734 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9735 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9736 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9737 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9738 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9739 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9740 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9741 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9742 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9743 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9744 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9745 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9746
9747 static opcode_t opcodes[] = {
9748 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9749 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9750 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9751 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9752 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9753 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9754 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9755 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9756 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9757 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9758 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9759 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9760 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9761 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9762 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9763 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9764 #if defined(TARGET_PPC64)
9765 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9766 #endif
9767 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9768 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9769 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9770 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9771 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9772 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9773 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9774 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9775 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9776 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9777 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9778 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9779 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
9780 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9781 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9782 #if defined(TARGET_PPC64)
9783 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9784 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9785 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9786 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9787 #endif
9788 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9789 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9790 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9791 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9792 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9793 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9794 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9795 #if defined(TARGET_PPC64)
9796 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9797 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9798 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9799 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9800 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9801 #endif
9802 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9803 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9804 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9805 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9806 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9807 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9808 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9809 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9810 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9811 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9812 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9813 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9814 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9815 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9816 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9817 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9818 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9819 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9820 #if defined(TARGET_PPC64)
9821 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9822 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9823 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9824 #endif
9825 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9826 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9827 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9828 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9829 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9830 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9831 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9832 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9833 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9834 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9835 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9836 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9837 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9838 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9839 #if defined(TARGET_PPC64)
9840 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9841 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9842 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9843 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9844 #endif
9845 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9846 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9847 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9848 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9849 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9850 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9851 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9852 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9853 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9854 #if defined(TARGET_PPC64)
9855 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9856 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9857 #endif
9858 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9859 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9860 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9861 #if defined(TARGET_PPC64)
9862 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9863 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9864 #endif
9865 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9866 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9867 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9868 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9869 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9870 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9871 #if defined(TARGET_PPC64)
9872 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9873 #endif
9874 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9875 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
9876 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9877 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9878 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9879 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9880 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9881 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9882 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9883 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9884 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9885 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9886 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9887 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9888 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9889 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9890 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9891 #if defined(TARGET_PPC64)
9892 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9893 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9894 PPC_SEGMENT_64B),
9895 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9896 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9897 PPC_SEGMENT_64B),
9898 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9899 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9900 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9901 #endif
9902 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9903 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9904 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9905 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9906 #if defined(TARGET_PPC64)
9907 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9908 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9909 #endif
9910 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9911 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9912 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9913 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9914 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9915 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9916 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9917 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9918 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9919 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9920 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9921 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9922 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9923 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9924 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9925 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9926 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9927 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9928 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9929 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9930 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9931 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9932 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9933 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9934 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9935 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9936 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9937 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9938 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9939 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9940 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9941 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9942 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9943 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9944 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9945 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9946 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9947 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9948 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9949 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
9950 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
9951 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
9952 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
9953 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
9954 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
9955 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
9956 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
9957 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
9958 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
9959 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9960 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9961 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
9962 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
9963 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9964 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9965 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
9966 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
9967 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
9968 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
9969 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
9970 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
9971 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
9972 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
9973 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
9974 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
9975 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
9976 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
9977 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
9978 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
9979 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
9980 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
9981 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
9982 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
9983 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
9984 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
9985 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
9986 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
9987 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
9988 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
9989 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
9990 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
9991 PPC_NONE, PPC2_BOOKE206),
9992 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
9993 PPC_NONE, PPC2_BOOKE206),
9994 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
9995 PPC_NONE, PPC2_BOOKE206),
9996 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
9997 PPC_NONE, PPC2_BOOKE206),
9998 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
9999 PPC_NONE, PPC2_BOOKE206),
10000 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10001 PPC_NONE, PPC2_PRCNTL),
10002 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10003 PPC_NONE, PPC2_PRCNTL),
10004 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
10005 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
10006 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
10007 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10008 PPC_BOOKE, PPC2_BOOKE206),
10009 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
10010 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10011 PPC_BOOKE, PPC2_BOOKE206),
10012 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10013 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10014 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10015 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
10016 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
10017 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10018 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10019 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10020 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10021 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10022
10023 #undef GEN_INT_ARITH_ADD
10024 #undef GEN_INT_ARITH_ADD_CONST
10025 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10026 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10027 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10028 add_ca, compute_ca, compute_ov) \
10029 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10030 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10031 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10032 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10033 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10034 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10035 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10036 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10037 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10038 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10039 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10040
10041 #undef GEN_INT_ARITH_DIVW
10042 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10043 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10044 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10045 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10046 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10047 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
10048 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10049 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10050 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10051 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10052
10053 #if defined(TARGET_PPC64)
10054 #undef GEN_INT_ARITH_DIVD
10055 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10056 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10057 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10058 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10059 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10060 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10061
10062 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10063 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10064 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10065 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10066
10067 #undef GEN_INT_ARITH_MUL_HELPER
10068 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10069 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10070 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10071 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10072 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10073 #endif
10074
10075 #undef GEN_INT_ARITH_SUBF
10076 #undef GEN_INT_ARITH_SUBF_CONST
10077 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10078 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10079 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10080 add_ca, compute_ca, compute_ov) \
10081 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10082 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10083 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10084 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10085 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10086 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10087 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10088 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10089 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10090 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10091 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10092
10093 #undef GEN_LOGICAL1
10094 #undef GEN_LOGICAL2
10095 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10096 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10097 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10098 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10099 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10100 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10101 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10102 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10103 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10104 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10105 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10106 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10107 #if defined(TARGET_PPC64)
10108 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10109 #endif
10110
10111 #if defined(TARGET_PPC64)
10112 #undef GEN_PPC64_R2
10113 #undef GEN_PPC64_R4
10114 #define GEN_PPC64_R2(name, opc1, opc2) \
10115 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10116 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10117 PPC_64B)
10118 #define GEN_PPC64_R4(name, opc1, opc2) \
10119 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10120 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10121 PPC_64B), \
10122 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10123 PPC_64B), \
10124 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10125 PPC_64B)
10126 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10127 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10128 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10129 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10130 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10131 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10132 #endif
10133
10134 #undef _GEN_FLOAT_ACB
10135 #undef GEN_FLOAT_ACB
10136 #undef _GEN_FLOAT_AB
10137 #undef GEN_FLOAT_AB
10138 #undef _GEN_FLOAT_AC
10139 #undef GEN_FLOAT_AC
10140 #undef GEN_FLOAT_B
10141 #undef GEN_FLOAT_BS
10142 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10143 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10144 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10145 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10146 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10147 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10148 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10149 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10150 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10151 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10152 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10153 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10154 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10155 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10156 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10157 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10158 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10159 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10160 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10161
10162 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10163 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10164 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10165 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10166 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10167 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10168 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10169 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10170 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10171 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10172 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10173 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10174 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10175 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10176 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10177 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10178 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10179 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10180 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10181 #if defined(TARGET_PPC64)
10182 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
10183 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10184 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10185 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10186 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
10187 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10188 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
10189 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10190 #endif
10191 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10192 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10193 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10194 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10195
10196 #undef GEN_LD
10197 #undef GEN_LDU
10198 #undef GEN_LDUX
10199 #undef GEN_LDX_E
10200 #undef GEN_LDS
10201 #define GEN_LD(name, ldop, opc, type) \
10202 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10203 #define GEN_LDU(name, ldop, opc, type) \
10204 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10205 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10206 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10207 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10208 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10209 #define GEN_LDS(name, ldop, op, type) \
10210 GEN_LD(name, ldop, op | 0x20, type) \
10211 GEN_LDU(name, ldop, op | 0x21, type) \
10212 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10213 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10214
10215 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10216 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10217 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10218 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10219 #if defined(TARGET_PPC64)
10220 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10221 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10222 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10223 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10224 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10225 #endif
10226 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10227 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10228
10229 #undef GEN_ST
10230 #undef GEN_STU
10231 #undef GEN_STUX
10232 #undef GEN_STX_E
10233 #undef GEN_STS
10234 #define GEN_ST(name, stop, opc, type) \
10235 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10236 #define GEN_STU(name, stop, opc, type) \
10237 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10238 #define GEN_STUX(name, stop, opc2, opc3, type) \
10239 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10240 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10241 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10242 #define GEN_STS(name, stop, op, type) \
10243 GEN_ST(name, stop, op | 0x20, type) \
10244 GEN_STU(name, stop, op | 0x21, type) \
10245 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10246 GEN_STX(name, stop, 0x17, op | 0x00, type)
10247
10248 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10249 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10250 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10251 #if defined(TARGET_PPC64)
10252 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10253 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10254 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10255 #endif
10256 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10257 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10258
10259 #undef GEN_LDF
10260 #undef GEN_LDUF
10261 #undef GEN_LDUXF
10262 #undef GEN_LDXF
10263 #undef GEN_LDFS
10264 #define GEN_LDF(name, ldop, opc, type) \
10265 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10266 #define GEN_LDUF(name, ldop, opc, type) \
10267 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10268 #define GEN_LDUXF(name, ldop, opc, type) \
10269 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10270 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10271 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10272 #define GEN_LDFS(name, ldop, op, type) \
10273 GEN_LDF(name, ldop, op | 0x20, type) \
10274 GEN_LDUF(name, ldop, op | 0x21, type) \
10275 GEN_LDUXF(name, ldop, op | 0x01, type) \
10276 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10277
10278 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10279 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10280 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10281 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10282 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10283 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10284
10285 #undef GEN_STF
10286 #undef GEN_STUF
10287 #undef GEN_STUXF
10288 #undef GEN_STXF
10289 #undef GEN_STFS
10290 #define GEN_STF(name, stop, opc, type) \
10291 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10292 #define GEN_STUF(name, stop, opc, type) \
10293 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10294 #define GEN_STUXF(name, stop, opc, type) \
10295 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10296 #define GEN_STXF(name, stop, opc2, opc3, type) \
10297 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10298 #define GEN_STFS(name, stop, op, type) \
10299 GEN_STF(name, stop, op | 0x20, type) \
10300 GEN_STUF(name, stop, op | 0x21, type) \
10301 GEN_STUXF(name, stop, op | 0x01, type) \
10302 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10303
10304 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10305 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10306 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10307 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10308 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10309
10310 #undef GEN_CRLOGIC
10311 #define GEN_CRLOGIC(name, tcg_op, opc) \
10312 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10313 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10314 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10315 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10316 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10317 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10318 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10319 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10320 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10321
10322 #undef GEN_MAC_HANDLER
10323 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10324 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10325 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10326 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10327 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10328 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10329 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10330 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10331 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10332 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10333 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10334 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10335 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10336 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10337 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10338 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10339 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10340 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10341 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10342 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10343 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10344 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10345 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10346 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10347 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10348 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10349 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10350 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10351 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10352 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10353 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10354 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10355 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10356 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10357 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10358 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10359 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10360 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10361 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10362 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10363 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10364 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10365 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10366 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10367
10368 #undef GEN_VR_LDX
10369 #undef GEN_VR_STX
10370 #undef GEN_VR_LVE
10371 #undef GEN_VR_STVE
10372 #define GEN_VR_LDX(name, opc2, opc3) \
10373 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10374 #define GEN_VR_STX(name, opc2, opc3) \
10375 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10376 #define GEN_VR_LVE(name, opc2, opc3) \
10377 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10378 #define GEN_VR_STVE(name, opc2, opc3) \
10379 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10380 GEN_VR_LDX(lvx, 0x07, 0x03),
10381 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10382 GEN_VR_LVE(bx, 0x07, 0x00),
10383 GEN_VR_LVE(hx, 0x07, 0x01),
10384 GEN_VR_LVE(wx, 0x07, 0x02),
10385 GEN_VR_STX(svx, 0x07, 0x07),
10386 GEN_VR_STX(svxl, 0x07, 0x0F),
10387 GEN_VR_STVE(bx, 0x07, 0x04),
10388 GEN_VR_STVE(hx, 0x07, 0x05),
10389 GEN_VR_STVE(wx, 0x07, 0x06),
10390
10391 #undef GEN_VX_LOGICAL
10392 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10393 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10394
10395 #undef GEN_VX_LOGICAL_207
10396 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10397 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10398
10399 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10400 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10401 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10402 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10403 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10404 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10405 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10406 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10407
10408 #undef GEN_VXFORM
10409 #define GEN_VXFORM(name, opc2, opc3) \
10410 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10411
10412 #undef GEN_VXFORM_207
10413 #define GEN_VXFORM_207(name, opc2, opc3) \
10414 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10415
10416 #undef GEN_VXFORM_DUAL
10417 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10418 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10419
10420 #undef GEN_VXRFORM_DUAL
10421 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10422 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10423 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10424
10425 GEN_VXFORM(vaddubm, 0, 0),
10426 GEN_VXFORM(vadduhm, 0, 1),
10427 GEN_VXFORM(vadduwm, 0, 2),
10428 GEN_VXFORM_207(vaddudm, 0, 3),
10429 GEN_VXFORM(vsububm, 0, 16),
10430 GEN_VXFORM(vsubuhm, 0, 17),
10431 GEN_VXFORM(vsubuwm, 0, 18),
10432 GEN_VXFORM_207(vsubudm, 0, 19),
10433 GEN_VXFORM(vmaxub, 1, 0),
10434 GEN_VXFORM(vmaxuh, 1, 1),
10435 GEN_VXFORM(vmaxuw, 1, 2),
10436 GEN_VXFORM_207(vmaxud, 1, 3),
10437 GEN_VXFORM(vmaxsb, 1, 4),
10438 GEN_VXFORM(vmaxsh, 1, 5),
10439 GEN_VXFORM(vmaxsw, 1, 6),
10440 GEN_VXFORM_207(vmaxsd, 1, 7),
10441 GEN_VXFORM(vminub, 1, 8),
10442 GEN_VXFORM(vminuh, 1, 9),
10443 GEN_VXFORM(vminuw, 1, 10),
10444 GEN_VXFORM_207(vminud, 1, 11),
10445 GEN_VXFORM(vminsb, 1, 12),
10446 GEN_VXFORM(vminsh, 1, 13),
10447 GEN_VXFORM(vminsw, 1, 14),
10448 GEN_VXFORM_207(vminsd, 1, 15),
10449 GEN_VXFORM(vavgub, 1, 16),
10450 GEN_VXFORM(vavguh, 1, 17),
10451 GEN_VXFORM(vavguw, 1, 18),
10452 GEN_VXFORM(vavgsb, 1, 20),
10453 GEN_VXFORM(vavgsh, 1, 21),
10454 GEN_VXFORM(vavgsw, 1, 22),
10455 GEN_VXFORM(vmrghb, 6, 0),
10456 GEN_VXFORM(vmrghh, 6, 1),
10457 GEN_VXFORM(vmrghw, 6, 2),
10458 GEN_VXFORM(vmrglb, 6, 4),
10459 GEN_VXFORM(vmrglh, 6, 5),
10460 GEN_VXFORM(vmrglw, 6, 6),
10461 GEN_VXFORM_207(vmrgew, 6, 30),
10462 GEN_VXFORM_207(vmrgow, 6, 26),
10463 GEN_VXFORM(vmuloub, 4, 0),
10464 GEN_VXFORM(vmulouh, 4, 1),
10465 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10466 GEN_VXFORM(vmulosb, 4, 4),
10467 GEN_VXFORM(vmulosh, 4, 5),
10468 GEN_VXFORM_207(vmulosw, 4, 6),
10469 GEN_VXFORM(vmuleub, 4, 8),
10470 GEN_VXFORM(vmuleuh, 4, 9),
10471 GEN_VXFORM_207(vmuleuw, 4, 10),
10472 GEN_VXFORM(vmulesb, 4, 12),
10473 GEN_VXFORM(vmulesh, 4, 13),
10474 GEN_VXFORM_207(vmulesw, 4, 14),
10475 GEN_VXFORM(vslb, 2, 4),
10476 GEN_VXFORM(vslh, 2, 5),
10477 GEN_VXFORM(vslw, 2, 6),
10478 GEN_VXFORM_207(vsld, 2, 23),
10479 GEN_VXFORM(vsrb, 2, 8),
10480 GEN_VXFORM(vsrh, 2, 9),
10481 GEN_VXFORM(vsrw, 2, 10),
10482 GEN_VXFORM_207(vsrd, 2, 27),
10483 GEN_VXFORM(vsrab, 2, 12),
10484 GEN_VXFORM(vsrah, 2, 13),
10485 GEN_VXFORM(vsraw, 2, 14),
10486 GEN_VXFORM_207(vsrad, 2, 15),
10487 GEN_VXFORM(vslo, 6, 16),
10488 GEN_VXFORM(vsro, 6, 17),
10489 GEN_VXFORM(vaddcuw, 0, 6),
10490 GEN_VXFORM(vsubcuw, 0, 22),
10491 GEN_VXFORM(vaddubs, 0, 8),
10492 GEN_VXFORM(vadduhs, 0, 9),
10493 GEN_VXFORM(vadduws, 0, 10),
10494 GEN_VXFORM(vaddsbs, 0, 12),
10495 GEN_VXFORM(vaddshs, 0, 13),
10496 GEN_VXFORM(vaddsws, 0, 14),
10497 GEN_VXFORM(vsububs, 0, 24),
10498 GEN_VXFORM(vsubuhs, 0, 25),
10499 GEN_VXFORM(vsubuws, 0, 26),
10500 GEN_VXFORM(vsubsbs, 0, 28),
10501 GEN_VXFORM(vsubshs, 0, 29),
10502 GEN_VXFORM(vsubsws, 0, 30),
10503 GEN_VXFORM_207(vadduqm, 0, 4),
10504 GEN_VXFORM_207(vaddcuq, 0, 5),
10505 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10506 GEN_VXFORM_207(vsubuqm, 0, 20),
10507 GEN_VXFORM_207(vsubcuq, 0, 21),
10508 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10509 GEN_VXFORM(vrlb, 2, 0),
10510 GEN_VXFORM(vrlh, 2, 1),
10511 GEN_VXFORM(vrlw, 2, 2),
10512 GEN_VXFORM_207(vrld, 2, 3),
10513 GEN_VXFORM(vsl, 2, 7),
10514 GEN_VXFORM(vsr, 2, 11),
10515 GEN_VXFORM(vpkuhum, 7, 0),
10516 GEN_VXFORM(vpkuwum, 7, 1),
10517 GEN_VXFORM_207(vpkudum, 7, 17),
10518 GEN_VXFORM(vpkuhus, 7, 2),
10519 GEN_VXFORM(vpkuwus, 7, 3),
10520 GEN_VXFORM_207(vpkudus, 7, 19),
10521 GEN_VXFORM(vpkshus, 7, 4),
10522 GEN_VXFORM(vpkswus, 7, 5),
10523 GEN_VXFORM_207(vpksdus, 7, 21),
10524 GEN_VXFORM(vpkshss, 7, 6),
10525 GEN_VXFORM(vpkswss, 7, 7),
10526 GEN_VXFORM_207(vpksdss, 7, 23),
10527 GEN_VXFORM(vpkpx, 7, 12),
10528 GEN_VXFORM(vsum4ubs, 4, 24),
10529 GEN_VXFORM(vsum4sbs, 4, 28),
10530 GEN_VXFORM(vsum4shs, 4, 25),
10531 GEN_VXFORM(vsum2sws, 4, 26),
10532 GEN_VXFORM(vsumsws, 4, 30),
10533 GEN_VXFORM(vaddfp, 5, 0),
10534 GEN_VXFORM(vsubfp, 5, 1),
10535 GEN_VXFORM(vmaxfp, 5, 16),
10536 GEN_VXFORM(vminfp, 5, 17),
10537
10538 #undef GEN_VXRFORM1
10539 #undef GEN_VXRFORM
10540 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10541 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10542 #define GEN_VXRFORM(name, opc2, opc3) \
10543 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10544 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10545 GEN_VXRFORM(vcmpequb, 3, 0)
10546 GEN_VXRFORM(vcmpequh, 3, 1)
10547 GEN_VXRFORM(vcmpequw, 3, 2)
10548 GEN_VXRFORM(vcmpgtsb, 3, 12)
10549 GEN_VXRFORM(vcmpgtsh, 3, 13)
10550 GEN_VXRFORM(vcmpgtsw, 3, 14)
10551 GEN_VXRFORM(vcmpgtub, 3, 8)
10552 GEN_VXRFORM(vcmpgtuh, 3, 9)
10553 GEN_VXRFORM(vcmpgtuw, 3, 10)
10554 GEN_VXRFORM(vcmpeqfp, 3, 3)
10555 GEN_VXRFORM(vcmpgefp, 3, 7)
10556 GEN_VXRFORM(vcmpgtfp, 3, 11)
10557 GEN_VXRFORM(vcmpbfp, 3, 15)
10558
10559 #undef GEN_VXFORM_SIMM
10560 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10561 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10562 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10563 GEN_VXFORM_SIMM(vspltish, 6, 13),
10564 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10565
10566 #undef GEN_VXFORM_NOA
10567 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10568 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10569 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10570 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10571 GEN_VXFORM_207(vupkhsw, 7, 25),
10572 GEN_VXFORM_NOA(vupklsb, 7, 10),
10573 GEN_VXFORM_NOA(vupklsh, 7, 11),
10574 GEN_VXFORM_207(vupklsw, 7, 27),
10575 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10576 GEN_VXFORM_NOA(vupklpx, 7, 15),
10577 GEN_VXFORM_NOA(vrefp, 5, 4),
10578 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10579 GEN_VXFORM_NOA(vexptefp, 5, 6),
10580 GEN_VXFORM_NOA(vlogefp, 5, 7),
10581 GEN_VXFORM_NOA(vrfim, 5, 8),
10582 GEN_VXFORM_NOA(vrfin, 5, 9),
10583 GEN_VXFORM_NOA(vrfip, 5, 10),
10584 GEN_VXFORM_NOA(vrfiz, 5, 11),
10585
10586 #undef GEN_VXFORM_UIMM
10587 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10588 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10589 GEN_VXFORM_UIMM(vspltb, 6, 8),
10590 GEN_VXFORM_UIMM(vsplth, 6, 9),
10591 GEN_VXFORM_UIMM(vspltw, 6, 10),
10592 GEN_VXFORM_UIMM(vcfux, 5, 12),
10593 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10594 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10595 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10596
10597 #undef GEN_VAFORM_PAIRED
10598 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10599 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10600 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10601 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10602 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10603 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10604 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10605 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10606
10607 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10608 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10609 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10610 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10611
10612
10613 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10614 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10615 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10616 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10617 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10618 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10619 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10620
10621 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10622 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10623 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10624 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10625 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10626
10627 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10628 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10629 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10630 #if defined(TARGET_PPC64)
10631 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10632 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10633 #endif
10634
10635 #undef GEN_XX2FORM
10636 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10637 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10638 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10639
10640 #undef GEN_XX3FORM
10641 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10642 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10643 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10644 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10645 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10646
10647 #undef GEN_XX3_RC_FORM
10648 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10649 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10650 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10651 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10652 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10653 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10654 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10655 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10656 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10657
10658 #undef GEN_XX3FORM_DM
10659 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10660 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10661 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10662 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10663 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10664 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10665 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10666 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10667 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10668 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10669 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10670 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10671 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10672 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10673 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10674 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10675 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10676
10677 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10678 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10679 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10680 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10681
10682 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10683 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10684 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10685 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10686 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10687 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10688 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10689 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10690
10691 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10692 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10693 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10694 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10695 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10696 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10697 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10698 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10699 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10700 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10701 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10702 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10703 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10704 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10705 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10706 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10707 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10708 GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10709 GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10710 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10711 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10712 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10713 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10714 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10715 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10716 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10717 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10718 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10719 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10720 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10721 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10722 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10723 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10724 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10725 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10726 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10727
10728 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10729 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10730 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10731 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10732 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10733 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10734 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10735 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10736 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10737 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10738 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10739 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10740 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10741 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10742 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10743 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10744 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10745 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10746
10747 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10748 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10749 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10750 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10751 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10752 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10753 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10754 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10755 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10756 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10757 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10758 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10759 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10760 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10761 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10762 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10763 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10764 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10765 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10766 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10767 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10768 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10769 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10770 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10771 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10772 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10773 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10774 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10775 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10776 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10777 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10778 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10779 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10780 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10781 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10782 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10783
10784 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10785 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10786 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10787 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10788 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10789 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10790 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10791 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10792 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10793 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10794 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10795 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10796 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10797 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10798 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10799 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10800 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10801 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10802 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10803 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10804 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10805 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10806 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10807 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10808 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10809 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10810 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10811 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10812 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10813 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10814 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10815 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10816 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10817 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10818 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10819 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10820
10821 #undef VSX_LOGICAL
10822 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10823 GEN_XX3FORM(name, opc2, opc3, fl2)
10824
10825 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10826 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10827 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10828 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10829 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10830 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10831 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10832 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10833 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10834 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10835 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10836 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10837
10838 #define GEN_XXSEL_ROW(opc3) \
10839 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10840 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10841 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10842 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10843 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10844 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10845 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10846 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10847
10848 GEN_XXSEL_ROW(0x00)
10849 GEN_XXSEL_ROW(0x01)
10850 GEN_XXSEL_ROW(0x02)
10851 GEN_XXSEL_ROW(0x03)
10852 GEN_XXSEL_ROW(0x04)
10853 GEN_XXSEL_ROW(0x05)
10854 GEN_XXSEL_ROW(0x06)
10855 GEN_XXSEL_ROW(0x07)
10856 GEN_XXSEL_ROW(0x08)
10857 GEN_XXSEL_ROW(0x09)
10858 GEN_XXSEL_ROW(0x0A)
10859 GEN_XXSEL_ROW(0x0B)
10860 GEN_XXSEL_ROW(0x0C)
10861 GEN_XXSEL_ROW(0x0D)
10862 GEN_XXSEL_ROW(0x0E)
10863 GEN_XXSEL_ROW(0x0F)
10864 GEN_XXSEL_ROW(0x10)
10865 GEN_XXSEL_ROW(0x11)
10866 GEN_XXSEL_ROW(0x12)
10867 GEN_XXSEL_ROW(0x13)
10868 GEN_XXSEL_ROW(0x14)
10869 GEN_XXSEL_ROW(0x15)
10870 GEN_XXSEL_ROW(0x16)
10871 GEN_XXSEL_ROW(0x17)
10872 GEN_XXSEL_ROW(0x18)
10873 GEN_XXSEL_ROW(0x19)
10874 GEN_XXSEL_ROW(0x1A)
10875 GEN_XXSEL_ROW(0x1B)
10876 GEN_XXSEL_ROW(0x1C)
10877 GEN_XXSEL_ROW(0x1D)
10878 GEN_XXSEL_ROW(0x1E)
10879 GEN_XXSEL_ROW(0x1F)
10880
10881 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10882
10883 #undef GEN_SPE
10884 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
10885 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
10886 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10887 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10888 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10889 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10890 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10891 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10892 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10893 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
10894 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
10895 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10896 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10897 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10898 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10899 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10900 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10901 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
10902 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10903 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10904 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10905 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10906 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10907 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10908 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10909 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10910 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10911 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10912 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10913 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10914 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
10915
10916 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10917 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10918 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10919 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10920 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10921 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10922 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10923 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10924 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10925 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10926 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10927 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10928 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10929 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10930
10931 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10932 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10933 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10934 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10935 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10936 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
10937 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10938 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10939 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10940 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10941 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10942 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10943 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10944 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10945
10946 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
10947 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10948 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
10949 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10950 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
10951 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10952 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
10953 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
10954 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10955 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10956 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10957 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10958 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10959 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10960 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
10961 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10962
10963 #undef GEN_SPEOP_LDST
10964 #define GEN_SPEOP_LDST(name, opc2, sh) \
10965 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
10966 GEN_SPEOP_LDST(evldd, 0x00, 3),
10967 GEN_SPEOP_LDST(evldw, 0x01, 3),
10968 GEN_SPEOP_LDST(evldh, 0x02, 3),
10969 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
10970 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
10971 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
10972 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
10973 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
10974 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
10975 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
10976 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
10977
10978 GEN_SPEOP_LDST(evstdd, 0x10, 3),
10979 GEN_SPEOP_LDST(evstdw, 0x11, 3),
10980 GEN_SPEOP_LDST(evstdh, 0x12, 3),
10981 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
10982 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
10983 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
10984 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
10985 };
10986
10987 #include "helper_regs.h"
10988 #include "translate_init.c"
10989
10990 /*****************************************************************************/
10991 /* Misc PowerPC helpers */
10992 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
10993 int flags)
10994 {
10995 #define RGPL 4
10996 #define RFPL 4
10997
10998 PowerPCCPU *cpu = POWERPC_CPU(cs);
10999 CPUPPCState *env = &cpu->env;
11000 int i;
11001
11002 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11003 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
11004 env->nip, env->lr, env->ctr, cpu_read_xer(env));
11005 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11006 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
11007 env->hflags, env->mmu_idx);
11008 #if !defined(NO_TIMER_DUMP)
11009 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11010 #if !defined(CONFIG_USER_ONLY)
11011 " DECR %08" PRIu32
11012 #endif
11013 "\n",
11014 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11015 #if !defined(CONFIG_USER_ONLY)
11016 , cpu_ppc_load_decr(env)
11017 #endif
11018 );
11019 #endif
11020 for (i = 0; i < 32; i++) {
11021 if ((i & (RGPL - 1)) == 0)
11022 cpu_fprintf(f, "GPR%02d", i);
11023 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11024 if ((i & (RGPL - 1)) == (RGPL - 1))
11025 cpu_fprintf(f, "\n");
11026 }
11027 cpu_fprintf(f, "CR ");
11028 for (i = 0; i < 8; i++)
11029 cpu_fprintf(f, "%01x", env->crf[i]);
11030 cpu_fprintf(f, " [");
11031 for (i = 0; i < 8; i++) {
11032 char a = '-';
11033 if (env->crf[i] & 0x08)
11034 a = 'L';
11035 else if (env->crf[i] & 0x04)
11036 a = 'G';
11037 else if (env->crf[i] & 0x02)
11038 a = 'E';
11039 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11040 }
11041 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11042 env->reserve_addr);
11043 for (i = 0; i < 32; i++) {
11044 if ((i & (RFPL - 1)) == 0)
11045 cpu_fprintf(f, "FPR%02d", i);
11046 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11047 if ((i & (RFPL - 1)) == (RFPL - 1))
11048 cpu_fprintf(f, "\n");
11049 }
11050 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11051 #if !defined(CONFIG_USER_ONLY)
11052 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11053 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11054 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11055 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11056
11057 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11058 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11059 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11060 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11061
11062 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11063 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11064 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11065 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11066
11067 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11068 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11069 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11070 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11071 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11072
11073 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11074 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11075 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11076 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11077
11078 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11079 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11080 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11081 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11082
11083 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11084 " EPR " TARGET_FMT_lx "\n",
11085 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11086 env->spr[SPR_BOOKE_EPR]);
11087
11088 /* FSL-specific */
11089 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11090 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11091 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11092 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11093
11094 /*
11095 * IVORs are left out as they are large and do not change often --
11096 * they can be read with "p $ivor0", "p $ivor1", etc.
11097 */
11098 }
11099
11100 #if defined(TARGET_PPC64)
11101 if (env->flags & POWERPC_FLAG_CFAR) {
11102 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11103 }
11104 #endif
11105
11106 switch (env->mmu_model) {
11107 case POWERPC_MMU_32B:
11108 case POWERPC_MMU_601:
11109 case POWERPC_MMU_SOFT_6xx:
11110 case POWERPC_MMU_SOFT_74xx:
11111 #if defined(TARGET_PPC64)
11112 case POWERPC_MMU_64B:
11113 case POWERPC_MMU_2_06:
11114 case POWERPC_MMU_2_06a:
11115 case POWERPC_MMU_2_06d:
11116 #endif
11117 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11118 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11119 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11120 break;
11121 case POWERPC_MMU_BOOKE206:
11122 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11123 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11124 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11125 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11126
11127 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11128 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11129 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11130 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11131
11132 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11133 " TLB1CFG " TARGET_FMT_lx "\n",
11134 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11135 env->spr[SPR_BOOKE_TLB1CFG]);
11136 break;
11137 default:
11138 break;
11139 }
11140 #endif
11141
11142 #undef RGPL
11143 #undef RFPL
11144 }
11145
11146 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11147 fprintf_function cpu_fprintf, int flags)
11148 {
11149 #if defined(DO_PPC_STATISTICS)
11150 PowerPCCPU *cpu = POWERPC_CPU(cs);
11151 opc_handler_t **t1, **t2, **t3, *handler;
11152 int op1, op2, op3;
11153
11154 t1 = cpu->env.opcodes;
11155 for (op1 = 0; op1 < 64; op1++) {
11156 handler = t1[op1];
11157 if (is_indirect_opcode(handler)) {
11158 t2 = ind_table(handler);
11159 for (op2 = 0; op2 < 32; op2++) {
11160 handler = t2[op2];
11161 if (is_indirect_opcode(handler)) {
11162 t3 = ind_table(handler);
11163 for (op3 = 0; op3 < 32; op3++) {
11164 handler = t3[op3];
11165 if (handler->count == 0)
11166 continue;
11167 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11168 "%016" PRIx64 " %" PRId64 "\n",
11169 op1, op2, op3, op1, (op3 << 5) | op2,
11170 handler->oname,
11171 handler->count, handler->count);
11172 }
11173 } else {
11174 if (handler->count == 0)
11175 continue;
11176 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11177 "%016" PRIx64 " %" PRId64 "\n",
11178 op1, op2, op1, op2, handler->oname,
11179 handler->count, handler->count);
11180 }
11181 }
11182 } else {
11183 if (handler->count == 0)
11184 continue;
11185 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11186 " %" PRId64 "\n",
11187 op1, op1, handler->oname,
11188 handler->count, handler->count);
11189 }
11190 }
11191 #endif
11192 }
11193
11194 /*****************************************************************************/
11195 static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
11196 TranslationBlock *tb,
11197 bool search_pc)
11198 {
11199 CPUState *cs = CPU(cpu);
11200 CPUPPCState *env = &cpu->env;
11201 DisasContext ctx, *ctxp = &ctx;
11202 opc_handler_t **table, *handler;
11203 target_ulong pc_start;
11204 uint16_t *gen_opc_end;
11205 CPUBreakpoint *bp;
11206 int j, lj = -1;
11207 int num_insns;
11208 int max_insns;
11209
11210 pc_start = tb->pc;
11211 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
11212 ctx.nip = pc_start;
11213 ctx.tb = tb;
11214 ctx.exception = POWERPC_EXCP_NONE;
11215 ctx.spr_cb = env->spr_cb;
11216 ctx.mem_idx = env->mmu_idx;
11217 ctx.insns_flags = env->insns_flags;
11218 ctx.insns_flags2 = env->insns_flags2;
11219 ctx.access_type = -1;
11220 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11221 #if defined(TARGET_PPC64)
11222 ctx.sf_mode = msr_is_64bit(env, env->msr);
11223 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11224 #endif
11225 ctx.fpu_enabled = msr_fp;
11226 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11227 ctx.spe_enabled = msr_spe;
11228 else
11229 ctx.spe_enabled = 0;
11230 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11231 ctx.altivec_enabled = msr_vr;
11232 else
11233 ctx.altivec_enabled = 0;
11234 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11235 ctx.vsx_enabled = msr_vsx;
11236 } else {
11237 ctx.vsx_enabled = 0;
11238 }
11239 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11240 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11241 else
11242 ctx.singlestep_enabled = 0;
11243 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11244 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11245 if (unlikely(cs->singlestep_enabled)) {
11246 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11247 }
11248 #if defined (DO_SINGLE_STEP) && 0
11249 /* Single step trace mode */
11250 msr_se = 1;
11251 #endif
11252 num_insns = 0;
11253 max_insns = tb->cflags & CF_COUNT_MASK;
11254 if (max_insns == 0)
11255 max_insns = CF_COUNT_MASK;
11256
11257 gen_tb_start();
11258 /* Set env in case of segfault during code fetch */
11259 while (ctx.exception == POWERPC_EXCP_NONE
11260 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
11261 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
11262 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
11263 if (bp->pc == ctx.nip) {
11264 gen_debug_exception(ctxp);
11265 break;
11266 }
11267 }
11268 }
11269 if (unlikely(search_pc)) {
11270 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11271 if (lj < j) {
11272 lj++;
11273 while (lj < j)
11274 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11275 }
11276 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
11277 tcg_ctx.gen_opc_instr_start[lj] = 1;
11278 tcg_ctx.gen_opc_icount[lj] = num_insns;
11279 }
11280 LOG_DISAS("----------------\n");
11281 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11282 ctx.nip, ctx.mem_idx, (int)msr_ir);
11283 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
11284 gen_io_start();
11285 if (unlikely(ctx.le_mode)) {
11286 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11287 } else {
11288 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11289 }
11290 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11291 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11292 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11293 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
11294 tcg_gen_debug_insn_start(ctx.nip);
11295 }
11296 ctx.nip += 4;
11297 table = env->opcodes;
11298 num_insns++;
11299 handler = table[opc1(ctx.opcode)];
11300 if (is_indirect_opcode(handler)) {
11301 table = ind_table(handler);
11302 handler = table[opc2(ctx.opcode)];
11303 if (is_indirect_opcode(handler)) {
11304 table = ind_table(handler);
11305 handler = table[opc3(ctx.opcode)];
11306 }
11307 }
11308 /* Is opcode *REALLY* valid ? */
11309 if (unlikely(handler->handler == &gen_invalid)) {
11310 if (qemu_log_enabled()) {
11311 qemu_log("invalid/unsupported opcode: "
11312 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11313 opc1(ctx.opcode), opc2(ctx.opcode),
11314 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11315 }
11316 } else {
11317 uint32_t inval;
11318
11319 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11320 inval = handler->inval2;
11321 } else {
11322 inval = handler->inval1;
11323 }
11324
11325 if (unlikely((ctx.opcode & inval) != 0)) {
11326 if (qemu_log_enabled()) {
11327 qemu_log("invalid bits: %08x for opcode: "
11328 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11329 ctx.opcode & inval, opc1(ctx.opcode),
11330 opc2(ctx.opcode), opc3(ctx.opcode),
11331 ctx.opcode, ctx.nip - 4);
11332 }
11333 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11334 break;
11335 }
11336 }
11337 (*(handler->handler))(&ctx);
11338 #if defined(DO_PPC_STATISTICS)
11339 handler->count++;
11340 #endif
11341 /* Check trace mode exceptions */
11342 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11343 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11344 ctx.exception != POWERPC_SYSCALL &&
11345 ctx.exception != POWERPC_EXCP_TRAP &&
11346 ctx.exception != POWERPC_EXCP_BRANCH)) {
11347 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11348 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11349 (cs->singlestep_enabled) ||
11350 singlestep ||
11351 num_insns >= max_insns)) {
11352 /* if we reach a page boundary or are single stepping, stop
11353 * generation
11354 */
11355 break;
11356 }
11357 }
11358 if (tb->cflags & CF_LAST_IO)
11359 gen_io_end();
11360 if (ctx.exception == POWERPC_EXCP_NONE) {
11361 gen_goto_tb(&ctx, 0, ctx.nip);
11362 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11363 if (unlikely(cs->singlestep_enabled)) {
11364 gen_debug_exception(ctxp);
11365 }
11366 /* Generate the return instruction */
11367 tcg_gen_exit_tb(0);
11368 }
11369 gen_tb_end(tb, num_insns);
11370 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
11371 if (unlikely(search_pc)) {
11372 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11373 lj++;
11374 while (lj <= j)
11375 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11376 } else {
11377 tb->size = ctx.nip - pc_start;
11378 tb->icount = num_insns;
11379 }
11380 #if defined(DEBUG_DISAS)
11381 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11382 int flags;
11383 flags = env->bfd_mach;
11384 flags |= ctx.le_mode << 16;
11385 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11386 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
11387 qemu_log("\n");
11388 }
11389 #endif
11390 }
11391
11392 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
11393 {
11394 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false);
11395 }
11396
11397 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
11398 {
11399 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true);
11400 }
11401
11402 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
11403 {
11404 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
11405 }
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