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target-ppc: Add ISA 2.06 ftdiv Instruction
[mirror_qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 10*5 + 22*6 /* VSR */
55 + 8*5 /* CRF */];
56 static TCGv cpu_gpr[32];
57 #if !defined(TARGET_PPC64)
58 static TCGv cpu_gprh[32];
59 #endif
60 static TCGv_i64 cpu_fpr[32];
61 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
62 static TCGv_i64 cpu_vsr[32];
63 static TCGv_i32 cpu_crf[8];
64 static TCGv cpu_nip;
65 static TCGv cpu_msr;
66 static TCGv cpu_ctr;
67 static TCGv cpu_lr;
68 #if defined(TARGET_PPC64)
69 static TCGv cpu_cfar;
70 #endif
71 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
72 static TCGv cpu_reserve;
73 static TCGv cpu_fpscr;
74 static TCGv_i32 cpu_access_type;
75
76 #include "exec/gen-icount.h"
77
78 void ppc_translate_init(void)
79 {
80 int i;
81 char* p;
82 size_t cpu_reg_names_size;
83 static int done_init = 0;
84
85 if (done_init)
86 return;
87
88 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
89
90 p = cpu_reg_names;
91 cpu_reg_names_size = sizeof(cpu_reg_names);
92
93 for (i = 0; i < 8; i++) {
94 snprintf(p, cpu_reg_names_size, "crf%d", i);
95 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
96 offsetof(CPUPPCState, crf[i]), p);
97 p += 5;
98 cpu_reg_names_size -= 5;
99 }
100
101 for (i = 0; i < 32; i++) {
102 snprintf(p, cpu_reg_names_size, "r%d", i);
103 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
104 offsetof(CPUPPCState, gpr[i]), p);
105 p += (i < 10) ? 3 : 4;
106 cpu_reg_names_size -= (i < 10) ? 3 : 4;
107 #if !defined(TARGET_PPC64)
108 snprintf(p, cpu_reg_names_size, "r%dH", i);
109 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
110 offsetof(CPUPPCState, gprh[i]), p);
111 p += (i < 10) ? 4 : 5;
112 cpu_reg_names_size -= (i < 10) ? 4 : 5;
113 #endif
114
115 snprintf(p, cpu_reg_names_size, "fp%d", i);
116 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
117 offsetof(CPUPPCState, fpr[i]), p);
118 p += (i < 10) ? 4 : 5;
119 cpu_reg_names_size -= (i < 10) ? 4 : 5;
120
121 snprintf(p, cpu_reg_names_size, "avr%dH", i);
122 #ifdef HOST_WORDS_BIGENDIAN
123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
124 offsetof(CPUPPCState, avr[i].u64[0]), p);
125 #else
126 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
127 offsetof(CPUPPCState, avr[i].u64[1]), p);
128 #endif
129 p += (i < 10) ? 6 : 7;
130 cpu_reg_names_size -= (i < 10) ? 6 : 7;
131
132 snprintf(p, cpu_reg_names_size, "avr%dL", i);
133 #ifdef HOST_WORDS_BIGENDIAN
134 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
135 offsetof(CPUPPCState, avr[i].u64[1]), p);
136 #else
137 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
138 offsetof(CPUPPCState, avr[i].u64[0]), p);
139 #endif
140 p += (i < 10) ? 6 : 7;
141 cpu_reg_names_size -= (i < 10) ? 6 : 7;
142 snprintf(p, cpu_reg_names_size, "vsr%d", i);
143 cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
144 offsetof(CPUPPCState, vsr[i]), p);
145 p += (i < 10) ? 5 : 6;
146 cpu_reg_names_size -= (i < 10) ? 5 : 6;
147 }
148
149 cpu_nip = tcg_global_mem_new(TCG_AREG0,
150 offsetof(CPUPPCState, nip), "nip");
151
152 cpu_msr = tcg_global_mem_new(TCG_AREG0,
153 offsetof(CPUPPCState, msr), "msr");
154
155 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, ctr), "ctr");
157
158 cpu_lr = tcg_global_mem_new(TCG_AREG0,
159 offsetof(CPUPPCState, lr), "lr");
160
161 #if defined(TARGET_PPC64)
162 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
163 offsetof(CPUPPCState, cfar), "cfar");
164 #endif
165
166 cpu_xer = tcg_global_mem_new(TCG_AREG0,
167 offsetof(CPUPPCState, xer), "xer");
168 cpu_so = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, so), "SO");
170 cpu_ov = tcg_global_mem_new(TCG_AREG0,
171 offsetof(CPUPPCState, ov), "OV");
172 cpu_ca = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, ca), "CA");
174
175 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
176 offsetof(CPUPPCState, reserve_addr),
177 "reserve_addr");
178
179 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
180 offsetof(CPUPPCState, fpscr), "fpscr");
181
182 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
183 offsetof(CPUPPCState, access_type), "access_type");
184
185 done_init = 1;
186 }
187
188 /* internal defines */
189 typedef struct DisasContext {
190 struct TranslationBlock *tb;
191 target_ulong nip;
192 uint32_t opcode;
193 uint32_t exception;
194 /* Routine used to access memory */
195 int mem_idx;
196 int access_type;
197 /* Translation flags */
198 int le_mode;
199 #if defined(TARGET_PPC64)
200 int sf_mode;
201 int has_cfar;
202 #endif
203 int fpu_enabled;
204 int altivec_enabled;
205 int vsx_enabled;
206 int spe_enabled;
207 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
208 int singlestep_enabled;
209 uint64_t insns_flags;
210 uint64_t insns_flags2;
211 } DisasContext;
212
213 /* True when active word size < size of target_long. */
214 #ifdef TARGET_PPC64
215 # define NARROW_MODE(C) (!(C)->sf_mode)
216 #else
217 # define NARROW_MODE(C) 0
218 #endif
219
220 struct opc_handler_t {
221 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
222 uint32_t inval1;
223 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
224 uint32_t inval2;
225 /* instruction type */
226 uint64_t type;
227 /* extended instruction type */
228 uint64_t type2;
229 /* handler */
230 void (*handler)(DisasContext *ctx);
231 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
232 const char *oname;
233 #endif
234 #if defined(DO_PPC_STATISTICS)
235 uint64_t count;
236 #endif
237 };
238
239 static inline void gen_reset_fpstatus(void)
240 {
241 gen_helper_reset_fpstatus(cpu_env);
242 }
243
244 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
245 {
246 TCGv_i32 t0 = tcg_temp_new_i32();
247
248 if (set_fprf != 0) {
249 /* This case might be optimized later */
250 tcg_gen_movi_i32(t0, 1);
251 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
252 if (unlikely(set_rc)) {
253 tcg_gen_mov_i32(cpu_crf[1], t0);
254 }
255 gen_helper_float_check_status(cpu_env);
256 } else if (unlikely(set_rc)) {
257 /* We always need to compute fpcc */
258 tcg_gen_movi_i32(t0, 0);
259 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
260 tcg_gen_mov_i32(cpu_crf[1], t0);
261 }
262
263 tcg_temp_free_i32(t0);
264 }
265
266 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
267 {
268 if (ctx->access_type != access_type) {
269 tcg_gen_movi_i32(cpu_access_type, access_type);
270 ctx->access_type = access_type;
271 }
272 }
273
274 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
275 {
276 if (NARROW_MODE(ctx)) {
277 nip = (uint32_t)nip;
278 }
279 tcg_gen_movi_tl(cpu_nip, nip);
280 }
281
282 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
283 {
284 TCGv_i32 t0, t1;
285 if (ctx->exception == POWERPC_EXCP_NONE) {
286 gen_update_nip(ctx, ctx->nip);
287 }
288 t0 = tcg_const_i32(excp);
289 t1 = tcg_const_i32(error);
290 gen_helper_raise_exception_err(cpu_env, t0, t1);
291 tcg_temp_free_i32(t0);
292 tcg_temp_free_i32(t1);
293 ctx->exception = (excp);
294 }
295
296 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
297 {
298 TCGv_i32 t0;
299 if (ctx->exception == POWERPC_EXCP_NONE) {
300 gen_update_nip(ctx, ctx->nip);
301 }
302 t0 = tcg_const_i32(excp);
303 gen_helper_raise_exception(cpu_env, t0);
304 tcg_temp_free_i32(t0);
305 ctx->exception = (excp);
306 }
307
308 static inline void gen_debug_exception(DisasContext *ctx)
309 {
310 TCGv_i32 t0;
311
312 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
313 (ctx->exception != POWERPC_EXCP_SYNC)) {
314 gen_update_nip(ctx, ctx->nip);
315 }
316 t0 = tcg_const_i32(EXCP_DEBUG);
317 gen_helper_raise_exception(cpu_env, t0);
318 tcg_temp_free_i32(t0);
319 }
320
321 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
322 {
323 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
324 }
325
326 /* Stop translation */
327 static inline void gen_stop_exception(DisasContext *ctx)
328 {
329 gen_update_nip(ctx, ctx->nip);
330 ctx->exception = POWERPC_EXCP_STOP;
331 }
332
333 /* No need to update nip here, as execution flow will change */
334 static inline void gen_sync_exception(DisasContext *ctx)
335 {
336 ctx->exception = POWERPC_EXCP_SYNC;
337 }
338
339 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
340 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
341
342 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
343 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
344
345 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
346 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
347
348 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
349 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
350
351 typedef struct opcode_t {
352 unsigned char opc1, opc2, opc3;
353 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
354 unsigned char pad[5];
355 #else
356 unsigned char pad[1];
357 #endif
358 opc_handler_t handler;
359 const char *oname;
360 } opcode_t;
361
362 /*****************************************************************************/
363 /*** Instruction decoding ***/
364 #define EXTRACT_HELPER(name, shift, nb) \
365 static inline uint32_t name(uint32_t opcode) \
366 { \
367 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
368 }
369
370 #define EXTRACT_SHELPER(name, shift, nb) \
371 static inline int32_t name(uint32_t opcode) \
372 { \
373 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
374 }
375
376 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
377 static inline uint32_t name(uint32_t opcode) \
378 { \
379 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
380 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
381 }
382 /* Opcode part 1 */
383 EXTRACT_HELPER(opc1, 26, 6);
384 /* Opcode part 2 */
385 EXTRACT_HELPER(opc2, 1, 5);
386 /* Opcode part 3 */
387 EXTRACT_HELPER(opc3, 6, 5);
388 /* Update Cr0 flags */
389 EXTRACT_HELPER(Rc, 0, 1);
390 /* Destination */
391 EXTRACT_HELPER(rD, 21, 5);
392 /* Source */
393 EXTRACT_HELPER(rS, 21, 5);
394 /* First operand */
395 EXTRACT_HELPER(rA, 16, 5);
396 /* Second operand */
397 EXTRACT_HELPER(rB, 11, 5);
398 /* Third operand */
399 EXTRACT_HELPER(rC, 6, 5);
400 /*** Get CRn ***/
401 EXTRACT_HELPER(crfD, 23, 3);
402 EXTRACT_HELPER(crfS, 18, 3);
403 EXTRACT_HELPER(crbD, 21, 5);
404 EXTRACT_HELPER(crbA, 16, 5);
405 EXTRACT_HELPER(crbB, 11, 5);
406 /* SPR / TBL */
407 EXTRACT_HELPER(_SPR, 11, 10);
408 static inline uint32_t SPR(uint32_t opcode)
409 {
410 uint32_t sprn = _SPR(opcode);
411
412 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
413 }
414 /*** Get constants ***/
415 EXTRACT_HELPER(IMM, 12, 8);
416 /* 16 bits signed immediate value */
417 EXTRACT_SHELPER(SIMM, 0, 16);
418 /* 16 bits unsigned immediate value */
419 EXTRACT_HELPER(UIMM, 0, 16);
420 /* 5 bits signed immediate value */
421 EXTRACT_HELPER(SIMM5, 16, 5);
422 /* 5 bits signed immediate value */
423 EXTRACT_HELPER(UIMM5, 16, 5);
424 /* Bit count */
425 EXTRACT_HELPER(NB, 11, 5);
426 /* Shift count */
427 EXTRACT_HELPER(SH, 11, 5);
428 /* Vector shift count */
429 EXTRACT_HELPER(VSH, 6, 4);
430 /* Mask start */
431 EXTRACT_HELPER(MB, 6, 5);
432 /* Mask end */
433 EXTRACT_HELPER(ME, 1, 5);
434 /* Trap operand */
435 EXTRACT_HELPER(TO, 21, 5);
436
437 EXTRACT_HELPER(CRM, 12, 8);
438 EXTRACT_HELPER(SR, 16, 4);
439
440 /* mtfsf/mtfsfi */
441 EXTRACT_HELPER(FPBF, 23, 3);
442 EXTRACT_HELPER(FPIMM, 12, 4);
443 EXTRACT_HELPER(FPL, 25, 1);
444 EXTRACT_HELPER(FPFLM, 17, 8);
445 EXTRACT_HELPER(FPW, 16, 1);
446
447 /*** Jump target decoding ***/
448 /* Displacement */
449 EXTRACT_SHELPER(d, 0, 16);
450 /* Immediate address */
451 static inline target_ulong LI(uint32_t opcode)
452 {
453 return (opcode >> 0) & 0x03FFFFFC;
454 }
455
456 static inline uint32_t BD(uint32_t opcode)
457 {
458 return (opcode >> 0) & 0xFFFC;
459 }
460
461 EXTRACT_HELPER(BO, 21, 5);
462 EXTRACT_HELPER(BI, 16, 5);
463 /* Absolute/relative address */
464 EXTRACT_HELPER(AA, 1, 1);
465 /* Link */
466 EXTRACT_HELPER(LK, 0, 1);
467
468 /* Create a mask between <start> and <end> bits */
469 static inline target_ulong MASK(uint32_t start, uint32_t end)
470 {
471 target_ulong ret;
472
473 #if defined(TARGET_PPC64)
474 if (likely(start == 0)) {
475 ret = UINT64_MAX << (63 - end);
476 } else if (likely(end == 63)) {
477 ret = UINT64_MAX >> start;
478 }
479 #else
480 if (likely(start == 0)) {
481 ret = UINT32_MAX << (31 - end);
482 } else if (likely(end == 31)) {
483 ret = UINT32_MAX >> start;
484 }
485 #endif
486 else {
487 ret = (((target_ulong)(-1ULL)) >> (start)) ^
488 (((target_ulong)(-1ULL) >> (end)) >> 1);
489 if (unlikely(start > end))
490 return ~ret;
491 }
492
493 return ret;
494 }
495
496 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
497 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
498 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
499 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
500 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
501 EXTRACT_HELPER(DM, 8, 2);
502 EXTRACT_HELPER(UIM, 16, 2);
503 EXTRACT_HELPER(SHW, 8, 2);
504 /*****************************************************************************/
505 /* PowerPC instructions table */
506
507 #if defined(DO_PPC_STATISTICS)
508 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
509 { \
510 .opc1 = op1, \
511 .opc2 = op2, \
512 .opc3 = op3, \
513 .pad = { 0, }, \
514 .handler = { \
515 .inval1 = invl, \
516 .type = _typ, \
517 .type2 = _typ2, \
518 .handler = &gen_##name, \
519 .oname = stringify(name), \
520 }, \
521 .oname = stringify(name), \
522 }
523 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
524 { \
525 .opc1 = op1, \
526 .opc2 = op2, \
527 .opc3 = op3, \
528 .pad = { 0, }, \
529 .handler = { \
530 .inval1 = invl1, \
531 .inval2 = invl2, \
532 .type = _typ, \
533 .type2 = _typ2, \
534 .handler = &gen_##name, \
535 .oname = stringify(name), \
536 }, \
537 .oname = stringify(name), \
538 }
539 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
540 { \
541 .opc1 = op1, \
542 .opc2 = op2, \
543 .opc3 = op3, \
544 .pad = { 0, }, \
545 .handler = { \
546 .inval1 = invl, \
547 .type = _typ, \
548 .type2 = _typ2, \
549 .handler = &gen_##name, \
550 .oname = onam, \
551 }, \
552 .oname = onam, \
553 }
554 #else
555 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
556 { \
557 .opc1 = op1, \
558 .opc2 = op2, \
559 .opc3 = op3, \
560 .pad = { 0, }, \
561 .handler = { \
562 .inval1 = invl, \
563 .type = _typ, \
564 .type2 = _typ2, \
565 .handler = &gen_##name, \
566 }, \
567 .oname = stringify(name), \
568 }
569 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
570 { \
571 .opc1 = op1, \
572 .opc2 = op2, \
573 .opc3 = op3, \
574 .pad = { 0, }, \
575 .handler = { \
576 .inval1 = invl1, \
577 .inval2 = invl2, \
578 .type = _typ, \
579 .type2 = _typ2, \
580 .handler = &gen_##name, \
581 }, \
582 .oname = stringify(name), \
583 }
584 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
585 { \
586 .opc1 = op1, \
587 .opc2 = op2, \
588 .opc3 = op3, \
589 .pad = { 0, }, \
590 .handler = { \
591 .inval1 = invl, \
592 .type = _typ, \
593 .type2 = _typ2, \
594 .handler = &gen_##name, \
595 }, \
596 .oname = onam, \
597 }
598 #endif
599
600 /* SPR load/store helpers */
601 static inline void gen_load_spr(TCGv t, int reg)
602 {
603 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
604 }
605
606 static inline void gen_store_spr(int reg, TCGv t)
607 {
608 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
609 }
610
611 /* Invalid instruction */
612 static void gen_invalid(DisasContext *ctx)
613 {
614 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
615 }
616
617 static opc_handler_t invalid_handler = {
618 .inval1 = 0xFFFFFFFF,
619 .inval2 = 0xFFFFFFFF,
620 .type = PPC_NONE,
621 .type2 = PPC_NONE,
622 .handler = gen_invalid,
623 };
624
625 /*** Integer comparison ***/
626
627 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
628 {
629 TCGv t0 = tcg_temp_new();
630 TCGv_i32 t1 = tcg_temp_new_i32();
631
632 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
633
634 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
635 tcg_gen_trunc_tl_i32(t1, t0);
636 tcg_gen_shli_i32(t1, t1, CRF_LT);
637 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
638
639 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
640 tcg_gen_trunc_tl_i32(t1, t0);
641 tcg_gen_shli_i32(t1, t1, CRF_GT);
642 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
643
644 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
645 tcg_gen_trunc_tl_i32(t1, t0);
646 tcg_gen_shli_i32(t1, t1, CRF_EQ);
647 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
648
649 tcg_temp_free(t0);
650 tcg_temp_free_i32(t1);
651 }
652
653 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
654 {
655 TCGv t0 = tcg_const_tl(arg1);
656 gen_op_cmp(arg0, t0, s, crf);
657 tcg_temp_free(t0);
658 }
659
660 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
661 {
662 TCGv t0, t1;
663 t0 = tcg_temp_new();
664 t1 = tcg_temp_new();
665 if (s) {
666 tcg_gen_ext32s_tl(t0, arg0);
667 tcg_gen_ext32s_tl(t1, arg1);
668 } else {
669 tcg_gen_ext32u_tl(t0, arg0);
670 tcg_gen_ext32u_tl(t1, arg1);
671 }
672 gen_op_cmp(t0, t1, s, crf);
673 tcg_temp_free(t1);
674 tcg_temp_free(t0);
675 }
676
677 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
678 {
679 TCGv t0 = tcg_const_tl(arg1);
680 gen_op_cmp32(arg0, t0, s, crf);
681 tcg_temp_free(t0);
682 }
683
684 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
685 {
686 if (NARROW_MODE(ctx)) {
687 gen_op_cmpi32(reg, 0, 1, 0);
688 } else {
689 gen_op_cmpi(reg, 0, 1, 0);
690 }
691 }
692
693 /* cmp */
694 static void gen_cmp(DisasContext *ctx)
695 {
696 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
697 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
698 1, crfD(ctx->opcode));
699 } else {
700 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
701 1, crfD(ctx->opcode));
702 }
703 }
704
705 /* cmpi */
706 static void gen_cmpi(DisasContext *ctx)
707 {
708 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
709 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
710 1, crfD(ctx->opcode));
711 } else {
712 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
713 1, crfD(ctx->opcode));
714 }
715 }
716
717 /* cmpl */
718 static void gen_cmpl(DisasContext *ctx)
719 {
720 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
721 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
722 0, crfD(ctx->opcode));
723 } else {
724 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
725 0, crfD(ctx->opcode));
726 }
727 }
728
729 /* cmpli */
730 static void gen_cmpli(DisasContext *ctx)
731 {
732 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
733 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
734 0, crfD(ctx->opcode));
735 } else {
736 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
737 0, crfD(ctx->opcode));
738 }
739 }
740
741 /* isel (PowerPC 2.03 specification) */
742 static void gen_isel(DisasContext *ctx)
743 {
744 int l1, l2;
745 uint32_t bi = rC(ctx->opcode);
746 uint32_t mask;
747 TCGv_i32 t0;
748
749 l1 = gen_new_label();
750 l2 = gen_new_label();
751
752 mask = 1 << (3 - (bi & 0x03));
753 t0 = tcg_temp_new_i32();
754 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
755 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
756 if (rA(ctx->opcode) == 0)
757 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
758 else
759 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
760 tcg_gen_br(l2);
761 gen_set_label(l1);
762 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
763 gen_set_label(l2);
764 tcg_temp_free_i32(t0);
765 }
766
767 /* cmpb: PowerPC 2.05 specification */
768 static void gen_cmpb(DisasContext *ctx)
769 {
770 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
771 cpu_gpr[rB(ctx->opcode)]);
772 }
773
774 /*** Integer arithmetic ***/
775
776 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
777 TCGv arg1, TCGv arg2, int sub)
778 {
779 TCGv t0 = tcg_temp_new();
780
781 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
782 tcg_gen_xor_tl(t0, arg1, arg2);
783 if (sub) {
784 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
785 } else {
786 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
787 }
788 tcg_temp_free(t0);
789 if (NARROW_MODE(ctx)) {
790 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
791 }
792 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
793 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
794 }
795
796 /* Common add function */
797 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
798 TCGv arg2, bool add_ca, bool compute_ca,
799 bool compute_ov, bool compute_rc0)
800 {
801 TCGv t0 = ret;
802
803 if (compute_ca || compute_ov) {
804 t0 = tcg_temp_new();
805 }
806
807 if (compute_ca) {
808 if (NARROW_MODE(ctx)) {
809 /* Caution: a non-obvious corner case of the spec is that we
810 must produce the *entire* 64-bit addition, but produce the
811 carry into bit 32. */
812 TCGv t1 = tcg_temp_new();
813 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
814 tcg_gen_add_tl(t0, arg1, arg2);
815 if (add_ca) {
816 tcg_gen_add_tl(t0, t0, cpu_ca);
817 }
818 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
819 tcg_temp_free(t1);
820 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
821 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
822 } else {
823 TCGv zero = tcg_const_tl(0);
824 if (add_ca) {
825 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
826 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
827 } else {
828 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
829 }
830 tcg_temp_free(zero);
831 }
832 } else {
833 tcg_gen_add_tl(t0, arg1, arg2);
834 if (add_ca) {
835 tcg_gen_add_tl(t0, t0, cpu_ca);
836 }
837 }
838
839 if (compute_ov) {
840 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
841 }
842 if (unlikely(compute_rc0)) {
843 gen_set_Rc0(ctx, t0);
844 }
845
846 if (!TCGV_EQUAL(t0, ret)) {
847 tcg_gen_mov_tl(ret, t0);
848 tcg_temp_free(t0);
849 }
850 }
851 /* Add functions with two operands */
852 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
853 static void glue(gen_, name)(DisasContext *ctx) \
854 { \
855 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
856 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
857 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
858 }
859 /* Add functions with one operand and one immediate */
860 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
861 add_ca, compute_ca, compute_ov) \
862 static void glue(gen_, name)(DisasContext *ctx) \
863 { \
864 TCGv t0 = tcg_const_tl(const_val); \
865 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
866 cpu_gpr[rA(ctx->opcode)], t0, \
867 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
868 tcg_temp_free(t0); \
869 }
870
871 /* add add. addo addo. */
872 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
873 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
874 /* addc addc. addco addco. */
875 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
876 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
877 /* adde adde. addeo addeo. */
878 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
879 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
880 /* addme addme. addmeo addmeo. */
881 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
882 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
883 /* addze addze. addzeo addzeo.*/
884 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
885 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
886 /* addi */
887 static void gen_addi(DisasContext *ctx)
888 {
889 target_long simm = SIMM(ctx->opcode);
890
891 if (rA(ctx->opcode) == 0) {
892 /* li case */
893 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
894 } else {
895 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
896 cpu_gpr[rA(ctx->opcode)], simm);
897 }
898 }
899 /* addic addic.*/
900 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
901 {
902 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
903 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
904 c, 0, 1, 0, compute_rc0);
905 tcg_temp_free(c);
906 }
907
908 static void gen_addic(DisasContext *ctx)
909 {
910 gen_op_addic(ctx, 0);
911 }
912
913 static void gen_addic_(DisasContext *ctx)
914 {
915 gen_op_addic(ctx, 1);
916 }
917
918 /* addis */
919 static void gen_addis(DisasContext *ctx)
920 {
921 target_long simm = SIMM(ctx->opcode);
922
923 if (rA(ctx->opcode) == 0) {
924 /* lis case */
925 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
926 } else {
927 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
928 cpu_gpr[rA(ctx->opcode)], simm << 16);
929 }
930 }
931
932 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
933 TCGv arg2, int sign, int compute_ov)
934 {
935 int l1 = gen_new_label();
936 int l2 = gen_new_label();
937 TCGv_i32 t0 = tcg_temp_local_new_i32();
938 TCGv_i32 t1 = tcg_temp_local_new_i32();
939
940 tcg_gen_trunc_tl_i32(t0, arg1);
941 tcg_gen_trunc_tl_i32(t1, arg2);
942 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
943 if (sign) {
944 int l3 = gen_new_label();
945 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
946 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
947 gen_set_label(l3);
948 tcg_gen_div_i32(t0, t0, t1);
949 } else {
950 tcg_gen_divu_i32(t0, t0, t1);
951 }
952 if (compute_ov) {
953 tcg_gen_movi_tl(cpu_ov, 0);
954 }
955 tcg_gen_br(l2);
956 gen_set_label(l1);
957 if (sign) {
958 tcg_gen_sari_i32(t0, t0, 31);
959 } else {
960 tcg_gen_movi_i32(t0, 0);
961 }
962 if (compute_ov) {
963 tcg_gen_movi_tl(cpu_ov, 1);
964 tcg_gen_movi_tl(cpu_so, 1);
965 }
966 gen_set_label(l2);
967 tcg_gen_extu_i32_tl(ret, t0);
968 tcg_temp_free_i32(t0);
969 tcg_temp_free_i32(t1);
970 if (unlikely(Rc(ctx->opcode) != 0))
971 gen_set_Rc0(ctx, ret);
972 }
973 /* Div functions */
974 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
975 static void glue(gen_, name)(DisasContext *ctx) \
976 { \
977 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
978 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
979 sign, compute_ov); \
980 }
981 /* divwu divwu. divwuo divwuo. */
982 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
983 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
984 /* divw divw. divwo divwo. */
985 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
986 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
987
988 /* div[wd]eu[o][.] */
989 #define GEN_DIVE(name, hlpr, compute_ov) \
990 static void gen_##name(DisasContext *ctx) \
991 { \
992 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
993 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
994 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
995 tcg_temp_free_i32(t0); \
996 if (unlikely(Rc(ctx->opcode) != 0)) { \
997 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
998 } \
999 }
1000
1001 GEN_DIVE(divweu, divweu, 0);
1002 GEN_DIVE(divweuo, divweu, 1);
1003 GEN_DIVE(divwe, divwe, 0);
1004 GEN_DIVE(divweo, divwe, 1);
1005
1006 #if defined(TARGET_PPC64)
1007 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1008 TCGv arg2, int sign, int compute_ov)
1009 {
1010 int l1 = gen_new_label();
1011 int l2 = gen_new_label();
1012
1013 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1014 if (sign) {
1015 int l3 = gen_new_label();
1016 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1017 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1018 gen_set_label(l3);
1019 tcg_gen_div_i64(ret, arg1, arg2);
1020 } else {
1021 tcg_gen_divu_i64(ret, arg1, arg2);
1022 }
1023 if (compute_ov) {
1024 tcg_gen_movi_tl(cpu_ov, 0);
1025 }
1026 tcg_gen_br(l2);
1027 gen_set_label(l1);
1028 if (sign) {
1029 tcg_gen_sari_i64(ret, arg1, 63);
1030 } else {
1031 tcg_gen_movi_i64(ret, 0);
1032 }
1033 if (compute_ov) {
1034 tcg_gen_movi_tl(cpu_ov, 1);
1035 tcg_gen_movi_tl(cpu_so, 1);
1036 }
1037 gen_set_label(l2);
1038 if (unlikely(Rc(ctx->opcode) != 0))
1039 gen_set_Rc0(ctx, ret);
1040 }
1041 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1042 static void glue(gen_, name)(DisasContext *ctx) \
1043 { \
1044 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1045 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1046 sign, compute_ov); \
1047 }
1048 /* divwu divwu. divwuo divwuo. */
1049 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1050 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1051 /* divw divw. divwo divwo. */
1052 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1053 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1054
1055 GEN_DIVE(divdeu, divdeu, 0);
1056 GEN_DIVE(divdeuo, divdeu, 1);
1057 GEN_DIVE(divde, divde, 0);
1058 GEN_DIVE(divdeo, divde, 1);
1059 #endif
1060
1061 /* mulhw mulhw. */
1062 static void gen_mulhw(DisasContext *ctx)
1063 {
1064 TCGv_i32 t0 = tcg_temp_new_i32();
1065 TCGv_i32 t1 = tcg_temp_new_i32();
1066
1067 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1068 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1069 tcg_gen_muls2_i32(t0, t1, t0, t1);
1070 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1071 tcg_temp_free_i32(t0);
1072 tcg_temp_free_i32(t1);
1073 if (unlikely(Rc(ctx->opcode) != 0))
1074 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1075 }
1076
1077 /* mulhwu mulhwu. */
1078 static void gen_mulhwu(DisasContext *ctx)
1079 {
1080 TCGv_i32 t0 = tcg_temp_new_i32();
1081 TCGv_i32 t1 = tcg_temp_new_i32();
1082
1083 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1084 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1085 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1086 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1087 tcg_temp_free_i32(t0);
1088 tcg_temp_free_i32(t1);
1089 if (unlikely(Rc(ctx->opcode) != 0))
1090 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1091 }
1092
1093 /* mullw mullw. */
1094 static void gen_mullw(DisasContext *ctx)
1095 {
1096 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1097 cpu_gpr[rB(ctx->opcode)]);
1098 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1099 if (unlikely(Rc(ctx->opcode) != 0))
1100 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1101 }
1102
1103 /* mullwo mullwo. */
1104 static void gen_mullwo(DisasContext *ctx)
1105 {
1106 TCGv_i32 t0 = tcg_temp_new_i32();
1107 TCGv_i32 t1 = tcg_temp_new_i32();
1108
1109 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1110 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1111 tcg_gen_muls2_i32(t0, t1, t0, t1);
1112 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1113
1114 tcg_gen_sari_i32(t0, t0, 31);
1115 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1116 tcg_gen_extu_i32_tl(cpu_ov, t0);
1117 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1118
1119 tcg_temp_free_i32(t0);
1120 tcg_temp_free_i32(t1);
1121 if (unlikely(Rc(ctx->opcode) != 0))
1122 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1123 }
1124
1125 /* mulli */
1126 static void gen_mulli(DisasContext *ctx)
1127 {
1128 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1129 SIMM(ctx->opcode));
1130 }
1131
1132 #if defined(TARGET_PPC64)
1133 /* mulhd mulhd. */
1134 static void gen_mulhd(DisasContext *ctx)
1135 {
1136 TCGv lo = tcg_temp_new();
1137 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1138 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1139 tcg_temp_free(lo);
1140 if (unlikely(Rc(ctx->opcode) != 0)) {
1141 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1142 }
1143 }
1144
1145 /* mulhdu mulhdu. */
1146 static void gen_mulhdu(DisasContext *ctx)
1147 {
1148 TCGv lo = tcg_temp_new();
1149 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1150 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1151 tcg_temp_free(lo);
1152 if (unlikely(Rc(ctx->opcode) != 0)) {
1153 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1154 }
1155 }
1156
1157 /* mulld mulld. */
1158 static void gen_mulld(DisasContext *ctx)
1159 {
1160 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1161 cpu_gpr[rB(ctx->opcode)]);
1162 if (unlikely(Rc(ctx->opcode) != 0))
1163 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1164 }
1165
1166 /* mulldo mulldo. */
1167 static void gen_mulldo(DisasContext *ctx)
1168 {
1169 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1170 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1171 if (unlikely(Rc(ctx->opcode) != 0)) {
1172 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1173 }
1174 }
1175 #endif
1176
1177 /* Common subf function */
1178 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1179 TCGv arg2, bool add_ca, bool compute_ca,
1180 bool compute_ov, bool compute_rc0)
1181 {
1182 TCGv t0 = ret;
1183
1184 if (compute_ca || compute_ov) {
1185 t0 = tcg_temp_new();
1186 }
1187
1188 if (compute_ca) {
1189 /* dest = ~arg1 + arg2 [+ ca]. */
1190 if (NARROW_MODE(ctx)) {
1191 /* Caution: a non-obvious corner case of the spec is that we
1192 must produce the *entire* 64-bit addition, but produce the
1193 carry into bit 32. */
1194 TCGv inv1 = tcg_temp_new();
1195 TCGv t1 = tcg_temp_new();
1196 tcg_gen_not_tl(inv1, arg1);
1197 if (add_ca) {
1198 tcg_gen_add_tl(t0, arg2, cpu_ca);
1199 } else {
1200 tcg_gen_addi_tl(t0, arg2, 1);
1201 }
1202 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1203 tcg_gen_add_tl(t0, t0, inv1);
1204 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1205 tcg_temp_free(t1);
1206 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1207 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1208 } else if (add_ca) {
1209 TCGv zero, inv1 = tcg_temp_new();
1210 tcg_gen_not_tl(inv1, arg1);
1211 zero = tcg_const_tl(0);
1212 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1213 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1214 tcg_temp_free(zero);
1215 tcg_temp_free(inv1);
1216 } else {
1217 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1218 tcg_gen_sub_tl(t0, arg2, arg1);
1219 }
1220 } else if (add_ca) {
1221 /* Since we're ignoring carry-out, we can simplify the
1222 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1223 tcg_gen_sub_tl(t0, arg2, arg1);
1224 tcg_gen_add_tl(t0, t0, cpu_ca);
1225 tcg_gen_subi_tl(t0, t0, 1);
1226 } else {
1227 tcg_gen_sub_tl(t0, arg2, arg1);
1228 }
1229
1230 if (compute_ov) {
1231 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1232 }
1233 if (unlikely(compute_rc0)) {
1234 gen_set_Rc0(ctx, t0);
1235 }
1236
1237 if (!TCGV_EQUAL(t0, ret)) {
1238 tcg_gen_mov_tl(ret, t0);
1239 tcg_temp_free(t0);
1240 }
1241 }
1242 /* Sub functions with Two operands functions */
1243 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1244 static void glue(gen_, name)(DisasContext *ctx) \
1245 { \
1246 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1247 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1248 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1249 }
1250 /* Sub functions with one operand and one immediate */
1251 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1252 add_ca, compute_ca, compute_ov) \
1253 static void glue(gen_, name)(DisasContext *ctx) \
1254 { \
1255 TCGv t0 = tcg_const_tl(const_val); \
1256 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1257 cpu_gpr[rA(ctx->opcode)], t0, \
1258 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1259 tcg_temp_free(t0); \
1260 }
1261 /* subf subf. subfo subfo. */
1262 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1263 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1264 /* subfc subfc. subfco subfco. */
1265 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1266 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1267 /* subfe subfe. subfeo subfo. */
1268 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1269 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1270 /* subfme subfme. subfmeo subfmeo. */
1271 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1272 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1273 /* subfze subfze. subfzeo subfzeo.*/
1274 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1275 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1276
1277 /* subfic */
1278 static void gen_subfic(DisasContext *ctx)
1279 {
1280 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1281 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1282 c, 0, 1, 0, 0);
1283 tcg_temp_free(c);
1284 }
1285
1286 /* neg neg. nego nego. */
1287 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1288 {
1289 TCGv zero = tcg_const_tl(0);
1290 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1291 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1292 tcg_temp_free(zero);
1293 }
1294
1295 static void gen_neg(DisasContext *ctx)
1296 {
1297 gen_op_arith_neg(ctx, 0);
1298 }
1299
1300 static void gen_nego(DisasContext *ctx)
1301 {
1302 gen_op_arith_neg(ctx, 1);
1303 }
1304
1305 /*** Integer logical ***/
1306 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1307 static void glue(gen_, name)(DisasContext *ctx) \
1308 { \
1309 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1310 cpu_gpr[rB(ctx->opcode)]); \
1311 if (unlikely(Rc(ctx->opcode) != 0)) \
1312 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1313 }
1314
1315 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1316 static void glue(gen_, name)(DisasContext *ctx) \
1317 { \
1318 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1319 if (unlikely(Rc(ctx->opcode) != 0)) \
1320 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1321 }
1322
1323 /* and & and. */
1324 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1325 /* andc & andc. */
1326 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1327
1328 /* andi. */
1329 static void gen_andi_(DisasContext *ctx)
1330 {
1331 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1332 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1333 }
1334
1335 /* andis. */
1336 static void gen_andis_(DisasContext *ctx)
1337 {
1338 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1339 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1340 }
1341
1342 /* cntlzw */
1343 static void gen_cntlzw(DisasContext *ctx)
1344 {
1345 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1346 if (unlikely(Rc(ctx->opcode) != 0))
1347 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1348 }
1349 /* eqv & eqv. */
1350 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1351 /* extsb & extsb. */
1352 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1353 /* extsh & extsh. */
1354 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1355 /* nand & nand. */
1356 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1357 /* nor & nor. */
1358 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1359
1360 /* or & or. */
1361 static void gen_or(DisasContext *ctx)
1362 {
1363 int rs, ra, rb;
1364
1365 rs = rS(ctx->opcode);
1366 ra = rA(ctx->opcode);
1367 rb = rB(ctx->opcode);
1368 /* Optimisation for mr. ri case */
1369 if (rs != ra || rs != rb) {
1370 if (rs != rb)
1371 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1372 else
1373 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1374 if (unlikely(Rc(ctx->opcode) != 0))
1375 gen_set_Rc0(ctx, cpu_gpr[ra]);
1376 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1377 gen_set_Rc0(ctx, cpu_gpr[rs]);
1378 #if defined(TARGET_PPC64)
1379 } else {
1380 int prio = 0;
1381
1382 switch (rs) {
1383 case 1:
1384 /* Set process priority to low */
1385 prio = 2;
1386 break;
1387 case 6:
1388 /* Set process priority to medium-low */
1389 prio = 3;
1390 break;
1391 case 2:
1392 /* Set process priority to normal */
1393 prio = 4;
1394 break;
1395 #if !defined(CONFIG_USER_ONLY)
1396 case 31:
1397 if (ctx->mem_idx > 0) {
1398 /* Set process priority to very low */
1399 prio = 1;
1400 }
1401 break;
1402 case 5:
1403 if (ctx->mem_idx > 0) {
1404 /* Set process priority to medium-hight */
1405 prio = 5;
1406 }
1407 break;
1408 case 3:
1409 if (ctx->mem_idx > 0) {
1410 /* Set process priority to high */
1411 prio = 6;
1412 }
1413 break;
1414 case 7:
1415 if (ctx->mem_idx > 1) {
1416 /* Set process priority to very high */
1417 prio = 7;
1418 }
1419 break;
1420 #endif
1421 default:
1422 /* nop */
1423 break;
1424 }
1425 if (prio) {
1426 TCGv t0 = tcg_temp_new();
1427 gen_load_spr(t0, SPR_PPR);
1428 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1429 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1430 gen_store_spr(SPR_PPR, t0);
1431 tcg_temp_free(t0);
1432 }
1433 #endif
1434 }
1435 }
1436 /* orc & orc. */
1437 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1438
1439 /* xor & xor. */
1440 static void gen_xor(DisasContext *ctx)
1441 {
1442 /* Optimisation for "set to zero" case */
1443 if (rS(ctx->opcode) != rB(ctx->opcode))
1444 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1445 else
1446 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1447 if (unlikely(Rc(ctx->opcode) != 0))
1448 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1449 }
1450
1451 /* ori */
1452 static void gen_ori(DisasContext *ctx)
1453 {
1454 target_ulong uimm = UIMM(ctx->opcode);
1455
1456 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1457 /* NOP */
1458 /* XXX: should handle special NOPs for POWER series */
1459 return;
1460 }
1461 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1462 }
1463
1464 /* oris */
1465 static void gen_oris(DisasContext *ctx)
1466 {
1467 target_ulong uimm = UIMM(ctx->opcode);
1468
1469 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1470 /* NOP */
1471 return;
1472 }
1473 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1474 }
1475
1476 /* xori */
1477 static void gen_xori(DisasContext *ctx)
1478 {
1479 target_ulong uimm = UIMM(ctx->opcode);
1480
1481 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1482 /* NOP */
1483 return;
1484 }
1485 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1486 }
1487
1488 /* xoris */
1489 static void gen_xoris(DisasContext *ctx)
1490 {
1491 target_ulong uimm = UIMM(ctx->opcode);
1492
1493 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1494 /* NOP */
1495 return;
1496 }
1497 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1498 }
1499
1500 /* popcntb : PowerPC 2.03 specification */
1501 static void gen_popcntb(DisasContext *ctx)
1502 {
1503 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1504 }
1505
1506 static void gen_popcntw(DisasContext *ctx)
1507 {
1508 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1509 }
1510
1511 #if defined(TARGET_PPC64)
1512 /* popcntd: PowerPC 2.06 specification */
1513 static void gen_popcntd(DisasContext *ctx)
1514 {
1515 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1516 }
1517 #endif
1518
1519 /* prtyw: PowerPC 2.05 specification */
1520 static void gen_prtyw(DisasContext *ctx)
1521 {
1522 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1523 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1524 TCGv t0 = tcg_temp_new();
1525 tcg_gen_shri_tl(t0, rs, 16);
1526 tcg_gen_xor_tl(ra, rs, t0);
1527 tcg_gen_shri_tl(t0, ra, 8);
1528 tcg_gen_xor_tl(ra, ra, t0);
1529 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1530 tcg_temp_free(t0);
1531 }
1532
1533 #if defined(TARGET_PPC64)
1534 /* prtyd: PowerPC 2.05 specification */
1535 static void gen_prtyd(DisasContext *ctx)
1536 {
1537 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1538 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1539 TCGv t0 = tcg_temp_new();
1540 tcg_gen_shri_tl(t0, rs, 32);
1541 tcg_gen_xor_tl(ra, rs, t0);
1542 tcg_gen_shri_tl(t0, ra, 16);
1543 tcg_gen_xor_tl(ra, ra, t0);
1544 tcg_gen_shri_tl(t0, ra, 8);
1545 tcg_gen_xor_tl(ra, ra, t0);
1546 tcg_gen_andi_tl(ra, ra, 1);
1547 tcg_temp_free(t0);
1548 }
1549 #endif
1550
1551 #if defined(TARGET_PPC64)
1552 /* bpermd */
1553 static void gen_bpermd(DisasContext *ctx)
1554 {
1555 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1556 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1557 }
1558 #endif
1559
1560 #if defined(TARGET_PPC64)
1561 /* extsw & extsw. */
1562 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1563
1564 /* cntlzd */
1565 static void gen_cntlzd(DisasContext *ctx)
1566 {
1567 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1568 if (unlikely(Rc(ctx->opcode) != 0))
1569 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1570 }
1571 #endif
1572
1573 /*** Integer rotate ***/
1574
1575 /* rlwimi & rlwimi. */
1576 static void gen_rlwimi(DisasContext *ctx)
1577 {
1578 uint32_t mb, me, sh;
1579
1580 mb = MB(ctx->opcode);
1581 me = ME(ctx->opcode);
1582 sh = SH(ctx->opcode);
1583 if (likely(sh == 0 && mb == 0 && me == 31)) {
1584 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1585 } else {
1586 target_ulong mask;
1587 TCGv t1;
1588 TCGv t0 = tcg_temp_new();
1589 #if defined(TARGET_PPC64)
1590 TCGv_i32 t2 = tcg_temp_new_i32();
1591 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1592 tcg_gen_rotli_i32(t2, t2, sh);
1593 tcg_gen_extu_i32_i64(t0, t2);
1594 tcg_temp_free_i32(t2);
1595 #else
1596 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1597 #endif
1598 #if defined(TARGET_PPC64)
1599 mb += 32;
1600 me += 32;
1601 #endif
1602 mask = MASK(mb, me);
1603 t1 = tcg_temp_new();
1604 tcg_gen_andi_tl(t0, t0, mask);
1605 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1606 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1607 tcg_temp_free(t0);
1608 tcg_temp_free(t1);
1609 }
1610 if (unlikely(Rc(ctx->opcode) != 0))
1611 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1612 }
1613
1614 /* rlwinm & rlwinm. */
1615 static void gen_rlwinm(DisasContext *ctx)
1616 {
1617 uint32_t mb, me, sh;
1618
1619 sh = SH(ctx->opcode);
1620 mb = MB(ctx->opcode);
1621 me = ME(ctx->opcode);
1622
1623 if (likely(mb == 0 && me == (31 - sh))) {
1624 if (likely(sh == 0)) {
1625 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1626 } else {
1627 TCGv t0 = tcg_temp_new();
1628 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1629 tcg_gen_shli_tl(t0, t0, sh);
1630 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1631 tcg_temp_free(t0);
1632 }
1633 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1634 TCGv t0 = tcg_temp_new();
1635 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1636 tcg_gen_shri_tl(t0, t0, mb);
1637 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1638 tcg_temp_free(t0);
1639 } else {
1640 TCGv t0 = tcg_temp_new();
1641 #if defined(TARGET_PPC64)
1642 TCGv_i32 t1 = tcg_temp_new_i32();
1643 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1644 tcg_gen_rotli_i32(t1, t1, sh);
1645 tcg_gen_extu_i32_i64(t0, t1);
1646 tcg_temp_free_i32(t1);
1647 #else
1648 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1649 #endif
1650 #if defined(TARGET_PPC64)
1651 mb += 32;
1652 me += 32;
1653 #endif
1654 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1655 tcg_temp_free(t0);
1656 }
1657 if (unlikely(Rc(ctx->opcode) != 0))
1658 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1659 }
1660
1661 /* rlwnm & rlwnm. */
1662 static void gen_rlwnm(DisasContext *ctx)
1663 {
1664 uint32_t mb, me;
1665 TCGv t0;
1666 #if defined(TARGET_PPC64)
1667 TCGv_i32 t1, t2;
1668 #endif
1669
1670 mb = MB(ctx->opcode);
1671 me = ME(ctx->opcode);
1672 t0 = tcg_temp_new();
1673 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1674 #if defined(TARGET_PPC64)
1675 t1 = tcg_temp_new_i32();
1676 t2 = tcg_temp_new_i32();
1677 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1678 tcg_gen_trunc_i64_i32(t2, t0);
1679 tcg_gen_rotl_i32(t1, t1, t2);
1680 tcg_gen_extu_i32_i64(t0, t1);
1681 tcg_temp_free_i32(t1);
1682 tcg_temp_free_i32(t2);
1683 #else
1684 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1685 #endif
1686 if (unlikely(mb != 0 || me != 31)) {
1687 #if defined(TARGET_PPC64)
1688 mb += 32;
1689 me += 32;
1690 #endif
1691 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1692 } else {
1693 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1694 }
1695 tcg_temp_free(t0);
1696 if (unlikely(Rc(ctx->opcode) != 0))
1697 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1698 }
1699
1700 #if defined(TARGET_PPC64)
1701 #define GEN_PPC64_R2(name, opc1, opc2) \
1702 static void glue(gen_, name##0)(DisasContext *ctx) \
1703 { \
1704 gen_##name(ctx, 0); \
1705 } \
1706 \
1707 static void glue(gen_, name##1)(DisasContext *ctx) \
1708 { \
1709 gen_##name(ctx, 1); \
1710 }
1711 #define GEN_PPC64_R4(name, opc1, opc2) \
1712 static void glue(gen_, name##0)(DisasContext *ctx) \
1713 { \
1714 gen_##name(ctx, 0, 0); \
1715 } \
1716 \
1717 static void glue(gen_, name##1)(DisasContext *ctx) \
1718 { \
1719 gen_##name(ctx, 0, 1); \
1720 } \
1721 \
1722 static void glue(gen_, name##2)(DisasContext *ctx) \
1723 { \
1724 gen_##name(ctx, 1, 0); \
1725 } \
1726 \
1727 static void glue(gen_, name##3)(DisasContext *ctx) \
1728 { \
1729 gen_##name(ctx, 1, 1); \
1730 }
1731
1732 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1733 uint32_t sh)
1734 {
1735 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1736 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1737 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1738 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1739 } else {
1740 TCGv t0 = tcg_temp_new();
1741 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1742 if (likely(mb == 0 && me == 63)) {
1743 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1744 } else {
1745 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1746 }
1747 tcg_temp_free(t0);
1748 }
1749 if (unlikely(Rc(ctx->opcode) != 0))
1750 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1751 }
1752 /* rldicl - rldicl. */
1753 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1754 {
1755 uint32_t sh, mb;
1756
1757 sh = SH(ctx->opcode) | (shn << 5);
1758 mb = MB(ctx->opcode) | (mbn << 5);
1759 gen_rldinm(ctx, mb, 63, sh);
1760 }
1761 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1762 /* rldicr - rldicr. */
1763 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1764 {
1765 uint32_t sh, me;
1766
1767 sh = SH(ctx->opcode) | (shn << 5);
1768 me = MB(ctx->opcode) | (men << 5);
1769 gen_rldinm(ctx, 0, me, sh);
1770 }
1771 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1772 /* rldic - rldic. */
1773 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1774 {
1775 uint32_t sh, mb;
1776
1777 sh = SH(ctx->opcode) | (shn << 5);
1778 mb = MB(ctx->opcode) | (mbn << 5);
1779 gen_rldinm(ctx, mb, 63 - sh, sh);
1780 }
1781 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1782
1783 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1784 {
1785 TCGv t0;
1786
1787 t0 = tcg_temp_new();
1788 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1789 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1790 if (unlikely(mb != 0 || me != 63)) {
1791 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1792 } else {
1793 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1794 }
1795 tcg_temp_free(t0);
1796 if (unlikely(Rc(ctx->opcode) != 0))
1797 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1798 }
1799
1800 /* rldcl - rldcl. */
1801 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1802 {
1803 uint32_t mb;
1804
1805 mb = MB(ctx->opcode) | (mbn << 5);
1806 gen_rldnm(ctx, mb, 63);
1807 }
1808 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1809 /* rldcr - rldcr. */
1810 static inline void gen_rldcr(DisasContext *ctx, int men)
1811 {
1812 uint32_t me;
1813
1814 me = MB(ctx->opcode) | (men << 5);
1815 gen_rldnm(ctx, 0, me);
1816 }
1817 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1818 /* rldimi - rldimi. */
1819 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1820 {
1821 uint32_t sh, mb, me;
1822
1823 sh = SH(ctx->opcode) | (shn << 5);
1824 mb = MB(ctx->opcode) | (mbn << 5);
1825 me = 63 - sh;
1826 if (unlikely(sh == 0 && mb == 0)) {
1827 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1828 } else {
1829 TCGv t0, t1;
1830 target_ulong mask;
1831
1832 t0 = tcg_temp_new();
1833 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1834 t1 = tcg_temp_new();
1835 mask = MASK(mb, me);
1836 tcg_gen_andi_tl(t0, t0, mask);
1837 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1838 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1839 tcg_temp_free(t0);
1840 tcg_temp_free(t1);
1841 }
1842 if (unlikely(Rc(ctx->opcode) != 0))
1843 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1844 }
1845 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1846 #endif
1847
1848 /*** Integer shift ***/
1849
1850 /* slw & slw. */
1851 static void gen_slw(DisasContext *ctx)
1852 {
1853 TCGv t0, t1;
1854
1855 t0 = tcg_temp_new();
1856 /* AND rS with a mask that is 0 when rB >= 0x20 */
1857 #if defined(TARGET_PPC64)
1858 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1859 tcg_gen_sari_tl(t0, t0, 0x3f);
1860 #else
1861 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1862 tcg_gen_sari_tl(t0, t0, 0x1f);
1863 #endif
1864 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1865 t1 = tcg_temp_new();
1866 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1867 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1868 tcg_temp_free(t1);
1869 tcg_temp_free(t0);
1870 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1871 if (unlikely(Rc(ctx->opcode) != 0))
1872 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1873 }
1874
1875 /* sraw & sraw. */
1876 static void gen_sraw(DisasContext *ctx)
1877 {
1878 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1879 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1880 if (unlikely(Rc(ctx->opcode) != 0))
1881 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1882 }
1883
1884 /* srawi & srawi. */
1885 static void gen_srawi(DisasContext *ctx)
1886 {
1887 int sh = SH(ctx->opcode);
1888 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1889 TCGv src = cpu_gpr[rS(ctx->opcode)];
1890 if (sh == 0) {
1891 tcg_gen_mov_tl(dst, src);
1892 tcg_gen_movi_tl(cpu_ca, 0);
1893 } else {
1894 TCGv t0;
1895 tcg_gen_ext32s_tl(dst, src);
1896 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1897 t0 = tcg_temp_new();
1898 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1899 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1900 tcg_temp_free(t0);
1901 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1902 tcg_gen_sari_tl(dst, dst, sh);
1903 }
1904 if (unlikely(Rc(ctx->opcode) != 0)) {
1905 gen_set_Rc0(ctx, dst);
1906 }
1907 }
1908
1909 /* srw & srw. */
1910 static void gen_srw(DisasContext *ctx)
1911 {
1912 TCGv t0, t1;
1913
1914 t0 = tcg_temp_new();
1915 /* AND rS with a mask that is 0 when rB >= 0x20 */
1916 #if defined(TARGET_PPC64)
1917 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1918 tcg_gen_sari_tl(t0, t0, 0x3f);
1919 #else
1920 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1921 tcg_gen_sari_tl(t0, t0, 0x1f);
1922 #endif
1923 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1924 tcg_gen_ext32u_tl(t0, t0);
1925 t1 = tcg_temp_new();
1926 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1927 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1928 tcg_temp_free(t1);
1929 tcg_temp_free(t0);
1930 if (unlikely(Rc(ctx->opcode) != 0))
1931 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1932 }
1933
1934 #if defined(TARGET_PPC64)
1935 /* sld & sld. */
1936 static void gen_sld(DisasContext *ctx)
1937 {
1938 TCGv t0, t1;
1939
1940 t0 = tcg_temp_new();
1941 /* AND rS with a mask that is 0 when rB >= 0x40 */
1942 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1943 tcg_gen_sari_tl(t0, t0, 0x3f);
1944 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1945 t1 = tcg_temp_new();
1946 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1947 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1948 tcg_temp_free(t1);
1949 tcg_temp_free(t0);
1950 if (unlikely(Rc(ctx->opcode) != 0))
1951 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1952 }
1953
1954 /* srad & srad. */
1955 static void gen_srad(DisasContext *ctx)
1956 {
1957 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1958 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1959 if (unlikely(Rc(ctx->opcode) != 0))
1960 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1961 }
1962 /* sradi & sradi. */
1963 static inline void gen_sradi(DisasContext *ctx, int n)
1964 {
1965 int sh = SH(ctx->opcode) + (n << 5);
1966 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1967 TCGv src = cpu_gpr[rS(ctx->opcode)];
1968 if (sh == 0) {
1969 tcg_gen_mov_tl(dst, src);
1970 tcg_gen_movi_tl(cpu_ca, 0);
1971 } else {
1972 TCGv t0;
1973 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1974 t0 = tcg_temp_new();
1975 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1976 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1977 tcg_temp_free(t0);
1978 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1979 tcg_gen_sari_tl(dst, src, sh);
1980 }
1981 if (unlikely(Rc(ctx->opcode) != 0)) {
1982 gen_set_Rc0(ctx, dst);
1983 }
1984 }
1985
1986 static void gen_sradi0(DisasContext *ctx)
1987 {
1988 gen_sradi(ctx, 0);
1989 }
1990
1991 static void gen_sradi1(DisasContext *ctx)
1992 {
1993 gen_sradi(ctx, 1);
1994 }
1995
1996 /* srd & srd. */
1997 static void gen_srd(DisasContext *ctx)
1998 {
1999 TCGv t0, t1;
2000
2001 t0 = tcg_temp_new();
2002 /* AND rS with a mask that is 0 when rB >= 0x40 */
2003 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2004 tcg_gen_sari_tl(t0, t0, 0x3f);
2005 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2006 t1 = tcg_temp_new();
2007 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2008 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2009 tcg_temp_free(t1);
2010 tcg_temp_free(t0);
2011 if (unlikely(Rc(ctx->opcode) != 0))
2012 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2013 }
2014 #endif
2015
2016 /*** Floating-Point arithmetic ***/
2017 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2018 static void gen_f##name(DisasContext *ctx) \
2019 { \
2020 if (unlikely(!ctx->fpu_enabled)) { \
2021 gen_exception(ctx, POWERPC_EXCP_FPU); \
2022 return; \
2023 } \
2024 /* NIP cannot be restored if the memory exception comes from an helper */ \
2025 gen_update_nip(ctx, ctx->nip - 4); \
2026 gen_reset_fpstatus(); \
2027 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2028 cpu_fpr[rA(ctx->opcode)], \
2029 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2030 if (isfloat) { \
2031 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2032 cpu_fpr[rD(ctx->opcode)]); \
2033 } \
2034 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2035 Rc(ctx->opcode) != 0); \
2036 }
2037
2038 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2039 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2040 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2041
2042 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2043 static void gen_f##name(DisasContext *ctx) \
2044 { \
2045 if (unlikely(!ctx->fpu_enabled)) { \
2046 gen_exception(ctx, POWERPC_EXCP_FPU); \
2047 return; \
2048 } \
2049 /* NIP cannot be restored if the memory exception comes from an helper */ \
2050 gen_update_nip(ctx, ctx->nip - 4); \
2051 gen_reset_fpstatus(); \
2052 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2053 cpu_fpr[rA(ctx->opcode)], \
2054 cpu_fpr[rB(ctx->opcode)]); \
2055 if (isfloat) { \
2056 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2057 cpu_fpr[rD(ctx->opcode)]); \
2058 } \
2059 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2060 set_fprf, Rc(ctx->opcode) != 0); \
2061 }
2062 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2063 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2064 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2065
2066 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2067 static void gen_f##name(DisasContext *ctx) \
2068 { \
2069 if (unlikely(!ctx->fpu_enabled)) { \
2070 gen_exception(ctx, POWERPC_EXCP_FPU); \
2071 return; \
2072 } \
2073 /* NIP cannot be restored if the memory exception comes from an helper */ \
2074 gen_update_nip(ctx, ctx->nip - 4); \
2075 gen_reset_fpstatus(); \
2076 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2077 cpu_fpr[rA(ctx->opcode)], \
2078 cpu_fpr[rC(ctx->opcode)]); \
2079 if (isfloat) { \
2080 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2081 cpu_fpr[rD(ctx->opcode)]); \
2082 } \
2083 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2084 set_fprf, Rc(ctx->opcode) != 0); \
2085 }
2086 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2087 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2088 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2089
2090 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2091 static void gen_f##name(DisasContext *ctx) \
2092 { \
2093 if (unlikely(!ctx->fpu_enabled)) { \
2094 gen_exception(ctx, POWERPC_EXCP_FPU); \
2095 return; \
2096 } \
2097 /* NIP cannot be restored if the memory exception comes from an helper */ \
2098 gen_update_nip(ctx, ctx->nip - 4); \
2099 gen_reset_fpstatus(); \
2100 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2101 cpu_fpr[rB(ctx->opcode)]); \
2102 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2103 set_fprf, Rc(ctx->opcode) != 0); \
2104 }
2105
2106 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2107 static void gen_f##name(DisasContext *ctx) \
2108 { \
2109 if (unlikely(!ctx->fpu_enabled)) { \
2110 gen_exception(ctx, POWERPC_EXCP_FPU); \
2111 return; \
2112 } \
2113 /* NIP cannot be restored if the memory exception comes from an helper */ \
2114 gen_update_nip(ctx, ctx->nip - 4); \
2115 gen_reset_fpstatus(); \
2116 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2117 cpu_fpr[rB(ctx->opcode)]); \
2118 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2119 set_fprf, Rc(ctx->opcode) != 0); \
2120 }
2121
2122 /* fadd - fadds */
2123 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2124 /* fdiv - fdivs */
2125 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2126 /* fmul - fmuls */
2127 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2128
2129 /* fre */
2130 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2131
2132 /* fres */
2133 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2134
2135 /* frsqrte */
2136 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2137
2138 /* frsqrtes */
2139 static void gen_frsqrtes(DisasContext *ctx)
2140 {
2141 if (unlikely(!ctx->fpu_enabled)) {
2142 gen_exception(ctx, POWERPC_EXCP_FPU);
2143 return;
2144 }
2145 /* NIP cannot be restored if the memory exception comes from an helper */
2146 gen_update_nip(ctx, ctx->nip - 4);
2147 gen_reset_fpstatus();
2148 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2149 cpu_fpr[rB(ctx->opcode)]);
2150 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2151 cpu_fpr[rD(ctx->opcode)]);
2152 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2153 }
2154
2155 /* fsel */
2156 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2157 /* fsub - fsubs */
2158 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2159 /* Optional: */
2160
2161 /* fsqrt */
2162 static void gen_fsqrt(DisasContext *ctx)
2163 {
2164 if (unlikely(!ctx->fpu_enabled)) {
2165 gen_exception(ctx, POWERPC_EXCP_FPU);
2166 return;
2167 }
2168 /* NIP cannot be restored if the memory exception comes from an helper */
2169 gen_update_nip(ctx, ctx->nip - 4);
2170 gen_reset_fpstatus();
2171 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2172 cpu_fpr[rB(ctx->opcode)]);
2173 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2174 }
2175
2176 static void gen_fsqrts(DisasContext *ctx)
2177 {
2178 if (unlikely(!ctx->fpu_enabled)) {
2179 gen_exception(ctx, POWERPC_EXCP_FPU);
2180 return;
2181 }
2182 /* NIP cannot be restored if the memory exception comes from an helper */
2183 gen_update_nip(ctx, ctx->nip - 4);
2184 gen_reset_fpstatus();
2185 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2186 cpu_fpr[rB(ctx->opcode)]);
2187 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2188 cpu_fpr[rD(ctx->opcode)]);
2189 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2190 }
2191
2192 /*** Floating-Point multiply-and-add ***/
2193 /* fmadd - fmadds */
2194 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2195 /* fmsub - fmsubs */
2196 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2197 /* fnmadd - fnmadds */
2198 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2199 /* fnmsub - fnmsubs */
2200 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2201
2202 /*** Floating-Point round & convert ***/
2203 /* fctiw */
2204 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2205 /* fctiwu */
2206 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2207 /* fctiwz */
2208 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2209 /* fctiwuz */
2210 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2211 /* frsp */
2212 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2213 #if defined(TARGET_PPC64)
2214 /* fcfid */
2215 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2216 /* fcfids */
2217 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2218 /* fcfidu */
2219 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2220 /* fcfidus */
2221 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2222 /* fctid */
2223 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2224 /* fctidu */
2225 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2226 /* fctidz */
2227 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2228 /* fctidu */
2229 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2230 #endif
2231
2232 /* frin */
2233 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2234 /* friz */
2235 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2236 /* frip */
2237 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2238 /* frim */
2239 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2240
2241 static void gen_ftdiv(DisasContext *ctx)
2242 {
2243 if (unlikely(!ctx->fpu_enabled)) {
2244 gen_exception(ctx, POWERPC_EXCP_FPU);
2245 return;
2246 }
2247 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2248 cpu_fpr[rB(ctx->opcode)]);
2249 }
2250
2251
2252
2253 /*** Floating-Point compare ***/
2254
2255 /* fcmpo */
2256 static void gen_fcmpo(DisasContext *ctx)
2257 {
2258 TCGv_i32 crf;
2259 if (unlikely(!ctx->fpu_enabled)) {
2260 gen_exception(ctx, POWERPC_EXCP_FPU);
2261 return;
2262 }
2263 /* NIP cannot be restored if the memory exception comes from an helper */
2264 gen_update_nip(ctx, ctx->nip - 4);
2265 gen_reset_fpstatus();
2266 crf = tcg_const_i32(crfD(ctx->opcode));
2267 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2268 cpu_fpr[rB(ctx->opcode)], crf);
2269 tcg_temp_free_i32(crf);
2270 gen_helper_float_check_status(cpu_env);
2271 }
2272
2273 /* fcmpu */
2274 static void gen_fcmpu(DisasContext *ctx)
2275 {
2276 TCGv_i32 crf;
2277 if (unlikely(!ctx->fpu_enabled)) {
2278 gen_exception(ctx, POWERPC_EXCP_FPU);
2279 return;
2280 }
2281 /* NIP cannot be restored if the memory exception comes from an helper */
2282 gen_update_nip(ctx, ctx->nip - 4);
2283 gen_reset_fpstatus();
2284 crf = tcg_const_i32(crfD(ctx->opcode));
2285 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2286 cpu_fpr[rB(ctx->opcode)], crf);
2287 tcg_temp_free_i32(crf);
2288 gen_helper_float_check_status(cpu_env);
2289 }
2290
2291 /*** Floating-point move ***/
2292 /* fabs */
2293 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2294 static void gen_fabs(DisasContext *ctx)
2295 {
2296 if (unlikely(!ctx->fpu_enabled)) {
2297 gen_exception(ctx, POWERPC_EXCP_FPU);
2298 return;
2299 }
2300 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2301 ~(1ULL << 63));
2302 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2303 }
2304
2305 /* fmr - fmr. */
2306 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2307 static void gen_fmr(DisasContext *ctx)
2308 {
2309 if (unlikely(!ctx->fpu_enabled)) {
2310 gen_exception(ctx, POWERPC_EXCP_FPU);
2311 return;
2312 }
2313 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2314 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2315 }
2316
2317 /* fnabs */
2318 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2319 static void gen_fnabs(DisasContext *ctx)
2320 {
2321 if (unlikely(!ctx->fpu_enabled)) {
2322 gen_exception(ctx, POWERPC_EXCP_FPU);
2323 return;
2324 }
2325 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2326 1ULL << 63);
2327 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2328 }
2329
2330 /* fneg */
2331 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2332 static void gen_fneg(DisasContext *ctx)
2333 {
2334 if (unlikely(!ctx->fpu_enabled)) {
2335 gen_exception(ctx, POWERPC_EXCP_FPU);
2336 return;
2337 }
2338 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2339 1ULL << 63);
2340 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2341 }
2342
2343 /* fcpsgn: PowerPC 2.05 specification */
2344 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2345 static void gen_fcpsgn(DisasContext *ctx)
2346 {
2347 if (unlikely(!ctx->fpu_enabled)) {
2348 gen_exception(ctx, POWERPC_EXCP_FPU);
2349 return;
2350 }
2351 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2352 cpu_fpr[rB(ctx->opcode)], 0, 63);
2353 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2354 }
2355
2356 static void gen_fmrgew(DisasContext *ctx)
2357 {
2358 TCGv_i64 b0;
2359 if (unlikely(!ctx->fpu_enabled)) {
2360 gen_exception(ctx, POWERPC_EXCP_FPU);
2361 return;
2362 }
2363 b0 = tcg_temp_new_i64();
2364 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2365 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2366 b0, 0, 32);
2367 tcg_temp_free_i64(b0);
2368 }
2369
2370 static void gen_fmrgow(DisasContext *ctx)
2371 {
2372 if (unlikely(!ctx->fpu_enabled)) {
2373 gen_exception(ctx, POWERPC_EXCP_FPU);
2374 return;
2375 }
2376 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2377 cpu_fpr[rB(ctx->opcode)],
2378 cpu_fpr[rA(ctx->opcode)],
2379 32, 32);
2380 }
2381
2382 /*** Floating-Point status & ctrl register ***/
2383
2384 /* mcrfs */
2385 static void gen_mcrfs(DisasContext *ctx)
2386 {
2387 TCGv tmp = tcg_temp_new();
2388 int bfa;
2389
2390 if (unlikely(!ctx->fpu_enabled)) {
2391 gen_exception(ctx, POWERPC_EXCP_FPU);
2392 return;
2393 }
2394 bfa = 4 * (7 - crfS(ctx->opcode));
2395 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2396 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2397 tcg_temp_free(tmp);
2398 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2399 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2400 }
2401
2402 /* mffs */
2403 static void gen_mffs(DisasContext *ctx)
2404 {
2405 if (unlikely(!ctx->fpu_enabled)) {
2406 gen_exception(ctx, POWERPC_EXCP_FPU);
2407 return;
2408 }
2409 gen_reset_fpstatus();
2410 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2411 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2412 }
2413
2414 /* mtfsb0 */
2415 static void gen_mtfsb0(DisasContext *ctx)
2416 {
2417 uint8_t crb;
2418
2419 if (unlikely(!ctx->fpu_enabled)) {
2420 gen_exception(ctx, POWERPC_EXCP_FPU);
2421 return;
2422 }
2423 crb = 31 - crbD(ctx->opcode);
2424 gen_reset_fpstatus();
2425 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2426 TCGv_i32 t0;
2427 /* NIP cannot be restored if the memory exception comes from an helper */
2428 gen_update_nip(ctx, ctx->nip - 4);
2429 t0 = tcg_const_i32(crb);
2430 gen_helper_fpscr_clrbit(cpu_env, t0);
2431 tcg_temp_free_i32(t0);
2432 }
2433 if (unlikely(Rc(ctx->opcode) != 0)) {
2434 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2435 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2436 }
2437 }
2438
2439 /* mtfsb1 */
2440 static void gen_mtfsb1(DisasContext *ctx)
2441 {
2442 uint8_t crb;
2443
2444 if (unlikely(!ctx->fpu_enabled)) {
2445 gen_exception(ctx, POWERPC_EXCP_FPU);
2446 return;
2447 }
2448 crb = 31 - crbD(ctx->opcode);
2449 gen_reset_fpstatus();
2450 /* XXX: we pretend we can only do IEEE floating-point computations */
2451 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2452 TCGv_i32 t0;
2453 /* NIP cannot be restored if the memory exception comes from an helper */
2454 gen_update_nip(ctx, ctx->nip - 4);
2455 t0 = tcg_const_i32(crb);
2456 gen_helper_fpscr_setbit(cpu_env, t0);
2457 tcg_temp_free_i32(t0);
2458 }
2459 if (unlikely(Rc(ctx->opcode) != 0)) {
2460 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2461 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2462 }
2463 /* We can raise a differed exception */
2464 gen_helper_float_check_status(cpu_env);
2465 }
2466
2467 /* mtfsf */
2468 static void gen_mtfsf(DisasContext *ctx)
2469 {
2470 TCGv_i32 t0;
2471 int flm, l, w;
2472
2473 if (unlikely(!ctx->fpu_enabled)) {
2474 gen_exception(ctx, POWERPC_EXCP_FPU);
2475 return;
2476 }
2477 flm = FPFLM(ctx->opcode);
2478 l = FPL(ctx->opcode);
2479 w = FPW(ctx->opcode);
2480 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2481 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2482 return;
2483 }
2484 /* NIP cannot be restored if the memory exception comes from an helper */
2485 gen_update_nip(ctx, ctx->nip - 4);
2486 gen_reset_fpstatus();
2487 if (l) {
2488 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2489 } else {
2490 t0 = tcg_const_i32(flm << (w * 8));
2491 }
2492 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2493 tcg_temp_free_i32(t0);
2494 if (unlikely(Rc(ctx->opcode) != 0)) {
2495 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2496 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2497 }
2498 /* We can raise a differed exception */
2499 gen_helper_float_check_status(cpu_env);
2500 }
2501
2502 /* mtfsfi */
2503 static void gen_mtfsfi(DisasContext *ctx)
2504 {
2505 int bf, sh, w;
2506 TCGv_i64 t0;
2507 TCGv_i32 t1;
2508
2509 if (unlikely(!ctx->fpu_enabled)) {
2510 gen_exception(ctx, POWERPC_EXCP_FPU);
2511 return;
2512 }
2513 w = FPW(ctx->opcode);
2514 bf = FPBF(ctx->opcode);
2515 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2516 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2517 return;
2518 }
2519 sh = (8 * w) + 7 - bf;
2520 /* NIP cannot be restored if the memory exception comes from an helper */
2521 gen_update_nip(ctx, ctx->nip - 4);
2522 gen_reset_fpstatus();
2523 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2524 t1 = tcg_const_i32(1 << sh);
2525 gen_helper_store_fpscr(cpu_env, t0, t1);
2526 tcg_temp_free_i64(t0);
2527 tcg_temp_free_i32(t1);
2528 if (unlikely(Rc(ctx->opcode) != 0)) {
2529 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2530 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2531 }
2532 /* We can raise a differed exception */
2533 gen_helper_float_check_status(cpu_env);
2534 }
2535
2536 /*** Addressing modes ***/
2537 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2538 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2539 target_long maskl)
2540 {
2541 target_long simm = SIMM(ctx->opcode);
2542
2543 simm &= ~maskl;
2544 if (rA(ctx->opcode) == 0) {
2545 if (NARROW_MODE(ctx)) {
2546 simm = (uint32_t)simm;
2547 }
2548 tcg_gen_movi_tl(EA, simm);
2549 } else if (likely(simm != 0)) {
2550 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2551 if (NARROW_MODE(ctx)) {
2552 tcg_gen_ext32u_tl(EA, EA);
2553 }
2554 } else {
2555 if (NARROW_MODE(ctx)) {
2556 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2557 } else {
2558 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2559 }
2560 }
2561 }
2562
2563 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2564 {
2565 if (rA(ctx->opcode) == 0) {
2566 if (NARROW_MODE(ctx)) {
2567 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2568 } else {
2569 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2570 }
2571 } else {
2572 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2573 if (NARROW_MODE(ctx)) {
2574 tcg_gen_ext32u_tl(EA, EA);
2575 }
2576 }
2577 }
2578
2579 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2580 {
2581 if (rA(ctx->opcode) == 0) {
2582 tcg_gen_movi_tl(EA, 0);
2583 } else if (NARROW_MODE(ctx)) {
2584 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2585 } else {
2586 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2587 }
2588 }
2589
2590 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2591 target_long val)
2592 {
2593 tcg_gen_addi_tl(ret, arg1, val);
2594 if (NARROW_MODE(ctx)) {
2595 tcg_gen_ext32u_tl(ret, ret);
2596 }
2597 }
2598
2599 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2600 {
2601 int l1 = gen_new_label();
2602 TCGv t0 = tcg_temp_new();
2603 TCGv_i32 t1, t2;
2604 /* NIP cannot be restored if the memory exception comes from an helper */
2605 gen_update_nip(ctx, ctx->nip - 4);
2606 tcg_gen_andi_tl(t0, EA, mask);
2607 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2608 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2609 t2 = tcg_const_i32(0);
2610 gen_helper_raise_exception_err(cpu_env, t1, t2);
2611 tcg_temp_free_i32(t1);
2612 tcg_temp_free_i32(t2);
2613 gen_set_label(l1);
2614 tcg_temp_free(t0);
2615 }
2616
2617 /*** Integer load ***/
2618 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2619 {
2620 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2621 }
2622
2623 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2624 {
2625 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2626 }
2627
2628 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2629 {
2630 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2631 if (unlikely(ctx->le_mode)) {
2632 tcg_gen_bswap16_tl(arg1, arg1);
2633 }
2634 }
2635
2636 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2637 {
2638 if (unlikely(ctx->le_mode)) {
2639 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2640 tcg_gen_bswap16_tl(arg1, arg1);
2641 tcg_gen_ext16s_tl(arg1, arg1);
2642 } else {
2643 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2644 }
2645 }
2646
2647 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2648 {
2649 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2650 if (unlikely(ctx->le_mode)) {
2651 tcg_gen_bswap32_tl(arg1, arg1);
2652 }
2653 }
2654
2655 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2656 {
2657 TCGv tmp = tcg_temp_new();
2658 gen_qemu_ld32u(ctx, tmp, addr);
2659 tcg_gen_extu_tl_i64(val, tmp);
2660 tcg_temp_free(tmp);
2661 }
2662
2663 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2664 {
2665 if (unlikely(ctx->le_mode)) {
2666 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2667 tcg_gen_bswap32_tl(arg1, arg1);
2668 tcg_gen_ext32s_tl(arg1, arg1);
2669 } else
2670 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2671 }
2672
2673 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2674 {
2675 TCGv tmp = tcg_temp_new();
2676 gen_qemu_ld32s(ctx, tmp, addr);
2677 tcg_gen_ext_tl_i64(val, tmp);
2678 tcg_temp_free(tmp);
2679 }
2680
2681 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2682 {
2683 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2684 if (unlikely(ctx->le_mode)) {
2685 tcg_gen_bswap64_i64(arg1, arg1);
2686 }
2687 }
2688
2689 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2690 {
2691 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2692 }
2693
2694 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2695 {
2696 if (unlikely(ctx->le_mode)) {
2697 TCGv t0 = tcg_temp_new();
2698 tcg_gen_ext16u_tl(t0, arg1);
2699 tcg_gen_bswap16_tl(t0, t0);
2700 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2701 tcg_temp_free(t0);
2702 } else {
2703 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2704 }
2705 }
2706
2707 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2708 {
2709 if (unlikely(ctx->le_mode)) {
2710 TCGv t0 = tcg_temp_new();
2711 tcg_gen_ext32u_tl(t0, arg1);
2712 tcg_gen_bswap32_tl(t0, t0);
2713 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2714 tcg_temp_free(t0);
2715 } else {
2716 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2717 }
2718 }
2719
2720 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2721 {
2722 TCGv tmp = tcg_temp_new();
2723 tcg_gen_trunc_i64_tl(tmp, val);
2724 gen_qemu_st32(ctx, tmp, addr);
2725 tcg_temp_free(tmp);
2726 }
2727
2728 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2729 {
2730 if (unlikely(ctx->le_mode)) {
2731 TCGv_i64 t0 = tcg_temp_new_i64();
2732 tcg_gen_bswap64_i64(t0, arg1);
2733 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2734 tcg_temp_free_i64(t0);
2735 } else
2736 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2737 }
2738
2739 #define GEN_LD(name, ldop, opc, type) \
2740 static void glue(gen_, name)(DisasContext *ctx) \
2741 { \
2742 TCGv EA; \
2743 gen_set_access_type(ctx, ACCESS_INT); \
2744 EA = tcg_temp_new(); \
2745 gen_addr_imm_index(ctx, EA, 0); \
2746 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2747 tcg_temp_free(EA); \
2748 }
2749
2750 #define GEN_LDU(name, ldop, opc, type) \
2751 static void glue(gen_, name##u)(DisasContext *ctx) \
2752 { \
2753 TCGv EA; \
2754 if (unlikely(rA(ctx->opcode) == 0 || \
2755 rA(ctx->opcode) == rD(ctx->opcode))) { \
2756 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2757 return; \
2758 } \
2759 gen_set_access_type(ctx, ACCESS_INT); \
2760 EA = tcg_temp_new(); \
2761 if (type == PPC_64B) \
2762 gen_addr_imm_index(ctx, EA, 0x03); \
2763 else \
2764 gen_addr_imm_index(ctx, EA, 0); \
2765 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2766 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2767 tcg_temp_free(EA); \
2768 }
2769
2770 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2771 static void glue(gen_, name##ux)(DisasContext *ctx) \
2772 { \
2773 TCGv EA; \
2774 if (unlikely(rA(ctx->opcode) == 0 || \
2775 rA(ctx->opcode) == rD(ctx->opcode))) { \
2776 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2777 return; \
2778 } \
2779 gen_set_access_type(ctx, ACCESS_INT); \
2780 EA = tcg_temp_new(); \
2781 gen_addr_reg_index(ctx, EA); \
2782 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2783 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2784 tcg_temp_free(EA); \
2785 }
2786
2787 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2788 static void glue(gen_, name##x)(DisasContext *ctx) \
2789 { \
2790 TCGv EA; \
2791 gen_set_access_type(ctx, ACCESS_INT); \
2792 EA = tcg_temp_new(); \
2793 gen_addr_reg_index(ctx, EA); \
2794 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2795 tcg_temp_free(EA); \
2796 }
2797 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2798 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2799
2800 #define GEN_LDS(name, ldop, op, type) \
2801 GEN_LD(name, ldop, op | 0x20, type); \
2802 GEN_LDU(name, ldop, op | 0x21, type); \
2803 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2804 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2805
2806 /* lbz lbzu lbzux lbzx */
2807 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2808 /* lha lhau lhaux lhax */
2809 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2810 /* lhz lhzu lhzux lhzx */
2811 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2812 /* lwz lwzu lwzux lwzx */
2813 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2814 #if defined(TARGET_PPC64)
2815 /* lwaux */
2816 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2817 /* lwax */
2818 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2819 /* ldux */
2820 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2821 /* ldx */
2822 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2823
2824 static void gen_ld(DisasContext *ctx)
2825 {
2826 TCGv EA;
2827 if (Rc(ctx->opcode)) {
2828 if (unlikely(rA(ctx->opcode) == 0 ||
2829 rA(ctx->opcode) == rD(ctx->opcode))) {
2830 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2831 return;
2832 }
2833 }
2834 gen_set_access_type(ctx, ACCESS_INT);
2835 EA = tcg_temp_new();
2836 gen_addr_imm_index(ctx, EA, 0x03);
2837 if (ctx->opcode & 0x02) {
2838 /* lwa (lwau is undefined) */
2839 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2840 } else {
2841 /* ld - ldu */
2842 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2843 }
2844 if (Rc(ctx->opcode))
2845 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2846 tcg_temp_free(EA);
2847 }
2848
2849 /* lq */
2850 static void gen_lq(DisasContext *ctx)
2851 {
2852 #if defined(CONFIG_USER_ONLY)
2853 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2854 #else
2855 int ra, rd;
2856 TCGv EA;
2857
2858 /* Restore CPU state */
2859 if (unlikely(ctx->mem_idx == 0)) {
2860 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2861 return;
2862 }
2863 ra = rA(ctx->opcode);
2864 rd = rD(ctx->opcode);
2865 if (unlikely((rd & 1) || rd == ra)) {
2866 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2867 return;
2868 }
2869 if (unlikely(ctx->le_mode)) {
2870 /* Little-endian mode is not handled */
2871 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2872 return;
2873 }
2874 gen_set_access_type(ctx, ACCESS_INT);
2875 EA = tcg_temp_new();
2876 gen_addr_imm_index(ctx, EA, 0x0F);
2877 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2878 gen_addr_add(ctx, EA, EA, 8);
2879 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2880 tcg_temp_free(EA);
2881 #endif
2882 }
2883 #endif
2884
2885 /*** Integer store ***/
2886 #define GEN_ST(name, stop, opc, type) \
2887 static void glue(gen_, name)(DisasContext *ctx) \
2888 { \
2889 TCGv EA; \
2890 gen_set_access_type(ctx, ACCESS_INT); \
2891 EA = tcg_temp_new(); \
2892 gen_addr_imm_index(ctx, EA, 0); \
2893 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2894 tcg_temp_free(EA); \
2895 }
2896
2897 #define GEN_STU(name, stop, opc, type) \
2898 static void glue(gen_, stop##u)(DisasContext *ctx) \
2899 { \
2900 TCGv EA; \
2901 if (unlikely(rA(ctx->opcode) == 0)) { \
2902 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2903 return; \
2904 } \
2905 gen_set_access_type(ctx, ACCESS_INT); \
2906 EA = tcg_temp_new(); \
2907 if (type == PPC_64B) \
2908 gen_addr_imm_index(ctx, EA, 0x03); \
2909 else \
2910 gen_addr_imm_index(ctx, EA, 0); \
2911 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2912 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2913 tcg_temp_free(EA); \
2914 }
2915
2916 #define GEN_STUX(name, stop, opc2, opc3, type) \
2917 static void glue(gen_, name##ux)(DisasContext *ctx) \
2918 { \
2919 TCGv EA; \
2920 if (unlikely(rA(ctx->opcode) == 0)) { \
2921 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2922 return; \
2923 } \
2924 gen_set_access_type(ctx, ACCESS_INT); \
2925 EA = tcg_temp_new(); \
2926 gen_addr_reg_index(ctx, EA); \
2927 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2928 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2929 tcg_temp_free(EA); \
2930 }
2931
2932 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2933 static void glue(gen_, name##x)(DisasContext *ctx) \
2934 { \
2935 TCGv EA; \
2936 gen_set_access_type(ctx, ACCESS_INT); \
2937 EA = tcg_temp_new(); \
2938 gen_addr_reg_index(ctx, EA); \
2939 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2940 tcg_temp_free(EA); \
2941 }
2942 #define GEN_STX(name, stop, opc2, opc3, type) \
2943 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2944
2945 #define GEN_STS(name, stop, op, type) \
2946 GEN_ST(name, stop, op | 0x20, type); \
2947 GEN_STU(name, stop, op | 0x21, type); \
2948 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2949 GEN_STX(name, stop, 0x17, op | 0x00, type)
2950
2951 /* stb stbu stbux stbx */
2952 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2953 /* sth sthu sthux sthx */
2954 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2955 /* stw stwu stwux stwx */
2956 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2957 #if defined(TARGET_PPC64)
2958 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2959 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2960
2961 static void gen_std(DisasContext *ctx)
2962 {
2963 int rs;
2964 TCGv EA;
2965
2966 rs = rS(ctx->opcode);
2967 if ((ctx->opcode & 0x3) == 0x2) {
2968 #if defined(CONFIG_USER_ONLY)
2969 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2970 #else
2971 /* stq */
2972 if (unlikely(ctx->mem_idx == 0)) {
2973 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2974 return;
2975 }
2976 if (unlikely(rs & 1)) {
2977 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2978 return;
2979 }
2980 if (unlikely(ctx->le_mode)) {
2981 /* Little-endian mode is not handled */
2982 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2983 return;
2984 }
2985 gen_set_access_type(ctx, ACCESS_INT);
2986 EA = tcg_temp_new();
2987 gen_addr_imm_index(ctx, EA, 0x03);
2988 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2989 gen_addr_add(ctx, EA, EA, 8);
2990 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2991 tcg_temp_free(EA);
2992 #endif
2993 } else {
2994 /* std / stdu */
2995 if (Rc(ctx->opcode)) {
2996 if (unlikely(rA(ctx->opcode) == 0)) {
2997 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2998 return;
2999 }
3000 }
3001 gen_set_access_type(ctx, ACCESS_INT);
3002 EA = tcg_temp_new();
3003 gen_addr_imm_index(ctx, EA, 0x03);
3004 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3005 if (Rc(ctx->opcode))
3006 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3007 tcg_temp_free(EA);
3008 }
3009 }
3010 #endif
3011 /*** Integer load and store with byte reverse ***/
3012 /* lhbrx */
3013 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3014 {
3015 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
3016 if (likely(!ctx->le_mode)) {
3017 tcg_gen_bswap16_tl(arg1, arg1);
3018 }
3019 }
3020 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3021
3022 /* lwbrx */
3023 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3024 {
3025 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
3026 if (likely(!ctx->le_mode)) {
3027 tcg_gen_bswap32_tl(arg1, arg1);
3028 }
3029 }
3030 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3031
3032 #if defined(TARGET_PPC64)
3033 /* ldbrx */
3034 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3035 {
3036 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
3037 if (likely(!ctx->le_mode)) {
3038 tcg_gen_bswap64_tl(arg1, arg1);
3039 }
3040 }
3041 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3042 #endif /* TARGET_PPC64 */
3043
3044 /* sthbrx */
3045 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3046 {
3047 if (likely(!ctx->le_mode)) {
3048 TCGv t0 = tcg_temp_new();
3049 tcg_gen_ext16u_tl(t0, arg1);
3050 tcg_gen_bswap16_tl(t0, t0);
3051 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3052 tcg_temp_free(t0);
3053 } else {
3054 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3055 }
3056 }
3057 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3058
3059 /* stwbrx */
3060 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3061 {
3062 if (likely(!ctx->le_mode)) {
3063 TCGv t0 = tcg_temp_new();
3064 tcg_gen_ext32u_tl(t0, arg1);
3065 tcg_gen_bswap32_tl(t0, t0);
3066 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3067 tcg_temp_free(t0);
3068 } else {
3069 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3070 }
3071 }
3072 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3073
3074 #if defined(TARGET_PPC64)
3075 /* stdbrx */
3076 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3077 {
3078 if (likely(!ctx->le_mode)) {
3079 TCGv t0 = tcg_temp_new();
3080 tcg_gen_bswap64_tl(t0, arg1);
3081 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
3082 tcg_temp_free(t0);
3083 } else {
3084 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
3085 }
3086 }
3087 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3088 #endif /* TARGET_PPC64 */
3089
3090 /*** Integer load and store multiple ***/
3091
3092 /* lmw */
3093 static void gen_lmw(DisasContext *ctx)
3094 {
3095 TCGv t0;
3096 TCGv_i32 t1;
3097 gen_set_access_type(ctx, ACCESS_INT);
3098 /* NIP cannot be restored if the memory exception comes from an helper */
3099 gen_update_nip(ctx, ctx->nip - 4);
3100 t0 = tcg_temp_new();
3101 t1 = tcg_const_i32(rD(ctx->opcode));
3102 gen_addr_imm_index(ctx, t0, 0);
3103 gen_helper_lmw(cpu_env, t0, t1);
3104 tcg_temp_free(t0);
3105 tcg_temp_free_i32(t1);
3106 }
3107
3108 /* stmw */
3109 static void gen_stmw(DisasContext *ctx)
3110 {
3111 TCGv t0;
3112 TCGv_i32 t1;
3113 gen_set_access_type(ctx, ACCESS_INT);
3114 /* NIP cannot be restored if the memory exception comes from an helper */
3115 gen_update_nip(ctx, ctx->nip - 4);
3116 t0 = tcg_temp_new();
3117 t1 = tcg_const_i32(rS(ctx->opcode));
3118 gen_addr_imm_index(ctx, t0, 0);
3119 gen_helper_stmw(cpu_env, t0, t1);
3120 tcg_temp_free(t0);
3121 tcg_temp_free_i32(t1);
3122 }
3123
3124 /*** Integer load and store strings ***/
3125
3126 /* lswi */
3127 /* PowerPC32 specification says we must generate an exception if
3128 * rA is in the range of registers to be loaded.
3129 * In an other hand, IBM says this is valid, but rA won't be loaded.
3130 * For now, I'll follow the spec...
3131 */
3132 static void gen_lswi(DisasContext *ctx)
3133 {
3134 TCGv t0;
3135 TCGv_i32 t1, t2;
3136 int nb = NB(ctx->opcode);
3137 int start = rD(ctx->opcode);
3138 int ra = rA(ctx->opcode);
3139 int nr;
3140
3141 if (nb == 0)
3142 nb = 32;
3143 nr = nb / 4;
3144 if (unlikely(((start + nr) > 32 &&
3145 start <= ra && (start + nr - 32) > ra) ||
3146 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3147 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3148 return;
3149 }
3150 gen_set_access_type(ctx, ACCESS_INT);
3151 /* NIP cannot be restored if the memory exception comes from an helper */
3152 gen_update_nip(ctx, ctx->nip - 4);
3153 t0 = tcg_temp_new();
3154 gen_addr_register(ctx, t0);
3155 t1 = tcg_const_i32(nb);
3156 t2 = tcg_const_i32(start);
3157 gen_helper_lsw(cpu_env, t0, t1, t2);
3158 tcg_temp_free(t0);
3159 tcg_temp_free_i32(t1);
3160 tcg_temp_free_i32(t2);
3161 }
3162
3163 /* lswx */
3164 static void gen_lswx(DisasContext *ctx)
3165 {
3166 TCGv t0;
3167 TCGv_i32 t1, t2, t3;
3168 gen_set_access_type(ctx, ACCESS_INT);
3169 /* NIP cannot be restored if the memory exception comes from an helper */
3170 gen_update_nip(ctx, ctx->nip - 4);
3171 t0 = tcg_temp_new();
3172 gen_addr_reg_index(ctx, t0);
3173 t1 = tcg_const_i32(rD(ctx->opcode));
3174 t2 = tcg_const_i32(rA(ctx->opcode));
3175 t3 = tcg_const_i32(rB(ctx->opcode));
3176 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3177 tcg_temp_free(t0);
3178 tcg_temp_free_i32(t1);
3179 tcg_temp_free_i32(t2);
3180 tcg_temp_free_i32(t3);
3181 }
3182
3183 /* stswi */
3184 static void gen_stswi(DisasContext *ctx)
3185 {
3186 TCGv t0;
3187 TCGv_i32 t1, t2;
3188 int nb = NB(ctx->opcode);
3189 gen_set_access_type(ctx, ACCESS_INT);
3190 /* NIP cannot be restored if the memory exception comes from an helper */
3191 gen_update_nip(ctx, ctx->nip - 4);
3192 t0 = tcg_temp_new();
3193 gen_addr_register(ctx, t0);
3194 if (nb == 0)
3195 nb = 32;
3196 t1 = tcg_const_i32(nb);
3197 t2 = tcg_const_i32(rS(ctx->opcode));
3198 gen_helper_stsw(cpu_env, t0, t1, t2);
3199 tcg_temp_free(t0);
3200 tcg_temp_free_i32(t1);
3201 tcg_temp_free_i32(t2);
3202 }
3203
3204 /* stswx */
3205 static void gen_stswx(DisasContext *ctx)
3206 {
3207 TCGv t0;
3208 TCGv_i32 t1, t2;
3209 gen_set_access_type(ctx, ACCESS_INT);
3210 /* NIP cannot be restored if the memory exception comes from an helper */
3211 gen_update_nip(ctx, ctx->nip - 4);
3212 t0 = tcg_temp_new();
3213 gen_addr_reg_index(ctx, t0);
3214 t1 = tcg_temp_new_i32();
3215 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3216 tcg_gen_andi_i32(t1, t1, 0x7F);
3217 t2 = tcg_const_i32(rS(ctx->opcode));
3218 gen_helper_stsw(cpu_env, t0, t1, t2);
3219 tcg_temp_free(t0);
3220 tcg_temp_free_i32(t1);
3221 tcg_temp_free_i32(t2);
3222 }
3223
3224 /*** Memory synchronisation ***/
3225 /* eieio */
3226 static void gen_eieio(DisasContext *ctx)
3227 {
3228 }
3229
3230 /* isync */
3231 static void gen_isync(DisasContext *ctx)
3232 {
3233 gen_stop_exception(ctx);
3234 }
3235
3236 #define LARX(name, len, loadop) \
3237 static void gen_##name(DisasContext *ctx) \
3238 { \
3239 TCGv t0; \
3240 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3241 gen_set_access_type(ctx, ACCESS_RES); \
3242 t0 = tcg_temp_local_new(); \
3243 gen_addr_reg_index(ctx, t0); \
3244 if ((len) > 1) { \
3245 gen_check_align(ctx, t0, (len)-1); \
3246 } \
3247 gen_qemu_##loadop(ctx, gpr, t0); \
3248 tcg_gen_mov_tl(cpu_reserve, t0); \
3249 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3250 tcg_temp_free(t0); \
3251 }
3252
3253 /* lwarx */
3254 LARX(lbarx, 1, ld8u);
3255 LARX(lharx, 2, ld16u);
3256 LARX(lwarx, 4, ld32u);
3257
3258
3259 #if defined(CONFIG_USER_ONLY)
3260 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3261 int reg, int size)
3262 {
3263 TCGv t0 = tcg_temp_new();
3264 uint32_t save_exception = ctx->exception;
3265
3266 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3267 tcg_gen_movi_tl(t0, (size << 5) | reg);
3268 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3269 tcg_temp_free(t0);
3270 gen_update_nip(ctx, ctx->nip-4);
3271 ctx->exception = POWERPC_EXCP_BRANCH;
3272 gen_exception(ctx, POWERPC_EXCP_STCX);
3273 ctx->exception = save_exception;
3274 }
3275 #else
3276 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3277 int reg, int size)
3278 {
3279 int l1;
3280
3281 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3282 l1 = gen_new_label();
3283 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3284 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3285 #if defined(TARGET_PPC64)
3286 if (size == 8) {
3287 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3288 } else
3289 #endif
3290 if (size == 4) {
3291 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3292 } else if (size == 2) {
3293 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3294 } else {
3295 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3296 }
3297 gen_set_label(l1);
3298 tcg_gen_movi_tl(cpu_reserve, -1);
3299 }
3300 #endif
3301
3302 #define STCX(name, len) \
3303 static void gen_##name(DisasContext *ctx) \
3304 { \
3305 TCGv t0; \
3306 gen_set_access_type(ctx, ACCESS_RES); \
3307 t0 = tcg_temp_local_new(); \
3308 gen_addr_reg_index(ctx, t0); \
3309 if (len > 1) { \
3310 gen_check_align(ctx, t0, (len)-1); \
3311 } \
3312 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3313 tcg_temp_free(t0); \
3314 }
3315
3316 STCX(stbcx_, 1);
3317 STCX(sthcx_, 2);
3318 STCX(stwcx_, 4);
3319
3320 #if defined(TARGET_PPC64)
3321 /* ldarx */
3322 LARX(ldarx, 8, ld64);
3323
3324 /* stdcx. */
3325 STCX(stdcx_, 8);
3326 #endif /* defined(TARGET_PPC64) */
3327
3328 /* sync */
3329 static void gen_sync(DisasContext *ctx)
3330 {
3331 }
3332
3333 /* wait */
3334 static void gen_wait(DisasContext *ctx)
3335 {
3336 TCGv_i32 t0 = tcg_temp_new_i32();
3337 tcg_gen_st_i32(t0, cpu_env,
3338 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3339 tcg_temp_free_i32(t0);
3340 /* Stop translation, as the CPU is supposed to sleep from now */
3341 gen_exception_err(ctx, EXCP_HLT, 1);
3342 }
3343
3344 /*** Floating-point load ***/
3345 #define GEN_LDF(name, ldop, opc, type) \
3346 static void glue(gen_, name)(DisasContext *ctx) \
3347 { \
3348 TCGv EA; \
3349 if (unlikely(!ctx->fpu_enabled)) { \
3350 gen_exception(ctx, POWERPC_EXCP_FPU); \
3351 return; \
3352 } \
3353 gen_set_access_type(ctx, ACCESS_FLOAT); \
3354 EA = tcg_temp_new(); \
3355 gen_addr_imm_index(ctx, EA, 0); \
3356 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3357 tcg_temp_free(EA); \
3358 }
3359
3360 #define GEN_LDUF(name, ldop, opc, type) \
3361 static void glue(gen_, name##u)(DisasContext *ctx) \
3362 { \
3363 TCGv EA; \
3364 if (unlikely(!ctx->fpu_enabled)) { \
3365 gen_exception(ctx, POWERPC_EXCP_FPU); \
3366 return; \
3367 } \
3368 if (unlikely(rA(ctx->opcode) == 0)) { \
3369 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3370 return; \
3371 } \
3372 gen_set_access_type(ctx, ACCESS_FLOAT); \
3373 EA = tcg_temp_new(); \
3374 gen_addr_imm_index(ctx, EA, 0); \
3375 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3376 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3377 tcg_temp_free(EA); \
3378 }
3379
3380 #define GEN_LDUXF(name, ldop, opc, type) \
3381 static void glue(gen_, name##ux)(DisasContext *ctx) \
3382 { \
3383 TCGv EA; \
3384 if (unlikely(!ctx->fpu_enabled)) { \
3385 gen_exception(ctx, POWERPC_EXCP_FPU); \
3386 return; \
3387 } \
3388 if (unlikely(rA(ctx->opcode) == 0)) { \
3389 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3390 return; \
3391 } \
3392 gen_set_access_type(ctx, ACCESS_FLOAT); \
3393 EA = tcg_temp_new(); \
3394 gen_addr_reg_index(ctx, EA); \
3395 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3396 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3397 tcg_temp_free(EA); \
3398 }
3399
3400 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3401 static void glue(gen_, name##x)(DisasContext *ctx) \
3402 { \
3403 TCGv EA; \
3404 if (unlikely(!ctx->fpu_enabled)) { \
3405 gen_exception(ctx, POWERPC_EXCP_FPU); \
3406 return; \
3407 } \
3408 gen_set_access_type(ctx, ACCESS_FLOAT); \
3409 EA = tcg_temp_new(); \
3410 gen_addr_reg_index(ctx, EA); \
3411 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3412 tcg_temp_free(EA); \
3413 }
3414
3415 #define GEN_LDFS(name, ldop, op, type) \
3416 GEN_LDF(name, ldop, op | 0x20, type); \
3417 GEN_LDUF(name, ldop, op | 0x21, type); \
3418 GEN_LDUXF(name, ldop, op | 0x01, type); \
3419 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3420
3421 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3422 {
3423 TCGv t0 = tcg_temp_new();
3424 TCGv_i32 t1 = tcg_temp_new_i32();
3425 gen_qemu_ld32u(ctx, t0, arg2);
3426 tcg_gen_trunc_tl_i32(t1, t0);
3427 tcg_temp_free(t0);
3428 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3429 tcg_temp_free_i32(t1);
3430 }
3431
3432 /* lfd lfdu lfdux lfdx */
3433 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3434 /* lfs lfsu lfsux lfsx */
3435 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3436
3437 /* lfdp */
3438 static void gen_lfdp(DisasContext *ctx)
3439 {
3440 TCGv EA;
3441 if (unlikely(!ctx->fpu_enabled)) {
3442 gen_exception(ctx, POWERPC_EXCP_FPU);
3443 return;
3444 }
3445 gen_set_access_type(ctx, ACCESS_FLOAT);
3446 EA = tcg_temp_new();
3447 gen_addr_imm_index(ctx, EA, 0); \
3448 if (unlikely(ctx->le_mode)) {
3449 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3450 tcg_gen_addi_tl(EA, EA, 8);
3451 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3452 } else {
3453 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3454 tcg_gen_addi_tl(EA, EA, 8);
3455 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3456 }
3457 tcg_temp_free(EA);
3458 }
3459
3460 /* lfdpx */
3461 static void gen_lfdpx(DisasContext *ctx)
3462 {
3463 TCGv EA;
3464 if (unlikely(!ctx->fpu_enabled)) {
3465 gen_exception(ctx, POWERPC_EXCP_FPU);
3466 return;
3467 }
3468 gen_set_access_type(ctx, ACCESS_FLOAT);
3469 EA = tcg_temp_new();
3470 gen_addr_reg_index(ctx, EA);
3471 if (unlikely(ctx->le_mode)) {
3472 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3473 tcg_gen_addi_tl(EA, EA, 8);
3474 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3475 } else {
3476 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3477 tcg_gen_addi_tl(EA, EA, 8);
3478 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3479 }
3480 tcg_temp_free(EA);
3481 }
3482
3483 /* lfiwax */
3484 static void gen_lfiwax(DisasContext *ctx)
3485 {
3486 TCGv EA;
3487 TCGv t0;
3488 if (unlikely(!ctx->fpu_enabled)) {
3489 gen_exception(ctx, POWERPC_EXCP_FPU);
3490 return;
3491 }
3492 gen_set_access_type(ctx, ACCESS_FLOAT);
3493 EA = tcg_temp_new();
3494 t0 = tcg_temp_new();
3495 gen_addr_reg_index(ctx, EA);
3496 gen_qemu_ld32s(ctx, t0, EA);
3497 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3498 tcg_temp_free(EA);
3499 tcg_temp_free(t0);
3500 }
3501
3502 /*** Floating-point store ***/
3503 #define GEN_STF(name, stop, opc, type) \
3504 static void glue(gen_, name)(DisasContext *ctx) \
3505 { \
3506 TCGv EA; \
3507 if (unlikely(!ctx->fpu_enabled)) { \
3508 gen_exception(ctx, POWERPC_EXCP_FPU); \
3509 return; \
3510 } \
3511 gen_set_access_type(ctx, ACCESS_FLOAT); \
3512 EA = tcg_temp_new(); \
3513 gen_addr_imm_index(ctx, EA, 0); \
3514 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3515 tcg_temp_free(EA); \
3516 }
3517
3518 #define GEN_STUF(name, stop, opc, type) \
3519 static void glue(gen_, name##u)(DisasContext *ctx) \
3520 { \
3521 TCGv EA; \
3522 if (unlikely(!ctx->fpu_enabled)) { \
3523 gen_exception(ctx, POWERPC_EXCP_FPU); \
3524 return; \
3525 } \
3526 if (unlikely(rA(ctx->opcode) == 0)) { \
3527 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3528 return; \
3529 } \
3530 gen_set_access_type(ctx, ACCESS_FLOAT); \
3531 EA = tcg_temp_new(); \
3532 gen_addr_imm_index(ctx, EA, 0); \
3533 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3534 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3535 tcg_temp_free(EA); \
3536 }
3537
3538 #define GEN_STUXF(name, stop, opc, type) \
3539 static void glue(gen_, name##ux)(DisasContext *ctx) \
3540 { \
3541 TCGv EA; \
3542 if (unlikely(!ctx->fpu_enabled)) { \
3543 gen_exception(ctx, POWERPC_EXCP_FPU); \
3544 return; \
3545 } \
3546 if (unlikely(rA(ctx->opcode) == 0)) { \
3547 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3548 return; \
3549 } \
3550 gen_set_access_type(ctx, ACCESS_FLOAT); \
3551 EA = tcg_temp_new(); \
3552 gen_addr_reg_index(ctx, EA); \
3553 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3554 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3555 tcg_temp_free(EA); \
3556 }
3557
3558 #define GEN_STXF(name, stop, opc2, opc3, type) \
3559 static void glue(gen_, name##x)(DisasContext *ctx) \
3560 { \
3561 TCGv EA; \
3562 if (unlikely(!ctx->fpu_enabled)) { \
3563 gen_exception(ctx, POWERPC_EXCP_FPU); \
3564 return; \
3565 } \
3566 gen_set_access_type(ctx, ACCESS_FLOAT); \
3567 EA = tcg_temp_new(); \
3568 gen_addr_reg_index(ctx, EA); \
3569 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3570 tcg_temp_free(EA); \
3571 }
3572
3573 #define GEN_STFS(name, stop, op, type) \
3574 GEN_STF(name, stop, op | 0x20, type); \
3575 GEN_STUF(name, stop, op | 0x21, type); \
3576 GEN_STUXF(name, stop, op | 0x01, type); \
3577 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3578
3579 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3580 {
3581 TCGv_i32 t0 = tcg_temp_new_i32();
3582 TCGv t1 = tcg_temp_new();
3583 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3584 tcg_gen_extu_i32_tl(t1, t0);
3585 tcg_temp_free_i32(t0);
3586 gen_qemu_st32(ctx, t1, arg2);
3587 tcg_temp_free(t1);
3588 }
3589
3590 /* stfd stfdu stfdux stfdx */
3591 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3592 /* stfs stfsu stfsux stfsx */
3593 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3594
3595 /* stfdp */
3596 static void gen_stfdp(DisasContext *ctx)
3597 {
3598 TCGv EA;
3599 if (unlikely(!ctx->fpu_enabled)) {
3600 gen_exception(ctx, POWERPC_EXCP_FPU);
3601 return;
3602 }
3603 gen_set_access_type(ctx, ACCESS_FLOAT);
3604 EA = tcg_temp_new();
3605 gen_addr_imm_index(ctx, EA, 0); \
3606 if (unlikely(ctx->le_mode)) {
3607 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3608 tcg_gen_addi_tl(EA, EA, 8);
3609 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3610 } else {
3611 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3612 tcg_gen_addi_tl(EA, EA, 8);
3613 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3614 }
3615 tcg_temp_free(EA);
3616 }
3617
3618 /* stfdpx */
3619 static void gen_stfdpx(DisasContext *ctx)
3620 {
3621 TCGv EA;
3622 if (unlikely(!ctx->fpu_enabled)) {
3623 gen_exception(ctx, POWERPC_EXCP_FPU);
3624 return;
3625 }
3626 gen_set_access_type(ctx, ACCESS_FLOAT);
3627 EA = tcg_temp_new();
3628 gen_addr_reg_index(ctx, EA);
3629 if (unlikely(ctx->le_mode)) {
3630 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3631 tcg_gen_addi_tl(EA, EA, 8);
3632 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3633 } else {
3634 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3635 tcg_gen_addi_tl(EA, EA, 8);
3636 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3637 }
3638 tcg_temp_free(EA);
3639 }
3640
3641 /* Optional: */
3642 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3643 {
3644 TCGv t0 = tcg_temp_new();
3645 tcg_gen_trunc_i64_tl(t0, arg1),
3646 gen_qemu_st32(ctx, t0, arg2);
3647 tcg_temp_free(t0);
3648 }
3649 /* stfiwx */
3650 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3651
3652 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3653 {
3654 #if defined(TARGET_PPC64)
3655 if (ctx->has_cfar)
3656 tcg_gen_movi_tl(cpu_cfar, nip);
3657 #endif
3658 }
3659
3660 /*** Branch ***/
3661 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3662 {
3663 TranslationBlock *tb;
3664 tb = ctx->tb;
3665 if (NARROW_MODE(ctx)) {
3666 dest = (uint32_t) dest;
3667 }
3668 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3669 likely(!ctx->singlestep_enabled)) {
3670 tcg_gen_goto_tb(n);
3671 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3672 tcg_gen_exit_tb((uintptr_t)tb + n);
3673 } else {
3674 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3675 if (unlikely(ctx->singlestep_enabled)) {
3676 if ((ctx->singlestep_enabled &
3677 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3678 (ctx->exception == POWERPC_EXCP_BRANCH ||
3679 ctx->exception == POWERPC_EXCP_TRACE)) {
3680 target_ulong tmp = ctx->nip;
3681 ctx->nip = dest;
3682 gen_exception(ctx, POWERPC_EXCP_TRACE);
3683 ctx->nip = tmp;
3684 }
3685 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3686 gen_debug_exception(ctx);
3687 }
3688 }
3689 tcg_gen_exit_tb(0);
3690 }
3691 }
3692
3693 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3694 {
3695 if (NARROW_MODE(ctx)) {
3696 nip = (uint32_t)nip;
3697 }
3698 tcg_gen_movi_tl(cpu_lr, nip);
3699 }
3700
3701 /* b ba bl bla */
3702 static void gen_b(DisasContext *ctx)
3703 {
3704 target_ulong li, target;
3705
3706 ctx->exception = POWERPC_EXCP_BRANCH;
3707 /* sign extend LI */
3708 li = LI(ctx->opcode);
3709 li = (li ^ 0x02000000) - 0x02000000;
3710 if (likely(AA(ctx->opcode) == 0)) {
3711 target = ctx->nip + li - 4;
3712 } else {
3713 target = li;
3714 }
3715 if (LK(ctx->opcode)) {
3716 gen_setlr(ctx, ctx->nip);
3717 }
3718 gen_update_cfar(ctx, ctx->nip);
3719 gen_goto_tb(ctx, 0, target);
3720 }
3721
3722 #define BCOND_IM 0
3723 #define BCOND_LR 1
3724 #define BCOND_CTR 2
3725
3726 static inline void gen_bcond(DisasContext *ctx, int type)
3727 {
3728 uint32_t bo = BO(ctx->opcode);
3729 int l1;
3730 TCGv target;
3731
3732 ctx->exception = POWERPC_EXCP_BRANCH;
3733 if (type == BCOND_LR || type == BCOND_CTR) {
3734 target = tcg_temp_local_new();
3735 if (type == BCOND_CTR)
3736 tcg_gen_mov_tl(target, cpu_ctr);
3737 else
3738 tcg_gen_mov_tl(target, cpu_lr);
3739 } else {
3740 TCGV_UNUSED(target);
3741 }
3742 if (LK(ctx->opcode))
3743 gen_setlr(ctx, ctx->nip);
3744 l1 = gen_new_label();
3745 if ((bo & 0x4) == 0) {
3746 /* Decrement and test CTR */
3747 TCGv temp = tcg_temp_new();
3748 if (unlikely(type == BCOND_CTR)) {
3749 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3750 return;
3751 }
3752 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3753 if (NARROW_MODE(ctx)) {
3754 tcg_gen_ext32u_tl(temp, cpu_ctr);
3755 } else {
3756 tcg_gen_mov_tl(temp, cpu_ctr);
3757 }
3758 if (bo & 0x2) {
3759 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3760 } else {
3761 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3762 }
3763 tcg_temp_free(temp);
3764 }
3765 if ((bo & 0x10) == 0) {
3766 /* Test CR */
3767 uint32_t bi = BI(ctx->opcode);
3768 uint32_t mask = 1 << (3 - (bi & 0x03));
3769 TCGv_i32 temp = tcg_temp_new_i32();
3770
3771 if (bo & 0x8) {
3772 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3773 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3774 } else {
3775 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3776 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3777 }
3778 tcg_temp_free_i32(temp);
3779 }
3780 gen_update_cfar(ctx, ctx->nip);
3781 if (type == BCOND_IM) {
3782 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3783 if (likely(AA(ctx->opcode) == 0)) {
3784 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3785 } else {
3786 gen_goto_tb(ctx, 0, li);
3787 }
3788 gen_set_label(l1);
3789 gen_goto_tb(ctx, 1, ctx->nip);
3790 } else {
3791 if (NARROW_MODE(ctx)) {
3792 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3793 } else {
3794 tcg_gen_andi_tl(cpu_nip, target, ~3);
3795 }
3796 tcg_gen_exit_tb(0);
3797 gen_set_label(l1);
3798 gen_update_nip(ctx, ctx->nip);
3799 tcg_gen_exit_tb(0);
3800 }
3801 }
3802
3803 static void gen_bc(DisasContext *ctx)
3804 {
3805 gen_bcond(ctx, BCOND_IM);
3806 }
3807
3808 static void gen_bcctr(DisasContext *ctx)
3809 {
3810 gen_bcond(ctx, BCOND_CTR);
3811 }
3812
3813 static void gen_bclr(DisasContext *ctx)
3814 {
3815 gen_bcond(ctx, BCOND_LR);
3816 }
3817
3818 /*** Condition register logical ***/
3819 #define GEN_CRLOGIC(name, tcg_op, opc) \
3820 static void glue(gen_, name)(DisasContext *ctx) \
3821 { \
3822 uint8_t bitmask; \
3823 int sh; \
3824 TCGv_i32 t0, t1; \
3825 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3826 t0 = tcg_temp_new_i32(); \
3827 if (sh > 0) \
3828 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3829 else if (sh < 0) \
3830 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3831 else \
3832 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3833 t1 = tcg_temp_new_i32(); \
3834 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3835 if (sh > 0) \
3836 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3837 else if (sh < 0) \
3838 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3839 else \
3840 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3841 tcg_op(t0, t0, t1); \
3842 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3843 tcg_gen_andi_i32(t0, t0, bitmask); \
3844 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3845 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3846 tcg_temp_free_i32(t0); \
3847 tcg_temp_free_i32(t1); \
3848 }
3849
3850 /* crand */
3851 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3852 /* crandc */
3853 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3854 /* creqv */
3855 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3856 /* crnand */
3857 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3858 /* crnor */
3859 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3860 /* cror */
3861 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3862 /* crorc */
3863 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3864 /* crxor */
3865 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3866
3867 /* mcrf */
3868 static void gen_mcrf(DisasContext *ctx)
3869 {
3870 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3871 }
3872
3873 /*** System linkage ***/
3874
3875 /* rfi (mem_idx only) */
3876 static void gen_rfi(DisasContext *ctx)
3877 {
3878 #if defined(CONFIG_USER_ONLY)
3879 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3880 #else
3881 /* Restore CPU state */
3882 if (unlikely(!ctx->mem_idx)) {
3883 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3884 return;
3885 }
3886 gen_update_cfar(ctx, ctx->nip);
3887 gen_helper_rfi(cpu_env);
3888 gen_sync_exception(ctx);
3889 #endif
3890 }
3891
3892 #if defined(TARGET_PPC64)
3893 static void gen_rfid(DisasContext *ctx)
3894 {
3895 #if defined(CONFIG_USER_ONLY)
3896 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3897 #else
3898 /* Restore CPU state */
3899 if (unlikely(!ctx->mem_idx)) {
3900 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3901 return;
3902 }
3903 gen_update_cfar(ctx, ctx->nip);
3904 gen_helper_rfid(cpu_env);
3905 gen_sync_exception(ctx);
3906 #endif
3907 }
3908
3909 static void gen_hrfid(DisasContext *ctx)
3910 {
3911 #if defined(CONFIG_USER_ONLY)
3912 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3913 #else
3914 /* Restore CPU state */
3915 if (unlikely(ctx->mem_idx <= 1)) {
3916 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3917 return;
3918 }
3919 gen_helper_hrfid(cpu_env);
3920 gen_sync_exception(ctx);
3921 #endif
3922 }
3923 #endif
3924
3925 /* sc */
3926 #if defined(CONFIG_USER_ONLY)
3927 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3928 #else
3929 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3930 #endif
3931 static void gen_sc(DisasContext *ctx)
3932 {
3933 uint32_t lev;
3934
3935 lev = (ctx->opcode >> 5) & 0x7F;
3936 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3937 }
3938
3939 /*** Trap ***/
3940
3941 /* tw */
3942 static void gen_tw(DisasContext *ctx)
3943 {
3944 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3945 /* Update the nip since this might generate a trap exception */
3946 gen_update_nip(ctx, ctx->nip);
3947 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3948 t0);
3949 tcg_temp_free_i32(t0);
3950 }
3951
3952 /* twi */
3953 static void gen_twi(DisasContext *ctx)
3954 {
3955 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3956 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3957 /* Update the nip since this might generate a trap exception */
3958 gen_update_nip(ctx, ctx->nip);
3959 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3960 tcg_temp_free(t0);
3961 tcg_temp_free_i32(t1);
3962 }
3963
3964 #if defined(TARGET_PPC64)
3965 /* td */
3966 static void gen_td(DisasContext *ctx)
3967 {
3968 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3969 /* Update the nip since this might generate a trap exception */
3970 gen_update_nip(ctx, ctx->nip);
3971 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3972 t0);
3973 tcg_temp_free_i32(t0);
3974 }
3975
3976 /* tdi */
3977 static void gen_tdi(DisasContext *ctx)
3978 {
3979 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3980 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3981 /* Update the nip since this might generate a trap exception */
3982 gen_update_nip(ctx, ctx->nip);
3983 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3984 tcg_temp_free(t0);
3985 tcg_temp_free_i32(t1);
3986 }
3987 #endif
3988
3989 /*** Processor control ***/
3990
3991 static void gen_read_xer(TCGv dst)
3992 {
3993 TCGv t0 = tcg_temp_new();
3994 TCGv t1 = tcg_temp_new();
3995 TCGv t2 = tcg_temp_new();
3996 tcg_gen_mov_tl(dst, cpu_xer);
3997 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3998 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3999 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4000 tcg_gen_or_tl(t0, t0, t1);
4001 tcg_gen_or_tl(dst, dst, t2);
4002 tcg_gen_or_tl(dst, dst, t0);
4003 tcg_temp_free(t0);
4004 tcg_temp_free(t1);
4005 tcg_temp_free(t2);
4006 }
4007
4008 static void gen_write_xer(TCGv src)
4009 {
4010 tcg_gen_andi_tl(cpu_xer, src,
4011 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4012 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4013 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4014 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4015 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4016 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4017 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4018 }
4019
4020 /* mcrxr */
4021 static void gen_mcrxr(DisasContext *ctx)
4022 {
4023 TCGv_i32 t0 = tcg_temp_new_i32();
4024 TCGv_i32 t1 = tcg_temp_new_i32();
4025 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4026
4027 tcg_gen_trunc_tl_i32(t0, cpu_so);
4028 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4029 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4030 tcg_gen_shri_i32(t0, t0, 2);
4031 tcg_gen_shri_i32(t1, t1, 1);
4032 tcg_gen_or_i32(dst, dst, t0);
4033 tcg_gen_or_i32(dst, dst, t1);
4034 tcg_temp_free_i32(t0);
4035 tcg_temp_free_i32(t1);
4036
4037 tcg_gen_movi_tl(cpu_so, 0);
4038 tcg_gen_movi_tl(cpu_ov, 0);
4039 tcg_gen_movi_tl(cpu_ca, 0);
4040 }
4041
4042 /* mfcr mfocrf */
4043 static void gen_mfcr(DisasContext *ctx)
4044 {
4045 uint32_t crm, crn;
4046
4047 if (likely(ctx->opcode & 0x00100000)) {
4048 crm = CRM(ctx->opcode);
4049 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4050 crn = ctz32 (crm);
4051 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4052 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4053 cpu_gpr[rD(ctx->opcode)], crn * 4);
4054 }
4055 } else {
4056 TCGv_i32 t0 = tcg_temp_new_i32();
4057 tcg_gen_mov_i32(t0, cpu_crf[0]);
4058 tcg_gen_shli_i32(t0, t0, 4);
4059 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4060 tcg_gen_shli_i32(t0, t0, 4);
4061 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4062 tcg_gen_shli_i32(t0, t0, 4);
4063 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4064 tcg_gen_shli_i32(t0, t0, 4);
4065 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4066 tcg_gen_shli_i32(t0, t0, 4);
4067 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4068 tcg_gen_shli_i32(t0, t0, 4);
4069 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4070 tcg_gen_shli_i32(t0, t0, 4);
4071 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4072 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4073 tcg_temp_free_i32(t0);
4074 }
4075 }
4076
4077 /* mfmsr */
4078 static void gen_mfmsr(DisasContext *ctx)
4079 {
4080 #if defined(CONFIG_USER_ONLY)
4081 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4082 #else
4083 if (unlikely(!ctx->mem_idx)) {
4084 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4085 return;
4086 }
4087 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4088 #endif
4089 }
4090
4091 static void spr_noaccess(void *opaque, int gprn, int sprn)
4092 {
4093 #if 0
4094 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4095 printf("ERROR: try to access SPR %d !\n", sprn);
4096 #endif
4097 }
4098 #define SPR_NOACCESS (&spr_noaccess)
4099
4100 /* mfspr */
4101 static inline void gen_op_mfspr(DisasContext *ctx)
4102 {
4103 void (*read_cb)(void *opaque, int gprn, int sprn);
4104 uint32_t sprn = SPR(ctx->opcode);
4105
4106 #if !defined(CONFIG_USER_ONLY)
4107 if (ctx->mem_idx == 2)
4108 read_cb = ctx->spr_cb[sprn].hea_read;
4109 else if (ctx->mem_idx)
4110 read_cb = ctx->spr_cb[sprn].oea_read;
4111 else
4112 #endif
4113 read_cb = ctx->spr_cb[sprn].uea_read;
4114 if (likely(read_cb != NULL)) {
4115 if (likely(read_cb != SPR_NOACCESS)) {
4116 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4117 } else {
4118 /* Privilege exception */
4119 /* This is a hack to avoid warnings when running Linux:
4120 * this OS breaks the PowerPC virtualisation model,
4121 * allowing userland application to read the PVR
4122 */
4123 if (sprn != SPR_PVR) {
4124 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4125 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4126 printf("Trying to read privileged spr %d (0x%03x) at "
4127 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4128 }
4129 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4130 }
4131 } else {
4132 /* Not defined */
4133 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4134 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4135 printf("Trying to read invalid spr %d (0x%03x) at "
4136 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4137 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4138 }
4139 }
4140
4141 static void gen_mfspr(DisasContext *ctx)
4142 {
4143 gen_op_mfspr(ctx);
4144 }
4145
4146 /* mftb */
4147 static void gen_mftb(DisasContext *ctx)
4148 {
4149 gen_op_mfspr(ctx);
4150 }
4151
4152 /* mtcrf mtocrf*/
4153 static void gen_mtcrf(DisasContext *ctx)
4154 {
4155 uint32_t crm, crn;
4156
4157 crm = CRM(ctx->opcode);
4158 if (likely((ctx->opcode & 0x00100000))) {
4159 if (crm && ((crm & (crm - 1)) == 0)) {
4160 TCGv_i32 temp = tcg_temp_new_i32();
4161 crn = ctz32 (crm);
4162 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4163 tcg_gen_shri_i32(temp, temp, crn * 4);
4164 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4165 tcg_temp_free_i32(temp);
4166 }
4167 } else {
4168 TCGv_i32 temp = tcg_temp_new_i32();
4169 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4170 for (crn = 0 ; crn < 8 ; crn++) {
4171 if (crm & (1 << crn)) {
4172 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4173 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4174 }
4175 }
4176 tcg_temp_free_i32(temp);
4177 }
4178 }
4179
4180 /* mtmsr */
4181 #if defined(TARGET_PPC64)
4182 static void gen_mtmsrd(DisasContext *ctx)
4183 {
4184 #if defined(CONFIG_USER_ONLY)
4185 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4186 #else
4187 if (unlikely(!ctx->mem_idx)) {
4188 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4189 return;
4190 }
4191 if (ctx->opcode & 0x00010000) {
4192 /* Special form that does not need any synchronisation */
4193 TCGv t0 = tcg_temp_new();
4194 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4195 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4196 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4197 tcg_temp_free(t0);
4198 } else {
4199 /* XXX: we need to update nip before the store
4200 * if we enter power saving mode, we will exit the loop
4201 * directly from ppc_store_msr
4202 */
4203 gen_update_nip(ctx, ctx->nip);
4204 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4205 /* Must stop the translation as machine state (may have) changed */
4206 /* Note that mtmsr is not always defined as context-synchronizing */
4207 gen_stop_exception(ctx);
4208 }
4209 #endif
4210 }
4211 #endif
4212
4213 static void gen_mtmsr(DisasContext *ctx)
4214 {
4215 #if defined(CONFIG_USER_ONLY)
4216 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4217 #else
4218 if (unlikely(!ctx->mem_idx)) {
4219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4220 return;
4221 }
4222 if (ctx->opcode & 0x00010000) {
4223 /* Special form that does not need any synchronisation */
4224 TCGv t0 = tcg_temp_new();
4225 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4226 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4227 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4228 tcg_temp_free(t0);
4229 } else {
4230 TCGv msr = tcg_temp_new();
4231
4232 /* XXX: we need to update nip before the store
4233 * if we enter power saving mode, we will exit the loop
4234 * directly from ppc_store_msr
4235 */
4236 gen_update_nip(ctx, ctx->nip);
4237 #if defined(TARGET_PPC64)
4238 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4239 #else
4240 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4241 #endif
4242 gen_helper_store_msr(cpu_env, msr);
4243 /* Must stop the translation as machine state (may have) changed */
4244 /* Note that mtmsr is not always defined as context-synchronizing */
4245 gen_stop_exception(ctx);
4246 }
4247 #endif
4248 }
4249
4250 /* mtspr */
4251 static void gen_mtspr(DisasContext *ctx)
4252 {
4253 void (*write_cb)(void *opaque, int sprn, int gprn);
4254 uint32_t sprn = SPR(ctx->opcode);
4255
4256 #if !defined(CONFIG_USER_ONLY)
4257 if (ctx->mem_idx == 2)
4258 write_cb = ctx->spr_cb[sprn].hea_write;
4259 else if (ctx->mem_idx)
4260 write_cb = ctx->spr_cb[sprn].oea_write;
4261 else
4262 #endif
4263 write_cb = ctx->spr_cb[sprn].uea_write;
4264 if (likely(write_cb != NULL)) {
4265 if (likely(write_cb != SPR_NOACCESS)) {
4266 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4267 } else {
4268 /* Privilege exception */
4269 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4270 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4271 printf("Trying to write privileged spr %d (0x%03x) at "
4272 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4273 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4274 }
4275 } else {
4276 /* Not defined */
4277 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4278 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4279 printf("Trying to write invalid spr %d (0x%03x) at "
4280 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4281 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4282 }
4283 }
4284
4285 /*** Cache management ***/
4286
4287 /* dcbf */
4288 static void gen_dcbf(DisasContext *ctx)
4289 {
4290 /* XXX: specification says this is treated as a load by the MMU */
4291 TCGv t0;
4292 gen_set_access_type(ctx, ACCESS_CACHE);
4293 t0 = tcg_temp_new();
4294 gen_addr_reg_index(ctx, t0);
4295 gen_qemu_ld8u(ctx, t0, t0);
4296 tcg_temp_free(t0);
4297 }
4298
4299 /* dcbi (Supervisor only) */
4300 static void gen_dcbi(DisasContext *ctx)
4301 {
4302 #if defined(CONFIG_USER_ONLY)
4303 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4304 #else
4305 TCGv EA, val;
4306 if (unlikely(!ctx->mem_idx)) {
4307 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4308 return;
4309 }
4310 EA = tcg_temp_new();
4311 gen_set_access_type(ctx, ACCESS_CACHE);
4312 gen_addr_reg_index(ctx, EA);
4313 val = tcg_temp_new();
4314 /* XXX: specification says this should be treated as a store by the MMU */
4315 gen_qemu_ld8u(ctx, val, EA);
4316 gen_qemu_st8(ctx, val, EA);
4317 tcg_temp_free(val);
4318 tcg_temp_free(EA);
4319 #endif
4320 }
4321
4322 /* dcdst */
4323 static void gen_dcbst(DisasContext *ctx)
4324 {
4325 /* XXX: specification say this is treated as a load by the MMU */
4326 TCGv t0;
4327 gen_set_access_type(ctx, ACCESS_CACHE);
4328 t0 = tcg_temp_new();
4329 gen_addr_reg_index(ctx, t0);
4330 gen_qemu_ld8u(ctx, t0, t0);
4331 tcg_temp_free(t0);
4332 }
4333
4334 /* dcbt */
4335 static void gen_dcbt(DisasContext *ctx)
4336 {
4337 /* interpreted as no-op */
4338 /* XXX: specification say this is treated as a load by the MMU
4339 * but does not generate any exception
4340 */
4341 }
4342
4343 /* dcbtst */
4344 static void gen_dcbtst(DisasContext *ctx)
4345 {
4346 /* interpreted as no-op */
4347 /* XXX: specification say this is treated as a load by the MMU
4348 * but does not generate any exception
4349 */
4350 }
4351
4352 /* dcbz */
4353 static void gen_dcbz(DisasContext *ctx)
4354 {
4355 TCGv tcgv_addr;
4356 TCGv_i32 tcgv_is_dcbzl;
4357 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4358
4359 gen_set_access_type(ctx, ACCESS_CACHE);
4360 /* NIP cannot be restored if the memory exception comes from an helper */
4361 gen_update_nip(ctx, ctx->nip - 4);
4362 tcgv_addr = tcg_temp_new();
4363 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4364
4365 gen_addr_reg_index(ctx, tcgv_addr);
4366 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4367
4368 tcg_temp_free(tcgv_addr);
4369 tcg_temp_free_i32(tcgv_is_dcbzl);
4370 }
4371
4372 /* dst / dstt */
4373 static void gen_dst(DisasContext *ctx)
4374 {
4375 if (rA(ctx->opcode) == 0) {
4376 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4377 } else {
4378 /* interpreted as no-op */
4379 }
4380 }
4381
4382 /* dstst /dststt */
4383 static void gen_dstst(DisasContext *ctx)
4384 {
4385 if (rA(ctx->opcode) == 0) {
4386 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4387 } else {
4388 /* interpreted as no-op */
4389 }
4390
4391 }
4392
4393 /* dss / dssall */
4394 static void gen_dss(DisasContext *ctx)
4395 {
4396 /* interpreted as no-op */
4397 }
4398
4399 /* icbi */
4400 static void gen_icbi(DisasContext *ctx)
4401 {
4402 TCGv t0;
4403 gen_set_access_type(ctx, ACCESS_CACHE);
4404 /* NIP cannot be restored if the memory exception comes from an helper */
4405 gen_update_nip(ctx, ctx->nip - 4);
4406 t0 = tcg_temp_new();
4407 gen_addr_reg_index(ctx, t0);
4408 gen_helper_icbi(cpu_env, t0);
4409 tcg_temp_free(t0);
4410 }
4411
4412 /* Optional: */
4413 /* dcba */
4414 static void gen_dcba(DisasContext *ctx)
4415 {
4416 /* interpreted as no-op */
4417 /* XXX: specification say this is treated as a store by the MMU
4418 * but does not generate any exception
4419 */
4420 }
4421
4422 /*** Segment register manipulation ***/
4423 /* Supervisor only: */
4424
4425 /* mfsr */
4426 static void gen_mfsr(DisasContext *ctx)
4427 {
4428 #if defined(CONFIG_USER_ONLY)
4429 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4430 #else
4431 TCGv t0;
4432 if (unlikely(!ctx->mem_idx)) {
4433 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4434 return;
4435 }
4436 t0 = tcg_const_tl(SR(ctx->opcode));
4437 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4438 tcg_temp_free(t0);
4439 #endif
4440 }
4441
4442 /* mfsrin */
4443 static void gen_mfsrin(DisasContext *ctx)
4444 {
4445 #if defined(CONFIG_USER_ONLY)
4446 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4447 #else
4448 TCGv t0;
4449 if (unlikely(!ctx->mem_idx)) {
4450 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4451 return;
4452 }
4453 t0 = tcg_temp_new();
4454 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4455 tcg_gen_andi_tl(t0, t0, 0xF);
4456 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4457 tcg_temp_free(t0);
4458 #endif
4459 }
4460
4461 /* mtsr */
4462 static void gen_mtsr(DisasContext *ctx)
4463 {
4464 #if defined(CONFIG_USER_ONLY)
4465 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4466 #else
4467 TCGv t0;
4468 if (unlikely(!ctx->mem_idx)) {
4469 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4470 return;
4471 }
4472 t0 = tcg_const_tl(SR(ctx->opcode));
4473 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4474 tcg_temp_free(t0);
4475 #endif
4476 }
4477
4478 /* mtsrin */
4479 static void gen_mtsrin(DisasContext *ctx)
4480 {
4481 #if defined(CONFIG_USER_ONLY)
4482 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4483 #else
4484 TCGv t0;
4485 if (unlikely(!ctx->mem_idx)) {
4486 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4487 return;
4488 }
4489 t0 = tcg_temp_new();
4490 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4491 tcg_gen_andi_tl(t0, t0, 0xF);
4492 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4493 tcg_temp_free(t0);
4494 #endif
4495 }
4496
4497 #if defined(TARGET_PPC64)
4498 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4499
4500 /* mfsr */
4501 static void gen_mfsr_64b(DisasContext *ctx)
4502 {
4503 #if defined(CONFIG_USER_ONLY)
4504 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4505 #else
4506 TCGv t0;
4507 if (unlikely(!ctx->mem_idx)) {
4508 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4509 return;
4510 }
4511 t0 = tcg_const_tl(SR(ctx->opcode));
4512 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4513 tcg_temp_free(t0);
4514 #endif
4515 }
4516
4517 /* mfsrin */
4518 static void gen_mfsrin_64b(DisasContext *ctx)
4519 {
4520 #if defined(CONFIG_USER_ONLY)
4521 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4522 #else
4523 TCGv t0;
4524 if (unlikely(!ctx->mem_idx)) {
4525 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4526 return;
4527 }
4528 t0 = tcg_temp_new();
4529 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4530 tcg_gen_andi_tl(t0, t0, 0xF);
4531 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4532 tcg_temp_free(t0);
4533 #endif
4534 }
4535
4536 /* mtsr */
4537 static void gen_mtsr_64b(DisasContext *ctx)
4538 {
4539 #if defined(CONFIG_USER_ONLY)
4540 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4541 #else
4542 TCGv t0;
4543 if (unlikely(!ctx->mem_idx)) {
4544 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4545 return;
4546 }
4547 t0 = tcg_const_tl(SR(ctx->opcode));
4548 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4549 tcg_temp_free(t0);
4550 #endif
4551 }
4552
4553 /* mtsrin */
4554 static void gen_mtsrin_64b(DisasContext *ctx)
4555 {
4556 #if defined(CONFIG_USER_ONLY)
4557 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4558 #else
4559 TCGv t0;
4560 if (unlikely(!ctx->mem_idx)) {
4561 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4562 return;
4563 }
4564 t0 = tcg_temp_new();
4565 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4566 tcg_gen_andi_tl(t0, t0, 0xF);
4567 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4568 tcg_temp_free(t0);
4569 #endif
4570 }
4571
4572 /* slbmte */
4573 static void gen_slbmte(DisasContext *ctx)
4574 {
4575 #if defined(CONFIG_USER_ONLY)
4576 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4577 #else
4578 if (unlikely(!ctx->mem_idx)) {
4579 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4580 return;
4581 }
4582 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4583 cpu_gpr[rS(ctx->opcode)]);
4584 #endif
4585 }
4586
4587 static void gen_slbmfee(DisasContext *ctx)
4588 {
4589 #if defined(CONFIG_USER_ONLY)
4590 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4591 #else
4592 if (unlikely(!ctx->mem_idx)) {
4593 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4594 return;
4595 }
4596 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4597 cpu_gpr[rB(ctx->opcode)]);
4598 #endif
4599 }
4600
4601 static void gen_slbmfev(DisasContext *ctx)
4602 {
4603 #if defined(CONFIG_USER_ONLY)
4604 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4605 #else
4606 if (unlikely(!ctx->mem_idx)) {
4607 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4608 return;
4609 }
4610 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4611 cpu_gpr[rB(ctx->opcode)]);
4612 #endif
4613 }
4614 #endif /* defined(TARGET_PPC64) */
4615
4616 /*** Lookaside buffer management ***/
4617 /* Optional & mem_idx only: */
4618
4619 /* tlbia */
4620 static void gen_tlbia(DisasContext *ctx)
4621 {
4622 #if defined(CONFIG_USER_ONLY)
4623 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4624 #else
4625 if (unlikely(!ctx->mem_idx)) {
4626 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4627 return;
4628 }
4629 gen_helper_tlbia(cpu_env);
4630 #endif
4631 }
4632
4633 /* tlbiel */
4634 static void gen_tlbiel(DisasContext *ctx)
4635 {
4636 #if defined(CONFIG_USER_ONLY)
4637 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4638 #else
4639 if (unlikely(!ctx->mem_idx)) {
4640 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4641 return;
4642 }
4643 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4644 #endif
4645 }
4646
4647 /* tlbie */
4648 static void gen_tlbie(DisasContext *ctx)
4649 {
4650 #if defined(CONFIG_USER_ONLY)
4651 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4652 #else
4653 if (unlikely(!ctx->mem_idx)) {
4654 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4655 return;
4656 }
4657 if (NARROW_MODE(ctx)) {
4658 TCGv t0 = tcg_temp_new();
4659 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4660 gen_helper_tlbie(cpu_env, t0);
4661 tcg_temp_free(t0);
4662 } else {
4663 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4664 }
4665 #endif
4666 }
4667
4668 /* tlbsync */
4669 static void gen_tlbsync(DisasContext *ctx)
4670 {
4671 #if defined(CONFIG_USER_ONLY)
4672 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4673 #else
4674 if (unlikely(!ctx->mem_idx)) {
4675 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4676 return;
4677 }
4678 /* This has no effect: it should ensure that all previous
4679 * tlbie have completed
4680 */
4681 gen_stop_exception(ctx);
4682 #endif
4683 }
4684
4685 #if defined(TARGET_PPC64)
4686 /* slbia */
4687 static void gen_slbia(DisasContext *ctx)
4688 {
4689 #if defined(CONFIG_USER_ONLY)
4690 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4691 #else
4692 if (unlikely(!ctx->mem_idx)) {
4693 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4694 return;
4695 }
4696 gen_helper_slbia(cpu_env);
4697 #endif
4698 }
4699
4700 /* slbie */
4701 static void gen_slbie(DisasContext *ctx)
4702 {
4703 #if defined(CONFIG_USER_ONLY)
4704 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4705 #else
4706 if (unlikely(!ctx->mem_idx)) {
4707 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4708 return;
4709 }
4710 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4711 #endif
4712 }
4713 #endif
4714
4715 /*** External control ***/
4716 /* Optional: */
4717
4718 /* eciwx */
4719 static void gen_eciwx(DisasContext *ctx)
4720 {
4721 TCGv t0;
4722 /* Should check EAR[E] ! */
4723 gen_set_access_type(ctx, ACCESS_EXT);
4724 t0 = tcg_temp_new();
4725 gen_addr_reg_index(ctx, t0);
4726 gen_check_align(ctx, t0, 0x03);
4727 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4728 tcg_temp_free(t0);
4729 }
4730
4731 /* ecowx */
4732 static void gen_ecowx(DisasContext *ctx)
4733 {
4734 TCGv t0;
4735 /* Should check EAR[E] ! */
4736 gen_set_access_type(ctx, ACCESS_EXT);
4737 t0 = tcg_temp_new();
4738 gen_addr_reg_index(ctx, t0);
4739 gen_check_align(ctx, t0, 0x03);
4740 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4741 tcg_temp_free(t0);
4742 }
4743
4744 /* PowerPC 601 specific instructions */
4745
4746 /* abs - abs. */
4747 static void gen_abs(DisasContext *ctx)
4748 {
4749 int l1 = gen_new_label();
4750 int l2 = gen_new_label();
4751 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4752 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4753 tcg_gen_br(l2);
4754 gen_set_label(l1);
4755 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4756 gen_set_label(l2);
4757 if (unlikely(Rc(ctx->opcode) != 0))
4758 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4759 }
4760
4761 /* abso - abso. */
4762 static void gen_abso(DisasContext *ctx)
4763 {
4764 int l1 = gen_new_label();
4765 int l2 = gen_new_label();
4766 int l3 = gen_new_label();
4767 /* Start with XER OV disabled, the most likely case */
4768 tcg_gen_movi_tl(cpu_ov, 0);
4769 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4770 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4771 tcg_gen_movi_tl(cpu_ov, 1);
4772 tcg_gen_movi_tl(cpu_so, 1);
4773 tcg_gen_br(l2);
4774 gen_set_label(l1);
4775 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4776 tcg_gen_br(l3);
4777 gen_set_label(l2);
4778 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4779 gen_set_label(l3);
4780 if (unlikely(Rc(ctx->opcode) != 0))
4781 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4782 }
4783
4784 /* clcs */
4785 static void gen_clcs(DisasContext *ctx)
4786 {
4787 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4788 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4789 tcg_temp_free_i32(t0);
4790 /* Rc=1 sets CR0 to an undefined state */
4791 }
4792
4793 /* div - div. */
4794 static void gen_div(DisasContext *ctx)
4795 {
4796 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4797 cpu_gpr[rB(ctx->opcode)]);
4798 if (unlikely(Rc(ctx->opcode) != 0))
4799 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4800 }
4801
4802 /* divo - divo. */
4803 static void gen_divo(DisasContext *ctx)
4804 {
4805 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4806 cpu_gpr[rB(ctx->opcode)]);
4807 if (unlikely(Rc(ctx->opcode) != 0))
4808 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4809 }
4810
4811 /* divs - divs. */
4812 static void gen_divs(DisasContext *ctx)
4813 {
4814 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4815 cpu_gpr[rB(ctx->opcode)]);
4816 if (unlikely(Rc(ctx->opcode) != 0))
4817 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4818 }
4819
4820 /* divso - divso. */
4821 static void gen_divso(DisasContext *ctx)
4822 {
4823 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4824 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4825 if (unlikely(Rc(ctx->opcode) != 0))
4826 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4827 }
4828
4829 /* doz - doz. */
4830 static void gen_doz(DisasContext *ctx)
4831 {
4832 int l1 = gen_new_label();
4833 int l2 = gen_new_label();
4834 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4835 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4836 tcg_gen_br(l2);
4837 gen_set_label(l1);
4838 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4839 gen_set_label(l2);
4840 if (unlikely(Rc(ctx->opcode) != 0))
4841 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4842 }
4843
4844 /* dozo - dozo. */
4845 static void gen_dozo(DisasContext *ctx)
4846 {
4847 int l1 = gen_new_label();
4848 int l2 = gen_new_label();
4849 TCGv t0 = tcg_temp_new();
4850 TCGv t1 = tcg_temp_new();
4851 TCGv t2 = tcg_temp_new();
4852 /* Start with XER OV disabled, the most likely case */
4853 tcg_gen_movi_tl(cpu_ov, 0);
4854 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4855 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4856 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4857 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4858 tcg_gen_andc_tl(t1, t1, t2);
4859 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4860 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4861 tcg_gen_movi_tl(cpu_ov, 1);
4862 tcg_gen_movi_tl(cpu_so, 1);
4863 tcg_gen_br(l2);
4864 gen_set_label(l1);
4865 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4866 gen_set_label(l2);
4867 tcg_temp_free(t0);
4868 tcg_temp_free(t1);
4869 tcg_temp_free(t2);
4870 if (unlikely(Rc(ctx->opcode) != 0))
4871 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4872 }
4873
4874 /* dozi */
4875 static void gen_dozi(DisasContext *ctx)
4876 {
4877 target_long simm = SIMM(ctx->opcode);
4878 int l1 = gen_new_label();
4879 int l2 = gen_new_label();
4880 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4881 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4882 tcg_gen_br(l2);
4883 gen_set_label(l1);
4884 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4885 gen_set_label(l2);
4886 if (unlikely(Rc(ctx->opcode) != 0))
4887 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4888 }
4889
4890 /* lscbx - lscbx. */
4891 static void gen_lscbx(DisasContext *ctx)
4892 {
4893 TCGv t0 = tcg_temp_new();
4894 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4895 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4896 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4897
4898 gen_addr_reg_index(ctx, t0);
4899 /* NIP cannot be restored if the memory exception comes from an helper */
4900 gen_update_nip(ctx, ctx->nip - 4);
4901 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4902 tcg_temp_free_i32(t1);
4903 tcg_temp_free_i32(t2);
4904 tcg_temp_free_i32(t3);
4905 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4906 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4907 if (unlikely(Rc(ctx->opcode) != 0))
4908 gen_set_Rc0(ctx, t0);
4909 tcg_temp_free(t0);
4910 }
4911
4912 /* maskg - maskg. */
4913 static void gen_maskg(DisasContext *ctx)
4914 {
4915 int l1 = gen_new_label();
4916 TCGv t0 = tcg_temp_new();
4917 TCGv t1 = tcg_temp_new();
4918 TCGv t2 = tcg_temp_new();
4919 TCGv t3 = tcg_temp_new();
4920 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4921 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4922 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4923 tcg_gen_addi_tl(t2, t0, 1);
4924 tcg_gen_shr_tl(t2, t3, t2);
4925 tcg_gen_shr_tl(t3, t3, t1);
4926 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4927 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4928 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4929 gen_set_label(l1);
4930 tcg_temp_free(t0);
4931 tcg_temp_free(t1);
4932 tcg_temp_free(t2);
4933 tcg_temp_free(t3);
4934 if (unlikely(Rc(ctx->opcode) != 0))
4935 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4936 }
4937
4938 /* maskir - maskir. */
4939 static void gen_maskir(DisasContext *ctx)
4940 {
4941 TCGv t0 = tcg_temp_new();
4942 TCGv t1 = tcg_temp_new();
4943 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4944 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4945 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4946 tcg_temp_free(t0);
4947 tcg_temp_free(t1);
4948 if (unlikely(Rc(ctx->opcode) != 0))
4949 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4950 }
4951
4952 /* mul - mul. */
4953 static void gen_mul(DisasContext *ctx)
4954 {
4955 TCGv_i64 t0 = tcg_temp_new_i64();
4956 TCGv_i64 t1 = tcg_temp_new_i64();
4957 TCGv t2 = tcg_temp_new();
4958 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4959 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4960 tcg_gen_mul_i64(t0, t0, t1);
4961 tcg_gen_trunc_i64_tl(t2, t0);
4962 gen_store_spr(SPR_MQ, t2);
4963 tcg_gen_shri_i64(t1, t0, 32);
4964 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4965 tcg_temp_free_i64(t0);
4966 tcg_temp_free_i64(t1);
4967 tcg_temp_free(t2);
4968 if (unlikely(Rc(ctx->opcode) != 0))
4969 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4970 }
4971
4972 /* mulo - mulo. */
4973 static void gen_mulo(DisasContext *ctx)
4974 {
4975 int l1 = gen_new_label();
4976 TCGv_i64 t0 = tcg_temp_new_i64();
4977 TCGv_i64 t1 = tcg_temp_new_i64();
4978 TCGv t2 = tcg_temp_new();
4979 /* Start with XER OV disabled, the most likely case */
4980 tcg_gen_movi_tl(cpu_ov, 0);
4981 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4982 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4983 tcg_gen_mul_i64(t0, t0, t1);
4984 tcg_gen_trunc_i64_tl(t2, t0);
4985 gen_store_spr(SPR_MQ, t2);
4986 tcg_gen_shri_i64(t1, t0, 32);
4987 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4988 tcg_gen_ext32s_i64(t1, t0);
4989 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4990 tcg_gen_movi_tl(cpu_ov, 1);
4991 tcg_gen_movi_tl(cpu_so, 1);
4992 gen_set_label(l1);
4993 tcg_temp_free_i64(t0);
4994 tcg_temp_free_i64(t1);
4995 tcg_temp_free(t2);
4996 if (unlikely(Rc(ctx->opcode) != 0))
4997 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4998 }
4999
5000 /* nabs - nabs. */
5001 static void gen_nabs(DisasContext *ctx)
5002 {
5003 int l1 = gen_new_label();
5004 int l2 = gen_new_label();
5005 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5006 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5007 tcg_gen_br(l2);
5008 gen_set_label(l1);
5009 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5010 gen_set_label(l2);
5011 if (unlikely(Rc(ctx->opcode) != 0))
5012 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5013 }
5014
5015 /* nabso - nabso. */
5016 static void gen_nabso(DisasContext *ctx)
5017 {
5018 int l1 = gen_new_label();
5019 int l2 = gen_new_label();
5020 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5021 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5022 tcg_gen_br(l2);
5023 gen_set_label(l1);
5024 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5025 gen_set_label(l2);
5026 /* nabs never overflows */
5027 tcg_gen_movi_tl(cpu_ov, 0);
5028 if (unlikely(Rc(ctx->opcode) != 0))
5029 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5030 }
5031
5032 /* rlmi - rlmi. */
5033 static void gen_rlmi(DisasContext *ctx)
5034 {
5035 uint32_t mb = MB(ctx->opcode);
5036 uint32_t me = ME(ctx->opcode);
5037 TCGv t0 = tcg_temp_new();
5038 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5039 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5040 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5041 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5042 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5043 tcg_temp_free(t0);
5044 if (unlikely(Rc(ctx->opcode) != 0))
5045 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5046 }
5047
5048 /* rrib - rrib. */
5049 static void gen_rrib(DisasContext *ctx)
5050 {
5051 TCGv t0 = tcg_temp_new();
5052 TCGv t1 = tcg_temp_new();
5053 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5054 tcg_gen_movi_tl(t1, 0x80000000);
5055 tcg_gen_shr_tl(t1, t1, t0);
5056 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5057 tcg_gen_and_tl(t0, t0, t1);
5058 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5059 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5060 tcg_temp_free(t0);
5061 tcg_temp_free(t1);
5062 if (unlikely(Rc(ctx->opcode) != 0))
5063 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5064 }
5065
5066 /* sle - sle. */
5067 static void gen_sle(DisasContext *ctx)
5068 {
5069 TCGv t0 = tcg_temp_new();
5070 TCGv t1 = tcg_temp_new();
5071 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5072 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5073 tcg_gen_subfi_tl(t1, 32, t1);
5074 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5075 tcg_gen_or_tl(t1, t0, t1);
5076 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5077 gen_store_spr(SPR_MQ, t1);
5078 tcg_temp_free(t0);
5079 tcg_temp_free(t1);
5080 if (unlikely(Rc(ctx->opcode) != 0))
5081 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5082 }
5083
5084 /* sleq - sleq. */
5085 static void gen_sleq(DisasContext *ctx)
5086 {
5087 TCGv t0 = tcg_temp_new();
5088 TCGv t1 = tcg_temp_new();
5089 TCGv t2 = tcg_temp_new();
5090 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5091 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5092 tcg_gen_shl_tl(t2, t2, t0);
5093 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5094 gen_load_spr(t1, SPR_MQ);
5095 gen_store_spr(SPR_MQ, t0);
5096 tcg_gen_and_tl(t0, t0, t2);
5097 tcg_gen_andc_tl(t1, t1, t2);
5098 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5099 tcg_temp_free(t0);
5100 tcg_temp_free(t1);
5101 tcg_temp_free(t2);
5102 if (unlikely(Rc(ctx->opcode) != 0))
5103 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5104 }
5105
5106 /* sliq - sliq. */
5107 static void gen_sliq(DisasContext *ctx)
5108 {
5109 int sh = SH(ctx->opcode);
5110 TCGv t0 = tcg_temp_new();
5111 TCGv t1 = tcg_temp_new();
5112 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5113 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5114 tcg_gen_or_tl(t1, t0, t1);
5115 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5116 gen_store_spr(SPR_MQ, t1);
5117 tcg_temp_free(t0);
5118 tcg_temp_free(t1);
5119 if (unlikely(Rc(ctx->opcode) != 0))
5120 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5121 }
5122
5123 /* slliq - slliq. */
5124 static void gen_slliq(DisasContext *ctx)
5125 {
5126 int sh = SH(ctx->opcode);
5127 TCGv t0 = tcg_temp_new();
5128 TCGv t1 = tcg_temp_new();
5129 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5130 gen_load_spr(t1, SPR_MQ);
5131 gen_store_spr(SPR_MQ, t0);
5132 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5133 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5134 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5135 tcg_temp_free(t0);
5136 tcg_temp_free(t1);
5137 if (unlikely(Rc(ctx->opcode) != 0))
5138 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5139 }
5140
5141 /* sllq - sllq. */
5142 static void gen_sllq(DisasContext *ctx)
5143 {
5144 int l1 = gen_new_label();
5145 int l2 = gen_new_label();
5146 TCGv t0 = tcg_temp_local_new();
5147 TCGv t1 = tcg_temp_local_new();
5148 TCGv t2 = tcg_temp_local_new();
5149 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5150 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5151 tcg_gen_shl_tl(t1, t1, t2);
5152 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5153 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5154 gen_load_spr(t0, SPR_MQ);
5155 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5156 tcg_gen_br(l2);
5157 gen_set_label(l1);
5158 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5159 gen_load_spr(t2, SPR_MQ);
5160 tcg_gen_andc_tl(t1, t2, t1);
5161 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5162 gen_set_label(l2);
5163 tcg_temp_free(t0);
5164 tcg_temp_free(t1);
5165 tcg_temp_free(t2);
5166 if (unlikely(Rc(ctx->opcode) != 0))
5167 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5168 }
5169
5170 /* slq - slq. */
5171 static void gen_slq(DisasContext *ctx)
5172 {
5173 int l1 = gen_new_label();
5174 TCGv t0 = tcg_temp_new();
5175 TCGv t1 = tcg_temp_new();
5176 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5177 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5178 tcg_gen_subfi_tl(t1, 32, t1);
5179 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5180 tcg_gen_or_tl(t1, t0, t1);
5181 gen_store_spr(SPR_MQ, t1);
5182 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5183 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5184 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5185 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5186 gen_set_label(l1);
5187 tcg_temp_free(t0);
5188 tcg_temp_free(t1);
5189 if (unlikely(Rc(ctx->opcode) != 0))
5190 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5191 }
5192
5193 /* sraiq - sraiq. */
5194 static void gen_sraiq(DisasContext *ctx)
5195 {
5196 int sh = SH(ctx->opcode);
5197 int l1 = gen_new_label();
5198 TCGv t0 = tcg_temp_new();
5199 TCGv t1 = tcg_temp_new();
5200 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5201 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5202 tcg_gen_or_tl(t0, t0, t1);
5203 gen_store_spr(SPR_MQ, t0);
5204 tcg_gen_movi_tl(cpu_ca, 0);
5205 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5206 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5207 tcg_gen_movi_tl(cpu_ca, 1);
5208 gen_set_label(l1);
5209 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5210 tcg_temp_free(t0);
5211 tcg_temp_free(t1);
5212 if (unlikely(Rc(ctx->opcode) != 0))
5213 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5214 }
5215
5216 /* sraq - sraq. */
5217 static void gen_sraq(DisasContext *ctx)
5218 {
5219 int l1 = gen_new_label();
5220 int l2 = gen_new_label();
5221 TCGv t0 = tcg_temp_new();
5222 TCGv t1 = tcg_temp_local_new();
5223 TCGv t2 = tcg_temp_local_new();
5224 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5225 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5226 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5227 tcg_gen_subfi_tl(t2, 32, t2);
5228 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5229 tcg_gen_or_tl(t0, t0, t2);
5230 gen_store_spr(SPR_MQ, t0);
5231 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5232 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5233 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5234 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5235 gen_set_label(l1);
5236 tcg_temp_free(t0);
5237 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5238 tcg_gen_movi_tl(cpu_ca, 0);
5239 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5240 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5241 tcg_gen_movi_tl(cpu_ca, 1);
5242 gen_set_label(l2);
5243 tcg_temp_free(t1);
5244 tcg_temp_free(t2);
5245 if (unlikely(Rc(ctx->opcode) != 0))
5246 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5247 }
5248
5249 /* sre - sre. */
5250 static void gen_sre(DisasContext *ctx)
5251 {
5252 TCGv t0 = tcg_temp_new();
5253 TCGv t1 = tcg_temp_new();
5254 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5255 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5256 tcg_gen_subfi_tl(t1, 32, t1);
5257 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5258 tcg_gen_or_tl(t1, t0, t1);
5259 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5260 gen_store_spr(SPR_MQ, t1);
5261 tcg_temp_free(t0);
5262 tcg_temp_free(t1);
5263 if (unlikely(Rc(ctx->opcode) != 0))
5264 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5265 }
5266
5267 /* srea - srea. */
5268 static void gen_srea(DisasContext *ctx)
5269 {
5270 TCGv t0 = tcg_temp_new();
5271 TCGv t1 = tcg_temp_new();
5272 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5273 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5274 gen_store_spr(SPR_MQ, t0);
5275 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5276 tcg_temp_free(t0);
5277 tcg_temp_free(t1);
5278 if (unlikely(Rc(ctx->opcode) != 0))
5279 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5280 }
5281
5282 /* sreq */
5283 static void gen_sreq(DisasContext *ctx)
5284 {
5285 TCGv t0 = tcg_temp_new();
5286 TCGv t1 = tcg_temp_new();
5287 TCGv t2 = tcg_temp_new();
5288 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5289 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5290 tcg_gen_shr_tl(t1, t1, t0);
5291 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5292 gen_load_spr(t2, SPR_MQ);
5293 gen_store_spr(SPR_MQ, t0);
5294 tcg_gen_and_tl(t0, t0, t1);
5295 tcg_gen_andc_tl(t2, t2, t1);
5296 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5297 tcg_temp_free(t0);
5298 tcg_temp_free(t1);
5299 tcg_temp_free(t2);
5300 if (unlikely(Rc(ctx->opcode) != 0))
5301 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5302 }
5303
5304 /* sriq */
5305 static void gen_sriq(DisasContext *ctx)
5306 {
5307 int sh = SH(ctx->opcode);
5308 TCGv t0 = tcg_temp_new();
5309 TCGv t1 = tcg_temp_new();
5310 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5311 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5312 tcg_gen_or_tl(t1, t0, t1);
5313 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5314 gen_store_spr(SPR_MQ, t1);
5315 tcg_temp_free(t0);
5316 tcg_temp_free(t1);
5317 if (unlikely(Rc(ctx->opcode) != 0))
5318 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5319 }
5320
5321 /* srliq */
5322 static void gen_srliq(DisasContext *ctx)
5323 {
5324 int sh = SH(ctx->opcode);
5325 TCGv t0 = tcg_temp_new();
5326 TCGv t1 = tcg_temp_new();
5327 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5328 gen_load_spr(t1, SPR_MQ);
5329 gen_store_spr(SPR_MQ, t0);
5330 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5331 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5332 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5333 tcg_temp_free(t0);
5334 tcg_temp_free(t1);
5335 if (unlikely(Rc(ctx->opcode) != 0))
5336 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5337 }
5338
5339 /* srlq */
5340 static void gen_srlq(DisasContext *ctx)
5341 {
5342 int l1 = gen_new_label();
5343 int l2 = gen_new_label();
5344 TCGv t0 = tcg_temp_local_new();
5345 TCGv t1 = tcg_temp_local_new();
5346 TCGv t2 = tcg_temp_local_new();
5347 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5348 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5349 tcg_gen_shr_tl(t2, t1, t2);
5350 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5351 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5352 gen_load_spr(t0, SPR_MQ);
5353 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5354 tcg_gen_br(l2);
5355 gen_set_label(l1);
5356 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5357 tcg_gen_and_tl(t0, t0, t2);
5358 gen_load_spr(t1, SPR_MQ);
5359 tcg_gen_andc_tl(t1, t1, t2);
5360 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5361 gen_set_label(l2);
5362 tcg_temp_free(t0);
5363 tcg_temp_free(t1);
5364 tcg_temp_free(t2);
5365 if (unlikely(Rc(ctx->opcode) != 0))
5366 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5367 }
5368
5369 /* srq */
5370 static void gen_srq(DisasContext *ctx)
5371 {
5372 int l1 = gen_new_label();
5373 TCGv t0 = tcg_temp_new();
5374 TCGv t1 = tcg_temp_new();
5375 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5376 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5377 tcg_gen_subfi_tl(t1, 32, t1);
5378 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5379 tcg_gen_or_tl(t1, t0, t1);
5380 gen_store_spr(SPR_MQ, t1);
5381 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5382 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5383 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5384 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5385 gen_set_label(l1);
5386 tcg_temp_free(t0);
5387 tcg_temp_free(t1);
5388 if (unlikely(Rc(ctx->opcode) != 0))
5389 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5390 }
5391
5392 /* PowerPC 602 specific instructions */
5393
5394 /* dsa */
5395 static void gen_dsa(DisasContext *ctx)
5396 {
5397 /* XXX: TODO */
5398 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5399 }
5400
5401 /* esa */
5402 static void gen_esa(DisasContext *ctx)
5403 {
5404 /* XXX: TODO */
5405 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5406 }
5407
5408 /* mfrom */
5409 static void gen_mfrom(DisasContext *ctx)
5410 {
5411 #if defined(CONFIG_USER_ONLY)
5412 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5413 #else
5414 if (unlikely(!ctx->mem_idx)) {
5415 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5416 return;
5417 }
5418 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5419 #endif
5420 }
5421
5422 /* 602 - 603 - G2 TLB management */
5423
5424 /* tlbld */
5425 static void gen_tlbld_6xx(DisasContext *ctx)
5426 {
5427 #if defined(CONFIG_USER_ONLY)
5428 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5429 #else
5430 if (unlikely(!ctx->mem_idx)) {
5431 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5432 return;
5433 }
5434 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5435 #endif
5436 }
5437
5438 /* tlbli */
5439 static void gen_tlbli_6xx(DisasContext *ctx)
5440 {
5441 #if defined(CONFIG_USER_ONLY)
5442 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5443 #else
5444 if (unlikely(!ctx->mem_idx)) {
5445 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5446 return;
5447 }
5448 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5449 #endif
5450 }
5451
5452 /* 74xx TLB management */
5453
5454 /* tlbld */
5455 static void gen_tlbld_74xx(DisasContext *ctx)
5456 {
5457 #if defined(CONFIG_USER_ONLY)
5458 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5459 #else
5460 if (unlikely(!ctx->mem_idx)) {
5461 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5462 return;
5463 }
5464 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5465 #endif
5466 }
5467
5468 /* tlbli */
5469 static void gen_tlbli_74xx(DisasContext *ctx)
5470 {
5471 #if defined(CONFIG_USER_ONLY)
5472 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5473 #else
5474 if (unlikely(!ctx->mem_idx)) {
5475 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5476 return;
5477 }
5478 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5479 #endif
5480 }
5481
5482 /* POWER instructions not in PowerPC 601 */
5483
5484 /* clf */
5485 static void gen_clf(DisasContext *ctx)
5486 {
5487 /* Cache line flush: implemented as no-op */
5488 }
5489
5490 /* cli */
5491 static void gen_cli(DisasContext *ctx)
5492 {
5493 /* Cache line invalidate: privileged and treated as no-op */
5494 #if defined(CONFIG_USER_ONLY)
5495 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5496 #else
5497 if (unlikely(!ctx->mem_idx)) {
5498 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5499 return;
5500 }
5501 #endif
5502 }
5503
5504 /* dclst */
5505 static void gen_dclst(DisasContext *ctx)
5506 {
5507 /* Data cache line store: treated as no-op */
5508 }
5509
5510 static void gen_mfsri(DisasContext *ctx)
5511 {
5512 #if defined(CONFIG_USER_ONLY)
5513 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5514 #else
5515 int ra = rA(ctx->opcode);
5516 int rd = rD(ctx->opcode);
5517 TCGv t0;
5518 if (unlikely(!ctx->mem_idx)) {
5519 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5520 return;
5521 }
5522 t0 = tcg_temp_new();
5523 gen_addr_reg_index(ctx, t0);
5524 tcg_gen_shri_tl(t0, t0, 28);
5525 tcg_gen_andi_tl(t0, t0, 0xF);
5526 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5527 tcg_temp_free(t0);
5528 if (ra != 0 && ra != rd)
5529 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5530 #endif
5531 }
5532
5533 static void gen_rac(DisasContext *ctx)
5534 {
5535 #if defined(CONFIG_USER_ONLY)
5536 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5537 #else
5538 TCGv t0;
5539 if (unlikely(!ctx->mem_idx)) {
5540 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5541 return;
5542 }
5543 t0 = tcg_temp_new();
5544 gen_addr_reg_index(ctx, t0);
5545 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5546 tcg_temp_free(t0);
5547 #endif
5548 }
5549
5550 static void gen_rfsvc(DisasContext *ctx)
5551 {
5552 #if defined(CONFIG_USER_ONLY)
5553 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5554 #else
5555 if (unlikely(!ctx->mem_idx)) {
5556 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5557 return;
5558 }
5559 gen_helper_rfsvc(cpu_env);
5560 gen_sync_exception(ctx);
5561 #endif
5562 }
5563
5564 /* svc is not implemented for now */
5565
5566 /* POWER2 specific instructions */
5567 /* Quad manipulation (load/store two floats at a time) */
5568
5569 /* lfq */
5570 static void gen_lfq(DisasContext *ctx)
5571 {
5572 int rd = rD(ctx->opcode);
5573 TCGv t0;
5574 gen_set_access_type(ctx, ACCESS_FLOAT);
5575 t0 = tcg_temp_new();
5576 gen_addr_imm_index(ctx, t0, 0);
5577 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5578 gen_addr_add(ctx, t0, t0, 8);
5579 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5580 tcg_temp_free(t0);
5581 }
5582
5583 /* lfqu */
5584 static void gen_lfqu(DisasContext *ctx)
5585 {
5586 int ra = rA(ctx->opcode);
5587 int rd = rD(ctx->opcode);
5588 TCGv t0, t1;
5589 gen_set_access_type(ctx, ACCESS_FLOAT);
5590 t0 = tcg_temp_new();
5591 t1 = tcg_temp_new();
5592 gen_addr_imm_index(ctx, t0, 0);
5593 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5594 gen_addr_add(ctx, t1, t0, 8);
5595 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5596 if (ra != 0)
5597 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5598 tcg_temp_free(t0);
5599 tcg_temp_free(t1);
5600 }
5601
5602 /* lfqux */
5603 static void gen_lfqux(DisasContext *ctx)
5604 {
5605 int ra = rA(ctx->opcode);
5606 int rd = rD(ctx->opcode);
5607 gen_set_access_type(ctx, ACCESS_FLOAT);
5608 TCGv t0, t1;
5609 t0 = tcg_temp_new();
5610 gen_addr_reg_index(ctx, t0);
5611 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5612 t1 = tcg_temp_new();
5613 gen_addr_add(ctx, t1, t0, 8);
5614 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5615 tcg_temp_free(t1);
5616 if (ra != 0)
5617 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5618 tcg_temp_free(t0);
5619 }
5620
5621 /* lfqx */
5622 static void gen_lfqx(DisasContext *ctx)
5623 {
5624 int rd = rD(ctx->opcode);
5625 TCGv t0;
5626 gen_set_access_type(ctx, ACCESS_FLOAT);
5627 t0 = tcg_temp_new();
5628 gen_addr_reg_index(ctx, t0);
5629 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5630 gen_addr_add(ctx, t0, t0, 8);
5631 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5632 tcg_temp_free(t0);
5633 }
5634
5635 /* stfq */
5636 static void gen_stfq(DisasContext *ctx)
5637 {
5638 int rd = rD(ctx->opcode);
5639 TCGv t0;
5640 gen_set_access_type(ctx, ACCESS_FLOAT);
5641 t0 = tcg_temp_new();
5642 gen_addr_imm_index(ctx, t0, 0);
5643 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5644 gen_addr_add(ctx, t0, t0, 8);
5645 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5646 tcg_temp_free(t0);
5647 }
5648
5649 /* stfqu */
5650 static void gen_stfqu(DisasContext *ctx)
5651 {
5652 int ra = rA(ctx->opcode);
5653 int rd = rD(ctx->opcode);
5654 TCGv t0, t1;
5655 gen_set_access_type(ctx, ACCESS_FLOAT);
5656 t0 = tcg_temp_new();
5657 gen_addr_imm_index(ctx, t0, 0);
5658 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5659 t1 = tcg_temp_new();
5660 gen_addr_add(ctx, t1, t0, 8);
5661 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5662 tcg_temp_free(t1);
5663 if (ra != 0)
5664 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5665 tcg_temp_free(t0);
5666 }
5667
5668 /* stfqux */
5669 static void gen_stfqux(DisasContext *ctx)
5670 {
5671 int ra = rA(ctx->opcode);
5672 int rd = rD(ctx->opcode);
5673 TCGv t0, t1;
5674 gen_set_access_type(ctx, ACCESS_FLOAT);
5675 t0 = tcg_temp_new();
5676 gen_addr_reg_index(ctx, t0);
5677 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5678 t1 = tcg_temp_new();
5679 gen_addr_add(ctx, t1, t0, 8);
5680 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5681 tcg_temp_free(t1);
5682 if (ra != 0)
5683 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5684 tcg_temp_free(t0);
5685 }
5686
5687 /* stfqx */
5688 static void gen_stfqx(DisasContext *ctx)
5689 {
5690 int rd = rD(ctx->opcode);
5691 TCGv t0;
5692 gen_set_access_type(ctx, ACCESS_FLOAT);
5693 t0 = tcg_temp_new();
5694 gen_addr_reg_index(ctx, t0);
5695 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5696 gen_addr_add(ctx, t0, t0, 8);
5697 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5698 tcg_temp_free(t0);
5699 }
5700
5701 /* BookE specific instructions */
5702
5703 /* XXX: not implemented on 440 ? */
5704 static void gen_mfapidi(DisasContext *ctx)
5705 {
5706 /* XXX: TODO */
5707 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5708 }
5709
5710 /* XXX: not implemented on 440 ? */
5711 static void gen_tlbiva(DisasContext *ctx)
5712 {
5713 #if defined(CONFIG_USER_ONLY)
5714 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5715 #else
5716 TCGv t0;
5717 if (unlikely(!ctx->mem_idx)) {
5718 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5719 return;
5720 }
5721 t0 = tcg_temp_new();
5722 gen_addr_reg_index(ctx, t0);
5723 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5724 tcg_temp_free(t0);
5725 #endif
5726 }
5727
5728 /* All 405 MAC instructions are translated here */
5729 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5730 int ra, int rb, int rt, int Rc)
5731 {
5732 TCGv t0, t1;
5733
5734 t0 = tcg_temp_local_new();
5735 t1 = tcg_temp_local_new();
5736
5737 switch (opc3 & 0x0D) {
5738 case 0x05:
5739 /* macchw - macchw. - macchwo - macchwo. */
5740 /* macchws - macchws. - macchwso - macchwso. */
5741 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5742 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5743 /* mulchw - mulchw. */
5744 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5745 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5746 tcg_gen_ext16s_tl(t1, t1);
5747 break;
5748 case 0x04:
5749 /* macchwu - macchwu. - macchwuo - macchwuo. */
5750 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5751 /* mulchwu - mulchwu. */
5752 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5753 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5754 tcg_gen_ext16u_tl(t1, t1);
5755 break;
5756 case 0x01:
5757 /* machhw - machhw. - machhwo - machhwo. */
5758 /* machhws - machhws. - machhwso - machhwso. */
5759 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5760 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5761 /* mulhhw - mulhhw. */
5762 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5763 tcg_gen_ext16s_tl(t0, t0);
5764 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5765 tcg_gen_ext16s_tl(t1, t1);
5766 break;
5767 case 0x00:
5768 /* machhwu - machhwu. - machhwuo - machhwuo. */
5769 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5770 /* mulhhwu - mulhhwu. */
5771 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5772 tcg_gen_ext16u_tl(t0, t0);
5773 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5774 tcg_gen_ext16u_tl(t1, t1);
5775 break;
5776 case 0x0D:
5777 /* maclhw - maclhw. - maclhwo - maclhwo. */
5778 /* maclhws - maclhws. - maclhwso - maclhwso. */
5779 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5780 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5781 /* mullhw - mullhw. */
5782 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5783 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5784 break;
5785 case 0x0C:
5786 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5787 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5788 /* mullhwu - mullhwu. */
5789 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5790 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5791 break;
5792 }
5793 if (opc2 & 0x04) {
5794 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5795 tcg_gen_mul_tl(t1, t0, t1);
5796 if (opc2 & 0x02) {
5797 /* nmultiply-and-accumulate (0x0E) */
5798 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5799 } else {
5800 /* multiply-and-accumulate (0x0C) */
5801 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5802 }
5803
5804 if (opc3 & 0x12) {
5805 /* Check overflow and/or saturate */
5806 int l1 = gen_new_label();
5807
5808 if (opc3 & 0x10) {
5809 /* Start with XER OV disabled, the most likely case */
5810 tcg_gen_movi_tl(cpu_ov, 0);
5811 }
5812 if (opc3 & 0x01) {
5813 /* Signed */
5814 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5815 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5816 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5817 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5818 if (opc3 & 0x02) {
5819 /* Saturate */
5820 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5821 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5822 }
5823 } else {
5824 /* Unsigned */
5825 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5826 if (opc3 & 0x02) {
5827 /* Saturate */
5828 tcg_gen_movi_tl(t0, UINT32_MAX);
5829 }
5830 }
5831 if (opc3 & 0x10) {
5832 /* Check overflow */
5833 tcg_gen_movi_tl(cpu_ov, 1);
5834 tcg_gen_movi_tl(cpu_so, 1);
5835 }
5836 gen_set_label(l1);
5837 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5838 }
5839 } else {
5840 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5841 }
5842 tcg_temp_free(t0);
5843 tcg_temp_free(t1);
5844 if (unlikely(Rc) != 0) {
5845 /* Update Rc0 */
5846 gen_set_Rc0(ctx, cpu_gpr[rt]);
5847 }
5848 }
5849
5850 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5851 static void glue(gen_, name)(DisasContext *ctx) \
5852 { \
5853 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5854 rD(ctx->opcode), Rc(ctx->opcode)); \
5855 }
5856
5857 /* macchw - macchw. */
5858 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5859 /* macchwo - macchwo. */
5860 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5861 /* macchws - macchws. */
5862 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5863 /* macchwso - macchwso. */
5864 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5865 /* macchwsu - macchwsu. */
5866 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5867 /* macchwsuo - macchwsuo. */
5868 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5869 /* macchwu - macchwu. */
5870 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5871 /* macchwuo - macchwuo. */
5872 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5873 /* machhw - machhw. */
5874 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5875 /* machhwo - machhwo. */
5876 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5877 /* machhws - machhws. */
5878 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5879 /* machhwso - machhwso. */
5880 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5881 /* machhwsu - machhwsu. */
5882 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5883 /* machhwsuo - machhwsuo. */
5884 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5885 /* machhwu - machhwu. */
5886 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5887 /* machhwuo - machhwuo. */
5888 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5889 /* maclhw - maclhw. */
5890 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5891 /* maclhwo - maclhwo. */
5892 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5893 /* maclhws - maclhws. */
5894 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5895 /* maclhwso - maclhwso. */
5896 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5897 /* maclhwu - maclhwu. */
5898 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5899 /* maclhwuo - maclhwuo. */
5900 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5901 /* maclhwsu - maclhwsu. */
5902 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5903 /* maclhwsuo - maclhwsuo. */
5904 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5905 /* nmacchw - nmacchw. */
5906 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5907 /* nmacchwo - nmacchwo. */
5908 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5909 /* nmacchws - nmacchws. */
5910 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5911 /* nmacchwso - nmacchwso. */
5912 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5913 /* nmachhw - nmachhw. */
5914 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5915 /* nmachhwo - nmachhwo. */
5916 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5917 /* nmachhws - nmachhws. */
5918 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5919 /* nmachhwso - nmachhwso. */
5920 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5921 /* nmaclhw - nmaclhw. */
5922 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5923 /* nmaclhwo - nmaclhwo. */
5924 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5925 /* nmaclhws - nmaclhws. */
5926 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5927 /* nmaclhwso - nmaclhwso. */
5928 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5929
5930 /* mulchw - mulchw. */
5931 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5932 /* mulchwu - mulchwu. */
5933 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5934 /* mulhhw - mulhhw. */
5935 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5936 /* mulhhwu - mulhhwu. */
5937 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5938 /* mullhw - mullhw. */
5939 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5940 /* mullhwu - mullhwu. */
5941 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5942
5943 /* mfdcr */
5944 static void gen_mfdcr(DisasContext *ctx)
5945 {
5946 #if defined(CONFIG_USER_ONLY)
5947 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5948 #else
5949 TCGv dcrn;
5950 if (unlikely(!ctx->mem_idx)) {
5951 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5952 return;
5953 }
5954 /* NIP cannot be restored if the memory exception comes from an helper */
5955 gen_update_nip(ctx, ctx->nip - 4);
5956 dcrn = tcg_const_tl(SPR(ctx->opcode));
5957 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5958 tcg_temp_free(dcrn);
5959 #endif
5960 }
5961
5962 /* mtdcr */
5963 static void gen_mtdcr(DisasContext *ctx)
5964 {
5965 #if defined(CONFIG_USER_ONLY)
5966 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5967 #else
5968 TCGv dcrn;
5969 if (unlikely(!ctx->mem_idx)) {
5970 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5971 return;
5972 }
5973 /* NIP cannot be restored if the memory exception comes from an helper */
5974 gen_update_nip(ctx, ctx->nip - 4);
5975 dcrn = tcg_const_tl(SPR(ctx->opcode));
5976 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5977 tcg_temp_free(dcrn);
5978 #endif
5979 }
5980
5981 /* mfdcrx */
5982 /* XXX: not implemented on 440 ? */
5983 static void gen_mfdcrx(DisasContext *ctx)
5984 {
5985 #if defined(CONFIG_USER_ONLY)
5986 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5987 #else
5988 if (unlikely(!ctx->mem_idx)) {
5989 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5990 return;
5991 }
5992 /* NIP cannot be restored if the memory exception comes from an helper */
5993 gen_update_nip(ctx, ctx->nip - 4);
5994 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5995 cpu_gpr[rA(ctx->opcode)]);
5996 /* Note: Rc update flag set leads to undefined state of Rc0 */
5997 #endif
5998 }
5999
6000 /* mtdcrx */
6001 /* XXX: not implemented on 440 ? */
6002 static void gen_mtdcrx(DisasContext *ctx)
6003 {
6004 #if defined(CONFIG_USER_ONLY)
6005 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6006 #else
6007 if (unlikely(!ctx->mem_idx)) {
6008 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6009 return;
6010 }
6011 /* NIP cannot be restored if the memory exception comes from an helper */
6012 gen_update_nip(ctx, ctx->nip - 4);
6013 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6014 cpu_gpr[rS(ctx->opcode)]);
6015 /* Note: Rc update flag set leads to undefined state of Rc0 */
6016 #endif
6017 }
6018
6019 /* mfdcrux (PPC 460) : user-mode access to DCR */
6020 static void gen_mfdcrux(DisasContext *ctx)
6021 {
6022 /* NIP cannot be restored if the memory exception comes from an helper */
6023 gen_update_nip(ctx, ctx->nip - 4);
6024 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6025 cpu_gpr[rA(ctx->opcode)]);
6026 /* Note: Rc update flag set leads to undefined state of Rc0 */
6027 }
6028
6029 /* mtdcrux (PPC 460) : user-mode access to DCR */
6030 static void gen_mtdcrux(DisasContext *ctx)
6031 {
6032 /* NIP cannot be restored if the memory exception comes from an helper */
6033 gen_update_nip(ctx, ctx->nip - 4);
6034 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6035 cpu_gpr[rS(ctx->opcode)]);
6036 /* Note: Rc update flag set leads to undefined state of Rc0 */
6037 }
6038
6039 /* dccci */
6040 static void gen_dccci(DisasContext *ctx)
6041 {
6042 #if defined(CONFIG_USER_ONLY)
6043 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6044 #else
6045 if (unlikely(!ctx->mem_idx)) {
6046 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6047 return;
6048 }
6049 /* interpreted as no-op */
6050 #endif
6051 }
6052
6053 /* dcread */
6054 static void gen_dcread(DisasContext *ctx)
6055 {
6056 #if defined(CONFIG_USER_ONLY)
6057 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6058 #else
6059 TCGv EA, val;
6060 if (unlikely(!ctx->mem_idx)) {
6061 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6062 return;
6063 }
6064 gen_set_access_type(ctx, ACCESS_CACHE);
6065 EA = tcg_temp_new();
6066 gen_addr_reg_index(ctx, EA);
6067 val = tcg_temp_new();
6068 gen_qemu_ld32u(ctx, val, EA);
6069 tcg_temp_free(val);
6070 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6071 tcg_temp_free(EA);
6072 #endif
6073 }
6074
6075 /* icbt */
6076 static void gen_icbt_40x(DisasContext *ctx)
6077 {
6078 /* interpreted as no-op */
6079 /* XXX: specification say this is treated as a load by the MMU
6080 * but does not generate any exception
6081 */
6082 }
6083
6084 /* iccci */
6085 static void gen_iccci(DisasContext *ctx)
6086 {
6087 #if defined(CONFIG_USER_ONLY)
6088 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6089 #else
6090 if (unlikely(!ctx->mem_idx)) {
6091 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6092 return;
6093 }
6094 /* interpreted as no-op */
6095 #endif
6096 }
6097
6098 /* icread */
6099 static void gen_icread(DisasContext *ctx)
6100 {
6101 #if defined(CONFIG_USER_ONLY)
6102 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6103 #else
6104 if (unlikely(!ctx->mem_idx)) {
6105 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6106 return;
6107 }
6108 /* interpreted as no-op */
6109 #endif
6110 }
6111
6112 /* rfci (mem_idx only) */
6113 static void gen_rfci_40x(DisasContext *ctx)
6114 {
6115 #if defined(CONFIG_USER_ONLY)
6116 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6117 #else
6118 if (unlikely(!ctx->mem_idx)) {
6119 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6120 return;
6121 }
6122 /* Restore CPU state */
6123 gen_helper_40x_rfci(cpu_env);
6124 gen_sync_exception(ctx);
6125 #endif
6126 }
6127
6128 static void gen_rfci(DisasContext *ctx)
6129 {
6130 #if defined(CONFIG_USER_ONLY)
6131 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6132 #else
6133 if (unlikely(!ctx->mem_idx)) {
6134 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6135 return;
6136 }
6137 /* Restore CPU state */
6138 gen_helper_rfci(cpu_env);
6139 gen_sync_exception(ctx);
6140 #endif
6141 }
6142
6143 /* BookE specific */
6144
6145 /* XXX: not implemented on 440 ? */
6146 static void gen_rfdi(DisasContext *ctx)
6147 {
6148 #if defined(CONFIG_USER_ONLY)
6149 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6150 #else
6151 if (unlikely(!ctx->mem_idx)) {
6152 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6153 return;
6154 }
6155 /* Restore CPU state */
6156 gen_helper_rfdi(cpu_env);
6157 gen_sync_exception(ctx);
6158 #endif
6159 }
6160
6161 /* XXX: not implemented on 440 ? */
6162 static void gen_rfmci(DisasContext *ctx)
6163 {
6164 #if defined(CONFIG_USER_ONLY)
6165 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6166 #else
6167 if (unlikely(!ctx->mem_idx)) {
6168 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6169 return;
6170 }
6171 /* Restore CPU state */
6172 gen_helper_rfmci(cpu_env);
6173 gen_sync_exception(ctx);
6174 #endif
6175 }
6176
6177 /* TLB management - PowerPC 405 implementation */
6178
6179 /* tlbre */
6180 static void gen_tlbre_40x(DisasContext *ctx)
6181 {
6182 #if defined(CONFIG_USER_ONLY)
6183 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6184 #else
6185 if (unlikely(!ctx->mem_idx)) {
6186 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6187 return;
6188 }
6189 switch (rB(ctx->opcode)) {
6190 case 0:
6191 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6192 cpu_gpr[rA(ctx->opcode)]);
6193 break;
6194 case 1:
6195 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6196 cpu_gpr[rA(ctx->opcode)]);
6197 break;
6198 default:
6199 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6200 break;
6201 }
6202 #endif
6203 }
6204
6205 /* tlbsx - tlbsx. */
6206 static void gen_tlbsx_40x(DisasContext *ctx)
6207 {
6208 #if defined(CONFIG_USER_ONLY)
6209 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6210 #else
6211 TCGv t0;
6212 if (unlikely(!ctx->mem_idx)) {
6213 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6214 return;
6215 }
6216 t0 = tcg_temp_new();
6217 gen_addr_reg_index(ctx, t0);
6218 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6219 tcg_temp_free(t0);
6220 if (Rc(ctx->opcode)) {
6221 int l1 = gen_new_label();
6222 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6223 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6224 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6225 gen_set_label(l1);
6226 }
6227 #endif
6228 }
6229
6230 /* tlbwe */
6231 static void gen_tlbwe_40x(DisasContext *ctx)
6232 {
6233 #if defined(CONFIG_USER_ONLY)
6234 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6235 #else
6236 if (unlikely(!ctx->mem_idx)) {
6237 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6238 return;
6239 }
6240 switch (rB(ctx->opcode)) {
6241 case 0:
6242 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6243 cpu_gpr[rS(ctx->opcode)]);
6244 break;
6245 case 1:
6246 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6247 cpu_gpr[rS(ctx->opcode)]);
6248 break;
6249 default:
6250 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6251 break;
6252 }
6253 #endif
6254 }
6255
6256 /* TLB management - PowerPC 440 implementation */
6257
6258 /* tlbre */
6259 static void gen_tlbre_440(DisasContext *ctx)
6260 {
6261 #if defined(CONFIG_USER_ONLY)
6262 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6263 #else
6264 if (unlikely(!ctx->mem_idx)) {
6265 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6266 return;
6267 }
6268 switch (rB(ctx->opcode)) {
6269 case 0:
6270 case 1:
6271 case 2:
6272 {
6273 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6274 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6275 t0, cpu_gpr[rA(ctx->opcode)]);
6276 tcg_temp_free_i32(t0);
6277 }
6278 break;
6279 default:
6280 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6281 break;
6282 }
6283 #endif
6284 }
6285
6286 /* tlbsx - tlbsx. */
6287 static void gen_tlbsx_440(DisasContext *ctx)
6288 {
6289 #if defined(CONFIG_USER_ONLY)
6290 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6291 #else
6292 TCGv t0;
6293 if (unlikely(!ctx->mem_idx)) {
6294 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6295 return;
6296 }
6297 t0 = tcg_temp_new();
6298 gen_addr_reg_index(ctx, t0);
6299 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6300 tcg_temp_free(t0);
6301 if (Rc(ctx->opcode)) {
6302 int l1 = gen_new_label();
6303 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6304 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6305 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6306 gen_set_label(l1);
6307 }
6308 #endif
6309 }
6310
6311 /* tlbwe */
6312 static void gen_tlbwe_440(DisasContext *ctx)
6313 {
6314 #if defined(CONFIG_USER_ONLY)
6315 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6316 #else
6317 if (unlikely(!ctx->mem_idx)) {
6318 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6319 return;
6320 }
6321 switch (rB(ctx->opcode)) {
6322 case 0:
6323 case 1:
6324 case 2:
6325 {
6326 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6327 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6328 cpu_gpr[rS(ctx->opcode)]);
6329 tcg_temp_free_i32(t0);
6330 }
6331 break;
6332 default:
6333 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6334 break;
6335 }
6336 #endif
6337 }
6338
6339 /* TLB management - PowerPC BookE 2.06 implementation */
6340
6341 /* tlbre */
6342 static void gen_tlbre_booke206(DisasContext *ctx)
6343 {
6344 #if defined(CONFIG_USER_ONLY)
6345 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6346 #else
6347 if (unlikely(!ctx->mem_idx)) {
6348 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6349 return;
6350 }
6351
6352 gen_helper_booke206_tlbre(cpu_env);
6353 #endif
6354 }
6355
6356 /* tlbsx - tlbsx. */
6357 static void gen_tlbsx_booke206(DisasContext *ctx)
6358 {
6359 #if defined(CONFIG_USER_ONLY)
6360 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6361 #else
6362 TCGv t0;
6363 if (unlikely(!ctx->mem_idx)) {
6364 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6365 return;
6366 }
6367
6368 if (rA(ctx->opcode)) {
6369 t0 = tcg_temp_new();
6370 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6371 } else {
6372 t0 = tcg_const_tl(0);
6373 }
6374
6375 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6376 gen_helper_booke206_tlbsx(cpu_env, t0);
6377 #endif
6378 }
6379
6380 /* tlbwe */
6381 static void gen_tlbwe_booke206(DisasContext *ctx)
6382 {
6383 #if defined(CONFIG_USER_ONLY)
6384 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6385 #else
6386 if (unlikely(!ctx->mem_idx)) {
6387 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6388 return;
6389 }
6390 gen_update_nip(ctx, ctx->nip - 4);
6391 gen_helper_booke206_tlbwe(cpu_env);
6392 #endif
6393 }
6394
6395 static void gen_tlbivax_booke206(DisasContext *ctx)
6396 {
6397 #if defined(CONFIG_USER_ONLY)
6398 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6399 #else
6400 TCGv t0;
6401 if (unlikely(!ctx->mem_idx)) {
6402 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6403 return;
6404 }
6405
6406 t0 = tcg_temp_new();
6407 gen_addr_reg_index(ctx, t0);
6408
6409 gen_helper_booke206_tlbivax(cpu_env, t0);
6410 #endif
6411 }
6412
6413 static void gen_tlbilx_booke206(DisasContext *ctx)
6414 {
6415 #if defined(CONFIG_USER_ONLY)
6416 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6417 #else
6418 TCGv t0;
6419 if (unlikely(!ctx->mem_idx)) {
6420 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6421 return;
6422 }
6423
6424 t0 = tcg_temp_new();
6425 gen_addr_reg_index(ctx, t0);
6426
6427 switch((ctx->opcode >> 21) & 0x3) {
6428 case 0:
6429 gen_helper_booke206_tlbilx0(cpu_env, t0);
6430 break;
6431 case 1:
6432 gen_helper_booke206_tlbilx1(cpu_env, t0);
6433 break;
6434 case 3:
6435 gen_helper_booke206_tlbilx3(cpu_env, t0);
6436 break;
6437 default:
6438 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6439 break;
6440 }
6441
6442 tcg_temp_free(t0);
6443 #endif
6444 }
6445
6446
6447 /* wrtee */
6448 static void gen_wrtee(DisasContext *ctx)
6449 {
6450 #if defined(CONFIG_USER_ONLY)
6451 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6452 #else
6453 TCGv t0;
6454 if (unlikely(!ctx->mem_idx)) {
6455 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6456 return;
6457 }
6458 t0 = tcg_temp_new();
6459 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6460 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6461 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6462 tcg_temp_free(t0);
6463 /* Stop translation to have a chance to raise an exception
6464 * if we just set msr_ee to 1
6465 */
6466 gen_stop_exception(ctx);
6467 #endif
6468 }
6469
6470 /* wrteei */
6471 static void gen_wrteei(DisasContext *ctx)
6472 {
6473 #if defined(CONFIG_USER_ONLY)
6474 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6475 #else
6476 if (unlikely(!ctx->mem_idx)) {
6477 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6478 return;
6479 }
6480 if (ctx->opcode & 0x00008000) {
6481 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6482 /* Stop translation to have a chance to raise an exception */
6483 gen_stop_exception(ctx);
6484 } else {
6485 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6486 }
6487 #endif
6488 }
6489
6490 /* PowerPC 440 specific instructions */
6491
6492 /* dlmzb */
6493 static void gen_dlmzb(DisasContext *ctx)
6494 {
6495 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6496 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6497 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6498 tcg_temp_free_i32(t0);
6499 }
6500
6501 /* mbar replaces eieio on 440 */
6502 static void gen_mbar(DisasContext *ctx)
6503 {
6504 /* interpreted as no-op */
6505 }
6506
6507 /* msync replaces sync on 440 */
6508 static void gen_msync_4xx(DisasContext *ctx)
6509 {
6510 /* interpreted as no-op */
6511 }
6512
6513 /* icbt */
6514 static void gen_icbt_440(DisasContext *ctx)
6515 {
6516 /* interpreted as no-op */
6517 /* XXX: specification say this is treated as a load by the MMU
6518 * but does not generate any exception
6519 */
6520 }
6521
6522 /* Embedded.Processor Control */
6523
6524 static void gen_msgclr(DisasContext *ctx)
6525 {
6526 #if defined(CONFIG_USER_ONLY)
6527 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6528 #else
6529 if (unlikely(ctx->mem_idx == 0)) {
6530 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6531 return;
6532 }
6533
6534 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6535 #endif
6536 }
6537
6538 static void gen_msgsnd(DisasContext *ctx)
6539 {
6540 #if defined(CONFIG_USER_ONLY)
6541 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6542 #else
6543 if (unlikely(ctx->mem_idx == 0)) {
6544 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6545 return;
6546 }
6547
6548 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6549 #endif
6550 }
6551
6552 /*** Altivec vector extension ***/
6553 /* Altivec registers moves */
6554
6555 static inline TCGv_ptr gen_avr_ptr(int reg)
6556 {
6557 TCGv_ptr r = tcg_temp_new_ptr();
6558 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6559 return r;
6560 }
6561
6562 #define GEN_VR_LDX(name, opc2, opc3) \
6563 static void glue(gen_, name)(DisasContext *ctx) \
6564 { \
6565 TCGv EA; \
6566 if (unlikely(!ctx->altivec_enabled)) { \
6567 gen_exception(ctx, POWERPC_EXCP_VPU); \
6568 return; \
6569 } \
6570 gen_set_access_type(ctx, ACCESS_INT); \
6571 EA = tcg_temp_new(); \
6572 gen_addr_reg_index(ctx, EA); \
6573 tcg_gen_andi_tl(EA, EA, ~0xf); \
6574 if (ctx->le_mode) { \
6575 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6576 tcg_gen_addi_tl(EA, EA, 8); \
6577 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6578 } else { \
6579 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6580 tcg_gen_addi_tl(EA, EA, 8); \
6581 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6582 } \
6583 tcg_temp_free(EA); \
6584 }
6585
6586 #define GEN_VR_STX(name, opc2, opc3) \
6587 static void gen_st##name(DisasContext *ctx) \
6588 { \
6589 TCGv EA; \
6590 if (unlikely(!ctx->altivec_enabled)) { \
6591 gen_exception(ctx, POWERPC_EXCP_VPU); \
6592 return; \
6593 } \
6594 gen_set_access_type(ctx, ACCESS_INT); \
6595 EA = tcg_temp_new(); \
6596 gen_addr_reg_index(ctx, EA); \
6597 tcg_gen_andi_tl(EA, EA, ~0xf); \
6598 if (ctx->le_mode) { \
6599 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6600 tcg_gen_addi_tl(EA, EA, 8); \
6601 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6602 } else { \
6603 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6604 tcg_gen_addi_tl(EA, EA, 8); \
6605 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6606 } \
6607 tcg_temp_free(EA); \
6608 }
6609
6610 #define GEN_VR_LVE(name, opc2, opc3) \
6611 static void gen_lve##name(DisasContext *ctx) \
6612 { \
6613 TCGv EA; \
6614 TCGv_ptr rs; \
6615 if (unlikely(!ctx->altivec_enabled)) { \
6616 gen_exception(ctx, POWERPC_EXCP_VPU); \
6617 return; \
6618 } \
6619 gen_set_access_type(ctx, ACCESS_INT); \
6620 EA = tcg_temp_new(); \
6621 gen_addr_reg_index(ctx, EA); \
6622 rs = gen_avr_ptr(rS(ctx->opcode)); \
6623 gen_helper_lve##name(cpu_env, rs, EA); \
6624 tcg_temp_free(EA); \
6625 tcg_temp_free_ptr(rs); \
6626 }
6627
6628 #define GEN_VR_STVE(name, opc2, opc3) \
6629 static void gen_stve##name(DisasContext *ctx) \
6630 { \
6631 TCGv EA; \
6632 TCGv_ptr rs; \
6633 if (unlikely(!ctx->altivec_enabled)) { \
6634 gen_exception(ctx, POWERPC_EXCP_VPU); \
6635 return; \
6636 } \
6637 gen_set_access_type(ctx, ACCESS_INT); \
6638 EA = tcg_temp_new(); \
6639 gen_addr_reg_index(ctx, EA); \
6640 rs = gen_avr_ptr(rS(ctx->opcode)); \
6641 gen_helper_stve##name(cpu_env, rs, EA); \
6642 tcg_temp_free(EA); \
6643 tcg_temp_free_ptr(rs); \
6644 }
6645
6646 GEN_VR_LDX(lvx, 0x07, 0x03);
6647 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6648 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6649
6650 GEN_VR_LVE(bx, 0x07, 0x00);
6651 GEN_VR_LVE(hx, 0x07, 0x01);
6652 GEN_VR_LVE(wx, 0x07, 0x02);
6653
6654 GEN_VR_STX(svx, 0x07, 0x07);
6655 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6656 GEN_VR_STX(svxl, 0x07, 0x0F);
6657
6658 GEN_VR_STVE(bx, 0x07, 0x04);
6659 GEN_VR_STVE(hx, 0x07, 0x05);
6660 GEN_VR_STVE(wx, 0x07, 0x06);
6661
6662 static void gen_lvsl(DisasContext *ctx)
6663 {
6664 TCGv_ptr rd;
6665 TCGv EA;
6666 if (unlikely(!ctx->altivec_enabled)) {
6667 gen_exception(ctx, POWERPC_EXCP_VPU);
6668 return;
6669 }
6670 EA = tcg_temp_new();
6671 gen_addr_reg_index(ctx, EA);
6672 rd = gen_avr_ptr(rD(ctx->opcode));
6673 gen_helper_lvsl(rd, EA);
6674 tcg_temp_free(EA);
6675 tcg_temp_free_ptr(rd);
6676 }
6677
6678 static void gen_lvsr(DisasContext *ctx)
6679 {
6680 TCGv_ptr rd;
6681 TCGv EA;
6682 if (unlikely(!ctx->altivec_enabled)) {
6683 gen_exception(ctx, POWERPC_EXCP_VPU);
6684 return;
6685 }
6686 EA = tcg_temp_new();
6687 gen_addr_reg_index(ctx, EA);
6688 rd = gen_avr_ptr(rD(ctx->opcode));
6689 gen_helper_lvsr(rd, EA);
6690 tcg_temp_free(EA);
6691 tcg_temp_free_ptr(rd);
6692 }
6693
6694 static void gen_mfvscr(DisasContext *ctx)
6695 {
6696 TCGv_i32 t;
6697 if (unlikely(!ctx->altivec_enabled)) {
6698 gen_exception(ctx, POWERPC_EXCP_VPU);
6699 return;
6700 }
6701 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6702 t = tcg_temp_new_i32();
6703 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6704 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6705 tcg_temp_free_i32(t);
6706 }
6707
6708 static void gen_mtvscr(DisasContext *ctx)
6709 {
6710 TCGv_ptr p;
6711 if (unlikely(!ctx->altivec_enabled)) {
6712 gen_exception(ctx, POWERPC_EXCP_VPU);
6713 return;
6714 }
6715 p = gen_avr_ptr(rD(ctx->opcode));
6716 gen_helper_mtvscr(cpu_env, p);
6717 tcg_temp_free_ptr(p);
6718 }
6719
6720 /* Logical operations */
6721 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6722 static void glue(gen_, name)(DisasContext *ctx) \
6723 { \
6724 if (unlikely(!ctx->altivec_enabled)) { \
6725 gen_exception(ctx, POWERPC_EXCP_VPU); \
6726 return; \
6727 } \
6728 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6729 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6730 }
6731
6732 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6733 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6734 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6735 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6736 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6737
6738 #define GEN_VXFORM(name, opc2, opc3) \
6739 static void glue(gen_, name)(DisasContext *ctx) \
6740 { \
6741 TCGv_ptr ra, rb, rd; \
6742 if (unlikely(!ctx->altivec_enabled)) { \
6743 gen_exception(ctx, POWERPC_EXCP_VPU); \
6744 return; \
6745 } \
6746 ra = gen_avr_ptr(rA(ctx->opcode)); \
6747 rb = gen_avr_ptr(rB(ctx->opcode)); \
6748 rd = gen_avr_ptr(rD(ctx->opcode)); \
6749 gen_helper_##name (rd, ra, rb); \
6750 tcg_temp_free_ptr(ra); \
6751 tcg_temp_free_ptr(rb); \
6752 tcg_temp_free_ptr(rd); \
6753 }
6754
6755 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6756 static void glue(gen_, name)(DisasContext *ctx) \
6757 { \
6758 TCGv_ptr ra, rb, rd; \
6759 if (unlikely(!ctx->altivec_enabled)) { \
6760 gen_exception(ctx, POWERPC_EXCP_VPU); \
6761 return; \
6762 } \
6763 ra = gen_avr_ptr(rA(ctx->opcode)); \
6764 rb = gen_avr_ptr(rB(ctx->opcode)); \
6765 rd = gen_avr_ptr(rD(ctx->opcode)); \
6766 gen_helper_##name(cpu_env, rd, ra, rb); \
6767 tcg_temp_free_ptr(ra); \
6768 tcg_temp_free_ptr(rb); \
6769 tcg_temp_free_ptr(rd); \
6770 }
6771
6772 GEN_VXFORM(vaddubm, 0, 0);
6773 GEN_VXFORM(vadduhm, 0, 1);
6774 GEN_VXFORM(vadduwm, 0, 2);
6775 GEN_VXFORM(vsububm, 0, 16);
6776 GEN_VXFORM(vsubuhm, 0, 17);
6777 GEN_VXFORM(vsubuwm, 0, 18);
6778 GEN_VXFORM(vmaxub, 1, 0);
6779 GEN_VXFORM(vmaxuh, 1, 1);
6780 GEN_VXFORM(vmaxuw, 1, 2);
6781 GEN_VXFORM(vmaxsb, 1, 4);
6782 GEN_VXFORM(vmaxsh, 1, 5);
6783 GEN_VXFORM(vmaxsw, 1, 6);
6784 GEN_VXFORM(vminub, 1, 8);
6785 GEN_VXFORM(vminuh, 1, 9);
6786 GEN_VXFORM(vminuw, 1, 10);
6787 GEN_VXFORM(vminsb, 1, 12);
6788 GEN_VXFORM(vminsh, 1, 13);
6789 GEN_VXFORM(vminsw, 1, 14);
6790 GEN_VXFORM(vavgub, 1, 16);
6791 GEN_VXFORM(vavguh, 1, 17);
6792 GEN_VXFORM(vavguw, 1, 18);
6793 GEN_VXFORM(vavgsb, 1, 20);
6794 GEN_VXFORM(vavgsh, 1, 21);
6795 GEN_VXFORM(vavgsw, 1, 22);
6796 GEN_VXFORM(vmrghb, 6, 0);
6797 GEN_VXFORM(vmrghh, 6, 1);
6798 GEN_VXFORM(vmrghw, 6, 2);
6799 GEN_VXFORM(vmrglb, 6, 4);
6800 GEN_VXFORM(vmrglh, 6, 5);
6801 GEN_VXFORM(vmrglw, 6, 6);
6802 GEN_VXFORM(vmuloub, 4, 0);
6803 GEN_VXFORM(vmulouh, 4, 1);
6804 GEN_VXFORM(vmulosb, 4, 4);
6805 GEN_VXFORM(vmulosh, 4, 5);
6806 GEN_VXFORM(vmuleub, 4, 8);
6807 GEN_VXFORM(vmuleuh, 4, 9);
6808 GEN_VXFORM(vmulesb, 4, 12);
6809 GEN_VXFORM(vmulesh, 4, 13);
6810 GEN_VXFORM(vslb, 2, 4);
6811 GEN_VXFORM(vslh, 2, 5);
6812 GEN_VXFORM(vslw, 2, 6);
6813 GEN_VXFORM(vsrb, 2, 8);
6814 GEN_VXFORM(vsrh, 2, 9);
6815 GEN_VXFORM(vsrw, 2, 10);
6816 GEN_VXFORM(vsrab, 2, 12);
6817 GEN_VXFORM(vsrah, 2, 13);
6818 GEN_VXFORM(vsraw, 2, 14);
6819 GEN_VXFORM(vslo, 6, 16);
6820 GEN_VXFORM(vsro, 6, 17);
6821 GEN_VXFORM(vaddcuw, 0, 6);
6822 GEN_VXFORM(vsubcuw, 0, 22);
6823 GEN_VXFORM_ENV(vaddubs, 0, 8);
6824 GEN_VXFORM_ENV(vadduhs, 0, 9);
6825 GEN_VXFORM_ENV(vadduws, 0, 10);
6826 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6827 GEN_VXFORM_ENV(vaddshs, 0, 13);
6828 GEN_VXFORM_ENV(vaddsws, 0, 14);
6829 GEN_VXFORM_ENV(vsububs, 0, 24);
6830 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6831 GEN_VXFORM_ENV(vsubuws, 0, 26);
6832 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6833 GEN_VXFORM_ENV(vsubshs, 0, 29);
6834 GEN_VXFORM_ENV(vsubsws, 0, 30);
6835 GEN_VXFORM(vrlb, 2, 0);
6836 GEN_VXFORM(vrlh, 2, 1);
6837 GEN_VXFORM(vrlw, 2, 2);
6838 GEN_VXFORM(vsl, 2, 7);
6839 GEN_VXFORM(vsr, 2, 11);
6840 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6841 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6842 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6843 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6844 GEN_VXFORM_ENV(vpkshus, 7, 4);
6845 GEN_VXFORM_ENV(vpkswus, 7, 5);
6846 GEN_VXFORM_ENV(vpkshss, 7, 6);
6847 GEN_VXFORM_ENV(vpkswss, 7, 7);
6848 GEN_VXFORM(vpkpx, 7, 12);
6849 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6850 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6851 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6852 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6853 GEN_VXFORM_ENV(vsumsws, 4, 30);
6854 GEN_VXFORM_ENV(vaddfp, 5, 0);
6855 GEN_VXFORM_ENV(vsubfp, 5, 1);
6856 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6857 GEN_VXFORM_ENV(vminfp, 5, 17);
6858
6859 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6860 static void glue(gen_, name)(DisasContext *ctx) \
6861 { \
6862 TCGv_ptr ra, rb, rd; \
6863 if (unlikely(!ctx->altivec_enabled)) { \
6864 gen_exception(ctx, POWERPC_EXCP_VPU); \
6865 return; \
6866 } \
6867 ra = gen_avr_ptr(rA(ctx->opcode)); \
6868 rb = gen_avr_ptr(rB(ctx->opcode)); \
6869 rd = gen_avr_ptr(rD(ctx->opcode)); \
6870 gen_helper_##opname(cpu_env, rd, ra, rb); \
6871 tcg_temp_free_ptr(ra); \
6872 tcg_temp_free_ptr(rb); \
6873 tcg_temp_free_ptr(rd); \
6874 }
6875
6876 #define GEN_VXRFORM(name, opc2, opc3) \
6877 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6878 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6879
6880 GEN_VXRFORM(vcmpequb, 3, 0)
6881 GEN_VXRFORM(vcmpequh, 3, 1)
6882 GEN_VXRFORM(vcmpequw, 3, 2)
6883 GEN_VXRFORM(vcmpgtsb, 3, 12)
6884 GEN_VXRFORM(vcmpgtsh, 3, 13)
6885 GEN_VXRFORM(vcmpgtsw, 3, 14)
6886 GEN_VXRFORM(vcmpgtub, 3, 8)
6887 GEN_VXRFORM(vcmpgtuh, 3, 9)
6888 GEN_VXRFORM(vcmpgtuw, 3, 10)
6889 GEN_VXRFORM(vcmpeqfp, 3, 3)
6890 GEN_VXRFORM(vcmpgefp, 3, 7)
6891 GEN_VXRFORM(vcmpgtfp, 3, 11)
6892 GEN_VXRFORM(vcmpbfp, 3, 15)
6893
6894 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6895 static void glue(gen_, name)(DisasContext *ctx) \
6896 { \
6897 TCGv_ptr rd; \
6898 TCGv_i32 simm; \
6899 if (unlikely(!ctx->altivec_enabled)) { \
6900 gen_exception(ctx, POWERPC_EXCP_VPU); \
6901 return; \
6902 } \
6903 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6904 rd = gen_avr_ptr(rD(ctx->opcode)); \
6905 gen_helper_##name (rd, simm); \
6906 tcg_temp_free_i32(simm); \
6907 tcg_temp_free_ptr(rd); \
6908 }
6909
6910 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6911 GEN_VXFORM_SIMM(vspltish, 6, 13);
6912 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6913
6914 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6915 static void glue(gen_, name)(DisasContext *ctx) \
6916 { \
6917 TCGv_ptr rb, rd; \
6918 if (unlikely(!ctx->altivec_enabled)) { \
6919 gen_exception(ctx, POWERPC_EXCP_VPU); \
6920 return; \
6921 } \
6922 rb = gen_avr_ptr(rB(ctx->opcode)); \
6923 rd = gen_avr_ptr(rD(ctx->opcode)); \
6924 gen_helper_##name (rd, rb); \
6925 tcg_temp_free_ptr(rb); \
6926 tcg_temp_free_ptr(rd); \
6927 }
6928
6929 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6930 static void glue(gen_, name)(DisasContext *ctx) \
6931 { \
6932 TCGv_ptr rb, rd; \
6933 \
6934 if (unlikely(!ctx->altivec_enabled)) { \
6935 gen_exception(ctx, POWERPC_EXCP_VPU); \
6936 return; \
6937 } \
6938 rb = gen_avr_ptr(rB(ctx->opcode)); \
6939 rd = gen_avr_ptr(rD(ctx->opcode)); \
6940 gen_helper_##name(cpu_env, rd, rb); \
6941 tcg_temp_free_ptr(rb); \
6942 tcg_temp_free_ptr(rd); \
6943 }
6944
6945 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6946 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6947 GEN_VXFORM_NOA(vupklsb, 7, 10);
6948 GEN_VXFORM_NOA(vupklsh, 7, 11);
6949 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6950 GEN_VXFORM_NOA(vupklpx, 7, 15);
6951 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6952 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6953 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6954 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6955 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6956 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6957 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6958 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6959
6960 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6961 static void glue(gen_, name)(DisasContext *ctx) \
6962 { \
6963 TCGv_ptr rd; \
6964 TCGv_i32 simm; \
6965 if (unlikely(!ctx->altivec_enabled)) { \
6966 gen_exception(ctx, POWERPC_EXCP_VPU); \
6967 return; \
6968 } \
6969 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6970 rd = gen_avr_ptr(rD(ctx->opcode)); \
6971 gen_helper_##name (rd, simm); \
6972 tcg_temp_free_i32(simm); \
6973 tcg_temp_free_ptr(rd); \
6974 }
6975
6976 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6977 static void glue(gen_, name)(DisasContext *ctx) \
6978 { \
6979 TCGv_ptr rb, rd; \
6980 TCGv_i32 uimm; \
6981 if (unlikely(!ctx->altivec_enabled)) { \
6982 gen_exception(ctx, POWERPC_EXCP_VPU); \
6983 return; \
6984 } \
6985 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6986 rb = gen_avr_ptr(rB(ctx->opcode)); \
6987 rd = gen_avr_ptr(rD(ctx->opcode)); \
6988 gen_helper_##name (rd, rb, uimm); \
6989 tcg_temp_free_i32(uimm); \
6990 tcg_temp_free_ptr(rb); \
6991 tcg_temp_free_ptr(rd); \
6992 }
6993
6994 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6995 static void glue(gen_, name)(DisasContext *ctx) \
6996 { \
6997 TCGv_ptr rb, rd; \
6998 TCGv_i32 uimm; \
6999 \
7000 if (unlikely(!ctx->altivec_enabled)) { \
7001 gen_exception(ctx, POWERPC_EXCP_VPU); \
7002 return; \
7003 } \
7004 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7005 rb = gen_avr_ptr(rB(ctx->opcode)); \
7006 rd = gen_avr_ptr(rD(ctx->opcode)); \
7007 gen_helper_##name(cpu_env, rd, rb, uimm); \
7008 tcg_temp_free_i32(uimm); \
7009 tcg_temp_free_ptr(rb); \
7010 tcg_temp_free_ptr(rd); \
7011 }
7012
7013 GEN_VXFORM_UIMM(vspltb, 6, 8);
7014 GEN_VXFORM_UIMM(vsplth, 6, 9);
7015 GEN_VXFORM_UIMM(vspltw, 6, 10);
7016 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7017 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7018 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7019 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7020
7021 static void gen_vsldoi(DisasContext *ctx)
7022 {
7023 TCGv_ptr ra, rb, rd;
7024 TCGv_i32 sh;
7025 if (unlikely(!ctx->altivec_enabled)) {
7026 gen_exception(ctx, POWERPC_EXCP_VPU);
7027 return;
7028 }
7029 ra = gen_avr_ptr(rA(ctx->opcode));
7030 rb = gen_avr_ptr(rB(ctx->opcode));
7031 rd = gen_avr_ptr(rD(ctx->opcode));
7032 sh = tcg_const_i32(VSH(ctx->opcode));
7033 gen_helper_vsldoi (rd, ra, rb, sh);
7034 tcg_temp_free_ptr(ra);
7035 tcg_temp_free_ptr(rb);
7036 tcg_temp_free_ptr(rd);
7037 tcg_temp_free_i32(sh);
7038 }
7039
7040 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7041 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7042 { \
7043 TCGv_ptr ra, rb, rc, rd; \
7044 if (unlikely(!ctx->altivec_enabled)) { \
7045 gen_exception(ctx, POWERPC_EXCP_VPU); \
7046 return; \
7047 } \
7048 ra = gen_avr_ptr(rA(ctx->opcode)); \
7049 rb = gen_avr_ptr(rB(ctx->opcode)); \
7050 rc = gen_avr_ptr(rC(ctx->opcode)); \
7051 rd = gen_avr_ptr(rD(ctx->opcode)); \
7052 if (Rc(ctx->opcode)) { \
7053 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7054 } else { \
7055 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7056 } \
7057 tcg_temp_free_ptr(ra); \
7058 tcg_temp_free_ptr(rb); \
7059 tcg_temp_free_ptr(rc); \
7060 tcg_temp_free_ptr(rd); \
7061 }
7062
7063 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7064
7065 static void gen_vmladduhm(DisasContext *ctx)
7066 {
7067 TCGv_ptr ra, rb, rc, rd;
7068 if (unlikely(!ctx->altivec_enabled)) {
7069 gen_exception(ctx, POWERPC_EXCP_VPU);
7070 return;
7071 }
7072 ra = gen_avr_ptr(rA(ctx->opcode));
7073 rb = gen_avr_ptr(rB(ctx->opcode));
7074 rc = gen_avr_ptr(rC(ctx->opcode));
7075 rd = gen_avr_ptr(rD(ctx->opcode));
7076 gen_helper_vmladduhm(rd, ra, rb, rc);
7077 tcg_temp_free_ptr(ra);
7078 tcg_temp_free_ptr(rb);
7079 tcg_temp_free_ptr(rc);
7080 tcg_temp_free_ptr(rd);
7081 }
7082
7083 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7084 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7085 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7086 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7087 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7088
7089 /*** VSX extension ***/
7090
7091 static inline TCGv_i64 cpu_vsrh(int n)
7092 {
7093 if (n < 32) {
7094 return cpu_fpr[n];
7095 } else {
7096 return cpu_avrh[n-32];
7097 }
7098 }
7099
7100 static inline TCGv_i64 cpu_vsrl(int n)
7101 {
7102 if (n < 32) {
7103 return cpu_vsr[n];
7104 } else {
7105 return cpu_avrl[n-32];
7106 }
7107 }
7108
7109 #define VSX_LOAD_SCALAR(name, operation) \
7110 static void gen_##name(DisasContext *ctx) \
7111 { \
7112 TCGv EA; \
7113 if (unlikely(!ctx->vsx_enabled)) { \
7114 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7115 return; \
7116 } \
7117 gen_set_access_type(ctx, ACCESS_INT); \
7118 EA = tcg_temp_new(); \
7119 gen_addr_reg_index(ctx, EA); \
7120 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7121 /* NOTE: cpu_vsrl is undefined */ \
7122 tcg_temp_free(EA); \
7123 }
7124
7125 VSX_LOAD_SCALAR(lxsdx, ld64)
7126 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7127 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7128 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7129
7130 static void gen_lxvd2x(DisasContext *ctx)
7131 {
7132 TCGv EA;
7133 if (unlikely(!ctx->vsx_enabled)) {
7134 gen_exception(ctx, POWERPC_EXCP_VSXU);
7135 return;
7136 }
7137 gen_set_access_type(ctx, ACCESS_INT);
7138 EA = tcg_temp_new();
7139 gen_addr_reg_index(ctx, EA);
7140 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7141 tcg_gen_addi_tl(EA, EA, 8);
7142 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7143 tcg_temp_free(EA);
7144 }
7145
7146 static void gen_lxvdsx(DisasContext *ctx)
7147 {
7148 TCGv EA;
7149 if (unlikely(!ctx->vsx_enabled)) {
7150 gen_exception(ctx, POWERPC_EXCP_VSXU);
7151 return;
7152 }
7153 gen_set_access_type(ctx, ACCESS_INT);
7154 EA = tcg_temp_new();
7155 gen_addr_reg_index(ctx, EA);
7156 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7157 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7158 tcg_temp_free(EA);
7159 }
7160
7161 static void gen_lxvw4x(DisasContext *ctx)
7162 {
7163 TCGv EA;
7164 TCGv_i64 tmp;
7165 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7166 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7167 if (unlikely(!ctx->vsx_enabled)) {
7168 gen_exception(ctx, POWERPC_EXCP_VSXU);
7169 return;
7170 }
7171 gen_set_access_type(ctx, ACCESS_INT);
7172 EA = tcg_temp_new();
7173 tmp = tcg_temp_new_i64();
7174
7175 gen_addr_reg_index(ctx, EA);
7176 gen_qemu_ld32u_i64(ctx, tmp, EA);
7177 tcg_gen_addi_tl(EA, EA, 4);
7178 gen_qemu_ld32u_i64(ctx, xth, EA);
7179 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7180
7181 tcg_gen_addi_tl(EA, EA, 4);
7182 gen_qemu_ld32u_i64(ctx, tmp, EA);
7183 tcg_gen_addi_tl(EA, EA, 4);
7184 gen_qemu_ld32u_i64(ctx, xtl, EA);
7185 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7186
7187 tcg_temp_free(EA);
7188 tcg_temp_free_i64(tmp);
7189 }
7190
7191 #define VSX_STORE_SCALAR(name, operation) \
7192 static void gen_##name(DisasContext *ctx) \
7193 { \
7194 TCGv EA; \
7195 if (unlikely(!ctx->vsx_enabled)) { \
7196 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7197 return; \
7198 } \
7199 gen_set_access_type(ctx, ACCESS_INT); \
7200 EA = tcg_temp_new(); \
7201 gen_addr_reg_index(ctx, EA); \
7202 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7203 tcg_temp_free(EA); \
7204 }
7205
7206 VSX_STORE_SCALAR(stxsdx, st64)
7207 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7208 VSX_STORE_SCALAR(stxsspx, st32fs)
7209
7210 static void gen_stxvd2x(DisasContext *ctx)
7211 {
7212 TCGv EA;
7213 if (unlikely(!ctx->vsx_enabled)) {
7214 gen_exception(ctx, POWERPC_EXCP_VSXU);
7215 return;
7216 }
7217 gen_set_access_type(ctx, ACCESS_INT);
7218 EA = tcg_temp_new();
7219 gen_addr_reg_index(ctx, EA);
7220 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7221 tcg_gen_addi_tl(EA, EA, 8);
7222 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7223 tcg_temp_free(EA);
7224 }
7225
7226 static void gen_stxvw4x(DisasContext *ctx)
7227 {
7228 TCGv_i64 tmp;
7229 TCGv EA;
7230 if (unlikely(!ctx->vsx_enabled)) {
7231 gen_exception(ctx, POWERPC_EXCP_VSXU);
7232 return;
7233 }
7234 gen_set_access_type(ctx, ACCESS_INT);
7235 EA = tcg_temp_new();
7236 gen_addr_reg_index(ctx, EA);
7237 tmp = tcg_temp_new_i64();
7238
7239 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7240 gen_qemu_st32_i64(ctx, tmp, EA);
7241 tcg_gen_addi_tl(EA, EA, 4);
7242 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7243
7244 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7245 tcg_gen_addi_tl(EA, EA, 4);
7246 gen_qemu_st32_i64(ctx, tmp, EA);
7247 tcg_gen_addi_tl(EA, EA, 4);
7248 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7249
7250 tcg_temp_free(EA);
7251 tcg_temp_free_i64(tmp);
7252 }
7253
7254 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7255 static void gen_##name(DisasContext *ctx) \
7256 { \
7257 if (xS(ctx->opcode) < 32) { \
7258 if (unlikely(!ctx->fpu_enabled)) { \
7259 gen_exception(ctx, POWERPC_EXCP_FPU); \
7260 return; \
7261 } \
7262 } else { \
7263 if (unlikely(!ctx->altivec_enabled)) { \
7264 gen_exception(ctx, POWERPC_EXCP_VPU); \
7265 return; \
7266 } \
7267 } \
7268 TCGv_i64 tmp = tcg_temp_new_i64(); \
7269 tcg_gen_##tcgop1(tmp, source); \
7270 tcg_gen_##tcgop2(target, tmp); \
7271 tcg_temp_free_i64(tmp); \
7272 }
7273
7274
7275 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7276 cpu_vsrh(xS(ctx->opcode)))
7277 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7278 cpu_gpr[rA(ctx->opcode)])
7279 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7280 cpu_gpr[rA(ctx->opcode)])
7281
7282 #if defined(TARGET_PPC64)
7283 #define MV_VSRD(name, target, source) \
7284 static void gen_##name(DisasContext *ctx) \
7285 { \
7286 if (xS(ctx->opcode) < 32) { \
7287 if (unlikely(!ctx->fpu_enabled)) { \
7288 gen_exception(ctx, POWERPC_EXCP_FPU); \
7289 return; \
7290 } \
7291 } else { \
7292 if (unlikely(!ctx->altivec_enabled)) { \
7293 gen_exception(ctx, POWERPC_EXCP_VPU); \
7294 return; \
7295 } \
7296 } \
7297 tcg_gen_mov_i64(target, source); \
7298 }
7299
7300 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7301 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7302
7303 #endif
7304
7305 static void gen_xxpermdi(DisasContext *ctx)
7306 {
7307 if (unlikely(!ctx->vsx_enabled)) {
7308 gen_exception(ctx, POWERPC_EXCP_VSXU);
7309 return;
7310 }
7311
7312 if ((DM(ctx->opcode) & 2) == 0) {
7313 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7314 } else {
7315 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7316 }
7317 if ((DM(ctx->opcode) & 1) == 0) {
7318 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7319 } else {
7320 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7321 }
7322 }
7323
7324 #define OP_ABS 1
7325 #define OP_NABS 2
7326 #define OP_NEG 3
7327 #define OP_CPSGN 4
7328 #define SGN_MASK_DP 0x8000000000000000ul
7329 #define SGN_MASK_SP 0x8000000080000000ul
7330
7331 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7332 static void glue(gen_, name)(DisasContext * ctx) \
7333 { \
7334 TCGv_i64 xb, sgm; \
7335 if (unlikely(!ctx->vsx_enabled)) { \
7336 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7337 return; \
7338 } \
7339 xb = tcg_temp_new_i64(); \
7340 sgm = tcg_temp_new_i64(); \
7341 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7342 tcg_gen_movi_i64(sgm, sgn_mask); \
7343 switch (op) { \
7344 case OP_ABS: { \
7345 tcg_gen_andc_i64(xb, xb, sgm); \
7346 break; \
7347 } \
7348 case OP_NABS: { \
7349 tcg_gen_or_i64(xb, xb, sgm); \
7350 break; \
7351 } \
7352 case OP_NEG: { \
7353 tcg_gen_xor_i64(xb, xb, sgm); \
7354 break; \
7355 } \
7356 case OP_CPSGN: { \
7357 TCGv_i64 xa = tcg_temp_new_i64(); \
7358 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7359 tcg_gen_and_i64(xa, xa, sgm); \
7360 tcg_gen_andc_i64(xb, xb, sgm); \
7361 tcg_gen_or_i64(xb, xb, xa); \
7362 tcg_temp_free_i64(xa); \
7363 break; \
7364 } \
7365 } \
7366 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7367 tcg_temp_free_i64(xb); \
7368 tcg_temp_free_i64(sgm); \
7369 }
7370
7371 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7372 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7373 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7374 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7375
7376 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7377 static void glue(gen_, name)(DisasContext * ctx) \
7378 { \
7379 TCGv_i64 xbh, xbl, sgm; \
7380 if (unlikely(!ctx->vsx_enabled)) { \
7381 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7382 return; \
7383 } \
7384 xbh = tcg_temp_new_i64(); \
7385 xbl = tcg_temp_new_i64(); \
7386 sgm = tcg_temp_new_i64(); \
7387 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7388 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7389 tcg_gen_movi_i64(sgm, sgn_mask); \
7390 switch (op) { \
7391 case OP_ABS: { \
7392 tcg_gen_andc_i64(xbh, xbh, sgm); \
7393 tcg_gen_andc_i64(xbl, xbl, sgm); \
7394 break; \
7395 } \
7396 case OP_NABS: { \
7397 tcg_gen_or_i64(xbh, xbh, sgm); \
7398 tcg_gen_or_i64(xbl, xbl, sgm); \
7399 break; \
7400 } \
7401 case OP_NEG: { \
7402 tcg_gen_xor_i64(xbh, xbh, sgm); \
7403 tcg_gen_xor_i64(xbl, xbl, sgm); \
7404 break; \
7405 } \
7406 case OP_CPSGN: { \
7407 TCGv_i64 xah = tcg_temp_new_i64(); \
7408 TCGv_i64 xal = tcg_temp_new_i64(); \
7409 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7410 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7411 tcg_gen_and_i64(xah, xah, sgm); \
7412 tcg_gen_and_i64(xal, xal, sgm); \
7413 tcg_gen_andc_i64(xbh, xbh, sgm); \
7414 tcg_gen_andc_i64(xbl, xbl, sgm); \
7415 tcg_gen_or_i64(xbh, xbh, xah); \
7416 tcg_gen_or_i64(xbl, xbl, xal); \
7417 tcg_temp_free_i64(xah); \
7418 tcg_temp_free_i64(xal); \
7419 break; \
7420 } \
7421 } \
7422 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7423 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7424 tcg_temp_free_i64(xbh); \
7425 tcg_temp_free_i64(xbl); \
7426 tcg_temp_free_i64(sgm); \
7427 }
7428
7429 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7430 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7431 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7432 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7433 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7434 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7435 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7436 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7437
7438 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7439 static void gen_##name(DisasContext * ctx) \
7440 { \
7441 TCGv_i32 opc; \
7442 if (unlikely(!ctx->vsx_enabled)) { \
7443 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7444 return; \
7445 } \
7446 /* NIP cannot be restored if the memory exception comes from an helper */ \
7447 gen_update_nip(ctx, ctx->nip - 4); \
7448 opc = tcg_const_i32(ctx->opcode); \
7449 gen_helper_##name(cpu_env, opc); \
7450 tcg_temp_free_i32(opc); \
7451 }
7452
7453 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7454 static void gen_##name(DisasContext * ctx) \
7455 { \
7456 if (unlikely(!ctx->vsx_enabled)) { \
7457 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7458 return; \
7459 } \
7460 /* NIP cannot be restored if the exception comes */ \
7461 /* from a helper. */ \
7462 gen_update_nip(ctx, ctx->nip - 4); \
7463 \
7464 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7465 cpu_vsrh(xB(ctx->opcode))); \
7466 }
7467
7468 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7469 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7470 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7471 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7472 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7473 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7474 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7475 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7476 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7477 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7478 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7479 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7480 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7481 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7482 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7483 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7484 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7485 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7486 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7487 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7488 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7489 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7490 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
7491 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7492 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
7493 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7494 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7495 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7496 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7497 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7498 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
7499 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7500 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7501 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7502 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7503 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
7504 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
7505
7506 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
7507 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
7508 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
7509 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
7510 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
7511 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
7512 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
7513 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
7514 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
7515 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
7516 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
7517 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
7518 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
7519 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
7520 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
7521 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
7522 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
7523
7524 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
7525 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
7526 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
7527 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
7528 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
7529 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
7530 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
7531 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
7532 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
7533 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
7534 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
7535 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
7536 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
7537 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
7538 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
7539 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
7540 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
7541 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
7542 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
7543 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
7544 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
7545 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
7546 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
7547 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
7548 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
7549 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
7550 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
7551 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
7552 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
7553 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
7554 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
7555 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
7556 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
7557 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
7558 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
7559 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
7560
7561 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
7562 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
7563 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
7564 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
7565 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
7566 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
7567 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
7568 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
7569 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
7570 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
7571 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
7572 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
7573 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
7574 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
7575 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
7576 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
7577 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
7578 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
7579 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
7580 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
7581 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
7582 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
7583 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
7584 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
7585 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
7586 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
7587 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
7588 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
7589 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
7590 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
7591 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
7592 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
7593 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
7594 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
7595 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
7596 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
7597
7598 #define VSX_LOGICAL(name, tcg_op) \
7599 static void glue(gen_, name)(DisasContext * ctx) \
7600 { \
7601 if (unlikely(!ctx->vsx_enabled)) { \
7602 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7603 return; \
7604 } \
7605 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
7606 cpu_vsrh(xB(ctx->opcode))); \
7607 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
7608 cpu_vsrl(xB(ctx->opcode))); \
7609 }
7610
7611 VSX_LOGICAL(xxland, tcg_gen_and_i64)
7612 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
7613 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
7614 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
7615 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
7616 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
7617 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
7618 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
7619
7620 #define VSX_XXMRG(name, high) \
7621 static void glue(gen_, name)(DisasContext * ctx) \
7622 { \
7623 TCGv_i64 a0, a1, b0, b1; \
7624 if (unlikely(!ctx->vsx_enabled)) { \
7625 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7626 return; \
7627 } \
7628 a0 = tcg_temp_new_i64(); \
7629 a1 = tcg_temp_new_i64(); \
7630 b0 = tcg_temp_new_i64(); \
7631 b1 = tcg_temp_new_i64(); \
7632 if (high) { \
7633 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
7634 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
7635 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
7636 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
7637 } else { \
7638 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
7639 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
7640 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
7641 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
7642 } \
7643 tcg_gen_shri_i64(a0, a0, 32); \
7644 tcg_gen_shri_i64(b0, b0, 32); \
7645 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
7646 b0, a0, 32, 32); \
7647 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
7648 b1, a1, 32, 32); \
7649 tcg_temp_free_i64(a0); \
7650 tcg_temp_free_i64(a1); \
7651 tcg_temp_free_i64(b0); \
7652 tcg_temp_free_i64(b1); \
7653 }
7654
7655 VSX_XXMRG(xxmrghw, 1)
7656 VSX_XXMRG(xxmrglw, 0)
7657
7658 static void gen_xxsel(DisasContext * ctx)
7659 {
7660 TCGv_i64 a, b, c;
7661 if (unlikely(!ctx->vsx_enabled)) {
7662 gen_exception(ctx, POWERPC_EXCP_VSXU);
7663 return;
7664 }
7665 a = tcg_temp_new_i64();
7666 b = tcg_temp_new_i64();
7667 c = tcg_temp_new_i64();
7668
7669 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
7670 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
7671 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
7672
7673 tcg_gen_and_i64(b, b, c);
7674 tcg_gen_andc_i64(a, a, c);
7675 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
7676
7677 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
7678 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
7679 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
7680
7681 tcg_gen_and_i64(b, b, c);
7682 tcg_gen_andc_i64(a, a, c);
7683 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
7684
7685 tcg_temp_free_i64(a);
7686 tcg_temp_free_i64(b);
7687 tcg_temp_free_i64(c);
7688 }
7689
7690 static void gen_xxspltw(DisasContext *ctx)
7691 {
7692 TCGv_i64 b, b2;
7693 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
7694 cpu_vsrl(xB(ctx->opcode)) :
7695 cpu_vsrh(xB(ctx->opcode));
7696
7697 if (unlikely(!ctx->vsx_enabled)) {
7698 gen_exception(ctx, POWERPC_EXCP_VSXU);
7699 return;
7700 }
7701
7702 b = tcg_temp_new_i64();
7703 b2 = tcg_temp_new_i64();
7704
7705 if (UIM(ctx->opcode) & 1) {
7706 tcg_gen_ext32u_i64(b, vsr);
7707 } else {
7708 tcg_gen_shri_i64(b, vsr, 32);
7709 }
7710
7711 tcg_gen_shli_i64(b2, b, 32);
7712 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
7713 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7714
7715 tcg_temp_free_i64(b);
7716 tcg_temp_free_i64(b2);
7717 }
7718
7719 static void gen_xxsldwi(DisasContext *ctx)
7720 {
7721 TCGv_i64 xth, xtl;
7722 if (unlikely(!ctx->vsx_enabled)) {
7723 gen_exception(ctx, POWERPC_EXCP_VSXU);
7724 return;
7725 }
7726 xth = tcg_temp_new_i64();
7727 xtl = tcg_temp_new_i64();
7728
7729 switch (SHW(ctx->opcode)) {
7730 case 0: {
7731 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
7732 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
7733 break;
7734 }
7735 case 1: {
7736 TCGv_i64 t0 = tcg_temp_new_i64();
7737 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
7738 tcg_gen_shli_i64(xth, xth, 32);
7739 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
7740 tcg_gen_shri_i64(t0, t0, 32);
7741 tcg_gen_or_i64(xth, xth, t0);
7742 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
7743 tcg_gen_shli_i64(xtl, xtl, 32);
7744 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
7745 tcg_gen_shri_i64(t0, t0, 32);
7746 tcg_gen_or_i64(xtl, xtl, t0);
7747 tcg_temp_free_i64(t0);
7748 break;
7749 }
7750 case 2: {
7751 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
7752 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
7753 break;
7754 }
7755 case 3: {
7756 TCGv_i64 t0 = tcg_temp_new_i64();
7757 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
7758 tcg_gen_shli_i64(xth, xth, 32);
7759 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
7760 tcg_gen_shri_i64(t0, t0, 32);
7761 tcg_gen_or_i64(xth, xth, t0);
7762 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
7763 tcg_gen_shli_i64(xtl, xtl, 32);
7764 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
7765 tcg_gen_shri_i64(t0, t0, 32);
7766 tcg_gen_or_i64(xtl, xtl, t0);
7767 tcg_temp_free_i64(t0);
7768 break;
7769 }
7770 }
7771
7772 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
7773 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
7774
7775 tcg_temp_free_i64(xth);
7776 tcg_temp_free_i64(xtl);
7777 }
7778
7779
7780 /*** SPE extension ***/
7781 /* Register moves */
7782
7783 static inline void gen_evmra(DisasContext *ctx)
7784 {
7785
7786 if (unlikely(!ctx->spe_enabled)) {
7787 gen_exception(ctx, POWERPC_EXCP_SPEU);
7788 return;
7789 }
7790
7791 #if defined(TARGET_PPC64)
7792 /* rD := rA */
7793 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7794
7795 /* spe_acc := rA */
7796 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
7797 cpu_env,
7798 offsetof(CPUPPCState, spe_acc));
7799 #else
7800 TCGv_i64 tmp = tcg_temp_new_i64();
7801
7802 /* tmp := rA_lo + rA_hi << 32 */
7803 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7804
7805 /* spe_acc := tmp */
7806 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7807 tcg_temp_free_i64(tmp);
7808
7809 /* rD := rA */
7810 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7811 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7812 #endif
7813 }
7814
7815 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
7816 {
7817 #if defined(TARGET_PPC64)
7818 tcg_gen_mov_i64(t, cpu_gpr[reg]);
7819 #else
7820 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
7821 #endif
7822 }
7823
7824 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
7825 {
7826 #if defined(TARGET_PPC64)
7827 tcg_gen_mov_i64(cpu_gpr[reg], t);
7828 #else
7829 TCGv_i64 tmp = tcg_temp_new_i64();
7830 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
7831 tcg_gen_shri_i64(tmp, t, 32);
7832 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
7833 tcg_temp_free_i64(tmp);
7834 #endif
7835 }
7836
7837 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
7838 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7839 { \
7840 if (Rc(ctx->opcode)) \
7841 gen_##name1(ctx); \
7842 else \
7843 gen_##name0(ctx); \
7844 }
7845
7846 /* Handler for undefined SPE opcodes */
7847 static inline void gen_speundef(DisasContext *ctx)
7848 {
7849 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7850 }
7851
7852 /* SPE logic */
7853 #if defined(TARGET_PPC64)
7854 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
7855 static inline void gen_##name(DisasContext *ctx) \
7856 { \
7857 if (unlikely(!ctx->spe_enabled)) { \
7858 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7859 return; \
7860 } \
7861 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7862 cpu_gpr[rB(ctx->opcode)]); \
7863 }
7864 #else
7865 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
7866 static inline void gen_##name(DisasContext *ctx) \
7867 { \
7868 if (unlikely(!ctx->spe_enabled)) { \
7869 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7870 return; \
7871 } \
7872 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7873 cpu_gpr[rB(ctx->opcode)]); \
7874 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7875 cpu_gprh[rB(ctx->opcode)]); \
7876 }
7877 #endif
7878
7879 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
7880 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
7881 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
7882 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
7883 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
7884 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
7885 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
7886 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
7887
7888 /* SPE logic immediate */
7889 #if defined(TARGET_PPC64)
7890 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
7891 static inline void gen_##name(DisasContext *ctx) \
7892 { \
7893 if (unlikely(!ctx->spe_enabled)) { \
7894 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7895 return; \
7896 } \
7897 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7898 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7899 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7900 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7901 tcg_opi(t0, t0, rB(ctx->opcode)); \
7902 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7903 tcg_gen_trunc_i64_i32(t1, t2); \
7904 tcg_temp_free_i64(t2); \
7905 tcg_opi(t1, t1, rB(ctx->opcode)); \
7906 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7907 tcg_temp_free_i32(t0); \
7908 tcg_temp_free_i32(t1); \
7909 }
7910 #else
7911 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
7912 static inline void gen_##name(DisasContext *ctx) \
7913 { \
7914 if (unlikely(!ctx->spe_enabled)) { \
7915 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7916 return; \
7917 } \
7918 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7919 rB(ctx->opcode)); \
7920 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7921 rB(ctx->opcode)); \
7922 }
7923 #endif
7924 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
7925 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
7926 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
7927 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
7928
7929 /* SPE arithmetic */
7930 #if defined(TARGET_PPC64)
7931 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7932 static inline void gen_##name(DisasContext *ctx) \
7933 { \
7934 if (unlikely(!ctx->spe_enabled)) { \
7935 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7936 return; \
7937 } \
7938 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7939 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7940 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7941 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7942 tcg_op(t0, t0); \
7943 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7944 tcg_gen_trunc_i64_i32(t1, t2); \
7945 tcg_temp_free_i64(t2); \
7946 tcg_op(t1, t1); \
7947 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7948 tcg_temp_free_i32(t0); \
7949 tcg_temp_free_i32(t1); \
7950 }
7951 #else
7952 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7953 static inline void gen_##name(DisasContext *ctx) \
7954 { \
7955 if (unlikely(!ctx->spe_enabled)) { \
7956 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7957 return; \
7958 } \
7959 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
7960 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
7961 }
7962 #endif
7963
7964 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
7965 {
7966 int l1 = gen_new_label();
7967 int l2 = gen_new_label();
7968
7969 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
7970 tcg_gen_neg_i32(ret, arg1);
7971 tcg_gen_br(l2);
7972 gen_set_label(l1);
7973 tcg_gen_mov_i32(ret, arg1);
7974 gen_set_label(l2);
7975 }
7976 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
7977 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
7978 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
7979 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
7980 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
7981 {
7982 tcg_gen_addi_i32(ret, arg1, 0x8000);
7983 tcg_gen_ext16u_i32(ret, ret);
7984 }
7985 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
7986 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
7987 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
7988
7989 #if defined(TARGET_PPC64)
7990 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7991 static inline void gen_##name(DisasContext *ctx) \
7992 { \
7993 if (unlikely(!ctx->spe_enabled)) { \
7994 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7995 return; \
7996 } \
7997 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7998 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7999 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
8000 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
8001 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8002 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
8003 tcg_op(t0, t0, t2); \
8004 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
8005 tcg_gen_trunc_i64_i32(t1, t3); \
8006 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
8007 tcg_gen_trunc_i64_i32(t2, t3); \
8008 tcg_temp_free_i64(t3); \
8009 tcg_op(t1, t1, t2); \
8010 tcg_temp_free_i32(t2); \
8011 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
8012 tcg_temp_free_i32(t0); \
8013 tcg_temp_free_i32(t1); \
8014 }
8015 #else
8016 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8017 static inline void gen_##name(DisasContext *ctx) \
8018 { \
8019 if (unlikely(!ctx->spe_enabled)) { \
8020 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8021 return; \
8022 } \
8023 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8024 cpu_gpr[rB(ctx->opcode)]); \
8025 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8026 cpu_gprh[rB(ctx->opcode)]); \
8027 }
8028 #endif
8029
8030 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8031 {
8032 TCGv_i32 t0;
8033 int l1, l2;
8034
8035 l1 = gen_new_label();
8036 l2 = gen_new_label();
8037 t0 = tcg_temp_local_new_i32();
8038 /* No error here: 6 bits are used */
8039 tcg_gen_andi_i32(t0, arg2, 0x3F);
8040 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8041 tcg_gen_shr_i32(ret, arg1, t0);
8042 tcg_gen_br(l2);
8043 gen_set_label(l1);
8044 tcg_gen_movi_i32(ret, 0);
8045 gen_set_label(l2);
8046 tcg_temp_free_i32(t0);
8047 }
8048 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8049 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8050 {
8051 TCGv_i32 t0;
8052 int l1, l2;
8053
8054 l1 = gen_new_label();
8055 l2 = gen_new_label();
8056 t0 = tcg_temp_local_new_i32();
8057 /* No error here: 6 bits are used */
8058 tcg_gen_andi_i32(t0, arg2, 0x3F);
8059 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8060 tcg_gen_sar_i32(ret, arg1, t0);
8061 tcg_gen_br(l2);
8062 gen_set_label(l1);
8063 tcg_gen_movi_i32(ret, 0);
8064 gen_set_label(l2);
8065 tcg_temp_free_i32(t0);
8066 }
8067 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8068 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8069 {
8070 TCGv_i32 t0;
8071 int l1, l2;
8072
8073 l1 = gen_new_label();
8074 l2 = gen_new_label();
8075 t0 = tcg_temp_local_new_i32();
8076 /* No error here: 6 bits are used */
8077 tcg_gen_andi_i32(t0, arg2, 0x3F);
8078 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8079 tcg_gen_shl_i32(ret, arg1, t0);
8080 tcg_gen_br(l2);
8081 gen_set_label(l1);
8082 tcg_gen_movi_i32(ret, 0);
8083 gen_set_label(l2);
8084 tcg_temp_free_i32(t0);
8085 }
8086 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8087 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8088 {
8089 TCGv_i32 t0 = tcg_temp_new_i32();
8090 tcg_gen_andi_i32(t0, arg2, 0x1F);
8091 tcg_gen_rotl_i32(ret, arg1, t0);
8092 tcg_temp_free_i32(t0);
8093 }
8094 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8095 static inline void gen_evmergehi(DisasContext *ctx)
8096 {
8097 if (unlikely(!ctx->spe_enabled)) {
8098 gen_exception(ctx, POWERPC_EXCP_SPEU);
8099 return;
8100 }
8101 #if defined(TARGET_PPC64)
8102 TCGv t0 = tcg_temp_new();
8103 TCGv t1 = tcg_temp_new();
8104 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
8105 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
8106 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8107 tcg_temp_free(t0);
8108 tcg_temp_free(t1);
8109 #else
8110 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8111 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8112 #endif
8113 }
8114 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8115 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8116 {
8117 tcg_gen_sub_i32(ret, arg2, arg1);
8118 }
8119 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8120
8121 /* SPE arithmetic immediate */
8122 #if defined(TARGET_PPC64)
8123 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8124 static inline void gen_##name(DisasContext *ctx) \
8125 { \
8126 if (unlikely(!ctx->spe_enabled)) { \
8127 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8128 return; \
8129 } \
8130 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8131 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8132 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8133 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8134 tcg_op(t0, t0, rA(ctx->opcode)); \
8135 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
8136 tcg_gen_trunc_i64_i32(t1, t2); \
8137 tcg_temp_free_i64(t2); \
8138 tcg_op(t1, t1, rA(ctx->opcode)); \
8139 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
8140 tcg_temp_free_i32(t0); \
8141 tcg_temp_free_i32(t1); \
8142 }
8143 #else
8144 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8145 static inline void gen_##name(DisasContext *ctx) \
8146 { \
8147 if (unlikely(!ctx->spe_enabled)) { \
8148 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8149 return; \
8150 } \
8151 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
8152 rA(ctx->opcode)); \
8153 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
8154 rA(ctx->opcode)); \
8155 }
8156 #endif
8157 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8158 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8159
8160 /* SPE comparison */
8161 #if defined(TARGET_PPC64)
8162 #define GEN_SPEOP_COMP(name, tcg_cond) \
8163 static inline void gen_##name(DisasContext *ctx) \
8164 { \
8165 if (unlikely(!ctx->spe_enabled)) { \
8166 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8167 return; \
8168 } \
8169 int l1 = gen_new_label(); \
8170 int l2 = gen_new_label(); \
8171 int l3 = gen_new_label(); \
8172 int l4 = gen_new_label(); \
8173 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8174 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8175 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8176 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8177 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8178 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
8179 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8180 tcg_gen_br(l2); \
8181 gen_set_label(l1); \
8182 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8183 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8184 gen_set_label(l2); \
8185 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
8186 tcg_gen_trunc_i64_i32(t0, t2); \
8187 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
8188 tcg_gen_trunc_i64_i32(t1, t2); \
8189 tcg_temp_free_i64(t2); \
8190 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
8191 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8192 ~(CRF_CH | CRF_CH_AND_CL)); \
8193 tcg_gen_br(l4); \
8194 gen_set_label(l3); \
8195 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8196 CRF_CH | CRF_CH_OR_CL); \
8197 gen_set_label(l4); \
8198 tcg_temp_free_i32(t0); \
8199 tcg_temp_free_i32(t1); \
8200 }
8201 #else
8202 #define GEN_SPEOP_COMP(name, tcg_cond) \
8203 static inline void gen_##name(DisasContext *ctx) \
8204 { \
8205 if (unlikely(!ctx->spe_enabled)) { \
8206 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8207 return; \
8208 } \
8209 int l1 = gen_new_label(); \
8210 int l2 = gen_new_label(); \
8211 int l3 = gen_new_label(); \
8212 int l4 = gen_new_label(); \
8213 \
8214 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8215 cpu_gpr[rB(ctx->opcode)], l1); \
8216 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
8217 tcg_gen_br(l2); \
8218 gen_set_label(l1); \
8219 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8220 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8221 gen_set_label(l2); \
8222 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8223 cpu_gprh[rB(ctx->opcode)], l3); \
8224 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8225 ~(CRF_CH | CRF_CH_AND_CL)); \
8226 tcg_gen_br(l4); \
8227 gen_set_label(l3); \
8228 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8229 CRF_CH | CRF_CH_OR_CL); \
8230 gen_set_label(l4); \
8231 }
8232 #endif
8233 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8234 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8235 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8236 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8237 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8238
8239 /* SPE misc */
8240 static inline void gen_brinc(DisasContext *ctx)
8241 {
8242 /* Note: brinc is usable even if SPE is disabled */
8243 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8244 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8245 }
8246 static inline void gen_evmergelo(DisasContext *ctx)
8247 {
8248 if (unlikely(!ctx->spe_enabled)) {
8249 gen_exception(ctx, POWERPC_EXCP_SPEU);
8250 return;
8251 }
8252 #if defined(TARGET_PPC64)
8253 TCGv t0 = tcg_temp_new();
8254 TCGv t1 = tcg_temp_new();
8255 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
8256 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
8257 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8258 tcg_temp_free(t0);
8259 tcg_temp_free(t1);
8260 #else
8261 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8262 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8263 #endif
8264 }
8265 static inline void gen_evmergehilo(DisasContext *ctx)
8266 {
8267 if (unlikely(!ctx->spe_enabled)) {
8268 gen_exception(ctx, POWERPC_EXCP_SPEU);
8269 return;
8270 }
8271 #if defined(TARGET_PPC64)
8272 TCGv t0 = tcg_temp_new();
8273 TCGv t1 = tcg_temp_new();
8274 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
8275 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
8276 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8277 tcg_temp_free(t0);
8278 tcg_temp_free(t1);
8279 #else
8280 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8281 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8282 #endif
8283 }
8284 static inline void gen_evmergelohi(DisasContext *ctx)
8285 {
8286 if (unlikely(!ctx->spe_enabled)) {
8287 gen_exception(ctx, POWERPC_EXCP_SPEU);
8288 return;
8289 }
8290 #if defined(TARGET_PPC64)
8291 TCGv t0 = tcg_temp_new();
8292 TCGv t1 = tcg_temp_new();
8293 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
8294 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
8295 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8296 tcg_temp_free(t0);
8297 tcg_temp_free(t1);
8298 #else
8299 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8300 TCGv_i32 tmp = tcg_temp_new_i32();
8301 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
8302 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8303 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
8304 tcg_temp_free_i32(tmp);
8305 } else {
8306 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8307 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8308 }
8309 #endif
8310 }
8311 static inline void gen_evsplati(DisasContext *ctx)
8312 {
8313 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8314
8315 #if defined(TARGET_PPC64)
8316 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
8317 #else
8318 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
8319 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
8320 #endif
8321 }
8322 static inline void gen_evsplatfi(DisasContext *ctx)
8323 {
8324 uint64_t imm = rA(ctx->opcode) << 27;
8325
8326 #if defined(TARGET_PPC64)
8327 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
8328 #else
8329 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
8330 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
8331 #endif
8332 }
8333
8334 static inline void gen_evsel(DisasContext *ctx)
8335 {
8336 int l1 = gen_new_label();
8337 int l2 = gen_new_label();
8338 int l3 = gen_new_label();
8339 int l4 = gen_new_label();
8340 TCGv_i32 t0 = tcg_temp_local_new_i32();
8341 #if defined(TARGET_PPC64)
8342 TCGv t1 = tcg_temp_local_new();
8343 TCGv t2 = tcg_temp_local_new();
8344 #endif
8345 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8346 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8347 #if defined(TARGET_PPC64)
8348 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
8349 #else
8350 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8351 #endif
8352 tcg_gen_br(l2);
8353 gen_set_label(l1);
8354 #if defined(TARGET_PPC64)
8355 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
8356 #else
8357 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8358 #endif
8359 gen_set_label(l2);
8360 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8361 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8362 #if defined(TARGET_PPC64)
8363 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
8364 #else
8365 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8366 #endif
8367 tcg_gen_br(l4);
8368 gen_set_label(l3);
8369 #if defined(TARGET_PPC64)
8370 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
8371 #else
8372 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8373 #endif
8374 gen_set_label(l4);
8375 tcg_temp_free_i32(t0);
8376 #if defined(TARGET_PPC64)
8377 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
8378 tcg_temp_free(t1);
8379 tcg_temp_free(t2);
8380 #endif
8381 }
8382
8383 static void gen_evsel0(DisasContext *ctx)
8384 {
8385 gen_evsel(ctx);
8386 }
8387
8388 static void gen_evsel1(DisasContext *ctx)
8389 {
8390 gen_evsel(ctx);
8391 }
8392
8393 static void gen_evsel2(DisasContext *ctx)
8394 {
8395 gen_evsel(ctx);
8396 }
8397
8398 static void gen_evsel3(DisasContext *ctx)
8399 {
8400 gen_evsel(ctx);
8401 }
8402
8403 /* Multiply */
8404
8405 static inline void gen_evmwumi(DisasContext *ctx)
8406 {
8407 TCGv_i64 t0, t1;
8408
8409 if (unlikely(!ctx->spe_enabled)) {
8410 gen_exception(ctx, POWERPC_EXCP_SPEU);
8411 return;
8412 }
8413
8414 t0 = tcg_temp_new_i64();
8415 t1 = tcg_temp_new_i64();
8416
8417 /* t0 := rA; t1 := rB */
8418 #if defined(TARGET_PPC64)
8419 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
8420 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
8421 #else
8422 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8423 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8424 #endif
8425
8426 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8427
8428 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8429
8430 tcg_temp_free_i64(t0);
8431 tcg_temp_free_i64(t1);
8432 }
8433
8434 static inline void gen_evmwumia(DisasContext *ctx)
8435 {
8436 TCGv_i64 tmp;
8437
8438 if (unlikely(!ctx->spe_enabled)) {
8439 gen_exception(ctx, POWERPC_EXCP_SPEU);
8440 return;
8441 }
8442
8443 gen_evmwumi(ctx); /* rD := rA * rB */
8444
8445 tmp = tcg_temp_new_i64();
8446
8447 /* acc := rD */
8448 gen_load_gpr64(tmp, rD(ctx->opcode));
8449 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8450 tcg_temp_free_i64(tmp);
8451 }
8452
8453 static inline void gen_evmwumiaa(DisasContext *ctx)
8454 {
8455 TCGv_i64 acc;
8456 TCGv_i64 tmp;
8457
8458 if (unlikely(!ctx->spe_enabled)) {
8459 gen_exception(ctx, POWERPC_EXCP_SPEU);
8460 return;
8461 }
8462
8463 gen_evmwumi(ctx); /* rD := rA * rB */
8464
8465 acc = tcg_temp_new_i64();
8466 tmp = tcg_temp_new_i64();
8467
8468 /* tmp := rD */
8469 gen_load_gpr64(tmp, rD(ctx->opcode));
8470
8471 /* Load acc */
8472 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8473
8474 /* acc := tmp + acc */
8475 tcg_gen_add_i64(acc, acc, tmp);
8476
8477 /* Store acc */
8478 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8479
8480 /* rD := acc */
8481 gen_store_gpr64(rD(ctx->opcode), acc);
8482
8483 tcg_temp_free_i64(acc);
8484 tcg_temp_free_i64(tmp);
8485 }
8486
8487 static inline void gen_evmwsmi(DisasContext *ctx)
8488 {
8489 TCGv_i64 t0, t1;
8490
8491 if (unlikely(!ctx->spe_enabled)) {
8492 gen_exception(ctx, POWERPC_EXCP_SPEU);
8493 return;
8494 }
8495
8496 t0 = tcg_temp_new_i64();
8497 t1 = tcg_temp_new_i64();
8498
8499 /* t0 := rA; t1 := rB */
8500 #if defined(TARGET_PPC64)
8501 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
8502 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
8503 #else
8504 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8505 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8506 #endif
8507
8508 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8509
8510 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8511
8512 tcg_temp_free_i64(t0);
8513 tcg_temp_free_i64(t1);
8514 }
8515
8516 static inline void gen_evmwsmia(DisasContext *ctx)
8517 {
8518 TCGv_i64 tmp;
8519
8520 gen_evmwsmi(ctx); /* rD := rA * rB */
8521
8522 tmp = tcg_temp_new_i64();
8523
8524 /* acc := rD */
8525 gen_load_gpr64(tmp, rD(ctx->opcode));
8526 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8527
8528 tcg_temp_free_i64(tmp);
8529 }
8530
8531 static inline void gen_evmwsmiaa(DisasContext *ctx)
8532 {
8533 TCGv_i64 acc = tcg_temp_new_i64();
8534 TCGv_i64 tmp = tcg_temp_new_i64();
8535
8536 gen_evmwsmi(ctx); /* rD := rA * rB */
8537
8538 acc = tcg_temp_new_i64();
8539 tmp = tcg_temp_new_i64();
8540
8541 /* tmp := rD */
8542 gen_load_gpr64(tmp, rD(ctx->opcode));
8543
8544 /* Load acc */
8545 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8546
8547 /* acc := tmp + acc */
8548 tcg_gen_add_i64(acc, acc, tmp);
8549
8550 /* Store acc */
8551 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8552
8553 /* rD := acc */
8554 gen_store_gpr64(rD(ctx->opcode), acc);
8555
8556 tcg_temp_free_i64(acc);
8557 tcg_temp_free_i64(tmp);
8558 }
8559
8560 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8561 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8562 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8563 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8564 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8565 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8566 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8567 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
8568 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
8569 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8570 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8571 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8572 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8573 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8574 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8575 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8576 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8577 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8578 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8579 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
8580 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8581 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8582 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
8583 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
8584 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8585 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8586 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8587 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8588 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
8589
8590 /* SPE load and stores */
8591 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
8592 {
8593 target_ulong uimm = rB(ctx->opcode);
8594
8595 if (rA(ctx->opcode) == 0) {
8596 tcg_gen_movi_tl(EA, uimm << sh);
8597 } else {
8598 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
8599 if (NARROW_MODE(ctx)) {
8600 tcg_gen_ext32u_tl(EA, EA);
8601 }
8602 }
8603 }
8604
8605 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
8606 {
8607 #if defined(TARGET_PPC64)
8608 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8609 #else
8610 TCGv_i64 t0 = tcg_temp_new_i64();
8611 gen_qemu_ld64(ctx, t0, addr);
8612 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
8613 tcg_gen_shri_i64(t0, t0, 32);
8614 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
8615 tcg_temp_free_i64(t0);
8616 #endif
8617 }
8618
8619 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
8620 {
8621 #if defined(TARGET_PPC64)
8622 TCGv t0 = tcg_temp_new();
8623 gen_qemu_ld32u(ctx, t0, addr);
8624 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8625 gen_addr_add(ctx, addr, addr, 4);
8626 gen_qemu_ld32u(ctx, t0, addr);
8627 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8628 tcg_temp_free(t0);
8629 #else
8630 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
8631 gen_addr_add(ctx, addr, addr, 4);
8632 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8633 #endif
8634 }
8635
8636 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
8637 {
8638 TCGv t0 = tcg_temp_new();
8639 #if defined(TARGET_PPC64)
8640 gen_qemu_ld16u(ctx, t0, addr);
8641 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8642 gen_addr_add(ctx, addr, addr, 2);
8643 gen_qemu_ld16u(ctx, t0, addr);
8644 tcg_gen_shli_tl(t0, t0, 32);
8645 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8646 gen_addr_add(ctx, addr, addr, 2);
8647 gen_qemu_ld16u(ctx, t0, addr);
8648 tcg_gen_shli_tl(t0, t0, 16);
8649 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8650 gen_addr_add(ctx, addr, addr, 2);
8651 gen_qemu_ld16u(ctx, t0, addr);
8652 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8653 #else
8654 gen_qemu_ld16u(ctx, t0, addr);
8655 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8656 gen_addr_add(ctx, addr, addr, 2);
8657 gen_qemu_ld16u(ctx, t0, addr);
8658 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
8659 gen_addr_add(ctx, addr, addr, 2);
8660 gen_qemu_ld16u(ctx, t0, addr);
8661 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8662 gen_addr_add(ctx, addr, addr, 2);
8663 gen_qemu_ld16u(ctx, t0, addr);
8664 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8665 #endif
8666 tcg_temp_free(t0);
8667 }
8668
8669 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
8670 {
8671 TCGv t0 = tcg_temp_new();
8672 gen_qemu_ld16u(ctx, t0, addr);
8673 #if defined(TARGET_PPC64)
8674 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8675 tcg_gen_shli_tl(t0, t0, 16);
8676 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8677 #else
8678 tcg_gen_shli_tl(t0, t0, 16);
8679 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8680 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8681 #endif
8682 tcg_temp_free(t0);
8683 }
8684
8685 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
8686 {
8687 TCGv t0 = tcg_temp_new();
8688 gen_qemu_ld16u(ctx, t0, addr);
8689 #if defined(TARGET_PPC64)
8690 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8691 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8692 #else
8693 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8694 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8695 #endif
8696 tcg_temp_free(t0);
8697 }
8698
8699 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
8700 {
8701 TCGv t0 = tcg_temp_new();
8702 gen_qemu_ld16s(ctx, t0, addr);
8703 #if defined(TARGET_PPC64)
8704 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8705 tcg_gen_ext32u_tl(t0, t0);
8706 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8707 #else
8708 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8709 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8710 #endif
8711 tcg_temp_free(t0);
8712 }
8713
8714 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
8715 {
8716 TCGv t0 = tcg_temp_new();
8717 #if defined(TARGET_PPC64)
8718 gen_qemu_ld16u(ctx, t0, addr);
8719 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8720 gen_addr_add(ctx, addr, addr, 2);
8721 gen_qemu_ld16u(ctx, t0, addr);
8722 tcg_gen_shli_tl(t0, t0, 16);
8723 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8724 #else
8725 gen_qemu_ld16u(ctx, t0, addr);
8726 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8727 gen_addr_add(ctx, addr, addr, 2);
8728 gen_qemu_ld16u(ctx, t0, addr);
8729 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
8730 #endif
8731 tcg_temp_free(t0);
8732 }
8733
8734 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
8735 {
8736 #if defined(TARGET_PPC64)
8737 TCGv t0 = tcg_temp_new();
8738 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8739 gen_addr_add(ctx, addr, addr, 2);
8740 gen_qemu_ld16u(ctx, t0, addr);
8741 tcg_gen_shli_tl(t0, t0, 32);
8742 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8743 tcg_temp_free(t0);
8744 #else
8745 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
8746 gen_addr_add(ctx, addr, addr, 2);
8747 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8748 #endif
8749 }
8750
8751 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
8752 {
8753 #if defined(TARGET_PPC64)
8754 TCGv t0 = tcg_temp_new();
8755 gen_qemu_ld16s(ctx, t0, addr);
8756 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
8757 gen_addr_add(ctx, addr, addr, 2);
8758 gen_qemu_ld16s(ctx, t0, addr);
8759 tcg_gen_shli_tl(t0, t0, 32);
8760 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8761 tcg_temp_free(t0);
8762 #else
8763 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
8764 gen_addr_add(ctx, addr, addr, 2);
8765 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8766 #endif
8767 }
8768
8769 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
8770 {
8771 TCGv t0 = tcg_temp_new();
8772 gen_qemu_ld32u(ctx, t0, addr);
8773 #if defined(TARGET_PPC64)
8774 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8775 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8776 #else
8777 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8778 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8779 #endif
8780 tcg_temp_free(t0);
8781 }
8782
8783 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
8784 {
8785 TCGv t0 = tcg_temp_new();
8786 #if defined(TARGET_PPC64)
8787 gen_qemu_ld16u(ctx, t0, addr);
8788 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8789 tcg_gen_shli_tl(t0, t0, 32);
8790 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8791 gen_addr_add(ctx, addr, addr, 2);
8792 gen_qemu_ld16u(ctx, t0, addr);
8793 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8794 tcg_gen_shli_tl(t0, t0, 16);
8795 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8796 #else
8797 gen_qemu_ld16u(ctx, t0, addr);
8798 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8799 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
8800 gen_addr_add(ctx, addr, addr, 2);
8801 gen_qemu_ld16u(ctx, t0, addr);
8802 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
8803 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
8804 #endif
8805 tcg_temp_free(t0);
8806 }
8807
8808 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
8809 {
8810 #if defined(TARGET_PPC64)
8811 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8812 #else
8813 TCGv_i64 t0 = tcg_temp_new_i64();
8814 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
8815 gen_qemu_st64(ctx, t0, addr);
8816 tcg_temp_free_i64(t0);
8817 #endif
8818 }
8819
8820 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
8821 {
8822 #if defined(TARGET_PPC64)
8823 TCGv t0 = tcg_temp_new();
8824 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8825 gen_qemu_st32(ctx, t0, addr);
8826 tcg_temp_free(t0);
8827 #else
8828 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8829 #endif
8830 gen_addr_add(ctx, addr, addr, 4);
8831 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8832 }
8833
8834 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
8835 {
8836 TCGv t0 = tcg_temp_new();
8837 #if defined(TARGET_PPC64)
8838 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
8839 #else
8840 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
8841 #endif
8842 gen_qemu_st16(ctx, t0, addr);
8843 gen_addr_add(ctx, addr, addr, 2);
8844 #if defined(TARGET_PPC64)
8845 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8846 gen_qemu_st16(ctx, t0, addr);
8847 #else
8848 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8849 #endif
8850 gen_addr_add(ctx, addr, addr, 2);
8851 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
8852 gen_qemu_st16(ctx, t0, addr);
8853 tcg_temp_free(t0);
8854 gen_addr_add(ctx, addr, addr, 2);
8855 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8856 }
8857
8858 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
8859 {
8860 TCGv t0 = tcg_temp_new();
8861 #if defined(TARGET_PPC64)
8862 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
8863 #else
8864 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
8865 #endif
8866 gen_qemu_st16(ctx, t0, addr);
8867 gen_addr_add(ctx, addr, addr, 2);
8868 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
8869 gen_qemu_st16(ctx, t0, addr);
8870 tcg_temp_free(t0);
8871 }
8872
8873 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
8874 {
8875 #if defined(TARGET_PPC64)
8876 TCGv t0 = tcg_temp_new();
8877 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8878 gen_qemu_st16(ctx, t0, addr);
8879 tcg_temp_free(t0);
8880 #else
8881 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8882 #endif
8883 gen_addr_add(ctx, addr, addr, 2);
8884 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8885 }
8886
8887 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
8888 {
8889 #if defined(TARGET_PPC64)
8890 TCGv t0 = tcg_temp_new();
8891 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8892 gen_qemu_st32(ctx, t0, addr);
8893 tcg_temp_free(t0);
8894 #else
8895 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8896 #endif
8897 }
8898
8899 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
8900 {
8901 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8902 }
8903
8904 #define GEN_SPEOP_LDST(name, opc2, sh) \
8905 static void glue(gen_, name)(DisasContext *ctx) \
8906 { \
8907 TCGv t0; \
8908 if (unlikely(!ctx->spe_enabled)) { \
8909 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8910 return; \
8911 } \
8912 gen_set_access_type(ctx, ACCESS_INT); \
8913 t0 = tcg_temp_new(); \
8914 if (Rc(ctx->opcode)) { \
8915 gen_addr_spe_imm_index(ctx, t0, sh); \
8916 } else { \
8917 gen_addr_reg_index(ctx, t0); \
8918 } \
8919 gen_op_##name(ctx, t0); \
8920 tcg_temp_free(t0); \
8921 }
8922
8923 GEN_SPEOP_LDST(evldd, 0x00, 3);
8924 GEN_SPEOP_LDST(evldw, 0x01, 3);
8925 GEN_SPEOP_LDST(evldh, 0x02, 3);
8926 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
8927 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
8928 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
8929 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
8930 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
8931 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
8932 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
8933 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
8934
8935 GEN_SPEOP_LDST(evstdd, 0x10, 3);
8936 GEN_SPEOP_LDST(evstdw, 0x11, 3);
8937 GEN_SPEOP_LDST(evstdh, 0x12, 3);
8938 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
8939 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
8940 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
8941 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
8942
8943 /* Multiply and add - TODO */
8944 #if 0
8945 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
8946 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8947 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8948 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8949 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8950 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8951 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8952 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8953 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8954 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8955 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8956 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8957
8958 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8959 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8960 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8961 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8962 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8963 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8964 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8965 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8966 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8967 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8968 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8969 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8970
8971 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8972 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8973 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8974 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8975 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
8976
8977 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8978 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8979 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8980 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8981 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8982 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8983 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8984 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8985 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8986 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8987 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8988 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8989
8990 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8991 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8992 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8993 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8994
8995 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8996 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8997 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8998 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8999 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9000 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9001 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9002 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9003 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9004 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9005 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9006 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9007
9008 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9009 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9010 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9011 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9012 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9013 #endif
9014
9015 /*** SPE floating-point extension ***/
9016 #if defined(TARGET_PPC64)
9017 #define GEN_SPEFPUOP_CONV_32_32(name) \
9018 static inline void gen_##name(DisasContext *ctx) \
9019 { \
9020 TCGv_i32 t0; \
9021 TCGv t1; \
9022 t0 = tcg_temp_new_i32(); \
9023 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9024 gen_helper_##name(t0, cpu_env, t0); \
9025 t1 = tcg_temp_new(); \
9026 tcg_gen_extu_i32_tl(t1, t0); \
9027 tcg_temp_free_i32(t0); \
9028 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9029 0xFFFFFFFF00000000ULL); \
9030 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
9031 tcg_temp_free(t1); \
9032 }
9033 #define GEN_SPEFPUOP_CONV_32_64(name) \
9034 static inline void gen_##name(DisasContext *ctx) \
9035 { \
9036 TCGv_i32 t0; \
9037 TCGv t1; \
9038 t0 = tcg_temp_new_i32(); \
9039 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
9040 t1 = tcg_temp_new(); \
9041 tcg_gen_extu_i32_tl(t1, t0); \
9042 tcg_temp_free_i32(t0); \
9043 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9044 0xFFFFFFFF00000000ULL); \
9045 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
9046 tcg_temp_free(t1); \
9047 }
9048 #define GEN_SPEFPUOP_CONV_64_32(name) \
9049 static inline void gen_##name(DisasContext *ctx) \
9050 { \
9051 TCGv_i32 t0 = tcg_temp_new_i32(); \
9052 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9053 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
9054 tcg_temp_free_i32(t0); \
9055 }
9056 #define GEN_SPEFPUOP_CONV_64_64(name) \
9057 static inline void gen_##name(DisasContext *ctx) \
9058 { \
9059 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9060 cpu_gpr[rB(ctx->opcode)]); \
9061 }
9062 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9063 static inline void gen_##name(DisasContext *ctx) \
9064 { \
9065 TCGv_i32 t0, t1; \
9066 TCGv_i64 t2; \
9067 if (unlikely(!ctx->spe_enabled)) { \
9068 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9069 return; \
9070 } \
9071 t0 = tcg_temp_new_i32(); \
9072 t1 = tcg_temp_new_i32(); \
9073 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9074 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9075 gen_helper_##name(t0, cpu_env, t0, t1); \
9076 tcg_temp_free_i32(t1); \
9077 t2 = tcg_temp_new(); \
9078 tcg_gen_extu_i32_tl(t2, t0); \
9079 tcg_temp_free_i32(t0); \
9080 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9081 0xFFFFFFFF00000000ULL); \
9082 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
9083 tcg_temp_free(t2); \
9084 }
9085 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9086 static inline void gen_##name(DisasContext *ctx) \
9087 { \
9088 if (unlikely(!ctx->spe_enabled)) { \
9089 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9090 return; \
9091 } \
9092 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9093 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9094 }
9095 #define GEN_SPEFPUOP_COMP_32(name) \
9096 static inline void gen_##name(DisasContext *ctx) \
9097 { \
9098 TCGv_i32 t0, t1; \
9099 if (unlikely(!ctx->spe_enabled)) { \
9100 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9101 return; \
9102 } \
9103 t0 = tcg_temp_new_i32(); \
9104 t1 = tcg_temp_new_i32(); \
9105 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9106 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9107 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9108 tcg_temp_free_i32(t0); \
9109 tcg_temp_free_i32(t1); \
9110 }
9111 #define GEN_SPEFPUOP_COMP_64(name) \
9112 static inline void gen_##name(DisasContext *ctx) \
9113 { \
9114 if (unlikely(!ctx->spe_enabled)) { \
9115 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9116 return; \
9117 } \
9118 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
9119 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9120 }
9121 #else
9122 #define GEN_SPEFPUOP_CONV_32_32(name) \
9123 static inline void gen_##name(DisasContext *ctx) \
9124 { \
9125 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9126 cpu_gpr[rB(ctx->opcode)]); \
9127 }
9128 #define GEN_SPEFPUOP_CONV_32_64(name) \
9129 static inline void gen_##name(DisasContext *ctx) \
9130 { \
9131 TCGv_i64 t0 = tcg_temp_new_i64(); \
9132 gen_load_gpr64(t0, rB(ctx->opcode)); \
9133 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
9134 tcg_temp_free_i64(t0); \
9135 }
9136 #define GEN_SPEFPUOP_CONV_64_32(name) \
9137 static inline void gen_##name(DisasContext *ctx) \
9138 { \
9139 TCGv_i64 t0 = tcg_temp_new_i64(); \
9140 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
9141 gen_store_gpr64(rD(ctx->opcode), t0); \
9142 tcg_temp_free_i64(t0); \
9143 }
9144 #define GEN_SPEFPUOP_CONV_64_64(name) \
9145 static inline void gen_##name(DisasContext *ctx) \
9146 { \
9147 TCGv_i64 t0 = tcg_temp_new_i64(); \
9148 gen_load_gpr64(t0, rB(ctx->opcode)); \
9149 gen_helper_##name(t0, cpu_env, t0); \
9150 gen_store_gpr64(rD(ctx->opcode), t0); \
9151 tcg_temp_free_i64(t0); \
9152 }
9153 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9154 static inline void gen_##name(DisasContext *ctx) \
9155 { \
9156 if (unlikely(!ctx->spe_enabled)) { \
9157 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9158 return; \
9159 } \
9160 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9161 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9162 }
9163 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9164 static inline void gen_##name(DisasContext *ctx) \
9165 { \
9166 TCGv_i64 t0, t1; \
9167 if (unlikely(!ctx->spe_enabled)) { \
9168 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9169 return; \
9170 } \
9171 t0 = tcg_temp_new_i64(); \
9172 t1 = tcg_temp_new_i64(); \
9173 gen_load_gpr64(t0, rA(ctx->opcode)); \
9174 gen_load_gpr64(t1, rB(ctx->opcode)); \
9175 gen_helper_##name(t0, cpu_env, t0, t1); \
9176 gen_store_gpr64(rD(ctx->opcode), t0); \
9177 tcg_temp_free_i64(t0); \
9178 tcg_temp_free_i64(t1); \
9179 }
9180 #define GEN_SPEFPUOP_COMP_32(name) \
9181 static inline void gen_##name(DisasContext *ctx) \
9182 { \
9183 if (unlikely(!ctx->spe_enabled)) { \
9184 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9185 return; \
9186 } \
9187 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
9188 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9189 }
9190 #define GEN_SPEFPUOP_COMP_64(name) \
9191 static inline void gen_##name(DisasContext *ctx) \
9192 { \
9193 TCGv_i64 t0, t1; \
9194 if (unlikely(!ctx->spe_enabled)) { \
9195 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9196 return; \
9197 } \
9198 t0 = tcg_temp_new_i64(); \
9199 t1 = tcg_temp_new_i64(); \
9200 gen_load_gpr64(t0, rA(ctx->opcode)); \
9201 gen_load_gpr64(t1, rB(ctx->opcode)); \
9202 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9203 tcg_temp_free_i64(t0); \
9204 tcg_temp_free_i64(t1); \
9205 }
9206 #endif
9207
9208 /* Single precision floating-point vectors operations */
9209 /* Arithmetic */
9210 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9211 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9212 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9213 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9214 static inline void gen_evfsabs(DisasContext *ctx)
9215 {
9216 if (unlikely(!ctx->spe_enabled)) {
9217 gen_exception(ctx, POWERPC_EXCP_SPEU);
9218 return;
9219 }
9220 #if defined(TARGET_PPC64)
9221 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
9222 #else
9223 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
9224 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
9225 #endif
9226 }
9227 static inline void gen_evfsnabs(DisasContext *ctx)
9228 {
9229 if (unlikely(!ctx->spe_enabled)) {
9230 gen_exception(ctx, POWERPC_EXCP_SPEU);
9231 return;
9232 }
9233 #if defined(TARGET_PPC64)
9234 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
9235 #else
9236 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9237 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9238 #endif
9239 }
9240 static inline void gen_evfsneg(DisasContext *ctx)
9241 {
9242 if (unlikely(!ctx->spe_enabled)) {
9243 gen_exception(ctx, POWERPC_EXCP_SPEU);
9244 return;
9245 }
9246 #if defined(TARGET_PPC64)
9247 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
9248 #else
9249 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9250 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9251 #endif
9252 }
9253
9254 /* Conversion */
9255 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9256 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9257 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9258 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9259 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9260 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9261 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9262 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9263 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9264 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9265
9266 /* Comparison */
9267 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9268 GEN_SPEFPUOP_COMP_64(evfscmplt);
9269 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9270 GEN_SPEFPUOP_COMP_64(evfststgt);
9271 GEN_SPEFPUOP_COMP_64(evfststlt);
9272 GEN_SPEFPUOP_COMP_64(evfststeq);
9273
9274 /* Opcodes definitions */
9275 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9276 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9277 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9278 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9279 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9280 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9281 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9282 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9283 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9284 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9285 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9286 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9287 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9288 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9289
9290 /* Single precision floating-point operations */
9291 /* Arithmetic */
9292 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9293 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9294 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9295 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9296 static inline void gen_efsabs(DisasContext *ctx)
9297 {
9298 if (unlikely(!ctx->spe_enabled)) {
9299 gen_exception(ctx, POWERPC_EXCP_SPEU);
9300 return;
9301 }
9302 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9303 }
9304 static inline void gen_efsnabs(DisasContext *ctx)
9305 {
9306 if (unlikely(!ctx->spe_enabled)) {
9307 gen_exception(ctx, POWERPC_EXCP_SPEU);
9308 return;
9309 }
9310 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9311 }
9312 static inline void gen_efsneg(DisasContext *ctx)
9313 {
9314 if (unlikely(!ctx->spe_enabled)) {
9315 gen_exception(ctx, POWERPC_EXCP_SPEU);
9316 return;
9317 }
9318 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9319 }
9320
9321 /* Conversion */
9322 GEN_SPEFPUOP_CONV_32_32(efscfui);
9323 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9324 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9325 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9326 GEN_SPEFPUOP_CONV_32_32(efsctui);
9327 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9328 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9329 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9330 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9331 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9332 GEN_SPEFPUOP_CONV_32_64(efscfd);
9333
9334 /* Comparison */
9335 GEN_SPEFPUOP_COMP_32(efscmpgt);
9336 GEN_SPEFPUOP_COMP_32(efscmplt);
9337 GEN_SPEFPUOP_COMP_32(efscmpeq);
9338 GEN_SPEFPUOP_COMP_32(efststgt);
9339 GEN_SPEFPUOP_COMP_32(efststlt);
9340 GEN_SPEFPUOP_COMP_32(efststeq);
9341
9342 /* Opcodes definitions */
9343 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9344 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9345 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9346 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9347 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9348 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9349 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9350 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9351 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9352 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9353 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9354 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9355 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9356 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9357
9358 /* Double precision floating-point operations */
9359 /* Arithmetic */
9360 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9361 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9362 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9363 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9364 static inline void gen_efdabs(DisasContext *ctx)
9365 {
9366 if (unlikely(!ctx->spe_enabled)) {
9367 gen_exception(ctx, POWERPC_EXCP_SPEU);
9368 return;
9369 }
9370 #if defined(TARGET_PPC64)
9371 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
9372 #else
9373 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9374 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
9375 #endif
9376 }
9377 static inline void gen_efdnabs(DisasContext *ctx)
9378 {
9379 if (unlikely(!ctx->spe_enabled)) {
9380 gen_exception(ctx, POWERPC_EXCP_SPEU);
9381 return;
9382 }
9383 #if defined(TARGET_PPC64)
9384 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
9385 #else
9386 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9387 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9388 #endif
9389 }
9390 static inline void gen_efdneg(DisasContext *ctx)
9391 {
9392 if (unlikely(!ctx->spe_enabled)) {
9393 gen_exception(ctx, POWERPC_EXCP_SPEU);
9394 return;
9395 }
9396 #if defined(TARGET_PPC64)
9397 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
9398 #else
9399 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9400 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9401 #endif
9402 }
9403
9404 /* Conversion */
9405 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9406 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9407 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9408 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9409 GEN_SPEFPUOP_CONV_32_64(efdctui);
9410 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9411 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9412 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9413 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9414 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9415 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9416 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9417 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9418 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9419 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9420
9421 /* Comparison */
9422 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9423 GEN_SPEFPUOP_COMP_64(efdcmplt);
9424 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9425 GEN_SPEFPUOP_COMP_64(efdtstgt);
9426 GEN_SPEFPUOP_COMP_64(efdtstlt);
9427 GEN_SPEFPUOP_COMP_64(efdtsteq);
9428
9429 /* Opcodes definitions */
9430 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9431 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9432 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9433 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9434 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9435 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9436 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9437 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9438 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9439 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9440 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9441 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9442 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9443 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9444 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9445 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9446
9447 static opcode_t opcodes[] = {
9448 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9449 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9450 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9451 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9452 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9453 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9454 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9455 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9456 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9457 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9458 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9459 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9460 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9461 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9462 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9463 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9464 #if defined(TARGET_PPC64)
9465 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9466 #endif
9467 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9468 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9469 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9470 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9471 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9472 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9473 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9474 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9475 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9476 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9477 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9478 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9479 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
9480 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9481 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9482 #if defined(TARGET_PPC64)
9483 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9484 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9485 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9486 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9487 #endif
9488 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9489 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9490 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9491 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9492 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9493 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9494 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9495 #if defined(TARGET_PPC64)
9496 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9497 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9498 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9499 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9500 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9501 #endif
9502 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9503 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9504 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9505 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9506 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9507 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9508 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9509 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9510 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9511 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9512 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9513 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9514 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9515 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9516 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9517 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9518 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9519 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9520 #if defined(TARGET_PPC64)
9521 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9522 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9523 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9524 #endif
9525 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9526 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9527 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9528 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9529 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9530 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9531 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9532 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9533 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9534 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9535 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9536 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9537 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9538 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9539 #if defined(TARGET_PPC64)
9540 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9541 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9542 #endif
9543 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9544 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9545 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9546 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9547 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9548 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9549 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9550 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9551 #if defined(TARGET_PPC64)
9552 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9553 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9554 #endif
9555 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9556 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9557 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9558 #if defined(TARGET_PPC64)
9559 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9560 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9561 #endif
9562 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9563 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9564 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9565 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9566 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9567 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9568 #if defined(TARGET_PPC64)
9569 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9570 #endif
9571 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9572 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
9573 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9574 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9575 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9576 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
9577 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
9578 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9579 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9580 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9581 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9582 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9583 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9584 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9585 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9586 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9587 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9588 #if defined(TARGET_PPC64)
9589 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9590 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9591 PPC_SEGMENT_64B),
9592 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9593 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9594 PPC_SEGMENT_64B),
9595 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9596 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9597 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9598 #endif
9599 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9600 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9601 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9602 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9603 #if defined(TARGET_PPC64)
9604 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9605 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9606 #endif
9607 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9608 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9609 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9610 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9611 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9612 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9613 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9614 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9615 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9616 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9617 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9618 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9619 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9620 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9621 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9622 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9623 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9624 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9625 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9626 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9627 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9628 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9629 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9630 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9631 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9632 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9633 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9634 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9635 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9636 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9637 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9638 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9639 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9640 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9641 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9642 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9643 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9644 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9645 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9646 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
9647 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
9648 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
9649 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
9650 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
9651 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
9652 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
9653 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
9654 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
9655 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
9656 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9657 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9658 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
9659 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
9660 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9661 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9662 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
9663 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
9664 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
9665 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
9666 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
9667 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
9668 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
9669 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
9670 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
9671 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
9672 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
9673 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
9674 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
9675 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
9676 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
9677 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
9678 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
9679 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
9680 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
9681 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
9682 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
9683 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
9684 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
9685 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
9686 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
9687 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
9688 PPC_NONE, PPC2_BOOKE206),
9689 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
9690 PPC_NONE, PPC2_BOOKE206),
9691 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
9692 PPC_NONE, PPC2_BOOKE206),
9693 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
9694 PPC_NONE, PPC2_BOOKE206),
9695 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
9696 PPC_NONE, PPC2_BOOKE206),
9697 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
9698 PPC_NONE, PPC2_PRCNTL),
9699 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
9700 PPC_NONE, PPC2_PRCNTL),
9701 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
9702 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
9703 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
9704 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
9705 PPC_BOOKE, PPC2_BOOKE206),
9706 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
9707 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
9708 PPC_BOOKE, PPC2_BOOKE206),
9709 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
9710 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
9711 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
9712 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
9713 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
9714 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
9715 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
9716 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
9717 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
9718 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
9719
9720 #undef GEN_INT_ARITH_ADD
9721 #undef GEN_INT_ARITH_ADD_CONST
9722 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
9723 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
9724 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
9725 add_ca, compute_ca, compute_ov) \
9726 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
9727 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
9728 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
9729 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
9730 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
9731 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
9732 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
9733 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
9734 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
9735 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
9736 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
9737
9738 #undef GEN_INT_ARITH_DIVW
9739 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
9740 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
9741 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
9742 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
9743 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
9744 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
9745 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9746 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9747 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9748 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9749
9750 #if defined(TARGET_PPC64)
9751 #undef GEN_INT_ARITH_DIVD
9752 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
9753 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9754 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
9755 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
9756 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
9757 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
9758
9759 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9760 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9761 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9762 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9763
9764 #undef GEN_INT_ARITH_MUL_HELPER
9765 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
9766 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9767 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
9768 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
9769 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
9770 #endif
9771
9772 #undef GEN_INT_ARITH_SUBF
9773 #undef GEN_INT_ARITH_SUBF_CONST
9774 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
9775 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
9776 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
9777 add_ca, compute_ca, compute_ov) \
9778 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
9779 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
9780 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
9781 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
9782 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
9783 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
9784 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
9785 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
9786 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
9787 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
9788 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
9789
9790 #undef GEN_LOGICAL1
9791 #undef GEN_LOGICAL2
9792 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
9793 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
9794 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
9795 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
9796 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
9797 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
9798 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
9799 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
9800 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
9801 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
9802 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
9803 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
9804 #if defined(TARGET_PPC64)
9805 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
9806 #endif
9807
9808 #if defined(TARGET_PPC64)
9809 #undef GEN_PPC64_R2
9810 #undef GEN_PPC64_R4
9811 #define GEN_PPC64_R2(name, opc1, opc2) \
9812 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9813 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9814 PPC_64B)
9815 #define GEN_PPC64_R4(name, opc1, opc2) \
9816 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9817 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
9818 PPC_64B), \
9819 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9820 PPC_64B), \
9821 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
9822 PPC_64B)
9823 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
9824 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
9825 GEN_PPC64_R4(rldic, 0x1E, 0x04),
9826 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
9827 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
9828 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
9829 #endif
9830
9831 #undef _GEN_FLOAT_ACB
9832 #undef GEN_FLOAT_ACB
9833 #undef _GEN_FLOAT_AB
9834 #undef GEN_FLOAT_AB
9835 #undef _GEN_FLOAT_AC
9836 #undef GEN_FLOAT_AC
9837 #undef GEN_FLOAT_B
9838 #undef GEN_FLOAT_BS
9839 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
9840 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
9841 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
9842 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
9843 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
9844 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
9845 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
9846 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
9847 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
9848 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
9849 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
9850 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
9851 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
9852 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
9853 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
9854 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
9855 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
9856 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
9857 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
9858
9859 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
9860 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
9861 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
9862 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
9863 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
9864 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
9865 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
9866 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
9867 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
9868 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
9869 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
9870 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
9871 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
9872 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
9873 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
9874 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
9875 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
9876 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
9877 #if defined(TARGET_PPC64)
9878 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
9879 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
9880 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
9881 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
9882 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
9883 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
9884 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
9885 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
9886 #endif
9887 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
9888 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
9889 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
9890 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
9891
9892 #undef GEN_LD
9893 #undef GEN_LDU
9894 #undef GEN_LDUX
9895 #undef GEN_LDX_E
9896 #undef GEN_LDS
9897 #define GEN_LD(name, ldop, opc, type) \
9898 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9899 #define GEN_LDU(name, ldop, opc, type) \
9900 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9901 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
9902 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
9903 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
9904 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
9905 #define GEN_LDS(name, ldop, op, type) \
9906 GEN_LD(name, ldop, op | 0x20, type) \
9907 GEN_LDU(name, ldop, op | 0x21, type) \
9908 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
9909 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
9910
9911 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
9912 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
9913 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
9914 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
9915 #if defined(TARGET_PPC64)
9916 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
9917 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
9918 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
9919 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
9920 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
9921 #endif
9922 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
9923 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
9924
9925 #undef GEN_ST
9926 #undef GEN_STU
9927 #undef GEN_STUX
9928 #undef GEN_STX_E
9929 #undef GEN_STS
9930 #define GEN_ST(name, stop, opc, type) \
9931 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9932 #define GEN_STU(name, stop, opc, type) \
9933 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
9934 #define GEN_STUX(name, stop, opc2, opc3, type) \
9935 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
9936 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
9937 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
9938 #define GEN_STS(name, stop, op, type) \
9939 GEN_ST(name, stop, op | 0x20, type) \
9940 GEN_STU(name, stop, op | 0x21, type) \
9941 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
9942 GEN_STX(name, stop, 0x17, op | 0x00, type)
9943
9944 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
9945 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
9946 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
9947 #if defined(TARGET_PPC64)
9948 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
9949 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
9950 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
9951 #endif
9952 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
9953 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
9954
9955 #undef GEN_LDF
9956 #undef GEN_LDUF
9957 #undef GEN_LDUXF
9958 #undef GEN_LDXF
9959 #undef GEN_LDFS
9960 #define GEN_LDF(name, ldop, opc, type) \
9961 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9962 #define GEN_LDUF(name, ldop, opc, type) \
9963 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9964 #define GEN_LDUXF(name, ldop, opc, type) \
9965 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9966 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
9967 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9968 #define GEN_LDFS(name, ldop, op, type) \
9969 GEN_LDF(name, ldop, op | 0x20, type) \
9970 GEN_LDUF(name, ldop, op | 0x21, type) \
9971 GEN_LDUXF(name, ldop, op | 0x01, type) \
9972 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
9973
9974 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
9975 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
9976 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
9977 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
9978 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
9979
9980 #undef GEN_STF
9981 #undef GEN_STUF
9982 #undef GEN_STUXF
9983 #undef GEN_STXF
9984 #undef GEN_STFS
9985 #define GEN_STF(name, stop, opc, type) \
9986 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9987 #define GEN_STUF(name, stop, opc, type) \
9988 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9989 #define GEN_STUXF(name, stop, opc, type) \
9990 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9991 #define GEN_STXF(name, stop, opc2, opc3, type) \
9992 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9993 #define GEN_STFS(name, stop, op, type) \
9994 GEN_STF(name, stop, op | 0x20, type) \
9995 GEN_STUF(name, stop, op | 0x21, type) \
9996 GEN_STUXF(name, stop, op | 0x01, type) \
9997 GEN_STXF(name, stop, 0x17, op | 0x00, type)
9998
9999 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10000 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10001 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10002 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10003 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10004
10005 #undef GEN_CRLOGIC
10006 #define GEN_CRLOGIC(name, tcg_op, opc) \
10007 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10008 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10009 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10010 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10011 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10012 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10013 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10014 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10015 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10016
10017 #undef GEN_MAC_HANDLER
10018 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10019 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10020 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10021 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10022 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10023 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10024 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10025 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10026 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10027 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10028 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10029 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10030 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10031 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10032 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10033 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10034 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10035 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10036 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10037 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10038 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10039 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10040 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10041 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10042 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10043 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10044 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10045 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10046 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10047 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10048 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10049 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10050 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10051 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10052 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10053 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10054 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10055 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10056 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10057 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10058 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10059 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10060 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10061 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10062
10063 #undef GEN_VR_LDX
10064 #undef GEN_VR_STX
10065 #undef GEN_VR_LVE
10066 #undef GEN_VR_STVE
10067 #define GEN_VR_LDX(name, opc2, opc3) \
10068 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10069 #define GEN_VR_STX(name, opc2, opc3) \
10070 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10071 #define GEN_VR_LVE(name, opc2, opc3) \
10072 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10073 #define GEN_VR_STVE(name, opc2, opc3) \
10074 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10075 GEN_VR_LDX(lvx, 0x07, 0x03),
10076 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10077 GEN_VR_LVE(bx, 0x07, 0x00),
10078 GEN_VR_LVE(hx, 0x07, 0x01),
10079 GEN_VR_LVE(wx, 0x07, 0x02),
10080 GEN_VR_STX(svx, 0x07, 0x07),
10081 GEN_VR_STX(svxl, 0x07, 0x0F),
10082 GEN_VR_STVE(bx, 0x07, 0x04),
10083 GEN_VR_STVE(hx, 0x07, 0x05),
10084 GEN_VR_STVE(wx, 0x07, 0x06),
10085
10086 #undef GEN_VX_LOGICAL
10087 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10088 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10089 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10090 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10091 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10092 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10093 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10094
10095 #undef GEN_VXFORM
10096 #define GEN_VXFORM(name, opc2, opc3) \
10097 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10098 GEN_VXFORM(vaddubm, 0, 0),
10099 GEN_VXFORM(vadduhm, 0, 1),
10100 GEN_VXFORM(vadduwm, 0, 2),
10101 GEN_VXFORM(vsububm, 0, 16),
10102 GEN_VXFORM(vsubuhm, 0, 17),
10103 GEN_VXFORM(vsubuwm, 0, 18),
10104 GEN_VXFORM(vmaxub, 1, 0),
10105 GEN_VXFORM(vmaxuh, 1, 1),
10106 GEN_VXFORM(vmaxuw, 1, 2),
10107 GEN_VXFORM(vmaxsb, 1, 4),
10108 GEN_VXFORM(vmaxsh, 1, 5),
10109 GEN_VXFORM(vmaxsw, 1, 6),
10110 GEN_VXFORM(vminub, 1, 8),
10111 GEN_VXFORM(vminuh, 1, 9),
10112 GEN_VXFORM(vminuw, 1, 10),
10113 GEN_VXFORM(vminsb, 1, 12),
10114 GEN_VXFORM(vminsh, 1, 13),
10115 GEN_VXFORM(vminsw, 1, 14),
10116 GEN_VXFORM(vavgub, 1, 16),
10117 GEN_VXFORM(vavguh, 1, 17),
10118 GEN_VXFORM(vavguw, 1, 18),
10119 GEN_VXFORM(vavgsb, 1, 20),
10120 GEN_VXFORM(vavgsh, 1, 21),
10121 GEN_VXFORM(vavgsw, 1, 22),
10122 GEN_VXFORM(vmrghb, 6, 0),
10123 GEN_VXFORM(vmrghh, 6, 1),
10124 GEN_VXFORM(vmrghw, 6, 2),
10125 GEN_VXFORM(vmrglb, 6, 4),
10126 GEN_VXFORM(vmrglh, 6, 5),
10127 GEN_VXFORM(vmrglw, 6, 6),
10128 GEN_VXFORM(vmuloub, 4, 0),
10129 GEN_VXFORM(vmulouh, 4, 1),
10130 GEN_VXFORM(vmulosb, 4, 4),
10131 GEN_VXFORM(vmulosh, 4, 5),
10132 GEN_VXFORM(vmuleub, 4, 8),
10133 GEN_VXFORM(vmuleuh, 4, 9),
10134 GEN_VXFORM(vmulesb, 4, 12),
10135 GEN_VXFORM(vmulesh, 4, 13),
10136 GEN_VXFORM(vslb, 2, 4),
10137 GEN_VXFORM(vslh, 2, 5),
10138 GEN_VXFORM(vslw, 2, 6),
10139 GEN_VXFORM(vsrb, 2, 8),
10140 GEN_VXFORM(vsrh, 2, 9),
10141 GEN_VXFORM(vsrw, 2, 10),
10142 GEN_VXFORM(vsrab, 2, 12),
10143 GEN_VXFORM(vsrah, 2, 13),
10144 GEN_VXFORM(vsraw, 2, 14),
10145 GEN_VXFORM(vslo, 6, 16),
10146 GEN_VXFORM(vsro, 6, 17),
10147 GEN_VXFORM(vaddcuw, 0, 6),
10148 GEN_VXFORM(vsubcuw, 0, 22),
10149 GEN_VXFORM(vaddubs, 0, 8),
10150 GEN_VXFORM(vadduhs, 0, 9),
10151 GEN_VXFORM(vadduws, 0, 10),
10152 GEN_VXFORM(vaddsbs, 0, 12),
10153 GEN_VXFORM(vaddshs, 0, 13),
10154 GEN_VXFORM(vaddsws, 0, 14),
10155 GEN_VXFORM(vsububs, 0, 24),
10156 GEN_VXFORM(vsubuhs, 0, 25),
10157 GEN_VXFORM(vsubuws, 0, 26),
10158 GEN_VXFORM(vsubsbs, 0, 28),
10159 GEN_VXFORM(vsubshs, 0, 29),
10160 GEN_VXFORM(vsubsws, 0, 30),
10161 GEN_VXFORM(vrlb, 2, 0),
10162 GEN_VXFORM(vrlh, 2, 1),
10163 GEN_VXFORM(vrlw, 2, 2),
10164 GEN_VXFORM(vsl, 2, 7),
10165 GEN_VXFORM(vsr, 2, 11),
10166 GEN_VXFORM(vpkuhum, 7, 0),
10167 GEN_VXFORM(vpkuwum, 7, 1),
10168 GEN_VXFORM(vpkuhus, 7, 2),
10169 GEN_VXFORM(vpkuwus, 7, 3),
10170 GEN_VXFORM(vpkshus, 7, 4),
10171 GEN_VXFORM(vpkswus, 7, 5),
10172 GEN_VXFORM(vpkshss, 7, 6),
10173 GEN_VXFORM(vpkswss, 7, 7),
10174 GEN_VXFORM(vpkpx, 7, 12),
10175 GEN_VXFORM(vsum4ubs, 4, 24),
10176 GEN_VXFORM(vsum4sbs, 4, 28),
10177 GEN_VXFORM(vsum4shs, 4, 25),
10178 GEN_VXFORM(vsum2sws, 4, 26),
10179 GEN_VXFORM(vsumsws, 4, 30),
10180 GEN_VXFORM(vaddfp, 5, 0),
10181 GEN_VXFORM(vsubfp, 5, 1),
10182 GEN_VXFORM(vmaxfp, 5, 16),
10183 GEN_VXFORM(vminfp, 5, 17),
10184
10185 #undef GEN_VXRFORM1
10186 #undef GEN_VXRFORM
10187 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10188 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10189 #define GEN_VXRFORM(name, opc2, opc3) \
10190 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10191 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10192 GEN_VXRFORM(vcmpequb, 3, 0)
10193 GEN_VXRFORM(vcmpequh, 3, 1)
10194 GEN_VXRFORM(vcmpequw, 3, 2)
10195 GEN_VXRFORM(vcmpgtsb, 3, 12)
10196 GEN_VXRFORM(vcmpgtsh, 3, 13)
10197 GEN_VXRFORM(vcmpgtsw, 3, 14)
10198 GEN_VXRFORM(vcmpgtub, 3, 8)
10199 GEN_VXRFORM(vcmpgtuh, 3, 9)
10200 GEN_VXRFORM(vcmpgtuw, 3, 10)
10201 GEN_VXRFORM(vcmpeqfp, 3, 3)
10202 GEN_VXRFORM(vcmpgefp, 3, 7)
10203 GEN_VXRFORM(vcmpgtfp, 3, 11)
10204 GEN_VXRFORM(vcmpbfp, 3, 15)
10205
10206 #undef GEN_VXFORM_SIMM
10207 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10208 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10209 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10210 GEN_VXFORM_SIMM(vspltish, 6, 13),
10211 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10212
10213 #undef GEN_VXFORM_NOA
10214 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10215 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10216 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10217 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10218 GEN_VXFORM_NOA(vupklsb, 7, 10),
10219 GEN_VXFORM_NOA(vupklsh, 7, 11),
10220 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10221 GEN_VXFORM_NOA(vupklpx, 7, 15),
10222 GEN_VXFORM_NOA(vrefp, 5, 4),
10223 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10224 GEN_VXFORM_NOA(vexptefp, 5, 6),
10225 GEN_VXFORM_NOA(vlogefp, 5, 7),
10226 GEN_VXFORM_NOA(vrfim, 5, 8),
10227 GEN_VXFORM_NOA(vrfin, 5, 9),
10228 GEN_VXFORM_NOA(vrfip, 5, 10),
10229 GEN_VXFORM_NOA(vrfiz, 5, 11),
10230
10231 #undef GEN_VXFORM_UIMM
10232 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10233 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10234 GEN_VXFORM_UIMM(vspltb, 6, 8),
10235 GEN_VXFORM_UIMM(vsplth, 6, 9),
10236 GEN_VXFORM_UIMM(vspltw, 6, 10),
10237 GEN_VXFORM_UIMM(vcfux, 5, 12),
10238 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10239 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10240 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10241
10242 #undef GEN_VAFORM_PAIRED
10243 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10244 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10245 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10246 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10247 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10248 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10249 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10250 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10251
10252 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10253 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10254 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10255 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10256 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10257 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10258 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10259
10260 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10261 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10262 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10263 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10264 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10265
10266 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10267 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10268 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10269 #if defined(TARGET_PPC64)
10270 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10271 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10272 #endif
10273
10274 #undef GEN_XX2FORM
10275 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10276 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10277 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10278
10279 #undef GEN_XX3FORM
10280 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10281 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10282 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10283 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10284 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10285
10286 #undef GEN_XX3_RC_FORM
10287 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10288 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10289 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10290 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10291 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10292 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10293 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10294 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10295 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10296
10297 #undef GEN_XX3FORM_DM
10298 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10299 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10300 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10301 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10302 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10303 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10304 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10305 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10306 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10307 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10308 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10309 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10310 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10311 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10312 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10313 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10314 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10315
10316 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10317 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10318 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10319 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10320
10321 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10322 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10323 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10324 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10325 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10326 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10327 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10328 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10329
10330 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10331 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10332 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10333 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10334 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10335 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10336 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10337 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10338 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10339 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10340 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10341 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10342 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10343 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10344 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10345 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10346 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10347 GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10348 GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10349 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10350 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10351 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10352 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10353 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10354 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10355 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10356 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10357 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10358 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10359 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10360 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10361 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10362 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10363 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10364 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10365 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10366
10367 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10368 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10369 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10370 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10371 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10372 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10373 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10374 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10375 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10376 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10377 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10378 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10379 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10380 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10381 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10382 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10383 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10384 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10385
10386 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10387 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10388 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10389 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10390 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10391 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10392 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10393 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10394 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10395 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10396 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10397 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10398 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10399 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10400 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10401 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10402 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10403 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10404 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10405 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10406 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10407 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10408 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10409 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10410 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10411 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10412 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10413 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10414 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10415 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10416 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10417 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10418 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10419 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10420 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10421 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10422
10423 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10424 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10425 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10426 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10427 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10428 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10429 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10430 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10431 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10432 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10433 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10434 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10435 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10436 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10437 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10438 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10439 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10440 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10441 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10442 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10443 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10444 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10445 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10446 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10447 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10448 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10449 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10450 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10451 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10452 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10453 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10454 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10455 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10456 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10457 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10458 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10459
10460 #undef VSX_LOGICAL
10461 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10462 GEN_XX3FORM(name, opc2, opc3, fl2)
10463
10464 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10465 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10466 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10467 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10468 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10469 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10470 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10471 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10472 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10473 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10474 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10475 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10476
10477 #define GEN_XXSEL_ROW(opc3) \
10478 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10479 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10480 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10481 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10482 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10483 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10484 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10485 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10486
10487 GEN_XXSEL_ROW(0x00)
10488 GEN_XXSEL_ROW(0x01)
10489 GEN_XXSEL_ROW(0x02)
10490 GEN_XXSEL_ROW(0x03)
10491 GEN_XXSEL_ROW(0x04)
10492 GEN_XXSEL_ROW(0x05)
10493 GEN_XXSEL_ROW(0x06)
10494 GEN_XXSEL_ROW(0x07)
10495 GEN_XXSEL_ROW(0x08)
10496 GEN_XXSEL_ROW(0x09)
10497 GEN_XXSEL_ROW(0x0A)
10498 GEN_XXSEL_ROW(0x0B)
10499 GEN_XXSEL_ROW(0x0C)
10500 GEN_XXSEL_ROW(0x0D)
10501 GEN_XXSEL_ROW(0x0E)
10502 GEN_XXSEL_ROW(0x0F)
10503 GEN_XXSEL_ROW(0x10)
10504 GEN_XXSEL_ROW(0x11)
10505 GEN_XXSEL_ROW(0x12)
10506 GEN_XXSEL_ROW(0x13)
10507 GEN_XXSEL_ROW(0x14)
10508 GEN_XXSEL_ROW(0x15)
10509 GEN_XXSEL_ROW(0x16)
10510 GEN_XXSEL_ROW(0x17)
10511 GEN_XXSEL_ROW(0x18)
10512 GEN_XXSEL_ROW(0x19)
10513 GEN_XXSEL_ROW(0x1A)
10514 GEN_XXSEL_ROW(0x1B)
10515 GEN_XXSEL_ROW(0x1C)
10516 GEN_XXSEL_ROW(0x1D)
10517 GEN_XXSEL_ROW(0x1E)
10518 GEN_XXSEL_ROW(0x1F)
10519
10520 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10521
10522 #undef GEN_SPE
10523 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
10524 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
10525 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10526 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10527 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10528 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10529 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10530 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10531 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10532 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
10533 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
10534 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10535 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10536 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10537 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10538 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10539 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10540 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
10541 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10542 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10543 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10544 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10545 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10546 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10547 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10548 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10549 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10550 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10551 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10552 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10553 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
10554
10555 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10556 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10557 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10558 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10559 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10560 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10561 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10562 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10563 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10564 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10565 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10566 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10567 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10568 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10569
10570 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10571 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10572 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10573 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10574 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10575 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
10576 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10577 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10578 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10579 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10580 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10581 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10582 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10583 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10584
10585 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
10586 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10587 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
10588 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10589 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
10590 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10591 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
10592 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
10593 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10594 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10595 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10596 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10597 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10598 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10599 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
10600 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10601
10602 #undef GEN_SPEOP_LDST
10603 #define GEN_SPEOP_LDST(name, opc2, sh) \
10604 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
10605 GEN_SPEOP_LDST(evldd, 0x00, 3),
10606 GEN_SPEOP_LDST(evldw, 0x01, 3),
10607 GEN_SPEOP_LDST(evldh, 0x02, 3),
10608 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
10609 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
10610 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
10611 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
10612 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
10613 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
10614 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
10615 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
10616
10617 GEN_SPEOP_LDST(evstdd, 0x10, 3),
10618 GEN_SPEOP_LDST(evstdw, 0x11, 3),
10619 GEN_SPEOP_LDST(evstdh, 0x12, 3),
10620 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
10621 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
10622 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
10623 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
10624 };
10625
10626 #include "helper_regs.h"
10627 #include "translate_init.c"
10628
10629 /*****************************************************************************/
10630 /* Misc PowerPC helpers */
10631 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
10632 int flags)
10633 {
10634 #define RGPL 4
10635 #define RFPL 4
10636
10637 PowerPCCPU *cpu = POWERPC_CPU(cs);
10638 CPUPPCState *env = &cpu->env;
10639 int i;
10640
10641 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
10642 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
10643 env->nip, env->lr, env->ctr, cpu_read_xer(env));
10644 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
10645 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
10646 env->hflags, env->mmu_idx);
10647 #if !defined(NO_TIMER_DUMP)
10648 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
10649 #if !defined(CONFIG_USER_ONLY)
10650 " DECR %08" PRIu32
10651 #endif
10652 "\n",
10653 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
10654 #if !defined(CONFIG_USER_ONLY)
10655 , cpu_ppc_load_decr(env)
10656 #endif
10657 );
10658 #endif
10659 for (i = 0; i < 32; i++) {
10660 if ((i & (RGPL - 1)) == 0)
10661 cpu_fprintf(f, "GPR%02d", i);
10662 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
10663 if ((i & (RGPL - 1)) == (RGPL - 1))
10664 cpu_fprintf(f, "\n");
10665 }
10666 cpu_fprintf(f, "CR ");
10667 for (i = 0; i < 8; i++)
10668 cpu_fprintf(f, "%01x", env->crf[i]);
10669 cpu_fprintf(f, " [");
10670 for (i = 0; i < 8; i++) {
10671 char a = '-';
10672 if (env->crf[i] & 0x08)
10673 a = 'L';
10674 else if (env->crf[i] & 0x04)
10675 a = 'G';
10676 else if (env->crf[i] & 0x02)
10677 a = 'E';
10678 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
10679 }
10680 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
10681 env->reserve_addr);
10682 for (i = 0; i < 32; i++) {
10683 if ((i & (RFPL - 1)) == 0)
10684 cpu_fprintf(f, "FPR%02d", i);
10685 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
10686 if ((i & (RFPL - 1)) == (RFPL - 1))
10687 cpu_fprintf(f, "\n");
10688 }
10689 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
10690 #if !defined(CONFIG_USER_ONLY)
10691 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
10692 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
10693 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
10694 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
10695
10696 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
10697 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
10698 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
10699 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
10700
10701 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
10702 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
10703 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
10704 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
10705
10706 if (env->excp_model == POWERPC_EXCP_BOOKE) {
10707 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
10708 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
10709 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
10710 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
10711
10712 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
10713 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
10714 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
10715 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
10716
10717 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
10718 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
10719 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
10720 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
10721
10722 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
10723 " EPR " TARGET_FMT_lx "\n",
10724 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
10725 env->spr[SPR_BOOKE_EPR]);
10726
10727 /* FSL-specific */
10728 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
10729 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
10730 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
10731 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
10732
10733 /*
10734 * IVORs are left out as they are large and do not change often --
10735 * they can be read with "p $ivor0", "p $ivor1", etc.
10736 */
10737 }
10738
10739 #if defined(TARGET_PPC64)
10740 if (env->flags & POWERPC_FLAG_CFAR) {
10741 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
10742 }
10743 #endif
10744
10745 switch (env->mmu_model) {
10746 case POWERPC_MMU_32B:
10747 case POWERPC_MMU_601:
10748 case POWERPC_MMU_SOFT_6xx:
10749 case POWERPC_MMU_SOFT_74xx:
10750 #if defined(TARGET_PPC64)
10751 case POWERPC_MMU_64B:
10752 case POWERPC_MMU_2_06:
10753 case POWERPC_MMU_2_06a:
10754 case POWERPC_MMU_2_06d:
10755 #endif
10756 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
10757 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
10758 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
10759 break;
10760 case POWERPC_MMU_BOOKE206:
10761 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
10762 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
10763 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
10764 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
10765
10766 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
10767 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
10768 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
10769 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
10770
10771 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
10772 " TLB1CFG " TARGET_FMT_lx "\n",
10773 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
10774 env->spr[SPR_BOOKE_TLB1CFG]);
10775 break;
10776 default:
10777 break;
10778 }
10779 #endif
10780
10781 #undef RGPL
10782 #undef RFPL
10783 }
10784
10785 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
10786 fprintf_function cpu_fprintf, int flags)
10787 {
10788 #if defined(DO_PPC_STATISTICS)
10789 PowerPCCPU *cpu = POWERPC_CPU(cs);
10790 opc_handler_t **t1, **t2, **t3, *handler;
10791 int op1, op2, op3;
10792
10793 t1 = cpu->env.opcodes;
10794 for (op1 = 0; op1 < 64; op1++) {
10795 handler = t1[op1];
10796 if (is_indirect_opcode(handler)) {
10797 t2 = ind_table(handler);
10798 for (op2 = 0; op2 < 32; op2++) {
10799 handler = t2[op2];
10800 if (is_indirect_opcode(handler)) {
10801 t3 = ind_table(handler);
10802 for (op3 = 0; op3 < 32; op3++) {
10803 handler = t3[op3];
10804 if (handler->count == 0)
10805 continue;
10806 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
10807 "%016" PRIx64 " %" PRId64 "\n",
10808 op1, op2, op3, op1, (op3 << 5) | op2,
10809 handler->oname,
10810 handler->count, handler->count);
10811 }
10812 } else {
10813 if (handler->count == 0)
10814 continue;
10815 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
10816 "%016" PRIx64 " %" PRId64 "\n",
10817 op1, op2, op1, op2, handler->oname,
10818 handler->count, handler->count);
10819 }
10820 }
10821 } else {
10822 if (handler->count == 0)
10823 continue;
10824 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
10825 " %" PRId64 "\n",
10826 op1, op1, handler->oname,
10827 handler->count, handler->count);
10828 }
10829 }
10830 #endif
10831 }
10832
10833 /*****************************************************************************/
10834 static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
10835 TranslationBlock *tb,
10836 bool search_pc)
10837 {
10838 CPUState *cs = CPU(cpu);
10839 CPUPPCState *env = &cpu->env;
10840 DisasContext ctx, *ctxp = &ctx;
10841 opc_handler_t **table, *handler;
10842 target_ulong pc_start;
10843 uint16_t *gen_opc_end;
10844 CPUBreakpoint *bp;
10845 int j, lj = -1;
10846 int num_insns;
10847 int max_insns;
10848
10849 pc_start = tb->pc;
10850 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
10851 ctx.nip = pc_start;
10852 ctx.tb = tb;
10853 ctx.exception = POWERPC_EXCP_NONE;
10854 ctx.spr_cb = env->spr_cb;
10855 ctx.mem_idx = env->mmu_idx;
10856 ctx.insns_flags = env->insns_flags;
10857 ctx.insns_flags2 = env->insns_flags2;
10858 ctx.access_type = -1;
10859 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
10860 #if defined(TARGET_PPC64)
10861 ctx.sf_mode = msr_is_64bit(env, env->msr);
10862 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
10863 #endif
10864 ctx.fpu_enabled = msr_fp;
10865 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
10866 ctx.spe_enabled = msr_spe;
10867 else
10868 ctx.spe_enabled = 0;
10869 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
10870 ctx.altivec_enabled = msr_vr;
10871 else
10872 ctx.altivec_enabled = 0;
10873 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
10874 ctx.vsx_enabled = msr_vsx;
10875 } else {
10876 ctx.vsx_enabled = 0;
10877 }
10878 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
10879 ctx.singlestep_enabled = CPU_SINGLE_STEP;
10880 else
10881 ctx.singlestep_enabled = 0;
10882 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
10883 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
10884 if (unlikely(cs->singlestep_enabled)) {
10885 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
10886 }
10887 #if defined (DO_SINGLE_STEP) && 0
10888 /* Single step trace mode */
10889 msr_se = 1;
10890 #endif
10891 num_insns = 0;
10892 max_insns = tb->cflags & CF_COUNT_MASK;
10893 if (max_insns == 0)
10894 max_insns = CF_COUNT_MASK;
10895
10896 gen_tb_start();
10897 /* Set env in case of segfault during code fetch */
10898 while (ctx.exception == POWERPC_EXCP_NONE
10899 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
10900 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
10901 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
10902 if (bp->pc == ctx.nip) {
10903 gen_debug_exception(ctxp);
10904 break;
10905 }
10906 }
10907 }
10908 if (unlikely(search_pc)) {
10909 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
10910 if (lj < j) {
10911 lj++;
10912 while (lj < j)
10913 tcg_ctx.gen_opc_instr_start[lj++] = 0;
10914 }
10915 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
10916 tcg_ctx.gen_opc_instr_start[lj] = 1;
10917 tcg_ctx.gen_opc_icount[lj] = num_insns;
10918 }
10919 LOG_DISAS("----------------\n");
10920 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
10921 ctx.nip, ctx.mem_idx, (int)msr_ir);
10922 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
10923 gen_io_start();
10924 if (unlikely(ctx.le_mode)) {
10925 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
10926 } else {
10927 ctx.opcode = cpu_ldl_code(env, ctx.nip);
10928 }
10929 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
10930 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
10931 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
10932 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
10933 tcg_gen_debug_insn_start(ctx.nip);
10934 }
10935 ctx.nip += 4;
10936 table = env->opcodes;
10937 num_insns++;
10938 handler = table[opc1(ctx.opcode)];
10939 if (is_indirect_opcode(handler)) {
10940 table = ind_table(handler);
10941 handler = table[opc2(ctx.opcode)];
10942 if (is_indirect_opcode(handler)) {
10943 table = ind_table(handler);
10944 handler = table[opc3(ctx.opcode)];
10945 }
10946 }
10947 /* Is opcode *REALLY* valid ? */
10948 if (unlikely(handler->handler == &gen_invalid)) {
10949 if (qemu_log_enabled()) {
10950 qemu_log("invalid/unsupported opcode: "
10951 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
10952 opc1(ctx.opcode), opc2(ctx.opcode),
10953 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
10954 }
10955 } else {
10956 uint32_t inval;
10957
10958 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
10959 inval = handler->inval2;
10960 } else {
10961 inval = handler->inval1;
10962 }
10963
10964 if (unlikely((ctx.opcode & inval) != 0)) {
10965 if (qemu_log_enabled()) {
10966 qemu_log("invalid bits: %08x for opcode: "
10967 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
10968 ctx.opcode & inval, opc1(ctx.opcode),
10969 opc2(ctx.opcode), opc3(ctx.opcode),
10970 ctx.opcode, ctx.nip - 4);
10971 }
10972 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
10973 break;
10974 }
10975 }
10976 (*(handler->handler))(&ctx);
10977 #if defined(DO_PPC_STATISTICS)
10978 handler->count++;
10979 #endif
10980 /* Check trace mode exceptions */
10981 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
10982 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
10983 ctx.exception != POWERPC_SYSCALL &&
10984 ctx.exception != POWERPC_EXCP_TRAP &&
10985 ctx.exception != POWERPC_EXCP_BRANCH)) {
10986 gen_exception(ctxp, POWERPC_EXCP_TRACE);
10987 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
10988 (cs->singlestep_enabled) ||
10989 singlestep ||
10990 num_insns >= max_insns)) {
10991 /* if we reach a page boundary or are single stepping, stop
10992 * generation
10993 */
10994 break;
10995 }
10996 }
10997 if (tb->cflags & CF_LAST_IO)
10998 gen_io_end();
10999 if (ctx.exception == POWERPC_EXCP_NONE) {
11000 gen_goto_tb(&ctx, 0, ctx.nip);
11001 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11002 if (unlikely(cs->singlestep_enabled)) {
11003 gen_debug_exception(ctxp);
11004 }
11005 /* Generate the return instruction */
11006 tcg_gen_exit_tb(0);
11007 }
11008 gen_tb_end(tb, num_insns);
11009 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
11010 if (unlikely(search_pc)) {
11011 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11012 lj++;
11013 while (lj <= j)
11014 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11015 } else {
11016 tb->size = ctx.nip - pc_start;
11017 tb->icount = num_insns;
11018 }
11019 #if defined(DEBUG_DISAS)
11020 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11021 int flags;
11022 flags = env->bfd_mach;
11023 flags |= ctx.le_mode << 16;
11024 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11025 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
11026 qemu_log("\n");
11027 }
11028 #endif
11029 }
11030
11031 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
11032 {
11033 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false);
11034 }
11035
11036 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
11037 {
11038 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true);
11039 }
11040
11041 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
11042 {
11043 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
11044 }
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