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ppc: Avoid AREG0 for exception helpers
[mirror_qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas.h"
23 #include "tcg-op.h"
24 #include "host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i32 cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_msr;
64 static TCGv cpu_ctr;
65 static TCGv cpu_lr;
66 #if defined(TARGET_PPC64)
67 static TCGv cpu_cfar;
68 #endif
69 static TCGv cpu_xer;
70 static TCGv cpu_reserve;
71 static TCGv_i32 cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111 #endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154 #if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157 #endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161
162 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
163 offsetof(CPUPPCState, reserve_addr),
164 "reserve_addr");
165
166 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
167 offsetof(CPUPPCState, fpscr), "fpscr");
168
169 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
170 offsetof(CPUPPCState, access_type), "access_type");
171
172 /* register helpers */
173 #define GEN_HELPER 2
174 #include "helper.h"
175
176 done_init = 1;
177 }
178
179 /* internal defines */
180 typedef struct DisasContext {
181 struct TranslationBlock *tb;
182 target_ulong nip;
183 uint32_t opcode;
184 uint32_t exception;
185 /* Routine used to access memory */
186 int mem_idx;
187 int access_type;
188 /* Translation flags */
189 int le_mode;
190 #if defined(TARGET_PPC64)
191 int sf_mode;
192 int has_cfar;
193 #endif
194 int fpu_enabled;
195 int altivec_enabled;
196 int spe_enabled;
197 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
198 int singlestep_enabled;
199 } DisasContext;
200
201 struct opc_handler_t {
202 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
203 uint32_t inval1;
204 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
205 uint32_t inval2;
206 /* instruction type */
207 uint64_t type;
208 /* extended instruction type */
209 uint64_t type2;
210 /* handler */
211 void (*handler)(DisasContext *ctx);
212 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
213 const char *oname;
214 #endif
215 #if defined(DO_PPC_STATISTICS)
216 uint64_t count;
217 #endif
218 };
219
220 static inline void gen_reset_fpstatus(void)
221 {
222 gen_helper_reset_fpstatus();
223 }
224
225 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
226 {
227 TCGv_i32 t0 = tcg_temp_new_i32();
228
229 if (set_fprf != 0) {
230 /* This case might be optimized later */
231 tcg_gen_movi_i32(t0, 1);
232 gen_helper_compute_fprf(t0, arg, t0);
233 if (unlikely(set_rc)) {
234 tcg_gen_mov_i32(cpu_crf[1], t0);
235 }
236 gen_helper_float_check_status();
237 } else if (unlikely(set_rc)) {
238 /* We always need to compute fpcc */
239 tcg_gen_movi_i32(t0, 0);
240 gen_helper_compute_fprf(t0, arg, t0);
241 tcg_gen_mov_i32(cpu_crf[1], t0);
242 }
243
244 tcg_temp_free_i32(t0);
245 }
246
247 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
248 {
249 if (ctx->access_type != access_type) {
250 tcg_gen_movi_i32(cpu_access_type, access_type);
251 ctx->access_type = access_type;
252 }
253 }
254
255 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
256 {
257 #if defined(TARGET_PPC64)
258 if (ctx->sf_mode)
259 tcg_gen_movi_tl(cpu_nip, nip);
260 else
261 #endif
262 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
263 }
264
265 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
266 {
267 TCGv_i32 t0, t1;
268 if (ctx->exception == POWERPC_EXCP_NONE) {
269 gen_update_nip(ctx, ctx->nip);
270 }
271 t0 = tcg_const_i32(excp);
272 t1 = tcg_const_i32(error);
273 gen_helper_raise_exception_err(cpu_env, t0, t1);
274 tcg_temp_free_i32(t0);
275 tcg_temp_free_i32(t1);
276 ctx->exception = (excp);
277 }
278
279 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
280 {
281 TCGv_i32 t0;
282 if (ctx->exception == POWERPC_EXCP_NONE) {
283 gen_update_nip(ctx, ctx->nip);
284 }
285 t0 = tcg_const_i32(excp);
286 gen_helper_raise_exception(cpu_env, t0);
287 tcg_temp_free_i32(t0);
288 ctx->exception = (excp);
289 }
290
291 static inline void gen_debug_exception(DisasContext *ctx)
292 {
293 TCGv_i32 t0;
294
295 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
296 (ctx->exception != POWERPC_EXCP_SYNC)) {
297 gen_update_nip(ctx, ctx->nip);
298 }
299 t0 = tcg_const_i32(EXCP_DEBUG);
300 gen_helper_raise_exception(cpu_env, t0);
301 tcg_temp_free_i32(t0);
302 }
303
304 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
305 {
306 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
307 }
308
309 /* Stop translation */
310 static inline void gen_stop_exception(DisasContext *ctx)
311 {
312 gen_update_nip(ctx, ctx->nip);
313 ctx->exception = POWERPC_EXCP_STOP;
314 }
315
316 /* No need to update nip here, as execution flow will change */
317 static inline void gen_sync_exception(DisasContext *ctx)
318 {
319 ctx->exception = POWERPC_EXCP_SYNC;
320 }
321
322 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
323 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
324
325 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
326 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
327
328 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
329 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
330
331 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
332 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
333
334 typedef struct opcode_t {
335 unsigned char opc1, opc2, opc3;
336 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
337 unsigned char pad[5];
338 #else
339 unsigned char pad[1];
340 #endif
341 opc_handler_t handler;
342 const char *oname;
343 } opcode_t;
344
345 /*****************************************************************************/
346 /*** Instruction decoding ***/
347 #define EXTRACT_HELPER(name, shift, nb) \
348 static inline uint32_t name(uint32_t opcode) \
349 { \
350 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
351 }
352
353 #define EXTRACT_SHELPER(name, shift, nb) \
354 static inline int32_t name(uint32_t opcode) \
355 { \
356 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
357 }
358
359 /* Opcode part 1 */
360 EXTRACT_HELPER(opc1, 26, 6);
361 /* Opcode part 2 */
362 EXTRACT_HELPER(opc2, 1, 5);
363 /* Opcode part 3 */
364 EXTRACT_HELPER(opc3, 6, 5);
365 /* Update Cr0 flags */
366 EXTRACT_HELPER(Rc, 0, 1);
367 /* Destination */
368 EXTRACT_HELPER(rD, 21, 5);
369 /* Source */
370 EXTRACT_HELPER(rS, 21, 5);
371 /* First operand */
372 EXTRACT_HELPER(rA, 16, 5);
373 /* Second operand */
374 EXTRACT_HELPER(rB, 11, 5);
375 /* Third operand */
376 EXTRACT_HELPER(rC, 6, 5);
377 /*** Get CRn ***/
378 EXTRACT_HELPER(crfD, 23, 3);
379 EXTRACT_HELPER(crfS, 18, 3);
380 EXTRACT_HELPER(crbD, 21, 5);
381 EXTRACT_HELPER(crbA, 16, 5);
382 EXTRACT_HELPER(crbB, 11, 5);
383 /* SPR / TBL */
384 EXTRACT_HELPER(_SPR, 11, 10);
385 static inline uint32_t SPR(uint32_t opcode)
386 {
387 uint32_t sprn = _SPR(opcode);
388
389 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
390 }
391 /*** Get constants ***/
392 EXTRACT_HELPER(IMM, 12, 8);
393 /* 16 bits signed immediate value */
394 EXTRACT_SHELPER(SIMM, 0, 16);
395 /* 16 bits unsigned immediate value */
396 EXTRACT_HELPER(UIMM, 0, 16);
397 /* 5 bits signed immediate value */
398 EXTRACT_HELPER(SIMM5, 16, 5);
399 /* 5 bits signed immediate value */
400 EXTRACT_HELPER(UIMM5, 16, 5);
401 /* Bit count */
402 EXTRACT_HELPER(NB, 11, 5);
403 /* Shift count */
404 EXTRACT_HELPER(SH, 11, 5);
405 /* Vector shift count */
406 EXTRACT_HELPER(VSH, 6, 4);
407 /* Mask start */
408 EXTRACT_HELPER(MB, 6, 5);
409 /* Mask end */
410 EXTRACT_HELPER(ME, 1, 5);
411 /* Trap operand */
412 EXTRACT_HELPER(TO, 21, 5);
413
414 EXTRACT_HELPER(CRM, 12, 8);
415 EXTRACT_HELPER(FM, 17, 8);
416 EXTRACT_HELPER(SR, 16, 4);
417 EXTRACT_HELPER(FPIMM, 12, 4);
418
419 /*** Jump target decoding ***/
420 /* Displacement */
421 EXTRACT_SHELPER(d, 0, 16);
422 /* Immediate address */
423 static inline target_ulong LI(uint32_t opcode)
424 {
425 return (opcode >> 0) & 0x03FFFFFC;
426 }
427
428 static inline uint32_t BD(uint32_t opcode)
429 {
430 return (opcode >> 0) & 0xFFFC;
431 }
432
433 EXTRACT_HELPER(BO, 21, 5);
434 EXTRACT_HELPER(BI, 16, 5);
435 /* Absolute/relative address */
436 EXTRACT_HELPER(AA, 1, 1);
437 /* Link */
438 EXTRACT_HELPER(LK, 0, 1);
439
440 /* Create a mask between <start> and <end> bits */
441 static inline target_ulong MASK(uint32_t start, uint32_t end)
442 {
443 target_ulong ret;
444
445 #if defined(TARGET_PPC64)
446 if (likely(start == 0)) {
447 ret = UINT64_MAX << (63 - end);
448 } else if (likely(end == 63)) {
449 ret = UINT64_MAX >> start;
450 }
451 #else
452 if (likely(start == 0)) {
453 ret = UINT32_MAX << (31 - end);
454 } else if (likely(end == 31)) {
455 ret = UINT32_MAX >> start;
456 }
457 #endif
458 else {
459 ret = (((target_ulong)(-1ULL)) >> (start)) ^
460 (((target_ulong)(-1ULL) >> (end)) >> 1);
461 if (unlikely(start > end))
462 return ~ret;
463 }
464
465 return ret;
466 }
467
468 /*****************************************************************************/
469 /* PowerPC instructions table */
470
471 #if defined(DO_PPC_STATISTICS)
472 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
473 { \
474 .opc1 = op1, \
475 .opc2 = op2, \
476 .opc3 = op3, \
477 .pad = { 0, }, \
478 .handler = { \
479 .inval1 = invl, \
480 .type = _typ, \
481 .type2 = _typ2, \
482 .handler = &gen_##name, \
483 .oname = stringify(name), \
484 }, \
485 .oname = stringify(name), \
486 }
487 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
488 { \
489 .opc1 = op1, \
490 .opc2 = op2, \
491 .opc3 = op3, \
492 .pad = { 0, }, \
493 .handler = { \
494 .inval1 = invl1, \
495 .inval2 = invl2, \
496 .type = _typ, \
497 .type2 = _typ2, \
498 .handler = &gen_##name, \
499 .oname = stringify(name), \
500 }, \
501 .oname = stringify(name), \
502 }
503 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
504 { \
505 .opc1 = op1, \
506 .opc2 = op2, \
507 .opc3 = op3, \
508 .pad = { 0, }, \
509 .handler = { \
510 .inval1 = invl, \
511 .type = _typ, \
512 .type2 = _typ2, \
513 .handler = &gen_##name, \
514 .oname = onam, \
515 }, \
516 .oname = onam, \
517 }
518 #else
519 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
520 { \
521 .opc1 = op1, \
522 .opc2 = op2, \
523 .opc3 = op3, \
524 .pad = { 0, }, \
525 .handler = { \
526 .inval1 = invl, \
527 .type = _typ, \
528 .type2 = _typ2, \
529 .handler = &gen_##name, \
530 }, \
531 .oname = stringify(name), \
532 }
533 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
534 { \
535 .opc1 = op1, \
536 .opc2 = op2, \
537 .opc3 = op3, \
538 .pad = { 0, }, \
539 .handler = { \
540 .inval1 = invl1, \
541 .inval2 = invl2, \
542 .type = _typ, \
543 .type2 = _typ2, \
544 .handler = &gen_##name, \
545 }, \
546 .oname = stringify(name), \
547 }
548 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
549 { \
550 .opc1 = op1, \
551 .opc2 = op2, \
552 .opc3 = op3, \
553 .pad = { 0, }, \
554 .handler = { \
555 .inval1 = invl, \
556 .type = _typ, \
557 .type2 = _typ2, \
558 .handler = &gen_##name, \
559 }, \
560 .oname = onam, \
561 }
562 #endif
563
564 /* SPR load/store helpers */
565 static inline void gen_load_spr(TCGv t, int reg)
566 {
567 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
568 }
569
570 static inline void gen_store_spr(int reg, TCGv t)
571 {
572 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
573 }
574
575 /* Invalid instruction */
576 static void gen_invalid(DisasContext *ctx)
577 {
578 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
579 }
580
581 static opc_handler_t invalid_handler = {
582 .inval1 = 0xFFFFFFFF,
583 .inval2 = 0xFFFFFFFF,
584 .type = PPC_NONE,
585 .type2 = PPC_NONE,
586 .handler = gen_invalid,
587 };
588
589 /*** Integer comparison ***/
590
591 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
592 {
593 int l1, l2, l3;
594
595 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
596 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
597 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
598
599 l1 = gen_new_label();
600 l2 = gen_new_label();
601 l3 = gen_new_label();
602 if (s) {
603 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
604 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
605 } else {
606 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
607 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
608 }
609 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
610 tcg_gen_br(l3);
611 gen_set_label(l1);
612 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
613 tcg_gen_br(l3);
614 gen_set_label(l2);
615 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
616 gen_set_label(l3);
617 }
618
619 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
620 {
621 TCGv t0 = tcg_const_local_tl(arg1);
622 gen_op_cmp(arg0, t0, s, crf);
623 tcg_temp_free(t0);
624 }
625
626 #if defined(TARGET_PPC64)
627 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
628 {
629 TCGv t0, t1;
630 t0 = tcg_temp_local_new();
631 t1 = tcg_temp_local_new();
632 if (s) {
633 tcg_gen_ext32s_tl(t0, arg0);
634 tcg_gen_ext32s_tl(t1, arg1);
635 } else {
636 tcg_gen_ext32u_tl(t0, arg0);
637 tcg_gen_ext32u_tl(t1, arg1);
638 }
639 gen_op_cmp(t0, t1, s, crf);
640 tcg_temp_free(t1);
641 tcg_temp_free(t0);
642 }
643
644 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
645 {
646 TCGv t0 = tcg_const_local_tl(arg1);
647 gen_op_cmp32(arg0, t0, s, crf);
648 tcg_temp_free(t0);
649 }
650 #endif
651
652 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
653 {
654 #if defined(TARGET_PPC64)
655 if (!(ctx->sf_mode))
656 gen_op_cmpi32(reg, 0, 1, 0);
657 else
658 #endif
659 gen_op_cmpi(reg, 0, 1, 0);
660 }
661
662 /* cmp */
663 static void gen_cmp(DisasContext *ctx)
664 {
665 #if defined(TARGET_PPC64)
666 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
667 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
668 1, crfD(ctx->opcode));
669 else
670 #endif
671 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
672 1, crfD(ctx->opcode));
673 }
674
675 /* cmpi */
676 static void gen_cmpi(DisasContext *ctx)
677 {
678 #if defined(TARGET_PPC64)
679 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
680 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
681 1, crfD(ctx->opcode));
682 else
683 #endif
684 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
685 1, crfD(ctx->opcode));
686 }
687
688 /* cmpl */
689 static void gen_cmpl(DisasContext *ctx)
690 {
691 #if defined(TARGET_PPC64)
692 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
693 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
694 0, crfD(ctx->opcode));
695 else
696 #endif
697 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
698 0, crfD(ctx->opcode));
699 }
700
701 /* cmpli */
702 static void gen_cmpli(DisasContext *ctx)
703 {
704 #if defined(TARGET_PPC64)
705 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
706 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
707 0, crfD(ctx->opcode));
708 else
709 #endif
710 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
711 0, crfD(ctx->opcode));
712 }
713
714 /* isel (PowerPC 2.03 specification) */
715 static void gen_isel(DisasContext *ctx)
716 {
717 int l1, l2;
718 uint32_t bi = rC(ctx->opcode);
719 uint32_t mask;
720 TCGv_i32 t0;
721
722 l1 = gen_new_label();
723 l2 = gen_new_label();
724
725 mask = 1 << (3 - (bi & 0x03));
726 t0 = tcg_temp_new_i32();
727 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
728 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
729 if (rA(ctx->opcode) == 0)
730 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
731 else
732 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
733 tcg_gen_br(l2);
734 gen_set_label(l1);
735 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
736 gen_set_label(l2);
737 tcg_temp_free_i32(t0);
738 }
739
740 /*** Integer arithmetic ***/
741
742 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
743 TCGv arg1, TCGv arg2, int sub)
744 {
745 int l1;
746 TCGv t0;
747
748 l1 = gen_new_label();
749 /* Start with XER OV disabled, the most likely case */
750 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
751 t0 = tcg_temp_local_new();
752 tcg_gen_xor_tl(t0, arg0, arg1);
753 #if defined(TARGET_PPC64)
754 if (!ctx->sf_mode)
755 tcg_gen_ext32s_tl(t0, t0);
756 #endif
757 if (sub)
758 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
759 else
760 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
761 tcg_gen_xor_tl(t0, arg1, arg2);
762 #if defined(TARGET_PPC64)
763 if (!ctx->sf_mode)
764 tcg_gen_ext32s_tl(t0, t0);
765 #endif
766 if (sub)
767 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
768 else
769 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
770 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
771 gen_set_label(l1);
772 tcg_temp_free(t0);
773 }
774
775 static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1,
776 TCGv arg2, int sub)
777 {
778 int l1 = gen_new_label();
779
780 #if defined(TARGET_PPC64)
781 if (!(ctx->sf_mode)) {
782 TCGv t0, t1;
783 t0 = tcg_temp_new();
784 t1 = tcg_temp_new();
785
786 tcg_gen_ext32u_tl(t0, arg1);
787 tcg_gen_ext32u_tl(t1, arg2);
788 if (sub) {
789 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
790 } else {
791 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
792 }
793 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
794 gen_set_label(l1);
795 tcg_temp_free(t0);
796 tcg_temp_free(t1);
797 } else
798 #endif
799 {
800 if (sub) {
801 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
802 } else {
803 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
804 }
805 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
806 gen_set_label(l1);
807 }
808 }
809
810 /* Common add function */
811 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
812 TCGv arg2, int add_ca, int compute_ca,
813 int compute_ov)
814 {
815 TCGv t0, t1;
816
817 if ((!compute_ca && !compute_ov) ||
818 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
819 t0 = ret;
820 } else {
821 t0 = tcg_temp_local_new();
822 }
823
824 if (add_ca) {
825 t1 = tcg_temp_local_new();
826 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
827 tcg_gen_shri_tl(t1, t1, XER_CA);
828 } else {
829 TCGV_UNUSED(t1);
830 }
831
832 if (compute_ca && compute_ov) {
833 /* Start with XER CA and OV disabled, the most likely case */
834 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
835 } else if (compute_ca) {
836 /* Start with XER CA disabled, the most likely case */
837 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
838 } else if (compute_ov) {
839 /* Start with XER OV disabled, the most likely case */
840 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
841 }
842
843 tcg_gen_add_tl(t0, arg1, arg2);
844
845 if (compute_ca) {
846 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
847 }
848 if (add_ca) {
849 tcg_gen_add_tl(t0, t0, t1);
850 gen_op_arith_compute_ca(ctx, t0, t1, 0);
851 tcg_temp_free(t1);
852 }
853 if (compute_ov) {
854 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
855 }
856
857 if (unlikely(Rc(ctx->opcode) != 0))
858 gen_set_Rc0(ctx, t0);
859
860 if (!TCGV_EQUAL(t0, ret)) {
861 tcg_gen_mov_tl(ret, t0);
862 tcg_temp_free(t0);
863 }
864 }
865 /* Add functions with two operands */
866 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
867 static void glue(gen_, name)(DisasContext *ctx) \
868 { \
869 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
870 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
871 add_ca, compute_ca, compute_ov); \
872 }
873 /* Add functions with one operand and one immediate */
874 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
875 add_ca, compute_ca, compute_ov) \
876 static void glue(gen_, name)(DisasContext *ctx) \
877 { \
878 TCGv t0 = tcg_const_local_tl(const_val); \
879 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
880 cpu_gpr[rA(ctx->opcode)], t0, \
881 add_ca, compute_ca, compute_ov); \
882 tcg_temp_free(t0); \
883 }
884
885 /* add add. addo addo. */
886 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
887 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
888 /* addc addc. addco addco. */
889 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
890 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
891 /* adde adde. addeo addeo. */
892 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
893 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
894 /* addme addme. addmeo addmeo. */
895 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
896 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
897 /* addze addze. addzeo addzeo.*/
898 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
899 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
900 /* addi */
901 static void gen_addi(DisasContext *ctx)
902 {
903 target_long simm = SIMM(ctx->opcode);
904
905 if (rA(ctx->opcode) == 0) {
906 /* li case */
907 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
908 } else {
909 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
910 }
911 }
912 /* addic addic.*/
913 static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1,
914 int compute_Rc0)
915 {
916 target_long simm = SIMM(ctx->opcode);
917
918 /* Start with XER CA and OV disabled, the most likely case */
919 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
920
921 if (likely(simm != 0)) {
922 TCGv t0 = tcg_temp_local_new();
923 tcg_gen_addi_tl(t0, arg1, simm);
924 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
925 tcg_gen_mov_tl(ret, t0);
926 tcg_temp_free(t0);
927 } else {
928 tcg_gen_mov_tl(ret, arg1);
929 }
930 if (compute_Rc0) {
931 gen_set_Rc0(ctx, ret);
932 }
933 }
934
935 static void gen_addic(DisasContext *ctx)
936 {
937 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
938 }
939
940 static void gen_addic_(DisasContext *ctx)
941 {
942 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
943 }
944
945 /* addis */
946 static void gen_addis(DisasContext *ctx)
947 {
948 target_long simm = SIMM(ctx->opcode);
949
950 if (rA(ctx->opcode) == 0) {
951 /* lis case */
952 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
953 } else {
954 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
955 }
956 }
957
958 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
959 TCGv arg2, int sign, int compute_ov)
960 {
961 int l1 = gen_new_label();
962 int l2 = gen_new_label();
963 TCGv_i32 t0 = tcg_temp_local_new_i32();
964 TCGv_i32 t1 = tcg_temp_local_new_i32();
965
966 tcg_gen_trunc_tl_i32(t0, arg1);
967 tcg_gen_trunc_tl_i32(t1, arg2);
968 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
969 if (sign) {
970 int l3 = gen_new_label();
971 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
972 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
973 gen_set_label(l3);
974 tcg_gen_div_i32(t0, t0, t1);
975 } else {
976 tcg_gen_divu_i32(t0, t0, t1);
977 }
978 if (compute_ov) {
979 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
980 }
981 tcg_gen_br(l2);
982 gen_set_label(l1);
983 if (sign) {
984 tcg_gen_sari_i32(t0, t0, 31);
985 } else {
986 tcg_gen_movi_i32(t0, 0);
987 }
988 if (compute_ov) {
989 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
990 }
991 gen_set_label(l2);
992 tcg_gen_extu_i32_tl(ret, t0);
993 tcg_temp_free_i32(t0);
994 tcg_temp_free_i32(t1);
995 if (unlikely(Rc(ctx->opcode) != 0))
996 gen_set_Rc0(ctx, ret);
997 }
998 /* Div functions */
999 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1000 static void glue(gen_, name)(DisasContext *ctx) \
1001 { \
1002 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1003 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1004 sign, compute_ov); \
1005 }
1006 /* divwu divwu. divwuo divwuo. */
1007 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1008 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1009 /* divw divw. divwo divwo. */
1010 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1011 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1012 #if defined(TARGET_PPC64)
1013 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1014 TCGv arg2, int sign, int compute_ov)
1015 {
1016 int l1 = gen_new_label();
1017 int l2 = gen_new_label();
1018
1019 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1020 if (sign) {
1021 int l3 = gen_new_label();
1022 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1023 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1024 gen_set_label(l3);
1025 tcg_gen_div_i64(ret, arg1, arg2);
1026 } else {
1027 tcg_gen_divu_i64(ret, arg1, arg2);
1028 }
1029 if (compute_ov) {
1030 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1031 }
1032 tcg_gen_br(l2);
1033 gen_set_label(l1);
1034 if (sign) {
1035 tcg_gen_sari_i64(ret, arg1, 63);
1036 } else {
1037 tcg_gen_movi_i64(ret, 0);
1038 }
1039 if (compute_ov) {
1040 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1041 }
1042 gen_set_label(l2);
1043 if (unlikely(Rc(ctx->opcode) != 0))
1044 gen_set_Rc0(ctx, ret);
1045 }
1046 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1047 static void glue(gen_, name)(DisasContext *ctx) \
1048 { \
1049 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1050 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1051 sign, compute_ov); \
1052 }
1053 /* divwu divwu. divwuo divwuo. */
1054 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1055 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1056 /* divw divw. divwo divwo. */
1057 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1058 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1059 #endif
1060
1061 /* mulhw mulhw. */
1062 static void gen_mulhw(DisasContext *ctx)
1063 {
1064 TCGv_i64 t0, t1;
1065
1066 t0 = tcg_temp_new_i64();
1067 t1 = tcg_temp_new_i64();
1068 #if defined(TARGET_PPC64)
1069 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1070 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1071 tcg_gen_mul_i64(t0, t0, t1);
1072 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1073 #else
1074 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1075 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1076 tcg_gen_mul_i64(t0, t0, t1);
1077 tcg_gen_shri_i64(t0, t0, 32);
1078 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1079 #endif
1080 tcg_temp_free_i64(t0);
1081 tcg_temp_free_i64(t1);
1082 if (unlikely(Rc(ctx->opcode) != 0))
1083 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1084 }
1085
1086 /* mulhwu mulhwu. */
1087 static void gen_mulhwu(DisasContext *ctx)
1088 {
1089 TCGv_i64 t0, t1;
1090
1091 t0 = tcg_temp_new_i64();
1092 t1 = tcg_temp_new_i64();
1093 #if defined(TARGET_PPC64)
1094 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1095 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1096 tcg_gen_mul_i64(t0, t0, t1);
1097 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1098 #else
1099 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1100 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1101 tcg_gen_mul_i64(t0, t0, t1);
1102 tcg_gen_shri_i64(t0, t0, 32);
1103 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1104 #endif
1105 tcg_temp_free_i64(t0);
1106 tcg_temp_free_i64(t1);
1107 if (unlikely(Rc(ctx->opcode) != 0))
1108 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1109 }
1110
1111 /* mullw mullw. */
1112 static void gen_mullw(DisasContext *ctx)
1113 {
1114 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1115 cpu_gpr[rB(ctx->opcode)]);
1116 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1117 if (unlikely(Rc(ctx->opcode) != 0))
1118 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1119 }
1120
1121 /* mullwo mullwo. */
1122 static void gen_mullwo(DisasContext *ctx)
1123 {
1124 int l1;
1125 TCGv_i64 t0, t1;
1126
1127 t0 = tcg_temp_new_i64();
1128 t1 = tcg_temp_new_i64();
1129 l1 = gen_new_label();
1130 /* Start with XER OV disabled, the most likely case */
1131 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1132 #if defined(TARGET_PPC64)
1133 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1134 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1135 #else
1136 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1137 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1138 #endif
1139 tcg_gen_mul_i64(t0, t0, t1);
1140 #if defined(TARGET_PPC64)
1141 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1142 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1143 #else
1144 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1145 tcg_gen_ext32s_i64(t1, t0);
1146 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1147 #endif
1148 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1149 gen_set_label(l1);
1150 tcg_temp_free_i64(t0);
1151 tcg_temp_free_i64(t1);
1152 if (unlikely(Rc(ctx->opcode) != 0))
1153 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1154 }
1155
1156 /* mulli */
1157 static void gen_mulli(DisasContext *ctx)
1158 {
1159 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1160 SIMM(ctx->opcode));
1161 }
1162 #if defined(TARGET_PPC64)
1163 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1164 static void glue(gen_, name)(DisasContext *ctx) \
1165 { \
1166 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1167 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1168 if (unlikely(Rc(ctx->opcode) != 0)) \
1169 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1170 }
1171 /* mulhd mulhd. */
1172 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1173 /* mulhdu mulhdu. */
1174 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1175
1176 /* mulld mulld. */
1177 static void gen_mulld(DisasContext *ctx)
1178 {
1179 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1180 cpu_gpr[rB(ctx->opcode)]);
1181 if (unlikely(Rc(ctx->opcode) != 0))
1182 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1183 }
1184 /* mulldo mulldo. */
1185 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1186 #endif
1187
1188 /* neg neg. nego nego. */
1189 static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1,
1190 int ov_check)
1191 {
1192 int l1 = gen_new_label();
1193 int l2 = gen_new_label();
1194 TCGv t0 = tcg_temp_local_new();
1195 #if defined(TARGET_PPC64)
1196 if (ctx->sf_mode) {
1197 tcg_gen_mov_tl(t0, arg1);
1198 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1199 } else
1200 #endif
1201 {
1202 tcg_gen_ext32s_tl(t0, arg1);
1203 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1204 }
1205 tcg_gen_neg_tl(ret, arg1);
1206 if (ov_check) {
1207 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1208 }
1209 tcg_gen_br(l2);
1210 gen_set_label(l1);
1211 tcg_gen_mov_tl(ret, t0);
1212 if (ov_check) {
1213 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1214 }
1215 gen_set_label(l2);
1216 tcg_temp_free(t0);
1217 if (unlikely(Rc(ctx->opcode) != 0))
1218 gen_set_Rc0(ctx, ret);
1219 }
1220
1221 static void gen_neg(DisasContext *ctx)
1222 {
1223 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1224 }
1225
1226 static void gen_nego(DisasContext *ctx)
1227 {
1228 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1229 }
1230
1231 /* Common subf function */
1232 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1233 TCGv arg2, int add_ca, int compute_ca,
1234 int compute_ov)
1235 {
1236 TCGv t0, t1;
1237
1238 if ((!compute_ca && !compute_ov) ||
1239 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1240 t0 = ret;
1241 } else {
1242 t0 = tcg_temp_local_new();
1243 }
1244
1245 if (add_ca) {
1246 t1 = tcg_temp_local_new();
1247 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1248 tcg_gen_shri_tl(t1, t1, XER_CA);
1249 } else {
1250 TCGV_UNUSED(t1);
1251 }
1252
1253 if (compute_ca && compute_ov) {
1254 /* Start with XER CA and OV disabled, the most likely case */
1255 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1256 } else if (compute_ca) {
1257 /* Start with XER CA disabled, the most likely case */
1258 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1259 } else if (compute_ov) {
1260 /* Start with XER OV disabled, the most likely case */
1261 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1262 }
1263
1264 if (add_ca) {
1265 tcg_gen_not_tl(t0, arg1);
1266 tcg_gen_add_tl(t0, t0, arg2);
1267 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1268 tcg_gen_add_tl(t0, t0, t1);
1269 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1270 tcg_temp_free(t1);
1271 } else {
1272 tcg_gen_sub_tl(t0, arg2, arg1);
1273 if (compute_ca) {
1274 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1275 }
1276 }
1277 if (compute_ov) {
1278 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1279 }
1280
1281 if (unlikely(Rc(ctx->opcode) != 0))
1282 gen_set_Rc0(ctx, t0);
1283
1284 if (!TCGV_EQUAL(t0, ret)) {
1285 tcg_gen_mov_tl(ret, t0);
1286 tcg_temp_free(t0);
1287 }
1288 }
1289 /* Sub functions with Two operands functions */
1290 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1291 static void glue(gen_, name)(DisasContext *ctx) \
1292 { \
1293 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1294 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1295 add_ca, compute_ca, compute_ov); \
1296 }
1297 /* Sub functions with one operand and one immediate */
1298 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1299 add_ca, compute_ca, compute_ov) \
1300 static void glue(gen_, name)(DisasContext *ctx) \
1301 { \
1302 TCGv t0 = tcg_const_local_tl(const_val); \
1303 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1304 cpu_gpr[rA(ctx->opcode)], t0, \
1305 add_ca, compute_ca, compute_ov); \
1306 tcg_temp_free(t0); \
1307 }
1308 /* subf subf. subfo subfo. */
1309 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1310 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1311 /* subfc subfc. subfco subfco. */
1312 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1313 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1314 /* subfe subfe. subfeo subfo. */
1315 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1316 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1317 /* subfme subfme. subfmeo subfmeo. */
1318 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1319 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1320 /* subfze subfze. subfzeo subfzeo.*/
1321 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1322 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1323
1324 /* subfic */
1325 static void gen_subfic(DisasContext *ctx)
1326 {
1327 /* Start with XER CA and OV disabled, the most likely case */
1328 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1329 TCGv t0 = tcg_temp_local_new();
1330 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1331 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1332 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1333 tcg_temp_free(t1);
1334 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1335 tcg_temp_free(t0);
1336 }
1337
1338 /*** Integer logical ***/
1339 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1340 static void glue(gen_, name)(DisasContext *ctx) \
1341 { \
1342 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1343 cpu_gpr[rB(ctx->opcode)]); \
1344 if (unlikely(Rc(ctx->opcode) != 0)) \
1345 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1346 }
1347
1348 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1349 static void glue(gen_, name)(DisasContext *ctx) \
1350 { \
1351 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1352 if (unlikely(Rc(ctx->opcode) != 0)) \
1353 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1354 }
1355
1356 /* and & and. */
1357 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1358 /* andc & andc. */
1359 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1360
1361 /* andi. */
1362 static void gen_andi_(DisasContext *ctx)
1363 {
1364 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1365 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1366 }
1367
1368 /* andis. */
1369 static void gen_andis_(DisasContext *ctx)
1370 {
1371 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1372 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1373 }
1374
1375 /* cntlzw */
1376 static void gen_cntlzw(DisasContext *ctx)
1377 {
1378 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1379 if (unlikely(Rc(ctx->opcode) != 0))
1380 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1381 }
1382 /* eqv & eqv. */
1383 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1384 /* extsb & extsb. */
1385 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1386 /* extsh & extsh. */
1387 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1388 /* nand & nand. */
1389 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1390 /* nor & nor. */
1391 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1392
1393 /* or & or. */
1394 static void gen_or(DisasContext *ctx)
1395 {
1396 int rs, ra, rb;
1397
1398 rs = rS(ctx->opcode);
1399 ra = rA(ctx->opcode);
1400 rb = rB(ctx->opcode);
1401 /* Optimisation for mr. ri case */
1402 if (rs != ra || rs != rb) {
1403 if (rs != rb)
1404 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1405 else
1406 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1407 if (unlikely(Rc(ctx->opcode) != 0))
1408 gen_set_Rc0(ctx, cpu_gpr[ra]);
1409 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1410 gen_set_Rc0(ctx, cpu_gpr[rs]);
1411 #if defined(TARGET_PPC64)
1412 } else {
1413 int prio = 0;
1414
1415 switch (rs) {
1416 case 1:
1417 /* Set process priority to low */
1418 prio = 2;
1419 break;
1420 case 6:
1421 /* Set process priority to medium-low */
1422 prio = 3;
1423 break;
1424 case 2:
1425 /* Set process priority to normal */
1426 prio = 4;
1427 break;
1428 #if !defined(CONFIG_USER_ONLY)
1429 case 31:
1430 if (ctx->mem_idx > 0) {
1431 /* Set process priority to very low */
1432 prio = 1;
1433 }
1434 break;
1435 case 5:
1436 if (ctx->mem_idx > 0) {
1437 /* Set process priority to medium-hight */
1438 prio = 5;
1439 }
1440 break;
1441 case 3:
1442 if (ctx->mem_idx > 0) {
1443 /* Set process priority to high */
1444 prio = 6;
1445 }
1446 break;
1447 case 7:
1448 if (ctx->mem_idx > 1) {
1449 /* Set process priority to very high */
1450 prio = 7;
1451 }
1452 break;
1453 #endif
1454 default:
1455 /* nop */
1456 break;
1457 }
1458 if (prio) {
1459 TCGv t0 = tcg_temp_new();
1460 gen_load_spr(t0, SPR_PPR);
1461 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1462 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1463 gen_store_spr(SPR_PPR, t0);
1464 tcg_temp_free(t0);
1465 }
1466 #endif
1467 }
1468 }
1469 /* orc & orc. */
1470 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1471
1472 /* xor & xor. */
1473 static void gen_xor(DisasContext *ctx)
1474 {
1475 /* Optimisation for "set to zero" case */
1476 if (rS(ctx->opcode) != rB(ctx->opcode))
1477 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1478 else
1479 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1480 if (unlikely(Rc(ctx->opcode) != 0))
1481 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1482 }
1483
1484 /* ori */
1485 static void gen_ori(DisasContext *ctx)
1486 {
1487 target_ulong uimm = UIMM(ctx->opcode);
1488
1489 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1490 /* NOP */
1491 /* XXX: should handle special NOPs for POWER series */
1492 return;
1493 }
1494 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1495 }
1496
1497 /* oris */
1498 static void gen_oris(DisasContext *ctx)
1499 {
1500 target_ulong uimm = UIMM(ctx->opcode);
1501
1502 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1503 /* NOP */
1504 return;
1505 }
1506 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1507 }
1508
1509 /* xori */
1510 static void gen_xori(DisasContext *ctx)
1511 {
1512 target_ulong uimm = UIMM(ctx->opcode);
1513
1514 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1515 /* NOP */
1516 return;
1517 }
1518 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1519 }
1520
1521 /* xoris */
1522 static void gen_xoris(DisasContext *ctx)
1523 {
1524 target_ulong uimm = UIMM(ctx->opcode);
1525
1526 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1527 /* NOP */
1528 return;
1529 }
1530 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1531 }
1532
1533 /* popcntb : PowerPC 2.03 specification */
1534 static void gen_popcntb(DisasContext *ctx)
1535 {
1536 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1537 }
1538
1539 static void gen_popcntw(DisasContext *ctx)
1540 {
1541 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1542 }
1543
1544 #if defined(TARGET_PPC64)
1545 /* popcntd: PowerPC 2.06 specification */
1546 static void gen_popcntd(DisasContext *ctx)
1547 {
1548 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1549 }
1550 #endif
1551
1552 #if defined(TARGET_PPC64)
1553 /* extsw & extsw. */
1554 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1555
1556 /* cntlzd */
1557 static void gen_cntlzd(DisasContext *ctx)
1558 {
1559 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1560 if (unlikely(Rc(ctx->opcode) != 0))
1561 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1562 }
1563 #endif
1564
1565 /*** Integer rotate ***/
1566
1567 /* rlwimi & rlwimi. */
1568 static void gen_rlwimi(DisasContext *ctx)
1569 {
1570 uint32_t mb, me, sh;
1571
1572 mb = MB(ctx->opcode);
1573 me = ME(ctx->opcode);
1574 sh = SH(ctx->opcode);
1575 if (likely(sh == 0 && mb == 0 && me == 31)) {
1576 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1577 } else {
1578 target_ulong mask;
1579 TCGv t1;
1580 TCGv t0 = tcg_temp_new();
1581 #if defined(TARGET_PPC64)
1582 TCGv_i32 t2 = tcg_temp_new_i32();
1583 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1584 tcg_gen_rotli_i32(t2, t2, sh);
1585 tcg_gen_extu_i32_i64(t0, t2);
1586 tcg_temp_free_i32(t2);
1587 #else
1588 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1589 #endif
1590 #if defined(TARGET_PPC64)
1591 mb += 32;
1592 me += 32;
1593 #endif
1594 mask = MASK(mb, me);
1595 t1 = tcg_temp_new();
1596 tcg_gen_andi_tl(t0, t0, mask);
1597 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1598 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1599 tcg_temp_free(t0);
1600 tcg_temp_free(t1);
1601 }
1602 if (unlikely(Rc(ctx->opcode) != 0))
1603 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1604 }
1605
1606 /* rlwinm & rlwinm. */
1607 static void gen_rlwinm(DisasContext *ctx)
1608 {
1609 uint32_t mb, me, sh;
1610
1611 sh = SH(ctx->opcode);
1612 mb = MB(ctx->opcode);
1613 me = ME(ctx->opcode);
1614
1615 if (likely(mb == 0 && me == (31 - sh))) {
1616 if (likely(sh == 0)) {
1617 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1618 } else {
1619 TCGv t0 = tcg_temp_new();
1620 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1621 tcg_gen_shli_tl(t0, t0, sh);
1622 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1623 tcg_temp_free(t0);
1624 }
1625 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1626 TCGv t0 = tcg_temp_new();
1627 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1628 tcg_gen_shri_tl(t0, t0, mb);
1629 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1630 tcg_temp_free(t0);
1631 } else {
1632 TCGv t0 = tcg_temp_new();
1633 #if defined(TARGET_PPC64)
1634 TCGv_i32 t1 = tcg_temp_new_i32();
1635 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1636 tcg_gen_rotli_i32(t1, t1, sh);
1637 tcg_gen_extu_i32_i64(t0, t1);
1638 tcg_temp_free_i32(t1);
1639 #else
1640 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1641 #endif
1642 #if defined(TARGET_PPC64)
1643 mb += 32;
1644 me += 32;
1645 #endif
1646 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1647 tcg_temp_free(t0);
1648 }
1649 if (unlikely(Rc(ctx->opcode) != 0))
1650 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1651 }
1652
1653 /* rlwnm & rlwnm. */
1654 static void gen_rlwnm(DisasContext *ctx)
1655 {
1656 uint32_t mb, me;
1657 TCGv t0;
1658 #if defined(TARGET_PPC64)
1659 TCGv_i32 t1, t2;
1660 #endif
1661
1662 mb = MB(ctx->opcode);
1663 me = ME(ctx->opcode);
1664 t0 = tcg_temp_new();
1665 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1666 #if defined(TARGET_PPC64)
1667 t1 = tcg_temp_new_i32();
1668 t2 = tcg_temp_new_i32();
1669 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1670 tcg_gen_trunc_i64_i32(t2, t0);
1671 tcg_gen_rotl_i32(t1, t1, t2);
1672 tcg_gen_extu_i32_i64(t0, t1);
1673 tcg_temp_free_i32(t1);
1674 tcg_temp_free_i32(t2);
1675 #else
1676 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1677 #endif
1678 if (unlikely(mb != 0 || me != 31)) {
1679 #if defined(TARGET_PPC64)
1680 mb += 32;
1681 me += 32;
1682 #endif
1683 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1684 } else {
1685 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1686 }
1687 tcg_temp_free(t0);
1688 if (unlikely(Rc(ctx->opcode) != 0))
1689 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1690 }
1691
1692 #if defined(TARGET_PPC64)
1693 #define GEN_PPC64_R2(name, opc1, opc2) \
1694 static void glue(gen_, name##0)(DisasContext *ctx) \
1695 { \
1696 gen_##name(ctx, 0); \
1697 } \
1698 \
1699 static void glue(gen_, name##1)(DisasContext *ctx) \
1700 { \
1701 gen_##name(ctx, 1); \
1702 }
1703 #define GEN_PPC64_R4(name, opc1, opc2) \
1704 static void glue(gen_, name##0)(DisasContext *ctx) \
1705 { \
1706 gen_##name(ctx, 0, 0); \
1707 } \
1708 \
1709 static void glue(gen_, name##1)(DisasContext *ctx) \
1710 { \
1711 gen_##name(ctx, 0, 1); \
1712 } \
1713 \
1714 static void glue(gen_, name##2)(DisasContext *ctx) \
1715 { \
1716 gen_##name(ctx, 1, 0); \
1717 } \
1718 \
1719 static void glue(gen_, name##3)(DisasContext *ctx) \
1720 { \
1721 gen_##name(ctx, 1, 1); \
1722 }
1723
1724 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1725 uint32_t sh)
1726 {
1727 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1728 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1729 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1730 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1731 } else {
1732 TCGv t0 = tcg_temp_new();
1733 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1734 if (likely(mb == 0 && me == 63)) {
1735 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1736 } else {
1737 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1738 }
1739 tcg_temp_free(t0);
1740 }
1741 if (unlikely(Rc(ctx->opcode) != 0))
1742 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1743 }
1744 /* rldicl - rldicl. */
1745 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1746 {
1747 uint32_t sh, mb;
1748
1749 sh = SH(ctx->opcode) | (shn << 5);
1750 mb = MB(ctx->opcode) | (mbn << 5);
1751 gen_rldinm(ctx, mb, 63, sh);
1752 }
1753 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1754 /* rldicr - rldicr. */
1755 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1756 {
1757 uint32_t sh, me;
1758
1759 sh = SH(ctx->opcode) | (shn << 5);
1760 me = MB(ctx->opcode) | (men << 5);
1761 gen_rldinm(ctx, 0, me, sh);
1762 }
1763 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1764 /* rldic - rldic. */
1765 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1766 {
1767 uint32_t sh, mb;
1768
1769 sh = SH(ctx->opcode) | (shn << 5);
1770 mb = MB(ctx->opcode) | (mbn << 5);
1771 gen_rldinm(ctx, mb, 63 - sh, sh);
1772 }
1773 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1774
1775 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1776 {
1777 TCGv t0;
1778
1779 mb = MB(ctx->opcode);
1780 me = ME(ctx->opcode);
1781 t0 = tcg_temp_new();
1782 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1783 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1784 if (unlikely(mb != 0 || me != 63)) {
1785 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1786 } else {
1787 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1788 }
1789 tcg_temp_free(t0);
1790 if (unlikely(Rc(ctx->opcode) != 0))
1791 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1792 }
1793
1794 /* rldcl - rldcl. */
1795 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1796 {
1797 uint32_t mb;
1798
1799 mb = MB(ctx->opcode) | (mbn << 5);
1800 gen_rldnm(ctx, mb, 63);
1801 }
1802 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1803 /* rldcr - rldcr. */
1804 static inline void gen_rldcr(DisasContext *ctx, int men)
1805 {
1806 uint32_t me;
1807
1808 me = MB(ctx->opcode) | (men << 5);
1809 gen_rldnm(ctx, 0, me);
1810 }
1811 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1812 /* rldimi - rldimi. */
1813 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1814 {
1815 uint32_t sh, mb, me;
1816
1817 sh = SH(ctx->opcode) | (shn << 5);
1818 mb = MB(ctx->opcode) | (mbn << 5);
1819 me = 63 - sh;
1820 if (unlikely(sh == 0 && mb == 0)) {
1821 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1822 } else {
1823 TCGv t0, t1;
1824 target_ulong mask;
1825
1826 t0 = tcg_temp_new();
1827 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1828 t1 = tcg_temp_new();
1829 mask = MASK(mb, me);
1830 tcg_gen_andi_tl(t0, t0, mask);
1831 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1832 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1833 tcg_temp_free(t0);
1834 tcg_temp_free(t1);
1835 }
1836 if (unlikely(Rc(ctx->opcode) != 0))
1837 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1838 }
1839 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1840 #endif
1841
1842 /*** Integer shift ***/
1843
1844 /* slw & slw. */
1845 static void gen_slw(DisasContext *ctx)
1846 {
1847 TCGv t0, t1;
1848
1849 t0 = tcg_temp_new();
1850 /* AND rS with a mask that is 0 when rB >= 0x20 */
1851 #if defined(TARGET_PPC64)
1852 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1853 tcg_gen_sari_tl(t0, t0, 0x3f);
1854 #else
1855 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1856 tcg_gen_sari_tl(t0, t0, 0x1f);
1857 #endif
1858 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1859 t1 = tcg_temp_new();
1860 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1861 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1862 tcg_temp_free(t1);
1863 tcg_temp_free(t0);
1864 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1865 if (unlikely(Rc(ctx->opcode) != 0))
1866 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1867 }
1868
1869 /* sraw & sraw. */
1870 static void gen_sraw(DisasContext *ctx)
1871 {
1872 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1873 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1874 if (unlikely(Rc(ctx->opcode) != 0))
1875 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1876 }
1877
1878 /* srawi & srawi. */
1879 static void gen_srawi(DisasContext *ctx)
1880 {
1881 int sh = SH(ctx->opcode);
1882 if (sh != 0) {
1883 int l1, l2;
1884 TCGv t0;
1885 l1 = gen_new_label();
1886 l2 = gen_new_label();
1887 t0 = tcg_temp_local_new();
1888 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1889 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1890 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1891 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1892 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1893 tcg_gen_br(l2);
1894 gen_set_label(l1);
1895 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1896 gen_set_label(l2);
1897 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1898 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1899 tcg_temp_free(t0);
1900 } else {
1901 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1902 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1903 }
1904 if (unlikely(Rc(ctx->opcode) != 0))
1905 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1906 }
1907
1908 /* srw & srw. */
1909 static void gen_srw(DisasContext *ctx)
1910 {
1911 TCGv t0, t1;
1912
1913 t0 = tcg_temp_new();
1914 /* AND rS with a mask that is 0 when rB >= 0x20 */
1915 #if defined(TARGET_PPC64)
1916 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1917 tcg_gen_sari_tl(t0, t0, 0x3f);
1918 #else
1919 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1920 tcg_gen_sari_tl(t0, t0, 0x1f);
1921 #endif
1922 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1923 tcg_gen_ext32u_tl(t0, t0);
1924 t1 = tcg_temp_new();
1925 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1926 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1927 tcg_temp_free(t1);
1928 tcg_temp_free(t0);
1929 if (unlikely(Rc(ctx->opcode) != 0))
1930 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1931 }
1932
1933 #if defined(TARGET_PPC64)
1934 /* sld & sld. */
1935 static void gen_sld(DisasContext *ctx)
1936 {
1937 TCGv t0, t1;
1938
1939 t0 = tcg_temp_new();
1940 /* AND rS with a mask that is 0 when rB >= 0x40 */
1941 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1942 tcg_gen_sari_tl(t0, t0, 0x3f);
1943 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1944 t1 = tcg_temp_new();
1945 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1946 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1947 tcg_temp_free(t1);
1948 tcg_temp_free(t0);
1949 if (unlikely(Rc(ctx->opcode) != 0))
1950 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1951 }
1952
1953 /* srad & srad. */
1954 static void gen_srad(DisasContext *ctx)
1955 {
1956 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
1957 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1958 if (unlikely(Rc(ctx->opcode) != 0))
1959 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1960 }
1961 /* sradi & sradi. */
1962 static inline void gen_sradi(DisasContext *ctx, int n)
1963 {
1964 int sh = SH(ctx->opcode) + (n << 5);
1965 if (sh != 0) {
1966 int l1, l2;
1967 TCGv t0;
1968 l1 = gen_new_label();
1969 l2 = gen_new_label();
1970 t0 = tcg_temp_local_new();
1971 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
1972 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1973 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1974 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1975 tcg_gen_br(l2);
1976 gen_set_label(l1);
1977 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1978 gen_set_label(l2);
1979 tcg_temp_free(t0);
1980 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1981 } else {
1982 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1983 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1984 }
1985 if (unlikely(Rc(ctx->opcode) != 0))
1986 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1987 }
1988
1989 static void gen_sradi0(DisasContext *ctx)
1990 {
1991 gen_sradi(ctx, 0);
1992 }
1993
1994 static void gen_sradi1(DisasContext *ctx)
1995 {
1996 gen_sradi(ctx, 1);
1997 }
1998
1999 /* srd & srd. */
2000 static void gen_srd(DisasContext *ctx)
2001 {
2002 TCGv t0, t1;
2003
2004 t0 = tcg_temp_new();
2005 /* AND rS with a mask that is 0 when rB >= 0x40 */
2006 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2007 tcg_gen_sari_tl(t0, t0, 0x3f);
2008 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2009 t1 = tcg_temp_new();
2010 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2011 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2012 tcg_temp_free(t1);
2013 tcg_temp_free(t0);
2014 if (unlikely(Rc(ctx->opcode) != 0))
2015 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2016 }
2017 #endif
2018
2019 /*** Floating-Point arithmetic ***/
2020 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2021 static void gen_f##name(DisasContext *ctx) \
2022 { \
2023 if (unlikely(!ctx->fpu_enabled)) { \
2024 gen_exception(ctx, POWERPC_EXCP_FPU); \
2025 return; \
2026 } \
2027 /* NIP cannot be restored if the memory exception comes from an helper */ \
2028 gen_update_nip(ctx, ctx->nip - 4); \
2029 gen_reset_fpstatus(); \
2030 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2031 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2032 if (isfloat) { \
2033 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2034 } \
2035 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2036 Rc(ctx->opcode) != 0); \
2037 }
2038
2039 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2040 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2041 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2042
2043 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2044 static void gen_f##name(DisasContext *ctx) \
2045 { \
2046 if (unlikely(!ctx->fpu_enabled)) { \
2047 gen_exception(ctx, POWERPC_EXCP_FPU); \
2048 return; \
2049 } \
2050 /* NIP cannot be restored if the memory exception comes from an helper */ \
2051 gen_update_nip(ctx, ctx->nip - 4); \
2052 gen_reset_fpstatus(); \
2053 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2054 cpu_fpr[rB(ctx->opcode)]); \
2055 if (isfloat) { \
2056 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2057 } \
2058 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2059 set_fprf, Rc(ctx->opcode) != 0); \
2060 }
2061 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2062 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2063 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2064
2065 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2066 static void gen_f##name(DisasContext *ctx) \
2067 { \
2068 if (unlikely(!ctx->fpu_enabled)) { \
2069 gen_exception(ctx, POWERPC_EXCP_FPU); \
2070 return; \
2071 } \
2072 /* NIP cannot be restored if the memory exception comes from an helper */ \
2073 gen_update_nip(ctx, ctx->nip - 4); \
2074 gen_reset_fpstatus(); \
2075 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2076 cpu_fpr[rC(ctx->opcode)]); \
2077 if (isfloat) { \
2078 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2079 } \
2080 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2081 set_fprf, Rc(ctx->opcode) != 0); \
2082 }
2083 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2084 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2085 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2086
2087 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2088 static void gen_f##name(DisasContext *ctx) \
2089 { \
2090 if (unlikely(!ctx->fpu_enabled)) { \
2091 gen_exception(ctx, POWERPC_EXCP_FPU); \
2092 return; \
2093 } \
2094 /* NIP cannot be restored if the memory exception comes from an helper */ \
2095 gen_update_nip(ctx, ctx->nip - 4); \
2096 gen_reset_fpstatus(); \
2097 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2098 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2099 set_fprf, Rc(ctx->opcode) != 0); \
2100 }
2101
2102 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2103 static void gen_f##name(DisasContext *ctx) \
2104 { \
2105 if (unlikely(!ctx->fpu_enabled)) { \
2106 gen_exception(ctx, POWERPC_EXCP_FPU); \
2107 return; \
2108 } \
2109 /* NIP cannot be restored if the memory exception comes from an helper */ \
2110 gen_update_nip(ctx, ctx->nip - 4); \
2111 gen_reset_fpstatus(); \
2112 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2113 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2114 set_fprf, Rc(ctx->opcode) != 0); \
2115 }
2116
2117 /* fadd - fadds */
2118 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2119 /* fdiv - fdivs */
2120 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2121 /* fmul - fmuls */
2122 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2123
2124 /* fre */
2125 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2126
2127 /* fres */
2128 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2129
2130 /* frsqrte */
2131 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2132
2133 /* frsqrtes */
2134 static void gen_frsqrtes(DisasContext *ctx)
2135 {
2136 if (unlikely(!ctx->fpu_enabled)) {
2137 gen_exception(ctx, POWERPC_EXCP_FPU);
2138 return;
2139 }
2140 /* NIP cannot be restored if the memory exception comes from an helper */
2141 gen_update_nip(ctx, ctx->nip - 4);
2142 gen_reset_fpstatus();
2143 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2144 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2145 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2146 }
2147
2148 /* fsel */
2149 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2150 /* fsub - fsubs */
2151 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2152 /* Optional: */
2153
2154 /* fsqrt */
2155 static void gen_fsqrt(DisasContext *ctx)
2156 {
2157 if (unlikely(!ctx->fpu_enabled)) {
2158 gen_exception(ctx, POWERPC_EXCP_FPU);
2159 return;
2160 }
2161 /* NIP cannot be restored if the memory exception comes from an helper */
2162 gen_update_nip(ctx, ctx->nip - 4);
2163 gen_reset_fpstatus();
2164 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2165 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2166 }
2167
2168 static void gen_fsqrts(DisasContext *ctx)
2169 {
2170 if (unlikely(!ctx->fpu_enabled)) {
2171 gen_exception(ctx, POWERPC_EXCP_FPU);
2172 return;
2173 }
2174 /* NIP cannot be restored if the memory exception comes from an helper */
2175 gen_update_nip(ctx, ctx->nip - 4);
2176 gen_reset_fpstatus();
2177 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2178 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2179 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2180 }
2181
2182 /*** Floating-Point multiply-and-add ***/
2183 /* fmadd - fmadds */
2184 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2185 /* fmsub - fmsubs */
2186 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2187 /* fnmadd - fnmadds */
2188 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2189 /* fnmsub - fnmsubs */
2190 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2191
2192 /*** Floating-Point round & convert ***/
2193 /* fctiw */
2194 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2195 /* fctiwz */
2196 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2197 /* frsp */
2198 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2199 #if defined(TARGET_PPC64)
2200 /* fcfid */
2201 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2202 /* fctid */
2203 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2204 /* fctidz */
2205 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2206 #endif
2207
2208 /* frin */
2209 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2210 /* friz */
2211 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2212 /* frip */
2213 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2214 /* frim */
2215 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2216
2217 /*** Floating-Point compare ***/
2218
2219 /* fcmpo */
2220 static void gen_fcmpo(DisasContext *ctx)
2221 {
2222 TCGv_i32 crf;
2223 if (unlikely(!ctx->fpu_enabled)) {
2224 gen_exception(ctx, POWERPC_EXCP_FPU);
2225 return;
2226 }
2227 /* NIP cannot be restored if the memory exception comes from an helper */
2228 gen_update_nip(ctx, ctx->nip - 4);
2229 gen_reset_fpstatus();
2230 crf = tcg_const_i32(crfD(ctx->opcode));
2231 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2232 tcg_temp_free_i32(crf);
2233 gen_helper_float_check_status();
2234 }
2235
2236 /* fcmpu */
2237 static void gen_fcmpu(DisasContext *ctx)
2238 {
2239 TCGv_i32 crf;
2240 if (unlikely(!ctx->fpu_enabled)) {
2241 gen_exception(ctx, POWERPC_EXCP_FPU);
2242 return;
2243 }
2244 /* NIP cannot be restored if the memory exception comes from an helper */
2245 gen_update_nip(ctx, ctx->nip - 4);
2246 gen_reset_fpstatus();
2247 crf = tcg_const_i32(crfD(ctx->opcode));
2248 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2249 tcg_temp_free_i32(crf);
2250 gen_helper_float_check_status();
2251 }
2252
2253 /*** Floating-point move ***/
2254 /* fabs */
2255 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2256 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2257
2258 /* fmr - fmr. */
2259 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2260 static void gen_fmr(DisasContext *ctx)
2261 {
2262 if (unlikely(!ctx->fpu_enabled)) {
2263 gen_exception(ctx, POWERPC_EXCP_FPU);
2264 return;
2265 }
2266 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2267 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2268 }
2269
2270 /* fnabs */
2271 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2272 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2273 /* fneg */
2274 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2275 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2276
2277 /*** Floating-Point status & ctrl register ***/
2278
2279 /* mcrfs */
2280 static void gen_mcrfs(DisasContext *ctx)
2281 {
2282 int bfa;
2283
2284 if (unlikely(!ctx->fpu_enabled)) {
2285 gen_exception(ctx, POWERPC_EXCP_FPU);
2286 return;
2287 }
2288 bfa = 4 * (7 - crfS(ctx->opcode));
2289 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2290 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2291 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2292 }
2293
2294 /* mffs */
2295 static void gen_mffs(DisasContext *ctx)
2296 {
2297 if (unlikely(!ctx->fpu_enabled)) {
2298 gen_exception(ctx, POWERPC_EXCP_FPU);
2299 return;
2300 }
2301 gen_reset_fpstatus();
2302 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2303 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2304 }
2305
2306 /* mtfsb0 */
2307 static void gen_mtfsb0(DisasContext *ctx)
2308 {
2309 uint8_t crb;
2310
2311 if (unlikely(!ctx->fpu_enabled)) {
2312 gen_exception(ctx, POWERPC_EXCP_FPU);
2313 return;
2314 }
2315 crb = 31 - crbD(ctx->opcode);
2316 gen_reset_fpstatus();
2317 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2318 TCGv_i32 t0;
2319 /* NIP cannot be restored if the memory exception comes from an helper */
2320 gen_update_nip(ctx, ctx->nip - 4);
2321 t0 = tcg_const_i32(crb);
2322 gen_helper_fpscr_clrbit(t0);
2323 tcg_temp_free_i32(t0);
2324 }
2325 if (unlikely(Rc(ctx->opcode) != 0)) {
2326 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2327 }
2328 }
2329
2330 /* mtfsb1 */
2331 static void gen_mtfsb1(DisasContext *ctx)
2332 {
2333 uint8_t crb;
2334
2335 if (unlikely(!ctx->fpu_enabled)) {
2336 gen_exception(ctx, POWERPC_EXCP_FPU);
2337 return;
2338 }
2339 crb = 31 - crbD(ctx->opcode);
2340 gen_reset_fpstatus();
2341 /* XXX: we pretend we can only do IEEE floating-point computations */
2342 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2343 TCGv_i32 t0;
2344 /* NIP cannot be restored if the memory exception comes from an helper */
2345 gen_update_nip(ctx, ctx->nip - 4);
2346 t0 = tcg_const_i32(crb);
2347 gen_helper_fpscr_setbit(t0);
2348 tcg_temp_free_i32(t0);
2349 }
2350 if (unlikely(Rc(ctx->opcode) != 0)) {
2351 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2352 }
2353 /* We can raise a differed exception */
2354 gen_helper_float_check_status();
2355 }
2356
2357 /* mtfsf */
2358 static void gen_mtfsf(DisasContext *ctx)
2359 {
2360 TCGv_i32 t0;
2361 int L = ctx->opcode & 0x02000000;
2362
2363 if (unlikely(!ctx->fpu_enabled)) {
2364 gen_exception(ctx, POWERPC_EXCP_FPU);
2365 return;
2366 }
2367 /* NIP cannot be restored if the memory exception comes from an helper */
2368 gen_update_nip(ctx, ctx->nip - 4);
2369 gen_reset_fpstatus();
2370 if (L)
2371 t0 = tcg_const_i32(0xff);
2372 else
2373 t0 = tcg_const_i32(FM(ctx->opcode));
2374 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2375 tcg_temp_free_i32(t0);
2376 if (unlikely(Rc(ctx->opcode) != 0)) {
2377 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2378 }
2379 /* We can raise a differed exception */
2380 gen_helper_float_check_status();
2381 }
2382
2383 /* mtfsfi */
2384 static void gen_mtfsfi(DisasContext *ctx)
2385 {
2386 int bf, sh;
2387 TCGv_i64 t0;
2388 TCGv_i32 t1;
2389
2390 if (unlikely(!ctx->fpu_enabled)) {
2391 gen_exception(ctx, POWERPC_EXCP_FPU);
2392 return;
2393 }
2394 bf = crbD(ctx->opcode) >> 2;
2395 sh = 7 - bf;
2396 /* NIP cannot be restored if the memory exception comes from an helper */
2397 gen_update_nip(ctx, ctx->nip - 4);
2398 gen_reset_fpstatus();
2399 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2400 t1 = tcg_const_i32(1 << sh);
2401 gen_helper_store_fpscr(t0, t1);
2402 tcg_temp_free_i64(t0);
2403 tcg_temp_free_i32(t1);
2404 if (unlikely(Rc(ctx->opcode) != 0)) {
2405 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2406 }
2407 /* We can raise a differed exception */
2408 gen_helper_float_check_status();
2409 }
2410
2411 /*** Addressing modes ***/
2412 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2413 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2414 target_long maskl)
2415 {
2416 target_long simm = SIMM(ctx->opcode);
2417
2418 simm &= ~maskl;
2419 if (rA(ctx->opcode) == 0) {
2420 #if defined(TARGET_PPC64)
2421 if (!ctx->sf_mode) {
2422 tcg_gen_movi_tl(EA, (uint32_t)simm);
2423 } else
2424 #endif
2425 tcg_gen_movi_tl(EA, simm);
2426 } else if (likely(simm != 0)) {
2427 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2428 #if defined(TARGET_PPC64)
2429 if (!ctx->sf_mode) {
2430 tcg_gen_ext32u_tl(EA, EA);
2431 }
2432 #endif
2433 } else {
2434 #if defined(TARGET_PPC64)
2435 if (!ctx->sf_mode) {
2436 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2437 } else
2438 #endif
2439 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2440 }
2441 }
2442
2443 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2444 {
2445 if (rA(ctx->opcode) == 0) {
2446 #if defined(TARGET_PPC64)
2447 if (!ctx->sf_mode) {
2448 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2449 } else
2450 #endif
2451 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2452 } else {
2453 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2454 #if defined(TARGET_PPC64)
2455 if (!ctx->sf_mode) {
2456 tcg_gen_ext32u_tl(EA, EA);
2457 }
2458 #endif
2459 }
2460 }
2461
2462 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2463 {
2464 if (rA(ctx->opcode) == 0) {
2465 tcg_gen_movi_tl(EA, 0);
2466 } else {
2467 #if defined(TARGET_PPC64)
2468 if (!ctx->sf_mode) {
2469 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2470 } else
2471 #endif
2472 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2473 }
2474 }
2475
2476 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2477 target_long val)
2478 {
2479 tcg_gen_addi_tl(ret, arg1, val);
2480 #if defined(TARGET_PPC64)
2481 if (!ctx->sf_mode) {
2482 tcg_gen_ext32u_tl(ret, ret);
2483 }
2484 #endif
2485 }
2486
2487 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2488 {
2489 int l1 = gen_new_label();
2490 TCGv t0 = tcg_temp_new();
2491 TCGv_i32 t1, t2;
2492 /* NIP cannot be restored if the memory exception comes from an helper */
2493 gen_update_nip(ctx, ctx->nip - 4);
2494 tcg_gen_andi_tl(t0, EA, mask);
2495 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2496 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2497 t2 = tcg_const_i32(0);
2498 gen_helper_raise_exception_err(cpu_env, t1, t2);
2499 tcg_temp_free_i32(t1);
2500 tcg_temp_free_i32(t2);
2501 gen_set_label(l1);
2502 tcg_temp_free(t0);
2503 }
2504
2505 /*** Integer load ***/
2506 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2507 {
2508 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2509 }
2510
2511 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2512 {
2513 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2514 }
2515
2516 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2517 {
2518 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2519 if (unlikely(ctx->le_mode)) {
2520 tcg_gen_bswap16_tl(arg1, arg1);
2521 }
2522 }
2523
2524 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2525 {
2526 if (unlikely(ctx->le_mode)) {
2527 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2528 tcg_gen_bswap16_tl(arg1, arg1);
2529 tcg_gen_ext16s_tl(arg1, arg1);
2530 } else {
2531 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2532 }
2533 }
2534
2535 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2536 {
2537 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2538 if (unlikely(ctx->le_mode)) {
2539 tcg_gen_bswap32_tl(arg1, arg1);
2540 }
2541 }
2542
2543 #if defined(TARGET_PPC64)
2544 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2545 {
2546 if (unlikely(ctx->le_mode)) {
2547 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2548 tcg_gen_bswap32_tl(arg1, arg1);
2549 tcg_gen_ext32s_tl(arg1, arg1);
2550 } else
2551 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2552 }
2553 #endif
2554
2555 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2556 {
2557 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2558 if (unlikely(ctx->le_mode)) {
2559 tcg_gen_bswap64_i64(arg1, arg1);
2560 }
2561 }
2562
2563 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2564 {
2565 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2566 }
2567
2568 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2569 {
2570 if (unlikely(ctx->le_mode)) {
2571 TCGv t0 = tcg_temp_new();
2572 tcg_gen_ext16u_tl(t0, arg1);
2573 tcg_gen_bswap16_tl(t0, t0);
2574 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2575 tcg_temp_free(t0);
2576 } else {
2577 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2578 }
2579 }
2580
2581 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2582 {
2583 if (unlikely(ctx->le_mode)) {
2584 TCGv t0 = tcg_temp_new();
2585 tcg_gen_ext32u_tl(t0, arg1);
2586 tcg_gen_bswap32_tl(t0, t0);
2587 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2588 tcg_temp_free(t0);
2589 } else {
2590 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2591 }
2592 }
2593
2594 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2595 {
2596 if (unlikely(ctx->le_mode)) {
2597 TCGv_i64 t0 = tcg_temp_new_i64();
2598 tcg_gen_bswap64_i64(t0, arg1);
2599 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2600 tcg_temp_free_i64(t0);
2601 } else
2602 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2603 }
2604
2605 #define GEN_LD(name, ldop, opc, type) \
2606 static void glue(gen_, name)(DisasContext *ctx) \
2607 { \
2608 TCGv EA; \
2609 gen_set_access_type(ctx, ACCESS_INT); \
2610 EA = tcg_temp_new(); \
2611 gen_addr_imm_index(ctx, EA, 0); \
2612 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2613 tcg_temp_free(EA); \
2614 }
2615
2616 #define GEN_LDU(name, ldop, opc, type) \
2617 static void glue(gen_, name##u)(DisasContext *ctx) \
2618 { \
2619 TCGv EA; \
2620 if (unlikely(rA(ctx->opcode) == 0 || \
2621 rA(ctx->opcode) == rD(ctx->opcode))) { \
2622 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2623 return; \
2624 } \
2625 gen_set_access_type(ctx, ACCESS_INT); \
2626 EA = tcg_temp_new(); \
2627 if (type == PPC_64B) \
2628 gen_addr_imm_index(ctx, EA, 0x03); \
2629 else \
2630 gen_addr_imm_index(ctx, EA, 0); \
2631 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2632 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2633 tcg_temp_free(EA); \
2634 }
2635
2636 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2637 static void glue(gen_, name##ux)(DisasContext *ctx) \
2638 { \
2639 TCGv EA; \
2640 if (unlikely(rA(ctx->opcode) == 0 || \
2641 rA(ctx->opcode) == rD(ctx->opcode))) { \
2642 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2643 return; \
2644 } \
2645 gen_set_access_type(ctx, ACCESS_INT); \
2646 EA = tcg_temp_new(); \
2647 gen_addr_reg_index(ctx, EA); \
2648 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2649 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2650 tcg_temp_free(EA); \
2651 }
2652
2653 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2654 static void glue(gen_, name##x)(DisasContext *ctx) \
2655 { \
2656 TCGv EA; \
2657 gen_set_access_type(ctx, ACCESS_INT); \
2658 EA = tcg_temp_new(); \
2659 gen_addr_reg_index(ctx, EA); \
2660 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2661 tcg_temp_free(EA); \
2662 }
2663 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2664 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2665
2666 #define GEN_LDS(name, ldop, op, type) \
2667 GEN_LD(name, ldop, op | 0x20, type); \
2668 GEN_LDU(name, ldop, op | 0x21, type); \
2669 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2670 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2671
2672 /* lbz lbzu lbzux lbzx */
2673 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2674 /* lha lhau lhaux lhax */
2675 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2676 /* lhz lhzu lhzux lhzx */
2677 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2678 /* lwz lwzu lwzux lwzx */
2679 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2680 #if defined(TARGET_PPC64)
2681 /* lwaux */
2682 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2683 /* lwax */
2684 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2685 /* ldux */
2686 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2687 /* ldx */
2688 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2689
2690 static void gen_ld(DisasContext *ctx)
2691 {
2692 TCGv EA;
2693 if (Rc(ctx->opcode)) {
2694 if (unlikely(rA(ctx->opcode) == 0 ||
2695 rA(ctx->opcode) == rD(ctx->opcode))) {
2696 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2697 return;
2698 }
2699 }
2700 gen_set_access_type(ctx, ACCESS_INT);
2701 EA = tcg_temp_new();
2702 gen_addr_imm_index(ctx, EA, 0x03);
2703 if (ctx->opcode & 0x02) {
2704 /* lwa (lwau is undefined) */
2705 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2706 } else {
2707 /* ld - ldu */
2708 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2709 }
2710 if (Rc(ctx->opcode))
2711 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2712 tcg_temp_free(EA);
2713 }
2714
2715 /* lq */
2716 static void gen_lq(DisasContext *ctx)
2717 {
2718 #if defined(CONFIG_USER_ONLY)
2719 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2720 #else
2721 int ra, rd;
2722 TCGv EA;
2723
2724 /* Restore CPU state */
2725 if (unlikely(ctx->mem_idx == 0)) {
2726 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2727 return;
2728 }
2729 ra = rA(ctx->opcode);
2730 rd = rD(ctx->opcode);
2731 if (unlikely((rd & 1) || rd == ra)) {
2732 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2733 return;
2734 }
2735 if (unlikely(ctx->le_mode)) {
2736 /* Little-endian mode is not handled */
2737 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2738 return;
2739 }
2740 gen_set_access_type(ctx, ACCESS_INT);
2741 EA = tcg_temp_new();
2742 gen_addr_imm_index(ctx, EA, 0x0F);
2743 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2744 gen_addr_add(ctx, EA, EA, 8);
2745 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2746 tcg_temp_free(EA);
2747 #endif
2748 }
2749 #endif
2750
2751 /*** Integer store ***/
2752 #define GEN_ST(name, stop, opc, type) \
2753 static void glue(gen_, name)(DisasContext *ctx) \
2754 { \
2755 TCGv EA; \
2756 gen_set_access_type(ctx, ACCESS_INT); \
2757 EA = tcg_temp_new(); \
2758 gen_addr_imm_index(ctx, EA, 0); \
2759 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2760 tcg_temp_free(EA); \
2761 }
2762
2763 #define GEN_STU(name, stop, opc, type) \
2764 static void glue(gen_, stop##u)(DisasContext *ctx) \
2765 { \
2766 TCGv EA; \
2767 if (unlikely(rA(ctx->opcode) == 0)) { \
2768 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2769 return; \
2770 } \
2771 gen_set_access_type(ctx, ACCESS_INT); \
2772 EA = tcg_temp_new(); \
2773 if (type == PPC_64B) \
2774 gen_addr_imm_index(ctx, EA, 0x03); \
2775 else \
2776 gen_addr_imm_index(ctx, EA, 0); \
2777 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2778 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2779 tcg_temp_free(EA); \
2780 }
2781
2782 #define GEN_STUX(name, stop, opc2, opc3, type) \
2783 static void glue(gen_, name##ux)(DisasContext *ctx) \
2784 { \
2785 TCGv EA; \
2786 if (unlikely(rA(ctx->opcode) == 0)) { \
2787 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2788 return; \
2789 } \
2790 gen_set_access_type(ctx, ACCESS_INT); \
2791 EA = tcg_temp_new(); \
2792 gen_addr_reg_index(ctx, EA); \
2793 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2794 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2795 tcg_temp_free(EA); \
2796 }
2797
2798 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2799 static void glue(gen_, name##x)(DisasContext *ctx) \
2800 { \
2801 TCGv EA; \
2802 gen_set_access_type(ctx, ACCESS_INT); \
2803 EA = tcg_temp_new(); \
2804 gen_addr_reg_index(ctx, EA); \
2805 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2806 tcg_temp_free(EA); \
2807 }
2808 #define GEN_STX(name, stop, opc2, opc3, type) \
2809 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2810
2811 #define GEN_STS(name, stop, op, type) \
2812 GEN_ST(name, stop, op | 0x20, type); \
2813 GEN_STU(name, stop, op | 0x21, type); \
2814 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2815 GEN_STX(name, stop, 0x17, op | 0x00, type)
2816
2817 /* stb stbu stbux stbx */
2818 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2819 /* sth sthu sthux sthx */
2820 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2821 /* stw stwu stwux stwx */
2822 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2823 #if defined(TARGET_PPC64)
2824 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2825 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2826
2827 static void gen_std(DisasContext *ctx)
2828 {
2829 int rs;
2830 TCGv EA;
2831
2832 rs = rS(ctx->opcode);
2833 if ((ctx->opcode & 0x3) == 0x2) {
2834 #if defined(CONFIG_USER_ONLY)
2835 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2836 #else
2837 /* stq */
2838 if (unlikely(ctx->mem_idx == 0)) {
2839 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2840 return;
2841 }
2842 if (unlikely(rs & 1)) {
2843 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2844 return;
2845 }
2846 if (unlikely(ctx->le_mode)) {
2847 /* Little-endian mode is not handled */
2848 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2849 return;
2850 }
2851 gen_set_access_type(ctx, ACCESS_INT);
2852 EA = tcg_temp_new();
2853 gen_addr_imm_index(ctx, EA, 0x03);
2854 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2855 gen_addr_add(ctx, EA, EA, 8);
2856 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2857 tcg_temp_free(EA);
2858 #endif
2859 } else {
2860 /* std / stdu */
2861 if (Rc(ctx->opcode)) {
2862 if (unlikely(rA(ctx->opcode) == 0)) {
2863 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2864 return;
2865 }
2866 }
2867 gen_set_access_type(ctx, ACCESS_INT);
2868 EA = tcg_temp_new();
2869 gen_addr_imm_index(ctx, EA, 0x03);
2870 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2871 if (Rc(ctx->opcode))
2872 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2873 tcg_temp_free(EA);
2874 }
2875 }
2876 #endif
2877 /*** Integer load and store with byte reverse ***/
2878 /* lhbrx */
2879 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2880 {
2881 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2882 if (likely(!ctx->le_mode)) {
2883 tcg_gen_bswap16_tl(arg1, arg1);
2884 }
2885 }
2886 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2887
2888 /* lwbrx */
2889 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2890 {
2891 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2892 if (likely(!ctx->le_mode)) {
2893 tcg_gen_bswap32_tl(arg1, arg1);
2894 }
2895 }
2896 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2897
2898 #if defined(TARGET_PPC64)
2899 /* ldbrx */
2900 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2901 {
2902 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2903 if (likely(!ctx->le_mode)) {
2904 tcg_gen_bswap64_tl(arg1, arg1);
2905 }
2906 }
2907 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2908 #endif /* TARGET_PPC64 */
2909
2910 /* sthbrx */
2911 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2912 {
2913 if (likely(!ctx->le_mode)) {
2914 TCGv t0 = tcg_temp_new();
2915 tcg_gen_ext16u_tl(t0, arg1);
2916 tcg_gen_bswap16_tl(t0, t0);
2917 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2918 tcg_temp_free(t0);
2919 } else {
2920 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2921 }
2922 }
2923 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2924
2925 /* stwbrx */
2926 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2927 {
2928 if (likely(!ctx->le_mode)) {
2929 TCGv t0 = tcg_temp_new();
2930 tcg_gen_ext32u_tl(t0, arg1);
2931 tcg_gen_bswap32_tl(t0, t0);
2932 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2933 tcg_temp_free(t0);
2934 } else {
2935 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2936 }
2937 }
2938 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2939
2940 #if defined(TARGET_PPC64)
2941 /* stdbrx */
2942 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2943 {
2944 if (likely(!ctx->le_mode)) {
2945 TCGv t0 = tcg_temp_new();
2946 tcg_gen_bswap64_tl(t0, arg1);
2947 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2948 tcg_temp_free(t0);
2949 } else {
2950 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2951 }
2952 }
2953 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2954 #endif /* TARGET_PPC64 */
2955
2956 /*** Integer load and store multiple ***/
2957
2958 /* lmw */
2959 static void gen_lmw(DisasContext *ctx)
2960 {
2961 TCGv t0;
2962 TCGv_i32 t1;
2963 gen_set_access_type(ctx, ACCESS_INT);
2964 /* NIP cannot be restored if the memory exception comes from an helper */
2965 gen_update_nip(ctx, ctx->nip - 4);
2966 t0 = tcg_temp_new();
2967 t1 = tcg_const_i32(rD(ctx->opcode));
2968 gen_addr_imm_index(ctx, t0, 0);
2969 gen_helper_lmw(t0, t1);
2970 tcg_temp_free(t0);
2971 tcg_temp_free_i32(t1);
2972 }
2973
2974 /* stmw */
2975 static void gen_stmw(DisasContext *ctx)
2976 {
2977 TCGv t0;
2978 TCGv_i32 t1;
2979 gen_set_access_type(ctx, ACCESS_INT);
2980 /* NIP cannot be restored if the memory exception comes from an helper */
2981 gen_update_nip(ctx, ctx->nip - 4);
2982 t0 = tcg_temp_new();
2983 t1 = tcg_const_i32(rS(ctx->opcode));
2984 gen_addr_imm_index(ctx, t0, 0);
2985 gen_helper_stmw(t0, t1);
2986 tcg_temp_free(t0);
2987 tcg_temp_free_i32(t1);
2988 }
2989
2990 /*** Integer load and store strings ***/
2991
2992 /* lswi */
2993 /* PowerPC32 specification says we must generate an exception if
2994 * rA is in the range of registers to be loaded.
2995 * In an other hand, IBM says this is valid, but rA won't be loaded.
2996 * For now, I'll follow the spec...
2997 */
2998 static void gen_lswi(DisasContext *ctx)
2999 {
3000 TCGv t0;
3001 TCGv_i32 t1, t2;
3002 int nb = NB(ctx->opcode);
3003 int start = rD(ctx->opcode);
3004 int ra = rA(ctx->opcode);
3005 int nr;
3006
3007 if (nb == 0)
3008 nb = 32;
3009 nr = nb / 4;
3010 if (unlikely(((start + nr) > 32 &&
3011 start <= ra && (start + nr - 32) > ra) ||
3012 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3013 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3014 return;
3015 }
3016 gen_set_access_type(ctx, ACCESS_INT);
3017 /* NIP cannot be restored if the memory exception comes from an helper */
3018 gen_update_nip(ctx, ctx->nip - 4);
3019 t0 = tcg_temp_new();
3020 gen_addr_register(ctx, t0);
3021 t1 = tcg_const_i32(nb);
3022 t2 = tcg_const_i32(start);
3023 gen_helper_lsw(t0, t1, t2);
3024 tcg_temp_free(t0);
3025 tcg_temp_free_i32(t1);
3026 tcg_temp_free_i32(t2);
3027 }
3028
3029 /* lswx */
3030 static void gen_lswx(DisasContext *ctx)
3031 {
3032 TCGv t0;
3033 TCGv_i32 t1, t2, t3;
3034 gen_set_access_type(ctx, ACCESS_INT);
3035 /* NIP cannot be restored if the memory exception comes from an helper */
3036 gen_update_nip(ctx, ctx->nip - 4);
3037 t0 = tcg_temp_new();
3038 gen_addr_reg_index(ctx, t0);
3039 t1 = tcg_const_i32(rD(ctx->opcode));
3040 t2 = tcg_const_i32(rA(ctx->opcode));
3041 t3 = tcg_const_i32(rB(ctx->opcode));
3042 gen_helper_lswx(t0, t1, t2, t3);
3043 tcg_temp_free(t0);
3044 tcg_temp_free_i32(t1);
3045 tcg_temp_free_i32(t2);
3046 tcg_temp_free_i32(t3);
3047 }
3048
3049 /* stswi */
3050 static void gen_stswi(DisasContext *ctx)
3051 {
3052 TCGv t0;
3053 TCGv_i32 t1, t2;
3054 int nb = NB(ctx->opcode);
3055 gen_set_access_type(ctx, ACCESS_INT);
3056 /* NIP cannot be restored if the memory exception comes from an helper */
3057 gen_update_nip(ctx, ctx->nip - 4);
3058 t0 = tcg_temp_new();
3059 gen_addr_register(ctx, t0);
3060 if (nb == 0)
3061 nb = 32;
3062 t1 = tcg_const_i32(nb);
3063 t2 = tcg_const_i32(rS(ctx->opcode));
3064 gen_helper_stsw(t0, t1, t2);
3065 tcg_temp_free(t0);
3066 tcg_temp_free_i32(t1);
3067 tcg_temp_free_i32(t2);
3068 }
3069
3070 /* stswx */
3071 static void gen_stswx(DisasContext *ctx)
3072 {
3073 TCGv t0;
3074 TCGv_i32 t1, t2;
3075 gen_set_access_type(ctx, ACCESS_INT);
3076 /* NIP cannot be restored if the memory exception comes from an helper */
3077 gen_update_nip(ctx, ctx->nip - 4);
3078 t0 = tcg_temp_new();
3079 gen_addr_reg_index(ctx, t0);
3080 t1 = tcg_temp_new_i32();
3081 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3082 tcg_gen_andi_i32(t1, t1, 0x7F);
3083 t2 = tcg_const_i32(rS(ctx->opcode));
3084 gen_helper_stsw(t0, t1, t2);
3085 tcg_temp_free(t0);
3086 tcg_temp_free_i32(t1);
3087 tcg_temp_free_i32(t2);
3088 }
3089
3090 /*** Memory synchronisation ***/
3091 /* eieio */
3092 static void gen_eieio(DisasContext *ctx)
3093 {
3094 }
3095
3096 /* isync */
3097 static void gen_isync(DisasContext *ctx)
3098 {
3099 gen_stop_exception(ctx);
3100 }
3101
3102 /* lwarx */
3103 static void gen_lwarx(DisasContext *ctx)
3104 {
3105 TCGv t0;
3106 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3107 gen_set_access_type(ctx, ACCESS_RES);
3108 t0 = tcg_temp_local_new();
3109 gen_addr_reg_index(ctx, t0);
3110 gen_check_align(ctx, t0, 0x03);
3111 gen_qemu_ld32u(ctx, gpr, t0);
3112 tcg_gen_mov_tl(cpu_reserve, t0);
3113 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3114 tcg_temp_free(t0);
3115 }
3116
3117 #if defined(CONFIG_USER_ONLY)
3118 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3119 int reg, int size)
3120 {
3121 TCGv t0 = tcg_temp_new();
3122 uint32_t save_exception = ctx->exception;
3123
3124 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3125 tcg_gen_movi_tl(t0, (size << 5) | reg);
3126 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3127 tcg_temp_free(t0);
3128 gen_update_nip(ctx, ctx->nip-4);
3129 ctx->exception = POWERPC_EXCP_BRANCH;
3130 gen_exception(ctx, POWERPC_EXCP_STCX);
3131 ctx->exception = save_exception;
3132 }
3133 #endif
3134
3135 /* stwcx. */
3136 static void gen_stwcx_(DisasContext *ctx)
3137 {
3138 TCGv t0;
3139 gen_set_access_type(ctx, ACCESS_RES);
3140 t0 = tcg_temp_local_new();
3141 gen_addr_reg_index(ctx, t0);
3142 gen_check_align(ctx, t0, 0x03);
3143 #if defined(CONFIG_USER_ONLY)
3144 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3145 #else
3146 {
3147 int l1;
3148
3149 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3150 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3151 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3152 l1 = gen_new_label();
3153 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3154 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3155 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3156 gen_set_label(l1);
3157 tcg_gen_movi_tl(cpu_reserve, -1);
3158 }
3159 #endif
3160 tcg_temp_free(t0);
3161 }
3162
3163 #if defined(TARGET_PPC64)
3164 /* ldarx */
3165 static void gen_ldarx(DisasContext *ctx)
3166 {
3167 TCGv t0;
3168 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3169 gen_set_access_type(ctx, ACCESS_RES);
3170 t0 = tcg_temp_local_new();
3171 gen_addr_reg_index(ctx, t0);
3172 gen_check_align(ctx, t0, 0x07);
3173 gen_qemu_ld64(ctx, gpr, t0);
3174 tcg_gen_mov_tl(cpu_reserve, t0);
3175 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3176 tcg_temp_free(t0);
3177 }
3178
3179 /* stdcx. */
3180 static void gen_stdcx_(DisasContext *ctx)
3181 {
3182 TCGv t0;
3183 gen_set_access_type(ctx, ACCESS_RES);
3184 t0 = tcg_temp_local_new();
3185 gen_addr_reg_index(ctx, t0);
3186 gen_check_align(ctx, t0, 0x07);
3187 #if defined(CONFIG_USER_ONLY)
3188 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3189 #else
3190 {
3191 int l1;
3192 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3193 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3194 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3195 l1 = gen_new_label();
3196 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3197 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3198 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3199 gen_set_label(l1);
3200 tcg_gen_movi_tl(cpu_reserve, -1);
3201 }
3202 #endif
3203 tcg_temp_free(t0);
3204 }
3205 #endif /* defined(TARGET_PPC64) */
3206
3207 /* sync */
3208 static void gen_sync(DisasContext *ctx)
3209 {
3210 }
3211
3212 /* wait */
3213 static void gen_wait(DisasContext *ctx)
3214 {
3215 TCGv_i32 t0 = tcg_temp_new_i32();
3216 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, halted));
3217 tcg_temp_free_i32(t0);
3218 /* Stop translation, as the CPU is supposed to sleep from now */
3219 gen_exception_err(ctx, EXCP_HLT, 1);
3220 }
3221
3222 /*** Floating-point load ***/
3223 #define GEN_LDF(name, ldop, opc, type) \
3224 static void glue(gen_, name)(DisasContext *ctx) \
3225 { \
3226 TCGv EA; \
3227 if (unlikely(!ctx->fpu_enabled)) { \
3228 gen_exception(ctx, POWERPC_EXCP_FPU); \
3229 return; \
3230 } \
3231 gen_set_access_type(ctx, ACCESS_FLOAT); \
3232 EA = tcg_temp_new(); \
3233 gen_addr_imm_index(ctx, EA, 0); \
3234 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3235 tcg_temp_free(EA); \
3236 }
3237
3238 #define GEN_LDUF(name, ldop, opc, type) \
3239 static void glue(gen_, name##u)(DisasContext *ctx) \
3240 { \
3241 TCGv EA; \
3242 if (unlikely(!ctx->fpu_enabled)) { \
3243 gen_exception(ctx, POWERPC_EXCP_FPU); \
3244 return; \
3245 } \
3246 if (unlikely(rA(ctx->opcode) == 0)) { \
3247 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3248 return; \
3249 } \
3250 gen_set_access_type(ctx, ACCESS_FLOAT); \
3251 EA = tcg_temp_new(); \
3252 gen_addr_imm_index(ctx, EA, 0); \
3253 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3254 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3255 tcg_temp_free(EA); \
3256 }
3257
3258 #define GEN_LDUXF(name, ldop, opc, type) \
3259 static void glue(gen_, name##ux)(DisasContext *ctx) \
3260 { \
3261 TCGv EA; \
3262 if (unlikely(!ctx->fpu_enabled)) { \
3263 gen_exception(ctx, POWERPC_EXCP_FPU); \
3264 return; \
3265 } \
3266 if (unlikely(rA(ctx->opcode) == 0)) { \
3267 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3268 return; \
3269 } \
3270 gen_set_access_type(ctx, ACCESS_FLOAT); \
3271 EA = tcg_temp_new(); \
3272 gen_addr_reg_index(ctx, EA); \
3273 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3274 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3275 tcg_temp_free(EA); \
3276 }
3277
3278 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3279 static void glue(gen_, name##x)(DisasContext *ctx) \
3280 { \
3281 TCGv EA; \
3282 if (unlikely(!ctx->fpu_enabled)) { \
3283 gen_exception(ctx, POWERPC_EXCP_FPU); \
3284 return; \
3285 } \
3286 gen_set_access_type(ctx, ACCESS_FLOAT); \
3287 EA = tcg_temp_new(); \
3288 gen_addr_reg_index(ctx, EA); \
3289 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3290 tcg_temp_free(EA); \
3291 }
3292
3293 #define GEN_LDFS(name, ldop, op, type) \
3294 GEN_LDF(name, ldop, op | 0x20, type); \
3295 GEN_LDUF(name, ldop, op | 0x21, type); \
3296 GEN_LDUXF(name, ldop, op | 0x01, type); \
3297 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3298
3299 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3300 {
3301 TCGv t0 = tcg_temp_new();
3302 TCGv_i32 t1 = tcg_temp_new_i32();
3303 gen_qemu_ld32u(ctx, t0, arg2);
3304 tcg_gen_trunc_tl_i32(t1, t0);
3305 tcg_temp_free(t0);
3306 gen_helper_float32_to_float64(arg1, t1);
3307 tcg_temp_free_i32(t1);
3308 }
3309
3310 /* lfd lfdu lfdux lfdx */
3311 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3312 /* lfs lfsu lfsux lfsx */
3313 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3314
3315 /*** Floating-point store ***/
3316 #define GEN_STF(name, stop, opc, type) \
3317 static void glue(gen_, name)(DisasContext *ctx) \
3318 { \
3319 TCGv EA; \
3320 if (unlikely(!ctx->fpu_enabled)) { \
3321 gen_exception(ctx, POWERPC_EXCP_FPU); \
3322 return; \
3323 } \
3324 gen_set_access_type(ctx, ACCESS_FLOAT); \
3325 EA = tcg_temp_new(); \
3326 gen_addr_imm_index(ctx, EA, 0); \
3327 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3328 tcg_temp_free(EA); \
3329 }
3330
3331 #define GEN_STUF(name, stop, opc, type) \
3332 static void glue(gen_, name##u)(DisasContext *ctx) \
3333 { \
3334 TCGv EA; \
3335 if (unlikely(!ctx->fpu_enabled)) { \
3336 gen_exception(ctx, POWERPC_EXCP_FPU); \
3337 return; \
3338 } \
3339 if (unlikely(rA(ctx->opcode) == 0)) { \
3340 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3341 return; \
3342 } \
3343 gen_set_access_type(ctx, ACCESS_FLOAT); \
3344 EA = tcg_temp_new(); \
3345 gen_addr_imm_index(ctx, EA, 0); \
3346 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3347 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3348 tcg_temp_free(EA); \
3349 }
3350
3351 #define GEN_STUXF(name, stop, opc, type) \
3352 static void glue(gen_, name##ux)(DisasContext *ctx) \
3353 { \
3354 TCGv EA; \
3355 if (unlikely(!ctx->fpu_enabled)) { \
3356 gen_exception(ctx, POWERPC_EXCP_FPU); \
3357 return; \
3358 } \
3359 if (unlikely(rA(ctx->opcode) == 0)) { \
3360 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3361 return; \
3362 } \
3363 gen_set_access_type(ctx, ACCESS_FLOAT); \
3364 EA = tcg_temp_new(); \
3365 gen_addr_reg_index(ctx, EA); \
3366 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3367 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3368 tcg_temp_free(EA); \
3369 }
3370
3371 #define GEN_STXF(name, stop, opc2, opc3, type) \
3372 static void glue(gen_, name##x)(DisasContext *ctx) \
3373 { \
3374 TCGv EA; \
3375 if (unlikely(!ctx->fpu_enabled)) { \
3376 gen_exception(ctx, POWERPC_EXCP_FPU); \
3377 return; \
3378 } \
3379 gen_set_access_type(ctx, ACCESS_FLOAT); \
3380 EA = tcg_temp_new(); \
3381 gen_addr_reg_index(ctx, EA); \
3382 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3383 tcg_temp_free(EA); \
3384 }
3385
3386 #define GEN_STFS(name, stop, op, type) \
3387 GEN_STF(name, stop, op | 0x20, type); \
3388 GEN_STUF(name, stop, op | 0x21, type); \
3389 GEN_STUXF(name, stop, op | 0x01, type); \
3390 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3391
3392 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3393 {
3394 TCGv_i32 t0 = tcg_temp_new_i32();
3395 TCGv t1 = tcg_temp_new();
3396 gen_helper_float64_to_float32(t0, arg1);
3397 tcg_gen_extu_i32_tl(t1, t0);
3398 tcg_temp_free_i32(t0);
3399 gen_qemu_st32(ctx, t1, arg2);
3400 tcg_temp_free(t1);
3401 }
3402
3403 /* stfd stfdu stfdux stfdx */
3404 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3405 /* stfs stfsu stfsux stfsx */
3406 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3407
3408 /* Optional: */
3409 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3410 {
3411 TCGv t0 = tcg_temp_new();
3412 tcg_gen_trunc_i64_tl(t0, arg1),
3413 gen_qemu_st32(ctx, t0, arg2);
3414 tcg_temp_free(t0);
3415 }
3416 /* stfiwx */
3417 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3418
3419 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3420 {
3421 #if defined(TARGET_PPC64)
3422 if (ctx->has_cfar)
3423 tcg_gen_movi_tl(cpu_cfar, nip);
3424 #endif
3425 }
3426
3427 /*** Branch ***/
3428 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3429 {
3430 TranslationBlock *tb;
3431 tb = ctx->tb;
3432 #if defined(TARGET_PPC64)
3433 if (!ctx->sf_mode)
3434 dest = (uint32_t) dest;
3435 #endif
3436 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3437 likely(!ctx->singlestep_enabled)) {
3438 tcg_gen_goto_tb(n);
3439 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3440 tcg_gen_exit_tb((tcg_target_long)tb + n);
3441 } else {
3442 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3443 if (unlikely(ctx->singlestep_enabled)) {
3444 if ((ctx->singlestep_enabled &
3445 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3446 ctx->exception == POWERPC_EXCP_BRANCH) {
3447 target_ulong tmp = ctx->nip;
3448 ctx->nip = dest;
3449 gen_exception(ctx, POWERPC_EXCP_TRACE);
3450 ctx->nip = tmp;
3451 }
3452 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3453 gen_debug_exception(ctx);
3454 }
3455 }
3456 tcg_gen_exit_tb(0);
3457 }
3458 }
3459
3460 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3461 {
3462 #if defined(TARGET_PPC64)
3463 if (ctx->sf_mode == 0)
3464 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3465 else
3466 #endif
3467 tcg_gen_movi_tl(cpu_lr, nip);
3468 }
3469
3470 /* b ba bl bla */
3471 static void gen_b(DisasContext *ctx)
3472 {
3473 target_ulong li, target;
3474
3475 ctx->exception = POWERPC_EXCP_BRANCH;
3476 /* sign extend LI */
3477 #if defined(TARGET_PPC64)
3478 if (ctx->sf_mode)
3479 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3480 else
3481 #endif
3482 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3483 if (likely(AA(ctx->opcode) == 0))
3484 target = ctx->nip + li - 4;
3485 else
3486 target = li;
3487 if (LK(ctx->opcode))
3488 gen_setlr(ctx, ctx->nip);
3489 gen_update_cfar(ctx, ctx->nip);
3490 gen_goto_tb(ctx, 0, target);
3491 }
3492
3493 #define BCOND_IM 0
3494 #define BCOND_LR 1
3495 #define BCOND_CTR 2
3496
3497 static inline void gen_bcond(DisasContext *ctx, int type)
3498 {
3499 uint32_t bo = BO(ctx->opcode);
3500 int l1;
3501 TCGv target;
3502
3503 ctx->exception = POWERPC_EXCP_BRANCH;
3504 if (type == BCOND_LR || type == BCOND_CTR) {
3505 target = tcg_temp_local_new();
3506 if (type == BCOND_CTR)
3507 tcg_gen_mov_tl(target, cpu_ctr);
3508 else
3509 tcg_gen_mov_tl(target, cpu_lr);
3510 } else {
3511 TCGV_UNUSED(target);
3512 }
3513 if (LK(ctx->opcode))
3514 gen_setlr(ctx, ctx->nip);
3515 l1 = gen_new_label();
3516 if ((bo & 0x4) == 0) {
3517 /* Decrement and test CTR */
3518 TCGv temp = tcg_temp_new();
3519 if (unlikely(type == BCOND_CTR)) {
3520 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3521 return;
3522 }
3523 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3524 #if defined(TARGET_PPC64)
3525 if (!ctx->sf_mode)
3526 tcg_gen_ext32u_tl(temp, cpu_ctr);
3527 else
3528 #endif
3529 tcg_gen_mov_tl(temp, cpu_ctr);
3530 if (bo & 0x2) {
3531 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3532 } else {
3533 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3534 }
3535 tcg_temp_free(temp);
3536 }
3537 if ((bo & 0x10) == 0) {
3538 /* Test CR */
3539 uint32_t bi = BI(ctx->opcode);
3540 uint32_t mask = 1 << (3 - (bi & 0x03));
3541 TCGv_i32 temp = tcg_temp_new_i32();
3542
3543 if (bo & 0x8) {
3544 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3545 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3546 } else {
3547 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3548 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3549 }
3550 tcg_temp_free_i32(temp);
3551 }
3552 gen_update_cfar(ctx, ctx->nip);
3553 if (type == BCOND_IM) {
3554 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3555 if (likely(AA(ctx->opcode) == 0)) {
3556 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3557 } else {
3558 gen_goto_tb(ctx, 0, li);
3559 }
3560 gen_set_label(l1);
3561 gen_goto_tb(ctx, 1, ctx->nip);
3562 } else {
3563 #if defined(TARGET_PPC64)
3564 if (!(ctx->sf_mode))
3565 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3566 else
3567 #endif
3568 tcg_gen_andi_tl(cpu_nip, target, ~3);
3569 tcg_gen_exit_tb(0);
3570 gen_set_label(l1);
3571 #if defined(TARGET_PPC64)
3572 if (!(ctx->sf_mode))
3573 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3574 else
3575 #endif
3576 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3577 tcg_gen_exit_tb(0);
3578 }
3579 }
3580
3581 static void gen_bc(DisasContext *ctx)
3582 {
3583 gen_bcond(ctx, BCOND_IM);
3584 }
3585
3586 static void gen_bcctr(DisasContext *ctx)
3587 {
3588 gen_bcond(ctx, BCOND_CTR);
3589 }
3590
3591 static void gen_bclr(DisasContext *ctx)
3592 {
3593 gen_bcond(ctx, BCOND_LR);
3594 }
3595
3596 /*** Condition register logical ***/
3597 #define GEN_CRLOGIC(name, tcg_op, opc) \
3598 static void glue(gen_, name)(DisasContext *ctx) \
3599 { \
3600 uint8_t bitmask; \
3601 int sh; \
3602 TCGv_i32 t0, t1; \
3603 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3604 t0 = tcg_temp_new_i32(); \
3605 if (sh > 0) \
3606 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3607 else if (sh < 0) \
3608 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3609 else \
3610 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3611 t1 = tcg_temp_new_i32(); \
3612 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3613 if (sh > 0) \
3614 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3615 else if (sh < 0) \
3616 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3617 else \
3618 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3619 tcg_op(t0, t0, t1); \
3620 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3621 tcg_gen_andi_i32(t0, t0, bitmask); \
3622 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3623 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3624 tcg_temp_free_i32(t0); \
3625 tcg_temp_free_i32(t1); \
3626 }
3627
3628 /* crand */
3629 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3630 /* crandc */
3631 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3632 /* creqv */
3633 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3634 /* crnand */
3635 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3636 /* crnor */
3637 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3638 /* cror */
3639 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3640 /* crorc */
3641 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3642 /* crxor */
3643 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3644
3645 /* mcrf */
3646 static void gen_mcrf(DisasContext *ctx)
3647 {
3648 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3649 }
3650
3651 /*** System linkage ***/
3652
3653 /* rfi (mem_idx only) */
3654 static void gen_rfi(DisasContext *ctx)
3655 {
3656 #if defined(CONFIG_USER_ONLY)
3657 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3658 #else
3659 /* Restore CPU state */
3660 if (unlikely(!ctx->mem_idx)) {
3661 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3662 return;
3663 }
3664 gen_update_cfar(ctx, ctx->nip);
3665 gen_helper_rfi(cpu_env);
3666 gen_sync_exception(ctx);
3667 #endif
3668 }
3669
3670 #if defined(TARGET_PPC64)
3671 static void gen_rfid(DisasContext *ctx)
3672 {
3673 #if defined(CONFIG_USER_ONLY)
3674 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3675 #else
3676 /* Restore CPU state */
3677 if (unlikely(!ctx->mem_idx)) {
3678 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3679 return;
3680 }
3681 gen_update_cfar(ctx, ctx->nip);
3682 gen_helper_rfid(cpu_env);
3683 gen_sync_exception(ctx);
3684 #endif
3685 }
3686
3687 static void gen_hrfid(DisasContext *ctx)
3688 {
3689 #if defined(CONFIG_USER_ONLY)
3690 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3691 #else
3692 /* Restore CPU state */
3693 if (unlikely(ctx->mem_idx <= 1)) {
3694 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3695 return;
3696 }
3697 gen_helper_hrfid(cpu_env);
3698 gen_sync_exception(ctx);
3699 #endif
3700 }
3701 #endif
3702
3703 /* sc */
3704 #if defined(CONFIG_USER_ONLY)
3705 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3706 #else
3707 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3708 #endif
3709 static void gen_sc(DisasContext *ctx)
3710 {
3711 uint32_t lev;
3712
3713 lev = (ctx->opcode >> 5) & 0x7F;
3714 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3715 }
3716
3717 /*** Trap ***/
3718
3719 /* tw */
3720 static void gen_tw(DisasContext *ctx)
3721 {
3722 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3723 /* Update the nip since this might generate a trap exception */
3724 gen_update_nip(ctx, ctx->nip);
3725 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3726 t0);
3727 tcg_temp_free_i32(t0);
3728 }
3729
3730 /* twi */
3731 static void gen_twi(DisasContext *ctx)
3732 {
3733 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3734 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3735 /* Update the nip since this might generate a trap exception */
3736 gen_update_nip(ctx, ctx->nip);
3737 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3738 tcg_temp_free(t0);
3739 tcg_temp_free_i32(t1);
3740 }
3741
3742 #if defined(TARGET_PPC64)
3743 /* td */
3744 static void gen_td(DisasContext *ctx)
3745 {
3746 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3747 /* Update the nip since this might generate a trap exception */
3748 gen_update_nip(ctx, ctx->nip);
3749 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3750 t0);
3751 tcg_temp_free_i32(t0);
3752 }
3753
3754 /* tdi */
3755 static void gen_tdi(DisasContext *ctx)
3756 {
3757 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3758 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3759 /* Update the nip since this might generate a trap exception */
3760 gen_update_nip(ctx, ctx->nip);
3761 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3762 tcg_temp_free(t0);
3763 tcg_temp_free_i32(t1);
3764 }
3765 #endif
3766
3767 /*** Processor control ***/
3768
3769 /* mcrxr */
3770 static void gen_mcrxr(DisasContext *ctx)
3771 {
3772 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3773 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3774 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3775 }
3776
3777 /* mfcr mfocrf */
3778 static void gen_mfcr(DisasContext *ctx)
3779 {
3780 uint32_t crm, crn;
3781
3782 if (likely(ctx->opcode & 0x00100000)) {
3783 crm = CRM(ctx->opcode);
3784 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3785 crn = ctz32 (crm);
3786 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3787 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3788 cpu_gpr[rD(ctx->opcode)], crn * 4);
3789 }
3790 } else {
3791 TCGv_i32 t0 = tcg_temp_new_i32();
3792 tcg_gen_mov_i32(t0, cpu_crf[0]);
3793 tcg_gen_shli_i32(t0, t0, 4);
3794 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3795 tcg_gen_shli_i32(t0, t0, 4);
3796 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3797 tcg_gen_shli_i32(t0, t0, 4);
3798 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3799 tcg_gen_shli_i32(t0, t0, 4);
3800 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3801 tcg_gen_shli_i32(t0, t0, 4);
3802 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3803 tcg_gen_shli_i32(t0, t0, 4);
3804 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3805 tcg_gen_shli_i32(t0, t0, 4);
3806 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3807 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3808 tcg_temp_free_i32(t0);
3809 }
3810 }
3811
3812 /* mfmsr */
3813 static void gen_mfmsr(DisasContext *ctx)
3814 {
3815 #if defined(CONFIG_USER_ONLY)
3816 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3817 #else
3818 if (unlikely(!ctx->mem_idx)) {
3819 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3820 return;
3821 }
3822 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3823 #endif
3824 }
3825
3826 static void spr_noaccess(void *opaque, int gprn, int sprn)
3827 {
3828 #if 0
3829 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3830 printf("ERROR: try to access SPR %d !\n", sprn);
3831 #endif
3832 }
3833 #define SPR_NOACCESS (&spr_noaccess)
3834
3835 /* mfspr */
3836 static inline void gen_op_mfspr(DisasContext *ctx)
3837 {
3838 void (*read_cb)(void *opaque, int gprn, int sprn);
3839 uint32_t sprn = SPR(ctx->opcode);
3840
3841 #if !defined(CONFIG_USER_ONLY)
3842 if (ctx->mem_idx == 2)
3843 read_cb = ctx->spr_cb[sprn].hea_read;
3844 else if (ctx->mem_idx)
3845 read_cb = ctx->spr_cb[sprn].oea_read;
3846 else
3847 #endif
3848 read_cb = ctx->spr_cb[sprn].uea_read;
3849 if (likely(read_cb != NULL)) {
3850 if (likely(read_cb != SPR_NOACCESS)) {
3851 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3852 } else {
3853 /* Privilege exception */
3854 /* This is a hack to avoid warnings when running Linux:
3855 * this OS breaks the PowerPC virtualisation model,
3856 * allowing userland application to read the PVR
3857 */
3858 if (sprn != SPR_PVR) {
3859 qemu_log("Trying to read privileged spr %d %03x at "
3860 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3861 printf("Trying to read privileged spr %d %03x at "
3862 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3863 }
3864 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3865 }
3866 } else {
3867 /* Not defined */
3868 qemu_log("Trying to read invalid spr %d %03x at "
3869 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3870 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3871 sprn, sprn, ctx->nip);
3872 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3873 }
3874 }
3875
3876 static void gen_mfspr(DisasContext *ctx)
3877 {
3878 gen_op_mfspr(ctx);
3879 }
3880
3881 /* mftb */
3882 static void gen_mftb(DisasContext *ctx)
3883 {
3884 gen_op_mfspr(ctx);
3885 }
3886
3887 /* mtcrf mtocrf*/
3888 static void gen_mtcrf(DisasContext *ctx)
3889 {
3890 uint32_t crm, crn;
3891
3892 crm = CRM(ctx->opcode);
3893 if (likely((ctx->opcode & 0x00100000))) {
3894 if (crm && ((crm & (crm - 1)) == 0)) {
3895 TCGv_i32 temp = tcg_temp_new_i32();
3896 crn = ctz32 (crm);
3897 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3898 tcg_gen_shri_i32(temp, temp, crn * 4);
3899 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3900 tcg_temp_free_i32(temp);
3901 }
3902 } else {
3903 TCGv_i32 temp = tcg_temp_new_i32();
3904 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3905 for (crn = 0 ; crn < 8 ; crn++) {
3906 if (crm & (1 << crn)) {
3907 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3908 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3909 }
3910 }
3911 tcg_temp_free_i32(temp);
3912 }
3913 }
3914
3915 /* mtmsr */
3916 #if defined(TARGET_PPC64)
3917 static void gen_mtmsrd(DisasContext *ctx)
3918 {
3919 #if defined(CONFIG_USER_ONLY)
3920 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3921 #else
3922 if (unlikely(!ctx->mem_idx)) {
3923 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3924 return;
3925 }
3926 if (ctx->opcode & 0x00010000) {
3927 /* Special form that does not need any synchronisation */
3928 TCGv t0 = tcg_temp_new();
3929 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3930 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3931 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3932 tcg_temp_free(t0);
3933 } else {
3934 /* XXX: we need to update nip before the store
3935 * if we enter power saving mode, we will exit the loop
3936 * directly from ppc_store_msr
3937 */
3938 gen_update_nip(ctx, ctx->nip);
3939 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3940 /* Must stop the translation as machine state (may have) changed */
3941 /* Note that mtmsr is not always defined as context-synchronizing */
3942 gen_stop_exception(ctx);
3943 }
3944 #endif
3945 }
3946 #endif
3947
3948 static void gen_mtmsr(DisasContext *ctx)
3949 {
3950 #if defined(CONFIG_USER_ONLY)
3951 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3952 #else
3953 if (unlikely(!ctx->mem_idx)) {
3954 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3955 return;
3956 }
3957 if (ctx->opcode & 0x00010000) {
3958 /* Special form that does not need any synchronisation */
3959 TCGv t0 = tcg_temp_new();
3960 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3961 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3962 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3963 tcg_temp_free(t0);
3964 } else {
3965 TCGv msr = tcg_temp_new();
3966
3967 /* XXX: we need to update nip before the store
3968 * if we enter power saving mode, we will exit the loop
3969 * directly from ppc_store_msr
3970 */
3971 gen_update_nip(ctx, ctx->nip);
3972 #if defined(TARGET_PPC64)
3973 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3974 #else
3975 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3976 #endif
3977 gen_helper_store_msr(cpu_env, msr);
3978 /* Must stop the translation as machine state (may have) changed */
3979 /* Note that mtmsr is not always defined as context-synchronizing */
3980 gen_stop_exception(ctx);
3981 }
3982 #endif
3983 }
3984
3985 /* mtspr */
3986 static void gen_mtspr(DisasContext *ctx)
3987 {
3988 void (*write_cb)(void *opaque, int sprn, int gprn);
3989 uint32_t sprn = SPR(ctx->opcode);
3990
3991 #if !defined(CONFIG_USER_ONLY)
3992 if (ctx->mem_idx == 2)
3993 write_cb = ctx->spr_cb[sprn].hea_write;
3994 else if (ctx->mem_idx)
3995 write_cb = ctx->spr_cb[sprn].oea_write;
3996 else
3997 #endif
3998 write_cb = ctx->spr_cb[sprn].uea_write;
3999 if (likely(write_cb != NULL)) {
4000 if (likely(write_cb != SPR_NOACCESS)) {
4001 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4002 } else {
4003 /* Privilege exception */
4004 qemu_log("Trying to write privileged spr %d %03x at "
4005 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
4006 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
4007 "\n", sprn, sprn, ctx->nip);
4008 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4009 }
4010 } else {
4011 /* Not defined */
4012 qemu_log("Trying to write invalid spr %d %03x at "
4013 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
4014 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
4015 sprn, sprn, ctx->nip);
4016 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4017 }
4018 }
4019
4020 /*** Cache management ***/
4021
4022 /* dcbf */
4023 static void gen_dcbf(DisasContext *ctx)
4024 {
4025 /* XXX: specification says this is treated as a load by the MMU */
4026 TCGv t0;
4027 gen_set_access_type(ctx, ACCESS_CACHE);
4028 t0 = tcg_temp_new();
4029 gen_addr_reg_index(ctx, t0);
4030 gen_qemu_ld8u(ctx, t0, t0);
4031 tcg_temp_free(t0);
4032 }
4033
4034 /* dcbi (Supervisor only) */
4035 static void gen_dcbi(DisasContext *ctx)
4036 {
4037 #if defined(CONFIG_USER_ONLY)
4038 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4039 #else
4040 TCGv EA, val;
4041 if (unlikely(!ctx->mem_idx)) {
4042 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4043 return;
4044 }
4045 EA = tcg_temp_new();
4046 gen_set_access_type(ctx, ACCESS_CACHE);
4047 gen_addr_reg_index(ctx, EA);
4048 val = tcg_temp_new();
4049 /* XXX: specification says this should be treated as a store by the MMU */
4050 gen_qemu_ld8u(ctx, val, EA);
4051 gen_qemu_st8(ctx, val, EA);
4052 tcg_temp_free(val);
4053 tcg_temp_free(EA);
4054 #endif
4055 }
4056
4057 /* dcdst */
4058 static void gen_dcbst(DisasContext *ctx)
4059 {
4060 /* XXX: specification say this is treated as a load by the MMU */
4061 TCGv t0;
4062 gen_set_access_type(ctx, ACCESS_CACHE);
4063 t0 = tcg_temp_new();
4064 gen_addr_reg_index(ctx, t0);
4065 gen_qemu_ld8u(ctx, t0, t0);
4066 tcg_temp_free(t0);
4067 }
4068
4069 /* dcbt */
4070 static void gen_dcbt(DisasContext *ctx)
4071 {
4072 /* interpreted as no-op */
4073 /* XXX: specification say this is treated as a load by the MMU
4074 * but does not generate any exception
4075 */
4076 }
4077
4078 /* dcbtst */
4079 static void gen_dcbtst(DisasContext *ctx)
4080 {
4081 /* interpreted as no-op */
4082 /* XXX: specification say this is treated as a load by the MMU
4083 * but does not generate any exception
4084 */
4085 }
4086
4087 /* dcbz */
4088 static void gen_dcbz(DisasContext *ctx)
4089 {
4090 TCGv t0;
4091 gen_set_access_type(ctx, ACCESS_CACHE);
4092 /* NIP cannot be restored if the memory exception comes from an helper */
4093 gen_update_nip(ctx, ctx->nip - 4);
4094 t0 = tcg_temp_new();
4095 gen_addr_reg_index(ctx, t0);
4096 gen_helper_dcbz(t0);
4097 tcg_temp_free(t0);
4098 }
4099
4100 static void gen_dcbz_970(DisasContext *ctx)
4101 {
4102 TCGv t0;
4103 gen_set_access_type(ctx, ACCESS_CACHE);
4104 /* NIP cannot be restored if the memory exception comes from an helper */
4105 gen_update_nip(ctx, ctx->nip - 4);
4106 t0 = tcg_temp_new();
4107 gen_addr_reg_index(ctx, t0);
4108 if (ctx->opcode & 0x00200000)
4109 gen_helper_dcbz(t0);
4110 else
4111 gen_helper_dcbz_970(t0);
4112 tcg_temp_free(t0);
4113 }
4114
4115 /* dst / dstt */
4116 static void gen_dst(DisasContext *ctx)
4117 {
4118 if (rA(ctx->opcode) == 0) {
4119 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4120 } else {
4121 /* interpreted as no-op */
4122 }
4123 }
4124
4125 /* dstst /dststt */
4126 static void gen_dstst(DisasContext *ctx)
4127 {
4128 if (rA(ctx->opcode) == 0) {
4129 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4130 } else {
4131 /* interpreted as no-op */
4132 }
4133
4134 }
4135
4136 /* dss / dssall */
4137 static void gen_dss(DisasContext *ctx)
4138 {
4139 /* interpreted as no-op */
4140 }
4141
4142 /* icbi */
4143 static void gen_icbi(DisasContext *ctx)
4144 {
4145 TCGv t0;
4146 gen_set_access_type(ctx, ACCESS_CACHE);
4147 /* NIP cannot be restored if the memory exception comes from an helper */
4148 gen_update_nip(ctx, ctx->nip - 4);
4149 t0 = tcg_temp_new();
4150 gen_addr_reg_index(ctx, t0);
4151 gen_helper_icbi(t0);
4152 tcg_temp_free(t0);
4153 }
4154
4155 /* Optional: */
4156 /* dcba */
4157 static void gen_dcba(DisasContext *ctx)
4158 {
4159 /* interpreted as no-op */
4160 /* XXX: specification say this is treated as a store by the MMU
4161 * but does not generate any exception
4162 */
4163 }
4164
4165 /*** Segment register manipulation ***/
4166 /* Supervisor only: */
4167
4168 /* mfsr */
4169 static void gen_mfsr(DisasContext *ctx)
4170 {
4171 #if defined(CONFIG_USER_ONLY)
4172 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4173 #else
4174 TCGv t0;
4175 if (unlikely(!ctx->mem_idx)) {
4176 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4177 return;
4178 }
4179 t0 = tcg_const_tl(SR(ctx->opcode));
4180 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4181 tcg_temp_free(t0);
4182 #endif
4183 }
4184
4185 /* mfsrin */
4186 static void gen_mfsrin(DisasContext *ctx)
4187 {
4188 #if defined(CONFIG_USER_ONLY)
4189 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4190 #else
4191 TCGv t0;
4192 if (unlikely(!ctx->mem_idx)) {
4193 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4194 return;
4195 }
4196 t0 = tcg_temp_new();
4197 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4198 tcg_gen_andi_tl(t0, t0, 0xF);
4199 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4200 tcg_temp_free(t0);
4201 #endif
4202 }
4203
4204 /* mtsr */
4205 static void gen_mtsr(DisasContext *ctx)
4206 {
4207 #if defined(CONFIG_USER_ONLY)
4208 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4209 #else
4210 TCGv t0;
4211 if (unlikely(!ctx->mem_idx)) {
4212 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4213 return;
4214 }
4215 t0 = tcg_const_tl(SR(ctx->opcode));
4216 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4217 tcg_temp_free(t0);
4218 #endif
4219 }
4220
4221 /* mtsrin */
4222 static void gen_mtsrin(DisasContext *ctx)
4223 {
4224 #if defined(CONFIG_USER_ONLY)
4225 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4226 #else
4227 TCGv t0;
4228 if (unlikely(!ctx->mem_idx)) {
4229 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4230 return;
4231 }
4232 t0 = tcg_temp_new();
4233 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4234 tcg_gen_andi_tl(t0, t0, 0xF);
4235 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4236 tcg_temp_free(t0);
4237 #endif
4238 }
4239
4240 #if defined(TARGET_PPC64)
4241 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4242
4243 /* mfsr */
4244 static void gen_mfsr_64b(DisasContext *ctx)
4245 {
4246 #if defined(CONFIG_USER_ONLY)
4247 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4248 #else
4249 TCGv t0;
4250 if (unlikely(!ctx->mem_idx)) {
4251 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4252 return;
4253 }
4254 t0 = tcg_const_tl(SR(ctx->opcode));
4255 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4256 tcg_temp_free(t0);
4257 #endif
4258 }
4259
4260 /* mfsrin */
4261 static void gen_mfsrin_64b(DisasContext *ctx)
4262 {
4263 #if defined(CONFIG_USER_ONLY)
4264 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4265 #else
4266 TCGv t0;
4267 if (unlikely(!ctx->mem_idx)) {
4268 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4269 return;
4270 }
4271 t0 = tcg_temp_new();
4272 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4273 tcg_gen_andi_tl(t0, t0, 0xF);
4274 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4275 tcg_temp_free(t0);
4276 #endif
4277 }
4278
4279 /* mtsr */
4280 static void gen_mtsr_64b(DisasContext *ctx)
4281 {
4282 #if defined(CONFIG_USER_ONLY)
4283 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4284 #else
4285 TCGv t0;
4286 if (unlikely(!ctx->mem_idx)) {
4287 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4288 return;
4289 }
4290 t0 = tcg_const_tl(SR(ctx->opcode));
4291 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4292 tcg_temp_free(t0);
4293 #endif
4294 }
4295
4296 /* mtsrin */
4297 static void gen_mtsrin_64b(DisasContext *ctx)
4298 {
4299 #if defined(CONFIG_USER_ONLY)
4300 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4301 #else
4302 TCGv t0;
4303 if (unlikely(!ctx->mem_idx)) {
4304 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4305 return;
4306 }
4307 t0 = tcg_temp_new();
4308 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4309 tcg_gen_andi_tl(t0, t0, 0xF);
4310 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4311 tcg_temp_free(t0);
4312 #endif
4313 }
4314
4315 /* slbmte */
4316 static void gen_slbmte(DisasContext *ctx)
4317 {
4318 #if defined(CONFIG_USER_ONLY)
4319 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4320 #else
4321 if (unlikely(!ctx->mem_idx)) {
4322 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4323 return;
4324 }
4325 gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
4326 #endif
4327 }
4328
4329 static void gen_slbmfee(DisasContext *ctx)
4330 {
4331 #if defined(CONFIG_USER_ONLY)
4332 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4333 #else
4334 if (unlikely(!ctx->mem_idx)) {
4335 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4336 return;
4337 }
4338 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)],
4339 cpu_gpr[rB(ctx->opcode)]);
4340 #endif
4341 }
4342
4343 static void gen_slbmfev(DisasContext *ctx)
4344 {
4345 #if defined(CONFIG_USER_ONLY)
4346 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4347 #else
4348 if (unlikely(!ctx->mem_idx)) {
4349 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4350 return;
4351 }
4352 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)],
4353 cpu_gpr[rB(ctx->opcode)]);
4354 #endif
4355 }
4356 #endif /* defined(TARGET_PPC64) */
4357
4358 /*** Lookaside buffer management ***/
4359 /* Optional & mem_idx only: */
4360
4361 /* tlbia */
4362 static void gen_tlbia(DisasContext *ctx)
4363 {
4364 #if defined(CONFIG_USER_ONLY)
4365 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4366 #else
4367 if (unlikely(!ctx->mem_idx)) {
4368 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4369 return;
4370 }
4371 gen_helper_tlbia();
4372 #endif
4373 }
4374
4375 /* tlbiel */
4376 static void gen_tlbiel(DisasContext *ctx)
4377 {
4378 #if defined(CONFIG_USER_ONLY)
4379 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4380 #else
4381 if (unlikely(!ctx->mem_idx)) {
4382 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4383 return;
4384 }
4385 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4386 #endif
4387 }
4388
4389 /* tlbie */
4390 static void gen_tlbie(DisasContext *ctx)
4391 {
4392 #if defined(CONFIG_USER_ONLY)
4393 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4394 #else
4395 if (unlikely(!ctx->mem_idx)) {
4396 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4397 return;
4398 }
4399 #if defined(TARGET_PPC64)
4400 if (!ctx->sf_mode) {
4401 TCGv t0 = tcg_temp_new();
4402 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4403 gen_helper_tlbie(t0);
4404 tcg_temp_free(t0);
4405 } else
4406 #endif
4407 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4408 #endif
4409 }
4410
4411 /* tlbsync */
4412 static void gen_tlbsync(DisasContext *ctx)
4413 {
4414 #if defined(CONFIG_USER_ONLY)
4415 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4416 #else
4417 if (unlikely(!ctx->mem_idx)) {
4418 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4419 return;
4420 }
4421 /* This has no effect: it should ensure that all previous
4422 * tlbie have completed
4423 */
4424 gen_stop_exception(ctx);
4425 #endif
4426 }
4427
4428 #if defined(TARGET_PPC64)
4429 /* slbia */
4430 static void gen_slbia(DisasContext *ctx)
4431 {
4432 #if defined(CONFIG_USER_ONLY)
4433 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4434 #else
4435 if (unlikely(!ctx->mem_idx)) {
4436 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4437 return;
4438 }
4439 gen_helper_slbia();
4440 #endif
4441 }
4442
4443 /* slbie */
4444 static void gen_slbie(DisasContext *ctx)
4445 {
4446 #if defined(CONFIG_USER_ONLY)
4447 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4448 #else
4449 if (unlikely(!ctx->mem_idx)) {
4450 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4451 return;
4452 }
4453 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
4454 #endif
4455 }
4456 #endif
4457
4458 /*** External control ***/
4459 /* Optional: */
4460
4461 /* eciwx */
4462 static void gen_eciwx(DisasContext *ctx)
4463 {
4464 TCGv t0;
4465 /* Should check EAR[E] ! */
4466 gen_set_access_type(ctx, ACCESS_EXT);
4467 t0 = tcg_temp_new();
4468 gen_addr_reg_index(ctx, t0);
4469 gen_check_align(ctx, t0, 0x03);
4470 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4471 tcg_temp_free(t0);
4472 }
4473
4474 /* ecowx */
4475 static void gen_ecowx(DisasContext *ctx)
4476 {
4477 TCGv t0;
4478 /* Should check EAR[E] ! */
4479 gen_set_access_type(ctx, ACCESS_EXT);
4480 t0 = tcg_temp_new();
4481 gen_addr_reg_index(ctx, t0);
4482 gen_check_align(ctx, t0, 0x03);
4483 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4484 tcg_temp_free(t0);
4485 }
4486
4487 /* PowerPC 601 specific instructions */
4488
4489 /* abs - abs. */
4490 static void gen_abs(DisasContext *ctx)
4491 {
4492 int l1 = gen_new_label();
4493 int l2 = gen_new_label();
4494 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4495 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4496 tcg_gen_br(l2);
4497 gen_set_label(l1);
4498 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4499 gen_set_label(l2);
4500 if (unlikely(Rc(ctx->opcode) != 0))
4501 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4502 }
4503
4504 /* abso - abso. */
4505 static void gen_abso(DisasContext *ctx)
4506 {
4507 int l1 = gen_new_label();
4508 int l2 = gen_new_label();
4509 int l3 = gen_new_label();
4510 /* Start with XER OV disabled, the most likely case */
4511 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4512 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4513 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4514 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4515 tcg_gen_br(l2);
4516 gen_set_label(l1);
4517 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4518 tcg_gen_br(l3);
4519 gen_set_label(l2);
4520 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4521 gen_set_label(l3);
4522 if (unlikely(Rc(ctx->opcode) != 0))
4523 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4524 }
4525
4526 /* clcs */
4527 static void gen_clcs(DisasContext *ctx)
4528 {
4529 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4530 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4531 tcg_temp_free_i32(t0);
4532 /* Rc=1 sets CR0 to an undefined state */
4533 }
4534
4535 /* div - div. */
4536 static void gen_div(DisasContext *ctx)
4537 {
4538 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4539 if (unlikely(Rc(ctx->opcode) != 0))
4540 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4541 }
4542
4543 /* divo - divo. */
4544 static void gen_divo(DisasContext *ctx)
4545 {
4546 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4547 if (unlikely(Rc(ctx->opcode) != 0))
4548 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4549 }
4550
4551 /* divs - divs. */
4552 static void gen_divs(DisasContext *ctx)
4553 {
4554 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4555 if (unlikely(Rc(ctx->opcode) != 0))
4556 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4557 }
4558
4559 /* divso - divso. */
4560 static void gen_divso(DisasContext *ctx)
4561 {
4562 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4563 if (unlikely(Rc(ctx->opcode) != 0))
4564 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4565 }
4566
4567 /* doz - doz. */
4568 static void gen_doz(DisasContext *ctx)
4569 {
4570 int l1 = gen_new_label();
4571 int l2 = gen_new_label();
4572 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4573 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4574 tcg_gen_br(l2);
4575 gen_set_label(l1);
4576 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4577 gen_set_label(l2);
4578 if (unlikely(Rc(ctx->opcode) != 0))
4579 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4580 }
4581
4582 /* dozo - dozo. */
4583 static void gen_dozo(DisasContext *ctx)
4584 {
4585 int l1 = gen_new_label();
4586 int l2 = gen_new_label();
4587 TCGv t0 = tcg_temp_new();
4588 TCGv t1 = tcg_temp_new();
4589 TCGv t2 = tcg_temp_new();
4590 /* Start with XER OV disabled, the most likely case */
4591 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4592 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4593 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4594 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4595 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4596 tcg_gen_andc_tl(t1, t1, t2);
4597 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4598 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4599 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4600 tcg_gen_br(l2);
4601 gen_set_label(l1);
4602 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4603 gen_set_label(l2);
4604 tcg_temp_free(t0);
4605 tcg_temp_free(t1);
4606 tcg_temp_free(t2);
4607 if (unlikely(Rc(ctx->opcode) != 0))
4608 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4609 }
4610
4611 /* dozi */
4612 static void gen_dozi(DisasContext *ctx)
4613 {
4614 target_long simm = SIMM(ctx->opcode);
4615 int l1 = gen_new_label();
4616 int l2 = gen_new_label();
4617 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4618 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4619 tcg_gen_br(l2);
4620 gen_set_label(l1);
4621 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4622 gen_set_label(l2);
4623 if (unlikely(Rc(ctx->opcode) != 0))
4624 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4625 }
4626
4627 /* lscbx - lscbx. */
4628 static void gen_lscbx(DisasContext *ctx)
4629 {
4630 TCGv t0 = tcg_temp_new();
4631 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4632 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4633 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4634
4635 gen_addr_reg_index(ctx, t0);
4636 /* NIP cannot be restored if the memory exception comes from an helper */
4637 gen_update_nip(ctx, ctx->nip - 4);
4638 gen_helper_lscbx(t0, t0, t1, t2, t3);
4639 tcg_temp_free_i32(t1);
4640 tcg_temp_free_i32(t2);
4641 tcg_temp_free_i32(t3);
4642 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4643 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4644 if (unlikely(Rc(ctx->opcode) != 0))
4645 gen_set_Rc0(ctx, t0);
4646 tcg_temp_free(t0);
4647 }
4648
4649 /* maskg - maskg. */
4650 static void gen_maskg(DisasContext *ctx)
4651 {
4652 int l1 = gen_new_label();
4653 TCGv t0 = tcg_temp_new();
4654 TCGv t1 = tcg_temp_new();
4655 TCGv t2 = tcg_temp_new();
4656 TCGv t3 = tcg_temp_new();
4657 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4658 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4659 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4660 tcg_gen_addi_tl(t2, t0, 1);
4661 tcg_gen_shr_tl(t2, t3, t2);
4662 tcg_gen_shr_tl(t3, t3, t1);
4663 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4664 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4665 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4666 gen_set_label(l1);
4667 tcg_temp_free(t0);
4668 tcg_temp_free(t1);
4669 tcg_temp_free(t2);
4670 tcg_temp_free(t3);
4671 if (unlikely(Rc(ctx->opcode) != 0))
4672 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4673 }
4674
4675 /* maskir - maskir. */
4676 static void gen_maskir(DisasContext *ctx)
4677 {
4678 TCGv t0 = tcg_temp_new();
4679 TCGv t1 = tcg_temp_new();
4680 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4681 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4682 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4683 tcg_temp_free(t0);
4684 tcg_temp_free(t1);
4685 if (unlikely(Rc(ctx->opcode) != 0))
4686 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4687 }
4688
4689 /* mul - mul. */
4690 static void gen_mul(DisasContext *ctx)
4691 {
4692 TCGv_i64 t0 = tcg_temp_new_i64();
4693 TCGv_i64 t1 = tcg_temp_new_i64();
4694 TCGv t2 = tcg_temp_new();
4695 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4696 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4697 tcg_gen_mul_i64(t0, t0, t1);
4698 tcg_gen_trunc_i64_tl(t2, t0);
4699 gen_store_spr(SPR_MQ, t2);
4700 tcg_gen_shri_i64(t1, t0, 32);
4701 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4702 tcg_temp_free_i64(t0);
4703 tcg_temp_free_i64(t1);
4704 tcg_temp_free(t2);
4705 if (unlikely(Rc(ctx->opcode) != 0))
4706 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4707 }
4708
4709 /* mulo - mulo. */
4710 static void gen_mulo(DisasContext *ctx)
4711 {
4712 int l1 = gen_new_label();
4713 TCGv_i64 t0 = tcg_temp_new_i64();
4714 TCGv_i64 t1 = tcg_temp_new_i64();
4715 TCGv t2 = tcg_temp_new();
4716 /* Start with XER OV disabled, the most likely case */
4717 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4718 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4719 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4720 tcg_gen_mul_i64(t0, t0, t1);
4721 tcg_gen_trunc_i64_tl(t2, t0);
4722 gen_store_spr(SPR_MQ, t2);
4723 tcg_gen_shri_i64(t1, t0, 32);
4724 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4725 tcg_gen_ext32s_i64(t1, t0);
4726 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4727 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4728 gen_set_label(l1);
4729 tcg_temp_free_i64(t0);
4730 tcg_temp_free_i64(t1);
4731 tcg_temp_free(t2);
4732 if (unlikely(Rc(ctx->opcode) != 0))
4733 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4734 }
4735
4736 /* nabs - nabs. */
4737 static void gen_nabs(DisasContext *ctx)
4738 {
4739 int l1 = gen_new_label();
4740 int l2 = gen_new_label();
4741 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4742 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4743 tcg_gen_br(l2);
4744 gen_set_label(l1);
4745 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4746 gen_set_label(l2);
4747 if (unlikely(Rc(ctx->opcode) != 0))
4748 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4749 }
4750
4751 /* nabso - nabso. */
4752 static void gen_nabso(DisasContext *ctx)
4753 {
4754 int l1 = gen_new_label();
4755 int l2 = gen_new_label();
4756 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4757 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4758 tcg_gen_br(l2);
4759 gen_set_label(l1);
4760 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4761 gen_set_label(l2);
4762 /* nabs never overflows */
4763 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4764 if (unlikely(Rc(ctx->opcode) != 0))
4765 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4766 }
4767
4768 /* rlmi - rlmi. */
4769 static void gen_rlmi(DisasContext *ctx)
4770 {
4771 uint32_t mb = MB(ctx->opcode);
4772 uint32_t me = ME(ctx->opcode);
4773 TCGv t0 = tcg_temp_new();
4774 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4775 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4776 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4777 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4778 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4779 tcg_temp_free(t0);
4780 if (unlikely(Rc(ctx->opcode) != 0))
4781 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4782 }
4783
4784 /* rrib - rrib. */
4785 static void gen_rrib(DisasContext *ctx)
4786 {
4787 TCGv t0 = tcg_temp_new();
4788 TCGv t1 = tcg_temp_new();
4789 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4790 tcg_gen_movi_tl(t1, 0x80000000);
4791 tcg_gen_shr_tl(t1, t1, t0);
4792 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4793 tcg_gen_and_tl(t0, t0, t1);
4794 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4795 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4796 tcg_temp_free(t0);
4797 tcg_temp_free(t1);
4798 if (unlikely(Rc(ctx->opcode) != 0))
4799 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4800 }
4801
4802 /* sle - sle. */
4803 static void gen_sle(DisasContext *ctx)
4804 {
4805 TCGv t0 = tcg_temp_new();
4806 TCGv t1 = tcg_temp_new();
4807 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4808 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4809 tcg_gen_subfi_tl(t1, 32, t1);
4810 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4811 tcg_gen_or_tl(t1, t0, t1);
4812 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4813 gen_store_spr(SPR_MQ, t1);
4814 tcg_temp_free(t0);
4815 tcg_temp_free(t1);
4816 if (unlikely(Rc(ctx->opcode) != 0))
4817 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4818 }
4819
4820 /* sleq - sleq. */
4821 static void gen_sleq(DisasContext *ctx)
4822 {
4823 TCGv t0 = tcg_temp_new();
4824 TCGv t1 = tcg_temp_new();
4825 TCGv t2 = tcg_temp_new();
4826 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4827 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4828 tcg_gen_shl_tl(t2, t2, t0);
4829 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4830 gen_load_spr(t1, SPR_MQ);
4831 gen_store_spr(SPR_MQ, t0);
4832 tcg_gen_and_tl(t0, t0, t2);
4833 tcg_gen_andc_tl(t1, t1, t2);
4834 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4835 tcg_temp_free(t0);
4836 tcg_temp_free(t1);
4837 tcg_temp_free(t2);
4838 if (unlikely(Rc(ctx->opcode) != 0))
4839 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4840 }
4841
4842 /* sliq - sliq. */
4843 static void gen_sliq(DisasContext *ctx)
4844 {
4845 int sh = SH(ctx->opcode);
4846 TCGv t0 = tcg_temp_new();
4847 TCGv t1 = tcg_temp_new();
4848 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4849 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4850 tcg_gen_or_tl(t1, t0, t1);
4851 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4852 gen_store_spr(SPR_MQ, t1);
4853 tcg_temp_free(t0);
4854 tcg_temp_free(t1);
4855 if (unlikely(Rc(ctx->opcode) != 0))
4856 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4857 }
4858
4859 /* slliq - slliq. */
4860 static void gen_slliq(DisasContext *ctx)
4861 {
4862 int sh = SH(ctx->opcode);
4863 TCGv t0 = tcg_temp_new();
4864 TCGv t1 = tcg_temp_new();
4865 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4866 gen_load_spr(t1, SPR_MQ);
4867 gen_store_spr(SPR_MQ, t0);
4868 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4869 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4870 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4871 tcg_temp_free(t0);
4872 tcg_temp_free(t1);
4873 if (unlikely(Rc(ctx->opcode) != 0))
4874 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4875 }
4876
4877 /* sllq - sllq. */
4878 static void gen_sllq(DisasContext *ctx)
4879 {
4880 int l1 = gen_new_label();
4881 int l2 = gen_new_label();
4882 TCGv t0 = tcg_temp_local_new();
4883 TCGv t1 = tcg_temp_local_new();
4884 TCGv t2 = tcg_temp_local_new();
4885 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4886 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4887 tcg_gen_shl_tl(t1, t1, t2);
4888 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4889 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4890 gen_load_spr(t0, SPR_MQ);
4891 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4892 tcg_gen_br(l2);
4893 gen_set_label(l1);
4894 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4895 gen_load_spr(t2, SPR_MQ);
4896 tcg_gen_andc_tl(t1, t2, t1);
4897 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4898 gen_set_label(l2);
4899 tcg_temp_free(t0);
4900 tcg_temp_free(t1);
4901 tcg_temp_free(t2);
4902 if (unlikely(Rc(ctx->opcode) != 0))
4903 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4904 }
4905
4906 /* slq - slq. */
4907 static void gen_slq(DisasContext *ctx)
4908 {
4909 int l1 = gen_new_label();
4910 TCGv t0 = tcg_temp_new();
4911 TCGv t1 = tcg_temp_new();
4912 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4913 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4914 tcg_gen_subfi_tl(t1, 32, t1);
4915 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4916 tcg_gen_or_tl(t1, t0, t1);
4917 gen_store_spr(SPR_MQ, t1);
4918 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4919 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4920 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4921 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4922 gen_set_label(l1);
4923 tcg_temp_free(t0);
4924 tcg_temp_free(t1);
4925 if (unlikely(Rc(ctx->opcode) != 0))
4926 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4927 }
4928
4929 /* sraiq - sraiq. */
4930 static void gen_sraiq(DisasContext *ctx)
4931 {
4932 int sh = SH(ctx->opcode);
4933 int l1 = gen_new_label();
4934 TCGv t0 = tcg_temp_new();
4935 TCGv t1 = tcg_temp_new();
4936 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4937 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4938 tcg_gen_or_tl(t0, t0, t1);
4939 gen_store_spr(SPR_MQ, t0);
4940 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4941 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4942 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4943 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4944 gen_set_label(l1);
4945 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4946 tcg_temp_free(t0);
4947 tcg_temp_free(t1);
4948 if (unlikely(Rc(ctx->opcode) != 0))
4949 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4950 }
4951
4952 /* sraq - sraq. */
4953 static void gen_sraq(DisasContext *ctx)
4954 {
4955 int l1 = gen_new_label();
4956 int l2 = gen_new_label();
4957 TCGv t0 = tcg_temp_new();
4958 TCGv t1 = tcg_temp_local_new();
4959 TCGv t2 = tcg_temp_local_new();
4960 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4961 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4962 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4963 tcg_gen_subfi_tl(t2, 32, t2);
4964 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4965 tcg_gen_or_tl(t0, t0, t2);
4966 gen_store_spr(SPR_MQ, t0);
4967 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4968 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4969 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4970 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4971 gen_set_label(l1);
4972 tcg_temp_free(t0);
4973 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4974 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4975 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4976 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4977 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4978 gen_set_label(l2);
4979 tcg_temp_free(t1);
4980 tcg_temp_free(t2);
4981 if (unlikely(Rc(ctx->opcode) != 0))
4982 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4983 }
4984
4985 /* sre - sre. */
4986 static void gen_sre(DisasContext *ctx)
4987 {
4988 TCGv t0 = tcg_temp_new();
4989 TCGv t1 = tcg_temp_new();
4990 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4991 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4992 tcg_gen_subfi_tl(t1, 32, t1);
4993 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4994 tcg_gen_or_tl(t1, t0, t1);
4995 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4996 gen_store_spr(SPR_MQ, t1);
4997 tcg_temp_free(t0);
4998 tcg_temp_free(t1);
4999 if (unlikely(Rc(ctx->opcode) != 0))
5000 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5001 }
5002
5003 /* srea - srea. */
5004 static void gen_srea(DisasContext *ctx)
5005 {
5006 TCGv t0 = tcg_temp_new();
5007 TCGv t1 = tcg_temp_new();
5008 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5009 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5010 gen_store_spr(SPR_MQ, t0);
5011 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5012 tcg_temp_free(t0);
5013 tcg_temp_free(t1);
5014 if (unlikely(Rc(ctx->opcode) != 0))
5015 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5016 }
5017
5018 /* sreq */
5019 static void gen_sreq(DisasContext *ctx)
5020 {
5021 TCGv t0 = tcg_temp_new();
5022 TCGv t1 = tcg_temp_new();
5023 TCGv t2 = tcg_temp_new();
5024 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5025 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5026 tcg_gen_shr_tl(t1, t1, t0);
5027 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5028 gen_load_spr(t2, SPR_MQ);
5029 gen_store_spr(SPR_MQ, t0);
5030 tcg_gen_and_tl(t0, t0, t1);
5031 tcg_gen_andc_tl(t2, t2, t1);
5032 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5033 tcg_temp_free(t0);
5034 tcg_temp_free(t1);
5035 tcg_temp_free(t2);
5036 if (unlikely(Rc(ctx->opcode) != 0))
5037 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5038 }
5039
5040 /* sriq */
5041 static void gen_sriq(DisasContext *ctx)
5042 {
5043 int sh = SH(ctx->opcode);
5044 TCGv t0 = tcg_temp_new();
5045 TCGv t1 = tcg_temp_new();
5046 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5047 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5048 tcg_gen_or_tl(t1, t0, t1);
5049 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5050 gen_store_spr(SPR_MQ, t1);
5051 tcg_temp_free(t0);
5052 tcg_temp_free(t1);
5053 if (unlikely(Rc(ctx->opcode) != 0))
5054 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5055 }
5056
5057 /* srliq */
5058 static void gen_srliq(DisasContext *ctx)
5059 {
5060 int sh = SH(ctx->opcode);
5061 TCGv t0 = tcg_temp_new();
5062 TCGv t1 = tcg_temp_new();
5063 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5064 gen_load_spr(t1, SPR_MQ);
5065 gen_store_spr(SPR_MQ, t0);
5066 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5067 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5068 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5069 tcg_temp_free(t0);
5070 tcg_temp_free(t1);
5071 if (unlikely(Rc(ctx->opcode) != 0))
5072 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5073 }
5074
5075 /* srlq */
5076 static void gen_srlq(DisasContext *ctx)
5077 {
5078 int l1 = gen_new_label();
5079 int l2 = gen_new_label();
5080 TCGv t0 = tcg_temp_local_new();
5081 TCGv t1 = tcg_temp_local_new();
5082 TCGv t2 = tcg_temp_local_new();
5083 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5084 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5085 tcg_gen_shr_tl(t2, t1, t2);
5086 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5087 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5088 gen_load_spr(t0, SPR_MQ);
5089 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5090 tcg_gen_br(l2);
5091 gen_set_label(l1);
5092 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5093 tcg_gen_and_tl(t0, t0, t2);
5094 gen_load_spr(t1, SPR_MQ);
5095 tcg_gen_andc_tl(t1, t1, t2);
5096 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5097 gen_set_label(l2);
5098 tcg_temp_free(t0);
5099 tcg_temp_free(t1);
5100 tcg_temp_free(t2);
5101 if (unlikely(Rc(ctx->opcode) != 0))
5102 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5103 }
5104
5105 /* srq */
5106 static void gen_srq(DisasContext *ctx)
5107 {
5108 int l1 = gen_new_label();
5109 TCGv t0 = tcg_temp_new();
5110 TCGv t1 = tcg_temp_new();
5111 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5112 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5113 tcg_gen_subfi_tl(t1, 32, t1);
5114 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5115 tcg_gen_or_tl(t1, t0, t1);
5116 gen_store_spr(SPR_MQ, t1);
5117 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5118 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5119 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5120 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5121 gen_set_label(l1);
5122 tcg_temp_free(t0);
5123 tcg_temp_free(t1);
5124 if (unlikely(Rc(ctx->opcode) != 0))
5125 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5126 }
5127
5128 /* PowerPC 602 specific instructions */
5129
5130 /* dsa */
5131 static void gen_dsa(DisasContext *ctx)
5132 {
5133 /* XXX: TODO */
5134 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5135 }
5136
5137 /* esa */
5138 static void gen_esa(DisasContext *ctx)
5139 {
5140 /* XXX: TODO */
5141 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5142 }
5143
5144 /* mfrom */
5145 static void gen_mfrom(DisasContext *ctx)
5146 {
5147 #if defined(CONFIG_USER_ONLY)
5148 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5149 #else
5150 if (unlikely(!ctx->mem_idx)) {
5151 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5152 return;
5153 }
5154 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5155 #endif
5156 }
5157
5158 /* 602 - 603 - G2 TLB management */
5159
5160 /* tlbld */
5161 static void gen_tlbld_6xx(DisasContext *ctx)
5162 {
5163 #if defined(CONFIG_USER_ONLY)
5164 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5165 #else
5166 if (unlikely(!ctx->mem_idx)) {
5167 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5168 return;
5169 }
5170 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5171 #endif
5172 }
5173
5174 /* tlbli */
5175 static void gen_tlbli_6xx(DisasContext *ctx)
5176 {
5177 #if defined(CONFIG_USER_ONLY)
5178 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5179 #else
5180 if (unlikely(!ctx->mem_idx)) {
5181 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5182 return;
5183 }
5184 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5185 #endif
5186 }
5187
5188 /* 74xx TLB management */
5189
5190 /* tlbld */
5191 static void gen_tlbld_74xx(DisasContext *ctx)
5192 {
5193 #if defined(CONFIG_USER_ONLY)
5194 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5195 #else
5196 if (unlikely(!ctx->mem_idx)) {
5197 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5198 return;
5199 }
5200 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5201 #endif
5202 }
5203
5204 /* tlbli */
5205 static void gen_tlbli_74xx(DisasContext *ctx)
5206 {
5207 #if defined(CONFIG_USER_ONLY)
5208 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5209 #else
5210 if (unlikely(!ctx->mem_idx)) {
5211 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5212 return;
5213 }
5214 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5215 #endif
5216 }
5217
5218 /* POWER instructions not in PowerPC 601 */
5219
5220 /* clf */
5221 static void gen_clf(DisasContext *ctx)
5222 {
5223 /* Cache line flush: implemented as no-op */
5224 }
5225
5226 /* cli */
5227 static void gen_cli(DisasContext *ctx)
5228 {
5229 /* Cache line invalidate: privileged and treated as no-op */
5230 #if defined(CONFIG_USER_ONLY)
5231 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5232 #else
5233 if (unlikely(!ctx->mem_idx)) {
5234 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5235 return;
5236 }
5237 #endif
5238 }
5239
5240 /* dclst */
5241 static void gen_dclst(DisasContext *ctx)
5242 {
5243 /* Data cache line store: treated as no-op */
5244 }
5245
5246 static void gen_mfsri(DisasContext *ctx)
5247 {
5248 #if defined(CONFIG_USER_ONLY)
5249 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5250 #else
5251 int ra = rA(ctx->opcode);
5252 int rd = rD(ctx->opcode);
5253 TCGv t0;
5254 if (unlikely(!ctx->mem_idx)) {
5255 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5256 return;
5257 }
5258 t0 = tcg_temp_new();
5259 gen_addr_reg_index(ctx, t0);
5260 tcg_gen_shri_tl(t0, t0, 28);
5261 tcg_gen_andi_tl(t0, t0, 0xF);
5262 gen_helper_load_sr(cpu_gpr[rd], t0);
5263 tcg_temp_free(t0);
5264 if (ra != 0 && ra != rd)
5265 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5266 #endif
5267 }
5268
5269 static void gen_rac(DisasContext *ctx)
5270 {
5271 #if defined(CONFIG_USER_ONLY)
5272 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5273 #else
5274 TCGv t0;
5275 if (unlikely(!ctx->mem_idx)) {
5276 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5277 return;
5278 }
5279 t0 = tcg_temp_new();
5280 gen_addr_reg_index(ctx, t0);
5281 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5282 tcg_temp_free(t0);
5283 #endif
5284 }
5285
5286 static void gen_rfsvc(DisasContext *ctx)
5287 {
5288 #if defined(CONFIG_USER_ONLY)
5289 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5290 #else
5291 if (unlikely(!ctx->mem_idx)) {
5292 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5293 return;
5294 }
5295 gen_helper_rfsvc(cpu_env);
5296 gen_sync_exception(ctx);
5297 #endif
5298 }
5299
5300 /* svc is not implemented for now */
5301
5302 /* POWER2 specific instructions */
5303 /* Quad manipulation (load/store two floats at a time) */
5304
5305 /* lfq */
5306 static void gen_lfq(DisasContext *ctx)
5307 {
5308 int rd = rD(ctx->opcode);
5309 TCGv t0;
5310 gen_set_access_type(ctx, ACCESS_FLOAT);
5311 t0 = tcg_temp_new();
5312 gen_addr_imm_index(ctx, t0, 0);
5313 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5314 gen_addr_add(ctx, t0, t0, 8);
5315 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5316 tcg_temp_free(t0);
5317 }
5318
5319 /* lfqu */
5320 static void gen_lfqu(DisasContext *ctx)
5321 {
5322 int ra = rA(ctx->opcode);
5323 int rd = rD(ctx->opcode);
5324 TCGv t0, t1;
5325 gen_set_access_type(ctx, ACCESS_FLOAT);
5326 t0 = tcg_temp_new();
5327 t1 = tcg_temp_new();
5328 gen_addr_imm_index(ctx, t0, 0);
5329 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5330 gen_addr_add(ctx, t1, t0, 8);
5331 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5332 if (ra != 0)
5333 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5334 tcg_temp_free(t0);
5335 tcg_temp_free(t1);
5336 }
5337
5338 /* lfqux */
5339 static void gen_lfqux(DisasContext *ctx)
5340 {
5341 int ra = rA(ctx->opcode);
5342 int rd = rD(ctx->opcode);
5343 gen_set_access_type(ctx, ACCESS_FLOAT);
5344 TCGv t0, t1;
5345 t0 = tcg_temp_new();
5346 gen_addr_reg_index(ctx, t0);
5347 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5348 t1 = tcg_temp_new();
5349 gen_addr_add(ctx, t1, t0, 8);
5350 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5351 tcg_temp_free(t1);
5352 if (ra != 0)
5353 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5354 tcg_temp_free(t0);
5355 }
5356
5357 /* lfqx */
5358 static void gen_lfqx(DisasContext *ctx)
5359 {
5360 int rd = rD(ctx->opcode);
5361 TCGv t0;
5362 gen_set_access_type(ctx, ACCESS_FLOAT);
5363 t0 = tcg_temp_new();
5364 gen_addr_reg_index(ctx, t0);
5365 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5366 gen_addr_add(ctx, t0, t0, 8);
5367 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5368 tcg_temp_free(t0);
5369 }
5370
5371 /* stfq */
5372 static void gen_stfq(DisasContext *ctx)
5373 {
5374 int rd = rD(ctx->opcode);
5375 TCGv t0;
5376 gen_set_access_type(ctx, ACCESS_FLOAT);
5377 t0 = tcg_temp_new();
5378 gen_addr_imm_index(ctx, t0, 0);
5379 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5380 gen_addr_add(ctx, t0, t0, 8);
5381 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5382 tcg_temp_free(t0);
5383 }
5384
5385 /* stfqu */
5386 static void gen_stfqu(DisasContext *ctx)
5387 {
5388 int ra = rA(ctx->opcode);
5389 int rd = rD(ctx->opcode);
5390 TCGv t0, t1;
5391 gen_set_access_type(ctx, ACCESS_FLOAT);
5392 t0 = tcg_temp_new();
5393 gen_addr_imm_index(ctx, t0, 0);
5394 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5395 t1 = tcg_temp_new();
5396 gen_addr_add(ctx, t1, t0, 8);
5397 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5398 tcg_temp_free(t1);
5399 if (ra != 0)
5400 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5401 tcg_temp_free(t0);
5402 }
5403
5404 /* stfqux */
5405 static void gen_stfqux(DisasContext *ctx)
5406 {
5407 int ra = rA(ctx->opcode);
5408 int rd = rD(ctx->opcode);
5409 TCGv t0, t1;
5410 gen_set_access_type(ctx, ACCESS_FLOAT);
5411 t0 = tcg_temp_new();
5412 gen_addr_reg_index(ctx, t0);
5413 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5414 t1 = tcg_temp_new();
5415 gen_addr_add(ctx, t1, t0, 8);
5416 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5417 tcg_temp_free(t1);
5418 if (ra != 0)
5419 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5420 tcg_temp_free(t0);
5421 }
5422
5423 /* stfqx */
5424 static void gen_stfqx(DisasContext *ctx)
5425 {
5426 int rd = rD(ctx->opcode);
5427 TCGv t0;
5428 gen_set_access_type(ctx, ACCESS_FLOAT);
5429 t0 = tcg_temp_new();
5430 gen_addr_reg_index(ctx, t0);
5431 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5432 gen_addr_add(ctx, t0, t0, 8);
5433 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5434 tcg_temp_free(t0);
5435 }
5436
5437 /* BookE specific instructions */
5438
5439 /* XXX: not implemented on 440 ? */
5440 static void gen_mfapidi(DisasContext *ctx)
5441 {
5442 /* XXX: TODO */
5443 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5444 }
5445
5446 /* XXX: not implemented on 440 ? */
5447 static void gen_tlbiva(DisasContext *ctx)
5448 {
5449 #if defined(CONFIG_USER_ONLY)
5450 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5451 #else
5452 TCGv t0;
5453 if (unlikely(!ctx->mem_idx)) {
5454 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5455 return;
5456 }
5457 t0 = tcg_temp_new();
5458 gen_addr_reg_index(ctx, t0);
5459 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5460 tcg_temp_free(t0);
5461 #endif
5462 }
5463
5464 /* All 405 MAC instructions are translated here */
5465 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5466 int ra, int rb, int rt, int Rc)
5467 {
5468 TCGv t0, t1;
5469
5470 t0 = tcg_temp_local_new();
5471 t1 = tcg_temp_local_new();
5472
5473 switch (opc3 & 0x0D) {
5474 case 0x05:
5475 /* macchw - macchw. - macchwo - macchwo. */
5476 /* macchws - macchws. - macchwso - macchwso. */
5477 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5478 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5479 /* mulchw - mulchw. */
5480 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5481 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5482 tcg_gen_ext16s_tl(t1, t1);
5483 break;
5484 case 0x04:
5485 /* macchwu - macchwu. - macchwuo - macchwuo. */
5486 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5487 /* mulchwu - mulchwu. */
5488 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5489 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5490 tcg_gen_ext16u_tl(t1, t1);
5491 break;
5492 case 0x01:
5493 /* machhw - machhw. - machhwo - machhwo. */
5494 /* machhws - machhws. - machhwso - machhwso. */
5495 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5496 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5497 /* mulhhw - mulhhw. */
5498 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5499 tcg_gen_ext16s_tl(t0, t0);
5500 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5501 tcg_gen_ext16s_tl(t1, t1);
5502 break;
5503 case 0x00:
5504 /* machhwu - machhwu. - machhwuo - machhwuo. */
5505 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5506 /* mulhhwu - mulhhwu. */
5507 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5508 tcg_gen_ext16u_tl(t0, t0);
5509 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5510 tcg_gen_ext16u_tl(t1, t1);
5511 break;
5512 case 0x0D:
5513 /* maclhw - maclhw. - maclhwo - maclhwo. */
5514 /* maclhws - maclhws. - maclhwso - maclhwso. */
5515 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5516 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5517 /* mullhw - mullhw. */
5518 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5519 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5520 break;
5521 case 0x0C:
5522 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5523 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5524 /* mullhwu - mullhwu. */
5525 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5526 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5527 break;
5528 }
5529 if (opc2 & 0x04) {
5530 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5531 tcg_gen_mul_tl(t1, t0, t1);
5532 if (opc2 & 0x02) {
5533 /* nmultiply-and-accumulate (0x0E) */
5534 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5535 } else {
5536 /* multiply-and-accumulate (0x0C) */
5537 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5538 }
5539
5540 if (opc3 & 0x12) {
5541 /* Check overflow and/or saturate */
5542 int l1 = gen_new_label();
5543
5544 if (opc3 & 0x10) {
5545 /* Start with XER OV disabled, the most likely case */
5546 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5547 }
5548 if (opc3 & 0x01) {
5549 /* Signed */
5550 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5551 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5552 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5553 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5554 if (opc3 & 0x02) {
5555 /* Saturate */
5556 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5557 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5558 }
5559 } else {
5560 /* Unsigned */
5561 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5562 if (opc3 & 0x02) {
5563 /* Saturate */
5564 tcg_gen_movi_tl(t0, UINT32_MAX);
5565 }
5566 }
5567 if (opc3 & 0x10) {
5568 /* Check overflow */
5569 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5570 }
5571 gen_set_label(l1);
5572 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5573 }
5574 } else {
5575 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5576 }
5577 tcg_temp_free(t0);
5578 tcg_temp_free(t1);
5579 if (unlikely(Rc) != 0) {
5580 /* Update Rc0 */
5581 gen_set_Rc0(ctx, cpu_gpr[rt]);
5582 }
5583 }
5584
5585 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5586 static void glue(gen_, name)(DisasContext *ctx) \
5587 { \
5588 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5589 rD(ctx->opcode), Rc(ctx->opcode)); \
5590 }
5591
5592 /* macchw - macchw. */
5593 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5594 /* macchwo - macchwo. */
5595 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5596 /* macchws - macchws. */
5597 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5598 /* macchwso - macchwso. */
5599 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5600 /* macchwsu - macchwsu. */
5601 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5602 /* macchwsuo - macchwsuo. */
5603 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5604 /* macchwu - macchwu. */
5605 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5606 /* macchwuo - macchwuo. */
5607 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5608 /* machhw - machhw. */
5609 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5610 /* machhwo - machhwo. */
5611 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5612 /* machhws - machhws. */
5613 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5614 /* machhwso - machhwso. */
5615 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5616 /* machhwsu - machhwsu. */
5617 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5618 /* machhwsuo - machhwsuo. */
5619 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5620 /* machhwu - machhwu. */
5621 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5622 /* machhwuo - machhwuo. */
5623 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5624 /* maclhw - maclhw. */
5625 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5626 /* maclhwo - maclhwo. */
5627 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5628 /* maclhws - maclhws. */
5629 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5630 /* maclhwso - maclhwso. */
5631 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5632 /* maclhwu - maclhwu. */
5633 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5634 /* maclhwuo - maclhwuo. */
5635 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5636 /* maclhwsu - maclhwsu. */
5637 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5638 /* maclhwsuo - maclhwsuo. */
5639 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5640 /* nmacchw - nmacchw. */
5641 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5642 /* nmacchwo - nmacchwo. */
5643 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5644 /* nmacchws - nmacchws. */
5645 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5646 /* nmacchwso - nmacchwso. */
5647 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5648 /* nmachhw - nmachhw. */
5649 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5650 /* nmachhwo - nmachhwo. */
5651 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5652 /* nmachhws - nmachhws. */
5653 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5654 /* nmachhwso - nmachhwso. */
5655 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5656 /* nmaclhw - nmaclhw. */
5657 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5658 /* nmaclhwo - nmaclhwo. */
5659 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5660 /* nmaclhws - nmaclhws. */
5661 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5662 /* nmaclhwso - nmaclhwso. */
5663 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5664
5665 /* mulchw - mulchw. */
5666 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5667 /* mulchwu - mulchwu. */
5668 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5669 /* mulhhw - mulhhw. */
5670 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5671 /* mulhhwu - mulhhwu. */
5672 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5673 /* mullhw - mullhw. */
5674 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5675 /* mullhwu - mullhwu. */
5676 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5677
5678 /* mfdcr */
5679 static void gen_mfdcr(DisasContext *ctx)
5680 {
5681 #if defined(CONFIG_USER_ONLY)
5682 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5683 #else
5684 TCGv dcrn;
5685 if (unlikely(!ctx->mem_idx)) {
5686 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5687 return;
5688 }
5689 /* NIP cannot be restored if the memory exception comes from an helper */
5690 gen_update_nip(ctx, ctx->nip - 4);
5691 dcrn = tcg_const_tl(SPR(ctx->opcode));
5692 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5693 tcg_temp_free(dcrn);
5694 #endif
5695 }
5696
5697 /* mtdcr */
5698 static void gen_mtdcr(DisasContext *ctx)
5699 {
5700 #if defined(CONFIG_USER_ONLY)
5701 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5702 #else
5703 TCGv dcrn;
5704 if (unlikely(!ctx->mem_idx)) {
5705 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5706 return;
5707 }
5708 /* NIP cannot be restored if the memory exception comes from an helper */
5709 gen_update_nip(ctx, ctx->nip - 4);
5710 dcrn = tcg_const_tl(SPR(ctx->opcode));
5711 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5712 tcg_temp_free(dcrn);
5713 #endif
5714 }
5715
5716 /* mfdcrx */
5717 /* XXX: not implemented on 440 ? */
5718 static void gen_mfdcrx(DisasContext *ctx)
5719 {
5720 #if defined(CONFIG_USER_ONLY)
5721 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5722 #else
5723 if (unlikely(!ctx->mem_idx)) {
5724 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5725 return;
5726 }
5727 /* NIP cannot be restored if the memory exception comes from an helper */
5728 gen_update_nip(ctx, ctx->nip - 4);
5729 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5730 /* Note: Rc update flag set leads to undefined state of Rc0 */
5731 #endif
5732 }
5733
5734 /* mtdcrx */
5735 /* XXX: not implemented on 440 ? */
5736 static void gen_mtdcrx(DisasContext *ctx)
5737 {
5738 #if defined(CONFIG_USER_ONLY)
5739 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5740 #else
5741 if (unlikely(!ctx->mem_idx)) {
5742 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5743 return;
5744 }
5745 /* NIP cannot be restored if the memory exception comes from an helper */
5746 gen_update_nip(ctx, ctx->nip - 4);
5747 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5748 /* Note: Rc update flag set leads to undefined state of Rc0 */
5749 #endif
5750 }
5751
5752 /* mfdcrux (PPC 460) : user-mode access to DCR */
5753 static void gen_mfdcrux(DisasContext *ctx)
5754 {
5755 /* NIP cannot be restored if the memory exception comes from an helper */
5756 gen_update_nip(ctx, ctx->nip - 4);
5757 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5758 /* Note: Rc update flag set leads to undefined state of Rc0 */
5759 }
5760
5761 /* mtdcrux (PPC 460) : user-mode access to DCR */
5762 static void gen_mtdcrux(DisasContext *ctx)
5763 {
5764 /* NIP cannot be restored if the memory exception comes from an helper */
5765 gen_update_nip(ctx, ctx->nip - 4);
5766 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5767 /* Note: Rc update flag set leads to undefined state of Rc0 */
5768 }
5769
5770 /* dccci */
5771 static void gen_dccci(DisasContext *ctx)
5772 {
5773 #if defined(CONFIG_USER_ONLY)
5774 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5775 #else
5776 if (unlikely(!ctx->mem_idx)) {
5777 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5778 return;
5779 }
5780 /* interpreted as no-op */
5781 #endif
5782 }
5783
5784 /* dcread */
5785 static void gen_dcread(DisasContext *ctx)
5786 {
5787 #if defined(CONFIG_USER_ONLY)
5788 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5789 #else
5790 TCGv EA, val;
5791 if (unlikely(!ctx->mem_idx)) {
5792 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5793 return;
5794 }
5795 gen_set_access_type(ctx, ACCESS_CACHE);
5796 EA = tcg_temp_new();
5797 gen_addr_reg_index(ctx, EA);
5798 val = tcg_temp_new();
5799 gen_qemu_ld32u(ctx, val, EA);
5800 tcg_temp_free(val);
5801 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5802 tcg_temp_free(EA);
5803 #endif
5804 }
5805
5806 /* icbt */
5807 static void gen_icbt_40x(DisasContext *ctx)
5808 {
5809 /* interpreted as no-op */
5810 /* XXX: specification say this is treated as a load by the MMU
5811 * but does not generate any exception
5812 */
5813 }
5814
5815 /* iccci */
5816 static void gen_iccci(DisasContext *ctx)
5817 {
5818 #if defined(CONFIG_USER_ONLY)
5819 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5820 #else
5821 if (unlikely(!ctx->mem_idx)) {
5822 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5823 return;
5824 }
5825 /* interpreted as no-op */
5826 #endif
5827 }
5828
5829 /* icread */
5830 static void gen_icread(DisasContext *ctx)
5831 {
5832 #if defined(CONFIG_USER_ONLY)
5833 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5834 #else
5835 if (unlikely(!ctx->mem_idx)) {
5836 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5837 return;
5838 }
5839 /* interpreted as no-op */
5840 #endif
5841 }
5842
5843 /* rfci (mem_idx only) */
5844 static void gen_rfci_40x(DisasContext *ctx)
5845 {
5846 #if defined(CONFIG_USER_ONLY)
5847 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5848 #else
5849 if (unlikely(!ctx->mem_idx)) {
5850 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5851 return;
5852 }
5853 /* Restore CPU state */
5854 gen_helper_40x_rfci(cpu_env);
5855 gen_sync_exception(ctx);
5856 #endif
5857 }
5858
5859 static void gen_rfci(DisasContext *ctx)
5860 {
5861 #if defined(CONFIG_USER_ONLY)
5862 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5863 #else
5864 if (unlikely(!ctx->mem_idx)) {
5865 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5866 return;
5867 }
5868 /* Restore CPU state */
5869 gen_helper_rfci(cpu_env);
5870 gen_sync_exception(ctx);
5871 #endif
5872 }
5873
5874 /* BookE specific */
5875
5876 /* XXX: not implemented on 440 ? */
5877 static void gen_rfdi(DisasContext *ctx)
5878 {
5879 #if defined(CONFIG_USER_ONLY)
5880 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5881 #else
5882 if (unlikely(!ctx->mem_idx)) {
5883 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5884 return;
5885 }
5886 /* Restore CPU state */
5887 gen_helper_rfdi(cpu_env);
5888 gen_sync_exception(ctx);
5889 #endif
5890 }
5891
5892 /* XXX: not implemented on 440 ? */
5893 static void gen_rfmci(DisasContext *ctx)
5894 {
5895 #if defined(CONFIG_USER_ONLY)
5896 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5897 #else
5898 if (unlikely(!ctx->mem_idx)) {
5899 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5900 return;
5901 }
5902 /* Restore CPU state */
5903 gen_helper_rfmci(cpu_env);
5904 gen_sync_exception(ctx);
5905 #endif
5906 }
5907
5908 /* TLB management - PowerPC 405 implementation */
5909
5910 /* tlbre */
5911 static void gen_tlbre_40x(DisasContext *ctx)
5912 {
5913 #if defined(CONFIG_USER_ONLY)
5914 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5915 #else
5916 if (unlikely(!ctx->mem_idx)) {
5917 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5918 return;
5919 }
5920 switch (rB(ctx->opcode)) {
5921 case 0:
5922 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5923 break;
5924 case 1:
5925 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5926 break;
5927 default:
5928 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5929 break;
5930 }
5931 #endif
5932 }
5933
5934 /* tlbsx - tlbsx. */
5935 static void gen_tlbsx_40x(DisasContext *ctx)
5936 {
5937 #if defined(CONFIG_USER_ONLY)
5938 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5939 #else
5940 TCGv t0;
5941 if (unlikely(!ctx->mem_idx)) {
5942 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5943 return;
5944 }
5945 t0 = tcg_temp_new();
5946 gen_addr_reg_index(ctx, t0);
5947 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5948 tcg_temp_free(t0);
5949 if (Rc(ctx->opcode)) {
5950 int l1 = gen_new_label();
5951 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5952 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5953 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5954 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5955 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5956 gen_set_label(l1);
5957 }
5958 #endif
5959 }
5960
5961 /* tlbwe */
5962 static void gen_tlbwe_40x(DisasContext *ctx)
5963 {
5964 #if defined(CONFIG_USER_ONLY)
5965 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5966 #else
5967 if (unlikely(!ctx->mem_idx)) {
5968 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5969 return;
5970 }
5971 switch (rB(ctx->opcode)) {
5972 case 0:
5973 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5974 break;
5975 case 1:
5976 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5977 break;
5978 default:
5979 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5980 break;
5981 }
5982 #endif
5983 }
5984
5985 /* TLB management - PowerPC 440 implementation */
5986
5987 /* tlbre */
5988 static void gen_tlbre_440(DisasContext *ctx)
5989 {
5990 #if defined(CONFIG_USER_ONLY)
5991 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5992 #else
5993 if (unlikely(!ctx->mem_idx)) {
5994 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5995 return;
5996 }
5997 switch (rB(ctx->opcode)) {
5998 case 0:
5999 case 1:
6000 case 2:
6001 {
6002 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6003 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], t0, cpu_gpr[rA(ctx->opcode)]);
6004 tcg_temp_free_i32(t0);
6005 }
6006 break;
6007 default:
6008 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6009 break;
6010 }
6011 #endif
6012 }
6013
6014 /* tlbsx - tlbsx. */
6015 static void gen_tlbsx_440(DisasContext *ctx)
6016 {
6017 #if defined(CONFIG_USER_ONLY)
6018 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6019 #else
6020 TCGv t0;
6021 if (unlikely(!ctx->mem_idx)) {
6022 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6023 return;
6024 }
6025 t0 = tcg_temp_new();
6026 gen_addr_reg_index(ctx, t0);
6027 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
6028 tcg_temp_free(t0);
6029 if (Rc(ctx->opcode)) {
6030 int l1 = gen_new_label();
6031 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
6032 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
6033 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
6034 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6035 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6036 gen_set_label(l1);
6037 }
6038 #endif
6039 }
6040
6041 /* tlbwe */
6042 static void gen_tlbwe_440(DisasContext *ctx)
6043 {
6044 #if defined(CONFIG_USER_ONLY)
6045 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6046 #else
6047 if (unlikely(!ctx->mem_idx)) {
6048 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6049 return;
6050 }
6051 switch (rB(ctx->opcode)) {
6052 case 0:
6053 case 1:
6054 case 2:
6055 {
6056 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6057 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6058 tcg_temp_free_i32(t0);
6059 }
6060 break;
6061 default:
6062 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6063 break;
6064 }
6065 #endif
6066 }
6067
6068 /* TLB management - PowerPC BookE 2.06 implementation */
6069
6070 /* tlbre */
6071 static void gen_tlbre_booke206(DisasContext *ctx)
6072 {
6073 #if defined(CONFIG_USER_ONLY)
6074 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6075 #else
6076 if (unlikely(!ctx->mem_idx)) {
6077 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6078 return;
6079 }
6080
6081 gen_helper_booke206_tlbre();
6082 #endif
6083 }
6084
6085 /* tlbsx - tlbsx. */
6086 static void gen_tlbsx_booke206(DisasContext *ctx)
6087 {
6088 #if defined(CONFIG_USER_ONLY)
6089 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6090 #else
6091 TCGv t0;
6092 if (unlikely(!ctx->mem_idx)) {
6093 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6094 return;
6095 }
6096
6097 if (rA(ctx->opcode)) {
6098 t0 = tcg_temp_new();
6099 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6100 } else {
6101 t0 = tcg_const_tl(0);
6102 }
6103
6104 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6105 gen_helper_booke206_tlbsx(t0);
6106 #endif
6107 }
6108
6109 /* tlbwe */
6110 static void gen_tlbwe_booke206(DisasContext *ctx)
6111 {
6112 #if defined(CONFIG_USER_ONLY)
6113 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6114 #else
6115 if (unlikely(!ctx->mem_idx)) {
6116 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6117 return;
6118 }
6119 gen_update_nip(ctx, ctx->nip - 4);
6120 gen_helper_booke206_tlbwe();
6121 #endif
6122 }
6123
6124 static void gen_tlbivax_booke206(DisasContext *ctx)
6125 {
6126 #if defined(CONFIG_USER_ONLY)
6127 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6128 #else
6129 TCGv t0;
6130 if (unlikely(!ctx->mem_idx)) {
6131 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6132 return;
6133 }
6134
6135 t0 = tcg_temp_new();
6136 gen_addr_reg_index(ctx, t0);
6137
6138 gen_helper_booke206_tlbivax(t0);
6139 #endif
6140 }
6141
6142 static void gen_tlbilx_booke206(DisasContext *ctx)
6143 {
6144 #if defined(CONFIG_USER_ONLY)
6145 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6146 #else
6147 TCGv t0;
6148 if (unlikely(!ctx->mem_idx)) {
6149 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6150 return;
6151 }
6152
6153 t0 = tcg_temp_new();
6154 gen_addr_reg_index(ctx, t0);
6155
6156 switch((ctx->opcode >> 21) & 0x3) {
6157 case 0:
6158 gen_helper_booke206_tlbilx0(t0);
6159 break;
6160 case 1:
6161 gen_helper_booke206_tlbilx1(t0);
6162 break;
6163 case 3:
6164 gen_helper_booke206_tlbilx3(t0);
6165 break;
6166 default:
6167 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6168 break;
6169 }
6170
6171 tcg_temp_free(t0);
6172 #endif
6173 }
6174
6175
6176 /* wrtee */
6177 static void gen_wrtee(DisasContext *ctx)
6178 {
6179 #if defined(CONFIG_USER_ONLY)
6180 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6181 #else
6182 TCGv t0;
6183 if (unlikely(!ctx->mem_idx)) {
6184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6185 return;
6186 }
6187 t0 = tcg_temp_new();
6188 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6189 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6190 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6191 tcg_temp_free(t0);
6192 /* Stop translation to have a chance to raise an exception
6193 * if we just set msr_ee to 1
6194 */
6195 gen_stop_exception(ctx);
6196 #endif
6197 }
6198
6199 /* wrteei */
6200 static void gen_wrteei(DisasContext *ctx)
6201 {
6202 #if defined(CONFIG_USER_ONLY)
6203 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6204 #else
6205 if (unlikely(!ctx->mem_idx)) {
6206 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6207 return;
6208 }
6209 if (ctx->opcode & 0x00008000) {
6210 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6211 /* Stop translation to have a chance to raise an exception */
6212 gen_stop_exception(ctx);
6213 } else {
6214 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6215 }
6216 #endif
6217 }
6218
6219 /* PowerPC 440 specific instructions */
6220
6221 /* dlmzb */
6222 static void gen_dlmzb(DisasContext *ctx)
6223 {
6224 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6225 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6226 cpu_gpr[rB(ctx->opcode)], t0);
6227 tcg_temp_free_i32(t0);
6228 }
6229
6230 /* mbar replaces eieio on 440 */
6231 static void gen_mbar(DisasContext *ctx)
6232 {
6233 /* interpreted as no-op */
6234 }
6235
6236 /* msync replaces sync on 440 */
6237 static void gen_msync_4xx(DisasContext *ctx)
6238 {
6239 /* interpreted as no-op */
6240 }
6241
6242 /* icbt */
6243 static void gen_icbt_440(DisasContext *ctx)
6244 {
6245 /* interpreted as no-op */
6246 /* XXX: specification say this is treated as a load by the MMU
6247 * but does not generate any exception
6248 */
6249 }
6250
6251 /* Embedded.Processor Control */
6252
6253 static void gen_msgclr(DisasContext *ctx)
6254 {
6255 #if defined(CONFIG_USER_ONLY)
6256 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6257 #else
6258 if (unlikely(ctx->mem_idx == 0)) {
6259 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6260 return;
6261 }
6262
6263 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6264 #endif
6265 }
6266
6267 static void gen_msgsnd(DisasContext *ctx)
6268 {
6269 #if defined(CONFIG_USER_ONLY)
6270 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6271 #else
6272 if (unlikely(ctx->mem_idx == 0)) {
6273 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6274 return;
6275 }
6276
6277 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6278 #endif
6279 }
6280
6281 /*** Altivec vector extension ***/
6282 /* Altivec registers moves */
6283
6284 static inline TCGv_ptr gen_avr_ptr(int reg)
6285 {
6286 TCGv_ptr r = tcg_temp_new_ptr();
6287 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6288 return r;
6289 }
6290
6291 #define GEN_VR_LDX(name, opc2, opc3) \
6292 static void glue(gen_, name)(DisasContext *ctx) \
6293 { \
6294 TCGv EA; \
6295 if (unlikely(!ctx->altivec_enabled)) { \
6296 gen_exception(ctx, POWERPC_EXCP_VPU); \
6297 return; \
6298 } \
6299 gen_set_access_type(ctx, ACCESS_INT); \
6300 EA = tcg_temp_new(); \
6301 gen_addr_reg_index(ctx, EA); \
6302 tcg_gen_andi_tl(EA, EA, ~0xf); \
6303 if (ctx->le_mode) { \
6304 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6305 tcg_gen_addi_tl(EA, EA, 8); \
6306 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6307 } else { \
6308 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6309 tcg_gen_addi_tl(EA, EA, 8); \
6310 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6311 } \
6312 tcg_temp_free(EA); \
6313 }
6314
6315 #define GEN_VR_STX(name, opc2, opc3) \
6316 static void gen_st##name(DisasContext *ctx) \
6317 { \
6318 TCGv EA; \
6319 if (unlikely(!ctx->altivec_enabled)) { \
6320 gen_exception(ctx, POWERPC_EXCP_VPU); \
6321 return; \
6322 } \
6323 gen_set_access_type(ctx, ACCESS_INT); \
6324 EA = tcg_temp_new(); \
6325 gen_addr_reg_index(ctx, EA); \
6326 tcg_gen_andi_tl(EA, EA, ~0xf); \
6327 if (ctx->le_mode) { \
6328 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6329 tcg_gen_addi_tl(EA, EA, 8); \
6330 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6331 } else { \
6332 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6333 tcg_gen_addi_tl(EA, EA, 8); \
6334 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6335 } \
6336 tcg_temp_free(EA); \
6337 }
6338
6339 #define GEN_VR_LVE(name, opc2, opc3) \
6340 static void gen_lve##name(DisasContext *ctx) \
6341 { \
6342 TCGv EA; \
6343 TCGv_ptr rs; \
6344 if (unlikely(!ctx->altivec_enabled)) { \
6345 gen_exception(ctx, POWERPC_EXCP_VPU); \
6346 return; \
6347 } \
6348 gen_set_access_type(ctx, ACCESS_INT); \
6349 EA = tcg_temp_new(); \
6350 gen_addr_reg_index(ctx, EA); \
6351 rs = gen_avr_ptr(rS(ctx->opcode)); \
6352 gen_helper_lve##name (rs, EA); \
6353 tcg_temp_free(EA); \
6354 tcg_temp_free_ptr(rs); \
6355 }
6356
6357 #define GEN_VR_STVE(name, opc2, opc3) \
6358 static void gen_stve##name(DisasContext *ctx) \
6359 { \
6360 TCGv EA; \
6361 TCGv_ptr rs; \
6362 if (unlikely(!ctx->altivec_enabled)) { \
6363 gen_exception(ctx, POWERPC_EXCP_VPU); \
6364 return; \
6365 } \
6366 gen_set_access_type(ctx, ACCESS_INT); \
6367 EA = tcg_temp_new(); \
6368 gen_addr_reg_index(ctx, EA); \
6369 rs = gen_avr_ptr(rS(ctx->opcode)); \
6370 gen_helper_stve##name (rs, EA); \
6371 tcg_temp_free(EA); \
6372 tcg_temp_free_ptr(rs); \
6373 }
6374
6375 GEN_VR_LDX(lvx, 0x07, 0x03);
6376 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6377 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6378
6379 GEN_VR_LVE(bx, 0x07, 0x00);
6380 GEN_VR_LVE(hx, 0x07, 0x01);
6381 GEN_VR_LVE(wx, 0x07, 0x02);
6382
6383 GEN_VR_STX(svx, 0x07, 0x07);
6384 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6385 GEN_VR_STX(svxl, 0x07, 0x0F);
6386
6387 GEN_VR_STVE(bx, 0x07, 0x04);
6388 GEN_VR_STVE(hx, 0x07, 0x05);
6389 GEN_VR_STVE(wx, 0x07, 0x06);
6390
6391 static void gen_lvsl(DisasContext *ctx)
6392 {
6393 TCGv_ptr rd;
6394 TCGv EA;
6395 if (unlikely(!ctx->altivec_enabled)) {
6396 gen_exception(ctx, POWERPC_EXCP_VPU);
6397 return;
6398 }
6399 EA = tcg_temp_new();
6400 gen_addr_reg_index(ctx, EA);
6401 rd = gen_avr_ptr(rD(ctx->opcode));
6402 gen_helper_lvsl(rd, EA);
6403 tcg_temp_free(EA);
6404 tcg_temp_free_ptr(rd);
6405 }
6406
6407 static void gen_lvsr(DisasContext *ctx)
6408 {
6409 TCGv_ptr rd;
6410 TCGv EA;
6411 if (unlikely(!ctx->altivec_enabled)) {
6412 gen_exception(ctx, POWERPC_EXCP_VPU);
6413 return;
6414 }
6415 EA = tcg_temp_new();
6416 gen_addr_reg_index(ctx, EA);
6417 rd = gen_avr_ptr(rD(ctx->opcode));
6418 gen_helper_lvsr(rd, EA);
6419 tcg_temp_free(EA);
6420 tcg_temp_free_ptr(rd);
6421 }
6422
6423 static void gen_mfvscr(DisasContext *ctx)
6424 {
6425 TCGv_i32 t;
6426 if (unlikely(!ctx->altivec_enabled)) {
6427 gen_exception(ctx, POWERPC_EXCP_VPU);
6428 return;
6429 }
6430 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6431 t = tcg_temp_new_i32();
6432 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6433 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6434 tcg_temp_free_i32(t);
6435 }
6436
6437 static void gen_mtvscr(DisasContext *ctx)
6438 {
6439 TCGv_ptr p;
6440 if (unlikely(!ctx->altivec_enabled)) {
6441 gen_exception(ctx, POWERPC_EXCP_VPU);
6442 return;
6443 }
6444 p = gen_avr_ptr(rD(ctx->opcode));
6445 gen_helper_mtvscr(p);
6446 tcg_temp_free_ptr(p);
6447 }
6448
6449 /* Logical operations */
6450 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6451 static void glue(gen_, name)(DisasContext *ctx) \
6452 { \
6453 if (unlikely(!ctx->altivec_enabled)) { \
6454 gen_exception(ctx, POWERPC_EXCP_VPU); \
6455 return; \
6456 } \
6457 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6458 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6459 }
6460
6461 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6462 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6463 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6464 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6465 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6466
6467 #define GEN_VXFORM(name, opc2, opc3) \
6468 static void glue(gen_, name)(DisasContext *ctx) \
6469 { \
6470 TCGv_ptr ra, rb, rd; \
6471 if (unlikely(!ctx->altivec_enabled)) { \
6472 gen_exception(ctx, POWERPC_EXCP_VPU); \
6473 return; \
6474 } \
6475 ra = gen_avr_ptr(rA(ctx->opcode)); \
6476 rb = gen_avr_ptr(rB(ctx->opcode)); \
6477 rd = gen_avr_ptr(rD(ctx->opcode)); \
6478 gen_helper_##name (rd, ra, rb); \
6479 tcg_temp_free_ptr(ra); \
6480 tcg_temp_free_ptr(rb); \
6481 tcg_temp_free_ptr(rd); \
6482 }
6483
6484 GEN_VXFORM(vaddubm, 0, 0);
6485 GEN_VXFORM(vadduhm, 0, 1);
6486 GEN_VXFORM(vadduwm, 0, 2);
6487 GEN_VXFORM(vsububm, 0, 16);
6488 GEN_VXFORM(vsubuhm, 0, 17);
6489 GEN_VXFORM(vsubuwm, 0, 18);
6490 GEN_VXFORM(vmaxub, 1, 0);
6491 GEN_VXFORM(vmaxuh, 1, 1);
6492 GEN_VXFORM(vmaxuw, 1, 2);
6493 GEN_VXFORM(vmaxsb, 1, 4);
6494 GEN_VXFORM(vmaxsh, 1, 5);
6495 GEN_VXFORM(vmaxsw, 1, 6);
6496 GEN_VXFORM(vminub, 1, 8);
6497 GEN_VXFORM(vminuh, 1, 9);
6498 GEN_VXFORM(vminuw, 1, 10);
6499 GEN_VXFORM(vminsb, 1, 12);
6500 GEN_VXFORM(vminsh, 1, 13);
6501 GEN_VXFORM(vminsw, 1, 14);
6502 GEN_VXFORM(vavgub, 1, 16);
6503 GEN_VXFORM(vavguh, 1, 17);
6504 GEN_VXFORM(vavguw, 1, 18);
6505 GEN_VXFORM(vavgsb, 1, 20);
6506 GEN_VXFORM(vavgsh, 1, 21);
6507 GEN_VXFORM(vavgsw, 1, 22);
6508 GEN_VXFORM(vmrghb, 6, 0);
6509 GEN_VXFORM(vmrghh, 6, 1);
6510 GEN_VXFORM(vmrghw, 6, 2);
6511 GEN_VXFORM(vmrglb, 6, 4);
6512 GEN_VXFORM(vmrglh, 6, 5);
6513 GEN_VXFORM(vmrglw, 6, 6);
6514 GEN_VXFORM(vmuloub, 4, 0);
6515 GEN_VXFORM(vmulouh, 4, 1);
6516 GEN_VXFORM(vmulosb, 4, 4);
6517 GEN_VXFORM(vmulosh, 4, 5);
6518 GEN_VXFORM(vmuleub, 4, 8);
6519 GEN_VXFORM(vmuleuh, 4, 9);
6520 GEN_VXFORM(vmulesb, 4, 12);
6521 GEN_VXFORM(vmulesh, 4, 13);
6522 GEN_VXFORM(vslb, 2, 4);
6523 GEN_VXFORM(vslh, 2, 5);
6524 GEN_VXFORM(vslw, 2, 6);
6525 GEN_VXFORM(vsrb, 2, 8);
6526 GEN_VXFORM(vsrh, 2, 9);
6527 GEN_VXFORM(vsrw, 2, 10);
6528 GEN_VXFORM(vsrab, 2, 12);
6529 GEN_VXFORM(vsrah, 2, 13);
6530 GEN_VXFORM(vsraw, 2, 14);
6531 GEN_VXFORM(vslo, 6, 16);
6532 GEN_VXFORM(vsro, 6, 17);
6533 GEN_VXFORM(vaddcuw, 0, 6);
6534 GEN_VXFORM(vsubcuw, 0, 22);
6535 GEN_VXFORM(vaddubs, 0, 8);
6536 GEN_VXFORM(vadduhs, 0, 9);
6537 GEN_VXFORM(vadduws, 0, 10);
6538 GEN_VXFORM(vaddsbs, 0, 12);
6539 GEN_VXFORM(vaddshs, 0, 13);
6540 GEN_VXFORM(vaddsws, 0, 14);
6541 GEN_VXFORM(vsububs, 0, 24);
6542 GEN_VXFORM(vsubuhs, 0, 25);
6543 GEN_VXFORM(vsubuws, 0, 26);
6544 GEN_VXFORM(vsubsbs, 0, 28);
6545 GEN_VXFORM(vsubshs, 0, 29);
6546 GEN_VXFORM(vsubsws, 0, 30);
6547 GEN_VXFORM(vrlb, 2, 0);
6548 GEN_VXFORM(vrlh, 2, 1);
6549 GEN_VXFORM(vrlw, 2, 2);
6550 GEN_VXFORM(vsl, 2, 7);
6551 GEN_VXFORM(vsr, 2, 11);
6552 GEN_VXFORM(vpkuhum, 7, 0);
6553 GEN_VXFORM(vpkuwum, 7, 1);
6554 GEN_VXFORM(vpkuhus, 7, 2);
6555 GEN_VXFORM(vpkuwus, 7, 3);
6556 GEN_VXFORM(vpkshus, 7, 4);
6557 GEN_VXFORM(vpkswus, 7, 5);
6558 GEN_VXFORM(vpkshss, 7, 6);
6559 GEN_VXFORM(vpkswss, 7, 7);
6560 GEN_VXFORM(vpkpx, 7, 12);
6561 GEN_VXFORM(vsum4ubs, 4, 24);
6562 GEN_VXFORM(vsum4sbs, 4, 28);
6563 GEN_VXFORM(vsum4shs, 4, 25);
6564 GEN_VXFORM(vsum2sws, 4, 26);
6565 GEN_VXFORM(vsumsws, 4, 30);
6566 GEN_VXFORM(vaddfp, 5, 0);
6567 GEN_VXFORM(vsubfp, 5, 1);
6568 GEN_VXFORM(vmaxfp, 5, 16);
6569 GEN_VXFORM(vminfp, 5, 17);
6570
6571 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6572 static void glue(gen_, name)(DisasContext *ctx) \
6573 { \
6574 TCGv_ptr ra, rb, rd; \
6575 if (unlikely(!ctx->altivec_enabled)) { \
6576 gen_exception(ctx, POWERPC_EXCP_VPU); \
6577 return; \
6578 } \
6579 ra = gen_avr_ptr(rA(ctx->opcode)); \
6580 rb = gen_avr_ptr(rB(ctx->opcode)); \
6581 rd = gen_avr_ptr(rD(ctx->opcode)); \
6582 gen_helper_##opname (rd, ra, rb); \
6583 tcg_temp_free_ptr(ra); \
6584 tcg_temp_free_ptr(rb); \
6585 tcg_temp_free_ptr(rd); \
6586 }
6587
6588 #define GEN_VXRFORM(name, opc2, opc3) \
6589 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6590 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6591
6592 GEN_VXRFORM(vcmpequb, 3, 0)
6593 GEN_VXRFORM(vcmpequh, 3, 1)
6594 GEN_VXRFORM(vcmpequw, 3, 2)
6595 GEN_VXRFORM(vcmpgtsb, 3, 12)
6596 GEN_VXRFORM(vcmpgtsh, 3, 13)
6597 GEN_VXRFORM(vcmpgtsw, 3, 14)
6598 GEN_VXRFORM(vcmpgtub, 3, 8)
6599 GEN_VXRFORM(vcmpgtuh, 3, 9)
6600 GEN_VXRFORM(vcmpgtuw, 3, 10)
6601 GEN_VXRFORM(vcmpeqfp, 3, 3)
6602 GEN_VXRFORM(vcmpgefp, 3, 7)
6603 GEN_VXRFORM(vcmpgtfp, 3, 11)
6604 GEN_VXRFORM(vcmpbfp, 3, 15)
6605
6606 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6607 static void glue(gen_, name)(DisasContext *ctx) \
6608 { \
6609 TCGv_ptr rd; \
6610 TCGv_i32 simm; \
6611 if (unlikely(!ctx->altivec_enabled)) { \
6612 gen_exception(ctx, POWERPC_EXCP_VPU); \
6613 return; \
6614 } \
6615 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6616 rd = gen_avr_ptr(rD(ctx->opcode)); \
6617 gen_helper_##name (rd, simm); \
6618 tcg_temp_free_i32(simm); \
6619 tcg_temp_free_ptr(rd); \
6620 }
6621
6622 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6623 GEN_VXFORM_SIMM(vspltish, 6, 13);
6624 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6625
6626 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6627 static void glue(gen_, name)(DisasContext *ctx) \
6628 { \
6629 TCGv_ptr rb, rd; \
6630 if (unlikely(!ctx->altivec_enabled)) { \
6631 gen_exception(ctx, POWERPC_EXCP_VPU); \
6632 return; \
6633 } \
6634 rb = gen_avr_ptr(rB(ctx->opcode)); \
6635 rd = gen_avr_ptr(rD(ctx->opcode)); \
6636 gen_helper_##name (rd, rb); \
6637 tcg_temp_free_ptr(rb); \
6638 tcg_temp_free_ptr(rd); \
6639 }
6640
6641 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6642 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6643 GEN_VXFORM_NOA(vupklsb, 7, 10);
6644 GEN_VXFORM_NOA(vupklsh, 7, 11);
6645 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6646 GEN_VXFORM_NOA(vupklpx, 7, 15);
6647 GEN_VXFORM_NOA(vrefp, 5, 4);
6648 GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
6649 GEN_VXFORM_NOA(vexptefp, 5, 6);
6650 GEN_VXFORM_NOA(vlogefp, 5, 7);
6651 GEN_VXFORM_NOA(vrfim, 5, 8);
6652 GEN_VXFORM_NOA(vrfin, 5, 9);
6653 GEN_VXFORM_NOA(vrfip, 5, 10);
6654 GEN_VXFORM_NOA(vrfiz, 5, 11);
6655
6656 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6657 static void glue(gen_, name)(DisasContext *ctx) \
6658 { \
6659 TCGv_ptr rd; \
6660 TCGv_i32 simm; \
6661 if (unlikely(!ctx->altivec_enabled)) { \
6662 gen_exception(ctx, POWERPC_EXCP_VPU); \
6663 return; \
6664 } \
6665 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6666 rd = gen_avr_ptr(rD(ctx->opcode)); \
6667 gen_helper_##name (rd, simm); \
6668 tcg_temp_free_i32(simm); \
6669 tcg_temp_free_ptr(rd); \
6670 }
6671
6672 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6673 static void glue(gen_, name)(DisasContext *ctx) \
6674 { \
6675 TCGv_ptr rb, rd; \
6676 TCGv_i32 uimm; \
6677 if (unlikely(!ctx->altivec_enabled)) { \
6678 gen_exception(ctx, POWERPC_EXCP_VPU); \
6679 return; \
6680 } \
6681 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6682 rb = gen_avr_ptr(rB(ctx->opcode)); \
6683 rd = gen_avr_ptr(rD(ctx->opcode)); \
6684 gen_helper_##name (rd, rb, uimm); \
6685 tcg_temp_free_i32(uimm); \
6686 tcg_temp_free_ptr(rb); \
6687 tcg_temp_free_ptr(rd); \
6688 }
6689
6690 GEN_VXFORM_UIMM(vspltb, 6, 8);
6691 GEN_VXFORM_UIMM(vsplth, 6, 9);
6692 GEN_VXFORM_UIMM(vspltw, 6, 10);
6693 GEN_VXFORM_UIMM(vcfux, 5, 12);
6694 GEN_VXFORM_UIMM(vcfsx, 5, 13);
6695 GEN_VXFORM_UIMM(vctuxs, 5, 14);
6696 GEN_VXFORM_UIMM(vctsxs, 5, 15);
6697
6698 static void gen_vsldoi(DisasContext *ctx)
6699 {
6700 TCGv_ptr ra, rb, rd;
6701 TCGv_i32 sh;
6702 if (unlikely(!ctx->altivec_enabled)) {
6703 gen_exception(ctx, POWERPC_EXCP_VPU);
6704 return;
6705 }
6706 ra = gen_avr_ptr(rA(ctx->opcode));
6707 rb = gen_avr_ptr(rB(ctx->opcode));
6708 rd = gen_avr_ptr(rD(ctx->opcode));
6709 sh = tcg_const_i32(VSH(ctx->opcode));
6710 gen_helper_vsldoi (rd, ra, rb, sh);
6711 tcg_temp_free_ptr(ra);
6712 tcg_temp_free_ptr(rb);
6713 tcg_temp_free_ptr(rd);
6714 tcg_temp_free_i32(sh);
6715 }
6716
6717 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6718 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6719 { \
6720 TCGv_ptr ra, rb, rc, rd; \
6721 if (unlikely(!ctx->altivec_enabled)) { \
6722 gen_exception(ctx, POWERPC_EXCP_VPU); \
6723 return; \
6724 } \
6725 ra = gen_avr_ptr(rA(ctx->opcode)); \
6726 rb = gen_avr_ptr(rB(ctx->opcode)); \
6727 rc = gen_avr_ptr(rC(ctx->opcode)); \
6728 rd = gen_avr_ptr(rD(ctx->opcode)); \
6729 if (Rc(ctx->opcode)) { \
6730 gen_helper_##name1 (rd, ra, rb, rc); \
6731 } else { \
6732 gen_helper_##name0 (rd, ra, rb, rc); \
6733 } \
6734 tcg_temp_free_ptr(ra); \
6735 tcg_temp_free_ptr(rb); \
6736 tcg_temp_free_ptr(rc); \
6737 tcg_temp_free_ptr(rd); \
6738 }
6739
6740 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6741
6742 static void gen_vmladduhm(DisasContext *ctx)
6743 {
6744 TCGv_ptr ra, rb, rc, rd;
6745 if (unlikely(!ctx->altivec_enabled)) {
6746 gen_exception(ctx, POWERPC_EXCP_VPU);
6747 return;
6748 }
6749 ra = gen_avr_ptr(rA(ctx->opcode));
6750 rb = gen_avr_ptr(rB(ctx->opcode));
6751 rc = gen_avr_ptr(rC(ctx->opcode));
6752 rd = gen_avr_ptr(rD(ctx->opcode));
6753 gen_helper_vmladduhm(rd, ra, rb, rc);
6754 tcg_temp_free_ptr(ra);
6755 tcg_temp_free_ptr(rb);
6756 tcg_temp_free_ptr(rc);
6757 tcg_temp_free_ptr(rd);
6758 }
6759
6760 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6761 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6762 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6763 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6764 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6765
6766 /*** SPE extension ***/
6767 /* Register moves */
6768
6769
6770 static inline void gen_evmra(DisasContext *ctx)
6771 {
6772
6773 if (unlikely(!ctx->spe_enabled)) {
6774 gen_exception(ctx, POWERPC_EXCP_SPEU);
6775 return;
6776 }
6777
6778 #if defined(TARGET_PPC64)
6779 /* rD := rA */
6780 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6781
6782 /* spe_acc := rA */
6783 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6784 cpu_env,
6785 offsetof(CPUPPCState, spe_acc));
6786 #else
6787 TCGv_i64 tmp = tcg_temp_new_i64();
6788
6789 /* tmp := rA_lo + rA_hi << 32 */
6790 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6791
6792 /* spe_acc := tmp */
6793 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6794 tcg_temp_free_i64(tmp);
6795
6796 /* rD := rA */
6797 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6798 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6799 #endif
6800 }
6801
6802 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6803 {
6804 #if defined(TARGET_PPC64)
6805 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6806 #else
6807 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6808 #endif
6809 }
6810
6811 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6812 {
6813 #if defined(TARGET_PPC64)
6814 tcg_gen_mov_i64(cpu_gpr[reg], t);
6815 #else
6816 TCGv_i64 tmp = tcg_temp_new_i64();
6817 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6818 tcg_gen_shri_i64(tmp, t, 32);
6819 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6820 tcg_temp_free_i64(tmp);
6821 #endif
6822 }
6823
6824 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6825 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6826 { \
6827 if (Rc(ctx->opcode)) \
6828 gen_##name1(ctx); \
6829 else \
6830 gen_##name0(ctx); \
6831 }
6832
6833 /* Handler for undefined SPE opcodes */
6834 static inline void gen_speundef(DisasContext *ctx)
6835 {
6836 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6837 }
6838
6839 /* SPE logic */
6840 #if defined(TARGET_PPC64)
6841 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6842 static inline void gen_##name(DisasContext *ctx) \
6843 { \
6844 if (unlikely(!ctx->spe_enabled)) { \
6845 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6846 return; \
6847 } \
6848 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6849 cpu_gpr[rB(ctx->opcode)]); \
6850 }
6851 #else
6852 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6853 static inline void gen_##name(DisasContext *ctx) \
6854 { \
6855 if (unlikely(!ctx->spe_enabled)) { \
6856 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6857 return; \
6858 } \
6859 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6860 cpu_gpr[rB(ctx->opcode)]); \
6861 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6862 cpu_gprh[rB(ctx->opcode)]); \
6863 }
6864 #endif
6865
6866 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6867 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6868 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6869 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6870 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6871 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6872 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6873 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6874
6875 /* SPE logic immediate */
6876 #if defined(TARGET_PPC64)
6877 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6878 static inline void gen_##name(DisasContext *ctx) \
6879 { \
6880 if (unlikely(!ctx->spe_enabled)) { \
6881 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6882 return; \
6883 } \
6884 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6885 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6886 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6887 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6888 tcg_opi(t0, t0, rB(ctx->opcode)); \
6889 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6890 tcg_gen_trunc_i64_i32(t1, t2); \
6891 tcg_temp_free_i64(t2); \
6892 tcg_opi(t1, t1, rB(ctx->opcode)); \
6893 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6894 tcg_temp_free_i32(t0); \
6895 tcg_temp_free_i32(t1); \
6896 }
6897 #else
6898 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6899 static inline void gen_##name(DisasContext *ctx) \
6900 { \
6901 if (unlikely(!ctx->spe_enabled)) { \
6902 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6903 return; \
6904 } \
6905 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6906 rB(ctx->opcode)); \
6907 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6908 rB(ctx->opcode)); \
6909 }
6910 #endif
6911 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6912 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6913 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6914 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6915
6916 /* SPE arithmetic */
6917 #if defined(TARGET_PPC64)
6918 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6919 static inline void gen_##name(DisasContext *ctx) \
6920 { \
6921 if (unlikely(!ctx->spe_enabled)) { \
6922 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6923 return; \
6924 } \
6925 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6926 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6927 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6928 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6929 tcg_op(t0, t0); \
6930 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6931 tcg_gen_trunc_i64_i32(t1, t2); \
6932 tcg_temp_free_i64(t2); \
6933 tcg_op(t1, t1); \
6934 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6935 tcg_temp_free_i32(t0); \
6936 tcg_temp_free_i32(t1); \
6937 }
6938 #else
6939 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6940 static inline void gen_##name(DisasContext *ctx) \
6941 { \
6942 if (unlikely(!ctx->spe_enabled)) { \
6943 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6944 return; \
6945 } \
6946 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6947 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6948 }
6949 #endif
6950
6951 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
6952 {
6953 int l1 = gen_new_label();
6954 int l2 = gen_new_label();
6955
6956 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6957 tcg_gen_neg_i32(ret, arg1);
6958 tcg_gen_br(l2);
6959 gen_set_label(l1);
6960 tcg_gen_mov_i32(ret, arg1);
6961 gen_set_label(l2);
6962 }
6963 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6964 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6965 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6966 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6967 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
6968 {
6969 tcg_gen_addi_i32(ret, arg1, 0x8000);
6970 tcg_gen_ext16u_i32(ret, ret);
6971 }
6972 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6973 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6974 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6975
6976 #if defined(TARGET_PPC64)
6977 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6978 static inline void gen_##name(DisasContext *ctx) \
6979 { \
6980 if (unlikely(!ctx->spe_enabled)) { \
6981 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6982 return; \
6983 } \
6984 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6985 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6986 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6987 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6988 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6989 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6990 tcg_op(t0, t0, t2); \
6991 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6992 tcg_gen_trunc_i64_i32(t1, t3); \
6993 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6994 tcg_gen_trunc_i64_i32(t2, t3); \
6995 tcg_temp_free_i64(t3); \
6996 tcg_op(t1, t1, t2); \
6997 tcg_temp_free_i32(t2); \
6998 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6999 tcg_temp_free_i32(t0); \
7000 tcg_temp_free_i32(t1); \
7001 }
7002 #else
7003 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7004 static inline void gen_##name(DisasContext *ctx) \
7005 { \
7006 if (unlikely(!ctx->spe_enabled)) { \
7007 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7008 return; \
7009 } \
7010 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7011 cpu_gpr[rB(ctx->opcode)]); \
7012 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7013 cpu_gprh[rB(ctx->opcode)]); \
7014 }
7015 #endif
7016
7017 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7018 {
7019 TCGv_i32 t0;
7020 int l1, l2;
7021
7022 l1 = gen_new_label();
7023 l2 = gen_new_label();
7024 t0 = tcg_temp_local_new_i32();
7025 /* No error here: 6 bits are used */
7026 tcg_gen_andi_i32(t0, arg2, 0x3F);
7027 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7028 tcg_gen_shr_i32(ret, arg1, t0);
7029 tcg_gen_br(l2);
7030 gen_set_label(l1);
7031 tcg_gen_movi_i32(ret, 0);
7032 gen_set_label(l2);
7033 tcg_temp_free_i32(t0);
7034 }
7035 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7036 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7037 {
7038 TCGv_i32 t0;
7039 int l1, l2;
7040
7041 l1 = gen_new_label();
7042 l2 = gen_new_label();
7043 t0 = tcg_temp_local_new_i32();
7044 /* No error here: 6 bits are used */
7045 tcg_gen_andi_i32(t0, arg2, 0x3F);
7046 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7047 tcg_gen_sar_i32(ret, arg1, t0);
7048 tcg_gen_br(l2);
7049 gen_set_label(l1);
7050 tcg_gen_movi_i32(ret, 0);
7051 gen_set_label(l2);
7052 tcg_temp_free_i32(t0);
7053 }
7054 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7055 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7056 {
7057 TCGv_i32 t0;
7058 int l1, l2;
7059
7060 l1 = gen_new_label();
7061 l2 = gen_new_label();
7062 t0 = tcg_temp_local_new_i32();
7063 /* No error here: 6 bits are used */
7064 tcg_gen_andi_i32(t0, arg2, 0x3F);
7065 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7066 tcg_gen_shl_i32(ret, arg1, t0);
7067 tcg_gen_br(l2);
7068 gen_set_label(l1);
7069 tcg_gen_movi_i32(ret, 0);
7070 gen_set_label(l2);
7071 tcg_temp_free_i32(t0);
7072 }
7073 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7074 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7075 {
7076 TCGv_i32 t0 = tcg_temp_new_i32();
7077 tcg_gen_andi_i32(t0, arg2, 0x1F);
7078 tcg_gen_rotl_i32(ret, arg1, t0);
7079 tcg_temp_free_i32(t0);
7080 }
7081 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7082 static inline void gen_evmergehi(DisasContext *ctx)
7083 {
7084 if (unlikely(!ctx->spe_enabled)) {
7085 gen_exception(ctx, POWERPC_EXCP_SPEU);
7086 return;
7087 }
7088 #if defined(TARGET_PPC64)
7089 TCGv t0 = tcg_temp_new();
7090 TCGv t1 = tcg_temp_new();
7091 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7092 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7093 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7094 tcg_temp_free(t0);
7095 tcg_temp_free(t1);
7096 #else
7097 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7098 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7099 #endif
7100 }
7101 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7102 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7103 {
7104 tcg_gen_sub_i32(ret, arg2, arg1);
7105 }
7106 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7107
7108 /* SPE arithmetic immediate */
7109 #if defined(TARGET_PPC64)
7110 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7111 static inline void gen_##name(DisasContext *ctx) \
7112 { \
7113 if (unlikely(!ctx->spe_enabled)) { \
7114 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7115 return; \
7116 } \
7117 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7118 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7119 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7120 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7121 tcg_op(t0, t0, rA(ctx->opcode)); \
7122 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7123 tcg_gen_trunc_i64_i32(t1, t2); \
7124 tcg_temp_free_i64(t2); \
7125 tcg_op(t1, t1, rA(ctx->opcode)); \
7126 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7127 tcg_temp_free_i32(t0); \
7128 tcg_temp_free_i32(t1); \
7129 }
7130 #else
7131 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7132 static inline void gen_##name(DisasContext *ctx) \
7133 { \
7134 if (unlikely(!ctx->spe_enabled)) { \
7135 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7136 return; \
7137 } \
7138 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7139 rA(ctx->opcode)); \
7140 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7141 rA(ctx->opcode)); \
7142 }
7143 #endif
7144 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7145 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7146
7147 /* SPE comparison */
7148 #if defined(TARGET_PPC64)
7149 #define GEN_SPEOP_COMP(name, tcg_cond) \
7150 static inline void gen_##name(DisasContext *ctx) \
7151 { \
7152 if (unlikely(!ctx->spe_enabled)) { \
7153 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7154 return; \
7155 } \
7156 int l1 = gen_new_label(); \
7157 int l2 = gen_new_label(); \
7158 int l3 = gen_new_label(); \
7159 int l4 = gen_new_label(); \
7160 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7161 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7162 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7163 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7164 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7165 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7166 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7167 tcg_gen_br(l2); \
7168 gen_set_label(l1); \
7169 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7170 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7171 gen_set_label(l2); \
7172 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7173 tcg_gen_trunc_i64_i32(t0, t2); \
7174 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7175 tcg_gen_trunc_i64_i32(t1, t2); \
7176 tcg_temp_free_i64(t2); \
7177 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7178 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7179 ~(CRF_CH | CRF_CH_AND_CL)); \
7180 tcg_gen_br(l4); \
7181 gen_set_label(l3); \
7182 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7183 CRF_CH | CRF_CH_OR_CL); \
7184 gen_set_label(l4); \
7185 tcg_temp_free_i32(t0); \
7186 tcg_temp_free_i32(t1); \
7187 }
7188 #else
7189 #define GEN_SPEOP_COMP(name, tcg_cond) \
7190 static inline void gen_##name(DisasContext *ctx) \
7191 { \
7192 if (unlikely(!ctx->spe_enabled)) { \
7193 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7194 return; \
7195 } \
7196 int l1 = gen_new_label(); \
7197 int l2 = gen_new_label(); \
7198 int l3 = gen_new_label(); \
7199 int l4 = gen_new_label(); \
7200 \
7201 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7202 cpu_gpr[rB(ctx->opcode)], l1); \
7203 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7204 tcg_gen_br(l2); \
7205 gen_set_label(l1); \
7206 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7207 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7208 gen_set_label(l2); \
7209 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7210 cpu_gprh[rB(ctx->opcode)], l3); \
7211 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7212 ~(CRF_CH | CRF_CH_AND_CL)); \
7213 tcg_gen_br(l4); \
7214 gen_set_label(l3); \
7215 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7216 CRF_CH | CRF_CH_OR_CL); \
7217 gen_set_label(l4); \
7218 }
7219 #endif
7220 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7221 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7222 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7223 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7224 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7225
7226 /* SPE misc */
7227 static inline void gen_brinc(DisasContext *ctx)
7228 {
7229 /* Note: brinc is usable even if SPE is disabled */
7230 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7231 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7232 }
7233 static inline void gen_evmergelo(DisasContext *ctx)
7234 {
7235 if (unlikely(!ctx->spe_enabled)) {
7236 gen_exception(ctx, POWERPC_EXCP_SPEU);
7237 return;
7238 }
7239 #if defined(TARGET_PPC64)
7240 TCGv t0 = tcg_temp_new();
7241 TCGv t1 = tcg_temp_new();
7242 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7243 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7244 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7245 tcg_temp_free(t0);
7246 tcg_temp_free(t1);
7247 #else
7248 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7249 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7250 #endif
7251 }
7252 static inline void gen_evmergehilo(DisasContext *ctx)
7253 {
7254 if (unlikely(!ctx->spe_enabled)) {
7255 gen_exception(ctx, POWERPC_EXCP_SPEU);
7256 return;
7257 }
7258 #if defined(TARGET_PPC64)
7259 TCGv t0 = tcg_temp_new();
7260 TCGv t1 = tcg_temp_new();
7261 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7262 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7263 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7264 tcg_temp_free(t0);
7265 tcg_temp_free(t1);
7266 #else
7267 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7268 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7269 #endif
7270 }
7271 static inline void gen_evmergelohi(DisasContext *ctx)
7272 {
7273 if (unlikely(!ctx->spe_enabled)) {
7274 gen_exception(ctx, POWERPC_EXCP_SPEU);
7275 return;
7276 }
7277 #if defined(TARGET_PPC64)
7278 TCGv t0 = tcg_temp_new();
7279 TCGv t1 = tcg_temp_new();
7280 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7281 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7282 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7283 tcg_temp_free(t0);
7284 tcg_temp_free(t1);
7285 #else
7286 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7287 TCGv_i32 tmp = tcg_temp_new_i32();
7288 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7289 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7290 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7291 tcg_temp_free_i32(tmp);
7292 } else {
7293 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7294 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7295 }
7296 #endif
7297 }
7298 static inline void gen_evsplati(DisasContext *ctx)
7299 {
7300 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7301
7302 #if defined(TARGET_PPC64)
7303 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7304 #else
7305 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7306 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7307 #endif
7308 }
7309 static inline void gen_evsplatfi(DisasContext *ctx)
7310 {
7311 uint64_t imm = rA(ctx->opcode) << 27;
7312
7313 #if defined(TARGET_PPC64)
7314 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7315 #else
7316 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7317 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7318 #endif
7319 }
7320
7321 static inline void gen_evsel(DisasContext *ctx)
7322 {
7323 int l1 = gen_new_label();
7324 int l2 = gen_new_label();
7325 int l3 = gen_new_label();
7326 int l4 = gen_new_label();
7327 TCGv_i32 t0 = tcg_temp_local_new_i32();
7328 #if defined(TARGET_PPC64)
7329 TCGv t1 = tcg_temp_local_new();
7330 TCGv t2 = tcg_temp_local_new();
7331 #endif
7332 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7333 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7334 #if defined(TARGET_PPC64)
7335 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7336 #else
7337 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7338 #endif
7339 tcg_gen_br(l2);
7340 gen_set_label(l1);
7341 #if defined(TARGET_PPC64)
7342 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7343 #else
7344 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7345 #endif
7346 gen_set_label(l2);
7347 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7348 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7349 #if defined(TARGET_PPC64)
7350 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7351 #else
7352 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7353 #endif
7354 tcg_gen_br(l4);
7355 gen_set_label(l3);
7356 #if defined(TARGET_PPC64)
7357 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7358 #else
7359 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7360 #endif
7361 gen_set_label(l4);
7362 tcg_temp_free_i32(t0);
7363 #if defined(TARGET_PPC64)
7364 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7365 tcg_temp_free(t1);
7366 tcg_temp_free(t2);
7367 #endif
7368 }
7369
7370 static void gen_evsel0(DisasContext *ctx)
7371 {
7372 gen_evsel(ctx);
7373 }
7374
7375 static void gen_evsel1(DisasContext *ctx)
7376 {
7377 gen_evsel(ctx);
7378 }
7379
7380 static void gen_evsel2(DisasContext *ctx)
7381 {
7382 gen_evsel(ctx);
7383 }
7384
7385 static void gen_evsel3(DisasContext *ctx)
7386 {
7387 gen_evsel(ctx);
7388 }
7389
7390 /* Multiply */
7391
7392 static inline void gen_evmwumi(DisasContext *ctx)
7393 {
7394 TCGv_i64 t0, t1;
7395
7396 if (unlikely(!ctx->spe_enabled)) {
7397 gen_exception(ctx, POWERPC_EXCP_SPEU);
7398 return;
7399 }
7400
7401 t0 = tcg_temp_new_i64();
7402 t1 = tcg_temp_new_i64();
7403
7404 /* t0 := rA; t1 := rB */
7405 #if defined(TARGET_PPC64)
7406 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7407 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7408 #else
7409 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7410 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7411 #endif
7412
7413 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7414
7415 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7416
7417 tcg_temp_free_i64(t0);
7418 tcg_temp_free_i64(t1);
7419 }
7420
7421 static inline void gen_evmwumia(DisasContext *ctx)
7422 {
7423 TCGv_i64 tmp;
7424
7425 if (unlikely(!ctx->spe_enabled)) {
7426 gen_exception(ctx, POWERPC_EXCP_SPEU);
7427 return;
7428 }
7429
7430 gen_evmwumi(ctx); /* rD := rA * rB */
7431
7432 tmp = tcg_temp_new_i64();
7433
7434 /* acc := rD */
7435 gen_load_gpr64(tmp, rD(ctx->opcode));
7436 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7437 tcg_temp_free_i64(tmp);
7438 }
7439
7440 static inline void gen_evmwumiaa(DisasContext *ctx)
7441 {
7442 TCGv_i64 acc;
7443 TCGv_i64 tmp;
7444
7445 if (unlikely(!ctx->spe_enabled)) {
7446 gen_exception(ctx, POWERPC_EXCP_SPEU);
7447 return;
7448 }
7449
7450 gen_evmwumi(ctx); /* rD := rA * rB */
7451
7452 acc = tcg_temp_new_i64();
7453 tmp = tcg_temp_new_i64();
7454
7455 /* tmp := rD */
7456 gen_load_gpr64(tmp, rD(ctx->opcode));
7457
7458 /* Load acc */
7459 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7460
7461 /* acc := tmp + acc */
7462 tcg_gen_add_i64(acc, acc, tmp);
7463
7464 /* Store acc */
7465 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7466
7467 /* rD := acc */
7468 gen_store_gpr64(rD(ctx->opcode), acc);
7469
7470 tcg_temp_free_i64(acc);
7471 tcg_temp_free_i64(tmp);
7472 }
7473
7474 static inline void gen_evmwsmi(DisasContext *ctx)
7475 {
7476 TCGv_i64 t0, t1;
7477
7478 if (unlikely(!ctx->spe_enabled)) {
7479 gen_exception(ctx, POWERPC_EXCP_SPEU);
7480 return;
7481 }
7482
7483 t0 = tcg_temp_new_i64();
7484 t1 = tcg_temp_new_i64();
7485
7486 /* t0 := rA; t1 := rB */
7487 #if defined(TARGET_PPC64)
7488 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7489 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7490 #else
7491 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7492 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7493 #endif
7494
7495 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7496
7497 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7498
7499 tcg_temp_free_i64(t0);
7500 tcg_temp_free_i64(t1);
7501 }
7502
7503 static inline void gen_evmwsmia(DisasContext *ctx)
7504 {
7505 TCGv_i64 tmp;
7506
7507 gen_evmwsmi(ctx); /* rD := rA * rB */
7508
7509 tmp = tcg_temp_new_i64();
7510
7511 /* acc := rD */
7512 gen_load_gpr64(tmp, rD(ctx->opcode));
7513 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7514
7515 tcg_temp_free_i64(tmp);
7516 }
7517
7518 static inline void gen_evmwsmiaa(DisasContext *ctx)
7519 {
7520 TCGv_i64 acc = tcg_temp_new_i64();
7521 TCGv_i64 tmp = tcg_temp_new_i64();
7522
7523 gen_evmwsmi(ctx); /* rD := rA * rB */
7524
7525 acc = tcg_temp_new_i64();
7526 tmp = tcg_temp_new_i64();
7527
7528 /* tmp := rD */
7529 gen_load_gpr64(tmp, rD(ctx->opcode));
7530
7531 /* Load acc */
7532 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7533
7534 /* acc := tmp + acc */
7535 tcg_gen_add_i64(acc, acc, tmp);
7536
7537 /* Store acc */
7538 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7539
7540 /* rD := acc */
7541 gen_store_gpr64(rD(ctx->opcode), acc);
7542
7543 tcg_temp_free_i64(acc);
7544 tcg_temp_free_i64(tmp);
7545 }
7546
7547 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7548 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7549 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7550 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7551 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7552 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7553 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7554 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7555 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7556 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7557 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7558 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7559 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7560 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7561 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7562 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7563 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7564 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7565 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7566 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7567 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7568 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7569 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7570 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7571 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7572 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7573 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7574 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7575 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7576
7577 /* SPE load and stores */
7578 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7579 {
7580 target_ulong uimm = rB(ctx->opcode);
7581
7582 if (rA(ctx->opcode) == 0) {
7583 tcg_gen_movi_tl(EA, uimm << sh);
7584 } else {
7585 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7586 #if defined(TARGET_PPC64)
7587 if (!ctx->sf_mode) {
7588 tcg_gen_ext32u_tl(EA, EA);
7589 }
7590 #endif
7591 }
7592 }
7593
7594 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7595 {
7596 #if defined(TARGET_PPC64)
7597 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7598 #else
7599 TCGv_i64 t0 = tcg_temp_new_i64();
7600 gen_qemu_ld64(ctx, t0, addr);
7601 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7602 tcg_gen_shri_i64(t0, t0, 32);
7603 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7604 tcg_temp_free_i64(t0);
7605 #endif
7606 }
7607
7608 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7609 {
7610 #if defined(TARGET_PPC64)
7611 TCGv t0 = tcg_temp_new();
7612 gen_qemu_ld32u(ctx, t0, addr);
7613 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7614 gen_addr_add(ctx, addr, addr, 4);
7615 gen_qemu_ld32u(ctx, t0, addr);
7616 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7617 tcg_temp_free(t0);
7618 #else
7619 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7620 gen_addr_add(ctx, addr, addr, 4);
7621 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7622 #endif
7623 }
7624
7625 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7626 {
7627 TCGv t0 = tcg_temp_new();
7628 #if defined(TARGET_PPC64)
7629 gen_qemu_ld16u(ctx, t0, addr);
7630 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7631 gen_addr_add(ctx, addr, addr, 2);
7632 gen_qemu_ld16u(ctx, t0, addr);
7633 tcg_gen_shli_tl(t0, t0, 32);
7634 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7635 gen_addr_add(ctx, addr, addr, 2);
7636 gen_qemu_ld16u(ctx, t0, addr);
7637 tcg_gen_shli_tl(t0, t0, 16);
7638 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7639 gen_addr_add(ctx, addr, addr, 2);
7640 gen_qemu_ld16u(ctx, t0, addr);
7641 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7642 #else
7643 gen_qemu_ld16u(ctx, t0, addr);
7644 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7645 gen_addr_add(ctx, addr, addr, 2);
7646 gen_qemu_ld16u(ctx, t0, addr);
7647 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7648 gen_addr_add(ctx, addr, addr, 2);
7649 gen_qemu_ld16u(ctx, t0, addr);
7650 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7651 gen_addr_add(ctx, addr, addr, 2);
7652 gen_qemu_ld16u(ctx, t0, addr);
7653 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7654 #endif
7655 tcg_temp_free(t0);
7656 }
7657
7658 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7659 {
7660 TCGv t0 = tcg_temp_new();
7661 gen_qemu_ld16u(ctx, t0, addr);
7662 #if defined(TARGET_PPC64)
7663 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7664 tcg_gen_shli_tl(t0, t0, 16);
7665 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7666 #else
7667 tcg_gen_shli_tl(t0, t0, 16);
7668 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7669 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7670 #endif
7671 tcg_temp_free(t0);
7672 }
7673
7674 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7675 {
7676 TCGv t0 = tcg_temp_new();
7677 gen_qemu_ld16u(ctx, t0, addr);
7678 #if defined(TARGET_PPC64)
7679 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7680 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7681 #else
7682 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7683 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7684 #endif
7685 tcg_temp_free(t0);
7686 }
7687
7688 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7689 {
7690 TCGv t0 = tcg_temp_new();
7691 gen_qemu_ld16s(ctx, t0, addr);
7692 #if defined(TARGET_PPC64)
7693 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7694 tcg_gen_ext32u_tl(t0, t0);
7695 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7696 #else
7697 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7698 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7699 #endif
7700 tcg_temp_free(t0);
7701 }
7702
7703 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7704 {
7705 TCGv t0 = tcg_temp_new();
7706 #if defined(TARGET_PPC64)
7707 gen_qemu_ld16u(ctx, t0, addr);
7708 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7709 gen_addr_add(ctx, addr, addr, 2);
7710 gen_qemu_ld16u(ctx, t0, addr);
7711 tcg_gen_shli_tl(t0, t0, 16);
7712 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7713 #else
7714 gen_qemu_ld16u(ctx, t0, addr);
7715 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7716 gen_addr_add(ctx, addr, addr, 2);
7717 gen_qemu_ld16u(ctx, t0, addr);
7718 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7719 #endif
7720 tcg_temp_free(t0);
7721 }
7722
7723 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7724 {
7725 #if defined(TARGET_PPC64)
7726 TCGv t0 = tcg_temp_new();
7727 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7728 gen_addr_add(ctx, addr, addr, 2);
7729 gen_qemu_ld16u(ctx, t0, addr);
7730 tcg_gen_shli_tl(t0, t0, 32);
7731 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7732 tcg_temp_free(t0);
7733 #else
7734 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7735 gen_addr_add(ctx, addr, addr, 2);
7736 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7737 #endif
7738 }
7739
7740 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7741 {
7742 #if defined(TARGET_PPC64)
7743 TCGv t0 = tcg_temp_new();
7744 gen_qemu_ld16s(ctx, t0, addr);
7745 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7746 gen_addr_add(ctx, addr, addr, 2);
7747 gen_qemu_ld16s(ctx, t0, addr);
7748 tcg_gen_shli_tl(t0, t0, 32);
7749 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7750 tcg_temp_free(t0);
7751 #else
7752 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7753 gen_addr_add(ctx, addr, addr, 2);
7754 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7755 #endif
7756 }
7757
7758 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7759 {
7760 TCGv t0 = tcg_temp_new();
7761 gen_qemu_ld32u(ctx, t0, addr);
7762 #if defined(TARGET_PPC64)
7763 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7764 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7765 #else
7766 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7767 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7768 #endif
7769 tcg_temp_free(t0);
7770 }
7771
7772 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7773 {
7774 TCGv t0 = tcg_temp_new();
7775 #if defined(TARGET_PPC64)
7776 gen_qemu_ld16u(ctx, t0, addr);
7777 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7778 tcg_gen_shli_tl(t0, t0, 32);
7779 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7780 gen_addr_add(ctx, addr, addr, 2);
7781 gen_qemu_ld16u(ctx, t0, addr);
7782 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7783 tcg_gen_shli_tl(t0, t0, 16);
7784 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7785 #else
7786 gen_qemu_ld16u(ctx, t0, addr);
7787 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7788 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7789 gen_addr_add(ctx, addr, addr, 2);
7790 gen_qemu_ld16u(ctx, t0, addr);
7791 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7792 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7793 #endif
7794 tcg_temp_free(t0);
7795 }
7796
7797 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7798 {
7799 #if defined(TARGET_PPC64)
7800 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7801 #else
7802 TCGv_i64 t0 = tcg_temp_new_i64();
7803 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7804 gen_qemu_st64(ctx, t0, addr);
7805 tcg_temp_free_i64(t0);
7806 #endif
7807 }
7808
7809 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7810 {
7811 #if defined(TARGET_PPC64)
7812 TCGv t0 = tcg_temp_new();
7813 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7814 gen_qemu_st32(ctx, t0, addr);
7815 tcg_temp_free(t0);
7816 #else
7817 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7818 #endif
7819 gen_addr_add(ctx, addr, addr, 4);
7820 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7821 }
7822
7823 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7824 {
7825 TCGv t0 = tcg_temp_new();
7826 #if defined(TARGET_PPC64)
7827 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7828 #else
7829 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7830 #endif
7831 gen_qemu_st16(ctx, t0, addr);
7832 gen_addr_add(ctx, addr, addr, 2);
7833 #if defined(TARGET_PPC64)
7834 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7835 gen_qemu_st16(ctx, t0, addr);
7836 #else
7837 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7838 #endif
7839 gen_addr_add(ctx, addr, addr, 2);
7840 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7841 gen_qemu_st16(ctx, t0, addr);
7842 tcg_temp_free(t0);
7843 gen_addr_add(ctx, addr, addr, 2);
7844 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7845 }
7846
7847 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7848 {
7849 TCGv t0 = tcg_temp_new();
7850 #if defined(TARGET_PPC64)
7851 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7852 #else
7853 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7854 #endif
7855 gen_qemu_st16(ctx, t0, addr);
7856 gen_addr_add(ctx, addr, addr, 2);
7857 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7858 gen_qemu_st16(ctx, t0, addr);
7859 tcg_temp_free(t0);
7860 }
7861
7862 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7863 {
7864 #if defined(TARGET_PPC64)
7865 TCGv t0 = tcg_temp_new();
7866 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7867 gen_qemu_st16(ctx, t0, addr);
7868 tcg_temp_free(t0);
7869 #else
7870 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7871 #endif
7872 gen_addr_add(ctx, addr, addr, 2);
7873 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7874 }
7875
7876 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7877 {
7878 #if defined(TARGET_PPC64)
7879 TCGv t0 = tcg_temp_new();
7880 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7881 gen_qemu_st32(ctx, t0, addr);
7882 tcg_temp_free(t0);
7883 #else
7884 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7885 #endif
7886 }
7887
7888 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7889 {
7890 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7891 }
7892
7893 #define GEN_SPEOP_LDST(name, opc2, sh) \
7894 static void glue(gen_, name)(DisasContext *ctx) \
7895 { \
7896 TCGv t0; \
7897 if (unlikely(!ctx->spe_enabled)) { \
7898 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7899 return; \
7900 } \
7901 gen_set_access_type(ctx, ACCESS_INT); \
7902 t0 = tcg_temp_new(); \
7903 if (Rc(ctx->opcode)) { \
7904 gen_addr_spe_imm_index(ctx, t0, sh); \
7905 } else { \
7906 gen_addr_reg_index(ctx, t0); \
7907 } \
7908 gen_op_##name(ctx, t0); \
7909 tcg_temp_free(t0); \
7910 }
7911
7912 GEN_SPEOP_LDST(evldd, 0x00, 3);
7913 GEN_SPEOP_LDST(evldw, 0x01, 3);
7914 GEN_SPEOP_LDST(evldh, 0x02, 3);
7915 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7916 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7917 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7918 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7919 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7920 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7921 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7922 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7923
7924 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7925 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7926 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7927 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7928 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7929 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7930 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7931
7932 /* Multiply and add - TODO */
7933 #if 0
7934 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
7935 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7936 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7937 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7938 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7939 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7940 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7941 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7942 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7943 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7944 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7945 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7946
7947 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7948 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7949 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7950 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7951 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7952 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7953 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7954 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7955 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7956 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7957 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7958 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7959
7960 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7961 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7962 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7963 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7964 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
7965
7966 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7967 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7968 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7969 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7970 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7971 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7972 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7973 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7974 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7975 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7976 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7977 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7978
7979 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7980 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7981 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7982 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7983
7984 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7985 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7986 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7987 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7988 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7989 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7990 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7991 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7992 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7993 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7994 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7995 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7996
7997 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7998 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7999 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8000 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8001 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8002 #endif
8003
8004 /*** SPE floating-point extension ***/
8005 #if defined(TARGET_PPC64)
8006 #define GEN_SPEFPUOP_CONV_32_32(name) \
8007 static inline void gen_##name(DisasContext *ctx) \
8008 { \
8009 TCGv_i32 t0; \
8010 TCGv t1; \
8011 t0 = tcg_temp_new_i32(); \
8012 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8013 gen_helper_##name(t0, t0); \
8014 t1 = tcg_temp_new(); \
8015 tcg_gen_extu_i32_tl(t1, t0); \
8016 tcg_temp_free_i32(t0); \
8017 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8018 0xFFFFFFFF00000000ULL); \
8019 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8020 tcg_temp_free(t1); \
8021 }
8022 #define GEN_SPEFPUOP_CONV_32_64(name) \
8023 static inline void gen_##name(DisasContext *ctx) \
8024 { \
8025 TCGv_i32 t0; \
8026 TCGv t1; \
8027 t0 = tcg_temp_new_i32(); \
8028 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
8029 t1 = tcg_temp_new(); \
8030 tcg_gen_extu_i32_tl(t1, t0); \
8031 tcg_temp_free_i32(t0); \
8032 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8033 0xFFFFFFFF00000000ULL); \
8034 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8035 tcg_temp_free(t1); \
8036 }
8037 #define GEN_SPEFPUOP_CONV_64_32(name) \
8038 static inline void gen_##name(DisasContext *ctx) \
8039 { \
8040 TCGv_i32 t0 = tcg_temp_new_i32(); \
8041 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8042 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
8043 tcg_temp_free_i32(t0); \
8044 }
8045 #define GEN_SPEFPUOP_CONV_64_64(name) \
8046 static inline void gen_##name(DisasContext *ctx) \
8047 { \
8048 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8049 }
8050 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8051 static inline void gen_##name(DisasContext *ctx) \
8052 { \
8053 TCGv_i32 t0, t1; \
8054 TCGv_i64 t2; \
8055 if (unlikely(!ctx->spe_enabled)) { \
8056 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8057 return; \
8058 } \
8059 t0 = tcg_temp_new_i32(); \
8060 t1 = tcg_temp_new_i32(); \
8061 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8062 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8063 gen_helper_##name(t0, t0, t1); \
8064 tcg_temp_free_i32(t1); \
8065 t2 = tcg_temp_new(); \
8066 tcg_gen_extu_i32_tl(t2, t0); \
8067 tcg_temp_free_i32(t0); \
8068 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8069 0xFFFFFFFF00000000ULL); \
8070 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8071 tcg_temp_free(t2); \
8072 }
8073 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8074 static inline void gen_##name(DisasContext *ctx) \
8075 { \
8076 if (unlikely(!ctx->spe_enabled)) { \
8077 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8078 return; \
8079 } \
8080 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8081 cpu_gpr[rB(ctx->opcode)]); \
8082 }
8083 #define GEN_SPEFPUOP_COMP_32(name) \
8084 static inline void gen_##name(DisasContext *ctx) \
8085 { \
8086 TCGv_i32 t0, t1; \
8087 if (unlikely(!ctx->spe_enabled)) { \
8088 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8089 return; \
8090 } \
8091 t0 = tcg_temp_new_i32(); \
8092 t1 = tcg_temp_new_i32(); \
8093 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8094 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8095 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
8096 tcg_temp_free_i32(t0); \
8097 tcg_temp_free_i32(t1); \
8098 }
8099 #define GEN_SPEFPUOP_COMP_64(name) \
8100 static inline void gen_##name(DisasContext *ctx) \
8101 { \
8102 if (unlikely(!ctx->spe_enabled)) { \
8103 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8104 return; \
8105 } \
8106 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8107 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8108 }
8109 #else
8110 #define GEN_SPEFPUOP_CONV_32_32(name) \
8111 static inline void gen_##name(DisasContext *ctx) \
8112 { \
8113 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8114 }
8115 #define GEN_SPEFPUOP_CONV_32_64(name) \
8116 static inline void gen_##name(DisasContext *ctx) \
8117 { \
8118 TCGv_i64 t0 = tcg_temp_new_i64(); \
8119 gen_load_gpr64(t0, rB(ctx->opcode)); \
8120 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
8121 tcg_temp_free_i64(t0); \
8122 }
8123 #define GEN_SPEFPUOP_CONV_64_32(name) \
8124 static inline void gen_##name(DisasContext *ctx) \
8125 { \
8126 TCGv_i64 t0 = tcg_temp_new_i64(); \
8127 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
8128 gen_store_gpr64(rD(ctx->opcode), t0); \
8129 tcg_temp_free_i64(t0); \
8130 }
8131 #define GEN_SPEFPUOP_CONV_64_64(name) \
8132 static inline void gen_##name(DisasContext *ctx) \
8133 { \
8134 TCGv_i64 t0 = tcg_temp_new_i64(); \
8135 gen_load_gpr64(t0, rB(ctx->opcode)); \
8136 gen_helper_##name(t0, t0); \
8137 gen_store_gpr64(rD(ctx->opcode), t0); \
8138 tcg_temp_free_i64(t0); \
8139 }
8140 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8141 static inline void gen_##name(DisasContext *ctx) \
8142 { \
8143 if (unlikely(!ctx->spe_enabled)) { \
8144 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8145 return; \
8146 } \
8147 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
8148 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8149 }
8150 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8151 static inline void gen_##name(DisasContext *ctx) \
8152 { \
8153 TCGv_i64 t0, t1; \
8154 if (unlikely(!ctx->spe_enabled)) { \
8155 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8156 return; \
8157 } \
8158 t0 = tcg_temp_new_i64(); \
8159 t1 = tcg_temp_new_i64(); \
8160 gen_load_gpr64(t0, rA(ctx->opcode)); \
8161 gen_load_gpr64(t1, rB(ctx->opcode)); \
8162 gen_helper_##name(t0, t0, t1); \
8163 gen_store_gpr64(rD(ctx->opcode), t0); \
8164 tcg_temp_free_i64(t0); \
8165 tcg_temp_free_i64(t1); \
8166 }
8167 #define GEN_SPEFPUOP_COMP_32(name) \
8168 static inline void gen_##name(DisasContext *ctx) \
8169 { \
8170 if (unlikely(!ctx->spe_enabled)) { \
8171 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8172 return; \
8173 } \
8174 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8175 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8176 }
8177 #define GEN_SPEFPUOP_COMP_64(name) \
8178 static inline void gen_##name(DisasContext *ctx) \
8179 { \
8180 TCGv_i64 t0, t1; \
8181 if (unlikely(!ctx->spe_enabled)) { \
8182 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8183 return; \
8184 } \
8185 t0 = tcg_temp_new_i64(); \
8186 t1 = tcg_temp_new_i64(); \
8187 gen_load_gpr64(t0, rA(ctx->opcode)); \
8188 gen_load_gpr64(t1, rB(ctx->opcode)); \
8189 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
8190 tcg_temp_free_i64(t0); \
8191 tcg_temp_free_i64(t1); \
8192 }
8193 #endif
8194
8195 /* Single precision floating-point vectors operations */
8196 /* Arithmetic */
8197 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8198 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8199 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8200 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8201 static inline void gen_evfsabs(DisasContext *ctx)
8202 {
8203 if (unlikely(!ctx->spe_enabled)) {
8204 gen_exception(ctx, POWERPC_EXCP_SPEU);
8205 return;
8206 }
8207 #if defined(TARGET_PPC64)
8208 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8209 #else
8210 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8211 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8212 #endif
8213 }
8214 static inline void gen_evfsnabs(DisasContext *ctx)
8215 {
8216 if (unlikely(!ctx->spe_enabled)) {
8217 gen_exception(ctx, POWERPC_EXCP_SPEU);
8218 return;
8219 }
8220 #if defined(TARGET_PPC64)
8221 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8222 #else
8223 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8224 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8225 #endif
8226 }
8227 static inline void gen_evfsneg(DisasContext *ctx)
8228 {
8229 if (unlikely(!ctx->spe_enabled)) {
8230 gen_exception(ctx, POWERPC_EXCP_SPEU);
8231 return;
8232 }
8233 #if defined(TARGET_PPC64)
8234 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8235 #else
8236 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8237 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8238 #endif
8239 }
8240
8241 /* Conversion */
8242 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8243 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8244 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8245 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8246 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8247 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8248 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8249 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8250 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8251 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8252
8253 /* Comparison */
8254 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8255 GEN_SPEFPUOP_COMP_64(evfscmplt);
8256 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8257 GEN_SPEFPUOP_COMP_64(evfststgt);
8258 GEN_SPEFPUOP_COMP_64(evfststlt);
8259 GEN_SPEFPUOP_COMP_64(evfststeq);
8260
8261 /* Opcodes definitions */
8262 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8263 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8264 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8265 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8266 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8267 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8268 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8269 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8270 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8271 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8272 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8273 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8274 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8275 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8276
8277 /* Single precision floating-point operations */
8278 /* Arithmetic */
8279 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8280 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8281 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8282 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8283 static inline void gen_efsabs(DisasContext *ctx)
8284 {
8285 if (unlikely(!ctx->spe_enabled)) {
8286 gen_exception(ctx, POWERPC_EXCP_SPEU);
8287 return;
8288 }
8289 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8290 }
8291 static inline void gen_efsnabs(DisasContext *ctx)
8292 {
8293 if (unlikely(!ctx->spe_enabled)) {
8294 gen_exception(ctx, POWERPC_EXCP_SPEU);
8295 return;
8296 }
8297 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8298 }
8299 static inline void gen_efsneg(DisasContext *ctx)
8300 {
8301 if (unlikely(!ctx->spe_enabled)) {
8302 gen_exception(ctx, POWERPC_EXCP_SPEU);
8303 return;
8304 }
8305 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8306 }
8307
8308 /* Conversion */
8309 GEN_SPEFPUOP_CONV_32_32(efscfui);
8310 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8311 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8312 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8313 GEN_SPEFPUOP_CONV_32_32(efsctui);
8314 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8315 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8316 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8317 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8318 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8319 GEN_SPEFPUOP_CONV_32_64(efscfd);
8320
8321 /* Comparison */
8322 GEN_SPEFPUOP_COMP_32(efscmpgt);
8323 GEN_SPEFPUOP_COMP_32(efscmplt);
8324 GEN_SPEFPUOP_COMP_32(efscmpeq);
8325 GEN_SPEFPUOP_COMP_32(efststgt);
8326 GEN_SPEFPUOP_COMP_32(efststlt);
8327 GEN_SPEFPUOP_COMP_32(efststeq);
8328
8329 /* Opcodes definitions */
8330 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8331 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8332 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8333 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8334 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8335 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8336 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8337 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8338 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8339 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8340 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8341 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8342 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8343 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8344
8345 /* Double precision floating-point operations */
8346 /* Arithmetic */
8347 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8348 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8349 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8350 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8351 static inline void gen_efdabs(DisasContext *ctx)
8352 {
8353 if (unlikely(!ctx->spe_enabled)) {
8354 gen_exception(ctx, POWERPC_EXCP_SPEU);
8355 return;
8356 }
8357 #if defined(TARGET_PPC64)
8358 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8359 #else
8360 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8361 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8362 #endif
8363 }
8364 static inline void gen_efdnabs(DisasContext *ctx)
8365 {
8366 if (unlikely(!ctx->spe_enabled)) {
8367 gen_exception(ctx, POWERPC_EXCP_SPEU);
8368 return;
8369 }
8370 #if defined(TARGET_PPC64)
8371 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8372 #else
8373 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8374 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8375 #endif
8376 }
8377 static inline void gen_efdneg(DisasContext *ctx)
8378 {
8379 if (unlikely(!ctx->spe_enabled)) {
8380 gen_exception(ctx, POWERPC_EXCP_SPEU);
8381 return;
8382 }
8383 #if defined(TARGET_PPC64)
8384 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8385 #else
8386 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8387 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8388 #endif
8389 }
8390
8391 /* Conversion */
8392 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8393 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8394 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8395 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8396 GEN_SPEFPUOP_CONV_32_64(efdctui);
8397 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8398 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8399 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8400 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8401 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8402 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8403 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8404 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8405 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8406 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8407
8408 /* Comparison */
8409 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8410 GEN_SPEFPUOP_COMP_64(efdcmplt);
8411 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8412 GEN_SPEFPUOP_COMP_64(efdtstgt);
8413 GEN_SPEFPUOP_COMP_64(efdtstlt);
8414 GEN_SPEFPUOP_COMP_64(efdtsteq);
8415
8416 /* Opcodes definitions */
8417 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8418 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8419 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8420 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8421 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8422 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8423 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8424 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8425 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8426 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8427 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8428 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8429 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8430 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8431 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8432 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8433
8434 static opcode_t opcodes[] = {
8435 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8436 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8437 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8438 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8439 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8440 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8441 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8442 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8443 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8444 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8445 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8446 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8447 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8448 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8449 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8450 #if defined(TARGET_PPC64)
8451 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8452 #endif
8453 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8454 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8455 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8456 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8457 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8458 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8459 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8460 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8461 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8462 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8463 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8464 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8465 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8466 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8467 #if defined(TARGET_PPC64)
8468 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8469 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8470 #endif
8471 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8472 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8473 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8474 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8475 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8476 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8477 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8478 #if defined(TARGET_PPC64)
8479 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8480 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8481 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8482 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8483 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8484 #endif
8485 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8486 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8487 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8488 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8489 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8490 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8491 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8492 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8493 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8494 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8495 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8496 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8497 #if defined(TARGET_PPC64)
8498 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8499 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8500 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8501 #endif
8502 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8503 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8504 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8505 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8506 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8507 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8508 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8509 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8510 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8511 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8512 #if defined(TARGET_PPC64)
8513 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8514 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8515 #endif
8516 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8517 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8518 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8519 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8520 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8521 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8522 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8523 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8524 #if defined(TARGET_PPC64)
8525 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8526 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8527 #endif
8528 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8529 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8530 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8531 #if defined(TARGET_PPC64)
8532 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8533 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8534 #endif
8535 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8536 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8537 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8538 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8539 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8540 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8541 #if defined(TARGET_PPC64)
8542 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8543 #endif
8544 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8545 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8546 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8547 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8548 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8549 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8550 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8551 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ),
8552 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT),
8553 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8554 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8555 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8556 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8557 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8558 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8559 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8560 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8561 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8562 #if defined(TARGET_PPC64)
8563 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8564 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8565 PPC_SEGMENT_64B),
8566 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8567 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8568 PPC_SEGMENT_64B),
8569 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8570 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8571 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8572 #endif
8573 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8574 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8575 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8576 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8577 #if defined(TARGET_PPC64)
8578 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8579 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8580 #endif
8581 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8582 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8583 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8584 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8585 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8586 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8587 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8588 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8589 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8590 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8591 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8592 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8593 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8594 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8595 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8596 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8597 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8598 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8599 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8600 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8601 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8602 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8603 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8604 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8605 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8606 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8607 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8608 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8609 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8610 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8611 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8612 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8613 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8614 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8615 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8616 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8617 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8618 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8619 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8620 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8621 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8622 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8623 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8624 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8625 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8626 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8627 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8628 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8629 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8630 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8631 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8632 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8633 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8634 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8635 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8636 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8637 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8638 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8639 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8640 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8641 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8642 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8643 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8644 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8645 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8646 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8647 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8648 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8649 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8650 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8651 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8652 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8653 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8654 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8655 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8656 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8657 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8658 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8659 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8660 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8661 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8662 PPC_NONE, PPC2_BOOKE206),
8663 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8664 PPC_NONE, PPC2_BOOKE206),
8665 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8666 PPC_NONE, PPC2_BOOKE206),
8667 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8668 PPC_NONE, PPC2_BOOKE206),
8669 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8670 PPC_NONE, PPC2_BOOKE206),
8671 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8672 PPC_NONE, PPC2_PRCNTL),
8673 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8674 PPC_NONE, PPC2_PRCNTL),
8675 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8676 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8677 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8678 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8679 PPC_BOOKE, PPC2_BOOKE206),
8680 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8681 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8682 PPC_BOOKE, PPC2_BOOKE206),
8683 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8684 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8685 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8686 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8687 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8688 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8689 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8690 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8691 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8692 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8693
8694 #undef GEN_INT_ARITH_ADD
8695 #undef GEN_INT_ARITH_ADD_CONST
8696 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8697 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8698 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8699 add_ca, compute_ca, compute_ov) \
8700 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8701 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8702 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8703 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8704 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8705 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8706 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8707 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8708 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8709 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8710 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8711
8712 #undef GEN_INT_ARITH_DIVW
8713 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8714 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8715 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8716 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8717 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8718 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8719
8720 #if defined(TARGET_PPC64)
8721 #undef GEN_INT_ARITH_DIVD
8722 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8723 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8724 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8725 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8726 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8727 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8728
8729 #undef GEN_INT_ARITH_MUL_HELPER
8730 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8731 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8732 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8733 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8734 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8735 #endif
8736
8737 #undef GEN_INT_ARITH_SUBF
8738 #undef GEN_INT_ARITH_SUBF_CONST
8739 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8740 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8741 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8742 add_ca, compute_ca, compute_ov) \
8743 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8744 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8745 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8746 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8747 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8748 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8749 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8750 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8751 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8752 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8753 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8754
8755 #undef GEN_LOGICAL1
8756 #undef GEN_LOGICAL2
8757 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8758 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8759 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8760 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8761 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8762 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8763 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8764 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8765 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8766 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8767 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8768 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8769 #if defined(TARGET_PPC64)
8770 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8771 #endif
8772
8773 #if defined(TARGET_PPC64)
8774 #undef GEN_PPC64_R2
8775 #undef GEN_PPC64_R4
8776 #define GEN_PPC64_R2(name, opc1, opc2) \
8777 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8778 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8779 PPC_64B)
8780 #define GEN_PPC64_R4(name, opc1, opc2) \
8781 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8782 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8783 PPC_64B), \
8784 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8785 PPC_64B), \
8786 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8787 PPC_64B)
8788 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8789 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8790 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8791 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8792 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8793 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8794 #endif
8795
8796 #undef _GEN_FLOAT_ACB
8797 #undef GEN_FLOAT_ACB
8798 #undef _GEN_FLOAT_AB
8799 #undef GEN_FLOAT_AB
8800 #undef _GEN_FLOAT_AC
8801 #undef GEN_FLOAT_AC
8802 #undef GEN_FLOAT_B
8803 #undef GEN_FLOAT_BS
8804 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8805 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8806 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8807 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8808 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8809 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8810 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8811 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8812 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8813 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8814 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8815 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8816 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8817 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8818 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8819 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8820 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8821 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8822 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8823
8824 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8825 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8826 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8827 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8828 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8829 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8830 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8831 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8832 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8833 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8834 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8835 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8836 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8837 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8838 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8839 #if defined(TARGET_PPC64)
8840 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8841 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8842 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8843 #endif
8844 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8845 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8846 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8847 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8848 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8849 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8850 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8851
8852 #undef GEN_LD
8853 #undef GEN_LDU
8854 #undef GEN_LDUX
8855 #undef GEN_LDX_E
8856 #undef GEN_LDS
8857 #define GEN_LD(name, ldop, opc, type) \
8858 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8859 #define GEN_LDU(name, ldop, opc, type) \
8860 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8861 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8862 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8863 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8864 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8865 #define GEN_LDS(name, ldop, op, type) \
8866 GEN_LD(name, ldop, op | 0x20, type) \
8867 GEN_LDU(name, ldop, op | 0x21, type) \
8868 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8869 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8870
8871 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8872 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8873 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8874 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8875 #if defined(TARGET_PPC64)
8876 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8877 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8878 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8879 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8880 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
8881 #endif
8882 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8883 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8884
8885 #undef GEN_ST
8886 #undef GEN_STU
8887 #undef GEN_STUX
8888 #undef GEN_STX_E
8889 #undef GEN_STS
8890 #define GEN_ST(name, stop, opc, type) \
8891 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8892 #define GEN_STU(name, stop, opc, type) \
8893 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8894 #define GEN_STUX(name, stop, opc2, opc3, type) \
8895 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8896 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
8897 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8898 #define GEN_STS(name, stop, op, type) \
8899 GEN_ST(name, stop, op | 0x20, type) \
8900 GEN_STU(name, stop, op | 0x21, type) \
8901 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8902 GEN_STX(name, stop, 0x17, op | 0x00, type)
8903
8904 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8905 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8906 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8907 #if defined(TARGET_PPC64)
8908 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8909 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8910 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
8911 #endif
8912 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8913 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8914
8915 #undef GEN_LDF
8916 #undef GEN_LDUF
8917 #undef GEN_LDUXF
8918 #undef GEN_LDXF
8919 #undef GEN_LDFS
8920 #define GEN_LDF(name, ldop, opc, type) \
8921 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8922 #define GEN_LDUF(name, ldop, opc, type) \
8923 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8924 #define GEN_LDUXF(name, ldop, opc, type) \
8925 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8926 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
8927 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8928 #define GEN_LDFS(name, ldop, op, type) \
8929 GEN_LDF(name, ldop, op | 0x20, type) \
8930 GEN_LDUF(name, ldop, op | 0x21, type) \
8931 GEN_LDUXF(name, ldop, op | 0x01, type) \
8932 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
8933
8934 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
8935 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
8936
8937 #undef GEN_STF
8938 #undef GEN_STUF
8939 #undef GEN_STUXF
8940 #undef GEN_STXF
8941 #undef GEN_STFS
8942 #define GEN_STF(name, stop, opc, type) \
8943 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8944 #define GEN_STUF(name, stop, opc, type) \
8945 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8946 #define GEN_STUXF(name, stop, opc, type) \
8947 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8948 #define GEN_STXF(name, stop, opc2, opc3, type) \
8949 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8950 #define GEN_STFS(name, stop, op, type) \
8951 GEN_STF(name, stop, op | 0x20, type) \
8952 GEN_STUF(name, stop, op | 0x21, type) \
8953 GEN_STUXF(name, stop, op | 0x01, type) \
8954 GEN_STXF(name, stop, 0x17, op | 0x00, type)
8955
8956 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
8957 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
8958 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
8959
8960 #undef GEN_CRLOGIC
8961 #define GEN_CRLOGIC(name, tcg_op, opc) \
8962 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8963 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8964 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8965 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8966 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
8967 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
8968 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
8969 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
8970 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
8971
8972 #undef GEN_MAC_HANDLER
8973 #define GEN_MAC_HANDLER(name, opc2, opc3) \
8974 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8975 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
8976 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
8977 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
8978 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
8979 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
8980 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
8981 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
8982 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
8983 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
8984 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
8985 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
8986 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
8987 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
8988 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
8989 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
8990 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
8991 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
8992 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
8993 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
8994 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
8995 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
8996 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
8997 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
8998 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
8999 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
9000 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
9001 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
9002 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
9003 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
9004 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
9005 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
9006 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
9007 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
9008 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
9009 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
9010 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
9011 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9012 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9013 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9014 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9015 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9016 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9017
9018 #undef GEN_VR_LDX
9019 #undef GEN_VR_STX
9020 #undef GEN_VR_LVE
9021 #undef GEN_VR_STVE
9022 #define GEN_VR_LDX(name, opc2, opc3) \
9023 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9024 #define GEN_VR_STX(name, opc2, opc3) \
9025 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9026 #define GEN_VR_LVE(name, opc2, opc3) \
9027 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9028 #define GEN_VR_STVE(name, opc2, opc3) \
9029 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9030 GEN_VR_LDX(lvx, 0x07, 0x03),
9031 GEN_VR_LDX(lvxl, 0x07, 0x0B),
9032 GEN_VR_LVE(bx, 0x07, 0x00),
9033 GEN_VR_LVE(hx, 0x07, 0x01),
9034 GEN_VR_LVE(wx, 0x07, 0x02),
9035 GEN_VR_STX(svx, 0x07, 0x07),
9036 GEN_VR_STX(svxl, 0x07, 0x0F),
9037 GEN_VR_STVE(bx, 0x07, 0x04),
9038 GEN_VR_STVE(hx, 0x07, 0x05),
9039 GEN_VR_STVE(wx, 0x07, 0x06),
9040
9041 #undef GEN_VX_LOGICAL
9042 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9043 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9044 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9045 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9046 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9047 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9048 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9049
9050 #undef GEN_VXFORM
9051 #define GEN_VXFORM(name, opc2, opc3) \
9052 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9053 GEN_VXFORM(vaddubm, 0, 0),
9054 GEN_VXFORM(vadduhm, 0, 1),
9055 GEN_VXFORM(vadduwm, 0, 2),
9056 GEN_VXFORM(vsububm, 0, 16),
9057 GEN_VXFORM(vsubuhm, 0, 17),
9058 GEN_VXFORM(vsubuwm, 0, 18),
9059 GEN_VXFORM(vmaxub, 1, 0),
9060 GEN_VXFORM(vmaxuh, 1, 1),
9061 GEN_VXFORM(vmaxuw, 1, 2),
9062 GEN_VXFORM(vmaxsb, 1, 4),
9063 GEN_VXFORM(vmaxsh, 1, 5),
9064 GEN_VXFORM(vmaxsw, 1, 6),
9065 GEN_VXFORM(vminub, 1, 8),
9066 GEN_VXFORM(vminuh, 1, 9),
9067 GEN_VXFORM(vminuw, 1, 10),
9068 GEN_VXFORM(vminsb, 1, 12),
9069 GEN_VXFORM(vminsh, 1, 13),
9070 GEN_VXFORM(vminsw, 1, 14),
9071 GEN_VXFORM(vavgub, 1, 16),
9072 GEN_VXFORM(vavguh, 1, 17),
9073 GEN_VXFORM(vavguw, 1, 18),
9074 GEN_VXFORM(vavgsb, 1, 20),
9075 GEN_VXFORM(vavgsh, 1, 21),
9076 GEN_VXFORM(vavgsw, 1, 22),
9077 GEN_VXFORM(vmrghb, 6, 0),
9078 GEN_VXFORM(vmrghh, 6, 1),
9079 GEN_VXFORM(vmrghw, 6, 2),
9080 GEN_VXFORM(vmrglb, 6, 4),
9081 GEN_VXFORM(vmrglh, 6, 5),
9082 GEN_VXFORM(vmrglw, 6, 6),
9083 GEN_VXFORM(vmuloub, 4, 0),
9084 GEN_VXFORM(vmulouh, 4, 1),
9085 GEN_VXFORM(vmulosb, 4, 4),
9086 GEN_VXFORM(vmulosh, 4, 5),
9087 GEN_VXFORM(vmuleub, 4, 8),
9088 GEN_VXFORM(vmuleuh, 4, 9),
9089 GEN_VXFORM(vmulesb, 4, 12),
9090 GEN_VXFORM(vmulesh, 4, 13),
9091 GEN_VXFORM(vslb, 2, 4),
9092 GEN_VXFORM(vslh, 2, 5),
9093 GEN_VXFORM(vslw, 2, 6),
9094 GEN_VXFORM(vsrb, 2, 8),
9095 GEN_VXFORM(vsrh, 2, 9),
9096 GEN_VXFORM(vsrw, 2, 10),
9097 GEN_VXFORM(vsrab, 2, 12),
9098 GEN_VXFORM(vsrah, 2, 13),
9099 GEN_VXFORM(vsraw, 2, 14),
9100 GEN_VXFORM(vslo, 6, 16),
9101 GEN_VXFORM(vsro, 6, 17),
9102 GEN_VXFORM(vaddcuw, 0, 6),
9103 GEN_VXFORM(vsubcuw, 0, 22),
9104 GEN_VXFORM(vaddubs, 0, 8),
9105 GEN_VXFORM(vadduhs, 0, 9),
9106 GEN_VXFORM(vadduws, 0, 10),
9107 GEN_VXFORM(vaddsbs, 0, 12),
9108 GEN_VXFORM(vaddshs, 0, 13),
9109 GEN_VXFORM(vaddsws, 0, 14),
9110 GEN_VXFORM(vsububs, 0, 24),
9111 GEN_VXFORM(vsubuhs, 0, 25),
9112 GEN_VXFORM(vsubuws, 0, 26),
9113 GEN_VXFORM(vsubsbs, 0, 28),
9114 GEN_VXFORM(vsubshs, 0, 29),
9115 GEN_VXFORM(vsubsws, 0, 30),
9116 GEN_VXFORM(vrlb, 2, 0),
9117 GEN_VXFORM(vrlh, 2, 1),
9118 GEN_VXFORM(vrlw, 2, 2),
9119 GEN_VXFORM(vsl, 2, 7),
9120 GEN_VXFORM(vsr, 2, 11),
9121 GEN_VXFORM(vpkuhum, 7, 0),
9122 GEN_VXFORM(vpkuwum, 7, 1),
9123 GEN_VXFORM(vpkuhus, 7, 2),
9124 GEN_VXFORM(vpkuwus, 7, 3),
9125 GEN_VXFORM(vpkshus, 7, 4),
9126 GEN_VXFORM(vpkswus, 7, 5),
9127 GEN_VXFORM(vpkshss, 7, 6),
9128 GEN_VXFORM(vpkswss, 7, 7),
9129 GEN_VXFORM(vpkpx, 7, 12),
9130 GEN_VXFORM(vsum4ubs, 4, 24),
9131 GEN_VXFORM(vsum4sbs, 4, 28),
9132 GEN_VXFORM(vsum4shs, 4, 25),
9133 GEN_VXFORM(vsum2sws, 4, 26),
9134 GEN_VXFORM(vsumsws, 4, 30),
9135 GEN_VXFORM(vaddfp, 5, 0),
9136 GEN_VXFORM(vsubfp, 5, 1),
9137 GEN_VXFORM(vmaxfp, 5, 16),
9138 GEN_VXFORM(vminfp, 5, 17),
9139
9140 #undef GEN_VXRFORM1
9141 #undef GEN_VXRFORM
9142 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9143 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9144 #define GEN_VXRFORM(name, opc2, opc3) \
9145 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9146 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9147 GEN_VXRFORM(vcmpequb, 3, 0)
9148 GEN_VXRFORM(vcmpequh, 3, 1)
9149 GEN_VXRFORM(vcmpequw, 3, 2)
9150 GEN_VXRFORM(vcmpgtsb, 3, 12)
9151 GEN_VXRFORM(vcmpgtsh, 3, 13)
9152 GEN_VXRFORM(vcmpgtsw, 3, 14)
9153 GEN_VXRFORM(vcmpgtub, 3, 8)
9154 GEN_VXRFORM(vcmpgtuh, 3, 9)
9155 GEN_VXRFORM(vcmpgtuw, 3, 10)
9156 GEN_VXRFORM(vcmpeqfp, 3, 3)
9157 GEN_VXRFORM(vcmpgefp, 3, 7)
9158 GEN_VXRFORM(vcmpgtfp, 3, 11)
9159 GEN_VXRFORM(vcmpbfp, 3, 15)
9160
9161 #undef GEN_VXFORM_SIMM
9162 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9163 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9164 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9165 GEN_VXFORM_SIMM(vspltish, 6, 13),
9166 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9167
9168 #undef GEN_VXFORM_NOA
9169 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9170 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9171 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9172 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9173 GEN_VXFORM_NOA(vupklsb, 7, 10),
9174 GEN_VXFORM_NOA(vupklsh, 7, 11),
9175 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9176 GEN_VXFORM_NOA(vupklpx, 7, 15),
9177 GEN_VXFORM_NOA(vrefp, 5, 4),
9178 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9179 GEN_VXFORM_NOA(vexptefp, 5, 6),
9180 GEN_VXFORM_NOA(vlogefp, 5, 7),
9181 GEN_VXFORM_NOA(vrfim, 5, 8),
9182 GEN_VXFORM_NOA(vrfin, 5, 9),
9183 GEN_VXFORM_NOA(vrfip, 5, 10),
9184 GEN_VXFORM_NOA(vrfiz, 5, 11),
9185
9186 #undef GEN_VXFORM_UIMM
9187 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9188 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9189 GEN_VXFORM_UIMM(vspltb, 6, 8),
9190 GEN_VXFORM_UIMM(vsplth, 6, 9),
9191 GEN_VXFORM_UIMM(vspltw, 6, 10),
9192 GEN_VXFORM_UIMM(vcfux, 5, 12),
9193 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9194 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9195 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9196
9197 #undef GEN_VAFORM_PAIRED
9198 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9199 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9200 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9201 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9202 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9203 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9204 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9205 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9206
9207 #undef GEN_SPE
9208 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9209 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9210 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9211 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9212 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9213 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9214 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9215 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9216 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9217 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9218 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9219 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9220 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9221 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9222 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9223 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9224 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9225 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9226 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9227 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9228 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9229 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9230 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9231 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9232 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9233 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9234 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9235 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9236 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9237 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9238 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9239
9240 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9241 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9242 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9243 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9244 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9245 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9246 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9247 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9248 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9249 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9250 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9251 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9252 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9253 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9254
9255 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9256 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9257 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9258 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9259 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9260 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9261 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9262 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9263 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9264 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9265 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9266 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9267 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9268 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9269
9270 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9271 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9272 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9273 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9274 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9275 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9276 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9277 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9278 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9279 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9280 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9281 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9282 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9283 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9284 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9285 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9286
9287 #undef GEN_SPEOP_LDST
9288 #define GEN_SPEOP_LDST(name, opc2, sh) \
9289 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9290 GEN_SPEOP_LDST(evldd, 0x00, 3),
9291 GEN_SPEOP_LDST(evldw, 0x01, 3),
9292 GEN_SPEOP_LDST(evldh, 0x02, 3),
9293 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9294 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9295 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9296 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9297 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9298 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9299 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9300 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9301
9302 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9303 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9304 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9305 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9306 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9307 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9308 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9309 };
9310
9311 #include "helper_regs.h"
9312 #include "translate_init.c"
9313
9314 /*****************************************************************************/
9315 /* Misc PowerPC helpers */
9316 void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
9317 int flags)
9318 {
9319 #define RGPL 4
9320 #define RFPL 4
9321
9322 int i;
9323
9324 cpu_synchronize_state(env);
9325
9326 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9327 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9328 env->nip, env->lr, env->ctr, env->xer);
9329 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9330 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9331 env->hflags, env->mmu_idx);
9332 #if !defined(NO_TIMER_DUMP)
9333 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9334 #if !defined(CONFIG_USER_ONLY)
9335 " DECR %08" PRIu32
9336 #endif
9337 "\n",
9338 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9339 #if !defined(CONFIG_USER_ONLY)
9340 , cpu_ppc_load_decr(env)
9341 #endif
9342 );
9343 #endif
9344 for (i = 0; i < 32; i++) {
9345 if ((i & (RGPL - 1)) == 0)
9346 cpu_fprintf(f, "GPR%02d", i);
9347 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9348 if ((i & (RGPL - 1)) == (RGPL - 1))
9349 cpu_fprintf(f, "\n");
9350 }
9351 cpu_fprintf(f, "CR ");
9352 for (i = 0; i < 8; i++)
9353 cpu_fprintf(f, "%01x", env->crf[i]);
9354 cpu_fprintf(f, " [");
9355 for (i = 0; i < 8; i++) {
9356 char a = '-';
9357 if (env->crf[i] & 0x08)
9358 a = 'L';
9359 else if (env->crf[i] & 0x04)
9360 a = 'G';
9361 else if (env->crf[i] & 0x02)
9362 a = 'E';
9363 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9364 }
9365 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9366 env->reserve_addr);
9367 for (i = 0; i < 32; i++) {
9368 if ((i & (RFPL - 1)) == 0)
9369 cpu_fprintf(f, "FPR%02d", i);
9370 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9371 if ((i & (RFPL - 1)) == (RFPL - 1))
9372 cpu_fprintf(f, "\n");
9373 }
9374 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
9375 #if !defined(CONFIG_USER_ONLY)
9376 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9377 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9378 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9379 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9380
9381 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9382 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9383 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9384 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9385
9386 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9387 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9388 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9389 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9390
9391 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9392 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9393 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9394 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9395 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9396
9397 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9398 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9399 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9400 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9401
9402 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9403 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9404 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9405 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9406
9407 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9408 " EPR " TARGET_FMT_lx "\n",
9409 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9410 env->spr[SPR_BOOKE_EPR]);
9411
9412 /* FSL-specific */
9413 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9414 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9415 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9416 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9417
9418 /*
9419 * IVORs are left out as they are large and do not change often --
9420 * they can be read with "p $ivor0", "p $ivor1", etc.
9421 */
9422 }
9423
9424 #if defined(TARGET_PPC64)
9425 if (env->flags & POWERPC_FLAG_CFAR) {
9426 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9427 }
9428 #endif
9429
9430 switch (env->mmu_model) {
9431 case POWERPC_MMU_32B:
9432 case POWERPC_MMU_601:
9433 case POWERPC_MMU_SOFT_6xx:
9434 case POWERPC_MMU_SOFT_74xx:
9435 #if defined(TARGET_PPC64)
9436 case POWERPC_MMU_620:
9437 case POWERPC_MMU_64B:
9438 #endif
9439 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9440 break;
9441 case POWERPC_MMU_BOOKE206:
9442 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9443 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9444 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9445 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9446
9447 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9448 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9449 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9450 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9451
9452 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9453 " TLB1CFG " TARGET_FMT_lx "\n",
9454 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9455 env->spr[SPR_BOOKE_TLB1CFG]);
9456 break;
9457 default:
9458 break;
9459 }
9460 #endif
9461
9462 #undef RGPL
9463 #undef RFPL
9464 }
9465
9466 void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
9467 int flags)
9468 {
9469 #if defined(DO_PPC_STATISTICS)
9470 opc_handler_t **t1, **t2, **t3, *handler;
9471 int op1, op2, op3;
9472
9473 t1 = env->opcodes;
9474 for (op1 = 0; op1 < 64; op1++) {
9475 handler = t1[op1];
9476 if (is_indirect_opcode(handler)) {
9477 t2 = ind_table(handler);
9478 for (op2 = 0; op2 < 32; op2++) {
9479 handler = t2[op2];
9480 if (is_indirect_opcode(handler)) {
9481 t3 = ind_table(handler);
9482 for (op3 = 0; op3 < 32; op3++) {
9483 handler = t3[op3];
9484 if (handler->count == 0)
9485 continue;
9486 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9487 "%016" PRIx64 " %" PRId64 "\n",
9488 op1, op2, op3, op1, (op3 << 5) | op2,
9489 handler->oname,
9490 handler->count, handler->count);
9491 }
9492 } else {
9493 if (handler->count == 0)
9494 continue;
9495 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9496 "%016" PRIx64 " %" PRId64 "\n",
9497 op1, op2, op1, op2, handler->oname,
9498 handler->count, handler->count);
9499 }
9500 }
9501 } else {
9502 if (handler->count == 0)
9503 continue;
9504 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9505 " %" PRId64 "\n",
9506 op1, op1, handler->oname,
9507 handler->count, handler->count);
9508 }
9509 }
9510 #endif
9511 }
9512
9513 /*****************************************************************************/
9514 static inline void gen_intermediate_code_internal(CPUPPCState *env,
9515 TranslationBlock *tb,
9516 int search_pc)
9517 {
9518 DisasContext ctx, *ctxp = &ctx;
9519 opc_handler_t **table, *handler;
9520 target_ulong pc_start;
9521 uint16_t *gen_opc_end;
9522 CPUBreakpoint *bp;
9523 int j, lj = -1;
9524 int num_insns;
9525 int max_insns;
9526
9527 pc_start = tb->pc;
9528 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
9529 ctx.nip = pc_start;
9530 ctx.tb = tb;
9531 ctx.exception = POWERPC_EXCP_NONE;
9532 ctx.spr_cb = env->spr_cb;
9533 ctx.mem_idx = env->mmu_idx;
9534 ctx.access_type = -1;
9535 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9536 #if defined(TARGET_PPC64)
9537 ctx.sf_mode = msr_sf;
9538 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9539 #endif
9540 ctx.fpu_enabled = msr_fp;
9541 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9542 ctx.spe_enabled = msr_spe;
9543 else
9544 ctx.spe_enabled = 0;
9545 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9546 ctx.altivec_enabled = msr_vr;
9547 else
9548 ctx.altivec_enabled = 0;
9549 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9550 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9551 else
9552 ctx.singlestep_enabled = 0;
9553 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9554 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9555 if (unlikely(env->singlestep_enabled))
9556 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9557 #if defined (DO_SINGLE_STEP) && 0
9558 /* Single step trace mode */
9559 msr_se = 1;
9560 #endif
9561 num_insns = 0;
9562 max_insns = tb->cflags & CF_COUNT_MASK;
9563 if (max_insns == 0)
9564 max_insns = CF_COUNT_MASK;
9565
9566 gen_icount_start();
9567 /* Set env in case of segfault during code fetch */
9568 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
9569 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9570 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9571 if (bp->pc == ctx.nip) {
9572 gen_debug_exception(ctxp);
9573 break;
9574 }
9575 }
9576 }
9577 if (unlikely(search_pc)) {
9578 j = gen_opc_ptr - gen_opc_buf;
9579 if (lj < j) {
9580 lj++;
9581 while (lj < j)
9582 gen_opc_instr_start[lj++] = 0;
9583 }
9584 gen_opc_pc[lj] = ctx.nip;
9585 gen_opc_instr_start[lj] = 1;
9586 gen_opc_icount[lj] = num_insns;
9587 }
9588 LOG_DISAS("----------------\n");
9589 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9590 ctx.nip, ctx.mem_idx, (int)msr_ir);
9591 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9592 gen_io_start();
9593 if (unlikely(ctx.le_mode)) {
9594 ctx.opcode = bswap32(ldl_code(ctx.nip));
9595 } else {
9596 ctx.opcode = ldl_code(ctx.nip);
9597 }
9598 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9599 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9600 opc3(ctx.opcode), little_endian ? "little" : "big");
9601 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
9602 tcg_gen_debug_insn_start(ctx.nip);
9603 ctx.nip += 4;
9604 table = env->opcodes;
9605 num_insns++;
9606 handler = table[opc1(ctx.opcode)];
9607 if (is_indirect_opcode(handler)) {
9608 table = ind_table(handler);
9609 handler = table[opc2(ctx.opcode)];
9610 if (is_indirect_opcode(handler)) {
9611 table = ind_table(handler);
9612 handler = table[opc3(ctx.opcode)];
9613 }
9614 }
9615 /* Is opcode *REALLY* valid ? */
9616 if (unlikely(handler->handler == &gen_invalid)) {
9617 if (qemu_log_enabled()) {
9618 qemu_log("invalid/unsupported opcode: "
9619 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9620 opc1(ctx.opcode), opc2(ctx.opcode),
9621 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9622 }
9623 } else {
9624 uint32_t inval;
9625
9626 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9627 inval = handler->inval2;
9628 } else {
9629 inval = handler->inval1;
9630 }
9631
9632 if (unlikely((ctx.opcode & inval) != 0)) {
9633 if (qemu_log_enabled()) {
9634 qemu_log("invalid bits: %08x for opcode: "
9635 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9636 ctx.opcode & inval, opc1(ctx.opcode),
9637 opc2(ctx.opcode), opc3(ctx.opcode),
9638 ctx.opcode, ctx.nip - 4);
9639 }
9640 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9641 break;
9642 }
9643 }
9644 (*(handler->handler))(&ctx);
9645 #if defined(DO_PPC_STATISTICS)
9646 handler->count++;
9647 #endif
9648 /* Check trace mode exceptions */
9649 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9650 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9651 ctx.exception != POWERPC_SYSCALL &&
9652 ctx.exception != POWERPC_EXCP_TRAP &&
9653 ctx.exception != POWERPC_EXCP_BRANCH)) {
9654 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9655 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9656 (env->singlestep_enabled) ||
9657 singlestep ||
9658 num_insns >= max_insns)) {
9659 /* if we reach a page boundary or are single stepping, stop
9660 * generation
9661 */
9662 break;
9663 }
9664 }
9665 if (tb->cflags & CF_LAST_IO)
9666 gen_io_end();
9667 if (ctx.exception == POWERPC_EXCP_NONE) {
9668 gen_goto_tb(&ctx, 0, ctx.nip);
9669 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9670 if (unlikely(env->singlestep_enabled)) {
9671 gen_debug_exception(ctxp);
9672 }
9673 /* Generate the return instruction */
9674 tcg_gen_exit_tb(0);
9675 }
9676 gen_icount_end(tb, num_insns);
9677 *gen_opc_ptr = INDEX_op_end;
9678 if (unlikely(search_pc)) {
9679 j = gen_opc_ptr - gen_opc_buf;
9680 lj++;
9681 while (lj <= j)
9682 gen_opc_instr_start[lj++] = 0;
9683 } else {
9684 tb->size = ctx.nip - pc_start;
9685 tb->icount = num_insns;
9686 }
9687 #if defined(DEBUG_DISAS)
9688 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9689 int flags;
9690 flags = env->bfd_mach;
9691 flags |= ctx.le_mode << 16;
9692 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9693 log_target_disas(pc_start, ctx.nip - pc_start, flags);
9694 qemu_log("\n");
9695 }
9696 #endif
9697 }
9698
9699 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9700 {
9701 gen_intermediate_code_internal(env, tb, 0);
9702 }
9703
9704 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9705 {
9706 gen_intermediate_code_internal(env, tb, 1);
9707 }
9708
9709 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9710 {
9711 env->nip = gen_opc_pc[pc_pos];
9712 }
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