]> git.proxmox.com Git - mirror_qemu.git/blob - target-ppc/translate.c
projects / mirror_qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
target-ppc: VSX Stage 4: Refactor stxsdx
[mirror_qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 10*5 + 22*6 /* VSR */
55 + 8*5 /* CRF */];
56 static TCGv cpu_gpr[32];
57 #if !defined(TARGET_PPC64)
58 static TCGv cpu_gprh[32];
59 #endif
60 static TCGv_i64 cpu_fpr[32];
61 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
62 static TCGv_i64 cpu_vsr[32];
63 static TCGv_i32 cpu_crf[8];
64 static TCGv cpu_nip;
65 static TCGv cpu_msr;
66 static TCGv cpu_ctr;
67 static TCGv cpu_lr;
68 #if defined(TARGET_PPC64)
69 static TCGv cpu_cfar;
70 #endif
71 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
72 static TCGv cpu_reserve;
73 static TCGv cpu_fpscr;
74 static TCGv_i32 cpu_access_type;
75
76 #include "exec/gen-icount.h"
77
78 void ppc_translate_init(void)
79 {
80 int i;
81 char* p;
82 size_t cpu_reg_names_size;
83 static int done_init = 0;
84
85 if (done_init)
86 return;
87
88 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
89
90 p = cpu_reg_names;
91 cpu_reg_names_size = sizeof(cpu_reg_names);
92
93 for (i = 0; i < 8; i++) {
94 snprintf(p, cpu_reg_names_size, "crf%d", i);
95 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
96 offsetof(CPUPPCState, crf[i]), p);
97 p += 5;
98 cpu_reg_names_size -= 5;
99 }
100
101 for (i = 0; i < 32; i++) {
102 snprintf(p, cpu_reg_names_size, "r%d", i);
103 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
104 offsetof(CPUPPCState, gpr[i]), p);
105 p += (i < 10) ? 3 : 4;
106 cpu_reg_names_size -= (i < 10) ? 3 : 4;
107 #if !defined(TARGET_PPC64)
108 snprintf(p, cpu_reg_names_size, "r%dH", i);
109 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
110 offsetof(CPUPPCState, gprh[i]), p);
111 p += (i < 10) ? 4 : 5;
112 cpu_reg_names_size -= (i < 10) ? 4 : 5;
113 #endif
114
115 snprintf(p, cpu_reg_names_size, "fp%d", i);
116 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
117 offsetof(CPUPPCState, fpr[i]), p);
118 p += (i < 10) ? 4 : 5;
119 cpu_reg_names_size -= (i < 10) ? 4 : 5;
120
121 snprintf(p, cpu_reg_names_size, "avr%dH", i);
122 #ifdef HOST_WORDS_BIGENDIAN
123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
124 offsetof(CPUPPCState, avr[i].u64[0]), p);
125 #else
126 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
127 offsetof(CPUPPCState, avr[i].u64[1]), p);
128 #endif
129 p += (i < 10) ? 6 : 7;
130 cpu_reg_names_size -= (i < 10) ? 6 : 7;
131
132 snprintf(p, cpu_reg_names_size, "avr%dL", i);
133 #ifdef HOST_WORDS_BIGENDIAN
134 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
135 offsetof(CPUPPCState, avr[i].u64[1]), p);
136 #else
137 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
138 offsetof(CPUPPCState, avr[i].u64[0]), p);
139 #endif
140 p += (i < 10) ? 6 : 7;
141 cpu_reg_names_size -= (i < 10) ? 6 : 7;
142 snprintf(p, cpu_reg_names_size, "vsr%d", i);
143 cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
144 offsetof(CPUPPCState, vsr[i]), p);
145 p += (i < 10) ? 5 : 6;
146 cpu_reg_names_size -= (i < 10) ? 5 : 6;
147 }
148
149 cpu_nip = tcg_global_mem_new(TCG_AREG0,
150 offsetof(CPUPPCState, nip), "nip");
151
152 cpu_msr = tcg_global_mem_new(TCG_AREG0,
153 offsetof(CPUPPCState, msr), "msr");
154
155 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, ctr), "ctr");
157
158 cpu_lr = tcg_global_mem_new(TCG_AREG0,
159 offsetof(CPUPPCState, lr), "lr");
160
161 #if defined(TARGET_PPC64)
162 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
163 offsetof(CPUPPCState, cfar), "cfar");
164 #endif
165
166 cpu_xer = tcg_global_mem_new(TCG_AREG0,
167 offsetof(CPUPPCState, xer), "xer");
168 cpu_so = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, so), "SO");
170 cpu_ov = tcg_global_mem_new(TCG_AREG0,
171 offsetof(CPUPPCState, ov), "OV");
172 cpu_ca = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, ca), "CA");
174
175 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
176 offsetof(CPUPPCState, reserve_addr),
177 "reserve_addr");
178
179 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
180 offsetof(CPUPPCState, fpscr), "fpscr");
181
182 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
183 offsetof(CPUPPCState, access_type), "access_type");
184
185 done_init = 1;
186 }
187
188 /* internal defines */
189 typedef struct DisasContext {
190 struct TranslationBlock *tb;
191 target_ulong nip;
192 uint32_t opcode;
193 uint32_t exception;
194 /* Routine used to access memory */
195 int mem_idx;
196 int access_type;
197 /* Translation flags */
198 int le_mode;
199 #if defined(TARGET_PPC64)
200 int sf_mode;
201 int has_cfar;
202 #endif
203 int fpu_enabled;
204 int altivec_enabled;
205 int vsx_enabled;
206 int spe_enabled;
207 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
208 int singlestep_enabled;
209 uint64_t insns_flags;
210 uint64_t insns_flags2;
211 } DisasContext;
212
213 /* True when active word size < size of target_long. */
214 #ifdef TARGET_PPC64
215 # define NARROW_MODE(C) (!(C)->sf_mode)
216 #else
217 # define NARROW_MODE(C) 0
218 #endif
219
220 struct opc_handler_t {
221 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
222 uint32_t inval1;
223 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
224 uint32_t inval2;
225 /* instruction type */
226 uint64_t type;
227 /* extended instruction type */
228 uint64_t type2;
229 /* handler */
230 void (*handler)(DisasContext *ctx);
231 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
232 const char *oname;
233 #endif
234 #if defined(DO_PPC_STATISTICS)
235 uint64_t count;
236 #endif
237 };
238
239 static inline void gen_reset_fpstatus(void)
240 {
241 gen_helper_reset_fpstatus(cpu_env);
242 }
243
244 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
245 {
246 TCGv_i32 t0 = tcg_temp_new_i32();
247
248 if (set_fprf != 0) {
249 /* This case might be optimized later */
250 tcg_gen_movi_i32(t0, 1);
251 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
252 if (unlikely(set_rc)) {
253 tcg_gen_mov_i32(cpu_crf[1], t0);
254 }
255 gen_helper_float_check_status(cpu_env);
256 } else if (unlikely(set_rc)) {
257 /* We always need to compute fpcc */
258 tcg_gen_movi_i32(t0, 0);
259 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
260 tcg_gen_mov_i32(cpu_crf[1], t0);
261 }
262
263 tcg_temp_free_i32(t0);
264 }
265
266 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
267 {
268 if (ctx->access_type != access_type) {
269 tcg_gen_movi_i32(cpu_access_type, access_type);
270 ctx->access_type = access_type;
271 }
272 }
273
274 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
275 {
276 if (NARROW_MODE(ctx)) {
277 nip = (uint32_t)nip;
278 }
279 tcg_gen_movi_tl(cpu_nip, nip);
280 }
281
282 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
283 {
284 TCGv_i32 t0, t1;
285 if (ctx->exception == POWERPC_EXCP_NONE) {
286 gen_update_nip(ctx, ctx->nip);
287 }
288 t0 = tcg_const_i32(excp);
289 t1 = tcg_const_i32(error);
290 gen_helper_raise_exception_err(cpu_env, t0, t1);
291 tcg_temp_free_i32(t0);
292 tcg_temp_free_i32(t1);
293 ctx->exception = (excp);
294 }
295
296 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
297 {
298 TCGv_i32 t0;
299 if (ctx->exception == POWERPC_EXCP_NONE) {
300 gen_update_nip(ctx, ctx->nip);
301 }
302 t0 = tcg_const_i32(excp);
303 gen_helper_raise_exception(cpu_env, t0);
304 tcg_temp_free_i32(t0);
305 ctx->exception = (excp);
306 }
307
308 static inline void gen_debug_exception(DisasContext *ctx)
309 {
310 TCGv_i32 t0;
311
312 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
313 (ctx->exception != POWERPC_EXCP_SYNC)) {
314 gen_update_nip(ctx, ctx->nip);
315 }
316 t0 = tcg_const_i32(EXCP_DEBUG);
317 gen_helper_raise_exception(cpu_env, t0);
318 tcg_temp_free_i32(t0);
319 }
320
321 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
322 {
323 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
324 }
325
326 /* Stop translation */
327 static inline void gen_stop_exception(DisasContext *ctx)
328 {
329 gen_update_nip(ctx, ctx->nip);
330 ctx->exception = POWERPC_EXCP_STOP;
331 }
332
333 /* No need to update nip here, as execution flow will change */
334 static inline void gen_sync_exception(DisasContext *ctx)
335 {
336 ctx->exception = POWERPC_EXCP_SYNC;
337 }
338
339 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
340 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
341
342 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
343 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
344
345 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
346 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
347
348 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
349 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
350
351 typedef struct opcode_t {
352 unsigned char opc1, opc2, opc3;
353 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
354 unsigned char pad[5];
355 #else
356 unsigned char pad[1];
357 #endif
358 opc_handler_t handler;
359 const char *oname;
360 } opcode_t;
361
362 /*****************************************************************************/
363 /*** Instruction decoding ***/
364 #define EXTRACT_HELPER(name, shift, nb) \
365 static inline uint32_t name(uint32_t opcode) \
366 { \
367 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
368 }
369
370 #define EXTRACT_SHELPER(name, shift, nb) \
371 static inline int32_t name(uint32_t opcode) \
372 { \
373 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
374 }
375
376 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
377 static inline uint32_t name(uint32_t opcode) \
378 { \
379 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
380 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
381 }
382 /* Opcode part 1 */
383 EXTRACT_HELPER(opc1, 26, 6);
384 /* Opcode part 2 */
385 EXTRACT_HELPER(opc2, 1, 5);
386 /* Opcode part 3 */
387 EXTRACT_HELPER(opc3, 6, 5);
388 /* Update Cr0 flags */
389 EXTRACT_HELPER(Rc, 0, 1);
390 /* Destination */
391 EXTRACT_HELPER(rD, 21, 5);
392 /* Source */
393 EXTRACT_HELPER(rS, 21, 5);
394 /* First operand */
395 EXTRACT_HELPER(rA, 16, 5);
396 /* Second operand */
397 EXTRACT_HELPER(rB, 11, 5);
398 /* Third operand */
399 EXTRACT_HELPER(rC, 6, 5);
400 /*** Get CRn ***/
401 EXTRACT_HELPER(crfD, 23, 3);
402 EXTRACT_HELPER(crfS, 18, 3);
403 EXTRACT_HELPER(crbD, 21, 5);
404 EXTRACT_HELPER(crbA, 16, 5);
405 EXTRACT_HELPER(crbB, 11, 5);
406 /* SPR / TBL */
407 EXTRACT_HELPER(_SPR, 11, 10);
408 static inline uint32_t SPR(uint32_t opcode)
409 {
410 uint32_t sprn = _SPR(opcode);
411
412 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
413 }
414 /*** Get constants ***/
415 EXTRACT_HELPER(IMM, 12, 8);
416 /* 16 bits signed immediate value */
417 EXTRACT_SHELPER(SIMM, 0, 16);
418 /* 16 bits unsigned immediate value */
419 EXTRACT_HELPER(UIMM, 0, 16);
420 /* 5 bits signed immediate value */
421 EXTRACT_HELPER(SIMM5, 16, 5);
422 /* 5 bits signed immediate value */
423 EXTRACT_HELPER(UIMM5, 16, 5);
424 /* Bit count */
425 EXTRACT_HELPER(NB, 11, 5);
426 /* Shift count */
427 EXTRACT_HELPER(SH, 11, 5);
428 /* Vector shift count */
429 EXTRACT_HELPER(VSH, 6, 4);
430 /* Mask start */
431 EXTRACT_HELPER(MB, 6, 5);
432 /* Mask end */
433 EXTRACT_HELPER(ME, 1, 5);
434 /* Trap operand */
435 EXTRACT_HELPER(TO, 21, 5);
436
437 EXTRACT_HELPER(CRM, 12, 8);
438 EXTRACT_HELPER(SR, 16, 4);
439
440 /* mtfsf/mtfsfi */
441 EXTRACT_HELPER(FPBF, 23, 3);
442 EXTRACT_HELPER(FPIMM, 12, 4);
443 EXTRACT_HELPER(FPL, 25, 1);
444 EXTRACT_HELPER(FPFLM, 17, 8);
445 EXTRACT_HELPER(FPW, 16, 1);
446
447 /*** Jump target decoding ***/
448 /* Displacement */
449 EXTRACT_SHELPER(d, 0, 16);
450 /* Immediate address */
451 static inline target_ulong LI(uint32_t opcode)
452 {
453 return (opcode >> 0) & 0x03FFFFFC;
454 }
455
456 static inline uint32_t BD(uint32_t opcode)
457 {
458 return (opcode >> 0) & 0xFFFC;
459 }
460
461 EXTRACT_HELPER(BO, 21, 5);
462 EXTRACT_HELPER(BI, 16, 5);
463 /* Absolute/relative address */
464 EXTRACT_HELPER(AA, 1, 1);
465 /* Link */
466 EXTRACT_HELPER(LK, 0, 1);
467
468 /* Create a mask between <start> and <end> bits */
469 static inline target_ulong MASK(uint32_t start, uint32_t end)
470 {
471 target_ulong ret;
472
473 #if defined(TARGET_PPC64)
474 if (likely(start == 0)) {
475 ret = UINT64_MAX << (63 - end);
476 } else if (likely(end == 63)) {
477 ret = UINT64_MAX >> start;
478 }
479 #else
480 if (likely(start == 0)) {
481 ret = UINT32_MAX << (31 - end);
482 } else if (likely(end == 31)) {
483 ret = UINT32_MAX >> start;
484 }
485 #endif
486 else {
487 ret = (((target_ulong)(-1ULL)) >> (start)) ^
488 (((target_ulong)(-1ULL) >> (end)) >> 1);
489 if (unlikely(start > end))
490 return ~ret;
491 }
492
493 return ret;
494 }
495
496 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
497 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
498 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
499 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
500 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
501 EXTRACT_HELPER(DM, 8, 2);
502 EXTRACT_HELPER(UIM, 16, 2);
503 EXTRACT_HELPER(SHW, 8, 2);
504 /*****************************************************************************/
505 /* PowerPC instructions table */
506
507 #if defined(DO_PPC_STATISTICS)
508 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
509 { \
510 .opc1 = op1, \
511 .opc2 = op2, \
512 .opc3 = op3, \
513 .pad = { 0, }, \
514 .handler = { \
515 .inval1 = invl, \
516 .type = _typ, \
517 .type2 = _typ2, \
518 .handler = &gen_##name, \
519 .oname = stringify(name), \
520 }, \
521 .oname = stringify(name), \
522 }
523 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
524 { \
525 .opc1 = op1, \
526 .opc2 = op2, \
527 .opc3 = op3, \
528 .pad = { 0, }, \
529 .handler = { \
530 .inval1 = invl1, \
531 .inval2 = invl2, \
532 .type = _typ, \
533 .type2 = _typ2, \
534 .handler = &gen_##name, \
535 .oname = stringify(name), \
536 }, \
537 .oname = stringify(name), \
538 }
539 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
540 { \
541 .opc1 = op1, \
542 .opc2 = op2, \
543 .opc3 = op3, \
544 .pad = { 0, }, \
545 .handler = { \
546 .inval1 = invl, \
547 .type = _typ, \
548 .type2 = _typ2, \
549 .handler = &gen_##name, \
550 .oname = onam, \
551 }, \
552 .oname = onam, \
553 }
554 #else
555 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
556 { \
557 .opc1 = op1, \
558 .opc2 = op2, \
559 .opc3 = op3, \
560 .pad = { 0, }, \
561 .handler = { \
562 .inval1 = invl, \
563 .type = _typ, \
564 .type2 = _typ2, \
565 .handler = &gen_##name, \
566 }, \
567 .oname = stringify(name), \
568 }
569 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
570 { \
571 .opc1 = op1, \
572 .opc2 = op2, \
573 .opc3 = op3, \
574 .pad = { 0, }, \
575 .handler = { \
576 .inval1 = invl1, \
577 .inval2 = invl2, \
578 .type = _typ, \
579 .type2 = _typ2, \
580 .handler = &gen_##name, \
581 }, \
582 .oname = stringify(name), \
583 }
584 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
585 { \
586 .opc1 = op1, \
587 .opc2 = op2, \
588 .opc3 = op3, \
589 .pad = { 0, }, \
590 .handler = { \
591 .inval1 = invl, \
592 .type = _typ, \
593 .type2 = _typ2, \
594 .handler = &gen_##name, \
595 }, \
596 .oname = onam, \
597 }
598 #endif
599
600 /* SPR load/store helpers */
601 static inline void gen_load_spr(TCGv t, int reg)
602 {
603 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
604 }
605
606 static inline void gen_store_spr(int reg, TCGv t)
607 {
608 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
609 }
610
611 /* Invalid instruction */
612 static void gen_invalid(DisasContext *ctx)
613 {
614 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
615 }
616
617 static opc_handler_t invalid_handler = {
618 .inval1 = 0xFFFFFFFF,
619 .inval2 = 0xFFFFFFFF,
620 .type = PPC_NONE,
621 .type2 = PPC_NONE,
622 .handler = gen_invalid,
623 };
624
625 /*** Integer comparison ***/
626
627 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
628 {
629 TCGv t0 = tcg_temp_new();
630 TCGv_i32 t1 = tcg_temp_new_i32();
631
632 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
633
634 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
635 tcg_gen_trunc_tl_i32(t1, t0);
636 tcg_gen_shli_i32(t1, t1, CRF_LT);
637 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
638
639 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
640 tcg_gen_trunc_tl_i32(t1, t0);
641 tcg_gen_shli_i32(t1, t1, CRF_GT);
642 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
643
644 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
645 tcg_gen_trunc_tl_i32(t1, t0);
646 tcg_gen_shli_i32(t1, t1, CRF_EQ);
647 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
648
649 tcg_temp_free(t0);
650 tcg_temp_free_i32(t1);
651 }
652
653 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
654 {
655 TCGv t0 = tcg_const_tl(arg1);
656 gen_op_cmp(arg0, t0, s, crf);
657 tcg_temp_free(t0);
658 }
659
660 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
661 {
662 TCGv t0, t1;
663 t0 = tcg_temp_new();
664 t1 = tcg_temp_new();
665 if (s) {
666 tcg_gen_ext32s_tl(t0, arg0);
667 tcg_gen_ext32s_tl(t1, arg1);
668 } else {
669 tcg_gen_ext32u_tl(t0, arg0);
670 tcg_gen_ext32u_tl(t1, arg1);
671 }
672 gen_op_cmp(t0, t1, s, crf);
673 tcg_temp_free(t1);
674 tcg_temp_free(t0);
675 }
676
677 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
678 {
679 TCGv t0 = tcg_const_tl(arg1);
680 gen_op_cmp32(arg0, t0, s, crf);
681 tcg_temp_free(t0);
682 }
683
684 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
685 {
686 if (NARROW_MODE(ctx)) {
687 gen_op_cmpi32(reg, 0, 1, 0);
688 } else {
689 gen_op_cmpi(reg, 0, 1, 0);
690 }
691 }
692
693 /* cmp */
694 static void gen_cmp(DisasContext *ctx)
695 {
696 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
697 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
698 1, crfD(ctx->opcode));
699 } else {
700 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
701 1, crfD(ctx->opcode));
702 }
703 }
704
705 /* cmpi */
706 static void gen_cmpi(DisasContext *ctx)
707 {
708 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
709 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
710 1, crfD(ctx->opcode));
711 } else {
712 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
713 1, crfD(ctx->opcode));
714 }
715 }
716
717 /* cmpl */
718 static void gen_cmpl(DisasContext *ctx)
719 {
720 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
721 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
722 0, crfD(ctx->opcode));
723 } else {
724 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
725 0, crfD(ctx->opcode));
726 }
727 }
728
729 /* cmpli */
730 static void gen_cmpli(DisasContext *ctx)
731 {
732 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
733 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
734 0, crfD(ctx->opcode));
735 } else {
736 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
737 0, crfD(ctx->opcode));
738 }
739 }
740
741 /* isel (PowerPC 2.03 specification) */
742 static void gen_isel(DisasContext *ctx)
743 {
744 int l1, l2;
745 uint32_t bi = rC(ctx->opcode);
746 uint32_t mask;
747 TCGv_i32 t0;
748
749 l1 = gen_new_label();
750 l2 = gen_new_label();
751
752 mask = 1 << (3 - (bi & 0x03));
753 t0 = tcg_temp_new_i32();
754 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
755 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
756 if (rA(ctx->opcode) == 0)
757 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
758 else
759 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
760 tcg_gen_br(l2);
761 gen_set_label(l1);
762 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
763 gen_set_label(l2);
764 tcg_temp_free_i32(t0);
765 }
766
767 /* cmpb: PowerPC 2.05 specification */
768 static void gen_cmpb(DisasContext *ctx)
769 {
770 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
771 cpu_gpr[rB(ctx->opcode)]);
772 }
773
774 /*** Integer arithmetic ***/
775
776 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
777 TCGv arg1, TCGv arg2, int sub)
778 {
779 TCGv t0 = tcg_temp_new();
780
781 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
782 tcg_gen_xor_tl(t0, arg1, arg2);
783 if (sub) {
784 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
785 } else {
786 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
787 }
788 tcg_temp_free(t0);
789 if (NARROW_MODE(ctx)) {
790 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
791 }
792 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
793 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
794 }
795
796 /* Common add function */
797 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
798 TCGv arg2, bool add_ca, bool compute_ca,
799 bool compute_ov, bool compute_rc0)
800 {
801 TCGv t0 = ret;
802
803 if (compute_ca || compute_ov) {
804 t0 = tcg_temp_new();
805 }
806
807 if (compute_ca) {
808 if (NARROW_MODE(ctx)) {
809 /* Caution: a non-obvious corner case of the spec is that we
810 must produce the *entire* 64-bit addition, but produce the
811 carry into bit 32. */
812 TCGv t1 = tcg_temp_new();
813 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
814 tcg_gen_add_tl(t0, arg1, arg2);
815 if (add_ca) {
816 tcg_gen_add_tl(t0, t0, cpu_ca);
817 }
818 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
819 tcg_temp_free(t1);
820 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
821 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
822 } else {
823 TCGv zero = tcg_const_tl(0);
824 if (add_ca) {
825 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
826 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
827 } else {
828 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
829 }
830 tcg_temp_free(zero);
831 }
832 } else {
833 tcg_gen_add_tl(t0, arg1, arg2);
834 if (add_ca) {
835 tcg_gen_add_tl(t0, t0, cpu_ca);
836 }
837 }
838
839 if (compute_ov) {
840 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
841 }
842 if (unlikely(compute_rc0)) {
843 gen_set_Rc0(ctx, t0);
844 }
845
846 if (!TCGV_EQUAL(t0, ret)) {
847 tcg_gen_mov_tl(ret, t0);
848 tcg_temp_free(t0);
849 }
850 }
851 /* Add functions with two operands */
852 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
853 static void glue(gen_, name)(DisasContext *ctx) \
854 { \
855 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
856 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
857 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
858 }
859 /* Add functions with one operand and one immediate */
860 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
861 add_ca, compute_ca, compute_ov) \
862 static void glue(gen_, name)(DisasContext *ctx) \
863 { \
864 TCGv t0 = tcg_const_tl(const_val); \
865 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
866 cpu_gpr[rA(ctx->opcode)], t0, \
867 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
868 tcg_temp_free(t0); \
869 }
870
871 /* add add. addo addo. */
872 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
873 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
874 /* addc addc. addco addco. */
875 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
876 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
877 /* adde adde. addeo addeo. */
878 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
879 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
880 /* addme addme. addmeo addmeo. */
881 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
882 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
883 /* addze addze. addzeo addzeo.*/
884 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
885 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
886 /* addi */
887 static void gen_addi(DisasContext *ctx)
888 {
889 target_long simm = SIMM(ctx->opcode);
890
891 if (rA(ctx->opcode) == 0) {
892 /* li case */
893 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
894 } else {
895 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
896 cpu_gpr[rA(ctx->opcode)], simm);
897 }
898 }
899 /* addic addic.*/
900 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
901 {
902 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
903 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
904 c, 0, 1, 0, compute_rc0);
905 tcg_temp_free(c);
906 }
907
908 static void gen_addic(DisasContext *ctx)
909 {
910 gen_op_addic(ctx, 0);
911 }
912
913 static void gen_addic_(DisasContext *ctx)
914 {
915 gen_op_addic(ctx, 1);
916 }
917
918 /* addis */
919 static void gen_addis(DisasContext *ctx)
920 {
921 target_long simm = SIMM(ctx->opcode);
922
923 if (rA(ctx->opcode) == 0) {
924 /* lis case */
925 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
926 } else {
927 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
928 cpu_gpr[rA(ctx->opcode)], simm << 16);
929 }
930 }
931
932 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
933 TCGv arg2, int sign, int compute_ov)
934 {
935 int l1 = gen_new_label();
936 int l2 = gen_new_label();
937 TCGv_i32 t0 = tcg_temp_local_new_i32();
938 TCGv_i32 t1 = tcg_temp_local_new_i32();
939
940 tcg_gen_trunc_tl_i32(t0, arg1);
941 tcg_gen_trunc_tl_i32(t1, arg2);
942 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
943 if (sign) {
944 int l3 = gen_new_label();
945 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
946 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
947 gen_set_label(l3);
948 tcg_gen_div_i32(t0, t0, t1);
949 } else {
950 tcg_gen_divu_i32(t0, t0, t1);
951 }
952 if (compute_ov) {
953 tcg_gen_movi_tl(cpu_ov, 0);
954 }
955 tcg_gen_br(l2);
956 gen_set_label(l1);
957 if (sign) {
958 tcg_gen_sari_i32(t0, t0, 31);
959 } else {
960 tcg_gen_movi_i32(t0, 0);
961 }
962 if (compute_ov) {
963 tcg_gen_movi_tl(cpu_ov, 1);
964 tcg_gen_movi_tl(cpu_so, 1);
965 }
966 gen_set_label(l2);
967 tcg_gen_extu_i32_tl(ret, t0);
968 tcg_temp_free_i32(t0);
969 tcg_temp_free_i32(t1);
970 if (unlikely(Rc(ctx->opcode) != 0))
971 gen_set_Rc0(ctx, ret);
972 }
973 /* Div functions */
974 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
975 static void glue(gen_, name)(DisasContext *ctx) \
976 { \
977 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
978 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
979 sign, compute_ov); \
980 }
981 /* divwu divwu. divwuo divwuo. */
982 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
983 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
984 /* divw divw. divwo divwo. */
985 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
986 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
987 #if defined(TARGET_PPC64)
988 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
989 TCGv arg2, int sign, int compute_ov)
990 {
991 int l1 = gen_new_label();
992 int l2 = gen_new_label();
993
994 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
995 if (sign) {
996 int l3 = gen_new_label();
997 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
998 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
999 gen_set_label(l3);
1000 tcg_gen_div_i64(ret, arg1, arg2);
1001 } else {
1002 tcg_gen_divu_i64(ret, arg1, arg2);
1003 }
1004 if (compute_ov) {
1005 tcg_gen_movi_tl(cpu_ov, 0);
1006 }
1007 tcg_gen_br(l2);
1008 gen_set_label(l1);
1009 if (sign) {
1010 tcg_gen_sari_i64(ret, arg1, 63);
1011 } else {
1012 tcg_gen_movi_i64(ret, 0);
1013 }
1014 if (compute_ov) {
1015 tcg_gen_movi_tl(cpu_ov, 1);
1016 tcg_gen_movi_tl(cpu_so, 1);
1017 }
1018 gen_set_label(l2);
1019 if (unlikely(Rc(ctx->opcode) != 0))
1020 gen_set_Rc0(ctx, ret);
1021 }
1022 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1023 static void glue(gen_, name)(DisasContext *ctx) \
1024 { \
1025 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1026 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1027 sign, compute_ov); \
1028 }
1029 /* divwu divwu. divwuo divwuo. */
1030 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1031 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1032 /* divw divw. divwo divwo. */
1033 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1034 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1035 #endif
1036
1037 /* mulhw mulhw. */
1038 static void gen_mulhw(DisasContext *ctx)
1039 {
1040 TCGv_i32 t0 = tcg_temp_new_i32();
1041 TCGv_i32 t1 = tcg_temp_new_i32();
1042
1043 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1044 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1045 tcg_gen_muls2_i32(t0, t1, t0, t1);
1046 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1047 tcg_temp_free_i32(t0);
1048 tcg_temp_free_i32(t1);
1049 if (unlikely(Rc(ctx->opcode) != 0))
1050 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1051 }
1052
1053 /* mulhwu mulhwu. */
1054 static void gen_mulhwu(DisasContext *ctx)
1055 {
1056 TCGv_i32 t0 = tcg_temp_new_i32();
1057 TCGv_i32 t1 = tcg_temp_new_i32();
1058
1059 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1060 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1061 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1062 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1063 tcg_temp_free_i32(t0);
1064 tcg_temp_free_i32(t1);
1065 if (unlikely(Rc(ctx->opcode) != 0))
1066 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1067 }
1068
1069 /* mullw mullw. */
1070 static void gen_mullw(DisasContext *ctx)
1071 {
1072 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1073 cpu_gpr[rB(ctx->opcode)]);
1074 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1075 if (unlikely(Rc(ctx->opcode) != 0))
1076 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1077 }
1078
1079 /* mullwo mullwo. */
1080 static void gen_mullwo(DisasContext *ctx)
1081 {
1082 TCGv_i32 t0 = tcg_temp_new_i32();
1083 TCGv_i32 t1 = tcg_temp_new_i32();
1084
1085 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1086 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1087 tcg_gen_muls2_i32(t0, t1, t0, t1);
1088 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1089
1090 tcg_gen_sari_i32(t0, t0, 31);
1091 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1092 tcg_gen_extu_i32_tl(cpu_ov, t0);
1093 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1094
1095 tcg_temp_free_i32(t0);
1096 tcg_temp_free_i32(t1);
1097 if (unlikely(Rc(ctx->opcode) != 0))
1098 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1099 }
1100
1101 /* mulli */
1102 static void gen_mulli(DisasContext *ctx)
1103 {
1104 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1105 SIMM(ctx->opcode));
1106 }
1107
1108 #if defined(TARGET_PPC64)
1109 /* mulhd mulhd. */
1110 static void gen_mulhd(DisasContext *ctx)
1111 {
1112 TCGv lo = tcg_temp_new();
1113 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1114 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1115 tcg_temp_free(lo);
1116 if (unlikely(Rc(ctx->opcode) != 0)) {
1117 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1118 }
1119 }
1120
1121 /* mulhdu mulhdu. */
1122 static void gen_mulhdu(DisasContext *ctx)
1123 {
1124 TCGv lo = tcg_temp_new();
1125 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1126 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1127 tcg_temp_free(lo);
1128 if (unlikely(Rc(ctx->opcode) != 0)) {
1129 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1130 }
1131 }
1132
1133 /* mulld mulld. */
1134 static void gen_mulld(DisasContext *ctx)
1135 {
1136 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1137 cpu_gpr[rB(ctx->opcode)]);
1138 if (unlikely(Rc(ctx->opcode) != 0))
1139 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1140 }
1141
1142 /* mulldo mulldo. */
1143 static void gen_mulldo(DisasContext *ctx)
1144 {
1145 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1146 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1147 if (unlikely(Rc(ctx->opcode) != 0)) {
1148 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1149 }
1150 }
1151 #endif
1152
1153 /* Common subf function */
1154 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1155 TCGv arg2, bool add_ca, bool compute_ca,
1156 bool compute_ov, bool compute_rc0)
1157 {
1158 TCGv t0 = ret;
1159
1160 if (compute_ca || compute_ov) {
1161 t0 = tcg_temp_new();
1162 }
1163
1164 if (compute_ca) {
1165 /* dest = ~arg1 + arg2 [+ ca]. */
1166 if (NARROW_MODE(ctx)) {
1167 /* Caution: a non-obvious corner case of the spec is that we
1168 must produce the *entire* 64-bit addition, but produce the
1169 carry into bit 32. */
1170 TCGv inv1 = tcg_temp_new();
1171 TCGv t1 = tcg_temp_new();
1172 tcg_gen_not_tl(inv1, arg1);
1173 if (add_ca) {
1174 tcg_gen_add_tl(t0, arg2, cpu_ca);
1175 } else {
1176 tcg_gen_addi_tl(t0, arg2, 1);
1177 }
1178 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1179 tcg_gen_add_tl(t0, t0, inv1);
1180 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1181 tcg_temp_free(t1);
1182 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1183 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1184 } else if (add_ca) {
1185 TCGv zero, inv1 = tcg_temp_new();
1186 tcg_gen_not_tl(inv1, arg1);
1187 zero = tcg_const_tl(0);
1188 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1189 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1190 tcg_temp_free(zero);
1191 tcg_temp_free(inv1);
1192 } else {
1193 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1194 tcg_gen_sub_tl(t0, arg2, arg1);
1195 }
1196 } else if (add_ca) {
1197 /* Since we're ignoring carry-out, we can simplify the
1198 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1199 tcg_gen_sub_tl(t0, arg2, arg1);
1200 tcg_gen_add_tl(t0, t0, cpu_ca);
1201 tcg_gen_subi_tl(t0, t0, 1);
1202 } else {
1203 tcg_gen_sub_tl(t0, arg2, arg1);
1204 }
1205
1206 if (compute_ov) {
1207 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1208 }
1209 if (unlikely(compute_rc0)) {
1210 gen_set_Rc0(ctx, t0);
1211 }
1212
1213 if (!TCGV_EQUAL(t0, ret)) {
1214 tcg_gen_mov_tl(ret, t0);
1215 tcg_temp_free(t0);
1216 }
1217 }
1218 /* Sub functions with Two operands functions */
1219 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1220 static void glue(gen_, name)(DisasContext *ctx) \
1221 { \
1222 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1223 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1224 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1225 }
1226 /* Sub functions with one operand and one immediate */
1227 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1228 add_ca, compute_ca, compute_ov) \
1229 static void glue(gen_, name)(DisasContext *ctx) \
1230 { \
1231 TCGv t0 = tcg_const_tl(const_val); \
1232 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1233 cpu_gpr[rA(ctx->opcode)], t0, \
1234 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1235 tcg_temp_free(t0); \
1236 }
1237 /* subf subf. subfo subfo. */
1238 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1239 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1240 /* subfc subfc. subfco subfco. */
1241 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1242 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1243 /* subfe subfe. subfeo subfo. */
1244 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1245 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1246 /* subfme subfme. subfmeo subfmeo. */
1247 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1248 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1249 /* subfze subfze. subfzeo subfzeo.*/
1250 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1251 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1252
1253 /* subfic */
1254 static void gen_subfic(DisasContext *ctx)
1255 {
1256 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1257 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1258 c, 0, 1, 0, 0);
1259 tcg_temp_free(c);
1260 }
1261
1262 /* neg neg. nego nego. */
1263 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1264 {
1265 TCGv zero = tcg_const_tl(0);
1266 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1267 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1268 tcg_temp_free(zero);
1269 }
1270
1271 static void gen_neg(DisasContext *ctx)
1272 {
1273 gen_op_arith_neg(ctx, 0);
1274 }
1275
1276 static void gen_nego(DisasContext *ctx)
1277 {
1278 gen_op_arith_neg(ctx, 1);
1279 }
1280
1281 /*** Integer logical ***/
1282 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1283 static void glue(gen_, name)(DisasContext *ctx) \
1284 { \
1285 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1286 cpu_gpr[rB(ctx->opcode)]); \
1287 if (unlikely(Rc(ctx->opcode) != 0)) \
1288 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1289 }
1290
1291 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1292 static void glue(gen_, name)(DisasContext *ctx) \
1293 { \
1294 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1295 if (unlikely(Rc(ctx->opcode) != 0)) \
1296 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1297 }
1298
1299 /* and & and. */
1300 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1301 /* andc & andc. */
1302 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1303
1304 /* andi. */
1305 static void gen_andi_(DisasContext *ctx)
1306 {
1307 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1308 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1309 }
1310
1311 /* andis. */
1312 static void gen_andis_(DisasContext *ctx)
1313 {
1314 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1315 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1316 }
1317
1318 /* cntlzw */
1319 static void gen_cntlzw(DisasContext *ctx)
1320 {
1321 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1322 if (unlikely(Rc(ctx->opcode) != 0))
1323 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1324 }
1325 /* eqv & eqv. */
1326 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1327 /* extsb & extsb. */
1328 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1329 /* extsh & extsh. */
1330 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1331 /* nand & nand. */
1332 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1333 /* nor & nor. */
1334 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1335
1336 /* or & or. */
1337 static void gen_or(DisasContext *ctx)
1338 {
1339 int rs, ra, rb;
1340
1341 rs = rS(ctx->opcode);
1342 ra = rA(ctx->opcode);
1343 rb = rB(ctx->opcode);
1344 /* Optimisation for mr. ri case */
1345 if (rs != ra || rs != rb) {
1346 if (rs != rb)
1347 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1348 else
1349 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1350 if (unlikely(Rc(ctx->opcode) != 0))
1351 gen_set_Rc0(ctx, cpu_gpr[ra]);
1352 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1353 gen_set_Rc0(ctx, cpu_gpr[rs]);
1354 #if defined(TARGET_PPC64)
1355 } else {
1356 int prio = 0;
1357
1358 switch (rs) {
1359 case 1:
1360 /* Set process priority to low */
1361 prio = 2;
1362 break;
1363 case 6:
1364 /* Set process priority to medium-low */
1365 prio = 3;
1366 break;
1367 case 2:
1368 /* Set process priority to normal */
1369 prio = 4;
1370 break;
1371 #if !defined(CONFIG_USER_ONLY)
1372 case 31:
1373 if (ctx->mem_idx > 0) {
1374 /* Set process priority to very low */
1375 prio = 1;
1376 }
1377 break;
1378 case 5:
1379 if (ctx->mem_idx > 0) {
1380 /* Set process priority to medium-hight */
1381 prio = 5;
1382 }
1383 break;
1384 case 3:
1385 if (ctx->mem_idx > 0) {
1386 /* Set process priority to high */
1387 prio = 6;
1388 }
1389 break;
1390 case 7:
1391 if (ctx->mem_idx > 1) {
1392 /* Set process priority to very high */
1393 prio = 7;
1394 }
1395 break;
1396 #endif
1397 default:
1398 /* nop */
1399 break;
1400 }
1401 if (prio) {
1402 TCGv t0 = tcg_temp_new();
1403 gen_load_spr(t0, SPR_PPR);
1404 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1405 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1406 gen_store_spr(SPR_PPR, t0);
1407 tcg_temp_free(t0);
1408 }
1409 #endif
1410 }
1411 }
1412 /* orc & orc. */
1413 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1414
1415 /* xor & xor. */
1416 static void gen_xor(DisasContext *ctx)
1417 {
1418 /* Optimisation for "set to zero" case */
1419 if (rS(ctx->opcode) != rB(ctx->opcode))
1420 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1421 else
1422 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1423 if (unlikely(Rc(ctx->opcode) != 0))
1424 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1425 }
1426
1427 /* ori */
1428 static void gen_ori(DisasContext *ctx)
1429 {
1430 target_ulong uimm = UIMM(ctx->opcode);
1431
1432 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1433 /* NOP */
1434 /* XXX: should handle special NOPs for POWER series */
1435 return;
1436 }
1437 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1438 }
1439
1440 /* oris */
1441 static void gen_oris(DisasContext *ctx)
1442 {
1443 target_ulong uimm = UIMM(ctx->opcode);
1444
1445 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1446 /* NOP */
1447 return;
1448 }
1449 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1450 }
1451
1452 /* xori */
1453 static void gen_xori(DisasContext *ctx)
1454 {
1455 target_ulong uimm = UIMM(ctx->opcode);
1456
1457 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1458 /* NOP */
1459 return;
1460 }
1461 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1462 }
1463
1464 /* xoris */
1465 static void gen_xoris(DisasContext *ctx)
1466 {
1467 target_ulong uimm = UIMM(ctx->opcode);
1468
1469 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1470 /* NOP */
1471 return;
1472 }
1473 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1474 }
1475
1476 /* popcntb : PowerPC 2.03 specification */
1477 static void gen_popcntb(DisasContext *ctx)
1478 {
1479 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1480 }
1481
1482 static void gen_popcntw(DisasContext *ctx)
1483 {
1484 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1485 }
1486
1487 #if defined(TARGET_PPC64)
1488 /* popcntd: PowerPC 2.06 specification */
1489 static void gen_popcntd(DisasContext *ctx)
1490 {
1491 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1492 }
1493 #endif
1494
1495 /* prtyw: PowerPC 2.05 specification */
1496 static void gen_prtyw(DisasContext *ctx)
1497 {
1498 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1499 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1500 TCGv t0 = tcg_temp_new();
1501 tcg_gen_shri_tl(t0, rs, 16);
1502 tcg_gen_xor_tl(ra, rs, t0);
1503 tcg_gen_shri_tl(t0, ra, 8);
1504 tcg_gen_xor_tl(ra, ra, t0);
1505 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1506 tcg_temp_free(t0);
1507 }
1508
1509 #if defined(TARGET_PPC64)
1510 /* prtyd: PowerPC 2.05 specification */
1511 static void gen_prtyd(DisasContext *ctx)
1512 {
1513 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1514 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1515 TCGv t0 = tcg_temp_new();
1516 tcg_gen_shri_tl(t0, rs, 32);
1517 tcg_gen_xor_tl(ra, rs, t0);
1518 tcg_gen_shri_tl(t0, ra, 16);
1519 tcg_gen_xor_tl(ra, ra, t0);
1520 tcg_gen_shri_tl(t0, ra, 8);
1521 tcg_gen_xor_tl(ra, ra, t0);
1522 tcg_gen_andi_tl(ra, ra, 1);
1523 tcg_temp_free(t0);
1524 }
1525 #endif
1526
1527 #if defined(TARGET_PPC64)
1528 /* extsw & extsw. */
1529 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1530
1531 /* cntlzd */
1532 static void gen_cntlzd(DisasContext *ctx)
1533 {
1534 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1535 if (unlikely(Rc(ctx->opcode) != 0))
1536 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1537 }
1538 #endif
1539
1540 /*** Integer rotate ***/
1541
1542 /* rlwimi & rlwimi. */
1543 static void gen_rlwimi(DisasContext *ctx)
1544 {
1545 uint32_t mb, me, sh;
1546
1547 mb = MB(ctx->opcode);
1548 me = ME(ctx->opcode);
1549 sh = SH(ctx->opcode);
1550 if (likely(sh == 0 && mb == 0 && me == 31)) {
1551 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1552 } else {
1553 target_ulong mask;
1554 TCGv t1;
1555 TCGv t0 = tcg_temp_new();
1556 #if defined(TARGET_PPC64)
1557 TCGv_i32 t2 = tcg_temp_new_i32();
1558 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1559 tcg_gen_rotli_i32(t2, t2, sh);
1560 tcg_gen_extu_i32_i64(t0, t2);
1561 tcg_temp_free_i32(t2);
1562 #else
1563 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1564 #endif
1565 #if defined(TARGET_PPC64)
1566 mb += 32;
1567 me += 32;
1568 #endif
1569 mask = MASK(mb, me);
1570 t1 = tcg_temp_new();
1571 tcg_gen_andi_tl(t0, t0, mask);
1572 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1573 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1574 tcg_temp_free(t0);
1575 tcg_temp_free(t1);
1576 }
1577 if (unlikely(Rc(ctx->opcode) != 0))
1578 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1579 }
1580
1581 /* rlwinm & rlwinm. */
1582 static void gen_rlwinm(DisasContext *ctx)
1583 {
1584 uint32_t mb, me, sh;
1585
1586 sh = SH(ctx->opcode);
1587 mb = MB(ctx->opcode);
1588 me = ME(ctx->opcode);
1589
1590 if (likely(mb == 0 && me == (31 - sh))) {
1591 if (likely(sh == 0)) {
1592 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1593 } else {
1594 TCGv t0 = tcg_temp_new();
1595 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1596 tcg_gen_shli_tl(t0, t0, sh);
1597 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1598 tcg_temp_free(t0);
1599 }
1600 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1601 TCGv t0 = tcg_temp_new();
1602 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1603 tcg_gen_shri_tl(t0, t0, mb);
1604 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1605 tcg_temp_free(t0);
1606 } else {
1607 TCGv t0 = tcg_temp_new();
1608 #if defined(TARGET_PPC64)
1609 TCGv_i32 t1 = tcg_temp_new_i32();
1610 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1611 tcg_gen_rotli_i32(t1, t1, sh);
1612 tcg_gen_extu_i32_i64(t0, t1);
1613 tcg_temp_free_i32(t1);
1614 #else
1615 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1616 #endif
1617 #if defined(TARGET_PPC64)
1618 mb += 32;
1619 me += 32;
1620 #endif
1621 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1622 tcg_temp_free(t0);
1623 }
1624 if (unlikely(Rc(ctx->opcode) != 0))
1625 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1626 }
1627
1628 /* rlwnm & rlwnm. */
1629 static void gen_rlwnm(DisasContext *ctx)
1630 {
1631 uint32_t mb, me;
1632 TCGv t0;
1633 #if defined(TARGET_PPC64)
1634 TCGv_i32 t1, t2;
1635 #endif
1636
1637 mb = MB(ctx->opcode);
1638 me = ME(ctx->opcode);
1639 t0 = tcg_temp_new();
1640 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1641 #if defined(TARGET_PPC64)
1642 t1 = tcg_temp_new_i32();
1643 t2 = tcg_temp_new_i32();
1644 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1645 tcg_gen_trunc_i64_i32(t2, t0);
1646 tcg_gen_rotl_i32(t1, t1, t2);
1647 tcg_gen_extu_i32_i64(t0, t1);
1648 tcg_temp_free_i32(t1);
1649 tcg_temp_free_i32(t2);
1650 #else
1651 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1652 #endif
1653 if (unlikely(mb != 0 || me != 31)) {
1654 #if defined(TARGET_PPC64)
1655 mb += 32;
1656 me += 32;
1657 #endif
1658 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1659 } else {
1660 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1661 }
1662 tcg_temp_free(t0);
1663 if (unlikely(Rc(ctx->opcode) != 0))
1664 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1665 }
1666
1667 #if defined(TARGET_PPC64)
1668 #define GEN_PPC64_R2(name, opc1, opc2) \
1669 static void glue(gen_, name##0)(DisasContext *ctx) \
1670 { \
1671 gen_##name(ctx, 0); \
1672 } \
1673 \
1674 static void glue(gen_, name##1)(DisasContext *ctx) \
1675 { \
1676 gen_##name(ctx, 1); \
1677 }
1678 #define GEN_PPC64_R4(name, opc1, opc2) \
1679 static void glue(gen_, name##0)(DisasContext *ctx) \
1680 { \
1681 gen_##name(ctx, 0, 0); \
1682 } \
1683 \
1684 static void glue(gen_, name##1)(DisasContext *ctx) \
1685 { \
1686 gen_##name(ctx, 0, 1); \
1687 } \
1688 \
1689 static void glue(gen_, name##2)(DisasContext *ctx) \
1690 { \
1691 gen_##name(ctx, 1, 0); \
1692 } \
1693 \
1694 static void glue(gen_, name##3)(DisasContext *ctx) \
1695 { \
1696 gen_##name(ctx, 1, 1); \
1697 }
1698
1699 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1700 uint32_t sh)
1701 {
1702 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1703 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1704 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1705 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1706 } else {
1707 TCGv t0 = tcg_temp_new();
1708 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1709 if (likely(mb == 0 && me == 63)) {
1710 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1711 } else {
1712 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1713 }
1714 tcg_temp_free(t0);
1715 }
1716 if (unlikely(Rc(ctx->opcode) != 0))
1717 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1718 }
1719 /* rldicl - rldicl. */
1720 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1721 {
1722 uint32_t sh, mb;
1723
1724 sh = SH(ctx->opcode) | (shn << 5);
1725 mb = MB(ctx->opcode) | (mbn << 5);
1726 gen_rldinm(ctx, mb, 63, sh);
1727 }
1728 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1729 /* rldicr - rldicr. */
1730 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1731 {
1732 uint32_t sh, me;
1733
1734 sh = SH(ctx->opcode) | (shn << 5);
1735 me = MB(ctx->opcode) | (men << 5);
1736 gen_rldinm(ctx, 0, me, sh);
1737 }
1738 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1739 /* rldic - rldic. */
1740 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1741 {
1742 uint32_t sh, mb;
1743
1744 sh = SH(ctx->opcode) | (shn << 5);
1745 mb = MB(ctx->opcode) | (mbn << 5);
1746 gen_rldinm(ctx, mb, 63 - sh, sh);
1747 }
1748 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1749
1750 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1751 {
1752 TCGv t0;
1753
1754 t0 = tcg_temp_new();
1755 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1756 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1757 if (unlikely(mb != 0 || me != 63)) {
1758 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1759 } else {
1760 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1761 }
1762 tcg_temp_free(t0);
1763 if (unlikely(Rc(ctx->opcode) != 0))
1764 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1765 }
1766
1767 /* rldcl - rldcl. */
1768 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1769 {
1770 uint32_t mb;
1771
1772 mb = MB(ctx->opcode) | (mbn << 5);
1773 gen_rldnm(ctx, mb, 63);
1774 }
1775 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1776 /* rldcr - rldcr. */
1777 static inline void gen_rldcr(DisasContext *ctx, int men)
1778 {
1779 uint32_t me;
1780
1781 me = MB(ctx->opcode) | (men << 5);
1782 gen_rldnm(ctx, 0, me);
1783 }
1784 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1785 /* rldimi - rldimi. */
1786 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1787 {
1788 uint32_t sh, mb, me;
1789
1790 sh = SH(ctx->opcode) | (shn << 5);
1791 mb = MB(ctx->opcode) | (mbn << 5);
1792 me = 63 - sh;
1793 if (unlikely(sh == 0 && mb == 0)) {
1794 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1795 } else {
1796 TCGv t0, t1;
1797 target_ulong mask;
1798
1799 t0 = tcg_temp_new();
1800 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1801 t1 = tcg_temp_new();
1802 mask = MASK(mb, me);
1803 tcg_gen_andi_tl(t0, t0, mask);
1804 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1805 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1806 tcg_temp_free(t0);
1807 tcg_temp_free(t1);
1808 }
1809 if (unlikely(Rc(ctx->opcode) != 0))
1810 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1811 }
1812 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1813 #endif
1814
1815 /*** Integer shift ***/
1816
1817 /* slw & slw. */
1818 static void gen_slw(DisasContext *ctx)
1819 {
1820 TCGv t0, t1;
1821
1822 t0 = tcg_temp_new();
1823 /* AND rS with a mask that is 0 when rB >= 0x20 */
1824 #if defined(TARGET_PPC64)
1825 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1826 tcg_gen_sari_tl(t0, t0, 0x3f);
1827 #else
1828 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1829 tcg_gen_sari_tl(t0, t0, 0x1f);
1830 #endif
1831 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1832 t1 = tcg_temp_new();
1833 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1834 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1835 tcg_temp_free(t1);
1836 tcg_temp_free(t0);
1837 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1838 if (unlikely(Rc(ctx->opcode) != 0))
1839 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1840 }
1841
1842 /* sraw & sraw. */
1843 static void gen_sraw(DisasContext *ctx)
1844 {
1845 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1846 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1847 if (unlikely(Rc(ctx->opcode) != 0))
1848 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1849 }
1850
1851 /* srawi & srawi. */
1852 static void gen_srawi(DisasContext *ctx)
1853 {
1854 int sh = SH(ctx->opcode);
1855 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1856 TCGv src = cpu_gpr[rS(ctx->opcode)];
1857 if (sh == 0) {
1858 tcg_gen_mov_tl(dst, src);
1859 tcg_gen_movi_tl(cpu_ca, 0);
1860 } else {
1861 TCGv t0;
1862 tcg_gen_ext32s_tl(dst, src);
1863 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1864 t0 = tcg_temp_new();
1865 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1866 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1867 tcg_temp_free(t0);
1868 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1869 tcg_gen_sari_tl(dst, dst, sh);
1870 }
1871 if (unlikely(Rc(ctx->opcode) != 0)) {
1872 gen_set_Rc0(ctx, dst);
1873 }
1874 }
1875
1876 /* srw & srw. */
1877 static void gen_srw(DisasContext *ctx)
1878 {
1879 TCGv t0, t1;
1880
1881 t0 = tcg_temp_new();
1882 /* AND rS with a mask that is 0 when rB >= 0x20 */
1883 #if defined(TARGET_PPC64)
1884 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1885 tcg_gen_sari_tl(t0, t0, 0x3f);
1886 #else
1887 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1888 tcg_gen_sari_tl(t0, t0, 0x1f);
1889 #endif
1890 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1891 tcg_gen_ext32u_tl(t0, t0);
1892 t1 = tcg_temp_new();
1893 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1894 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1895 tcg_temp_free(t1);
1896 tcg_temp_free(t0);
1897 if (unlikely(Rc(ctx->opcode) != 0))
1898 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1899 }
1900
1901 #if defined(TARGET_PPC64)
1902 /* sld & sld. */
1903 static void gen_sld(DisasContext *ctx)
1904 {
1905 TCGv t0, t1;
1906
1907 t0 = tcg_temp_new();
1908 /* AND rS with a mask that is 0 when rB >= 0x40 */
1909 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1910 tcg_gen_sari_tl(t0, t0, 0x3f);
1911 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1912 t1 = tcg_temp_new();
1913 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1914 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1915 tcg_temp_free(t1);
1916 tcg_temp_free(t0);
1917 if (unlikely(Rc(ctx->opcode) != 0))
1918 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1919 }
1920
1921 /* srad & srad. */
1922 static void gen_srad(DisasContext *ctx)
1923 {
1924 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1925 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1926 if (unlikely(Rc(ctx->opcode) != 0))
1927 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1928 }
1929 /* sradi & sradi. */
1930 static inline void gen_sradi(DisasContext *ctx, int n)
1931 {
1932 int sh = SH(ctx->opcode) + (n << 5);
1933 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1934 TCGv src = cpu_gpr[rS(ctx->opcode)];
1935 if (sh == 0) {
1936 tcg_gen_mov_tl(dst, src);
1937 tcg_gen_movi_tl(cpu_ca, 0);
1938 } else {
1939 TCGv t0;
1940 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1941 t0 = tcg_temp_new();
1942 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1943 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1944 tcg_temp_free(t0);
1945 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1946 tcg_gen_sari_tl(dst, src, sh);
1947 }
1948 if (unlikely(Rc(ctx->opcode) != 0)) {
1949 gen_set_Rc0(ctx, dst);
1950 }
1951 }
1952
1953 static void gen_sradi0(DisasContext *ctx)
1954 {
1955 gen_sradi(ctx, 0);
1956 }
1957
1958 static void gen_sradi1(DisasContext *ctx)
1959 {
1960 gen_sradi(ctx, 1);
1961 }
1962
1963 /* srd & srd. */
1964 static void gen_srd(DisasContext *ctx)
1965 {
1966 TCGv t0, t1;
1967
1968 t0 = tcg_temp_new();
1969 /* AND rS with a mask that is 0 when rB >= 0x40 */
1970 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1971 tcg_gen_sari_tl(t0, t0, 0x3f);
1972 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1973 t1 = tcg_temp_new();
1974 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1975 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1976 tcg_temp_free(t1);
1977 tcg_temp_free(t0);
1978 if (unlikely(Rc(ctx->opcode) != 0))
1979 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1980 }
1981 #endif
1982
1983 /*** Floating-Point arithmetic ***/
1984 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1985 static void gen_f##name(DisasContext *ctx) \
1986 { \
1987 if (unlikely(!ctx->fpu_enabled)) { \
1988 gen_exception(ctx, POWERPC_EXCP_FPU); \
1989 return; \
1990 } \
1991 /* NIP cannot be restored if the memory exception comes from an helper */ \
1992 gen_update_nip(ctx, ctx->nip - 4); \
1993 gen_reset_fpstatus(); \
1994 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1995 cpu_fpr[rA(ctx->opcode)], \
1996 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1997 if (isfloat) { \
1998 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1999 cpu_fpr[rD(ctx->opcode)]); \
2000 } \
2001 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2002 Rc(ctx->opcode) != 0); \
2003 }
2004
2005 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2006 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2007 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2008
2009 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2010 static void gen_f##name(DisasContext *ctx) \
2011 { \
2012 if (unlikely(!ctx->fpu_enabled)) { \
2013 gen_exception(ctx, POWERPC_EXCP_FPU); \
2014 return; \
2015 } \
2016 /* NIP cannot be restored if the memory exception comes from an helper */ \
2017 gen_update_nip(ctx, ctx->nip - 4); \
2018 gen_reset_fpstatus(); \
2019 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2020 cpu_fpr[rA(ctx->opcode)], \
2021 cpu_fpr[rB(ctx->opcode)]); \
2022 if (isfloat) { \
2023 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2024 cpu_fpr[rD(ctx->opcode)]); \
2025 } \
2026 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2027 set_fprf, Rc(ctx->opcode) != 0); \
2028 }
2029 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2030 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2031 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2032
2033 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2034 static void gen_f##name(DisasContext *ctx) \
2035 { \
2036 if (unlikely(!ctx->fpu_enabled)) { \
2037 gen_exception(ctx, POWERPC_EXCP_FPU); \
2038 return; \
2039 } \
2040 /* NIP cannot be restored if the memory exception comes from an helper */ \
2041 gen_update_nip(ctx, ctx->nip - 4); \
2042 gen_reset_fpstatus(); \
2043 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2044 cpu_fpr[rA(ctx->opcode)], \
2045 cpu_fpr[rC(ctx->opcode)]); \
2046 if (isfloat) { \
2047 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2048 cpu_fpr[rD(ctx->opcode)]); \
2049 } \
2050 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2051 set_fprf, Rc(ctx->opcode) != 0); \
2052 }
2053 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2054 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2055 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2056
2057 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2058 static void gen_f##name(DisasContext *ctx) \
2059 { \
2060 if (unlikely(!ctx->fpu_enabled)) { \
2061 gen_exception(ctx, POWERPC_EXCP_FPU); \
2062 return; \
2063 } \
2064 /* NIP cannot be restored if the memory exception comes from an helper */ \
2065 gen_update_nip(ctx, ctx->nip - 4); \
2066 gen_reset_fpstatus(); \
2067 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2068 cpu_fpr[rB(ctx->opcode)]); \
2069 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2070 set_fprf, Rc(ctx->opcode) != 0); \
2071 }
2072
2073 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2074 static void gen_f##name(DisasContext *ctx) \
2075 { \
2076 if (unlikely(!ctx->fpu_enabled)) { \
2077 gen_exception(ctx, POWERPC_EXCP_FPU); \
2078 return; \
2079 } \
2080 /* NIP cannot be restored if the memory exception comes from an helper */ \
2081 gen_update_nip(ctx, ctx->nip - 4); \
2082 gen_reset_fpstatus(); \
2083 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2084 cpu_fpr[rB(ctx->opcode)]); \
2085 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2086 set_fprf, Rc(ctx->opcode) != 0); \
2087 }
2088
2089 /* fadd - fadds */
2090 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2091 /* fdiv - fdivs */
2092 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2093 /* fmul - fmuls */
2094 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2095
2096 /* fre */
2097 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2098
2099 /* fres */
2100 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2101
2102 /* frsqrte */
2103 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2104
2105 /* frsqrtes */
2106 static void gen_frsqrtes(DisasContext *ctx)
2107 {
2108 if (unlikely(!ctx->fpu_enabled)) {
2109 gen_exception(ctx, POWERPC_EXCP_FPU);
2110 return;
2111 }
2112 /* NIP cannot be restored if the memory exception comes from an helper */
2113 gen_update_nip(ctx, ctx->nip - 4);
2114 gen_reset_fpstatus();
2115 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2116 cpu_fpr[rB(ctx->opcode)]);
2117 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2118 cpu_fpr[rD(ctx->opcode)]);
2119 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2120 }
2121
2122 /* fsel */
2123 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2124 /* fsub - fsubs */
2125 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2126 /* Optional: */
2127
2128 /* fsqrt */
2129 static void gen_fsqrt(DisasContext *ctx)
2130 {
2131 if (unlikely(!ctx->fpu_enabled)) {
2132 gen_exception(ctx, POWERPC_EXCP_FPU);
2133 return;
2134 }
2135 /* NIP cannot be restored if the memory exception comes from an helper */
2136 gen_update_nip(ctx, ctx->nip - 4);
2137 gen_reset_fpstatus();
2138 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2139 cpu_fpr[rB(ctx->opcode)]);
2140 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2141 }
2142
2143 static void gen_fsqrts(DisasContext *ctx)
2144 {
2145 if (unlikely(!ctx->fpu_enabled)) {
2146 gen_exception(ctx, POWERPC_EXCP_FPU);
2147 return;
2148 }
2149 /* NIP cannot be restored if the memory exception comes from an helper */
2150 gen_update_nip(ctx, ctx->nip - 4);
2151 gen_reset_fpstatus();
2152 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2153 cpu_fpr[rB(ctx->opcode)]);
2154 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2155 cpu_fpr[rD(ctx->opcode)]);
2156 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2157 }
2158
2159 /*** Floating-Point multiply-and-add ***/
2160 /* fmadd - fmadds */
2161 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2162 /* fmsub - fmsubs */
2163 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2164 /* fnmadd - fnmadds */
2165 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2166 /* fnmsub - fnmsubs */
2167 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2168
2169 /*** Floating-Point round & convert ***/
2170 /* fctiw */
2171 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2172 /* fctiwz */
2173 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2174 /* frsp */
2175 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2176 #if defined(TARGET_PPC64)
2177 /* fcfid */
2178 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2179 /* fctid */
2180 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2181 /* fctidz */
2182 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2183 #endif
2184
2185 /* frin */
2186 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2187 /* friz */
2188 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2189 /* frip */
2190 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2191 /* frim */
2192 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2193
2194 /*** Floating-Point compare ***/
2195
2196 /* fcmpo */
2197 static void gen_fcmpo(DisasContext *ctx)
2198 {
2199 TCGv_i32 crf;
2200 if (unlikely(!ctx->fpu_enabled)) {
2201 gen_exception(ctx, POWERPC_EXCP_FPU);
2202 return;
2203 }
2204 /* NIP cannot be restored if the memory exception comes from an helper */
2205 gen_update_nip(ctx, ctx->nip - 4);
2206 gen_reset_fpstatus();
2207 crf = tcg_const_i32(crfD(ctx->opcode));
2208 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2209 cpu_fpr[rB(ctx->opcode)], crf);
2210 tcg_temp_free_i32(crf);
2211 gen_helper_float_check_status(cpu_env);
2212 }
2213
2214 /* fcmpu */
2215 static void gen_fcmpu(DisasContext *ctx)
2216 {
2217 TCGv_i32 crf;
2218 if (unlikely(!ctx->fpu_enabled)) {
2219 gen_exception(ctx, POWERPC_EXCP_FPU);
2220 return;
2221 }
2222 /* NIP cannot be restored if the memory exception comes from an helper */
2223 gen_update_nip(ctx, ctx->nip - 4);
2224 gen_reset_fpstatus();
2225 crf = tcg_const_i32(crfD(ctx->opcode));
2226 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2227 cpu_fpr[rB(ctx->opcode)], crf);
2228 tcg_temp_free_i32(crf);
2229 gen_helper_float_check_status(cpu_env);
2230 }
2231
2232 /*** Floating-point move ***/
2233 /* fabs */
2234 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2235 static void gen_fabs(DisasContext *ctx)
2236 {
2237 if (unlikely(!ctx->fpu_enabled)) {
2238 gen_exception(ctx, POWERPC_EXCP_FPU);
2239 return;
2240 }
2241 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2242 ~(1ULL << 63));
2243 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2244 }
2245
2246 /* fmr - fmr. */
2247 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2248 static void gen_fmr(DisasContext *ctx)
2249 {
2250 if (unlikely(!ctx->fpu_enabled)) {
2251 gen_exception(ctx, POWERPC_EXCP_FPU);
2252 return;
2253 }
2254 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2255 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2256 }
2257
2258 /* fnabs */
2259 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2260 static void gen_fnabs(DisasContext *ctx)
2261 {
2262 if (unlikely(!ctx->fpu_enabled)) {
2263 gen_exception(ctx, POWERPC_EXCP_FPU);
2264 return;
2265 }
2266 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2267 1ULL << 63);
2268 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2269 }
2270
2271 /* fneg */
2272 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2273 static void gen_fneg(DisasContext *ctx)
2274 {
2275 if (unlikely(!ctx->fpu_enabled)) {
2276 gen_exception(ctx, POWERPC_EXCP_FPU);
2277 return;
2278 }
2279 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2280 1ULL << 63);
2281 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2282 }
2283
2284 /* fcpsgn: PowerPC 2.05 specification */
2285 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2286 static void gen_fcpsgn(DisasContext *ctx)
2287 {
2288 if (unlikely(!ctx->fpu_enabled)) {
2289 gen_exception(ctx, POWERPC_EXCP_FPU);
2290 return;
2291 }
2292 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2293 cpu_fpr[rB(ctx->opcode)], 0, 63);
2294 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2295 }
2296
2297 /*** Floating-Point status & ctrl register ***/
2298
2299 /* mcrfs */
2300 static void gen_mcrfs(DisasContext *ctx)
2301 {
2302 TCGv tmp = tcg_temp_new();
2303 int bfa;
2304
2305 if (unlikely(!ctx->fpu_enabled)) {
2306 gen_exception(ctx, POWERPC_EXCP_FPU);
2307 return;
2308 }
2309 bfa = 4 * (7 - crfS(ctx->opcode));
2310 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2311 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2312 tcg_temp_free(tmp);
2313 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2314 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2315 }
2316
2317 /* mffs */
2318 static void gen_mffs(DisasContext *ctx)
2319 {
2320 if (unlikely(!ctx->fpu_enabled)) {
2321 gen_exception(ctx, POWERPC_EXCP_FPU);
2322 return;
2323 }
2324 gen_reset_fpstatus();
2325 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2326 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2327 }
2328
2329 /* mtfsb0 */
2330 static void gen_mtfsb0(DisasContext *ctx)
2331 {
2332 uint8_t crb;
2333
2334 if (unlikely(!ctx->fpu_enabled)) {
2335 gen_exception(ctx, POWERPC_EXCP_FPU);
2336 return;
2337 }
2338 crb = 31 - crbD(ctx->opcode);
2339 gen_reset_fpstatus();
2340 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2341 TCGv_i32 t0;
2342 /* NIP cannot be restored if the memory exception comes from an helper */
2343 gen_update_nip(ctx, ctx->nip - 4);
2344 t0 = tcg_const_i32(crb);
2345 gen_helper_fpscr_clrbit(cpu_env, t0);
2346 tcg_temp_free_i32(t0);
2347 }
2348 if (unlikely(Rc(ctx->opcode) != 0)) {
2349 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2350 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2351 }
2352 }
2353
2354 /* mtfsb1 */
2355 static void gen_mtfsb1(DisasContext *ctx)
2356 {
2357 uint8_t crb;
2358
2359 if (unlikely(!ctx->fpu_enabled)) {
2360 gen_exception(ctx, POWERPC_EXCP_FPU);
2361 return;
2362 }
2363 crb = 31 - crbD(ctx->opcode);
2364 gen_reset_fpstatus();
2365 /* XXX: we pretend we can only do IEEE floating-point computations */
2366 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2367 TCGv_i32 t0;
2368 /* NIP cannot be restored if the memory exception comes from an helper */
2369 gen_update_nip(ctx, ctx->nip - 4);
2370 t0 = tcg_const_i32(crb);
2371 gen_helper_fpscr_setbit(cpu_env, t0);
2372 tcg_temp_free_i32(t0);
2373 }
2374 if (unlikely(Rc(ctx->opcode) != 0)) {
2375 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2376 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2377 }
2378 /* We can raise a differed exception */
2379 gen_helper_float_check_status(cpu_env);
2380 }
2381
2382 /* mtfsf */
2383 static void gen_mtfsf(DisasContext *ctx)
2384 {
2385 TCGv_i32 t0;
2386 int flm, l, w;
2387
2388 if (unlikely(!ctx->fpu_enabled)) {
2389 gen_exception(ctx, POWERPC_EXCP_FPU);
2390 return;
2391 }
2392 flm = FPFLM(ctx->opcode);
2393 l = FPL(ctx->opcode);
2394 w = FPW(ctx->opcode);
2395 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2396 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2397 return;
2398 }
2399 /* NIP cannot be restored if the memory exception comes from an helper */
2400 gen_update_nip(ctx, ctx->nip - 4);
2401 gen_reset_fpstatus();
2402 if (l) {
2403 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2404 } else {
2405 t0 = tcg_const_i32(flm << (w * 8));
2406 }
2407 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2408 tcg_temp_free_i32(t0);
2409 if (unlikely(Rc(ctx->opcode) != 0)) {
2410 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2411 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2412 }
2413 /* We can raise a differed exception */
2414 gen_helper_float_check_status(cpu_env);
2415 }
2416
2417 /* mtfsfi */
2418 static void gen_mtfsfi(DisasContext *ctx)
2419 {
2420 int bf, sh, w;
2421 TCGv_i64 t0;
2422 TCGv_i32 t1;
2423
2424 if (unlikely(!ctx->fpu_enabled)) {
2425 gen_exception(ctx, POWERPC_EXCP_FPU);
2426 return;
2427 }
2428 w = FPW(ctx->opcode);
2429 bf = FPBF(ctx->opcode);
2430 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2431 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2432 return;
2433 }
2434 sh = (8 * w) + 7 - bf;
2435 /* NIP cannot be restored if the memory exception comes from an helper */
2436 gen_update_nip(ctx, ctx->nip - 4);
2437 gen_reset_fpstatus();
2438 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2439 t1 = tcg_const_i32(1 << sh);
2440 gen_helper_store_fpscr(cpu_env, t0, t1);
2441 tcg_temp_free_i64(t0);
2442 tcg_temp_free_i32(t1);
2443 if (unlikely(Rc(ctx->opcode) != 0)) {
2444 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2445 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2446 }
2447 /* We can raise a differed exception */
2448 gen_helper_float_check_status(cpu_env);
2449 }
2450
2451 /*** Addressing modes ***/
2452 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2453 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2454 target_long maskl)
2455 {
2456 target_long simm = SIMM(ctx->opcode);
2457
2458 simm &= ~maskl;
2459 if (rA(ctx->opcode) == 0) {
2460 if (NARROW_MODE(ctx)) {
2461 simm = (uint32_t)simm;
2462 }
2463 tcg_gen_movi_tl(EA, simm);
2464 } else if (likely(simm != 0)) {
2465 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2466 if (NARROW_MODE(ctx)) {
2467 tcg_gen_ext32u_tl(EA, EA);
2468 }
2469 } else {
2470 if (NARROW_MODE(ctx)) {
2471 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2472 } else {
2473 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2474 }
2475 }
2476 }
2477
2478 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2479 {
2480 if (rA(ctx->opcode) == 0) {
2481 if (NARROW_MODE(ctx)) {
2482 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2483 } else {
2484 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2485 }
2486 } else {
2487 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2488 if (NARROW_MODE(ctx)) {
2489 tcg_gen_ext32u_tl(EA, EA);
2490 }
2491 }
2492 }
2493
2494 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2495 {
2496 if (rA(ctx->opcode) == 0) {
2497 tcg_gen_movi_tl(EA, 0);
2498 } else if (NARROW_MODE(ctx)) {
2499 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2500 } else {
2501 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2502 }
2503 }
2504
2505 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2506 target_long val)
2507 {
2508 tcg_gen_addi_tl(ret, arg1, val);
2509 if (NARROW_MODE(ctx)) {
2510 tcg_gen_ext32u_tl(ret, ret);
2511 }
2512 }
2513
2514 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2515 {
2516 int l1 = gen_new_label();
2517 TCGv t0 = tcg_temp_new();
2518 TCGv_i32 t1, t2;
2519 /* NIP cannot be restored if the memory exception comes from an helper */
2520 gen_update_nip(ctx, ctx->nip - 4);
2521 tcg_gen_andi_tl(t0, EA, mask);
2522 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2523 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2524 t2 = tcg_const_i32(0);
2525 gen_helper_raise_exception_err(cpu_env, t1, t2);
2526 tcg_temp_free_i32(t1);
2527 tcg_temp_free_i32(t2);
2528 gen_set_label(l1);
2529 tcg_temp_free(t0);
2530 }
2531
2532 /*** Integer load ***/
2533 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2534 {
2535 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2536 }
2537
2538 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2539 {
2540 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2541 }
2542
2543 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2544 {
2545 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2546 if (unlikely(ctx->le_mode)) {
2547 tcg_gen_bswap16_tl(arg1, arg1);
2548 }
2549 }
2550
2551 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2552 {
2553 if (unlikely(ctx->le_mode)) {
2554 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2555 tcg_gen_bswap16_tl(arg1, arg1);
2556 tcg_gen_ext16s_tl(arg1, arg1);
2557 } else {
2558 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2559 }
2560 }
2561
2562 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2563 {
2564 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2565 if (unlikely(ctx->le_mode)) {
2566 tcg_gen_bswap32_tl(arg1, arg1);
2567 }
2568 }
2569
2570 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2571 {
2572 TCGv tmp = tcg_temp_new();
2573 gen_qemu_ld32u(ctx, tmp, addr);
2574 tcg_gen_extu_tl_i64(val, tmp);
2575 tcg_temp_free(tmp);
2576 }
2577
2578 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2579 {
2580 if (unlikely(ctx->le_mode)) {
2581 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2582 tcg_gen_bswap32_tl(arg1, arg1);
2583 tcg_gen_ext32s_tl(arg1, arg1);
2584 } else
2585 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2586 }
2587
2588 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2589 {
2590 TCGv tmp = tcg_temp_new();
2591 gen_qemu_ld32s(ctx, tmp, addr);
2592 tcg_gen_ext_tl_i64(val, tmp);
2593 tcg_temp_free(tmp);
2594 }
2595
2596 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2597 {
2598 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2599 if (unlikely(ctx->le_mode)) {
2600 tcg_gen_bswap64_i64(arg1, arg1);
2601 }
2602 }
2603
2604 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2605 {
2606 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2607 }
2608
2609 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2610 {
2611 if (unlikely(ctx->le_mode)) {
2612 TCGv t0 = tcg_temp_new();
2613 tcg_gen_ext16u_tl(t0, arg1);
2614 tcg_gen_bswap16_tl(t0, t0);
2615 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2616 tcg_temp_free(t0);
2617 } else {
2618 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2619 }
2620 }
2621
2622 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2623 {
2624 if (unlikely(ctx->le_mode)) {
2625 TCGv t0 = tcg_temp_new();
2626 tcg_gen_ext32u_tl(t0, arg1);
2627 tcg_gen_bswap32_tl(t0, t0);
2628 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2629 tcg_temp_free(t0);
2630 } else {
2631 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2632 }
2633 }
2634
2635 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2636 {
2637 TCGv tmp = tcg_temp_new();
2638 tcg_gen_trunc_i64_tl(tmp, val);
2639 gen_qemu_st32(ctx, tmp, addr);
2640 tcg_temp_free(tmp);
2641 }
2642
2643 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2644 {
2645 if (unlikely(ctx->le_mode)) {
2646 TCGv_i64 t0 = tcg_temp_new_i64();
2647 tcg_gen_bswap64_i64(t0, arg1);
2648 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2649 tcg_temp_free_i64(t0);
2650 } else
2651 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2652 }
2653
2654 #define GEN_LD(name, ldop, opc, type) \
2655 static void glue(gen_, name)(DisasContext *ctx) \
2656 { \
2657 TCGv EA; \
2658 gen_set_access_type(ctx, ACCESS_INT); \
2659 EA = tcg_temp_new(); \
2660 gen_addr_imm_index(ctx, EA, 0); \
2661 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2662 tcg_temp_free(EA); \
2663 }
2664
2665 #define GEN_LDU(name, ldop, opc, type) \
2666 static void glue(gen_, name##u)(DisasContext *ctx) \
2667 { \
2668 TCGv EA; \
2669 if (unlikely(rA(ctx->opcode) == 0 || \
2670 rA(ctx->opcode) == rD(ctx->opcode))) { \
2671 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2672 return; \
2673 } \
2674 gen_set_access_type(ctx, ACCESS_INT); \
2675 EA = tcg_temp_new(); \
2676 if (type == PPC_64B) \
2677 gen_addr_imm_index(ctx, EA, 0x03); \
2678 else \
2679 gen_addr_imm_index(ctx, EA, 0); \
2680 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2681 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2682 tcg_temp_free(EA); \
2683 }
2684
2685 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2686 static void glue(gen_, name##ux)(DisasContext *ctx) \
2687 { \
2688 TCGv EA; \
2689 if (unlikely(rA(ctx->opcode) == 0 || \
2690 rA(ctx->opcode) == rD(ctx->opcode))) { \
2691 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2692 return; \
2693 } \
2694 gen_set_access_type(ctx, ACCESS_INT); \
2695 EA = tcg_temp_new(); \
2696 gen_addr_reg_index(ctx, EA); \
2697 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2698 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2699 tcg_temp_free(EA); \
2700 }
2701
2702 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2703 static void glue(gen_, name##x)(DisasContext *ctx) \
2704 { \
2705 TCGv EA; \
2706 gen_set_access_type(ctx, ACCESS_INT); \
2707 EA = tcg_temp_new(); \
2708 gen_addr_reg_index(ctx, EA); \
2709 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2710 tcg_temp_free(EA); \
2711 }
2712 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2713 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2714
2715 #define GEN_LDS(name, ldop, op, type) \
2716 GEN_LD(name, ldop, op | 0x20, type); \
2717 GEN_LDU(name, ldop, op | 0x21, type); \
2718 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2719 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2720
2721 /* lbz lbzu lbzux lbzx */
2722 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2723 /* lha lhau lhaux lhax */
2724 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2725 /* lhz lhzu lhzux lhzx */
2726 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2727 /* lwz lwzu lwzux lwzx */
2728 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2729 #if defined(TARGET_PPC64)
2730 /* lwaux */
2731 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2732 /* lwax */
2733 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2734 /* ldux */
2735 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2736 /* ldx */
2737 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2738
2739 static void gen_ld(DisasContext *ctx)
2740 {
2741 TCGv EA;
2742 if (Rc(ctx->opcode)) {
2743 if (unlikely(rA(ctx->opcode) == 0 ||
2744 rA(ctx->opcode) == rD(ctx->opcode))) {
2745 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2746 return;
2747 }
2748 }
2749 gen_set_access_type(ctx, ACCESS_INT);
2750 EA = tcg_temp_new();
2751 gen_addr_imm_index(ctx, EA, 0x03);
2752 if (ctx->opcode & 0x02) {
2753 /* lwa (lwau is undefined) */
2754 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2755 } else {
2756 /* ld - ldu */
2757 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2758 }
2759 if (Rc(ctx->opcode))
2760 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2761 tcg_temp_free(EA);
2762 }
2763
2764 /* lq */
2765 static void gen_lq(DisasContext *ctx)
2766 {
2767 #if defined(CONFIG_USER_ONLY)
2768 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2769 #else
2770 int ra, rd;
2771 TCGv EA;
2772
2773 /* Restore CPU state */
2774 if (unlikely(ctx->mem_idx == 0)) {
2775 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2776 return;
2777 }
2778 ra = rA(ctx->opcode);
2779 rd = rD(ctx->opcode);
2780 if (unlikely((rd & 1) || rd == ra)) {
2781 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2782 return;
2783 }
2784 if (unlikely(ctx->le_mode)) {
2785 /* Little-endian mode is not handled */
2786 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2787 return;
2788 }
2789 gen_set_access_type(ctx, ACCESS_INT);
2790 EA = tcg_temp_new();
2791 gen_addr_imm_index(ctx, EA, 0x0F);
2792 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2793 gen_addr_add(ctx, EA, EA, 8);
2794 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2795 tcg_temp_free(EA);
2796 #endif
2797 }
2798 #endif
2799
2800 /*** Integer store ***/
2801 #define GEN_ST(name, stop, opc, type) \
2802 static void glue(gen_, name)(DisasContext *ctx) \
2803 { \
2804 TCGv EA; \
2805 gen_set_access_type(ctx, ACCESS_INT); \
2806 EA = tcg_temp_new(); \
2807 gen_addr_imm_index(ctx, EA, 0); \
2808 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2809 tcg_temp_free(EA); \
2810 }
2811
2812 #define GEN_STU(name, stop, opc, type) \
2813 static void glue(gen_, stop##u)(DisasContext *ctx) \
2814 { \
2815 TCGv EA; \
2816 if (unlikely(rA(ctx->opcode) == 0)) { \
2817 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2818 return; \
2819 } \
2820 gen_set_access_type(ctx, ACCESS_INT); \
2821 EA = tcg_temp_new(); \
2822 if (type == PPC_64B) \
2823 gen_addr_imm_index(ctx, EA, 0x03); \
2824 else \
2825 gen_addr_imm_index(ctx, EA, 0); \
2826 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2827 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2828 tcg_temp_free(EA); \
2829 }
2830
2831 #define GEN_STUX(name, stop, opc2, opc3, type) \
2832 static void glue(gen_, name##ux)(DisasContext *ctx) \
2833 { \
2834 TCGv EA; \
2835 if (unlikely(rA(ctx->opcode) == 0)) { \
2836 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2837 return; \
2838 } \
2839 gen_set_access_type(ctx, ACCESS_INT); \
2840 EA = tcg_temp_new(); \
2841 gen_addr_reg_index(ctx, EA); \
2842 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2843 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2844 tcg_temp_free(EA); \
2845 }
2846
2847 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2848 static void glue(gen_, name##x)(DisasContext *ctx) \
2849 { \
2850 TCGv EA; \
2851 gen_set_access_type(ctx, ACCESS_INT); \
2852 EA = tcg_temp_new(); \
2853 gen_addr_reg_index(ctx, EA); \
2854 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2855 tcg_temp_free(EA); \
2856 }
2857 #define GEN_STX(name, stop, opc2, opc3, type) \
2858 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2859
2860 #define GEN_STS(name, stop, op, type) \
2861 GEN_ST(name, stop, op | 0x20, type); \
2862 GEN_STU(name, stop, op | 0x21, type); \
2863 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2864 GEN_STX(name, stop, 0x17, op | 0x00, type)
2865
2866 /* stb stbu stbux stbx */
2867 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2868 /* sth sthu sthux sthx */
2869 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2870 /* stw stwu stwux stwx */
2871 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2872 #if defined(TARGET_PPC64)
2873 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2874 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2875
2876 static void gen_std(DisasContext *ctx)
2877 {
2878 int rs;
2879 TCGv EA;
2880
2881 rs = rS(ctx->opcode);
2882 if ((ctx->opcode & 0x3) == 0x2) {
2883 #if defined(CONFIG_USER_ONLY)
2884 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2885 #else
2886 /* stq */
2887 if (unlikely(ctx->mem_idx == 0)) {
2888 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2889 return;
2890 }
2891 if (unlikely(rs & 1)) {
2892 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2893 return;
2894 }
2895 if (unlikely(ctx->le_mode)) {
2896 /* Little-endian mode is not handled */
2897 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2898 return;
2899 }
2900 gen_set_access_type(ctx, ACCESS_INT);
2901 EA = tcg_temp_new();
2902 gen_addr_imm_index(ctx, EA, 0x03);
2903 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2904 gen_addr_add(ctx, EA, EA, 8);
2905 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2906 tcg_temp_free(EA);
2907 #endif
2908 } else {
2909 /* std / stdu */
2910 if (Rc(ctx->opcode)) {
2911 if (unlikely(rA(ctx->opcode) == 0)) {
2912 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2913 return;
2914 }
2915 }
2916 gen_set_access_type(ctx, ACCESS_INT);
2917 EA = tcg_temp_new();
2918 gen_addr_imm_index(ctx, EA, 0x03);
2919 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2920 if (Rc(ctx->opcode))
2921 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2922 tcg_temp_free(EA);
2923 }
2924 }
2925 #endif
2926 /*** Integer load and store with byte reverse ***/
2927 /* lhbrx */
2928 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2929 {
2930 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2931 if (likely(!ctx->le_mode)) {
2932 tcg_gen_bswap16_tl(arg1, arg1);
2933 }
2934 }
2935 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2936
2937 /* lwbrx */
2938 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2939 {
2940 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2941 if (likely(!ctx->le_mode)) {
2942 tcg_gen_bswap32_tl(arg1, arg1);
2943 }
2944 }
2945 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2946
2947 #if defined(TARGET_PPC64)
2948 /* ldbrx */
2949 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2950 {
2951 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2952 if (likely(!ctx->le_mode)) {
2953 tcg_gen_bswap64_tl(arg1, arg1);
2954 }
2955 }
2956 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2957 #endif /* TARGET_PPC64 */
2958
2959 /* sthbrx */
2960 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2961 {
2962 if (likely(!ctx->le_mode)) {
2963 TCGv t0 = tcg_temp_new();
2964 tcg_gen_ext16u_tl(t0, arg1);
2965 tcg_gen_bswap16_tl(t0, t0);
2966 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2967 tcg_temp_free(t0);
2968 } else {
2969 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2970 }
2971 }
2972 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2973
2974 /* stwbrx */
2975 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2976 {
2977 if (likely(!ctx->le_mode)) {
2978 TCGv t0 = tcg_temp_new();
2979 tcg_gen_ext32u_tl(t0, arg1);
2980 tcg_gen_bswap32_tl(t0, t0);
2981 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2982 tcg_temp_free(t0);
2983 } else {
2984 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2985 }
2986 }
2987 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2988
2989 #if defined(TARGET_PPC64)
2990 /* stdbrx */
2991 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2992 {
2993 if (likely(!ctx->le_mode)) {
2994 TCGv t0 = tcg_temp_new();
2995 tcg_gen_bswap64_tl(t0, arg1);
2996 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2997 tcg_temp_free(t0);
2998 } else {
2999 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
3000 }
3001 }
3002 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3003 #endif /* TARGET_PPC64 */
3004
3005 /*** Integer load and store multiple ***/
3006
3007 /* lmw */
3008 static void gen_lmw(DisasContext *ctx)
3009 {
3010 TCGv t0;
3011 TCGv_i32 t1;
3012 gen_set_access_type(ctx, ACCESS_INT);
3013 /* NIP cannot be restored if the memory exception comes from an helper */
3014 gen_update_nip(ctx, ctx->nip - 4);
3015 t0 = tcg_temp_new();
3016 t1 = tcg_const_i32(rD(ctx->opcode));
3017 gen_addr_imm_index(ctx, t0, 0);
3018 gen_helper_lmw(cpu_env, t0, t1);
3019 tcg_temp_free(t0);
3020 tcg_temp_free_i32(t1);
3021 }
3022
3023 /* stmw */
3024 static void gen_stmw(DisasContext *ctx)
3025 {
3026 TCGv t0;
3027 TCGv_i32 t1;
3028 gen_set_access_type(ctx, ACCESS_INT);
3029 /* NIP cannot be restored if the memory exception comes from an helper */
3030 gen_update_nip(ctx, ctx->nip - 4);
3031 t0 = tcg_temp_new();
3032 t1 = tcg_const_i32(rS(ctx->opcode));
3033 gen_addr_imm_index(ctx, t0, 0);
3034 gen_helper_stmw(cpu_env, t0, t1);
3035 tcg_temp_free(t0);
3036 tcg_temp_free_i32(t1);
3037 }
3038
3039 /*** Integer load and store strings ***/
3040
3041 /* lswi */
3042 /* PowerPC32 specification says we must generate an exception if
3043 * rA is in the range of registers to be loaded.
3044 * In an other hand, IBM says this is valid, but rA won't be loaded.
3045 * For now, I'll follow the spec...
3046 */
3047 static void gen_lswi(DisasContext *ctx)
3048 {
3049 TCGv t0;
3050 TCGv_i32 t1, t2;
3051 int nb = NB(ctx->opcode);
3052 int start = rD(ctx->opcode);
3053 int ra = rA(ctx->opcode);
3054 int nr;
3055
3056 if (nb == 0)
3057 nb = 32;
3058 nr = nb / 4;
3059 if (unlikely(((start + nr) > 32 &&
3060 start <= ra && (start + nr - 32) > ra) ||
3061 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3062 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3063 return;
3064 }
3065 gen_set_access_type(ctx, ACCESS_INT);
3066 /* NIP cannot be restored if the memory exception comes from an helper */
3067 gen_update_nip(ctx, ctx->nip - 4);
3068 t0 = tcg_temp_new();
3069 gen_addr_register(ctx, t0);
3070 t1 = tcg_const_i32(nb);
3071 t2 = tcg_const_i32(start);
3072 gen_helper_lsw(cpu_env, t0, t1, t2);
3073 tcg_temp_free(t0);
3074 tcg_temp_free_i32(t1);
3075 tcg_temp_free_i32(t2);
3076 }
3077
3078 /* lswx */
3079 static void gen_lswx(DisasContext *ctx)
3080 {
3081 TCGv t0;
3082 TCGv_i32 t1, t2, t3;
3083 gen_set_access_type(ctx, ACCESS_INT);
3084 /* NIP cannot be restored if the memory exception comes from an helper */
3085 gen_update_nip(ctx, ctx->nip - 4);
3086 t0 = tcg_temp_new();
3087 gen_addr_reg_index(ctx, t0);
3088 t1 = tcg_const_i32(rD(ctx->opcode));
3089 t2 = tcg_const_i32(rA(ctx->opcode));
3090 t3 = tcg_const_i32(rB(ctx->opcode));
3091 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3092 tcg_temp_free(t0);
3093 tcg_temp_free_i32(t1);
3094 tcg_temp_free_i32(t2);
3095 tcg_temp_free_i32(t3);
3096 }
3097
3098 /* stswi */
3099 static void gen_stswi(DisasContext *ctx)
3100 {
3101 TCGv t0;
3102 TCGv_i32 t1, t2;
3103 int nb = NB(ctx->opcode);
3104 gen_set_access_type(ctx, ACCESS_INT);
3105 /* NIP cannot be restored if the memory exception comes from an helper */
3106 gen_update_nip(ctx, ctx->nip - 4);
3107 t0 = tcg_temp_new();
3108 gen_addr_register(ctx, t0);
3109 if (nb == 0)
3110 nb = 32;
3111 t1 = tcg_const_i32(nb);
3112 t2 = tcg_const_i32(rS(ctx->opcode));
3113 gen_helper_stsw(cpu_env, t0, t1, t2);
3114 tcg_temp_free(t0);
3115 tcg_temp_free_i32(t1);
3116 tcg_temp_free_i32(t2);
3117 }
3118
3119 /* stswx */
3120 static void gen_stswx(DisasContext *ctx)
3121 {
3122 TCGv t0;
3123 TCGv_i32 t1, t2;
3124 gen_set_access_type(ctx, ACCESS_INT);
3125 /* NIP cannot be restored if the memory exception comes from an helper */
3126 gen_update_nip(ctx, ctx->nip - 4);
3127 t0 = tcg_temp_new();
3128 gen_addr_reg_index(ctx, t0);
3129 t1 = tcg_temp_new_i32();
3130 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3131 tcg_gen_andi_i32(t1, t1, 0x7F);
3132 t2 = tcg_const_i32(rS(ctx->opcode));
3133 gen_helper_stsw(cpu_env, t0, t1, t2);
3134 tcg_temp_free(t0);
3135 tcg_temp_free_i32(t1);
3136 tcg_temp_free_i32(t2);
3137 }
3138
3139 /*** Memory synchronisation ***/
3140 /* eieio */
3141 static void gen_eieio(DisasContext *ctx)
3142 {
3143 }
3144
3145 /* isync */
3146 static void gen_isync(DisasContext *ctx)
3147 {
3148 gen_stop_exception(ctx);
3149 }
3150
3151 /* lwarx */
3152 static void gen_lwarx(DisasContext *ctx)
3153 {
3154 TCGv t0;
3155 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3156 gen_set_access_type(ctx, ACCESS_RES);
3157 t0 = tcg_temp_local_new();
3158 gen_addr_reg_index(ctx, t0);
3159 gen_check_align(ctx, t0, 0x03);
3160 gen_qemu_ld32u(ctx, gpr, t0);
3161 tcg_gen_mov_tl(cpu_reserve, t0);
3162 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3163 tcg_temp_free(t0);
3164 }
3165
3166 #if defined(CONFIG_USER_ONLY)
3167 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3168 int reg, int size)
3169 {
3170 TCGv t0 = tcg_temp_new();
3171 uint32_t save_exception = ctx->exception;
3172
3173 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3174 tcg_gen_movi_tl(t0, (size << 5) | reg);
3175 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3176 tcg_temp_free(t0);
3177 gen_update_nip(ctx, ctx->nip-4);
3178 ctx->exception = POWERPC_EXCP_BRANCH;
3179 gen_exception(ctx, POWERPC_EXCP_STCX);
3180 ctx->exception = save_exception;
3181 }
3182 #endif
3183
3184 /* stwcx. */
3185 static void gen_stwcx_(DisasContext *ctx)
3186 {
3187 TCGv t0;
3188 gen_set_access_type(ctx, ACCESS_RES);
3189 t0 = tcg_temp_local_new();
3190 gen_addr_reg_index(ctx, t0);
3191 gen_check_align(ctx, t0, 0x03);
3192 #if defined(CONFIG_USER_ONLY)
3193 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3194 #else
3195 {
3196 int l1;
3197
3198 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3199 l1 = gen_new_label();
3200 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3201 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3202 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3203 gen_set_label(l1);
3204 tcg_gen_movi_tl(cpu_reserve, -1);
3205 }
3206 #endif
3207 tcg_temp_free(t0);
3208 }
3209
3210 #if defined(TARGET_PPC64)
3211 /* ldarx */
3212 static void gen_ldarx(DisasContext *ctx)
3213 {
3214 TCGv t0;
3215 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3216 gen_set_access_type(ctx, ACCESS_RES);
3217 t0 = tcg_temp_local_new();
3218 gen_addr_reg_index(ctx, t0);
3219 gen_check_align(ctx, t0, 0x07);
3220 gen_qemu_ld64(ctx, gpr, t0);
3221 tcg_gen_mov_tl(cpu_reserve, t0);
3222 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3223 tcg_temp_free(t0);
3224 }
3225
3226 /* stdcx. */
3227 static void gen_stdcx_(DisasContext *ctx)
3228 {
3229 TCGv t0;
3230 gen_set_access_type(ctx, ACCESS_RES);
3231 t0 = tcg_temp_local_new();
3232 gen_addr_reg_index(ctx, t0);
3233 gen_check_align(ctx, t0, 0x07);
3234 #if defined(CONFIG_USER_ONLY)
3235 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3236 #else
3237 {
3238 int l1;
3239 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3240 l1 = gen_new_label();
3241 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3242 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3243 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3244 gen_set_label(l1);
3245 tcg_gen_movi_tl(cpu_reserve, -1);
3246 }
3247 #endif
3248 tcg_temp_free(t0);
3249 }
3250 #endif /* defined(TARGET_PPC64) */
3251
3252 /* sync */
3253 static void gen_sync(DisasContext *ctx)
3254 {
3255 }
3256
3257 /* wait */
3258 static void gen_wait(DisasContext *ctx)
3259 {
3260 TCGv_i32 t0 = tcg_temp_new_i32();
3261 tcg_gen_st_i32(t0, cpu_env,
3262 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3263 tcg_temp_free_i32(t0);
3264 /* Stop translation, as the CPU is supposed to sleep from now */
3265 gen_exception_err(ctx, EXCP_HLT, 1);
3266 }
3267
3268 /*** Floating-point load ***/
3269 #define GEN_LDF(name, ldop, opc, type) \
3270 static void glue(gen_, name)(DisasContext *ctx) \
3271 { \
3272 TCGv EA; \
3273 if (unlikely(!ctx->fpu_enabled)) { \
3274 gen_exception(ctx, POWERPC_EXCP_FPU); \
3275 return; \
3276 } \
3277 gen_set_access_type(ctx, ACCESS_FLOAT); \
3278 EA = tcg_temp_new(); \
3279 gen_addr_imm_index(ctx, EA, 0); \
3280 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3281 tcg_temp_free(EA); \
3282 }
3283
3284 #define GEN_LDUF(name, ldop, opc, type) \
3285 static void glue(gen_, name##u)(DisasContext *ctx) \
3286 { \
3287 TCGv EA; \
3288 if (unlikely(!ctx->fpu_enabled)) { \
3289 gen_exception(ctx, POWERPC_EXCP_FPU); \
3290 return; \
3291 } \
3292 if (unlikely(rA(ctx->opcode) == 0)) { \
3293 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3294 return; \
3295 } \
3296 gen_set_access_type(ctx, ACCESS_FLOAT); \
3297 EA = tcg_temp_new(); \
3298 gen_addr_imm_index(ctx, EA, 0); \
3299 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3300 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3301 tcg_temp_free(EA); \
3302 }
3303
3304 #define GEN_LDUXF(name, ldop, opc, type) \
3305 static void glue(gen_, name##ux)(DisasContext *ctx) \
3306 { \
3307 TCGv EA; \
3308 if (unlikely(!ctx->fpu_enabled)) { \
3309 gen_exception(ctx, POWERPC_EXCP_FPU); \
3310 return; \
3311 } \
3312 if (unlikely(rA(ctx->opcode) == 0)) { \
3313 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3314 return; \
3315 } \
3316 gen_set_access_type(ctx, ACCESS_FLOAT); \
3317 EA = tcg_temp_new(); \
3318 gen_addr_reg_index(ctx, EA); \
3319 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3320 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3321 tcg_temp_free(EA); \
3322 }
3323
3324 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3325 static void glue(gen_, name##x)(DisasContext *ctx) \
3326 { \
3327 TCGv EA; \
3328 if (unlikely(!ctx->fpu_enabled)) { \
3329 gen_exception(ctx, POWERPC_EXCP_FPU); \
3330 return; \
3331 } \
3332 gen_set_access_type(ctx, ACCESS_FLOAT); \
3333 EA = tcg_temp_new(); \
3334 gen_addr_reg_index(ctx, EA); \
3335 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3336 tcg_temp_free(EA); \
3337 }
3338
3339 #define GEN_LDFS(name, ldop, op, type) \
3340 GEN_LDF(name, ldop, op | 0x20, type); \
3341 GEN_LDUF(name, ldop, op | 0x21, type); \
3342 GEN_LDUXF(name, ldop, op | 0x01, type); \
3343 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3344
3345 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3346 {
3347 TCGv t0 = tcg_temp_new();
3348 TCGv_i32 t1 = tcg_temp_new_i32();
3349 gen_qemu_ld32u(ctx, t0, arg2);
3350 tcg_gen_trunc_tl_i32(t1, t0);
3351 tcg_temp_free(t0);
3352 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3353 tcg_temp_free_i32(t1);
3354 }
3355
3356 /* lfd lfdu lfdux lfdx */
3357 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3358 /* lfs lfsu lfsux lfsx */
3359 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3360
3361 /* lfdp */
3362 static void gen_lfdp(DisasContext *ctx)
3363 {
3364 TCGv EA;
3365 if (unlikely(!ctx->fpu_enabled)) {
3366 gen_exception(ctx, POWERPC_EXCP_FPU);
3367 return;
3368 }
3369 gen_set_access_type(ctx, ACCESS_FLOAT);
3370 EA = tcg_temp_new();
3371 gen_addr_imm_index(ctx, EA, 0); \
3372 if (unlikely(ctx->le_mode)) {
3373 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3374 tcg_gen_addi_tl(EA, EA, 8);
3375 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3376 } else {
3377 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3378 tcg_gen_addi_tl(EA, EA, 8);
3379 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3380 }
3381 tcg_temp_free(EA);
3382 }
3383
3384 /* lfdpx */
3385 static void gen_lfdpx(DisasContext *ctx)
3386 {
3387 TCGv EA;
3388 if (unlikely(!ctx->fpu_enabled)) {
3389 gen_exception(ctx, POWERPC_EXCP_FPU);
3390 return;
3391 }
3392 gen_set_access_type(ctx, ACCESS_FLOAT);
3393 EA = tcg_temp_new();
3394 gen_addr_reg_index(ctx, EA);
3395 if (unlikely(ctx->le_mode)) {
3396 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3397 tcg_gen_addi_tl(EA, EA, 8);
3398 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3399 } else {
3400 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3401 tcg_gen_addi_tl(EA, EA, 8);
3402 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3403 }
3404 tcg_temp_free(EA);
3405 }
3406
3407 /* lfiwax */
3408 static void gen_lfiwax(DisasContext *ctx)
3409 {
3410 TCGv EA;
3411 TCGv t0;
3412 if (unlikely(!ctx->fpu_enabled)) {
3413 gen_exception(ctx, POWERPC_EXCP_FPU);
3414 return;
3415 }
3416 gen_set_access_type(ctx, ACCESS_FLOAT);
3417 EA = tcg_temp_new();
3418 t0 = tcg_temp_new();
3419 gen_addr_reg_index(ctx, EA);
3420 gen_qemu_ld32s(ctx, t0, EA);
3421 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3422 tcg_temp_free(EA);
3423 tcg_temp_free(t0);
3424 }
3425
3426 /*** Floating-point store ***/
3427 #define GEN_STF(name, stop, opc, type) \
3428 static void glue(gen_, name)(DisasContext *ctx) \
3429 { \
3430 TCGv EA; \
3431 if (unlikely(!ctx->fpu_enabled)) { \
3432 gen_exception(ctx, POWERPC_EXCP_FPU); \
3433 return; \
3434 } \
3435 gen_set_access_type(ctx, ACCESS_FLOAT); \
3436 EA = tcg_temp_new(); \
3437 gen_addr_imm_index(ctx, EA, 0); \
3438 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3439 tcg_temp_free(EA); \
3440 }
3441
3442 #define GEN_STUF(name, stop, opc, type) \
3443 static void glue(gen_, name##u)(DisasContext *ctx) \
3444 { \
3445 TCGv EA; \
3446 if (unlikely(!ctx->fpu_enabled)) { \
3447 gen_exception(ctx, POWERPC_EXCP_FPU); \
3448 return; \
3449 } \
3450 if (unlikely(rA(ctx->opcode) == 0)) { \
3451 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3452 return; \
3453 } \
3454 gen_set_access_type(ctx, ACCESS_FLOAT); \
3455 EA = tcg_temp_new(); \
3456 gen_addr_imm_index(ctx, EA, 0); \
3457 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3458 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3459 tcg_temp_free(EA); \
3460 }
3461
3462 #define GEN_STUXF(name, stop, opc, type) \
3463 static void glue(gen_, name##ux)(DisasContext *ctx) \
3464 { \
3465 TCGv EA; \
3466 if (unlikely(!ctx->fpu_enabled)) { \
3467 gen_exception(ctx, POWERPC_EXCP_FPU); \
3468 return; \
3469 } \
3470 if (unlikely(rA(ctx->opcode) == 0)) { \
3471 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3472 return; \
3473 } \
3474 gen_set_access_type(ctx, ACCESS_FLOAT); \
3475 EA = tcg_temp_new(); \
3476 gen_addr_reg_index(ctx, EA); \
3477 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3478 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3479 tcg_temp_free(EA); \
3480 }
3481
3482 #define GEN_STXF(name, stop, opc2, opc3, type) \
3483 static void glue(gen_, name##x)(DisasContext *ctx) \
3484 { \
3485 TCGv EA; \
3486 if (unlikely(!ctx->fpu_enabled)) { \
3487 gen_exception(ctx, POWERPC_EXCP_FPU); \
3488 return; \
3489 } \
3490 gen_set_access_type(ctx, ACCESS_FLOAT); \
3491 EA = tcg_temp_new(); \
3492 gen_addr_reg_index(ctx, EA); \
3493 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3494 tcg_temp_free(EA); \
3495 }
3496
3497 #define GEN_STFS(name, stop, op, type) \
3498 GEN_STF(name, stop, op | 0x20, type); \
3499 GEN_STUF(name, stop, op | 0x21, type); \
3500 GEN_STUXF(name, stop, op | 0x01, type); \
3501 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3502
3503 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3504 {
3505 TCGv_i32 t0 = tcg_temp_new_i32();
3506 TCGv t1 = tcg_temp_new();
3507 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3508 tcg_gen_extu_i32_tl(t1, t0);
3509 tcg_temp_free_i32(t0);
3510 gen_qemu_st32(ctx, t1, arg2);
3511 tcg_temp_free(t1);
3512 }
3513
3514 /* stfd stfdu stfdux stfdx */
3515 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3516 /* stfs stfsu stfsux stfsx */
3517 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3518
3519 /* stfdp */
3520 static void gen_stfdp(DisasContext *ctx)
3521 {
3522 TCGv EA;
3523 if (unlikely(!ctx->fpu_enabled)) {
3524 gen_exception(ctx, POWERPC_EXCP_FPU);
3525 return;
3526 }
3527 gen_set_access_type(ctx, ACCESS_FLOAT);
3528 EA = tcg_temp_new();
3529 gen_addr_imm_index(ctx, EA, 0); \
3530 if (unlikely(ctx->le_mode)) {
3531 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3532 tcg_gen_addi_tl(EA, EA, 8);
3533 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3534 } else {
3535 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3536 tcg_gen_addi_tl(EA, EA, 8);
3537 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3538 }
3539 tcg_temp_free(EA);
3540 }
3541
3542 /* stfdpx */
3543 static void gen_stfdpx(DisasContext *ctx)
3544 {
3545 TCGv EA;
3546 if (unlikely(!ctx->fpu_enabled)) {
3547 gen_exception(ctx, POWERPC_EXCP_FPU);
3548 return;
3549 }
3550 gen_set_access_type(ctx, ACCESS_FLOAT);
3551 EA = tcg_temp_new();
3552 gen_addr_reg_index(ctx, EA);
3553 if (unlikely(ctx->le_mode)) {
3554 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3555 tcg_gen_addi_tl(EA, EA, 8);
3556 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3557 } else {
3558 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3559 tcg_gen_addi_tl(EA, EA, 8);
3560 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3561 }
3562 tcg_temp_free(EA);
3563 }
3564
3565 /* Optional: */
3566 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3567 {
3568 TCGv t0 = tcg_temp_new();
3569 tcg_gen_trunc_i64_tl(t0, arg1),
3570 gen_qemu_st32(ctx, t0, arg2);
3571 tcg_temp_free(t0);
3572 }
3573 /* stfiwx */
3574 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3575
3576 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3577 {
3578 #if defined(TARGET_PPC64)
3579 if (ctx->has_cfar)
3580 tcg_gen_movi_tl(cpu_cfar, nip);
3581 #endif
3582 }
3583
3584 /*** Branch ***/
3585 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3586 {
3587 TranslationBlock *tb;
3588 tb = ctx->tb;
3589 if (NARROW_MODE(ctx)) {
3590 dest = (uint32_t) dest;
3591 }
3592 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3593 likely(!ctx->singlestep_enabled)) {
3594 tcg_gen_goto_tb(n);
3595 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3596 tcg_gen_exit_tb((uintptr_t)tb + n);
3597 } else {
3598 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3599 if (unlikely(ctx->singlestep_enabled)) {
3600 if ((ctx->singlestep_enabled &
3601 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3602 (ctx->exception == POWERPC_EXCP_BRANCH ||
3603 ctx->exception == POWERPC_EXCP_TRACE)) {
3604 target_ulong tmp = ctx->nip;
3605 ctx->nip = dest;
3606 gen_exception(ctx, POWERPC_EXCP_TRACE);
3607 ctx->nip = tmp;
3608 }
3609 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3610 gen_debug_exception(ctx);
3611 }
3612 }
3613 tcg_gen_exit_tb(0);
3614 }
3615 }
3616
3617 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3618 {
3619 if (NARROW_MODE(ctx)) {
3620 nip = (uint32_t)nip;
3621 }
3622 tcg_gen_movi_tl(cpu_lr, nip);
3623 }
3624
3625 /* b ba bl bla */
3626 static void gen_b(DisasContext *ctx)
3627 {
3628 target_ulong li, target;
3629
3630 ctx->exception = POWERPC_EXCP_BRANCH;
3631 /* sign extend LI */
3632 li = LI(ctx->opcode);
3633 li = (li ^ 0x02000000) - 0x02000000;
3634 if (likely(AA(ctx->opcode) == 0)) {
3635 target = ctx->nip + li - 4;
3636 } else {
3637 target = li;
3638 }
3639 if (LK(ctx->opcode)) {
3640 gen_setlr(ctx, ctx->nip);
3641 }
3642 gen_update_cfar(ctx, ctx->nip);
3643 gen_goto_tb(ctx, 0, target);
3644 }
3645
3646 #define BCOND_IM 0
3647 #define BCOND_LR 1
3648 #define BCOND_CTR 2
3649
3650 static inline void gen_bcond(DisasContext *ctx, int type)
3651 {
3652 uint32_t bo = BO(ctx->opcode);
3653 int l1;
3654 TCGv target;
3655
3656 ctx->exception = POWERPC_EXCP_BRANCH;
3657 if (type == BCOND_LR || type == BCOND_CTR) {
3658 target = tcg_temp_local_new();
3659 if (type == BCOND_CTR)
3660 tcg_gen_mov_tl(target, cpu_ctr);
3661 else
3662 tcg_gen_mov_tl(target, cpu_lr);
3663 } else {
3664 TCGV_UNUSED(target);
3665 }
3666 if (LK(ctx->opcode))
3667 gen_setlr(ctx, ctx->nip);
3668 l1 = gen_new_label();
3669 if ((bo & 0x4) == 0) {
3670 /* Decrement and test CTR */
3671 TCGv temp = tcg_temp_new();
3672 if (unlikely(type == BCOND_CTR)) {
3673 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3674 return;
3675 }
3676 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3677 if (NARROW_MODE(ctx)) {
3678 tcg_gen_ext32u_tl(temp, cpu_ctr);
3679 } else {
3680 tcg_gen_mov_tl(temp, cpu_ctr);
3681 }
3682 if (bo & 0x2) {
3683 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3684 } else {
3685 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3686 }
3687 tcg_temp_free(temp);
3688 }
3689 if ((bo & 0x10) == 0) {
3690 /* Test CR */
3691 uint32_t bi = BI(ctx->opcode);
3692 uint32_t mask = 1 << (3 - (bi & 0x03));
3693 TCGv_i32 temp = tcg_temp_new_i32();
3694
3695 if (bo & 0x8) {
3696 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3697 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3698 } else {
3699 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3700 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3701 }
3702 tcg_temp_free_i32(temp);
3703 }
3704 gen_update_cfar(ctx, ctx->nip);
3705 if (type == BCOND_IM) {
3706 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3707 if (likely(AA(ctx->opcode) == 0)) {
3708 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3709 } else {
3710 gen_goto_tb(ctx, 0, li);
3711 }
3712 gen_set_label(l1);
3713 gen_goto_tb(ctx, 1, ctx->nip);
3714 } else {
3715 if (NARROW_MODE(ctx)) {
3716 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3717 } else {
3718 tcg_gen_andi_tl(cpu_nip, target, ~3);
3719 }
3720 tcg_gen_exit_tb(0);
3721 gen_set_label(l1);
3722 gen_update_nip(ctx, ctx->nip);
3723 tcg_gen_exit_tb(0);
3724 }
3725 }
3726
3727 static void gen_bc(DisasContext *ctx)
3728 {
3729 gen_bcond(ctx, BCOND_IM);
3730 }
3731
3732 static void gen_bcctr(DisasContext *ctx)
3733 {
3734 gen_bcond(ctx, BCOND_CTR);
3735 }
3736
3737 static void gen_bclr(DisasContext *ctx)
3738 {
3739 gen_bcond(ctx, BCOND_LR);
3740 }
3741
3742 /*** Condition register logical ***/
3743 #define GEN_CRLOGIC(name, tcg_op, opc) \
3744 static void glue(gen_, name)(DisasContext *ctx) \
3745 { \
3746 uint8_t bitmask; \
3747 int sh; \
3748 TCGv_i32 t0, t1; \
3749 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3750 t0 = tcg_temp_new_i32(); \
3751 if (sh > 0) \
3752 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3753 else if (sh < 0) \
3754 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3755 else \
3756 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3757 t1 = tcg_temp_new_i32(); \
3758 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3759 if (sh > 0) \
3760 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3761 else if (sh < 0) \
3762 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3763 else \
3764 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3765 tcg_op(t0, t0, t1); \
3766 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3767 tcg_gen_andi_i32(t0, t0, bitmask); \
3768 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3769 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3770 tcg_temp_free_i32(t0); \
3771 tcg_temp_free_i32(t1); \
3772 }
3773
3774 /* crand */
3775 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3776 /* crandc */
3777 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3778 /* creqv */
3779 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3780 /* crnand */
3781 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3782 /* crnor */
3783 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3784 /* cror */
3785 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3786 /* crorc */
3787 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3788 /* crxor */
3789 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3790
3791 /* mcrf */
3792 static void gen_mcrf(DisasContext *ctx)
3793 {
3794 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3795 }
3796
3797 /*** System linkage ***/
3798
3799 /* rfi (mem_idx only) */
3800 static void gen_rfi(DisasContext *ctx)
3801 {
3802 #if defined(CONFIG_USER_ONLY)
3803 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3804 #else
3805 /* Restore CPU state */
3806 if (unlikely(!ctx->mem_idx)) {
3807 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3808 return;
3809 }
3810 gen_update_cfar(ctx, ctx->nip);
3811 gen_helper_rfi(cpu_env);
3812 gen_sync_exception(ctx);
3813 #endif
3814 }
3815
3816 #if defined(TARGET_PPC64)
3817 static void gen_rfid(DisasContext *ctx)
3818 {
3819 #if defined(CONFIG_USER_ONLY)
3820 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3821 #else
3822 /* Restore CPU state */
3823 if (unlikely(!ctx->mem_idx)) {
3824 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3825 return;
3826 }
3827 gen_update_cfar(ctx, ctx->nip);
3828 gen_helper_rfid(cpu_env);
3829 gen_sync_exception(ctx);
3830 #endif
3831 }
3832
3833 static void gen_hrfid(DisasContext *ctx)
3834 {
3835 #if defined(CONFIG_USER_ONLY)
3836 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3837 #else
3838 /* Restore CPU state */
3839 if (unlikely(ctx->mem_idx <= 1)) {
3840 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3841 return;
3842 }
3843 gen_helper_hrfid(cpu_env);
3844 gen_sync_exception(ctx);
3845 #endif
3846 }
3847 #endif
3848
3849 /* sc */
3850 #if defined(CONFIG_USER_ONLY)
3851 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3852 #else
3853 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3854 #endif
3855 static void gen_sc(DisasContext *ctx)
3856 {
3857 uint32_t lev;
3858
3859 lev = (ctx->opcode >> 5) & 0x7F;
3860 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3861 }
3862
3863 /*** Trap ***/
3864
3865 /* tw */
3866 static void gen_tw(DisasContext *ctx)
3867 {
3868 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3869 /* Update the nip since this might generate a trap exception */
3870 gen_update_nip(ctx, ctx->nip);
3871 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3872 t0);
3873 tcg_temp_free_i32(t0);
3874 }
3875
3876 /* twi */
3877 static void gen_twi(DisasContext *ctx)
3878 {
3879 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3880 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3881 /* Update the nip since this might generate a trap exception */
3882 gen_update_nip(ctx, ctx->nip);
3883 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3884 tcg_temp_free(t0);
3885 tcg_temp_free_i32(t1);
3886 }
3887
3888 #if defined(TARGET_PPC64)
3889 /* td */
3890 static void gen_td(DisasContext *ctx)
3891 {
3892 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3893 /* Update the nip since this might generate a trap exception */
3894 gen_update_nip(ctx, ctx->nip);
3895 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3896 t0);
3897 tcg_temp_free_i32(t0);
3898 }
3899
3900 /* tdi */
3901 static void gen_tdi(DisasContext *ctx)
3902 {
3903 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3904 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3905 /* Update the nip since this might generate a trap exception */
3906 gen_update_nip(ctx, ctx->nip);
3907 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3908 tcg_temp_free(t0);
3909 tcg_temp_free_i32(t1);
3910 }
3911 #endif
3912
3913 /*** Processor control ***/
3914
3915 static void gen_read_xer(TCGv dst)
3916 {
3917 TCGv t0 = tcg_temp_new();
3918 TCGv t1 = tcg_temp_new();
3919 TCGv t2 = tcg_temp_new();
3920 tcg_gen_mov_tl(dst, cpu_xer);
3921 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3922 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3923 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3924 tcg_gen_or_tl(t0, t0, t1);
3925 tcg_gen_or_tl(dst, dst, t2);
3926 tcg_gen_or_tl(dst, dst, t0);
3927 tcg_temp_free(t0);
3928 tcg_temp_free(t1);
3929 tcg_temp_free(t2);
3930 }
3931
3932 static void gen_write_xer(TCGv src)
3933 {
3934 tcg_gen_andi_tl(cpu_xer, src,
3935 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3936 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3937 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3938 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3939 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3940 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3941 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3942 }
3943
3944 /* mcrxr */
3945 static void gen_mcrxr(DisasContext *ctx)
3946 {
3947 TCGv_i32 t0 = tcg_temp_new_i32();
3948 TCGv_i32 t1 = tcg_temp_new_i32();
3949 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3950
3951 tcg_gen_trunc_tl_i32(t0, cpu_so);
3952 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3953 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3954 tcg_gen_shri_i32(t0, t0, 2);
3955 tcg_gen_shri_i32(t1, t1, 1);
3956 tcg_gen_or_i32(dst, dst, t0);
3957 tcg_gen_or_i32(dst, dst, t1);
3958 tcg_temp_free_i32(t0);
3959 tcg_temp_free_i32(t1);
3960
3961 tcg_gen_movi_tl(cpu_so, 0);
3962 tcg_gen_movi_tl(cpu_ov, 0);
3963 tcg_gen_movi_tl(cpu_ca, 0);
3964 }
3965
3966 /* mfcr mfocrf */
3967 static void gen_mfcr(DisasContext *ctx)
3968 {
3969 uint32_t crm, crn;
3970
3971 if (likely(ctx->opcode & 0x00100000)) {
3972 crm = CRM(ctx->opcode);
3973 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3974 crn = ctz32 (crm);
3975 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3976 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3977 cpu_gpr[rD(ctx->opcode)], crn * 4);
3978 }
3979 } else {
3980 TCGv_i32 t0 = tcg_temp_new_i32();
3981 tcg_gen_mov_i32(t0, cpu_crf[0]);
3982 tcg_gen_shli_i32(t0, t0, 4);
3983 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3984 tcg_gen_shli_i32(t0, t0, 4);
3985 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3986 tcg_gen_shli_i32(t0, t0, 4);
3987 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3988 tcg_gen_shli_i32(t0, t0, 4);
3989 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3990 tcg_gen_shli_i32(t0, t0, 4);
3991 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3992 tcg_gen_shli_i32(t0, t0, 4);
3993 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3994 tcg_gen_shli_i32(t0, t0, 4);
3995 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3996 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3997 tcg_temp_free_i32(t0);
3998 }
3999 }
4000
4001 /* mfmsr */
4002 static void gen_mfmsr(DisasContext *ctx)
4003 {
4004 #if defined(CONFIG_USER_ONLY)
4005 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4006 #else
4007 if (unlikely(!ctx->mem_idx)) {
4008 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4009 return;
4010 }
4011 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4012 #endif
4013 }
4014
4015 static void spr_noaccess(void *opaque, int gprn, int sprn)
4016 {
4017 #if 0
4018 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4019 printf("ERROR: try to access SPR %d !\n", sprn);
4020 #endif
4021 }
4022 #define SPR_NOACCESS (&spr_noaccess)
4023
4024 /* mfspr */
4025 static inline void gen_op_mfspr(DisasContext *ctx)
4026 {
4027 void (*read_cb)(void *opaque, int gprn, int sprn);
4028 uint32_t sprn = SPR(ctx->opcode);
4029
4030 #if !defined(CONFIG_USER_ONLY)
4031 if (ctx->mem_idx == 2)
4032 read_cb = ctx->spr_cb[sprn].hea_read;
4033 else if (ctx->mem_idx)
4034 read_cb = ctx->spr_cb[sprn].oea_read;
4035 else
4036 #endif
4037 read_cb = ctx->spr_cb[sprn].uea_read;
4038 if (likely(read_cb != NULL)) {
4039 if (likely(read_cb != SPR_NOACCESS)) {
4040 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4041 } else {
4042 /* Privilege exception */
4043 /* This is a hack to avoid warnings when running Linux:
4044 * this OS breaks the PowerPC virtualisation model,
4045 * allowing userland application to read the PVR
4046 */
4047 if (sprn != SPR_PVR) {
4048 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4049 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4050 printf("Trying to read privileged spr %d (0x%03x) at "
4051 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4052 }
4053 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4054 }
4055 } else {
4056 /* Not defined */
4057 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4058 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4059 printf("Trying to read invalid spr %d (0x%03x) at "
4060 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4061 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4062 }
4063 }
4064
4065 static void gen_mfspr(DisasContext *ctx)
4066 {
4067 gen_op_mfspr(ctx);
4068 }
4069
4070 /* mftb */
4071 static void gen_mftb(DisasContext *ctx)
4072 {
4073 gen_op_mfspr(ctx);
4074 }
4075
4076 /* mtcrf mtocrf*/
4077 static void gen_mtcrf(DisasContext *ctx)
4078 {
4079 uint32_t crm, crn;
4080
4081 crm = CRM(ctx->opcode);
4082 if (likely((ctx->opcode & 0x00100000))) {
4083 if (crm && ((crm & (crm - 1)) == 0)) {
4084 TCGv_i32 temp = tcg_temp_new_i32();
4085 crn = ctz32 (crm);
4086 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4087 tcg_gen_shri_i32(temp, temp, crn * 4);
4088 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4089 tcg_temp_free_i32(temp);
4090 }
4091 } else {
4092 TCGv_i32 temp = tcg_temp_new_i32();
4093 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4094 for (crn = 0 ; crn < 8 ; crn++) {
4095 if (crm & (1 << crn)) {
4096 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4097 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4098 }
4099 }
4100 tcg_temp_free_i32(temp);
4101 }
4102 }
4103
4104 /* mtmsr */
4105 #if defined(TARGET_PPC64)
4106 static void gen_mtmsrd(DisasContext *ctx)
4107 {
4108 #if defined(CONFIG_USER_ONLY)
4109 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4110 #else
4111 if (unlikely(!ctx->mem_idx)) {
4112 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4113 return;
4114 }
4115 if (ctx->opcode & 0x00010000) {
4116 /* Special form that does not need any synchronisation */
4117 TCGv t0 = tcg_temp_new();
4118 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4119 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4120 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4121 tcg_temp_free(t0);
4122 } else {
4123 /* XXX: we need to update nip before the store
4124 * if we enter power saving mode, we will exit the loop
4125 * directly from ppc_store_msr
4126 */
4127 gen_update_nip(ctx, ctx->nip);
4128 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4129 /* Must stop the translation as machine state (may have) changed */
4130 /* Note that mtmsr is not always defined as context-synchronizing */
4131 gen_stop_exception(ctx);
4132 }
4133 #endif
4134 }
4135 #endif
4136
4137 static void gen_mtmsr(DisasContext *ctx)
4138 {
4139 #if defined(CONFIG_USER_ONLY)
4140 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4141 #else
4142 if (unlikely(!ctx->mem_idx)) {
4143 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4144 return;
4145 }
4146 if (ctx->opcode & 0x00010000) {
4147 /* Special form that does not need any synchronisation */
4148 TCGv t0 = tcg_temp_new();
4149 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4150 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4151 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4152 tcg_temp_free(t0);
4153 } else {
4154 TCGv msr = tcg_temp_new();
4155
4156 /* XXX: we need to update nip before the store
4157 * if we enter power saving mode, we will exit the loop
4158 * directly from ppc_store_msr
4159 */
4160 gen_update_nip(ctx, ctx->nip);
4161 #if defined(TARGET_PPC64)
4162 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4163 #else
4164 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4165 #endif
4166 gen_helper_store_msr(cpu_env, msr);
4167 /* Must stop the translation as machine state (may have) changed */
4168 /* Note that mtmsr is not always defined as context-synchronizing */
4169 gen_stop_exception(ctx);
4170 }
4171 #endif
4172 }
4173
4174 /* mtspr */
4175 static void gen_mtspr(DisasContext *ctx)
4176 {
4177 void (*write_cb)(void *opaque, int sprn, int gprn);
4178 uint32_t sprn = SPR(ctx->opcode);
4179
4180 #if !defined(CONFIG_USER_ONLY)
4181 if (ctx->mem_idx == 2)
4182 write_cb = ctx->spr_cb[sprn].hea_write;
4183 else if (ctx->mem_idx)
4184 write_cb = ctx->spr_cb[sprn].oea_write;
4185 else
4186 #endif
4187 write_cb = ctx->spr_cb[sprn].uea_write;
4188 if (likely(write_cb != NULL)) {
4189 if (likely(write_cb != SPR_NOACCESS)) {
4190 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4191 } else {
4192 /* Privilege exception */
4193 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4194 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4195 printf("Trying to write privileged spr %d (0x%03x) at "
4196 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4197 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4198 }
4199 } else {
4200 /* Not defined */
4201 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4202 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4203 printf("Trying to write invalid spr %d (0x%03x) at "
4204 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4205 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4206 }
4207 }
4208
4209 /*** Cache management ***/
4210
4211 /* dcbf */
4212 static void gen_dcbf(DisasContext *ctx)
4213 {
4214 /* XXX: specification says this is treated as a load by the MMU */
4215 TCGv t0;
4216 gen_set_access_type(ctx, ACCESS_CACHE);
4217 t0 = tcg_temp_new();
4218 gen_addr_reg_index(ctx, t0);
4219 gen_qemu_ld8u(ctx, t0, t0);
4220 tcg_temp_free(t0);
4221 }
4222
4223 /* dcbi (Supervisor only) */
4224 static void gen_dcbi(DisasContext *ctx)
4225 {
4226 #if defined(CONFIG_USER_ONLY)
4227 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4228 #else
4229 TCGv EA, val;
4230 if (unlikely(!ctx->mem_idx)) {
4231 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4232 return;
4233 }
4234 EA = tcg_temp_new();
4235 gen_set_access_type(ctx, ACCESS_CACHE);
4236 gen_addr_reg_index(ctx, EA);
4237 val = tcg_temp_new();
4238 /* XXX: specification says this should be treated as a store by the MMU */
4239 gen_qemu_ld8u(ctx, val, EA);
4240 gen_qemu_st8(ctx, val, EA);
4241 tcg_temp_free(val);
4242 tcg_temp_free(EA);
4243 #endif
4244 }
4245
4246 /* dcdst */
4247 static void gen_dcbst(DisasContext *ctx)
4248 {
4249 /* XXX: specification say this is treated as a load by the MMU */
4250 TCGv t0;
4251 gen_set_access_type(ctx, ACCESS_CACHE);
4252 t0 = tcg_temp_new();
4253 gen_addr_reg_index(ctx, t0);
4254 gen_qemu_ld8u(ctx, t0, t0);
4255 tcg_temp_free(t0);
4256 }
4257
4258 /* dcbt */
4259 static void gen_dcbt(DisasContext *ctx)
4260 {
4261 /* interpreted as no-op */
4262 /* XXX: specification say this is treated as a load by the MMU
4263 * but does not generate any exception
4264 */
4265 }
4266
4267 /* dcbtst */
4268 static void gen_dcbtst(DisasContext *ctx)
4269 {
4270 /* interpreted as no-op */
4271 /* XXX: specification say this is treated as a load by the MMU
4272 * but does not generate any exception
4273 */
4274 }
4275
4276 /* dcbz */
4277 static void gen_dcbz(DisasContext *ctx)
4278 {
4279 TCGv tcgv_addr;
4280 TCGv_i32 tcgv_is_dcbzl;
4281 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4282
4283 gen_set_access_type(ctx, ACCESS_CACHE);
4284 /* NIP cannot be restored if the memory exception comes from an helper */
4285 gen_update_nip(ctx, ctx->nip - 4);
4286 tcgv_addr = tcg_temp_new();
4287 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4288
4289 gen_addr_reg_index(ctx, tcgv_addr);
4290 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4291
4292 tcg_temp_free(tcgv_addr);
4293 tcg_temp_free_i32(tcgv_is_dcbzl);
4294 }
4295
4296 /* dst / dstt */
4297 static void gen_dst(DisasContext *ctx)
4298 {
4299 if (rA(ctx->opcode) == 0) {
4300 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4301 } else {
4302 /* interpreted as no-op */
4303 }
4304 }
4305
4306 /* dstst /dststt */
4307 static void gen_dstst(DisasContext *ctx)
4308 {
4309 if (rA(ctx->opcode) == 0) {
4310 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4311 } else {
4312 /* interpreted as no-op */
4313 }
4314
4315 }
4316
4317 /* dss / dssall */
4318 static void gen_dss(DisasContext *ctx)
4319 {
4320 /* interpreted as no-op */
4321 }
4322
4323 /* icbi */
4324 static void gen_icbi(DisasContext *ctx)
4325 {
4326 TCGv t0;
4327 gen_set_access_type(ctx, ACCESS_CACHE);
4328 /* NIP cannot be restored if the memory exception comes from an helper */
4329 gen_update_nip(ctx, ctx->nip - 4);
4330 t0 = tcg_temp_new();
4331 gen_addr_reg_index(ctx, t0);
4332 gen_helper_icbi(cpu_env, t0);
4333 tcg_temp_free(t0);
4334 }
4335
4336 /* Optional: */
4337 /* dcba */
4338 static void gen_dcba(DisasContext *ctx)
4339 {
4340 /* interpreted as no-op */
4341 /* XXX: specification say this is treated as a store by the MMU
4342 * but does not generate any exception
4343 */
4344 }
4345
4346 /*** Segment register manipulation ***/
4347 /* Supervisor only: */
4348
4349 /* mfsr */
4350 static void gen_mfsr(DisasContext *ctx)
4351 {
4352 #if defined(CONFIG_USER_ONLY)
4353 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4354 #else
4355 TCGv t0;
4356 if (unlikely(!ctx->mem_idx)) {
4357 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4358 return;
4359 }
4360 t0 = tcg_const_tl(SR(ctx->opcode));
4361 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4362 tcg_temp_free(t0);
4363 #endif
4364 }
4365
4366 /* mfsrin */
4367 static void gen_mfsrin(DisasContext *ctx)
4368 {
4369 #if defined(CONFIG_USER_ONLY)
4370 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4371 #else
4372 TCGv t0;
4373 if (unlikely(!ctx->mem_idx)) {
4374 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4375 return;
4376 }
4377 t0 = tcg_temp_new();
4378 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4379 tcg_gen_andi_tl(t0, t0, 0xF);
4380 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4381 tcg_temp_free(t0);
4382 #endif
4383 }
4384
4385 /* mtsr */
4386 static void gen_mtsr(DisasContext *ctx)
4387 {
4388 #if defined(CONFIG_USER_ONLY)
4389 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4390 #else
4391 TCGv t0;
4392 if (unlikely(!ctx->mem_idx)) {
4393 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4394 return;
4395 }
4396 t0 = tcg_const_tl(SR(ctx->opcode));
4397 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4398 tcg_temp_free(t0);
4399 #endif
4400 }
4401
4402 /* mtsrin */
4403 static void gen_mtsrin(DisasContext *ctx)
4404 {
4405 #if defined(CONFIG_USER_ONLY)
4406 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4407 #else
4408 TCGv t0;
4409 if (unlikely(!ctx->mem_idx)) {
4410 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4411 return;
4412 }
4413 t0 = tcg_temp_new();
4414 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4415 tcg_gen_andi_tl(t0, t0, 0xF);
4416 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4417 tcg_temp_free(t0);
4418 #endif
4419 }
4420
4421 #if defined(TARGET_PPC64)
4422 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4423
4424 /* mfsr */
4425 static void gen_mfsr_64b(DisasContext *ctx)
4426 {
4427 #if defined(CONFIG_USER_ONLY)
4428 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4429 #else
4430 TCGv t0;
4431 if (unlikely(!ctx->mem_idx)) {
4432 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4433 return;
4434 }
4435 t0 = tcg_const_tl(SR(ctx->opcode));
4436 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4437 tcg_temp_free(t0);
4438 #endif
4439 }
4440
4441 /* mfsrin */
4442 static void gen_mfsrin_64b(DisasContext *ctx)
4443 {
4444 #if defined(CONFIG_USER_ONLY)
4445 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4446 #else
4447 TCGv t0;
4448 if (unlikely(!ctx->mem_idx)) {
4449 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4450 return;
4451 }
4452 t0 = tcg_temp_new();
4453 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4454 tcg_gen_andi_tl(t0, t0, 0xF);
4455 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4456 tcg_temp_free(t0);
4457 #endif
4458 }
4459
4460 /* mtsr */
4461 static void gen_mtsr_64b(DisasContext *ctx)
4462 {
4463 #if defined(CONFIG_USER_ONLY)
4464 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4465 #else
4466 TCGv t0;
4467 if (unlikely(!ctx->mem_idx)) {
4468 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4469 return;
4470 }
4471 t0 = tcg_const_tl(SR(ctx->opcode));
4472 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4473 tcg_temp_free(t0);
4474 #endif
4475 }
4476
4477 /* mtsrin */
4478 static void gen_mtsrin_64b(DisasContext *ctx)
4479 {
4480 #if defined(CONFIG_USER_ONLY)
4481 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4482 #else
4483 TCGv t0;
4484 if (unlikely(!ctx->mem_idx)) {
4485 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4486 return;
4487 }
4488 t0 = tcg_temp_new();
4489 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4490 tcg_gen_andi_tl(t0, t0, 0xF);
4491 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4492 tcg_temp_free(t0);
4493 #endif
4494 }
4495
4496 /* slbmte */
4497 static void gen_slbmte(DisasContext *ctx)
4498 {
4499 #if defined(CONFIG_USER_ONLY)
4500 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4501 #else
4502 if (unlikely(!ctx->mem_idx)) {
4503 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4504 return;
4505 }
4506 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4507 cpu_gpr[rS(ctx->opcode)]);
4508 #endif
4509 }
4510
4511 static void gen_slbmfee(DisasContext *ctx)
4512 {
4513 #if defined(CONFIG_USER_ONLY)
4514 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4515 #else
4516 if (unlikely(!ctx->mem_idx)) {
4517 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4518 return;
4519 }
4520 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4521 cpu_gpr[rB(ctx->opcode)]);
4522 #endif
4523 }
4524
4525 static void gen_slbmfev(DisasContext *ctx)
4526 {
4527 #if defined(CONFIG_USER_ONLY)
4528 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4529 #else
4530 if (unlikely(!ctx->mem_idx)) {
4531 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4532 return;
4533 }
4534 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4535 cpu_gpr[rB(ctx->opcode)]);
4536 #endif
4537 }
4538 #endif /* defined(TARGET_PPC64) */
4539
4540 /*** Lookaside buffer management ***/
4541 /* Optional & mem_idx only: */
4542
4543 /* tlbia */
4544 static void gen_tlbia(DisasContext *ctx)
4545 {
4546 #if defined(CONFIG_USER_ONLY)
4547 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4548 #else
4549 if (unlikely(!ctx->mem_idx)) {
4550 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4551 return;
4552 }
4553 gen_helper_tlbia(cpu_env);
4554 #endif
4555 }
4556
4557 /* tlbiel */
4558 static void gen_tlbiel(DisasContext *ctx)
4559 {
4560 #if defined(CONFIG_USER_ONLY)
4561 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4562 #else
4563 if (unlikely(!ctx->mem_idx)) {
4564 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4565 return;
4566 }
4567 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4568 #endif
4569 }
4570
4571 /* tlbie */
4572 static void gen_tlbie(DisasContext *ctx)
4573 {
4574 #if defined(CONFIG_USER_ONLY)
4575 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4576 #else
4577 if (unlikely(!ctx->mem_idx)) {
4578 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4579 return;
4580 }
4581 if (NARROW_MODE(ctx)) {
4582 TCGv t0 = tcg_temp_new();
4583 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4584 gen_helper_tlbie(cpu_env, t0);
4585 tcg_temp_free(t0);
4586 } else {
4587 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4588 }
4589 #endif
4590 }
4591
4592 /* tlbsync */
4593 static void gen_tlbsync(DisasContext *ctx)
4594 {
4595 #if defined(CONFIG_USER_ONLY)
4596 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4597 #else
4598 if (unlikely(!ctx->mem_idx)) {
4599 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4600 return;
4601 }
4602 /* This has no effect: it should ensure that all previous
4603 * tlbie have completed
4604 */
4605 gen_stop_exception(ctx);
4606 #endif
4607 }
4608
4609 #if defined(TARGET_PPC64)
4610 /* slbia */
4611 static void gen_slbia(DisasContext *ctx)
4612 {
4613 #if defined(CONFIG_USER_ONLY)
4614 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4615 #else
4616 if (unlikely(!ctx->mem_idx)) {
4617 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4618 return;
4619 }
4620 gen_helper_slbia(cpu_env);
4621 #endif
4622 }
4623
4624 /* slbie */
4625 static void gen_slbie(DisasContext *ctx)
4626 {
4627 #if defined(CONFIG_USER_ONLY)
4628 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4629 #else
4630 if (unlikely(!ctx->mem_idx)) {
4631 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4632 return;
4633 }
4634 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4635 #endif
4636 }
4637 #endif
4638
4639 /*** External control ***/
4640 /* Optional: */
4641
4642 /* eciwx */
4643 static void gen_eciwx(DisasContext *ctx)
4644 {
4645 TCGv t0;
4646 /* Should check EAR[E] ! */
4647 gen_set_access_type(ctx, ACCESS_EXT);
4648 t0 = tcg_temp_new();
4649 gen_addr_reg_index(ctx, t0);
4650 gen_check_align(ctx, t0, 0x03);
4651 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4652 tcg_temp_free(t0);
4653 }
4654
4655 /* ecowx */
4656 static void gen_ecowx(DisasContext *ctx)
4657 {
4658 TCGv t0;
4659 /* Should check EAR[E] ! */
4660 gen_set_access_type(ctx, ACCESS_EXT);
4661 t0 = tcg_temp_new();
4662 gen_addr_reg_index(ctx, t0);
4663 gen_check_align(ctx, t0, 0x03);
4664 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4665 tcg_temp_free(t0);
4666 }
4667
4668 /* PowerPC 601 specific instructions */
4669
4670 /* abs - abs. */
4671 static void gen_abs(DisasContext *ctx)
4672 {
4673 int l1 = gen_new_label();
4674 int l2 = gen_new_label();
4675 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4676 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4677 tcg_gen_br(l2);
4678 gen_set_label(l1);
4679 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4680 gen_set_label(l2);
4681 if (unlikely(Rc(ctx->opcode) != 0))
4682 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4683 }
4684
4685 /* abso - abso. */
4686 static void gen_abso(DisasContext *ctx)
4687 {
4688 int l1 = gen_new_label();
4689 int l2 = gen_new_label();
4690 int l3 = gen_new_label();
4691 /* Start with XER OV disabled, the most likely case */
4692 tcg_gen_movi_tl(cpu_ov, 0);
4693 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4694 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4695 tcg_gen_movi_tl(cpu_ov, 1);
4696 tcg_gen_movi_tl(cpu_so, 1);
4697 tcg_gen_br(l2);
4698 gen_set_label(l1);
4699 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4700 tcg_gen_br(l3);
4701 gen_set_label(l2);
4702 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4703 gen_set_label(l3);
4704 if (unlikely(Rc(ctx->opcode) != 0))
4705 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4706 }
4707
4708 /* clcs */
4709 static void gen_clcs(DisasContext *ctx)
4710 {
4711 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4712 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4713 tcg_temp_free_i32(t0);
4714 /* Rc=1 sets CR0 to an undefined state */
4715 }
4716
4717 /* div - div. */
4718 static void gen_div(DisasContext *ctx)
4719 {
4720 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4721 cpu_gpr[rB(ctx->opcode)]);
4722 if (unlikely(Rc(ctx->opcode) != 0))
4723 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4724 }
4725
4726 /* divo - divo. */
4727 static void gen_divo(DisasContext *ctx)
4728 {
4729 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4730 cpu_gpr[rB(ctx->opcode)]);
4731 if (unlikely(Rc(ctx->opcode) != 0))
4732 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4733 }
4734
4735 /* divs - divs. */
4736 static void gen_divs(DisasContext *ctx)
4737 {
4738 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4739 cpu_gpr[rB(ctx->opcode)]);
4740 if (unlikely(Rc(ctx->opcode) != 0))
4741 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4742 }
4743
4744 /* divso - divso. */
4745 static void gen_divso(DisasContext *ctx)
4746 {
4747 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4748 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4749 if (unlikely(Rc(ctx->opcode) != 0))
4750 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4751 }
4752
4753 /* doz - doz. */
4754 static void gen_doz(DisasContext *ctx)
4755 {
4756 int l1 = gen_new_label();
4757 int l2 = gen_new_label();
4758 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4759 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4760 tcg_gen_br(l2);
4761 gen_set_label(l1);
4762 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4763 gen_set_label(l2);
4764 if (unlikely(Rc(ctx->opcode) != 0))
4765 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4766 }
4767
4768 /* dozo - dozo. */
4769 static void gen_dozo(DisasContext *ctx)
4770 {
4771 int l1 = gen_new_label();
4772 int l2 = gen_new_label();
4773 TCGv t0 = tcg_temp_new();
4774 TCGv t1 = tcg_temp_new();
4775 TCGv t2 = tcg_temp_new();
4776 /* Start with XER OV disabled, the most likely case */
4777 tcg_gen_movi_tl(cpu_ov, 0);
4778 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4779 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4780 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4781 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4782 tcg_gen_andc_tl(t1, t1, t2);
4783 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4784 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4785 tcg_gen_movi_tl(cpu_ov, 1);
4786 tcg_gen_movi_tl(cpu_so, 1);
4787 tcg_gen_br(l2);
4788 gen_set_label(l1);
4789 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4790 gen_set_label(l2);
4791 tcg_temp_free(t0);
4792 tcg_temp_free(t1);
4793 tcg_temp_free(t2);
4794 if (unlikely(Rc(ctx->opcode) != 0))
4795 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4796 }
4797
4798 /* dozi */
4799 static void gen_dozi(DisasContext *ctx)
4800 {
4801 target_long simm = SIMM(ctx->opcode);
4802 int l1 = gen_new_label();
4803 int l2 = gen_new_label();
4804 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4805 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4806 tcg_gen_br(l2);
4807 gen_set_label(l1);
4808 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4809 gen_set_label(l2);
4810 if (unlikely(Rc(ctx->opcode) != 0))
4811 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4812 }
4813
4814 /* lscbx - lscbx. */
4815 static void gen_lscbx(DisasContext *ctx)
4816 {
4817 TCGv t0 = tcg_temp_new();
4818 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4819 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4820 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4821
4822 gen_addr_reg_index(ctx, t0);
4823 /* NIP cannot be restored if the memory exception comes from an helper */
4824 gen_update_nip(ctx, ctx->nip - 4);
4825 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4826 tcg_temp_free_i32(t1);
4827 tcg_temp_free_i32(t2);
4828 tcg_temp_free_i32(t3);
4829 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4830 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4831 if (unlikely(Rc(ctx->opcode) != 0))
4832 gen_set_Rc0(ctx, t0);
4833 tcg_temp_free(t0);
4834 }
4835
4836 /* maskg - maskg. */
4837 static void gen_maskg(DisasContext *ctx)
4838 {
4839 int l1 = gen_new_label();
4840 TCGv t0 = tcg_temp_new();
4841 TCGv t1 = tcg_temp_new();
4842 TCGv t2 = tcg_temp_new();
4843 TCGv t3 = tcg_temp_new();
4844 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4845 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4846 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4847 tcg_gen_addi_tl(t2, t0, 1);
4848 tcg_gen_shr_tl(t2, t3, t2);
4849 tcg_gen_shr_tl(t3, t3, t1);
4850 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4851 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4852 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4853 gen_set_label(l1);
4854 tcg_temp_free(t0);
4855 tcg_temp_free(t1);
4856 tcg_temp_free(t2);
4857 tcg_temp_free(t3);
4858 if (unlikely(Rc(ctx->opcode) != 0))
4859 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4860 }
4861
4862 /* maskir - maskir. */
4863 static void gen_maskir(DisasContext *ctx)
4864 {
4865 TCGv t0 = tcg_temp_new();
4866 TCGv t1 = tcg_temp_new();
4867 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4868 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4869 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4870 tcg_temp_free(t0);
4871 tcg_temp_free(t1);
4872 if (unlikely(Rc(ctx->opcode) != 0))
4873 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4874 }
4875
4876 /* mul - mul. */
4877 static void gen_mul(DisasContext *ctx)
4878 {
4879 TCGv_i64 t0 = tcg_temp_new_i64();
4880 TCGv_i64 t1 = tcg_temp_new_i64();
4881 TCGv t2 = tcg_temp_new();
4882 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4883 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4884 tcg_gen_mul_i64(t0, t0, t1);
4885 tcg_gen_trunc_i64_tl(t2, t0);
4886 gen_store_spr(SPR_MQ, t2);
4887 tcg_gen_shri_i64(t1, t0, 32);
4888 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4889 tcg_temp_free_i64(t0);
4890 tcg_temp_free_i64(t1);
4891 tcg_temp_free(t2);
4892 if (unlikely(Rc(ctx->opcode) != 0))
4893 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4894 }
4895
4896 /* mulo - mulo. */
4897 static void gen_mulo(DisasContext *ctx)
4898 {
4899 int l1 = gen_new_label();
4900 TCGv_i64 t0 = tcg_temp_new_i64();
4901 TCGv_i64 t1 = tcg_temp_new_i64();
4902 TCGv t2 = tcg_temp_new();
4903 /* Start with XER OV disabled, the most likely case */
4904 tcg_gen_movi_tl(cpu_ov, 0);
4905 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4906 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4907 tcg_gen_mul_i64(t0, t0, t1);
4908 tcg_gen_trunc_i64_tl(t2, t0);
4909 gen_store_spr(SPR_MQ, t2);
4910 tcg_gen_shri_i64(t1, t0, 32);
4911 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4912 tcg_gen_ext32s_i64(t1, t0);
4913 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4914 tcg_gen_movi_tl(cpu_ov, 1);
4915 tcg_gen_movi_tl(cpu_so, 1);
4916 gen_set_label(l1);
4917 tcg_temp_free_i64(t0);
4918 tcg_temp_free_i64(t1);
4919 tcg_temp_free(t2);
4920 if (unlikely(Rc(ctx->opcode) != 0))
4921 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4922 }
4923
4924 /* nabs - nabs. */
4925 static void gen_nabs(DisasContext *ctx)
4926 {
4927 int l1 = gen_new_label();
4928 int l2 = gen_new_label();
4929 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4930 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4931 tcg_gen_br(l2);
4932 gen_set_label(l1);
4933 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4934 gen_set_label(l2);
4935 if (unlikely(Rc(ctx->opcode) != 0))
4936 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4937 }
4938
4939 /* nabso - nabso. */
4940 static void gen_nabso(DisasContext *ctx)
4941 {
4942 int l1 = gen_new_label();
4943 int l2 = gen_new_label();
4944 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4945 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4946 tcg_gen_br(l2);
4947 gen_set_label(l1);
4948 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4949 gen_set_label(l2);
4950 /* nabs never overflows */
4951 tcg_gen_movi_tl(cpu_ov, 0);
4952 if (unlikely(Rc(ctx->opcode) != 0))
4953 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4954 }
4955
4956 /* rlmi - rlmi. */
4957 static void gen_rlmi(DisasContext *ctx)
4958 {
4959 uint32_t mb = MB(ctx->opcode);
4960 uint32_t me = ME(ctx->opcode);
4961 TCGv t0 = tcg_temp_new();
4962 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4963 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4964 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4965 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4966 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4967 tcg_temp_free(t0);
4968 if (unlikely(Rc(ctx->opcode) != 0))
4969 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4970 }
4971
4972 /* rrib - rrib. */
4973 static void gen_rrib(DisasContext *ctx)
4974 {
4975 TCGv t0 = tcg_temp_new();
4976 TCGv t1 = tcg_temp_new();
4977 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4978 tcg_gen_movi_tl(t1, 0x80000000);
4979 tcg_gen_shr_tl(t1, t1, t0);
4980 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4981 tcg_gen_and_tl(t0, t0, t1);
4982 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4983 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4984 tcg_temp_free(t0);
4985 tcg_temp_free(t1);
4986 if (unlikely(Rc(ctx->opcode) != 0))
4987 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4988 }
4989
4990 /* sle - sle. */
4991 static void gen_sle(DisasContext *ctx)
4992 {
4993 TCGv t0 = tcg_temp_new();
4994 TCGv t1 = tcg_temp_new();
4995 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4996 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4997 tcg_gen_subfi_tl(t1, 32, t1);
4998 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4999 tcg_gen_or_tl(t1, t0, t1);
5000 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5001 gen_store_spr(SPR_MQ, t1);
5002 tcg_temp_free(t0);
5003 tcg_temp_free(t1);
5004 if (unlikely(Rc(ctx->opcode) != 0))
5005 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5006 }
5007
5008 /* sleq - sleq. */
5009 static void gen_sleq(DisasContext *ctx)
5010 {
5011 TCGv t0 = tcg_temp_new();
5012 TCGv t1 = tcg_temp_new();
5013 TCGv t2 = tcg_temp_new();
5014 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5015 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5016 tcg_gen_shl_tl(t2, t2, t0);
5017 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5018 gen_load_spr(t1, SPR_MQ);
5019 gen_store_spr(SPR_MQ, t0);
5020 tcg_gen_and_tl(t0, t0, t2);
5021 tcg_gen_andc_tl(t1, t1, t2);
5022 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5023 tcg_temp_free(t0);
5024 tcg_temp_free(t1);
5025 tcg_temp_free(t2);
5026 if (unlikely(Rc(ctx->opcode) != 0))
5027 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5028 }
5029
5030 /* sliq - sliq. */
5031 static void gen_sliq(DisasContext *ctx)
5032 {
5033 int sh = SH(ctx->opcode);
5034 TCGv t0 = tcg_temp_new();
5035 TCGv t1 = tcg_temp_new();
5036 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5037 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5038 tcg_gen_or_tl(t1, t0, t1);
5039 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5040 gen_store_spr(SPR_MQ, t1);
5041 tcg_temp_free(t0);
5042 tcg_temp_free(t1);
5043 if (unlikely(Rc(ctx->opcode) != 0))
5044 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5045 }
5046
5047 /* slliq - slliq. */
5048 static void gen_slliq(DisasContext *ctx)
5049 {
5050 int sh = SH(ctx->opcode);
5051 TCGv t0 = tcg_temp_new();
5052 TCGv t1 = tcg_temp_new();
5053 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5054 gen_load_spr(t1, SPR_MQ);
5055 gen_store_spr(SPR_MQ, t0);
5056 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5057 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5058 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5059 tcg_temp_free(t0);
5060 tcg_temp_free(t1);
5061 if (unlikely(Rc(ctx->opcode) != 0))
5062 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5063 }
5064
5065 /* sllq - sllq. */
5066 static void gen_sllq(DisasContext *ctx)
5067 {
5068 int l1 = gen_new_label();
5069 int l2 = gen_new_label();
5070 TCGv t0 = tcg_temp_local_new();
5071 TCGv t1 = tcg_temp_local_new();
5072 TCGv t2 = tcg_temp_local_new();
5073 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5074 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5075 tcg_gen_shl_tl(t1, t1, t2);
5076 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5077 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5078 gen_load_spr(t0, SPR_MQ);
5079 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5080 tcg_gen_br(l2);
5081 gen_set_label(l1);
5082 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5083 gen_load_spr(t2, SPR_MQ);
5084 tcg_gen_andc_tl(t1, t2, t1);
5085 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5086 gen_set_label(l2);
5087 tcg_temp_free(t0);
5088 tcg_temp_free(t1);
5089 tcg_temp_free(t2);
5090 if (unlikely(Rc(ctx->opcode) != 0))
5091 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5092 }
5093
5094 /* slq - slq. */
5095 static void gen_slq(DisasContext *ctx)
5096 {
5097 int l1 = gen_new_label();
5098 TCGv t0 = tcg_temp_new();
5099 TCGv t1 = tcg_temp_new();
5100 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5101 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5102 tcg_gen_subfi_tl(t1, 32, t1);
5103 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5104 tcg_gen_or_tl(t1, t0, t1);
5105 gen_store_spr(SPR_MQ, t1);
5106 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5107 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5108 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5109 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5110 gen_set_label(l1);
5111 tcg_temp_free(t0);
5112 tcg_temp_free(t1);
5113 if (unlikely(Rc(ctx->opcode) != 0))
5114 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5115 }
5116
5117 /* sraiq - sraiq. */
5118 static void gen_sraiq(DisasContext *ctx)
5119 {
5120 int sh = SH(ctx->opcode);
5121 int l1 = gen_new_label();
5122 TCGv t0 = tcg_temp_new();
5123 TCGv t1 = tcg_temp_new();
5124 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5125 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5126 tcg_gen_or_tl(t0, t0, t1);
5127 gen_store_spr(SPR_MQ, t0);
5128 tcg_gen_movi_tl(cpu_ca, 0);
5129 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5130 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5131 tcg_gen_movi_tl(cpu_ca, 1);
5132 gen_set_label(l1);
5133 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5134 tcg_temp_free(t0);
5135 tcg_temp_free(t1);
5136 if (unlikely(Rc(ctx->opcode) != 0))
5137 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5138 }
5139
5140 /* sraq - sraq. */
5141 static void gen_sraq(DisasContext *ctx)
5142 {
5143 int l1 = gen_new_label();
5144 int l2 = gen_new_label();
5145 TCGv t0 = tcg_temp_new();
5146 TCGv t1 = tcg_temp_local_new();
5147 TCGv t2 = tcg_temp_local_new();
5148 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5149 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5150 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5151 tcg_gen_subfi_tl(t2, 32, t2);
5152 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5153 tcg_gen_or_tl(t0, t0, t2);
5154 gen_store_spr(SPR_MQ, t0);
5155 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5156 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5157 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5158 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5159 gen_set_label(l1);
5160 tcg_temp_free(t0);
5161 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5162 tcg_gen_movi_tl(cpu_ca, 0);
5163 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5164 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5165 tcg_gen_movi_tl(cpu_ca, 1);
5166 gen_set_label(l2);
5167 tcg_temp_free(t1);
5168 tcg_temp_free(t2);
5169 if (unlikely(Rc(ctx->opcode) != 0))
5170 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5171 }
5172
5173 /* sre - sre. */
5174 static void gen_sre(DisasContext *ctx)
5175 {
5176 TCGv t0 = tcg_temp_new();
5177 TCGv t1 = tcg_temp_new();
5178 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5179 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5180 tcg_gen_subfi_tl(t1, 32, t1);
5181 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5182 tcg_gen_or_tl(t1, t0, t1);
5183 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5184 gen_store_spr(SPR_MQ, t1);
5185 tcg_temp_free(t0);
5186 tcg_temp_free(t1);
5187 if (unlikely(Rc(ctx->opcode) != 0))
5188 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5189 }
5190
5191 /* srea - srea. */
5192 static void gen_srea(DisasContext *ctx)
5193 {
5194 TCGv t0 = tcg_temp_new();
5195 TCGv t1 = tcg_temp_new();
5196 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5197 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5198 gen_store_spr(SPR_MQ, t0);
5199 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5200 tcg_temp_free(t0);
5201 tcg_temp_free(t1);
5202 if (unlikely(Rc(ctx->opcode) != 0))
5203 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5204 }
5205
5206 /* sreq */
5207 static void gen_sreq(DisasContext *ctx)
5208 {
5209 TCGv t0 = tcg_temp_new();
5210 TCGv t1 = tcg_temp_new();
5211 TCGv t2 = tcg_temp_new();
5212 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5213 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5214 tcg_gen_shr_tl(t1, t1, t0);
5215 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5216 gen_load_spr(t2, SPR_MQ);
5217 gen_store_spr(SPR_MQ, t0);
5218 tcg_gen_and_tl(t0, t0, t1);
5219 tcg_gen_andc_tl(t2, t2, t1);
5220 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5221 tcg_temp_free(t0);
5222 tcg_temp_free(t1);
5223 tcg_temp_free(t2);
5224 if (unlikely(Rc(ctx->opcode) != 0))
5225 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5226 }
5227
5228 /* sriq */
5229 static void gen_sriq(DisasContext *ctx)
5230 {
5231 int sh = SH(ctx->opcode);
5232 TCGv t0 = tcg_temp_new();
5233 TCGv t1 = tcg_temp_new();
5234 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5235 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5236 tcg_gen_or_tl(t1, t0, t1);
5237 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5238 gen_store_spr(SPR_MQ, t1);
5239 tcg_temp_free(t0);
5240 tcg_temp_free(t1);
5241 if (unlikely(Rc(ctx->opcode) != 0))
5242 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5243 }
5244
5245 /* srliq */
5246 static void gen_srliq(DisasContext *ctx)
5247 {
5248 int sh = SH(ctx->opcode);
5249 TCGv t0 = tcg_temp_new();
5250 TCGv t1 = tcg_temp_new();
5251 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5252 gen_load_spr(t1, SPR_MQ);
5253 gen_store_spr(SPR_MQ, t0);
5254 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5255 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5256 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5257 tcg_temp_free(t0);
5258 tcg_temp_free(t1);
5259 if (unlikely(Rc(ctx->opcode) != 0))
5260 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5261 }
5262
5263 /* srlq */
5264 static void gen_srlq(DisasContext *ctx)
5265 {
5266 int l1 = gen_new_label();
5267 int l2 = gen_new_label();
5268 TCGv t0 = tcg_temp_local_new();
5269 TCGv t1 = tcg_temp_local_new();
5270 TCGv t2 = tcg_temp_local_new();
5271 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5272 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5273 tcg_gen_shr_tl(t2, t1, t2);
5274 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5275 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5276 gen_load_spr(t0, SPR_MQ);
5277 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5278 tcg_gen_br(l2);
5279 gen_set_label(l1);
5280 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5281 tcg_gen_and_tl(t0, t0, t2);
5282 gen_load_spr(t1, SPR_MQ);
5283 tcg_gen_andc_tl(t1, t1, t2);
5284 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5285 gen_set_label(l2);
5286 tcg_temp_free(t0);
5287 tcg_temp_free(t1);
5288 tcg_temp_free(t2);
5289 if (unlikely(Rc(ctx->opcode) != 0))
5290 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5291 }
5292
5293 /* srq */
5294 static void gen_srq(DisasContext *ctx)
5295 {
5296 int l1 = gen_new_label();
5297 TCGv t0 = tcg_temp_new();
5298 TCGv t1 = tcg_temp_new();
5299 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5300 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5301 tcg_gen_subfi_tl(t1, 32, t1);
5302 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5303 tcg_gen_or_tl(t1, t0, t1);
5304 gen_store_spr(SPR_MQ, t1);
5305 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5306 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5307 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5308 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5309 gen_set_label(l1);
5310 tcg_temp_free(t0);
5311 tcg_temp_free(t1);
5312 if (unlikely(Rc(ctx->opcode) != 0))
5313 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5314 }
5315
5316 /* PowerPC 602 specific instructions */
5317
5318 /* dsa */
5319 static void gen_dsa(DisasContext *ctx)
5320 {
5321 /* XXX: TODO */
5322 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5323 }
5324
5325 /* esa */
5326 static void gen_esa(DisasContext *ctx)
5327 {
5328 /* XXX: TODO */
5329 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5330 }
5331
5332 /* mfrom */
5333 static void gen_mfrom(DisasContext *ctx)
5334 {
5335 #if defined(CONFIG_USER_ONLY)
5336 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5337 #else
5338 if (unlikely(!ctx->mem_idx)) {
5339 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5340 return;
5341 }
5342 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5343 #endif
5344 }
5345
5346 /* 602 - 603 - G2 TLB management */
5347
5348 /* tlbld */
5349 static void gen_tlbld_6xx(DisasContext *ctx)
5350 {
5351 #if defined(CONFIG_USER_ONLY)
5352 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5353 #else
5354 if (unlikely(!ctx->mem_idx)) {
5355 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5356 return;
5357 }
5358 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5359 #endif
5360 }
5361
5362 /* tlbli */
5363 static void gen_tlbli_6xx(DisasContext *ctx)
5364 {
5365 #if defined(CONFIG_USER_ONLY)
5366 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5367 #else
5368 if (unlikely(!ctx->mem_idx)) {
5369 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5370 return;
5371 }
5372 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5373 #endif
5374 }
5375
5376 /* 74xx TLB management */
5377
5378 /* tlbld */
5379 static void gen_tlbld_74xx(DisasContext *ctx)
5380 {
5381 #if defined(CONFIG_USER_ONLY)
5382 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5383 #else
5384 if (unlikely(!ctx->mem_idx)) {
5385 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5386 return;
5387 }
5388 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5389 #endif
5390 }
5391
5392 /* tlbli */
5393 static void gen_tlbli_74xx(DisasContext *ctx)
5394 {
5395 #if defined(CONFIG_USER_ONLY)
5396 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5397 #else
5398 if (unlikely(!ctx->mem_idx)) {
5399 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5400 return;
5401 }
5402 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5403 #endif
5404 }
5405
5406 /* POWER instructions not in PowerPC 601 */
5407
5408 /* clf */
5409 static void gen_clf(DisasContext *ctx)
5410 {
5411 /* Cache line flush: implemented as no-op */
5412 }
5413
5414 /* cli */
5415 static void gen_cli(DisasContext *ctx)
5416 {
5417 /* Cache line invalidate: privileged and treated as no-op */
5418 #if defined(CONFIG_USER_ONLY)
5419 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5420 #else
5421 if (unlikely(!ctx->mem_idx)) {
5422 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5423 return;
5424 }
5425 #endif
5426 }
5427
5428 /* dclst */
5429 static void gen_dclst(DisasContext *ctx)
5430 {
5431 /* Data cache line store: treated as no-op */
5432 }
5433
5434 static void gen_mfsri(DisasContext *ctx)
5435 {
5436 #if defined(CONFIG_USER_ONLY)
5437 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5438 #else
5439 int ra = rA(ctx->opcode);
5440 int rd = rD(ctx->opcode);
5441 TCGv t0;
5442 if (unlikely(!ctx->mem_idx)) {
5443 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5444 return;
5445 }
5446 t0 = tcg_temp_new();
5447 gen_addr_reg_index(ctx, t0);
5448 tcg_gen_shri_tl(t0, t0, 28);
5449 tcg_gen_andi_tl(t0, t0, 0xF);
5450 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5451 tcg_temp_free(t0);
5452 if (ra != 0 && ra != rd)
5453 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5454 #endif
5455 }
5456
5457 static void gen_rac(DisasContext *ctx)
5458 {
5459 #if defined(CONFIG_USER_ONLY)
5460 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5461 #else
5462 TCGv t0;
5463 if (unlikely(!ctx->mem_idx)) {
5464 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5465 return;
5466 }
5467 t0 = tcg_temp_new();
5468 gen_addr_reg_index(ctx, t0);
5469 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5470 tcg_temp_free(t0);
5471 #endif
5472 }
5473
5474 static void gen_rfsvc(DisasContext *ctx)
5475 {
5476 #if defined(CONFIG_USER_ONLY)
5477 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5478 #else
5479 if (unlikely(!ctx->mem_idx)) {
5480 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5481 return;
5482 }
5483 gen_helper_rfsvc(cpu_env);
5484 gen_sync_exception(ctx);
5485 #endif
5486 }
5487
5488 /* svc is not implemented for now */
5489
5490 /* POWER2 specific instructions */
5491 /* Quad manipulation (load/store two floats at a time) */
5492
5493 /* lfq */
5494 static void gen_lfq(DisasContext *ctx)
5495 {
5496 int rd = rD(ctx->opcode);
5497 TCGv t0;
5498 gen_set_access_type(ctx, ACCESS_FLOAT);
5499 t0 = tcg_temp_new();
5500 gen_addr_imm_index(ctx, t0, 0);
5501 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5502 gen_addr_add(ctx, t0, t0, 8);
5503 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5504 tcg_temp_free(t0);
5505 }
5506
5507 /* lfqu */
5508 static void gen_lfqu(DisasContext *ctx)
5509 {
5510 int ra = rA(ctx->opcode);
5511 int rd = rD(ctx->opcode);
5512 TCGv t0, t1;
5513 gen_set_access_type(ctx, ACCESS_FLOAT);
5514 t0 = tcg_temp_new();
5515 t1 = tcg_temp_new();
5516 gen_addr_imm_index(ctx, t0, 0);
5517 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5518 gen_addr_add(ctx, t1, t0, 8);
5519 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5520 if (ra != 0)
5521 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5522 tcg_temp_free(t0);
5523 tcg_temp_free(t1);
5524 }
5525
5526 /* lfqux */
5527 static void gen_lfqux(DisasContext *ctx)
5528 {
5529 int ra = rA(ctx->opcode);
5530 int rd = rD(ctx->opcode);
5531 gen_set_access_type(ctx, ACCESS_FLOAT);
5532 TCGv t0, t1;
5533 t0 = tcg_temp_new();
5534 gen_addr_reg_index(ctx, t0);
5535 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5536 t1 = tcg_temp_new();
5537 gen_addr_add(ctx, t1, t0, 8);
5538 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5539 tcg_temp_free(t1);
5540 if (ra != 0)
5541 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5542 tcg_temp_free(t0);
5543 }
5544
5545 /* lfqx */
5546 static void gen_lfqx(DisasContext *ctx)
5547 {
5548 int rd = rD(ctx->opcode);
5549 TCGv t0;
5550 gen_set_access_type(ctx, ACCESS_FLOAT);
5551 t0 = tcg_temp_new();
5552 gen_addr_reg_index(ctx, t0);
5553 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5554 gen_addr_add(ctx, t0, t0, 8);
5555 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5556 tcg_temp_free(t0);
5557 }
5558
5559 /* stfq */
5560 static void gen_stfq(DisasContext *ctx)
5561 {
5562 int rd = rD(ctx->opcode);
5563 TCGv t0;
5564 gen_set_access_type(ctx, ACCESS_FLOAT);
5565 t0 = tcg_temp_new();
5566 gen_addr_imm_index(ctx, t0, 0);
5567 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5568 gen_addr_add(ctx, t0, t0, 8);
5569 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5570 tcg_temp_free(t0);
5571 }
5572
5573 /* stfqu */
5574 static void gen_stfqu(DisasContext *ctx)
5575 {
5576 int ra = rA(ctx->opcode);
5577 int rd = rD(ctx->opcode);
5578 TCGv t0, t1;
5579 gen_set_access_type(ctx, ACCESS_FLOAT);
5580 t0 = tcg_temp_new();
5581 gen_addr_imm_index(ctx, t0, 0);
5582 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5583 t1 = tcg_temp_new();
5584 gen_addr_add(ctx, t1, t0, 8);
5585 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5586 tcg_temp_free(t1);
5587 if (ra != 0)
5588 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5589 tcg_temp_free(t0);
5590 }
5591
5592 /* stfqux */
5593 static void gen_stfqux(DisasContext *ctx)
5594 {
5595 int ra = rA(ctx->opcode);
5596 int rd = rD(ctx->opcode);
5597 TCGv t0, t1;
5598 gen_set_access_type(ctx, ACCESS_FLOAT);
5599 t0 = tcg_temp_new();
5600 gen_addr_reg_index(ctx, t0);
5601 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5602 t1 = tcg_temp_new();
5603 gen_addr_add(ctx, t1, t0, 8);
5604 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5605 tcg_temp_free(t1);
5606 if (ra != 0)
5607 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5608 tcg_temp_free(t0);
5609 }
5610
5611 /* stfqx */
5612 static void gen_stfqx(DisasContext *ctx)
5613 {
5614 int rd = rD(ctx->opcode);
5615 TCGv t0;
5616 gen_set_access_type(ctx, ACCESS_FLOAT);
5617 t0 = tcg_temp_new();
5618 gen_addr_reg_index(ctx, t0);
5619 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5620 gen_addr_add(ctx, t0, t0, 8);
5621 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5622 tcg_temp_free(t0);
5623 }
5624
5625 /* BookE specific instructions */
5626
5627 /* XXX: not implemented on 440 ? */
5628 static void gen_mfapidi(DisasContext *ctx)
5629 {
5630 /* XXX: TODO */
5631 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5632 }
5633
5634 /* XXX: not implemented on 440 ? */
5635 static void gen_tlbiva(DisasContext *ctx)
5636 {
5637 #if defined(CONFIG_USER_ONLY)
5638 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5639 #else
5640 TCGv t0;
5641 if (unlikely(!ctx->mem_idx)) {
5642 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5643 return;
5644 }
5645 t0 = tcg_temp_new();
5646 gen_addr_reg_index(ctx, t0);
5647 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5648 tcg_temp_free(t0);
5649 #endif
5650 }
5651
5652 /* All 405 MAC instructions are translated here */
5653 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5654 int ra, int rb, int rt, int Rc)
5655 {
5656 TCGv t0, t1;
5657
5658 t0 = tcg_temp_local_new();
5659 t1 = tcg_temp_local_new();
5660
5661 switch (opc3 & 0x0D) {
5662 case 0x05:
5663 /* macchw - macchw. - macchwo - macchwo. */
5664 /* macchws - macchws. - macchwso - macchwso. */
5665 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5666 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5667 /* mulchw - mulchw. */
5668 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5669 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5670 tcg_gen_ext16s_tl(t1, t1);
5671 break;
5672 case 0x04:
5673 /* macchwu - macchwu. - macchwuo - macchwuo. */
5674 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5675 /* mulchwu - mulchwu. */
5676 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5677 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5678 tcg_gen_ext16u_tl(t1, t1);
5679 break;
5680 case 0x01:
5681 /* machhw - machhw. - machhwo - machhwo. */
5682 /* machhws - machhws. - machhwso - machhwso. */
5683 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5684 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5685 /* mulhhw - mulhhw. */
5686 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5687 tcg_gen_ext16s_tl(t0, t0);
5688 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5689 tcg_gen_ext16s_tl(t1, t1);
5690 break;
5691 case 0x00:
5692 /* machhwu - machhwu. - machhwuo - machhwuo. */
5693 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5694 /* mulhhwu - mulhhwu. */
5695 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5696 tcg_gen_ext16u_tl(t0, t0);
5697 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5698 tcg_gen_ext16u_tl(t1, t1);
5699 break;
5700 case 0x0D:
5701 /* maclhw - maclhw. - maclhwo - maclhwo. */
5702 /* maclhws - maclhws. - maclhwso - maclhwso. */
5703 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5704 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5705 /* mullhw - mullhw. */
5706 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5707 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5708 break;
5709 case 0x0C:
5710 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5711 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5712 /* mullhwu - mullhwu. */
5713 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5714 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5715 break;
5716 }
5717 if (opc2 & 0x04) {
5718 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5719 tcg_gen_mul_tl(t1, t0, t1);
5720 if (opc2 & 0x02) {
5721 /* nmultiply-and-accumulate (0x0E) */
5722 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5723 } else {
5724 /* multiply-and-accumulate (0x0C) */
5725 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5726 }
5727
5728 if (opc3 & 0x12) {
5729 /* Check overflow and/or saturate */
5730 int l1 = gen_new_label();
5731
5732 if (opc3 & 0x10) {
5733 /* Start with XER OV disabled, the most likely case */
5734 tcg_gen_movi_tl(cpu_ov, 0);
5735 }
5736 if (opc3 & 0x01) {
5737 /* Signed */
5738 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5739 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5740 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5741 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5742 if (opc3 & 0x02) {
5743 /* Saturate */
5744 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5745 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5746 }
5747 } else {
5748 /* Unsigned */
5749 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5750 if (opc3 & 0x02) {
5751 /* Saturate */
5752 tcg_gen_movi_tl(t0, UINT32_MAX);
5753 }
5754 }
5755 if (opc3 & 0x10) {
5756 /* Check overflow */
5757 tcg_gen_movi_tl(cpu_ov, 1);
5758 tcg_gen_movi_tl(cpu_so, 1);
5759 }
5760 gen_set_label(l1);
5761 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5762 }
5763 } else {
5764 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5765 }
5766 tcg_temp_free(t0);
5767 tcg_temp_free(t1);
5768 if (unlikely(Rc) != 0) {
5769 /* Update Rc0 */
5770 gen_set_Rc0(ctx, cpu_gpr[rt]);
5771 }
5772 }
5773
5774 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5775 static void glue(gen_, name)(DisasContext *ctx) \
5776 { \
5777 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5778 rD(ctx->opcode), Rc(ctx->opcode)); \
5779 }
5780
5781 /* macchw - macchw. */
5782 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5783 /* macchwo - macchwo. */
5784 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5785 /* macchws - macchws. */
5786 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5787 /* macchwso - macchwso. */
5788 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5789 /* macchwsu - macchwsu. */
5790 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5791 /* macchwsuo - macchwsuo. */
5792 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5793 /* macchwu - macchwu. */
5794 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5795 /* macchwuo - macchwuo. */
5796 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5797 /* machhw - machhw. */
5798 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5799 /* machhwo - machhwo. */
5800 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5801 /* machhws - machhws. */
5802 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5803 /* machhwso - machhwso. */
5804 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5805 /* machhwsu - machhwsu. */
5806 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5807 /* machhwsuo - machhwsuo. */
5808 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5809 /* machhwu - machhwu. */
5810 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5811 /* machhwuo - machhwuo. */
5812 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5813 /* maclhw - maclhw. */
5814 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5815 /* maclhwo - maclhwo. */
5816 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5817 /* maclhws - maclhws. */
5818 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5819 /* maclhwso - maclhwso. */
5820 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5821 /* maclhwu - maclhwu. */
5822 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5823 /* maclhwuo - maclhwuo. */
5824 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5825 /* maclhwsu - maclhwsu. */
5826 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5827 /* maclhwsuo - maclhwsuo. */
5828 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5829 /* nmacchw - nmacchw. */
5830 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5831 /* nmacchwo - nmacchwo. */
5832 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5833 /* nmacchws - nmacchws. */
5834 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5835 /* nmacchwso - nmacchwso. */
5836 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5837 /* nmachhw - nmachhw. */
5838 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5839 /* nmachhwo - nmachhwo. */
5840 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5841 /* nmachhws - nmachhws. */
5842 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5843 /* nmachhwso - nmachhwso. */
5844 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5845 /* nmaclhw - nmaclhw. */
5846 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5847 /* nmaclhwo - nmaclhwo. */
5848 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5849 /* nmaclhws - nmaclhws. */
5850 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5851 /* nmaclhwso - nmaclhwso. */
5852 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5853
5854 /* mulchw - mulchw. */
5855 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5856 /* mulchwu - mulchwu. */
5857 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5858 /* mulhhw - mulhhw. */
5859 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5860 /* mulhhwu - mulhhwu. */
5861 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5862 /* mullhw - mullhw. */
5863 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5864 /* mullhwu - mullhwu. */
5865 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5866
5867 /* mfdcr */
5868 static void gen_mfdcr(DisasContext *ctx)
5869 {
5870 #if defined(CONFIG_USER_ONLY)
5871 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5872 #else
5873 TCGv dcrn;
5874 if (unlikely(!ctx->mem_idx)) {
5875 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5876 return;
5877 }
5878 /* NIP cannot be restored if the memory exception comes from an helper */
5879 gen_update_nip(ctx, ctx->nip - 4);
5880 dcrn = tcg_const_tl(SPR(ctx->opcode));
5881 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5882 tcg_temp_free(dcrn);
5883 #endif
5884 }
5885
5886 /* mtdcr */
5887 static void gen_mtdcr(DisasContext *ctx)
5888 {
5889 #if defined(CONFIG_USER_ONLY)
5890 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5891 #else
5892 TCGv dcrn;
5893 if (unlikely(!ctx->mem_idx)) {
5894 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5895 return;
5896 }
5897 /* NIP cannot be restored if the memory exception comes from an helper */
5898 gen_update_nip(ctx, ctx->nip - 4);
5899 dcrn = tcg_const_tl(SPR(ctx->opcode));
5900 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5901 tcg_temp_free(dcrn);
5902 #endif
5903 }
5904
5905 /* mfdcrx */
5906 /* XXX: not implemented on 440 ? */
5907 static void gen_mfdcrx(DisasContext *ctx)
5908 {
5909 #if defined(CONFIG_USER_ONLY)
5910 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5911 #else
5912 if (unlikely(!ctx->mem_idx)) {
5913 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5914 return;
5915 }
5916 /* NIP cannot be restored if the memory exception comes from an helper */
5917 gen_update_nip(ctx, ctx->nip - 4);
5918 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5919 cpu_gpr[rA(ctx->opcode)]);
5920 /* Note: Rc update flag set leads to undefined state of Rc0 */
5921 #endif
5922 }
5923
5924 /* mtdcrx */
5925 /* XXX: not implemented on 440 ? */
5926 static void gen_mtdcrx(DisasContext *ctx)
5927 {
5928 #if defined(CONFIG_USER_ONLY)
5929 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5930 #else
5931 if (unlikely(!ctx->mem_idx)) {
5932 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5933 return;
5934 }
5935 /* NIP cannot be restored if the memory exception comes from an helper */
5936 gen_update_nip(ctx, ctx->nip - 4);
5937 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5938 cpu_gpr[rS(ctx->opcode)]);
5939 /* Note: Rc update flag set leads to undefined state of Rc0 */
5940 #endif
5941 }
5942
5943 /* mfdcrux (PPC 460) : user-mode access to DCR */
5944 static void gen_mfdcrux(DisasContext *ctx)
5945 {
5946 /* NIP cannot be restored if the memory exception comes from an helper */
5947 gen_update_nip(ctx, ctx->nip - 4);
5948 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5949 cpu_gpr[rA(ctx->opcode)]);
5950 /* Note: Rc update flag set leads to undefined state of Rc0 */
5951 }
5952
5953 /* mtdcrux (PPC 460) : user-mode access to DCR */
5954 static void gen_mtdcrux(DisasContext *ctx)
5955 {
5956 /* NIP cannot be restored if the memory exception comes from an helper */
5957 gen_update_nip(ctx, ctx->nip - 4);
5958 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5959 cpu_gpr[rS(ctx->opcode)]);
5960 /* Note: Rc update flag set leads to undefined state of Rc0 */
5961 }
5962
5963 /* dccci */
5964 static void gen_dccci(DisasContext *ctx)
5965 {
5966 #if defined(CONFIG_USER_ONLY)
5967 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5968 #else
5969 if (unlikely(!ctx->mem_idx)) {
5970 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5971 return;
5972 }
5973 /* interpreted as no-op */
5974 #endif
5975 }
5976
5977 /* dcread */
5978 static void gen_dcread(DisasContext *ctx)
5979 {
5980 #if defined(CONFIG_USER_ONLY)
5981 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5982 #else
5983 TCGv EA, val;
5984 if (unlikely(!ctx->mem_idx)) {
5985 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5986 return;
5987 }
5988 gen_set_access_type(ctx, ACCESS_CACHE);
5989 EA = tcg_temp_new();
5990 gen_addr_reg_index(ctx, EA);
5991 val = tcg_temp_new();
5992 gen_qemu_ld32u(ctx, val, EA);
5993 tcg_temp_free(val);
5994 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5995 tcg_temp_free(EA);
5996 #endif
5997 }
5998
5999 /* icbt */
6000 static void gen_icbt_40x(DisasContext *ctx)
6001 {
6002 /* interpreted as no-op */
6003 /* XXX: specification say this is treated as a load by the MMU
6004 * but does not generate any exception
6005 */
6006 }
6007
6008 /* iccci */
6009 static void gen_iccci(DisasContext *ctx)
6010 {
6011 #if defined(CONFIG_USER_ONLY)
6012 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6013 #else
6014 if (unlikely(!ctx->mem_idx)) {
6015 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6016 return;
6017 }
6018 /* interpreted as no-op */
6019 #endif
6020 }
6021
6022 /* icread */
6023 static void gen_icread(DisasContext *ctx)
6024 {
6025 #if defined(CONFIG_USER_ONLY)
6026 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6027 #else
6028 if (unlikely(!ctx->mem_idx)) {
6029 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6030 return;
6031 }
6032 /* interpreted as no-op */
6033 #endif
6034 }
6035
6036 /* rfci (mem_idx only) */
6037 static void gen_rfci_40x(DisasContext *ctx)
6038 {
6039 #if defined(CONFIG_USER_ONLY)
6040 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6041 #else
6042 if (unlikely(!ctx->mem_idx)) {
6043 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6044 return;
6045 }
6046 /* Restore CPU state */
6047 gen_helper_40x_rfci(cpu_env);
6048 gen_sync_exception(ctx);
6049 #endif
6050 }
6051
6052 static void gen_rfci(DisasContext *ctx)
6053 {
6054 #if defined(CONFIG_USER_ONLY)
6055 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6056 #else
6057 if (unlikely(!ctx->mem_idx)) {
6058 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6059 return;
6060 }
6061 /* Restore CPU state */
6062 gen_helper_rfci(cpu_env);
6063 gen_sync_exception(ctx);
6064 #endif
6065 }
6066
6067 /* BookE specific */
6068
6069 /* XXX: not implemented on 440 ? */
6070 static void gen_rfdi(DisasContext *ctx)
6071 {
6072 #if defined(CONFIG_USER_ONLY)
6073 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6074 #else
6075 if (unlikely(!ctx->mem_idx)) {
6076 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6077 return;
6078 }
6079 /* Restore CPU state */
6080 gen_helper_rfdi(cpu_env);
6081 gen_sync_exception(ctx);
6082 #endif
6083 }
6084
6085 /* XXX: not implemented on 440 ? */
6086 static void gen_rfmci(DisasContext *ctx)
6087 {
6088 #if defined(CONFIG_USER_ONLY)
6089 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6090 #else
6091 if (unlikely(!ctx->mem_idx)) {
6092 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6093 return;
6094 }
6095 /* Restore CPU state */
6096 gen_helper_rfmci(cpu_env);
6097 gen_sync_exception(ctx);
6098 #endif
6099 }
6100
6101 /* TLB management - PowerPC 405 implementation */
6102
6103 /* tlbre */
6104 static void gen_tlbre_40x(DisasContext *ctx)
6105 {
6106 #if defined(CONFIG_USER_ONLY)
6107 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6108 #else
6109 if (unlikely(!ctx->mem_idx)) {
6110 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6111 return;
6112 }
6113 switch (rB(ctx->opcode)) {
6114 case 0:
6115 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6116 cpu_gpr[rA(ctx->opcode)]);
6117 break;
6118 case 1:
6119 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6120 cpu_gpr[rA(ctx->opcode)]);
6121 break;
6122 default:
6123 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6124 break;
6125 }
6126 #endif
6127 }
6128
6129 /* tlbsx - tlbsx. */
6130 static void gen_tlbsx_40x(DisasContext *ctx)
6131 {
6132 #if defined(CONFIG_USER_ONLY)
6133 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6134 #else
6135 TCGv t0;
6136 if (unlikely(!ctx->mem_idx)) {
6137 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6138 return;
6139 }
6140 t0 = tcg_temp_new();
6141 gen_addr_reg_index(ctx, t0);
6142 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6143 tcg_temp_free(t0);
6144 if (Rc(ctx->opcode)) {
6145 int l1 = gen_new_label();
6146 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6147 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6148 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6149 gen_set_label(l1);
6150 }
6151 #endif
6152 }
6153
6154 /* tlbwe */
6155 static void gen_tlbwe_40x(DisasContext *ctx)
6156 {
6157 #if defined(CONFIG_USER_ONLY)
6158 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6159 #else
6160 if (unlikely(!ctx->mem_idx)) {
6161 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6162 return;
6163 }
6164 switch (rB(ctx->opcode)) {
6165 case 0:
6166 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6167 cpu_gpr[rS(ctx->opcode)]);
6168 break;
6169 case 1:
6170 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6171 cpu_gpr[rS(ctx->opcode)]);
6172 break;
6173 default:
6174 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6175 break;
6176 }
6177 #endif
6178 }
6179
6180 /* TLB management - PowerPC 440 implementation */
6181
6182 /* tlbre */
6183 static void gen_tlbre_440(DisasContext *ctx)
6184 {
6185 #if defined(CONFIG_USER_ONLY)
6186 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6187 #else
6188 if (unlikely(!ctx->mem_idx)) {
6189 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6190 return;
6191 }
6192 switch (rB(ctx->opcode)) {
6193 case 0:
6194 case 1:
6195 case 2:
6196 {
6197 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6198 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6199 t0, cpu_gpr[rA(ctx->opcode)]);
6200 tcg_temp_free_i32(t0);
6201 }
6202 break;
6203 default:
6204 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6205 break;
6206 }
6207 #endif
6208 }
6209
6210 /* tlbsx - tlbsx. */
6211 static void gen_tlbsx_440(DisasContext *ctx)
6212 {
6213 #if defined(CONFIG_USER_ONLY)
6214 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6215 #else
6216 TCGv t0;
6217 if (unlikely(!ctx->mem_idx)) {
6218 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6219 return;
6220 }
6221 t0 = tcg_temp_new();
6222 gen_addr_reg_index(ctx, t0);
6223 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6224 tcg_temp_free(t0);
6225 if (Rc(ctx->opcode)) {
6226 int l1 = gen_new_label();
6227 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6228 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6229 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6230 gen_set_label(l1);
6231 }
6232 #endif
6233 }
6234
6235 /* tlbwe */
6236 static void gen_tlbwe_440(DisasContext *ctx)
6237 {
6238 #if defined(CONFIG_USER_ONLY)
6239 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6240 #else
6241 if (unlikely(!ctx->mem_idx)) {
6242 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6243 return;
6244 }
6245 switch (rB(ctx->opcode)) {
6246 case 0:
6247 case 1:
6248 case 2:
6249 {
6250 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6251 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6252 cpu_gpr[rS(ctx->opcode)]);
6253 tcg_temp_free_i32(t0);
6254 }
6255 break;
6256 default:
6257 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6258 break;
6259 }
6260 #endif
6261 }
6262
6263 /* TLB management - PowerPC BookE 2.06 implementation */
6264
6265 /* tlbre */
6266 static void gen_tlbre_booke206(DisasContext *ctx)
6267 {
6268 #if defined(CONFIG_USER_ONLY)
6269 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6270 #else
6271 if (unlikely(!ctx->mem_idx)) {
6272 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6273 return;
6274 }
6275
6276 gen_helper_booke206_tlbre(cpu_env);
6277 #endif
6278 }
6279
6280 /* tlbsx - tlbsx. */
6281 static void gen_tlbsx_booke206(DisasContext *ctx)
6282 {
6283 #if defined(CONFIG_USER_ONLY)
6284 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6285 #else
6286 TCGv t0;
6287 if (unlikely(!ctx->mem_idx)) {
6288 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6289 return;
6290 }
6291
6292 if (rA(ctx->opcode)) {
6293 t0 = tcg_temp_new();
6294 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6295 } else {
6296 t0 = tcg_const_tl(0);
6297 }
6298
6299 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6300 gen_helper_booke206_tlbsx(cpu_env, t0);
6301 #endif
6302 }
6303
6304 /* tlbwe */
6305 static void gen_tlbwe_booke206(DisasContext *ctx)
6306 {
6307 #if defined(CONFIG_USER_ONLY)
6308 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6309 #else
6310 if (unlikely(!ctx->mem_idx)) {
6311 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6312 return;
6313 }
6314 gen_update_nip(ctx, ctx->nip - 4);
6315 gen_helper_booke206_tlbwe(cpu_env);
6316 #endif
6317 }
6318
6319 static void gen_tlbivax_booke206(DisasContext *ctx)
6320 {
6321 #if defined(CONFIG_USER_ONLY)
6322 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6323 #else
6324 TCGv t0;
6325 if (unlikely(!ctx->mem_idx)) {
6326 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6327 return;
6328 }
6329
6330 t0 = tcg_temp_new();
6331 gen_addr_reg_index(ctx, t0);
6332
6333 gen_helper_booke206_tlbivax(cpu_env, t0);
6334 #endif
6335 }
6336
6337 static void gen_tlbilx_booke206(DisasContext *ctx)
6338 {
6339 #if defined(CONFIG_USER_ONLY)
6340 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6341 #else
6342 TCGv t0;
6343 if (unlikely(!ctx->mem_idx)) {
6344 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6345 return;
6346 }
6347
6348 t0 = tcg_temp_new();
6349 gen_addr_reg_index(ctx, t0);
6350
6351 switch((ctx->opcode >> 21) & 0x3) {
6352 case 0:
6353 gen_helper_booke206_tlbilx0(cpu_env, t0);
6354 break;
6355 case 1:
6356 gen_helper_booke206_tlbilx1(cpu_env, t0);
6357 break;
6358 case 3:
6359 gen_helper_booke206_tlbilx3(cpu_env, t0);
6360 break;
6361 default:
6362 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6363 break;
6364 }
6365
6366 tcg_temp_free(t0);
6367 #endif
6368 }
6369
6370
6371 /* wrtee */
6372 static void gen_wrtee(DisasContext *ctx)
6373 {
6374 #if defined(CONFIG_USER_ONLY)
6375 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6376 #else
6377 TCGv t0;
6378 if (unlikely(!ctx->mem_idx)) {
6379 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6380 return;
6381 }
6382 t0 = tcg_temp_new();
6383 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6384 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6385 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6386 tcg_temp_free(t0);
6387 /* Stop translation to have a chance to raise an exception
6388 * if we just set msr_ee to 1
6389 */
6390 gen_stop_exception(ctx);
6391 #endif
6392 }
6393
6394 /* wrteei */
6395 static void gen_wrteei(DisasContext *ctx)
6396 {
6397 #if defined(CONFIG_USER_ONLY)
6398 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6399 #else
6400 if (unlikely(!ctx->mem_idx)) {
6401 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6402 return;
6403 }
6404 if (ctx->opcode & 0x00008000) {
6405 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6406 /* Stop translation to have a chance to raise an exception */
6407 gen_stop_exception(ctx);
6408 } else {
6409 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6410 }
6411 #endif
6412 }
6413
6414 /* PowerPC 440 specific instructions */
6415
6416 /* dlmzb */
6417 static void gen_dlmzb(DisasContext *ctx)
6418 {
6419 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6420 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6421 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6422 tcg_temp_free_i32(t0);
6423 }
6424
6425 /* mbar replaces eieio on 440 */
6426 static void gen_mbar(DisasContext *ctx)
6427 {
6428 /* interpreted as no-op */
6429 }
6430
6431 /* msync replaces sync on 440 */
6432 static void gen_msync_4xx(DisasContext *ctx)
6433 {
6434 /* interpreted as no-op */
6435 }
6436
6437 /* icbt */
6438 static void gen_icbt_440(DisasContext *ctx)
6439 {
6440 /* interpreted as no-op */
6441 /* XXX: specification say this is treated as a load by the MMU
6442 * but does not generate any exception
6443 */
6444 }
6445
6446 /* Embedded.Processor Control */
6447
6448 static void gen_msgclr(DisasContext *ctx)
6449 {
6450 #if defined(CONFIG_USER_ONLY)
6451 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6452 #else
6453 if (unlikely(ctx->mem_idx == 0)) {
6454 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6455 return;
6456 }
6457
6458 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6459 #endif
6460 }
6461
6462 static void gen_msgsnd(DisasContext *ctx)
6463 {
6464 #if defined(CONFIG_USER_ONLY)
6465 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6466 #else
6467 if (unlikely(ctx->mem_idx == 0)) {
6468 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6469 return;
6470 }
6471
6472 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6473 #endif
6474 }
6475
6476 /*** Altivec vector extension ***/
6477 /* Altivec registers moves */
6478
6479 static inline TCGv_ptr gen_avr_ptr(int reg)
6480 {
6481 TCGv_ptr r = tcg_temp_new_ptr();
6482 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6483 return r;
6484 }
6485
6486 #define GEN_VR_LDX(name, opc2, opc3) \
6487 static void glue(gen_, name)(DisasContext *ctx) \
6488 { \
6489 TCGv EA; \
6490 if (unlikely(!ctx->altivec_enabled)) { \
6491 gen_exception(ctx, POWERPC_EXCP_VPU); \
6492 return; \
6493 } \
6494 gen_set_access_type(ctx, ACCESS_INT); \
6495 EA = tcg_temp_new(); \
6496 gen_addr_reg_index(ctx, EA); \
6497 tcg_gen_andi_tl(EA, EA, ~0xf); \
6498 if (ctx->le_mode) { \
6499 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6500 tcg_gen_addi_tl(EA, EA, 8); \
6501 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6502 } else { \
6503 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6504 tcg_gen_addi_tl(EA, EA, 8); \
6505 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6506 } \
6507 tcg_temp_free(EA); \
6508 }
6509
6510 #define GEN_VR_STX(name, opc2, opc3) \
6511 static void gen_st##name(DisasContext *ctx) \
6512 { \
6513 TCGv EA; \
6514 if (unlikely(!ctx->altivec_enabled)) { \
6515 gen_exception(ctx, POWERPC_EXCP_VPU); \
6516 return; \
6517 } \
6518 gen_set_access_type(ctx, ACCESS_INT); \
6519 EA = tcg_temp_new(); \
6520 gen_addr_reg_index(ctx, EA); \
6521 tcg_gen_andi_tl(EA, EA, ~0xf); \
6522 if (ctx->le_mode) { \
6523 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6524 tcg_gen_addi_tl(EA, EA, 8); \
6525 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6526 } else { \
6527 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6528 tcg_gen_addi_tl(EA, EA, 8); \
6529 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6530 } \
6531 tcg_temp_free(EA); \
6532 }
6533
6534 #define GEN_VR_LVE(name, opc2, opc3) \
6535 static void gen_lve##name(DisasContext *ctx) \
6536 { \
6537 TCGv EA; \
6538 TCGv_ptr rs; \
6539 if (unlikely(!ctx->altivec_enabled)) { \
6540 gen_exception(ctx, POWERPC_EXCP_VPU); \
6541 return; \
6542 } \
6543 gen_set_access_type(ctx, ACCESS_INT); \
6544 EA = tcg_temp_new(); \
6545 gen_addr_reg_index(ctx, EA); \
6546 rs = gen_avr_ptr(rS(ctx->opcode)); \
6547 gen_helper_lve##name(cpu_env, rs, EA); \
6548 tcg_temp_free(EA); \
6549 tcg_temp_free_ptr(rs); \
6550 }
6551
6552 #define GEN_VR_STVE(name, opc2, opc3) \
6553 static void gen_stve##name(DisasContext *ctx) \
6554 { \
6555 TCGv EA; \
6556 TCGv_ptr rs; \
6557 if (unlikely(!ctx->altivec_enabled)) { \
6558 gen_exception(ctx, POWERPC_EXCP_VPU); \
6559 return; \
6560 } \
6561 gen_set_access_type(ctx, ACCESS_INT); \
6562 EA = tcg_temp_new(); \
6563 gen_addr_reg_index(ctx, EA); \
6564 rs = gen_avr_ptr(rS(ctx->opcode)); \
6565 gen_helper_stve##name(cpu_env, rs, EA); \
6566 tcg_temp_free(EA); \
6567 tcg_temp_free_ptr(rs); \
6568 }
6569
6570 GEN_VR_LDX(lvx, 0x07, 0x03);
6571 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6572 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6573
6574 GEN_VR_LVE(bx, 0x07, 0x00);
6575 GEN_VR_LVE(hx, 0x07, 0x01);
6576 GEN_VR_LVE(wx, 0x07, 0x02);
6577
6578 GEN_VR_STX(svx, 0x07, 0x07);
6579 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6580 GEN_VR_STX(svxl, 0x07, 0x0F);
6581
6582 GEN_VR_STVE(bx, 0x07, 0x04);
6583 GEN_VR_STVE(hx, 0x07, 0x05);
6584 GEN_VR_STVE(wx, 0x07, 0x06);
6585
6586 static void gen_lvsl(DisasContext *ctx)
6587 {
6588 TCGv_ptr rd;
6589 TCGv EA;
6590 if (unlikely(!ctx->altivec_enabled)) {
6591 gen_exception(ctx, POWERPC_EXCP_VPU);
6592 return;
6593 }
6594 EA = tcg_temp_new();
6595 gen_addr_reg_index(ctx, EA);
6596 rd = gen_avr_ptr(rD(ctx->opcode));
6597 gen_helper_lvsl(rd, EA);
6598 tcg_temp_free(EA);
6599 tcg_temp_free_ptr(rd);
6600 }
6601
6602 static void gen_lvsr(DisasContext *ctx)
6603 {
6604 TCGv_ptr rd;
6605 TCGv EA;
6606 if (unlikely(!ctx->altivec_enabled)) {
6607 gen_exception(ctx, POWERPC_EXCP_VPU);
6608 return;
6609 }
6610 EA = tcg_temp_new();
6611 gen_addr_reg_index(ctx, EA);
6612 rd = gen_avr_ptr(rD(ctx->opcode));
6613 gen_helper_lvsr(rd, EA);
6614 tcg_temp_free(EA);
6615 tcg_temp_free_ptr(rd);
6616 }
6617
6618 static void gen_mfvscr(DisasContext *ctx)
6619 {
6620 TCGv_i32 t;
6621 if (unlikely(!ctx->altivec_enabled)) {
6622 gen_exception(ctx, POWERPC_EXCP_VPU);
6623 return;
6624 }
6625 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6626 t = tcg_temp_new_i32();
6627 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6628 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6629 tcg_temp_free_i32(t);
6630 }
6631
6632 static void gen_mtvscr(DisasContext *ctx)
6633 {
6634 TCGv_ptr p;
6635 if (unlikely(!ctx->altivec_enabled)) {
6636 gen_exception(ctx, POWERPC_EXCP_VPU);
6637 return;
6638 }
6639 p = gen_avr_ptr(rD(ctx->opcode));
6640 gen_helper_mtvscr(cpu_env, p);
6641 tcg_temp_free_ptr(p);
6642 }
6643
6644 /* Logical operations */
6645 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6646 static void glue(gen_, name)(DisasContext *ctx) \
6647 { \
6648 if (unlikely(!ctx->altivec_enabled)) { \
6649 gen_exception(ctx, POWERPC_EXCP_VPU); \
6650 return; \
6651 } \
6652 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6653 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6654 }
6655
6656 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6657 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6658 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6659 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6660 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6661
6662 #define GEN_VXFORM(name, opc2, opc3) \
6663 static void glue(gen_, name)(DisasContext *ctx) \
6664 { \
6665 TCGv_ptr ra, rb, rd; \
6666 if (unlikely(!ctx->altivec_enabled)) { \
6667 gen_exception(ctx, POWERPC_EXCP_VPU); \
6668 return; \
6669 } \
6670 ra = gen_avr_ptr(rA(ctx->opcode)); \
6671 rb = gen_avr_ptr(rB(ctx->opcode)); \
6672 rd = gen_avr_ptr(rD(ctx->opcode)); \
6673 gen_helper_##name (rd, ra, rb); \
6674 tcg_temp_free_ptr(ra); \
6675 tcg_temp_free_ptr(rb); \
6676 tcg_temp_free_ptr(rd); \
6677 }
6678
6679 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6680 static void glue(gen_, name)(DisasContext *ctx) \
6681 { \
6682 TCGv_ptr ra, rb, rd; \
6683 if (unlikely(!ctx->altivec_enabled)) { \
6684 gen_exception(ctx, POWERPC_EXCP_VPU); \
6685 return; \
6686 } \
6687 ra = gen_avr_ptr(rA(ctx->opcode)); \
6688 rb = gen_avr_ptr(rB(ctx->opcode)); \
6689 rd = gen_avr_ptr(rD(ctx->opcode)); \
6690 gen_helper_##name(cpu_env, rd, ra, rb); \
6691 tcg_temp_free_ptr(ra); \
6692 tcg_temp_free_ptr(rb); \
6693 tcg_temp_free_ptr(rd); \
6694 }
6695
6696 GEN_VXFORM(vaddubm, 0, 0);
6697 GEN_VXFORM(vadduhm, 0, 1);
6698 GEN_VXFORM(vadduwm, 0, 2);
6699 GEN_VXFORM(vsububm, 0, 16);
6700 GEN_VXFORM(vsubuhm, 0, 17);
6701 GEN_VXFORM(vsubuwm, 0, 18);
6702 GEN_VXFORM(vmaxub, 1, 0);
6703 GEN_VXFORM(vmaxuh, 1, 1);
6704 GEN_VXFORM(vmaxuw, 1, 2);
6705 GEN_VXFORM(vmaxsb, 1, 4);
6706 GEN_VXFORM(vmaxsh, 1, 5);
6707 GEN_VXFORM(vmaxsw, 1, 6);
6708 GEN_VXFORM(vminub, 1, 8);
6709 GEN_VXFORM(vminuh, 1, 9);
6710 GEN_VXFORM(vminuw, 1, 10);
6711 GEN_VXFORM(vminsb, 1, 12);
6712 GEN_VXFORM(vminsh, 1, 13);
6713 GEN_VXFORM(vminsw, 1, 14);
6714 GEN_VXFORM(vavgub, 1, 16);
6715 GEN_VXFORM(vavguh, 1, 17);
6716 GEN_VXFORM(vavguw, 1, 18);
6717 GEN_VXFORM(vavgsb, 1, 20);
6718 GEN_VXFORM(vavgsh, 1, 21);
6719 GEN_VXFORM(vavgsw, 1, 22);
6720 GEN_VXFORM(vmrghb, 6, 0);
6721 GEN_VXFORM(vmrghh, 6, 1);
6722 GEN_VXFORM(vmrghw, 6, 2);
6723 GEN_VXFORM(vmrglb, 6, 4);
6724 GEN_VXFORM(vmrglh, 6, 5);
6725 GEN_VXFORM(vmrglw, 6, 6);
6726 GEN_VXFORM(vmuloub, 4, 0);
6727 GEN_VXFORM(vmulouh, 4, 1);
6728 GEN_VXFORM(vmulosb, 4, 4);
6729 GEN_VXFORM(vmulosh, 4, 5);
6730 GEN_VXFORM(vmuleub, 4, 8);
6731 GEN_VXFORM(vmuleuh, 4, 9);
6732 GEN_VXFORM(vmulesb, 4, 12);
6733 GEN_VXFORM(vmulesh, 4, 13);
6734 GEN_VXFORM(vslb, 2, 4);
6735 GEN_VXFORM(vslh, 2, 5);
6736 GEN_VXFORM(vslw, 2, 6);
6737 GEN_VXFORM(vsrb, 2, 8);
6738 GEN_VXFORM(vsrh, 2, 9);
6739 GEN_VXFORM(vsrw, 2, 10);
6740 GEN_VXFORM(vsrab, 2, 12);
6741 GEN_VXFORM(vsrah, 2, 13);
6742 GEN_VXFORM(vsraw, 2, 14);
6743 GEN_VXFORM(vslo, 6, 16);
6744 GEN_VXFORM(vsro, 6, 17);
6745 GEN_VXFORM(vaddcuw, 0, 6);
6746 GEN_VXFORM(vsubcuw, 0, 22);
6747 GEN_VXFORM_ENV(vaddubs, 0, 8);
6748 GEN_VXFORM_ENV(vadduhs, 0, 9);
6749 GEN_VXFORM_ENV(vadduws, 0, 10);
6750 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6751 GEN_VXFORM_ENV(vaddshs, 0, 13);
6752 GEN_VXFORM_ENV(vaddsws, 0, 14);
6753 GEN_VXFORM_ENV(vsububs, 0, 24);
6754 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6755 GEN_VXFORM_ENV(vsubuws, 0, 26);
6756 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6757 GEN_VXFORM_ENV(vsubshs, 0, 29);
6758 GEN_VXFORM_ENV(vsubsws, 0, 30);
6759 GEN_VXFORM(vrlb, 2, 0);
6760 GEN_VXFORM(vrlh, 2, 1);
6761 GEN_VXFORM(vrlw, 2, 2);
6762 GEN_VXFORM(vsl, 2, 7);
6763 GEN_VXFORM(vsr, 2, 11);
6764 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6765 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6766 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6767 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6768 GEN_VXFORM_ENV(vpkshus, 7, 4);
6769 GEN_VXFORM_ENV(vpkswus, 7, 5);
6770 GEN_VXFORM_ENV(vpkshss, 7, 6);
6771 GEN_VXFORM_ENV(vpkswss, 7, 7);
6772 GEN_VXFORM(vpkpx, 7, 12);
6773 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6774 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6775 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6776 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6777 GEN_VXFORM_ENV(vsumsws, 4, 30);
6778 GEN_VXFORM_ENV(vaddfp, 5, 0);
6779 GEN_VXFORM_ENV(vsubfp, 5, 1);
6780 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6781 GEN_VXFORM_ENV(vminfp, 5, 17);
6782
6783 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6784 static void glue(gen_, name)(DisasContext *ctx) \
6785 { \
6786 TCGv_ptr ra, rb, rd; \
6787 if (unlikely(!ctx->altivec_enabled)) { \
6788 gen_exception(ctx, POWERPC_EXCP_VPU); \
6789 return; \
6790 } \
6791 ra = gen_avr_ptr(rA(ctx->opcode)); \
6792 rb = gen_avr_ptr(rB(ctx->opcode)); \
6793 rd = gen_avr_ptr(rD(ctx->opcode)); \
6794 gen_helper_##opname(cpu_env, rd, ra, rb); \
6795 tcg_temp_free_ptr(ra); \
6796 tcg_temp_free_ptr(rb); \
6797 tcg_temp_free_ptr(rd); \
6798 }
6799
6800 #define GEN_VXRFORM(name, opc2, opc3) \
6801 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6802 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6803
6804 GEN_VXRFORM(vcmpequb, 3, 0)
6805 GEN_VXRFORM(vcmpequh, 3, 1)
6806 GEN_VXRFORM(vcmpequw, 3, 2)
6807 GEN_VXRFORM(vcmpgtsb, 3, 12)
6808 GEN_VXRFORM(vcmpgtsh, 3, 13)
6809 GEN_VXRFORM(vcmpgtsw, 3, 14)
6810 GEN_VXRFORM(vcmpgtub, 3, 8)
6811 GEN_VXRFORM(vcmpgtuh, 3, 9)
6812 GEN_VXRFORM(vcmpgtuw, 3, 10)
6813 GEN_VXRFORM(vcmpeqfp, 3, 3)
6814 GEN_VXRFORM(vcmpgefp, 3, 7)
6815 GEN_VXRFORM(vcmpgtfp, 3, 11)
6816 GEN_VXRFORM(vcmpbfp, 3, 15)
6817
6818 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6819 static void glue(gen_, name)(DisasContext *ctx) \
6820 { \
6821 TCGv_ptr rd; \
6822 TCGv_i32 simm; \
6823 if (unlikely(!ctx->altivec_enabled)) { \
6824 gen_exception(ctx, POWERPC_EXCP_VPU); \
6825 return; \
6826 } \
6827 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6828 rd = gen_avr_ptr(rD(ctx->opcode)); \
6829 gen_helper_##name (rd, simm); \
6830 tcg_temp_free_i32(simm); \
6831 tcg_temp_free_ptr(rd); \
6832 }
6833
6834 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6835 GEN_VXFORM_SIMM(vspltish, 6, 13);
6836 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6837
6838 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6839 static void glue(gen_, name)(DisasContext *ctx) \
6840 { \
6841 TCGv_ptr rb, rd; \
6842 if (unlikely(!ctx->altivec_enabled)) { \
6843 gen_exception(ctx, POWERPC_EXCP_VPU); \
6844 return; \
6845 } \
6846 rb = gen_avr_ptr(rB(ctx->opcode)); \
6847 rd = gen_avr_ptr(rD(ctx->opcode)); \
6848 gen_helper_##name (rd, rb); \
6849 tcg_temp_free_ptr(rb); \
6850 tcg_temp_free_ptr(rd); \
6851 }
6852
6853 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6854 static void glue(gen_, name)(DisasContext *ctx) \
6855 { \
6856 TCGv_ptr rb, rd; \
6857 \
6858 if (unlikely(!ctx->altivec_enabled)) { \
6859 gen_exception(ctx, POWERPC_EXCP_VPU); \
6860 return; \
6861 } \
6862 rb = gen_avr_ptr(rB(ctx->opcode)); \
6863 rd = gen_avr_ptr(rD(ctx->opcode)); \
6864 gen_helper_##name(cpu_env, rd, rb); \
6865 tcg_temp_free_ptr(rb); \
6866 tcg_temp_free_ptr(rd); \
6867 }
6868
6869 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6870 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6871 GEN_VXFORM_NOA(vupklsb, 7, 10);
6872 GEN_VXFORM_NOA(vupklsh, 7, 11);
6873 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6874 GEN_VXFORM_NOA(vupklpx, 7, 15);
6875 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6876 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6877 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6878 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6879 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6880 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6881 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6882 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6883
6884 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6885 static void glue(gen_, name)(DisasContext *ctx) \
6886 { \
6887 TCGv_ptr rd; \
6888 TCGv_i32 simm; \
6889 if (unlikely(!ctx->altivec_enabled)) { \
6890 gen_exception(ctx, POWERPC_EXCP_VPU); \
6891 return; \
6892 } \
6893 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6894 rd = gen_avr_ptr(rD(ctx->opcode)); \
6895 gen_helper_##name (rd, simm); \
6896 tcg_temp_free_i32(simm); \
6897 tcg_temp_free_ptr(rd); \
6898 }
6899
6900 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6901 static void glue(gen_, name)(DisasContext *ctx) \
6902 { \
6903 TCGv_ptr rb, rd; \
6904 TCGv_i32 uimm; \
6905 if (unlikely(!ctx->altivec_enabled)) { \
6906 gen_exception(ctx, POWERPC_EXCP_VPU); \
6907 return; \
6908 } \
6909 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6910 rb = gen_avr_ptr(rB(ctx->opcode)); \
6911 rd = gen_avr_ptr(rD(ctx->opcode)); \
6912 gen_helper_##name (rd, rb, uimm); \
6913 tcg_temp_free_i32(uimm); \
6914 tcg_temp_free_ptr(rb); \
6915 tcg_temp_free_ptr(rd); \
6916 }
6917
6918 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6919 static void glue(gen_, name)(DisasContext *ctx) \
6920 { \
6921 TCGv_ptr rb, rd; \
6922 TCGv_i32 uimm; \
6923 \
6924 if (unlikely(!ctx->altivec_enabled)) { \
6925 gen_exception(ctx, POWERPC_EXCP_VPU); \
6926 return; \
6927 } \
6928 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6929 rb = gen_avr_ptr(rB(ctx->opcode)); \
6930 rd = gen_avr_ptr(rD(ctx->opcode)); \
6931 gen_helper_##name(cpu_env, rd, rb, uimm); \
6932 tcg_temp_free_i32(uimm); \
6933 tcg_temp_free_ptr(rb); \
6934 tcg_temp_free_ptr(rd); \
6935 }
6936
6937 GEN_VXFORM_UIMM(vspltb, 6, 8);
6938 GEN_VXFORM_UIMM(vsplth, 6, 9);
6939 GEN_VXFORM_UIMM(vspltw, 6, 10);
6940 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6941 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6942 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6943 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6944
6945 static void gen_vsldoi(DisasContext *ctx)
6946 {
6947 TCGv_ptr ra, rb, rd;
6948 TCGv_i32 sh;
6949 if (unlikely(!ctx->altivec_enabled)) {
6950 gen_exception(ctx, POWERPC_EXCP_VPU);
6951 return;
6952 }
6953 ra = gen_avr_ptr(rA(ctx->opcode));
6954 rb = gen_avr_ptr(rB(ctx->opcode));
6955 rd = gen_avr_ptr(rD(ctx->opcode));
6956 sh = tcg_const_i32(VSH(ctx->opcode));
6957 gen_helper_vsldoi (rd, ra, rb, sh);
6958 tcg_temp_free_ptr(ra);
6959 tcg_temp_free_ptr(rb);
6960 tcg_temp_free_ptr(rd);
6961 tcg_temp_free_i32(sh);
6962 }
6963
6964 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6965 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6966 { \
6967 TCGv_ptr ra, rb, rc, rd; \
6968 if (unlikely(!ctx->altivec_enabled)) { \
6969 gen_exception(ctx, POWERPC_EXCP_VPU); \
6970 return; \
6971 } \
6972 ra = gen_avr_ptr(rA(ctx->opcode)); \
6973 rb = gen_avr_ptr(rB(ctx->opcode)); \
6974 rc = gen_avr_ptr(rC(ctx->opcode)); \
6975 rd = gen_avr_ptr(rD(ctx->opcode)); \
6976 if (Rc(ctx->opcode)) { \
6977 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6978 } else { \
6979 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6980 } \
6981 tcg_temp_free_ptr(ra); \
6982 tcg_temp_free_ptr(rb); \
6983 tcg_temp_free_ptr(rc); \
6984 tcg_temp_free_ptr(rd); \
6985 }
6986
6987 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6988
6989 static void gen_vmladduhm(DisasContext *ctx)
6990 {
6991 TCGv_ptr ra, rb, rc, rd;
6992 if (unlikely(!ctx->altivec_enabled)) {
6993 gen_exception(ctx, POWERPC_EXCP_VPU);
6994 return;
6995 }
6996 ra = gen_avr_ptr(rA(ctx->opcode));
6997 rb = gen_avr_ptr(rB(ctx->opcode));
6998 rc = gen_avr_ptr(rC(ctx->opcode));
6999 rd = gen_avr_ptr(rD(ctx->opcode));
7000 gen_helper_vmladduhm(rd, ra, rb, rc);
7001 tcg_temp_free_ptr(ra);
7002 tcg_temp_free_ptr(rb);
7003 tcg_temp_free_ptr(rc);
7004 tcg_temp_free_ptr(rd);
7005 }
7006
7007 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7008 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7009 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7010 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7011 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7012
7013 /*** VSX extension ***/
7014
7015 static inline TCGv_i64 cpu_vsrh(int n)
7016 {
7017 if (n < 32) {
7018 return cpu_fpr[n];
7019 } else {
7020 return cpu_avrh[n-32];
7021 }
7022 }
7023
7024 static inline TCGv_i64 cpu_vsrl(int n)
7025 {
7026 if (n < 32) {
7027 return cpu_vsr[n];
7028 } else {
7029 return cpu_avrl[n-32];
7030 }
7031 }
7032
7033 #define VSX_LOAD_SCALAR(name, operation) \
7034 static void gen_##name(DisasContext *ctx) \
7035 { \
7036 TCGv EA; \
7037 if (unlikely(!ctx->vsx_enabled)) { \
7038 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7039 return; \
7040 } \
7041 gen_set_access_type(ctx, ACCESS_INT); \
7042 EA = tcg_temp_new(); \
7043 gen_addr_reg_index(ctx, EA); \
7044 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7045 /* NOTE: cpu_vsrl is undefined */ \
7046 tcg_temp_free(EA); \
7047 }
7048
7049 VSX_LOAD_SCALAR(lxsdx, ld64)
7050 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7051 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7052 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7053
7054 static void gen_lxvd2x(DisasContext *ctx)
7055 {
7056 TCGv EA;
7057 if (unlikely(!ctx->vsx_enabled)) {
7058 gen_exception(ctx, POWERPC_EXCP_VSXU);
7059 return;
7060 }
7061 gen_set_access_type(ctx, ACCESS_INT);
7062 EA = tcg_temp_new();
7063 gen_addr_reg_index(ctx, EA);
7064 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7065 tcg_gen_addi_tl(EA, EA, 8);
7066 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7067 tcg_temp_free(EA);
7068 }
7069
7070 static void gen_lxvdsx(DisasContext *ctx)
7071 {
7072 TCGv EA;
7073 if (unlikely(!ctx->vsx_enabled)) {
7074 gen_exception(ctx, POWERPC_EXCP_VSXU);
7075 return;
7076 }
7077 gen_set_access_type(ctx, ACCESS_INT);
7078 EA = tcg_temp_new();
7079 gen_addr_reg_index(ctx, EA);
7080 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7081 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7082 tcg_temp_free(EA);
7083 }
7084
7085 static void gen_lxvw4x(DisasContext *ctx)
7086 {
7087 TCGv EA;
7088 TCGv_i64 tmp;
7089 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7090 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7091 if (unlikely(!ctx->vsx_enabled)) {
7092 gen_exception(ctx, POWERPC_EXCP_VSXU);
7093 return;
7094 }
7095 gen_set_access_type(ctx, ACCESS_INT);
7096 EA = tcg_temp_new();
7097 tmp = tcg_temp_new_i64();
7098
7099 gen_addr_reg_index(ctx, EA);
7100 gen_qemu_ld32u_i64(ctx, tmp, EA);
7101 tcg_gen_addi_tl(EA, EA, 4);
7102 gen_qemu_ld32u_i64(ctx, xth, EA);
7103 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7104
7105 tcg_gen_addi_tl(EA, EA, 4);
7106 gen_qemu_ld32u_i64(ctx, tmp, EA);
7107 tcg_gen_addi_tl(EA, EA, 4);
7108 gen_qemu_ld32u_i64(ctx, xtl, EA);
7109 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7110
7111 tcg_temp_free(EA);
7112 tcg_temp_free_i64(tmp);
7113 }
7114
7115 #define VSX_STORE_SCALAR(name, operation) \
7116 static void gen_##name(DisasContext *ctx) \
7117 { \
7118 TCGv EA; \
7119 if (unlikely(!ctx->vsx_enabled)) { \
7120 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7121 return; \
7122 } \
7123 gen_set_access_type(ctx, ACCESS_INT); \
7124 EA = tcg_temp_new(); \
7125 gen_addr_reg_index(ctx, EA); \
7126 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7127 tcg_temp_free(EA); \
7128 }
7129
7130 VSX_STORE_SCALAR(stxsdx, st64)
7131
7132 static void gen_stxvd2x(DisasContext *ctx)
7133 {
7134 TCGv EA;
7135 if (unlikely(!ctx->vsx_enabled)) {
7136 gen_exception(ctx, POWERPC_EXCP_VSXU);
7137 return;
7138 }
7139 gen_set_access_type(ctx, ACCESS_INT);
7140 EA = tcg_temp_new();
7141 gen_addr_reg_index(ctx, EA);
7142 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7143 tcg_gen_addi_tl(EA, EA, 8);
7144 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7145 tcg_temp_free(EA);
7146 }
7147
7148 static void gen_stxvw4x(DisasContext *ctx)
7149 {
7150 TCGv_i64 tmp;
7151 TCGv EA;
7152 if (unlikely(!ctx->vsx_enabled)) {
7153 gen_exception(ctx, POWERPC_EXCP_VSXU);
7154 return;
7155 }
7156 gen_set_access_type(ctx, ACCESS_INT);
7157 EA = tcg_temp_new();
7158 gen_addr_reg_index(ctx, EA);
7159 tmp = tcg_temp_new_i64();
7160
7161 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7162 gen_qemu_st32_i64(ctx, tmp, EA);
7163 tcg_gen_addi_tl(EA, EA, 4);
7164 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7165
7166 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7167 tcg_gen_addi_tl(EA, EA, 4);
7168 gen_qemu_st32_i64(ctx, tmp, EA);
7169 tcg_gen_addi_tl(EA, EA, 4);
7170 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7171
7172 tcg_temp_free(EA);
7173 tcg_temp_free_i64(tmp);
7174 }
7175
7176 static void gen_xxpermdi(DisasContext *ctx)
7177 {
7178 if (unlikely(!ctx->vsx_enabled)) {
7179 gen_exception(ctx, POWERPC_EXCP_VSXU);
7180 return;
7181 }
7182
7183 if ((DM(ctx->opcode) & 2) == 0) {
7184 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7185 } else {
7186 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7187 }
7188 if ((DM(ctx->opcode) & 1) == 0) {
7189 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7190 } else {
7191 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7192 }
7193 }
7194
7195 #define OP_ABS 1
7196 #define OP_NABS 2
7197 #define OP_NEG 3
7198 #define OP_CPSGN 4
7199 #define SGN_MASK_DP 0x8000000000000000ul
7200 #define SGN_MASK_SP 0x8000000080000000ul
7201
7202 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7203 static void glue(gen_, name)(DisasContext * ctx) \
7204 { \
7205 TCGv_i64 xb, sgm; \
7206 if (unlikely(!ctx->vsx_enabled)) { \
7207 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7208 return; \
7209 } \
7210 xb = tcg_temp_new_i64(); \
7211 sgm = tcg_temp_new_i64(); \
7212 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7213 tcg_gen_movi_i64(sgm, sgn_mask); \
7214 switch (op) { \
7215 case OP_ABS: { \
7216 tcg_gen_andc_i64(xb, xb, sgm); \
7217 break; \
7218 } \
7219 case OP_NABS: { \
7220 tcg_gen_or_i64(xb, xb, sgm); \
7221 break; \
7222 } \
7223 case OP_NEG: { \
7224 tcg_gen_xor_i64(xb, xb, sgm); \
7225 break; \
7226 } \
7227 case OP_CPSGN: { \
7228 TCGv_i64 xa = tcg_temp_new_i64(); \
7229 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7230 tcg_gen_and_i64(xa, xa, sgm); \
7231 tcg_gen_andc_i64(xb, xb, sgm); \
7232 tcg_gen_or_i64(xb, xb, xa); \
7233 tcg_temp_free_i64(xa); \
7234 break; \
7235 } \
7236 } \
7237 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7238 tcg_temp_free_i64(xb); \
7239 tcg_temp_free_i64(sgm); \
7240 }
7241
7242 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7243 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7244 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7245 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7246
7247 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7248 static void glue(gen_, name)(DisasContext * ctx) \
7249 { \
7250 TCGv_i64 xbh, xbl, sgm; \
7251 if (unlikely(!ctx->vsx_enabled)) { \
7252 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7253 return; \
7254 } \
7255 xbh = tcg_temp_new_i64(); \
7256 xbl = tcg_temp_new_i64(); \
7257 sgm = tcg_temp_new_i64(); \
7258 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7259 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7260 tcg_gen_movi_i64(sgm, sgn_mask); \
7261 switch (op) { \
7262 case OP_ABS: { \
7263 tcg_gen_andc_i64(xbh, xbh, sgm); \
7264 tcg_gen_andc_i64(xbl, xbl, sgm); \
7265 break; \
7266 } \
7267 case OP_NABS: { \
7268 tcg_gen_or_i64(xbh, xbh, sgm); \
7269 tcg_gen_or_i64(xbl, xbl, sgm); \
7270 break; \
7271 } \
7272 case OP_NEG: { \
7273 tcg_gen_xor_i64(xbh, xbh, sgm); \
7274 tcg_gen_xor_i64(xbl, xbl, sgm); \
7275 break; \
7276 } \
7277 case OP_CPSGN: { \
7278 TCGv_i64 xah = tcg_temp_new_i64(); \
7279 TCGv_i64 xal = tcg_temp_new_i64(); \
7280 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7281 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7282 tcg_gen_and_i64(xah, xah, sgm); \
7283 tcg_gen_and_i64(xal, xal, sgm); \
7284 tcg_gen_andc_i64(xbh, xbh, sgm); \
7285 tcg_gen_andc_i64(xbl, xbl, sgm); \
7286 tcg_gen_or_i64(xbh, xbh, xah); \
7287 tcg_gen_or_i64(xbl, xbl, xal); \
7288 tcg_temp_free_i64(xah); \
7289 tcg_temp_free_i64(xal); \
7290 break; \
7291 } \
7292 } \
7293 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7294 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7295 tcg_temp_free_i64(xbh); \
7296 tcg_temp_free_i64(xbl); \
7297 tcg_temp_free_i64(sgm); \
7298 }
7299
7300 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7301 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7302 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7303 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7304 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7305 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7306 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7307 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7308
7309 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7310 static void gen_##name(DisasContext * ctx) \
7311 { \
7312 TCGv_i32 opc; \
7313 if (unlikely(!ctx->vsx_enabled)) { \
7314 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7315 return; \
7316 } \
7317 /* NIP cannot be restored if the memory exception comes from an helper */ \
7318 gen_update_nip(ctx, ctx->nip - 4); \
7319 opc = tcg_const_i32(ctx->opcode); \
7320 gen_helper_##name(cpu_env, opc); \
7321 tcg_temp_free_i32(opc); \
7322 }
7323
7324 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7325 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7326 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7327 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7328 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7329 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7330 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7331 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7332 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7333 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7334 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7335 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7336 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7337 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7338 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7339 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7340 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7341 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7342 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7343 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7344 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7345 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7346 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7347 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7348 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7349 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7350 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7351 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7352 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
7353 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7354 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7355 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7356 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7357 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
7358
7359 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
7360 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
7361 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
7362 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
7363 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
7364 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
7365 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
7366 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
7367 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
7368 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
7369 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
7370 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
7371 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
7372 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
7373 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
7374 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
7375 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
7376 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
7377 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
7378 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
7379 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
7380 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
7381 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
7382 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
7383 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
7384 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
7385 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
7386 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
7387 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
7388 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
7389 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
7390 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
7391 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
7392 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
7393 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
7394 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
7395
7396 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
7397 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
7398 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
7399 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
7400 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
7401 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
7402 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
7403 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
7404 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
7405 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
7406 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
7407 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
7408 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
7409 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
7410 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
7411 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
7412 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
7413 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
7414 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
7415 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
7416 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
7417 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
7418 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
7419 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
7420 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
7421 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
7422 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
7423 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
7424 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
7425 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
7426 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
7427 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
7428 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
7429 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
7430 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
7431 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
7432
7433 #define VSX_LOGICAL(name, tcg_op) \
7434 static void glue(gen_, name)(DisasContext * ctx) \
7435 { \
7436 if (unlikely(!ctx->vsx_enabled)) { \
7437 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7438 return; \
7439 } \
7440 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
7441 cpu_vsrh(xB(ctx->opcode))); \
7442 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
7443 cpu_vsrl(xB(ctx->opcode))); \
7444 }
7445
7446 VSX_LOGICAL(xxland, tcg_gen_and_i64)
7447 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
7448 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
7449 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
7450 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
7451
7452 #define VSX_XXMRG(name, high) \
7453 static void glue(gen_, name)(DisasContext * ctx) \
7454 { \
7455 TCGv_i64 a0, a1, b0, b1; \
7456 if (unlikely(!ctx->vsx_enabled)) { \
7457 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7458 return; \
7459 } \
7460 a0 = tcg_temp_new_i64(); \
7461 a1 = tcg_temp_new_i64(); \
7462 b0 = tcg_temp_new_i64(); \
7463 b1 = tcg_temp_new_i64(); \
7464 if (high) { \
7465 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
7466 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
7467 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
7468 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
7469 } else { \
7470 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
7471 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
7472 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
7473 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
7474 } \
7475 tcg_gen_shri_i64(a0, a0, 32); \
7476 tcg_gen_shri_i64(b0, b0, 32); \
7477 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
7478 b0, a0, 32, 32); \
7479 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
7480 b1, a1, 32, 32); \
7481 tcg_temp_free_i64(a0); \
7482 tcg_temp_free_i64(a1); \
7483 tcg_temp_free_i64(b0); \
7484 tcg_temp_free_i64(b1); \
7485 }
7486
7487 VSX_XXMRG(xxmrghw, 1)
7488 VSX_XXMRG(xxmrglw, 0)
7489
7490 static void gen_xxsel(DisasContext * ctx)
7491 {
7492 TCGv_i64 a, b, c;
7493 if (unlikely(!ctx->vsx_enabled)) {
7494 gen_exception(ctx, POWERPC_EXCP_VSXU);
7495 return;
7496 }
7497 a = tcg_temp_new_i64();
7498 b = tcg_temp_new_i64();
7499 c = tcg_temp_new_i64();
7500
7501 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
7502 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
7503 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
7504
7505 tcg_gen_and_i64(b, b, c);
7506 tcg_gen_andc_i64(a, a, c);
7507 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
7508
7509 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
7510 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
7511 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
7512
7513 tcg_gen_and_i64(b, b, c);
7514 tcg_gen_andc_i64(a, a, c);
7515 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
7516
7517 tcg_temp_free_i64(a);
7518 tcg_temp_free_i64(b);
7519 tcg_temp_free_i64(c);
7520 }
7521
7522 static void gen_xxspltw(DisasContext *ctx)
7523 {
7524 TCGv_i64 b, b2;
7525 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
7526 cpu_vsrl(xB(ctx->opcode)) :
7527 cpu_vsrh(xB(ctx->opcode));
7528
7529 if (unlikely(!ctx->vsx_enabled)) {
7530 gen_exception(ctx, POWERPC_EXCP_VSXU);
7531 return;
7532 }
7533
7534 b = tcg_temp_new_i64();
7535 b2 = tcg_temp_new_i64();
7536
7537 if (UIM(ctx->opcode) & 1) {
7538 tcg_gen_ext32u_i64(b, vsr);
7539 } else {
7540 tcg_gen_shri_i64(b, vsr, 32);
7541 }
7542
7543 tcg_gen_shli_i64(b2, b, 32);
7544 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
7545 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7546
7547 tcg_temp_free_i64(b);
7548 tcg_temp_free_i64(b2);
7549 }
7550
7551 static void gen_xxsldwi(DisasContext *ctx)
7552 {
7553 TCGv_i64 xth, xtl;
7554 if (unlikely(!ctx->vsx_enabled)) {
7555 gen_exception(ctx, POWERPC_EXCP_VSXU);
7556 return;
7557 }
7558 xth = tcg_temp_new_i64();
7559 xtl = tcg_temp_new_i64();
7560
7561 switch (SHW(ctx->opcode)) {
7562 case 0: {
7563 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
7564 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
7565 break;
7566 }
7567 case 1: {
7568 TCGv_i64 t0 = tcg_temp_new_i64();
7569 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
7570 tcg_gen_shli_i64(xth, xth, 32);
7571 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
7572 tcg_gen_shri_i64(t0, t0, 32);
7573 tcg_gen_or_i64(xth, xth, t0);
7574 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
7575 tcg_gen_shli_i64(xtl, xtl, 32);
7576 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
7577 tcg_gen_shri_i64(t0, t0, 32);
7578 tcg_gen_or_i64(xtl, xtl, t0);
7579 tcg_temp_free_i64(t0);
7580 break;
7581 }
7582 case 2: {
7583 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
7584 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
7585 break;
7586 }
7587 case 3: {
7588 TCGv_i64 t0 = tcg_temp_new_i64();
7589 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
7590 tcg_gen_shli_i64(xth, xth, 32);
7591 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
7592 tcg_gen_shri_i64(t0, t0, 32);
7593 tcg_gen_or_i64(xth, xth, t0);
7594 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
7595 tcg_gen_shli_i64(xtl, xtl, 32);
7596 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
7597 tcg_gen_shri_i64(t0, t0, 32);
7598 tcg_gen_or_i64(xtl, xtl, t0);
7599 tcg_temp_free_i64(t0);
7600 break;
7601 }
7602 }
7603
7604 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
7605 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
7606
7607 tcg_temp_free_i64(xth);
7608 tcg_temp_free_i64(xtl);
7609 }
7610
7611
7612 /*** SPE extension ***/
7613 /* Register moves */
7614
7615 static inline void gen_evmra(DisasContext *ctx)
7616 {
7617
7618 if (unlikely(!ctx->spe_enabled)) {
7619 gen_exception(ctx, POWERPC_EXCP_SPEU);
7620 return;
7621 }
7622
7623 #if defined(TARGET_PPC64)
7624 /* rD := rA */
7625 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7626
7627 /* spe_acc := rA */
7628 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
7629 cpu_env,
7630 offsetof(CPUPPCState, spe_acc));
7631 #else
7632 TCGv_i64 tmp = tcg_temp_new_i64();
7633
7634 /* tmp := rA_lo + rA_hi << 32 */
7635 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7636
7637 /* spe_acc := tmp */
7638 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7639 tcg_temp_free_i64(tmp);
7640
7641 /* rD := rA */
7642 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7643 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7644 #endif
7645 }
7646
7647 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
7648 {
7649 #if defined(TARGET_PPC64)
7650 tcg_gen_mov_i64(t, cpu_gpr[reg]);
7651 #else
7652 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
7653 #endif
7654 }
7655
7656 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
7657 {
7658 #if defined(TARGET_PPC64)
7659 tcg_gen_mov_i64(cpu_gpr[reg], t);
7660 #else
7661 TCGv_i64 tmp = tcg_temp_new_i64();
7662 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
7663 tcg_gen_shri_i64(tmp, t, 32);
7664 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
7665 tcg_temp_free_i64(tmp);
7666 #endif
7667 }
7668
7669 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
7670 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7671 { \
7672 if (Rc(ctx->opcode)) \
7673 gen_##name1(ctx); \
7674 else \
7675 gen_##name0(ctx); \
7676 }
7677
7678 /* Handler for undefined SPE opcodes */
7679 static inline void gen_speundef(DisasContext *ctx)
7680 {
7681 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7682 }
7683
7684 /* SPE logic */
7685 #if defined(TARGET_PPC64)
7686 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
7687 static inline void gen_##name(DisasContext *ctx) \
7688 { \
7689 if (unlikely(!ctx->spe_enabled)) { \
7690 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7691 return; \
7692 } \
7693 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7694 cpu_gpr[rB(ctx->opcode)]); \
7695 }
7696 #else
7697 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
7698 static inline void gen_##name(DisasContext *ctx) \
7699 { \
7700 if (unlikely(!ctx->spe_enabled)) { \
7701 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7702 return; \
7703 } \
7704 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7705 cpu_gpr[rB(ctx->opcode)]); \
7706 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7707 cpu_gprh[rB(ctx->opcode)]); \
7708 }
7709 #endif
7710
7711 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
7712 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
7713 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
7714 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
7715 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
7716 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
7717 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
7718 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
7719
7720 /* SPE logic immediate */
7721 #if defined(TARGET_PPC64)
7722 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
7723 static inline void gen_##name(DisasContext *ctx) \
7724 { \
7725 if (unlikely(!ctx->spe_enabled)) { \
7726 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7727 return; \
7728 } \
7729 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7730 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7731 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7732 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7733 tcg_opi(t0, t0, rB(ctx->opcode)); \
7734 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7735 tcg_gen_trunc_i64_i32(t1, t2); \
7736 tcg_temp_free_i64(t2); \
7737 tcg_opi(t1, t1, rB(ctx->opcode)); \
7738 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7739 tcg_temp_free_i32(t0); \
7740 tcg_temp_free_i32(t1); \
7741 }
7742 #else
7743 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
7744 static inline void gen_##name(DisasContext *ctx) \
7745 { \
7746 if (unlikely(!ctx->spe_enabled)) { \
7747 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7748 return; \
7749 } \
7750 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7751 rB(ctx->opcode)); \
7752 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7753 rB(ctx->opcode)); \
7754 }
7755 #endif
7756 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
7757 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
7758 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
7759 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
7760
7761 /* SPE arithmetic */
7762 #if defined(TARGET_PPC64)
7763 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7764 static inline void gen_##name(DisasContext *ctx) \
7765 { \
7766 if (unlikely(!ctx->spe_enabled)) { \
7767 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7768 return; \
7769 } \
7770 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7771 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7772 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7773 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7774 tcg_op(t0, t0); \
7775 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7776 tcg_gen_trunc_i64_i32(t1, t2); \
7777 tcg_temp_free_i64(t2); \
7778 tcg_op(t1, t1); \
7779 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7780 tcg_temp_free_i32(t0); \
7781 tcg_temp_free_i32(t1); \
7782 }
7783 #else
7784 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7785 static inline void gen_##name(DisasContext *ctx) \
7786 { \
7787 if (unlikely(!ctx->spe_enabled)) { \
7788 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7789 return; \
7790 } \
7791 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
7792 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
7793 }
7794 #endif
7795
7796 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
7797 {
7798 int l1 = gen_new_label();
7799 int l2 = gen_new_label();
7800
7801 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
7802 tcg_gen_neg_i32(ret, arg1);
7803 tcg_gen_br(l2);
7804 gen_set_label(l1);
7805 tcg_gen_mov_i32(ret, arg1);
7806 gen_set_label(l2);
7807 }
7808 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
7809 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
7810 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
7811 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
7812 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
7813 {
7814 tcg_gen_addi_i32(ret, arg1, 0x8000);
7815 tcg_gen_ext16u_i32(ret, ret);
7816 }
7817 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
7818 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
7819 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
7820
7821 #if defined(TARGET_PPC64)
7822 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7823 static inline void gen_##name(DisasContext *ctx) \
7824 { \
7825 if (unlikely(!ctx->spe_enabled)) { \
7826 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7827 return; \
7828 } \
7829 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7830 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7831 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
7832 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
7833 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7834 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
7835 tcg_op(t0, t0, t2); \
7836 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
7837 tcg_gen_trunc_i64_i32(t1, t3); \
7838 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
7839 tcg_gen_trunc_i64_i32(t2, t3); \
7840 tcg_temp_free_i64(t3); \
7841 tcg_op(t1, t1, t2); \
7842 tcg_temp_free_i32(t2); \
7843 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7844 tcg_temp_free_i32(t0); \
7845 tcg_temp_free_i32(t1); \
7846 }
7847 #else
7848 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7849 static inline void gen_##name(DisasContext *ctx) \
7850 { \
7851 if (unlikely(!ctx->spe_enabled)) { \
7852 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7853 return; \
7854 } \
7855 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7856 cpu_gpr[rB(ctx->opcode)]); \
7857 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7858 cpu_gprh[rB(ctx->opcode)]); \
7859 }
7860 #endif
7861
7862 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7863 {
7864 TCGv_i32 t0;
7865 int l1, l2;
7866
7867 l1 = gen_new_label();
7868 l2 = gen_new_label();
7869 t0 = tcg_temp_local_new_i32();
7870 /* No error here: 6 bits are used */
7871 tcg_gen_andi_i32(t0, arg2, 0x3F);
7872 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7873 tcg_gen_shr_i32(ret, arg1, t0);
7874 tcg_gen_br(l2);
7875 gen_set_label(l1);
7876 tcg_gen_movi_i32(ret, 0);
7877 gen_set_label(l2);
7878 tcg_temp_free_i32(t0);
7879 }
7880 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7881 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7882 {
7883 TCGv_i32 t0;
7884 int l1, l2;
7885
7886 l1 = gen_new_label();
7887 l2 = gen_new_label();
7888 t0 = tcg_temp_local_new_i32();
7889 /* No error here: 6 bits are used */
7890 tcg_gen_andi_i32(t0, arg2, 0x3F);
7891 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7892 tcg_gen_sar_i32(ret, arg1, t0);
7893 tcg_gen_br(l2);
7894 gen_set_label(l1);
7895 tcg_gen_movi_i32(ret, 0);
7896 gen_set_label(l2);
7897 tcg_temp_free_i32(t0);
7898 }
7899 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7900 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7901 {
7902 TCGv_i32 t0;
7903 int l1, l2;
7904
7905 l1 = gen_new_label();
7906 l2 = gen_new_label();
7907 t0 = tcg_temp_local_new_i32();
7908 /* No error here: 6 bits are used */
7909 tcg_gen_andi_i32(t0, arg2, 0x3F);
7910 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7911 tcg_gen_shl_i32(ret, arg1, t0);
7912 tcg_gen_br(l2);
7913 gen_set_label(l1);
7914 tcg_gen_movi_i32(ret, 0);
7915 gen_set_label(l2);
7916 tcg_temp_free_i32(t0);
7917 }
7918 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7919 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7920 {
7921 TCGv_i32 t0 = tcg_temp_new_i32();
7922 tcg_gen_andi_i32(t0, arg2, 0x1F);
7923 tcg_gen_rotl_i32(ret, arg1, t0);
7924 tcg_temp_free_i32(t0);
7925 }
7926 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7927 static inline void gen_evmergehi(DisasContext *ctx)
7928 {
7929 if (unlikely(!ctx->spe_enabled)) {
7930 gen_exception(ctx, POWERPC_EXCP_SPEU);
7931 return;
7932 }
7933 #if defined(TARGET_PPC64)
7934 TCGv t0 = tcg_temp_new();
7935 TCGv t1 = tcg_temp_new();
7936 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7937 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7938 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7939 tcg_temp_free(t0);
7940 tcg_temp_free(t1);
7941 #else
7942 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7943 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7944 #endif
7945 }
7946 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7947 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7948 {
7949 tcg_gen_sub_i32(ret, arg2, arg1);
7950 }
7951 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7952
7953 /* SPE arithmetic immediate */
7954 #if defined(TARGET_PPC64)
7955 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7956 static inline void gen_##name(DisasContext *ctx) \
7957 { \
7958 if (unlikely(!ctx->spe_enabled)) { \
7959 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7960 return; \
7961 } \
7962 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7963 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7964 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7965 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7966 tcg_op(t0, t0, rA(ctx->opcode)); \
7967 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7968 tcg_gen_trunc_i64_i32(t1, t2); \
7969 tcg_temp_free_i64(t2); \
7970 tcg_op(t1, t1, rA(ctx->opcode)); \
7971 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7972 tcg_temp_free_i32(t0); \
7973 tcg_temp_free_i32(t1); \
7974 }
7975 #else
7976 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7977 static inline void gen_##name(DisasContext *ctx) \
7978 { \
7979 if (unlikely(!ctx->spe_enabled)) { \
7980 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7981 return; \
7982 } \
7983 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7984 rA(ctx->opcode)); \
7985 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7986 rA(ctx->opcode)); \
7987 }
7988 #endif
7989 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7990 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7991
7992 /* SPE comparison */
7993 #if defined(TARGET_PPC64)
7994 #define GEN_SPEOP_COMP(name, tcg_cond) \
7995 static inline void gen_##name(DisasContext *ctx) \
7996 { \
7997 if (unlikely(!ctx->spe_enabled)) { \
7998 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7999 return; \
8000 } \
8001 int l1 = gen_new_label(); \
8002 int l2 = gen_new_label(); \
8003 int l3 = gen_new_label(); \
8004 int l4 = gen_new_label(); \
8005 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8006 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8007 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8008 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8009 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8010 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
8011 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8012 tcg_gen_br(l2); \
8013 gen_set_label(l1); \
8014 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8015 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8016 gen_set_label(l2); \
8017 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
8018 tcg_gen_trunc_i64_i32(t0, t2); \
8019 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
8020 tcg_gen_trunc_i64_i32(t1, t2); \
8021 tcg_temp_free_i64(t2); \
8022 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
8023 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8024 ~(CRF_CH | CRF_CH_AND_CL)); \
8025 tcg_gen_br(l4); \
8026 gen_set_label(l3); \
8027 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8028 CRF_CH | CRF_CH_OR_CL); \
8029 gen_set_label(l4); \
8030 tcg_temp_free_i32(t0); \
8031 tcg_temp_free_i32(t1); \
8032 }
8033 #else
8034 #define GEN_SPEOP_COMP(name, tcg_cond) \
8035 static inline void gen_##name(DisasContext *ctx) \
8036 { \
8037 if (unlikely(!ctx->spe_enabled)) { \
8038 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8039 return; \
8040 } \
8041 int l1 = gen_new_label(); \
8042 int l2 = gen_new_label(); \
8043 int l3 = gen_new_label(); \
8044 int l4 = gen_new_label(); \
8045 \
8046 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8047 cpu_gpr[rB(ctx->opcode)], l1); \
8048 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
8049 tcg_gen_br(l2); \
8050 gen_set_label(l1); \
8051 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8052 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8053 gen_set_label(l2); \
8054 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8055 cpu_gprh[rB(ctx->opcode)], l3); \
8056 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8057 ~(CRF_CH | CRF_CH_AND_CL)); \
8058 tcg_gen_br(l4); \
8059 gen_set_label(l3); \
8060 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8061 CRF_CH | CRF_CH_OR_CL); \
8062 gen_set_label(l4); \
8063 }
8064 #endif
8065 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8066 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8067 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8068 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8069 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8070
8071 /* SPE misc */
8072 static inline void gen_brinc(DisasContext *ctx)
8073 {
8074 /* Note: brinc is usable even if SPE is disabled */
8075 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8076 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8077 }
8078 static inline void gen_evmergelo(DisasContext *ctx)
8079 {
8080 if (unlikely(!ctx->spe_enabled)) {
8081 gen_exception(ctx, POWERPC_EXCP_SPEU);
8082 return;
8083 }
8084 #if defined(TARGET_PPC64)
8085 TCGv t0 = tcg_temp_new();
8086 TCGv t1 = tcg_temp_new();
8087 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
8088 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
8089 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8090 tcg_temp_free(t0);
8091 tcg_temp_free(t1);
8092 #else
8093 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8094 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8095 #endif
8096 }
8097 static inline void gen_evmergehilo(DisasContext *ctx)
8098 {
8099 if (unlikely(!ctx->spe_enabled)) {
8100 gen_exception(ctx, POWERPC_EXCP_SPEU);
8101 return;
8102 }
8103 #if defined(TARGET_PPC64)
8104 TCGv t0 = tcg_temp_new();
8105 TCGv t1 = tcg_temp_new();
8106 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
8107 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
8108 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8109 tcg_temp_free(t0);
8110 tcg_temp_free(t1);
8111 #else
8112 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8113 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8114 #endif
8115 }
8116 static inline void gen_evmergelohi(DisasContext *ctx)
8117 {
8118 if (unlikely(!ctx->spe_enabled)) {
8119 gen_exception(ctx, POWERPC_EXCP_SPEU);
8120 return;
8121 }
8122 #if defined(TARGET_PPC64)
8123 TCGv t0 = tcg_temp_new();
8124 TCGv t1 = tcg_temp_new();
8125 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
8126 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
8127 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8128 tcg_temp_free(t0);
8129 tcg_temp_free(t1);
8130 #else
8131 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8132 TCGv_i32 tmp = tcg_temp_new_i32();
8133 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
8134 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8135 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
8136 tcg_temp_free_i32(tmp);
8137 } else {
8138 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8139 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8140 }
8141 #endif
8142 }
8143 static inline void gen_evsplati(DisasContext *ctx)
8144 {
8145 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8146
8147 #if defined(TARGET_PPC64)
8148 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
8149 #else
8150 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
8151 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
8152 #endif
8153 }
8154 static inline void gen_evsplatfi(DisasContext *ctx)
8155 {
8156 uint64_t imm = rA(ctx->opcode) << 27;
8157
8158 #if defined(TARGET_PPC64)
8159 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
8160 #else
8161 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
8162 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
8163 #endif
8164 }
8165
8166 static inline void gen_evsel(DisasContext *ctx)
8167 {
8168 int l1 = gen_new_label();
8169 int l2 = gen_new_label();
8170 int l3 = gen_new_label();
8171 int l4 = gen_new_label();
8172 TCGv_i32 t0 = tcg_temp_local_new_i32();
8173 #if defined(TARGET_PPC64)
8174 TCGv t1 = tcg_temp_local_new();
8175 TCGv t2 = tcg_temp_local_new();
8176 #endif
8177 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8178 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8179 #if defined(TARGET_PPC64)
8180 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
8181 #else
8182 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8183 #endif
8184 tcg_gen_br(l2);
8185 gen_set_label(l1);
8186 #if defined(TARGET_PPC64)
8187 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
8188 #else
8189 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8190 #endif
8191 gen_set_label(l2);
8192 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8193 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8194 #if defined(TARGET_PPC64)
8195 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
8196 #else
8197 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8198 #endif
8199 tcg_gen_br(l4);
8200 gen_set_label(l3);
8201 #if defined(TARGET_PPC64)
8202 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
8203 #else
8204 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8205 #endif
8206 gen_set_label(l4);
8207 tcg_temp_free_i32(t0);
8208 #if defined(TARGET_PPC64)
8209 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
8210 tcg_temp_free(t1);
8211 tcg_temp_free(t2);
8212 #endif
8213 }
8214
8215 static void gen_evsel0(DisasContext *ctx)
8216 {
8217 gen_evsel(ctx);
8218 }
8219
8220 static void gen_evsel1(DisasContext *ctx)
8221 {
8222 gen_evsel(ctx);
8223 }
8224
8225 static void gen_evsel2(DisasContext *ctx)
8226 {
8227 gen_evsel(ctx);
8228 }
8229
8230 static void gen_evsel3(DisasContext *ctx)
8231 {
8232 gen_evsel(ctx);
8233 }
8234
8235 /* Multiply */
8236
8237 static inline void gen_evmwumi(DisasContext *ctx)
8238 {
8239 TCGv_i64 t0, t1;
8240
8241 if (unlikely(!ctx->spe_enabled)) {
8242 gen_exception(ctx, POWERPC_EXCP_SPEU);
8243 return;
8244 }
8245
8246 t0 = tcg_temp_new_i64();
8247 t1 = tcg_temp_new_i64();
8248
8249 /* t0 := rA; t1 := rB */
8250 #if defined(TARGET_PPC64)
8251 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
8252 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
8253 #else
8254 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8255 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8256 #endif
8257
8258 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8259
8260 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8261
8262 tcg_temp_free_i64(t0);
8263 tcg_temp_free_i64(t1);
8264 }
8265
8266 static inline void gen_evmwumia(DisasContext *ctx)
8267 {
8268 TCGv_i64 tmp;
8269
8270 if (unlikely(!ctx->spe_enabled)) {
8271 gen_exception(ctx, POWERPC_EXCP_SPEU);
8272 return;
8273 }
8274
8275 gen_evmwumi(ctx); /* rD := rA * rB */
8276
8277 tmp = tcg_temp_new_i64();
8278
8279 /* acc := rD */
8280 gen_load_gpr64(tmp, rD(ctx->opcode));
8281 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8282 tcg_temp_free_i64(tmp);
8283 }
8284
8285 static inline void gen_evmwumiaa(DisasContext *ctx)
8286 {
8287 TCGv_i64 acc;
8288 TCGv_i64 tmp;
8289
8290 if (unlikely(!ctx->spe_enabled)) {
8291 gen_exception(ctx, POWERPC_EXCP_SPEU);
8292 return;
8293 }
8294
8295 gen_evmwumi(ctx); /* rD := rA * rB */
8296
8297 acc = tcg_temp_new_i64();
8298 tmp = tcg_temp_new_i64();
8299
8300 /* tmp := rD */
8301 gen_load_gpr64(tmp, rD(ctx->opcode));
8302
8303 /* Load acc */
8304 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8305
8306 /* acc := tmp + acc */
8307 tcg_gen_add_i64(acc, acc, tmp);
8308
8309 /* Store acc */
8310 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8311
8312 /* rD := acc */
8313 gen_store_gpr64(rD(ctx->opcode), acc);
8314
8315 tcg_temp_free_i64(acc);
8316 tcg_temp_free_i64(tmp);
8317 }
8318
8319 static inline void gen_evmwsmi(DisasContext *ctx)
8320 {
8321 TCGv_i64 t0, t1;
8322
8323 if (unlikely(!ctx->spe_enabled)) {
8324 gen_exception(ctx, POWERPC_EXCP_SPEU);
8325 return;
8326 }
8327
8328 t0 = tcg_temp_new_i64();
8329 t1 = tcg_temp_new_i64();
8330
8331 /* t0 := rA; t1 := rB */
8332 #if defined(TARGET_PPC64)
8333 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
8334 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
8335 #else
8336 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8337 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8338 #endif
8339
8340 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8341
8342 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8343
8344 tcg_temp_free_i64(t0);
8345 tcg_temp_free_i64(t1);
8346 }
8347
8348 static inline void gen_evmwsmia(DisasContext *ctx)
8349 {
8350 TCGv_i64 tmp;
8351
8352 gen_evmwsmi(ctx); /* rD := rA * rB */
8353
8354 tmp = tcg_temp_new_i64();
8355
8356 /* acc := rD */
8357 gen_load_gpr64(tmp, rD(ctx->opcode));
8358 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8359
8360 tcg_temp_free_i64(tmp);
8361 }
8362
8363 static inline void gen_evmwsmiaa(DisasContext *ctx)
8364 {
8365 TCGv_i64 acc = tcg_temp_new_i64();
8366 TCGv_i64 tmp = tcg_temp_new_i64();
8367
8368 gen_evmwsmi(ctx); /* rD := rA * rB */
8369
8370 acc = tcg_temp_new_i64();
8371 tmp = tcg_temp_new_i64();
8372
8373 /* tmp := rD */
8374 gen_load_gpr64(tmp, rD(ctx->opcode));
8375
8376 /* Load acc */
8377 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8378
8379 /* acc := tmp + acc */
8380 tcg_gen_add_i64(acc, acc, tmp);
8381
8382 /* Store acc */
8383 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8384
8385 /* rD := acc */
8386 gen_store_gpr64(rD(ctx->opcode), acc);
8387
8388 tcg_temp_free_i64(acc);
8389 tcg_temp_free_i64(tmp);
8390 }
8391
8392 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8393 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8394 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8395 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8396 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8397 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8398 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8399 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
8400 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
8401 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8402 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8403 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8404 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8405 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8406 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8407 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8408 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8409 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8410 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8411 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
8412 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8413 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8414 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
8415 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
8416 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8417 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8418 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8419 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8420 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
8421
8422 /* SPE load and stores */
8423 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
8424 {
8425 target_ulong uimm = rB(ctx->opcode);
8426
8427 if (rA(ctx->opcode) == 0) {
8428 tcg_gen_movi_tl(EA, uimm << sh);
8429 } else {
8430 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
8431 if (NARROW_MODE(ctx)) {
8432 tcg_gen_ext32u_tl(EA, EA);
8433 }
8434 }
8435 }
8436
8437 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
8438 {
8439 #if defined(TARGET_PPC64)
8440 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8441 #else
8442 TCGv_i64 t0 = tcg_temp_new_i64();
8443 gen_qemu_ld64(ctx, t0, addr);
8444 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
8445 tcg_gen_shri_i64(t0, t0, 32);
8446 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
8447 tcg_temp_free_i64(t0);
8448 #endif
8449 }
8450
8451 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
8452 {
8453 #if defined(TARGET_PPC64)
8454 TCGv t0 = tcg_temp_new();
8455 gen_qemu_ld32u(ctx, t0, addr);
8456 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8457 gen_addr_add(ctx, addr, addr, 4);
8458 gen_qemu_ld32u(ctx, t0, addr);
8459 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8460 tcg_temp_free(t0);
8461 #else
8462 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
8463 gen_addr_add(ctx, addr, addr, 4);
8464 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8465 #endif
8466 }
8467
8468 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
8469 {
8470 TCGv t0 = tcg_temp_new();
8471 #if defined(TARGET_PPC64)
8472 gen_qemu_ld16u(ctx, t0, addr);
8473 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8474 gen_addr_add(ctx, addr, addr, 2);
8475 gen_qemu_ld16u(ctx, t0, addr);
8476 tcg_gen_shli_tl(t0, t0, 32);
8477 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8478 gen_addr_add(ctx, addr, addr, 2);
8479 gen_qemu_ld16u(ctx, t0, addr);
8480 tcg_gen_shli_tl(t0, t0, 16);
8481 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8482 gen_addr_add(ctx, addr, addr, 2);
8483 gen_qemu_ld16u(ctx, t0, addr);
8484 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8485 #else
8486 gen_qemu_ld16u(ctx, t0, addr);
8487 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8488 gen_addr_add(ctx, addr, addr, 2);
8489 gen_qemu_ld16u(ctx, t0, addr);
8490 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
8491 gen_addr_add(ctx, addr, addr, 2);
8492 gen_qemu_ld16u(ctx, t0, addr);
8493 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8494 gen_addr_add(ctx, addr, addr, 2);
8495 gen_qemu_ld16u(ctx, t0, addr);
8496 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8497 #endif
8498 tcg_temp_free(t0);
8499 }
8500
8501 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
8502 {
8503 TCGv t0 = tcg_temp_new();
8504 gen_qemu_ld16u(ctx, t0, addr);
8505 #if defined(TARGET_PPC64)
8506 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8507 tcg_gen_shli_tl(t0, t0, 16);
8508 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8509 #else
8510 tcg_gen_shli_tl(t0, t0, 16);
8511 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8512 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8513 #endif
8514 tcg_temp_free(t0);
8515 }
8516
8517 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
8518 {
8519 TCGv t0 = tcg_temp_new();
8520 gen_qemu_ld16u(ctx, t0, addr);
8521 #if defined(TARGET_PPC64)
8522 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8523 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8524 #else
8525 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8526 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8527 #endif
8528 tcg_temp_free(t0);
8529 }
8530
8531 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
8532 {
8533 TCGv t0 = tcg_temp_new();
8534 gen_qemu_ld16s(ctx, t0, addr);
8535 #if defined(TARGET_PPC64)
8536 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8537 tcg_gen_ext32u_tl(t0, t0);
8538 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8539 #else
8540 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8541 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8542 #endif
8543 tcg_temp_free(t0);
8544 }
8545
8546 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
8547 {
8548 TCGv t0 = tcg_temp_new();
8549 #if defined(TARGET_PPC64)
8550 gen_qemu_ld16u(ctx, t0, addr);
8551 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8552 gen_addr_add(ctx, addr, addr, 2);
8553 gen_qemu_ld16u(ctx, t0, addr);
8554 tcg_gen_shli_tl(t0, t0, 16);
8555 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8556 #else
8557 gen_qemu_ld16u(ctx, t0, addr);
8558 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8559 gen_addr_add(ctx, addr, addr, 2);
8560 gen_qemu_ld16u(ctx, t0, addr);
8561 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
8562 #endif
8563 tcg_temp_free(t0);
8564 }
8565
8566 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
8567 {
8568 #if defined(TARGET_PPC64)
8569 TCGv t0 = tcg_temp_new();
8570 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8571 gen_addr_add(ctx, addr, addr, 2);
8572 gen_qemu_ld16u(ctx, t0, addr);
8573 tcg_gen_shli_tl(t0, t0, 32);
8574 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8575 tcg_temp_free(t0);
8576 #else
8577 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
8578 gen_addr_add(ctx, addr, addr, 2);
8579 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8580 #endif
8581 }
8582
8583 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
8584 {
8585 #if defined(TARGET_PPC64)
8586 TCGv t0 = tcg_temp_new();
8587 gen_qemu_ld16s(ctx, t0, addr);
8588 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
8589 gen_addr_add(ctx, addr, addr, 2);
8590 gen_qemu_ld16s(ctx, t0, addr);
8591 tcg_gen_shli_tl(t0, t0, 32);
8592 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8593 tcg_temp_free(t0);
8594 #else
8595 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
8596 gen_addr_add(ctx, addr, addr, 2);
8597 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8598 #endif
8599 }
8600
8601 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
8602 {
8603 TCGv t0 = tcg_temp_new();
8604 gen_qemu_ld32u(ctx, t0, addr);
8605 #if defined(TARGET_PPC64)
8606 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8607 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8608 #else
8609 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8610 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8611 #endif
8612 tcg_temp_free(t0);
8613 }
8614
8615 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
8616 {
8617 TCGv t0 = tcg_temp_new();
8618 #if defined(TARGET_PPC64)
8619 gen_qemu_ld16u(ctx, t0, addr);
8620 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8621 tcg_gen_shli_tl(t0, t0, 32);
8622 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8623 gen_addr_add(ctx, addr, addr, 2);
8624 gen_qemu_ld16u(ctx, t0, addr);
8625 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8626 tcg_gen_shli_tl(t0, t0, 16);
8627 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8628 #else
8629 gen_qemu_ld16u(ctx, t0, addr);
8630 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8631 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
8632 gen_addr_add(ctx, addr, addr, 2);
8633 gen_qemu_ld16u(ctx, t0, addr);
8634 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
8635 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
8636 #endif
8637 tcg_temp_free(t0);
8638 }
8639
8640 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
8641 {
8642 #if defined(TARGET_PPC64)
8643 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8644 #else
8645 TCGv_i64 t0 = tcg_temp_new_i64();
8646 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
8647 gen_qemu_st64(ctx, t0, addr);
8648 tcg_temp_free_i64(t0);
8649 #endif
8650 }
8651
8652 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
8653 {
8654 #if defined(TARGET_PPC64)
8655 TCGv t0 = tcg_temp_new();
8656 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8657 gen_qemu_st32(ctx, t0, addr);
8658 tcg_temp_free(t0);
8659 #else
8660 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8661 #endif
8662 gen_addr_add(ctx, addr, addr, 4);
8663 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8664 }
8665
8666 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
8667 {
8668 TCGv t0 = tcg_temp_new();
8669 #if defined(TARGET_PPC64)
8670 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
8671 #else
8672 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
8673 #endif
8674 gen_qemu_st16(ctx, t0, addr);
8675 gen_addr_add(ctx, addr, addr, 2);
8676 #if defined(TARGET_PPC64)
8677 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8678 gen_qemu_st16(ctx, t0, addr);
8679 #else
8680 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8681 #endif
8682 gen_addr_add(ctx, addr, addr, 2);
8683 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
8684 gen_qemu_st16(ctx, t0, addr);
8685 tcg_temp_free(t0);
8686 gen_addr_add(ctx, addr, addr, 2);
8687 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8688 }
8689
8690 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
8691 {
8692 TCGv t0 = tcg_temp_new();
8693 #if defined(TARGET_PPC64)
8694 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
8695 #else
8696 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
8697 #endif
8698 gen_qemu_st16(ctx, t0, addr);
8699 gen_addr_add(ctx, addr, addr, 2);
8700 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
8701 gen_qemu_st16(ctx, t0, addr);
8702 tcg_temp_free(t0);
8703 }
8704
8705 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
8706 {
8707 #if defined(TARGET_PPC64)
8708 TCGv t0 = tcg_temp_new();
8709 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8710 gen_qemu_st16(ctx, t0, addr);
8711 tcg_temp_free(t0);
8712 #else
8713 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8714 #endif
8715 gen_addr_add(ctx, addr, addr, 2);
8716 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8717 }
8718
8719 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
8720 {
8721 #if defined(TARGET_PPC64)
8722 TCGv t0 = tcg_temp_new();
8723 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8724 gen_qemu_st32(ctx, t0, addr);
8725 tcg_temp_free(t0);
8726 #else
8727 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8728 #endif
8729 }
8730
8731 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
8732 {
8733 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8734 }
8735
8736 #define GEN_SPEOP_LDST(name, opc2, sh) \
8737 static void glue(gen_, name)(DisasContext *ctx) \
8738 { \
8739 TCGv t0; \
8740 if (unlikely(!ctx->spe_enabled)) { \
8741 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8742 return; \
8743 } \
8744 gen_set_access_type(ctx, ACCESS_INT); \
8745 t0 = tcg_temp_new(); \
8746 if (Rc(ctx->opcode)) { \
8747 gen_addr_spe_imm_index(ctx, t0, sh); \
8748 } else { \
8749 gen_addr_reg_index(ctx, t0); \
8750 } \
8751 gen_op_##name(ctx, t0); \
8752 tcg_temp_free(t0); \
8753 }
8754
8755 GEN_SPEOP_LDST(evldd, 0x00, 3);
8756 GEN_SPEOP_LDST(evldw, 0x01, 3);
8757 GEN_SPEOP_LDST(evldh, 0x02, 3);
8758 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
8759 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
8760 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
8761 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
8762 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
8763 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
8764 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
8765 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
8766
8767 GEN_SPEOP_LDST(evstdd, 0x10, 3);
8768 GEN_SPEOP_LDST(evstdw, 0x11, 3);
8769 GEN_SPEOP_LDST(evstdh, 0x12, 3);
8770 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
8771 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
8772 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
8773 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
8774
8775 /* Multiply and add - TODO */
8776 #if 0
8777 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
8778 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8779 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8780 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8781 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8782 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8783 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8784 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8785 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8786 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8787 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8788 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8789
8790 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8791 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8792 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8793 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8794 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8795 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8796 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8797 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8798 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8799 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8800 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8801 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8802
8803 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8804 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8805 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8806 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8807 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
8808
8809 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8810 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8811 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8812 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8813 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8814 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8815 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8816 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8817 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8818 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8819 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8820 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8821
8822 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8823 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8824 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8825 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8826
8827 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8828 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8829 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8830 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8831 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8832 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8833 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8834 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8835 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8836 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8837 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8838 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8839
8840 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8841 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8842 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8843 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8844 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8845 #endif
8846
8847 /*** SPE floating-point extension ***/
8848 #if defined(TARGET_PPC64)
8849 #define GEN_SPEFPUOP_CONV_32_32(name) \
8850 static inline void gen_##name(DisasContext *ctx) \
8851 { \
8852 TCGv_i32 t0; \
8853 TCGv t1; \
8854 t0 = tcg_temp_new_i32(); \
8855 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8856 gen_helper_##name(t0, cpu_env, t0); \
8857 t1 = tcg_temp_new(); \
8858 tcg_gen_extu_i32_tl(t1, t0); \
8859 tcg_temp_free_i32(t0); \
8860 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8861 0xFFFFFFFF00000000ULL); \
8862 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8863 tcg_temp_free(t1); \
8864 }
8865 #define GEN_SPEFPUOP_CONV_32_64(name) \
8866 static inline void gen_##name(DisasContext *ctx) \
8867 { \
8868 TCGv_i32 t0; \
8869 TCGv t1; \
8870 t0 = tcg_temp_new_i32(); \
8871 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8872 t1 = tcg_temp_new(); \
8873 tcg_gen_extu_i32_tl(t1, t0); \
8874 tcg_temp_free_i32(t0); \
8875 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8876 0xFFFFFFFF00000000ULL); \
8877 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8878 tcg_temp_free(t1); \
8879 }
8880 #define GEN_SPEFPUOP_CONV_64_32(name) \
8881 static inline void gen_##name(DisasContext *ctx) \
8882 { \
8883 TCGv_i32 t0 = tcg_temp_new_i32(); \
8884 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8885 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8886 tcg_temp_free_i32(t0); \
8887 }
8888 #define GEN_SPEFPUOP_CONV_64_64(name) \
8889 static inline void gen_##name(DisasContext *ctx) \
8890 { \
8891 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8892 cpu_gpr[rB(ctx->opcode)]); \
8893 }
8894 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8895 static inline void gen_##name(DisasContext *ctx) \
8896 { \
8897 TCGv_i32 t0, t1; \
8898 TCGv_i64 t2; \
8899 if (unlikely(!ctx->spe_enabled)) { \
8900 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8901 return; \
8902 } \
8903 t0 = tcg_temp_new_i32(); \
8904 t1 = tcg_temp_new_i32(); \
8905 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8906 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8907 gen_helper_##name(t0, cpu_env, t0, t1); \
8908 tcg_temp_free_i32(t1); \
8909 t2 = tcg_temp_new(); \
8910 tcg_gen_extu_i32_tl(t2, t0); \
8911 tcg_temp_free_i32(t0); \
8912 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8913 0xFFFFFFFF00000000ULL); \
8914 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8915 tcg_temp_free(t2); \
8916 }
8917 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8918 static inline void gen_##name(DisasContext *ctx) \
8919 { \
8920 if (unlikely(!ctx->spe_enabled)) { \
8921 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8922 return; \
8923 } \
8924 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8925 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8926 }
8927 #define GEN_SPEFPUOP_COMP_32(name) \
8928 static inline void gen_##name(DisasContext *ctx) \
8929 { \
8930 TCGv_i32 t0, t1; \
8931 if (unlikely(!ctx->spe_enabled)) { \
8932 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8933 return; \
8934 } \
8935 t0 = tcg_temp_new_i32(); \
8936 t1 = tcg_temp_new_i32(); \
8937 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8938 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8939 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8940 tcg_temp_free_i32(t0); \
8941 tcg_temp_free_i32(t1); \
8942 }
8943 #define GEN_SPEFPUOP_COMP_64(name) \
8944 static inline void gen_##name(DisasContext *ctx) \
8945 { \
8946 if (unlikely(!ctx->spe_enabled)) { \
8947 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8948 return; \
8949 } \
8950 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8951 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8952 }
8953 #else
8954 #define GEN_SPEFPUOP_CONV_32_32(name) \
8955 static inline void gen_##name(DisasContext *ctx) \
8956 { \
8957 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8958 cpu_gpr[rB(ctx->opcode)]); \
8959 }
8960 #define GEN_SPEFPUOP_CONV_32_64(name) \
8961 static inline void gen_##name(DisasContext *ctx) \
8962 { \
8963 TCGv_i64 t0 = tcg_temp_new_i64(); \
8964 gen_load_gpr64(t0, rB(ctx->opcode)); \
8965 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8966 tcg_temp_free_i64(t0); \
8967 }
8968 #define GEN_SPEFPUOP_CONV_64_32(name) \
8969 static inline void gen_##name(DisasContext *ctx) \
8970 { \
8971 TCGv_i64 t0 = tcg_temp_new_i64(); \
8972 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8973 gen_store_gpr64(rD(ctx->opcode), t0); \
8974 tcg_temp_free_i64(t0); \
8975 }
8976 #define GEN_SPEFPUOP_CONV_64_64(name) \
8977 static inline void gen_##name(DisasContext *ctx) \
8978 { \
8979 TCGv_i64 t0 = tcg_temp_new_i64(); \
8980 gen_load_gpr64(t0, rB(ctx->opcode)); \
8981 gen_helper_##name(t0, cpu_env, t0); \
8982 gen_store_gpr64(rD(ctx->opcode), t0); \
8983 tcg_temp_free_i64(t0); \
8984 }
8985 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8986 static inline void gen_##name(DisasContext *ctx) \
8987 { \
8988 if (unlikely(!ctx->spe_enabled)) { \
8989 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8990 return; \
8991 } \
8992 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8993 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8994 }
8995 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8996 static inline void gen_##name(DisasContext *ctx) \
8997 { \
8998 TCGv_i64 t0, t1; \
8999 if (unlikely(!ctx->spe_enabled)) { \
9000 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9001 return; \
9002 } \
9003 t0 = tcg_temp_new_i64(); \
9004 t1 = tcg_temp_new_i64(); \
9005 gen_load_gpr64(t0, rA(ctx->opcode)); \
9006 gen_load_gpr64(t1, rB(ctx->opcode)); \
9007 gen_helper_##name(t0, cpu_env, t0, t1); \
9008 gen_store_gpr64(rD(ctx->opcode), t0); \
9009 tcg_temp_free_i64(t0); \
9010 tcg_temp_free_i64(t1); \
9011 }
9012 #define GEN_SPEFPUOP_COMP_32(name) \
9013 static inline void gen_##name(DisasContext *ctx) \
9014 { \
9015 if (unlikely(!ctx->spe_enabled)) { \
9016 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9017 return; \
9018 } \
9019 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
9020 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9021 }
9022 #define GEN_SPEFPUOP_COMP_64(name) \
9023 static inline void gen_##name(DisasContext *ctx) \
9024 { \
9025 TCGv_i64 t0, t1; \
9026 if (unlikely(!ctx->spe_enabled)) { \
9027 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9028 return; \
9029 } \
9030 t0 = tcg_temp_new_i64(); \
9031 t1 = tcg_temp_new_i64(); \
9032 gen_load_gpr64(t0, rA(ctx->opcode)); \
9033 gen_load_gpr64(t1, rB(ctx->opcode)); \
9034 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9035 tcg_temp_free_i64(t0); \
9036 tcg_temp_free_i64(t1); \
9037 }
9038 #endif
9039
9040 /* Single precision floating-point vectors operations */
9041 /* Arithmetic */
9042 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9043 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9044 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9045 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9046 static inline void gen_evfsabs(DisasContext *ctx)
9047 {
9048 if (unlikely(!ctx->spe_enabled)) {
9049 gen_exception(ctx, POWERPC_EXCP_SPEU);
9050 return;
9051 }
9052 #if defined(TARGET_PPC64)
9053 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
9054 #else
9055 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
9056 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
9057 #endif
9058 }
9059 static inline void gen_evfsnabs(DisasContext *ctx)
9060 {
9061 if (unlikely(!ctx->spe_enabled)) {
9062 gen_exception(ctx, POWERPC_EXCP_SPEU);
9063 return;
9064 }
9065 #if defined(TARGET_PPC64)
9066 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
9067 #else
9068 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9069 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9070 #endif
9071 }
9072 static inline void gen_evfsneg(DisasContext *ctx)
9073 {
9074 if (unlikely(!ctx->spe_enabled)) {
9075 gen_exception(ctx, POWERPC_EXCP_SPEU);
9076 return;
9077 }
9078 #if defined(TARGET_PPC64)
9079 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
9080 #else
9081 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9082 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9083 #endif
9084 }
9085
9086 /* Conversion */
9087 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9088 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9089 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9090 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9091 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9092 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9093 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9094 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9095 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9096 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9097
9098 /* Comparison */
9099 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9100 GEN_SPEFPUOP_COMP_64(evfscmplt);
9101 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9102 GEN_SPEFPUOP_COMP_64(evfststgt);
9103 GEN_SPEFPUOP_COMP_64(evfststlt);
9104 GEN_SPEFPUOP_COMP_64(evfststeq);
9105
9106 /* Opcodes definitions */
9107 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9108 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9109 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9110 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9111 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9112 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9113 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9114 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9115 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9116 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9117 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9118 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9119 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9120 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9121
9122 /* Single precision floating-point operations */
9123 /* Arithmetic */
9124 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9125 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9126 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9127 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9128 static inline void gen_efsabs(DisasContext *ctx)
9129 {
9130 if (unlikely(!ctx->spe_enabled)) {
9131 gen_exception(ctx, POWERPC_EXCP_SPEU);
9132 return;
9133 }
9134 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9135 }
9136 static inline void gen_efsnabs(DisasContext *ctx)
9137 {
9138 if (unlikely(!ctx->spe_enabled)) {
9139 gen_exception(ctx, POWERPC_EXCP_SPEU);
9140 return;
9141 }
9142 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9143 }
9144 static inline void gen_efsneg(DisasContext *ctx)
9145 {
9146 if (unlikely(!ctx->spe_enabled)) {
9147 gen_exception(ctx, POWERPC_EXCP_SPEU);
9148 return;
9149 }
9150 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9151 }
9152
9153 /* Conversion */
9154 GEN_SPEFPUOP_CONV_32_32(efscfui);
9155 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9156 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9157 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9158 GEN_SPEFPUOP_CONV_32_32(efsctui);
9159 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9160 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9161 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9162 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9163 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9164 GEN_SPEFPUOP_CONV_32_64(efscfd);
9165
9166 /* Comparison */
9167 GEN_SPEFPUOP_COMP_32(efscmpgt);
9168 GEN_SPEFPUOP_COMP_32(efscmplt);
9169 GEN_SPEFPUOP_COMP_32(efscmpeq);
9170 GEN_SPEFPUOP_COMP_32(efststgt);
9171 GEN_SPEFPUOP_COMP_32(efststlt);
9172 GEN_SPEFPUOP_COMP_32(efststeq);
9173
9174 /* Opcodes definitions */
9175 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9176 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9177 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9178 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9179 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9180 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9181 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9182 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9183 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9184 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9185 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9186 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9187 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9188 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9189
9190 /* Double precision floating-point operations */
9191 /* Arithmetic */
9192 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9193 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9194 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9195 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9196 static inline void gen_efdabs(DisasContext *ctx)
9197 {
9198 if (unlikely(!ctx->spe_enabled)) {
9199 gen_exception(ctx, POWERPC_EXCP_SPEU);
9200 return;
9201 }
9202 #if defined(TARGET_PPC64)
9203 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
9204 #else
9205 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9206 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
9207 #endif
9208 }
9209 static inline void gen_efdnabs(DisasContext *ctx)
9210 {
9211 if (unlikely(!ctx->spe_enabled)) {
9212 gen_exception(ctx, POWERPC_EXCP_SPEU);
9213 return;
9214 }
9215 #if defined(TARGET_PPC64)
9216 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
9217 #else
9218 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9219 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9220 #endif
9221 }
9222 static inline void gen_efdneg(DisasContext *ctx)
9223 {
9224 if (unlikely(!ctx->spe_enabled)) {
9225 gen_exception(ctx, POWERPC_EXCP_SPEU);
9226 return;
9227 }
9228 #if defined(TARGET_PPC64)
9229 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
9230 #else
9231 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9232 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9233 #endif
9234 }
9235
9236 /* Conversion */
9237 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9238 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9239 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9240 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9241 GEN_SPEFPUOP_CONV_32_64(efdctui);
9242 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9243 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9244 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9245 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9246 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9247 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9248 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9249 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9250 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9251 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9252
9253 /* Comparison */
9254 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9255 GEN_SPEFPUOP_COMP_64(efdcmplt);
9256 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9257 GEN_SPEFPUOP_COMP_64(efdtstgt);
9258 GEN_SPEFPUOP_COMP_64(efdtstlt);
9259 GEN_SPEFPUOP_COMP_64(efdtsteq);
9260
9261 /* Opcodes definitions */
9262 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9263 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9264 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9265 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9266 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9267 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9268 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9269 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9270 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9271 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9272 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9273 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9274 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9275 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9276 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9277 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9278
9279 static opcode_t opcodes[] = {
9280 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9281 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9282 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9283 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9284 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9285 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9286 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9287 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9288 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9289 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9290 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9291 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9292 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9293 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9294 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9295 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9296 #if defined(TARGET_PPC64)
9297 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9298 #endif
9299 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9300 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9301 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9302 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9303 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9304 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9305 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9306 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9307 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9308 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9309 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9310 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9311 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
9312 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9313 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9314 #if defined(TARGET_PPC64)
9315 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9316 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9317 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9318 #endif
9319 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9320 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9321 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9322 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9323 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9324 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9325 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9326 #if defined(TARGET_PPC64)
9327 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9328 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9329 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9330 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9331 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9332 #endif
9333 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9334 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9335 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9336 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9337 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9338 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9339 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9340 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9341 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9342 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9343 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9344 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9345 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9346 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9347 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9348 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9349 #if defined(TARGET_PPC64)
9350 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9351 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9352 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9353 #endif
9354 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9355 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9356 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9357 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9358 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9359 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9360 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9361 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9362 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9363 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9364 #if defined(TARGET_PPC64)
9365 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9366 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9367 #endif
9368 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9369 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9370 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9371 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9372 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9373 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9374 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9375 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9376 #if defined(TARGET_PPC64)
9377 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9378 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9379 #endif
9380 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9381 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9382 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9383 #if defined(TARGET_PPC64)
9384 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9385 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9386 #endif
9387 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9388 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9389 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9390 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9391 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9392 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9393 #if defined(TARGET_PPC64)
9394 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9395 #endif
9396 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9397 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
9398 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9399 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9400 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9401 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
9402 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
9403 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9404 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9405 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9406 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9407 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9408 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9409 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9410 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9411 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9412 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9413 #if defined(TARGET_PPC64)
9414 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9415 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9416 PPC_SEGMENT_64B),
9417 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9418 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9419 PPC_SEGMENT_64B),
9420 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9421 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9422 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9423 #endif
9424 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9425 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9426 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9427 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9428 #if defined(TARGET_PPC64)
9429 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9430 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9431 #endif
9432 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9433 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9434 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9435 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9436 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9437 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9438 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9439 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9440 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9441 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9442 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9443 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9444 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9445 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9446 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9447 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9448 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9449 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9450 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9451 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9452 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9453 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9454 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9455 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9456 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9457 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9458 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9459 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9460 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9461 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9462 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9463 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9464 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9465 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9466 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9467 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9468 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9469 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9470 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9471 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
9472 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
9473 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
9474 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
9475 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
9476 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
9477 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
9478 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
9479 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
9480 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
9481 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9482 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9483 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
9484 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
9485 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9486 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9487 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
9488 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
9489 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
9490 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
9491 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
9492 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
9493 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
9494 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
9495 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
9496 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
9497 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
9498 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
9499 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
9500 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
9501 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
9502 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
9503 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
9504 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
9505 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
9506 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
9507 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
9508 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
9509 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
9510 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
9511 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
9512 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
9513 PPC_NONE, PPC2_BOOKE206),
9514 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
9515 PPC_NONE, PPC2_BOOKE206),
9516 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
9517 PPC_NONE, PPC2_BOOKE206),
9518 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
9519 PPC_NONE, PPC2_BOOKE206),
9520 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
9521 PPC_NONE, PPC2_BOOKE206),
9522 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
9523 PPC_NONE, PPC2_PRCNTL),
9524 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
9525 PPC_NONE, PPC2_PRCNTL),
9526 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
9527 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
9528 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
9529 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
9530 PPC_BOOKE, PPC2_BOOKE206),
9531 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
9532 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
9533 PPC_BOOKE, PPC2_BOOKE206),
9534 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
9535 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
9536 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
9537 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
9538 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
9539 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
9540 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
9541 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
9542 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
9543 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
9544
9545 #undef GEN_INT_ARITH_ADD
9546 #undef GEN_INT_ARITH_ADD_CONST
9547 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
9548 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
9549 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
9550 add_ca, compute_ca, compute_ov) \
9551 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
9552 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
9553 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
9554 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
9555 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
9556 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
9557 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
9558 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
9559 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
9560 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
9561 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
9562
9563 #undef GEN_INT_ARITH_DIVW
9564 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
9565 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
9566 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
9567 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
9568 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
9569 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
9570
9571 #if defined(TARGET_PPC64)
9572 #undef GEN_INT_ARITH_DIVD
9573 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
9574 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9575 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
9576 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
9577 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
9578 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
9579
9580 #undef GEN_INT_ARITH_MUL_HELPER
9581 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
9582 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9583 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
9584 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
9585 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
9586 #endif
9587
9588 #undef GEN_INT_ARITH_SUBF
9589 #undef GEN_INT_ARITH_SUBF_CONST
9590 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
9591 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
9592 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
9593 add_ca, compute_ca, compute_ov) \
9594 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
9595 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
9596 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
9597 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
9598 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
9599 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
9600 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
9601 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
9602 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
9603 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
9604 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
9605
9606 #undef GEN_LOGICAL1
9607 #undef GEN_LOGICAL2
9608 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
9609 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
9610 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
9611 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
9612 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
9613 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
9614 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
9615 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
9616 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
9617 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
9618 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
9619 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
9620 #if defined(TARGET_PPC64)
9621 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
9622 #endif
9623
9624 #if defined(TARGET_PPC64)
9625 #undef GEN_PPC64_R2
9626 #undef GEN_PPC64_R4
9627 #define GEN_PPC64_R2(name, opc1, opc2) \
9628 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9629 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9630 PPC_64B)
9631 #define GEN_PPC64_R4(name, opc1, opc2) \
9632 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9633 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
9634 PPC_64B), \
9635 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9636 PPC_64B), \
9637 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
9638 PPC_64B)
9639 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
9640 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
9641 GEN_PPC64_R4(rldic, 0x1E, 0x04),
9642 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
9643 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
9644 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
9645 #endif
9646
9647 #undef _GEN_FLOAT_ACB
9648 #undef GEN_FLOAT_ACB
9649 #undef _GEN_FLOAT_AB
9650 #undef GEN_FLOAT_AB
9651 #undef _GEN_FLOAT_AC
9652 #undef GEN_FLOAT_AC
9653 #undef GEN_FLOAT_B
9654 #undef GEN_FLOAT_BS
9655 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
9656 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
9657 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
9658 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
9659 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
9660 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
9661 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
9662 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
9663 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
9664 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
9665 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
9666 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
9667 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
9668 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
9669 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
9670 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
9671 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
9672 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
9673 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
9674
9675 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
9676 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
9677 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
9678 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
9679 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
9680 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
9681 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
9682 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
9683 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
9684 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
9685 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
9686 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
9687 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
9688 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
9689 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
9690 #if defined(TARGET_PPC64)
9691 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
9692 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
9693 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
9694 #endif
9695 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
9696 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
9697 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
9698 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
9699
9700 #undef GEN_LD
9701 #undef GEN_LDU
9702 #undef GEN_LDUX
9703 #undef GEN_LDX_E
9704 #undef GEN_LDS
9705 #define GEN_LD(name, ldop, opc, type) \
9706 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9707 #define GEN_LDU(name, ldop, opc, type) \
9708 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9709 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
9710 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
9711 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
9712 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
9713 #define GEN_LDS(name, ldop, op, type) \
9714 GEN_LD(name, ldop, op | 0x20, type) \
9715 GEN_LDU(name, ldop, op | 0x21, type) \
9716 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
9717 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
9718
9719 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
9720 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
9721 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
9722 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
9723 #if defined(TARGET_PPC64)
9724 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
9725 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
9726 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
9727 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
9728 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
9729 #endif
9730 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
9731 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
9732
9733 #undef GEN_ST
9734 #undef GEN_STU
9735 #undef GEN_STUX
9736 #undef GEN_STX_E
9737 #undef GEN_STS
9738 #define GEN_ST(name, stop, opc, type) \
9739 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9740 #define GEN_STU(name, stop, opc, type) \
9741 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
9742 #define GEN_STUX(name, stop, opc2, opc3, type) \
9743 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
9744 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
9745 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
9746 #define GEN_STS(name, stop, op, type) \
9747 GEN_ST(name, stop, op | 0x20, type) \
9748 GEN_STU(name, stop, op | 0x21, type) \
9749 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
9750 GEN_STX(name, stop, 0x17, op | 0x00, type)
9751
9752 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
9753 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
9754 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
9755 #if defined(TARGET_PPC64)
9756 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
9757 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
9758 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
9759 #endif
9760 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
9761 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
9762
9763 #undef GEN_LDF
9764 #undef GEN_LDUF
9765 #undef GEN_LDUXF
9766 #undef GEN_LDXF
9767 #undef GEN_LDFS
9768 #define GEN_LDF(name, ldop, opc, type) \
9769 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9770 #define GEN_LDUF(name, ldop, opc, type) \
9771 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9772 #define GEN_LDUXF(name, ldop, opc, type) \
9773 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9774 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
9775 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9776 #define GEN_LDFS(name, ldop, op, type) \
9777 GEN_LDF(name, ldop, op | 0x20, type) \
9778 GEN_LDUF(name, ldop, op | 0x21, type) \
9779 GEN_LDUXF(name, ldop, op | 0x01, type) \
9780 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
9781
9782 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
9783 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
9784 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
9785 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
9786 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
9787
9788 #undef GEN_STF
9789 #undef GEN_STUF
9790 #undef GEN_STUXF
9791 #undef GEN_STXF
9792 #undef GEN_STFS
9793 #define GEN_STF(name, stop, opc, type) \
9794 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9795 #define GEN_STUF(name, stop, opc, type) \
9796 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9797 #define GEN_STUXF(name, stop, opc, type) \
9798 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9799 #define GEN_STXF(name, stop, opc2, opc3, type) \
9800 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9801 #define GEN_STFS(name, stop, op, type) \
9802 GEN_STF(name, stop, op | 0x20, type) \
9803 GEN_STUF(name, stop, op | 0x21, type) \
9804 GEN_STUXF(name, stop, op | 0x01, type) \
9805 GEN_STXF(name, stop, 0x17, op | 0x00, type)
9806
9807 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
9808 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
9809 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
9810 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
9811 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
9812
9813 #undef GEN_CRLOGIC
9814 #define GEN_CRLOGIC(name, tcg_op, opc) \
9815 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
9816 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
9817 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
9818 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
9819 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
9820 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
9821 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
9822 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
9823 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
9824
9825 #undef GEN_MAC_HANDLER
9826 #define GEN_MAC_HANDLER(name, opc2, opc3) \
9827 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
9828 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
9829 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
9830 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
9831 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
9832 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
9833 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
9834 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
9835 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
9836 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
9837 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
9838 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
9839 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
9840 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
9841 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
9842 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
9843 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
9844 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
9845 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
9846 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
9847 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
9848 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
9849 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
9850 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
9851 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
9852 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
9853 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
9854 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
9855 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
9856 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
9857 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
9858 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
9859 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
9860 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
9861 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
9862 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
9863 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
9864 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9865 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9866 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9867 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9868 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9869 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9870
9871 #undef GEN_VR_LDX
9872 #undef GEN_VR_STX
9873 #undef GEN_VR_LVE
9874 #undef GEN_VR_STVE
9875 #define GEN_VR_LDX(name, opc2, opc3) \
9876 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9877 #define GEN_VR_STX(name, opc2, opc3) \
9878 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9879 #define GEN_VR_LVE(name, opc2, opc3) \
9880 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9881 #define GEN_VR_STVE(name, opc2, opc3) \
9882 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9883 GEN_VR_LDX(lvx, 0x07, 0x03),
9884 GEN_VR_LDX(lvxl, 0x07, 0x0B),
9885 GEN_VR_LVE(bx, 0x07, 0x00),
9886 GEN_VR_LVE(hx, 0x07, 0x01),
9887 GEN_VR_LVE(wx, 0x07, 0x02),
9888 GEN_VR_STX(svx, 0x07, 0x07),
9889 GEN_VR_STX(svxl, 0x07, 0x0F),
9890 GEN_VR_STVE(bx, 0x07, 0x04),
9891 GEN_VR_STVE(hx, 0x07, 0x05),
9892 GEN_VR_STVE(wx, 0x07, 0x06),
9893
9894 #undef GEN_VX_LOGICAL
9895 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9896 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9897 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9898 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9899 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9900 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9901 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9902
9903 #undef GEN_VXFORM
9904 #define GEN_VXFORM(name, opc2, opc3) \
9905 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9906 GEN_VXFORM(vaddubm, 0, 0),
9907 GEN_VXFORM(vadduhm, 0, 1),
9908 GEN_VXFORM(vadduwm, 0, 2),
9909 GEN_VXFORM(vsububm, 0, 16),
9910 GEN_VXFORM(vsubuhm, 0, 17),
9911 GEN_VXFORM(vsubuwm, 0, 18),
9912 GEN_VXFORM(vmaxub, 1, 0),
9913 GEN_VXFORM(vmaxuh, 1, 1),
9914 GEN_VXFORM(vmaxuw, 1, 2),
9915 GEN_VXFORM(vmaxsb, 1, 4),
9916 GEN_VXFORM(vmaxsh, 1, 5),
9917 GEN_VXFORM(vmaxsw, 1, 6),
9918 GEN_VXFORM(vminub, 1, 8),
9919 GEN_VXFORM(vminuh, 1, 9),
9920 GEN_VXFORM(vminuw, 1, 10),
9921 GEN_VXFORM(vminsb, 1, 12),
9922 GEN_VXFORM(vminsh, 1, 13),
9923 GEN_VXFORM(vminsw, 1, 14),
9924 GEN_VXFORM(vavgub, 1, 16),
9925 GEN_VXFORM(vavguh, 1, 17),
9926 GEN_VXFORM(vavguw, 1, 18),
9927 GEN_VXFORM(vavgsb, 1, 20),
9928 GEN_VXFORM(vavgsh, 1, 21),
9929 GEN_VXFORM(vavgsw, 1, 22),
9930 GEN_VXFORM(vmrghb, 6, 0),
9931 GEN_VXFORM(vmrghh, 6, 1),
9932 GEN_VXFORM(vmrghw, 6, 2),
9933 GEN_VXFORM(vmrglb, 6, 4),
9934 GEN_VXFORM(vmrglh, 6, 5),
9935 GEN_VXFORM(vmrglw, 6, 6),
9936 GEN_VXFORM(vmuloub, 4, 0),
9937 GEN_VXFORM(vmulouh, 4, 1),
9938 GEN_VXFORM(vmulosb, 4, 4),
9939 GEN_VXFORM(vmulosh, 4, 5),
9940 GEN_VXFORM(vmuleub, 4, 8),
9941 GEN_VXFORM(vmuleuh, 4, 9),
9942 GEN_VXFORM(vmulesb, 4, 12),
9943 GEN_VXFORM(vmulesh, 4, 13),
9944 GEN_VXFORM(vslb, 2, 4),
9945 GEN_VXFORM(vslh, 2, 5),
9946 GEN_VXFORM(vslw, 2, 6),
9947 GEN_VXFORM(vsrb, 2, 8),
9948 GEN_VXFORM(vsrh, 2, 9),
9949 GEN_VXFORM(vsrw, 2, 10),
9950 GEN_VXFORM(vsrab, 2, 12),
9951 GEN_VXFORM(vsrah, 2, 13),
9952 GEN_VXFORM(vsraw, 2, 14),
9953 GEN_VXFORM(vslo, 6, 16),
9954 GEN_VXFORM(vsro, 6, 17),
9955 GEN_VXFORM(vaddcuw, 0, 6),
9956 GEN_VXFORM(vsubcuw, 0, 22),
9957 GEN_VXFORM(vaddubs, 0, 8),
9958 GEN_VXFORM(vadduhs, 0, 9),
9959 GEN_VXFORM(vadduws, 0, 10),
9960 GEN_VXFORM(vaddsbs, 0, 12),
9961 GEN_VXFORM(vaddshs, 0, 13),
9962 GEN_VXFORM(vaddsws, 0, 14),
9963 GEN_VXFORM(vsububs, 0, 24),
9964 GEN_VXFORM(vsubuhs, 0, 25),
9965 GEN_VXFORM(vsubuws, 0, 26),
9966 GEN_VXFORM(vsubsbs, 0, 28),
9967 GEN_VXFORM(vsubshs, 0, 29),
9968 GEN_VXFORM(vsubsws, 0, 30),
9969 GEN_VXFORM(vrlb, 2, 0),
9970 GEN_VXFORM(vrlh, 2, 1),
9971 GEN_VXFORM(vrlw, 2, 2),
9972 GEN_VXFORM(vsl, 2, 7),
9973 GEN_VXFORM(vsr, 2, 11),
9974 GEN_VXFORM(vpkuhum, 7, 0),
9975 GEN_VXFORM(vpkuwum, 7, 1),
9976 GEN_VXFORM(vpkuhus, 7, 2),
9977 GEN_VXFORM(vpkuwus, 7, 3),
9978 GEN_VXFORM(vpkshus, 7, 4),
9979 GEN_VXFORM(vpkswus, 7, 5),
9980 GEN_VXFORM(vpkshss, 7, 6),
9981 GEN_VXFORM(vpkswss, 7, 7),
9982 GEN_VXFORM(vpkpx, 7, 12),
9983 GEN_VXFORM(vsum4ubs, 4, 24),
9984 GEN_VXFORM(vsum4sbs, 4, 28),
9985 GEN_VXFORM(vsum4shs, 4, 25),
9986 GEN_VXFORM(vsum2sws, 4, 26),
9987 GEN_VXFORM(vsumsws, 4, 30),
9988 GEN_VXFORM(vaddfp, 5, 0),
9989 GEN_VXFORM(vsubfp, 5, 1),
9990 GEN_VXFORM(vmaxfp, 5, 16),
9991 GEN_VXFORM(vminfp, 5, 17),
9992
9993 #undef GEN_VXRFORM1
9994 #undef GEN_VXRFORM
9995 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9996 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9997 #define GEN_VXRFORM(name, opc2, opc3) \
9998 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9999 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10000 GEN_VXRFORM(vcmpequb, 3, 0)
10001 GEN_VXRFORM(vcmpequh, 3, 1)
10002 GEN_VXRFORM(vcmpequw, 3, 2)
10003 GEN_VXRFORM(vcmpgtsb, 3, 12)
10004 GEN_VXRFORM(vcmpgtsh, 3, 13)
10005 GEN_VXRFORM(vcmpgtsw, 3, 14)
10006 GEN_VXRFORM(vcmpgtub, 3, 8)
10007 GEN_VXRFORM(vcmpgtuh, 3, 9)
10008 GEN_VXRFORM(vcmpgtuw, 3, 10)
10009 GEN_VXRFORM(vcmpeqfp, 3, 3)
10010 GEN_VXRFORM(vcmpgefp, 3, 7)
10011 GEN_VXRFORM(vcmpgtfp, 3, 11)
10012 GEN_VXRFORM(vcmpbfp, 3, 15)
10013
10014 #undef GEN_VXFORM_SIMM
10015 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10016 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10017 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10018 GEN_VXFORM_SIMM(vspltish, 6, 13),
10019 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10020
10021 #undef GEN_VXFORM_NOA
10022 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10023 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10024 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10025 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10026 GEN_VXFORM_NOA(vupklsb, 7, 10),
10027 GEN_VXFORM_NOA(vupklsh, 7, 11),
10028 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10029 GEN_VXFORM_NOA(vupklpx, 7, 15),
10030 GEN_VXFORM_NOA(vrefp, 5, 4),
10031 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10032 GEN_VXFORM_NOA(vexptefp, 5, 6),
10033 GEN_VXFORM_NOA(vlogefp, 5, 7),
10034 GEN_VXFORM_NOA(vrfim, 5, 8),
10035 GEN_VXFORM_NOA(vrfin, 5, 9),
10036 GEN_VXFORM_NOA(vrfip, 5, 10),
10037 GEN_VXFORM_NOA(vrfiz, 5, 11),
10038
10039 #undef GEN_VXFORM_UIMM
10040 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10041 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10042 GEN_VXFORM_UIMM(vspltb, 6, 8),
10043 GEN_VXFORM_UIMM(vsplth, 6, 9),
10044 GEN_VXFORM_UIMM(vspltw, 6, 10),
10045 GEN_VXFORM_UIMM(vcfux, 5, 12),
10046 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10047 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10048 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10049
10050 #undef GEN_VAFORM_PAIRED
10051 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10052 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10053 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10054 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10055 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10056 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10057 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10058 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10059
10060 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10061 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10062 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10063 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10064 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10065 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10066 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10067
10068 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10069 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10070 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10071
10072 #undef GEN_XX2FORM
10073 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10074 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10075 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10076
10077 #undef GEN_XX3FORM
10078 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10079 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10080 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10081 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10082 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10083
10084 #undef GEN_XX3_RC_FORM
10085 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10086 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10087 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10088 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10089 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10090 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10091 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10092 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10093 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10094
10095 #undef GEN_XX3FORM_DM
10096 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10097 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10098 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10099 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10100 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10101 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10102 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10103 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10104 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10105 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10106 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10107 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10108 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10109 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10110 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10111 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10112 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10113
10114 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10115 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10116 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10117 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10118
10119 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10120 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10121 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10122 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10123 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10124 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10125 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10126 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10127
10128 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10129 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10130 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10131 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10132 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10133 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10134 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10135 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10136 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10137 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10138 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10139 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10140 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10141 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10142 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10143 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10144 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10145 GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10146 GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10147 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10148 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10149 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10150 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10151 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10152 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10153 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10154 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10155 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10156 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10157 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10158 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10159 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10160 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10161 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10162
10163 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10164 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10165 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10166 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10167 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10168 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10169 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10170 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10171 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10172 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10173 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10174 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10175 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10176 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10177 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10178 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10179 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10180 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10181 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10182 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10183 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10184 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10185 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10186 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10187 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10188 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10189 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10190 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10191 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10192 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10193 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10194 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10195 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10196 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10197 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10198 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10199
10200 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10201 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10202 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10203 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10204 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10205 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10206 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10207 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10208 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10209 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10210 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10211 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10212 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10213 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10214 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10215 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10216 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10217 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10218 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10219 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10220 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10221 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10222 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10223 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10224 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10225 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10226 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10227 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10228 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10229 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10230 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10231 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10232 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10233 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10234 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10235 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10236
10237 #undef VSX_LOGICAL
10238 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10239 GEN_XX3FORM(name, opc2, opc3, fl2)
10240
10241 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10242 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10243 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10244 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10245 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10246 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10247 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10248 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10249 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10250
10251 #define GEN_XXSEL_ROW(opc3) \
10252 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10253 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10254 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10255 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10256 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10257 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10258 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10259 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10260
10261 GEN_XXSEL_ROW(0x00)
10262 GEN_XXSEL_ROW(0x01)
10263 GEN_XXSEL_ROW(0x02)
10264 GEN_XXSEL_ROW(0x03)
10265 GEN_XXSEL_ROW(0x04)
10266 GEN_XXSEL_ROW(0x05)
10267 GEN_XXSEL_ROW(0x06)
10268 GEN_XXSEL_ROW(0x07)
10269 GEN_XXSEL_ROW(0x08)
10270 GEN_XXSEL_ROW(0x09)
10271 GEN_XXSEL_ROW(0x0A)
10272 GEN_XXSEL_ROW(0x0B)
10273 GEN_XXSEL_ROW(0x0C)
10274 GEN_XXSEL_ROW(0x0D)
10275 GEN_XXSEL_ROW(0x0E)
10276 GEN_XXSEL_ROW(0x0F)
10277 GEN_XXSEL_ROW(0x10)
10278 GEN_XXSEL_ROW(0x11)
10279 GEN_XXSEL_ROW(0x12)
10280 GEN_XXSEL_ROW(0x13)
10281 GEN_XXSEL_ROW(0x14)
10282 GEN_XXSEL_ROW(0x15)
10283 GEN_XXSEL_ROW(0x16)
10284 GEN_XXSEL_ROW(0x17)
10285 GEN_XXSEL_ROW(0x18)
10286 GEN_XXSEL_ROW(0x19)
10287 GEN_XXSEL_ROW(0x1A)
10288 GEN_XXSEL_ROW(0x1B)
10289 GEN_XXSEL_ROW(0x1C)
10290 GEN_XXSEL_ROW(0x1D)
10291 GEN_XXSEL_ROW(0x1E)
10292 GEN_XXSEL_ROW(0x1F)
10293
10294 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10295
10296 #undef GEN_SPE
10297 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
10298 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
10299 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10300 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10301 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10302 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10303 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10304 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10305 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10306 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
10307 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
10308 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10309 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10310 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10311 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10312 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10313 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10314 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
10315 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10316 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10317 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10318 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10319 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10320 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10321 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10322 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10323 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10324 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10325 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10326 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10327 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
10328
10329 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10330 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10331 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10332 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10333 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10334 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10335 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10336 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10337 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10338 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10339 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10340 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10341 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10342 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10343
10344 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10345 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10346 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10347 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10348 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10349 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
10350 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10351 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10352 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10353 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10354 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10355 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10356 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10357 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10358
10359 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
10360 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10361 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
10362 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10363 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
10364 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10365 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
10366 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
10367 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10368 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10369 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10370 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10371 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10372 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10373 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
10374 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10375
10376 #undef GEN_SPEOP_LDST
10377 #define GEN_SPEOP_LDST(name, opc2, sh) \
10378 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
10379 GEN_SPEOP_LDST(evldd, 0x00, 3),
10380 GEN_SPEOP_LDST(evldw, 0x01, 3),
10381 GEN_SPEOP_LDST(evldh, 0x02, 3),
10382 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
10383 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
10384 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
10385 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
10386 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
10387 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
10388 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
10389 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
10390
10391 GEN_SPEOP_LDST(evstdd, 0x10, 3),
10392 GEN_SPEOP_LDST(evstdw, 0x11, 3),
10393 GEN_SPEOP_LDST(evstdh, 0x12, 3),
10394 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
10395 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
10396 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
10397 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
10398 };
10399
10400 #include "helper_regs.h"
10401 #include "translate_init.c"
10402
10403 /*****************************************************************************/
10404 /* Misc PowerPC helpers */
10405 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
10406 int flags)
10407 {
10408 #define RGPL 4
10409 #define RFPL 4
10410
10411 PowerPCCPU *cpu = POWERPC_CPU(cs);
10412 CPUPPCState *env = &cpu->env;
10413 int i;
10414
10415 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
10416 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
10417 env->nip, env->lr, env->ctr, cpu_read_xer(env));
10418 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
10419 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
10420 env->hflags, env->mmu_idx);
10421 #if !defined(NO_TIMER_DUMP)
10422 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
10423 #if !defined(CONFIG_USER_ONLY)
10424 " DECR %08" PRIu32
10425 #endif
10426 "\n",
10427 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
10428 #if !defined(CONFIG_USER_ONLY)
10429 , cpu_ppc_load_decr(env)
10430 #endif
10431 );
10432 #endif
10433 for (i = 0; i < 32; i++) {
10434 if ((i & (RGPL - 1)) == 0)
10435 cpu_fprintf(f, "GPR%02d", i);
10436 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
10437 if ((i & (RGPL - 1)) == (RGPL - 1))
10438 cpu_fprintf(f, "\n");
10439 }
10440 cpu_fprintf(f, "CR ");
10441 for (i = 0; i < 8; i++)
10442 cpu_fprintf(f, "%01x", env->crf[i]);
10443 cpu_fprintf(f, " [");
10444 for (i = 0; i < 8; i++) {
10445 char a = '-';
10446 if (env->crf[i] & 0x08)
10447 a = 'L';
10448 else if (env->crf[i] & 0x04)
10449 a = 'G';
10450 else if (env->crf[i] & 0x02)
10451 a = 'E';
10452 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
10453 }
10454 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
10455 env->reserve_addr);
10456 for (i = 0; i < 32; i++) {
10457 if ((i & (RFPL - 1)) == 0)
10458 cpu_fprintf(f, "FPR%02d", i);
10459 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
10460 if ((i & (RFPL - 1)) == (RFPL - 1))
10461 cpu_fprintf(f, "\n");
10462 }
10463 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
10464 #if !defined(CONFIG_USER_ONLY)
10465 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
10466 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
10467 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
10468 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
10469
10470 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
10471 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
10472 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
10473 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
10474
10475 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
10476 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
10477 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
10478 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
10479
10480 if (env->excp_model == POWERPC_EXCP_BOOKE) {
10481 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
10482 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
10483 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
10484 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
10485
10486 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
10487 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
10488 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
10489 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
10490
10491 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
10492 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
10493 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
10494 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
10495
10496 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
10497 " EPR " TARGET_FMT_lx "\n",
10498 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
10499 env->spr[SPR_BOOKE_EPR]);
10500
10501 /* FSL-specific */
10502 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
10503 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
10504 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
10505 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
10506
10507 /*
10508 * IVORs are left out as they are large and do not change often --
10509 * they can be read with "p $ivor0", "p $ivor1", etc.
10510 */
10511 }
10512
10513 #if defined(TARGET_PPC64)
10514 if (env->flags & POWERPC_FLAG_CFAR) {
10515 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
10516 }
10517 #endif
10518
10519 switch (env->mmu_model) {
10520 case POWERPC_MMU_32B:
10521 case POWERPC_MMU_601:
10522 case POWERPC_MMU_SOFT_6xx:
10523 case POWERPC_MMU_SOFT_74xx:
10524 #if defined(TARGET_PPC64)
10525 case POWERPC_MMU_64B:
10526 case POWERPC_MMU_2_06:
10527 case POWERPC_MMU_2_06a:
10528 case POWERPC_MMU_2_06d:
10529 #endif
10530 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
10531 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
10532 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
10533 break;
10534 case POWERPC_MMU_BOOKE206:
10535 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
10536 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
10537 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
10538 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
10539
10540 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
10541 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
10542 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
10543 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
10544
10545 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
10546 " TLB1CFG " TARGET_FMT_lx "\n",
10547 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
10548 env->spr[SPR_BOOKE_TLB1CFG]);
10549 break;
10550 default:
10551 break;
10552 }
10553 #endif
10554
10555 #undef RGPL
10556 #undef RFPL
10557 }
10558
10559 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
10560 fprintf_function cpu_fprintf, int flags)
10561 {
10562 #if defined(DO_PPC_STATISTICS)
10563 PowerPCCPU *cpu = POWERPC_CPU(cs);
10564 opc_handler_t **t1, **t2, **t3, *handler;
10565 int op1, op2, op3;
10566
10567 t1 = cpu->env.opcodes;
10568 for (op1 = 0; op1 < 64; op1++) {
10569 handler = t1[op1];
10570 if (is_indirect_opcode(handler)) {
10571 t2 = ind_table(handler);
10572 for (op2 = 0; op2 < 32; op2++) {
10573 handler = t2[op2];
10574 if (is_indirect_opcode(handler)) {
10575 t3 = ind_table(handler);
10576 for (op3 = 0; op3 < 32; op3++) {
10577 handler = t3[op3];
10578 if (handler->count == 0)
10579 continue;
10580 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
10581 "%016" PRIx64 " %" PRId64 "\n",
10582 op1, op2, op3, op1, (op3 << 5) | op2,
10583 handler->oname,
10584 handler->count, handler->count);
10585 }
10586 } else {
10587 if (handler->count == 0)
10588 continue;
10589 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
10590 "%016" PRIx64 " %" PRId64 "\n",
10591 op1, op2, op1, op2, handler->oname,
10592 handler->count, handler->count);
10593 }
10594 }
10595 } else {
10596 if (handler->count == 0)
10597 continue;
10598 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
10599 " %" PRId64 "\n",
10600 op1, op1, handler->oname,
10601 handler->count, handler->count);
10602 }
10603 }
10604 #endif
10605 }
10606
10607 /*****************************************************************************/
10608 static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
10609 TranslationBlock *tb,
10610 bool search_pc)
10611 {
10612 CPUState *cs = CPU(cpu);
10613 CPUPPCState *env = &cpu->env;
10614 DisasContext ctx, *ctxp = &ctx;
10615 opc_handler_t **table, *handler;
10616 target_ulong pc_start;
10617 uint16_t *gen_opc_end;
10618 CPUBreakpoint *bp;
10619 int j, lj = -1;
10620 int num_insns;
10621 int max_insns;
10622
10623 pc_start = tb->pc;
10624 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
10625 ctx.nip = pc_start;
10626 ctx.tb = tb;
10627 ctx.exception = POWERPC_EXCP_NONE;
10628 ctx.spr_cb = env->spr_cb;
10629 ctx.mem_idx = env->mmu_idx;
10630 ctx.insns_flags = env->insns_flags;
10631 ctx.insns_flags2 = env->insns_flags2;
10632 ctx.access_type = -1;
10633 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
10634 #if defined(TARGET_PPC64)
10635 ctx.sf_mode = msr_is_64bit(env, env->msr);
10636 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
10637 #endif
10638 ctx.fpu_enabled = msr_fp;
10639 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
10640 ctx.spe_enabled = msr_spe;
10641 else
10642 ctx.spe_enabled = 0;
10643 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
10644 ctx.altivec_enabled = msr_vr;
10645 else
10646 ctx.altivec_enabled = 0;
10647 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
10648 ctx.vsx_enabled = msr_vsx;
10649 } else {
10650 ctx.vsx_enabled = 0;
10651 }
10652 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
10653 ctx.singlestep_enabled = CPU_SINGLE_STEP;
10654 else
10655 ctx.singlestep_enabled = 0;
10656 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
10657 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
10658 if (unlikely(cs->singlestep_enabled)) {
10659 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
10660 }
10661 #if defined (DO_SINGLE_STEP) && 0
10662 /* Single step trace mode */
10663 msr_se = 1;
10664 #endif
10665 num_insns = 0;
10666 max_insns = tb->cflags & CF_COUNT_MASK;
10667 if (max_insns == 0)
10668 max_insns = CF_COUNT_MASK;
10669
10670 gen_tb_start();
10671 /* Set env in case of segfault during code fetch */
10672 while (ctx.exception == POWERPC_EXCP_NONE
10673 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
10674 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
10675 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
10676 if (bp->pc == ctx.nip) {
10677 gen_debug_exception(ctxp);
10678 break;
10679 }
10680 }
10681 }
10682 if (unlikely(search_pc)) {
10683 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
10684 if (lj < j) {
10685 lj++;
10686 while (lj < j)
10687 tcg_ctx.gen_opc_instr_start[lj++] = 0;
10688 }
10689 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
10690 tcg_ctx.gen_opc_instr_start[lj] = 1;
10691 tcg_ctx.gen_opc_icount[lj] = num_insns;
10692 }
10693 LOG_DISAS("----------------\n");
10694 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
10695 ctx.nip, ctx.mem_idx, (int)msr_ir);
10696 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
10697 gen_io_start();
10698 if (unlikely(ctx.le_mode)) {
10699 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
10700 } else {
10701 ctx.opcode = cpu_ldl_code(env, ctx.nip);
10702 }
10703 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
10704 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
10705 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
10706 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
10707 tcg_gen_debug_insn_start(ctx.nip);
10708 }
10709 ctx.nip += 4;
10710 table = env->opcodes;
10711 num_insns++;
10712 handler = table[opc1(ctx.opcode)];
10713 if (is_indirect_opcode(handler)) {
10714 table = ind_table(handler);
10715 handler = table[opc2(ctx.opcode)];
10716 if (is_indirect_opcode(handler)) {
10717 table = ind_table(handler);
10718 handler = table[opc3(ctx.opcode)];
10719 }
10720 }
10721 /* Is opcode *REALLY* valid ? */
10722 if (unlikely(handler->handler == &gen_invalid)) {
10723 if (qemu_log_enabled()) {
10724 qemu_log("invalid/unsupported opcode: "
10725 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
10726 opc1(ctx.opcode), opc2(ctx.opcode),
10727 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
10728 }
10729 } else {
10730 uint32_t inval;
10731
10732 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
10733 inval = handler->inval2;
10734 } else {
10735 inval = handler->inval1;
10736 }
10737
10738 if (unlikely((ctx.opcode & inval) != 0)) {
10739 if (qemu_log_enabled()) {
10740 qemu_log("invalid bits: %08x for opcode: "
10741 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
10742 ctx.opcode & inval, opc1(ctx.opcode),
10743 opc2(ctx.opcode), opc3(ctx.opcode),
10744 ctx.opcode, ctx.nip - 4);
10745 }
10746 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
10747 break;
10748 }
10749 }
10750 (*(handler->handler))(&ctx);
10751 #if defined(DO_PPC_STATISTICS)
10752 handler->count++;
10753 #endif
10754 /* Check trace mode exceptions */
10755 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
10756 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
10757 ctx.exception != POWERPC_SYSCALL &&
10758 ctx.exception != POWERPC_EXCP_TRAP &&
10759 ctx.exception != POWERPC_EXCP_BRANCH)) {
10760 gen_exception(ctxp, POWERPC_EXCP_TRACE);
10761 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
10762 (cs->singlestep_enabled) ||
10763 singlestep ||
10764 num_insns >= max_insns)) {
10765 /* if we reach a page boundary or are single stepping, stop
10766 * generation
10767 */
10768 break;
10769 }
10770 }
10771 if (tb->cflags & CF_LAST_IO)
10772 gen_io_end();
10773 if (ctx.exception == POWERPC_EXCP_NONE) {
10774 gen_goto_tb(&ctx, 0, ctx.nip);
10775 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
10776 if (unlikely(cs->singlestep_enabled)) {
10777 gen_debug_exception(ctxp);
10778 }
10779 /* Generate the return instruction */
10780 tcg_gen_exit_tb(0);
10781 }
10782 gen_tb_end(tb, num_insns);
10783 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
10784 if (unlikely(search_pc)) {
10785 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
10786 lj++;
10787 while (lj <= j)
10788 tcg_ctx.gen_opc_instr_start[lj++] = 0;
10789 } else {
10790 tb->size = ctx.nip - pc_start;
10791 tb->icount = num_insns;
10792 }
10793 #if defined(DEBUG_DISAS)
10794 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
10795 int flags;
10796 flags = env->bfd_mach;
10797 flags |= ctx.le_mode << 16;
10798 qemu_log("IN: %s\n", lookup_symbol(pc_start));
10799 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
10800 qemu_log("\n");
10801 }
10802 #endif
10803 }
10804
10805 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
10806 {
10807 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false);
10808 }
10809
10810 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
10811 {
10812 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true);
10813 }
10814
10815 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
10816 {
10817 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
10818 }
QEMU mirror