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[qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
26 #include "dis-asm.h"
27 #include "gdbstub.h"
28 #include <kvm.h>
29 #include "kvm_ppc.h"
30 #include "arch_init.h"
31
32 //#define PPC_DUMP_CPU
33 //#define PPC_DEBUG_SPR
34 //#define PPC_DUMP_SPR_ACCESSES
35 #if defined(CONFIG_USER_ONLY)
36 #define TODO_USER_ONLY 1
37 #endif
38
39 /* For user-mode emulation, we don't emulate any IRQ controller */
40 #if defined(CONFIG_USER_ONLY)
41 #define PPC_IRQ_INIT_FN(name) \
42 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
43 { \
44 }
45 #else
46 #define PPC_IRQ_INIT_FN(name) \
47 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
48 #endif
49
50 PPC_IRQ_INIT_FN(40x);
51 PPC_IRQ_INIT_FN(6xx);
52 PPC_IRQ_INIT_FN(970);
53 PPC_IRQ_INIT_FN(POWER7);
54 PPC_IRQ_INIT_FN(e500);
55
56 /* Generic callbacks:
57 * do nothing but store/retrieve spr value
58 */
59 static void spr_load_dump_spr(int sprn)
60 {
61 #ifdef PPC_DUMP_SPR_ACCESSES
62 TCGv_i32 t0 = tcg_const_i32(sprn);
63 gen_helper_load_dump_spr(t0);
64 tcg_temp_free_i32(t0);
65 #endif
66 }
67
68 static void spr_read_generic (void *opaque, int gprn, int sprn)
69 {
70 gen_load_spr(cpu_gpr[gprn], sprn);
71 spr_load_dump_spr(sprn);
72 }
73
74 static void spr_store_dump_spr(int sprn)
75 {
76 #ifdef PPC_DUMP_SPR_ACCESSES
77 TCGv_i32 t0 = tcg_const_i32(sprn);
78 gen_helper_store_dump_spr(t0);
79 tcg_temp_free_i32(t0);
80 #endif
81 }
82
83 static void spr_write_generic (void *opaque, int sprn, int gprn)
84 {
85 gen_store_spr(sprn, cpu_gpr[gprn]);
86 spr_store_dump_spr(sprn);
87 }
88
89 #if !defined(CONFIG_USER_ONLY)
90 static void spr_write_generic32(void *opaque, int sprn, int gprn)
91 {
92 #ifdef TARGET_PPC64
93 TCGv t0 = tcg_temp_new();
94 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
95 gen_store_spr(sprn, t0);
96 tcg_temp_free(t0);
97 spr_store_dump_spr(sprn);
98 #else
99 spr_write_generic(opaque, sprn, gprn);
100 #endif
101 }
102
103 static void spr_write_clear (void *opaque, int sprn, int gprn)
104 {
105 TCGv t0 = tcg_temp_new();
106 TCGv t1 = tcg_temp_new();
107 gen_load_spr(t0, sprn);
108 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
109 tcg_gen_and_tl(t0, t0, t1);
110 gen_store_spr(sprn, t0);
111 tcg_temp_free(t0);
112 tcg_temp_free(t1);
113 }
114 #endif
115
116 /* SPR common to all PowerPC */
117 /* XER */
118 static void spr_read_xer (void *opaque, int gprn, int sprn)
119 {
120 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
121 }
122
123 static void spr_write_xer (void *opaque, int sprn, int gprn)
124 {
125 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
126 }
127
128 /* LR */
129 static void spr_read_lr (void *opaque, int gprn, int sprn)
130 {
131 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
132 }
133
134 static void spr_write_lr (void *opaque, int sprn, int gprn)
135 {
136 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
137 }
138
139 /* CFAR */
140 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
141 static void spr_read_cfar (void *opaque, int gprn, int sprn)
142 {
143 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
144 }
145
146 static void spr_write_cfar (void *opaque, int sprn, int gprn)
147 {
148 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
149 }
150 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
151
152 /* CTR */
153 static void spr_read_ctr (void *opaque, int gprn, int sprn)
154 {
155 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
156 }
157
158 static void spr_write_ctr (void *opaque, int sprn, int gprn)
159 {
160 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
161 }
162
163 /* User read access to SPR */
164 /* USPRx */
165 /* UMMCRx */
166 /* UPMCx */
167 /* USIA */
168 /* UDECR */
169 static void spr_read_ureg (void *opaque, int gprn, int sprn)
170 {
171 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
172 }
173
174 /* SPR common to all non-embedded PowerPC */
175 /* DECR */
176 #if !defined(CONFIG_USER_ONLY)
177 static void spr_read_decr (void *opaque, int gprn, int sprn)
178 {
179 if (use_icount) {
180 gen_io_start();
181 }
182 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
183 if (use_icount) {
184 gen_io_end();
185 gen_stop_exception(opaque);
186 }
187 }
188
189 static void spr_write_decr (void *opaque, int sprn, int gprn)
190 {
191 if (use_icount) {
192 gen_io_start();
193 }
194 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
195 if (use_icount) {
196 gen_io_end();
197 gen_stop_exception(opaque);
198 }
199 }
200 #endif
201
202 /* SPR common to all non-embedded PowerPC, except 601 */
203 /* Time base */
204 static void spr_read_tbl (void *opaque, int gprn, int sprn)
205 {
206 if (use_icount) {
207 gen_io_start();
208 }
209 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
210 if (use_icount) {
211 gen_io_end();
212 gen_stop_exception(opaque);
213 }
214 }
215
216 static void spr_read_tbu (void *opaque, int gprn, int sprn)
217 {
218 if (use_icount) {
219 gen_io_start();
220 }
221 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
222 if (use_icount) {
223 gen_io_end();
224 gen_stop_exception(opaque);
225 }
226 }
227
228 __attribute__ (( unused ))
229 static void spr_read_atbl (void *opaque, int gprn, int sprn)
230 {
231 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
232 }
233
234 __attribute__ (( unused ))
235 static void spr_read_atbu (void *opaque, int gprn, int sprn)
236 {
237 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
238 }
239
240 #if !defined(CONFIG_USER_ONLY)
241 static void spr_write_tbl (void *opaque, int sprn, int gprn)
242 {
243 if (use_icount) {
244 gen_io_start();
245 }
246 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
247 if (use_icount) {
248 gen_io_end();
249 gen_stop_exception(opaque);
250 }
251 }
252
253 static void spr_write_tbu (void *opaque, int sprn, int gprn)
254 {
255 if (use_icount) {
256 gen_io_start();
257 }
258 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
259 if (use_icount) {
260 gen_io_end();
261 gen_stop_exception(opaque);
262 }
263 }
264
265 __attribute__ (( unused ))
266 static void spr_write_atbl (void *opaque, int sprn, int gprn)
267 {
268 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
269 }
270
271 __attribute__ (( unused ))
272 static void spr_write_atbu (void *opaque, int sprn, int gprn)
273 {
274 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
275 }
276
277 #if defined(TARGET_PPC64)
278 __attribute__ (( unused ))
279 static void spr_read_purr (void *opaque, int gprn, int sprn)
280 {
281 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
282 }
283 #endif
284 #endif
285
286 #if !defined(CONFIG_USER_ONLY)
287 /* IBAT0U...IBAT0U */
288 /* IBAT0L...IBAT7L */
289 static void spr_read_ibat (void *opaque, int gprn, int sprn)
290 {
291 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
292 }
293
294 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
295 {
296 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
297 }
298
299 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
300 {
301 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
302 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
303 tcg_temp_free_i32(t0);
304 }
305
306 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
307 {
308 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
309 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
310 tcg_temp_free_i32(t0);
311 }
312
313 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
314 {
315 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
316 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
317 tcg_temp_free_i32(t0);
318 }
319
320 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
321 {
322 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
323 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
324 tcg_temp_free_i32(t0);
325 }
326
327 /* DBAT0U...DBAT7U */
328 /* DBAT0L...DBAT7L */
329 static void spr_read_dbat (void *opaque, int gprn, int sprn)
330 {
331 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
332 }
333
334 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
335 {
336 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
337 }
338
339 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
340 {
341 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
342 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
343 tcg_temp_free_i32(t0);
344 }
345
346 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
347 {
348 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
349 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
350 tcg_temp_free_i32(t0);
351 }
352
353 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
354 {
355 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
356 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
357 tcg_temp_free_i32(t0);
358 }
359
360 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
361 {
362 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
363 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
364 tcg_temp_free_i32(t0);
365 }
366
367 /* SDR1 */
368 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
369 {
370 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
371 }
372
373 /* 64 bits PowerPC specific SPRs */
374 /* ASR */
375 #if defined(TARGET_PPC64)
376 static void spr_read_hior (void *opaque, int gprn, int sprn)
377 {
378 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
379 }
380
381 static void spr_write_hior (void *opaque, int sprn, int gprn)
382 {
383 TCGv t0 = tcg_temp_new();
384 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
385 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
386 tcg_temp_free(t0);
387 }
388
389 static void spr_read_asr (void *opaque, int gprn, int sprn)
390 {
391 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, asr));
392 }
393
394 static void spr_write_asr (void *opaque, int sprn, int gprn)
395 {
396 gen_helper_store_asr(cpu_env, cpu_gpr[gprn]);
397 }
398 #endif
399 #endif
400
401 /* PowerPC 601 specific registers */
402 /* RTC */
403 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
404 {
405 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
406 }
407
408 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
409 {
410 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
411 }
412
413 #if !defined(CONFIG_USER_ONLY)
414 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
415 {
416 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
417 }
418
419 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
420 {
421 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
422 }
423
424 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
425 {
426 DisasContext *ctx = opaque;
427
428 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
429 /* Must stop the translation as endianness may have changed */
430 gen_stop_exception(ctx);
431 }
432 #endif
433
434 /* Unified bats */
435 #if !defined(CONFIG_USER_ONLY)
436 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
437 {
438 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
439 }
440
441 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
442 {
443 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
444 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
445 tcg_temp_free_i32(t0);
446 }
447
448 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
449 {
450 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
451 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
452 tcg_temp_free_i32(t0);
453 }
454 #endif
455
456 /* PowerPC 40x specific registers */
457 #if !defined(CONFIG_USER_ONLY)
458 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
459 {
460 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
461 }
462
463 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
464 {
465 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
466 }
467
468 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
469 {
470 DisasContext *ctx = opaque;
471
472 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
473 /* We must stop translation as we may have rebooted */
474 gen_stop_exception(ctx);
475 }
476
477 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
478 {
479 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
480 }
481
482 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
483 {
484 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
485 }
486
487 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
488 {
489 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
490 }
491 #endif
492
493 /* PowerPC 403 specific registers */
494 /* PBL1 / PBU1 / PBL2 / PBU2 */
495 #if !defined(CONFIG_USER_ONLY)
496 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
497 {
498 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
499 }
500
501 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
502 {
503 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
504 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
505 tcg_temp_free_i32(t0);
506 }
507
508 static void spr_write_pir (void *opaque, int sprn, int gprn)
509 {
510 TCGv t0 = tcg_temp_new();
511 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
512 gen_store_spr(SPR_PIR, t0);
513 tcg_temp_free(t0);
514 }
515 #endif
516
517 /* SPE specific registers */
518 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
519 {
520 TCGv_i32 t0 = tcg_temp_new_i32();
521 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
522 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
523 tcg_temp_free_i32(t0);
524 }
525
526 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
527 {
528 TCGv_i32 t0 = tcg_temp_new_i32();
529 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
530 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
531 tcg_temp_free_i32(t0);
532 }
533
534 #if !defined(CONFIG_USER_ONLY)
535 /* Callback used to write the exception vector base */
536 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
537 {
538 TCGv t0 = tcg_temp_new();
539 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
540 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
541 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
542 gen_store_spr(sprn, t0);
543 tcg_temp_free(t0);
544 }
545
546 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
547 {
548 DisasContext *ctx = opaque;
549 int sprn_offs;
550
551 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
552 sprn_offs = sprn - SPR_BOOKE_IVOR0;
553 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
554 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
555 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
556 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
557 } else {
558 printf("Trying to write an unknown exception vector %d %03x\n",
559 sprn, sprn);
560 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
561 return;
562 }
563
564 TCGv t0 = tcg_temp_new();
565 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
566 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
567 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
568 gen_store_spr(sprn, t0);
569 tcg_temp_free(t0);
570 }
571 #endif
572
573 static inline void vscr_init (CPUPPCState *env, uint32_t val)
574 {
575 env->vscr = val;
576 /* Altivec always uses round-to-nearest */
577 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
578 set_flush_to_zero(vscr_nj, &env->vec_status);
579 }
580
581 #if defined(CONFIG_USER_ONLY)
582 #define spr_register(env, num, name, uea_read, uea_write, \
583 oea_read, oea_write, initial_value) \
584 do { \
585 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
586 } while (0)
587 static inline void _spr_register (CPUPPCState *env, int num,
588 const char *name,
589 void (*uea_read)(void *opaque, int gprn, int sprn),
590 void (*uea_write)(void *opaque, int sprn, int gprn),
591 target_ulong initial_value)
592 #else
593 static inline void spr_register (CPUPPCState *env, int num,
594 const char *name,
595 void (*uea_read)(void *opaque, int gprn, int sprn),
596 void (*uea_write)(void *opaque, int sprn, int gprn),
597 void (*oea_read)(void *opaque, int gprn, int sprn),
598 void (*oea_write)(void *opaque, int sprn, int gprn),
599 target_ulong initial_value)
600 #endif
601 {
602 ppc_spr_t *spr;
603
604 spr = &env->spr_cb[num];
605 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
606 #if !defined(CONFIG_USER_ONLY)
607 spr->oea_read != NULL || spr->oea_write != NULL ||
608 #endif
609 spr->uea_read != NULL || spr->uea_write != NULL) {
610 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
611 exit(1);
612 }
613 #if defined(PPC_DEBUG_SPR)
614 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
615 name, initial_value);
616 #endif
617 spr->name = name;
618 spr->uea_read = uea_read;
619 spr->uea_write = uea_write;
620 #if !defined(CONFIG_USER_ONLY)
621 spr->oea_read = oea_read;
622 spr->oea_write = oea_write;
623 #endif
624 env->spr[num] = initial_value;
625 }
626
627 /* Generic PowerPC SPRs */
628 static void gen_spr_generic (CPUPPCState *env)
629 {
630 /* Integer processing */
631 spr_register(env, SPR_XER, "XER",
632 &spr_read_xer, &spr_write_xer,
633 &spr_read_xer, &spr_write_xer,
634 0x00000000);
635 /* Branch contol */
636 spr_register(env, SPR_LR, "LR",
637 &spr_read_lr, &spr_write_lr,
638 &spr_read_lr, &spr_write_lr,
639 0x00000000);
640 spr_register(env, SPR_CTR, "CTR",
641 &spr_read_ctr, &spr_write_ctr,
642 &spr_read_ctr, &spr_write_ctr,
643 0x00000000);
644 /* Interrupt processing */
645 spr_register(env, SPR_SRR0, "SRR0",
646 SPR_NOACCESS, SPR_NOACCESS,
647 &spr_read_generic, &spr_write_generic,
648 0x00000000);
649 spr_register(env, SPR_SRR1, "SRR1",
650 SPR_NOACCESS, SPR_NOACCESS,
651 &spr_read_generic, &spr_write_generic,
652 0x00000000);
653 /* Processor control */
654 spr_register(env, SPR_SPRG0, "SPRG0",
655 SPR_NOACCESS, SPR_NOACCESS,
656 &spr_read_generic, &spr_write_generic,
657 0x00000000);
658 spr_register(env, SPR_SPRG1, "SPRG1",
659 SPR_NOACCESS, SPR_NOACCESS,
660 &spr_read_generic, &spr_write_generic,
661 0x00000000);
662 spr_register(env, SPR_SPRG2, "SPRG2",
663 SPR_NOACCESS, SPR_NOACCESS,
664 &spr_read_generic, &spr_write_generic,
665 0x00000000);
666 spr_register(env, SPR_SPRG3, "SPRG3",
667 SPR_NOACCESS, SPR_NOACCESS,
668 &spr_read_generic, &spr_write_generic,
669 0x00000000);
670 }
671
672 /* SPR common to all non-embedded PowerPC, including 601 */
673 static void gen_spr_ne_601 (CPUPPCState *env)
674 {
675 /* Exception processing */
676 spr_register(env, SPR_DSISR, "DSISR",
677 SPR_NOACCESS, SPR_NOACCESS,
678 &spr_read_generic, &spr_write_generic,
679 0x00000000);
680 spr_register(env, SPR_DAR, "DAR",
681 SPR_NOACCESS, SPR_NOACCESS,
682 &spr_read_generic, &spr_write_generic,
683 0x00000000);
684 /* Timer */
685 spr_register(env, SPR_DECR, "DECR",
686 SPR_NOACCESS, SPR_NOACCESS,
687 &spr_read_decr, &spr_write_decr,
688 0x00000000);
689 /* Memory management */
690 spr_register(env, SPR_SDR1, "SDR1",
691 SPR_NOACCESS, SPR_NOACCESS,
692 &spr_read_generic, &spr_write_sdr1,
693 0x00000000);
694 }
695
696 /* BATs 0-3 */
697 static void gen_low_BATs (CPUPPCState *env)
698 {
699 #if !defined(CONFIG_USER_ONLY)
700 spr_register(env, SPR_IBAT0U, "IBAT0U",
701 SPR_NOACCESS, SPR_NOACCESS,
702 &spr_read_ibat, &spr_write_ibatu,
703 0x00000000);
704 spr_register(env, SPR_IBAT0L, "IBAT0L",
705 SPR_NOACCESS, SPR_NOACCESS,
706 &spr_read_ibat, &spr_write_ibatl,
707 0x00000000);
708 spr_register(env, SPR_IBAT1U, "IBAT1U",
709 SPR_NOACCESS, SPR_NOACCESS,
710 &spr_read_ibat, &spr_write_ibatu,
711 0x00000000);
712 spr_register(env, SPR_IBAT1L, "IBAT1L",
713 SPR_NOACCESS, SPR_NOACCESS,
714 &spr_read_ibat, &spr_write_ibatl,
715 0x00000000);
716 spr_register(env, SPR_IBAT2U, "IBAT2U",
717 SPR_NOACCESS, SPR_NOACCESS,
718 &spr_read_ibat, &spr_write_ibatu,
719 0x00000000);
720 spr_register(env, SPR_IBAT2L, "IBAT2L",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_ibat, &spr_write_ibatl,
723 0x00000000);
724 spr_register(env, SPR_IBAT3U, "IBAT3U",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_ibat, &spr_write_ibatu,
727 0x00000000);
728 spr_register(env, SPR_IBAT3L, "IBAT3L",
729 SPR_NOACCESS, SPR_NOACCESS,
730 &spr_read_ibat, &spr_write_ibatl,
731 0x00000000);
732 spr_register(env, SPR_DBAT0U, "DBAT0U",
733 SPR_NOACCESS, SPR_NOACCESS,
734 &spr_read_dbat, &spr_write_dbatu,
735 0x00000000);
736 spr_register(env, SPR_DBAT0L, "DBAT0L",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_dbat, &spr_write_dbatl,
739 0x00000000);
740 spr_register(env, SPR_DBAT1U, "DBAT1U",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_dbat, &spr_write_dbatu,
743 0x00000000);
744 spr_register(env, SPR_DBAT1L, "DBAT1L",
745 SPR_NOACCESS, SPR_NOACCESS,
746 &spr_read_dbat, &spr_write_dbatl,
747 0x00000000);
748 spr_register(env, SPR_DBAT2U, "DBAT2U",
749 SPR_NOACCESS, SPR_NOACCESS,
750 &spr_read_dbat, &spr_write_dbatu,
751 0x00000000);
752 spr_register(env, SPR_DBAT2L, "DBAT2L",
753 SPR_NOACCESS, SPR_NOACCESS,
754 &spr_read_dbat, &spr_write_dbatl,
755 0x00000000);
756 spr_register(env, SPR_DBAT3U, "DBAT3U",
757 SPR_NOACCESS, SPR_NOACCESS,
758 &spr_read_dbat, &spr_write_dbatu,
759 0x00000000);
760 spr_register(env, SPR_DBAT3L, "DBAT3L",
761 SPR_NOACCESS, SPR_NOACCESS,
762 &spr_read_dbat, &spr_write_dbatl,
763 0x00000000);
764 env->nb_BATs += 4;
765 #endif
766 }
767
768 /* BATs 4-7 */
769 static void gen_high_BATs (CPUPPCState *env)
770 {
771 #if !defined(CONFIG_USER_ONLY)
772 spr_register(env, SPR_IBAT4U, "IBAT4U",
773 SPR_NOACCESS, SPR_NOACCESS,
774 &spr_read_ibat_h, &spr_write_ibatu_h,
775 0x00000000);
776 spr_register(env, SPR_IBAT4L, "IBAT4L",
777 SPR_NOACCESS, SPR_NOACCESS,
778 &spr_read_ibat_h, &spr_write_ibatl_h,
779 0x00000000);
780 spr_register(env, SPR_IBAT5U, "IBAT5U",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_ibat_h, &spr_write_ibatu_h,
783 0x00000000);
784 spr_register(env, SPR_IBAT5L, "IBAT5L",
785 SPR_NOACCESS, SPR_NOACCESS,
786 &spr_read_ibat_h, &spr_write_ibatl_h,
787 0x00000000);
788 spr_register(env, SPR_IBAT6U, "IBAT6U",
789 SPR_NOACCESS, SPR_NOACCESS,
790 &spr_read_ibat_h, &spr_write_ibatu_h,
791 0x00000000);
792 spr_register(env, SPR_IBAT6L, "IBAT6L",
793 SPR_NOACCESS, SPR_NOACCESS,
794 &spr_read_ibat_h, &spr_write_ibatl_h,
795 0x00000000);
796 spr_register(env, SPR_IBAT7U, "IBAT7U",
797 SPR_NOACCESS, SPR_NOACCESS,
798 &spr_read_ibat_h, &spr_write_ibatu_h,
799 0x00000000);
800 spr_register(env, SPR_IBAT7L, "IBAT7L",
801 SPR_NOACCESS, SPR_NOACCESS,
802 &spr_read_ibat_h, &spr_write_ibatl_h,
803 0x00000000);
804 spr_register(env, SPR_DBAT4U, "DBAT4U",
805 SPR_NOACCESS, SPR_NOACCESS,
806 &spr_read_dbat_h, &spr_write_dbatu_h,
807 0x00000000);
808 spr_register(env, SPR_DBAT4L, "DBAT4L",
809 SPR_NOACCESS, SPR_NOACCESS,
810 &spr_read_dbat_h, &spr_write_dbatl_h,
811 0x00000000);
812 spr_register(env, SPR_DBAT5U, "DBAT5U",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_dbat_h, &spr_write_dbatu_h,
815 0x00000000);
816 spr_register(env, SPR_DBAT5L, "DBAT5L",
817 SPR_NOACCESS, SPR_NOACCESS,
818 &spr_read_dbat_h, &spr_write_dbatl_h,
819 0x00000000);
820 spr_register(env, SPR_DBAT6U, "DBAT6U",
821 SPR_NOACCESS, SPR_NOACCESS,
822 &spr_read_dbat_h, &spr_write_dbatu_h,
823 0x00000000);
824 spr_register(env, SPR_DBAT6L, "DBAT6L",
825 SPR_NOACCESS, SPR_NOACCESS,
826 &spr_read_dbat_h, &spr_write_dbatl_h,
827 0x00000000);
828 spr_register(env, SPR_DBAT7U, "DBAT7U",
829 SPR_NOACCESS, SPR_NOACCESS,
830 &spr_read_dbat_h, &spr_write_dbatu_h,
831 0x00000000);
832 spr_register(env, SPR_DBAT7L, "DBAT7L",
833 SPR_NOACCESS, SPR_NOACCESS,
834 &spr_read_dbat_h, &spr_write_dbatl_h,
835 0x00000000);
836 env->nb_BATs += 4;
837 #endif
838 }
839
840 /* Generic PowerPC time base */
841 static void gen_tbl (CPUPPCState *env)
842 {
843 spr_register(env, SPR_VTBL, "TBL",
844 &spr_read_tbl, SPR_NOACCESS,
845 &spr_read_tbl, SPR_NOACCESS,
846 0x00000000);
847 spr_register(env, SPR_TBL, "TBL",
848 &spr_read_tbl, SPR_NOACCESS,
849 &spr_read_tbl, &spr_write_tbl,
850 0x00000000);
851 spr_register(env, SPR_VTBU, "TBU",
852 &spr_read_tbu, SPR_NOACCESS,
853 &spr_read_tbu, SPR_NOACCESS,
854 0x00000000);
855 spr_register(env, SPR_TBU, "TBU",
856 &spr_read_tbu, SPR_NOACCESS,
857 &spr_read_tbu, &spr_write_tbu,
858 0x00000000);
859 }
860
861 /* Softare table search registers */
862 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
863 {
864 #if !defined(CONFIG_USER_ONLY)
865 env->nb_tlb = nb_tlbs;
866 env->nb_ways = nb_ways;
867 env->id_tlbs = 1;
868 env->tlb_type = TLB_6XX;
869 spr_register(env, SPR_DMISS, "DMISS",
870 SPR_NOACCESS, SPR_NOACCESS,
871 &spr_read_generic, SPR_NOACCESS,
872 0x00000000);
873 spr_register(env, SPR_DCMP, "DCMP",
874 SPR_NOACCESS, SPR_NOACCESS,
875 &spr_read_generic, SPR_NOACCESS,
876 0x00000000);
877 spr_register(env, SPR_HASH1, "HASH1",
878 SPR_NOACCESS, SPR_NOACCESS,
879 &spr_read_generic, SPR_NOACCESS,
880 0x00000000);
881 spr_register(env, SPR_HASH2, "HASH2",
882 SPR_NOACCESS, SPR_NOACCESS,
883 &spr_read_generic, SPR_NOACCESS,
884 0x00000000);
885 spr_register(env, SPR_IMISS, "IMISS",
886 SPR_NOACCESS, SPR_NOACCESS,
887 &spr_read_generic, SPR_NOACCESS,
888 0x00000000);
889 spr_register(env, SPR_ICMP, "ICMP",
890 SPR_NOACCESS, SPR_NOACCESS,
891 &spr_read_generic, SPR_NOACCESS,
892 0x00000000);
893 spr_register(env, SPR_RPA, "RPA",
894 SPR_NOACCESS, SPR_NOACCESS,
895 &spr_read_generic, &spr_write_generic,
896 0x00000000);
897 #endif
898 }
899
900 /* SPR common to MPC755 and G2 */
901 static void gen_spr_G2_755 (CPUPPCState *env)
902 {
903 /* SGPRs */
904 spr_register(env, SPR_SPRG4, "SPRG4",
905 SPR_NOACCESS, SPR_NOACCESS,
906 &spr_read_generic, &spr_write_generic,
907 0x00000000);
908 spr_register(env, SPR_SPRG5, "SPRG5",
909 SPR_NOACCESS, SPR_NOACCESS,
910 &spr_read_generic, &spr_write_generic,
911 0x00000000);
912 spr_register(env, SPR_SPRG6, "SPRG6",
913 SPR_NOACCESS, SPR_NOACCESS,
914 &spr_read_generic, &spr_write_generic,
915 0x00000000);
916 spr_register(env, SPR_SPRG7, "SPRG7",
917 SPR_NOACCESS, SPR_NOACCESS,
918 &spr_read_generic, &spr_write_generic,
919 0x00000000);
920 }
921
922 /* SPR common to all 7xx PowerPC implementations */
923 static void gen_spr_7xx (CPUPPCState *env)
924 {
925 /* Breakpoints */
926 /* XXX : not implemented */
927 spr_register(env, SPR_DABR, "DABR",
928 SPR_NOACCESS, SPR_NOACCESS,
929 &spr_read_generic, &spr_write_generic,
930 0x00000000);
931 /* XXX : not implemented */
932 spr_register(env, SPR_IABR, "IABR",
933 SPR_NOACCESS, SPR_NOACCESS,
934 &spr_read_generic, &spr_write_generic,
935 0x00000000);
936 /* Cache management */
937 /* XXX : not implemented */
938 spr_register(env, SPR_ICTC, "ICTC",
939 SPR_NOACCESS, SPR_NOACCESS,
940 &spr_read_generic, &spr_write_generic,
941 0x00000000);
942 /* Performance monitors */
943 /* XXX : not implemented */
944 spr_register(env, SPR_MMCR0, "MMCR0",
945 SPR_NOACCESS, SPR_NOACCESS,
946 &spr_read_generic, &spr_write_generic,
947 0x00000000);
948 /* XXX : not implemented */
949 spr_register(env, SPR_MMCR1, "MMCR1",
950 SPR_NOACCESS, SPR_NOACCESS,
951 &spr_read_generic, &spr_write_generic,
952 0x00000000);
953 /* XXX : not implemented */
954 spr_register(env, SPR_PMC1, "PMC1",
955 SPR_NOACCESS, SPR_NOACCESS,
956 &spr_read_generic, &spr_write_generic,
957 0x00000000);
958 /* XXX : not implemented */
959 spr_register(env, SPR_PMC2, "PMC2",
960 SPR_NOACCESS, SPR_NOACCESS,
961 &spr_read_generic, &spr_write_generic,
962 0x00000000);
963 /* XXX : not implemented */
964 spr_register(env, SPR_PMC3, "PMC3",
965 SPR_NOACCESS, SPR_NOACCESS,
966 &spr_read_generic, &spr_write_generic,
967 0x00000000);
968 /* XXX : not implemented */
969 spr_register(env, SPR_PMC4, "PMC4",
970 SPR_NOACCESS, SPR_NOACCESS,
971 &spr_read_generic, &spr_write_generic,
972 0x00000000);
973 /* XXX : not implemented */
974 spr_register(env, SPR_SIAR, "SIAR",
975 SPR_NOACCESS, SPR_NOACCESS,
976 &spr_read_generic, SPR_NOACCESS,
977 0x00000000);
978 /* XXX : not implemented */
979 spr_register(env, SPR_UMMCR0, "UMMCR0",
980 &spr_read_ureg, SPR_NOACCESS,
981 &spr_read_ureg, SPR_NOACCESS,
982 0x00000000);
983 /* XXX : not implemented */
984 spr_register(env, SPR_UMMCR1, "UMMCR1",
985 &spr_read_ureg, SPR_NOACCESS,
986 &spr_read_ureg, SPR_NOACCESS,
987 0x00000000);
988 /* XXX : not implemented */
989 spr_register(env, SPR_UPMC1, "UPMC1",
990 &spr_read_ureg, SPR_NOACCESS,
991 &spr_read_ureg, SPR_NOACCESS,
992 0x00000000);
993 /* XXX : not implemented */
994 spr_register(env, SPR_UPMC2, "UPMC2",
995 &spr_read_ureg, SPR_NOACCESS,
996 &spr_read_ureg, SPR_NOACCESS,
997 0x00000000);
998 /* XXX : not implemented */
999 spr_register(env, SPR_UPMC3, "UPMC3",
1000 &spr_read_ureg, SPR_NOACCESS,
1001 &spr_read_ureg, SPR_NOACCESS,
1002 0x00000000);
1003 /* XXX : not implemented */
1004 spr_register(env, SPR_UPMC4, "UPMC4",
1005 &spr_read_ureg, SPR_NOACCESS,
1006 &spr_read_ureg, SPR_NOACCESS,
1007 0x00000000);
1008 /* XXX : not implemented */
1009 spr_register(env, SPR_USIAR, "USIAR",
1010 &spr_read_ureg, SPR_NOACCESS,
1011 &spr_read_ureg, SPR_NOACCESS,
1012 0x00000000);
1013 /* External access control */
1014 /* XXX : not implemented */
1015 spr_register(env, SPR_EAR, "EAR",
1016 SPR_NOACCESS, SPR_NOACCESS,
1017 &spr_read_generic, &spr_write_generic,
1018 0x00000000);
1019 }
1020
1021 static void gen_spr_thrm (CPUPPCState *env)
1022 {
1023 /* Thermal management */
1024 /* XXX : not implemented */
1025 spr_register(env, SPR_THRM1, "THRM1",
1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, &spr_write_generic,
1028 0x00000000);
1029 /* XXX : not implemented */
1030 spr_register(env, SPR_THRM2, "THRM2",
1031 SPR_NOACCESS, SPR_NOACCESS,
1032 &spr_read_generic, &spr_write_generic,
1033 0x00000000);
1034 /* XXX : not implemented */
1035 spr_register(env, SPR_THRM3, "THRM3",
1036 SPR_NOACCESS, SPR_NOACCESS,
1037 &spr_read_generic, &spr_write_generic,
1038 0x00000000);
1039 }
1040
1041 /* SPR specific to PowerPC 604 implementation */
1042 static void gen_spr_604 (CPUPPCState *env)
1043 {
1044 /* Processor identification */
1045 spr_register(env, SPR_PIR, "PIR",
1046 SPR_NOACCESS, SPR_NOACCESS,
1047 &spr_read_generic, &spr_write_pir,
1048 0x00000000);
1049 /* Breakpoints */
1050 /* XXX : not implemented */
1051 spr_register(env, SPR_IABR, "IABR",
1052 SPR_NOACCESS, SPR_NOACCESS,
1053 &spr_read_generic, &spr_write_generic,
1054 0x00000000);
1055 /* XXX : not implemented */
1056 spr_register(env, SPR_DABR, "DABR",
1057 SPR_NOACCESS, SPR_NOACCESS,
1058 &spr_read_generic, &spr_write_generic,
1059 0x00000000);
1060 /* Performance counters */
1061 /* XXX : not implemented */
1062 spr_register(env, SPR_MMCR0, "MMCR0",
1063 SPR_NOACCESS, SPR_NOACCESS,
1064 &spr_read_generic, &spr_write_generic,
1065 0x00000000);
1066 /* XXX : not implemented */
1067 spr_register(env, SPR_PMC1, "PMC1",
1068 SPR_NOACCESS, SPR_NOACCESS,
1069 &spr_read_generic, &spr_write_generic,
1070 0x00000000);
1071 /* XXX : not implemented */
1072 spr_register(env, SPR_PMC2, "PMC2",
1073 SPR_NOACCESS, SPR_NOACCESS,
1074 &spr_read_generic, &spr_write_generic,
1075 0x00000000);
1076 /* XXX : not implemented */
1077 spr_register(env, SPR_SIAR, "SIAR",
1078 SPR_NOACCESS, SPR_NOACCESS,
1079 &spr_read_generic, SPR_NOACCESS,
1080 0x00000000);
1081 /* XXX : not implemented */
1082 spr_register(env, SPR_SDA, "SDA",
1083 SPR_NOACCESS, SPR_NOACCESS,
1084 &spr_read_generic, SPR_NOACCESS,
1085 0x00000000);
1086 /* External access control */
1087 /* XXX : not implemented */
1088 spr_register(env, SPR_EAR, "EAR",
1089 SPR_NOACCESS, SPR_NOACCESS,
1090 &spr_read_generic, &spr_write_generic,
1091 0x00000000);
1092 }
1093
1094 /* SPR specific to PowerPC 603 implementation */
1095 static void gen_spr_603 (CPUPPCState *env)
1096 {
1097 /* External access control */
1098 /* XXX : not implemented */
1099 spr_register(env, SPR_EAR, "EAR",
1100 SPR_NOACCESS, SPR_NOACCESS,
1101 &spr_read_generic, &spr_write_generic,
1102 0x00000000);
1103 }
1104
1105 /* SPR specific to PowerPC G2 implementation */
1106 static void gen_spr_G2 (CPUPPCState *env)
1107 {
1108 /* Memory base address */
1109 /* MBAR */
1110 /* XXX : not implemented */
1111 spr_register(env, SPR_MBAR, "MBAR",
1112 SPR_NOACCESS, SPR_NOACCESS,
1113 &spr_read_generic, &spr_write_generic,
1114 0x00000000);
1115 /* Exception processing */
1116 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1117 SPR_NOACCESS, SPR_NOACCESS,
1118 &spr_read_generic, &spr_write_generic,
1119 0x00000000);
1120 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1121 SPR_NOACCESS, SPR_NOACCESS,
1122 &spr_read_generic, &spr_write_generic,
1123 0x00000000);
1124 /* Breakpoints */
1125 /* XXX : not implemented */
1126 spr_register(env, SPR_DABR, "DABR",
1127 SPR_NOACCESS, SPR_NOACCESS,
1128 &spr_read_generic, &spr_write_generic,
1129 0x00000000);
1130 /* XXX : not implemented */
1131 spr_register(env, SPR_DABR2, "DABR2",
1132 SPR_NOACCESS, SPR_NOACCESS,
1133 &spr_read_generic, &spr_write_generic,
1134 0x00000000);
1135 /* XXX : not implemented */
1136 spr_register(env, SPR_IABR, "IABR",
1137 SPR_NOACCESS, SPR_NOACCESS,
1138 &spr_read_generic, &spr_write_generic,
1139 0x00000000);
1140 /* XXX : not implemented */
1141 spr_register(env, SPR_IABR2, "IABR2",
1142 SPR_NOACCESS, SPR_NOACCESS,
1143 &spr_read_generic, &spr_write_generic,
1144 0x00000000);
1145 /* XXX : not implemented */
1146 spr_register(env, SPR_IBCR, "IBCR",
1147 SPR_NOACCESS, SPR_NOACCESS,
1148 &spr_read_generic, &spr_write_generic,
1149 0x00000000);
1150 /* XXX : not implemented */
1151 spr_register(env, SPR_DBCR, "DBCR",
1152 SPR_NOACCESS, SPR_NOACCESS,
1153 &spr_read_generic, &spr_write_generic,
1154 0x00000000);
1155 }
1156
1157 /* SPR specific to PowerPC 602 implementation */
1158 static void gen_spr_602 (CPUPPCState *env)
1159 {
1160 /* ESA registers */
1161 /* XXX : not implemented */
1162 spr_register(env, SPR_SER, "SER",
1163 SPR_NOACCESS, SPR_NOACCESS,
1164 &spr_read_generic, &spr_write_generic,
1165 0x00000000);
1166 /* XXX : not implemented */
1167 spr_register(env, SPR_SEBR, "SEBR",
1168 SPR_NOACCESS, SPR_NOACCESS,
1169 &spr_read_generic, &spr_write_generic,
1170 0x00000000);
1171 /* XXX : not implemented */
1172 spr_register(env, SPR_ESASRR, "ESASRR",
1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_generic, &spr_write_generic,
1175 0x00000000);
1176 /* Floating point status */
1177 /* XXX : not implemented */
1178 spr_register(env, SPR_SP, "SP",
1179 SPR_NOACCESS, SPR_NOACCESS,
1180 &spr_read_generic, &spr_write_generic,
1181 0x00000000);
1182 /* XXX : not implemented */
1183 spr_register(env, SPR_LT, "LT",
1184 SPR_NOACCESS, SPR_NOACCESS,
1185 &spr_read_generic, &spr_write_generic,
1186 0x00000000);
1187 /* Watchdog timer */
1188 /* XXX : not implemented */
1189 spr_register(env, SPR_TCR, "TCR",
1190 SPR_NOACCESS, SPR_NOACCESS,
1191 &spr_read_generic, &spr_write_generic,
1192 0x00000000);
1193 /* Interrupt base */
1194 spr_register(env, SPR_IBR, "IBR",
1195 SPR_NOACCESS, SPR_NOACCESS,
1196 &spr_read_generic, &spr_write_generic,
1197 0x00000000);
1198 /* XXX : not implemented */
1199 spr_register(env, SPR_IABR, "IABR",
1200 SPR_NOACCESS, SPR_NOACCESS,
1201 &spr_read_generic, &spr_write_generic,
1202 0x00000000);
1203 }
1204
1205 /* SPR specific to PowerPC 601 implementation */
1206 static void gen_spr_601 (CPUPPCState *env)
1207 {
1208 /* Multiplication/division register */
1209 /* MQ */
1210 spr_register(env, SPR_MQ, "MQ",
1211 &spr_read_generic, &spr_write_generic,
1212 &spr_read_generic, &spr_write_generic,
1213 0x00000000);
1214 /* RTC registers */
1215 spr_register(env, SPR_601_RTCU, "RTCU",
1216 SPR_NOACCESS, SPR_NOACCESS,
1217 SPR_NOACCESS, &spr_write_601_rtcu,
1218 0x00000000);
1219 spr_register(env, SPR_601_VRTCU, "RTCU",
1220 &spr_read_601_rtcu, SPR_NOACCESS,
1221 &spr_read_601_rtcu, SPR_NOACCESS,
1222 0x00000000);
1223 spr_register(env, SPR_601_RTCL, "RTCL",
1224 SPR_NOACCESS, SPR_NOACCESS,
1225 SPR_NOACCESS, &spr_write_601_rtcl,
1226 0x00000000);
1227 spr_register(env, SPR_601_VRTCL, "RTCL",
1228 &spr_read_601_rtcl, SPR_NOACCESS,
1229 &spr_read_601_rtcl, SPR_NOACCESS,
1230 0x00000000);
1231 /* Timer */
1232 #if 0 /* ? */
1233 spr_register(env, SPR_601_UDECR, "UDECR",
1234 &spr_read_decr, SPR_NOACCESS,
1235 &spr_read_decr, SPR_NOACCESS,
1236 0x00000000);
1237 #endif
1238 /* External access control */
1239 /* XXX : not implemented */
1240 spr_register(env, SPR_EAR, "EAR",
1241 SPR_NOACCESS, SPR_NOACCESS,
1242 &spr_read_generic, &spr_write_generic,
1243 0x00000000);
1244 /* Memory management */
1245 #if !defined(CONFIG_USER_ONLY)
1246 spr_register(env, SPR_IBAT0U, "IBAT0U",
1247 SPR_NOACCESS, SPR_NOACCESS,
1248 &spr_read_601_ubat, &spr_write_601_ubatu,
1249 0x00000000);
1250 spr_register(env, SPR_IBAT0L, "IBAT0L",
1251 SPR_NOACCESS, SPR_NOACCESS,
1252 &spr_read_601_ubat, &spr_write_601_ubatl,
1253 0x00000000);
1254 spr_register(env, SPR_IBAT1U, "IBAT1U",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_601_ubat, &spr_write_601_ubatu,
1257 0x00000000);
1258 spr_register(env, SPR_IBAT1L, "IBAT1L",
1259 SPR_NOACCESS, SPR_NOACCESS,
1260 &spr_read_601_ubat, &spr_write_601_ubatl,
1261 0x00000000);
1262 spr_register(env, SPR_IBAT2U, "IBAT2U",
1263 SPR_NOACCESS, SPR_NOACCESS,
1264 &spr_read_601_ubat, &spr_write_601_ubatu,
1265 0x00000000);
1266 spr_register(env, SPR_IBAT2L, "IBAT2L",
1267 SPR_NOACCESS, SPR_NOACCESS,
1268 &spr_read_601_ubat, &spr_write_601_ubatl,
1269 0x00000000);
1270 spr_register(env, SPR_IBAT3U, "IBAT3U",
1271 SPR_NOACCESS, SPR_NOACCESS,
1272 &spr_read_601_ubat, &spr_write_601_ubatu,
1273 0x00000000);
1274 spr_register(env, SPR_IBAT3L, "IBAT3L",
1275 SPR_NOACCESS, SPR_NOACCESS,
1276 &spr_read_601_ubat, &spr_write_601_ubatl,
1277 0x00000000);
1278 env->nb_BATs = 4;
1279 #endif
1280 }
1281
1282 static void gen_spr_74xx (CPUPPCState *env)
1283 {
1284 /* Processor identification */
1285 spr_register(env, SPR_PIR, "PIR",
1286 SPR_NOACCESS, SPR_NOACCESS,
1287 &spr_read_generic, &spr_write_pir,
1288 0x00000000);
1289 /* XXX : not implemented */
1290 spr_register(env, SPR_MMCR2, "MMCR2",
1291 SPR_NOACCESS, SPR_NOACCESS,
1292 &spr_read_generic, &spr_write_generic,
1293 0x00000000);
1294 /* XXX : not implemented */
1295 spr_register(env, SPR_UMMCR2, "UMMCR2",
1296 &spr_read_ureg, SPR_NOACCESS,
1297 &spr_read_ureg, SPR_NOACCESS,
1298 0x00000000);
1299 /* XXX: not implemented */
1300 spr_register(env, SPR_BAMR, "BAMR",
1301 SPR_NOACCESS, SPR_NOACCESS,
1302 &spr_read_generic, &spr_write_generic,
1303 0x00000000);
1304 /* XXX : not implemented */
1305 spr_register(env, SPR_MSSCR0, "MSSCR0",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, &spr_write_generic,
1308 0x00000000);
1309 /* Hardware implementation registers */
1310 /* XXX : not implemented */
1311 spr_register(env, SPR_HID0, "HID0",
1312 SPR_NOACCESS, SPR_NOACCESS,
1313 &spr_read_generic, &spr_write_generic,
1314 0x00000000);
1315 /* XXX : not implemented */
1316 spr_register(env, SPR_HID1, "HID1",
1317 SPR_NOACCESS, SPR_NOACCESS,
1318 &spr_read_generic, &spr_write_generic,
1319 0x00000000);
1320 /* Altivec */
1321 spr_register(env, SPR_VRSAVE, "VRSAVE",
1322 &spr_read_generic, &spr_write_generic,
1323 &spr_read_generic, &spr_write_generic,
1324 0x00000000);
1325 /* XXX : not implemented */
1326 spr_register(env, SPR_L2CR, "L2CR",
1327 SPR_NOACCESS, SPR_NOACCESS,
1328 &spr_read_generic, &spr_write_generic,
1329 0x00000000);
1330 /* Not strictly an SPR */
1331 vscr_init(env, 0x00010000);
1332 }
1333
1334 static void gen_l3_ctrl (CPUPPCState *env)
1335 {
1336 /* L3CR */
1337 /* XXX : not implemented */
1338 spr_register(env, SPR_L3CR, "L3CR",
1339 SPR_NOACCESS, SPR_NOACCESS,
1340 &spr_read_generic, &spr_write_generic,
1341 0x00000000);
1342 /* L3ITCR0 */
1343 /* XXX : not implemented */
1344 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1345 SPR_NOACCESS, SPR_NOACCESS,
1346 &spr_read_generic, &spr_write_generic,
1347 0x00000000);
1348 /* L3PM */
1349 /* XXX : not implemented */
1350 spr_register(env, SPR_L3PM, "L3PM",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_generic,
1353 0x00000000);
1354 }
1355
1356 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1357 {
1358 #if !defined(CONFIG_USER_ONLY)
1359 env->nb_tlb = nb_tlbs;
1360 env->nb_ways = nb_ways;
1361 env->id_tlbs = 1;
1362 env->tlb_type = TLB_6XX;
1363 /* XXX : not implemented */
1364 spr_register(env, SPR_PTEHI, "PTEHI",
1365 SPR_NOACCESS, SPR_NOACCESS,
1366 &spr_read_generic, &spr_write_generic,
1367 0x00000000);
1368 /* XXX : not implemented */
1369 spr_register(env, SPR_PTELO, "PTELO",
1370 SPR_NOACCESS, SPR_NOACCESS,
1371 &spr_read_generic, &spr_write_generic,
1372 0x00000000);
1373 /* XXX : not implemented */
1374 spr_register(env, SPR_TLBMISS, "TLBMISS",
1375 SPR_NOACCESS, SPR_NOACCESS,
1376 &spr_read_generic, &spr_write_generic,
1377 0x00000000);
1378 #endif
1379 }
1380
1381 #if !defined(CONFIG_USER_ONLY)
1382 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1383 {
1384 TCGv t0 = tcg_temp_new();
1385
1386 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1387 gen_store_spr(sprn, t0);
1388 tcg_temp_free(t0);
1389 }
1390
1391 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1392 {
1393 TCGv_i32 t0 = tcg_const_i32(sprn);
1394 gen_helper_booke206_tlbflush(cpu_env, t0);
1395 tcg_temp_free_i32(t0);
1396 }
1397
1398 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1399 {
1400 TCGv_i32 t0 = tcg_const_i32(sprn);
1401 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1402 tcg_temp_free_i32(t0);
1403 }
1404 #endif
1405
1406 static void gen_spr_usprgh (CPUPPCState *env)
1407 {
1408 spr_register(env, SPR_USPRG4, "USPRG4",
1409 &spr_read_ureg, SPR_NOACCESS,
1410 &spr_read_ureg, SPR_NOACCESS,
1411 0x00000000);
1412 spr_register(env, SPR_USPRG5, "USPRG5",
1413 &spr_read_ureg, SPR_NOACCESS,
1414 &spr_read_ureg, SPR_NOACCESS,
1415 0x00000000);
1416 spr_register(env, SPR_USPRG6, "USPRG6",
1417 &spr_read_ureg, SPR_NOACCESS,
1418 &spr_read_ureg, SPR_NOACCESS,
1419 0x00000000);
1420 spr_register(env, SPR_USPRG7, "USPRG7",
1421 &spr_read_ureg, SPR_NOACCESS,
1422 &spr_read_ureg, SPR_NOACCESS,
1423 0x00000000);
1424 }
1425
1426 /* PowerPC BookE SPR */
1427 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1428 {
1429 const char *ivor_names[64] = {
1430 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1431 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1432 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1433 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1434 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1435 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1436 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1437 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1438 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1439 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1440 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1441 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1442 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1443 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1444 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1445 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1446 };
1447 #define SPR_BOOKE_IVORxx (-1)
1448 int ivor_sprn[64] = {
1449 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1450 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1451 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1452 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1453 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1454 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1455 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1456 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1457 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1458 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1459 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1460 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1461 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1462 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1463 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1464 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1465 };
1466 int i;
1467
1468 /* Interrupt processing */
1469 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1470 SPR_NOACCESS, SPR_NOACCESS,
1471 &spr_read_generic, &spr_write_generic,
1472 0x00000000);
1473 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1474 SPR_NOACCESS, SPR_NOACCESS,
1475 &spr_read_generic, &spr_write_generic,
1476 0x00000000);
1477 /* Debug */
1478 /* XXX : not implemented */
1479 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1480 SPR_NOACCESS, SPR_NOACCESS,
1481 &spr_read_generic, &spr_write_generic,
1482 0x00000000);
1483 /* XXX : not implemented */
1484 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1485 SPR_NOACCESS, SPR_NOACCESS,
1486 &spr_read_generic, &spr_write_generic,
1487 0x00000000);
1488 /* XXX : not implemented */
1489 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1490 SPR_NOACCESS, SPR_NOACCESS,
1491 &spr_read_generic, &spr_write_generic,
1492 0x00000000);
1493 /* XXX : not implemented */
1494 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1495 SPR_NOACCESS, SPR_NOACCESS,
1496 &spr_read_generic, &spr_write_generic,
1497 0x00000000);
1498 /* XXX : not implemented */
1499 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1500 SPR_NOACCESS, SPR_NOACCESS,
1501 &spr_read_generic, &spr_write_generic,
1502 0x00000000);
1503 /* XXX : not implemented */
1504 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1505 SPR_NOACCESS, SPR_NOACCESS,
1506 &spr_read_generic, &spr_write_generic,
1507 0x00000000);
1508 /* XXX : not implemented */
1509 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1510 SPR_NOACCESS, SPR_NOACCESS,
1511 &spr_read_generic, &spr_write_generic,
1512 0x00000000);
1513 /* XXX : not implemented */
1514 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1515 SPR_NOACCESS, SPR_NOACCESS,
1516 &spr_read_generic, &spr_write_clear,
1517 0x00000000);
1518 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1519 SPR_NOACCESS, SPR_NOACCESS,
1520 &spr_read_generic, &spr_write_generic,
1521 0x00000000);
1522 spr_register(env, SPR_BOOKE_ESR, "ESR",
1523 SPR_NOACCESS, SPR_NOACCESS,
1524 &spr_read_generic, &spr_write_generic,
1525 0x00000000);
1526 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1527 SPR_NOACCESS, SPR_NOACCESS,
1528 &spr_read_generic, &spr_write_excp_prefix,
1529 0x00000000);
1530 /* Exception vectors */
1531 for (i = 0; i < 64; i++) {
1532 if (ivor_mask & (1ULL << i)) {
1533 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1534 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1535 exit(1);
1536 }
1537 spr_register(env, ivor_sprn[i], ivor_names[i],
1538 SPR_NOACCESS, SPR_NOACCESS,
1539 &spr_read_generic, &spr_write_excp_vector,
1540 0x00000000);
1541 }
1542 }
1543 spr_register(env, SPR_BOOKE_PID, "PID",
1544 SPR_NOACCESS, SPR_NOACCESS,
1545 &spr_read_generic, &spr_write_booke_pid,
1546 0x00000000);
1547 spr_register(env, SPR_BOOKE_TCR, "TCR",
1548 SPR_NOACCESS, SPR_NOACCESS,
1549 &spr_read_generic, &spr_write_booke_tcr,
1550 0x00000000);
1551 spr_register(env, SPR_BOOKE_TSR, "TSR",
1552 SPR_NOACCESS, SPR_NOACCESS,
1553 &spr_read_generic, &spr_write_booke_tsr,
1554 0x00000000);
1555 /* Timer */
1556 spr_register(env, SPR_DECR, "DECR",
1557 SPR_NOACCESS, SPR_NOACCESS,
1558 &spr_read_decr, &spr_write_decr,
1559 0x00000000);
1560 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1561 SPR_NOACCESS, SPR_NOACCESS,
1562 SPR_NOACCESS, &spr_write_generic,
1563 0x00000000);
1564 /* SPRGs */
1565 spr_register(env, SPR_USPRG0, "USPRG0",
1566 &spr_read_generic, &spr_write_generic,
1567 &spr_read_generic, &spr_write_generic,
1568 0x00000000);
1569 spr_register(env, SPR_SPRG4, "SPRG4",
1570 SPR_NOACCESS, SPR_NOACCESS,
1571 &spr_read_generic, &spr_write_generic,
1572 0x00000000);
1573 spr_register(env, SPR_SPRG5, "SPRG5",
1574 SPR_NOACCESS, SPR_NOACCESS,
1575 &spr_read_generic, &spr_write_generic,
1576 0x00000000);
1577 spr_register(env, SPR_SPRG6, "SPRG6",
1578 SPR_NOACCESS, SPR_NOACCESS,
1579 &spr_read_generic, &spr_write_generic,
1580 0x00000000);
1581 spr_register(env, SPR_SPRG7, "SPRG7",
1582 SPR_NOACCESS, SPR_NOACCESS,
1583 &spr_read_generic, &spr_write_generic,
1584 0x00000000);
1585 }
1586
1587 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1588 uint32_t maxsize, uint32_t flags,
1589 uint32_t nentries)
1590 {
1591 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1592 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1593 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1594 flags | nentries;
1595 }
1596
1597 /* BookE 2.06 storage control registers */
1598 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1599 uint32_t *tlbncfg)
1600 {
1601 #if !defined(CONFIG_USER_ONLY)
1602 const char *mas_names[8] = {
1603 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1604 };
1605 int mas_sprn[8] = {
1606 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1607 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1608 };
1609 int i;
1610
1611 /* TLB assist registers */
1612 /* XXX : not implemented */
1613 for (i = 0; i < 8; i++) {
1614 void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
1615 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1616 uea_write = &spr_write_generic;
1617 }
1618 if (mas_mask & (1 << i)) {
1619 spr_register(env, mas_sprn[i], mas_names[i],
1620 SPR_NOACCESS, SPR_NOACCESS,
1621 &spr_read_generic, uea_write,
1622 0x00000000);
1623 }
1624 }
1625 if (env->nb_pids > 1) {
1626 /* XXX : not implemented */
1627 spr_register(env, SPR_BOOKE_PID1, "PID1",
1628 SPR_NOACCESS, SPR_NOACCESS,
1629 &spr_read_generic, &spr_write_booke_pid,
1630 0x00000000);
1631 }
1632 if (env->nb_pids > 2) {
1633 /* XXX : not implemented */
1634 spr_register(env, SPR_BOOKE_PID2, "PID2",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 &spr_read_generic, &spr_write_booke_pid,
1637 0x00000000);
1638 }
1639 /* XXX : not implemented */
1640 spr_register(env, SPR_MMUCFG, "MMUCFG",
1641 SPR_NOACCESS, SPR_NOACCESS,
1642 &spr_read_generic, SPR_NOACCESS,
1643 0x00000000); /* TOFIX */
1644 switch (env->nb_ways) {
1645 case 4:
1646 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1647 SPR_NOACCESS, SPR_NOACCESS,
1648 &spr_read_generic, SPR_NOACCESS,
1649 tlbncfg[3]);
1650 /* Fallthru */
1651 case 3:
1652 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1653 SPR_NOACCESS, SPR_NOACCESS,
1654 &spr_read_generic, SPR_NOACCESS,
1655 tlbncfg[2]);
1656 /* Fallthru */
1657 case 2:
1658 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1659 SPR_NOACCESS, SPR_NOACCESS,
1660 &spr_read_generic, SPR_NOACCESS,
1661 tlbncfg[1]);
1662 /* Fallthru */
1663 case 1:
1664 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1665 SPR_NOACCESS, SPR_NOACCESS,
1666 &spr_read_generic, SPR_NOACCESS,
1667 tlbncfg[0]);
1668 /* Fallthru */
1669 case 0:
1670 default:
1671 break;
1672 }
1673 #endif
1674
1675 gen_spr_usprgh(env);
1676 }
1677
1678 /* SPR specific to PowerPC 440 implementation */
1679 static void gen_spr_440 (CPUPPCState *env)
1680 {
1681 /* Cache control */
1682 /* XXX : not implemented */
1683 spr_register(env, SPR_440_DNV0, "DNV0",
1684 SPR_NOACCESS, SPR_NOACCESS,
1685 &spr_read_generic, &spr_write_generic,
1686 0x00000000);
1687 /* XXX : not implemented */
1688 spr_register(env, SPR_440_DNV1, "DNV1",
1689 SPR_NOACCESS, SPR_NOACCESS,
1690 &spr_read_generic, &spr_write_generic,
1691 0x00000000);
1692 /* XXX : not implemented */
1693 spr_register(env, SPR_440_DNV2, "DNV2",
1694 SPR_NOACCESS, SPR_NOACCESS,
1695 &spr_read_generic, &spr_write_generic,
1696 0x00000000);
1697 /* XXX : not implemented */
1698 spr_register(env, SPR_440_DNV3, "DNV3",
1699 SPR_NOACCESS, SPR_NOACCESS,
1700 &spr_read_generic, &spr_write_generic,
1701 0x00000000);
1702 /* XXX : not implemented */
1703 spr_register(env, SPR_440_DTV0, "DTV0",
1704 SPR_NOACCESS, SPR_NOACCESS,
1705 &spr_read_generic, &spr_write_generic,
1706 0x00000000);
1707 /* XXX : not implemented */
1708 spr_register(env, SPR_440_DTV1, "DTV1",
1709 SPR_NOACCESS, SPR_NOACCESS,
1710 &spr_read_generic, &spr_write_generic,
1711 0x00000000);
1712 /* XXX : not implemented */
1713 spr_register(env, SPR_440_DTV2, "DTV2",
1714 SPR_NOACCESS, SPR_NOACCESS,
1715 &spr_read_generic, &spr_write_generic,
1716 0x00000000);
1717 /* XXX : not implemented */
1718 spr_register(env, SPR_440_DTV3, "DTV3",
1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, &spr_write_generic,
1721 0x00000000);
1722 /* XXX : not implemented */
1723 spr_register(env, SPR_440_DVLIM, "DVLIM",
1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_generic, &spr_write_generic,
1726 0x00000000);
1727 /* XXX : not implemented */
1728 spr_register(env, SPR_440_INV0, "INV0",
1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, &spr_write_generic,
1731 0x00000000);
1732 /* XXX : not implemented */
1733 spr_register(env, SPR_440_INV1, "INV1",
1734 SPR_NOACCESS, SPR_NOACCESS,
1735 &spr_read_generic, &spr_write_generic,
1736 0x00000000);
1737 /* XXX : not implemented */
1738 spr_register(env, SPR_440_INV2, "INV2",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, &spr_write_generic,
1741 0x00000000);
1742 /* XXX : not implemented */
1743 spr_register(env, SPR_440_INV3, "INV3",
1744 SPR_NOACCESS, SPR_NOACCESS,
1745 &spr_read_generic, &spr_write_generic,
1746 0x00000000);
1747 /* XXX : not implemented */
1748 spr_register(env, SPR_440_ITV0, "ITV0",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752 /* XXX : not implemented */
1753 spr_register(env, SPR_440_ITV1, "ITV1",
1754 SPR_NOACCESS, SPR_NOACCESS,
1755 &spr_read_generic, &spr_write_generic,
1756 0x00000000);
1757 /* XXX : not implemented */
1758 spr_register(env, SPR_440_ITV2, "ITV2",
1759 SPR_NOACCESS, SPR_NOACCESS,
1760 &spr_read_generic, &spr_write_generic,
1761 0x00000000);
1762 /* XXX : not implemented */
1763 spr_register(env, SPR_440_ITV3, "ITV3",
1764 SPR_NOACCESS, SPR_NOACCESS,
1765 &spr_read_generic, &spr_write_generic,
1766 0x00000000);
1767 /* XXX : not implemented */
1768 spr_register(env, SPR_440_IVLIM, "IVLIM",
1769 SPR_NOACCESS, SPR_NOACCESS,
1770 &spr_read_generic, &spr_write_generic,
1771 0x00000000);
1772 /* Cache debug */
1773 /* XXX : not implemented */
1774 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1775 SPR_NOACCESS, SPR_NOACCESS,
1776 &spr_read_generic, SPR_NOACCESS,
1777 0x00000000);
1778 /* XXX : not implemented */
1779 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1780 SPR_NOACCESS, SPR_NOACCESS,
1781 &spr_read_generic, SPR_NOACCESS,
1782 0x00000000);
1783 /* XXX : not implemented */
1784 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1785 SPR_NOACCESS, SPR_NOACCESS,
1786 &spr_read_generic, SPR_NOACCESS,
1787 0x00000000);
1788 /* XXX : not implemented */
1789 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1790 SPR_NOACCESS, SPR_NOACCESS,
1791 &spr_read_generic, SPR_NOACCESS,
1792 0x00000000);
1793 /* XXX : not implemented */
1794 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1795 SPR_NOACCESS, SPR_NOACCESS,
1796 &spr_read_generic, SPR_NOACCESS,
1797 0x00000000);
1798 /* XXX : not implemented */
1799 spr_register(env, SPR_440_DBDR, "DBDR",
1800 SPR_NOACCESS, SPR_NOACCESS,
1801 &spr_read_generic, &spr_write_generic,
1802 0x00000000);
1803 /* Processor control */
1804 spr_register(env, SPR_4xx_CCR0, "CCR0",
1805 SPR_NOACCESS, SPR_NOACCESS,
1806 &spr_read_generic, &spr_write_generic,
1807 0x00000000);
1808 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1809 SPR_NOACCESS, SPR_NOACCESS,
1810 &spr_read_generic, SPR_NOACCESS,
1811 0x00000000);
1812 /* Storage control */
1813 spr_register(env, SPR_440_MMUCR, "MMUCR",
1814 SPR_NOACCESS, SPR_NOACCESS,
1815 &spr_read_generic, &spr_write_generic,
1816 0x00000000);
1817 }
1818
1819 /* SPR shared between PowerPC 40x implementations */
1820 static void gen_spr_40x (CPUPPCState *env)
1821 {
1822 /* Cache */
1823 /* not emulated, as QEMU do not emulate caches */
1824 spr_register(env, SPR_40x_DCCR, "DCCR",
1825 SPR_NOACCESS, SPR_NOACCESS,
1826 &spr_read_generic, &spr_write_generic,
1827 0x00000000);
1828 /* not emulated, as QEMU do not emulate caches */
1829 spr_register(env, SPR_40x_ICCR, "ICCR",
1830 SPR_NOACCESS, SPR_NOACCESS,
1831 &spr_read_generic, &spr_write_generic,
1832 0x00000000);
1833 /* not emulated, as QEMU do not emulate caches */
1834 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1835 SPR_NOACCESS, SPR_NOACCESS,
1836 &spr_read_generic, SPR_NOACCESS,
1837 0x00000000);
1838 /* Exception */
1839 spr_register(env, SPR_40x_DEAR, "DEAR",
1840 SPR_NOACCESS, SPR_NOACCESS,
1841 &spr_read_generic, &spr_write_generic,
1842 0x00000000);
1843 spr_register(env, SPR_40x_ESR, "ESR",
1844 SPR_NOACCESS, SPR_NOACCESS,
1845 &spr_read_generic, &spr_write_generic,
1846 0x00000000);
1847 spr_register(env, SPR_40x_EVPR, "EVPR",
1848 SPR_NOACCESS, SPR_NOACCESS,
1849 &spr_read_generic, &spr_write_excp_prefix,
1850 0x00000000);
1851 spr_register(env, SPR_40x_SRR2, "SRR2",
1852 &spr_read_generic, &spr_write_generic,
1853 &spr_read_generic, &spr_write_generic,
1854 0x00000000);
1855 spr_register(env, SPR_40x_SRR3, "SRR3",
1856 &spr_read_generic, &spr_write_generic,
1857 &spr_read_generic, &spr_write_generic,
1858 0x00000000);
1859 /* Timers */
1860 spr_register(env, SPR_40x_PIT, "PIT",
1861 SPR_NOACCESS, SPR_NOACCESS,
1862 &spr_read_40x_pit, &spr_write_40x_pit,
1863 0x00000000);
1864 spr_register(env, SPR_40x_TCR, "TCR",
1865 SPR_NOACCESS, SPR_NOACCESS,
1866 &spr_read_generic, &spr_write_booke_tcr,
1867 0x00000000);
1868 spr_register(env, SPR_40x_TSR, "TSR",
1869 SPR_NOACCESS, SPR_NOACCESS,
1870 &spr_read_generic, &spr_write_booke_tsr,
1871 0x00000000);
1872 }
1873
1874 /* SPR specific to PowerPC 405 implementation */
1875 static void gen_spr_405 (CPUPPCState *env)
1876 {
1877 /* MMU */
1878 spr_register(env, SPR_40x_PID, "PID",
1879 SPR_NOACCESS, SPR_NOACCESS,
1880 &spr_read_generic, &spr_write_generic,
1881 0x00000000);
1882 spr_register(env, SPR_4xx_CCR0, "CCR0",
1883 SPR_NOACCESS, SPR_NOACCESS,
1884 &spr_read_generic, &spr_write_generic,
1885 0x00700000);
1886 /* Debug interface */
1887 /* XXX : not implemented */
1888 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1889 SPR_NOACCESS, SPR_NOACCESS,
1890 &spr_read_generic, &spr_write_40x_dbcr0,
1891 0x00000000);
1892 /* XXX : not implemented */
1893 spr_register(env, SPR_405_DBCR1, "DBCR1",
1894 SPR_NOACCESS, SPR_NOACCESS,
1895 &spr_read_generic, &spr_write_generic,
1896 0x00000000);
1897 /* XXX : not implemented */
1898 spr_register(env, SPR_40x_DBSR, "DBSR",
1899 SPR_NOACCESS, SPR_NOACCESS,
1900 &spr_read_generic, &spr_write_clear,
1901 /* Last reset was system reset */
1902 0x00000300);
1903 /* XXX : not implemented */
1904 spr_register(env, SPR_40x_DAC1, "DAC1",
1905 SPR_NOACCESS, SPR_NOACCESS,
1906 &spr_read_generic, &spr_write_generic,
1907 0x00000000);
1908 spr_register(env, SPR_40x_DAC2, "DAC2",
1909 SPR_NOACCESS, SPR_NOACCESS,
1910 &spr_read_generic, &spr_write_generic,
1911 0x00000000);
1912 /* XXX : not implemented */
1913 spr_register(env, SPR_405_DVC1, "DVC1",
1914 SPR_NOACCESS, SPR_NOACCESS,
1915 &spr_read_generic, &spr_write_generic,
1916 0x00000000);
1917 /* XXX : not implemented */
1918 spr_register(env, SPR_405_DVC2, "DVC2",
1919 SPR_NOACCESS, SPR_NOACCESS,
1920 &spr_read_generic, &spr_write_generic,
1921 0x00000000);
1922 /* XXX : not implemented */
1923 spr_register(env, SPR_40x_IAC1, "IAC1",
1924 SPR_NOACCESS, SPR_NOACCESS,
1925 &spr_read_generic, &spr_write_generic,
1926 0x00000000);
1927 spr_register(env, SPR_40x_IAC2, "IAC2",
1928 SPR_NOACCESS, SPR_NOACCESS,
1929 &spr_read_generic, &spr_write_generic,
1930 0x00000000);
1931 /* XXX : not implemented */
1932 spr_register(env, SPR_405_IAC3, "IAC3",
1933 SPR_NOACCESS, SPR_NOACCESS,
1934 &spr_read_generic, &spr_write_generic,
1935 0x00000000);
1936 /* XXX : not implemented */
1937 spr_register(env, SPR_405_IAC4, "IAC4",
1938 SPR_NOACCESS, SPR_NOACCESS,
1939 &spr_read_generic, &spr_write_generic,
1940 0x00000000);
1941 /* Storage control */
1942 /* XXX: TODO: not implemented */
1943 spr_register(env, SPR_405_SLER, "SLER",
1944 SPR_NOACCESS, SPR_NOACCESS,
1945 &spr_read_generic, &spr_write_40x_sler,
1946 0x00000000);
1947 spr_register(env, SPR_40x_ZPR, "ZPR",
1948 SPR_NOACCESS, SPR_NOACCESS,
1949 &spr_read_generic, &spr_write_generic,
1950 0x00000000);
1951 /* XXX : not implemented */
1952 spr_register(env, SPR_405_SU0R, "SU0R",
1953 SPR_NOACCESS, SPR_NOACCESS,
1954 &spr_read_generic, &spr_write_generic,
1955 0x00000000);
1956 /* SPRG */
1957 spr_register(env, SPR_USPRG0, "USPRG0",
1958 &spr_read_ureg, SPR_NOACCESS,
1959 &spr_read_ureg, SPR_NOACCESS,
1960 0x00000000);
1961 spr_register(env, SPR_SPRG4, "SPRG4",
1962 SPR_NOACCESS, SPR_NOACCESS,
1963 &spr_read_generic, &spr_write_generic,
1964 0x00000000);
1965 spr_register(env, SPR_SPRG5, "SPRG5",
1966 SPR_NOACCESS, SPR_NOACCESS,
1967 spr_read_generic, &spr_write_generic,
1968 0x00000000);
1969 spr_register(env, SPR_SPRG6, "SPRG6",
1970 SPR_NOACCESS, SPR_NOACCESS,
1971 spr_read_generic, &spr_write_generic,
1972 0x00000000);
1973 spr_register(env, SPR_SPRG7, "SPRG7",
1974 SPR_NOACCESS, SPR_NOACCESS,
1975 spr_read_generic, &spr_write_generic,
1976 0x00000000);
1977 gen_spr_usprgh(env);
1978 }
1979
1980 /* SPR shared between PowerPC 401 & 403 implementations */
1981 static void gen_spr_401_403 (CPUPPCState *env)
1982 {
1983 /* Time base */
1984 spr_register(env, SPR_403_VTBL, "TBL",
1985 &spr_read_tbl, SPR_NOACCESS,
1986 &spr_read_tbl, SPR_NOACCESS,
1987 0x00000000);
1988 spr_register(env, SPR_403_TBL, "TBL",
1989 SPR_NOACCESS, SPR_NOACCESS,
1990 SPR_NOACCESS, &spr_write_tbl,
1991 0x00000000);
1992 spr_register(env, SPR_403_VTBU, "TBU",
1993 &spr_read_tbu, SPR_NOACCESS,
1994 &spr_read_tbu, SPR_NOACCESS,
1995 0x00000000);
1996 spr_register(env, SPR_403_TBU, "TBU",
1997 SPR_NOACCESS, SPR_NOACCESS,
1998 SPR_NOACCESS, &spr_write_tbu,
1999 0x00000000);
2000 /* Debug */
2001 /* not emulated, as QEMU do not emulate caches */
2002 spr_register(env, SPR_403_CDBCR, "CDBCR",
2003 SPR_NOACCESS, SPR_NOACCESS,
2004 &spr_read_generic, &spr_write_generic,
2005 0x00000000);
2006 }
2007
2008 /* SPR specific to PowerPC 401 implementation */
2009 static void gen_spr_401 (CPUPPCState *env)
2010 {
2011 /* Debug interface */
2012 /* XXX : not implemented */
2013 spr_register(env, SPR_40x_DBCR0, "DBCR",
2014 SPR_NOACCESS, SPR_NOACCESS,
2015 &spr_read_generic, &spr_write_40x_dbcr0,
2016 0x00000000);
2017 /* XXX : not implemented */
2018 spr_register(env, SPR_40x_DBSR, "DBSR",
2019 SPR_NOACCESS, SPR_NOACCESS,
2020 &spr_read_generic, &spr_write_clear,
2021 /* Last reset was system reset */
2022 0x00000300);
2023 /* XXX : not implemented */
2024 spr_register(env, SPR_40x_DAC1, "DAC",
2025 SPR_NOACCESS, SPR_NOACCESS,
2026 &spr_read_generic, &spr_write_generic,
2027 0x00000000);
2028 /* XXX : not implemented */
2029 spr_register(env, SPR_40x_IAC1, "IAC",
2030 SPR_NOACCESS, SPR_NOACCESS,
2031 &spr_read_generic, &spr_write_generic,
2032 0x00000000);
2033 /* Storage control */
2034 /* XXX: TODO: not implemented */
2035 spr_register(env, SPR_405_SLER, "SLER",
2036 SPR_NOACCESS, SPR_NOACCESS,
2037 &spr_read_generic, &spr_write_40x_sler,
2038 0x00000000);
2039 /* not emulated, as QEMU never does speculative access */
2040 spr_register(env, SPR_40x_SGR, "SGR",
2041 SPR_NOACCESS, SPR_NOACCESS,
2042 &spr_read_generic, &spr_write_generic,
2043 0xFFFFFFFF);
2044 /* not emulated, as QEMU do not emulate caches */
2045 spr_register(env, SPR_40x_DCWR, "DCWR",
2046 SPR_NOACCESS, SPR_NOACCESS,
2047 &spr_read_generic, &spr_write_generic,
2048 0x00000000);
2049 }
2050
2051 static void gen_spr_401x2 (CPUPPCState *env)
2052 {
2053 gen_spr_401(env);
2054 spr_register(env, SPR_40x_PID, "PID",
2055 SPR_NOACCESS, SPR_NOACCESS,
2056 &spr_read_generic, &spr_write_generic,
2057 0x00000000);
2058 spr_register(env, SPR_40x_ZPR, "ZPR",
2059 SPR_NOACCESS, SPR_NOACCESS,
2060 &spr_read_generic, &spr_write_generic,
2061 0x00000000);
2062 }
2063
2064 /* SPR specific to PowerPC 403 implementation */
2065 static void gen_spr_403 (CPUPPCState *env)
2066 {
2067 /* Debug interface */
2068 /* XXX : not implemented */
2069 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2070 SPR_NOACCESS, SPR_NOACCESS,
2071 &spr_read_generic, &spr_write_40x_dbcr0,
2072 0x00000000);
2073 /* XXX : not implemented */
2074 spr_register(env, SPR_40x_DBSR, "DBSR",
2075 SPR_NOACCESS, SPR_NOACCESS,
2076 &spr_read_generic, &spr_write_clear,
2077 /* Last reset was system reset */
2078 0x00000300);
2079 /* XXX : not implemented */
2080 spr_register(env, SPR_40x_DAC1, "DAC1",
2081 SPR_NOACCESS, SPR_NOACCESS,
2082 &spr_read_generic, &spr_write_generic,
2083 0x00000000);
2084 /* XXX : not implemented */
2085 spr_register(env, SPR_40x_DAC2, "DAC2",
2086 SPR_NOACCESS, SPR_NOACCESS,
2087 &spr_read_generic, &spr_write_generic,
2088 0x00000000);
2089 /* XXX : not implemented */
2090 spr_register(env, SPR_40x_IAC1, "IAC1",
2091 SPR_NOACCESS, SPR_NOACCESS,
2092 &spr_read_generic, &spr_write_generic,
2093 0x00000000);
2094 /* XXX : not implemented */
2095 spr_register(env, SPR_40x_IAC2, "IAC2",
2096 SPR_NOACCESS, SPR_NOACCESS,
2097 &spr_read_generic, &spr_write_generic,
2098 0x00000000);
2099 }
2100
2101 static void gen_spr_403_real (CPUPPCState *env)
2102 {
2103 spr_register(env, SPR_403_PBL1, "PBL1",
2104 SPR_NOACCESS, SPR_NOACCESS,
2105 &spr_read_403_pbr, &spr_write_403_pbr,
2106 0x00000000);
2107 spr_register(env, SPR_403_PBU1, "PBU1",
2108 SPR_NOACCESS, SPR_NOACCESS,
2109 &spr_read_403_pbr, &spr_write_403_pbr,
2110 0x00000000);
2111 spr_register(env, SPR_403_PBL2, "PBL2",
2112 SPR_NOACCESS, SPR_NOACCESS,
2113 &spr_read_403_pbr, &spr_write_403_pbr,
2114 0x00000000);
2115 spr_register(env, SPR_403_PBU2, "PBU2",
2116 SPR_NOACCESS, SPR_NOACCESS,
2117 &spr_read_403_pbr, &spr_write_403_pbr,
2118 0x00000000);
2119 }
2120
2121 static void gen_spr_403_mmu (CPUPPCState *env)
2122 {
2123 /* MMU */
2124 spr_register(env, SPR_40x_PID, "PID",
2125 SPR_NOACCESS, SPR_NOACCESS,
2126 &spr_read_generic, &spr_write_generic,
2127 0x00000000);
2128 spr_register(env, SPR_40x_ZPR, "ZPR",
2129 SPR_NOACCESS, SPR_NOACCESS,
2130 &spr_read_generic, &spr_write_generic,
2131 0x00000000);
2132 }
2133
2134 /* SPR specific to PowerPC compression coprocessor extension */
2135 static void gen_spr_compress (CPUPPCState *env)
2136 {
2137 /* XXX : not implemented */
2138 spr_register(env, SPR_401_SKR, "SKR",
2139 SPR_NOACCESS, SPR_NOACCESS,
2140 &spr_read_generic, &spr_write_generic,
2141 0x00000000);
2142 }
2143
2144 #if defined (TARGET_PPC64)
2145 /* SPR specific to PowerPC 620 */
2146 static void gen_spr_620 (CPUPPCState *env)
2147 {
2148 /* Processor identification */
2149 spr_register(env, SPR_PIR, "PIR",
2150 SPR_NOACCESS, SPR_NOACCESS,
2151 &spr_read_generic, &spr_write_pir,
2152 0x00000000);
2153 spr_register(env, SPR_ASR, "ASR",
2154 SPR_NOACCESS, SPR_NOACCESS,
2155 &spr_read_asr, &spr_write_asr,
2156 0x00000000);
2157 /* Breakpoints */
2158 /* XXX : not implemented */
2159 spr_register(env, SPR_IABR, "IABR",
2160 SPR_NOACCESS, SPR_NOACCESS,
2161 &spr_read_generic, &spr_write_generic,
2162 0x00000000);
2163 /* XXX : not implemented */
2164 spr_register(env, SPR_DABR, "DABR",
2165 SPR_NOACCESS, SPR_NOACCESS,
2166 &spr_read_generic, &spr_write_generic,
2167 0x00000000);
2168 /* XXX : not implemented */
2169 spr_register(env, SPR_SIAR, "SIAR",
2170 SPR_NOACCESS, SPR_NOACCESS,
2171 &spr_read_generic, SPR_NOACCESS,
2172 0x00000000);
2173 /* XXX : not implemented */
2174 spr_register(env, SPR_SDA, "SDA",
2175 SPR_NOACCESS, SPR_NOACCESS,
2176 &spr_read_generic, SPR_NOACCESS,
2177 0x00000000);
2178 /* XXX : not implemented */
2179 spr_register(env, SPR_620_PMC1R, "PMC1",
2180 SPR_NOACCESS, SPR_NOACCESS,
2181 &spr_read_generic, SPR_NOACCESS,
2182 0x00000000);
2183 spr_register(env, SPR_620_PMC1W, "PMC1",
2184 SPR_NOACCESS, SPR_NOACCESS,
2185 SPR_NOACCESS, &spr_write_generic,
2186 0x00000000);
2187 /* XXX : not implemented */
2188 spr_register(env, SPR_620_PMC2R, "PMC2",
2189 SPR_NOACCESS, SPR_NOACCESS,
2190 &spr_read_generic, SPR_NOACCESS,
2191 0x00000000);
2192 spr_register(env, SPR_620_PMC2W, "PMC2",
2193 SPR_NOACCESS, SPR_NOACCESS,
2194 SPR_NOACCESS, &spr_write_generic,
2195 0x00000000);
2196 /* XXX : not implemented */
2197 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2198 SPR_NOACCESS, SPR_NOACCESS,
2199 &spr_read_generic, SPR_NOACCESS,
2200 0x00000000);
2201 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2202 SPR_NOACCESS, SPR_NOACCESS,
2203 SPR_NOACCESS, &spr_write_generic,
2204 0x00000000);
2205 /* External access control */
2206 /* XXX : not implemented */
2207 spr_register(env, SPR_EAR, "EAR",
2208 SPR_NOACCESS, SPR_NOACCESS,
2209 &spr_read_generic, &spr_write_generic,
2210 0x00000000);
2211 #if 0 // XXX: check this
2212 /* XXX : not implemented */
2213 spr_register(env, SPR_620_PMR0, "PMR0",
2214 SPR_NOACCESS, SPR_NOACCESS,
2215 &spr_read_generic, &spr_write_generic,
2216 0x00000000);
2217 /* XXX : not implemented */
2218 spr_register(env, SPR_620_PMR1, "PMR1",
2219 SPR_NOACCESS, SPR_NOACCESS,
2220 &spr_read_generic, &spr_write_generic,
2221 0x00000000);
2222 /* XXX : not implemented */
2223 spr_register(env, SPR_620_PMR2, "PMR2",
2224 SPR_NOACCESS, SPR_NOACCESS,
2225 &spr_read_generic, &spr_write_generic,
2226 0x00000000);
2227 /* XXX : not implemented */
2228 spr_register(env, SPR_620_PMR3, "PMR3",
2229 SPR_NOACCESS, SPR_NOACCESS,
2230 &spr_read_generic, &spr_write_generic,
2231 0x00000000);
2232 /* XXX : not implemented */
2233 spr_register(env, SPR_620_PMR4, "PMR4",
2234 SPR_NOACCESS, SPR_NOACCESS,
2235 &spr_read_generic, &spr_write_generic,
2236 0x00000000);
2237 /* XXX : not implemented */
2238 spr_register(env, SPR_620_PMR5, "PMR5",
2239 SPR_NOACCESS, SPR_NOACCESS,
2240 &spr_read_generic, &spr_write_generic,
2241 0x00000000);
2242 /* XXX : not implemented */
2243 spr_register(env, SPR_620_PMR6, "PMR6",
2244 SPR_NOACCESS, SPR_NOACCESS,
2245 &spr_read_generic, &spr_write_generic,
2246 0x00000000);
2247 /* XXX : not implemented */
2248 spr_register(env, SPR_620_PMR7, "PMR7",
2249 SPR_NOACCESS, SPR_NOACCESS,
2250 &spr_read_generic, &spr_write_generic,
2251 0x00000000);
2252 /* XXX : not implemented */
2253 spr_register(env, SPR_620_PMR8, "PMR8",
2254 SPR_NOACCESS, SPR_NOACCESS,
2255 &spr_read_generic, &spr_write_generic,
2256 0x00000000);
2257 /* XXX : not implemented */
2258 spr_register(env, SPR_620_PMR9, "PMR9",
2259 SPR_NOACCESS, SPR_NOACCESS,
2260 &spr_read_generic, &spr_write_generic,
2261 0x00000000);
2262 /* XXX : not implemented */
2263 spr_register(env, SPR_620_PMRA, "PMR10",
2264 SPR_NOACCESS, SPR_NOACCESS,
2265 &spr_read_generic, &spr_write_generic,
2266 0x00000000);
2267 /* XXX : not implemented */
2268 spr_register(env, SPR_620_PMRB, "PMR11",
2269 SPR_NOACCESS, SPR_NOACCESS,
2270 &spr_read_generic, &spr_write_generic,
2271 0x00000000);
2272 /* XXX : not implemented */
2273 spr_register(env, SPR_620_PMRC, "PMR12",
2274 SPR_NOACCESS, SPR_NOACCESS,
2275 &spr_read_generic, &spr_write_generic,
2276 0x00000000);
2277 /* XXX : not implemented */
2278 spr_register(env, SPR_620_PMRD, "PMR13",
2279 SPR_NOACCESS, SPR_NOACCESS,
2280 &spr_read_generic, &spr_write_generic,
2281 0x00000000);
2282 /* XXX : not implemented */
2283 spr_register(env, SPR_620_PMRE, "PMR14",
2284 SPR_NOACCESS, SPR_NOACCESS,
2285 &spr_read_generic, &spr_write_generic,
2286 0x00000000);
2287 /* XXX : not implemented */
2288 spr_register(env, SPR_620_PMRF, "PMR15",
2289 SPR_NOACCESS, SPR_NOACCESS,
2290 &spr_read_generic, &spr_write_generic,
2291 0x00000000);
2292 #endif
2293 /* XXX : not implemented */
2294 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2295 SPR_NOACCESS, SPR_NOACCESS,
2296 &spr_read_generic, &spr_write_generic,
2297 0x00000000);
2298 /* XXX : not implemented */
2299 spr_register(env, SPR_620_L2CR, "L2CR",
2300 SPR_NOACCESS, SPR_NOACCESS,
2301 &spr_read_generic, &spr_write_generic,
2302 0x00000000);
2303 /* XXX : not implemented */
2304 spr_register(env, SPR_620_L2SR, "L2SR",
2305 SPR_NOACCESS, SPR_NOACCESS,
2306 &spr_read_generic, &spr_write_generic,
2307 0x00000000);
2308 }
2309 #endif /* defined (TARGET_PPC64) */
2310
2311 static void gen_spr_5xx_8xx (CPUPPCState *env)
2312 {
2313 /* Exception processing */
2314 spr_register(env, SPR_DSISR, "DSISR",
2315 SPR_NOACCESS, SPR_NOACCESS,
2316 &spr_read_generic, &spr_write_generic,
2317 0x00000000);
2318 spr_register(env, SPR_DAR, "DAR",
2319 SPR_NOACCESS, SPR_NOACCESS,
2320 &spr_read_generic, &spr_write_generic,
2321 0x00000000);
2322 /* Timer */
2323 spr_register(env, SPR_DECR, "DECR",
2324 SPR_NOACCESS, SPR_NOACCESS,
2325 &spr_read_decr, &spr_write_decr,
2326 0x00000000);
2327 /* XXX : not implemented */
2328 spr_register(env, SPR_MPC_EIE, "EIE",
2329 SPR_NOACCESS, SPR_NOACCESS,
2330 &spr_read_generic, &spr_write_generic,
2331 0x00000000);
2332 /* XXX : not implemented */
2333 spr_register(env, SPR_MPC_EID, "EID",
2334 SPR_NOACCESS, SPR_NOACCESS,
2335 &spr_read_generic, &spr_write_generic,
2336 0x00000000);
2337 /* XXX : not implemented */
2338 spr_register(env, SPR_MPC_NRI, "NRI",
2339 SPR_NOACCESS, SPR_NOACCESS,
2340 &spr_read_generic, &spr_write_generic,
2341 0x00000000);
2342 /* XXX : not implemented */
2343 spr_register(env, SPR_MPC_CMPA, "CMPA",
2344 SPR_NOACCESS, SPR_NOACCESS,
2345 &spr_read_generic, &spr_write_generic,
2346 0x00000000);
2347 /* XXX : not implemented */
2348 spr_register(env, SPR_MPC_CMPB, "CMPB",
2349 SPR_NOACCESS, SPR_NOACCESS,
2350 &spr_read_generic, &spr_write_generic,
2351 0x00000000);
2352 /* XXX : not implemented */
2353 spr_register(env, SPR_MPC_CMPC, "CMPC",
2354 SPR_NOACCESS, SPR_NOACCESS,
2355 &spr_read_generic, &spr_write_generic,
2356 0x00000000);
2357 /* XXX : not implemented */
2358 spr_register(env, SPR_MPC_CMPD, "CMPD",
2359 SPR_NOACCESS, SPR_NOACCESS,
2360 &spr_read_generic, &spr_write_generic,
2361 0x00000000);
2362 /* XXX : not implemented */
2363 spr_register(env, SPR_MPC_ECR, "ECR",
2364 SPR_NOACCESS, SPR_NOACCESS,
2365 &spr_read_generic, &spr_write_generic,
2366 0x00000000);
2367 /* XXX : not implemented */
2368 spr_register(env, SPR_MPC_DER, "DER",
2369 SPR_NOACCESS, SPR_NOACCESS,
2370 &spr_read_generic, &spr_write_generic,
2371 0x00000000);
2372 /* XXX : not implemented */
2373 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2374 SPR_NOACCESS, SPR_NOACCESS,
2375 &spr_read_generic, &spr_write_generic,
2376 0x00000000);
2377 /* XXX : not implemented */
2378 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2379 SPR_NOACCESS, SPR_NOACCESS,
2380 &spr_read_generic, &spr_write_generic,
2381 0x00000000);
2382 /* XXX : not implemented */
2383 spr_register(env, SPR_MPC_CMPE, "CMPE",
2384 SPR_NOACCESS, SPR_NOACCESS,
2385 &spr_read_generic, &spr_write_generic,
2386 0x00000000);
2387 /* XXX : not implemented */
2388 spr_register(env, SPR_MPC_CMPF, "CMPF",
2389 SPR_NOACCESS, SPR_NOACCESS,
2390 &spr_read_generic, &spr_write_generic,
2391 0x00000000);
2392 /* XXX : not implemented */
2393 spr_register(env, SPR_MPC_CMPG, "CMPG",
2394 SPR_NOACCESS, SPR_NOACCESS,
2395 &spr_read_generic, &spr_write_generic,
2396 0x00000000);
2397 /* XXX : not implemented */
2398 spr_register(env, SPR_MPC_CMPH, "CMPH",
2399 SPR_NOACCESS, SPR_NOACCESS,
2400 &spr_read_generic, &spr_write_generic,
2401 0x00000000);
2402 /* XXX : not implemented */
2403 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2404 SPR_NOACCESS, SPR_NOACCESS,
2405 &spr_read_generic, &spr_write_generic,
2406 0x00000000);
2407 /* XXX : not implemented */
2408 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2409 SPR_NOACCESS, SPR_NOACCESS,
2410 &spr_read_generic, &spr_write_generic,
2411 0x00000000);
2412 /* XXX : not implemented */
2413 spr_register(env, SPR_MPC_BAR, "BAR",
2414 SPR_NOACCESS, SPR_NOACCESS,
2415 &spr_read_generic, &spr_write_generic,
2416 0x00000000);
2417 /* XXX : not implemented */
2418 spr_register(env, SPR_MPC_DPDR, "DPDR",
2419 SPR_NOACCESS, SPR_NOACCESS,
2420 &spr_read_generic, &spr_write_generic,
2421 0x00000000);
2422 /* XXX : not implemented */
2423 spr_register(env, SPR_MPC_IMMR, "IMMR",
2424 SPR_NOACCESS, SPR_NOACCESS,
2425 &spr_read_generic, &spr_write_generic,
2426 0x00000000);
2427 }
2428
2429 static void gen_spr_5xx (CPUPPCState *env)
2430 {
2431 /* XXX : not implemented */
2432 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2433 SPR_NOACCESS, SPR_NOACCESS,
2434 &spr_read_generic, &spr_write_generic,
2435 0x00000000);
2436 /* XXX : not implemented */
2437 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2438 SPR_NOACCESS, SPR_NOACCESS,
2439 &spr_read_generic, &spr_write_generic,
2440 0x00000000);
2441 /* XXX : not implemented */
2442 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2443 SPR_NOACCESS, SPR_NOACCESS,
2444 &spr_read_generic, &spr_write_generic,
2445 0x00000000);
2446 /* XXX : not implemented */
2447 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2448 SPR_NOACCESS, SPR_NOACCESS,
2449 &spr_read_generic, &spr_write_generic,
2450 0x00000000);
2451 /* XXX : not implemented */
2452 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2453 SPR_NOACCESS, SPR_NOACCESS,
2454 &spr_read_generic, &spr_write_generic,
2455 0x00000000);
2456 /* XXX : not implemented */
2457 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2458 SPR_NOACCESS, SPR_NOACCESS,
2459 &spr_read_generic, &spr_write_generic,
2460 0x00000000);
2461 /* XXX : not implemented */
2462 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2463 SPR_NOACCESS, SPR_NOACCESS,
2464 &spr_read_generic, &spr_write_generic,
2465 0x00000000);
2466 /* XXX : not implemented */
2467 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2468 SPR_NOACCESS, SPR_NOACCESS,
2469 &spr_read_generic, &spr_write_generic,
2470 0x00000000);
2471 /* XXX : not implemented */
2472 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2473 SPR_NOACCESS, SPR_NOACCESS,
2474 &spr_read_generic, &spr_write_generic,
2475 0x00000000);
2476 /* XXX : not implemented */
2477 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2478 SPR_NOACCESS, SPR_NOACCESS,
2479 &spr_read_generic, &spr_write_generic,
2480 0x00000000);
2481 /* XXX : not implemented */
2482 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2483 SPR_NOACCESS, SPR_NOACCESS,
2484 &spr_read_generic, &spr_write_generic,
2485 0x00000000);
2486 /* XXX : not implemented */
2487 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2488 SPR_NOACCESS, SPR_NOACCESS,
2489 &spr_read_generic, &spr_write_generic,
2490 0x00000000);
2491 /* XXX : not implemented */
2492 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2493 SPR_NOACCESS, SPR_NOACCESS,
2494 &spr_read_generic, &spr_write_generic,
2495 0x00000000);
2496 /* XXX : not implemented */
2497 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2498 SPR_NOACCESS, SPR_NOACCESS,
2499 &spr_read_generic, &spr_write_generic,
2500 0x00000000);
2501 /* XXX : not implemented */
2502 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2503 SPR_NOACCESS, SPR_NOACCESS,
2504 &spr_read_generic, &spr_write_generic,
2505 0x00000000);
2506 /* XXX : not implemented */
2507 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2508 SPR_NOACCESS, SPR_NOACCESS,
2509 &spr_read_generic, &spr_write_generic,
2510 0x00000000);
2511 /* XXX : not implemented */
2512 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2513 SPR_NOACCESS, SPR_NOACCESS,
2514 &spr_read_generic, &spr_write_generic,
2515 0x00000000);
2516 /* XXX : not implemented */
2517 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2518 SPR_NOACCESS, SPR_NOACCESS,
2519 &spr_read_generic, &spr_write_generic,
2520 0x00000000);
2521 /* XXX : not implemented */
2522 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2523 SPR_NOACCESS, SPR_NOACCESS,
2524 &spr_read_generic, &spr_write_generic,
2525 0x00000000);
2526 /* XXX : not implemented */
2527 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2528 SPR_NOACCESS, SPR_NOACCESS,
2529 &spr_read_generic, &spr_write_generic,
2530 0x00000000);
2531 /* XXX : not implemented */
2532 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2533 SPR_NOACCESS, SPR_NOACCESS,
2534 &spr_read_generic, &spr_write_generic,
2535 0x00000000);
2536 }
2537
2538 static void gen_spr_8xx (CPUPPCState *env)
2539 {
2540 /* XXX : not implemented */
2541 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2542 SPR_NOACCESS, SPR_NOACCESS,
2543 &spr_read_generic, &spr_write_generic,
2544 0x00000000);
2545 /* XXX : not implemented */
2546 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2547 SPR_NOACCESS, SPR_NOACCESS,
2548 &spr_read_generic, &spr_write_generic,
2549 0x00000000);
2550 /* XXX : not implemented */
2551 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2552 SPR_NOACCESS, SPR_NOACCESS,
2553 &spr_read_generic, &spr_write_generic,
2554 0x00000000);
2555 /* XXX : not implemented */
2556 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2557 SPR_NOACCESS, SPR_NOACCESS,
2558 &spr_read_generic, &spr_write_generic,
2559 0x00000000);
2560 /* XXX : not implemented */
2561 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2562 SPR_NOACCESS, SPR_NOACCESS,
2563 &spr_read_generic, &spr_write_generic,
2564 0x00000000);
2565 /* XXX : not implemented */
2566 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2567 SPR_NOACCESS, SPR_NOACCESS,
2568 &spr_read_generic, &spr_write_generic,
2569 0x00000000);
2570 /* XXX : not implemented */
2571 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2572 SPR_NOACCESS, SPR_NOACCESS,
2573 &spr_read_generic, &spr_write_generic,
2574 0x00000000);
2575 /* XXX : not implemented */
2576 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2577 SPR_NOACCESS, SPR_NOACCESS,
2578 &spr_read_generic, &spr_write_generic,
2579 0x00000000);
2580 /* XXX : not implemented */
2581 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2582 SPR_NOACCESS, SPR_NOACCESS,
2583 &spr_read_generic, &spr_write_generic,
2584 0x00000000);
2585 /* XXX : not implemented */
2586 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2587 SPR_NOACCESS, SPR_NOACCESS,
2588 &spr_read_generic, &spr_write_generic,
2589 0x00000000);
2590 /* XXX : not implemented */
2591 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2592 SPR_NOACCESS, SPR_NOACCESS,
2593 &spr_read_generic, &spr_write_generic,
2594 0x00000000);
2595 /* XXX : not implemented */
2596 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2597 SPR_NOACCESS, SPR_NOACCESS,
2598 &spr_read_generic, &spr_write_generic,
2599 0x00000000);
2600 /* XXX : not implemented */
2601 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2602 SPR_NOACCESS, SPR_NOACCESS,
2603 &spr_read_generic, &spr_write_generic,
2604 0x00000000);
2605 /* XXX : not implemented */
2606 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2607 SPR_NOACCESS, SPR_NOACCESS,
2608 &spr_read_generic, &spr_write_generic,
2609 0x00000000);
2610 /* XXX : not implemented */
2611 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2612 SPR_NOACCESS, SPR_NOACCESS,
2613 &spr_read_generic, &spr_write_generic,
2614 0x00000000);
2615 /* XXX : not implemented */
2616 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2617 SPR_NOACCESS, SPR_NOACCESS,
2618 &spr_read_generic, &spr_write_generic,
2619 0x00000000);
2620 /* XXX : not implemented */
2621 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2622 SPR_NOACCESS, SPR_NOACCESS,
2623 &spr_read_generic, &spr_write_generic,
2624 0x00000000);
2625 /* XXX : not implemented */
2626 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2627 SPR_NOACCESS, SPR_NOACCESS,
2628 &spr_read_generic, &spr_write_generic,
2629 0x00000000);
2630 /* XXX : not implemented */
2631 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2632 SPR_NOACCESS, SPR_NOACCESS,
2633 &spr_read_generic, &spr_write_generic,
2634 0x00000000);
2635 /* XXX : not implemented */
2636 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2637 SPR_NOACCESS, SPR_NOACCESS,
2638 &spr_read_generic, &spr_write_generic,
2639 0x00000000);
2640 /* XXX : not implemented */
2641 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2642 SPR_NOACCESS, SPR_NOACCESS,
2643 &spr_read_generic, &spr_write_generic,
2644 0x00000000);
2645 /* XXX : not implemented */
2646 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2647 SPR_NOACCESS, SPR_NOACCESS,
2648 &spr_read_generic, &spr_write_generic,
2649 0x00000000);
2650 /* XXX : not implemented */
2651 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2652 SPR_NOACCESS, SPR_NOACCESS,
2653 &spr_read_generic, &spr_write_generic,
2654 0x00000000);
2655 /* XXX : not implemented */
2656 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2657 SPR_NOACCESS, SPR_NOACCESS,
2658 &spr_read_generic, &spr_write_generic,
2659 0x00000000);
2660 /* XXX : not implemented */
2661 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2662 SPR_NOACCESS, SPR_NOACCESS,
2663 &spr_read_generic, &spr_write_generic,
2664 0x00000000);
2665 }
2666
2667 // XXX: TODO
2668 /*
2669 * AMR => SPR 29 (Power 2.04)
2670 * CTRL => SPR 136 (Power 2.04)
2671 * CTRL => SPR 152 (Power 2.04)
2672 * SCOMC => SPR 276 (64 bits ?)
2673 * SCOMD => SPR 277 (64 bits ?)
2674 * TBU40 => SPR 286 (Power 2.04 hypv)
2675 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2676 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2677 * HDSISR => SPR 306 (Power 2.04 hypv)
2678 * HDAR => SPR 307 (Power 2.04 hypv)
2679 * PURR => SPR 309 (Power 2.04 hypv)
2680 * HDEC => SPR 310 (Power 2.04 hypv)
2681 * HIOR => SPR 311 (hypv)
2682 * RMOR => SPR 312 (970)
2683 * HRMOR => SPR 313 (Power 2.04 hypv)
2684 * HSRR0 => SPR 314 (Power 2.04 hypv)
2685 * HSRR1 => SPR 315 (Power 2.04 hypv)
2686 * LPCR => SPR 316 (970)
2687 * LPIDR => SPR 317 (970)
2688 * EPR => SPR 702 (Power 2.04 emb)
2689 * perf => 768-783 (Power 2.04)
2690 * perf => 784-799 (Power 2.04)
2691 * PPR => SPR 896 (Power 2.04)
2692 * EPLC => SPR 947 (Power 2.04 emb)
2693 * EPSC => SPR 948 (Power 2.04 emb)
2694 * DABRX => 1015 (Power 2.04 hypv)
2695 * FPECR => SPR 1022 (?)
2696 * ... and more (thermal management, performance counters, ...)
2697 */
2698
2699 /*****************************************************************************/
2700 /* Exception vectors models */
2701 static void init_excp_4xx_real (CPUPPCState *env)
2702 {
2703 #if !defined(CONFIG_USER_ONLY)
2704 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2705 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2706 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2707 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2708 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2709 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2710 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2711 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2712 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2713 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2714 env->hreset_excp_prefix = 0x00000000UL;
2715 env->ivor_mask = 0x0000FFF0UL;
2716 env->ivpr_mask = 0xFFFF0000UL;
2717 /* Hardware reset vector */
2718 env->hreset_vector = 0xFFFFFFFCUL;
2719 #endif
2720 }
2721
2722 static void init_excp_4xx_softmmu (CPUPPCState *env)
2723 {
2724 #if !defined(CONFIG_USER_ONLY)
2725 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2726 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2727 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2728 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2729 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2730 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2731 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2732 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2733 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2734 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2735 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2736 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2737 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2738 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2739 env->hreset_excp_prefix = 0x00000000UL;
2740 env->ivor_mask = 0x0000FFF0UL;
2741 env->ivpr_mask = 0xFFFF0000UL;
2742 /* Hardware reset vector */
2743 env->hreset_vector = 0xFFFFFFFCUL;
2744 #endif
2745 }
2746
2747 static void init_excp_MPC5xx (CPUPPCState *env)
2748 {
2749 #if !defined(CONFIG_USER_ONLY)
2750 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2751 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2752 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2753 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2754 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2755 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2756 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2757 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2758 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2759 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2760 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2761 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2762 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2763 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2764 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2765 env->hreset_excp_prefix = 0x00000000UL;
2766 env->ivor_mask = 0x0000FFF0UL;
2767 env->ivpr_mask = 0xFFFF0000UL;
2768 /* Hardware reset vector */
2769 env->hreset_vector = 0xFFFFFFFCUL;
2770 #endif
2771 }
2772
2773 static void init_excp_MPC8xx (CPUPPCState *env)
2774 {
2775 #if !defined(CONFIG_USER_ONLY)
2776 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2777 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2778 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2779 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2780 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2781 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2782 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2783 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2784 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2785 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2786 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2787 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2788 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2789 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2790 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2791 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2792 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2793 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2794 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2795 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2796 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2797 env->hreset_excp_prefix = 0x00000000UL;
2798 env->ivor_mask = 0x0000FFF0UL;
2799 env->ivpr_mask = 0xFFFF0000UL;
2800 /* Hardware reset vector */
2801 env->hreset_vector = 0xFFFFFFFCUL;
2802 #endif
2803 }
2804
2805 static void init_excp_G2 (CPUPPCState *env)
2806 {
2807 #if !defined(CONFIG_USER_ONLY)
2808 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2809 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2810 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2811 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2812 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2813 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2814 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2815 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2816 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2817 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2818 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2819 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2820 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2821 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2822 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2823 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2824 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2825 env->hreset_excp_prefix = 0x00000000UL;
2826 /* Hardware reset vector */
2827 env->hreset_vector = 0xFFFFFFFCUL;
2828 #endif
2829 }
2830
2831 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2832 {
2833 #if !defined(CONFIG_USER_ONLY)
2834 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2835 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2836 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2837 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2838 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2839 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2840 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2841 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2842 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2843 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2844 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2845 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2846 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2847 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2848 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2849 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2850 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2851 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2852 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2853 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2854 env->hreset_excp_prefix = 0x00000000UL;
2855 env->ivor_mask = 0x0000FFF7UL;
2856 env->ivpr_mask = ivpr_mask;
2857 /* Hardware reset vector */
2858 env->hreset_vector = 0xFFFFFFFCUL;
2859 #endif
2860 }
2861
2862 static void init_excp_BookE (CPUPPCState *env)
2863 {
2864 #if !defined(CONFIG_USER_ONLY)
2865 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2866 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2867 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2868 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2869 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2870 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2871 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2872 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2873 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2874 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2875 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2876 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2877 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2878 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2879 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2880 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2881 env->hreset_excp_prefix = 0x00000000UL;
2882 env->ivor_mask = 0x0000FFE0UL;
2883 env->ivpr_mask = 0xFFFF0000UL;
2884 /* Hardware reset vector */
2885 env->hreset_vector = 0xFFFFFFFCUL;
2886 #endif
2887 }
2888
2889 static void init_excp_601 (CPUPPCState *env)
2890 {
2891 #if !defined(CONFIG_USER_ONLY)
2892 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2893 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2894 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2895 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2896 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2897 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2898 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2899 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2900 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2901 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2902 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2903 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2904 env->hreset_excp_prefix = 0xFFF00000UL;
2905 /* Hardware reset vector */
2906 env->hreset_vector = 0x00000100UL;
2907 #endif
2908 }
2909
2910 static void init_excp_602 (CPUPPCState *env)
2911 {
2912 #if !defined(CONFIG_USER_ONLY)
2913 /* XXX: exception prefix has a special behavior on 602 */
2914 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2915 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2916 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2917 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2918 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2919 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2920 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2921 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2922 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2923 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2924 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2925 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2926 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2927 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2928 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2929 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2930 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2931 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2932 env->hreset_excp_prefix = 0xFFF00000UL;
2933 /* Hardware reset vector */
2934 env->hreset_vector = 0xFFFFFFFCUL;
2935 #endif
2936 }
2937
2938 static void init_excp_603 (CPUPPCState *env)
2939 {
2940 #if !defined(CONFIG_USER_ONLY)
2941 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2942 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2943 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2944 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2945 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2946 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2947 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2948 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2949 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2950 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2951 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2952 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2953 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2954 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2955 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2956 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2957 env->hreset_excp_prefix = 0x00000000UL;
2958 /* Hardware reset vector */
2959 env->hreset_vector = 0xFFFFFFFCUL;
2960 #endif
2961 }
2962
2963 static void init_excp_604 (CPUPPCState *env)
2964 {
2965 #if !defined(CONFIG_USER_ONLY)
2966 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2967 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2968 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2969 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2970 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2971 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2972 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2973 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2974 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2975 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2976 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2977 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2978 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2979 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2980 env->hreset_excp_prefix = 0xFFF00000UL;
2981 /* Hardware reset vector */
2982 env->hreset_vector = 0x00000100UL;
2983 #endif
2984 }
2985
2986 #if defined(TARGET_PPC64)
2987 static void init_excp_620 (CPUPPCState *env)
2988 {
2989 #if !defined(CONFIG_USER_ONLY)
2990 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2991 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2992 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2993 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2994 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2995 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2996 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2997 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2998 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2999 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3000 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3001 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3002 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3003 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3004 env->hreset_excp_prefix = 0xFFF00000UL;
3005 /* Hardware reset vector */
3006 env->hreset_vector = 0x0000000000000100ULL;
3007 #endif
3008 }
3009 #endif /* defined(TARGET_PPC64) */
3010
3011 static void init_excp_7x0 (CPUPPCState *env)
3012 {
3013 #if !defined(CONFIG_USER_ONLY)
3014 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3015 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3016 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3017 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3018 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3019 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3020 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3021 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3022 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3023 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3024 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3025 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3026 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3027 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3028 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3029 env->hreset_excp_prefix = 0x00000000UL;
3030 /* Hardware reset vector */
3031 env->hreset_vector = 0xFFFFFFFCUL;
3032 #endif
3033 }
3034
3035 static void init_excp_750cl (CPUPPCState *env)
3036 {
3037 #if !defined(CONFIG_USER_ONLY)
3038 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3039 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3040 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3041 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3042 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3043 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3044 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3045 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3046 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3047 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3048 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3049 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3050 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3051 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3052 env->hreset_excp_prefix = 0x00000000UL;
3053 /* Hardware reset vector */
3054 env->hreset_vector = 0xFFFFFFFCUL;
3055 #endif
3056 }
3057
3058 static void init_excp_750cx (CPUPPCState *env)
3059 {
3060 #if !defined(CONFIG_USER_ONLY)
3061 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3062 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3063 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3064 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3065 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3066 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3067 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3068 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3069 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3070 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3071 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3072 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3073 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3074 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3075 env->hreset_excp_prefix = 0x00000000UL;
3076 /* Hardware reset vector */
3077 env->hreset_vector = 0xFFFFFFFCUL;
3078 #endif
3079 }
3080
3081 /* XXX: Check if this is correct */
3082 static void init_excp_7x5 (CPUPPCState *env)
3083 {
3084 #if !defined(CONFIG_USER_ONLY)
3085 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3086 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3087 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3088 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3089 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3090 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3091 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3092 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3093 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3094 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3095 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3096 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3097 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3098 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3099 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3100 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3101 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3102 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3103 env->hreset_excp_prefix = 0x00000000UL;
3104 /* Hardware reset vector */
3105 env->hreset_vector = 0xFFFFFFFCUL;
3106 #endif
3107 }
3108
3109 static void init_excp_7400 (CPUPPCState *env)
3110 {
3111 #if !defined(CONFIG_USER_ONLY)
3112 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3113 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3114 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3115 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3116 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3117 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3118 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3119 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3120 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3121 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3122 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3123 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3124 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3125 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3126 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3127 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3128 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3129 env->hreset_excp_prefix = 0x00000000UL;
3130 /* Hardware reset vector */
3131 env->hreset_vector = 0xFFFFFFFCUL;
3132 #endif
3133 }
3134
3135 static void init_excp_7450 (CPUPPCState *env)
3136 {
3137 #if !defined(CONFIG_USER_ONLY)
3138 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3139 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3140 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3141 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3142 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3143 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3144 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3145 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3146 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3147 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3148 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3149 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3150 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3151 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3152 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3153 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3154 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3155 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3156 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3157 env->hreset_excp_prefix = 0x00000000UL;
3158 /* Hardware reset vector */
3159 env->hreset_vector = 0xFFFFFFFCUL;
3160 #endif
3161 }
3162
3163 #if defined (TARGET_PPC64)
3164 static void init_excp_970 (CPUPPCState *env)
3165 {
3166 #if !defined(CONFIG_USER_ONLY)
3167 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3168 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3169 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3170 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3171 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3172 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3173 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3174 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3175 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3176 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3177 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3178 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3179 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3180 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3181 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3182 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3183 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3184 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3185 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3186 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3187 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
3188 /* Hardware reset vector */
3189 env->hreset_vector = 0x0000000000000100ULL;
3190 #endif
3191 }
3192
3193 static void init_excp_POWER7 (CPUPPCState *env)
3194 {
3195 #if !defined(CONFIG_USER_ONLY)
3196 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3197 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3198 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3199 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3200 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3201 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3202 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3203 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3204 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3205 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3206 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3207 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3208 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3209 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3210 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3211 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3212 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3213 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3214 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3215 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3216 env->hreset_excp_prefix = 0;
3217 /* Hardware reset vector */
3218 env->hreset_vector = 0x0000000000000100ULL;
3219 #endif
3220 }
3221 #endif
3222
3223 /*****************************************************************************/
3224 /* Power management enable checks */
3225 static int check_pow_none (CPUPPCState *env)
3226 {
3227 return 0;
3228 }
3229
3230 static int check_pow_nocheck (CPUPPCState *env)
3231 {
3232 return 1;
3233 }
3234
3235 static int check_pow_hid0 (CPUPPCState *env)
3236 {
3237 if (env->spr[SPR_HID0] & 0x00E00000)
3238 return 1;
3239
3240 return 0;
3241 }
3242
3243 static int check_pow_hid0_74xx (CPUPPCState *env)
3244 {
3245 if (env->spr[SPR_HID0] & 0x00600000)
3246 return 1;
3247
3248 return 0;
3249 }
3250
3251 /*****************************************************************************/
3252 /* PowerPC implementations definitions */
3253
3254 /* PowerPC 401 */
3255 #define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3256 PPC_WRTEE | PPC_DCR | \
3257 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3258 PPC_CACHE_DCBZ | \
3259 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3260 PPC_4xx_COMMON | PPC_40x_EXCP)
3261 #define POWERPC_INSNS2_401 (PPC_NONE)
3262 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
3263 #define POWERPC_MMU_401 (POWERPC_MMU_REAL)
3264 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3265 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
3266 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
3267 #define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3268 POWERPC_FLAG_BUS_CLK)
3269 #define check_pow_401 check_pow_nocheck
3270
3271 static void init_proc_401 (CPUPPCState *env)
3272 {
3273 gen_spr_40x(env);
3274 gen_spr_401_403(env);
3275 gen_spr_401(env);
3276 init_excp_4xx_real(env);
3277 env->dcache_line_size = 32;
3278 env->icache_line_size = 32;
3279 /* Allocate hardware IRQ controller */
3280 ppc40x_irq_init(env);
3281
3282 SET_FIT_PERIOD(12, 16, 20, 24);
3283 SET_WDT_PERIOD(16, 20, 24, 28);
3284 }
3285
3286 /* PowerPC 401x2 */
3287 #define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3288 PPC_DCR | PPC_WRTEE | \
3289 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3290 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3291 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3292 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3293 PPC_4xx_COMMON | PPC_40x_EXCP)
3294 #define POWERPC_INSNS2_401x2 (PPC_NONE)
3295 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3296 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3297 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3298 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
3299 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
3300 #define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3301 POWERPC_FLAG_BUS_CLK)
3302 #define check_pow_401x2 check_pow_nocheck
3303
3304 static void init_proc_401x2 (CPUPPCState *env)
3305 {
3306 gen_spr_40x(env);
3307 gen_spr_401_403(env);
3308 gen_spr_401x2(env);
3309 gen_spr_compress(env);
3310 /* Memory management */
3311 #if !defined(CONFIG_USER_ONLY)
3312 env->nb_tlb = 64;
3313 env->nb_ways = 1;
3314 env->id_tlbs = 0;
3315 env->tlb_type = TLB_EMB;
3316 #endif
3317 init_excp_4xx_softmmu(env);
3318 env->dcache_line_size = 32;
3319 env->icache_line_size = 32;
3320 /* Allocate hardware IRQ controller */
3321 ppc40x_irq_init(env);
3322
3323 SET_FIT_PERIOD(12, 16, 20, 24);
3324 SET_WDT_PERIOD(16, 20, 24, 28);
3325 }
3326
3327 /* PowerPC 401x3 */
3328 #define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3329 PPC_DCR | PPC_WRTEE | \
3330 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3331 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3332 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3333 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3334 PPC_4xx_COMMON | PPC_40x_EXCP)
3335 #define POWERPC_INSNS2_401x3 (PPC_NONE)
3336 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3337 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3338 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3339 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
3340 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
3341 #define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3342 POWERPC_FLAG_BUS_CLK)
3343 #define check_pow_401x3 check_pow_nocheck
3344
3345 __attribute__ (( unused ))
3346 static void init_proc_401x3 (CPUPPCState *env)
3347 {
3348 gen_spr_40x(env);
3349 gen_spr_401_403(env);
3350 gen_spr_401(env);
3351 gen_spr_401x2(env);
3352 gen_spr_compress(env);
3353 init_excp_4xx_softmmu(env);
3354 env->dcache_line_size = 32;
3355 env->icache_line_size = 32;
3356 /* Allocate hardware IRQ controller */
3357 ppc40x_irq_init(env);
3358
3359 SET_FIT_PERIOD(12, 16, 20, 24);
3360 SET_WDT_PERIOD(16, 20, 24, 28);
3361 }
3362
3363 /* IOP480 */
3364 #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3365 PPC_DCR | PPC_WRTEE | \
3366 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3367 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3368 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3369 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3370 PPC_4xx_COMMON | PPC_40x_EXCP)
3371 #define POWERPC_INSNS2_IOP480 (PPC_NONE)
3372 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3373 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3374 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3375 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
3376 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
3377 #define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3378 POWERPC_FLAG_BUS_CLK)
3379 #define check_pow_IOP480 check_pow_nocheck
3380
3381 static void init_proc_IOP480 (CPUPPCState *env)
3382 {
3383 gen_spr_40x(env);
3384 gen_spr_401_403(env);
3385 gen_spr_401x2(env);
3386 gen_spr_compress(env);
3387 /* Memory management */
3388 #if !defined(CONFIG_USER_ONLY)
3389 env->nb_tlb = 64;
3390 env->nb_ways = 1;
3391 env->id_tlbs = 0;
3392 env->tlb_type = TLB_EMB;
3393 #endif
3394 init_excp_4xx_softmmu(env);
3395 env->dcache_line_size = 32;
3396 env->icache_line_size = 32;
3397 /* Allocate hardware IRQ controller */
3398 ppc40x_irq_init(env);
3399
3400 SET_FIT_PERIOD(8, 12, 16, 20);
3401 SET_WDT_PERIOD(16, 20, 24, 28);
3402 }
3403
3404 /* PowerPC 403 */
3405 #define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3406 PPC_DCR | PPC_WRTEE | \
3407 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3408 PPC_CACHE_DCBZ | \
3409 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3410 PPC_4xx_COMMON | PPC_40x_EXCP)
3411 #define POWERPC_INSNS2_403 (PPC_NONE)
3412 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
3413 #define POWERPC_MMU_403 (POWERPC_MMU_REAL)
3414 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3415 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
3416 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
3417 #define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3418 POWERPC_FLAG_BUS_CLK)
3419 #define check_pow_403 check_pow_nocheck
3420
3421 static void init_proc_403 (CPUPPCState *env)
3422 {
3423 gen_spr_40x(env);
3424 gen_spr_401_403(env);
3425 gen_spr_403(env);
3426 gen_spr_403_real(env);
3427 init_excp_4xx_real(env);
3428 env->dcache_line_size = 32;
3429 env->icache_line_size = 32;
3430 /* Allocate hardware IRQ controller */
3431 ppc40x_irq_init(env);
3432
3433 SET_FIT_PERIOD(8, 12, 16, 20);
3434 SET_WDT_PERIOD(16, 20, 24, 28);
3435 }
3436
3437 /* PowerPC 403 GCX */
3438 #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3439 PPC_DCR | PPC_WRTEE | \
3440 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3441 PPC_CACHE_DCBZ | \
3442 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3443 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3444 PPC_4xx_COMMON | PPC_40x_EXCP)
3445 #define POWERPC_INSNS2_403GCX (PPC_NONE)
3446 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3447 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3448 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3449 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
3450 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
3451 #define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3452 POWERPC_FLAG_BUS_CLK)
3453 #define check_pow_403GCX check_pow_nocheck
3454
3455 static void init_proc_403GCX (CPUPPCState *env)
3456 {
3457 gen_spr_40x(env);
3458 gen_spr_401_403(env);
3459 gen_spr_403(env);
3460 gen_spr_403_real(env);
3461 gen_spr_403_mmu(env);
3462 /* Bus access control */
3463 /* not emulated, as QEMU never does speculative access */
3464 spr_register(env, SPR_40x_SGR, "SGR",
3465 SPR_NOACCESS, SPR_NOACCESS,
3466 &spr_read_generic, &spr_write_generic,
3467 0xFFFFFFFF);
3468 /* not emulated, as QEMU do not emulate caches */
3469 spr_register(env, SPR_40x_DCWR, "DCWR",
3470 SPR_NOACCESS, SPR_NOACCESS,
3471 &spr_read_generic, &spr_write_generic,
3472 0x00000000);
3473 /* Memory management */
3474 #if !defined(CONFIG_USER_ONLY)
3475 env->nb_tlb = 64;
3476 env->nb_ways = 1;
3477 env->id_tlbs = 0;
3478 env->tlb_type = TLB_EMB;
3479 #endif
3480 init_excp_4xx_softmmu(env);
3481 env->dcache_line_size = 32;
3482 env->icache_line_size = 32;
3483 /* Allocate hardware IRQ controller */
3484 ppc40x_irq_init(env);
3485
3486 SET_FIT_PERIOD(8, 12, 16, 20);
3487 SET_WDT_PERIOD(16, 20, 24, 28);
3488 }
3489
3490 /* PowerPC 405 */
3491 #define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3492 PPC_DCR | PPC_WRTEE | \
3493 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3494 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3495 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3496 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3497 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3498 #define POWERPC_INSNS2_405 (PPC_NONE)
3499 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
3500 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3501 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3502 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3503 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3504 #define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3505 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3506 #define check_pow_405 check_pow_nocheck
3507
3508 static void init_proc_405 (CPUPPCState *env)
3509 {
3510 /* Time base */
3511 gen_tbl(env);
3512 gen_spr_40x(env);
3513 gen_spr_405(env);
3514 /* Bus access control */
3515 /* not emulated, as QEMU never does speculative access */
3516 spr_register(env, SPR_40x_SGR, "SGR",
3517 SPR_NOACCESS, SPR_NOACCESS,
3518 &spr_read_generic, &spr_write_generic,
3519 0xFFFFFFFF);
3520 /* not emulated, as QEMU do not emulate caches */
3521 spr_register(env, SPR_40x_DCWR, "DCWR",
3522 SPR_NOACCESS, SPR_NOACCESS,
3523 &spr_read_generic, &spr_write_generic,
3524 0x00000000);
3525 /* Memory management */
3526 #if !defined(CONFIG_USER_ONLY)
3527 env->nb_tlb = 64;
3528 env->nb_ways = 1;
3529 env->id_tlbs = 0;
3530 env->tlb_type = TLB_EMB;
3531 #endif
3532 init_excp_4xx_softmmu(env);
3533 env->dcache_line_size = 32;
3534 env->icache_line_size = 32;
3535 /* Allocate hardware IRQ controller */
3536 ppc40x_irq_init(env);
3537
3538 SET_FIT_PERIOD(8, 12, 16, 20);
3539 SET_WDT_PERIOD(16, 20, 24, 28);
3540 }
3541
3542 /* PowerPC 440 EP */
3543 #define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3544 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3545 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3546 PPC_FLOAT_STFIWX | \
3547 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3548 PPC_CACHE | PPC_CACHE_ICBI | \
3549 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3550 PPC_MEM_TLBSYNC | PPC_MFTB | \
3551 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3552 PPC_440_SPEC)
3553 #define POWERPC_INSNS2_440EP (PPC_NONE)
3554 #define POWERPC_MSRM_440EP (0x000000000006FF30ULL)
3555 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3556 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3557 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3558 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3559 #define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3560 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3561 #define check_pow_440EP check_pow_nocheck
3562
3563 static void init_proc_440EP (CPUPPCState *env)
3564 {
3565 /* Time base */
3566 gen_tbl(env);
3567 gen_spr_BookE(env, 0x000000000000FFFFULL);
3568 gen_spr_440(env);
3569 gen_spr_usprgh(env);
3570 /* Processor identification */
3571 spr_register(env, SPR_BOOKE_PIR, "PIR",
3572 SPR_NOACCESS, SPR_NOACCESS,
3573 &spr_read_generic, &spr_write_pir,
3574 0x00000000);
3575 /* XXX : not implemented */
3576 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3577 SPR_NOACCESS, SPR_NOACCESS,
3578 &spr_read_generic, &spr_write_generic,
3579 0x00000000);
3580 /* XXX : not implemented */
3581 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3582 SPR_NOACCESS, SPR_NOACCESS,
3583 &spr_read_generic, &spr_write_generic,
3584 0x00000000);
3585 /* XXX : not implemented */
3586 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3587 SPR_NOACCESS, SPR_NOACCESS,
3588 &spr_read_generic, &spr_write_generic,
3589 0x00000000);
3590 /* XXX : not implemented */
3591 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3592 SPR_NOACCESS, SPR_NOACCESS,
3593 &spr_read_generic, &spr_write_generic,
3594 0x00000000);
3595 /* XXX : not implemented */
3596 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3597 SPR_NOACCESS, SPR_NOACCESS,
3598 &spr_read_generic, &spr_write_generic,
3599 0x00000000);
3600 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3601 SPR_NOACCESS, SPR_NOACCESS,
3602 &spr_read_generic, &spr_write_generic,
3603 0x00000000);
3604 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3605 SPR_NOACCESS, SPR_NOACCESS,
3606 &spr_read_generic, &spr_write_generic,
3607 0x00000000);
3608 /* XXX : not implemented */
3609 spr_register(env, SPR_440_CCR1, "CCR1",
3610 SPR_NOACCESS, SPR_NOACCESS,
3611 &spr_read_generic, &spr_write_generic,
3612 0x00000000);
3613 /* Memory management */
3614 #if !defined(CONFIG_USER_ONLY)
3615 env->nb_tlb = 64;
3616 env->nb_ways = 1;
3617 env->id_tlbs = 0;
3618 env->tlb_type = TLB_EMB;
3619 #endif
3620 init_excp_BookE(env);
3621 env->dcache_line_size = 32;
3622 env->icache_line_size = 32;
3623 ppc40x_irq_init(env);
3624
3625 SET_FIT_PERIOD(12, 16, 20, 24);
3626 SET_WDT_PERIOD(20, 24, 28, 32);
3627 }
3628
3629 /* PowerPC 440 GP */
3630 #define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3631 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3632 PPC_CACHE | PPC_CACHE_ICBI | \
3633 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3634 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \
3635 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3636 PPC_440_SPEC)
3637 #define POWERPC_INSNS2_440GP (PPC_NONE)
3638 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3639 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3640 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3641 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3642 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3643 #define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3644 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3645 #define check_pow_440GP check_pow_nocheck
3646
3647 __attribute__ (( unused ))
3648 static void init_proc_440GP (CPUPPCState *env)
3649 {
3650 /* Time base */
3651 gen_tbl(env);
3652 gen_spr_BookE(env, 0x000000000000FFFFULL);
3653 gen_spr_440(env);
3654 gen_spr_usprgh(env);
3655 /* Processor identification */
3656 spr_register(env, SPR_BOOKE_PIR, "PIR",
3657 SPR_NOACCESS, SPR_NOACCESS,
3658 &spr_read_generic, &spr_write_pir,
3659 0x00000000);
3660 /* XXX : not implemented */
3661 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3662 SPR_NOACCESS, SPR_NOACCESS,
3663 &spr_read_generic, &spr_write_generic,
3664 0x00000000);
3665 /* XXX : not implemented */
3666 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3667 SPR_NOACCESS, SPR_NOACCESS,
3668 &spr_read_generic, &spr_write_generic,
3669 0x00000000);
3670 /* XXX : not implemented */
3671 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3672 SPR_NOACCESS, SPR_NOACCESS,
3673 &spr_read_generic, &spr_write_generic,
3674 0x00000000);
3675 /* XXX : not implemented */
3676 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3677 SPR_NOACCESS, SPR_NOACCESS,
3678 &spr_read_generic, &spr_write_generic,
3679 0x00000000);
3680 /* Memory management */
3681 #if !defined(CONFIG_USER_ONLY)
3682 env->nb_tlb = 64;
3683 env->nb_ways = 1;
3684 env->id_tlbs = 0;
3685 env->tlb_type = TLB_EMB;
3686 #endif
3687 init_excp_BookE(env);
3688 env->dcache_line_size = 32;
3689 env->icache_line_size = 32;
3690 /* XXX: TODO: allocate internal IRQ controller */
3691
3692 SET_FIT_PERIOD(12, 16, 20, 24);
3693 SET_WDT_PERIOD(20, 24, 28, 32);
3694 }
3695
3696 /* PowerPC 440x4 */
3697 #define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3698 PPC_DCR | PPC_WRTEE | \
3699 PPC_CACHE | PPC_CACHE_ICBI | \
3700 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3701 PPC_MEM_TLBSYNC | PPC_MFTB | \
3702 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3703 PPC_440_SPEC)
3704 #define POWERPC_INSNS2_440x4 (PPC_NONE)
3705 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3706 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3707 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3708 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3709 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3710 #define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3711 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3712 #define check_pow_440x4 check_pow_nocheck
3713
3714 __attribute__ (( unused ))
3715 static void init_proc_440x4 (CPUPPCState *env)
3716 {
3717 /* Time base */
3718 gen_tbl(env);
3719 gen_spr_BookE(env, 0x000000000000FFFFULL);
3720 gen_spr_440(env);
3721 gen_spr_usprgh(env);
3722 /* Processor identification */
3723 spr_register(env, SPR_BOOKE_PIR, "PIR",
3724 SPR_NOACCESS, SPR_NOACCESS,
3725 &spr_read_generic, &spr_write_pir,
3726 0x00000000);
3727 /* XXX : not implemented */
3728 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3729 SPR_NOACCESS, SPR_NOACCESS,
3730 &spr_read_generic, &spr_write_generic,
3731 0x00000000);
3732 /* XXX : not implemented */
3733 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3734 SPR_NOACCESS, SPR_NOACCESS,
3735 &spr_read_generic, &spr_write_generic,
3736 0x00000000);
3737 /* XXX : not implemented */
3738 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3739 SPR_NOACCESS, SPR_NOACCESS,
3740 &spr_read_generic, &spr_write_generic,
3741 0x00000000);
3742 /* XXX : not implemented */
3743 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3744 SPR_NOACCESS, SPR_NOACCESS,
3745 &spr_read_generic, &spr_write_generic,
3746 0x00000000);
3747 /* Memory management */
3748 #if !defined(CONFIG_USER_ONLY)
3749 env->nb_tlb = 64;
3750 env->nb_ways = 1;
3751 env->id_tlbs = 0;
3752 env->tlb_type = TLB_EMB;
3753 #endif
3754 init_excp_BookE(env);
3755 env->dcache_line_size = 32;
3756 env->icache_line_size = 32;
3757 /* XXX: TODO: allocate internal IRQ controller */
3758
3759 SET_FIT_PERIOD(12, 16, 20, 24);
3760 SET_WDT_PERIOD(20, 24, 28, 32);
3761 }
3762
3763 /* PowerPC 440x5 */
3764 #define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3765 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3766 PPC_CACHE | PPC_CACHE_ICBI | \
3767 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3768 PPC_MEM_TLBSYNC | PPC_MFTB | \
3769 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3770 PPC_440_SPEC)
3771 #define POWERPC_INSNS2_440x5 (PPC_NONE)
3772 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3773 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3774 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3775 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3776 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3777 #define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3778 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3779 #define check_pow_440x5 check_pow_nocheck
3780
3781 static void init_proc_440x5 (CPUPPCState *env)
3782 {
3783 /* Time base */
3784 gen_tbl(env);
3785 gen_spr_BookE(env, 0x000000000000FFFFULL);
3786 gen_spr_440(env);
3787 gen_spr_usprgh(env);
3788 /* Processor identification */
3789 spr_register(env, SPR_BOOKE_PIR, "PIR",
3790 SPR_NOACCESS, SPR_NOACCESS,
3791 &spr_read_generic, &spr_write_pir,
3792 0x00000000);
3793 /* XXX : not implemented */
3794 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3795 SPR_NOACCESS, SPR_NOACCESS,
3796 &spr_read_generic, &spr_write_generic,
3797 0x00000000);
3798 /* XXX : not implemented */
3799 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3800 SPR_NOACCESS, SPR_NOACCESS,
3801 &spr_read_generic, &spr_write_generic,
3802 0x00000000);
3803 /* XXX : not implemented */
3804 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3805 SPR_NOACCESS, SPR_NOACCESS,
3806 &spr_read_generic, &spr_write_generic,
3807 0x00000000);
3808 /* XXX : not implemented */
3809 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3810 SPR_NOACCESS, SPR_NOACCESS,
3811 &spr_read_generic, &spr_write_generic,
3812 0x00000000);
3813 /* XXX : not implemented */
3814 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3815 SPR_NOACCESS, SPR_NOACCESS,
3816 &spr_read_generic, &spr_write_generic,
3817 0x00000000);
3818 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3819 SPR_NOACCESS, SPR_NOACCESS,
3820 &spr_read_generic, &spr_write_generic,
3821 0x00000000);
3822 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3823 SPR_NOACCESS, SPR_NOACCESS,
3824 &spr_read_generic, &spr_write_generic,
3825 0x00000000);
3826 /* XXX : not implemented */
3827 spr_register(env, SPR_440_CCR1, "CCR1",
3828 SPR_NOACCESS, SPR_NOACCESS,
3829 &spr_read_generic, &spr_write_generic,
3830 0x00000000);
3831 /* Memory management */
3832 #if !defined(CONFIG_USER_ONLY)
3833 env->nb_tlb = 64;
3834 env->nb_ways = 1;
3835 env->id_tlbs = 0;
3836 env->tlb_type = TLB_EMB;
3837 #endif
3838 init_excp_BookE(env);
3839 env->dcache_line_size = 32;
3840 env->icache_line_size = 32;
3841 ppc40x_irq_init(env);
3842
3843 SET_FIT_PERIOD(12, 16, 20, 24);
3844 SET_WDT_PERIOD(20, 24, 28, 32);
3845 }
3846
3847 /* PowerPC 460 (guessed) */
3848 #define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
3849 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3850 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | \
3851 PPC_CACHE | PPC_CACHE_ICBI | \
3852 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3853 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3854 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3855 PPC_440_SPEC)
3856 #define POWERPC_INSNS2_460 (PPC_NONE)
3857 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3858 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3859 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3860 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3861 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3862 #define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3863 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3864 #define check_pow_460 check_pow_nocheck
3865
3866 __attribute__ (( unused ))
3867 static void init_proc_460 (CPUPPCState *env)
3868 {
3869 /* Time base */
3870 gen_tbl(env);
3871 gen_spr_BookE(env, 0x000000000000FFFFULL);
3872 gen_spr_440(env);
3873 gen_spr_usprgh(env);
3874 /* Processor identification */
3875 spr_register(env, SPR_BOOKE_PIR, "PIR",
3876 SPR_NOACCESS, SPR_NOACCESS,
3877 &spr_read_generic, &spr_write_pir,
3878 0x00000000);
3879 /* XXX : not implemented */
3880 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3881 SPR_NOACCESS, SPR_NOACCESS,
3882 &spr_read_generic, &spr_write_generic,
3883 0x00000000);
3884 /* XXX : not implemented */
3885 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3886 SPR_NOACCESS, SPR_NOACCESS,
3887 &spr_read_generic, &spr_write_generic,
3888 0x00000000);
3889 /* XXX : not implemented */
3890 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3891 SPR_NOACCESS, SPR_NOACCESS,
3892 &spr_read_generic, &spr_write_generic,
3893 0x00000000);
3894 /* XXX : not implemented */
3895 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3896 SPR_NOACCESS, SPR_NOACCESS,
3897 &spr_read_generic, &spr_write_generic,
3898 0x00000000);
3899 /* XXX : not implemented */
3900 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3901 SPR_NOACCESS, SPR_NOACCESS,
3902 &spr_read_generic, &spr_write_generic,
3903 0x00000000);
3904 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3905 SPR_NOACCESS, SPR_NOACCESS,
3906 &spr_read_generic, &spr_write_generic,
3907 0x00000000);
3908 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3909 SPR_NOACCESS, SPR_NOACCESS,
3910 &spr_read_generic, &spr_write_generic,
3911 0x00000000);
3912 /* XXX : not implemented */
3913 spr_register(env, SPR_440_CCR1, "CCR1",
3914 SPR_NOACCESS, SPR_NOACCESS,
3915 &spr_read_generic, &spr_write_generic,
3916 0x00000000);
3917 /* XXX : not implemented */
3918 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3919 &spr_read_generic, &spr_write_generic,
3920 &spr_read_generic, &spr_write_generic,
3921 0x00000000);
3922 /* Memory management */
3923 #if !defined(CONFIG_USER_ONLY)
3924 env->nb_tlb = 64;
3925 env->nb_ways = 1;
3926 env->id_tlbs = 0;
3927 env->tlb_type = TLB_EMB;
3928 #endif
3929 init_excp_BookE(env);
3930 env->dcache_line_size = 32;
3931 env->icache_line_size = 32;
3932 /* XXX: TODO: allocate internal IRQ controller */
3933
3934 SET_FIT_PERIOD(12, 16, 20, 24);
3935 SET_WDT_PERIOD(20, 24, 28, 32);
3936 }
3937
3938 /* PowerPC 460F (guessed) */
3939 #define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3940 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3941 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3942 PPC_FLOAT_STFIWX | PPC_MFTB | \
3943 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3944 PPC_WRTEE | PPC_MFAPIDI | \
3945 PPC_CACHE | PPC_CACHE_ICBI | \
3946 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3947 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3948 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3949 PPC_440_SPEC)
3950 #define POWERPC_INSNS2_460F (PPC_NONE)
3951 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3952 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3953 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3954 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3955 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3956 #define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3957 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3958 #define check_pow_460F check_pow_nocheck
3959
3960 __attribute__ (( unused ))
3961 static void init_proc_460F (CPUPPCState *env)
3962 {
3963 /* Time base */
3964 gen_tbl(env);
3965 gen_spr_BookE(env, 0x000000000000FFFFULL);
3966 gen_spr_440(env);
3967 gen_spr_usprgh(env);
3968 /* Processor identification */
3969 spr_register(env, SPR_BOOKE_PIR, "PIR",
3970 SPR_NOACCESS, SPR_NOACCESS,
3971 &spr_read_generic, &spr_write_pir,
3972 0x00000000);
3973 /* XXX : not implemented */
3974 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3975 SPR_NOACCESS, SPR_NOACCESS,
3976 &spr_read_generic, &spr_write_generic,
3977 0x00000000);
3978 /* XXX : not implemented */
3979 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3980 SPR_NOACCESS, SPR_NOACCESS,
3981 &spr_read_generic, &spr_write_generic,
3982 0x00000000);
3983 /* XXX : not implemented */
3984 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3985 SPR_NOACCESS, SPR_NOACCESS,
3986 &spr_read_generic, &spr_write_generic,
3987 0x00000000);
3988 /* XXX : not implemented */
3989 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3990 SPR_NOACCESS, SPR_NOACCESS,
3991 &spr_read_generic, &spr_write_generic,
3992 0x00000000);
3993 /* XXX : not implemented */
3994 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3995 SPR_NOACCESS, SPR_NOACCESS,
3996 &spr_read_generic, &spr_write_generic,
3997 0x00000000);
3998 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3999 SPR_NOACCESS, SPR_NOACCESS,
4000 &spr_read_generic, &spr_write_generic,
4001 0x00000000);
4002 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4003 SPR_NOACCESS, SPR_NOACCESS,
4004 &spr_read_generic, &spr_write_generic,
4005 0x00000000);
4006 /* XXX : not implemented */
4007 spr_register(env, SPR_440_CCR1, "CCR1",
4008 SPR_NOACCESS, SPR_NOACCESS,
4009 &spr_read_generic, &spr_write_generic,
4010 0x00000000);
4011 /* XXX : not implemented */
4012 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4013 &spr_read_generic, &spr_write_generic,
4014 &spr_read_generic, &spr_write_generic,
4015 0x00000000);
4016 /* Memory management */
4017 #if !defined(CONFIG_USER_ONLY)
4018 env->nb_tlb = 64;
4019 env->nb_ways = 1;
4020 env->id_tlbs = 0;
4021 env->tlb_type = TLB_EMB;
4022 #endif
4023 init_excp_BookE(env);
4024 env->dcache_line_size = 32;
4025 env->icache_line_size = 32;
4026 /* XXX: TODO: allocate internal IRQ controller */
4027
4028 SET_FIT_PERIOD(12, 16, 20, 24);
4029 SET_WDT_PERIOD(20, 24, 28, 32);
4030 }
4031
4032 /* Freescale 5xx cores (aka RCPU) */
4033 #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
4034 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4035 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
4036 PPC_MFTB)
4037 #define POWERPC_INSNS2_MPC5xx (PPC_NONE)
4038 #define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
4039 #define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
4040 #define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
4041 #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
4042 #define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
4043 #define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4044 POWERPC_FLAG_BUS_CLK)
4045 #define check_pow_MPC5xx check_pow_none
4046
4047 __attribute__ (( unused ))
4048 static void init_proc_MPC5xx (CPUPPCState *env)
4049 {
4050 /* Time base */
4051 gen_tbl(env);
4052 gen_spr_5xx_8xx(env);
4053 gen_spr_5xx(env);
4054 init_excp_MPC5xx(env);
4055 env->dcache_line_size = 32;
4056 env->icache_line_size = 32;
4057 /* XXX: TODO: allocate internal IRQ controller */
4058 }
4059
4060 /* Freescale 8xx cores (aka PowerQUICC) */
4061 #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
4062 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4063 PPC_CACHE_ICBI | PPC_MFTB)
4064 #define POWERPC_INSNS2_MPC8xx (PPC_NONE)
4065 #define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
4066 #define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
4067 #define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
4068 #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
4069 #define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4070 #define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4071 POWERPC_FLAG_BUS_CLK)
4072 #define check_pow_MPC8xx check_pow_none
4073
4074 __attribute__ (( unused ))
4075 static void init_proc_MPC8xx (CPUPPCState *env)
4076 {
4077 /* Time base */
4078 gen_tbl(env);
4079 gen_spr_5xx_8xx(env);
4080 gen_spr_8xx(env);
4081 init_excp_MPC8xx(env);
4082 env->dcache_line_size = 32;
4083 env->icache_line_size = 32;
4084 /* XXX: TODO: allocate internal IRQ controller */
4085 }
4086
4087 /* Freescale 82xx cores (aka PowerQUICC-II) */
4088 /* PowerPC G2 */
4089 #define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4090 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4091 PPC_FLOAT_STFIWX | \
4092 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4093 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4094 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4095 PPC_SEGMENT | PPC_EXTERN)
4096 #define POWERPC_INSNS2_G2 (PPC_NONE)
4097 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
4098 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
4099 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
4100 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
4101 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
4102 #define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4103 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4104 #define check_pow_G2 check_pow_hid0
4105
4106 static void init_proc_G2 (CPUPPCState *env)
4107 {
4108 gen_spr_ne_601(env);
4109 gen_spr_G2_755(env);
4110 gen_spr_G2(env);
4111 /* Time base */
4112 gen_tbl(env);
4113 /* External access control */
4114 /* XXX : not implemented */
4115 spr_register(env, SPR_EAR, "EAR",
4116 SPR_NOACCESS, SPR_NOACCESS,
4117 &spr_read_generic, &spr_write_generic,
4118 0x00000000);
4119 /* Hardware implementation register */
4120 /* XXX : not implemented */
4121 spr_register(env, SPR_HID0, "HID0",
4122 SPR_NOACCESS, SPR_NOACCESS,
4123 &spr_read_generic, &spr_write_generic,
4124 0x00000000);
4125 /* XXX : not implemented */
4126 spr_register(env, SPR_HID1, "HID1",
4127 SPR_NOACCESS, SPR_NOACCESS,
4128 &spr_read_generic, &spr_write_generic,
4129 0x00000000);
4130 /* XXX : not implemented */
4131 spr_register(env, SPR_HID2, "HID2",
4132 SPR_NOACCESS, SPR_NOACCESS,
4133 &spr_read_generic, &spr_write_generic,
4134 0x00000000);
4135 /* Memory management */
4136 gen_low_BATs(env);
4137 gen_high_BATs(env);
4138 gen_6xx_7xx_soft_tlb(env, 64, 2);
4139 init_excp_G2(env);
4140 env->dcache_line_size = 32;
4141 env->icache_line_size = 32;
4142 /* Allocate hardware IRQ controller */
4143 ppc6xx_irq_init(env);
4144 }
4145
4146 /* PowerPC G2LE */
4147 #define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4148 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4149 PPC_FLOAT_STFIWX | \
4150 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4151 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4152 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4153 PPC_SEGMENT | PPC_EXTERN)
4154 #define POWERPC_INSNS2_G2LE (PPC_NONE)
4155 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
4156 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
4157 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
4158 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
4159 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
4160 #define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4161 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4162 #define check_pow_G2LE check_pow_hid0
4163
4164 static void init_proc_G2LE (CPUPPCState *env)
4165 {
4166 gen_spr_ne_601(env);
4167 gen_spr_G2_755(env);
4168 gen_spr_G2(env);
4169 /* Time base */
4170 gen_tbl(env);
4171 /* External access control */
4172 /* XXX : not implemented */
4173 spr_register(env, SPR_EAR, "EAR",
4174 SPR_NOACCESS, SPR_NOACCESS,
4175 &spr_read_generic, &spr_write_generic,
4176 0x00000000);
4177 /* Hardware implementation register */
4178 /* XXX : not implemented */
4179 spr_register(env, SPR_HID0, "HID0",
4180 SPR_NOACCESS, SPR_NOACCESS,
4181 &spr_read_generic, &spr_write_generic,
4182 0x00000000);
4183 /* XXX : not implemented */
4184 spr_register(env, SPR_HID1, "HID1",
4185 SPR_NOACCESS, SPR_NOACCESS,
4186 &spr_read_generic, &spr_write_generic,
4187 0x00000000);
4188 /* XXX : not implemented */
4189 spr_register(env, SPR_HID2, "HID2",
4190 SPR_NOACCESS, SPR_NOACCESS,
4191 &spr_read_generic, &spr_write_generic,
4192 0x00000000);
4193 /* Memory management */
4194 gen_low_BATs(env);
4195 gen_high_BATs(env);
4196 gen_6xx_7xx_soft_tlb(env, 64, 2);
4197 init_excp_G2(env);
4198 env->dcache_line_size = 32;
4199 env->icache_line_size = 32;
4200 /* Allocate hardware IRQ controller */
4201 ppc6xx_irq_init(env);
4202 }
4203
4204 /* e200 core */
4205 /* XXX: unimplemented instructions:
4206 * dcblc
4207 * dcbtlst
4208 * dcbtstls
4209 * icblc
4210 * icbtls
4211 * tlbivax
4212 * all SPE multiply-accumulate instructions
4213 */
4214 #define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
4215 PPC_SPE | PPC_SPE_SINGLE | \
4216 PPC_WRTEE | PPC_RFDI | \
4217 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4218 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4219 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4220 PPC_BOOKE)
4221 #define POWERPC_INSNS2_e200 (PPC_NONE)
4222 #define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
4223 #define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE206)
4224 #define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
4225 #define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
4226 #define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
4227 #define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4228 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4229 POWERPC_FLAG_BUS_CLK)
4230 #define check_pow_e200 check_pow_hid0
4231
4232 __attribute__ (( unused ))
4233 static void init_proc_e200 (CPUPPCState *env)
4234 {
4235 /* Time base */
4236 gen_tbl(env);
4237 gen_spr_BookE(env, 0x000000070000FFFFULL);
4238 /* XXX : not implemented */
4239 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4240 &spr_read_spefscr, &spr_write_spefscr,
4241 &spr_read_spefscr, &spr_write_spefscr,
4242 0x00000000);
4243 /* Memory management */
4244 gen_spr_BookE206(env, 0x0000005D, NULL);
4245 /* XXX : not implemented */
4246 spr_register(env, SPR_HID0, "HID0",
4247 SPR_NOACCESS, SPR_NOACCESS,
4248 &spr_read_generic, &spr_write_generic,
4249 0x00000000);
4250 /* XXX : not implemented */
4251 spr_register(env, SPR_HID1, "HID1",
4252 SPR_NOACCESS, SPR_NOACCESS,
4253 &spr_read_generic, &spr_write_generic,
4254 0x00000000);
4255 /* XXX : not implemented */
4256 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4257 SPR_NOACCESS, SPR_NOACCESS,
4258 &spr_read_generic, &spr_write_generic,
4259 0x00000000);
4260 /* XXX : not implemented */
4261 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4262 SPR_NOACCESS, SPR_NOACCESS,
4263 &spr_read_generic, &spr_write_generic,
4264 0x00000000);
4265 /* XXX : not implemented */
4266 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4267 SPR_NOACCESS, SPR_NOACCESS,
4268 &spr_read_generic, &spr_write_generic,
4269 0x00000000);
4270 /* XXX : not implemented */
4271 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4272 SPR_NOACCESS, SPR_NOACCESS,
4273 &spr_read_generic, &spr_write_generic,
4274 0x00000000);
4275 /* XXX : not implemented */
4276 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4277 SPR_NOACCESS, SPR_NOACCESS,
4278 &spr_read_generic, &spr_write_generic,
4279 0x00000000);
4280 /* XXX : not implemented */
4281 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4282 SPR_NOACCESS, SPR_NOACCESS,
4283 &spr_read_generic, &spr_write_generic,
4284 0x00000000);
4285 /* XXX : not implemented */
4286 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4287 SPR_NOACCESS, SPR_NOACCESS,
4288 &spr_read_generic, &spr_write_generic,
4289 0x00000000);
4290 /* XXX : not implemented */
4291 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4292 SPR_NOACCESS, SPR_NOACCESS,
4293 &spr_read_generic, &spr_write_generic,
4294 0x00000000);
4295 /* XXX : not implemented */
4296 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4297 SPR_NOACCESS, SPR_NOACCESS,
4298 &spr_read_generic, &spr_write_generic,
4299 0x00000000);
4300 /* XXX : not implemented */
4301 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4302 SPR_NOACCESS, SPR_NOACCESS,
4303 &spr_read_generic, &spr_write_generic,
4304 0x00000000);
4305 /* XXX : not implemented */
4306 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4307 SPR_NOACCESS, SPR_NOACCESS,
4308 &spr_read_generic, &spr_write_generic,
4309 0x00000000);
4310 /* XXX : not implemented */
4311 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4312 SPR_NOACCESS, SPR_NOACCESS,
4313 &spr_read_generic, &spr_write_generic,
4314 0x00000000);
4315 /* XXX : not implemented */
4316 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4317 SPR_NOACCESS, SPR_NOACCESS,
4318 &spr_read_generic, &spr_write_generic,
4319 0x00000000); /* TOFIX */
4320 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4321 SPR_NOACCESS, SPR_NOACCESS,
4322 &spr_read_generic, &spr_write_generic,
4323 0x00000000);
4324 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4325 SPR_NOACCESS, SPR_NOACCESS,
4326 &spr_read_generic, &spr_write_generic,
4327 0x00000000);
4328 #if !defined(CONFIG_USER_ONLY)
4329 env->nb_tlb = 64;
4330 env->nb_ways = 1;
4331 env->id_tlbs = 0;
4332 env->tlb_type = TLB_EMB;
4333 #endif
4334 init_excp_e200(env, 0xFFFF0000UL);
4335 env->dcache_line_size = 32;
4336 env->icache_line_size = 32;
4337 /* XXX: TODO: allocate internal IRQ controller */
4338 }
4339
4340 /* e300 core */
4341 #define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4342 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4343 PPC_FLOAT_STFIWX | \
4344 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4345 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4346 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4347 PPC_SEGMENT | PPC_EXTERN)
4348 #define POWERPC_INSNS2_e300 (PPC_NONE)
4349 #define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4350 #define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4351 #define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4352 #define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4353 #define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4354 #define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4355 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4356 #define check_pow_e300 check_pow_hid0
4357
4358 __attribute__ (( unused ))
4359 static void init_proc_e300 (CPUPPCState *env)
4360 {
4361 gen_spr_ne_601(env);
4362 gen_spr_603(env);
4363 /* Time base */
4364 gen_tbl(env);
4365 /* hardware implementation registers */
4366 /* XXX : not implemented */
4367 spr_register(env, SPR_HID0, "HID0",
4368 SPR_NOACCESS, SPR_NOACCESS,
4369 &spr_read_generic, &spr_write_generic,
4370 0x00000000);
4371 /* XXX : not implemented */
4372 spr_register(env, SPR_HID1, "HID1",
4373 SPR_NOACCESS, SPR_NOACCESS,
4374 &spr_read_generic, &spr_write_generic,
4375 0x00000000);
4376 /* XXX : not implemented */
4377 spr_register(env, SPR_HID2, "HID2",
4378 SPR_NOACCESS, SPR_NOACCESS,
4379 &spr_read_generic, &spr_write_generic,
4380 0x00000000);
4381 /* Memory management */
4382 gen_low_BATs(env);
4383 gen_high_BATs(env);
4384 gen_6xx_7xx_soft_tlb(env, 64, 2);
4385 init_excp_603(env);
4386 env->dcache_line_size = 32;
4387 env->icache_line_size = 32;
4388 /* Allocate hardware IRQ controller */
4389 ppc6xx_irq_init(env);
4390 }
4391
4392 /* e500v1 core */
4393 #define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
4394 PPC_SPE | PPC_SPE_SINGLE | \
4395 PPC_WRTEE | PPC_RFDI | \
4396 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4397 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4398 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
4399 #define POWERPC_INSNS2_e500v1 (PPC2_BOOKE206)
4400 #define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
4401 #define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206)
4402 #define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4403 #define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4404 #define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4405 #define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4406 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4407 POWERPC_FLAG_BUS_CLK)
4408 #define check_pow_e500v1 check_pow_hid0
4409 #define init_proc_e500v1 init_proc_e500v1
4410
4411 /* e500v2 core */
4412 #define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
4413 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
4414 PPC_WRTEE | PPC_RFDI | \
4415 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4416 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4417 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
4418 #define POWERPC_INSNS2_e500v2 (PPC2_BOOKE206)
4419 #define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
4420 #define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206)
4421 #define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4422 #define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4423 #define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4424 #define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4425 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4426 POWERPC_FLAG_BUS_CLK)
4427 #define check_pow_e500v2 check_pow_hid0
4428 #define init_proc_e500v2 init_proc_e500v2
4429
4430 /* e500mc core */
4431 #define POWERPC_INSNS_e500mc (PPC_INSNS_BASE | PPC_ISEL | \
4432 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | \
4433 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4434 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4435 PPC_FLOAT | PPC_FLOAT_FRES | \
4436 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
4437 PPC_FLOAT_STFIWX | PPC_WAIT | \
4438 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
4439 #define POWERPC_INSNS2_e500mc (PPC2_BOOKE206 | PPC2_PRCNTL)
4440 #define POWERPC_MSRM_e500mc (0x000000001402FB36ULL)
4441 #define POWERPC_MMU_e500mc (POWERPC_MMU_BOOKE206)
4442 #define POWERPC_EXCP_e500mc (POWERPC_EXCP_BOOKE)
4443 #define POWERPC_INPUT_e500mc (PPC_FLAGS_INPUT_BookE)
4444 /* Fixme: figure out the correct flag for e500mc */
4445 #define POWERPC_BFDM_e500mc (bfd_mach_ppc_e500)
4446 #define POWERPC_FLAG_e500mc (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
4447 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4448 #define check_pow_e500mc check_pow_none
4449 #define init_proc_e500mc init_proc_e500mc
4450
4451 /* e5500 core */
4452 #define POWERPC_INSNS_e5500 (PPC_INSNS_BASE | PPC_ISEL | \
4453 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | \
4454 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4455 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4456 PPC_FLOAT | PPC_FLOAT_FRES | \
4457 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
4458 PPC_FLOAT_STFIWX | PPC_WAIT | \
4459 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | \
4460 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD)
4461 #define POWERPC_INSNS2_e5500 (PPC2_BOOKE206 | PPC2_PRCNTL)
4462 #define POWERPC_MSRM_e5500 (0x000000009402FB36ULL)
4463 #define POWERPC_MMU_e5500 (POWERPC_MMU_BOOKE206)
4464 #define POWERPC_EXCP_e5500 (POWERPC_EXCP_BOOKE)
4465 #define POWERPC_INPUT_e5500 (PPC_FLAGS_INPUT_BookE)
4466 /* Fixme: figure out the correct flag for e5500 */
4467 #define POWERPC_BFDM_e5500 (bfd_mach_ppc_e500)
4468 #define POWERPC_FLAG_e5500 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
4469 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4470 #define check_pow_e5500 check_pow_none
4471 #define init_proc_e5500 init_proc_e5500
4472
4473 #if !defined(CONFIG_USER_ONLY)
4474 static void spr_write_mas73(void *opaque, int sprn, int gprn)
4475 {
4476 TCGv val = tcg_temp_new();
4477 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4478 gen_store_spr(SPR_BOOKE_MAS3, val);
4479 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4480 gen_store_spr(SPR_BOOKE_MAS7, val);
4481 tcg_temp_free(val);
4482 }
4483
4484 static void spr_read_mas73(void *opaque, int gprn, int sprn)
4485 {
4486 TCGv mas7 = tcg_temp_new();
4487 TCGv mas3 = tcg_temp_new();
4488 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4489 tcg_gen_shli_tl(mas7, mas7, 32);
4490 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4491 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4492 tcg_temp_free(mas3);
4493 tcg_temp_free(mas7);
4494 }
4495
4496 static void spr_load_epr(void *opaque, int gprn, int sprn)
4497 {
4498 gen_helper_load_epr(cpu_gpr[gprn], cpu_env);
4499 }
4500
4501 #endif
4502
4503 enum fsl_e500_version {
4504 fsl_e500v1,
4505 fsl_e500v2,
4506 fsl_e500mc,
4507 fsl_e5500,
4508 };
4509
4510 static void init_proc_e500 (CPUPPCState *env, int version)
4511 {
4512 uint32_t tlbncfg[2];
4513 uint64_t ivor_mask;
4514 uint64_t ivpr_mask = 0xFFFF0000ULL;
4515 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4516 | 0x0020; /* 32 kb */
4517 #if !defined(CONFIG_USER_ONLY)
4518 int i;
4519 #endif
4520
4521 /* Time base */
4522 gen_tbl(env);
4523 /*
4524 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4525 * complain when accessing them.
4526 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4527 */
4528 switch (version) {
4529 case fsl_e500v1:
4530 case fsl_e500v2:
4531 default:
4532 ivor_mask = 0x0000000F0000FFFFULL;
4533 break;
4534 case fsl_e500mc:
4535 case fsl_e5500:
4536 ivor_mask = 0x000003FE0000FFFFULL;
4537 break;
4538 }
4539 gen_spr_BookE(env, ivor_mask);
4540 /* Processor identification */
4541 spr_register(env, SPR_BOOKE_PIR, "PIR",
4542 SPR_NOACCESS, SPR_NOACCESS,
4543 &spr_read_generic, &spr_write_pir,
4544 0x00000000);
4545 /* XXX : not implemented */
4546 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4547 &spr_read_spefscr, &spr_write_spefscr,
4548 &spr_read_spefscr, &spr_write_spefscr,
4549 0x00000000);
4550 #if !defined(CONFIG_USER_ONLY)
4551 /* Memory management */
4552 env->nb_pids = 3;
4553 env->nb_ways = 2;
4554 env->id_tlbs = 0;
4555 switch (version) {
4556 case fsl_e500v1:
4557 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4558 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4559 break;
4560 case fsl_e500v2:
4561 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4562 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4563 break;
4564 case fsl_e500mc:
4565 case fsl_e5500:
4566 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4567 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4568 break;
4569 default:
4570 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4571 }
4572 #endif
4573 /* Cache sizes */
4574 switch (version) {
4575 case fsl_e500v1:
4576 case fsl_e500v2:
4577 env->dcache_line_size = 32;
4578 env->icache_line_size = 32;
4579 break;
4580 case fsl_e500mc:
4581 case fsl_e5500:
4582 env->dcache_line_size = 64;
4583 env->icache_line_size = 64;
4584 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4585 break;
4586 default:
4587 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4588 }
4589 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4590 /* XXX : not implemented */
4591 spr_register(env, SPR_HID0, "HID0",
4592 SPR_NOACCESS, SPR_NOACCESS,
4593 &spr_read_generic, &spr_write_generic,
4594 0x00000000);
4595 /* XXX : not implemented */
4596 spr_register(env, SPR_HID1, "HID1",
4597 SPR_NOACCESS, SPR_NOACCESS,
4598 &spr_read_generic, &spr_write_generic,
4599 0x00000000);
4600 /* XXX : not implemented */
4601 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4602 SPR_NOACCESS, SPR_NOACCESS,
4603 &spr_read_generic, &spr_write_generic,
4604 0x00000000);
4605 /* XXX : not implemented */
4606 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4607 SPR_NOACCESS, SPR_NOACCESS,
4608 &spr_read_generic, &spr_write_generic,
4609 0x00000000);
4610 /* XXX : not implemented */
4611 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4612 SPR_NOACCESS, SPR_NOACCESS,
4613 &spr_read_generic, &spr_write_generic,
4614 0x00000000);
4615 /* XXX : not implemented */
4616 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4617 SPR_NOACCESS, SPR_NOACCESS,
4618 &spr_read_generic, &spr_write_generic,
4619 0x00000000);
4620 /* XXX : not implemented */
4621 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4622 SPR_NOACCESS, SPR_NOACCESS,
4623 &spr_read_generic, &spr_write_generic,
4624 0x00000000);
4625 /* XXX : not implemented */
4626 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4627 SPR_NOACCESS, SPR_NOACCESS,
4628 &spr_read_generic, &spr_write_generic,
4629 0x00000000);
4630 /* XXX : not implemented */
4631 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4632 SPR_NOACCESS, SPR_NOACCESS,
4633 &spr_read_generic, &spr_write_generic,
4634 l1cfg0);
4635 /* XXX : not implemented */
4636 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4637 SPR_NOACCESS, SPR_NOACCESS,
4638 &spr_read_generic, &spr_write_e500_l1csr0,
4639 0x00000000);
4640 /* XXX : not implemented */
4641 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4642 SPR_NOACCESS, SPR_NOACCESS,
4643 &spr_read_generic, &spr_write_generic,
4644 0x00000000);
4645 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4646 SPR_NOACCESS, SPR_NOACCESS,
4647 &spr_read_generic, &spr_write_generic,
4648 0x00000000);
4649 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4650 SPR_NOACCESS, SPR_NOACCESS,
4651 &spr_read_generic, &spr_write_generic,
4652 0x00000000);
4653 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4654 SPR_NOACCESS, SPR_NOACCESS,
4655 &spr_read_generic, &spr_write_booke206_mmucsr0,
4656 0x00000000);
4657 spr_register(env, SPR_BOOKE_EPR, "EPR",
4658 SPR_NOACCESS, SPR_NOACCESS,
4659 &spr_load_epr, SPR_NOACCESS,
4660 0x00000000);
4661 /* XXX better abstract into Emb.xxx features */
4662 if (version == fsl_e5500) {
4663 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4664 SPR_NOACCESS, SPR_NOACCESS,
4665 &spr_read_generic, &spr_write_generic,
4666 0x00000000);
4667 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4668 SPR_NOACCESS, SPR_NOACCESS,
4669 &spr_read_mas73, &spr_write_mas73,
4670 0x00000000);
4671 ivpr_mask = (target_ulong)~0xFFFFULL;
4672 }
4673
4674 #if !defined(CONFIG_USER_ONLY)
4675 env->nb_tlb = 0;
4676 env->tlb_type = TLB_MAS;
4677 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4678 env->nb_tlb += booke206_tlb_size(env, i);
4679 }
4680 #endif
4681
4682 init_excp_e200(env, ivpr_mask);
4683 /* Allocate hardware IRQ controller */
4684 ppce500_irq_init(env);
4685 }
4686
4687 static void init_proc_e500v1(CPUPPCState *env)
4688 {
4689 init_proc_e500(env, fsl_e500v1);
4690 }
4691
4692 static void init_proc_e500v2(CPUPPCState *env)
4693 {
4694 init_proc_e500(env, fsl_e500v2);
4695 }
4696
4697 static void init_proc_e500mc(CPUPPCState *env)
4698 {
4699 init_proc_e500(env, fsl_e500mc);
4700 }
4701
4702 #ifdef TARGET_PPC64
4703 static void init_proc_e5500(CPUPPCState *env)
4704 {
4705 init_proc_e500(env, fsl_e5500);
4706 }
4707 #endif
4708
4709 /* Non-embedded PowerPC */
4710
4711 /* POWER : same as 601, without mfmsr, mfsr */
4712 #if defined(TODO)
4713 #define POWERPC_INSNS_POWER (XXX_TODO)
4714 /* POWER RSC (from RAD6000) */
4715 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4716 #endif /* TODO */
4717
4718 /* PowerPC 601 */
4719 #define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4720 PPC_FLOAT | \
4721 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4722 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4723 PPC_SEGMENT | PPC_EXTERN)
4724 #define POWERPC_INSNS2_601 (PPC_NONE)
4725 #define POWERPC_MSRM_601 (0x000000000000FD70ULL)
4726 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4727 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
4728 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4729 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
4730 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4731 #define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4732 #define check_pow_601 check_pow_none
4733
4734 static void init_proc_601 (CPUPPCState *env)
4735 {
4736 gen_spr_ne_601(env);
4737 gen_spr_601(env);
4738 /* Hardware implementation registers */
4739 /* XXX : not implemented */
4740 spr_register(env, SPR_HID0, "HID0",
4741 SPR_NOACCESS, SPR_NOACCESS,
4742 &spr_read_generic, &spr_write_hid0_601,
4743 0x80010080);
4744 /* XXX : not implemented */
4745 spr_register(env, SPR_HID1, "HID1",
4746 SPR_NOACCESS, SPR_NOACCESS,
4747 &spr_read_generic, &spr_write_generic,
4748 0x00000000);
4749 /* XXX : not implemented */
4750 spr_register(env, SPR_601_HID2, "HID2",
4751 SPR_NOACCESS, SPR_NOACCESS,
4752 &spr_read_generic, &spr_write_generic,
4753 0x00000000);
4754 /* XXX : not implemented */
4755 spr_register(env, SPR_601_HID5, "HID5",
4756 SPR_NOACCESS, SPR_NOACCESS,
4757 &spr_read_generic, &spr_write_generic,
4758 0x00000000);
4759 /* Memory management */
4760 init_excp_601(env);
4761 /* XXX: beware that dcache line size is 64
4762 * but dcbz uses 32 bytes "sectors"
4763 * XXX: this breaks clcs instruction !
4764 */
4765 env->dcache_line_size = 32;
4766 env->icache_line_size = 64;
4767 /* Allocate hardware IRQ controller */
4768 ppc6xx_irq_init(env);
4769 }
4770
4771 /* PowerPC 601v */
4772 #define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4773 PPC_FLOAT | \
4774 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4775 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4776 PPC_SEGMENT | PPC_EXTERN)
4777 #define POWERPC_INSNS2_601v (PPC_NONE)
4778 #define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4779 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4780 #define POWERPC_MMU_601v (POWERPC_MMU_601)
4781 #define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4782 #define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4783 #define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4784 #define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4785 #define check_pow_601v check_pow_none
4786
4787 static void init_proc_601v (CPUPPCState *env)
4788 {
4789 init_proc_601(env);
4790 /* XXX : not implemented */
4791 spr_register(env, SPR_601_HID15, "HID15",
4792 SPR_NOACCESS, SPR_NOACCESS,
4793 &spr_read_generic, &spr_write_generic,
4794 0x00000000);
4795 }
4796
4797 /* PowerPC 602 */
4798 #define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4799 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4800 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4801 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4802 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4803 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4804 PPC_SEGMENT | PPC_602_SPEC)
4805 #define POWERPC_INSNS2_602 (PPC_NONE)
4806 #define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4807 /* XXX: 602 MMU is quite specific. Should add a special case */
4808 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4809 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4810 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
4811 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
4812 #define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4813 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4814 #define check_pow_602 check_pow_hid0
4815
4816 static void init_proc_602 (CPUPPCState *env)
4817 {
4818 gen_spr_ne_601(env);
4819 gen_spr_602(env);
4820 /* Time base */
4821 gen_tbl(env);
4822 /* hardware implementation registers */
4823 /* XXX : not implemented */
4824 spr_register(env, SPR_HID0, "HID0",
4825 SPR_NOACCESS, SPR_NOACCESS,
4826 &spr_read_generic, &spr_write_generic,
4827 0x00000000);
4828 /* XXX : not implemented */
4829 spr_register(env, SPR_HID1, "HID1",
4830 SPR_NOACCESS, SPR_NOACCESS,
4831 &spr_read_generic, &spr_write_generic,
4832 0x00000000);
4833 /* Memory management */
4834 gen_low_BATs(env);
4835 gen_6xx_7xx_soft_tlb(env, 64, 2);
4836 init_excp_602(env);
4837 env->dcache_line_size = 32;
4838 env->icache_line_size = 32;
4839 /* Allocate hardware IRQ controller */
4840 ppc6xx_irq_init(env);
4841 }
4842
4843 /* PowerPC 603 */
4844 #define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4845 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4846 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4847 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4848 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4849 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4850 PPC_SEGMENT | PPC_EXTERN)
4851 #define POWERPC_INSNS2_603 (PPC_NONE)
4852 #define POWERPC_MSRM_603 (0x000000000007FF73ULL)
4853 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4854 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4855 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
4856 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
4857 #define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4858 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4859 #define check_pow_603 check_pow_hid0
4860
4861 static void init_proc_603 (CPUPPCState *env)
4862 {
4863 gen_spr_ne_601(env);
4864 gen_spr_603(env);
4865 /* Time base */
4866 gen_tbl(env);
4867 /* hardware implementation registers */
4868 /* XXX : not implemented */
4869 spr_register(env, SPR_HID0, "HID0",
4870 SPR_NOACCESS, SPR_NOACCESS,
4871 &spr_read_generic, &spr_write_generic,
4872 0x00000000);
4873 /* XXX : not implemented */
4874 spr_register(env, SPR_HID1, "HID1",
4875 SPR_NOACCESS, SPR_NOACCESS,
4876 &spr_read_generic, &spr_write_generic,
4877 0x00000000);
4878 /* Memory management */
4879 gen_low_BATs(env);
4880 gen_6xx_7xx_soft_tlb(env, 64, 2);
4881 init_excp_603(env);
4882 env->dcache_line_size = 32;
4883 env->icache_line_size = 32;
4884 /* Allocate hardware IRQ controller */
4885 ppc6xx_irq_init(env);
4886 }
4887
4888 /* PowerPC 603e */
4889 #define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4890 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4891 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4892 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4893 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4894 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4895 PPC_SEGMENT | PPC_EXTERN)
4896 #define POWERPC_INSNS2_603E (PPC_NONE)
4897 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4898 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4899 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4900 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
4901 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
4902 #define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4903 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4904 #define check_pow_603E check_pow_hid0
4905
4906 static void init_proc_603E (CPUPPCState *env)
4907 {
4908 gen_spr_ne_601(env);
4909 gen_spr_603(env);
4910 /* Time base */
4911 gen_tbl(env);
4912 /* hardware implementation registers */
4913 /* XXX : not implemented */
4914 spr_register(env, SPR_HID0, "HID0",
4915 SPR_NOACCESS, SPR_NOACCESS,
4916 &spr_read_generic, &spr_write_generic,
4917 0x00000000);
4918 /* XXX : not implemented */
4919 spr_register(env, SPR_HID1, "HID1",
4920 SPR_NOACCESS, SPR_NOACCESS,
4921 &spr_read_generic, &spr_write_generic,
4922 0x00000000);
4923 /* XXX : not implemented */
4924 spr_register(env, SPR_IABR, "IABR",
4925 SPR_NOACCESS, SPR_NOACCESS,
4926 &spr_read_generic, &spr_write_generic,
4927 0x00000000);
4928 /* Memory management */
4929 gen_low_BATs(env);
4930 gen_6xx_7xx_soft_tlb(env, 64, 2);
4931 init_excp_603(env);
4932 env->dcache_line_size = 32;
4933 env->icache_line_size = 32;
4934 /* Allocate hardware IRQ controller */
4935 ppc6xx_irq_init(env);
4936 }
4937
4938 /* PowerPC 604 */
4939 #define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4940 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4941 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4942 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4943 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4944 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4945 PPC_SEGMENT | PPC_EXTERN)
4946 #define POWERPC_INSNS2_604 (PPC_NONE)
4947 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4948 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
4949 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4950 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
4951 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
4952 #define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4953 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4954 #define check_pow_604 check_pow_nocheck
4955
4956 static void init_proc_604 (CPUPPCState *env)
4957 {
4958 gen_spr_ne_601(env);
4959 gen_spr_604(env);
4960 /* Time base */
4961 gen_tbl(env);
4962 /* Hardware implementation registers */
4963 /* XXX : not implemented */
4964 spr_register(env, SPR_HID0, "HID0",
4965 SPR_NOACCESS, SPR_NOACCESS,
4966 &spr_read_generic, &spr_write_generic,
4967 0x00000000);
4968 /* Memory management */
4969 gen_low_BATs(env);
4970 init_excp_604(env);
4971 env->dcache_line_size = 32;
4972 env->icache_line_size = 32;
4973 /* Allocate hardware IRQ controller */
4974 ppc6xx_irq_init(env);
4975 }
4976
4977 /* PowerPC 604E */
4978 #define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4979 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4980 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4981 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4982 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4983 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4984 PPC_SEGMENT | PPC_EXTERN)
4985 #define POWERPC_INSNS2_604E (PPC_NONE)
4986 #define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4987 #define POWERPC_MMU_604E (POWERPC_MMU_32B)
4988 #define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4989 #define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4990 #define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4991 #define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4992 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4993 #define check_pow_604E check_pow_nocheck
4994
4995 static void init_proc_604E (CPUPPCState *env)
4996 {
4997 gen_spr_ne_601(env);
4998 gen_spr_604(env);
4999 /* XXX : not implemented */
5000 spr_register(env, SPR_MMCR1, "MMCR1",
5001 SPR_NOACCESS, SPR_NOACCESS,
5002 &spr_read_generic, &spr_write_generic,
5003 0x00000000);
5004 /* XXX : not implemented */
5005 spr_register(env, SPR_PMC3, "PMC3",
5006 SPR_NOACCESS, SPR_NOACCESS,
5007 &spr_read_generic, &spr_write_generic,
5008 0x00000000);
5009 /* XXX : not implemented */
5010 spr_register(env, SPR_PMC4, "PMC4",
5011 SPR_NOACCESS, SPR_NOACCESS,
5012 &spr_read_generic, &spr_write_generic,
5013 0x00000000);
5014 /* Time base */
5015 gen_tbl(env);
5016 /* Hardware implementation registers */
5017 /* XXX : not implemented */
5018 spr_register(env, SPR_HID0, "HID0",
5019 SPR_NOACCESS, SPR_NOACCESS,
5020 &spr_read_generic, &spr_write_generic,
5021 0x00000000);
5022 /* XXX : not implemented */
5023 spr_register(env, SPR_HID1, "HID1",
5024 SPR_NOACCESS, SPR_NOACCESS,
5025 &spr_read_generic, &spr_write_generic,
5026 0x00000000);
5027 /* Memory management */
5028 gen_low_BATs(env);
5029 init_excp_604(env);
5030 env->dcache_line_size = 32;
5031 env->icache_line_size = 32;
5032 /* Allocate hardware IRQ controller */
5033 ppc6xx_irq_init(env);
5034 }
5035
5036 /* PowerPC 740 */
5037 #define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5038 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5039 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5040 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5041 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5042 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5043 PPC_SEGMENT | PPC_EXTERN)
5044 #define POWERPC_INSNS2_740 (PPC_NONE)
5045 #define POWERPC_MSRM_740 (0x000000000005FF77ULL)
5046 #define POWERPC_MMU_740 (POWERPC_MMU_32B)
5047 #define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
5048 #define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
5049 #define POWERPC_BFDM_740 (bfd_mach_ppc_750)
5050 #define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5051 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5052 #define check_pow_740 check_pow_hid0
5053
5054 static void init_proc_740 (CPUPPCState *env)
5055 {
5056 gen_spr_ne_601(env);
5057 gen_spr_7xx(env);
5058 /* Time base */
5059 gen_tbl(env);
5060 /* Thermal management */
5061 gen_spr_thrm(env);
5062 /* Hardware implementation registers */
5063 /* XXX : not implemented */
5064 spr_register(env, SPR_HID0, "HID0",
5065 SPR_NOACCESS, SPR_NOACCESS,
5066 &spr_read_generic, &spr_write_generic,
5067 0x00000000);
5068 /* XXX : not implemented */
5069 spr_register(env, SPR_HID1, "HID1",
5070 SPR_NOACCESS, SPR_NOACCESS,
5071 &spr_read_generic, &spr_write_generic,
5072 0x00000000);
5073 /* Memory management */
5074 gen_low_BATs(env);
5075 init_excp_7x0(env);
5076 env->dcache_line_size = 32;
5077 env->icache_line_size = 32;
5078 /* Allocate hardware IRQ controller */
5079 ppc6xx_irq_init(env);
5080 }
5081
5082 /* PowerPC 750 */
5083 #define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5084 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5085 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5086 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5087 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5088 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5089 PPC_SEGMENT | PPC_EXTERN)
5090 #define POWERPC_INSNS2_750 (PPC_NONE)
5091 #define POWERPC_MSRM_750 (0x000000000005FF77ULL)
5092 #define POWERPC_MMU_750 (POWERPC_MMU_32B)
5093 #define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
5094 #define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
5095 #define POWERPC_BFDM_750 (bfd_mach_ppc_750)
5096 #define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5097 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5098 #define check_pow_750 check_pow_hid0
5099
5100 static void init_proc_750 (CPUPPCState *env)
5101 {
5102 gen_spr_ne_601(env);
5103 gen_spr_7xx(env);
5104 /* XXX : not implemented */
5105 spr_register(env, SPR_L2CR, "L2CR",
5106 SPR_NOACCESS, SPR_NOACCESS,
5107 &spr_read_generic, &spr_write_generic,
5108 0x00000000);
5109 /* Time base */
5110 gen_tbl(env);
5111 /* Thermal management */
5112 gen_spr_thrm(env);
5113 /* Hardware implementation registers */
5114 /* XXX : not implemented */
5115 spr_register(env, SPR_HID0, "HID0",
5116 SPR_NOACCESS, SPR_NOACCESS,
5117 &spr_read_generic, &spr_write_generic,
5118 0x00000000);
5119 /* XXX : not implemented */
5120 spr_register(env, SPR_HID1, "HID1",
5121 SPR_NOACCESS, SPR_NOACCESS,
5122 &spr_read_generic, &spr_write_generic,
5123 0x00000000);
5124 /* Memory management */
5125 gen_low_BATs(env);
5126 /* XXX: high BATs are also present but are known to be bugged on
5127 * die version 1.x
5128 */
5129 init_excp_7x0(env);
5130 env->dcache_line_size = 32;
5131 env->icache_line_size = 32;
5132 /* Allocate hardware IRQ controller */
5133 ppc6xx_irq_init(env);
5134 }
5135
5136 /* PowerPC 750 CL */
5137 /* XXX: not implemented:
5138 * cache lock instructions:
5139 * dcbz_l
5140 * floating point paired instructions
5141 * psq_lux
5142 * psq_lx
5143 * psq_stux
5144 * psq_stx
5145 * ps_abs
5146 * ps_add
5147 * ps_cmpo0
5148 * ps_cmpo1
5149 * ps_cmpu0
5150 * ps_cmpu1
5151 * ps_div
5152 * ps_madd
5153 * ps_madds0
5154 * ps_madds1
5155 * ps_merge00
5156 * ps_merge01
5157 * ps_merge10
5158 * ps_merge11
5159 * ps_mr
5160 * ps_msub
5161 * ps_mul
5162 * ps_muls0
5163 * ps_muls1
5164 * ps_nabs
5165 * ps_neg
5166 * ps_nmadd
5167 * ps_nmsub
5168 * ps_res
5169 * ps_rsqrte
5170 * ps_sel
5171 * ps_sub
5172 * ps_sum0
5173 * ps_sum1
5174 */
5175 #define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5176 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5177 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5178 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5179 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5180 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5181 PPC_SEGMENT | PPC_EXTERN)
5182 #define POWERPC_INSNS2_750cl (PPC_NONE)
5183 #define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
5184 #define POWERPC_MMU_750cl (POWERPC_MMU_32B)
5185 #define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
5186 #define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
5187 #define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
5188 #define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5189 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5190 #define check_pow_750cl check_pow_hid0
5191
5192 static void init_proc_750cl (CPUPPCState *env)
5193 {
5194 gen_spr_ne_601(env);
5195 gen_spr_7xx(env);
5196 /* XXX : not implemented */
5197 spr_register(env, SPR_L2CR, "L2CR",
5198 SPR_NOACCESS, SPR_NOACCESS,
5199 &spr_read_generic, &spr_write_generic,
5200 0x00000000);
5201 /* Time base */
5202 gen_tbl(env);
5203 /* Thermal management */
5204 /* Those registers are fake on 750CL */
5205 spr_register(env, SPR_THRM1, "THRM1",
5206 SPR_NOACCESS, SPR_NOACCESS,
5207 &spr_read_generic, &spr_write_generic,
5208 0x00000000);
5209 spr_register(env, SPR_THRM2, "THRM2",
5210 SPR_NOACCESS, SPR_NOACCESS,
5211 &spr_read_generic, &spr_write_generic,
5212 0x00000000);
5213 spr_register(env, SPR_THRM3, "THRM3",
5214 SPR_NOACCESS, SPR_NOACCESS,
5215 &spr_read_generic, &spr_write_generic,
5216 0x00000000);
5217 /* XXX: not implemented */
5218 spr_register(env, SPR_750_TDCL, "TDCL",
5219 SPR_NOACCESS, SPR_NOACCESS,
5220 &spr_read_generic, &spr_write_generic,
5221 0x00000000);
5222 spr_register(env, SPR_750_TDCH, "TDCH",
5223 SPR_NOACCESS, SPR_NOACCESS,
5224 &spr_read_generic, &spr_write_generic,
5225 0x00000000);
5226 /* DMA */
5227 /* XXX : not implemented */
5228 spr_register(env, SPR_750_WPAR, "WPAR",
5229 SPR_NOACCESS, SPR_NOACCESS,
5230 &spr_read_generic, &spr_write_generic,
5231 0x00000000);
5232 spr_register(env, SPR_750_DMAL, "DMAL",
5233 SPR_NOACCESS, SPR_NOACCESS,
5234 &spr_read_generic, &spr_write_generic,
5235 0x00000000);
5236 spr_register(env, SPR_750_DMAU, "DMAU",
5237 SPR_NOACCESS, SPR_NOACCESS,
5238 &spr_read_generic, &spr_write_generic,
5239 0x00000000);
5240 /* Hardware implementation registers */
5241 /* XXX : not implemented */
5242 spr_register(env, SPR_HID0, "HID0",
5243 SPR_NOACCESS, SPR_NOACCESS,
5244 &spr_read_generic, &spr_write_generic,
5245 0x00000000);
5246 /* XXX : not implemented */
5247 spr_register(env, SPR_HID1, "HID1",
5248 SPR_NOACCESS, SPR_NOACCESS,
5249 &spr_read_generic, &spr_write_generic,
5250 0x00000000);
5251 /* XXX : not implemented */
5252 spr_register(env, SPR_750CL_HID2, "HID2",
5253 SPR_NOACCESS, SPR_NOACCESS,
5254 &spr_read_generic, &spr_write_generic,
5255 0x00000000);
5256 /* XXX : not implemented */
5257 spr_register(env, SPR_750CL_HID4, "HID4",
5258 SPR_NOACCESS, SPR_NOACCESS,
5259 &spr_read_generic, &spr_write_generic,
5260 0x00000000);
5261 /* Quantization registers */
5262 /* XXX : not implemented */
5263 spr_register(env, SPR_750_GQR0, "GQR0",
5264 SPR_NOACCESS, SPR_NOACCESS,
5265 &spr_read_generic, &spr_write_generic,
5266 0x00000000);
5267 /* XXX : not implemented */
5268 spr_register(env, SPR_750_GQR1, "GQR1",
5269 SPR_NOACCESS, SPR_NOACCESS,
5270 &spr_read_generic, &spr_write_generic,
5271 0x00000000);
5272 /* XXX : not implemented */
5273 spr_register(env, SPR_750_GQR2, "GQR2",
5274 SPR_NOACCESS, SPR_NOACCESS,
5275 &spr_read_generic, &spr_write_generic,
5276 0x00000000);
5277 /* XXX : not implemented */
5278 spr_register(env, SPR_750_GQR3, "GQR3",
5279 SPR_NOACCESS, SPR_NOACCESS,
5280 &spr_read_generic, &spr_write_generic,
5281 0x00000000);
5282 /* XXX : not implemented */
5283 spr_register(env, SPR_750_GQR4, "GQR4",
5284 SPR_NOACCESS, SPR_NOACCESS,
5285 &spr_read_generic, &spr_write_generic,
5286 0x00000000);
5287 /* XXX : not implemented */
5288 spr_register(env, SPR_750_GQR5, "GQR5",
5289 SPR_NOACCESS, SPR_NOACCESS,
5290 &spr_read_generic, &spr_write_generic,
5291 0x00000000);
5292 /* XXX : not implemented */
5293 spr_register(env, SPR_750_GQR6, "GQR6",
5294 SPR_NOACCESS, SPR_NOACCESS,
5295 &spr_read_generic, &spr_write_generic,
5296 0x00000000);
5297 /* XXX : not implemented */
5298 spr_register(env, SPR_750_GQR7, "GQR7",
5299 SPR_NOACCESS, SPR_NOACCESS,
5300 &spr_read_generic, &spr_write_generic,
5301 0x00000000);
5302 /* Memory management */
5303 gen_low_BATs(env);
5304 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5305 gen_high_BATs(env);
5306 init_excp_750cl(env);
5307 env->dcache_line_size = 32;
5308 env->icache_line_size = 32;
5309 /* Allocate hardware IRQ controller */
5310 ppc6xx_irq_init(env);
5311 }
5312
5313 /* PowerPC 750CX */
5314 #define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5315 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5316 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5317 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5318 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5319 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5320 PPC_SEGMENT | PPC_EXTERN)
5321 #define POWERPC_INSNS2_750cx (PPC_NONE)
5322 #define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
5323 #define POWERPC_MMU_750cx (POWERPC_MMU_32B)
5324 #define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
5325 #define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
5326 #define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
5327 #define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5328 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5329 #define check_pow_750cx check_pow_hid0
5330
5331 static void init_proc_750cx (CPUPPCState *env)
5332 {
5333 gen_spr_ne_601(env);
5334 gen_spr_7xx(env);
5335 /* XXX : not implemented */
5336 spr_register(env, SPR_L2CR, "L2CR",
5337 SPR_NOACCESS, SPR_NOACCESS,
5338 &spr_read_generic, &spr_write_generic,
5339 0x00000000);
5340 /* Time base */
5341 gen_tbl(env);
5342 /* Thermal management */
5343 gen_spr_thrm(env);
5344 /* This register is not implemented but is present for compatibility */
5345 spr_register(env, SPR_SDA, "SDA",
5346 SPR_NOACCESS, SPR_NOACCESS,
5347 &spr_read_generic, &spr_write_generic,
5348 0x00000000);
5349 /* Hardware implementation registers */
5350 /* XXX : not implemented */
5351 spr_register(env, SPR_HID0, "HID0",
5352 SPR_NOACCESS, SPR_NOACCESS,
5353 &spr_read_generic, &spr_write_generic,
5354 0x00000000);
5355 /* XXX : not implemented */
5356 spr_register(env, SPR_HID1, "HID1",
5357 SPR_NOACCESS, SPR_NOACCESS,
5358 &spr_read_generic, &spr_write_generic,
5359 0x00000000);
5360 /* Memory management */
5361 gen_low_BATs(env);
5362 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5363 gen_high_BATs(env);
5364 init_excp_750cx(env);
5365 env->dcache_line_size = 32;
5366 env->icache_line_size = 32;
5367 /* Allocate hardware IRQ controller */
5368 ppc6xx_irq_init(env);
5369 }
5370
5371 /* PowerPC 750FX */
5372 #define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5373 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5374 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5375 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5376 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5377 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5378 PPC_SEGMENT | PPC_EXTERN)
5379 #define POWERPC_INSNS2_750fx (PPC_NONE)
5380 #define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
5381 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
5382 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
5383 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
5384 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
5385 #define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5386 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5387 #define check_pow_750fx check_pow_hid0
5388
5389 static void init_proc_750fx (CPUPPCState *env)
5390 {
5391 gen_spr_ne_601(env);
5392 gen_spr_7xx(env);
5393 /* XXX : not implemented */
5394 spr_register(env, SPR_L2CR, "L2CR",
5395 SPR_NOACCESS, SPR_NOACCESS,
5396 &spr_read_generic, &spr_write_generic,
5397 0x00000000);
5398 /* Time base */
5399 gen_tbl(env);
5400 /* Thermal management */
5401 gen_spr_thrm(env);
5402 /* XXX : not implemented */
5403 spr_register(env, SPR_750_THRM4, "THRM4",
5404 SPR_NOACCESS, SPR_NOACCESS,
5405 &spr_read_generic, &spr_write_generic,
5406 0x00000000);
5407 /* Hardware implementation registers */
5408 /* XXX : not implemented */
5409 spr_register(env, SPR_HID0, "HID0",
5410 SPR_NOACCESS, SPR_NOACCESS,
5411 &spr_read_generic, &spr_write_generic,
5412 0x00000000);
5413 /* XXX : not implemented */
5414 spr_register(env, SPR_HID1, "HID1",
5415 SPR_NOACCESS, SPR_NOACCESS,
5416 &spr_read_generic, &spr_write_generic,
5417 0x00000000);
5418 /* XXX : not implemented */
5419 spr_register(env, SPR_750FX_HID2, "HID2",
5420 SPR_NOACCESS, SPR_NOACCESS,
5421 &spr_read_generic, &spr_write_generic,
5422 0x00000000);
5423 /* Memory management */
5424 gen_low_BATs(env);
5425 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5426 gen_high_BATs(env);
5427 init_excp_7x0(env);
5428 env->dcache_line_size = 32;
5429 env->icache_line_size = 32;
5430 /* Allocate hardware IRQ controller */
5431 ppc6xx_irq_init(env);
5432 }
5433
5434 /* PowerPC 750GX */
5435 #define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5436 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5437 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5438 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5439 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5440 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5441 PPC_SEGMENT | PPC_EXTERN)
5442 #define POWERPC_INSNS2_750gx (PPC_NONE)
5443 #define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5444 #define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5445 #define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5446 #define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5447 #define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5448 #define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5449 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5450 #define check_pow_750gx check_pow_hid0
5451
5452 static void init_proc_750gx (CPUPPCState *env)
5453 {
5454 gen_spr_ne_601(env);
5455 gen_spr_7xx(env);
5456 /* XXX : not implemented (XXX: different from 750fx) */
5457 spr_register(env, SPR_L2CR, "L2CR",
5458 SPR_NOACCESS, SPR_NOACCESS,
5459 &spr_read_generic, &spr_write_generic,
5460 0x00000000);
5461 /* Time base */
5462 gen_tbl(env);
5463 /* Thermal management */
5464 gen_spr_thrm(env);
5465 /* XXX : not implemented */
5466 spr_register(env, SPR_750_THRM4, "THRM4",
5467 SPR_NOACCESS, SPR_NOACCESS,
5468 &spr_read_generic, &spr_write_generic,
5469 0x00000000);
5470 /* Hardware implementation registers */
5471 /* XXX : not implemented (XXX: different from 750fx) */
5472 spr_register(env, SPR_HID0, "HID0",
5473 SPR_NOACCESS, SPR_NOACCESS,
5474 &spr_read_generic, &spr_write_generic,
5475 0x00000000);
5476 /* XXX : not implemented */
5477 spr_register(env, SPR_HID1, "HID1",
5478 SPR_NOACCESS, SPR_NOACCESS,
5479 &spr_read_generic, &spr_write_generic,
5480 0x00000000);
5481 /* XXX : not implemented (XXX: different from 750fx) */
5482 spr_register(env, SPR_750FX_HID2, "HID2",
5483 SPR_NOACCESS, SPR_NOACCESS,
5484 &spr_read_generic, &spr_write_generic,
5485 0x00000000);
5486 /* Memory management */
5487 gen_low_BATs(env);
5488 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5489 gen_high_BATs(env);
5490 init_excp_7x0(env);
5491 env->dcache_line_size = 32;
5492 env->icache_line_size = 32;
5493 /* Allocate hardware IRQ controller */
5494 ppc6xx_irq_init(env);
5495 }
5496
5497 /* PowerPC 745 */
5498 #define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5499 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5500 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5501 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5502 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5503 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5504 PPC_SEGMENT | PPC_EXTERN)
5505 #define POWERPC_INSNS2_745 (PPC_NONE)
5506 #define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5507 #define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5508 #define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5509 #define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5510 #define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5511 #define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5512 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5513 #define check_pow_745 check_pow_hid0
5514
5515 static void init_proc_745 (CPUPPCState *env)
5516 {
5517 gen_spr_ne_601(env);
5518 gen_spr_7xx(env);
5519 gen_spr_G2_755(env);
5520 /* Time base */
5521 gen_tbl(env);
5522 /* Thermal management */
5523 gen_spr_thrm(env);
5524 /* Hardware implementation registers */
5525 /* XXX : not implemented */
5526 spr_register(env, SPR_HID0, "HID0",
5527 SPR_NOACCESS, SPR_NOACCESS,
5528 &spr_read_generic, &spr_write_generic,
5529 0x00000000);
5530 /* XXX : not implemented */
5531 spr_register(env, SPR_HID1, "HID1",
5532 SPR_NOACCESS, SPR_NOACCESS,
5533 &spr_read_generic, &spr_write_generic,
5534 0x00000000);
5535 /* XXX : not implemented */
5536 spr_register(env, SPR_HID2, "HID2",
5537 SPR_NOACCESS, SPR_NOACCESS,
5538 &spr_read_generic, &spr_write_generic,
5539 0x00000000);
5540 /* Memory management */
5541 gen_low_BATs(env);
5542 gen_high_BATs(env);
5543 gen_6xx_7xx_soft_tlb(env, 64, 2);
5544 init_excp_7x5(env);
5545 env->dcache_line_size = 32;
5546 env->icache_line_size = 32;
5547 /* Allocate hardware IRQ controller */
5548 ppc6xx_irq_init(env);
5549 }
5550
5551 /* PowerPC 755 */
5552 #define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5553 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5554 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5555 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5556 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5557 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5558 PPC_SEGMENT | PPC_EXTERN)
5559 #define POWERPC_INSNS2_755 (PPC_NONE)
5560 #define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5561 #define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5562 #define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5563 #define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5564 #define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5565 #define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5566 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5567 #define check_pow_755 check_pow_hid0
5568
5569 static void init_proc_755 (CPUPPCState *env)
5570 {
5571 gen_spr_ne_601(env);
5572 gen_spr_7xx(env);
5573 gen_spr_G2_755(env);
5574 /* Time base */
5575 gen_tbl(env);
5576 /* L2 cache control */
5577 /* XXX : not implemented */
5578 spr_register(env, SPR_L2CR, "L2CR",
5579 SPR_NOACCESS, SPR_NOACCESS,
5580 &spr_read_generic, &spr_write_generic,
5581 0x00000000);
5582 /* XXX : not implemented */
5583 spr_register(env, SPR_L2PMCR, "L2PMCR",
5584 SPR_NOACCESS, SPR_NOACCESS,
5585 &spr_read_generic, &spr_write_generic,
5586 0x00000000);
5587 /* Thermal management */
5588 gen_spr_thrm(env);
5589 /* Hardware implementation registers */
5590 /* XXX : not implemented */
5591 spr_register(env, SPR_HID0, "HID0",
5592 SPR_NOACCESS, SPR_NOACCESS,
5593 &spr_read_generic, &spr_write_generic,
5594 0x00000000);
5595 /* XXX : not implemented */
5596 spr_register(env, SPR_HID1, "HID1",
5597 SPR_NOACCESS, SPR_NOACCESS,
5598 &spr_read_generic, &spr_write_generic,
5599 0x00000000);
5600 /* XXX : not implemented */
5601 spr_register(env, SPR_HID2, "HID2",
5602 SPR_NOACCESS, SPR_NOACCESS,
5603 &spr_read_generic, &spr_write_generic,
5604 0x00000000);
5605 /* Memory management */
5606 gen_low_BATs(env);
5607 gen_high_BATs(env);
5608 gen_6xx_7xx_soft_tlb(env, 64, 2);
5609 init_excp_7x5(env);
5610 env->dcache_line_size = 32;
5611 env->icache_line_size = 32;
5612 /* Allocate hardware IRQ controller */
5613 ppc6xx_irq_init(env);
5614 }
5615
5616 /* PowerPC 7400 (aka G4) */
5617 #define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5618 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5619 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5620 PPC_FLOAT_STFIWX | \
5621 PPC_CACHE | PPC_CACHE_ICBI | \
5622 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5623 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5624 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5625 PPC_MEM_TLBIA | \
5626 PPC_SEGMENT | PPC_EXTERN | \
5627 PPC_ALTIVEC)
5628 #define POWERPC_INSNS2_7400 (PPC_NONE)
5629 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5630 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5631 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5632 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
5633 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
5634 #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5635 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5636 POWERPC_FLAG_BUS_CLK)
5637 #define check_pow_7400 check_pow_hid0
5638
5639 static void init_proc_7400 (CPUPPCState *env)
5640 {
5641 gen_spr_ne_601(env);
5642 gen_spr_7xx(env);
5643 /* Time base */
5644 gen_tbl(env);
5645 /* 74xx specific SPR */
5646 gen_spr_74xx(env);
5647 /* XXX : not implemented */
5648 spr_register(env, SPR_UBAMR, "UBAMR",
5649 &spr_read_ureg, SPR_NOACCESS,
5650 &spr_read_ureg, SPR_NOACCESS,
5651 0x00000000);
5652 /* XXX: this seems not implemented on all revisions. */
5653 /* XXX : not implemented */
5654 spr_register(env, SPR_MSSCR1, "MSSCR1",
5655 SPR_NOACCESS, SPR_NOACCESS,
5656 &spr_read_generic, &spr_write_generic,
5657 0x00000000);
5658 /* Thermal management */
5659 gen_spr_thrm(env);
5660 /* Memory management */
5661 gen_low_BATs(env);
5662 init_excp_7400(env);
5663 env->dcache_line_size = 32;
5664 env->icache_line_size = 32;
5665 /* Allocate hardware IRQ controller */
5666 ppc6xx_irq_init(env);
5667 }
5668
5669 /* PowerPC 7410 (aka G4) */
5670 #define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5671 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5672 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5673 PPC_FLOAT_STFIWX | \
5674 PPC_CACHE | PPC_CACHE_ICBI | \
5675 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5676 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5677 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5678 PPC_MEM_TLBIA | \
5679 PPC_SEGMENT | PPC_EXTERN | \
5680 PPC_ALTIVEC)
5681 #define POWERPC_INSNS2_7410 (PPC_NONE)
5682 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5683 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5684 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5685 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
5686 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
5687 #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5688 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5689 POWERPC_FLAG_BUS_CLK)
5690 #define check_pow_7410 check_pow_hid0
5691
5692 static void init_proc_7410 (CPUPPCState *env)
5693 {
5694 gen_spr_ne_601(env);
5695 gen_spr_7xx(env);
5696 /* Time base */
5697 gen_tbl(env);
5698 /* 74xx specific SPR */
5699 gen_spr_74xx(env);
5700 /* XXX : not implemented */
5701 spr_register(env, SPR_UBAMR, "UBAMR",
5702 &spr_read_ureg, SPR_NOACCESS,
5703 &spr_read_ureg, SPR_NOACCESS,
5704 0x00000000);
5705 /* Thermal management */
5706 gen_spr_thrm(env);
5707 /* L2PMCR */
5708 /* XXX : not implemented */
5709 spr_register(env, SPR_L2PMCR, "L2PMCR",
5710 SPR_NOACCESS, SPR_NOACCESS,
5711 &spr_read_generic, &spr_write_generic,
5712 0x00000000);
5713 /* LDSTDB */
5714 /* XXX : not implemented */
5715 spr_register(env, SPR_LDSTDB, "LDSTDB",
5716 SPR_NOACCESS, SPR_NOACCESS,
5717 &spr_read_generic, &spr_write_generic,
5718 0x00000000);
5719 /* Memory management */
5720 gen_low_BATs(env);
5721 init_excp_7400(env);
5722 env->dcache_line_size = 32;
5723 env->icache_line_size = 32;
5724 /* Allocate hardware IRQ controller */
5725 ppc6xx_irq_init(env);
5726 }
5727
5728 /* PowerPC 7440 (aka G4) */
5729 #define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5730 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5731 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5732 PPC_FLOAT_STFIWX | \
5733 PPC_CACHE | PPC_CACHE_ICBI | \
5734 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5735 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5736 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5737 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5738 PPC_SEGMENT | PPC_EXTERN | \
5739 PPC_ALTIVEC)
5740 #define POWERPC_INSNS2_7440 (PPC_NONE)
5741 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5742 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5743 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5744 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
5745 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
5746 #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5747 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5748 POWERPC_FLAG_BUS_CLK)
5749 #define check_pow_7440 check_pow_hid0_74xx
5750
5751 __attribute__ (( unused ))
5752 static void init_proc_7440 (CPUPPCState *env)
5753 {
5754 gen_spr_ne_601(env);
5755 gen_spr_7xx(env);
5756 /* Time base */
5757 gen_tbl(env);
5758 /* 74xx specific SPR */
5759 gen_spr_74xx(env);
5760 /* XXX : not implemented */
5761 spr_register(env, SPR_UBAMR, "UBAMR",
5762 &spr_read_ureg, SPR_NOACCESS,
5763 &spr_read_ureg, SPR_NOACCESS,
5764 0x00000000);
5765 /* LDSTCR */
5766 /* XXX : not implemented */
5767 spr_register(env, SPR_LDSTCR, "LDSTCR",
5768 SPR_NOACCESS, SPR_NOACCESS,
5769 &spr_read_generic, &spr_write_generic,
5770 0x00000000);
5771 /* ICTRL */
5772 /* XXX : not implemented */
5773 spr_register(env, SPR_ICTRL, "ICTRL",
5774 SPR_NOACCESS, SPR_NOACCESS,
5775 &spr_read_generic, &spr_write_generic,
5776 0x00000000);
5777 /* MSSSR0 */
5778 /* XXX : not implemented */
5779 spr_register(env, SPR_MSSSR0, "MSSSR0",
5780 SPR_NOACCESS, SPR_NOACCESS,
5781 &spr_read_generic, &spr_write_generic,
5782 0x00000000);
5783 /* PMC */
5784 /* XXX : not implemented */
5785 spr_register(env, SPR_PMC5, "PMC5",
5786 SPR_NOACCESS, SPR_NOACCESS,
5787 &spr_read_generic, &spr_write_generic,
5788 0x00000000);
5789 /* XXX : not implemented */
5790 spr_register(env, SPR_UPMC5, "UPMC5",
5791 &spr_read_ureg, SPR_NOACCESS,
5792 &spr_read_ureg, SPR_NOACCESS,
5793 0x00000000);
5794 /* XXX : not implemented */
5795 spr_register(env, SPR_PMC6, "PMC6",
5796 SPR_NOACCESS, SPR_NOACCESS,
5797 &spr_read_generic, &spr_write_generic,
5798 0x00000000);
5799 /* XXX : not implemented */
5800 spr_register(env, SPR_UPMC6, "UPMC6",
5801 &spr_read_ureg, SPR_NOACCESS,
5802 &spr_read_ureg, SPR_NOACCESS,
5803 0x00000000);
5804 /* Memory management */
5805 gen_low_BATs(env);
5806 gen_74xx_soft_tlb(env, 128, 2);
5807 init_excp_7450(env);
5808 env->dcache_line_size = 32;
5809 env->icache_line_size = 32;
5810 /* Allocate hardware IRQ controller */
5811 ppc6xx_irq_init(env);
5812 }
5813
5814 /* PowerPC 7450 (aka G4) */
5815 #define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5816 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5817 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5818 PPC_FLOAT_STFIWX | \
5819 PPC_CACHE | PPC_CACHE_ICBI | \
5820 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5821 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5822 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5823 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5824 PPC_SEGMENT | PPC_EXTERN | \
5825 PPC_ALTIVEC)
5826 #define POWERPC_INSNS2_7450 (PPC_NONE)
5827 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5828 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5829 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5830 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
5831 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
5832 #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5833 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5834 POWERPC_FLAG_BUS_CLK)
5835 #define check_pow_7450 check_pow_hid0_74xx
5836
5837 __attribute__ (( unused ))
5838 static void init_proc_7450 (CPUPPCState *env)
5839 {
5840 gen_spr_ne_601(env);
5841 gen_spr_7xx(env);
5842 /* Time base */
5843 gen_tbl(env);
5844 /* 74xx specific SPR */
5845 gen_spr_74xx(env);
5846 /* Level 3 cache control */
5847 gen_l3_ctrl(env);
5848 /* L3ITCR1 */
5849 /* XXX : not implemented */
5850 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5851 SPR_NOACCESS, SPR_NOACCESS,
5852 &spr_read_generic, &spr_write_generic,
5853 0x00000000);
5854 /* L3ITCR2 */
5855 /* XXX : not implemented */
5856 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5857 SPR_NOACCESS, SPR_NOACCESS,
5858 &spr_read_generic, &spr_write_generic,
5859 0x00000000);
5860 /* L3ITCR3 */
5861 /* XXX : not implemented */
5862 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5863 SPR_NOACCESS, SPR_NOACCESS,
5864 &spr_read_generic, &spr_write_generic,
5865 0x00000000);
5866 /* L3OHCR */
5867 /* XXX : not implemented */
5868 spr_register(env, SPR_L3OHCR, "L3OHCR",
5869 SPR_NOACCESS, SPR_NOACCESS,
5870 &spr_read_generic, &spr_write_generic,
5871 0x00000000);
5872 /* XXX : not implemented */
5873 spr_register(env, SPR_UBAMR, "UBAMR",
5874 &spr_read_ureg, SPR_NOACCESS,
5875 &spr_read_ureg, SPR_NOACCESS,
5876 0x00000000);
5877 /* LDSTCR */
5878 /* XXX : not implemented */
5879 spr_register(env, SPR_LDSTCR, "LDSTCR",
5880 SPR_NOACCESS, SPR_NOACCESS,
5881 &spr_read_generic, &spr_write_generic,
5882 0x00000000);
5883 /* ICTRL */
5884 /* XXX : not implemented */
5885 spr_register(env, SPR_ICTRL, "ICTRL",
5886 SPR_NOACCESS, SPR_NOACCESS,
5887 &spr_read_generic, &spr_write_generic,
5888 0x00000000);
5889 /* MSSSR0 */
5890 /* XXX : not implemented */
5891 spr_register(env, SPR_MSSSR0, "MSSSR0",
5892 SPR_NOACCESS, SPR_NOACCESS,
5893 &spr_read_generic, &spr_write_generic,
5894 0x00000000);
5895 /* PMC */
5896 /* XXX : not implemented */
5897 spr_register(env, SPR_PMC5, "PMC5",
5898 SPR_NOACCESS, SPR_NOACCESS,
5899 &spr_read_generic, &spr_write_generic,
5900 0x00000000);
5901 /* XXX : not implemented */
5902 spr_register(env, SPR_UPMC5, "UPMC5",
5903 &spr_read_ureg, SPR_NOACCESS,
5904 &spr_read_ureg, SPR_NOACCESS,
5905 0x00000000);
5906 /* XXX : not implemented */
5907 spr_register(env, SPR_PMC6, "PMC6",
5908 SPR_NOACCESS, SPR_NOACCESS,
5909 &spr_read_generic, &spr_write_generic,
5910 0x00000000);
5911 /* XXX : not implemented */
5912 spr_register(env, SPR_UPMC6, "UPMC6",
5913 &spr_read_ureg, SPR_NOACCESS,
5914 &spr_read_ureg, SPR_NOACCESS,
5915 0x00000000);
5916 /* Memory management */
5917 gen_low_BATs(env);
5918 gen_74xx_soft_tlb(env, 128, 2);
5919 init_excp_7450(env);
5920 env->dcache_line_size = 32;
5921 env->icache_line_size = 32;
5922 /* Allocate hardware IRQ controller */
5923 ppc6xx_irq_init(env);
5924 }
5925
5926 /* PowerPC 7445 (aka G4) */
5927 #define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5928 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5929 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5930 PPC_FLOAT_STFIWX | \
5931 PPC_CACHE | PPC_CACHE_ICBI | \
5932 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5933 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5934 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5935 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5936 PPC_SEGMENT | PPC_EXTERN | \
5937 PPC_ALTIVEC)
5938 #define POWERPC_INSNS2_7445 (PPC_NONE)
5939 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5940 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5941 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5942 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
5943 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
5944 #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5945 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5946 POWERPC_FLAG_BUS_CLK)
5947 #define check_pow_7445 check_pow_hid0_74xx
5948
5949 __attribute__ (( unused ))
5950 static void init_proc_7445 (CPUPPCState *env)
5951 {
5952 gen_spr_ne_601(env);
5953 gen_spr_7xx(env);
5954 /* Time base */
5955 gen_tbl(env);
5956 /* 74xx specific SPR */
5957 gen_spr_74xx(env);
5958 /* LDSTCR */
5959 /* XXX : not implemented */
5960 spr_register(env, SPR_LDSTCR, "LDSTCR",
5961 SPR_NOACCESS, SPR_NOACCESS,
5962 &spr_read_generic, &spr_write_generic,
5963 0x00000000);
5964 /* ICTRL */
5965 /* XXX : not implemented */
5966 spr_register(env, SPR_ICTRL, "ICTRL",
5967 SPR_NOACCESS, SPR_NOACCESS,
5968 &spr_read_generic, &spr_write_generic,
5969 0x00000000);
5970 /* MSSSR0 */
5971 /* XXX : not implemented */
5972 spr_register(env, SPR_MSSSR0, "MSSSR0",
5973 SPR_NOACCESS, SPR_NOACCESS,
5974 &spr_read_generic, &spr_write_generic,
5975 0x00000000);
5976 /* PMC */
5977 /* XXX : not implemented */
5978 spr_register(env, SPR_PMC5, "PMC5",
5979 SPR_NOACCESS, SPR_NOACCESS,
5980 &spr_read_generic, &spr_write_generic,
5981 0x00000000);
5982 /* XXX : not implemented */
5983 spr_register(env, SPR_UPMC5, "UPMC5",
5984 &spr_read_ureg, SPR_NOACCESS,
5985 &spr_read_ureg, SPR_NOACCESS,
5986 0x00000000);
5987 /* XXX : not implemented */
5988 spr_register(env, SPR_PMC6, "PMC6",
5989 SPR_NOACCESS, SPR_NOACCESS,
5990 &spr_read_generic, &spr_write_generic,
5991 0x00000000);
5992 /* XXX : not implemented */
5993 spr_register(env, SPR_UPMC6, "UPMC6",
5994 &spr_read_ureg, SPR_NOACCESS,
5995 &spr_read_ureg, SPR_NOACCESS,
5996 0x00000000);
5997 /* SPRGs */
5998 spr_register(env, SPR_SPRG4, "SPRG4",
5999 SPR_NOACCESS, SPR_NOACCESS,
6000 &spr_read_generic, &spr_write_generic,
6001 0x00000000);
6002 spr_register(env, SPR_USPRG4, "USPRG4",
6003 &spr_read_ureg, SPR_NOACCESS,
6004 &spr_read_ureg, SPR_NOACCESS,
6005 0x00000000);
6006 spr_register(env, SPR_SPRG5, "SPRG5",
6007 SPR_NOACCESS, SPR_NOACCESS,
6008 &spr_read_generic, &spr_write_generic,
6009 0x00000000);
6010 spr_register(env, SPR_USPRG5, "USPRG5",
6011 &spr_read_ureg, SPR_NOACCESS,
6012 &spr_read_ureg, SPR_NOACCESS,
6013 0x00000000);
6014 spr_register(env, SPR_SPRG6, "SPRG6",
6015 SPR_NOACCESS, SPR_NOACCESS,
6016 &spr_read_generic, &spr_write_generic,
6017 0x00000000);
6018 spr_register(env, SPR_USPRG6, "USPRG6",
6019 &spr_read_ureg, SPR_NOACCESS,
6020 &spr_read_ureg, SPR_NOACCESS,
6021 0x00000000);
6022 spr_register(env, SPR_SPRG7, "SPRG7",
6023 SPR_NOACCESS, SPR_NOACCESS,
6024 &spr_read_generic, &spr_write_generic,
6025 0x00000000);
6026 spr_register(env, SPR_USPRG7, "USPRG7",
6027 &spr_read_ureg, SPR_NOACCESS,
6028 &spr_read_ureg, SPR_NOACCESS,
6029 0x00000000);
6030 /* Memory management */
6031 gen_low_BATs(env);
6032 gen_high_BATs(env);
6033 gen_74xx_soft_tlb(env, 128, 2);
6034 init_excp_7450(env);
6035 env->dcache_line_size = 32;
6036 env->icache_line_size = 32;
6037 /* Allocate hardware IRQ controller */
6038 ppc6xx_irq_init(env);
6039 }
6040
6041 /* PowerPC 7455 (aka G4) */
6042 #define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6043 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6044 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6045 PPC_FLOAT_STFIWX | \
6046 PPC_CACHE | PPC_CACHE_ICBI | \
6047 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
6048 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6049 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6050 PPC_MEM_TLBIA | PPC_74xx_TLB | \
6051 PPC_SEGMENT | PPC_EXTERN | \
6052 PPC_ALTIVEC)
6053 #define POWERPC_INSNS2_7455 (PPC_NONE)
6054 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
6055 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
6056 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
6057 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
6058 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
6059 #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6060 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6061 POWERPC_FLAG_BUS_CLK)
6062 #define check_pow_7455 check_pow_hid0_74xx
6063
6064 __attribute__ (( unused ))
6065 static void init_proc_7455 (CPUPPCState *env)
6066 {
6067 gen_spr_ne_601(env);
6068 gen_spr_7xx(env);
6069 /* Time base */
6070 gen_tbl(env);
6071 /* 74xx specific SPR */
6072 gen_spr_74xx(env);
6073 /* Level 3 cache control */
6074 gen_l3_ctrl(env);
6075 /* LDSTCR */
6076 /* XXX : not implemented */
6077 spr_register(env, SPR_LDSTCR, "LDSTCR",
6078 SPR_NOACCESS, SPR_NOACCESS,
6079 &spr_read_generic, &spr_write_generic,
6080 0x00000000);
6081 /* ICTRL */
6082 /* XXX : not implemented */
6083 spr_register(env, SPR_ICTRL, "ICTRL",
6084 SPR_NOACCESS, SPR_NOACCESS,
6085 &spr_read_generic, &spr_write_generic,
6086 0x00000000);
6087 /* MSSSR0 */
6088 /* XXX : not implemented */
6089 spr_register(env, SPR_MSSSR0, "MSSSR0",
6090 SPR_NOACCESS, SPR_NOACCESS,
6091 &spr_read_generic, &spr_write_generic,
6092 0x00000000);
6093 /* PMC */
6094 /* XXX : not implemented */
6095 spr_register(env, SPR_PMC5, "PMC5",
6096 SPR_NOACCESS, SPR_NOACCESS,
6097 &spr_read_generic, &spr_write_generic,
6098 0x00000000);
6099 /* XXX : not implemented */
6100 spr_register(env, SPR_UPMC5, "UPMC5",
6101 &spr_read_ureg, SPR_NOACCESS,
6102 &spr_read_ureg, SPR_NOACCESS,
6103 0x00000000);
6104 /* XXX : not implemented */
6105 spr_register(env, SPR_PMC6, "PMC6",
6106 SPR_NOACCESS, SPR_NOACCESS,
6107 &spr_read_generic, &spr_write_generic,
6108 0x00000000);
6109 /* XXX : not implemented */
6110 spr_register(env, SPR_UPMC6, "UPMC6",
6111 &spr_read_ureg, SPR_NOACCESS,
6112 &spr_read_ureg, SPR_NOACCESS,
6113 0x00000000);
6114 /* SPRGs */
6115 spr_register(env, SPR_SPRG4, "SPRG4",
6116 SPR_NOACCESS, SPR_NOACCESS,
6117 &spr_read_generic, &spr_write_generic,
6118 0x00000000);
6119 spr_register(env, SPR_USPRG4, "USPRG4",
6120 &spr_read_ureg, SPR_NOACCESS,
6121 &spr_read_ureg, SPR_NOACCESS,
6122 0x00000000);
6123 spr_register(env, SPR_SPRG5, "SPRG5",
6124 SPR_NOACCESS, SPR_NOACCESS,
6125 &spr_read_generic, &spr_write_generic,
6126 0x00000000);
6127 spr_register(env, SPR_USPRG5, "USPRG5",
6128 &spr_read_ureg, SPR_NOACCESS,
6129 &spr_read_ureg, SPR_NOACCESS,
6130 0x00000000);
6131 spr_register(env, SPR_SPRG6, "SPRG6",
6132 SPR_NOACCESS, SPR_NOACCESS,
6133 &spr_read_generic, &spr_write_generic,
6134 0x00000000);
6135 spr_register(env, SPR_USPRG6, "USPRG6",
6136 &spr_read_ureg, SPR_NOACCESS,
6137 &spr_read_ureg, SPR_NOACCESS,
6138 0x00000000);
6139 spr_register(env, SPR_SPRG7, "SPRG7",
6140 SPR_NOACCESS, SPR_NOACCESS,
6141 &spr_read_generic, &spr_write_generic,
6142 0x00000000);
6143 spr_register(env, SPR_USPRG7, "USPRG7",
6144 &spr_read_ureg, SPR_NOACCESS,
6145 &spr_read_ureg, SPR_NOACCESS,
6146 0x00000000);
6147 /* Memory management */
6148 gen_low_BATs(env);
6149 gen_high_BATs(env);
6150 gen_74xx_soft_tlb(env, 128, 2);
6151 init_excp_7450(env);
6152 env->dcache_line_size = 32;
6153 env->icache_line_size = 32;
6154 /* Allocate hardware IRQ controller */
6155 ppc6xx_irq_init(env);
6156 }
6157
6158 /* PowerPC 7457 (aka G4) */
6159 #define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6160 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6161 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6162 PPC_FLOAT_STFIWX | \
6163 PPC_CACHE | PPC_CACHE_ICBI | \
6164 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
6165 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6166 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6167 PPC_MEM_TLBIA | PPC_74xx_TLB | \
6168 PPC_SEGMENT | PPC_EXTERN | \
6169 PPC_ALTIVEC)
6170 #define POWERPC_INSNS2_7457 (PPC_NONE)
6171 #define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
6172 #define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
6173 #define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
6174 #define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
6175 #define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
6176 #define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6177 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6178 POWERPC_FLAG_BUS_CLK)
6179 #define check_pow_7457 check_pow_hid0_74xx
6180
6181 __attribute__ (( unused ))
6182 static void init_proc_7457 (CPUPPCState *env)
6183 {
6184 gen_spr_ne_601(env);
6185 gen_spr_7xx(env);
6186 /* Time base */
6187 gen_tbl(env);
6188 /* 74xx specific SPR */
6189 gen_spr_74xx(env);
6190 /* Level 3 cache control */
6191 gen_l3_ctrl(env);
6192 /* L3ITCR1 */
6193 /* XXX : not implemented */
6194 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6195 SPR_NOACCESS, SPR_NOACCESS,
6196 &spr_read_generic, &spr_write_generic,
6197 0x00000000);
6198 /* L3ITCR2 */
6199 /* XXX : not implemented */
6200 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6201 SPR_NOACCESS, SPR_NOACCESS,
6202 &spr_read_generic, &spr_write_generic,
6203 0x00000000);
6204 /* L3ITCR3 */
6205 /* XXX : not implemented */
6206 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6207 SPR_NOACCESS, SPR_NOACCESS,
6208 &spr_read_generic, &spr_write_generic,
6209 0x00000000);
6210 /* L3OHCR */
6211 /* XXX : not implemented */
6212 spr_register(env, SPR_L3OHCR, "L3OHCR",
6213 SPR_NOACCESS, SPR_NOACCESS,
6214 &spr_read_generic, &spr_write_generic,
6215 0x00000000);
6216 /* LDSTCR */
6217 /* XXX : not implemented */
6218 spr_register(env, SPR_LDSTCR, "LDSTCR",
6219 SPR_NOACCESS, SPR_NOACCESS,
6220 &spr_read_generic, &spr_write_generic,
6221 0x00000000);
6222 /* ICTRL */
6223 /* XXX : not implemented */
6224 spr_register(env, SPR_ICTRL, "ICTRL",
6225 SPR_NOACCESS, SPR_NOACCESS,
6226 &spr_read_generic, &spr_write_generic,
6227 0x00000000);
6228 /* MSSSR0 */
6229 /* XXX : not implemented */
6230 spr_register(env, SPR_MSSSR0, "MSSSR0",
6231 SPR_NOACCESS, SPR_NOACCESS,
6232 &spr_read_generic, &spr_write_generic,
6233 0x00000000);
6234 /* PMC */
6235 /* XXX : not implemented */
6236 spr_register(env, SPR_PMC5, "PMC5",
6237 SPR_NOACCESS, SPR_NOACCESS,
6238 &spr_read_generic, &spr_write_generic,
6239 0x00000000);
6240 /* XXX : not implemented */
6241 spr_register(env, SPR_UPMC5, "UPMC5",
6242 &spr_read_ureg, SPR_NOACCESS,
6243 &spr_read_ureg, SPR_NOACCESS,
6244 0x00000000);
6245 /* XXX : not implemented */
6246 spr_register(env, SPR_PMC6, "PMC6",
6247 SPR_NOACCESS, SPR_NOACCESS,
6248 &spr_read_generic, &spr_write_generic,
6249 0x00000000);
6250 /* XXX : not implemented */
6251 spr_register(env, SPR_UPMC6, "UPMC6",
6252 &spr_read_ureg, SPR_NOACCESS,
6253 &spr_read_ureg, SPR_NOACCESS,
6254 0x00000000);
6255 /* SPRGs */
6256 spr_register(env, SPR_SPRG4, "SPRG4",
6257 SPR_NOACCESS, SPR_NOACCESS,
6258 &spr_read_generic, &spr_write_generic,
6259 0x00000000);
6260 spr_register(env, SPR_USPRG4, "USPRG4",
6261 &spr_read_ureg, SPR_NOACCESS,
6262 &spr_read_ureg, SPR_NOACCESS,
6263 0x00000000);
6264 spr_register(env, SPR_SPRG5, "SPRG5",
6265 SPR_NOACCESS, SPR_NOACCESS,
6266 &spr_read_generic, &spr_write_generic,
6267 0x00000000);
6268 spr_register(env, SPR_USPRG5, "USPRG5",
6269 &spr_read_ureg, SPR_NOACCESS,
6270 &spr_read_ureg, SPR_NOACCESS,
6271 0x00000000);
6272 spr_register(env, SPR_SPRG6, "SPRG6",
6273 SPR_NOACCESS, SPR_NOACCESS,
6274 &spr_read_generic, &spr_write_generic,
6275 0x00000000);
6276 spr_register(env, SPR_USPRG6, "USPRG6",
6277 &spr_read_ureg, SPR_NOACCESS,
6278 &spr_read_ureg, SPR_NOACCESS,
6279 0x00000000);
6280 spr_register(env, SPR_SPRG7, "SPRG7",
6281 SPR_NOACCESS, SPR_NOACCESS,
6282 &spr_read_generic, &spr_write_generic,
6283 0x00000000);
6284 spr_register(env, SPR_USPRG7, "USPRG7",
6285 &spr_read_ureg, SPR_NOACCESS,
6286 &spr_read_ureg, SPR_NOACCESS,
6287 0x00000000);
6288 /* Memory management */
6289 gen_low_BATs(env);
6290 gen_high_BATs(env);
6291 gen_74xx_soft_tlb(env, 128, 2);
6292 init_excp_7450(env);
6293 env->dcache_line_size = 32;
6294 env->icache_line_size = 32;
6295 /* Allocate hardware IRQ controller */
6296 ppc6xx_irq_init(env);
6297 }
6298
6299 #if defined (TARGET_PPC64)
6300 /* PowerPC 970 */
6301 #define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6302 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6303 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6304 PPC_FLOAT_STFIWX | \
6305 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6306 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6307 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6308 PPC_64B | PPC_ALTIVEC | \
6309 PPC_SEGMENT_64B | PPC_SLBI)
6310 #define POWERPC_INSNS2_970 (PPC_NONE)
6311 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
6312 #define POWERPC_MMU_970 (POWERPC_MMU_64B)
6313 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
6314 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
6315 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
6316 #define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6317 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6318 POWERPC_FLAG_BUS_CLK)
6319
6320 #if defined(CONFIG_USER_ONLY)
6321 #define POWERPC970_HID5_INIT 0x00000080
6322 #else
6323 #define POWERPC970_HID5_INIT 0x00000000
6324 #endif
6325
6326 static int check_pow_970 (CPUPPCState *env)
6327 {
6328 if (env->spr[SPR_HID0] & 0x00600000)
6329 return 1;
6330
6331 return 0;
6332 }
6333
6334 static void init_proc_970 (CPUPPCState *env)
6335 {
6336 gen_spr_ne_601(env);
6337 gen_spr_7xx(env);
6338 /* Time base */
6339 gen_tbl(env);
6340 /* Hardware implementation registers */
6341 /* XXX : not implemented */
6342 spr_register(env, SPR_HID0, "HID0",
6343 SPR_NOACCESS, SPR_NOACCESS,
6344 &spr_read_generic, &spr_write_clear,
6345 0x60000000);
6346 /* XXX : not implemented */
6347 spr_register(env, SPR_HID1, "HID1",
6348 SPR_NOACCESS, SPR_NOACCESS,
6349 &spr_read_generic, &spr_write_generic,
6350 0x00000000);
6351 /* XXX : not implemented */
6352 spr_register(env, SPR_750FX_HID2, "HID2",
6353 SPR_NOACCESS, SPR_NOACCESS,
6354 &spr_read_generic, &spr_write_generic,
6355 0x00000000);
6356 /* XXX : not implemented */
6357 spr_register(env, SPR_970_HID5, "HID5",
6358 SPR_NOACCESS, SPR_NOACCESS,
6359 &spr_read_generic, &spr_write_generic,
6360 POWERPC970_HID5_INIT);
6361 /* XXX : not implemented */
6362 spr_register(env, SPR_L2CR, "L2CR",
6363 SPR_NOACCESS, SPR_NOACCESS,
6364 &spr_read_generic, &spr_write_generic,
6365 0x00000000);
6366 /* Memory management */
6367 /* XXX: not correct */
6368 gen_low_BATs(env);
6369 /* XXX : not implemented */
6370 spr_register(env, SPR_MMUCFG, "MMUCFG",
6371 SPR_NOACCESS, SPR_NOACCESS,
6372 &spr_read_generic, SPR_NOACCESS,
6373 0x00000000); /* TOFIX */
6374 /* XXX : not implemented */
6375 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6376 SPR_NOACCESS, SPR_NOACCESS,
6377 &spr_read_generic, &spr_write_generic,
6378 0x00000000); /* TOFIX */
6379 spr_register(env, SPR_HIOR, "SPR_HIOR",
6380 SPR_NOACCESS, SPR_NOACCESS,
6381 &spr_read_hior, &spr_write_hior,
6382 0x00000000);
6383 #if !defined(CONFIG_USER_ONLY)
6384 env->slb_nr = 32;
6385 #endif
6386 init_excp_970(env);
6387 env->dcache_line_size = 128;
6388 env->icache_line_size = 128;
6389 /* Allocate hardware IRQ controller */
6390 ppc970_irq_init(env);
6391 /* Can't find information on what this should be on reset. This
6392 * value is the one used by 74xx processors. */
6393 vscr_init(env, 0x00010000);
6394 }
6395
6396 /* PowerPC 970FX (aka G5) */
6397 #define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6398 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6399 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6400 PPC_FLOAT_STFIWX | \
6401 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6402 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6403 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6404 PPC_64B | PPC_ALTIVEC | \
6405 PPC_SEGMENT_64B | PPC_SLBI)
6406 #define POWERPC_INSNS2_970FX (PPC_NONE)
6407 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
6408 #define POWERPC_MMU_970FX (POWERPC_MMU_64B)
6409 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
6410 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
6411 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
6412 #define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6413 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6414 POWERPC_FLAG_BUS_CLK)
6415
6416 static int check_pow_970FX (CPUPPCState *env)
6417 {
6418 if (env->spr[SPR_HID0] & 0x00600000)
6419 return 1;
6420
6421 return 0;
6422 }
6423
6424 static void init_proc_970FX (CPUPPCState *env)
6425 {
6426 gen_spr_ne_601(env);
6427 gen_spr_7xx(env);
6428 /* Time base */
6429 gen_tbl(env);
6430 /* Hardware implementation registers */
6431 /* XXX : not implemented */
6432 spr_register(env, SPR_HID0, "HID0",
6433 SPR_NOACCESS, SPR_NOACCESS,
6434 &spr_read_generic, &spr_write_clear,
6435 0x60000000);
6436 /* XXX : not implemented */
6437 spr_register(env, SPR_HID1, "HID1",
6438 SPR_NOACCESS, SPR_NOACCESS,
6439 &spr_read_generic, &spr_write_generic,
6440 0x00000000);
6441 /* XXX : not implemented */
6442 spr_register(env, SPR_750FX_HID2, "HID2",
6443 SPR_NOACCESS, SPR_NOACCESS,
6444 &spr_read_generic, &spr_write_generic,
6445 0x00000000);
6446 /* XXX : not implemented */
6447 spr_register(env, SPR_970_HID5, "HID5",
6448 SPR_NOACCESS, SPR_NOACCESS,
6449 &spr_read_generic, &spr_write_generic,
6450 POWERPC970_HID5_INIT);
6451 /* XXX : not implemented */
6452 spr_register(env, SPR_L2CR, "L2CR",
6453 SPR_NOACCESS, SPR_NOACCESS,
6454 &spr_read_generic, &spr_write_generic,
6455 0x00000000);
6456 /* Memory management */
6457 /* XXX: not correct */
6458 gen_low_BATs(env);
6459 /* XXX : not implemented */
6460 spr_register(env, SPR_MMUCFG, "MMUCFG",
6461 SPR_NOACCESS, SPR_NOACCESS,
6462 &spr_read_generic, SPR_NOACCESS,
6463 0x00000000); /* TOFIX */
6464 /* XXX : not implemented */
6465 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6466 SPR_NOACCESS, SPR_NOACCESS,
6467 &spr_read_generic, &spr_write_generic,
6468 0x00000000); /* TOFIX */
6469 spr_register(env, SPR_HIOR, "SPR_HIOR",
6470 SPR_NOACCESS, SPR_NOACCESS,
6471 &spr_read_hior, &spr_write_hior,
6472 0x00000000);
6473 spr_register(env, SPR_CTRL, "SPR_CTRL",
6474 SPR_NOACCESS, SPR_NOACCESS,
6475 &spr_read_generic, &spr_write_generic,
6476 0x00000000);
6477 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6478 SPR_NOACCESS, SPR_NOACCESS,
6479 &spr_read_generic, &spr_write_generic,
6480 0x00000000);
6481 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6482 &spr_read_generic, &spr_write_generic,
6483 &spr_read_generic, &spr_write_generic,
6484 0x00000000);
6485 #if !defined(CONFIG_USER_ONLY)
6486 env->slb_nr = 64;
6487 #endif
6488 init_excp_970(env);
6489 env->dcache_line_size = 128;
6490 env->icache_line_size = 128;
6491 /* Allocate hardware IRQ controller */
6492 ppc970_irq_init(env);
6493 /* Can't find information on what this should be on reset. This
6494 * value is the one used by 74xx processors. */
6495 vscr_init(env, 0x00010000);
6496 }
6497
6498 /* PowerPC 970 GX */
6499 #define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6500 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6501 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6502 PPC_FLOAT_STFIWX | \
6503 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6504 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6505 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6506 PPC_64B | PPC_ALTIVEC | \
6507 PPC_SEGMENT_64B | PPC_SLBI)
6508 #define POWERPC_INSNS2_970GX (PPC_NONE)
6509 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
6510 #define POWERPC_MMU_970GX (POWERPC_MMU_64B)
6511 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6512 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
6513 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
6514 #define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6515 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6516 POWERPC_FLAG_BUS_CLK)
6517
6518 static int check_pow_970GX (CPUPPCState *env)
6519 {
6520 if (env->spr[SPR_HID0] & 0x00600000)
6521 return 1;
6522
6523 return 0;
6524 }
6525
6526 static void init_proc_970GX (CPUPPCState *env)
6527 {
6528 gen_spr_ne_601(env);
6529 gen_spr_7xx(env);
6530 /* Time base */
6531 gen_tbl(env);
6532 /* Hardware implementation registers */
6533 /* XXX : not implemented */
6534 spr_register(env, SPR_HID0, "HID0",
6535 SPR_NOACCESS, SPR_NOACCESS,
6536 &spr_read_generic, &spr_write_clear,
6537 0x60000000);
6538 /* XXX : not implemented */
6539 spr_register(env, SPR_HID1, "HID1",
6540 SPR_NOACCESS, SPR_NOACCESS,
6541 &spr_read_generic, &spr_write_generic,
6542 0x00000000);
6543 /* XXX : not implemented */
6544 spr_register(env, SPR_750FX_HID2, "HID2",
6545 SPR_NOACCESS, SPR_NOACCESS,
6546 &spr_read_generic, &spr_write_generic,
6547 0x00000000);
6548 /* XXX : not implemented */
6549 spr_register(env, SPR_970_HID5, "HID5",
6550 SPR_NOACCESS, SPR_NOACCESS,
6551 &spr_read_generic, &spr_write_generic,
6552 POWERPC970_HID5_INIT);
6553 /* XXX : not implemented */
6554 spr_register(env, SPR_L2CR, "L2CR",
6555 SPR_NOACCESS, SPR_NOACCESS,
6556 &spr_read_generic, &spr_write_generic,
6557 0x00000000);
6558 /* Memory management */
6559 /* XXX: not correct */
6560 gen_low_BATs(env);
6561 /* XXX : not implemented */
6562 spr_register(env, SPR_MMUCFG, "MMUCFG",
6563 SPR_NOACCESS, SPR_NOACCESS,
6564 &spr_read_generic, SPR_NOACCESS,
6565 0x00000000); /* TOFIX */
6566 /* XXX : not implemented */
6567 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6568 SPR_NOACCESS, SPR_NOACCESS,
6569 &spr_read_generic, &spr_write_generic,
6570 0x00000000); /* TOFIX */
6571 spr_register(env, SPR_HIOR, "SPR_HIOR",
6572 SPR_NOACCESS, SPR_NOACCESS,
6573 &spr_read_hior, &spr_write_hior,
6574 0x00000000);
6575 #if !defined(CONFIG_USER_ONLY)
6576 env->slb_nr = 32;
6577 #endif
6578 init_excp_970(env);
6579 env->dcache_line_size = 128;
6580 env->icache_line_size = 128;
6581 /* Allocate hardware IRQ controller */
6582 ppc970_irq_init(env);
6583 /* Can't find information on what this should be on reset. This
6584 * value is the one used by 74xx processors. */
6585 vscr_init(env, 0x00010000);
6586 }
6587
6588 /* PowerPC 970 MP */
6589 #define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6590 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6591 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6592 PPC_FLOAT_STFIWX | \
6593 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6594 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6595 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6596 PPC_64B | PPC_ALTIVEC | \
6597 PPC_SEGMENT_64B | PPC_SLBI)
6598 #define POWERPC_INSNS2_970MP (PPC_NONE)
6599 #define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6600 #define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6601 #define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6602 #define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6603 #define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6604 #define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6605 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6606 POWERPC_FLAG_BUS_CLK)
6607
6608 static int check_pow_970MP (CPUPPCState *env)
6609 {
6610 if (env->spr[SPR_HID0] & 0x01C00000)
6611 return 1;
6612
6613 return 0;
6614 }
6615
6616 static void init_proc_970MP (CPUPPCState *env)
6617 {
6618 gen_spr_ne_601(env);
6619 gen_spr_7xx(env);
6620 /* Time base */
6621 gen_tbl(env);
6622 /* Hardware implementation registers */
6623 /* XXX : not implemented */
6624 spr_register(env, SPR_HID0, "HID0",
6625 SPR_NOACCESS, SPR_NOACCESS,
6626 &spr_read_generic, &spr_write_clear,
6627 0x60000000);
6628 /* XXX : not implemented */
6629 spr_register(env, SPR_HID1, "HID1",
6630 SPR_NOACCESS, SPR_NOACCESS,
6631 &spr_read_generic, &spr_write_generic,
6632 0x00000000);
6633 /* XXX : not implemented */
6634 spr_register(env, SPR_750FX_HID2, "HID2",
6635 SPR_NOACCESS, SPR_NOACCESS,
6636 &spr_read_generic, &spr_write_generic,
6637 0x00000000);
6638 /* XXX : not implemented */
6639 spr_register(env, SPR_970_HID5, "HID5",
6640 SPR_NOACCESS, SPR_NOACCESS,
6641 &spr_read_generic, &spr_write_generic,
6642 POWERPC970_HID5_INIT);
6643 /* XXX : not implemented */
6644 spr_register(env, SPR_L2CR, "L2CR",
6645 SPR_NOACCESS, SPR_NOACCESS,
6646 &spr_read_generic, &spr_write_generic,
6647 0x00000000);
6648 /* Memory management */
6649 /* XXX: not correct */
6650 gen_low_BATs(env);
6651 /* XXX : not implemented */
6652 spr_register(env, SPR_MMUCFG, "MMUCFG",
6653 SPR_NOACCESS, SPR_NOACCESS,
6654 &spr_read_generic, SPR_NOACCESS,
6655 0x00000000); /* TOFIX */
6656 /* XXX : not implemented */
6657 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6658 SPR_NOACCESS, SPR_NOACCESS,
6659 &spr_read_generic, &spr_write_generic,
6660 0x00000000); /* TOFIX */
6661 spr_register(env, SPR_HIOR, "SPR_HIOR",
6662 SPR_NOACCESS, SPR_NOACCESS,
6663 &spr_read_hior, &spr_write_hior,
6664 0x00000000);
6665 #if !defined(CONFIG_USER_ONLY)
6666 env->slb_nr = 32;
6667 #endif
6668 init_excp_970(env);
6669 env->dcache_line_size = 128;
6670 env->icache_line_size = 128;
6671 /* Allocate hardware IRQ controller */
6672 ppc970_irq_init(env);
6673 /* Can't find information on what this should be on reset. This
6674 * value is the one used by 74xx processors. */
6675 vscr_init(env, 0x00010000);
6676 }
6677
6678 #if defined(TARGET_PPC64)
6679 /* POWER7 */
6680 #define POWERPC_INSNS_POWER7 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6681 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6682 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6683 PPC_FLOAT_STFIWX | \
6684 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6685 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6686 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6687 PPC_64B | PPC_ALTIVEC | \
6688 PPC_SEGMENT_64B | PPC_SLBI | \
6689 PPC_POPCNTB | PPC_POPCNTWD)
6690 #define POWERPC_INSNS2_POWER7 (PPC2_VSX | PPC2_DFP | PPC2_DBRX)
6691 #define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
6692 #define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
6693 #define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
6694 #define POWERPC_INPUT_POWER7 (PPC_FLAGS_INPUT_POWER7)
6695 #define POWERPC_BFDM_POWER7 (bfd_mach_ppc64)
6696 #define POWERPC_FLAG_POWER7 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6697 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6698 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR)
6699 #define check_pow_POWER7 check_pow_nocheck
6700
6701 static void init_proc_POWER7 (CPUPPCState *env)
6702 {
6703 gen_spr_ne_601(env);
6704 gen_spr_7xx(env);
6705 /* Time base */
6706 gen_tbl(env);
6707 /* Processor identification */
6708 spr_register(env, SPR_PIR, "PIR",
6709 SPR_NOACCESS, SPR_NOACCESS,
6710 &spr_read_generic, &spr_write_pir,
6711 0x00000000);
6712 #if !defined(CONFIG_USER_ONLY)
6713 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6714 spr_register(env, SPR_PURR, "PURR",
6715 &spr_read_purr, SPR_NOACCESS,
6716 &spr_read_purr, SPR_NOACCESS,
6717 0x00000000);
6718 spr_register(env, SPR_SPURR, "SPURR",
6719 &spr_read_purr, SPR_NOACCESS,
6720 &spr_read_purr, SPR_NOACCESS,
6721 0x00000000);
6722 spr_register(env, SPR_CFAR, "SPR_CFAR",
6723 SPR_NOACCESS, SPR_NOACCESS,
6724 &spr_read_cfar, &spr_write_cfar,
6725 0x00000000);
6726 spr_register(env, SPR_DSCR, "SPR_DSCR",
6727 SPR_NOACCESS, SPR_NOACCESS,
6728 &spr_read_generic, &spr_write_generic,
6729 0x00000000);
6730 #endif /* !CONFIG_USER_ONLY */
6731 /* Memory management */
6732 /* XXX : not implemented */
6733 spr_register(env, SPR_MMUCFG, "MMUCFG",
6734 SPR_NOACCESS, SPR_NOACCESS,
6735 &spr_read_generic, SPR_NOACCESS,
6736 0x00000000); /* TOFIX */
6737 /* XXX : not implemented */
6738 spr_register(env, SPR_CTRL, "SPR_CTRLT",
6739 SPR_NOACCESS, SPR_NOACCESS,
6740 &spr_read_generic, &spr_write_generic,
6741 0x80800000);
6742 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
6743 SPR_NOACCESS, SPR_NOACCESS,
6744 &spr_read_generic, &spr_write_generic,
6745 0x80800000);
6746 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6747 &spr_read_generic, &spr_write_generic,
6748 &spr_read_generic, &spr_write_generic,
6749 0x00000000);
6750 #if !defined(CONFIG_USER_ONLY)
6751 env->slb_nr = 32;
6752 #endif
6753 init_excp_POWER7(env);
6754 env->dcache_line_size = 128;
6755 env->icache_line_size = 128;
6756 /* Allocate hardware IRQ controller */
6757 ppcPOWER7_irq_init(env);
6758 /* Can't find information on what this should be on reset. This
6759 * value is the one used by 74xx processors. */
6760 vscr_init(env, 0x00010000);
6761 }
6762 #endif /* TARGET_PPC64 */
6763
6764 /* PowerPC 620 */
6765 #define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6766 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6767 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6768 PPC_FLOAT_STFIWX | \
6769 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6770 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6771 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6772 PPC_SEGMENT | PPC_EXTERN | \
6773 PPC_64B | PPC_SLBI)
6774 #define POWERPC_INSNS2_620 (PPC_NONE)
6775 #define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6776 //#define POWERPC_MMU_620 (POWERPC_MMU_620)
6777 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
6778 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
6779 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
6780 #define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
6781 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
6782 #define check_pow_620 check_pow_nocheck /* Check this */
6783
6784 __attribute__ (( unused ))
6785 static void init_proc_620 (CPUPPCState *env)
6786 {
6787 gen_spr_ne_601(env);
6788 gen_spr_620(env);
6789 /* Time base */
6790 gen_tbl(env);
6791 /* Hardware implementation registers */
6792 /* XXX : not implemented */
6793 spr_register(env, SPR_HID0, "HID0",
6794 SPR_NOACCESS, SPR_NOACCESS,
6795 &spr_read_generic, &spr_write_generic,
6796 0x00000000);
6797 /* Memory management */
6798 gen_low_BATs(env);
6799 init_excp_620(env);
6800 env->dcache_line_size = 64;
6801 env->icache_line_size = 64;
6802 /* Allocate hardware IRQ controller */
6803 ppc6xx_irq_init(env);
6804 }
6805 #endif /* defined (TARGET_PPC64) */
6806
6807 /* Default 32 bits PowerPC target will be 604 */
6808 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
6809 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
6810 #define POWERPC_INSNS2_PPC32 POWERPC_INSNS2_604
6811 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6812 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
6813 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6814 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
6815 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
6816 #define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
6817 #define check_pow_PPC32 check_pow_604
6818 #define init_proc_PPC32 init_proc_604
6819
6820 /* Default 64 bits PowerPC target will be 970 FX */
6821 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6822 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
6823 #define POWERPC_INSNS2_PPC64 POWERPC_INSNS2_970FX
6824 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6825 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6826 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6827 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
6828 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
6829 #define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
6830 #define check_pow_PPC64 check_pow_970FX
6831 #define init_proc_PPC64 init_proc_970FX
6832
6833 /* Default PowerPC target will be PowerPC 32 */
6834 #if defined (TARGET_PPC64) && 0 // XXX: TODO
6835 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6836 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6837 #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS2_PPC64
6838 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6839 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6840 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6841 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6842 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
6843 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
6844 #define check_pow_DEFAULT check_pow_PPC64
6845 #define init_proc_DEFAULT init_proc_PPC64
6846 #else
6847 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6848 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6849 #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS2_PPC32
6850 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6851 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6852 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6853 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6854 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
6855 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
6856 #define check_pow_DEFAULT check_pow_PPC32
6857 #define init_proc_DEFAULT init_proc_PPC32
6858 #endif
6859
6860 /*****************************************************************************/
6861 /* PVR definitions for most known PowerPC */
6862 enum {
6863 /* PowerPC 401 family */
6864 /* Generic PowerPC 401 */
6865 #define CPU_POWERPC_401 CPU_POWERPC_401G2
6866 /* PowerPC 401 cores */
6867 CPU_POWERPC_401A1 = 0x00210000,
6868 CPU_POWERPC_401B2 = 0x00220000,
6869 #if 0
6870 CPU_POWERPC_401B3 = xxx,
6871 #endif
6872 CPU_POWERPC_401C2 = 0x00230000,
6873 CPU_POWERPC_401D2 = 0x00240000,
6874 CPU_POWERPC_401E2 = 0x00250000,
6875 CPU_POWERPC_401F2 = 0x00260000,
6876 CPU_POWERPC_401G2 = 0x00270000,
6877 /* PowerPC 401 microcontrolers */
6878 #if 0
6879 CPU_POWERPC_401GF = xxx,
6880 #endif
6881 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
6882 /* IBM Processor for Network Resources */
6883 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
6884 #if 0
6885 CPU_POWERPC_XIPCHIP = xxx,
6886 #endif
6887 /* PowerPC 403 family */
6888 /* Generic PowerPC 403 */
6889 #define CPU_POWERPC_403 CPU_POWERPC_403GC
6890 /* PowerPC 403 microcontrollers */
6891 CPU_POWERPC_403GA = 0x00200011,
6892 CPU_POWERPC_403GB = 0x00200100,
6893 CPU_POWERPC_403GC = 0x00200200,
6894 CPU_POWERPC_403GCX = 0x00201400,
6895 #if 0
6896 CPU_POWERPC_403GP = xxx,
6897 #endif
6898 /* PowerPC 405 family */
6899 /* Generic PowerPC 405 */
6900 #define CPU_POWERPC_405 CPU_POWERPC_405D4
6901 /* PowerPC 405 cores */
6902 #if 0
6903 CPU_POWERPC_405A3 = xxx,
6904 #endif
6905 #if 0
6906 CPU_POWERPC_405A4 = xxx,
6907 #endif
6908 #if 0
6909 CPU_POWERPC_405B3 = xxx,
6910 #endif
6911 #if 0
6912 CPU_POWERPC_405B4 = xxx,
6913 #endif
6914 #if 0
6915 CPU_POWERPC_405C3 = xxx,
6916 #endif
6917 #if 0
6918 CPU_POWERPC_405C4 = xxx,
6919 #endif
6920 CPU_POWERPC_405D2 = 0x20010000,
6921 #if 0
6922 CPU_POWERPC_405D3 = xxx,
6923 #endif
6924 CPU_POWERPC_405D4 = 0x41810000,
6925 #if 0
6926 CPU_POWERPC_405D5 = xxx,
6927 #endif
6928 #if 0
6929 CPU_POWERPC_405E4 = xxx,
6930 #endif
6931 #if 0
6932 CPU_POWERPC_405F4 = xxx,
6933 #endif
6934 #if 0
6935 CPU_POWERPC_405F5 = xxx,
6936 #endif
6937 #if 0
6938 CPU_POWERPC_405F6 = xxx,
6939 #endif
6940 /* PowerPC 405 microcontrolers */
6941 /* XXX: missing 0x200108a0 */
6942 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6943 CPU_POWERPC_405CRa = 0x40110041,
6944 CPU_POWERPC_405CRb = 0x401100C5,
6945 CPU_POWERPC_405CRc = 0x40110145,
6946 CPU_POWERPC_405EP = 0x51210950,
6947 #if 0
6948 CPU_POWERPC_405EXr = xxx,
6949 #endif
6950 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
6951 #if 0
6952 CPU_POWERPC_405FX = xxx,
6953 #endif
6954 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6955 CPU_POWERPC_405GPa = 0x40110000,
6956 CPU_POWERPC_405GPb = 0x40110040,
6957 CPU_POWERPC_405GPc = 0x40110082,
6958 CPU_POWERPC_405GPd = 0x401100C4,
6959 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6960 CPU_POWERPC_405GPR = 0x50910951,
6961 #if 0
6962 CPU_POWERPC_405H = xxx,
6963 #endif
6964 #if 0
6965 CPU_POWERPC_405L = xxx,
6966 #endif
6967 CPU_POWERPC_405LP = 0x41F10000,
6968 #if 0
6969 CPU_POWERPC_405PM = xxx,
6970 #endif
6971 #if 0
6972 CPU_POWERPC_405PS = xxx,
6973 #endif
6974 #if 0
6975 CPU_POWERPC_405S = xxx,
6976 #endif
6977 /* IBM network processors */
6978 CPU_POWERPC_NPE405H = 0x414100C0,
6979 CPU_POWERPC_NPE405H2 = 0x41410140,
6980 CPU_POWERPC_NPE405L = 0x416100C0,
6981 CPU_POWERPC_NPE4GS3 = 0x40B10000,
6982 #if 0
6983 CPU_POWERPC_NPCxx1 = xxx,
6984 #endif
6985 #if 0
6986 CPU_POWERPC_NPR161 = xxx,
6987 #endif
6988 #if 0
6989 CPU_POWERPC_LC77700 = xxx,
6990 #endif
6991 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6992 #if 0
6993 CPU_POWERPC_STB01000 = xxx,
6994 #endif
6995 #if 0
6996 CPU_POWERPC_STB01010 = xxx,
6997 #endif
6998 #if 0
6999 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
7000 #endif
7001 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
7002 #if 0
7003 CPU_POWERPC_STB043 = xxx,
7004 #endif
7005 #if 0
7006 CPU_POWERPC_STB045 = xxx,
7007 #endif
7008 CPU_POWERPC_STB04 = 0x41810000,
7009 CPU_POWERPC_STB25 = 0x51510950,
7010 #if 0
7011 CPU_POWERPC_STB130 = xxx,
7012 #endif
7013 /* Xilinx cores */
7014 CPU_POWERPC_X2VP4 = 0x20010820,
7015 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
7016 CPU_POWERPC_X2VP20 = 0x20010860,
7017 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
7018 #if 0
7019 CPU_POWERPC_ZL10310 = xxx,
7020 #endif
7021 #if 0
7022 CPU_POWERPC_ZL10311 = xxx,
7023 #endif
7024 #if 0
7025 CPU_POWERPC_ZL10320 = xxx,
7026 #endif
7027 #if 0
7028 CPU_POWERPC_ZL10321 = xxx,
7029 #endif
7030 /* PowerPC 440 family */
7031 /* Generic PowerPC 440 */
7032 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
7033 /* PowerPC 440 cores */
7034 #if 0
7035 CPU_POWERPC_440A4 = xxx,
7036 #endif
7037 CPU_POWERPC_440_XILINX = 0x7ff21910,
7038 #if 0
7039 CPU_POWERPC_440A5 = xxx,
7040 #endif
7041 #if 0
7042 CPU_POWERPC_440B4 = xxx,
7043 #endif
7044 #if 0
7045 CPU_POWERPC_440F5 = xxx,
7046 #endif
7047 #if 0
7048 CPU_POWERPC_440G5 = xxx,
7049 #endif
7050 #if 0
7051 CPU_POWERPC_440H4 = xxx,
7052 #endif
7053 #if 0
7054 CPU_POWERPC_440H6 = xxx,
7055 #endif
7056 /* PowerPC 440 microcontrolers */
7057 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
7058 CPU_POWERPC_440EPa = 0x42221850,
7059 CPU_POWERPC_440EPb = 0x422218D3,
7060 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
7061 CPU_POWERPC_440GPb = 0x40120440,
7062 CPU_POWERPC_440GPc = 0x40120481,
7063 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
7064 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
7065 CPU_POWERPC_440GRX = 0x200008D0,
7066 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
7067 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
7068 CPU_POWERPC_440GXa = 0x51B21850,
7069 CPU_POWERPC_440GXb = 0x51B21851,
7070 CPU_POWERPC_440GXc = 0x51B21892,
7071 CPU_POWERPC_440GXf = 0x51B21894,
7072 #if 0
7073 CPU_POWERPC_440S = xxx,
7074 #endif
7075 CPU_POWERPC_440SP = 0x53221850,
7076 CPU_POWERPC_440SP2 = 0x53221891,
7077 CPU_POWERPC_440SPE = 0x53421890,
7078 /* PowerPC 460 family */
7079 #if 0
7080 /* Generic PowerPC 464 */
7081 #define CPU_POWERPC_464 CPU_POWERPC_464H90
7082 #endif
7083 /* PowerPC 464 microcontrolers */
7084 #if 0
7085 CPU_POWERPC_464H90 = xxx,
7086 #endif
7087 #if 0
7088 CPU_POWERPC_464H90FP = xxx,
7089 #endif
7090 /* Freescale embedded PowerPC cores */
7091 /* PowerPC MPC 5xx cores (aka RCPU) */
7092 CPU_POWERPC_MPC5xx = 0x00020020,
7093 #define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
7094 #define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
7095 #define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
7096 #define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
7097 #define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
7098 #define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
7099 #define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
7100 #define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
7101 #define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
7102 #define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
7103 #define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
7104 #define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
7105 #define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
7106 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
7107 CPU_POWERPC_MPC8xx = 0x00500000,
7108 #define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
7109 #define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
7110 #define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
7111 #define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
7112 #define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
7113 #define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
7114 #define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
7115 #define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
7116 #define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
7117 #define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
7118 #define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
7119 #define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
7120 #define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
7121 #define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
7122 #define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
7123 /* G2 cores (aka PowerQUICC-II) */
7124 CPU_POWERPC_G2 = 0x00810011,
7125 CPU_POWERPC_G2H4 = 0x80811010,
7126 CPU_POWERPC_G2gp = 0x80821010,
7127 CPU_POWERPC_G2ls = 0x90810010,
7128 CPU_POWERPC_MPC603 = 0x00810100,
7129 CPU_POWERPC_G2_HIP3 = 0x00810101,
7130 CPU_POWERPC_G2_HIP4 = 0x80811014,
7131 /* G2_LE core (aka PowerQUICC-II) */
7132 CPU_POWERPC_G2LE = 0x80820010,
7133 CPU_POWERPC_G2LEgp = 0x80822010,
7134 CPU_POWERPC_G2LEls = 0xA0822010,
7135 CPU_POWERPC_G2LEgp1 = 0x80822011,
7136 CPU_POWERPC_G2LEgp3 = 0x80822013,
7137 /* MPC52xx microcontrollers */
7138 /* XXX: MPC 5121 ? */
7139 #define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
7140 #define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
7141 #define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
7142 #define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
7143 #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
7144 #define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
7145 #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
7146 #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
7147 /* MPC82xx microcontrollers */
7148 #define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
7149 #define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
7150 #define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
7151 #define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
7152 #define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
7153 #define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
7154 #define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
7155 #define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
7156 #define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
7157 #define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
7158 #define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
7159 #define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
7160 #define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
7161 #define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
7162 #define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
7163 #define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
7164 #define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
7165 #define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
7166 #define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
7167 #define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
7168 #define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
7169 #define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
7170 #define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
7171 #define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
7172 #define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
7173 #define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
7174 #define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
7175 #define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
7176 #define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
7177 /* e200 family */
7178 /* e200 cores */
7179 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
7180 #if 0
7181 CPU_POWERPC_e200z0 = xxx,
7182 #endif
7183 #if 0
7184 CPU_POWERPC_e200z1 = xxx,
7185 #endif
7186 #if 0 /* ? */
7187 CPU_POWERPC_e200z3 = 0x81120000,
7188 #endif
7189 CPU_POWERPC_e200z5 = 0x81000000,
7190 CPU_POWERPC_e200z6 = 0x81120000,
7191 /* MPC55xx microcontrollers */
7192 #define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
7193 #if 0
7194 #define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
7195 #define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
7196 #define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
7197 #define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
7198 #define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
7199 #define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
7200 #define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
7201 #define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
7202 #define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
7203 #define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
7204 #define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
7205 #define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
7206 #define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
7207 #define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
7208 #endif
7209 #if 0
7210 #define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
7211 #define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
7212 #endif
7213 #define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
7214 #define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
7215 #define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
7216 #define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
7217 #define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
7218 #define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
7219 /* e300 family */
7220 /* e300 cores */
7221 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
7222 CPU_POWERPC_e300c1 = 0x00830010,
7223 CPU_POWERPC_e300c2 = 0x00840010,
7224 CPU_POWERPC_e300c3 = 0x00850010,
7225 CPU_POWERPC_e300c4 = 0x00860010,
7226 /* MPC83xx microcontrollers */
7227 #define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
7228 #define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
7229 #define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
7230 #define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
7231 #define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
7232 #define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
7233 /* e500 family */
7234 /* e500 cores */
7235 #define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
7236 #define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
7237 #define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
7238 CPU_POWERPC_e500v1_v10 = 0x80200010,
7239 CPU_POWERPC_e500v1_v20 = 0x80200020,
7240 CPU_POWERPC_e500v2_v10 = 0x80210010,
7241 CPU_POWERPC_e500v2_v11 = 0x80210011,
7242 CPU_POWERPC_e500v2_v20 = 0x80210020,
7243 CPU_POWERPC_e500v2_v21 = 0x80210021,
7244 CPU_POWERPC_e500v2_v22 = 0x80210022,
7245 CPU_POWERPC_e500v2_v30 = 0x80210030,
7246 CPU_POWERPC_e500mc = 0x80230020,
7247 CPU_POWERPC_e5500 = 0x80240020,
7248 /* MPC85xx microcontrollers */
7249 #define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
7250 #define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
7251 #define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
7252 #define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
7253 #define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
7254 #define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
7255 #define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
7256 #define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
7257 #define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
7258 #define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
7259 #define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
7260 #define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
7261 #define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
7262 #define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
7263 #define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
7264 #define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
7265 #define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
7266 #define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
7267 #define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
7268 #define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
7269 #define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
7270 #define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
7271 #define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
7272 #define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
7273 #define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
7274 #define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
7275 #define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
7276 #define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
7277 #define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
7278 #define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
7279 #define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
7280 #define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
7281 #define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
7282 #define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
7283 #define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
7284 #define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
7285 #define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
7286 #define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
7287 #define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
7288 #define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
7289 #define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
7290 #define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
7291 #define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
7292 #define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
7293 #define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
7294 #define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
7295 #define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
7296 #define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
7297 #define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
7298 #define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
7299 #define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
7300 #define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
7301 #define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
7302 #define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
7303 #define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
7304 #define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
7305 #define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
7306 #define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
7307 #define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
7308 #define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
7309 #define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
7310 #define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
7311 #define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
7312 #define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
7313 #define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
7314 #define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
7315 #define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
7316 #define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
7317 #define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
7318 #define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
7319 /* e600 family */
7320 /* e600 cores */
7321 CPU_POWERPC_e600 = 0x80040010,
7322 /* MPC86xx microcontrollers */
7323 #define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
7324 #define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
7325 #define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
7326 /* PowerPC 6xx cores */
7327 #define CPU_POWERPC_601 CPU_POWERPC_601_v2
7328 CPU_POWERPC_601_v0 = 0x00010001,
7329 CPU_POWERPC_601_v1 = 0x00010001,
7330 #define CPU_POWERPC_601v CPU_POWERPC_601_v2
7331 CPU_POWERPC_601_v2 = 0x00010002,
7332 CPU_POWERPC_602 = 0x00050100,
7333 CPU_POWERPC_603 = 0x00030100,
7334 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
7335 CPU_POWERPC_603E_v11 = 0x00060101,
7336 CPU_POWERPC_603E_v12 = 0x00060102,
7337 CPU_POWERPC_603E_v13 = 0x00060103,
7338 CPU_POWERPC_603E_v14 = 0x00060104,
7339 CPU_POWERPC_603E_v22 = 0x00060202,
7340 CPU_POWERPC_603E_v3 = 0x00060300,
7341 CPU_POWERPC_603E_v4 = 0x00060400,
7342 CPU_POWERPC_603E_v41 = 0x00060401,
7343 CPU_POWERPC_603E7t = 0x00071201,
7344 CPU_POWERPC_603E7v = 0x00070100,
7345 CPU_POWERPC_603E7v1 = 0x00070101,
7346 CPU_POWERPC_603E7v2 = 0x00070201,
7347 CPU_POWERPC_603E7 = 0x00070200,
7348 CPU_POWERPC_603P = 0x00070000,
7349 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
7350 /* XXX: missing 0x00040303 (604) */
7351 CPU_POWERPC_604 = 0x00040103,
7352 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
7353 /* XXX: missing 0x00091203 */
7354 /* XXX: missing 0x00092110 */
7355 /* XXX: missing 0x00092120 */
7356 CPU_POWERPC_604E_v10 = 0x00090100,
7357 CPU_POWERPC_604E_v22 = 0x00090202,
7358 CPU_POWERPC_604E_v24 = 0x00090204,
7359 /* XXX: missing 0x000a0100 */
7360 /* XXX: missing 0x00093102 */
7361 CPU_POWERPC_604R = 0x000a0101,
7362 #if 0
7363 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
7364 #endif
7365 /* PowerPC 740/750 cores (aka G3) */
7366 /* XXX: missing 0x00084202 */
7367 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
7368 CPU_POWERPC_7x0_v10 = 0x00080100,
7369 CPU_POWERPC_7x0_v20 = 0x00080200,
7370 CPU_POWERPC_7x0_v21 = 0x00080201,
7371 CPU_POWERPC_7x0_v22 = 0x00080202,
7372 CPU_POWERPC_7x0_v30 = 0x00080300,
7373 CPU_POWERPC_7x0_v31 = 0x00080301,
7374 CPU_POWERPC_740E = 0x00080100,
7375 CPU_POWERPC_750E = 0x00080200,
7376 CPU_POWERPC_7x0P = 0x10080000,
7377 /* XXX: missing 0x00087010 (CL ?) */
7378 #define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
7379 CPU_POWERPC_750CL_v10 = 0x00087200,
7380 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
7381 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
7382 CPU_POWERPC_750CX_v10 = 0x00082100,
7383 CPU_POWERPC_750CX_v20 = 0x00082200,
7384 CPU_POWERPC_750CX_v21 = 0x00082201,
7385 CPU_POWERPC_750CX_v22 = 0x00082202,
7386 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
7387 CPU_POWERPC_750CXE_v21 = 0x00082211,
7388 CPU_POWERPC_750CXE_v22 = 0x00082212,
7389 CPU_POWERPC_750CXE_v23 = 0x00082213,
7390 CPU_POWERPC_750CXE_v24 = 0x00082214,
7391 CPU_POWERPC_750CXE_v24b = 0x00083214,
7392 CPU_POWERPC_750CXE_v30 = 0x00082310,
7393 CPU_POWERPC_750CXE_v31 = 0x00082311,
7394 CPU_POWERPC_750CXE_v31b = 0x00083311,
7395 CPU_POWERPC_750CXR = 0x00083410,
7396 CPU_POWERPC_750FL = 0x70000203,
7397 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
7398 CPU_POWERPC_750FX_v10 = 0x70000100,
7399 CPU_POWERPC_750FX_v20 = 0x70000200,
7400 CPU_POWERPC_750FX_v21 = 0x70000201,
7401 CPU_POWERPC_750FX_v22 = 0x70000202,
7402 CPU_POWERPC_750FX_v23 = 0x70000203,
7403 CPU_POWERPC_750GL = 0x70020102,
7404 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
7405 CPU_POWERPC_750GX_v10 = 0x70020100,
7406 CPU_POWERPC_750GX_v11 = 0x70020101,
7407 CPU_POWERPC_750GX_v12 = 0x70020102,
7408 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
7409 CPU_POWERPC_750L_v20 = 0x00088200,
7410 CPU_POWERPC_750L_v21 = 0x00088201,
7411 CPU_POWERPC_750L_v22 = 0x00088202,
7412 CPU_POWERPC_750L_v30 = 0x00088300,
7413 CPU_POWERPC_750L_v32 = 0x00088302,
7414 /* PowerPC 745/755 cores */
7415 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
7416 CPU_POWERPC_7x5_v10 = 0x00083100,
7417 CPU_POWERPC_7x5_v11 = 0x00083101,
7418 CPU_POWERPC_7x5_v20 = 0x00083200,
7419 CPU_POWERPC_7x5_v21 = 0x00083201,
7420 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
7421 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
7422 CPU_POWERPC_7x5_v24 = 0x00083204,
7423 CPU_POWERPC_7x5_v25 = 0x00083205,
7424 CPU_POWERPC_7x5_v26 = 0x00083206,
7425 CPU_POWERPC_7x5_v27 = 0x00083207,
7426 CPU_POWERPC_7x5_v28 = 0x00083208,
7427 #if 0
7428 CPU_POWERPC_7x5P = xxx,
7429 #endif
7430 /* PowerPC 74xx cores (aka G4) */
7431 /* XXX: missing 0x000C1101 */
7432 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
7433 CPU_POWERPC_7400_v10 = 0x000C0100,
7434 CPU_POWERPC_7400_v11 = 0x000C0101,
7435 CPU_POWERPC_7400_v20 = 0x000C0200,
7436 CPU_POWERPC_7400_v21 = 0x000C0201,
7437 CPU_POWERPC_7400_v22 = 0x000C0202,
7438 CPU_POWERPC_7400_v26 = 0x000C0206,
7439 CPU_POWERPC_7400_v27 = 0x000C0207,
7440 CPU_POWERPC_7400_v28 = 0x000C0208,
7441 CPU_POWERPC_7400_v29 = 0x000C0209,
7442 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
7443 CPU_POWERPC_7410_v10 = 0x800C1100,
7444 CPU_POWERPC_7410_v11 = 0x800C1101,
7445 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
7446 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
7447 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
7448 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
7449 CPU_POWERPC_7448_v10 = 0x80040100,
7450 CPU_POWERPC_7448_v11 = 0x80040101,
7451 CPU_POWERPC_7448_v20 = 0x80040200,
7452 CPU_POWERPC_7448_v21 = 0x80040201,
7453 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
7454 CPU_POWERPC_7450_v10 = 0x80000100,
7455 CPU_POWERPC_7450_v11 = 0x80000101,
7456 CPU_POWERPC_7450_v12 = 0x80000102,
7457 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
7458 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
7459 #define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
7460 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
7461 /* XXX: this entry might be a bug in some documentation */
7462 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
7463 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
7464 CPU_POWERPC_74x5_v10 = 0x80010100,
7465 /* XXX: missing 0x80010200 */
7466 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
7467 CPU_POWERPC_74x5_v32 = 0x80010302,
7468 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
7469 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
7470 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
7471 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
7472 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
7473 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
7474 #define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
7475 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
7476 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
7477 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
7478 /* 64 bits PowerPC */
7479 #if defined(TARGET_PPC64)
7480 CPU_POWERPC_620 = 0x00140000,
7481 CPU_POWERPC_630 = 0x00400000,
7482 CPU_POWERPC_631 = 0x00410104,
7483 CPU_POWERPC_POWER4 = 0x00350000,
7484 CPU_POWERPC_POWER4P = 0x00380000,
7485 /* XXX: missing 0x003A0201 */
7486 CPU_POWERPC_POWER5 = 0x003A0203,
7487 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
7488 CPU_POWERPC_POWER5P = 0x003B0000,
7489 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
7490 CPU_POWERPC_POWER6 = 0x003E0000,
7491 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
7492 CPU_POWERPC_POWER6A = 0x0F000002,
7493 #define CPU_POWERPC_POWER7 CPU_POWERPC_POWER7_v20
7494 CPU_POWERPC_POWER7_v20 = 0x003F0200,
7495 CPU_POWERPC_POWER7_v21 = 0x003F0201,
7496 CPU_POWERPC_POWER7_v23 = 0x003F0203,
7497 CPU_POWERPC_970 = 0x00390202,
7498 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
7499 CPU_POWERPC_970FX_v10 = 0x00391100,
7500 CPU_POWERPC_970FX_v20 = 0x003C0200,
7501 CPU_POWERPC_970FX_v21 = 0x003C0201,
7502 CPU_POWERPC_970FX_v30 = 0x003C0300,
7503 CPU_POWERPC_970FX_v31 = 0x003C0301,
7504 CPU_POWERPC_970GX = 0x00450000,
7505 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
7506 CPU_POWERPC_970MP_v10 = 0x00440100,
7507 CPU_POWERPC_970MP_v11 = 0x00440101,
7508 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
7509 CPU_POWERPC_CELL_v10 = 0x00700100,
7510 CPU_POWERPC_CELL_v20 = 0x00700400,
7511 CPU_POWERPC_CELL_v30 = 0x00700500,
7512 CPU_POWERPC_CELL_v31 = 0x00700501,
7513 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
7514 CPU_POWERPC_RS64 = 0x00330000,
7515 CPU_POWERPC_RS64II = 0x00340000,
7516 CPU_POWERPC_RS64III = 0x00360000,
7517 CPU_POWERPC_RS64IV = 0x00370000,
7518 #endif /* defined(TARGET_PPC64) */
7519 /* Original POWER */
7520 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7521 * POWER2 (RIOS2) & RSC2 (P2SC) here
7522 */
7523 #if 0
7524 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
7525 #endif
7526 #if 0
7527 CPU_POWER2 = xxx, /* 0x40000 ? */
7528 #endif
7529 /* PA Semi core */
7530 CPU_POWERPC_PA6T = 0x00900000,
7531 };
7532
7533 /* System version register (used on MPC 8xxx) */
7534 enum {
7535 POWERPC_SVR_NONE = 0x00000000,
7536 #define POWERPC_SVR_52xx POWERPC_SVR_5200
7537 #define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
7538 POWERPC_SVR_5200_v10 = 0x80110010,
7539 POWERPC_SVR_5200_v11 = 0x80110011,
7540 POWERPC_SVR_5200_v12 = 0x80110012,
7541 #define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
7542 POWERPC_SVR_5200B_v20 = 0x80110020,
7543 POWERPC_SVR_5200B_v21 = 0x80110021,
7544 #define POWERPC_SVR_55xx POWERPC_SVR_5567
7545 #if 0
7546 POWERPC_SVR_5533 = xxx,
7547 #endif
7548 #if 0
7549 POWERPC_SVR_5534 = xxx,
7550 #endif
7551 #if 0
7552 POWERPC_SVR_5553 = xxx,
7553 #endif
7554 #if 0
7555 POWERPC_SVR_5554 = xxx,
7556 #endif
7557 #if 0
7558 POWERPC_SVR_5561 = xxx,
7559 #endif
7560 #if 0
7561 POWERPC_SVR_5565 = xxx,
7562 #endif
7563 #if 0
7564 POWERPC_SVR_5566 = xxx,
7565 #endif
7566 #if 0
7567 POWERPC_SVR_5567 = xxx,
7568 #endif
7569 #if 0
7570 POWERPC_SVR_8313 = xxx,
7571 #endif
7572 #if 0
7573 POWERPC_SVR_8313E = xxx,
7574 #endif
7575 #if 0
7576 POWERPC_SVR_8314 = xxx,
7577 #endif
7578 #if 0
7579 POWERPC_SVR_8314E = xxx,
7580 #endif
7581 #if 0
7582 POWERPC_SVR_8315 = xxx,
7583 #endif
7584 #if 0
7585 POWERPC_SVR_8315E = xxx,
7586 #endif
7587 #if 0
7588 POWERPC_SVR_8321 = xxx,
7589 #endif
7590 #if 0
7591 POWERPC_SVR_8321E = xxx,
7592 #endif
7593 #if 0
7594 POWERPC_SVR_8323 = xxx,
7595 #endif
7596 #if 0
7597 POWERPC_SVR_8323E = xxx,
7598 #endif
7599 POWERPC_SVR_8343 = 0x80570010,
7600 POWERPC_SVR_8343A = 0x80570030,
7601 POWERPC_SVR_8343E = 0x80560010,
7602 POWERPC_SVR_8343EA = 0x80560030,
7603 #define POWERPC_SVR_8347 POWERPC_SVR_8347T
7604 POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
7605 POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
7606 #define POWERPC_SVR_8347A POWERPC_SVR_8347AT
7607 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7608 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
7609 #define POWERPC_SVR_8347E POWERPC_SVR_8347ET
7610 POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
7611 POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
7612 #define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
7613 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7614 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7615 POWERPC_SVR_8349 = 0x80510010,
7616 POWERPC_SVR_8349A = 0x80510030,
7617 POWERPC_SVR_8349E = 0x80500010,
7618 POWERPC_SVR_8349EA = 0x80500030,
7619 #if 0
7620 POWERPC_SVR_8358E = xxx,
7621 #endif
7622 #if 0
7623 POWERPC_SVR_8360E = xxx,
7624 #endif
7625 #define POWERPC_SVR_E500 0x40000000
7626 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7627 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7628 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7629 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7630 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7631 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
7632 #define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
7633 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7634 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
7635 #define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
7636 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7637 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
7638 #define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
7639 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7640 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7641 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
7642 #define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
7643 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7644 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
7645 #define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
7646 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7647 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
7648 #define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
7649 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7650 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7651 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7652 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
7653 #define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
7654 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7655 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7656 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7657 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
7658 #define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
7659 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7660 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
7661 #define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
7662 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7663 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
7664 #define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
7665 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7666 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
7667 #define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
7668 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7669 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
7670 #define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
7671 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7672 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
7673 #define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
7674 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7675 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7676 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7677 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
7678 #define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
7679 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7680 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7681 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7682 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
7683 #define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
7684 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7685 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
7686 #define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
7687 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7688 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
7689 #define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
7690 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7691 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7692 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7693 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7694 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7695 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7696 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7697 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7698 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
7699 #if 0
7700 POWERPC_SVR_8610 = xxx,
7701 #endif
7702 POWERPC_SVR_8641 = 0x80900021,
7703 POWERPC_SVR_8641D = 0x80900121,
7704 };
7705
7706 /*****************************************************************************/
7707 /* PowerPC CPU definitions */
7708 #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
7709 { \
7710 .name = _name, \
7711 .pvr = _pvr, \
7712 .svr = _svr, \
7713 .insns_flags = glue(POWERPC_INSNS_,_type), \
7714 .insns_flags2 = glue(POWERPC_INSNS2_,_type), \
7715 .msr_mask = glue(POWERPC_MSRM_,_type), \
7716 .mmu_model = glue(POWERPC_MMU_,_type), \
7717 .excp_model = glue(POWERPC_EXCP_,_type), \
7718 .bus_model = glue(POWERPC_INPUT_,_type), \
7719 .bfd_mach = glue(POWERPC_BFDM_,_type), \
7720 .flags = glue(POWERPC_FLAG_,_type), \
7721 .init_proc = &glue(init_proc_,_type), \
7722 .check_pow = &glue(check_pow_,_type), \
7723 }
7724 #define POWERPC_DEF(_name, _pvr, _type) \
7725 POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
7726
7727 static const ppc_def_t ppc_defs[] = {
7728 /* Embedded PowerPC */
7729 /* PowerPC 401 family */
7730 /* Generic PowerPC 401 */
7731 POWERPC_DEF("401", CPU_POWERPC_401, 401),
7732 /* PowerPC 401 cores */
7733 /* PowerPC 401A1 */
7734 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
7735 /* PowerPC 401B2 */
7736 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
7737 #if defined (TODO)
7738 /* PowerPC 401B3 */
7739 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
7740 #endif
7741 /* PowerPC 401C2 */
7742 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
7743 /* PowerPC 401D2 */
7744 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
7745 /* PowerPC 401E2 */
7746 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
7747 /* PowerPC 401F2 */
7748 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
7749 /* PowerPC 401G2 */
7750 /* XXX: to be checked */
7751 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
7752 /* PowerPC 401 microcontrolers */
7753 #if defined (TODO)
7754 /* PowerPC 401GF */
7755 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
7756 #endif
7757 /* IOP480 (401 microcontroler) */
7758 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
7759 /* IBM Processor for Network Resources */
7760 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
7761 #if defined (TODO)
7762 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
7763 #endif
7764 /* PowerPC 403 family */
7765 /* Generic PowerPC 403 */
7766 POWERPC_DEF("403", CPU_POWERPC_403, 403),
7767 /* PowerPC 403 microcontrolers */
7768 /* PowerPC 403 GA */
7769 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
7770 /* PowerPC 403 GB */
7771 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
7772 /* PowerPC 403 GC */
7773 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
7774 /* PowerPC 403 GCX */
7775 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
7776 #if defined (TODO)
7777 /* PowerPC 403 GP */
7778 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
7779 #endif
7780 /* PowerPC 405 family */
7781 /* Generic PowerPC 405 */
7782 POWERPC_DEF("405", CPU_POWERPC_405, 405),
7783 /* PowerPC 405 cores */
7784 #if defined (TODO)
7785 /* PowerPC 405 A3 */
7786 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
7787 #endif
7788 #if defined (TODO)
7789 /* PowerPC 405 A4 */
7790 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
7791 #endif
7792 #if defined (TODO)
7793 /* PowerPC 405 B3 */
7794 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
7795 #endif
7796 #if defined (TODO)
7797 /* PowerPC 405 B4 */
7798 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
7799 #endif
7800 #if defined (TODO)
7801 /* PowerPC 405 C3 */
7802 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
7803 #endif
7804 #if defined (TODO)
7805 /* PowerPC 405 C4 */
7806 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
7807 #endif
7808 /* PowerPC 405 D2 */
7809 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
7810 #if defined (TODO)
7811 /* PowerPC 405 D3 */
7812 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
7813 #endif
7814 /* PowerPC 405 D4 */
7815 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
7816 #if defined (TODO)
7817 /* PowerPC 405 D5 */
7818 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
7819 #endif
7820 #if defined (TODO)
7821 /* PowerPC 405 E4 */
7822 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
7823 #endif
7824 #if defined (TODO)
7825 /* PowerPC 405 F4 */
7826 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
7827 #endif
7828 #if defined (TODO)
7829 /* PowerPC 405 F5 */
7830 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
7831 #endif
7832 #if defined (TODO)
7833 /* PowerPC 405 F6 */
7834 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
7835 #endif
7836 /* PowerPC 405 microcontrolers */
7837 /* PowerPC 405 CR */
7838 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
7839 /* PowerPC 405 CRa */
7840 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
7841 /* PowerPC 405 CRb */
7842 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
7843 /* PowerPC 405 CRc */
7844 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
7845 /* PowerPC 405 EP */
7846 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
7847 #if defined(TODO)
7848 /* PowerPC 405 EXr */
7849 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
7850 #endif
7851 /* PowerPC 405 EZ */
7852 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
7853 #if defined(TODO)
7854 /* PowerPC 405 FX */
7855 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
7856 #endif
7857 /* PowerPC 405 GP */
7858 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
7859 /* PowerPC 405 GPa */
7860 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
7861 /* PowerPC 405 GPb */
7862 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
7863 /* PowerPC 405 GPc */
7864 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
7865 /* PowerPC 405 GPd */
7866 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
7867 /* PowerPC 405 GPe */
7868 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
7869 /* PowerPC 405 GPR */
7870 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
7871 #if defined(TODO)
7872 /* PowerPC 405 H */
7873 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
7874 #endif
7875 #if defined(TODO)
7876 /* PowerPC 405 L */
7877 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
7878 #endif
7879 /* PowerPC 405 LP */
7880 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
7881 #if defined(TODO)
7882 /* PowerPC 405 PM */
7883 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
7884 #endif
7885 #if defined(TODO)
7886 /* PowerPC 405 PS */
7887 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
7888 #endif
7889 #if defined(TODO)
7890 /* PowerPC 405 S */
7891 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
7892 #endif
7893 /* Npe405 H */
7894 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
7895 /* Npe405 H2 */
7896 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
7897 /* Npe405 L */
7898 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
7899 /* Npe4GS3 */
7900 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
7901 #if defined (TODO)
7902 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
7903 #endif
7904 #if defined (TODO)
7905 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
7906 #endif
7907 #if defined (TODO)
7908 /* PowerPC LC77700 (Sanyo) */
7909 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
7910 #endif
7911 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7912 #if defined (TODO)
7913 /* STB010000 */
7914 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
7915 #endif
7916 #if defined (TODO)
7917 /* STB01010 */
7918 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
7919 #endif
7920 #if defined (TODO)
7921 /* STB0210 */
7922 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
7923 #endif
7924 /* STB03xx */
7925 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
7926 #if defined (TODO)
7927 /* STB043x */
7928 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
7929 #endif
7930 #if defined (TODO)
7931 /* STB045x */
7932 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
7933 #endif
7934 /* STB04xx */
7935 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
7936 /* STB25xx */
7937 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
7938 #if defined (TODO)
7939 /* STB130 */
7940 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
7941 #endif
7942 /* Xilinx PowerPC 405 cores */
7943 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
7944 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
7945 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
7946 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
7947 #if defined (TODO)
7948 /* Zarlink ZL10310 */
7949 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
7950 #endif
7951 #if defined (TODO)
7952 /* Zarlink ZL10311 */
7953 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
7954 #endif
7955 #if defined (TODO)
7956 /* Zarlink ZL10320 */
7957 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
7958 #endif
7959 #if defined (TODO)
7960 /* Zarlink ZL10321 */
7961 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
7962 #endif
7963 /* PowerPC 440 family */
7964 #if defined(TODO_USER_ONLY)
7965 /* Generic PowerPC 440 */
7966 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
7967 #endif
7968 /* PowerPC 440 cores */
7969 #if defined (TODO)
7970 /* PowerPC 440 A4 */
7971 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
7972 #endif
7973 /* PowerPC 440 Xilinx 5 */
7974 POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5),
7975 #if defined (TODO)
7976 /* PowerPC 440 A5 */
7977 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
7978 #endif
7979 #if defined (TODO)
7980 /* PowerPC 440 B4 */
7981 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
7982 #endif
7983 #if defined (TODO)
7984 /* PowerPC 440 G4 */
7985 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
7986 #endif
7987 #if defined (TODO)
7988 /* PowerPC 440 F5 */
7989 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
7990 #endif
7991 #if defined (TODO)
7992 /* PowerPC 440 G5 */
7993 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
7994 #endif
7995 #if defined (TODO)
7996 /* PowerPC 440H4 */
7997 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
7998 #endif
7999 #if defined (TODO)
8000 /* PowerPC 440H6 */
8001 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
8002 #endif
8003 /* PowerPC 440 microcontrolers */
8004 /* PowerPC 440 EP */
8005 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
8006 /* PowerPC 440 EPa */
8007 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
8008 /* PowerPC 440 EPb */
8009 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
8010 /* PowerPC 440 EPX */
8011 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
8012 #if defined(TODO_USER_ONLY)
8013 /* PowerPC 440 GP */
8014 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
8015 #endif
8016 #if defined(TODO_USER_ONLY)
8017 /* PowerPC 440 GPb */
8018 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
8019 #endif
8020 #if defined(TODO_USER_ONLY)
8021 /* PowerPC 440 GPc */
8022 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
8023 #endif
8024 #if defined(TODO_USER_ONLY)
8025 /* PowerPC 440 GR */
8026 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
8027 #endif
8028 #if defined(TODO_USER_ONLY)
8029 /* PowerPC 440 GRa */
8030 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
8031 #endif
8032 #if defined(TODO_USER_ONLY)
8033 /* PowerPC 440 GRX */
8034 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
8035 #endif
8036 #if defined(TODO_USER_ONLY)
8037 /* PowerPC 440 GX */
8038 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
8039 #endif
8040 #if defined(TODO_USER_ONLY)
8041 /* PowerPC 440 GXa */
8042 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
8043 #endif
8044 #if defined(TODO_USER_ONLY)
8045 /* PowerPC 440 GXb */
8046 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
8047 #endif
8048 #if defined(TODO_USER_ONLY)
8049 /* PowerPC 440 GXc */
8050 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
8051 #endif
8052 #if defined(TODO_USER_ONLY)
8053 /* PowerPC 440 GXf */
8054 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
8055 #endif
8056 #if defined(TODO)
8057 /* PowerPC 440 S */
8058 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
8059 #endif
8060 #if defined(TODO_USER_ONLY)
8061 /* PowerPC 440 SP */
8062 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
8063 #endif
8064 #if defined(TODO_USER_ONLY)
8065 /* PowerPC 440 SP2 */
8066 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
8067 #endif
8068 #if defined(TODO_USER_ONLY)
8069 /* PowerPC 440 SPE */
8070 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
8071 #endif
8072 /* PowerPC 460 family */
8073 #if defined (TODO)
8074 /* Generic PowerPC 464 */
8075 POWERPC_DEF("464", CPU_POWERPC_464, 460),
8076 #endif
8077 /* PowerPC 464 microcontrolers */
8078 #if defined (TODO)
8079 /* PowerPC 464H90 */
8080 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
8081 #endif
8082 #if defined (TODO)
8083 /* PowerPC 464H90F */
8084 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
8085 #endif
8086 /* Freescale embedded PowerPC cores */
8087 /* MPC5xx family (aka RCPU) */
8088 #if defined(TODO_USER_ONLY)
8089 /* Generic MPC5xx core */
8090 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
8091 #endif
8092 #if defined(TODO_USER_ONLY)
8093 /* Codename for MPC5xx core */
8094 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
8095 #endif
8096 /* MPC5xx microcontrollers */
8097 #if defined(TODO_USER_ONLY)
8098 /* MGT560 */
8099 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
8100 #endif
8101 #if defined(TODO_USER_ONLY)
8102 /* MPC509 */
8103 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
8104 #endif
8105 #if defined(TODO_USER_ONLY)
8106 /* MPC533 */
8107 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
8108 #endif
8109 #if defined(TODO_USER_ONLY)
8110 /* MPC534 */
8111 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
8112 #endif
8113 #if defined(TODO_USER_ONLY)
8114 /* MPC555 */
8115 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
8116 #endif
8117 #if defined(TODO_USER_ONLY)
8118 /* MPC556 */
8119 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
8120 #endif
8121 #if defined(TODO_USER_ONLY)
8122 /* MPC560 */
8123 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
8124 #endif
8125 #if defined(TODO_USER_ONLY)
8126 /* MPC561 */
8127 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
8128 #endif
8129 #if defined(TODO_USER_ONLY)
8130 /* MPC562 */
8131 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
8132 #endif
8133 #if defined(TODO_USER_ONLY)
8134 /* MPC563 */
8135 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
8136 #endif
8137 #if defined(TODO_USER_ONLY)
8138 /* MPC564 */
8139 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
8140 #endif
8141 #if defined(TODO_USER_ONLY)
8142 /* MPC565 */
8143 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
8144 #endif
8145 #if defined(TODO_USER_ONLY)
8146 /* MPC566 */
8147 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
8148 #endif
8149 /* MPC8xx family (aka PowerQUICC) */
8150 #if defined(TODO_USER_ONLY)
8151 /* Generic MPC8xx core */
8152 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
8153 #endif
8154 #if defined(TODO_USER_ONLY)
8155 /* Codename for MPC8xx core */
8156 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
8157 #endif
8158 /* MPC8xx microcontrollers */
8159 #if defined(TODO_USER_ONLY)
8160 /* MGT823 */
8161 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
8162 #endif
8163 #if defined(TODO_USER_ONLY)
8164 /* MPC821 */
8165 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
8166 #endif
8167 #if defined(TODO_USER_ONLY)
8168 /* MPC823 */
8169 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
8170 #endif
8171 #if defined(TODO_USER_ONLY)
8172 /* MPC850 */
8173 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
8174 #endif
8175 #if defined(TODO_USER_ONLY)
8176 /* MPC852T */
8177 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
8178 #endif
8179 #if defined(TODO_USER_ONLY)
8180 /* MPC855T */
8181 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
8182 #endif
8183 #if defined(TODO_USER_ONLY)
8184 /* MPC857 */
8185 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
8186 #endif
8187 #if defined(TODO_USER_ONLY)
8188 /* MPC859 */
8189 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
8190 #endif
8191 #if defined(TODO_USER_ONLY)
8192 /* MPC860 */
8193 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
8194 #endif
8195 #if defined(TODO_USER_ONLY)
8196 /* MPC862 */
8197 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
8198 #endif
8199 #if defined(TODO_USER_ONLY)
8200 /* MPC866 */
8201 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
8202 #endif
8203 #if defined(TODO_USER_ONLY)
8204 /* MPC870 */
8205 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
8206 #endif
8207 #if defined(TODO_USER_ONLY)
8208 /* MPC875 */
8209 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
8210 #endif
8211 #if defined(TODO_USER_ONLY)
8212 /* MPC880 */
8213 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
8214 #endif
8215 #if defined(TODO_USER_ONLY)
8216 /* MPC885 */
8217 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
8218 #endif
8219 /* MPC82xx family (aka PowerQUICC-II) */
8220 /* Generic MPC52xx core */
8221 POWERPC_DEF_SVR("MPC52xx",
8222 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
8223 /* Generic MPC82xx core */
8224 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
8225 /* Codename for MPC82xx */
8226 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
8227 /* PowerPC G2 core */
8228 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
8229 /* PowerPC G2 H4 core */
8230 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
8231 /* PowerPC G2 GP core */
8232 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
8233 /* PowerPC G2 LS core */
8234 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
8235 /* PowerPC G2 HiP3 core */
8236 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
8237 /* PowerPC G2 HiP4 core */
8238 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
8239 /* PowerPC MPC603 core */
8240 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
8241 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
8242 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
8243 /* PowerPC G2LE GP core */
8244 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
8245 /* PowerPC G2LE LS core */
8246 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
8247 /* PowerPC G2LE GP1 core */
8248 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
8249 /* PowerPC G2LE GP3 core */
8250 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
8251 /* PowerPC MPC603 microcontrollers */
8252 /* MPC8240 */
8253 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
8254 /* PowerPC G2 microcontrollers */
8255 #if defined(TODO)
8256 /* MPC5121 */
8257 POWERPC_DEF_SVR("MPC5121",
8258 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
8259 #endif
8260 /* MPC5200 */
8261 POWERPC_DEF_SVR("MPC5200",
8262 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
8263 /* MPC5200 v1.0 */
8264 POWERPC_DEF_SVR("MPC5200_v10",
8265 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
8266 /* MPC5200 v1.1 */
8267 POWERPC_DEF_SVR("MPC5200_v11",
8268 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
8269 /* MPC5200 v1.2 */
8270 POWERPC_DEF_SVR("MPC5200_v12",
8271 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
8272 /* MPC5200B */
8273 POWERPC_DEF_SVR("MPC5200B",
8274 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
8275 /* MPC5200B v2.0 */
8276 POWERPC_DEF_SVR("MPC5200B_v20",
8277 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
8278 /* MPC5200B v2.1 */
8279 POWERPC_DEF_SVR("MPC5200B_v21",
8280 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
8281 /* MPC8241 */
8282 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
8283 /* MPC8245 */
8284 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
8285 /* MPC8247 */
8286 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
8287 /* MPC8248 */
8288 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
8289 /* MPC8250 */
8290 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
8291 /* MPC8250 HiP3 */
8292 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
8293 /* MPC8250 HiP4 */
8294 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
8295 /* MPC8255 */
8296 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
8297 /* MPC8255 HiP3 */
8298 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
8299 /* MPC8255 HiP4 */
8300 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
8301 /* MPC8260 */
8302 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
8303 /* MPC8260 HiP3 */
8304 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
8305 /* MPC8260 HiP4 */
8306 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
8307 /* MPC8264 */
8308 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
8309 /* MPC8264 HiP3 */
8310 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
8311 /* MPC8264 HiP4 */
8312 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
8313 /* MPC8265 */
8314 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
8315 /* MPC8265 HiP3 */
8316 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
8317 /* MPC8265 HiP4 */
8318 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
8319 /* MPC8266 */
8320 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
8321 /* MPC8266 HiP3 */
8322 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
8323 /* MPC8266 HiP4 */
8324 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
8325 /* MPC8270 */
8326 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
8327 /* MPC8271 */
8328 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
8329 /* MPC8272 */
8330 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
8331 /* MPC8275 */
8332 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
8333 /* MPC8280 */
8334 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
8335 /* e200 family */
8336 /* Generic PowerPC e200 core */
8337 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
8338 /* Generic MPC55xx core */
8339 #if defined (TODO)
8340 POWERPC_DEF_SVR("MPC55xx",
8341 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
8342 #endif
8343 #if defined (TODO)
8344 /* PowerPC e200z0 core */
8345 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
8346 #endif
8347 #if defined (TODO)
8348 /* PowerPC e200z1 core */
8349 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
8350 #endif
8351 #if defined (TODO)
8352 /* PowerPC e200z3 core */
8353 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
8354 #endif
8355 /* PowerPC e200z5 core */
8356 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
8357 /* PowerPC e200z6 core */
8358 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
8359 /* PowerPC e200 microcontrollers */
8360 #if defined (TODO)
8361 /* MPC5514E */
8362 POWERPC_DEF_SVR("MPC5514E",
8363 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
8364 #endif
8365 #if defined (TODO)
8366 /* MPC5514E v0 */
8367 POWERPC_DEF_SVR("MPC5514E_v0",
8368 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
8369 #endif
8370 #if defined (TODO)
8371 /* MPC5514E v1 */
8372 POWERPC_DEF_SVR("MPC5514E_v1",
8373 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
8374 #endif
8375 #if defined (TODO)
8376 /* MPC5514G */
8377 POWERPC_DEF_SVR("MPC5514G",
8378 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
8379 #endif
8380 #if defined (TODO)
8381 /* MPC5514G v0 */
8382 POWERPC_DEF_SVR("MPC5514G_v0",
8383 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
8384 #endif
8385 #if defined (TODO)
8386 /* MPC5514G v1 */
8387 POWERPC_DEF_SVR("MPC5514G_v1",
8388 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
8389 #endif
8390 #if defined (TODO)
8391 /* MPC5515S */
8392 POWERPC_DEF_SVR("MPC5515S",
8393 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
8394 #endif
8395 #if defined (TODO)
8396 /* MPC5516E */
8397 POWERPC_DEF_SVR("MPC5516E",
8398 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
8399 #endif
8400 #if defined (TODO)
8401 /* MPC5516E v0 */
8402 POWERPC_DEF_SVR("MPC5516E_v0",
8403 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
8404 #endif
8405 #if defined (TODO)
8406 /* MPC5516E v1 */
8407 POWERPC_DEF_SVR("MPC5516E_v1",
8408 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
8409 #endif
8410 #if defined (TODO)
8411 /* MPC5516G */
8412 POWERPC_DEF_SVR("MPC5516G",
8413 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
8414 #endif
8415 #if defined (TODO)
8416 /* MPC5516G v0 */
8417 POWERPC_DEF_SVR("MPC5516G_v0",
8418 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
8419 #endif
8420 #if defined (TODO)
8421 /* MPC5516G v1 */
8422 POWERPC_DEF_SVR("MPC5516G_v1",
8423 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
8424 #endif
8425 #if defined (TODO)
8426 /* MPC5516S */
8427 POWERPC_DEF_SVR("MPC5516S",
8428 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
8429 #endif
8430 #if defined (TODO)
8431 /* MPC5533 */
8432 POWERPC_DEF_SVR("MPC5533",
8433 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
8434 #endif
8435 #if defined (TODO)
8436 /* MPC5534 */
8437 POWERPC_DEF_SVR("MPC5534",
8438 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
8439 #endif
8440 #if defined (TODO)
8441 /* MPC5553 */
8442 POWERPC_DEF_SVR("MPC5553",
8443 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
8444 #endif
8445 #if defined (TODO)
8446 /* MPC5554 */
8447 POWERPC_DEF_SVR("MPC5554",
8448 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
8449 #endif
8450 #if defined (TODO)
8451 /* MPC5561 */
8452 POWERPC_DEF_SVR("MPC5561",
8453 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
8454 #endif
8455 #if defined (TODO)
8456 /* MPC5565 */
8457 POWERPC_DEF_SVR("MPC5565",
8458 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
8459 #endif
8460 #if defined (TODO)
8461 /* MPC5566 */
8462 POWERPC_DEF_SVR("MPC5566",
8463 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
8464 #endif
8465 #if defined (TODO)
8466 /* MPC5567 */
8467 POWERPC_DEF_SVR("MPC5567",
8468 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
8469 #endif
8470 /* e300 family */
8471 /* Generic PowerPC e300 core */
8472 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
8473 /* PowerPC e300c1 core */
8474 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
8475 /* PowerPC e300c2 core */
8476 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
8477 /* PowerPC e300c3 core */
8478 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
8479 /* PowerPC e300c4 core */
8480 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
8481 /* PowerPC e300 microcontrollers */
8482 #if defined (TODO)
8483 /* MPC8313 */
8484 POWERPC_DEF_SVR("MPC8313",
8485 CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300),
8486 #endif
8487 #if defined (TODO)
8488 /* MPC8313E */
8489 POWERPC_DEF_SVR("MPC8313E",
8490 CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300),
8491 #endif
8492 #if defined (TODO)
8493 /* MPC8314 */
8494 POWERPC_DEF_SVR("MPC8314",
8495 CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300),
8496 #endif
8497 #if defined (TODO)
8498 /* MPC8314E */
8499 POWERPC_DEF_SVR("MPC8314E",
8500 CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300),
8501 #endif
8502 #if defined (TODO)
8503 /* MPC8315 */
8504 POWERPC_DEF_SVR("MPC8315",
8505 CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300),
8506 #endif
8507 #if defined (TODO)
8508 /* MPC8315E */
8509 POWERPC_DEF_SVR("MPC8315E",
8510 CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300),
8511 #endif
8512 #if defined (TODO)
8513 /* MPC8321 */
8514 POWERPC_DEF_SVR("MPC8321",
8515 CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300),
8516 #endif
8517 #if defined (TODO)
8518 /* MPC8321E */
8519 POWERPC_DEF_SVR("MPC8321E",
8520 CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300),
8521 #endif
8522 #if defined (TODO)
8523 /* MPC8323 */
8524 POWERPC_DEF_SVR("MPC8323",
8525 CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300),
8526 #endif
8527 #if defined (TODO)
8528 /* MPC8323E */
8529 POWERPC_DEF_SVR("MPC8323E",
8530 CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300),
8531 #endif
8532 /* MPC8343 */
8533 POWERPC_DEF_SVR("MPC8343",
8534 CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300),
8535 /* MPC8343A */
8536 POWERPC_DEF_SVR("MPC8343A",
8537 CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300),
8538 /* MPC8343E */
8539 POWERPC_DEF_SVR("MPC8343E",
8540 CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300),
8541 /* MPC8343EA */
8542 POWERPC_DEF_SVR("MPC8343EA",
8543 CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300),
8544 /* MPC8347 */
8545 POWERPC_DEF_SVR("MPC8347",
8546 CPU_POWERPC_MPC834x, POWERPC_SVR_8347, e300),
8547 /* MPC8347T */
8548 POWERPC_DEF_SVR("MPC8347T",
8549 CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300),
8550 /* MPC8347P */
8551 POWERPC_DEF_SVR("MPC8347P",
8552 CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300),
8553 /* MPC8347A */
8554 POWERPC_DEF_SVR("MPC8347A",
8555 CPU_POWERPC_MPC834x, POWERPC_SVR_8347A, e300),
8556 /* MPC8347AT */
8557 POWERPC_DEF_SVR("MPC8347AT",
8558 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300),
8559 /* MPC8347AP */
8560 POWERPC_DEF_SVR("MPC8347AP",
8561 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300),
8562 /* MPC8347E */
8563 POWERPC_DEF_SVR("MPC8347E",
8564 CPU_POWERPC_MPC834x, POWERPC_SVR_8347E, e300),
8565 /* MPC8347ET */
8566 POWERPC_DEF_SVR("MPC8347ET",
8567 CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300),
8568 /* MPC8343EP */
8569 POWERPC_DEF_SVR("MPC8347EP",
8570 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300),
8571 /* MPC8347EA */
8572 POWERPC_DEF_SVR("MPC8347EA",
8573 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EA, e300),
8574 /* MPC8347EAT */
8575 POWERPC_DEF_SVR("MPC8347EAT",
8576 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300),
8577 /* MPC8343EAP */
8578 POWERPC_DEF_SVR("MPC8347EAP",
8579 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300),
8580 /* MPC8349 */
8581 POWERPC_DEF_SVR("MPC8349",
8582 CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300),
8583 /* MPC8349A */
8584 POWERPC_DEF_SVR("MPC8349A",
8585 CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300),
8586 /* MPC8349E */
8587 POWERPC_DEF_SVR("MPC8349E",
8588 CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300),
8589 /* MPC8349EA */
8590 POWERPC_DEF_SVR("MPC8349EA",
8591 CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300),
8592 #if defined (TODO)
8593 /* MPC8358E */
8594 POWERPC_DEF_SVR("MPC8358E",
8595 CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300),
8596 #endif
8597 #if defined (TODO)
8598 /* MPC8360E */
8599 POWERPC_DEF_SVR("MPC8360E",
8600 CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300),
8601 #endif
8602 /* MPC8377 */
8603 POWERPC_DEF_SVR("MPC8377",
8604 CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300),
8605 /* MPC8377E */
8606 POWERPC_DEF_SVR("MPC8377E",
8607 CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300),
8608 /* MPC8378 */
8609 POWERPC_DEF_SVR("MPC8378",
8610 CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300),
8611 /* MPC8378E */
8612 POWERPC_DEF_SVR("MPC8378E",
8613 CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300),
8614 /* MPC8379 */
8615 POWERPC_DEF_SVR("MPC8379",
8616 CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300),
8617 /* MPC8379E */
8618 POWERPC_DEF_SVR("MPC8379E",
8619 CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300),
8620 /* e500 family */
8621 /* PowerPC e500 core */
8622 POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2),
8623 /* PowerPC e500v1 core */
8624 POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1),
8625 /* PowerPC e500 v1.0 core */
8626 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1),
8627 /* PowerPC e500 v2.0 core */
8628 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1),
8629 /* PowerPC e500v2 core */
8630 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2),
8631 /* PowerPC e500v2 v1.0 core */
8632 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2),
8633 /* PowerPC e500v2 v2.0 core */
8634 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2),
8635 /* PowerPC e500v2 v2.1 core */
8636 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2),
8637 /* PowerPC e500v2 v2.2 core */
8638 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2),
8639 /* PowerPC e500v2 v3.0 core */
8640 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
8641 POWERPC_DEF("e500mc", CPU_POWERPC_e500mc, e500mc),
8642 #ifdef TARGET_PPC64
8643 POWERPC_DEF("e5500", CPU_POWERPC_e5500, e5500),
8644 #endif
8645 /* PowerPC e500 microcontrollers */
8646 /* MPC8533 */
8647 POWERPC_DEF_SVR("MPC8533",
8648 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2),
8649 /* MPC8533 v1.0 */
8650 POWERPC_DEF_SVR("MPC8533_v10",
8651 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2),
8652 /* MPC8533 v1.1 */
8653 POWERPC_DEF_SVR("MPC8533_v11",
8654 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2),
8655 /* MPC8533E */
8656 POWERPC_DEF_SVR("MPC8533E",
8657 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2),
8658 /* MPC8533E v1.0 */
8659 POWERPC_DEF_SVR("MPC8533E_v10",
8660 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
8661 POWERPC_DEF_SVR("MPC8533E_v11",
8662 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
8663 /* MPC8540 */
8664 POWERPC_DEF_SVR("MPC8540",
8665 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1),
8666 /* MPC8540 v1.0 */
8667 POWERPC_DEF_SVR("MPC8540_v10",
8668 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1),
8669 /* MPC8540 v2.0 */
8670 POWERPC_DEF_SVR("MPC8540_v20",
8671 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1),
8672 /* MPC8540 v2.1 */
8673 POWERPC_DEF_SVR("MPC8540_v21",
8674 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1),
8675 /* MPC8541 */
8676 POWERPC_DEF_SVR("MPC8541",
8677 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1),
8678 /* MPC8541 v1.0 */
8679 POWERPC_DEF_SVR("MPC8541_v10",
8680 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1),
8681 /* MPC8541 v1.1 */
8682 POWERPC_DEF_SVR("MPC8541_v11",
8683 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1),
8684 /* MPC8541E */
8685 POWERPC_DEF_SVR("MPC8541E",
8686 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1),
8687 /* MPC8541E v1.0 */
8688 POWERPC_DEF_SVR("MPC8541E_v10",
8689 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
8690 /* MPC8541E v1.1 */
8691 POWERPC_DEF_SVR("MPC8541E_v11",
8692 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
8693 /* MPC8543 */
8694 POWERPC_DEF_SVR("MPC8543",
8695 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2),
8696 /* MPC8543 v1.0 */
8697 POWERPC_DEF_SVR("MPC8543_v10",
8698 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2),
8699 /* MPC8543 v1.1 */
8700 POWERPC_DEF_SVR("MPC8543_v11",
8701 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2),
8702 /* MPC8543 v2.0 */
8703 POWERPC_DEF_SVR("MPC8543_v20",
8704 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2),
8705 /* MPC8543 v2.1 */
8706 POWERPC_DEF_SVR("MPC8543_v21",
8707 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2),
8708 /* MPC8543E */
8709 POWERPC_DEF_SVR("MPC8543E",
8710 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2),
8711 /* MPC8543E v1.0 */
8712 POWERPC_DEF_SVR("MPC8543E_v10",
8713 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
8714 /* MPC8543E v1.1 */
8715 POWERPC_DEF_SVR("MPC8543E_v11",
8716 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
8717 /* MPC8543E v2.0 */
8718 POWERPC_DEF_SVR("MPC8543E_v20",
8719 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
8720 /* MPC8543E v2.1 */
8721 POWERPC_DEF_SVR("MPC8543E_v21",
8722 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
8723 /* MPC8544 */
8724 POWERPC_DEF_SVR("MPC8544",
8725 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2),
8726 /* MPC8544 v1.0 */
8727 POWERPC_DEF_SVR("MPC8544_v10",
8728 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2),
8729 /* MPC8544 v1.1 */
8730 POWERPC_DEF_SVR("MPC8544_v11",
8731 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2),
8732 /* MPC8544E */
8733 POWERPC_DEF_SVR("MPC8544E",
8734 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2),
8735 /* MPC8544E v1.0 */
8736 POWERPC_DEF_SVR("MPC8544E_v10",
8737 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
8738 /* MPC8544E v1.1 */
8739 POWERPC_DEF_SVR("MPC8544E_v11",
8740 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
8741 /* MPC8545 */
8742 POWERPC_DEF_SVR("MPC8545",
8743 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2),
8744 /* MPC8545 v2.0 */
8745 POWERPC_DEF_SVR("MPC8545_v20",
8746 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2),
8747 /* MPC8545 v2.1 */
8748 POWERPC_DEF_SVR("MPC8545_v21",
8749 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2),
8750 /* MPC8545E */
8751 POWERPC_DEF_SVR("MPC8545E",
8752 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2),
8753 /* MPC8545E v2.0 */
8754 POWERPC_DEF_SVR("MPC8545E_v20",
8755 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
8756 /* MPC8545E v2.1 */
8757 POWERPC_DEF_SVR("MPC8545E_v21",
8758 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
8759 /* MPC8547E */
8760 POWERPC_DEF_SVR("MPC8547E",
8761 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2),
8762 /* MPC8547E v2.0 */
8763 POWERPC_DEF_SVR("MPC8547E_v20",
8764 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
8765 /* MPC8547E v2.1 */
8766 POWERPC_DEF_SVR("MPC8547E_v21",
8767 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
8768 /* MPC8548 */
8769 POWERPC_DEF_SVR("MPC8548",
8770 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2),
8771 /* MPC8548 v1.0 */
8772 POWERPC_DEF_SVR("MPC8548_v10",
8773 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2),
8774 /* MPC8548 v1.1 */
8775 POWERPC_DEF_SVR("MPC8548_v11",
8776 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2),
8777 /* MPC8548 v2.0 */
8778 POWERPC_DEF_SVR("MPC8548_v20",
8779 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2),
8780 /* MPC8548 v2.1 */
8781 POWERPC_DEF_SVR("MPC8548_v21",
8782 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2),
8783 /* MPC8548E */
8784 POWERPC_DEF_SVR("MPC8548E",
8785 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2),
8786 /* MPC8548E v1.0 */
8787 POWERPC_DEF_SVR("MPC8548E_v10",
8788 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
8789 /* MPC8548E v1.1 */
8790 POWERPC_DEF_SVR("MPC8548E_v11",
8791 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
8792 /* MPC8548E v2.0 */
8793 POWERPC_DEF_SVR("MPC8548E_v20",
8794 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
8795 /* MPC8548E v2.1 */
8796 POWERPC_DEF_SVR("MPC8548E_v21",
8797 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
8798 /* MPC8555 */
8799 POWERPC_DEF_SVR("MPC8555",
8800 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2),
8801 /* MPC8555 v1.0 */
8802 POWERPC_DEF_SVR("MPC8555_v10",
8803 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2),
8804 /* MPC8555 v1.1 */
8805 POWERPC_DEF_SVR("MPC8555_v11",
8806 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2),
8807 /* MPC8555E */
8808 POWERPC_DEF_SVR("MPC8555E",
8809 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2),
8810 /* MPC8555E v1.0 */
8811 POWERPC_DEF_SVR("MPC8555E_v10",
8812 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
8813 /* MPC8555E v1.1 */
8814 POWERPC_DEF_SVR("MPC8555E_v11",
8815 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
8816 /* MPC8560 */
8817 POWERPC_DEF_SVR("MPC8560",
8818 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2),
8819 /* MPC8560 v1.0 */
8820 POWERPC_DEF_SVR("MPC8560_v10",
8821 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2),
8822 /* MPC8560 v2.0 */
8823 POWERPC_DEF_SVR("MPC8560_v20",
8824 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2),
8825 /* MPC8560 v2.1 */
8826 POWERPC_DEF_SVR("MPC8560_v21",
8827 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2),
8828 /* MPC8567 */
8829 POWERPC_DEF_SVR("MPC8567",
8830 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2),
8831 /* MPC8567E */
8832 POWERPC_DEF_SVR("MPC8567E",
8833 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2),
8834 /* MPC8568 */
8835 POWERPC_DEF_SVR("MPC8568",
8836 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2),
8837 /* MPC8568E */
8838 POWERPC_DEF_SVR("MPC8568E",
8839 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2),
8840 /* MPC8572 */
8841 POWERPC_DEF_SVR("MPC8572",
8842 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2),
8843 /* MPC8572E */
8844 POWERPC_DEF_SVR("MPC8572E",
8845 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2),
8846 /* e600 family */
8847 /* PowerPC e600 core */
8848 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
8849 /* PowerPC e600 microcontrollers */
8850 #if defined (TODO)
8851 /* MPC8610 */
8852 POWERPC_DEF_SVR("MPC8610",
8853 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
8854 #endif
8855 /* MPC8641 */
8856 POWERPC_DEF_SVR("MPC8641",
8857 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
8858 /* MPC8641D */
8859 POWERPC_DEF_SVR("MPC8641D",
8860 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
8861 /* 32 bits "classic" PowerPC */
8862 /* PowerPC 6xx family */
8863 /* PowerPC 601 */
8864 POWERPC_DEF("601", CPU_POWERPC_601, 601v),
8865 /* PowerPC 601v0 */
8866 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
8867 /* PowerPC 601v1 */
8868 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
8869 /* PowerPC 601v */
8870 POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
8871 /* PowerPC 601v2 */
8872 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
8873 /* PowerPC 602 */
8874 POWERPC_DEF("602", CPU_POWERPC_602, 602),
8875 /* PowerPC 603 */
8876 POWERPC_DEF("603", CPU_POWERPC_603, 603),
8877 /* Code name for PowerPC 603 */
8878 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
8879 /* PowerPC 603e (aka PID6) */
8880 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
8881 /* Code name for PowerPC 603e */
8882 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
8883 /* PowerPC 603e v1.1 */
8884 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
8885 /* PowerPC 603e v1.2 */
8886 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
8887 /* PowerPC 603e v1.3 */
8888 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
8889 /* PowerPC 603e v1.4 */
8890 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
8891 /* PowerPC 603e v2.2 */
8892 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
8893 /* PowerPC 603e v3 */
8894 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
8895 /* PowerPC 603e v4 */
8896 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
8897 /* PowerPC 603e v4.1 */
8898 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
8899 /* PowerPC 603e (aka PID7) */
8900 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
8901 /* PowerPC 603e7t */
8902 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
8903 /* PowerPC 603e7v */
8904 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
8905 /* Code name for PowerPC 603ev */
8906 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
8907 /* PowerPC 603e7v1 */
8908 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
8909 /* PowerPC 603e7v2 */
8910 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
8911 /* PowerPC 603p (aka PID7v) */
8912 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
8913 /* PowerPC 603r (aka PID7t) */
8914 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
8915 /* Code name for PowerPC 603r */
8916 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
8917 /* PowerPC 604 */
8918 POWERPC_DEF("604", CPU_POWERPC_604, 604),
8919 /* PowerPC 604e (aka PID9) */
8920 POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
8921 /* Code name for PowerPC 604e */
8922 POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
8923 /* PowerPC 604e v1.0 */
8924 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
8925 /* PowerPC 604e v2.2 */
8926 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
8927 /* PowerPC 604e v2.4 */
8928 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
8929 /* PowerPC 604r (aka PIDA) */
8930 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
8931 /* Code name for PowerPC 604r */
8932 POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
8933 #if defined(TODO)
8934 /* PowerPC 604ev */
8935 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
8936 #endif
8937 /* PowerPC 7xx family */
8938 /* Generic PowerPC 740 (G3) */
8939 POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
8940 /* Code name for PowerPC 740 */
8941 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
8942 /* Generic PowerPC 750 (G3) */
8943 POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
8944 /* Code name for PowerPC 750 */
8945 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
8946 /* PowerPC 740/750 is also known as G3 */
8947 POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
8948 /* PowerPC 740 v1.0 (G3) */
8949 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
8950 /* PowerPC 750 v1.0 (G3) */
8951 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
8952 /* PowerPC 740 v2.0 (G3) */
8953 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
8954 /* PowerPC 750 v2.0 (G3) */
8955 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
8956 /* PowerPC 740 v2.1 (G3) */
8957 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
8958 /* PowerPC 750 v2.1 (G3) */
8959 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
8960 /* PowerPC 740 v2.2 (G3) */
8961 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
8962 /* PowerPC 750 v2.2 (G3) */
8963 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
8964 /* PowerPC 740 v3.0 (G3) */
8965 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
8966 /* PowerPC 750 v3.0 (G3) */
8967 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
8968 /* PowerPC 740 v3.1 (G3) */
8969 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
8970 /* PowerPC 750 v3.1 (G3) */
8971 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
8972 /* PowerPC 740E (G3) */
8973 POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
8974 /* PowerPC 750E (G3) */
8975 POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
8976 /* PowerPC 740P (G3) */
8977 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
8978 /* PowerPC 750P (G3) */
8979 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
8980 /* Code name for PowerPC 740P/750P (G3) */
8981 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
8982 /* PowerPC 750CL (G3 embedded) */
8983 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
8984 /* PowerPC 750CL v1.0 */
8985 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
8986 /* PowerPC 750CL v2.0 */
8987 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
8988 /* PowerPC 750CX (G3 embedded) */
8989 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
8990 /* PowerPC 750CX v1.0 (G3 embedded) */
8991 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
8992 /* PowerPC 750CX v2.1 (G3 embedded) */
8993 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
8994 /* PowerPC 750CX v2.1 (G3 embedded) */
8995 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
8996 /* PowerPC 750CX v2.2 (G3 embedded) */
8997 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
8998 /* PowerPC 750CXe (G3 embedded) */
8999 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
9000 /* PowerPC 750CXe v2.1 (G3 embedded) */
9001 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
9002 /* PowerPC 750CXe v2.2 (G3 embedded) */
9003 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
9004 /* PowerPC 750CXe v2.3 (G3 embedded) */
9005 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
9006 /* PowerPC 750CXe v2.4 (G3 embedded) */
9007 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
9008 /* PowerPC 750CXe v2.4b (G3 embedded) */
9009 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
9010 /* PowerPC 750CXe v3.0 (G3 embedded) */
9011 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
9012 /* PowerPC 750CXe v3.1 (G3 embedded) */
9013 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
9014 /* PowerPC 750CXe v3.1b (G3 embedded) */
9015 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
9016 /* PowerPC 750CXr (G3 embedded) */
9017 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
9018 /* PowerPC 750FL (G3 embedded) */
9019 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
9020 /* PowerPC 750FX (G3 embedded) */
9021 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
9022 /* PowerPC 750FX v1.0 (G3 embedded) */
9023 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
9024 /* PowerPC 750FX v2.0 (G3 embedded) */
9025 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
9026 /* PowerPC 750FX v2.1 (G3 embedded) */
9027 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
9028 /* PowerPC 750FX v2.2 (G3 embedded) */
9029 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
9030 /* PowerPC 750FX v2.3 (G3 embedded) */
9031 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
9032 /* PowerPC 750GL (G3 embedded) */
9033 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
9034 /* PowerPC 750GX (G3 embedded) */
9035 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
9036 /* PowerPC 750GX v1.0 (G3 embedded) */
9037 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
9038 /* PowerPC 750GX v1.1 (G3 embedded) */
9039 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
9040 /* PowerPC 750GX v1.2 (G3 embedded) */
9041 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
9042 /* PowerPC 750L (G3 embedded) */
9043 POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
9044 /* Code name for PowerPC 750L (G3 embedded) */
9045 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
9046 /* PowerPC 750L v2.0 (G3 embedded) */
9047 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
9048 /* PowerPC 750L v2.1 (G3 embedded) */
9049 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
9050 /* PowerPC 750L v2.2 (G3 embedded) */
9051 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
9052 /* PowerPC 750L v3.0 (G3 embedded) */
9053 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
9054 /* PowerPC 750L v3.2 (G3 embedded) */
9055 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
9056 /* Generic PowerPC 745 */
9057 POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
9058 /* Generic PowerPC 755 */
9059 POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
9060 /* Code name for PowerPC 745/755 */
9061 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
9062 /* PowerPC 745 v1.0 */
9063 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
9064 /* PowerPC 755 v1.0 */
9065 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
9066 /* PowerPC 745 v1.1 */
9067 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
9068 /* PowerPC 755 v1.1 */
9069 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
9070 /* PowerPC 745 v2.0 */
9071 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
9072 /* PowerPC 755 v2.0 */
9073 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
9074 /* PowerPC 745 v2.1 */
9075 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
9076 /* PowerPC 755 v2.1 */
9077 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
9078 /* PowerPC 745 v2.2 */
9079 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
9080 /* PowerPC 755 v2.2 */
9081 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
9082 /* PowerPC 745 v2.3 */
9083 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
9084 /* PowerPC 755 v2.3 */
9085 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
9086 /* PowerPC 745 v2.4 */
9087 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
9088 /* PowerPC 755 v2.4 */
9089 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
9090 /* PowerPC 745 v2.5 */
9091 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
9092 /* PowerPC 755 v2.5 */
9093 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
9094 /* PowerPC 745 v2.6 */
9095 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
9096 /* PowerPC 755 v2.6 */
9097 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
9098 /* PowerPC 745 v2.7 */
9099 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
9100 /* PowerPC 755 v2.7 */
9101 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
9102 /* PowerPC 745 v2.8 */
9103 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
9104 /* PowerPC 755 v2.8 */
9105 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
9106 #if defined (TODO)
9107 /* PowerPC 745P (G3) */
9108 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
9109 /* PowerPC 755P (G3) */
9110 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
9111 #endif
9112 /* PowerPC 74xx family */
9113 /* PowerPC 7400 (G4) */
9114 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
9115 /* Code name for PowerPC 7400 */
9116 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
9117 /* PowerPC 74xx is also well known as G4 */
9118 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
9119 /* PowerPC 7400 v1.0 (G4) */
9120 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
9121 /* PowerPC 7400 v1.1 (G4) */
9122 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
9123 /* PowerPC 7400 v2.0 (G4) */
9124 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
9125 /* PowerPC 7400 v2.1 (G4) */
9126 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
9127 /* PowerPC 7400 v2.2 (G4) */
9128 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
9129 /* PowerPC 7400 v2.6 (G4) */
9130 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
9131 /* PowerPC 7400 v2.7 (G4) */
9132 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
9133 /* PowerPC 7400 v2.8 (G4) */
9134 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
9135 /* PowerPC 7400 v2.9 (G4) */
9136 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
9137 /* PowerPC 7410 (G4) */
9138 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
9139 /* Code name for PowerPC 7410 */
9140 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
9141 /* PowerPC 7410 v1.0 (G4) */
9142 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
9143 /* PowerPC 7410 v1.1 (G4) */
9144 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
9145 /* PowerPC 7410 v1.2 (G4) */
9146 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
9147 /* PowerPC 7410 v1.3 (G4) */
9148 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
9149 /* PowerPC 7410 v1.4 (G4) */
9150 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
9151 /* PowerPC 7448 (G4) */
9152 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
9153 /* PowerPC 7448 v1.0 (G4) */
9154 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
9155 /* PowerPC 7448 v1.1 (G4) */
9156 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
9157 /* PowerPC 7448 v2.0 (G4) */
9158 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
9159 /* PowerPC 7448 v2.1 (G4) */
9160 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
9161 /* PowerPC 7450 (G4) */
9162 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
9163 /* Code name for PowerPC 7450 */
9164 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
9165 /* PowerPC 7450 v1.0 (G4) */
9166 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
9167 /* PowerPC 7450 v1.1 (G4) */
9168 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
9169 /* PowerPC 7450 v1.2 (G4) */
9170 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
9171 /* PowerPC 7450 v2.0 (G4) */
9172 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
9173 /* PowerPC 7450 v2.1 (G4) */
9174 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
9175 /* PowerPC 7441 (G4) */
9176 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
9177 /* PowerPC 7451 (G4) */
9178 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
9179 /* PowerPC 7441 v2.1 (G4) */
9180 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
9181 /* PowerPC 7441 v2.3 (G4) */
9182 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
9183 /* PowerPC 7451 v2.3 (G4) */
9184 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
9185 /* PowerPC 7441 v2.10 (G4) */
9186 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
9187 /* PowerPC 7451 v2.10 (G4) */
9188 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
9189 /* PowerPC 7445 (G4) */
9190 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
9191 /* PowerPC 7455 (G4) */
9192 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
9193 /* Code name for PowerPC 7445/7455 */
9194 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
9195 /* PowerPC 7445 v1.0 (G4) */
9196 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
9197 /* PowerPC 7455 v1.0 (G4) */
9198 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
9199 /* PowerPC 7445 v2.1 (G4) */
9200 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
9201 /* PowerPC 7455 v2.1 (G4) */
9202 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
9203 /* PowerPC 7445 v3.2 (G4) */
9204 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
9205 /* PowerPC 7455 v3.2 (G4) */
9206 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
9207 /* PowerPC 7445 v3.3 (G4) */
9208 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
9209 /* PowerPC 7455 v3.3 (G4) */
9210 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
9211 /* PowerPC 7445 v3.4 (G4) */
9212 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
9213 /* PowerPC 7455 v3.4 (G4) */
9214 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
9215 /* PowerPC 7447 (G4) */
9216 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
9217 /* PowerPC 7457 (G4) */
9218 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
9219 /* Code name for PowerPC 7447/7457 */
9220 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
9221 /* PowerPC 7447 v1.0 (G4) */
9222 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
9223 /* PowerPC 7457 v1.0 (G4) */
9224 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
9225 /* PowerPC 7447 v1.1 (G4) */
9226 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
9227 /* PowerPC 7457 v1.1 (G4) */
9228 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
9229 /* PowerPC 7457 v1.2 (G4) */
9230 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
9231 /* PowerPC 7447A (G4) */
9232 POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
9233 /* PowerPC 7457A (G4) */
9234 POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
9235 /* PowerPC 7447A v1.0 (G4) */
9236 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
9237 /* PowerPC 7457A v1.0 (G4) */
9238 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
9239 /* Code name for PowerPC 7447A/7457A */
9240 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
9241 /* PowerPC 7447A v1.1 (G4) */
9242 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
9243 /* PowerPC 7457A v1.1 (G4) */
9244 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
9245 /* PowerPC 7447A v1.2 (G4) */
9246 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
9247 /* PowerPC 7457A v1.2 (G4) */
9248 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
9249 /* 64 bits PowerPC */
9250 #if defined (TARGET_PPC64)
9251 /* PowerPC 620 */
9252 POWERPC_DEF("620", CPU_POWERPC_620, 620),
9253 /* Code name for PowerPC 620 */
9254 POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
9255 #if defined (TODO)
9256 /* PowerPC 630 (POWER3) */
9257 POWERPC_DEF("630", CPU_POWERPC_630, 630),
9258 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
9259 /* Code names for POWER3 */
9260 POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
9261 POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
9262 #endif
9263 #if defined (TODO)
9264 /* PowerPC 631 (Power 3+) */
9265 POWERPC_DEF("631", CPU_POWERPC_631, 631),
9266 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
9267 #endif
9268 #if defined (TODO)
9269 /* POWER4 */
9270 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
9271 #endif
9272 #if defined (TODO)
9273 /* POWER4p */
9274 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
9275 #endif
9276 #if defined (TODO)
9277 /* POWER5 */
9278 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
9279 /* POWER5GR */
9280 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
9281 #endif
9282 #if defined (TODO)
9283 /* POWER5+ */
9284 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
9285 /* POWER5GS */
9286 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
9287 #endif
9288 #if defined (TODO)
9289 /* POWER6 */
9290 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
9291 /* POWER6 running in POWER5 mode */
9292 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
9293 /* POWER6A */
9294 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
9295 #endif
9296 /* POWER7 */
9297 POWERPC_DEF("POWER7", CPU_POWERPC_POWER7, POWER7),
9298 POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7),
9299 POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21, POWER7),
9300 POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7),
9301 /* PowerPC 970 */
9302 POWERPC_DEF("970", CPU_POWERPC_970, 970),
9303 /* PowerPC 970FX (G5) */
9304 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
9305 /* PowerPC 970FX v1.0 (G5) */
9306 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
9307 /* PowerPC 970FX v2.0 (G5) */
9308 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
9309 /* PowerPC 970FX v2.1 (G5) */
9310 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
9311 /* PowerPC 970FX v3.0 (G5) */
9312 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
9313 /* PowerPC 970FX v3.1 (G5) */
9314 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
9315 /* PowerPC 970GX (G5) */
9316 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
9317 /* PowerPC 970MP */
9318 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
9319 /* PowerPC 970MP v1.0 */
9320 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
9321 /* PowerPC 970MP v1.1 */
9322 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
9323 #if defined (TODO)
9324 /* PowerPC Cell */
9325 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
9326 #endif
9327 #if defined (TODO)
9328 /* PowerPC Cell v1.0 */
9329 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
9330 #endif
9331 #if defined (TODO)
9332 /* PowerPC Cell v2.0 */
9333 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
9334 #endif
9335 #if defined (TODO)
9336 /* PowerPC Cell v3.0 */
9337 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
9338 #endif
9339 #if defined (TODO)
9340 /* PowerPC Cell v3.1 */
9341 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
9342 #endif
9343 #if defined (TODO)
9344 /* PowerPC Cell v3.2 */
9345 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
9346 #endif
9347 #if defined (TODO)
9348 /* RS64 (Apache/A35) */
9349 /* This one seems to support the whole POWER2 instruction set
9350 * and the PowerPC 64 one.
9351 */
9352 /* What about A10 & A30 ? */
9353 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
9354 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
9355 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
9356 #endif
9357 #if defined (TODO)
9358 /* RS64-II (NorthStar/A50) */
9359 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
9360 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
9361 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
9362 #endif
9363 #if defined (TODO)
9364 /* RS64-III (Pulsar) */
9365 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
9366 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
9367 #endif
9368 #if defined (TODO)
9369 /* RS64-IV (IceStar/IStar/SStar) */
9370 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
9371 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
9372 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
9373 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
9374 #endif
9375 #endif /* defined (TARGET_PPC64) */
9376 /* POWER */
9377 #if defined (TODO)
9378 /* Original POWER */
9379 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
9380 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
9381 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
9382 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
9383 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
9384 #endif
9385 #if defined (TODO)
9386 /* POWER2 */
9387 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
9388 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
9389 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
9390 #endif
9391 /* PA semi cores */
9392 #if defined (TODO)
9393 /* PA PA6T */
9394 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
9395 #endif
9396 /* Generic PowerPCs */
9397 #if defined (TARGET_PPC64)
9398 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
9399 #endif
9400 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
9401 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
9402 /* Fallback */
9403 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
9404 };
9405
9406 /*****************************************************************************/
9407 /* Generic CPU instantiation routine */
9408 static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
9409 {
9410 #if !defined(CONFIG_USER_ONLY)
9411 int i;
9412
9413 env->irq_inputs = NULL;
9414 /* Set all exception vectors to an invalid address */
9415 for (i = 0; i < POWERPC_EXCP_NB; i++)
9416 env->excp_vectors[i] = (target_ulong)(-1ULL);
9417 env->hreset_excp_prefix = 0x00000000;
9418 env->ivor_mask = 0x00000000;
9419 env->ivpr_mask = 0x00000000;
9420 /* Default MMU definitions */
9421 env->nb_BATs = 0;
9422 env->nb_tlb = 0;
9423 env->nb_ways = 0;
9424 env->tlb_type = TLB_NONE;
9425 #endif
9426 /* Register SPR common to all PowerPC implementations */
9427 gen_spr_generic(env);
9428 spr_register(env, SPR_PVR, "PVR",
9429 /* Linux permits userspace to read PVR */
9430 #if defined(CONFIG_LINUX_USER)
9431 &spr_read_generic,
9432 #else
9433 SPR_NOACCESS,
9434 #endif
9435 SPR_NOACCESS,
9436 &spr_read_generic, SPR_NOACCESS,
9437 def->pvr);
9438 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
9439 if (def->svr != POWERPC_SVR_NONE) {
9440 if (def->svr & POWERPC_SVR_E500) {
9441 spr_register(env, SPR_E500_SVR, "SVR",
9442 SPR_NOACCESS, SPR_NOACCESS,
9443 &spr_read_generic, SPR_NOACCESS,
9444 def->svr & ~POWERPC_SVR_E500);
9445 } else {
9446 spr_register(env, SPR_SVR, "SVR",
9447 SPR_NOACCESS, SPR_NOACCESS,
9448 &spr_read_generic, SPR_NOACCESS,
9449 def->svr);
9450 }
9451 }
9452 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
9453 (*def->init_proc)(env);
9454 #if !defined(CONFIG_USER_ONLY)
9455 env->excp_prefix = env->hreset_excp_prefix;
9456 #endif
9457 /* MSR bits & flags consistency checks */
9458 if (env->msr_mask & (1 << 25)) {
9459 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9460 case POWERPC_FLAG_SPE:
9461 case POWERPC_FLAG_VRE:
9462 break;
9463 default:
9464 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9465 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9466 exit(1);
9467 }
9468 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9469 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9470 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9471 exit(1);
9472 }
9473 if (env->msr_mask & (1 << 17)) {
9474 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9475 case POWERPC_FLAG_TGPR:
9476 case POWERPC_FLAG_CE:
9477 break;
9478 default:
9479 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9480 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9481 exit(1);
9482 }
9483 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9484 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9485 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9486 exit(1);
9487 }
9488 if (env->msr_mask & (1 << 10)) {
9489 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9490 POWERPC_FLAG_UBLE)) {
9491 case POWERPC_FLAG_SE:
9492 case POWERPC_FLAG_DWE:
9493 case POWERPC_FLAG_UBLE:
9494 break;
9495 default:
9496 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9497 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9498 "POWERPC_FLAG_UBLE\n");
9499 exit(1);
9500 }
9501 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9502 POWERPC_FLAG_UBLE)) {
9503 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9504 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9505 "POWERPC_FLAG_UBLE\n");
9506 exit(1);
9507 }
9508 if (env->msr_mask & (1 << 9)) {
9509 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9510 case POWERPC_FLAG_BE:
9511 case POWERPC_FLAG_DE:
9512 break;
9513 default:
9514 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9515 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9516 exit(1);
9517 }
9518 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9519 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9520 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9521 exit(1);
9522 }
9523 if (env->msr_mask & (1 << 2)) {
9524 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9525 case POWERPC_FLAG_PX:
9526 case POWERPC_FLAG_PMM:
9527 break;
9528 default:
9529 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9530 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9531 exit(1);
9532 }
9533 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9534 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9535 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9536 exit(1);
9537 }
9538 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9539 fprintf(stderr, "PowerPC flags inconsistency\n"
9540 "Should define the time-base and decrementer clock source\n");
9541 exit(1);
9542 }
9543 /* Allocate TLBs buffer when needed */
9544 #if !defined(CONFIG_USER_ONLY)
9545 if (env->nb_tlb != 0) {
9546 int nb_tlb = env->nb_tlb;
9547 if (env->id_tlbs != 0)
9548 nb_tlb *= 2;
9549 switch (env->tlb_type) {
9550 case TLB_6XX:
9551 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
9552 break;
9553 case TLB_EMB:
9554 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
9555 break;
9556 case TLB_MAS:
9557 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
9558 break;
9559 }
9560 /* Pre-compute some useful values */
9561 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9562 }
9563 if (env->irq_inputs == NULL) {
9564 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
9565 " Attempt QEMU to crash very soon !\n");
9566 }
9567 #endif
9568 if (env->check_pow == NULL) {
9569 fprintf(stderr, "WARNING: no power management check handler "
9570 "registered.\n"
9571 " Attempt QEMU to crash very soon !\n");
9572 }
9573 }
9574
9575 #if defined(PPC_DUMP_CPU)
9576 static void dump_ppc_sprs (CPUPPCState *env)
9577 {
9578 ppc_spr_t *spr;
9579 #if !defined(CONFIG_USER_ONLY)
9580 uint32_t sr, sw;
9581 #endif
9582 uint32_t ur, uw;
9583 int i, j, n;
9584
9585 printf("Special purpose registers:\n");
9586 for (i = 0; i < 32; i++) {
9587 for (j = 0; j < 32; j++) {
9588 n = (i << 5) | j;
9589 spr = &env->spr_cb[n];
9590 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9591 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9592 #if !defined(CONFIG_USER_ONLY)
9593 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9594 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9595 if (sw || sr || uw || ur) {
9596 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9597 (i << 5) | j, (i << 5) | j, spr->name,
9598 sw ? 'w' : '-', sr ? 'r' : '-',
9599 uw ? 'w' : '-', ur ? 'r' : '-');
9600 }
9601 #else
9602 if (uw || ur) {
9603 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9604 (i << 5) | j, (i << 5) | j, spr->name,
9605 uw ? 'w' : '-', ur ? 'r' : '-');
9606 }
9607 #endif
9608 }
9609 }
9610 fflush(stdout);
9611 fflush(stderr);
9612 }
9613 #endif
9614
9615 /*****************************************************************************/
9616 #include <stdlib.h>
9617 #include <string.h>
9618
9619 /* Opcode types */
9620 enum {
9621 PPC_DIRECT = 0, /* Opcode routine */
9622 PPC_INDIRECT = 1, /* Indirect opcode table */
9623 };
9624
9625 static inline int is_indirect_opcode (void *handler)
9626 {
9627 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
9628 }
9629
9630 static inline opc_handler_t **ind_table(void *handler)
9631 {
9632 return (opc_handler_t **)((uintptr_t)handler & ~3);
9633 }
9634
9635 /* Instruction table creation */
9636 /* Opcodes tables creation */
9637 static void fill_new_table (opc_handler_t **table, int len)
9638 {
9639 int i;
9640
9641 for (i = 0; i < len; i++)
9642 table[i] = &invalid_handler;
9643 }
9644
9645 static int create_new_table (opc_handler_t **table, unsigned char idx)
9646 {
9647 opc_handler_t **tmp;
9648
9649 tmp = malloc(0x20 * sizeof(opc_handler_t));
9650 fill_new_table(tmp, 0x20);
9651 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
9652
9653 return 0;
9654 }
9655
9656 static int insert_in_table (opc_handler_t **table, unsigned char idx,
9657 opc_handler_t *handler)
9658 {
9659 if (table[idx] != &invalid_handler)
9660 return -1;
9661 table[idx] = handler;
9662
9663 return 0;
9664 }
9665
9666 static int register_direct_insn (opc_handler_t **ppc_opcodes,
9667 unsigned char idx, opc_handler_t *handler)
9668 {
9669 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9670 printf("*** ERROR: opcode %02x already assigned in main "
9671 "opcode table\n", idx);
9672 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9673 printf(" Registered handler '%s' - new handler '%s'\n",
9674 ppc_opcodes[idx]->oname, handler->oname);
9675 #endif
9676 return -1;
9677 }
9678
9679 return 0;
9680 }
9681
9682 static int register_ind_in_table (opc_handler_t **table,
9683 unsigned char idx1, unsigned char idx2,
9684 opc_handler_t *handler)
9685 {
9686 if (table[idx1] == &invalid_handler) {
9687 if (create_new_table(table, idx1) < 0) {
9688 printf("*** ERROR: unable to create indirect table "
9689 "idx=%02x\n", idx1);
9690 return -1;
9691 }
9692 } else {
9693 if (!is_indirect_opcode(table[idx1])) {
9694 printf("*** ERROR: idx %02x already assigned to a direct "
9695 "opcode\n", idx1);
9696 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9697 printf(" Registered handler '%s' - new handler '%s'\n",
9698 ind_table(table[idx1])[idx2]->oname, handler->oname);
9699 #endif
9700 return -1;
9701 }
9702 }
9703 if (handler != NULL &&
9704 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9705 printf("*** ERROR: opcode %02x already assigned in "
9706 "opcode table %02x\n", idx2, idx1);
9707 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9708 printf(" Registered handler '%s' - new handler '%s'\n",
9709 ind_table(table[idx1])[idx2]->oname, handler->oname);
9710 #endif
9711 return -1;
9712 }
9713
9714 return 0;
9715 }
9716
9717 static int register_ind_insn (opc_handler_t **ppc_opcodes,
9718 unsigned char idx1, unsigned char idx2,
9719 opc_handler_t *handler)
9720 {
9721 int ret;
9722
9723 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9724
9725 return ret;
9726 }
9727
9728 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
9729 unsigned char idx1, unsigned char idx2,
9730 unsigned char idx3, opc_handler_t *handler)
9731 {
9732 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9733 printf("*** ERROR: unable to join indirect table idx "
9734 "[%02x-%02x]\n", idx1, idx2);
9735 return -1;
9736 }
9737 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9738 handler) < 0) {
9739 printf("*** ERROR: unable to insert opcode "
9740 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9741 return -1;
9742 }
9743
9744 return 0;
9745 }
9746
9747 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
9748 {
9749 if (insn->opc2 != 0xFF) {
9750 if (insn->opc3 != 0xFF) {
9751 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9752 insn->opc3, &insn->handler) < 0)
9753 return -1;
9754 } else {
9755 if (register_ind_insn(ppc_opcodes, insn->opc1,
9756 insn->opc2, &insn->handler) < 0)
9757 return -1;
9758 }
9759 } else {
9760 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9761 return -1;
9762 }
9763
9764 return 0;
9765 }
9766
9767 static int test_opcode_table (opc_handler_t **table, int len)
9768 {
9769 int i, count, tmp;
9770
9771 for (i = 0, count = 0; i < len; i++) {
9772 /* Consistency fixup */
9773 if (table[i] == NULL)
9774 table[i] = &invalid_handler;
9775 if (table[i] != &invalid_handler) {
9776 if (is_indirect_opcode(table[i])) {
9777 tmp = test_opcode_table(ind_table(table[i]), 0x20);
9778 if (tmp == 0) {
9779 free(table[i]);
9780 table[i] = &invalid_handler;
9781 } else {
9782 count++;
9783 }
9784 } else {
9785 count++;
9786 }
9787 }
9788 }
9789
9790 return count;
9791 }
9792
9793 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
9794 {
9795 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9796 printf("*** WARNING: no opcode defined !\n");
9797 }
9798
9799 /*****************************************************************************/
9800 static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
9801 {
9802 opcode_t *opc;
9803
9804 fill_new_table(env->opcodes, 0x40);
9805 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
9806 if (((opc->handler.type & def->insns_flags) != 0) ||
9807 ((opc->handler.type2 & def->insns_flags2) != 0)) {
9808 if (register_insn(env->opcodes, opc) < 0) {
9809 printf("*** ERROR initializing PowerPC instruction "
9810 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9811 opc->opc3);
9812 return -1;
9813 }
9814 }
9815 }
9816 fix_opcode_tables(env->opcodes);
9817 fflush(stdout);
9818 fflush(stderr);
9819
9820 return 0;
9821 }
9822
9823 #if defined(PPC_DUMP_CPU)
9824 static void dump_ppc_insns (CPUPPCState *env)
9825 {
9826 opc_handler_t **table, *handler;
9827 const char *p, *q;
9828 uint8_t opc1, opc2, opc3;
9829
9830 printf("Instructions set:\n");
9831 /* opc1 is 6 bits long */
9832 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9833 table = env->opcodes;
9834 handler = table[opc1];
9835 if (is_indirect_opcode(handler)) {
9836 /* opc2 is 5 bits long */
9837 for (opc2 = 0; opc2 < 0x20; opc2++) {
9838 table = env->opcodes;
9839 handler = env->opcodes[opc1];
9840 table = ind_table(handler);
9841 handler = table[opc2];
9842 if (is_indirect_opcode(handler)) {
9843 table = ind_table(handler);
9844 /* opc3 is 5 bits long */
9845 for (opc3 = 0; opc3 < 0x20; opc3++) {
9846 handler = table[opc3];
9847 if (handler->handler != &gen_invalid) {
9848 /* Special hack to properly dump SPE insns */
9849 p = strchr(handler->oname, '_');
9850 if (p == NULL) {
9851 printf("INSN: %02x %02x %02x (%02d %04d) : "
9852 "%s\n",
9853 opc1, opc2, opc3, opc1,
9854 (opc3 << 5) | opc2,
9855 handler->oname);
9856 } else {
9857 q = "speundef";
9858 if ((p - handler->oname) != strlen(q) ||
9859 memcmp(handler->oname, q, strlen(q)) != 0) {
9860 /* First instruction */
9861 printf("INSN: %02x %02x %02x (%02d %04d) : "
9862 "%.*s\n",
9863 opc1, opc2 << 1, opc3, opc1,
9864 (opc3 << 6) | (opc2 << 1),
9865 (int)(p - handler->oname),
9866 handler->oname);
9867 }
9868 if (strcmp(p + 1, q) != 0) {
9869 /* Second instruction */
9870 printf("INSN: %02x %02x %02x (%02d %04d) : "
9871 "%s\n",
9872 opc1, (opc2 << 1) | 1, opc3, opc1,
9873 (opc3 << 6) | (opc2 << 1) | 1,
9874 p + 1);
9875 }
9876 }
9877 }
9878 }
9879 } else {
9880 if (handler->handler != &gen_invalid) {
9881 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9882 opc1, opc2, opc1, opc2, handler->oname);
9883 }
9884 }
9885 }
9886 } else {
9887 if (handler->handler != &gen_invalid) {
9888 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9889 opc1, opc1, handler->oname);
9890 }
9891 }
9892 }
9893 }
9894 #endif
9895
9896 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9897 {
9898 if (n < 32) {
9899 stfq_p(mem_buf, env->fpr[n]);
9900 return 8;
9901 }
9902 if (n == 32) {
9903 stl_p(mem_buf, env->fpscr);
9904 return 4;
9905 }
9906 return 0;
9907 }
9908
9909 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9910 {
9911 if (n < 32) {
9912 env->fpr[n] = ldfq_p(mem_buf);
9913 return 8;
9914 }
9915 if (n == 32) {
9916 /* FPSCR not implemented */
9917 return 4;
9918 }
9919 return 0;
9920 }
9921
9922 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9923 {
9924 if (n < 32) {
9925 #ifdef HOST_WORDS_BIGENDIAN
9926 stq_p(mem_buf, env->avr[n].u64[0]);
9927 stq_p(mem_buf+8, env->avr[n].u64[1]);
9928 #else
9929 stq_p(mem_buf, env->avr[n].u64[1]);
9930 stq_p(mem_buf+8, env->avr[n].u64[0]);
9931 #endif
9932 return 16;
9933 }
9934 if (n == 32) {
9935 stl_p(mem_buf, env->vscr);
9936 return 4;
9937 }
9938 if (n == 33) {
9939 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9940 return 4;
9941 }
9942 return 0;
9943 }
9944
9945 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9946 {
9947 if (n < 32) {
9948 #ifdef HOST_WORDS_BIGENDIAN
9949 env->avr[n].u64[0] = ldq_p(mem_buf);
9950 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9951 #else
9952 env->avr[n].u64[1] = ldq_p(mem_buf);
9953 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9954 #endif
9955 return 16;
9956 }
9957 if (n == 32) {
9958 env->vscr = ldl_p(mem_buf);
9959 return 4;
9960 }
9961 if (n == 33) {
9962 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9963 return 4;
9964 }
9965 return 0;
9966 }
9967
9968 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9969 {
9970 if (n < 32) {
9971 #if defined(TARGET_PPC64)
9972 stl_p(mem_buf, env->gpr[n] >> 32);
9973 #else
9974 stl_p(mem_buf, env->gprh[n]);
9975 #endif
9976 return 4;
9977 }
9978 if (n == 32) {
9979 stq_p(mem_buf, env->spe_acc);
9980 return 8;
9981 }
9982 if (n == 33) {
9983 stl_p(mem_buf, env->spe_fscr);
9984 return 4;
9985 }
9986 return 0;
9987 }
9988
9989 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9990 {
9991 if (n < 32) {
9992 #if defined(TARGET_PPC64)
9993 target_ulong lo = (uint32_t)env->gpr[n];
9994 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9995 env->gpr[n] = lo | hi;
9996 #else
9997 env->gprh[n] = ldl_p(mem_buf);
9998 #endif
9999 return 4;
10000 }
10001 if (n == 32) {
10002 env->spe_acc = ldq_p(mem_buf);
10003 return 8;
10004 }
10005 if (n == 33) {
10006 env->spe_fscr = ldl_p(mem_buf);
10007 return 4;
10008 }
10009 return 0;
10010 }
10011
10012 static int ppc_fixup_cpu(CPUPPCState *env)
10013 {
10014 /* TCG doesn't (yet) emulate some groups of instructions that
10015 * are implemented on some otherwise supported CPUs (e.g. VSX
10016 * and decimal floating point instructions on POWER7). We
10017 * remove unsupported instruction groups from the cpu state's
10018 * instruction masks and hope the guest can cope. For at
10019 * least the pseries machine, the unavailability of these
10020 * instructions can be advertised to the guest via the device
10021 * tree. */
10022 if ((env->insns_flags & ~PPC_TCG_INSNS)
10023 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
10024 fprintf(stderr, "Warning: Disabling some instructions which are not "
10025 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
10026 env->insns_flags & ~PPC_TCG_INSNS,
10027 env->insns_flags2 & ~PPC_TCG_INSNS2);
10028 }
10029 env->insns_flags &= PPC_TCG_INSNS;
10030 env->insns_flags2 &= PPC_TCG_INSNS2;
10031 return 0;
10032 }
10033
10034 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
10035 {
10036 env->msr_mask = def->msr_mask;
10037 env->mmu_model = def->mmu_model;
10038 env->excp_model = def->excp_model;
10039 env->bus_model = def->bus_model;
10040 env->insns_flags = def->insns_flags;
10041 env->insns_flags2 = def->insns_flags2;
10042 env->flags = def->flags;
10043 env->bfd_mach = def->bfd_mach;
10044 env->check_pow = def->check_pow;
10045
10046 #if defined(TARGET_PPC64)
10047 if (def->sps)
10048 env->sps = *def->sps;
10049 else if (env->mmu_model & POWERPC_MMU_64) {
10050 /* Use default sets of page sizes */
10051 static const struct ppc_segment_page_sizes defsps = {
10052 .sps = {
10053 { .page_shift = 12, /* 4K */
10054 .slb_enc = 0,
10055 .enc = { { .page_shift = 12, .pte_enc = 0 } }
10056 },
10057 { .page_shift = 24, /* 16M */
10058 .slb_enc = 0x100,
10059 .enc = { { .page_shift = 24, .pte_enc = 0 } }
10060 },
10061 },
10062 };
10063 env->sps = defsps;
10064 }
10065 #endif /* defined(TARGET_PPC64) */
10066
10067 if (kvm_enabled()) {
10068 if (kvmppc_fixup_cpu(env) != 0) {
10069 fprintf(stderr, "Unable to virtualize selected CPU with KVM\n");
10070 exit(1);
10071 }
10072 } else {
10073 if (ppc_fixup_cpu(env) != 0) {
10074 fprintf(stderr, "Unable to emulate selected CPU with TCG\n");
10075 exit(1);
10076 }
10077 }
10078
10079 if (create_ppc_opcodes(env, def) < 0)
10080 return -1;
10081 init_ppc_proc(env, def);
10082
10083 if (def->insns_flags & PPC_FLOAT) {
10084 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
10085 33, "power-fpu.xml", 0);
10086 }
10087 if (def->insns_flags & PPC_ALTIVEC) {
10088 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
10089 34, "power-altivec.xml", 0);
10090 }
10091 if (def->insns_flags & PPC_SPE) {
10092 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
10093 34, "power-spe.xml", 0);
10094 }
10095
10096 #if defined(PPC_DUMP_CPU)
10097 {
10098 const char *mmu_model, *excp_model, *bus_model;
10099 switch (env->mmu_model) {
10100 case POWERPC_MMU_32B:
10101 mmu_model = "PowerPC 32";
10102 break;
10103 case POWERPC_MMU_SOFT_6xx:
10104 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
10105 break;
10106 case POWERPC_MMU_SOFT_74xx:
10107 mmu_model = "PowerPC 74xx with software driven TLBs";
10108 break;
10109 case POWERPC_MMU_SOFT_4xx:
10110 mmu_model = "PowerPC 4xx with software driven TLBs";
10111 break;
10112 case POWERPC_MMU_SOFT_4xx_Z:
10113 mmu_model = "PowerPC 4xx with software driven TLBs "
10114 "and zones protections";
10115 break;
10116 case POWERPC_MMU_REAL:
10117 mmu_model = "PowerPC real mode only";
10118 break;
10119 case POWERPC_MMU_MPC8xx:
10120 mmu_model = "PowerPC MPC8xx";
10121 break;
10122 case POWERPC_MMU_BOOKE:
10123 mmu_model = "PowerPC BookE";
10124 break;
10125 case POWERPC_MMU_BOOKE206:
10126 mmu_model = "PowerPC BookE 2.06";
10127 break;
10128 case POWERPC_MMU_601:
10129 mmu_model = "PowerPC 601";
10130 break;
10131 #if defined (TARGET_PPC64)
10132 case POWERPC_MMU_64B:
10133 mmu_model = "PowerPC 64";
10134 break;
10135 case POWERPC_MMU_620:
10136 mmu_model = "PowerPC 620";
10137 break;
10138 #endif
10139 default:
10140 mmu_model = "Unknown or invalid";
10141 break;
10142 }
10143 switch (env->excp_model) {
10144 case POWERPC_EXCP_STD:
10145 excp_model = "PowerPC";
10146 break;
10147 case POWERPC_EXCP_40x:
10148 excp_model = "PowerPC 40x";
10149 break;
10150 case POWERPC_EXCP_601:
10151 excp_model = "PowerPC 601";
10152 break;
10153 case POWERPC_EXCP_602:
10154 excp_model = "PowerPC 602";
10155 break;
10156 case POWERPC_EXCP_603:
10157 excp_model = "PowerPC 603";
10158 break;
10159 case POWERPC_EXCP_603E:
10160 excp_model = "PowerPC 603e";
10161 break;
10162 case POWERPC_EXCP_604:
10163 excp_model = "PowerPC 604";
10164 break;
10165 case POWERPC_EXCP_7x0:
10166 excp_model = "PowerPC 740/750";
10167 break;
10168 case POWERPC_EXCP_7x5:
10169 excp_model = "PowerPC 745/755";
10170 break;
10171 case POWERPC_EXCP_74xx:
10172 excp_model = "PowerPC 74xx";
10173 break;
10174 case POWERPC_EXCP_BOOKE:
10175 excp_model = "PowerPC BookE";
10176 break;
10177 #if defined (TARGET_PPC64)
10178 case POWERPC_EXCP_970:
10179 excp_model = "PowerPC 970";
10180 break;
10181 #endif
10182 default:
10183 excp_model = "Unknown or invalid";
10184 break;
10185 }
10186 switch (env->bus_model) {
10187 case PPC_FLAGS_INPUT_6xx:
10188 bus_model = "PowerPC 6xx";
10189 break;
10190 case PPC_FLAGS_INPUT_BookE:
10191 bus_model = "PowerPC BookE";
10192 break;
10193 case PPC_FLAGS_INPUT_405:
10194 bus_model = "PowerPC 405";
10195 break;
10196 case PPC_FLAGS_INPUT_401:
10197 bus_model = "PowerPC 401/403";
10198 break;
10199 case PPC_FLAGS_INPUT_RCPU:
10200 bus_model = "RCPU / MPC8xx";
10201 break;
10202 #if defined (TARGET_PPC64)
10203 case PPC_FLAGS_INPUT_970:
10204 bus_model = "PowerPC 970";
10205 break;
10206 #endif
10207 default:
10208 bus_model = "Unknown or invalid";
10209 break;
10210 }
10211 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
10212 " MMU model : %s\n",
10213 def->name, def->pvr, def->msr_mask, mmu_model);
10214 #if !defined(CONFIG_USER_ONLY)
10215 if (env->tlb != NULL) {
10216 printf(" %d %s TLB in %d ways\n",
10217 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
10218 env->nb_ways);
10219 }
10220 #endif
10221 printf(" Exceptions model : %s\n"
10222 " Bus model : %s\n",
10223 excp_model, bus_model);
10224 printf(" MSR features :\n");
10225 if (env->flags & POWERPC_FLAG_SPE)
10226 printf(" signal processing engine enable"
10227 "\n");
10228 else if (env->flags & POWERPC_FLAG_VRE)
10229 printf(" vector processor enable\n");
10230 if (env->flags & POWERPC_FLAG_TGPR)
10231 printf(" temporary GPRs\n");
10232 else if (env->flags & POWERPC_FLAG_CE)
10233 printf(" critical input enable\n");
10234 if (env->flags & POWERPC_FLAG_SE)
10235 printf(" single-step trace mode\n");
10236 else if (env->flags & POWERPC_FLAG_DWE)
10237 printf(" debug wait enable\n");
10238 else if (env->flags & POWERPC_FLAG_UBLE)
10239 printf(" user BTB lock enable\n");
10240 if (env->flags & POWERPC_FLAG_BE)
10241 printf(" branch-step trace mode\n");
10242 else if (env->flags & POWERPC_FLAG_DE)
10243 printf(" debug interrupt enable\n");
10244 if (env->flags & POWERPC_FLAG_PX)
10245 printf(" inclusive protection\n");
10246 else if (env->flags & POWERPC_FLAG_PMM)
10247 printf(" performance monitor mark\n");
10248 if (env->flags == POWERPC_FLAG_NONE)
10249 printf(" none\n");
10250 printf(" Time-base/decrementer clock source: %s\n",
10251 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
10252 }
10253 dump_ppc_insns(env);
10254 dump_ppc_sprs(env);
10255 fflush(stdout);
10256 #endif
10257
10258 return 0;
10259 }
10260
10261 static bool ppc_cpu_usable(const ppc_def_t *def)
10262 {
10263 #if defined(TARGET_PPCEMB)
10264 /* When using the ppcemb target, we only support 440 style cores */
10265 if (def->mmu_model != POWERPC_MMU_BOOKE) {
10266 return false;
10267 }
10268 #endif
10269
10270 return true;
10271 }
10272
10273 const ppc_def_t *ppc_find_by_pvr(uint32_t pvr)
10274 {
10275 int i;
10276
10277 for (i = 0; i < ARRAY_SIZE(ppc_defs); i++) {
10278 if (!ppc_cpu_usable(&ppc_defs[i])) {
10279 continue;
10280 }
10281
10282 /* If we have an exact match, we're done */
10283 if (pvr == ppc_defs[i].pvr) {
10284 return &ppc_defs[i];
10285 }
10286 }
10287
10288 return NULL;
10289 }
10290
10291 #include <ctype.h>
10292
10293 const ppc_def_t *cpu_ppc_find_by_name (const char *name)
10294 {
10295 const ppc_def_t *ret;
10296 const char *p;
10297 int i, max, len;
10298
10299 if (kvm_enabled() && (strcasecmp(name, "host") == 0)) {
10300 return kvmppc_host_cpu_def();
10301 }
10302
10303 /* Check if the given name is a PVR */
10304 len = strlen(name);
10305 if (len == 10 && name[0] == '0' && name[1] == 'x') {
10306 p = name + 2;
10307 goto check_pvr;
10308 } else if (len == 8) {
10309 p = name;
10310 check_pvr:
10311 for (i = 0; i < 8; i++) {
10312 if (!qemu_isxdigit(*p++))
10313 break;
10314 }
10315 if (i == 8)
10316 return ppc_find_by_pvr(strtoul(name, NULL, 16));
10317 }
10318 ret = NULL;
10319 max = ARRAY_SIZE(ppc_defs);
10320 for (i = 0; i < max; i++) {
10321 if (!ppc_cpu_usable(&ppc_defs[i])) {
10322 continue;
10323 }
10324
10325 if (strcasecmp(name, ppc_defs[i].name) == 0) {
10326 ret = &ppc_defs[i];
10327 break;
10328 }
10329 }
10330
10331 return ret;
10332 }
10333
10334 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
10335 {
10336 int i, max;
10337
10338 max = ARRAY_SIZE(ppc_defs);
10339 for (i = 0; i < max; i++) {
10340 if (!ppc_cpu_usable(&ppc_defs[i])) {
10341 continue;
10342 }
10343
10344 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
10345 ppc_defs[i].name, ppc_defs[i].pvr);
10346 }
10347 }
10348
10349 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
10350 {
10351 CpuDefinitionInfoList *cpu_list = NULL;
10352 int i;
10353
10354 for (i = 0; i < ARRAY_SIZE(ppc_defs); i++) {
10355 CpuDefinitionInfoList *entry;
10356 CpuDefinitionInfo *info;
10357
10358 if (!ppc_cpu_usable(&ppc_defs[i])) {
10359 continue;
10360 }
10361
10362 info = g_malloc0(sizeof(*info));
10363 info->name = g_strdup(ppc_defs[i].name);
10364
10365 entry = g_malloc0(sizeof(*entry));
10366 entry->value = info;
10367 entry->next = cpu_list;
10368 cpu_list = entry;
10369 }
10370
10371 return cpu_list;
10372 }
10373
10374 /* CPUClass::reset() */
10375 static void ppc_cpu_reset(CPUState *s)
10376 {
10377 PowerPCCPU *cpu = POWERPC_CPU(s);
10378 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10379 CPUPPCState *env = &cpu->env;
10380 target_ulong msr;
10381
10382 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
10383 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
10384 log_cpu_state(env, 0);
10385 }
10386
10387 pcc->parent_reset(s);
10388
10389 msr = (target_ulong)0;
10390 if (0) {
10391 /* XXX: find a suitable condition to enable the hypervisor mode */
10392 msr |= (target_ulong)MSR_HVB;
10393 }
10394 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
10395 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
10396 msr |= (target_ulong)1 << MSR_EP;
10397 #if defined(DO_SINGLE_STEP) && 0
10398 /* Single step trace mode */
10399 msr |= (target_ulong)1 << MSR_SE;
10400 msr |= (target_ulong)1 << MSR_BE;
10401 #endif
10402 #if defined(CONFIG_USER_ONLY)
10403 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
10404 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
10405 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
10406 msr |= (target_ulong)1 << MSR_PR;
10407 #else
10408 env->excp_prefix = env->hreset_excp_prefix;
10409 env->nip = env->hreset_vector | env->excp_prefix;
10410 if (env->mmu_model != POWERPC_MMU_REAL) {
10411 ppc_tlb_invalidate_all(env);
10412 }
10413 #endif
10414 env->msr = msr & env->msr_mask;
10415 #if defined(TARGET_PPC64)
10416 if (env->mmu_model & POWERPC_MMU_64) {
10417 env->msr |= (1ULL << MSR_SF);
10418 }
10419 #endif
10420 hreg_compute_hflags(env);
10421 env->reserve_addr = (target_ulong)-1ULL;
10422 /* Be sure no exception or interrupt is pending */
10423 env->pending_interrupts = 0;
10424 env->exception_index = POWERPC_EXCP_NONE;
10425 env->error_code = 0;
10426
10427 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
10428 env->vpa = 0;
10429 env->slb_shadow = 0;
10430 env->dispatch_trace_log = 0;
10431 env->dtl_size = 0;
10432 #endif /* TARGET_PPC64 */
10433
10434 /* Flush all TLBs */
10435 tlb_flush(env, 1);
10436 }
10437
10438 static void ppc_cpu_initfn(Object *obj)
10439 {
10440 PowerPCCPU *cpu = POWERPC_CPU(obj);
10441 CPUPPCState *env = &cpu->env;
10442
10443 cpu_exec_init(env);
10444 }
10445
10446 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
10447 {
10448 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10449 CPUClass *cc = CPU_CLASS(oc);
10450
10451 pcc->parent_reset = cc->reset;
10452 cc->reset = ppc_cpu_reset;
10453 }
10454
10455 static const TypeInfo ppc_cpu_type_info = {
10456 .name = TYPE_POWERPC_CPU,
10457 .parent = TYPE_CPU,
10458 .instance_size = sizeof(PowerPCCPU),
10459 .instance_init = ppc_cpu_initfn,
10460 .abstract = false,
10461 .class_size = sizeof(PowerPCCPUClass),
10462 .class_init = ppc_cpu_class_init,
10463 };
10464
10465 static void ppc_cpu_register_types(void)
10466 {
10467 type_register_static(&ppc_cpu_type_info);
10468 }
10469
10470 type_init(ppc_cpu_register_types)
Qemu copy for testing