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1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
26 //#define PPC_DUMP_CPU
27 //#define PPC_DEBUG_SPR
28 //#define PPC_DEBUG_IRQ
29
30 struct ppc_def_t {
31 const unsigned char *name;
32 uint32_t pvr;
33 uint32_t pvr_mask;
34 uint64_t insns_flags;
35 uint64_t msr_mask;
36 uint8_t mmu_model;
37 uint8_t excp_model;
38 uint8_t bus_model;
39 uint8_t pad;
40 void (*init_proc)(CPUPPCState *env);
41 };
42
43 /* For user-mode emulation, we don't emulate any IRQ controller */
44 #if defined(CONFIG_USER_ONLY)
45 #define PPC_IRQ_INIT_FN(name) \
46 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
47 { \
48 }
49 #else
50 #define PPC_IRQ_INIT_FN(name) \
51 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
52 #endif
53
54 PPC_IRQ_INIT_FN(401);
55 PPC_IRQ_INIT_FN(405);
56 PPC_IRQ_INIT_FN(6xx);
57 PPC_IRQ_INIT_FN(970);
58
59 /* Generic callbacks:
60 * do nothing but store/retrieve spr value
61 */
62 #ifdef PPC_DUMP_SPR_ACCESSES
63 static void spr_read_generic (void *opaque, int sprn)
64 {
65 gen_op_load_dump_spr(sprn);
66 }
67
68 static void spr_write_generic (void *opaque, int sprn)
69 {
70 gen_op_store_dump_spr(sprn);
71 }
72 #else
73 static void spr_read_generic (void *opaque, int sprn)
74 {
75 gen_op_load_spr(sprn);
76 }
77
78 static void spr_write_generic (void *opaque, int sprn)
79 {
80 gen_op_store_spr(sprn);
81 }
82 #endif
83
84 #if !defined(CONFIG_USER_ONLY)
85 static void spr_write_clear (void *opaque, int sprn)
86 {
87 gen_op_mask_spr(sprn);
88 }
89 #endif
90
91 /* SPR common to all PowerPC */
92 /* XER */
93 static void spr_read_xer (void *opaque, int sprn)
94 {
95 gen_op_load_xer();
96 }
97
98 static void spr_write_xer (void *opaque, int sprn)
99 {
100 gen_op_store_xer();
101 }
102
103 /* LR */
104 static void spr_read_lr (void *opaque, int sprn)
105 {
106 gen_op_load_lr();
107 }
108
109 static void spr_write_lr (void *opaque, int sprn)
110 {
111 gen_op_store_lr();
112 }
113
114 /* CTR */
115 static void spr_read_ctr (void *opaque, int sprn)
116 {
117 gen_op_load_ctr();
118 }
119
120 static void spr_write_ctr (void *opaque, int sprn)
121 {
122 gen_op_store_ctr();
123 }
124
125 /* User read access to SPR */
126 /* USPRx */
127 /* UMMCRx */
128 /* UPMCx */
129 /* USIA */
130 /* UDECR */
131 static void spr_read_ureg (void *opaque, int sprn)
132 {
133 gen_op_load_spr(sprn + 0x10);
134 }
135
136 /* SPR common to all non-embedded PowerPC */
137 /* DECR */
138 #if !defined(CONFIG_USER_ONLY)
139 static void spr_read_decr (void *opaque, int sprn)
140 {
141 gen_op_load_decr();
142 }
143
144 static void spr_write_decr (void *opaque, int sprn)
145 {
146 gen_op_store_decr();
147 }
148 #endif
149
150 /* SPR common to all non-embedded PowerPC, except 601 */
151 /* Time base */
152 static void spr_read_tbl (void *opaque, int sprn)
153 {
154 gen_op_load_tbl();
155 }
156
157 static void spr_read_tbu (void *opaque, int sprn)
158 {
159 gen_op_load_tbu();
160 }
161
162 #if !defined(CONFIG_USER_ONLY)
163 static void spr_write_tbl (void *opaque, int sprn)
164 {
165 gen_op_store_tbl();
166 }
167
168 static void spr_write_tbu (void *opaque, int sprn)
169 {
170 gen_op_store_tbu();
171 }
172 #endif
173
174 #if !defined(CONFIG_USER_ONLY)
175 /* IBAT0U...IBAT0U */
176 /* IBAT0L...IBAT7L */
177 static void spr_read_ibat (void *opaque, int sprn)
178 {
179 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
180 }
181
182 static void spr_read_ibat_h (void *opaque, int sprn)
183 {
184 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
185 }
186
187 static void spr_write_ibatu (void *opaque, int sprn)
188 {
189 DisasContext *ctx = opaque;
190
191 gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
192 RET_STOP(ctx);
193 }
194
195 static void spr_write_ibatu_h (void *opaque, int sprn)
196 {
197 DisasContext *ctx = opaque;
198
199 gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
200 RET_STOP(ctx);
201 }
202
203 static void spr_write_ibatl (void *opaque, int sprn)
204 {
205 DisasContext *ctx = opaque;
206
207 gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
208 RET_STOP(ctx);
209 }
210
211 static void spr_write_ibatl_h (void *opaque, int sprn)
212 {
213 DisasContext *ctx = opaque;
214
215 gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
216 RET_STOP(ctx);
217 }
218
219 /* DBAT0U...DBAT7U */
220 /* DBAT0L...DBAT7L */
221 static void spr_read_dbat (void *opaque, int sprn)
222 {
223 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
224 }
225
226 static void spr_read_dbat_h (void *opaque, int sprn)
227 {
228 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
229 }
230
231 static void spr_write_dbatu (void *opaque, int sprn)
232 {
233 DisasContext *ctx = opaque;
234
235 gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
236 RET_STOP(ctx);
237 }
238
239 static void spr_write_dbatu_h (void *opaque, int sprn)
240 {
241 DisasContext *ctx = opaque;
242
243 gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
244 RET_STOP(ctx);
245 }
246
247 static void spr_write_dbatl (void *opaque, int sprn)
248 {
249 DisasContext *ctx = opaque;
250
251 gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
252 RET_STOP(ctx);
253 }
254
255 static void spr_write_dbatl_h (void *opaque, int sprn)
256 {
257 DisasContext *ctx = opaque;
258
259 gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
260 RET_STOP(ctx);
261 }
262
263 /* SDR1 */
264 static void spr_read_sdr1 (void *opaque, int sprn)
265 {
266 gen_op_load_sdr1();
267 }
268
269 static void spr_write_sdr1 (void *opaque, int sprn)
270 {
271 DisasContext *ctx = opaque;
272
273 gen_op_store_sdr1();
274 RET_STOP(ctx);
275 }
276
277 /* 64 bits PowerPC specific SPRs */
278 /* ASR */
279 /* Currently unused */
280 #if 0 && defined(TARGET_PPC64)
281 static void spr_read_asr (void *opaque, int sprn)
282 {
283 gen_op_load_asr();
284 }
285
286 static void spr_write_asr (void *opaque, int sprn)
287 {
288 DisasContext *ctx = opaque;
289
290 gen_op_store_asr();
291 RET_STOP(ctx);
292 }
293 #endif
294 #endif
295
296 /* PowerPC 601 specific registers */
297 /* RTC */
298 static void spr_read_601_rtcl (void *opaque, int sprn)
299 {
300 gen_op_load_601_rtcl();
301 }
302
303 static void spr_read_601_rtcu (void *opaque, int sprn)
304 {
305 gen_op_load_601_rtcu();
306 }
307
308 #if !defined(CONFIG_USER_ONLY)
309 static void spr_write_601_rtcu (void *opaque, int sprn)
310 {
311 gen_op_store_601_rtcu();
312 }
313
314 static void spr_write_601_rtcl (void *opaque, int sprn)
315 {
316 gen_op_store_601_rtcl();
317 }
318 #endif
319
320 /* Unified bats */
321 #if !defined(CONFIG_USER_ONLY)
322 static void spr_read_601_ubat (void *opaque, int sprn)
323 {
324 gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
325 }
326
327 static void spr_write_601_ubatu (void *opaque, int sprn)
328 {
329 DisasContext *ctx = opaque;
330
331 gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
332 RET_STOP(ctx);
333 }
334
335 static void spr_write_601_ubatl (void *opaque, int sprn)
336 {
337 DisasContext *ctx = opaque;
338
339 gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
340 RET_STOP(ctx);
341 }
342 #endif
343
344 /* PowerPC 40x specific registers */
345 #if !defined(CONFIG_USER_ONLY)
346 static void spr_read_40x_pit (void *opaque, int sprn)
347 {
348 gen_op_load_40x_pit();
349 }
350
351 static void spr_write_40x_pit (void *opaque, int sprn)
352 {
353 gen_op_store_40x_pit();
354 }
355
356 static void spr_write_40x_dbcr0 (void *opaque, int sprn)
357 {
358 DisasContext *ctx = opaque;
359
360 gen_op_store_40x_dbcr0();
361 /* We must stop translation as we may have rebooted */
362 RET_STOP(ctx);
363 }
364
365 static void spr_write_40x_sler (void *opaque, int sprn)
366 {
367 DisasContext *ctx = opaque;
368
369 gen_op_store_40x_sler();
370 /* We must stop the translation as we may have changed
371 * some regions endianness
372 */
373 RET_STOP(ctx);
374 }
375
376 static void spr_write_booke_tcr (void *opaque, int sprn)
377 {
378 gen_op_store_booke_tcr();
379 }
380
381 static void spr_write_booke_tsr (void *opaque, int sprn)
382 {
383 gen_op_store_booke_tsr();
384 }
385 #endif
386
387 /* PowerPC 403 specific registers */
388 /* PBL1 / PBU1 / PBL2 / PBU2 */
389 #if !defined(CONFIG_USER_ONLY)
390 static void spr_read_403_pbr (void *opaque, int sprn)
391 {
392 gen_op_load_403_pb(sprn - SPR_403_PBL1);
393 }
394
395 static void spr_write_403_pbr (void *opaque, int sprn)
396 {
397 DisasContext *ctx = opaque;
398
399 gen_op_store_403_pb(sprn - SPR_403_PBL1);
400 RET_STOP(ctx);
401 }
402
403 static void spr_write_pir (void *opaque, int sprn)
404 {
405 gen_op_store_pir();
406 }
407 #endif
408
409 #if defined(CONFIG_USER_ONLY)
410 #define spr_register(env, num, name, uea_read, uea_write, \
411 oea_read, oea_write, initial_value) \
412 do { \
413 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
414 } while (0)
415 static inline void _spr_register (CPUPPCState *env, int num,
416 const unsigned char *name,
417 void (*uea_read)(void *opaque, int sprn),
418 void (*uea_write)(void *opaque, int sprn),
419 target_ulong initial_value)
420 #else
421 static inline void spr_register (CPUPPCState *env, int num,
422 const unsigned char *name,
423 void (*uea_read)(void *opaque, int sprn),
424 void (*uea_write)(void *opaque, int sprn),
425 void (*oea_read)(void *opaque, int sprn),
426 void (*oea_write)(void *opaque, int sprn),
427 target_ulong initial_value)
428 #endif
429 {
430 ppc_spr_t *spr;
431
432 spr = &env->spr_cb[num];
433 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
434 #if !defined(CONFIG_USER_ONLY)
435 spr->oea_read != NULL || spr->oea_write != NULL ||
436 #endif
437 spr->uea_read != NULL || spr->uea_write != NULL) {
438 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
439 exit(1);
440 }
441 #if defined(PPC_DEBUG_SPR)
442 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
443 initial_value);
444 #endif
445 spr->name = name;
446 spr->uea_read = uea_read;
447 spr->uea_write = uea_write;
448 #if !defined(CONFIG_USER_ONLY)
449 spr->oea_read = oea_read;
450 spr->oea_write = oea_write;
451 #endif
452 env->spr[num] = initial_value;
453 }
454
455 /* Generic PowerPC SPRs */
456 static void gen_spr_generic (CPUPPCState *env)
457 {
458 /* Integer processing */
459 spr_register(env, SPR_XER, "XER",
460 &spr_read_xer, &spr_write_xer,
461 &spr_read_xer, &spr_write_xer,
462 0x00000000);
463 /* Branch contol */
464 spr_register(env, SPR_LR, "LR",
465 &spr_read_lr, &spr_write_lr,
466 &spr_read_lr, &spr_write_lr,
467 0x00000000);
468 spr_register(env, SPR_CTR, "CTR",
469 &spr_read_ctr, &spr_write_ctr,
470 &spr_read_ctr, &spr_write_ctr,
471 0x00000000);
472 /* Interrupt processing */
473 spr_register(env, SPR_SRR0, "SRR0",
474 SPR_NOACCESS, SPR_NOACCESS,
475 &spr_read_generic, &spr_write_generic,
476 0x00000000);
477 spr_register(env, SPR_SRR1, "SRR1",
478 SPR_NOACCESS, SPR_NOACCESS,
479 &spr_read_generic, &spr_write_generic,
480 0x00000000);
481 /* Processor control */
482 spr_register(env, SPR_SPRG0, "SPRG0",
483 SPR_NOACCESS, SPR_NOACCESS,
484 &spr_read_generic, &spr_write_generic,
485 0x00000000);
486 spr_register(env, SPR_SPRG1, "SPRG1",
487 SPR_NOACCESS, SPR_NOACCESS,
488 &spr_read_generic, &spr_write_generic,
489 0x00000000);
490 spr_register(env, SPR_SPRG2, "SPRG2",
491 SPR_NOACCESS, SPR_NOACCESS,
492 &spr_read_generic, &spr_write_generic,
493 0x00000000);
494 spr_register(env, SPR_SPRG3, "SPRG3",
495 SPR_NOACCESS, SPR_NOACCESS,
496 &spr_read_generic, &spr_write_generic,
497 0x00000000);
498 }
499
500 /* SPR common to all non-embedded PowerPC, including 601 */
501 static void gen_spr_ne_601 (CPUPPCState *env)
502 {
503 /* Exception processing */
504 spr_register(env, SPR_DSISR, "DSISR",
505 SPR_NOACCESS, SPR_NOACCESS,
506 &spr_read_generic, &spr_write_generic,
507 0x00000000);
508 spr_register(env, SPR_DAR, "DAR",
509 SPR_NOACCESS, SPR_NOACCESS,
510 &spr_read_generic, &spr_write_generic,
511 0x00000000);
512 /* Timer */
513 spr_register(env, SPR_DECR, "DECR",
514 SPR_NOACCESS, SPR_NOACCESS,
515 &spr_read_decr, &spr_write_decr,
516 0x00000000);
517 /* Memory management */
518 spr_register(env, SPR_SDR1, "SDR1",
519 SPR_NOACCESS, SPR_NOACCESS,
520 &spr_read_sdr1, &spr_write_sdr1,
521 0x00000000);
522 }
523
524 /* BATs 0-3 */
525 static void gen_low_BATs (CPUPPCState *env)
526 {
527 spr_register(env, SPR_IBAT0U, "IBAT0U",
528 SPR_NOACCESS, SPR_NOACCESS,
529 &spr_read_ibat, &spr_write_ibatu,
530 0x00000000);
531 spr_register(env, SPR_IBAT0L, "IBAT0L",
532 SPR_NOACCESS, SPR_NOACCESS,
533 &spr_read_ibat, &spr_write_ibatl,
534 0x00000000);
535 spr_register(env, SPR_IBAT1U, "IBAT1U",
536 SPR_NOACCESS, SPR_NOACCESS,
537 &spr_read_ibat, &spr_write_ibatu,
538 0x00000000);
539 spr_register(env, SPR_IBAT1L, "IBAT1L",
540 SPR_NOACCESS, SPR_NOACCESS,
541 &spr_read_ibat, &spr_write_ibatl,
542 0x00000000);
543 spr_register(env, SPR_IBAT2U, "IBAT2U",
544 SPR_NOACCESS, SPR_NOACCESS,
545 &spr_read_ibat, &spr_write_ibatu,
546 0x00000000);
547 spr_register(env, SPR_IBAT2L, "IBAT2L",
548 SPR_NOACCESS, SPR_NOACCESS,
549 &spr_read_ibat, &spr_write_ibatl,
550 0x00000000);
551 spr_register(env, SPR_IBAT3U, "IBAT3U",
552 SPR_NOACCESS, SPR_NOACCESS,
553 &spr_read_ibat, &spr_write_ibatu,
554 0x00000000);
555 spr_register(env, SPR_IBAT3L, "IBAT3L",
556 SPR_NOACCESS, SPR_NOACCESS,
557 &spr_read_ibat, &spr_write_ibatl,
558 0x00000000);
559 spr_register(env, SPR_DBAT0U, "DBAT0U",
560 SPR_NOACCESS, SPR_NOACCESS,
561 &spr_read_dbat, &spr_write_dbatu,
562 0x00000000);
563 spr_register(env, SPR_DBAT0L, "DBAT0L",
564 SPR_NOACCESS, SPR_NOACCESS,
565 &spr_read_dbat, &spr_write_dbatl,
566 0x00000000);
567 spr_register(env, SPR_DBAT1U, "DBAT1U",
568 SPR_NOACCESS, SPR_NOACCESS,
569 &spr_read_dbat, &spr_write_dbatu,
570 0x00000000);
571 spr_register(env, SPR_DBAT1L, "DBAT1L",
572 SPR_NOACCESS, SPR_NOACCESS,
573 &spr_read_dbat, &spr_write_dbatl,
574 0x00000000);
575 spr_register(env, SPR_DBAT2U, "DBAT2U",
576 SPR_NOACCESS, SPR_NOACCESS,
577 &spr_read_dbat, &spr_write_dbatu,
578 0x00000000);
579 spr_register(env, SPR_DBAT2L, "DBAT2L",
580 SPR_NOACCESS, SPR_NOACCESS,
581 &spr_read_dbat, &spr_write_dbatl,
582 0x00000000);
583 spr_register(env, SPR_DBAT3U, "DBAT3U",
584 SPR_NOACCESS, SPR_NOACCESS,
585 &spr_read_dbat, &spr_write_dbatu,
586 0x00000000);
587 spr_register(env, SPR_DBAT3L, "DBAT3L",
588 SPR_NOACCESS, SPR_NOACCESS,
589 &spr_read_dbat, &spr_write_dbatl,
590 0x00000000);
591 env->nb_BATs += 4;
592 }
593
594 /* BATs 4-7 */
595 static void gen_high_BATs (CPUPPCState *env)
596 {
597 spr_register(env, SPR_IBAT4U, "IBAT4U",
598 SPR_NOACCESS, SPR_NOACCESS,
599 &spr_read_ibat_h, &spr_write_ibatu_h,
600 0x00000000);
601 spr_register(env, SPR_IBAT4L, "IBAT4L",
602 SPR_NOACCESS, SPR_NOACCESS,
603 &spr_read_ibat_h, &spr_write_ibatl_h,
604 0x00000000);
605 spr_register(env, SPR_IBAT5U, "IBAT5U",
606 SPR_NOACCESS, SPR_NOACCESS,
607 &spr_read_ibat_h, &spr_write_ibatu_h,
608 0x00000000);
609 spr_register(env, SPR_IBAT5L, "IBAT5L",
610 SPR_NOACCESS, SPR_NOACCESS,
611 &spr_read_ibat_h, &spr_write_ibatl_h,
612 0x00000000);
613 spr_register(env, SPR_IBAT6U, "IBAT6U",
614 SPR_NOACCESS, SPR_NOACCESS,
615 &spr_read_ibat_h, &spr_write_ibatu_h,
616 0x00000000);
617 spr_register(env, SPR_IBAT6L, "IBAT6L",
618 SPR_NOACCESS, SPR_NOACCESS,
619 &spr_read_ibat_h, &spr_write_ibatl_h,
620 0x00000000);
621 spr_register(env, SPR_IBAT7U, "IBAT7U",
622 SPR_NOACCESS, SPR_NOACCESS,
623 &spr_read_ibat_h, &spr_write_ibatu_h,
624 0x00000000);
625 spr_register(env, SPR_IBAT7L, "IBAT7L",
626 SPR_NOACCESS, SPR_NOACCESS,
627 &spr_read_ibat_h, &spr_write_ibatl_h,
628 0x00000000);
629 spr_register(env, SPR_DBAT4U, "DBAT4U",
630 SPR_NOACCESS, SPR_NOACCESS,
631 &spr_read_dbat_h, &spr_write_dbatu_h,
632 0x00000000);
633 spr_register(env, SPR_DBAT4L, "DBAT4L",
634 SPR_NOACCESS, SPR_NOACCESS,
635 &spr_read_dbat_h, &spr_write_dbatl_h,
636 0x00000000);
637 spr_register(env, SPR_DBAT5U, "DBAT5U",
638 SPR_NOACCESS, SPR_NOACCESS,
639 &spr_read_dbat_h, &spr_write_dbatu_h,
640 0x00000000);
641 spr_register(env, SPR_DBAT5L, "DBAT5L",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_dbat_h, &spr_write_dbatl_h,
644 0x00000000);
645 spr_register(env, SPR_DBAT6U, "DBAT6U",
646 SPR_NOACCESS, SPR_NOACCESS,
647 &spr_read_dbat_h, &spr_write_dbatu_h,
648 0x00000000);
649 spr_register(env, SPR_DBAT6L, "DBAT6L",
650 SPR_NOACCESS, SPR_NOACCESS,
651 &spr_read_dbat_h, &spr_write_dbatl_h,
652 0x00000000);
653 spr_register(env, SPR_DBAT7U, "DBAT7U",
654 SPR_NOACCESS, SPR_NOACCESS,
655 &spr_read_dbat_h, &spr_write_dbatu_h,
656 0x00000000);
657 spr_register(env, SPR_DBAT7L, "DBAT7L",
658 SPR_NOACCESS, SPR_NOACCESS,
659 &spr_read_dbat_h, &spr_write_dbatl_h,
660 0x00000000);
661 env->nb_BATs += 4;
662 }
663
664 /* Generic PowerPC time base */
665 static void gen_tbl (CPUPPCState *env)
666 {
667 spr_register(env, SPR_VTBL, "TBL",
668 &spr_read_tbl, SPR_NOACCESS,
669 &spr_read_tbl, SPR_NOACCESS,
670 0x00000000);
671 spr_register(env, SPR_TBL, "TBL",
672 SPR_NOACCESS, SPR_NOACCESS,
673 SPR_NOACCESS, &spr_write_tbl,
674 0x00000000);
675 spr_register(env, SPR_VTBU, "TBU",
676 &spr_read_tbu, SPR_NOACCESS,
677 &spr_read_tbu, SPR_NOACCESS,
678 0x00000000);
679 spr_register(env, SPR_TBU, "TBU",
680 SPR_NOACCESS, SPR_NOACCESS,
681 SPR_NOACCESS, &spr_write_tbu,
682 0x00000000);
683 }
684
685 /* Softare table search registers */
686 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
687 {
688 env->nb_tlb = nb_tlbs;
689 env->nb_ways = nb_ways;
690 env->id_tlbs = 1;
691 spr_register(env, SPR_DMISS, "DMISS",
692 SPR_NOACCESS, SPR_NOACCESS,
693 &spr_read_generic, SPR_NOACCESS,
694 0x00000000);
695 spr_register(env, SPR_DCMP, "DCMP",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_generic, SPR_NOACCESS,
698 0x00000000);
699 spr_register(env, SPR_HASH1, "HASH1",
700 SPR_NOACCESS, SPR_NOACCESS,
701 &spr_read_generic, SPR_NOACCESS,
702 0x00000000);
703 spr_register(env, SPR_HASH2, "HASH2",
704 SPR_NOACCESS, SPR_NOACCESS,
705 &spr_read_generic, SPR_NOACCESS,
706 0x00000000);
707 spr_register(env, SPR_IMISS, "IMISS",
708 SPR_NOACCESS, SPR_NOACCESS,
709 &spr_read_generic, SPR_NOACCESS,
710 0x00000000);
711 spr_register(env, SPR_ICMP, "ICMP",
712 SPR_NOACCESS, SPR_NOACCESS,
713 &spr_read_generic, SPR_NOACCESS,
714 0x00000000);
715 spr_register(env, SPR_RPA, "RPA",
716 SPR_NOACCESS, SPR_NOACCESS,
717 &spr_read_generic, &spr_write_generic,
718 0x00000000);
719 }
720
721 /* SPR common to MPC755 and G2 */
722 static void gen_spr_G2_755 (CPUPPCState *env)
723 {
724 /* SGPRs */
725 spr_register(env, SPR_SPRG4, "SPRG4",
726 SPR_NOACCESS, SPR_NOACCESS,
727 &spr_read_generic, &spr_write_generic,
728 0x00000000);
729 spr_register(env, SPR_SPRG5, "SPRG5",
730 SPR_NOACCESS, SPR_NOACCESS,
731 &spr_read_generic, &spr_write_generic,
732 0x00000000);
733 spr_register(env, SPR_SPRG6, "SPRG6",
734 SPR_NOACCESS, SPR_NOACCESS,
735 &spr_read_generic, &spr_write_generic,
736 0x00000000);
737 spr_register(env, SPR_SPRG7, "SPRG7",
738 SPR_NOACCESS, SPR_NOACCESS,
739 &spr_read_generic, &spr_write_generic,
740 0x00000000);
741 /* External access control */
742 /* XXX : not implemented */
743 spr_register(env, SPR_EAR, "EAR",
744 SPR_NOACCESS, SPR_NOACCESS,
745 &spr_read_generic, &spr_write_generic,
746 0x00000000);
747 }
748
749 /* SPR common to all 7xx PowerPC implementations */
750 static void gen_spr_7xx (CPUPPCState *env)
751 {
752 /* Breakpoints */
753 /* XXX : not implemented */
754 spr_register(env, SPR_DABR, "DABR",
755 SPR_NOACCESS, SPR_NOACCESS,
756 &spr_read_generic, &spr_write_generic,
757 0x00000000);
758 /* XXX : not implemented */
759 spr_register(env, SPR_IABR, "IABR",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_generic, &spr_write_generic,
762 0x00000000);
763 /* Cache management */
764 /* XXX : not implemented */
765 spr_register(env, SPR_ICTC, "ICTC",
766 SPR_NOACCESS, SPR_NOACCESS,
767 &spr_read_generic, &spr_write_generic,
768 0x00000000);
769 /* XXX : not implemented */
770 spr_register(env, SPR_L2CR, "L2CR",
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_generic, &spr_write_generic,
773 0x00000000);
774 /* Performance monitors */
775 /* XXX : not implemented */
776 spr_register(env, SPR_MMCR0, "MMCR0",
777 SPR_NOACCESS, SPR_NOACCESS,
778 &spr_read_generic, &spr_write_generic,
779 0x00000000);
780 /* XXX : not implemented */
781 spr_register(env, SPR_MMCR1, "MMCR1",
782 SPR_NOACCESS, SPR_NOACCESS,
783 &spr_read_generic, &spr_write_generic,
784 0x00000000);
785 /* XXX : not implemented */
786 spr_register(env, SPR_PMC1, "PMC1",
787 SPR_NOACCESS, SPR_NOACCESS,
788 &spr_read_generic, &spr_write_generic,
789 0x00000000);
790 /* XXX : not implemented */
791 spr_register(env, SPR_PMC2, "PMC2",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_generic, &spr_write_generic,
794 0x00000000);
795 /* XXX : not implemented */
796 spr_register(env, SPR_PMC3, "PMC3",
797 SPR_NOACCESS, SPR_NOACCESS,
798 &spr_read_generic, &spr_write_generic,
799 0x00000000);
800 /* XXX : not implemented */
801 spr_register(env, SPR_PMC4, "PMC4",
802 SPR_NOACCESS, SPR_NOACCESS,
803 &spr_read_generic, &spr_write_generic,
804 0x00000000);
805 /* XXX : not implemented */
806 spr_register(env, SPR_SIAR, "SIAR",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_generic, SPR_NOACCESS,
809 0x00000000);
810 spr_register(env, SPR_UMMCR0, "UMMCR0",
811 &spr_read_ureg, SPR_NOACCESS,
812 &spr_read_ureg, SPR_NOACCESS,
813 0x00000000);
814 spr_register(env, SPR_UMMCR1, "UMMCR1",
815 &spr_read_ureg, SPR_NOACCESS,
816 &spr_read_ureg, SPR_NOACCESS,
817 0x00000000);
818 spr_register(env, SPR_UPMC1, "UPMC1",
819 &spr_read_ureg, SPR_NOACCESS,
820 &spr_read_ureg, SPR_NOACCESS,
821 0x00000000);
822 spr_register(env, SPR_UPMC2, "UPMC2",
823 &spr_read_ureg, SPR_NOACCESS,
824 &spr_read_ureg, SPR_NOACCESS,
825 0x00000000);
826 spr_register(env, SPR_UPMC3, "UPMC3",
827 &spr_read_ureg, SPR_NOACCESS,
828 &spr_read_ureg, SPR_NOACCESS,
829 0x00000000);
830 spr_register(env, SPR_UPMC4, "UPMC4",
831 &spr_read_ureg, SPR_NOACCESS,
832 &spr_read_ureg, SPR_NOACCESS,
833 0x00000000);
834 spr_register(env, SPR_USIAR, "USIAR",
835 &spr_read_ureg, SPR_NOACCESS,
836 &spr_read_ureg, SPR_NOACCESS,
837 0x00000000);
838 /* External access control */
839 /* XXX : not implemented */
840 spr_register(env, SPR_EAR, "EAR",
841 SPR_NOACCESS, SPR_NOACCESS,
842 &spr_read_generic, &spr_write_generic,
843 0x00000000);
844 }
845
846 static void gen_spr_thrm (CPUPPCState *env)
847 {
848 /* Thermal management */
849 /* XXX : not implemented */
850 spr_register(env, SPR_THRM1, "THRM1",
851 SPR_NOACCESS, SPR_NOACCESS,
852 &spr_read_generic, &spr_write_generic,
853 0x00000000);
854 /* XXX : not implemented */
855 spr_register(env, SPR_THRM2, "THRM2",
856 SPR_NOACCESS, SPR_NOACCESS,
857 &spr_read_generic, &spr_write_generic,
858 0x00000000);
859 /* XXX : not implemented */
860 spr_register(env, SPR_THRM3, "THRM3",
861 SPR_NOACCESS, SPR_NOACCESS,
862 &spr_read_generic, &spr_write_generic,
863 0x00000000);
864 }
865
866 /* SPR specific to PowerPC 604 implementation */
867 static void gen_spr_604 (CPUPPCState *env)
868 {
869 /* Processor identification */
870 spr_register(env, SPR_PIR, "PIR",
871 SPR_NOACCESS, SPR_NOACCESS,
872 &spr_read_generic, &spr_write_pir,
873 0x00000000);
874 /* Breakpoints */
875 /* XXX : not implemented */
876 spr_register(env, SPR_IABR, "IABR",
877 SPR_NOACCESS, SPR_NOACCESS,
878 &spr_read_generic, &spr_write_generic,
879 0x00000000);
880 /* XXX : not implemented */
881 spr_register(env, SPR_DABR, "DABR",
882 SPR_NOACCESS, SPR_NOACCESS,
883 &spr_read_generic, &spr_write_generic,
884 0x00000000);
885 /* Performance counters */
886 /* XXX : not implemented */
887 spr_register(env, SPR_MMCR0, "MMCR0",
888 SPR_NOACCESS, SPR_NOACCESS,
889 &spr_read_generic, &spr_write_generic,
890 0x00000000);
891 /* XXX : not implemented */
892 spr_register(env, SPR_MMCR1, "MMCR1",
893 SPR_NOACCESS, SPR_NOACCESS,
894 &spr_read_generic, &spr_write_generic,
895 0x00000000);
896 /* XXX : not implemented */
897 spr_register(env, SPR_PMC1, "PMC1",
898 SPR_NOACCESS, SPR_NOACCESS,
899 &spr_read_generic, &spr_write_generic,
900 0x00000000);
901 /* XXX : not implemented */
902 spr_register(env, SPR_PMC2, "PMC2",
903 SPR_NOACCESS, SPR_NOACCESS,
904 &spr_read_generic, &spr_write_generic,
905 0x00000000);
906 /* XXX : not implemented */
907 spr_register(env, SPR_PMC3, "PMC3",
908 SPR_NOACCESS, SPR_NOACCESS,
909 &spr_read_generic, &spr_write_generic,
910 0x00000000);
911 /* XXX : not implemented */
912 spr_register(env, SPR_PMC4, "PMC4",
913 SPR_NOACCESS, SPR_NOACCESS,
914 &spr_read_generic, &spr_write_generic,
915 0x00000000);
916 /* XXX : not implemented */
917 spr_register(env, SPR_SIAR, "SIAR",
918 SPR_NOACCESS, SPR_NOACCESS,
919 &spr_read_generic, SPR_NOACCESS,
920 0x00000000);
921 /* XXX : not implemented */
922 spr_register(env, SPR_SDA, "SDA",
923 SPR_NOACCESS, SPR_NOACCESS,
924 &spr_read_generic, SPR_NOACCESS,
925 0x00000000);
926 /* External access control */
927 /* XXX : not implemented */
928 spr_register(env, SPR_EAR, "EAR",
929 SPR_NOACCESS, SPR_NOACCESS,
930 &spr_read_generic, &spr_write_generic,
931 0x00000000);
932 }
933
934 /* SPR specific to PowerPC 603 implementation */
935 static void gen_spr_603 (CPUPPCState *env)
936 {
937 /* External access control */
938 /* XXX : not implemented */
939 spr_register(env, SPR_EAR, "EAR",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943 }
944
945 /* SPR specific to PowerPC G2 implementation */
946 static void gen_spr_G2 (CPUPPCState *env)
947 {
948 /* Memory base address */
949 /* MBAR */
950 spr_register(env, SPR_MBAR, "MBAR",
951 SPR_NOACCESS, SPR_NOACCESS,
952 &spr_read_generic, &spr_write_generic,
953 0x00000000);
954 /* System version register */
955 /* SVR */
956 spr_register(env, SPR_SVR, "SVR",
957 SPR_NOACCESS, SPR_NOACCESS,
958 &spr_read_generic, SPR_NOACCESS,
959 0x00000000);
960 /* Exception processing */
961 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
962 SPR_NOACCESS, SPR_NOACCESS,
963 &spr_read_generic, &spr_write_generic,
964 0x00000000);
965 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, &spr_write_generic,
968 0x00000000);
969 /* Breakpoints */
970 /* XXX : not implemented */
971 spr_register(env, SPR_DABR, "DABR",
972 SPR_NOACCESS, SPR_NOACCESS,
973 &spr_read_generic, &spr_write_generic,
974 0x00000000);
975 /* XXX : not implemented */
976 spr_register(env, SPR_DABR2, "DABR2",
977 SPR_NOACCESS, SPR_NOACCESS,
978 &spr_read_generic, &spr_write_generic,
979 0x00000000);
980 /* XXX : not implemented */
981 spr_register(env, SPR_IABR, "IABR",
982 SPR_NOACCESS, SPR_NOACCESS,
983 &spr_read_generic, &spr_write_generic,
984 0x00000000);
985 /* XXX : not implemented */
986 spr_register(env, SPR_IABR2, "IABR2",
987 SPR_NOACCESS, SPR_NOACCESS,
988 &spr_read_generic, &spr_write_generic,
989 0x00000000);
990 /* XXX : not implemented */
991 spr_register(env, SPR_IBCR, "IBCR",
992 SPR_NOACCESS, SPR_NOACCESS,
993 &spr_read_generic, &spr_write_generic,
994 0x00000000);
995 /* XXX : not implemented */
996 spr_register(env, SPR_DBCR, "DBCR",
997 SPR_NOACCESS, SPR_NOACCESS,
998 &spr_read_generic, &spr_write_generic,
999 0x00000000);
1000 }
1001
1002 /* SPR specific to PowerPC 602 implementation */
1003 static void gen_spr_602 (CPUPPCState *env)
1004 {
1005 /* ESA registers */
1006 /* XXX : not implemented */
1007 spr_register(env, SPR_SER, "SER",
1008 SPR_NOACCESS, SPR_NOACCESS,
1009 &spr_read_generic, &spr_write_generic,
1010 0x00000000);
1011 /* XXX : not implemented */
1012 spr_register(env, SPR_SEBR, "SEBR",
1013 SPR_NOACCESS, SPR_NOACCESS,
1014 &spr_read_generic, &spr_write_generic,
1015 0x00000000);
1016 /* XXX : not implemented */
1017 spr_register(env, SPR_ESASRR, "ESASRR",
1018 SPR_NOACCESS, SPR_NOACCESS,
1019 &spr_read_generic, &spr_write_generic,
1020 0x00000000);
1021 /* Floating point status */
1022 /* XXX : not implemented */
1023 spr_register(env, SPR_SP, "SP",
1024 SPR_NOACCESS, SPR_NOACCESS,
1025 &spr_read_generic, &spr_write_generic,
1026 0x00000000);
1027 /* XXX : not implemented */
1028 spr_register(env, SPR_LT, "LT",
1029 SPR_NOACCESS, SPR_NOACCESS,
1030 &spr_read_generic, &spr_write_generic,
1031 0x00000000);
1032 /* Watchdog timer */
1033 /* XXX : not implemented */
1034 spr_register(env, SPR_TCR, "TCR",
1035 SPR_NOACCESS, SPR_NOACCESS,
1036 &spr_read_generic, &spr_write_generic,
1037 0x00000000);
1038 /* Interrupt base */
1039 spr_register(env, SPR_IBR, "IBR",
1040 SPR_NOACCESS, SPR_NOACCESS,
1041 &spr_read_generic, &spr_write_generic,
1042 0x00000000);
1043 /* XXX : not implemented */
1044 spr_register(env, SPR_IABR, "IABR",
1045 SPR_NOACCESS, SPR_NOACCESS,
1046 &spr_read_generic, &spr_write_generic,
1047 0x00000000);
1048 }
1049
1050 /* SPR specific to PowerPC 601 implementation */
1051 static void gen_spr_601 (CPUPPCState *env)
1052 {
1053 /* Multiplication/division register */
1054 /* MQ */
1055 spr_register(env, SPR_MQ, "MQ",
1056 &spr_read_generic, &spr_write_generic,
1057 &spr_read_generic, &spr_write_generic,
1058 0x00000000);
1059 /* RTC registers */
1060 spr_register(env, SPR_601_RTCU, "RTCU",
1061 SPR_NOACCESS, SPR_NOACCESS,
1062 SPR_NOACCESS, &spr_write_601_rtcu,
1063 0x00000000);
1064 spr_register(env, SPR_601_VRTCU, "RTCU",
1065 &spr_read_601_rtcu, SPR_NOACCESS,
1066 &spr_read_601_rtcu, SPR_NOACCESS,
1067 0x00000000);
1068 spr_register(env, SPR_601_RTCL, "RTCL",
1069 SPR_NOACCESS, SPR_NOACCESS,
1070 SPR_NOACCESS, &spr_write_601_rtcl,
1071 0x00000000);
1072 spr_register(env, SPR_601_VRTCL, "RTCL",
1073 &spr_read_601_rtcl, SPR_NOACCESS,
1074 &spr_read_601_rtcl, SPR_NOACCESS,
1075 0x00000000);
1076 /* Timer */
1077 #if 0 /* ? */
1078 spr_register(env, SPR_601_UDECR, "UDECR",
1079 &spr_read_decr, SPR_NOACCESS,
1080 &spr_read_decr, SPR_NOACCESS,
1081 0x00000000);
1082 #endif
1083 /* External access control */
1084 /* XXX : not implemented */
1085 spr_register(env, SPR_EAR, "EAR",
1086 SPR_NOACCESS, SPR_NOACCESS,
1087 &spr_read_generic, &spr_write_generic,
1088 0x00000000);
1089 /* Memory management */
1090 spr_register(env, SPR_IBAT0U, "IBAT0U",
1091 SPR_NOACCESS, SPR_NOACCESS,
1092 &spr_read_601_ubat, &spr_write_601_ubatu,
1093 0x00000000);
1094 spr_register(env, SPR_IBAT0L, "IBAT0L",
1095 SPR_NOACCESS, SPR_NOACCESS,
1096 &spr_read_601_ubat, &spr_write_601_ubatl,
1097 0x00000000);
1098 spr_register(env, SPR_IBAT1U, "IBAT1U",
1099 SPR_NOACCESS, SPR_NOACCESS,
1100 &spr_read_601_ubat, &spr_write_601_ubatu,
1101 0x00000000);
1102 spr_register(env, SPR_IBAT1L, "IBAT1L",
1103 SPR_NOACCESS, SPR_NOACCESS,
1104 &spr_read_601_ubat, &spr_write_601_ubatl,
1105 0x00000000);
1106 spr_register(env, SPR_IBAT2U, "IBAT2U",
1107 SPR_NOACCESS, SPR_NOACCESS,
1108 &spr_read_601_ubat, &spr_write_601_ubatu,
1109 0x00000000);
1110 spr_register(env, SPR_IBAT2L, "IBAT2L",
1111 SPR_NOACCESS, SPR_NOACCESS,
1112 &spr_read_601_ubat, &spr_write_601_ubatl,
1113 0x00000000);
1114 spr_register(env, SPR_IBAT3U, "IBAT3U",
1115 SPR_NOACCESS, SPR_NOACCESS,
1116 &spr_read_601_ubat, &spr_write_601_ubatu,
1117 0x00000000);
1118 spr_register(env, SPR_IBAT3L, "IBAT3L",
1119 SPR_NOACCESS, SPR_NOACCESS,
1120 &spr_read_601_ubat, &spr_write_601_ubatl,
1121 0x00000000);
1122 env->nb_BATs = 4;
1123 }
1124
1125 static void gen_spr_74xx (CPUPPCState *env)
1126 {
1127 /* Processor identification */
1128 spr_register(env, SPR_PIR, "PIR",
1129 SPR_NOACCESS, SPR_NOACCESS,
1130 &spr_read_generic, &spr_write_pir,
1131 0x00000000);
1132 /* XXX : not implemented */
1133 spr_register(env, SPR_MMCR2, "MMCR2",
1134 SPR_NOACCESS, SPR_NOACCESS,
1135 &spr_read_generic, &spr_write_generic,
1136 0x00000000);
1137 spr_register(env, SPR_UMMCR2, "UMMCR2",
1138 &spr_read_ureg, SPR_NOACCESS,
1139 &spr_read_ureg, SPR_NOACCESS,
1140 0x00000000);
1141 /* XXX: not implemented */
1142 spr_register(env, SPR_BAMR, "BAMR",
1143 SPR_NOACCESS, SPR_NOACCESS,
1144 &spr_read_generic, &spr_write_generic,
1145 0x00000000);
1146 spr_register(env, SPR_UBAMR, "UBAMR",
1147 &spr_read_ureg, SPR_NOACCESS,
1148 &spr_read_ureg, SPR_NOACCESS,
1149 0x00000000);
1150 spr_register(env, SPR_MSSCR0, "MSSCR0",
1151 SPR_NOACCESS, SPR_NOACCESS,
1152 &spr_read_generic, &spr_write_generic,
1153 0x00000000);
1154 /* Hardware implementation registers */
1155 /* XXX : not implemented */
1156 spr_register(env, SPR_HID0, "HID0",
1157 SPR_NOACCESS, SPR_NOACCESS,
1158 &spr_read_generic, &spr_write_generic,
1159 0x00000000);
1160 /* XXX : not implemented */
1161 spr_register(env, SPR_HID1, "HID1",
1162 SPR_NOACCESS, SPR_NOACCESS,
1163 &spr_read_generic, &spr_write_generic,
1164 0x00000000);
1165 /* Altivec */
1166 spr_register(env, SPR_VRSAVE, "VRSAVE",
1167 &spr_read_generic, &spr_write_generic,
1168 &spr_read_generic, &spr_write_generic,
1169 0x00000000);
1170 }
1171
1172 #if defined (TODO)
1173 static void gen_l3_ctrl (CPUPPCState *env)
1174 {
1175 /* L3CR */
1176 /* XXX : not implemented */
1177 spr_register(env, SPR_L3CR, "L3CR",
1178 SPR_NOACCESS, SPR_NOACCESS,
1179 &spr_read_generic, &spr_write_generic,
1180 0x00000000);
1181 /* L3ITCR0 */
1182 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1183 SPR_NOACCESS, SPR_NOACCESS,
1184 &spr_read_generic, &spr_write_generic,
1185 0x00000000);
1186 /* L3ITCR1 */
1187 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1188 SPR_NOACCESS, SPR_NOACCESS,
1189 &spr_read_generic, &spr_write_generic,
1190 0x00000000);
1191 /* L3ITCR2 */
1192 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1193 SPR_NOACCESS, SPR_NOACCESS,
1194 &spr_read_generic, &spr_write_generic,
1195 0x00000000);
1196 /* L3ITCR3 */
1197 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1198 SPR_NOACCESS, SPR_NOACCESS,
1199 &spr_read_generic, &spr_write_generic,
1200 0x00000000);
1201 /* L3OHCR */
1202 spr_register(env, SPR_L3OHCR, "L3OHCR",
1203 SPR_NOACCESS, SPR_NOACCESS,
1204 &spr_read_generic, &spr_write_generic,
1205 0x00000000);
1206 /* L3PM */
1207 spr_register(env, SPR_L3PM, "L3PM",
1208 SPR_NOACCESS, SPR_NOACCESS,
1209 &spr_read_generic, &spr_write_generic,
1210 0x00000000);
1211 }
1212 #endif /* TODO */
1213
1214 #if defined (TODO)
1215 static void gen_74xx_soft_tlb (CPUPPCState *env)
1216 {
1217 /* XXX: TODO */
1218 spr_register(env, SPR_PTEHI, "PTEHI",
1219 SPR_NOACCESS, SPR_NOACCESS,
1220 &spr_read_generic, &spr_write_generic,
1221 0x00000000);
1222 spr_register(env, SPR_PTELO, "PTELO",
1223 SPR_NOACCESS, SPR_NOACCESS,
1224 &spr_read_generic, &spr_write_generic,
1225 0x00000000);
1226 spr_register(env, SPR_TLBMISS, "TLBMISS",
1227 SPR_NOACCESS, SPR_NOACCESS,
1228 &spr_read_generic, &spr_write_generic,
1229 0x00000000);
1230 }
1231 #endif /* TODO */
1232
1233 /* PowerPC BookE SPR */
1234 static void gen_spr_BookE (CPUPPCState *env)
1235 {
1236 /* Processor identification */
1237 spr_register(env, SPR_BOOKE_PIR, "PIR",
1238 SPR_NOACCESS, SPR_NOACCESS,
1239 &spr_read_generic, &spr_write_pir,
1240 0x00000000);
1241 /* Interrupt processing */
1242 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1243 SPR_NOACCESS, SPR_NOACCESS,
1244 &spr_read_generic, &spr_write_generic,
1245 0x00000000);
1246 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1247 SPR_NOACCESS, SPR_NOACCESS,
1248 &spr_read_generic, &spr_write_generic,
1249 0x00000000);
1250 #if 0
1251 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1252 SPR_NOACCESS, SPR_NOACCESS,
1253 &spr_read_generic, &spr_write_generic,
1254 0x00000000);
1255 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1256 SPR_NOACCESS, SPR_NOACCESS,
1257 &spr_read_generic, &spr_write_generic,
1258 0x00000000);
1259 #endif
1260 /* Debug */
1261 /* XXX : not implemented */
1262 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1263 SPR_NOACCESS, SPR_NOACCESS,
1264 &spr_read_generic, &spr_write_generic,
1265 0x00000000);
1266 /* XXX : not implemented */
1267 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1268 SPR_NOACCESS, SPR_NOACCESS,
1269 &spr_read_generic, &spr_write_generic,
1270 0x00000000);
1271 /* XXX : not implemented */
1272 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1273 SPR_NOACCESS, SPR_NOACCESS,
1274 &spr_read_generic, &spr_write_generic,
1275 0x00000000);
1276 /* XXX : not implemented */
1277 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1278 SPR_NOACCESS, SPR_NOACCESS,
1279 &spr_read_generic, &spr_write_generic,
1280 0x00000000);
1281 /* XXX : not implemented */
1282 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1283 SPR_NOACCESS, SPR_NOACCESS,
1284 &spr_read_generic, &spr_write_generic,
1285 0x00000000);
1286 /* XXX : not implemented */
1287 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1288 SPR_NOACCESS, SPR_NOACCESS,
1289 &spr_read_generic, &spr_write_generic,
1290 0x00000000);
1291 /* XXX : not implemented */
1292 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1293 SPR_NOACCESS, SPR_NOACCESS,
1294 &spr_read_generic, &spr_write_generic,
1295 0x00000000);
1296 /* XXX : not implemented */
1297 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1298 SPR_NOACCESS, SPR_NOACCESS,
1299 &spr_read_generic, &spr_write_generic,
1300 0x00000000);
1301 /* XXX : not implemented */
1302 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1303 SPR_NOACCESS, SPR_NOACCESS,
1304 &spr_read_generic, &spr_write_generic,
1305 0x00000000);
1306 /* XXX : not implemented */
1307 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1308 SPR_NOACCESS, SPR_NOACCESS,
1309 &spr_read_generic, &spr_write_generic,
1310 0x00000000);
1311 /* XXX : not implemented */
1312 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1313 SPR_NOACCESS, SPR_NOACCESS,
1314 &spr_read_generic, &spr_write_generic,
1315 0x00000000);
1316 /* XXX : not implemented */
1317 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1318 SPR_NOACCESS, SPR_NOACCESS,
1319 &spr_read_generic, &spr_write_clear,
1320 0x00000000);
1321 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1322 SPR_NOACCESS, SPR_NOACCESS,
1323 &spr_read_generic, &spr_write_generic,
1324 0x00000000);
1325 spr_register(env, SPR_BOOKE_ESR, "ESR",
1326 SPR_NOACCESS, SPR_NOACCESS,
1327 &spr_read_generic, &spr_write_generic,
1328 0x00000000);
1329 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1330 SPR_NOACCESS, SPR_NOACCESS,
1331 &spr_read_generic, &spr_write_generic,
1332 0x00000000);
1333 /* Exception vectors */
1334 spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1335 SPR_NOACCESS, SPR_NOACCESS,
1336 &spr_read_generic, &spr_write_generic,
1337 0x00000000);
1338 spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1339 SPR_NOACCESS, SPR_NOACCESS,
1340 &spr_read_generic, &spr_write_generic,
1341 0x00000000);
1342 spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1343 SPR_NOACCESS, SPR_NOACCESS,
1344 &spr_read_generic, &spr_write_generic,
1345 0x00000000);
1346 spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1347 SPR_NOACCESS, SPR_NOACCESS,
1348 &spr_read_generic, &spr_write_generic,
1349 0x00000000);
1350 spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_generic,
1353 0x00000000);
1354 spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1355 SPR_NOACCESS, SPR_NOACCESS,
1356 &spr_read_generic, &spr_write_generic,
1357 0x00000000);
1358 spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1359 SPR_NOACCESS, SPR_NOACCESS,
1360 &spr_read_generic, &spr_write_generic,
1361 0x00000000);
1362 spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1363 SPR_NOACCESS, SPR_NOACCESS,
1364 &spr_read_generic, &spr_write_generic,
1365 0x00000000);
1366 spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1367 SPR_NOACCESS, SPR_NOACCESS,
1368 &spr_read_generic, &spr_write_generic,
1369 0x00000000);
1370 spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1371 SPR_NOACCESS, SPR_NOACCESS,
1372 &spr_read_generic, &spr_write_generic,
1373 0x00000000);
1374 spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1375 SPR_NOACCESS, SPR_NOACCESS,
1376 &spr_read_generic, &spr_write_generic,
1377 0x00000000);
1378 spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1379 SPR_NOACCESS, SPR_NOACCESS,
1380 &spr_read_generic, &spr_write_generic,
1381 0x00000000);
1382 spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1383 SPR_NOACCESS, SPR_NOACCESS,
1384 &spr_read_generic, &spr_write_generic,
1385 0x00000000);
1386 spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1387 SPR_NOACCESS, SPR_NOACCESS,
1388 &spr_read_generic, &spr_write_generic,
1389 0x00000000);
1390 spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1391 SPR_NOACCESS, SPR_NOACCESS,
1392 &spr_read_generic, &spr_write_generic,
1393 0x00000000);
1394 spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1395 SPR_NOACCESS, SPR_NOACCESS,
1396 &spr_read_generic, &spr_write_generic,
1397 0x00000000);
1398 #if 0
1399 spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1400 SPR_NOACCESS, SPR_NOACCESS,
1401 &spr_read_generic, &spr_write_generic,
1402 0x00000000);
1403 spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1404 SPR_NOACCESS, SPR_NOACCESS,
1405 &spr_read_generic, &spr_write_generic,
1406 0x00000000);
1407 spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1408 SPR_NOACCESS, SPR_NOACCESS,
1409 &spr_read_generic, &spr_write_generic,
1410 0x00000000);
1411 spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1412 SPR_NOACCESS, SPR_NOACCESS,
1413 &spr_read_generic, &spr_write_generic,
1414 0x00000000);
1415 spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1416 SPR_NOACCESS, SPR_NOACCESS,
1417 &spr_read_generic, &spr_write_generic,
1418 0x00000000);
1419 spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1420 SPR_NOACCESS, SPR_NOACCESS,
1421 &spr_read_generic, &spr_write_generic,
1422 0x00000000);
1423 #endif
1424 spr_register(env, SPR_BOOKE_PID, "PID",
1425 SPR_NOACCESS, SPR_NOACCESS,
1426 &spr_read_generic, &spr_write_generic,
1427 0x00000000);
1428 spr_register(env, SPR_BOOKE_TCR, "TCR",
1429 SPR_NOACCESS, SPR_NOACCESS,
1430 &spr_read_generic, &spr_write_booke_tcr,
1431 0x00000000);
1432 spr_register(env, SPR_BOOKE_TSR, "TSR",
1433 SPR_NOACCESS, SPR_NOACCESS,
1434 &spr_read_generic, &spr_write_booke_tsr,
1435 0x00000000);
1436 /* Timer */
1437 spr_register(env, SPR_DECR, "DECR",
1438 SPR_NOACCESS, SPR_NOACCESS,
1439 &spr_read_decr, &spr_write_decr,
1440 0x00000000);
1441 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1442 SPR_NOACCESS, SPR_NOACCESS,
1443 SPR_NOACCESS, &spr_write_generic,
1444 0x00000000);
1445 /* SPRGs */
1446 spr_register(env, SPR_USPRG0, "USPRG0",
1447 &spr_read_generic, &spr_write_generic,
1448 &spr_read_generic, &spr_write_generic,
1449 0x00000000);
1450 spr_register(env, SPR_SPRG4, "SPRG4",
1451 SPR_NOACCESS, SPR_NOACCESS,
1452 &spr_read_generic, &spr_write_generic,
1453 0x00000000);
1454 spr_register(env, SPR_USPRG4, "USPRG4",
1455 &spr_read_ureg, SPR_NOACCESS,
1456 &spr_read_ureg, SPR_NOACCESS,
1457 0x00000000);
1458 spr_register(env, SPR_SPRG5, "SPRG5",
1459 SPR_NOACCESS, SPR_NOACCESS,
1460 &spr_read_generic, &spr_write_generic,
1461 0x00000000);
1462 spr_register(env, SPR_USPRG5, "USPRG5",
1463 &spr_read_ureg, SPR_NOACCESS,
1464 &spr_read_ureg, SPR_NOACCESS,
1465 0x00000000);
1466 spr_register(env, SPR_SPRG6, "SPRG6",
1467 SPR_NOACCESS, SPR_NOACCESS,
1468 &spr_read_generic, &spr_write_generic,
1469 0x00000000);
1470 spr_register(env, SPR_USPRG6, "USPRG6",
1471 &spr_read_ureg, SPR_NOACCESS,
1472 &spr_read_ureg, SPR_NOACCESS,
1473 0x00000000);
1474 spr_register(env, SPR_SPRG7, "SPRG7",
1475 SPR_NOACCESS, SPR_NOACCESS,
1476 &spr_read_generic, &spr_write_generic,
1477 0x00000000);
1478 spr_register(env, SPR_USPRG7, "USPRG7",
1479 &spr_read_ureg, SPR_NOACCESS,
1480 &spr_read_ureg, SPR_NOACCESS,
1481 0x00000000);
1482 }
1483
1484 /* FSL storage control registers */
1485 #if defined(TODO)
1486 static void gen_spr_BookE_FSL (CPUPPCState *env)
1487 {
1488 /* TLB assist registers */
1489 spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1490 SPR_NOACCESS, SPR_NOACCESS,
1491 &spr_read_generic, &spr_write_generic,
1492 0x00000000);
1493 spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1494 SPR_NOACCESS, SPR_NOACCESS,
1495 &spr_read_generic, &spr_write_generic,
1496 0x00000000);
1497 spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1498 SPR_NOACCESS, SPR_NOACCESS,
1499 &spr_read_generic, &spr_write_generic,
1500 0x00000000);
1501 spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1502 SPR_NOACCESS, SPR_NOACCESS,
1503 &spr_read_generic, &spr_write_generic,
1504 0x00000000);
1505 spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1506 SPR_NOACCESS, SPR_NOACCESS,
1507 &spr_read_generic, &spr_write_generic,
1508 0x00000000);
1509 spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1510 SPR_NOACCESS, SPR_NOACCESS,
1511 &spr_read_generic, &spr_write_generic,
1512 0x00000000);
1513 spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1514 SPR_NOACCESS, SPR_NOACCESS,
1515 &spr_read_generic, &spr_write_generic,
1516 0x00000000);
1517 if (env->nb_pids > 1) {
1518 spr_register(env, SPR_BOOKE_PID1, "PID1",
1519 SPR_NOACCESS, SPR_NOACCESS,
1520 &spr_read_generic, &spr_write_generic,
1521 0x00000000);
1522 }
1523 if (env->nb_pids > 2) {
1524 spr_register(env, SPR_BOOKE_PID2, "PID2",
1525 SPR_NOACCESS, SPR_NOACCESS,
1526 &spr_read_generic, &spr_write_generic,
1527 0x00000000);
1528 }
1529 spr_register(env, SPR_BOOKE_MMUCFG, "MMUCFG",
1530 SPR_NOACCESS, SPR_NOACCESS,
1531 &spr_read_generic, SPR_NOACCESS,
1532 0x00000000); /* TOFIX */
1533 spr_register(env, SPR_BOOKE_MMUCSR0, "MMUCSR0",
1534 SPR_NOACCESS, SPR_NOACCESS,
1535 &spr_read_generic, &spr_write_generic,
1536 0x00000000); /* TOFIX */
1537 switch (env->nb_ways) {
1538 case 4:
1539 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1540 SPR_NOACCESS, SPR_NOACCESS,
1541 &spr_read_generic, SPR_NOACCESS,
1542 0x00000000); /* TOFIX */
1543 /* Fallthru */
1544 case 3:
1545 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1546 SPR_NOACCESS, SPR_NOACCESS,
1547 &spr_read_generic, SPR_NOACCESS,
1548 0x00000000); /* TOFIX */
1549 /* Fallthru */
1550 case 2:
1551 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1552 SPR_NOACCESS, SPR_NOACCESS,
1553 &spr_read_generic, SPR_NOACCESS,
1554 0x00000000); /* TOFIX */
1555 /* Fallthru */
1556 case 1:
1557 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1558 SPR_NOACCESS, SPR_NOACCESS,
1559 &spr_read_generic, SPR_NOACCESS,
1560 0x00000000); /* TOFIX */
1561 /* Fallthru */
1562 case 0:
1563 default:
1564 break;
1565 }
1566 }
1567 #endif
1568
1569 /* SPR specific to PowerPC 440 implementation */
1570 static void gen_spr_440 (CPUPPCState *env)
1571 {
1572 /* Cache control */
1573 /* XXX : not implemented */
1574 spr_register(env, SPR_440_DNV0, "DNV0",
1575 SPR_NOACCESS, SPR_NOACCESS,
1576 &spr_read_generic, &spr_write_generic,
1577 0x00000000);
1578 /* XXX : not implemented */
1579 spr_register(env, SPR_440_DNV1, "DNV1",
1580 SPR_NOACCESS, SPR_NOACCESS,
1581 &spr_read_generic, &spr_write_generic,
1582 0x00000000);
1583 /* XXX : not implemented */
1584 spr_register(env, SPR_440_DNV2, "DNV2",
1585 SPR_NOACCESS, SPR_NOACCESS,
1586 &spr_read_generic, &spr_write_generic,
1587 0x00000000);
1588 /* XXX : not implemented */
1589 spr_register(env, SPR_440_DNV3, "DNV3",
1590 SPR_NOACCESS, SPR_NOACCESS,
1591 &spr_read_generic, &spr_write_generic,
1592 0x00000000);
1593 /* XXX : not implemented */
1594 spr_register(env, SPR_440_DTV0, "DTV0",
1595 SPR_NOACCESS, SPR_NOACCESS,
1596 &spr_read_generic, &spr_write_generic,
1597 0x00000000);
1598 /* XXX : not implemented */
1599 spr_register(env, SPR_440_DTV1, "DTV1",
1600 SPR_NOACCESS, SPR_NOACCESS,
1601 &spr_read_generic, &spr_write_generic,
1602 0x00000000);
1603 /* XXX : not implemented */
1604 spr_register(env, SPR_440_DTV2, "DTV2",
1605 SPR_NOACCESS, SPR_NOACCESS,
1606 &spr_read_generic, &spr_write_generic,
1607 0x00000000);
1608 /* XXX : not implemented */
1609 spr_register(env, SPR_440_DTV3, "DTV3",
1610 SPR_NOACCESS, SPR_NOACCESS,
1611 &spr_read_generic, &spr_write_generic,
1612 0x00000000);
1613 /* XXX : not implemented */
1614 spr_register(env, SPR_440_DVLIM, "DVLIM",
1615 SPR_NOACCESS, SPR_NOACCESS,
1616 &spr_read_generic, &spr_write_generic,
1617 0x00000000);
1618 /* XXX : not implemented */
1619 spr_register(env, SPR_440_INV0, "INV0",
1620 SPR_NOACCESS, SPR_NOACCESS,
1621 &spr_read_generic, &spr_write_generic,
1622 0x00000000);
1623 /* XXX : not implemented */
1624 spr_register(env, SPR_440_INV1, "INV1",
1625 SPR_NOACCESS, SPR_NOACCESS,
1626 &spr_read_generic, &spr_write_generic,
1627 0x00000000);
1628 /* XXX : not implemented */
1629 spr_register(env, SPR_440_INV2, "INV2",
1630 SPR_NOACCESS, SPR_NOACCESS,
1631 &spr_read_generic, &spr_write_generic,
1632 0x00000000);
1633 /* XXX : not implemented */
1634 spr_register(env, SPR_440_INV3, "INV3",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 &spr_read_generic, &spr_write_generic,
1637 0x00000000);
1638 /* XXX : not implemented */
1639 spr_register(env, SPR_440_ITV0, "ITV0",
1640 SPR_NOACCESS, SPR_NOACCESS,
1641 &spr_read_generic, &spr_write_generic,
1642 0x00000000);
1643 /* XXX : not implemented */
1644 spr_register(env, SPR_440_ITV1, "ITV1",
1645 SPR_NOACCESS, SPR_NOACCESS,
1646 &spr_read_generic, &spr_write_generic,
1647 0x00000000);
1648 /* XXX : not implemented */
1649 spr_register(env, SPR_440_ITV2, "ITV2",
1650 SPR_NOACCESS, SPR_NOACCESS,
1651 &spr_read_generic, &spr_write_generic,
1652 0x00000000);
1653 /* XXX : not implemented */
1654 spr_register(env, SPR_440_ITV3, "ITV3",
1655 SPR_NOACCESS, SPR_NOACCESS,
1656 &spr_read_generic, &spr_write_generic,
1657 0x00000000);
1658 /* XXX : not implemented */
1659 spr_register(env, SPR_440_IVLIM, "IVLIM",
1660 SPR_NOACCESS, SPR_NOACCESS,
1661 &spr_read_generic, &spr_write_generic,
1662 0x00000000);
1663 /* Cache debug */
1664 /* XXX : not implemented */
1665 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1666 SPR_NOACCESS, SPR_NOACCESS,
1667 &spr_read_generic, SPR_NOACCESS,
1668 0x00000000);
1669 /* XXX : not implemented */
1670 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1671 SPR_NOACCESS, SPR_NOACCESS,
1672 &spr_read_generic, SPR_NOACCESS,
1673 0x00000000);
1674 /* XXX : not implemented */
1675 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1676 SPR_NOACCESS, SPR_NOACCESS,
1677 &spr_read_generic, SPR_NOACCESS,
1678 0x00000000);
1679 /* XXX : not implemented */
1680 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1681 SPR_NOACCESS, SPR_NOACCESS,
1682 &spr_read_generic, SPR_NOACCESS,
1683 0x00000000);
1684 /* XXX : not implemented */
1685 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1686 SPR_NOACCESS, SPR_NOACCESS,
1687 &spr_read_generic, SPR_NOACCESS,
1688 0x00000000);
1689 /* XXX : not implemented */
1690 spr_register(env, SPR_440_DBDR, "DBDR",
1691 SPR_NOACCESS, SPR_NOACCESS,
1692 &spr_read_generic, &spr_write_generic,
1693 0x00000000);
1694 /* Processor control */
1695 spr_register(env, SPR_4xx_CCR0, "CCR0",
1696 SPR_NOACCESS, SPR_NOACCESS,
1697 &spr_read_generic, &spr_write_generic,
1698 0x00000000);
1699 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1700 SPR_NOACCESS, SPR_NOACCESS,
1701 &spr_read_generic, SPR_NOACCESS,
1702 0x00000000);
1703 /* Storage control */
1704 spr_register(env, SPR_440_MMUCR, "MMUCR",
1705 SPR_NOACCESS, SPR_NOACCESS,
1706 &spr_read_generic, &spr_write_generic,
1707 0x00000000);
1708 }
1709
1710 /* SPR shared between PowerPC 40x implementations */
1711 static void gen_spr_40x (CPUPPCState *env)
1712 {
1713 /* Cache */
1714 /* XXX : not implemented */
1715 spr_register(env, SPR_40x_DCCR, "DCCR",
1716 SPR_NOACCESS, SPR_NOACCESS,
1717 &spr_read_generic, &spr_write_generic,
1718 0x00000000);
1719 /* XXX : not implemented */
1720 spr_register(env, SPR_40x_ICCR, "ICCR",
1721 SPR_NOACCESS, SPR_NOACCESS,
1722 &spr_read_generic, &spr_write_generic,
1723 0x00000000);
1724 /* XXX : not implemented */
1725 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1726 SPR_NOACCESS, SPR_NOACCESS,
1727 &spr_read_generic, SPR_NOACCESS,
1728 0x00000000);
1729 /* Exception */
1730 spr_register(env, SPR_40x_DEAR, "DEAR",
1731 SPR_NOACCESS, SPR_NOACCESS,
1732 &spr_read_generic, &spr_write_generic,
1733 0x00000000);
1734 spr_register(env, SPR_40x_ESR, "ESR",
1735 SPR_NOACCESS, SPR_NOACCESS,
1736 &spr_read_generic, &spr_write_generic,
1737 0x00000000);
1738 spr_register(env, SPR_40x_EVPR, "EVPR",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, &spr_write_generic,
1741 0x00000000);
1742 spr_register(env, SPR_40x_SRR2, "SRR2",
1743 &spr_read_generic, &spr_write_generic,
1744 &spr_read_generic, &spr_write_generic,
1745 0x00000000);
1746 spr_register(env, SPR_40x_SRR3, "SRR3",
1747 &spr_read_generic, &spr_write_generic,
1748 &spr_read_generic, &spr_write_generic,
1749 0x00000000);
1750 /* Timers */
1751 spr_register(env, SPR_40x_PIT, "PIT",
1752 SPR_NOACCESS, SPR_NOACCESS,
1753 &spr_read_40x_pit, &spr_write_40x_pit,
1754 0x00000000);
1755 spr_register(env, SPR_40x_TCR, "TCR",
1756 SPR_NOACCESS, SPR_NOACCESS,
1757 &spr_read_generic, &spr_write_booke_tcr,
1758 0x00000000);
1759 spr_register(env, SPR_40x_TSR, "TSR",
1760 SPR_NOACCESS, SPR_NOACCESS,
1761 &spr_read_generic, &spr_write_booke_tsr,
1762 0x00000000);
1763 }
1764
1765 /* SPR specific to PowerPC 405 implementation */
1766 static void gen_spr_405 (CPUPPCState *env)
1767 {
1768 /* MMU */
1769 spr_register(env, SPR_40x_PID, "PID",
1770 SPR_NOACCESS, SPR_NOACCESS,
1771 &spr_read_generic, &spr_write_generic,
1772 0x00000000);
1773 spr_register(env, SPR_4xx_CCR0, "CCR0",
1774 SPR_NOACCESS, SPR_NOACCESS,
1775 &spr_read_generic, &spr_write_generic,
1776 0x00700000);
1777 /* Debug interface */
1778 /* XXX : not implemented */
1779 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1780 SPR_NOACCESS, SPR_NOACCESS,
1781 &spr_read_generic, &spr_write_40x_dbcr0,
1782 0x00000000);
1783 /* XXX : not implemented */
1784 spr_register(env, SPR_405_DBCR1, "DBCR1",
1785 SPR_NOACCESS, SPR_NOACCESS,
1786 &spr_read_generic, &spr_write_generic,
1787 0x00000000);
1788 /* XXX : not implemented */
1789 spr_register(env, SPR_40x_DBSR, "DBSR",
1790 SPR_NOACCESS, SPR_NOACCESS,
1791 &spr_read_generic, &spr_write_clear,
1792 /* Last reset was system reset */
1793 0x00000300);
1794 /* XXX : not implemented */
1795 spr_register(env, SPR_40x_DAC1, "DAC1",
1796 SPR_NOACCESS, SPR_NOACCESS,
1797 &spr_read_generic, &spr_write_generic,
1798 0x00000000);
1799 spr_register(env, SPR_40x_DAC2, "DAC2",
1800 SPR_NOACCESS, SPR_NOACCESS,
1801 &spr_read_generic, &spr_write_generic,
1802 0x00000000);
1803 /* XXX : not implemented */
1804 spr_register(env, SPR_405_DVC1, "DVC1",
1805 SPR_NOACCESS, SPR_NOACCESS,
1806 &spr_read_generic, &spr_write_generic,
1807 0x00000000);
1808 /* XXX : not implemented */
1809 spr_register(env, SPR_405_DVC2, "DVC2",
1810 SPR_NOACCESS, SPR_NOACCESS,
1811 &spr_read_generic, &spr_write_generic,
1812 0x00000000);
1813 /* XXX : not implemented */
1814 spr_register(env, SPR_40x_IAC1, "IAC1",
1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_generic, &spr_write_generic,
1817 0x00000000);
1818 spr_register(env, SPR_40x_IAC2, "IAC2",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, &spr_write_generic,
1821 0x00000000);
1822 /* XXX : not implemented */
1823 spr_register(env, SPR_405_IAC3, "IAC3",
1824 SPR_NOACCESS, SPR_NOACCESS,
1825 &spr_read_generic, &spr_write_generic,
1826 0x00000000);
1827 /* XXX : not implemented */
1828 spr_register(env, SPR_405_IAC4, "IAC4",
1829 SPR_NOACCESS, SPR_NOACCESS,
1830 &spr_read_generic, &spr_write_generic,
1831 0x00000000);
1832 /* Storage control */
1833 spr_register(env, SPR_405_SLER, "SLER",
1834 SPR_NOACCESS, SPR_NOACCESS,
1835 &spr_read_generic, &spr_write_40x_sler,
1836 0x00000000);
1837 spr_register(env, SPR_40x_ZPR, "ZPR",
1838 SPR_NOACCESS, SPR_NOACCESS,
1839 &spr_read_generic, &spr_write_generic,
1840 0x00000000);
1841 /* XXX : not implemented */
1842 spr_register(env, SPR_405_SU0R, "SU0R",
1843 SPR_NOACCESS, SPR_NOACCESS,
1844 &spr_read_generic, &spr_write_generic,
1845 0x00000000);
1846 /* SPRG */
1847 spr_register(env, SPR_USPRG0, "USPRG0",
1848 &spr_read_ureg, SPR_NOACCESS,
1849 &spr_read_ureg, SPR_NOACCESS,
1850 0x00000000);
1851 spr_register(env, SPR_SPRG4, "SPRG4",
1852 SPR_NOACCESS, SPR_NOACCESS,
1853 &spr_read_generic, &spr_write_generic,
1854 0x00000000);
1855 spr_register(env, SPR_USPRG4, "USPRG4",
1856 &spr_read_ureg, SPR_NOACCESS,
1857 &spr_read_ureg, SPR_NOACCESS,
1858 0x00000000);
1859 spr_register(env, SPR_SPRG5, "SPRG5",
1860 SPR_NOACCESS, SPR_NOACCESS,
1861 spr_read_generic, &spr_write_generic,
1862 0x00000000);
1863 spr_register(env, SPR_USPRG5, "USPRG5",
1864 &spr_read_ureg, SPR_NOACCESS,
1865 &spr_read_ureg, SPR_NOACCESS,
1866 0x00000000);
1867 spr_register(env, SPR_SPRG6, "SPRG6",
1868 SPR_NOACCESS, SPR_NOACCESS,
1869 spr_read_generic, &spr_write_generic,
1870 0x00000000);
1871 spr_register(env, SPR_USPRG6, "USPRG6",
1872 &spr_read_ureg, SPR_NOACCESS,
1873 &spr_read_ureg, SPR_NOACCESS,
1874 0x00000000);
1875 spr_register(env, SPR_SPRG7, "SPRG7",
1876 SPR_NOACCESS, SPR_NOACCESS,
1877 spr_read_generic, &spr_write_generic,
1878 0x00000000);
1879 spr_register(env, SPR_USPRG7, "USPRG7",
1880 &spr_read_ureg, SPR_NOACCESS,
1881 &spr_read_ureg, SPR_NOACCESS,
1882 0x00000000);
1883 }
1884
1885 /* SPR shared between PowerPC 401 & 403 implementations */
1886 static void gen_spr_401_403 (CPUPPCState *env)
1887 {
1888 /* Time base */
1889 spr_register(env, SPR_403_VTBL, "TBL",
1890 &spr_read_tbl, SPR_NOACCESS,
1891 &spr_read_tbl, SPR_NOACCESS,
1892 0x00000000);
1893 spr_register(env, SPR_403_TBL, "TBL",
1894 SPR_NOACCESS, SPR_NOACCESS,
1895 SPR_NOACCESS, &spr_write_tbl,
1896 0x00000000);
1897 spr_register(env, SPR_403_VTBU, "TBU",
1898 &spr_read_tbu, SPR_NOACCESS,
1899 &spr_read_tbu, SPR_NOACCESS,
1900 0x00000000);
1901 spr_register(env, SPR_403_TBU, "TBU",
1902 SPR_NOACCESS, SPR_NOACCESS,
1903 SPR_NOACCESS, &spr_write_tbu,
1904 0x00000000);
1905 /* Debug */
1906 /* XXX: not implemented */
1907 spr_register(env, SPR_403_CDBCR, "CDBCR",
1908 SPR_NOACCESS, SPR_NOACCESS,
1909 &spr_read_generic, &spr_write_generic,
1910 0x00000000);
1911 }
1912
1913 /* SPR specific to PowerPC 401 implementation */
1914 static void gen_spr_401 (CPUPPCState *env)
1915 {
1916 /* Debug interface */
1917 /* XXX : not implemented */
1918 spr_register(env, SPR_40x_DBCR0, "DBCR",
1919 SPR_NOACCESS, SPR_NOACCESS,
1920 &spr_read_generic, &spr_write_40x_dbcr0,
1921 0x00000000);
1922 /* XXX : not implemented */
1923 spr_register(env, SPR_40x_DBSR, "DBSR",
1924 SPR_NOACCESS, SPR_NOACCESS,
1925 &spr_read_generic, &spr_write_clear,
1926 /* Last reset was system reset */
1927 0x00000300);
1928 /* XXX : not implemented */
1929 spr_register(env, SPR_40x_DAC1, "DAC",
1930 SPR_NOACCESS, SPR_NOACCESS,
1931 &spr_read_generic, &spr_write_generic,
1932 0x00000000);
1933 /* XXX : not implemented */
1934 spr_register(env, SPR_40x_IAC1, "IAC",
1935 SPR_NOACCESS, SPR_NOACCESS,
1936 &spr_read_generic, &spr_write_generic,
1937 0x00000000);
1938 /* Storage control */
1939 spr_register(env, SPR_405_SLER, "SLER",
1940 SPR_NOACCESS, SPR_NOACCESS,
1941 &spr_read_generic, &spr_write_40x_sler,
1942 0x00000000);
1943 }
1944
1945 static void gen_spr_401x2 (CPUPPCState *env)
1946 {
1947 gen_spr_401(env);
1948 spr_register(env, SPR_40x_PID, "PID",
1949 SPR_NOACCESS, SPR_NOACCESS,
1950 &spr_read_generic, &spr_write_generic,
1951 0x00000000);
1952 spr_register(env, SPR_40x_ZPR, "ZPR",
1953 SPR_NOACCESS, SPR_NOACCESS,
1954 &spr_read_generic, &spr_write_generic,
1955 0x00000000);
1956 }
1957
1958 /* SPR specific to PowerPC 403 implementation */
1959 static void gen_spr_403 (CPUPPCState *env)
1960 {
1961 /* Debug interface */
1962 /* XXX : not implemented */
1963 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1964 SPR_NOACCESS, SPR_NOACCESS,
1965 &spr_read_generic, &spr_write_40x_dbcr0,
1966 0x00000000);
1967 /* XXX : not implemented */
1968 spr_register(env, SPR_40x_DBSR, "DBSR",
1969 SPR_NOACCESS, SPR_NOACCESS,
1970 &spr_read_generic, &spr_write_clear,
1971 /* Last reset was system reset */
1972 0x00000300);
1973 /* XXX : not implemented */
1974 spr_register(env, SPR_40x_DAC1, "DAC1",
1975 SPR_NOACCESS, SPR_NOACCESS,
1976 &spr_read_generic, &spr_write_generic,
1977 0x00000000);
1978 spr_register(env, SPR_40x_DAC2, "DAC2",
1979 SPR_NOACCESS, SPR_NOACCESS,
1980 &spr_read_generic, &spr_write_generic,
1981 0x00000000);
1982 /* XXX : not implemented */
1983 spr_register(env, SPR_40x_IAC1, "IAC1",
1984 SPR_NOACCESS, SPR_NOACCESS,
1985 &spr_read_generic, &spr_write_generic,
1986 0x00000000);
1987 spr_register(env, SPR_40x_IAC2, "IAC2",
1988 SPR_NOACCESS, SPR_NOACCESS,
1989 &spr_read_generic, &spr_write_generic,
1990 0x00000000);
1991 }
1992
1993 static void gen_spr_403_real (CPUPPCState *env)
1994 {
1995 spr_register(env, SPR_403_PBL1, "PBL1",
1996 SPR_NOACCESS, SPR_NOACCESS,
1997 &spr_read_403_pbr, &spr_write_403_pbr,
1998 0x00000000);
1999 spr_register(env, SPR_403_PBU1, "PBU1",
2000 SPR_NOACCESS, SPR_NOACCESS,
2001 &spr_read_403_pbr, &spr_write_403_pbr,
2002 0x00000000);
2003 spr_register(env, SPR_403_PBL2, "PBL2",
2004 SPR_NOACCESS, SPR_NOACCESS,
2005 &spr_read_403_pbr, &spr_write_403_pbr,
2006 0x00000000);
2007 spr_register(env, SPR_403_PBU2, "PBU2",
2008 SPR_NOACCESS, SPR_NOACCESS,
2009 &spr_read_403_pbr, &spr_write_403_pbr,
2010 0x00000000);
2011 }
2012
2013 static void gen_spr_403_mmu (CPUPPCState *env)
2014 {
2015 /* MMU */
2016 spr_register(env, SPR_40x_PID, "PID",
2017 SPR_NOACCESS, SPR_NOACCESS,
2018 &spr_read_generic, &spr_write_generic,
2019 0x00000000);
2020 spr_register(env, SPR_40x_ZPR, "ZPR",
2021 SPR_NOACCESS, SPR_NOACCESS,
2022 &spr_read_generic, &spr_write_generic,
2023 0x00000000);
2024 }
2025
2026 /* SPR specific to PowerPC compression coprocessor extension */
2027 static void gen_spr_compress (CPUPPCState *env)
2028 {
2029 spr_register(env, SPR_401_SKR, "SKR",
2030 SPR_NOACCESS, SPR_NOACCESS,
2031 &spr_read_generic, &spr_write_generic,
2032 0x00000000);
2033 }
2034
2035 #if defined (TARGET_PPC64)
2036 #if defined (TODO)
2037 /* SPR specific to PowerPC 620 */
2038 static void gen_spr_620 (CPUPPCState *env)
2039 {
2040 spr_register(env, SPR_620_PMR0, "PMR0",
2041 SPR_NOACCESS, SPR_NOACCESS,
2042 &spr_read_generic, &spr_write_generic,
2043 0x00000000);
2044 spr_register(env, SPR_620_PMR1, "PMR1",
2045 SPR_NOACCESS, SPR_NOACCESS,
2046 &spr_read_generic, &spr_write_generic,
2047 0x00000000);
2048 spr_register(env, SPR_620_PMR2, "PMR2",
2049 SPR_NOACCESS, SPR_NOACCESS,
2050 &spr_read_generic, &spr_write_generic,
2051 0x00000000);
2052 spr_register(env, SPR_620_PMR3, "PMR3",
2053 SPR_NOACCESS, SPR_NOACCESS,
2054 &spr_read_generic, &spr_write_generic,
2055 0x00000000);
2056 spr_register(env, SPR_620_PMR4, "PMR4",
2057 SPR_NOACCESS, SPR_NOACCESS,
2058 &spr_read_generic, &spr_write_generic,
2059 0x00000000);
2060 spr_register(env, SPR_620_PMR5, "PMR5",
2061 SPR_NOACCESS, SPR_NOACCESS,
2062 &spr_read_generic, &spr_write_generic,
2063 0x00000000);
2064 spr_register(env, SPR_620_PMR6, "PMR6",
2065 SPR_NOACCESS, SPR_NOACCESS,
2066 &spr_read_generic, &spr_write_generic,
2067 0x00000000);
2068 spr_register(env, SPR_620_PMR7, "PMR7",
2069 SPR_NOACCESS, SPR_NOACCESS,
2070 &spr_read_generic, &spr_write_generic,
2071 0x00000000);
2072 spr_register(env, SPR_620_PMR8, "PMR8",
2073 SPR_NOACCESS, SPR_NOACCESS,
2074 &spr_read_generic, &spr_write_generic,
2075 0x00000000);
2076 spr_register(env, SPR_620_PMR9, "PMR9",
2077 SPR_NOACCESS, SPR_NOACCESS,
2078 &spr_read_generic, &spr_write_generic,
2079 0x00000000);
2080 spr_register(env, SPR_620_PMRA, "PMR10",
2081 SPR_NOACCESS, SPR_NOACCESS,
2082 &spr_read_generic, &spr_write_generic,
2083 0x00000000);
2084 spr_register(env, SPR_620_PMRB, "PMR11",
2085 SPR_NOACCESS, SPR_NOACCESS,
2086 &spr_read_generic, &spr_write_generic,
2087 0x00000000);
2088 spr_register(env, SPR_620_PMRC, "PMR12",
2089 SPR_NOACCESS, SPR_NOACCESS,
2090 &spr_read_generic, &spr_write_generic,
2091 0x00000000);
2092 spr_register(env, SPR_620_PMRD, "PMR13",
2093 SPR_NOACCESS, SPR_NOACCESS,
2094 &spr_read_generic, &spr_write_generic,
2095 0x00000000);
2096 spr_register(env, SPR_620_PMRE, "PMR14",
2097 SPR_NOACCESS, SPR_NOACCESS,
2098 &spr_read_generic, &spr_write_generic,
2099 0x00000000);
2100 spr_register(env, SPR_620_PMRF, "PMR15",
2101 SPR_NOACCESS, SPR_NOACCESS,
2102 &spr_read_generic, &spr_write_generic,
2103 0x00000000);
2104 spr_register(env, SPR_620_HID8, "HID8",
2105 SPR_NOACCESS, SPR_NOACCESS,
2106 &spr_read_generic, &spr_write_generic,
2107 0x00000000);
2108 spr_register(env, SPR_620_HID9, "HID9",
2109 SPR_NOACCESS, SPR_NOACCESS,
2110 &spr_read_generic, &spr_write_generic,
2111 0x00000000);
2112 }
2113 #endif
2114 #endif /* defined (TARGET_PPC64) */
2115
2116 // XXX: TODO
2117 /*
2118 * AMR => SPR 29 (Power 2.04)
2119 * CTRL => SPR 136 (Power 2.04)
2120 * CTRL => SPR 152 (Power 2.04)
2121 * SCOMC => SPR 276 (64 bits ?)
2122 * SCOMD => SPR 277 (64 bits ?)
2123 * ASR => SPR 280 (64 bits)
2124 * TBU40 => SPR 286 (Power 2.04 hypv)
2125 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2126 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2127 * HDSISR => SPR 306 (Power 2.04 hypv)
2128 * HDAR => SPR 307 (Power 2.04 hypv)
2129 * PURR => SPR 309 (Power 2.04 hypv)
2130 * HDEC => SPR 310 (Power 2.04 hypv)
2131 * HIOR => SPR 311 (hypv)
2132 * RMOR => SPR 312 (970)
2133 * HRMOR => SPR 313 (Power 2.04 hypv)
2134 * HSRR0 => SPR 314 (Power 2.04 hypv)
2135 * HSRR1 => SPR 315 (Power 2.04 hypv)
2136 * LPCR => SPR 316 (970)
2137 * LPIDR => SPR 317 (970)
2138 * SPEFSCR => SPR 512 (Power 2.04 emb)
2139 * ATBL => SPR 526 (Power 2.04 emb)
2140 * ATBU => SPR 527 (Power 2.04 emb)
2141 * EPR => SPR 702 (Power 2.04 emb)
2142 * perf => 768-783 (Power 2.04)
2143 * perf => 784-799 (Power 2.04)
2144 * PPR => SPR 896 (Power 2.04)
2145 * EPLC => SPR 947 (Power 2.04 emb)
2146 * EPSC => SPR 948 (Power 2.04 emb)
2147 * DABRX => 1015 (Power 2.04 hypv)
2148 * FPECR => SPR 1022 (?)
2149 * ... and more (thermal management, performance counters, ...)
2150 */
2151
2152 /*****************************************************************************/
2153 /* PowerPC implementations definitions */
2154
2155 /* PowerPC 40x instruction set */
2156 #define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_EMB_COMMON)
2157
2158 /* PowerPC 401 */
2159 #define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | \
2160 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2161 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2162 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
2163 #define POWERPC_MMU_401 (POWERPC_MMU_REAL_4xx)
2164 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
2165 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
2166
2167 static void init_proc_401 (CPUPPCState *env)
2168 {
2169 gen_spr_40x(env);
2170 gen_spr_401_403(env);
2171 gen_spr_401(env);
2172 /* Bus access control */
2173 spr_register(env, SPR_40x_SGR, "SGR",
2174 SPR_NOACCESS, SPR_NOACCESS,
2175 &spr_read_generic, &spr_write_generic,
2176 0xFFFFFFFF);
2177 /* XXX : not implemented */
2178 spr_register(env, SPR_40x_DCWR, "DCWR",
2179 SPR_NOACCESS, SPR_NOACCESS,
2180 &spr_read_generic, &spr_write_generic,
2181 0x00000000);
2182 /* XXX: TODO: allocate internal IRQ controller */
2183 }
2184
2185 /* PowerPC 401x2 */
2186 #define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | \
2187 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2188 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2189 PPC_CACHE_DCBA | PPC_MFTB | \
2190 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2191 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
2192 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
2193 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
2194 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
2195
2196 static void init_proc_401x2 (CPUPPCState *env)
2197 {
2198 gen_spr_40x(env);
2199 gen_spr_401_403(env);
2200 gen_spr_401x2(env);
2201 gen_spr_compress(env);
2202 /* Bus access control */
2203 spr_register(env, SPR_40x_SGR, "SGR",
2204 SPR_NOACCESS, SPR_NOACCESS,
2205 &spr_read_generic, &spr_write_generic,
2206 0xFFFFFFFF);
2207 /* XXX : not implemented */
2208 spr_register(env, SPR_40x_DCWR, "DCWR",
2209 SPR_NOACCESS, SPR_NOACCESS,
2210 &spr_read_generic, &spr_write_generic,
2211 0x00000000);
2212 /* Memory management */
2213 env->nb_tlb = 64;
2214 env->nb_ways = 1;
2215 env->id_tlbs = 0;
2216 /* XXX: TODO: allocate internal IRQ controller */
2217 }
2218
2219 /* PowerPC 401x3 */
2220 #if defined(TODO)
2221 #define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | \
2222 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2223 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2224 PPC_CACHE_DCBA | PPC_MFTB | \
2225 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2226 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
2227 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
2228 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
2229 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
2230
2231 static void init_proc_401x2 (CPUPPCState *env)
2232 {
2233 }
2234 #endif /* TODO */
2235
2236 /* IOP480 */
2237 #define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | \
2238 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2239 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2240 PPC_CACHE_DCBA | \
2241 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2242 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
2243 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
2244 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
2245 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
2246
2247 static void init_proc_IOP480 (CPUPPCState *env)
2248 {
2249 gen_spr_40x(env);
2250 gen_spr_401_403(env);
2251 gen_spr_401x2(env);
2252 gen_spr_compress(env);
2253 /* Bus access control */
2254 spr_register(env, SPR_40x_SGR, "SGR",
2255 SPR_NOACCESS, SPR_NOACCESS,
2256 &spr_read_generic, &spr_write_generic,
2257 0xFFFFFFFF);
2258 /* XXX : not implemented */
2259 spr_register(env, SPR_40x_DCWR, "DCWR",
2260 SPR_NOACCESS, SPR_NOACCESS,
2261 &spr_read_generic, &spr_write_generic,
2262 0x00000000);
2263 /* Memory management */
2264 env->nb_tlb = 64;
2265 env->nb_ways = 1;
2266 env->id_tlbs = 0;
2267 /* XXX: TODO: allocate internal IRQ controller */
2268 }
2269
2270 /* PowerPC 403 */
2271 #define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | \
2272 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2273 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2274 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2275 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
2276 #define POWERPC_MMU_403 (POWERPC_MMU_REAL_4xx)
2277 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
2278 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
2279
2280 static void init_proc_403 (CPUPPCState *env)
2281 {
2282 gen_spr_40x(env);
2283 gen_spr_401_403(env);
2284 gen_spr_403(env);
2285 gen_spr_403_real(env);
2286 /* XXX: TODO: allocate internal IRQ controller */
2287 }
2288
2289 /* PowerPC 403 GCX */
2290 #define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | \
2291 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2292 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2293 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2294 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
2295 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
2296 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
2297 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
2298
2299 static void init_proc_403GCX (CPUPPCState *env)
2300 {
2301 gen_spr_40x(env);
2302 gen_spr_401_403(env);
2303 gen_spr_403(env);
2304 gen_spr_403_real(env);
2305 gen_spr_403_mmu(env);
2306 /* Bus access control */
2307 spr_register(env, SPR_40x_SGR, "SGR",
2308 SPR_NOACCESS, SPR_NOACCESS,
2309 &spr_read_generic, &spr_write_generic,
2310 0xFFFFFFFF);
2311 /* XXX : not implemented */
2312 spr_register(env, SPR_40x_DCWR, "DCWR",
2313 SPR_NOACCESS, SPR_NOACCESS,
2314 &spr_read_generic, &spr_write_generic,
2315 0x00000000);
2316 /* Memory management */
2317 env->nb_tlb = 64;
2318 env->nb_ways = 1;
2319 env->id_tlbs = 0;
2320 /* XXX: TODO: allocate internal IRQ controller */
2321 }
2322
2323 /* PowerPC 405 */
2324 #define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_MFTB | \
2325 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2326 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2327 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
2328 PPC_405_MAC)
2329 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
2330 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
2331 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
2332 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
2333
2334 static void init_proc_405 (CPUPPCState *env)
2335 {
2336 /* Time base */
2337 gen_tbl(env);
2338 gen_spr_40x(env);
2339 gen_spr_405(env);
2340 /* Bus access control */
2341 spr_register(env, SPR_40x_SGR, "SGR",
2342 SPR_NOACCESS, SPR_NOACCESS,
2343 &spr_read_generic, &spr_write_generic,
2344 0xFFFFFFFF);
2345 /* XXX : not implemented */
2346 spr_register(env, SPR_40x_DCWR, "DCWR",
2347 SPR_NOACCESS, SPR_NOACCESS,
2348 &spr_read_generic, &spr_write_generic,
2349 0x00000000);
2350 /* Memory management */
2351 env->nb_tlb = 64;
2352 env->nb_ways = 1;
2353 env->id_tlbs = 0;
2354 /* Allocate hardware IRQ controller */
2355 ppc405_irq_init(env);
2356 }
2357
2358 /* PowerPC 440 EP */
2359 #define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | \
2360 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2361 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2362 PPC_440_SPEC | PPC_RFMCI)
2363 #define POWERPC_MSRM_440EP (0x000000000006D630ULL)
2364 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
2365 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
2366 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
2367
2368 static void init_proc_440EP (CPUPPCState *env)
2369 {
2370 /* Time base */
2371 gen_tbl(env);
2372 gen_spr_BookE(env);
2373 gen_spr_440(env);
2374 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2375 SPR_NOACCESS, SPR_NOACCESS,
2376 &spr_read_generic, &spr_write_generic,
2377 0x00000000);
2378 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2379 SPR_NOACCESS, SPR_NOACCESS,
2380 &spr_read_generic, &spr_write_generic,
2381 0x00000000);
2382 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2383 SPR_NOACCESS, SPR_NOACCESS,
2384 &spr_read_generic, &spr_write_generic,
2385 0x00000000);
2386 spr_register(env, SPR_440_CCR1, "CCR1",
2387 SPR_NOACCESS, SPR_NOACCESS,
2388 &spr_read_generic, &spr_write_generic,
2389 0x00000000);
2390 /* Memory management */
2391 env->nb_tlb = 64;
2392 env->nb_ways = 1;
2393 env->id_tlbs = 0;
2394 /* XXX: TODO: allocate internal IRQ controller */
2395 }
2396
2397 /* PowerPC 440 GP */
2398 #define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | \
2399 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2400 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2401 PPC_405_MAC | PPC_440_SPEC)
2402 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
2403 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
2404 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
2405 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
2406
2407 static void init_proc_440GP (CPUPPCState *env)
2408 {
2409 /* Time base */
2410 gen_tbl(env);
2411 gen_spr_BookE(env);
2412 gen_spr_440(env);
2413 /* Memory management */
2414 env->nb_tlb = 64;
2415 env->nb_ways = 1;
2416 env->id_tlbs = 0;
2417 /* XXX: TODO: allocate internal IRQ controller */
2418 }
2419
2420 /* PowerPC 440x4 */
2421 #if defined(TODO)
2422 #define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | \
2423 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2424 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2425 PPC_440_SPEC)
2426 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
2427 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
2428 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
2429 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
2430
2431 static void init_proc_440x4 (CPUPPCState *env)
2432 {
2433 /* Time base */
2434 gen_tbl(env);
2435 gen_spr_BookE(env);
2436 gen_spr_440(env);
2437 /* Memory management */
2438 env->nb_tlb = 64;
2439 env->nb_ways = 1;
2440 env->id_tlbs = 0;
2441 /* XXX: TODO: allocate internal IRQ controller */
2442 }
2443 #endif /* TODO */
2444
2445 /* PowerPC 440x5 */
2446 #define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | \
2447 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2448 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2449 PPC_440_SPEC | PPC_RFMCI)
2450 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
2451 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
2452 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
2453 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
2454
2455 static void init_proc_440x5 (CPUPPCState *env)
2456 {
2457 /* Time base */
2458 gen_tbl(env);
2459 gen_spr_BookE(env);
2460 gen_spr_440(env);
2461 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2462 SPR_NOACCESS, SPR_NOACCESS,
2463 &spr_read_generic, &spr_write_generic,
2464 0x00000000);
2465 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2466 SPR_NOACCESS, SPR_NOACCESS,
2467 &spr_read_generic, &spr_write_generic,
2468 0x00000000);
2469 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2470 SPR_NOACCESS, SPR_NOACCESS,
2471 &spr_read_generic, &spr_write_generic,
2472 0x00000000);
2473 spr_register(env, SPR_440_CCR1, "CCR1",
2474 SPR_NOACCESS, SPR_NOACCESS,
2475 &spr_read_generic, &spr_write_generic,
2476 0x00000000);
2477 /* Memory management */
2478 env->nb_tlb = 64;
2479 env->nb_ways = 1;
2480 env->id_tlbs = 0;
2481 /* XXX: TODO: allocate internal IRQ controller */
2482 }
2483
2484 /* PowerPC 460 (guessed) */
2485 #if defined(TODO)
2486 #define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
2487 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2488 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2489 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
2490 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
2491 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
2492 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
2493 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
2494
2495 static void init_proc_460 (CPUPPCState *env)
2496 {
2497 }
2498 #endif /* TODO */
2499
2500 /* PowerPC 460F (guessed) */
2501 #if defined(TODO)
2502 #define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
2503 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2504 PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
2505 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
2506 PPC_FLOAT_STFIWX | \
2507 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2508 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
2509 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
2510 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
2511 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
2512 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
2513
2514 static void init_proc_460 (CPUPPCState *env)
2515 {
2516 /* Time base */
2517 gen_tbl(env);
2518 gen_spr_BookE(env);
2519 gen_spr_440(env);
2520 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2521 SPR_NOACCESS, SPR_NOACCESS,
2522 &spr_read_generic, &spr_write_generic,
2523 0x00000000);
2524 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2525 SPR_NOACCESS, SPR_NOACCESS,
2526 &spr_read_generic, &spr_write_generic,
2527 0x00000000);
2528 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2529 SPR_NOACCESS, SPR_NOACCESS,
2530 &spr_read_generic, &spr_write_generic,
2531 0x00000000);
2532 spr_register(env, SPR_440_CCR1, "CCR1",
2533 SPR_NOACCESS, SPR_NOACCESS,
2534 &spr_read_generic, &spr_write_generic,
2535 0x00000000);
2536 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
2537 &spr_read_generic, &spr_write_generic,
2538 &spr_read_generic, &spr_write_generic,
2539 0x00000000);
2540 /* Memory management */
2541 env->nb_tlb = 64;
2542 env->nb_ways = 1;
2543 env->id_tlbs = 0;
2544 /* XXX: TODO: allocate internal IRQ controller */
2545 }
2546 #endif /* TODO */
2547
2548 /* Generic BookE PowerPC */
2549 #if defined(TODO)
2550 #define POWERPC_INSNS_BookE (POWERPC_INSNS_EMB | \
2551 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
2552 PPC_CACHE_DCBA | \
2553 PPC_FLOAT | PPC_FLOAT_FSQRT | \
2554 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
2555 PPC_FLOAT_FSEL | PPC_FLOAT_STFIW | \
2556 PPC_BOOKE)
2557 #define POWERPC_MSRM_BookE (0x000000000006D630ULL)
2558 #define POWERPC_MMU_BookE (POWERPC_MMU_BOOKE)
2559 #define POWERPC_EXCP_BookE (POWERPC_EXCP_BOOKE)
2560 #define POWERPC_INPUT_BookE (PPC_FLAGS_INPUT_BookE)
2561
2562 static void init_proc_BookE (CPUPPCState *env)
2563 {
2564 }
2565 #endif /* TODO */
2566
2567 /* e200 core */
2568 #if defined(TODO)
2569 #endif /* TODO */
2570
2571 /* e300 core */
2572 #if defined(TODO)
2573 #endif /* TODO */
2574
2575 /* e500 core */
2576 #if defined(TODO)
2577 #define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | \
2578 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
2579 PPC_CACHE_DCBA | \
2580 PPC_BOOKE | PPC_E500_VECTOR)
2581 #define POWERPC_MMU_e500 (POWERPC_MMU_SOFT_4xx)
2582 #define POWERPC_EXCP_e500 (POWERPC_EXCP_40x)
2583 #define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
2584
2585 static void init_proc_e500 (CPUPPCState *env)
2586 {
2587 /* Time base */
2588 gen_tbl(env);
2589 gen_spr_BookE(env);
2590 /* Memory management */
2591 gen_spr_BookE_FSL(env);
2592 env->nb_tlb = 64;
2593 env->nb_ways = 1;
2594 env->id_tlbs = 0;
2595 /* XXX: TODO: allocate internal IRQ controller */
2596 }
2597 #endif /* TODO */
2598
2599 /* e600 core */
2600 #if defined(TODO)
2601 #endif /* TODO */
2602
2603 /* Non-embedded PowerPC */
2604 /* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
2605 #define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
2606 PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
2607 /* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */
2608 #define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
2609 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
2610 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
2611 PPC_MEM_TLBSYNC | PPC_MFTB)
2612
2613 /* POWER : same as 601, without mfmsr, mfsr */
2614 #if defined(TODO)
2615 #define POWERPC_INSNS_POWER (XXX_TODO)
2616 /* POWER RSC (from RAD6000) */
2617 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
2618 #endif /* TODO */
2619
2620 /* PowerPC 601 */
2621 #define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_EXTERN | PPC_POWER_BR)
2622 #define POWERPC_MSRM_601 (0x000000000000FE70ULL)
2623 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
2624 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
2625 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
2626
2627 static void init_proc_601 (CPUPPCState *env)
2628 {
2629 gen_spr_ne_601(env);
2630 gen_spr_601(env);
2631 /* Hardware implementation registers */
2632 /* XXX : not implemented */
2633 spr_register(env, SPR_HID0, "HID0",
2634 SPR_NOACCESS, SPR_NOACCESS,
2635 &spr_read_generic, &spr_write_generic,
2636 0x00000000);
2637 /* XXX : not implemented */
2638 spr_register(env, SPR_HID1, "HID1",
2639 SPR_NOACCESS, SPR_NOACCESS,
2640 &spr_read_generic, &spr_write_generic,
2641 0x00000000);
2642 /* XXX : not implemented */
2643 spr_register(env, SPR_601_HID2, "HID2",
2644 SPR_NOACCESS, SPR_NOACCESS,
2645 &spr_read_generic, &spr_write_generic,
2646 0x00000000);
2647 /* XXX : not implemented */
2648 spr_register(env, SPR_601_HID5, "HID5",
2649 SPR_NOACCESS, SPR_NOACCESS,
2650 &spr_read_generic, &spr_write_generic,
2651 0x00000000);
2652 /* XXX : not implemented */
2653 spr_register(env, SPR_601_HID15, "HID15",
2654 SPR_NOACCESS, SPR_NOACCESS,
2655 &spr_read_generic, &spr_write_generic,
2656 0x00000000);
2657 /* Memory management */
2658 env->nb_tlb = 64;
2659 env->nb_ways = 2;
2660 env->id_tlbs = 0;
2661 env->id_tlbs = 0;
2662 /* XXX: TODO: allocate internal IRQ controller */
2663 }
2664
2665 /* PowerPC 602 */
2666 #define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \
2667 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
2668 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
2669 PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_602_SPEC)
2670 #define POWERPC_MSRM_602 (0x000000000033FF73ULL)
2671 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
2672 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
2673 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
2674
2675 static void init_proc_602 (CPUPPCState *env)
2676 {
2677 gen_spr_ne_601(env);
2678 gen_spr_602(env);
2679 /* Time base */
2680 gen_tbl(env);
2681 /* hardware implementation registers */
2682 /* XXX : not implemented */
2683 spr_register(env, SPR_HID0, "HID0",
2684 SPR_NOACCESS, SPR_NOACCESS,
2685 &spr_read_generic, &spr_write_generic,
2686 0x00000000);
2687 /* XXX : not implemented */
2688 spr_register(env, SPR_HID1, "HID1",
2689 SPR_NOACCESS, SPR_NOACCESS,
2690 &spr_read_generic, &spr_write_generic,
2691 0x00000000);
2692 /* Memory management */
2693 gen_low_BATs(env);
2694 gen_6xx_7xx_soft_tlb(env, 64, 2);
2695 /* Allocate hardware IRQ controller */
2696 ppc6xx_irq_init(env);
2697 }
2698
2699 /* PowerPC 603 */
2700 #define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
2701 #define POWERPC_MSRM_603 (0x000000000001FF73ULL)
2702 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
2703 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
2704 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
2705
2706 static void init_proc_603 (CPUPPCState *env)
2707 {
2708 gen_spr_ne_601(env);
2709 gen_spr_603(env);
2710 /* Time base */
2711 gen_tbl(env);
2712 /* hardware implementation registers */
2713 /* XXX : not implemented */
2714 spr_register(env, SPR_HID0, "HID0",
2715 SPR_NOACCESS, SPR_NOACCESS,
2716 &spr_read_generic, &spr_write_generic,
2717 0x00000000);
2718 /* XXX : not implemented */
2719 spr_register(env, SPR_HID1, "HID1",
2720 SPR_NOACCESS, SPR_NOACCESS,
2721 &spr_read_generic, &spr_write_generic,
2722 0x00000000);
2723 /* Memory management */
2724 gen_low_BATs(env);
2725 gen_6xx_7xx_soft_tlb(env, 64, 2);
2726 /* Allocate hardware IRQ controller */
2727 ppc6xx_irq_init(env);
2728 }
2729
2730 /* PowerPC 603e */
2731 #define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
2732 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
2733 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
2734 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
2735 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
2736
2737 static void init_proc_603E (CPUPPCState *env)
2738 {
2739 gen_spr_ne_601(env);
2740 gen_spr_603(env);
2741 /* Time base */
2742 gen_tbl(env);
2743 /* hardware implementation registers */
2744 /* XXX : not implemented */
2745 spr_register(env, SPR_HID0, "HID0",
2746 SPR_NOACCESS, SPR_NOACCESS,
2747 &spr_read_generic, &spr_write_generic,
2748 0x00000000);
2749 /* XXX : not implemented */
2750 spr_register(env, SPR_HID1, "HID1",
2751 SPR_NOACCESS, SPR_NOACCESS,
2752 &spr_read_generic, &spr_write_generic,
2753 0x00000000);
2754 /* XXX : not implemented */
2755 spr_register(env, SPR_IABR, "IABR",
2756 SPR_NOACCESS, SPR_NOACCESS,
2757 &spr_read_generic, &spr_write_generic,
2758 0x00000000);
2759 /* Memory management */
2760 gen_low_BATs(env);
2761 gen_6xx_7xx_soft_tlb(env, 64, 2);
2762 /* Allocate hardware IRQ controller */
2763 ppc6xx_irq_init(env);
2764 }
2765
2766 /* PowerPC G2 */
2767 #define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
2768 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
2769 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
2770 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
2771 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
2772
2773 static void init_proc_G2 (CPUPPCState *env)
2774 {
2775 gen_spr_ne_601(env);
2776 gen_spr_G2_755(env);
2777 gen_spr_G2(env);
2778 /* Time base */
2779 gen_tbl(env);
2780 /* Hardware implementation register */
2781 /* XXX : not implemented */
2782 spr_register(env, SPR_HID0, "HID0",
2783 SPR_NOACCESS, SPR_NOACCESS,
2784 &spr_read_generic, &spr_write_generic,
2785 0x00000000);
2786 /* XXX : not implemented */
2787 spr_register(env, SPR_HID1, "HID1",
2788 SPR_NOACCESS, SPR_NOACCESS,
2789 &spr_read_generic, &spr_write_generic,
2790 0x00000000);
2791 /* XXX : not implemented */
2792 spr_register(env, SPR_HID2, "HID2",
2793 SPR_NOACCESS, SPR_NOACCESS,
2794 &spr_read_generic, &spr_write_generic,
2795 0x00000000);
2796 /* Memory management */
2797 gen_low_BATs(env);
2798 gen_high_BATs(env);
2799 gen_6xx_7xx_soft_tlb(env, 64, 2);
2800 /* Allocate hardware IRQ controller */
2801 ppc6xx_irq_init(env);
2802 }
2803
2804 /* PowerPC G2LE */
2805 #define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
2806 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
2807 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
2808 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
2809 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
2810
2811 static void init_proc_G2LE (CPUPPCState *env)
2812 {
2813 gen_spr_ne_601(env);
2814 gen_spr_G2_755(env);
2815 gen_spr_G2(env);
2816 /* Time base */
2817 gen_tbl(env);
2818 /* Hardware implementation register */
2819 /* XXX : not implemented */
2820 spr_register(env, SPR_HID0, "HID0",
2821 SPR_NOACCESS, SPR_NOACCESS,
2822 &spr_read_generic, &spr_write_generic,
2823 0x00000000);
2824 /* XXX : not implemented */
2825 spr_register(env, SPR_HID1, "HID1",
2826 SPR_NOACCESS, SPR_NOACCESS,
2827 &spr_read_generic, &spr_write_generic,
2828 0x00000000);
2829 /* XXX : not implemented */
2830 spr_register(env, SPR_HID2, "HID2",
2831 SPR_NOACCESS, SPR_NOACCESS,
2832 &spr_read_generic, &spr_write_generic,
2833 0x00000000);
2834 /* Memory management */
2835 gen_low_BATs(env);
2836 gen_high_BATs(env);
2837 gen_6xx_7xx_soft_tlb(env, 64, 2);
2838 /* Allocate hardware IRQ controller */
2839 ppc6xx_irq_init(env);
2840 }
2841
2842 /* PowerPC 604 */
2843 #define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN)
2844 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
2845 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
2846 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
2847 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
2848
2849 static void init_proc_604 (CPUPPCState *env)
2850 {
2851 gen_spr_ne_601(env);
2852 gen_spr_604(env);
2853 /* Time base */
2854 gen_tbl(env);
2855 /* Hardware implementation registers */
2856 /* XXX : not implemented */
2857 spr_register(env, SPR_HID0, "HID0",
2858 SPR_NOACCESS, SPR_NOACCESS,
2859 &spr_read_generic, &spr_write_generic,
2860 0x00000000);
2861 /* XXX : not implemented */
2862 spr_register(env, SPR_HID1, "HID1",
2863 SPR_NOACCESS, SPR_NOACCESS,
2864 &spr_read_generic, &spr_write_generic,
2865 0x00000000);
2866 /* Memory management */
2867 gen_low_BATs(env);
2868 /* Allocate hardware IRQ controller */
2869 ppc6xx_irq_init(env);
2870 }
2871
2872 /* PowerPC 740/750 (aka G3) */
2873 #define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN)
2874 #define POWERPC_MSRM_7x0 (0x000000000007FF77ULL)
2875 #define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
2876 //#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
2877 #define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)
2878
2879 static void init_proc_7x0 (CPUPPCState *env)
2880 {
2881 gen_spr_ne_601(env);
2882 gen_spr_7xx(env);
2883 /* Time base */
2884 gen_tbl(env);
2885 /* Thermal management */
2886 gen_spr_thrm(env);
2887 /* Hardware implementation registers */
2888 /* XXX : not implemented */
2889 spr_register(env, SPR_HID0, "HID0",
2890 SPR_NOACCESS, SPR_NOACCESS,
2891 &spr_read_generic, &spr_write_generic,
2892 0x00000000);
2893 /* XXX : not implemented */
2894 spr_register(env, SPR_HID1, "HID1",
2895 SPR_NOACCESS, SPR_NOACCESS,
2896 &spr_read_generic, &spr_write_generic,
2897 0x00000000);
2898 /* Memory management */
2899 gen_low_BATs(env);
2900 /* Allocate hardware IRQ controller */
2901 ppc6xx_irq_init(env);
2902 }
2903
2904 /* PowerPC 750FX/GX */
2905 #define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN)
2906 #define POWERPC_MSRM_750fx (0x000000000007FF77ULL)
2907 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
2908 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
2909 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
2910
2911 static void init_proc_750fx (CPUPPCState *env)
2912 {
2913 gen_spr_ne_601(env);
2914 gen_spr_7xx(env);
2915 /* Time base */
2916 gen_tbl(env);
2917 /* Thermal management */
2918 gen_spr_thrm(env);
2919 /* Hardware implementation registers */
2920 /* XXX : not implemented */
2921 spr_register(env, SPR_HID0, "HID0",
2922 SPR_NOACCESS, SPR_NOACCESS,
2923 &spr_read_generic, &spr_write_generic,
2924 0x00000000);
2925 /* XXX : not implemented */
2926 spr_register(env, SPR_HID1, "HID1",
2927 SPR_NOACCESS, SPR_NOACCESS,
2928 &spr_read_generic, &spr_write_generic,
2929 0x00000000);
2930 /* XXX : not implemented */
2931 spr_register(env, SPR_750_HID2, "HID2",
2932 SPR_NOACCESS, SPR_NOACCESS,
2933 &spr_read_generic, &spr_write_generic,
2934 0x00000000);
2935 /* Memory management */
2936 gen_low_BATs(env);
2937 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
2938 gen_high_BATs(env);
2939 /* Allocate hardware IRQ controller */
2940 ppc6xx_irq_init(env);
2941 }
2942
2943 /* PowerPC 745/755 */
2944 #define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
2945 #define POWERPC_MSRM_7x5 (0x000000000007FF77ULL)
2946 #define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
2947 //#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
2948 #define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)
2949
2950 static void init_proc_7x5 (CPUPPCState *env)
2951 {
2952 gen_spr_ne_601(env);
2953 gen_spr_G2_755(env);
2954 /* Time base */
2955 gen_tbl(env);
2956 /* L2 cache control */
2957 /* XXX : not implemented */
2958 spr_register(env, SPR_ICTC, "ICTC",
2959 SPR_NOACCESS, SPR_NOACCESS,
2960 &spr_read_generic, &spr_write_generic,
2961 0x00000000);
2962 /* XXX : not implemented */
2963 spr_register(env, SPR_L2PMCR, "L2PMCR",
2964 SPR_NOACCESS, SPR_NOACCESS,
2965 &spr_read_generic, &spr_write_generic,
2966 0x00000000);
2967 /* Hardware implementation registers */
2968 /* XXX : not implemented */
2969 spr_register(env, SPR_HID0, "HID0",
2970 SPR_NOACCESS, SPR_NOACCESS,
2971 &spr_read_generic, &spr_write_generic,
2972 0x00000000);
2973 /* XXX : not implemented */
2974 spr_register(env, SPR_HID1, "HID1",
2975 SPR_NOACCESS, SPR_NOACCESS,
2976 &spr_read_generic, &spr_write_generic,
2977 0x00000000);
2978 /* XXX : not implemented */
2979 spr_register(env, SPR_HID2, "HID2",
2980 SPR_NOACCESS, SPR_NOACCESS,
2981 &spr_read_generic, &spr_write_generic,
2982 0x00000000);
2983 /* Memory management */
2984 gen_low_BATs(env);
2985 gen_high_BATs(env);
2986 gen_6xx_7xx_soft_tlb(env, 64, 2);
2987 /* Allocate hardware IRQ controller */
2988 ppc6xx_irq_init(env);
2989 }
2990
2991 /* PowerPC 7400 (aka G4) */
2992 #define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
2993 PPC_EXTERN | PPC_MEM_TLBIA | \
2994 PPC_ALTIVEC)
2995 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
2996 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
2997 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
2998 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
2999
3000 static void init_proc_7400 (CPUPPCState *env)
3001 {
3002 gen_spr_ne_601(env);
3003 gen_spr_7xx(env);
3004 /* Time base */
3005 gen_tbl(env);
3006 /* 74xx specific SPR */
3007 gen_spr_74xx(env);
3008 /* Thermal management */
3009 gen_spr_thrm(env);
3010 /* Memory management */
3011 gen_low_BATs(env);
3012 /* Allocate hardware IRQ controller */
3013 ppc6xx_irq_init(env);
3014 }
3015
3016 /* PowerPC 7410 (aka G4) */
3017 #define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3018 PPC_EXTERN | PPC_MEM_TLBIA | \
3019 PPC_ALTIVEC)
3020 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
3021 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
3022 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
3023 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
3024
3025 static void init_proc_7410 (CPUPPCState *env)
3026 {
3027 gen_spr_ne_601(env);
3028 gen_spr_7xx(env);
3029 /* Time base */
3030 gen_tbl(env);
3031 /* 74xx specific SPR */
3032 gen_spr_74xx(env);
3033 /* Thermal management */
3034 gen_spr_thrm(env);
3035 /* L2PMCR */
3036 /* XXX : not implemented */
3037 spr_register(env, SPR_L2PMCR, "L2PMCR",
3038 SPR_NOACCESS, SPR_NOACCESS,
3039 &spr_read_generic, &spr_write_generic,
3040 0x00000000);
3041 /* LDSTDB */
3042 /* XXX : not implemented */
3043 spr_register(env, SPR_LDSTDB, "LDSTDB",
3044 SPR_NOACCESS, SPR_NOACCESS,
3045 &spr_read_generic, &spr_write_generic,
3046 0x00000000);
3047 /* Memory management */
3048 gen_low_BATs(env);
3049 /* Allocate hardware IRQ controller */
3050 ppc6xx_irq_init(env);
3051 }
3052
3053 /* PowerPC 7440 (aka G4) */
3054 #if defined (TODO)
3055 #define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3056 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3057 PPC_ALTIVEC)
3058 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
3059 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
3060 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
3061 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
3062
3063 static void init_proc_7440 (CPUPPCState *env)
3064 {
3065 gen_spr_ne_601(env);
3066 gen_spr_7xx(env);
3067 /* Time base */
3068 gen_tbl(env);
3069 /* 74xx specific SPR */
3070 gen_spr_74xx(env);
3071 /* LDSTCR */
3072 /* XXX : not implemented */
3073 spr_register(env, SPR_LDSTCR, "LDSTCR",
3074 SPR_NOACCESS, SPR_NOACCESS,
3075 &spr_read_generic, &spr_write_generic,
3076 0x00000000);
3077 /* ICTRL */
3078 /* XXX : not implemented */
3079 spr_register(env, SPR_ICTRL, "ICTRL",
3080 SPR_NOACCESS, SPR_NOACCESS,
3081 &spr_read_generic, &spr_write_generic,
3082 0x00000000);
3083 /* MSSSR0 */
3084 spr_register(env, SPR_MSSSR0, "MSSSR0",
3085 SPR_NOACCESS, SPR_NOACCESS,
3086 &spr_read_generic, &spr_write_generic,
3087 0x00000000);
3088 /* PMC */
3089 /* XXX : not implemented */
3090 spr_register(env, SPR_PMC5, "PMC5",
3091 SPR_NOACCESS, SPR_NOACCESS,
3092 &spr_read_generic, &spr_write_generic,
3093 0x00000000);
3094 spr_register(env, SPR_UPMC5, "UPMC5",
3095 &spr_read_ureg, SPR_NOACCESS,
3096 &spr_read_ureg, SPR_NOACCESS,
3097 0x00000000);
3098 spr_register(env, SPR_PMC6, "PMC6",
3099 SPR_NOACCESS, SPR_NOACCESS,
3100 &spr_read_generic, &spr_write_generic,
3101 0x00000000);
3102 spr_register(env, SPR_UPMC6, "UPMC6",
3103 &spr_read_ureg, SPR_NOACCESS,
3104 &spr_read_ureg, SPR_NOACCESS,
3105 0x00000000);
3106 /* Memory management */
3107 gen_low_BATs(env);
3108 gen_74xx_soft_tlb(env);
3109 /* Allocate hardware IRQ controller */
3110 ppc6xx_irq_init(env);
3111 }
3112 #endif /* TODO */
3113
3114 /* PowerPC 7450 (aka G4) */
3115 #if defined (TODO)
3116 #define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3117 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3118 PPC_ALTIVEC)
3119 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
3120 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
3121 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
3122 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
3123
3124 static void init_proc_7450 (CPUPPCState *env)
3125 {
3126 gen_spr_ne_601(env);
3127 gen_spr_7xx(env);
3128 /* Time base */
3129 gen_tbl(env);
3130 /* 74xx specific SPR */
3131 gen_spr_74xx(env);
3132 /* Level 3 cache control */
3133 gen_l3_ctrl(env);
3134 /* LDSTCR */
3135 /* XXX : not implemented */
3136 spr_register(env, SPR_LDSTCR, "LDSTCR",
3137 SPR_NOACCESS, SPR_NOACCESS,
3138 &spr_read_generic, &spr_write_generic,
3139 0x00000000);
3140 /* ICTRL */
3141 /* XXX : not implemented */
3142 spr_register(env, SPR_ICTRL, "ICTRL",
3143 SPR_NOACCESS, SPR_NOACCESS,
3144 &spr_read_generic, &spr_write_generic,
3145 0x00000000);
3146 /* MSSSR0 */
3147 spr_register(env, SPR_MSSSR0, "MSSSR0",
3148 SPR_NOACCESS, SPR_NOACCESS,
3149 &spr_read_generic, &spr_write_generic,
3150 0x00000000);
3151 /* PMC */
3152 /* XXX : not implemented */
3153 spr_register(env, SPR_PMC5, "PMC5",
3154 SPR_NOACCESS, SPR_NOACCESS,
3155 &spr_read_generic, &spr_write_generic,
3156 0x00000000);
3157 spr_register(env, SPR_UPMC5, "UPMC5",
3158 &spr_read_ureg, SPR_NOACCESS,
3159 &spr_read_ureg, SPR_NOACCESS,
3160 0x00000000);
3161 spr_register(env, SPR_PMC6, "PMC6",
3162 SPR_NOACCESS, SPR_NOACCESS,
3163 &spr_read_generic, &spr_write_generic,
3164 0x00000000);
3165 spr_register(env, SPR_UPMC6, "UPMC6",
3166 &spr_read_ureg, SPR_NOACCESS,
3167 &spr_read_ureg, SPR_NOACCESS,
3168 0x00000000);
3169 /* Memory management */
3170 gen_low_BATs(env);
3171 gen_74xx_soft_tlb(env);
3172 /* Allocate hardware IRQ controller */
3173 ppc6xx_irq_init(env);
3174 }
3175 #endif /* TODO */
3176
3177 /* PowerPC 7445 (aka G4) */
3178 #if defined (TODO)
3179 #define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3180 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3181 PPC_ALTIVEC)
3182 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
3183 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
3184 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
3185 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
3186
3187 static void init_proc_7445 (CPUPPCState *env)
3188 {
3189 gen_spr_ne_601(env);
3190 gen_spr_7xx(env);
3191 /* Time base */
3192 gen_tbl(env);
3193 /* 74xx specific SPR */
3194 gen_spr_74xx(env);
3195 /* LDSTCR */
3196 /* XXX : not implemented */
3197 spr_register(env, SPR_LDSTCR, "LDSTCR",
3198 SPR_NOACCESS, SPR_NOACCESS,
3199 &spr_read_generic, &spr_write_generic,
3200 0x00000000);
3201 /* ICTRL */
3202 /* XXX : not implemented */
3203 spr_register(env, SPR_ICTRL, "ICTRL",
3204 SPR_NOACCESS, SPR_NOACCESS,
3205 &spr_read_generic, &spr_write_generic,
3206 0x00000000);
3207 /* MSSSR0 */
3208 spr_register(env, SPR_MSSSR0, "MSSSR0",
3209 SPR_NOACCESS, SPR_NOACCESS,
3210 &spr_read_generic, &spr_write_generic,
3211 0x00000000);
3212 /* PMC */
3213 /* XXX : not implemented */
3214 spr_register(env, SPR_PMC5, "PMC5",
3215 SPR_NOACCESS, SPR_NOACCESS,
3216 &spr_read_generic, &spr_write_generic,
3217 0x00000000);
3218 spr_register(env, SPR_UPMC5, "UPMC5",
3219 &spr_read_ureg, SPR_NOACCESS,
3220 &spr_read_ureg, SPR_NOACCESS,
3221 0x00000000);
3222 spr_register(env, SPR_PMC6, "PMC6",
3223 SPR_NOACCESS, SPR_NOACCESS,
3224 &spr_read_generic, &spr_write_generic,
3225 0x00000000);
3226 spr_register(env, SPR_UPMC6, "UPMC6",
3227 &spr_read_ureg, SPR_NOACCESS,
3228 &spr_read_ureg, SPR_NOACCESS,
3229 0x00000000);
3230 /* SPRGs */
3231 spr_register(env, SPR_SPRG4, "SPRG4",
3232 SPR_NOACCESS, SPR_NOACCESS,
3233 &spr_read_generic, &spr_write_generic,
3234 0x00000000);
3235 spr_register(env, SPR_USPRG4, "USPRG4",
3236 &spr_read_ureg, SPR_NOACCESS,
3237 &spr_read_ureg, SPR_NOACCESS,
3238 0x00000000);
3239 spr_register(env, SPR_SPRG5, "SPRG5",
3240 SPR_NOACCESS, SPR_NOACCESS,
3241 &spr_read_generic, &spr_write_generic,
3242 0x00000000);
3243 spr_register(env, SPR_USPRG5, "USPRG5",
3244 &spr_read_ureg, SPR_NOACCESS,
3245 &spr_read_ureg, SPR_NOACCESS,
3246 0x00000000);
3247 spr_register(env, SPR_SPRG6, "SPRG6",
3248 SPR_NOACCESS, SPR_NOACCESS,
3249 &spr_read_generic, &spr_write_generic,
3250 0x00000000);
3251 spr_register(env, SPR_USPRG6, "USPRG6",
3252 &spr_read_ureg, SPR_NOACCESS,
3253 &spr_read_ureg, SPR_NOACCESS,
3254 0x00000000);
3255 spr_register(env, SPR_SPRG7, "SPRG7",
3256 SPR_NOACCESS, SPR_NOACCESS,
3257 &spr_read_generic, &spr_write_generic,
3258 0x00000000);
3259 spr_register(env, SPR_USPRG7, "USPRG7",
3260 &spr_read_ureg, SPR_NOACCESS,
3261 &spr_read_ureg, SPR_NOACCESS,
3262 0x00000000);
3263 /* Memory management */
3264 gen_low_BATs(env);
3265 gen_high_BATs(env);
3266 gen_74xx_soft_tlb(env);
3267 /* Allocate hardware IRQ controller */
3268 ppc6xx_irq_init(env);
3269 }
3270 #endif /* TODO */
3271
3272 /* PowerPC 7455 (aka G4) */
3273 #if defined (TODO)
3274 #define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3275 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3276 PPC_ALTIVEC)
3277 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
3278 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
3279 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
3280 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
3281
3282 static void init_proc_7455 (CPUPPCState *env)
3283 {
3284 gen_spr_ne_601(env);
3285 gen_spr_7xx(env);
3286 /* Time base */
3287 gen_tbl(env);
3288 /* 74xx specific SPR */
3289 gen_spr_74xx(env);
3290 /* Level 3 cache control */
3291 gen_l3_ctrl(env);
3292 /* LDSTCR */
3293 /* XXX : not implemented */
3294 spr_register(env, SPR_LDSTCR, "LDSTCR",
3295 SPR_NOACCESS, SPR_NOACCESS,
3296 &spr_read_generic, &spr_write_generic,
3297 0x00000000);
3298 /* ICTRL */
3299 /* XXX : not implemented */
3300 spr_register(env, SPR_ICTRL, "ICTRL",
3301 SPR_NOACCESS, SPR_NOACCESS,
3302 &spr_read_generic, &spr_write_generic,
3303 0x00000000);
3304 /* MSSSR0 */
3305 spr_register(env, SPR_MSSSR0, "MSSSR0",
3306 SPR_NOACCESS, SPR_NOACCESS,
3307 &spr_read_generic, &spr_write_generic,
3308 0x00000000);
3309 /* PMC */
3310 /* XXX : not implemented */
3311 spr_register(env, SPR_PMC5, "PMC5",
3312 SPR_NOACCESS, SPR_NOACCESS,
3313 &spr_read_generic, &spr_write_generic,
3314 0x00000000);
3315 spr_register(env, SPR_UPMC5, "UPMC5",
3316 &spr_read_ureg, SPR_NOACCESS,
3317 &spr_read_ureg, SPR_NOACCESS,
3318 0x00000000);
3319 spr_register(env, SPR_PMC6, "PMC6",
3320 SPR_NOACCESS, SPR_NOACCESS,
3321 &spr_read_generic, &spr_write_generic,
3322 0x00000000);
3323 spr_register(env, SPR_UPMC6, "UPMC6",
3324 &spr_read_ureg, SPR_NOACCESS,
3325 &spr_read_ureg, SPR_NOACCESS,
3326 0x00000000);
3327 /* SPRGs */
3328 spr_register(env, SPR_SPRG4, "SPRG4",
3329 SPR_NOACCESS, SPR_NOACCESS,
3330 &spr_read_generic, &spr_write_generic,
3331 0x00000000);
3332 spr_register(env, SPR_USPRG4, "USPRG4",
3333 &spr_read_ureg, SPR_NOACCESS,
3334 &spr_read_ureg, SPR_NOACCESS,
3335 0x00000000);
3336 spr_register(env, SPR_SPRG5, "SPRG5",
3337 SPR_NOACCESS, SPR_NOACCESS,
3338 &spr_read_generic, &spr_write_generic,
3339 0x00000000);
3340 spr_register(env, SPR_USPRG5, "USPRG5",
3341 &spr_read_ureg, SPR_NOACCESS,
3342 &spr_read_ureg, SPR_NOACCESS,
3343 0x00000000);
3344 spr_register(env, SPR_SPRG6, "SPRG6",
3345 SPR_NOACCESS, SPR_NOACCESS,
3346 &spr_read_generic, &spr_write_generic,
3347 0x00000000);
3348 spr_register(env, SPR_USPRG6, "USPRG6",
3349 &spr_read_ureg, SPR_NOACCESS,
3350 &spr_read_ureg, SPR_NOACCESS,
3351 0x00000000);
3352 spr_register(env, SPR_SPRG7, "SPRG7",
3353 SPR_NOACCESS, SPR_NOACCESS,
3354 &spr_read_generic, &spr_write_generic,
3355 0x00000000);
3356 spr_register(env, SPR_USPRG7, "USPRG7",
3357 &spr_read_ureg, SPR_NOACCESS,
3358 &spr_read_ureg, SPR_NOACCESS,
3359 0x00000000);
3360 /* Memory management */
3361 gen_low_BATs(env);
3362 gen_high_BATs(env);
3363 gen_74xx_soft_tlb(env);
3364 /* Allocate hardware IRQ controller */
3365 ppc6xx_irq_init(env);
3366 }
3367 #endif /* TODO */
3368
3369 #if defined (TARGET_PPC64)
3370 /* PowerPC 970 */
3371 #define POWERPC_INSNS_970 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
3372 PPC_64B | PPC_ALTIVEC | \
3373 PPC_64_BRIDGE | PPC_SLBI)
3374 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
3375 #define POWERPC_MMU_970 (POWERPC_MMU_64BRIDGE)
3376 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
3377 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
3378
3379 static void init_proc_970 (CPUPPCState *env)
3380 {
3381 gen_spr_ne_601(env);
3382 gen_spr_7xx(env);
3383 /* Time base */
3384 gen_tbl(env);
3385 /* Hardware implementation registers */
3386 /* XXX : not implemented */
3387 spr_register(env, SPR_HID0, "HID0",
3388 SPR_NOACCESS, SPR_NOACCESS,
3389 &spr_read_generic, &spr_write_generic,
3390 0x00000000);
3391 /* XXX : not implemented */
3392 spr_register(env, SPR_HID1, "HID1",
3393 SPR_NOACCESS, SPR_NOACCESS,
3394 &spr_read_generic, &spr_write_generic,
3395 0x00000000);
3396 /* XXX : not implemented */
3397 spr_register(env, SPR_750_HID2, "HID2",
3398 SPR_NOACCESS, SPR_NOACCESS,
3399 &spr_read_generic, &spr_write_generic,
3400 0x00000000);
3401 /* Memory management */
3402 /* XXX: not correct */
3403 gen_low_BATs(env);
3404 #if 0 // TODO
3405 env->slb_nr = 32;
3406 #endif
3407 /* Allocate hardware IRQ controller */
3408 ppc970_irq_init(env);
3409 }
3410
3411 /* PowerPC 970FX (aka G5) */
3412 #define POWERPC_INSNS_970FX (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
3413 PPC_64B | PPC_ALTIVEC | \
3414 PPC_64_BRIDGE | PPC_SLBI)
3415 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
3416 #define POWERPC_MMU_970FX (POWERPC_MMU_64BRIDGE)
3417 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
3418 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
3419
3420 static void init_proc_970FX (CPUPPCState *env)
3421 {
3422 gen_spr_ne_601(env);
3423 gen_spr_7xx(env);
3424 /* Time base */
3425 gen_tbl(env);
3426 /* Hardware implementation registers */
3427 /* XXX : not implemented */
3428 spr_register(env, SPR_HID0, "HID0",
3429 SPR_NOACCESS, SPR_NOACCESS,
3430 &spr_read_generic, &spr_write_generic,
3431 0x00000000);
3432 /* XXX : not implemented */
3433 spr_register(env, SPR_HID1, "HID1",
3434 SPR_NOACCESS, SPR_NOACCESS,
3435 &spr_read_generic, &spr_write_generic,
3436 0x00000000);
3437 /* XXX : not implemented */
3438 spr_register(env, SPR_750_HID2, "HID2",
3439 SPR_NOACCESS, SPR_NOACCESS,
3440 &spr_read_generic, &spr_write_generic,
3441 0x00000000);
3442 /* Memory management */
3443 /* XXX: not correct */
3444 gen_low_BATs(env);
3445 #if 0 // TODO
3446 env->slb_nr = 32;
3447 #endif
3448 /* Allocate hardware IRQ controller */
3449 ppc970_irq_init(env);
3450 }
3451
3452 /* PowerPC 970 GX */
3453 #define POWERPC_INSNS_970GX (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
3454 PPC_64B | PPC_ALTIVEC | \
3455 PPC_64_BRIDGE | PPC_SLBI)
3456 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
3457 #define POWERPC_MMU_970GX (POWERPC_MMU_64BRIDGE)
3458 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
3459 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
3460
3461 static void init_proc_970GX (CPUPPCState *env)
3462 {
3463 gen_spr_ne_601(env);
3464 gen_spr_7xx(env);
3465 /* Time base */
3466 gen_tbl(env);
3467 /* Hardware implementation registers */
3468 /* XXX : not implemented */
3469 spr_register(env, SPR_HID0, "HID0",
3470 SPR_NOACCESS, SPR_NOACCESS,
3471 &spr_read_generic, &spr_write_generic,
3472 0x00000000);
3473 /* XXX : not implemented */
3474 spr_register(env, SPR_HID1, "HID1",
3475 SPR_NOACCESS, SPR_NOACCESS,
3476 &spr_read_generic, &spr_write_generic,
3477 0x00000000);
3478 /* XXX : not implemented */
3479 spr_register(env, SPR_750_HID2, "HID2",
3480 SPR_NOACCESS, SPR_NOACCESS,
3481 &spr_read_generic, &spr_write_generic,
3482 0x00000000);
3483 /* Memory management */
3484 /* XXX: not correct */
3485 gen_low_BATs(env);
3486 #if 0 // TODO
3487 env->slb_nr = 32;
3488 #endif
3489 /* Allocate hardware IRQ controller */
3490 ppc970_irq_init(env);
3491 }
3492
3493 /* PowerPC 620 */
3494 #if defined (TODO)
3495 #define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
3496 PPC_64B | PPC_SLBI)
3497 #define POWERPC_MSRM_620 (0x800000000005FF73ULL)
3498 #define POWERPC_MMU_620 (POWERPC_MMU_64B)
3499 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
3500 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_970)
3501
3502 static void init_proc_620 (CPUPPCState *env)
3503 {
3504 gen_spr_ne_601(env);
3505 gen_spr_620(env);
3506 /* Time base */
3507 gen_tbl(env);
3508 /* Hardware implementation registers */
3509 /* XXX : not implemented */
3510 spr_register(env, SPR_HID0, "HID0",
3511 SPR_NOACCESS, SPR_NOACCESS,
3512 &spr_read_generic, &spr_write_generic,
3513 0x00000000);
3514 /* Memory management */
3515 gen_low_BATs(env);
3516 gen_high_BATs(env);
3517 /* XXX: TODO: initialize internal interrupt controller */
3518 }
3519 #endif /* TODO */
3520 #endif /* defined (TARGET_PPC64) */
3521
3522 /* Default 32 bits PowerPC target will be 604 */
3523 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
3524 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
3525 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
3526 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
3527 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
3528 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
3529 #define init_proc_PPC32 init_proc_604
3530
3531 /* Default 64 bits PowerPC target will be 970 FX */
3532 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
3533 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
3534 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
3535 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
3536 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
3537 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
3538 #define init_proc_PPC64 init_proc_970FX
3539
3540 /* Default PowerPC target will be PowerPC 32 */
3541 #if defined (TARGET_PPC64) && 0 // XXX: TODO
3542 #define CPU_POWERPC_PPC CPU_POWERPC_PPC64
3543 #define POWERPC_INSNS_PPC_GENERIC POWERPC_INSNS_PPC64
3544 #define POWERPC_MSRM_PPC_GENERIC POWERPC_MSRM_PPC64
3545 #define POWERPC_MMU_PPC_GENERIC POWERPC_MMU_PPC64
3546 #define POWERPC_EXCP_PPC_GENERIC POWERPC_EXCP_PPC64
3547 #define POWERPC_INPUT_PPC_GENERIC POWERPC_INPUT_PPC64
3548 #define init_proc_PPC_GENERIC init_proc_PPC64
3549 #else
3550 #define CPU_POWERPC_PPC CPU_POWERPC_PPC32
3551 #define POWERPC_INSNS_PPC_GENERIC POWERPC_INSNS_PPC32
3552 #define POWERPC_MSRM_PPC_GENERIC POWERPC_MSRM_PPC32
3553 #define POWERPC_MMU_PPC_GENERIC POWERPC_MMU_PPC32
3554 #define POWERPC_EXCP_PPC_GENERIC POWERPC_EXCP_PPC32
3555 #define POWERPC_INPUT_PPC_GENERIC POWERPC_INPUT_PPC32
3556 #define init_proc_PPC_GENERIC init_proc_PPC32
3557 #endif
3558
3559 /*****************************************************************************/
3560 /* PVR definitions for most known PowerPC */
3561 enum {
3562 /* PowerPC 401 family */
3563 /* Generic PowerPC 401 */
3564 #define CPU_POWERPC_401 CPU_POWERPC_401G2
3565 /* PowerPC 401 cores */
3566 CPU_POWERPC_401A1 = 0x00210000,
3567 CPU_POWERPC_401B2 = 0x00220000,
3568 #if 0
3569 CPU_POWERPC_401B3 = xxx,
3570 #endif
3571 CPU_POWERPC_401C2 = 0x00230000,
3572 CPU_POWERPC_401D2 = 0x00240000,
3573 CPU_POWERPC_401E2 = 0x00250000,
3574 CPU_POWERPC_401F2 = 0x00260000,
3575 CPU_POWERPC_401G2 = 0x00270000,
3576 /* PowerPC 401 microcontrolers */
3577 #if 0
3578 CPU_POWERPC_401GF = xxx,
3579 #endif
3580 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
3581 /* IBM Processor for Network Resources */
3582 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
3583 #if 0
3584 CPU_POWERPC_XIPCHIP = xxx,
3585 #endif
3586 /* PowerPC 403 family */
3587 /* Generic PowerPC 403 */
3588 #define CPU_POWERPC_403 CPU_POWERPC_403GC
3589 /* PowerPC 403 microcontrollers */
3590 CPU_POWERPC_403GA = 0x00200011,
3591 CPU_POWERPC_403GB = 0x00200100,
3592 CPU_POWERPC_403GC = 0x00200200,
3593 CPU_POWERPC_403GCX = 0x00201400,
3594 #if 0
3595 CPU_POWERPC_403GP = xxx,
3596 #endif
3597 /* PowerPC 405 family */
3598 /* Generic PowerPC 405 */
3599 #define CPU_POWERPC_405 CPU_POWERPC_405D4
3600 /* PowerPC 405 cores */
3601 #if 0
3602 CPU_POWERPC_405A3 = xxx,
3603 #endif
3604 #if 0
3605 CPU_POWERPC_405A4 = xxx,
3606 #endif
3607 #if 0
3608 CPU_POWERPC_405B3 = xxx,
3609 #endif
3610 #if 0
3611 CPU_POWERPC_405B4 = xxx,
3612 #endif
3613 #if 0
3614 CPU_POWERPC_405C3 = xxx,
3615 #endif
3616 #if 0
3617 CPU_POWERPC_405C4 = xxx,
3618 #endif
3619 CPU_POWERPC_405D2 = 0x20010000,
3620 #if 0
3621 CPU_POWERPC_405D3 = xxx,
3622 #endif
3623 CPU_POWERPC_405D4 = 0x41810000,
3624 #if 0
3625 CPU_POWERPC_405D5 = xxx,
3626 #endif
3627 #if 0
3628 CPU_POWERPC_405E4 = xxx,
3629 #endif
3630 #if 0
3631 CPU_POWERPC_405F4 = xxx,
3632 #endif
3633 #if 0
3634 CPU_POWERPC_405F5 = xxx,
3635 #endif
3636 #if 0
3637 CPU_POWERPC_405F6 = xxx,
3638 #endif
3639 /* PowerPC 405 microcontrolers */
3640 /* XXX: missing 0x200108a0 */
3641 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
3642 CPU_POWERPC_405CRa = 0x40110041,
3643 CPU_POWERPC_405CRb = 0x401100C5,
3644 CPU_POWERPC_405CRc = 0x40110145,
3645 CPU_POWERPC_405EP = 0x51210950,
3646 #if 0
3647 CPU_POWERPC_405EXr = xxx,
3648 #endif
3649 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
3650 #if 0
3651 CPU_POWERPC_405FX = xxx,
3652 #endif
3653 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
3654 CPU_POWERPC_405GPa = 0x40110000,
3655 CPU_POWERPC_405GPb = 0x40110040,
3656 CPU_POWERPC_405GPc = 0x40110082,
3657 CPU_POWERPC_405GPd = 0x401100C4,
3658 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
3659 CPU_POWERPC_405GPR = 0x50910951,
3660 #if 0
3661 CPU_POWERPC_405H = xxx,
3662 #endif
3663 #if 0
3664 CPU_POWERPC_405L = xxx,
3665 #endif
3666 CPU_POWERPC_405LP = 0x41F10000,
3667 #if 0
3668 CPU_POWERPC_405PM = xxx,
3669 #endif
3670 #if 0
3671 CPU_POWERPC_405PS = xxx,
3672 #endif
3673 #if 0
3674 CPU_POWERPC_405S = xxx,
3675 #endif
3676 /* IBM network processors */
3677 CPU_POWERPC_NPE405H = 0x414100C0,
3678 CPU_POWERPC_NPE405H2 = 0x41410140,
3679 CPU_POWERPC_NPE405L = 0x416100C0,
3680 CPU_POWERPC_NPE4GS3 = 0x40B10000,
3681 #if 0
3682 CPU_POWERPC_NPCxx1 = xxx,
3683 #endif
3684 #if 0
3685 CPU_POWERPC_NPR161 = xxx,
3686 #endif
3687 #if 0
3688 CPU_POWERPC_LC77700 = xxx,
3689 #endif
3690 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
3691 #if 0
3692 CPU_POWERPC_STB01000 = xxx,
3693 #endif
3694 #if 0
3695 CPU_POWERPC_STB01010 = xxx,
3696 #endif
3697 #if 0
3698 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
3699 #endif
3700 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
3701 #if 0
3702 CPU_POWERPC_STB043 = xxx,
3703 #endif
3704 #if 0
3705 CPU_POWERPC_STB045 = xxx,
3706 #endif
3707 CPU_POWERPC_STB04 = 0x41810000,
3708 CPU_POWERPC_STB25 = 0x51510950,
3709 #if 0
3710 CPU_POWERPC_STB130 = xxx,
3711 #endif
3712 /* Xilinx cores */
3713 CPU_POWERPC_X2VP4 = 0x20010820,
3714 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
3715 CPU_POWERPC_X2VP20 = 0x20010860,
3716 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
3717 #if 0
3718 CPU_POWERPC_ZL10310 = xxx,
3719 #endif
3720 #if 0
3721 CPU_POWERPC_ZL10311 = xxx,
3722 #endif
3723 #if 0
3724 CPU_POWERPC_ZL10320 = xxx,
3725 #endif
3726 #if 0
3727 CPU_POWERPC_ZL10321 = xxx,
3728 #endif
3729 /* PowerPC 440 family */
3730 /* Generic PowerPC 440 */
3731 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
3732 /* PowerPC 440 cores */
3733 #if 0
3734 CPU_POWERPC_440A4 = xxx,
3735 #endif
3736 #if 0
3737 CPU_POWERPC_440A5 = xxx,
3738 #endif
3739 #if 0
3740 CPU_POWERPC_440B4 = xxx,
3741 #endif
3742 #if 0
3743 CPU_POWERPC_440F5 = xxx,
3744 #endif
3745 #if 0
3746 CPU_POWERPC_440G5 = xxx,
3747 #endif
3748 #if 0
3749 CPU_POWERPC_440H4 = xxx,
3750 #endif
3751 #if 0
3752 CPU_POWERPC_440H6 = xxx,
3753 #endif
3754 /* PowerPC 440 microcontrolers */
3755 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
3756 CPU_POWERPC_440EPa = 0x42221850,
3757 CPU_POWERPC_440EPb = 0x422218D3,
3758 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
3759 CPU_POWERPC_440GPb = 0x40120440,
3760 CPU_POWERPC_440GPc = 0x40120481,
3761 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
3762 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
3763 CPU_POWERPC_440GRX = 0x200008D0,
3764 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
3765 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
3766 CPU_POWERPC_440GXa = 0x51B21850,
3767 CPU_POWERPC_440GXb = 0x51B21851,
3768 CPU_POWERPC_440GXc = 0x51B21892,
3769 CPU_POWERPC_440GXf = 0x51B21894,
3770 #if 0
3771 CPU_POWERPC_440S = xxx,
3772 #endif
3773 CPU_POWERPC_440SP = 0x53221850,
3774 CPU_POWERPC_440SP2 = 0x53221891,
3775 CPU_POWERPC_440SPE = 0x53421890,
3776 /* PowerPC 460 family */
3777 #if 0
3778 /* Generic PowerPC 464 */
3779 #define CPU_POWERPC_464 CPU_POWERPC_464H90
3780 #endif
3781 /* PowerPC 464 microcontrolers */
3782 #if 0
3783 CPU_POWERPC_464H90 = xxx,
3784 #endif
3785 #if 0
3786 CPU_POWERPC_464H90FP = xxx,
3787 #endif
3788 /* Freescale embedded PowerPC cores */
3789 /* e200 family */
3790 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
3791 #if 0
3792 CPU_POWERPC_e200z0 = xxx,
3793 #endif
3794 #if 0
3795 CPU_POWERPC_e200z3 = xxx,
3796 #endif
3797 CPU_POWERPC_e200z5 = 0x81000000,
3798 CPU_POWERPC_e200z6 = 0x81120000,
3799 /* e300 family */
3800 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
3801 CPU_POWERPC_e300c1 = 0x00830000,
3802 CPU_POWERPC_e300c2 = 0x00840000,
3803 CPU_POWERPC_e300c3 = 0x00850000,
3804 /* e500 family */
3805 #define CPU_POWERPC_e500 CPU_POWERPC_e500_v22
3806 CPU_POWERPC_e500_v11 = 0x80200010,
3807 CPU_POWERPC_e500_v12 = 0x80200020,
3808 CPU_POWERPC_e500_v21 = 0x80210010,
3809 CPU_POWERPC_e500_v22 = 0x80210020,
3810 #if 0
3811 CPU_POWERPC_e500mc = xxx,
3812 #endif
3813 /* e600 family */
3814 CPU_POWERPC_e600 = 0x80040010,
3815 /* PowerPC MPC 5xx cores */
3816 CPU_POWERPC_5xx = 0x00020020,
3817 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
3818 CPU_POWERPC_8xx = 0x00500000,
3819 /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
3820 CPU_POWERPC_82xx_HIP3 = 0x00810101,
3821 CPU_POWERPC_82xx_HIP4 = 0x80811014,
3822 CPU_POWERPC_827x = 0x80822013,
3823 /* PowerPC 6xx cores */
3824 CPU_POWERPC_601 = 0x00010001,
3825 CPU_POWERPC_601a = 0x00010002,
3826 CPU_POWERPC_602 = 0x00050100,
3827 CPU_POWERPC_603 = 0x00030100,
3828 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
3829 CPU_POWERPC_603E_v11 = 0x00060101,
3830 CPU_POWERPC_603E_v12 = 0x00060102,
3831 CPU_POWERPC_603E_v13 = 0x00060103,
3832 CPU_POWERPC_603E_v14 = 0x00060104,
3833 CPU_POWERPC_603E_v22 = 0x00060202,
3834 CPU_POWERPC_603E_v3 = 0x00060300,
3835 CPU_POWERPC_603E_v4 = 0x00060400,
3836 CPU_POWERPC_603E_v41 = 0x00060401,
3837 CPU_POWERPC_603E7t = 0x00071201,
3838 CPU_POWERPC_603E7v = 0x00070100,
3839 CPU_POWERPC_603E7v1 = 0x00070101,
3840 CPU_POWERPC_603E7v2 = 0x00070201,
3841 CPU_POWERPC_603E7 = 0x00070200,
3842 CPU_POWERPC_603P = 0x00070000,
3843 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
3844 CPU_POWERPC_G2 = 0x00810011,
3845 #if 0 // Linux pretends the MSB is zero...
3846 CPU_POWERPC_G2H4 = 0x80811010,
3847 CPU_POWERPC_G2gp = 0x80821010,
3848 CPU_POWERPC_G2ls = 0x90810010,
3849 CPU_POWERPC_G2LE = 0x80820010,
3850 CPU_POWERPC_G2LEgp = 0x80822010,
3851 CPU_POWERPC_G2LEls = 0xA0822010,
3852 #else
3853 CPU_POWERPC_G2H4 = 0x00811010,
3854 CPU_POWERPC_G2gp = 0x00821010,
3855 CPU_POWERPC_G2ls = 0x10810010,
3856 CPU_POWERPC_G2LE = 0x00820010,
3857 CPU_POWERPC_G2LEgp = 0x00822010,
3858 CPU_POWERPC_G2LEls = 0x20822010,
3859 #endif
3860 CPU_POWERPC_604 = 0x00040103,
3861 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
3862 CPU_POWERPC_604E_v10 = 0x00090100, /* Also 2110 & 2120 */
3863 CPU_POWERPC_604E_v22 = 0x00090202,
3864 CPU_POWERPC_604E_v24 = 0x00090204,
3865 CPU_POWERPC_604R = 0x000a0101, /* Also 0x00093102 */
3866 #if 0
3867 CPU_POWERPC_604EV = xxx,
3868 #endif
3869 /* PowerPC 740/750 cores (aka G3) */
3870 /* XXX: missing 0x00084202 */
3871 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
3872 CPU_POWERPC_7x0_v20 = 0x00080200,
3873 CPU_POWERPC_7x0_v21 = 0x00080201,
3874 CPU_POWERPC_7x0_v22 = 0x00080202,
3875 CPU_POWERPC_7x0_v30 = 0x00080300,
3876 CPU_POWERPC_7x0_v31 = 0x00080301,
3877 CPU_POWERPC_740E = 0x00080100,
3878 CPU_POWERPC_7x0P = 0x10080000,
3879 /* XXX: missing 0x00087010 (CL ?) */
3880 CPU_POWERPC_750CL = 0x00087200,
3881 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
3882 CPU_POWERPC_750CX_v21 = 0x00082201,
3883 CPU_POWERPC_750CX_v22 = 0x00082202,
3884 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
3885 CPU_POWERPC_750CXE_v21 = 0x00082211,
3886 CPU_POWERPC_750CXE_v22 = 0x00082212,
3887 CPU_POWERPC_750CXE_v23 = 0x00082213,
3888 CPU_POWERPC_750CXE_v24 = 0x00082214,
3889 CPU_POWERPC_750CXE_v24b = 0x00083214,
3890 CPU_POWERPC_750CXE_v31 = 0x00083211,
3891 CPU_POWERPC_750CXE_v31b = 0x00083311,
3892 CPU_POWERPC_750CXR = 0x00083410,
3893 CPU_POWERPC_750E = 0x00080200,
3894 CPU_POWERPC_750FL = 0x700A0203,
3895 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
3896 CPU_POWERPC_750FX_v10 = 0x70000100,
3897 CPU_POWERPC_750FX_v20 = 0x70000200,
3898 CPU_POWERPC_750FX_v21 = 0x70000201,
3899 CPU_POWERPC_750FX_v22 = 0x70000202,
3900 CPU_POWERPC_750FX_v23 = 0x70000203,
3901 CPU_POWERPC_750GL = 0x70020102,
3902 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
3903 CPU_POWERPC_750GX_v10 = 0x70020100,
3904 CPU_POWERPC_750GX_v11 = 0x70020101,
3905 CPU_POWERPC_750GX_v12 = 0x70020102,
3906 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
3907 CPU_POWERPC_750L_v22 = 0x00088202,
3908 CPU_POWERPC_750L_v30 = 0x00088300,
3909 CPU_POWERPC_750L_v32 = 0x00088302,
3910 /* PowerPC 745/755 cores */
3911 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
3912 CPU_POWERPC_7x5_v10 = 0x00083100,
3913 CPU_POWERPC_7x5_v11 = 0x00083101,
3914 CPU_POWERPC_7x5_v20 = 0x00083200,
3915 CPU_POWERPC_7x5_v21 = 0x00083201,
3916 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
3917 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
3918 CPU_POWERPC_7x5_v24 = 0x00083204,
3919 CPU_POWERPC_7x5_v25 = 0x00083205,
3920 CPU_POWERPC_7x5_v26 = 0x00083206,
3921 CPU_POWERPC_7x5_v27 = 0x00083207,
3922 CPU_POWERPC_7x5_v28 = 0x00083208,
3923 #if 0
3924 CPU_POWERPC_7x5P = xxx,
3925 #endif
3926 /* PowerPC 74xx cores (aka G4) */
3927 /* XXX: missing 0x000C1101 */
3928 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
3929 CPU_POWERPC_7400_v10 = 0x000C0100,
3930 CPU_POWERPC_7400_v11 = 0x000C0101,
3931 CPU_POWERPC_7400_v20 = 0x000C0200,
3932 CPU_POWERPC_7400_v22 = 0x000C0202,
3933 CPU_POWERPC_7400_v26 = 0x000C0206,
3934 CPU_POWERPC_7400_v27 = 0x000C0207,
3935 CPU_POWERPC_7400_v28 = 0x000C0208,
3936 CPU_POWERPC_7400_v29 = 0x000C0209,
3937 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
3938 CPU_POWERPC_7410_v10 = 0x800C1100,
3939 CPU_POWERPC_7410_v11 = 0x800C1101,
3940 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
3941 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
3942 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
3943 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
3944 CPU_POWERPC_7448_v10 = 0x80040100,
3945 CPU_POWERPC_7448_v11 = 0x80040101,
3946 CPU_POWERPC_7448_v20 = 0x80040200,
3947 CPU_POWERPC_7448_v21 = 0x80040201,
3948 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
3949 CPU_POWERPC_7450_v10 = 0x80000100,
3950 CPU_POWERPC_7450_v11 = 0x80000101,
3951 CPU_POWERPC_7450_v12 = 0x80000102,
3952 CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
3953 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
3954 CPU_POWERPC_74x1 = 0x80000203,
3955 CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
3956 /* XXX: missing 0x80010200 */
3957 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
3958 CPU_POWERPC_74x5_v10 = 0x80010100,
3959 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
3960 CPU_POWERPC_74x5_v32 = 0x80010302,
3961 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
3962 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
3963 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
3964 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
3965 CPU_POWERPC_74x7_v11 = 0x80030101, /* aka B: 1.1 */
3966 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
3967 /* 64 bits PowerPC */
3968 CPU_POWERPC_620 = 0x00140000,
3969 CPU_POWERPC_630 = 0x00400000,
3970 CPU_POWERPC_631 = 0x00410104,
3971 CPU_POWERPC_POWER4 = 0x00350000,
3972 CPU_POWERPC_POWER4P = 0x00380000,
3973 CPU_POWERPC_POWER5 = 0x003A0203,
3974 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
3975 CPU_POWERPC_POWER5P = 0x003B0000,
3976 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
3977 CPU_POWERPC_POWER6 = 0x003E0000,
3978 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 running POWER5 mode */
3979 CPU_POWERPC_POWER6A = 0x0F000002,
3980 CPU_POWERPC_970 = 0x00390202,
3981 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
3982 CPU_POWERPC_970FX_v10 = 0x00391100,
3983 CPU_POWERPC_970FX_v20 = 0x003C0200,
3984 CPU_POWERPC_970FX_v21 = 0x003C0201,
3985 CPU_POWERPC_970FX_v30 = 0x003C0300,
3986 CPU_POWERPC_970FX_v31 = 0x003C0301,
3987 CPU_POWERPC_970GX = 0x00450000,
3988 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
3989 CPU_POWERPC_970MP_v10 = 0x00440100,
3990 CPU_POWERPC_970MP_v11 = 0x00440101,
3991 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
3992 CPU_POWERPC_CELL_v10 = 0x00700100,
3993 CPU_POWERPC_CELL_v20 = 0x00700400,
3994 CPU_POWERPC_CELL_v30 = 0x00700500,
3995 CPU_POWERPC_CELL_v31 = 0x00700501,
3996 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
3997 CPU_POWERPC_RS64 = 0x00330000,
3998 CPU_POWERPC_RS64II = 0x00340000,
3999 CPU_POWERPC_RS64III = 0x00360000,
4000 CPU_POWERPC_RS64IV = 0x00370000,
4001 /* Original POWER */
4002 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
4003 * POWER2 (RIOS2) & RSC2 (P2SC) here
4004 */
4005 #if 0
4006 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
4007 #endif
4008 #if 0
4009 CPU_POWER2 = xxx, /* 0x40000 ? */
4010 #endif
4011 /* PA Semi core */
4012 CPU_POWERPC_PA6T = 0x00900000,
4013 };
4014
4015 /* System version register (used on MPC 8xxx) */
4016 enum {
4017 PPC_SVR_8540 = 0x80300000,
4018 PPC_SVR_8541E = 0x807A0010,
4019 PPC_SVR_8543v10 = 0x80320010,
4020 PPC_SVR_8543v11 = 0x80320011,
4021 PPC_SVR_8543v20 = 0x80320020,
4022 PPC_SVR_8543Ev10 = 0x803A0010,
4023 PPC_SVR_8543Ev11 = 0x803A0011,
4024 PPC_SVR_8543Ev20 = 0x803A0020,
4025 PPC_SVR_8545 = 0x80310220,
4026 PPC_SVR_8545E = 0x80390220,
4027 PPC_SVR_8547E = 0x80390120,
4028 PPC_SCR_8548v10 = 0x80310010,
4029 PPC_SCR_8548v11 = 0x80310011,
4030 PPC_SCR_8548v20 = 0x80310020,
4031 PPC_SVR_8548Ev10 = 0x80390010,
4032 PPC_SVR_8548Ev11 = 0x80390011,
4033 PPC_SVR_8548Ev20 = 0x80390020,
4034 PPC_SVR_8555E = 0x80790010,
4035 PPC_SVR_8560v10 = 0x80700010,
4036 PPC_SVR_8560v20 = 0x80700020,
4037 };
4038
4039 /*****************************************************************************/
4040 /* PowerPC CPU definitions */
4041 #define POWERPC_DEF(_name, _pvr, _pvr_mask, _type) \
4042 { \
4043 .name = _name, \
4044 .pvr = _pvr, \
4045 .pvr_mask = _pvr_mask, \
4046 .insns_flags = glue(POWERPC_INSNS_,_type), \
4047 .msr_mask = glue(POWERPC_MSRM_,_type), \
4048 .mmu_model = glue(POWERPC_MMU_,_type), \
4049 .excp_model = glue(POWERPC_EXCP_,_type), \
4050 .bus_model = glue(POWERPC_INPUT_,_type), \
4051 .init_proc = &glue(init_proc_,_type), \
4052 }
4053
4054 static ppc_def_t ppc_defs[] = {
4055 /* Embedded PowerPC */
4056 /* PowerPC 401 family */
4057 /* Generic PowerPC 401 */
4058 POWERPC_DEF("401", CPU_POWERPC_401, 0xFFFF0000, 401),
4059 /* PowerPC 401 cores */
4060 /* PowerPC 401A1 */
4061 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 0xFFFFFFFF, 401),
4062 /* PowerPC 401B2 */
4063 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 0xFFFFFFFF, 401x2),
4064 #if defined (TODO)
4065 /* PowerPC 401B3 */
4066 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 0xFFFFFFFF, 401x3),
4067 #endif
4068 /* PowerPC 401C2 */
4069 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 0xFFFFFFFF, 401x2),
4070 /* PowerPC 401D2 */
4071 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 0xFFFFFFFF, 401x2),
4072 /* PowerPC 401E2 */
4073 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 0xFFFFFFFF, 401x2),
4074 /* PowerPC 401F2 */
4075 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 0xFFFFFFFF, 401x2),
4076 /* PowerPC 401G2 */
4077 /* XXX: to be checked */
4078 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 0xFFFFFFFF, 401x2),
4079 /* PowerPC 401 microcontrolers */
4080 #if defined (TODO)
4081 /* PowerPC 401GF */
4082 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 0xFFFFFFFF, 401),
4083 #endif
4084 /* IOP480 (401 microcontroler) */
4085 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, 0xFFFFFFFF, IOP480),
4086 /* IBM Processor for Network Resources */
4087 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 0xFFFFFFFF, 401),
4088 #if defined (TODO)
4089 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 0xFFFFFFFF, 401),
4090 #endif
4091 /* PowerPC 403 family */
4092 /* Generic PowerPC 403 */
4093 POWERPC_DEF("403", CPU_POWERPC_403, 0xFFFF0000, 403),
4094 /* PowerPC 403 microcontrolers */
4095 /* PowerPC 403 GA */
4096 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 0xFFFFFFFF, 403),
4097 /* PowerPC 403 GB */
4098 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 0xFFFFFFFF, 403),
4099 /* PowerPC 403 GC */
4100 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 0xFFFFFFFF, 403),
4101 /* PowerPC 403 GCX */
4102 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 0xFFFFFFFF, 403GCX),
4103 #if defined (TODO)
4104 /* PowerPC 403 GP */
4105 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 0xFFFFFFFF, 403),
4106 #endif
4107 /* PowerPC 405 family */
4108 /* Generic PowerPC 405 */
4109 POWERPC_DEF("405", CPU_POWERPC_405, 0xFFFF0000, 405),
4110 /* PowerPC 405 cores */
4111 #if defined (TODO)
4112 /* PowerPC 405 A3 */
4113 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 0xFFFFFFFF, 405),
4114 #endif
4115 #if defined (TODO)
4116 /* PowerPC 405 A4 */
4117 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 0xFFFFFFFF, 405),
4118 #endif
4119 #if defined (TODO)
4120 /* PowerPC 405 B3 */
4121 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 0xFFFFFFFF, 405),
4122 #endif
4123 #if defined (TODO)
4124 /* PowerPC 405 B4 */
4125 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 0xFFFFFFFF, 405),
4126 #endif
4127 #if defined (TODO)
4128 /* PowerPC 405 C3 */
4129 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 0xFFFFFFFF, 405),
4130 #endif
4131 #if defined (TODO)
4132 /* PowerPC 405 C4 */
4133 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 0xFFFFFFFF, 405),
4134 #endif
4135 /* PowerPC 405 D2 */
4136 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 0xFFFFFFFF, 405),
4137 #if defined (TODO)
4138 /* PowerPC 405 D3 */
4139 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 0xFFFFFFFF, 405),
4140 #endif
4141 /* PowerPC 405 D4 */
4142 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 0xFFFFFFFF, 405),
4143 #if defined (TODO)
4144 /* PowerPC 405 D5 */
4145 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 0xFFFFFFFF, 405),
4146 #endif
4147 #if defined (TODO)
4148 /* PowerPC 405 E4 */
4149 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 0xFFFFFFFF, 405),
4150 #endif
4151 #if defined (TODO)
4152 /* PowerPC 405 F4 */
4153 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 0xFFFFFFFF, 405),
4154 #endif
4155 #if defined (TODO)
4156 /* PowerPC 405 F5 */
4157 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 0xFFFFFFFF, 405),
4158 #endif
4159 #if defined (TODO)
4160 /* PowerPC 405 F6 */
4161 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 0xFFFFFFFF, 405),
4162 #endif
4163 /* PowerPC 405 microcontrolers */
4164 /* PowerPC 405 CR */
4165 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 0xFFFFFFFF, 405),
4166 /* PowerPC 405 CRa */
4167 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 0xFFFFFFFF, 405),
4168 /* PowerPC 405 CRb */
4169 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 0xFFFFFFFF, 405),
4170 /* PowerPC 405 CRc */
4171 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 0xFFFFFFFF, 405),
4172 /* PowerPC 405 EP */
4173 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 0xFFFFFFFF, 405),
4174 #if defined(TODO)
4175 /* PowerPC 405 EXr */
4176 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 0xFFFFFFFF, 405),
4177 #endif
4178 /* PowerPC 405 EZ */
4179 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 0xFFFFFFFF, 405),
4180 #if defined(TODO)
4181 /* PowerPC 405 FX */
4182 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 0xFFFFFFFF, 405),
4183 #endif
4184 /* PowerPC 405 GP */
4185 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 0xFFFFFFFF, 405),
4186 /* PowerPC 405 GPa */
4187 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 0xFFFFFFFF, 405),
4188 /* PowerPC 405 GPb */
4189 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 0xFFFFFFFF, 405),
4190 /* PowerPC 405 GPc */
4191 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 0xFFFFFFFF, 405),
4192 /* PowerPC 405 GPd */
4193 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 0xFFFFFFFF, 405),
4194 /* PowerPC 405 GPe */
4195 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 0xFFFFFFFF, 405),
4196 /* PowerPC 405 GPR */
4197 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 0xFFFFFFFF, 405),
4198 #if defined(TODO)
4199 /* PowerPC 405 H */
4200 POWERPC_DEF("405H", CPU_POWERPC_405H, 0xFFFFFFFF, 405),
4201 #endif
4202 #if defined(TODO)
4203 /* PowerPC 405 L */
4204 POWERPC_DEF("405L", CPU_POWERPC_405L, 0xFFFFFFFF, 405),
4205 #endif
4206 /* PowerPC 405 LP */
4207 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 0xFFFFFFFF, 405),
4208 #if defined(TODO)
4209 /* PowerPC 405 PM */
4210 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 0xFFFFFFFF, 405),
4211 #endif
4212 #if defined(TODO)
4213 /* PowerPC 405 PS */
4214 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 0xFFFFFFFF, 405),
4215 #endif
4216 #if defined(TODO)
4217 /* PowerPC 405 S */
4218 POWERPC_DEF("405S", CPU_POWERPC_405S, 0xFFFFFFFF, 405),
4219 #endif
4220 /* Npe405 H */
4221 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 0xFFFFFFFF, 405),
4222 /* Npe405 H2 */
4223 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 0xFFFFFFFF, 405),
4224 /* Npe405 L */
4225 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 0xFFFFFFFF, 405),
4226 /* Npe4GS3 */
4227 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 0xFFFFFFFF, 405),
4228 #if defined (TODO)
4229 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 0xFFFFFFFF, 405),
4230 #endif
4231 #if defined (TODO)
4232 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 0xFFFFFFFF, 405),
4233 #endif
4234 #if defined (TODO)
4235 /* PowerPC LC77700 (Sanyo) */
4236 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 0xFFFFFFFF, 405),
4237 #endif
4238 /* PowerPC 401/403/405 based set-top-box microcontrolers */
4239 #if defined (TODO)
4240 /* STB010000 */
4241 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 0xFFFFFFFF, 401x2),
4242 #endif
4243 #if defined (TODO)
4244 /* STB01010 */
4245 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 0xFFFFFFFF, 401x2),
4246 #endif
4247 #if defined (TODO)
4248 /* STB0210 */
4249 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 0xFFFFFFFF, 401x3),
4250 #endif
4251 /* STB03xx */
4252 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 0xFFFFFFFF, 405),
4253 #if defined (TODO)
4254 /* STB043x */
4255 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 0xFFFFFFFF, 405),
4256 #endif
4257 #if defined (TODO)
4258 /* STB045x */
4259 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 0xFFFFFFFF, 405),
4260 #endif
4261 /* STB04xx */
4262 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 0xFFFF0000, 405),
4263 /* STB25xx */
4264 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 0xFFFFFFFF, 405),
4265 #if defined (TODO)
4266 /* STB130 */
4267 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 0xFFFFFFFF, 405),
4268 #endif
4269 /* Xilinx PowerPC 405 cores */
4270 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 0xFFFFFFFF, 405),
4271 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 0xFFFFFFFF, 405),
4272 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 0xFFFFFFFF, 405),
4273 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 0xFFFFFFFF, 405),
4274 #if defined (TODO)
4275 /* Zarlink ZL10310 */
4276 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 0xFFFFFFFF, 405),
4277 #endif
4278 #if defined (TODO)
4279 /* Zarlink ZL10311 */
4280 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 0xFFFFFFFF, 405),
4281 #endif
4282 #if defined (TODO)
4283 /* Zarlink ZL10320 */
4284 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 0xFFFFFFFF, 405),
4285 #endif
4286 #if defined (TODO)
4287 /* Zarlink ZL10321 */
4288 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 0xFFFFFFFF, 405),
4289 #endif
4290 /* PowerPC 440 family */
4291 /* Generic PowerPC 440 */
4292 POWERPC_DEF("440", CPU_POWERPC_440, 0xFFFFFFFF, 440GP),
4293 /* PowerPC 440 cores */
4294 #if defined (TODO)
4295 /* PowerPC 440 A4 */
4296 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 0xFFFFFFFF, 440x4),
4297 #endif
4298 #if defined (TODO)
4299 /* PowerPC 440 A5 */
4300 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 0xFFFFFFFF, 440x5),
4301 #endif
4302 #if defined (TODO)
4303 /* PowerPC 440 B4 */
4304 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 0xFFFFFFFF, 440x4),
4305 #endif
4306 #if defined (TODO)
4307 /* PowerPC 440 G4 */
4308 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 0xFFFFFFFF, 440x4),
4309 #endif
4310 #if defined (TODO)
4311 /* PowerPC 440 F5 */
4312 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 0xFFFFFFFF, 440x5),
4313 #endif
4314 #if defined (TODO)
4315 /* PowerPC 440 G5 */
4316 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 0xFFFFFFFF, 440x5),
4317 #endif
4318 #if defined (TODO)
4319 /* PowerPC 440H4 */
4320 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 0xFFFFFFFF, 440x4),
4321 #endif
4322 #if defined (TODO)
4323 /* PowerPC 440H6 */
4324 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 0xFFFFFFFF, 440Gx5),
4325 #endif
4326 /* PowerPC 440 microcontrolers */
4327 /* PowerPC 440 EP */
4328 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 0xFFFFFFFF, 440EP),
4329 /* PowerPC 440 EPa */
4330 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 0xFFFFFFFF, 440EP),
4331 /* PowerPC 440 EPb */
4332 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 0xFFFFFFFF, 440EP),
4333 /* PowerPC 440 EPX */
4334 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 0xFFFFFFFF, 440EP),
4335 /* PowerPC 440 GP */
4336 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 0xFFFFFFFF, 440GP),
4337 /* PowerPC 440 GPb */
4338 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 0xFFFFFFFF, 440GP),
4339 /* PowerPC 440 GPc */
4340 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 0xFFFFFFFF, 440GP),
4341 /* PowerPC 440 GR */
4342 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 0xFFFFFFFF, 440x5),
4343 /* PowerPC 440 GRa */
4344 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 0xFFFFFFFF, 440x5),
4345 /* PowerPC 440 GRX */
4346 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 0xFFFFFFFF, 440x5),
4347 /* PowerPC 440 GX */
4348 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 0xFFFFFFFF, 440EP),
4349 /* PowerPC 440 GXa */
4350 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 0xFFFFFFFF, 440EP),
4351 /* PowerPC 440 GXb */
4352 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 0xFFFFFFFF, 440EP),
4353 /* PowerPC 440 GXc */
4354 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 0xFFFFFFFF, 440EP),
4355 /* PowerPC 440 GXf */
4356 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 0xFFFFFFFF, 440EP),
4357 #if defined(TODO)
4358 /* PowerPC 440 S */
4359 POWERPC_DEF("440S", CPU_POWERPC_440S, 0xFFFFFFFF, 440),
4360 #endif
4361 /* PowerPC 440 SP */
4362 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 0xFFFFFFFF, 440EP),
4363 /* PowerPC 440 SP2 */
4364 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 0xFFFFFFFF, 440EP),
4365 /* PowerPC 440 SPE */
4366 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 0xFFFFFFFF, 440EP),
4367 /* PowerPC 460 family */
4368 #if defined (TODO)
4369 /* Generic PowerPC 464 */
4370 POWERPC_DEF("464", CPU_POWERPC_464, 0xFFFFFFFF, 460),
4371 #endif
4372 /* PowerPC 464 microcontrolers */
4373 #if defined (TODO)
4374 /* PowerPC 464H90 */
4375 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 0xFFFFFFFF, 460),
4376 #endif
4377 #if defined (TODO)
4378 /* PowerPC 464H90F */
4379 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 0xFFFFFFFF, 460F),
4380 #endif
4381 /* Freescale embedded PowerPC cores */
4382 /* e200 family */
4383 #if defined (TODO)
4384 /* Generic PowerPC e200 core */
4385 POWERPC_DEF("e200", CPU_POWERPC_e200, 0xFFFFFFFF, e200),
4386 #endif
4387 #if defined (TODO)
4388 /* PowerPC e200z5 core */
4389 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, 0xFFFFFFFF, e200),
4390 #endif
4391 #if defined (TODO)
4392 /* PowerPC e200z6 core */
4393 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, 0xFFFFFFFF, e200),
4394 #endif
4395 /* e300 family */
4396 #if defined (TODO)
4397 /* Generic PowerPC e300 core */
4398 POWERPC_DEF("e300", CPU_POWERPC_e300, 0xFFFFFFFF, e300),
4399 #endif
4400 #if defined (TODO)
4401 /* PowerPC e300c1 core */
4402 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, 0xFFFFFFFF, e300),
4403 #endif
4404 #if defined (TODO)
4405 /* PowerPC e300c2 core */
4406 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, 0xFFFFFFFF, e300),
4407 #endif
4408 #if defined (TODO)
4409 /* PowerPC e300c3 core */
4410 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, 0xFFFFFFFF, e300),
4411 #endif
4412 /* e500 family */
4413 #if defined (TODO)
4414 /* PowerPC e500 core */
4415 POWERPC_DEF("e500", CPU_POWERPC_e500, 0xFFFFFFFF, e500),
4416 #endif
4417 #if defined (TODO)
4418 /* PowerPC e500 v1.1 core */
4419 POWERPC_DEF("e500v1.1", CPU_POWERPC_e500_v11, 0xFFFFFFFF, e500),
4420 #endif
4421 #if defined (TODO)
4422 /* PowerPC e500 v1.2 core */
4423 POWERPC_DEF("e500v1.2", CPU_POWERPC_e500_v12, 0xFFFFFFFF, e500),
4424 #endif
4425 #if defined (TODO)
4426 /* PowerPC e500 v2.1 core */
4427 POWERPC_DEF("e500v2.1", CPU_POWERPC_e500_v21, 0xFFFFFFFF, e500),
4428 #endif
4429 #if defined (TODO)
4430 /* PowerPC e500 v2.2 core */
4431 POWERPC_DEF("e500v2.2", CPU_POWERPC_e500_v22, 0xFFFFFFFF, e500),
4432 #endif
4433 /* e600 family */
4434 #if defined (TODO)
4435 /* PowerPC e600 core */
4436 POWERPC_DEF("e600", CPU_POWERPC_e600, 0xFFFFFFFF, e600),
4437 #endif
4438 /* PowerPC MPC 5xx cores */
4439 #if defined (TODO)
4440 /* PowerPC MPC 5xx */
4441 POWERPC_DEF("mpc5xx", CPU_POWERPC_5xx, 0xFFFFFFFF, 5xx),
4442 #endif
4443 /* PowerPC MPC 8xx cores */
4444 #if defined (TODO)
4445 /* PowerPC MPC 8xx */
4446 POWERPC_DEF("mpc8xx", CPU_POWERPC_8xx, 0xFFFFFFFF, 8xx),
4447 #endif
4448 /* PowerPC MPC 8xxx cores */
4449 #if defined (TODO)
4450 /* PowerPC MPC 82xx HIP3 */
4451 POWERPC_DEF("mpc82xxhip3", CPU_POWERPC_82xx_HIP3, 0xFFFFFFFF, 82xx),
4452 #endif
4453 #if defined (TODO)
4454 /* PowerPC MPC 82xx HIP4 */
4455 POWERPC_DEF("mpc82xxhip4", CPU_POWERPC_82xx_HIP4, 0xFFFFFFFF, 82xx),
4456 #endif
4457 #if defined (TODO)
4458 /* PowerPC MPC 827x */
4459 POWERPC_DEF("mpc827x", CPU_POWERPC_827x, 0xFFFFFFFF, 827x),
4460 #endif
4461
4462 /* 32 bits "classic" PowerPC */
4463 /* PowerPC 6xx family */
4464 /* PowerPC 601 */
4465 POWERPC_DEF("601", CPU_POWERPC_601, 0xFFFFFFFF, 601),
4466 /* PowerPC 601v2 */
4467 POWERPC_DEF("601a", CPU_POWERPC_601a, 0xFFFFFFFF, 601),
4468 /* PowerPC 602 */
4469 POWERPC_DEF("602", CPU_POWERPC_602, 0xFFFFFFFF, 602),
4470 /* PowerPC 603 */
4471 POWERPC_DEF("603", CPU_POWERPC_603, 0xFFFFFFFF, 603),
4472 /* Code name for PowerPC 603 */
4473 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 0xFFFFFFFF, 603),
4474 /* PowerPC 603e */
4475 POWERPC_DEF("603e", CPU_POWERPC_603E, 0xFFFFFFFF, 603E),
4476 /* Code name for PowerPC 603e */
4477 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 0xFFFFFFFF, 603E),
4478 /* PowerPC 603e v1.1 */
4479 POWERPC_DEF("603e1.1", CPU_POWERPC_603E_v11, 0xFFFFFFFF, 603E),
4480 /* PowerPC 603e v1.2 */
4481 POWERPC_DEF("603e1.2", CPU_POWERPC_603E_v12, 0xFFFFFFFF, 603E),
4482 /* PowerPC 603e v1.3 */
4483 POWERPC_DEF("603e1.3", CPU_POWERPC_603E_v13, 0xFFFFFFFF, 603E),
4484 /* PowerPC 603e v1.4 */
4485 POWERPC_DEF("603e1.4", CPU_POWERPC_603E_v14, 0xFFFFFFFF, 603E),
4486 /* PowerPC 603e v2.2 */
4487 POWERPC_DEF("603e2.2", CPU_POWERPC_603E_v22, 0xFFFFFFFF, 603E),
4488 /* PowerPC 603e v3 */
4489 POWERPC_DEF("603e3", CPU_POWERPC_603E_v3, 0xFFFFFFFF, 603E),
4490 /* PowerPC 603e v4 */
4491 POWERPC_DEF("603e4", CPU_POWERPC_603E_v4, 0xFFFFFFFF, 603E),
4492 /* PowerPC 603e v4.1 */
4493 POWERPC_DEF("603e4.1", CPU_POWERPC_603E_v41, 0xFFFFFFFF, 603E),
4494 /* PowerPC 603e */
4495 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 0xFFFFFFFF, 603E),
4496 /* PowerPC 603e7t */
4497 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 0xFFFFFFFF, 603E),
4498 /* PowerPC 603e7v */
4499 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E),
4500 /* Code name for PowerPC 603ev */
4501 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E),
4502 /* PowerPC 603e7v1 */
4503 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 0xFFFFFFFF, 603E),
4504 /* PowerPC 603e7v2 */
4505 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 0xFFFFFFFF, 603E),
4506 /* PowerPC 603p */
4507 /* to be checked */
4508 POWERPC_DEF("603p", CPU_POWERPC_603P, 0xFFFFFFFF, 603),
4509 /* PowerPC 603r */
4510 POWERPC_DEF("603r", CPU_POWERPC_603R, 0xFFFFFFFF, 603E),
4511 /* Code name for PowerPC 603r */
4512 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 0xFFFFFFFF, 603E),
4513 /* PowerPC G2 core */
4514 POWERPC_DEF("G2", CPU_POWERPC_G2, 0xFFFFFFFF, G2),
4515 /* PowerPC G2 H4 */
4516 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, 0xFFFFFFFF, G2),
4517 /* PowerPC G2 GP */
4518 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, 0xFFFFFFFF, G2),
4519 /* PowerPC G2 LS */
4520 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, 0xFFFFFFFF, G2),
4521 /* PowerPC G2LE */
4522 /* Same as G2, with little-endian mode support */
4523 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, 0xFFFFFFFF, G2LE),
4524 /* PowerPC G2LE GP */
4525 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, 0xFFFFFFFF, G2LE),
4526 /* PowerPC G2LE LS */
4527 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, 0xFFFFFFFF, G2LE),
4528 /* PowerPC 604 */
4529 POWERPC_DEF("604", CPU_POWERPC_604, 0xFFFFFFFF, 604),
4530 /* PowerPC 604e */
4531 POWERPC_DEF("604e", CPU_POWERPC_604E, 0xFFFFFFFF, 604),
4532 /* PowerPC 604e v1.0 */
4533 POWERPC_DEF("604e1.0", CPU_POWERPC_604E_v10, 0xFFFFFFFF, 604),
4534 /* PowerPC 604e v2.2 */
4535 POWERPC_DEF("604e2.2", CPU_POWERPC_604E_v22, 0xFFFFFFFF, 604),
4536 /* PowerPC 604e v2.4 */
4537 POWERPC_DEF("604e2.4", CPU_POWERPC_604E_v24, 0xFFFFFFFF, 604),
4538 /* PowerPC 604r */
4539 POWERPC_DEF("604r", CPU_POWERPC_604R, 0xFFFFFFFF, 604),
4540 #if defined(TODO)
4541 /* PowerPC 604ev */
4542 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 0xFFFFFFFF, 604),
4543 #endif
4544 /* PowerPC 7xx family */
4545 /* Generic PowerPC 740 (G3) */
4546 POWERPC_DEF("740", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
4547 /* Generic PowerPC 750 (G3) */
4548 POWERPC_DEF("750", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
4549 /* Code name for generic PowerPC 740/750 (G3) */
4550 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
4551 /* PowerPC 740/750 is also known as G3 */
4552 POWERPC_DEF("G3", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
4553 /* PowerPC 740 v2.0 (G3) */
4554 POWERPC_DEF("740v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0),
4555 /* PowerPC 750 v2.0 (G3) */
4556 POWERPC_DEF("750v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0),
4557 /* PowerPC 740 v2.1 (G3) */
4558 POWERPC_DEF("740v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0),
4559 /* PowerPC 750 v2.1 (G3) */
4560 POWERPC_DEF("750v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0),
4561 /* PowerPC 740 v2.2 (G3) */
4562 POWERPC_DEF("740v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0),
4563 /* PowerPC 750 v2.2 (G3) */
4564 POWERPC_DEF("750v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0),
4565 /* PowerPC 740 v3.0 (G3) */
4566 POWERPC_DEF("740v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0),
4567 /* PowerPC 750 v3.0 (G3) */
4568 POWERPC_DEF("750v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0),
4569 /* PowerPC 740 v3.1 (G3) */
4570 POWERPC_DEF("740v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0),
4571 /* PowerPC 750 v3.1 (G3) */
4572 POWERPC_DEF("750v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0),
4573 /* PowerPC 740E (G3) */
4574 POWERPC_DEF("740e", CPU_POWERPC_740E, 0xFFFFFFFF, 7x0),
4575 /* PowerPC 740P (G3) */
4576 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
4577 /* PowerPC 750P (G3) */
4578 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
4579 /* Code name for PowerPC 740P/750P (G3) */
4580 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
4581 /* PowerPC 750CL (G3 embedded) */
4582 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 0xFFFFFFFF, 7x0),
4583 /* PowerPC 750CX (G3 embedded) */
4584 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 0xFFFFFFFF, 7x0),
4585 /* PowerPC 750CX v2.1 (G3 embedded) */
4586 POWERPC_DEF("750cx2.1", CPU_POWERPC_750CX_v21, 0xFFFFFFFF, 7x0),
4587 /* PowerPC 750CX v2.2 (G3 embedded) */
4588 POWERPC_DEF("750cx2.2", CPU_POWERPC_750CX_v22, 0xFFFFFFFF, 7x0),
4589 /* PowerPC 750CXe (G3 embedded) */
4590 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 0xFFFFFFFF, 7x0),
4591 /* PowerPC 750CXe v2.1 (G3 embedded) */
4592 POWERPC_DEF("750cxe21", CPU_POWERPC_750CXE_v21, 0xFFFFFFFF, 7x0),
4593 /* PowerPC 750CXe v2.2 (G3 embedded) */
4594 POWERPC_DEF("750cxe22", CPU_POWERPC_750CXE_v22, 0xFFFFFFFF, 7x0),
4595 /* PowerPC 750CXe v2.3 (G3 embedded) */
4596 POWERPC_DEF("750cxe23", CPU_POWERPC_750CXE_v23, 0xFFFFFFFF, 7x0),
4597 /* PowerPC 750CXe v2.4 (G3 embedded) */
4598 POWERPC_DEF("750cxe24", CPU_POWERPC_750CXE_v24, 0xFFFFFFFF, 7x0),
4599 /* PowerPC 750CXe v2.4b (G3 embedded) */
4600 POWERPC_DEF("750cxe24b", CPU_POWERPC_750CXE_v24b, 0xFFFFFFFF, 7x0),
4601 /* PowerPC 750CXe v3.1 (G3 embedded) */
4602 POWERPC_DEF("750cxe31", CPU_POWERPC_750CXE_v31, 0xFFFFFFFF, 7x0),
4603 /* PowerPC 750CXe v3.1b (G3 embedded) */
4604 POWERPC_DEF("750cxe3.1b", CPU_POWERPC_750CXE_v31b, 0xFFFFFFFF, 7x0),
4605 /* PowerPC 750CXr (G3 embedded) */
4606 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 0xFFFFFFFF, 7x0),
4607 /* PowerPC 750E (G3) */
4608 POWERPC_DEF("750e", CPU_POWERPC_750E, 0xFFFFFFFF, 7x0),
4609 /* PowerPC 750FL (G3 embedded) */
4610 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 0xFFFFFFFF, 7x0),
4611 /* PowerPC 750FX (G3 embedded) */
4612 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 0xFFFFFFFF, 750fx),
4613 /* PowerPC 750FX v1.0 (G3 embedded) */
4614 POWERPC_DEF("750fx1.0", CPU_POWERPC_750FX_v10, 0xFFFFFFFF, 750fx),
4615 /* PowerPC 750FX v2.0 (G3 embedded) */
4616 POWERPC_DEF("750fx2.0", CPU_POWERPC_750FX_v20, 0xFFFFFFFF, 750fx),
4617 /* PowerPC 750FX v2.1 (G3 embedded) */
4618 POWERPC_DEF("750fx2.1", CPU_POWERPC_750FX_v21, 0xFFFFFFFF, 750fx),
4619 /* PowerPC 750FX v2.2 (G3 embedded) */
4620 POWERPC_DEF("750fx2.2", CPU_POWERPC_750FX_v22, 0xFFFFFFFF, 750fx),
4621 /* PowerPC 750FX v2.3 (G3 embedded) */
4622 POWERPC_DEF("750fx2.3", CPU_POWERPC_750FX_v23, 0xFFFFFFFF, 750fx),
4623 /* PowerPC 750GL (G3 embedded) */
4624 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 0xFFFFFFFF, 7x0),
4625 /* PowerPC 750GX (G3 embedded) */
4626 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 0xFFFFFFFF, 750fx),
4627 /* PowerPC 750GX v1.0 (G3 embedded) */
4628 POWERPC_DEF("750gx1.0", CPU_POWERPC_750GX_v10, 0xFFFFFFFF, 750fx),
4629 /* PowerPC 750GX v1.1 (G3 embedded) */
4630 POWERPC_DEF("750gx1.1", CPU_POWERPC_750GX_v11, 0xFFFFFFFF, 750fx),
4631 /* PowerPC 750GX v1.2 (G3 embedded) */
4632 POWERPC_DEF("750gx1.2", CPU_POWERPC_750GX_v12, 0xFFFFFFFF, 750fx),
4633 /* PowerPC 750L (G3 embedded) */
4634 POWERPC_DEF("750l", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0),
4635 /* Code name for PowerPC 750L (G3 embedded) */
4636 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0),
4637 /* PowerPC 750L v2.2 (G3 embedded) */
4638 POWERPC_DEF("750l2.2", CPU_POWERPC_750L_v22, 0xFFFFFFFF, 7x0),
4639 /* PowerPC 750L v3.0 (G3 embedded) */
4640 POWERPC_DEF("750l3.0", CPU_POWERPC_750L_v30, 0xFFFFFFFF, 7x0),
4641 /* PowerPC 750L v3.2 (G3 embedded) */
4642 POWERPC_DEF("750l3.2", CPU_POWERPC_750L_v32, 0xFFFFFFFF, 7x0),
4643 /* Generic PowerPC 745 */
4644 POWERPC_DEF("745", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
4645 /* Generic PowerPC 755 */
4646 POWERPC_DEF("755", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
4647 /* Code name for PowerPC 745/755 */
4648 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
4649 /* PowerPC 745 v1.0 */
4650 POWERPC_DEF("745v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5),
4651 /* PowerPC 755 v1.0 */
4652 POWERPC_DEF("755v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5),
4653 /* PowerPC 745 v1.1 */
4654 POWERPC_DEF("745v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5),
4655 /* PowerPC 755 v1.1 */
4656 POWERPC_DEF("755v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5),
4657 /* PowerPC 745 v2.0 */
4658 POWERPC_DEF("745v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5),
4659 /* PowerPC 755 v2.0 */
4660 POWERPC_DEF("755v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5),
4661 /* PowerPC 745 v2.1 */
4662 POWERPC_DEF("745v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5),
4663 /* PowerPC 755 v2.1 */
4664 POWERPC_DEF("755v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5),
4665 /* PowerPC 745 v2.2 */
4666 POWERPC_DEF("745v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5),
4667 /* PowerPC 755 v2.2 */
4668 POWERPC_DEF("755v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5),
4669 /* PowerPC 745 v2.3 */
4670 POWERPC_DEF("745v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5),
4671 /* PowerPC 755 v2.3 */
4672 POWERPC_DEF("755v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5),
4673 /* PowerPC 745 v2.4 */
4674 POWERPC_DEF("745v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5),
4675 /* PowerPC 755 v2.4 */
4676 POWERPC_DEF("755v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5),
4677 /* PowerPC 745 v2.5 */
4678 POWERPC_DEF("745v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5),
4679 /* PowerPC 755 v2.5 */
4680 POWERPC_DEF("755v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5),
4681 /* PowerPC 745 v2.6 */
4682 POWERPC_DEF("745v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5),
4683 /* PowerPC 755 v2.6 */
4684 POWERPC_DEF("755v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5),
4685 /* PowerPC 745 v2.7 */
4686 POWERPC_DEF("745v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5),
4687 /* PowerPC 755 v2.7 */
4688 POWERPC_DEF("755v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5),
4689 /* PowerPC 745 v2.8 */
4690 POWERPC_DEF("745v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5),
4691 /* PowerPC 755 v2.8 */
4692 POWERPC_DEF("755v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5),
4693 #if defined (TODO)
4694 /* PowerPC 745P (G3) */
4695 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5),
4696 /* PowerPC 755P (G3) */
4697 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5),
4698 #endif
4699 /* PowerPC 74xx family */
4700 /* PowerPC 7400 (G4) */
4701 POWERPC_DEF("7400", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
4702 /* Code name for PowerPC 7400 */
4703 POWERPC_DEF("Max", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
4704 /* PowerPC 74xx is also well known as G4 */
4705 POWERPC_DEF("G4", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
4706 /* PowerPC 7400 v1.0 (G4) */
4707 POWERPC_DEF("7400v1.0", CPU_POWERPC_7400_v10, 0xFFFFFFFF, 7400),
4708 /* PowerPC 7400 v1.1 (G4) */
4709 POWERPC_DEF("7400v1.1", CPU_POWERPC_7400_v11, 0xFFFFFFFF, 7400),
4710 /* PowerPC 7400 v2.0 (G4) */
4711 POWERPC_DEF("7400v2.0", CPU_POWERPC_7400_v20, 0xFFFFFFFF, 7400),
4712 /* PowerPC 7400 v2.2 (G4) */
4713 POWERPC_DEF("7400v2.2", CPU_POWERPC_7400_v22, 0xFFFFFFFF, 7400),
4714 /* PowerPC 7400 v2.6 (G4) */
4715 POWERPC_DEF("7400v2.6", CPU_POWERPC_7400_v26, 0xFFFFFFFF, 7400),
4716 /* PowerPC 7400 v2.7 (G4) */
4717 POWERPC_DEF("7400v2.7", CPU_POWERPC_7400_v27, 0xFFFFFFFF, 7400),
4718 /* PowerPC 7400 v2.8 (G4) */
4719 POWERPC_DEF("7400v2.8", CPU_POWERPC_7400_v28, 0xFFFFFFFF, 7400),
4720 /* PowerPC 7400 v2.9 (G4) */
4721 POWERPC_DEF("7400v2.9", CPU_POWERPC_7400_v29, 0xFFFFFFFF, 7400),
4722 /* PowerPC 7410 (G4) */
4723 POWERPC_DEF("7410", CPU_POWERPC_7410, 0xFFFFFFFF, 7410),
4724 /* Code name for PowerPC 7410 */
4725 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 0xFFFFFFFF, 7410),
4726 /* PowerPC 7410 v1.0 (G4) */
4727 POWERPC_DEF("7410v1.0", CPU_POWERPC_7410_v10, 0xFFFFFFFF, 7410),
4728 /* PowerPC 7410 v1.1 (G4) */
4729 POWERPC_DEF("7410v1.1", CPU_POWERPC_7410_v11, 0xFFFFFFFF, 7410),
4730 /* PowerPC 7410 v1.2 (G4) */
4731 POWERPC_DEF("7410v1.2", CPU_POWERPC_7410_v12, 0xFFFFFFFF, 7410),
4732 /* PowerPC 7410 v1.3 (G4) */
4733 POWERPC_DEF("7410v1.3", CPU_POWERPC_7410_v13, 0xFFFFFFFF, 7410),
4734 /* PowerPC 7410 v1.4 (G4) */
4735 POWERPC_DEF("7410v1.4", CPU_POWERPC_7410_v14, 0xFFFFFFFF, 7410),
4736 /* PowerPC 7448 (G4) */
4737 POWERPC_DEF("7448", CPU_POWERPC_7448, 0xFFFFFFFF, 7400),
4738 /* PowerPC 7448 v1.0 (G4) */
4739 POWERPC_DEF("7448v1.0", CPU_POWERPC_7448_v10, 0xFFFFFFFF, 7400),
4740 /* PowerPC 7448 v1.1 (G4) */
4741 POWERPC_DEF("7448v1.1", CPU_POWERPC_7448_v11, 0xFFFFFFFF, 7400),
4742 /* PowerPC 7448 v2.0 (G4) */
4743 POWERPC_DEF("7448v2.0", CPU_POWERPC_7448_v20, 0xFFFFFFFF, 7400),
4744 /* PowerPC 7448 v2.1 (G4) */
4745 POWERPC_DEF("7448v2.1", CPU_POWERPC_7448_v21, 0xFFFFFFFF, 7400),
4746 #if defined (TODO)
4747 /* PowerPC 7450 (G4) */
4748 POWERPC_DEF("7450", CPU_POWERPC_7450, 0xFFFFFFFF, 7450),
4749 /* Code name for PowerPC 7450 */
4750 POWERPC_DEF("Vger", CPU_POWERPC_7450, 0xFFFFFFFF, 7450),
4751 #endif
4752 #if defined (TODO)
4753 /* PowerPC 7450 v1.0 (G4) */
4754 POWERPC_DEF("7450v1.0", CPU_POWERPC_7450_v10, 0xFFFFFFFF, 7450),
4755 #endif
4756 #if defined (TODO)
4757 /* PowerPC 7450 v1.1 (G4) */
4758 POWERPC_DEF("7450v1.1", CPU_POWERPC_7450_v11, 0xFFFFFFFF, 7450),
4759 #endif
4760 #if defined (TODO)
4761 /* PowerPC 7450 v1.2 (G4) */
4762 POWERPC_DEF("7450v1.2", CPU_POWERPC_7450_v12, 0xFFFFFFFF, 7450),
4763 #endif
4764 #if defined (TODO)
4765 /* PowerPC 7450 v2.0 (G4) */
4766 POWERPC_DEF("7450v2.0", CPU_POWERPC_7450_v20, 0xFFFFFFFF, 7450),
4767 #endif
4768 #if defined (TODO)
4769 /* PowerPC 7450 v2.1 (G4) */
4770 POWERPC_DEF("7450v2.1", CPU_POWERPC_7450_v21, 0xFFFFFFFF, 7450),
4771 #endif
4772 #if defined (TODO)
4773 /* PowerPC 7441 (G4) */
4774 POWERPC_DEF("7441", CPU_POWERPC_74x1, 0xFFFFFFFF, 7440),
4775 /* PowerPC 7451 (G4) */
4776 POWERPC_DEF("7451", CPU_POWERPC_74x1, 0xFFFFFFFF, 7450),
4777 #endif
4778 #if defined (TODO)
4779 /* PowerPC 7441g (G4) */
4780 POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7440),
4781 /* PowerPC 7451g (G4) */
4782 POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7450),
4783 #endif
4784 #if defined (TODO)
4785 /* PowerPC 7445 (G4) */
4786 POWERPC_DEF("7445", CPU_POWERPC_74x5, 0xFFFFFFFF, 7445),
4787 /* PowerPC 7455 (G4) */
4788 POWERPC_DEF("7455", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455),
4789 /* Code name for PowerPC 7445/7455 */
4790 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455),
4791 #endif
4792 #if defined (TODO)
4793 /* PowerPC 7445 v1.0 (G4) */
4794 POWERPC_DEF("7445v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7445),
4795 /* PowerPC 7455 v1.0 (G4) */
4796 POWERPC_DEF("7455v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7455),
4797 #endif
4798 #if defined (TODO)
4799 /* PowerPC 7445 v2.1 (G4) */
4800 POWERPC_DEF("7445v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7445),
4801 /* PowerPC 7455 v2.1 (G4) */
4802 POWERPC_DEF("7455v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7455),
4803 #endif
4804 #if defined (TODO)
4805 /* PowerPC 7445 v3.2 (G4) */
4806 POWERPC_DEF("7445v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7445),
4807 /* PowerPC 7455 v3.2 (G4) */
4808 POWERPC_DEF("7455v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7455),
4809 #endif
4810 #if defined (TODO)
4811 /* PowerPC 7445 v3.3 (G4) */
4812 POWERPC_DEF("7445v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7445),
4813 /* PowerPC 7455 v3.3 (G4) */
4814 POWERPC_DEF("7455v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7455),
4815 #endif
4816 #if defined (TODO)
4817 /* PowerPC 7445 v3.4 (G4) */
4818 POWERPC_DEF("7445v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7445),
4819 /* PowerPC 7455 v3.4 (G4) */
4820 POWERPC_DEF("7455v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7455),
4821 #endif
4822 #if defined (TODO)
4823 /* PowerPC 7447 (G4) */
4824 POWERPC_DEF("7447", CPU_POWERPC_74x7, 0xFFFFFFFF, 7445),
4825 /* PowerPC 7457 (G4) */
4826 POWERPC_DEF("7457", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455),
4827 /* Code name for PowerPC 7447/7457 */
4828 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455),
4829 #endif
4830 #if defined (TODO)
4831 /* PowerPC 7447 v1.0 (G4) */
4832 POWERPC_DEF("7447v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7445),
4833 /* PowerPC 7457 v1.0 (G4) */
4834 POWERPC_DEF("7457v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455),
4835 /* Code name for PowerPC 7447A/7457A */
4836 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455),
4837 #endif
4838 #if defined (TODO)
4839 /* PowerPC 7447 v1.1 (G4) */
4840 POWERPC_DEF("7447v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7445),
4841 /* PowerPC 7457 v1.1 (G4) */
4842 POWERPC_DEF("7457v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7455),
4843 #endif
4844 #if defined (TODO)
4845 /* PowerPC 7447 v1.2 (G4) */
4846 POWERPC_DEF("7447v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7445),
4847 /* PowerPC 7457 v1.2 (G4) */
4848 POWERPC_DEF("7457v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7455),
4849 #endif
4850 /* 64 bits PowerPC */
4851 #if defined (TARGET_PPC64)
4852 #if defined (TODO)
4853 /* PowerPC 620 */
4854 POWERPC_DEF("620", CPU_POWERPC_620, 0xFFFFFFFF, 620),
4855 #endif
4856 #if defined (TODO)
4857 /* PowerPC 630 (POWER3) */
4858 POWERPC_DEF("630", CPU_POWERPC_630, 0xFFFFFFFF, 630),
4859 POWERPC_DEF("POWER3", CPU_POWERPC_630, 0xFFFFFFFF, 630),
4860 #endif
4861 #if defined (TODO)
4862 /* PowerPC 631 (Power 3+) */
4863 POWERPC_DEF("631", CPU_POWERPC_631, 0xFFFFFFFF, 631),
4864 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 0xFFFFFFFF, 631),
4865 #endif
4866 #if defined (TODO)
4867 /* POWER4 */
4868 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, 0xFFFFFFFF, POWER4),
4869 #endif
4870 #if defined (TODO)
4871 /* POWER4p */
4872 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, 0xFFFFFFFF, POWER4P),
4873 #endif
4874 #if defined (TODO)
4875 /* POWER5 */
4876 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, 0xFFFFFFFF, POWER5),
4877 /* POWER5GR */
4878 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, 0xFFFFFFFF, POWER5),
4879 #endif
4880 #if defined (TODO)
4881 /* POWER5+ */
4882 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, 0xFFFFFFFF, POWER5P),
4883 /* POWER5GS */
4884 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, 0xFFFFFFFF, POWER5P),
4885 #endif
4886 #if defined (TODO)
4887 /* POWER6 */
4888 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, 0xFFFFFFFF, POWER6),
4889 /* POWER6 running in POWER5 mode */
4890 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, 0xFFFFFFFF, POWER5),
4891 /* POWER6A */
4892 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, 0xFFFFFFFF, POWER6),
4893 #endif
4894 /* PowerPC 970 */
4895 POWERPC_DEF("970", CPU_POWERPC_970, 0xFFFFFFFF, 970),
4896 /* PowerPC 970FX (G5) */
4897 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 0xFFFFFFFF, 970FX),
4898 /* PowerPC 970FX v1.0 (G5) */
4899 POWERPC_DEF("970fx1.0", CPU_POWERPC_970FX_v10, 0xFFFFFFFF, 970FX),
4900 /* PowerPC 970FX v2.0 (G5) */
4901 POWERPC_DEF("970fx2.0", CPU_POWERPC_970FX_v20, 0xFFFFFFFF, 970FX),
4902 /* PowerPC 970FX v2.1 (G5) */
4903 POWERPC_DEF("970fx2.1", CPU_POWERPC_970FX_v21, 0xFFFFFFFF, 970FX),
4904 /* PowerPC 970FX v3.0 (G5) */
4905 POWERPC_DEF("970fx3.0", CPU_POWERPC_970FX_v30, 0xFFFFFFFF, 970FX),
4906 /* PowerPC 970FX v3.1 (G5) */
4907 POWERPC_DEF("970fx3.1", CPU_POWERPC_970FX_v31, 0xFFFFFFFF, 970FX),
4908 /* PowerPC 970GX (G5) */
4909 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 0xFFFFFFFF, 970GX),
4910 /* PowerPC 970MP */
4911 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 0xFFFFFFFF, 970),
4912 /* PowerPC 970MP v1.0 */
4913 POWERPC_DEF("970mp1.0", CPU_POWERPC_970MP_v10, 0xFFFFFFFF, 970),
4914 /* PowerPC 970MP v1.1 */
4915 POWERPC_DEF("970mp1.1", CPU_POWERPC_970MP_v11, 0xFFFFFFFF, 970),
4916 #if defined (TODO)
4917 /* PowerPC Cell */
4918 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 0xFFFFFFFF, 970),
4919 #endif
4920 #if defined (TODO)
4921 /* PowerPC Cell v1.0 */
4922 POWERPC_DEF("Cell1.0", CPU_POWERPC_CELL_v10, 0xFFFFFFFF, 970),
4923 #endif
4924 #if defined (TODO)
4925 /* PowerPC Cell v2.0 */
4926 POWERPC_DEF("Cell2.0", CPU_POWERPC_CELL_v20, 0xFFFFFFFF, 970),
4927 #endif
4928 #if defined (TODO)
4929 /* PowerPC Cell v3.0 */
4930 POWERPC_DEF("Cell3.0", CPU_POWERPC_CELL_v30, 0xFFFFFFFF, 970),
4931 #endif
4932 #if defined (TODO)
4933 /* PowerPC Cell v3.1 */
4934 POWERPC_DEF("Cell3.1", CPU_POWERPC_CELL_v31, 0xFFFFFFFF, 970),
4935 #endif
4936 #if defined (TODO)
4937 /* PowerPC Cell v3.2 */
4938 POWERPC_DEF("Cell3.2", CPU_POWERPC_CELL_v32, 0xFFFFFFFF, 970),
4939 #endif
4940 #if defined (TODO)
4941 /* RS64 (Apache/A35) */
4942 /* This one seems to support the whole POWER2 instruction set
4943 * and the PowerPC 64 one.
4944 */
4945 /* What about A10 & A30 ? */
4946 POWERPC_DEF("RS64", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
4947 POWERPC_DEF("Apache", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
4948 POWERPC_DEF("A35", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
4949 #endif
4950 #if defined (TODO)
4951 /* RS64-II (NorthStar/A50) */
4952 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
4953 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
4954 POWERPC_DEF("A50", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
4955 #endif
4956 #if defined (TODO)
4957 /* RS64-III (Pulsar) */
4958 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64),
4959 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64),
4960 #endif
4961 #if defined (TODO)
4962 /* RS64-IV (IceStar/IStar/SStar) */
4963 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
4964 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
4965 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
4966 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
4967 #endif
4968 #endif /* defined (TARGET_PPC64) */
4969 /* POWER */
4970 #if defined (TODO)
4971 /* Original POWER */
4972 POWERPC_DEF("POWER", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
4973 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
4974 POWERPC_DEF("RSC", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
4975 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
4976 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
4977 #endif
4978 #if defined (TODO)
4979 /* POWER2 */
4980 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
4981 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
4982 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
4983 #endif
4984 /* PA semi cores */
4985 #if defined (TODO)
4986 /* PA PA6T */
4987 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, 0xFFFFFFFF, PA6T),
4988 #endif
4989 /* Generic PowerPCs */
4990 #if defined (TARGET_PPC64)
4991 #if defined (TODO)
4992 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, 0xFFFFFFFF, PPC64),
4993 #endif
4994 #endif
4995 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, 0xFFFFFFFF, PPC32),
4996 /* Fallback */
4997 POWERPC_DEF("ppc", CPU_POWERPC_PPC, 0xFFFFFFFF, PPC_GENERIC),
4998 };
4999
5000 /*****************************************************************************/
5001 /* Generic CPU instanciation routine */
5002 static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
5003 {
5004 #if !defined(CONFIG_USER_ONLY)
5005 env->irq_inputs = NULL;
5006 #endif
5007 /* Default MMU definitions */
5008 env->nb_BATs = 0;
5009 env->nb_tlb = 0;
5010 env->nb_ways = 0;
5011 /* Register SPR common to all PowerPC implementations */
5012 gen_spr_generic(env);
5013 spr_register(env, SPR_PVR, "PVR",
5014 SPR_NOACCESS, SPR_NOACCESS,
5015 &spr_read_generic, SPR_NOACCESS,
5016 def->pvr);
5017 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
5018 (*def->init_proc)(env);
5019 /* Allocate TLBs buffer when needed */
5020 if (env->nb_tlb != 0) {
5021 int nb_tlb = env->nb_tlb;
5022 if (env->id_tlbs != 0)
5023 nb_tlb *= 2;
5024 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
5025 /* Pre-compute some useful values */
5026 env->tlb_per_way = env->nb_tlb / env->nb_ways;
5027 }
5028 #if !defined(CONFIG_USER_ONLY)
5029 if (env->irq_inputs == NULL) {
5030 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
5031 " Attempt Qemu to crash very soon !\n");
5032 }
5033 #endif
5034 }
5035
5036 #if defined(PPC_DUMP_CPU)
5037 static void dump_ppc_sprs (CPUPPCState *env)
5038 {
5039 ppc_spr_t *spr;
5040 #if !defined(CONFIG_USER_ONLY)
5041 uint32_t sr, sw;
5042 #endif
5043 uint32_t ur, uw;
5044 int i, j, n;
5045
5046 printf("Special purpose registers:\n");
5047 for (i = 0; i < 32; i++) {
5048 for (j = 0; j < 32; j++) {
5049 n = (i << 5) | j;
5050 spr = &env->spr_cb[n];
5051 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
5052 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
5053 #if !defined(CONFIG_USER_ONLY)
5054 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
5055 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
5056 if (sw || sr || uw || ur) {
5057 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
5058 (i << 5) | j, (i << 5) | j, spr->name,
5059 sw ? 'w' : '-', sr ? 'r' : '-',
5060 uw ? 'w' : '-', ur ? 'r' : '-');
5061 }
5062 #else
5063 if (uw || ur) {
5064 printf("SPR: %4d (%03x) %-8s u%c%c\n",
5065 (i << 5) | j, (i << 5) | j, spr->name,
5066 uw ? 'w' : '-', ur ? 'r' : '-');
5067 }
5068 #endif
5069 }
5070 }
5071 fflush(stdout);
5072 fflush(stderr);
5073 }
5074 #endif
5075
5076 /*****************************************************************************/
5077 #include <stdlib.h>
5078 #include <string.h>
5079
5080 int fflush (FILE *stream);
5081
5082 /* Opcode types */
5083 enum {
5084 PPC_DIRECT = 0, /* Opcode routine */
5085 PPC_INDIRECT = 1, /* Indirect opcode table */
5086 };
5087
5088 static inline int is_indirect_opcode (void *handler)
5089 {
5090 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
5091 }
5092
5093 static inline opc_handler_t **ind_table(void *handler)
5094 {
5095 return (opc_handler_t **)((unsigned long)handler & ~3);
5096 }
5097
5098 /* Instruction table creation */
5099 /* Opcodes tables creation */
5100 static void fill_new_table (opc_handler_t **table, int len)
5101 {
5102 int i;
5103
5104 for (i = 0; i < len; i++)
5105 table[i] = &invalid_handler;
5106 }
5107
5108 static int create_new_table (opc_handler_t **table, unsigned char idx)
5109 {
5110 opc_handler_t **tmp;
5111
5112 tmp = malloc(0x20 * sizeof(opc_handler_t));
5113 if (tmp == NULL)
5114 return -1;
5115 fill_new_table(tmp, 0x20);
5116 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
5117
5118 return 0;
5119 }
5120
5121 static int insert_in_table (opc_handler_t **table, unsigned char idx,
5122 opc_handler_t *handler)
5123 {
5124 if (table[idx] != &invalid_handler)
5125 return -1;
5126 table[idx] = handler;
5127
5128 return 0;
5129 }
5130
5131 static int register_direct_insn (opc_handler_t **ppc_opcodes,
5132 unsigned char idx, opc_handler_t *handler)
5133 {
5134 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
5135 printf("*** ERROR: opcode %02x already assigned in main "
5136 "opcode table\n", idx);
5137 return -1;
5138 }
5139
5140 return 0;
5141 }
5142
5143 static int register_ind_in_table (opc_handler_t **table,
5144 unsigned char idx1, unsigned char idx2,
5145 opc_handler_t *handler)
5146 {
5147 if (table[idx1] == &invalid_handler) {
5148 if (create_new_table(table, idx1) < 0) {
5149 printf("*** ERROR: unable to create indirect table "
5150 "idx=%02x\n", idx1);
5151 return -1;
5152 }
5153 } else {
5154 if (!is_indirect_opcode(table[idx1])) {
5155 printf("*** ERROR: idx %02x already assigned to a direct "
5156 "opcode\n", idx1);
5157 return -1;
5158 }
5159 }
5160 if (handler != NULL &&
5161 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
5162 printf("*** ERROR: opcode %02x already assigned in "
5163 "opcode table %02x\n", idx2, idx1);
5164 return -1;
5165 }
5166
5167 return 0;
5168 }
5169
5170 static int register_ind_insn (opc_handler_t **ppc_opcodes,
5171 unsigned char idx1, unsigned char idx2,
5172 opc_handler_t *handler)
5173 {
5174 int ret;
5175
5176 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
5177
5178 return ret;
5179 }
5180
5181 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
5182 unsigned char idx1, unsigned char idx2,
5183 unsigned char idx3, opc_handler_t *handler)
5184 {
5185 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
5186 printf("*** ERROR: unable to join indirect table idx "
5187 "[%02x-%02x]\n", idx1, idx2);
5188 return -1;
5189 }
5190 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
5191 handler) < 0) {
5192 printf("*** ERROR: unable to insert opcode "
5193 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
5194 return -1;
5195 }
5196
5197 return 0;
5198 }
5199
5200 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
5201 {
5202 if (insn->opc2 != 0xFF) {
5203 if (insn->opc3 != 0xFF) {
5204 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
5205 insn->opc3, &insn->handler) < 0)
5206 return -1;
5207 } else {
5208 if (register_ind_insn(ppc_opcodes, insn->opc1,
5209 insn->opc2, &insn->handler) < 0)
5210 return -1;
5211 }
5212 } else {
5213 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
5214 return -1;
5215 }
5216
5217 return 0;
5218 }
5219
5220 static int test_opcode_table (opc_handler_t **table, int len)
5221 {
5222 int i, count, tmp;
5223
5224 for (i = 0, count = 0; i < len; i++) {
5225 /* Consistency fixup */
5226 if (table[i] == NULL)
5227 table[i] = &invalid_handler;
5228 if (table[i] != &invalid_handler) {
5229 if (is_indirect_opcode(table[i])) {
5230 tmp = test_opcode_table(ind_table(table[i]), 0x20);
5231 if (tmp == 0) {
5232 free(table[i]);
5233 table[i] = &invalid_handler;
5234 } else {
5235 count++;
5236 }
5237 } else {
5238 count++;
5239 }
5240 }
5241 }
5242
5243 return count;
5244 }
5245
5246 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
5247 {
5248 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
5249 printf("*** WARNING: no opcode defined !\n");
5250 }
5251
5252 /*****************************************************************************/
5253 static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def)
5254 {
5255 opcode_t *opc, *start, *end;
5256
5257 fill_new_table(env->opcodes, 0x40);
5258 if (&opc_start < &opc_end) {
5259 start = &opc_start;
5260 end = &opc_end;
5261 } else {
5262 start = &opc_end;
5263 end = &opc_start;
5264 }
5265 for (opc = start + 1; opc != end; opc++) {
5266 if ((opc->handler.type & def->insns_flags) != 0) {
5267 if (register_insn(env->opcodes, opc) < 0) {
5268 printf("*** ERROR initializing PowerPC instruction "
5269 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
5270 opc->opc3);
5271 return -1;
5272 }
5273 }
5274 }
5275 fix_opcode_tables(env->opcodes);
5276 fflush(stdout);
5277 fflush(stderr);
5278
5279 return 0;
5280 }
5281
5282 #if defined(PPC_DUMP_CPU)
5283 static int dump_ppc_insns (CPUPPCState *env)
5284 {
5285 opc_handler_t **table, *handler;
5286 uint8_t opc1, opc2, opc3;
5287
5288 printf("Instructions set:\n");
5289 /* opc1 is 6 bits long */
5290 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
5291 table = env->opcodes;
5292 handler = table[opc1];
5293 if (is_indirect_opcode(handler)) {
5294 /* opc2 is 5 bits long */
5295 for (opc2 = 0; opc2 < 0x20; opc2++) {
5296 table = env->opcodes;
5297 handler = env->opcodes[opc1];
5298 table = ind_table(handler);
5299 handler = table[opc2];
5300 if (is_indirect_opcode(handler)) {
5301 table = ind_table(handler);
5302 /* opc3 is 5 bits long */
5303 for (opc3 = 0; opc3 < 0x20; opc3++) {
5304 handler = table[opc3];
5305 if (handler->handler != &gen_invalid) {
5306 printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
5307 opc1, opc2, opc3, opc1, (opc3 << 5) | opc2,
5308 handler->oname);
5309 }
5310 }
5311 } else {
5312 if (handler->handler != &gen_invalid) {
5313 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
5314 opc1, opc2, opc1, opc2, handler->oname);
5315 }
5316 }
5317 }
5318 } else {
5319 if (handler->handler != &gen_invalid) {
5320 printf("INSN: %02x -- -- (%02d ----) : %s\n",
5321 opc1, opc1, handler->oname);
5322 }
5323 }
5324 }
5325 }
5326 #endif
5327
5328 int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
5329 {
5330 env->msr_mask = def->msr_mask;
5331 env->mmu_model = def->mmu_model;
5332 env->excp_model = def->excp_model;
5333 env->bus_model = def->bus_model;
5334 if (create_ppc_opcodes(env, def) < 0)
5335 return -1;
5336 init_ppc_proc(env, def);
5337 #if defined(PPC_DUMP_CPU)
5338 {
5339 const unsigned char *mmu_model, *excp_model, *bus_model;
5340 switch (env->mmu_model) {
5341 case POWERPC_MMU_32B:
5342 mmu_model = "PowerPC 32";
5343 break;
5344 case POWERPC_MMU_64B:
5345 mmu_model = "PowerPC 64";
5346 break;
5347 case POWERPC_MMU_601:
5348 mmu_model = "PowerPC 601";
5349 break;
5350 case POWERPC_MMU_SOFT_6xx:
5351 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
5352 break;
5353 case POWERPC_MMU_SOFT_74xx:
5354 mmu_model = "PowerPC 74xx with software driven TLBs";
5355 break;
5356 case POWERPC_MMU_SOFT_4xx:
5357 mmu_model = "PowerPC 4xx with software driven TLBs";
5358 break;
5359 case POWERPC_MMU_SOFT_4xx_Z:
5360 mmu_model = "PowerPC 4xx with software driven TLBs "
5361 "and zones protections";
5362 break;
5363 case POWERPC_MMU_REAL_4xx:
5364 mmu_model = "PowerPC 4xx real mode only";
5365 break;
5366 case POWERPC_MMU_BOOKE:
5367 mmu_model = "PowerPC BookE";
5368 break;
5369 case POWERPC_MMU_BOOKE_FSL:
5370 mmu_model = "PowerPC BookE FSL";
5371 break;
5372 case POWERPC_MMU_64BRIDGE:
5373 mmu_model = "PowerPC 64 bridge";
5374 break;
5375 default:
5376 mmu_model = "Unknown or invalid";
5377 break;
5378 }
5379 switch (env->excp_model) {
5380 case POWERPC_EXCP_STD:
5381 excp_model = "PowerPC";
5382 break;
5383 case POWERPC_EXCP_40x:
5384 excp_model = "PowerPC 40x";
5385 break;
5386 case POWERPC_EXCP_601:
5387 excp_model = "PowerPC 601";
5388 break;
5389 case POWERPC_EXCP_602:
5390 excp_model = "PowerPC 602";
5391 break;
5392 case POWERPC_EXCP_603:
5393 excp_model = "PowerPC 603";
5394 break;
5395 case POWERPC_EXCP_603E:
5396 excp_model = "PowerPC 603e";
5397 break;
5398 case POWERPC_EXCP_604:
5399 excp_model = "PowerPC 604";
5400 break;
5401 case POWERPC_EXCP_7x0:
5402 excp_model = "PowerPC 740/750";
5403 break;
5404 case POWERPC_EXCP_7x5:
5405 excp_model = "PowerPC 745/755";
5406 break;
5407 case POWERPC_EXCP_74xx:
5408 excp_model = "PowerPC 74xx";
5409 break;
5410 case POWERPC_EXCP_970:
5411 excp_model = "PowerPC 970";
5412 break;
5413 case POWERPC_EXCP_BOOKE:
5414 excp_model = "PowerPC BookE";
5415 break;
5416 default:
5417 excp_model = "Unknown or invalid";
5418 break;
5419 }
5420 switch (env->bus_model) {
5421 case PPC_FLAGS_INPUT_6xx:
5422 bus_model = "PowerPC 6xx";
5423 break;
5424 case PPC_FLAGS_INPUT_BookE:
5425 bus_model = "PowerPC BookE";
5426 break;
5427 case PPC_FLAGS_INPUT_405:
5428 bus_model = "PowerPC 405";
5429 break;
5430 case PPC_FLAGS_INPUT_970:
5431 bus_model = "PowerPC 970";
5432 break;
5433 case PPC_FLAGS_INPUT_401:
5434 bus_model = "PowerPC 401/403";
5435 break;
5436 default:
5437 bus_model = "Unknown or invalid";
5438 break;
5439 }
5440 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
5441 " MMU model : %s\n",
5442 def->name, def->pvr, def->msr_mask, mmu_model);
5443 if (env->tlb != NULL) {
5444 printf(" %d %s TLB in %d ways\n",
5445 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
5446 env->nb_ways);
5447 }
5448 printf(" Exceptions model : %s\n"
5449 " Bus model : %s\n",
5450 excp_model, bus_model);
5451 }
5452 dump_ppc_insns(env);
5453 dump_ppc_sprs(env);
5454 fflush(stdout);
5455 #endif
5456
5457 return 0;
5458 }
5459
5460 int ppc_find_by_name (const unsigned char *name, ppc_def_t **def)
5461 {
5462 int i, ret;
5463
5464 ret = -1;
5465 *def = NULL;
5466 for (i = 0; strcmp(ppc_defs[i].name, "ppc") != 0; i++) {
5467 if (strcasecmp(name, ppc_defs[i].name) == 0) {
5468 *def = &ppc_defs[i];
5469 ret = 0;
5470 break;
5471 }
5472 }
5473
5474 return ret;
5475 }
5476
5477 int ppc_find_by_pvr (uint32_t pvr, ppc_def_t **def)
5478 {
5479 int i, ret;
5480
5481 ret = -1;
5482 *def = NULL;
5483 for (i = 0; ppc_defs[i].name != NULL; i++) {
5484 if ((pvr & ppc_defs[i].pvr_mask) ==
5485 (ppc_defs[i].pvr & ppc_defs[i].pvr_mask)) {
5486 *def = &ppc_defs[i];
5487 ret = 0;
5488 break;
5489 }
5490 }
5491
5492 return ret;
5493 }
5494
5495 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
5496 {
5497 int i;
5498
5499 for (i = 0; ; i++) {
5500 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
5501 ppc_defs[i].name, ppc_defs[i].pvr);
5502 if (strcmp(ppc_defs[i].name, "ppc") == 0)
5503 break;
5504 }
5505 }
Qemu copy for testing