2 * PowerPC CPU initialization for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
28 //#define PPC_DUMP_CPU
29 //#define PPC_DEBUG_SPR
30 //#define PPC_DEBUG_IRQ
33 const unsigned char *name
;
43 void (*init_proc
)(CPUPPCState
*env
);
46 /* For user-mode emulation, we don't emulate any IRQ controller */
47 #if defined(CONFIG_USER_ONLY)
48 #define PPC_IRQ_INIT_FN(name) \
49 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
53 #define PPC_IRQ_INIT_FN(name) \
54 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
63 * do nothing but store/retrieve spr value
65 #ifdef PPC_DUMP_SPR_ACCESSES
66 static void spr_read_generic (void *opaque
, int sprn
)
68 gen_op_load_dump_spr(sprn
);
71 static void spr_write_generic (void *opaque
, int sprn
)
73 gen_op_store_dump_spr(sprn
);
76 static void spr_read_generic (void *opaque
, int sprn
)
78 gen_op_load_spr(sprn
);
81 static void spr_write_generic (void *opaque
, int sprn
)
83 gen_op_store_spr(sprn
);
87 #if !defined(CONFIG_USER_ONLY)
88 static void spr_write_clear (void *opaque
, int sprn
)
90 gen_op_mask_spr(sprn
);
94 /* SPR common to all PowerPC */
96 static void spr_read_xer (void *opaque
, int sprn
)
101 static void spr_write_xer (void *opaque
, int sprn
)
107 static void spr_read_lr (void *opaque
, int sprn
)
112 static void spr_write_lr (void *opaque
, int sprn
)
118 static void spr_read_ctr (void *opaque
, int sprn
)
123 static void spr_write_ctr (void *opaque
, int sprn
)
128 /* User read access to SPR */
134 static void spr_read_ureg (void *opaque
, int sprn
)
136 gen_op_load_spr(sprn
+ 0x10);
139 /* SPR common to all non-embedded PowerPC */
141 #if !defined(CONFIG_USER_ONLY)
142 static void spr_read_decr (void *opaque
, int sprn
)
147 static void spr_write_decr (void *opaque
, int sprn
)
153 /* SPR common to all non-embedded PowerPC, except 601 */
155 static void spr_read_tbl (void *opaque
, int sprn
)
160 static void spr_read_tbu (void *opaque
, int sprn
)
165 #if !defined(CONFIG_USER_ONLY)
166 static void spr_write_tbl (void *opaque
, int sprn
)
171 static void spr_write_tbu (void *opaque
, int sprn
)
177 #if !defined(CONFIG_USER_ONLY)
178 /* IBAT0U...IBAT0U */
179 /* IBAT0L...IBAT7L */
180 static void spr_read_ibat (void *opaque
, int sprn
)
182 gen_op_load_ibat(sprn
& 1, (sprn
- SPR_IBAT0U
) / 2);
185 static void spr_read_ibat_h (void *opaque
, int sprn
)
187 gen_op_load_ibat(sprn
& 1, (sprn
- SPR_IBAT4U
) / 2);
190 static void spr_write_ibatu (void *opaque
, int sprn
)
192 DisasContext
*ctx
= opaque
;
194 gen_op_store_ibatu((sprn
- SPR_IBAT0U
) / 2);
198 static void spr_write_ibatu_h (void *opaque
, int sprn
)
200 DisasContext
*ctx
= opaque
;
202 gen_op_store_ibatu((sprn
- SPR_IBAT4U
) / 2);
206 static void spr_write_ibatl (void *opaque
, int sprn
)
208 DisasContext
*ctx
= opaque
;
210 gen_op_store_ibatl((sprn
- SPR_IBAT0L
) / 2);
214 static void spr_write_ibatl_h (void *opaque
, int sprn
)
216 DisasContext
*ctx
= opaque
;
218 gen_op_store_ibatl((sprn
- SPR_IBAT4L
) / 2);
222 /* DBAT0U...DBAT7U */
223 /* DBAT0L...DBAT7L */
224 static void spr_read_dbat (void *opaque
, int sprn
)
226 gen_op_load_dbat(sprn
& 1, (sprn
- SPR_DBAT0U
) / 2);
229 static void spr_read_dbat_h (void *opaque
, int sprn
)
231 gen_op_load_dbat(sprn
& 1, (sprn
- SPR_DBAT4U
) / 2);
234 static void spr_write_dbatu (void *opaque
, int sprn
)
236 DisasContext
*ctx
= opaque
;
238 gen_op_store_dbatu((sprn
- SPR_DBAT0U
) / 2);
242 static void spr_write_dbatu_h (void *opaque
, int sprn
)
244 DisasContext
*ctx
= opaque
;
246 gen_op_store_dbatu((sprn
- SPR_DBAT4U
) / 2);
250 static void spr_write_dbatl (void *opaque
, int sprn
)
252 DisasContext
*ctx
= opaque
;
254 gen_op_store_dbatl((sprn
- SPR_DBAT0L
) / 2);
258 static void spr_write_dbatl_h (void *opaque
, int sprn
)
260 DisasContext
*ctx
= opaque
;
262 gen_op_store_dbatl((sprn
- SPR_DBAT4L
) / 2);
267 static void spr_read_sdr1 (void *opaque
, int sprn
)
272 static void spr_write_sdr1 (void *opaque
, int sprn
)
274 DisasContext
*ctx
= opaque
;
280 /* 64 bits PowerPC specific SPRs */
282 /* Currently unused */
283 #if 0 && defined(TARGET_PPC64)
284 static void spr_read_asr (void *opaque
, int sprn
)
289 static void spr_write_asr (void *opaque
, int sprn
)
291 DisasContext
*ctx
= opaque
;
299 /* PowerPC 601 specific registers */
301 static void spr_read_601_rtcl (void *opaque
, int sprn
)
303 gen_op_load_601_rtcl();
306 static void spr_read_601_rtcu (void *opaque
, int sprn
)
308 gen_op_load_601_rtcu();
311 #if !defined(CONFIG_USER_ONLY)
312 static void spr_write_601_rtcu (void *opaque
, int sprn
)
314 gen_op_store_601_rtcu();
317 static void spr_write_601_rtcl (void *opaque
, int sprn
)
319 gen_op_store_601_rtcl();
324 #if !defined(CONFIG_USER_ONLY)
325 static void spr_read_601_ubat (void *opaque
, int sprn
)
327 gen_op_load_601_bat(sprn
& 1, (sprn
- SPR_IBAT0U
) / 2);
330 static void spr_write_601_ubatu (void *opaque
, int sprn
)
332 DisasContext
*ctx
= opaque
;
334 gen_op_store_601_batu((sprn
- SPR_IBAT0U
) / 2);
338 static void spr_write_601_ubatl (void *opaque
, int sprn
)
340 DisasContext
*ctx
= opaque
;
342 gen_op_store_601_batl((sprn
- SPR_IBAT0L
) / 2);
347 /* PowerPC 40x specific registers */
348 #if !defined(CONFIG_USER_ONLY)
349 static void spr_read_40x_pit (void *opaque
, int sprn
)
351 gen_op_load_40x_pit();
354 static void spr_write_40x_pit (void *opaque
, int sprn
)
356 gen_op_store_40x_pit();
359 static void spr_write_40x_dbcr0 (void *opaque
, int sprn
)
361 DisasContext
*ctx
= opaque
;
363 gen_op_store_40x_dbcr0();
364 /* We must stop translation as we may have rebooted */
368 static void spr_write_40x_sler (void *opaque
, int sprn
)
370 DisasContext
*ctx
= opaque
;
372 gen_op_store_40x_sler();
373 /* We must stop the translation as we may have changed
374 * some regions endianness
379 static void spr_write_booke_tcr (void *opaque
, int sprn
)
381 gen_op_store_booke_tcr();
384 static void spr_write_booke_tsr (void *opaque
, int sprn
)
386 gen_op_store_booke_tsr();
390 /* PowerPC 403 specific registers */
391 /* PBL1 / PBU1 / PBL2 / PBU2 */
392 #if !defined(CONFIG_USER_ONLY)
393 static void spr_read_403_pbr (void *opaque
, int sprn
)
395 gen_op_load_403_pb(sprn
- SPR_403_PBL1
);
398 static void spr_write_403_pbr (void *opaque
, int sprn
)
400 DisasContext
*ctx
= opaque
;
402 gen_op_store_403_pb(sprn
- SPR_403_PBL1
);
406 static void spr_write_pir (void *opaque
, int sprn
)
412 #if defined(CONFIG_USER_ONLY)
413 #define spr_register(env, num, name, uea_read, uea_write, \
414 oea_read, oea_write, initial_value) \
416 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
418 static inline void _spr_register (CPUPPCState
*env
, int num
,
419 const unsigned char *name
,
420 void (*uea_read
)(void *opaque
, int sprn
),
421 void (*uea_write
)(void *opaque
, int sprn
),
422 target_ulong initial_value
)
424 static inline void spr_register (CPUPPCState
*env
, int num
,
425 const unsigned char *name
,
426 void (*uea_read
)(void *opaque
, int sprn
),
427 void (*uea_write
)(void *opaque
, int sprn
),
428 void (*oea_read
)(void *opaque
, int sprn
),
429 void (*oea_write
)(void *opaque
, int sprn
),
430 target_ulong initial_value
)
435 spr
= &env
->spr_cb
[num
];
436 if (spr
->name
!= NULL
||env
-> spr
[num
] != 0x00000000 ||
437 #if !defined(CONFIG_USER_ONLY)
438 spr
->oea_read
!= NULL
|| spr
->oea_write
!= NULL
||
440 spr
->uea_read
!= NULL
|| spr
->uea_write
!= NULL
) {
441 printf("Error: Trying to register SPR %d (%03x) twice !\n", num
, num
);
444 #if defined(PPC_DEBUG_SPR)
445 printf("*** register spr %d (%03x) %s val " ADDRX
"\n", num
, num
, name
,
449 spr
->uea_read
= uea_read
;
450 spr
->uea_write
= uea_write
;
451 #if !defined(CONFIG_USER_ONLY)
452 spr
->oea_read
= oea_read
;
453 spr
->oea_write
= oea_write
;
455 env
->spr
[num
] = initial_value
;
458 /* Generic PowerPC SPRs */
459 static void gen_spr_generic (CPUPPCState
*env
)
461 /* Integer processing */
462 spr_register(env
, SPR_XER
, "XER",
463 &spr_read_xer
, &spr_write_xer
,
464 &spr_read_xer
, &spr_write_xer
,
467 spr_register(env
, SPR_LR
, "LR",
468 &spr_read_lr
, &spr_write_lr
,
469 &spr_read_lr
, &spr_write_lr
,
471 spr_register(env
, SPR_CTR
, "CTR",
472 &spr_read_ctr
, &spr_write_ctr
,
473 &spr_read_ctr
, &spr_write_ctr
,
475 /* Interrupt processing */
476 spr_register(env
, SPR_SRR0
, "SRR0",
477 SPR_NOACCESS
, SPR_NOACCESS
,
478 &spr_read_generic
, &spr_write_generic
,
480 spr_register(env
, SPR_SRR1
, "SRR1",
481 SPR_NOACCESS
, SPR_NOACCESS
,
482 &spr_read_generic
, &spr_write_generic
,
484 /* Processor control */
485 spr_register(env
, SPR_SPRG0
, "SPRG0",
486 SPR_NOACCESS
, SPR_NOACCESS
,
487 &spr_read_generic
, &spr_write_generic
,
489 spr_register(env
, SPR_SPRG1
, "SPRG1",
490 SPR_NOACCESS
, SPR_NOACCESS
,
491 &spr_read_generic
, &spr_write_generic
,
493 spr_register(env
, SPR_SPRG2
, "SPRG2",
494 SPR_NOACCESS
, SPR_NOACCESS
,
495 &spr_read_generic
, &spr_write_generic
,
497 spr_register(env
, SPR_SPRG3
, "SPRG3",
498 SPR_NOACCESS
, SPR_NOACCESS
,
499 &spr_read_generic
, &spr_write_generic
,
503 /* SPR common to all non-embedded PowerPC, including 601 */
504 static void gen_spr_ne_601 (CPUPPCState
*env
)
506 /* Exception processing */
507 spr_register(env
, SPR_DSISR
, "DSISR",
508 SPR_NOACCESS
, SPR_NOACCESS
,
509 &spr_read_generic
, &spr_write_generic
,
511 spr_register(env
, SPR_DAR
, "DAR",
512 SPR_NOACCESS
, SPR_NOACCESS
,
513 &spr_read_generic
, &spr_write_generic
,
516 spr_register(env
, SPR_DECR
, "DECR",
517 SPR_NOACCESS
, SPR_NOACCESS
,
518 &spr_read_decr
, &spr_write_decr
,
520 /* Memory management */
521 spr_register(env
, SPR_SDR1
, "SDR1",
522 SPR_NOACCESS
, SPR_NOACCESS
,
523 &spr_read_sdr1
, &spr_write_sdr1
,
528 static void gen_low_BATs (CPUPPCState
*env
)
530 spr_register(env
, SPR_IBAT0U
, "IBAT0U",
531 SPR_NOACCESS
, SPR_NOACCESS
,
532 &spr_read_ibat
, &spr_write_ibatu
,
534 spr_register(env
, SPR_IBAT0L
, "IBAT0L",
535 SPR_NOACCESS
, SPR_NOACCESS
,
536 &spr_read_ibat
, &spr_write_ibatl
,
538 spr_register(env
, SPR_IBAT1U
, "IBAT1U",
539 SPR_NOACCESS
, SPR_NOACCESS
,
540 &spr_read_ibat
, &spr_write_ibatu
,
542 spr_register(env
, SPR_IBAT1L
, "IBAT1L",
543 SPR_NOACCESS
, SPR_NOACCESS
,
544 &spr_read_ibat
, &spr_write_ibatl
,
546 spr_register(env
, SPR_IBAT2U
, "IBAT2U",
547 SPR_NOACCESS
, SPR_NOACCESS
,
548 &spr_read_ibat
, &spr_write_ibatu
,
550 spr_register(env
, SPR_IBAT2L
, "IBAT2L",
551 SPR_NOACCESS
, SPR_NOACCESS
,
552 &spr_read_ibat
, &spr_write_ibatl
,
554 spr_register(env
, SPR_IBAT3U
, "IBAT3U",
555 SPR_NOACCESS
, SPR_NOACCESS
,
556 &spr_read_ibat
, &spr_write_ibatu
,
558 spr_register(env
, SPR_IBAT3L
, "IBAT3L",
559 SPR_NOACCESS
, SPR_NOACCESS
,
560 &spr_read_ibat
, &spr_write_ibatl
,
562 spr_register(env
, SPR_DBAT0U
, "DBAT0U",
563 SPR_NOACCESS
, SPR_NOACCESS
,
564 &spr_read_dbat
, &spr_write_dbatu
,
566 spr_register(env
, SPR_DBAT0L
, "DBAT0L",
567 SPR_NOACCESS
, SPR_NOACCESS
,
568 &spr_read_dbat
, &spr_write_dbatl
,
570 spr_register(env
, SPR_DBAT1U
, "DBAT1U",
571 SPR_NOACCESS
, SPR_NOACCESS
,
572 &spr_read_dbat
, &spr_write_dbatu
,
574 spr_register(env
, SPR_DBAT1L
, "DBAT1L",
575 SPR_NOACCESS
, SPR_NOACCESS
,
576 &spr_read_dbat
, &spr_write_dbatl
,
578 spr_register(env
, SPR_DBAT2U
, "DBAT2U",
579 SPR_NOACCESS
, SPR_NOACCESS
,
580 &spr_read_dbat
, &spr_write_dbatu
,
582 spr_register(env
, SPR_DBAT2L
, "DBAT2L",
583 SPR_NOACCESS
, SPR_NOACCESS
,
584 &spr_read_dbat
, &spr_write_dbatl
,
586 spr_register(env
, SPR_DBAT3U
, "DBAT3U",
587 SPR_NOACCESS
, SPR_NOACCESS
,
588 &spr_read_dbat
, &spr_write_dbatu
,
590 spr_register(env
, SPR_DBAT3L
, "DBAT3L",
591 SPR_NOACCESS
, SPR_NOACCESS
,
592 &spr_read_dbat
, &spr_write_dbatl
,
598 static void gen_high_BATs (CPUPPCState
*env
)
600 spr_register(env
, SPR_IBAT4U
, "IBAT4U",
601 SPR_NOACCESS
, SPR_NOACCESS
,
602 &spr_read_ibat_h
, &spr_write_ibatu_h
,
604 spr_register(env
, SPR_IBAT4L
, "IBAT4L",
605 SPR_NOACCESS
, SPR_NOACCESS
,
606 &spr_read_ibat_h
, &spr_write_ibatl_h
,
608 spr_register(env
, SPR_IBAT5U
, "IBAT5U",
609 SPR_NOACCESS
, SPR_NOACCESS
,
610 &spr_read_ibat_h
, &spr_write_ibatu_h
,
612 spr_register(env
, SPR_IBAT5L
, "IBAT5L",
613 SPR_NOACCESS
, SPR_NOACCESS
,
614 &spr_read_ibat_h
, &spr_write_ibatl_h
,
616 spr_register(env
, SPR_IBAT6U
, "IBAT6U",
617 SPR_NOACCESS
, SPR_NOACCESS
,
618 &spr_read_ibat_h
, &spr_write_ibatu_h
,
620 spr_register(env
, SPR_IBAT6L
, "IBAT6L",
621 SPR_NOACCESS
, SPR_NOACCESS
,
622 &spr_read_ibat_h
, &spr_write_ibatl_h
,
624 spr_register(env
, SPR_IBAT7U
, "IBAT7U",
625 SPR_NOACCESS
, SPR_NOACCESS
,
626 &spr_read_ibat_h
, &spr_write_ibatu_h
,
628 spr_register(env
, SPR_IBAT7L
, "IBAT7L",
629 SPR_NOACCESS
, SPR_NOACCESS
,
630 &spr_read_ibat_h
, &spr_write_ibatl_h
,
632 spr_register(env
, SPR_DBAT4U
, "DBAT4U",
633 SPR_NOACCESS
, SPR_NOACCESS
,
634 &spr_read_dbat_h
, &spr_write_dbatu_h
,
636 spr_register(env
, SPR_DBAT4L
, "DBAT4L",
637 SPR_NOACCESS
, SPR_NOACCESS
,
638 &spr_read_dbat_h
, &spr_write_dbatl_h
,
640 spr_register(env
, SPR_DBAT5U
, "DBAT5U",
641 SPR_NOACCESS
, SPR_NOACCESS
,
642 &spr_read_dbat_h
, &spr_write_dbatu_h
,
644 spr_register(env
, SPR_DBAT5L
, "DBAT5L",
645 SPR_NOACCESS
, SPR_NOACCESS
,
646 &spr_read_dbat_h
, &spr_write_dbatl_h
,
648 spr_register(env
, SPR_DBAT6U
, "DBAT6U",
649 SPR_NOACCESS
, SPR_NOACCESS
,
650 &spr_read_dbat_h
, &spr_write_dbatu_h
,
652 spr_register(env
, SPR_DBAT6L
, "DBAT6L",
653 SPR_NOACCESS
, SPR_NOACCESS
,
654 &spr_read_dbat_h
, &spr_write_dbatl_h
,
656 spr_register(env
, SPR_DBAT7U
, "DBAT7U",
657 SPR_NOACCESS
, SPR_NOACCESS
,
658 &spr_read_dbat_h
, &spr_write_dbatu_h
,
660 spr_register(env
, SPR_DBAT7L
, "DBAT7L",
661 SPR_NOACCESS
, SPR_NOACCESS
,
662 &spr_read_dbat_h
, &spr_write_dbatl_h
,
667 /* Generic PowerPC time base */
668 static void gen_tbl (CPUPPCState
*env
)
670 spr_register(env
, SPR_VTBL
, "TBL",
671 &spr_read_tbl
, SPR_NOACCESS
,
672 &spr_read_tbl
, SPR_NOACCESS
,
674 spr_register(env
, SPR_TBL
, "TBL",
675 SPR_NOACCESS
, SPR_NOACCESS
,
676 SPR_NOACCESS
, &spr_write_tbl
,
678 spr_register(env
, SPR_VTBU
, "TBU",
679 &spr_read_tbu
, SPR_NOACCESS
,
680 &spr_read_tbu
, SPR_NOACCESS
,
682 spr_register(env
, SPR_TBU
, "TBU",
683 SPR_NOACCESS
, SPR_NOACCESS
,
684 SPR_NOACCESS
, &spr_write_tbu
,
688 /* Softare table search registers */
689 static void gen_6xx_7xx_soft_tlb (CPUPPCState
*env
, int nb_tlbs
, int nb_ways
)
691 env
->nb_tlb
= nb_tlbs
;
692 env
->nb_ways
= nb_ways
;
694 spr_register(env
, SPR_DMISS
, "DMISS",
695 SPR_NOACCESS
, SPR_NOACCESS
,
696 &spr_read_generic
, SPR_NOACCESS
,
698 spr_register(env
, SPR_DCMP
, "DCMP",
699 SPR_NOACCESS
, SPR_NOACCESS
,
700 &spr_read_generic
, SPR_NOACCESS
,
702 spr_register(env
, SPR_HASH1
, "HASH1",
703 SPR_NOACCESS
, SPR_NOACCESS
,
704 &spr_read_generic
, SPR_NOACCESS
,
706 spr_register(env
, SPR_HASH2
, "HASH2",
707 SPR_NOACCESS
, SPR_NOACCESS
,
708 &spr_read_generic
, SPR_NOACCESS
,
710 spr_register(env
, SPR_IMISS
, "IMISS",
711 SPR_NOACCESS
, SPR_NOACCESS
,
712 &spr_read_generic
, SPR_NOACCESS
,
714 spr_register(env
, SPR_ICMP
, "ICMP",
715 SPR_NOACCESS
, SPR_NOACCESS
,
716 &spr_read_generic
, SPR_NOACCESS
,
718 spr_register(env
, SPR_RPA
, "RPA",
719 SPR_NOACCESS
, SPR_NOACCESS
,
720 &spr_read_generic
, &spr_write_generic
,
724 /* SPR common to MPC755 and G2 */
725 static void gen_spr_G2_755 (CPUPPCState
*env
)
728 spr_register(env
, SPR_SPRG4
, "SPRG4",
729 SPR_NOACCESS
, SPR_NOACCESS
,
730 &spr_read_generic
, &spr_write_generic
,
732 spr_register(env
, SPR_SPRG5
, "SPRG5",
733 SPR_NOACCESS
, SPR_NOACCESS
,
734 &spr_read_generic
, &spr_write_generic
,
736 spr_register(env
, SPR_SPRG6
, "SPRG6",
737 SPR_NOACCESS
, SPR_NOACCESS
,
738 &spr_read_generic
, &spr_write_generic
,
740 spr_register(env
, SPR_SPRG7
, "SPRG7",
741 SPR_NOACCESS
, SPR_NOACCESS
,
742 &spr_read_generic
, &spr_write_generic
,
744 /* External access control */
745 /* XXX : not implemented */
746 spr_register(env
, SPR_EAR
, "EAR",
747 SPR_NOACCESS
, SPR_NOACCESS
,
748 &spr_read_generic
, &spr_write_generic
,
752 /* SPR common to all 7xx PowerPC implementations */
753 static void gen_spr_7xx (CPUPPCState
*env
)
756 /* XXX : not implemented */
757 spr_register(env
, SPR_DABR
, "DABR",
758 SPR_NOACCESS
, SPR_NOACCESS
,
759 &spr_read_generic
, &spr_write_generic
,
761 /* XXX : not implemented */
762 spr_register(env
, SPR_IABR
, "IABR",
763 SPR_NOACCESS
, SPR_NOACCESS
,
764 &spr_read_generic
, &spr_write_generic
,
766 /* Cache management */
767 /* XXX : not implemented */
768 spr_register(env
, SPR_ICTC
, "ICTC",
769 SPR_NOACCESS
, SPR_NOACCESS
,
770 &spr_read_generic
, &spr_write_generic
,
772 /* XXX : not implemented */
773 spr_register(env
, SPR_L2CR
, "L2CR",
774 SPR_NOACCESS
, SPR_NOACCESS
,
775 &spr_read_generic
, &spr_write_generic
,
777 /* Performance monitors */
778 /* XXX : not implemented */
779 spr_register(env
, SPR_MMCR0
, "MMCR0",
780 SPR_NOACCESS
, SPR_NOACCESS
,
781 &spr_read_generic
, &spr_write_generic
,
783 /* XXX : not implemented */
784 spr_register(env
, SPR_MMCR1
, "MMCR1",
785 SPR_NOACCESS
, SPR_NOACCESS
,
786 &spr_read_generic
, &spr_write_generic
,
788 /* XXX : not implemented */
789 spr_register(env
, SPR_PMC1
, "PMC1",
790 SPR_NOACCESS
, SPR_NOACCESS
,
791 &spr_read_generic
, &spr_write_generic
,
793 /* XXX : not implemented */
794 spr_register(env
, SPR_PMC2
, "PMC2",
795 SPR_NOACCESS
, SPR_NOACCESS
,
796 &spr_read_generic
, &spr_write_generic
,
798 /* XXX : not implemented */
799 spr_register(env
, SPR_PMC3
, "PMC3",
800 SPR_NOACCESS
, SPR_NOACCESS
,
801 &spr_read_generic
, &spr_write_generic
,
803 /* XXX : not implemented */
804 spr_register(env
, SPR_PMC4
, "PMC4",
805 SPR_NOACCESS
, SPR_NOACCESS
,
806 &spr_read_generic
, &spr_write_generic
,
808 /* XXX : not implemented */
809 spr_register(env
, SPR_SIAR
, "SIAR",
810 SPR_NOACCESS
, SPR_NOACCESS
,
811 &spr_read_generic
, SPR_NOACCESS
,
813 spr_register(env
, SPR_UMMCR0
, "UMMCR0",
814 &spr_read_ureg
, SPR_NOACCESS
,
815 &spr_read_ureg
, SPR_NOACCESS
,
817 spr_register(env
, SPR_UMMCR1
, "UMMCR1",
818 &spr_read_ureg
, SPR_NOACCESS
,
819 &spr_read_ureg
, SPR_NOACCESS
,
821 spr_register(env
, SPR_UPMC1
, "UPMC1",
822 &spr_read_ureg
, SPR_NOACCESS
,
823 &spr_read_ureg
, SPR_NOACCESS
,
825 spr_register(env
, SPR_UPMC2
, "UPMC2",
826 &spr_read_ureg
, SPR_NOACCESS
,
827 &spr_read_ureg
, SPR_NOACCESS
,
829 spr_register(env
, SPR_UPMC3
, "UPMC3",
830 &spr_read_ureg
, SPR_NOACCESS
,
831 &spr_read_ureg
, SPR_NOACCESS
,
833 spr_register(env
, SPR_UPMC4
, "UPMC4",
834 &spr_read_ureg
, SPR_NOACCESS
,
835 &spr_read_ureg
, SPR_NOACCESS
,
837 spr_register(env
, SPR_USIAR
, "USIAR",
838 &spr_read_ureg
, SPR_NOACCESS
,
839 &spr_read_ureg
, SPR_NOACCESS
,
841 /* External access control */
842 /* XXX : not implemented */
843 spr_register(env
, SPR_EAR
, "EAR",
844 SPR_NOACCESS
, SPR_NOACCESS
,
845 &spr_read_generic
, &spr_write_generic
,
849 static void gen_spr_thrm (CPUPPCState
*env
)
851 /* Thermal management */
852 /* XXX : not implemented */
853 spr_register(env
, SPR_THRM1
, "THRM1",
854 SPR_NOACCESS
, SPR_NOACCESS
,
855 &spr_read_generic
, &spr_write_generic
,
857 /* XXX : not implemented */
858 spr_register(env
, SPR_THRM2
, "THRM2",
859 SPR_NOACCESS
, SPR_NOACCESS
,
860 &spr_read_generic
, &spr_write_generic
,
862 /* XXX : not implemented */
863 spr_register(env
, SPR_THRM3
, "THRM3",
864 SPR_NOACCESS
, SPR_NOACCESS
,
865 &spr_read_generic
, &spr_write_generic
,
869 /* SPR specific to PowerPC 604 implementation */
870 static void gen_spr_604 (CPUPPCState
*env
)
872 /* Processor identification */
873 spr_register(env
, SPR_PIR
, "PIR",
874 SPR_NOACCESS
, SPR_NOACCESS
,
875 &spr_read_generic
, &spr_write_pir
,
878 /* XXX : not implemented */
879 spr_register(env
, SPR_IABR
, "IABR",
880 SPR_NOACCESS
, SPR_NOACCESS
,
881 &spr_read_generic
, &spr_write_generic
,
883 /* XXX : not implemented */
884 spr_register(env
, SPR_DABR
, "DABR",
885 SPR_NOACCESS
, SPR_NOACCESS
,
886 &spr_read_generic
, &spr_write_generic
,
888 /* Performance counters */
889 /* XXX : not implemented */
890 spr_register(env
, SPR_MMCR0
, "MMCR0",
891 SPR_NOACCESS
, SPR_NOACCESS
,
892 &spr_read_generic
, &spr_write_generic
,
894 /* XXX : not implemented */
895 spr_register(env
, SPR_MMCR1
, "MMCR1",
896 SPR_NOACCESS
, SPR_NOACCESS
,
897 &spr_read_generic
, &spr_write_generic
,
899 /* XXX : not implemented */
900 spr_register(env
, SPR_PMC1
, "PMC1",
901 SPR_NOACCESS
, SPR_NOACCESS
,
902 &spr_read_generic
, &spr_write_generic
,
904 /* XXX : not implemented */
905 spr_register(env
, SPR_PMC2
, "PMC2",
906 SPR_NOACCESS
, SPR_NOACCESS
,
907 &spr_read_generic
, &spr_write_generic
,
909 /* XXX : not implemented */
910 spr_register(env
, SPR_PMC3
, "PMC3",
911 SPR_NOACCESS
, SPR_NOACCESS
,
912 &spr_read_generic
, &spr_write_generic
,
914 /* XXX : not implemented */
915 spr_register(env
, SPR_PMC4
, "PMC4",
916 SPR_NOACCESS
, SPR_NOACCESS
,
917 &spr_read_generic
, &spr_write_generic
,
919 /* XXX : not implemented */
920 spr_register(env
, SPR_SIAR
, "SIAR",
921 SPR_NOACCESS
, SPR_NOACCESS
,
922 &spr_read_generic
, SPR_NOACCESS
,
924 /* XXX : not implemented */
925 spr_register(env
, SPR_SDA
, "SDA",
926 SPR_NOACCESS
, SPR_NOACCESS
,
927 &spr_read_generic
, SPR_NOACCESS
,
929 /* External access control */
930 /* XXX : not implemented */
931 spr_register(env
, SPR_EAR
, "EAR",
932 SPR_NOACCESS
, SPR_NOACCESS
,
933 &spr_read_generic
, &spr_write_generic
,
937 /* SPR specific to PowerPC 603 implementation */
938 static void gen_spr_603 (CPUPPCState
*env
)
940 /* External access control */
941 /* XXX : not implemented */
942 spr_register(env
, SPR_EAR
, "EAR",
943 SPR_NOACCESS
, SPR_NOACCESS
,
944 &spr_read_generic
, &spr_write_generic
,
948 /* SPR specific to PowerPC G2 implementation */
949 static void gen_spr_G2 (CPUPPCState
*env
)
951 /* Memory base address */
953 spr_register(env
, SPR_MBAR
, "MBAR",
954 SPR_NOACCESS
, SPR_NOACCESS
,
955 &spr_read_generic
, &spr_write_generic
,
957 /* System version register */
959 spr_register(env
, SPR_SVR
, "SVR",
960 SPR_NOACCESS
, SPR_NOACCESS
,
961 &spr_read_generic
, SPR_NOACCESS
,
963 /* Exception processing */
964 spr_register(env
, SPR_BOOKE_CSRR0
, "CSRR0",
965 SPR_NOACCESS
, SPR_NOACCESS
,
966 &spr_read_generic
, &spr_write_generic
,
968 spr_register(env
, SPR_BOOKE_CSRR1
, "CSRR1",
969 SPR_NOACCESS
, SPR_NOACCESS
,
970 &spr_read_generic
, &spr_write_generic
,
973 /* XXX : not implemented */
974 spr_register(env
, SPR_DABR
, "DABR",
975 SPR_NOACCESS
, SPR_NOACCESS
,
976 &spr_read_generic
, &spr_write_generic
,
978 /* XXX : not implemented */
979 spr_register(env
, SPR_DABR2
, "DABR2",
980 SPR_NOACCESS
, SPR_NOACCESS
,
981 &spr_read_generic
, &spr_write_generic
,
983 /* XXX : not implemented */
984 spr_register(env
, SPR_IABR
, "IABR",
985 SPR_NOACCESS
, SPR_NOACCESS
,
986 &spr_read_generic
, &spr_write_generic
,
988 /* XXX : not implemented */
989 spr_register(env
, SPR_IABR2
, "IABR2",
990 SPR_NOACCESS
, SPR_NOACCESS
,
991 &spr_read_generic
, &spr_write_generic
,
993 /* XXX : not implemented */
994 spr_register(env
, SPR_IBCR
, "IBCR",
995 SPR_NOACCESS
, SPR_NOACCESS
,
996 &spr_read_generic
, &spr_write_generic
,
998 /* XXX : not implemented */
999 spr_register(env
, SPR_DBCR
, "DBCR",
1000 SPR_NOACCESS
, SPR_NOACCESS
,
1001 &spr_read_generic
, &spr_write_generic
,
1005 /* SPR specific to PowerPC 602 implementation */
1006 static void gen_spr_602 (CPUPPCState
*env
)
1009 /* XXX : not implemented */
1010 spr_register(env
, SPR_SER
, "SER",
1011 SPR_NOACCESS
, SPR_NOACCESS
,
1012 &spr_read_generic
, &spr_write_generic
,
1014 /* XXX : not implemented */
1015 spr_register(env
, SPR_SEBR
, "SEBR",
1016 SPR_NOACCESS
, SPR_NOACCESS
,
1017 &spr_read_generic
, &spr_write_generic
,
1019 /* XXX : not implemented */
1020 spr_register(env
, SPR_ESASRR
, "ESASRR",
1021 SPR_NOACCESS
, SPR_NOACCESS
,
1022 &spr_read_generic
, &spr_write_generic
,
1024 /* Floating point status */
1025 /* XXX : not implemented */
1026 spr_register(env
, SPR_SP
, "SP",
1027 SPR_NOACCESS
, SPR_NOACCESS
,
1028 &spr_read_generic
, &spr_write_generic
,
1030 /* XXX : not implemented */
1031 spr_register(env
, SPR_LT
, "LT",
1032 SPR_NOACCESS
, SPR_NOACCESS
,
1033 &spr_read_generic
, &spr_write_generic
,
1035 /* Watchdog timer */
1036 /* XXX : not implemented */
1037 spr_register(env
, SPR_TCR
, "TCR",
1038 SPR_NOACCESS
, SPR_NOACCESS
,
1039 &spr_read_generic
, &spr_write_generic
,
1041 /* Interrupt base */
1042 spr_register(env
, SPR_IBR
, "IBR",
1043 SPR_NOACCESS
, SPR_NOACCESS
,
1044 &spr_read_generic
, &spr_write_generic
,
1046 /* XXX : not implemented */
1047 spr_register(env
, SPR_IABR
, "IABR",
1048 SPR_NOACCESS
, SPR_NOACCESS
,
1049 &spr_read_generic
, &spr_write_generic
,
1053 /* SPR specific to PowerPC 601 implementation */
1054 static void gen_spr_601 (CPUPPCState
*env
)
1056 /* Multiplication/division register */
1058 spr_register(env
, SPR_MQ
, "MQ",
1059 &spr_read_generic
, &spr_write_generic
,
1060 &spr_read_generic
, &spr_write_generic
,
1063 spr_register(env
, SPR_601_RTCU
, "RTCU",
1064 SPR_NOACCESS
, SPR_NOACCESS
,
1065 SPR_NOACCESS
, &spr_write_601_rtcu
,
1067 spr_register(env
, SPR_601_VRTCU
, "RTCU",
1068 &spr_read_601_rtcu
, SPR_NOACCESS
,
1069 &spr_read_601_rtcu
, SPR_NOACCESS
,
1071 spr_register(env
, SPR_601_RTCL
, "RTCL",
1072 SPR_NOACCESS
, SPR_NOACCESS
,
1073 SPR_NOACCESS
, &spr_write_601_rtcl
,
1075 spr_register(env
, SPR_601_VRTCL
, "RTCL",
1076 &spr_read_601_rtcl
, SPR_NOACCESS
,
1077 &spr_read_601_rtcl
, SPR_NOACCESS
,
1081 spr_register(env
, SPR_601_UDECR
, "UDECR",
1082 &spr_read_decr
, SPR_NOACCESS
,
1083 &spr_read_decr
, SPR_NOACCESS
,
1086 /* External access control */
1087 /* XXX : not implemented */
1088 spr_register(env
, SPR_EAR
, "EAR",
1089 SPR_NOACCESS
, SPR_NOACCESS
,
1090 &spr_read_generic
, &spr_write_generic
,
1092 /* Memory management */
1093 spr_register(env
, SPR_IBAT0U
, "IBAT0U",
1094 SPR_NOACCESS
, SPR_NOACCESS
,
1095 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1097 spr_register(env
, SPR_IBAT0L
, "IBAT0L",
1098 SPR_NOACCESS
, SPR_NOACCESS
,
1099 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1101 spr_register(env
, SPR_IBAT1U
, "IBAT1U",
1102 SPR_NOACCESS
, SPR_NOACCESS
,
1103 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1105 spr_register(env
, SPR_IBAT1L
, "IBAT1L",
1106 SPR_NOACCESS
, SPR_NOACCESS
,
1107 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1109 spr_register(env
, SPR_IBAT2U
, "IBAT2U",
1110 SPR_NOACCESS
, SPR_NOACCESS
,
1111 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1113 spr_register(env
, SPR_IBAT2L
, "IBAT2L",
1114 SPR_NOACCESS
, SPR_NOACCESS
,
1115 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1117 spr_register(env
, SPR_IBAT3U
, "IBAT3U",
1118 SPR_NOACCESS
, SPR_NOACCESS
,
1119 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1121 spr_register(env
, SPR_IBAT3L
, "IBAT3L",
1122 SPR_NOACCESS
, SPR_NOACCESS
,
1123 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1128 static void gen_spr_74xx (CPUPPCState
*env
)
1130 /* Processor identification */
1131 spr_register(env
, SPR_PIR
, "PIR",
1132 SPR_NOACCESS
, SPR_NOACCESS
,
1133 &spr_read_generic
, &spr_write_pir
,
1135 /* XXX : not implemented */
1136 spr_register(env
, SPR_MMCR2
, "MMCR2",
1137 SPR_NOACCESS
, SPR_NOACCESS
,
1138 &spr_read_generic
, &spr_write_generic
,
1140 spr_register(env
, SPR_UMMCR2
, "UMMCR2",
1141 &spr_read_ureg
, SPR_NOACCESS
,
1142 &spr_read_ureg
, SPR_NOACCESS
,
1144 /* XXX: not implemented */
1145 spr_register(env
, SPR_BAMR
, "BAMR",
1146 SPR_NOACCESS
, SPR_NOACCESS
,
1147 &spr_read_generic
, &spr_write_generic
,
1149 spr_register(env
, SPR_UBAMR
, "UBAMR",
1150 &spr_read_ureg
, SPR_NOACCESS
,
1151 &spr_read_ureg
, SPR_NOACCESS
,
1153 spr_register(env
, SPR_MSSCR0
, "MSSCR0",
1154 SPR_NOACCESS
, SPR_NOACCESS
,
1155 &spr_read_generic
, &spr_write_generic
,
1157 /* Hardware implementation registers */
1158 /* XXX : not implemented */
1159 spr_register(env
, SPR_HID0
, "HID0",
1160 SPR_NOACCESS
, SPR_NOACCESS
,
1161 &spr_read_generic
, &spr_write_generic
,
1163 /* XXX : not implemented */
1164 spr_register(env
, SPR_HID1
, "HID1",
1165 SPR_NOACCESS
, SPR_NOACCESS
,
1166 &spr_read_generic
, &spr_write_generic
,
1169 spr_register(env
, SPR_VRSAVE
, "VRSAVE",
1170 &spr_read_generic
, &spr_write_generic
,
1171 &spr_read_generic
, &spr_write_generic
,
1176 static void gen_l3_ctrl (CPUPPCState
*env
)
1179 /* XXX : not implemented */
1180 spr_register(env
, SPR_L3CR
, "L3CR",
1181 SPR_NOACCESS
, SPR_NOACCESS
,
1182 &spr_read_generic
, &spr_write_generic
,
1185 spr_register(env
, SPR_L3ITCR0
, "L3ITCR0",
1186 SPR_NOACCESS
, SPR_NOACCESS
,
1187 &spr_read_generic
, &spr_write_generic
,
1190 spr_register(env
, SPR_L3ITCR1
, "L3ITCR1",
1191 SPR_NOACCESS
, SPR_NOACCESS
,
1192 &spr_read_generic
, &spr_write_generic
,
1195 spr_register(env
, SPR_L3ITCR2
, "L3ITCR2",
1196 SPR_NOACCESS
, SPR_NOACCESS
,
1197 &spr_read_generic
, &spr_write_generic
,
1200 spr_register(env
, SPR_L3ITCR3
, "L3ITCR3",
1201 SPR_NOACCESS
, SPR_NOACCESS
,
1202 &spr_read_generic
, &spr_write_generic
,
1205 spr_register(env
, SPR_L3OHCR
, "L3OHCR",
1206 SPR_NOACCESS
, SPR_NOACCESS
,
1207 &spr_read_generic
, &spr_write_generic
,
1210 spr_register(env
, SPR_L3PM
, "L3PM",
1211 SPR_NOACCESS
, SPR_NOACCESS
,
1212 &spr_read_generic
, &spr_write_generic
,
1218 static void gen_74xx_soft_tlb (CPUPPCState
*env
)
1221 spr_register(env
, SPR_PTEHI
, "PTEHI",
1222 SPR_NOACCESS
, SPR_NOACCESS
,
1223 &spr_read_generic
, &spr_write_generic
,
1225 spr_register(env
, SPR_PTELO
, "PTELO",
1226 SPR_NOACCESS
, SPR_NOACCESS
,
1227 &spr_read_generic
, &spr_write_generic
,
1229 spr_register(env
, SPR_TLBMISS
, "TLBMISS",
1230 SPR_NOACCESS
, SPR_NOACCESS
,
1231 &spr_read_generic
, &spr_write_generic
,
1236 /* PowerPC BookE SPR */
1237 static void gen_spr_BookE (CPUPPCState
*env
)
1239 /* Processor identification */
1240 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
1241 SPR_NOACCESS
, SPR_NOACCESS
,
1242 &spr_read_generic
, &spr_write_pir
,
1244 /* Interrupt processing */
1245 spr_register(env
, SPR_BOOKE_CSRR0
, "CSRR0",
1246 SPR_NOACCESS
, SPR_NOACCESS
,
1247 &spr_read_generic
, &spr_write_generic
,
1249 spr_register(env
, SPR_BOOKE_CSRR1
, "CSRR1",
1250 SPR_NOACCESS
, SPR_NOACCESS
,
1251 &spr_read_generic
, &spr_write_generic
,
1254 spr_register(env
, SPR_BOOKE_DSRR0
, "DSRR0",
1255 SPR_NOACCESS
, SPR_NOACCESS
,
1256 &spr_read_generic
, &spr_write_generic
,
1258 spr_register(env
, SPR_BOOKE_DSRR1
, "DSRR1",
1259 SPR_NOACCESS
, SPR_NOACCESS
,
1260 &spr_read_generic
, &spr_write_generic
,
1264 /* XXX : not implemented */
1265 spr_register(env
, SPR_BOOKE_IAC1
, "IAC1",
1266 SPR_NOACCESS
, SPR_NOACCESS
,
1267 &spr_read_generic
, &spr_write_generic
,
1269 /* XXX : not implemented */
1270 spr_register(env
, SPR_BOOKE_IAC2
, "IAC2",
1271 SPR_NOACCESS
, SPR_NOACCESS
,
1272 &spr_read_generic
, &spr_write_generic
,
1274 /* XXX : not implemented */
1275 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
1276 SPR_NOACCESS
, SPR_NOACCESS
,
1277 &spr_read_generic
, &spr_write_generic
,
1279 /* XXX : not implemented */
1280 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
1281 SPR_NOACCESS
, SPR_NOACCESS
,
1282 &spr_read_generic
, &spr_write_generic
,
1284 /* XXX : not implemented */
1285 spr_register(env
, SPR_BOOKE_DAC1
, "DAC1",
1286 SPR_NOACCESS
, SPR_NOACCESS
,
1287 &spr_read_generic
, &spr_write_generic
,
1289 /* XXX : not implemented */
1290 spr_register(env
, SPR_BOOKE_DAC2
, "DAC2",
1291 SPR_NOACCESS
, SPR_NOACCESS
,
1292 &spr_read_generic
, &spr_write_generic
,
1294 /* XXX : not implemented */
1295 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
1296 SPR_NOACCESS
, SPR_NOACCESS
,
1297 &spr_read_generic
, &spr_write_generic
,
1299 /* XXX : not implemented */
1300 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
1301 SPR_NOACCESS
, SPR_NOACCESS
,
1302 &spr_read_generic
, &spr_write_generic
,
1304 /* XXX : not implemented */
1305 spr_register(env
, SPR_BOOKE_DBCR0
, "DBCR0",
1306 SPR_NOACCESS
, SPR_NOACCESS
,
1307 &spr_read_generic
, &spr_write_generic
,
1309 /* XXX : not implemented */
1310 spr_register(env
, SPR_BOOKE_DBCR1
, "DBCR1",
1311 SPR_NOACCESS
, SPR_NOACCESS
,
1312 &spr_read_generic
, &spr_write_generic
,
1314 /* XXX : not implemented */
1315 spr_register(env
, SPR_BOOKE_DBCR2
, "DBCR2",
1316 SPR_NOACCESS
, SPR_NOACCESS
,
1317 &spr_read_generic
, &spr_write_generic
,
1319 /* XXX : not implemented */
1320 spr_register(env
, SPR_BOOKE_DBSR
, "DBSR",
1321 SPR_NOACCESS
, SPR_NOACCESS
,
1322 &spr_read_generic
, &spr_write_clear
,
1324 spr_register(env
, SPR_BOOKE_DEAR
, "DEAR",
1325 SPR_NOACCESS
, SPR_NOACCESS
,
1326 &spr_read_generic
, &spr_write_generic
,
1328 spr_register(env
, SPR_BOOKE_ESR
, "ESR",
1329 SPR_NOACCESS
, SPR_NOACCESS
,
1330 &spr_read_generic
, &spr_write_generic
,
1332 spr_register(env
, SPR_BOOKE_IVPR
, "IVPR",
1333 SPR_NOACCESS
, SPR_NOACCESS
,
1334 &spr_read_generic
, &spr_write_generic
,
1336 /* Exception vectors */
1337 spr_register(env
, SPR_BOOKE_IVOR0
, "IVOR0",
1338 SPR_NOACCESS
, SPR_NOACCESS
,
1339 &spr_read_generic
, &spr_write_generic
,
1341 spr_register(env
, SPR_BOOKE_IVOR1
, "IVOR1",
1342 SPR_NOACCESS
, SPR_NOACCESS
,
1343 &spr_read_generic
, &spr_write_generic
,
1345 spr_register(env
, SPR_BOOKE_IVOR2
, "IVOR2",
1346 SPR_NOACCESS
, SPR_NOACCESS
,
1347 &spr_read_generic
, &spr_write_generic
,
1349 spr_register(env
, SPR_BOOKE_IVOR3
, "IVOR3",
1350 SPR_NOACCESS
, SPR_NOACCESS
,
1351 &spr_read_generic
, &spr_write_generic
,
1353 spr_register(env
, SPR_BOOKE_IVOR4
, "IVOR4",
1354 SPR_NOACCESS
, SPR_NOACCESS
,
1355 &spr_read_generic
, &spr_write_generic
,
1357 spr_register(env
, SPR_BOOKE_IVOR5
, "IVOR5",
1358 SPR_NOACCESS
, SPR_NOACCESS
,
1359 &spr_read_generic
, &spr_write_generic
,
1361 spr_register(env
, SPR_BOOKE_IVOR6
, "IVOR6",
1362 SPR_NOACCESS
, SPR_NOACCESS
,
1363 &spr_read_generic
, &spr_write_generic
,
1365 spr_register(env
, SPR_BOOKE_IVOR7
, "IVOR7",
1366 SPR_NOACCESS
, SPR_NOACCESS
,
1367 &spr_read_generic
, &spr_write_generic
,
1369 spr_register(env
, SPR_BOOKE_IVOR8
, "IVOR8",
1370 SPR_NOACCESS
, SPR_NOACCESS
,
1371 &spr_read_generic
, &spr_write_generic
,
1373 spr_register(env
, SPR_BOOKE_IVOR9
, "IVOR9",
1374 SPR_NOACCESS
, SPR_NOACCESS
,
1375 &spr_read_generic
, &spr_write_generic
,
1377 spr_register(env
, SPR_BOOKE_IVOR10
, "IVOR10",
1378 SPR_NOACCESS
, SPR_NOACCESS
,
1379 &spr_read_generic
, &spr_write_generic
,
1381 spr_register(env
, SPR_BOOKE_IVOR11
, "IVOR11",
1382 SPR_NOACCESS
, SPR_NOACCESS
,
1383 &spr_read_generic
, &spr_write_generic
,
1385 spr_register(env
, SPR_BOOKE_IVOR12
, "IVOR12",
1386 SPR_NOACCESS
, SPR_NOACCESS
,
1387 &spr_read_generic
, &spr_write_generic
,
1389 spr_register(env
, SPR_BOOKE_IVOR13
, "IVOR13",
1390 SPR_NOACCESS
, SPR_NOACCESS
,
1391 &spr_read_generic
, &spr_write_generic
,
1393 spr_register(env
, SPR_BOOKE_IVOR14
, "IVOR14",
1394 SPR_NOACCESS
, SPR_NOACCESS
,
1395 &spr_read_generic
, &spr_write_generic
,
1397 spr_register(env
, SPR_BOOKE_IVOR15
, "IVOR15",
1398 SPR_NOACCESS
, SPR_NOACCESS
,
1399 &spr_read_generic
, &spr_write_generic
,
1402 spr_register(env
, SPR_BOOKE_IVOR32
, "IVOR32",
1403 SPR_NOACCESS
, SPR_NOACCESS
,
1404 &spr_read_generic
, &spr_write_generic
,
1406 spr_register(env
, SPR_BOOKE_IVOR33
, "IVOR33",
1407 SPR_NOACCESS
, SPR_NOACCESS
,
1408 &spr_read_generic
, &spr_write_generic
,
1410 spr_register(env
, SPR_BOOKE_IVOR34
, "IVOR34",
1411 SPR_NOACCESS
, SPR_NOACCESS
,
1412 &spr_read_generic
, &spr_write_generic
,
1414 spr_register(env
, SPR_BOOKE_IVOR35
, "IVOR35",
1415 SPR_NOACCESS
, SPR_NOACCESS
,
1416 &spr_read_generic
, &spr_write_generic
,
1418 spr_register(env
, SPR_BOOKE_IVOR36
, "IVOR36",
1419 SPR_NOACCESS
, SPR_NOACCESS
,
1420 &spr_read_generic
, &spr_write_generic
,
1422 spr_register(env
, SPR_BOOKE_IVOR37
, "IVOR37",
1423 SPR_NOACCESS
, SPR_NOACCESS
,
1424 &spr_read_generic
, &spr_write_generic
,
1427 spr_register(env
, SPR_BOOKE_PID
, "PID",
1428 SPR_NOACCESS
, SPR_NOACCESS
,
1429 &spr_read_generic
, &spr_write_generic
,
1431 spr_register(env
, SPR_BOOKE_TCR
, "TCR",
1432 SPR_NOACCESS
, SPR_NOACCESS
,
1433 &spr_read_generic
, &spr_write_booke_tcr
,
1435 spr_register(env
, SPR_BOOKE_TSR
, "TSR",
1436 SPR_NOACCESS
, SPR_NOACCESS
,
1437 &spr_read_generic
, &spr_write_booke_tsr
,
1440 spr_register(env
, SPR_DECR
, "DECR",
1441 SPR_NOACCESS
, SPR_NOACCESS
,
1442 &spr_read_decr
, &spr_write_decr
,
1444 spr_register(env
, SPR_BOOKE_DECAR
, "DECAR",
1445 SPR_NOACCESS
, SPR_NOACCESS
,
1446 SPR_NOACCESS
, &spr_write_generic
,
1449 spr_register(env
, SPR_USPRG0
, "USPRG0",
1450 &spr_read_generic
, &spr_write_generic
,
1451 &spr_read_generic
, &spr_write_generic
,
1453 spr_register(env
, SPR_SPRG4
, "SPRG4",
1454 SPR_NOACCESS
, SPR_NOACCESS
,
1455 &spr_read_generic
, &spr_write_generic
,
1457 spr_register(env
, SPR_USPRG4
, "USPRG4",
1458 &spr_read_ureg
, SPR_NOACCESS
,
1459 &spr_read_ureg
, SPR_NOACCESS
,
1461 spr_register(env
, SPR_SPRG5
, "SPRG5",
1462 SPR_NOACCESS
, SPR_NOACCESS
,
1463 &spr_read_generic
, &spr_write_generic
,
1465 spr_register(env
, SPR_USPRG5
, "USPRG5",
1466 &spr_read_ureg
, SPR_NOACCESS
,
1467 &spr_read_ureg
, SPR_NOACCESS
,
1469 spr_register(env
, SPR_SPRG6
, "SPRG6",
1470 SPR_NOACCESS
, SPR_NOACCESS
,
1471 &spr_read_generic
, &spr_write_generic
,
1473 spr_register(env
, SPR_USPRG6
, "USPRG6",
1474 &spr_read_ureg
, SPR_NOACCESS
,
1475 &spr_read_ureg
, SPR_NOACCESS
,
1477 spr_register(env
, SPR_SPRG7
, "SPRG7",
1478 SPR_NOACCESS
, SPR_NOACCESS
,
1479 &spr_read_generic
, &spr_write_generic
,
1481 spr_register(env
, SPR_USPRG7
, "USPRG7",
1482 &spr_read_ureg
, SPR_NOACCESS
,
1483 &spr_read_ureg
, SPR_NOACCESS
,
1487 /* FSL storage control registers */
1489 static void gen_spr_BookE_FSL (CPUPPCState
*env
)
1491 /* TLB assist registers */
1492 spr_register(env
, SPR_BOOKE_MAS0
, "MAS0",
1493 SPR_NOACCESS
, SPR_NOACCESS
,
1494 &spr_read_generic
, &spr_write_generic
,
1496 spr_register(env
, SPR_BOOKE_MAS1
, "MAS2",
1497 SPR_NOACCESS
, SPR_NOACCESS
,
1498 &spr_read_generic
, &spr_write_generic
,
1500 spr_register(env
, SPR_BOOKE_MAS2
, "MAS3",
1501 SPR_NOACCESS
, SPR_NOACCESS
,
1502 &spr_read_generic
, &spr_write_generic
,
1504 spr_register(env
, SPR_BOOKE_MAS3
, "MAS4",
1505 SPR_NOACCESS
, SPR_NOACCESS
,
1506 &spr_read_generic
, &spr_write_generic
,
1508 spr_register(env
, SPR_BOOKE_MAS4
, "MAS5",
1509 SPR_NOACCESS
, SPR_NOACCESS
,
1510 &spr_read_generic
, &spr_write_generic
,
1512 spr_register(env
, SPR_BOOKE_MAS6
, "MAS6",
1513 SPR_NOACCESS
, SPR_NOACCESS
,
1514 &spr_read_generic
, &spr_write_generic
,
1516 spr_register(env
, SPR_BOOKE_MAS7
, "MAS7",
1517 SPR_NOACCESS
, SPR_NOACCESS
,
1518 &spr_read_generic
, &spr_write_generic
,
1520 if (env
->nb_pids
> 1) {
1521 spr_register(env
, SPR_BOOKE_PID1
, "PID1",
1522 SPR_NOACCESS
, SPR_NOACCESS
,
1523 &spr_read_generic
, &spr_write_generic
,
1526 if (env
->nb_pids
> 2) {
1527 spr_register(env
, SPR_BOOKE_PID2
, "PID2",
1528 SPR_NOACCESS
, SPR_NOACCESS
,
1529 &spr_read_generic
, &spr_write_generic
,
1532 spr_register(env
, SPR_BOOKE_MMUCFG
, "MMUCFG",
1533 SPR_NOACCESS
, SPR_NOACCESS
,
1534 &spr_read_generic
, SPR_NOACCESS
,
1535 0x00000000); /* TOFIX */
1536 spr_register(env
, SPR_BOOKE_MMUCSR0
, "MMUCSR0",
1537 SPR_NOACCESS
, SPR_NOACCESS
,
1538 &spr_read_generic
, &spr_write_generic
,
1539 0x00000000); /* TOFIX */
1540 switch (env
->nb_ways
) {
1542 spr_register(env
, SPR_BOOKE_TLB3CFG
, "TLB3CFG",
1543 SPR_NOACCESS
, SPR_NOACCESS
,
1544 &spr_read_generic
, SPR_NOACCESS
,
1545 0x00000000); /* TOFIX */
1548 spr_register(env
, SPR_BOOKE_TLB2CFG
, "TLB2CFG",
1549 SPR_NOACCESS
, SPR_NOACCESS
,
1550 &spr_read_generic
, SPR_NOACCESS
,
1551 0x00000000); /* TOFIX */
1554 spr_register(env
, SPR_BOOKE_TLB1CFG
, "TLB1CFG",
1555 SPR_NOACCESS
, SPR_NOACCESS
,
1556 &spr_read_generic
, SPR_NOACCESS
,
1557 0x00000000); /* TOFIX */
1560 spr_register(env
, SPR_BOOKE_TLB0CFG
, "TLB0CFG",
1561 SPR_NOACCESS
, SPR_NOACCESS
,
1562 &spr_read_generic
, SPR_NOACCESS
,
1563 0x00000000); /* TOFIX */
1572 /* SPR specific to PowerPC 440 implementation */
1573 static void gen_spr_440 (CPUPPCState
*env
)
1576 /* XXX : not implemented */
1577 spr_register(env
, SPR_440_DNV0
, "DNV0",
1578 SPR_NOACCESS
, SPR_NOACCESS
,
1579 &spr_read_generic
, &spr_write_generic
,
1581 /* XXX : not implemented */
1582 spr_register(env
, SPR_440_DNV1
, "DNV1",
1583 SPR_NOACCESS
, SPR_NOACCESS
,
1584 &spr_read_generic
, &spr_write_generic
,
1586 /* XXX : not implemented */
1587 spr_register(env
, SPR_440_DNV2
, "DNV2",
1588 SPR_NOACCESS
, SPR_NOACCESS
,
1589 &spr_read_generic
, &spr_write_generic
,
1591 /* XXX : not implemented */
1592 spr_register(env
, SPR_440_DNV3
, "DNV3",
1593 SPR_NOACCESS
, SPR_NOACCESS
,
1594 &spr_read_generic
, &spr_write_generic
,
1596 /* XXX : not implemented */
1597 spr_register(env
, SPR_440_DTV0
, "DTV0",
1598 SPR_NOACCESS
, SPR_NOACCESS
,
1599 &spr_read_generic
, &spr_write_generic
,
1601 /* XXX : not implemented */
1602 spr_register(env
, SPR_440_DTV1
, "DTV1",
1603 SPR_NOACCESS
, SPR_NOACCESS
,
1604 &spr_read_generic
, &spr_write_generic
,
1606 /* XXX : not implemented */
1607 spr_register(env
, SPR_440_DTV2
, "DTV2",
1608 SPR_NOACCESS
, SPR_NOACCESS
,
1609 &spr_read_generic
, &spr_write_generic
,
1611 /* XXX : not implemented */
1612 spr_register(env
, SPR_440_DTV3
, "DTV3",
1613 SPR_NOACCESS
, SPR_NOACCESS
,
1614 &spr_read_generic
, &spr_write_generic
,
1616 /* XXX : not implemented */
1617 spr_register(env
, SPR_440_DVLIM
, "DVLIM",
1618 SPR_NOACCESS
, SPR_NOACCESS
,
1619 &spr_read_generic
, &spr_write_generic
,
1621 /* XXX : not implemented */
1622 spr_register(env
, SPR_440_INV0
, "INV0",
1623 SPR_NOACCESS
, SPR_NOACCESS
,
1624 &spr_read_generic
, &spr_write_generic
,
1626 /* XXX : not implemented */
1627 spr_register(env
, SPR_440_INV1
, "INV1",
1628 SPR_NOACCESS
, SPR_NOACCESS
,
1629 &spr_read_generic
, &spr_write_generic
,
1631 /* XXX : not implemented */
1632 spr_register(env
, SPR_440_INV2
, "INV2",
1633 SPR_NOACCESS
, SPR_NOACCESS
,
1634 &spr_read_generic
, &spr_write_generic
,
1636 /* XXX : not implemented */
1637 spr_register(env
, SPR_440_INV3
, "INV3",
1638 SPR_NOACCESS
, SPR_NOACCESS
,
1639 &spr_read_generic
, &spr_write_generic
,
1641 /* XXX : not implemented */
1642 spr_register(env
, SPR_440_ITV0
, "ITV0",
1643 SPR_NOACCESS
, SPR_NOACCESS
,
1644 &spr_read_generic
, &spr_write_generic
,
1646 /* XXX : not implemented */
1647 spr_register(env
, SPR_440_ITV1
, "ITV1",
1648 SPR_NOACCESS
, SPR_NOACCESS
,
1649 &spr_read_generic
, &spr_write_generic
,
1651 /* XXX : not implemented */
1652 spr_register(env
, SPR_440_ITV2
, "ITV2",
1653 SPR_NOACCESS
, SPR_NOACCESS
,
1654 &spr_read_generic
, &spr_write_generic
,
1656 /* XXX : not implemented */
1657 spr_register(env
, SPR_440_ITV3
, "ITV3",
1658 SPR_NOACCESS
, SPR_NOACCESS
,
1659 &spr_read_generic
, &spr_write_generic
,
1661 /* XXX : not implemented */
1662 spr_register(env
, SPR_440_IVLIM
, "IVLIM",
1663 SPR_NOACCESS
, SPR_NOACCESS
,
1664 &spr_read_generic
, &spr_write_generic
,
1667 /* XXX : not implemented */
1668 spr_register(env
, SPR_BOOKE_DCDBTRH
, "DCDBTRH",
1669 SPR_NOACCESS
, SPR_NOACCESS
,
1670 &spr_read_generic
, SPR_NOACCESS
,
1672 /* XXX : not implemented */
1673 spr_register(env
, SPR_BOOKE_DCDBTRL
, "DCDBTRL",
1674 SPR_NOACCESS
, SPR_NOACCESS
,
1675 &spr_read_generic
, SPR_NOACCESS
,
1677 /* XXX : not implemented */
1678 spr_register(env
, SPR_BOOKE_ICDBDR
, "ICDBDR",
1679 SPR_NOACCESS
, SPR_NOACCESS
,
1680 &spr_read_generic
, SPR_NOACCESS
,
1682 /* XXX : not implemented */
1683 spr_register(env
, SPR_BOOKE_ICDBTRH
, "ICDBTRH",
1684 SPR_NOACCESS
, SPR_NOACCESS
,
1685 &spr_read_generic
, SPR_NOACCESS
,
1687 /* XXX : not implemented */
1688 spr_register(env
, SPR_BOOKE_ICDBTRL
, "ICDBTRL",
1689 SPR_NOACCESS
, SPR_NOACCESS
,
1690 &spr_read_generic
, SPR_NOACCESS
,
1692 /* XXX : not implemented */
1693 spr_register(env
, SPR_440_DBDR
, "DBDR",
1694 SPR_NOACCESS
, SPR_NOACCESS
,
1695 &spr_read_generic
, &spr_write_generic
,
1697 /* Processor control */
1698 spr_register(env
, SPR_4xx_CCR0
, "CCR0",
1699 SPR_NOACCESS
, SPR_NOACCESS
,
1700 &spr_read_generic
, &spr_write_generic
,
1702 spr_register(env
, SPR_440_RSTCFG
, "RSTCFG",
1703 SPR_NOACCESS
, SPR_NOACCESS
,
1704 &spr_read_generic
, SPR_NOACCESS
,
1706 /* Storage control */
1707 spr_register(env
, SPR_440_MMUCR
, "MMUCR",
1708 SPR_NOACCESS
, SPR_NOACCESS
,
1709 &spr_read_generic
, &spr_write_generic
,
1713 /* SPR shared between PowerPC 40x implementations */
1714 static void gen_spr_40x (CPUPPCState
*env
)
1717 /* XXX : not implemented */
1718 spr_register(env
, SPR_40x_DCCR
, "DCCR",
1719 SPR_NOACCESS
, SPR_NOACCESS
,
1720 &spr_read_generic
, &spr_write_generic
,
1722 /* XXX : not implemented */
1723 spr_register(env
, SPR_40x_ICCR
, "ICCR",
1724 SPR_NOACCESS
, SPR_NOACCESS
,
1725 &spr_read_generic
, &spr_write_generic
,
1727 /* XXX : not implemented */
1728 spr_register(env
, SPR_BOOKE_ICDBDR
, "ICDBDR",
1729 SPR_NOACCESS
, SPR_NOACCESS
,
1730 &spr_read_generic
, SPR_NOACCESS
,
1733 spr_register(env
, SPR_40x_DEAR
, "DEAR",
1734 SPR_NOACCESS
, SPR_NOACCESS
,
1735 &spr_read_generic
, &spr_write_generic
,
1737 spr_register(env
, SPR_40x_ESR
, "ESR",
1738 SPR_NOACCESS
, SPR_NOACCESS
,
1739 &spr_read_generic
, &spr_write_generic
,
1741 spr_register(env
, SPR_40x_EVPR
, "EVPR",
1742 SPR_NOACCESS
, SPR_NOACCESS
,
1743 &spr_read_generic
, &spr_write_generic
,
1745 spr_register(env
, SPR_40x_SRR2
, "SRR2",
1746 &spr_read_generic
, &spr_write_generic
,
1747 &spr_read_generic
, &spr_write_generic
,
1749 spr_register(env
, SPR_40x_SRR3
, "SRR3",
1750 &spr_read_generic
, &spr_write_generic
,
1751 &spr_read_generic
, &spr_write_generic
,
1754 spr_register(env
, SPR_40x_PIT
, "PIT",
1755 SPR_NOACCESS
, SPR_NOACCESS
,
1756 &spr_read_40x_pit
, &spr_write_40x_pit
,
1758 spr_register(env
, SPR_40x_TCR
, "TCR",
1759 SPR_NOACCESS
, SPR_NOACCESS
,
1760 &spr_read_generic
, &spr_write_booke_tcr
,
1762 spr_register(env
, SPR_40x_TSR
, "TSR",
1763 SPR_NOACCESS
, SPR_NOACCESS
,
1764 &spr_read_generic
, &spr_write_booke_tsr
,
1768 /* SPR specific to PowerPC 405 implementation */
1769 static void gen_spr_405 (CPUPPCState
*env
)
1772 spr_register(env
, SPR_40x_PID
, "PID",
1773 SPR_NOACCESS
, SPR_NOACCESS
,
1774 &spr_read_generic
, &spr_write_generic
,
1776 spr_register(env
, SPR_4xx_CCR0
, "CCR0",
1777 SPR_NOACCESS
, SPR_NOACCESS
,
1778 &spr_read_generic
, &spr_write_generic
,
1780 /* Debug interface */
1781 /* XXX : not implemented */
1782 spr_register(env
, SPR_40x_DBCR0
, "DBCR0",
1783 SPR_NOACCESS
, SPR_NOACCESS
,
1784 &spr_read_generic
, &spr_write_40x_dbcr0
,
1786 /* XXX : not implemented */
1787 spr_register(env
, SPR_405_DBCR1
, "DBCR1",
1788 SPR_NOACCESS
, SPR_NOACCESS
,
1789 &spr_read_generic
, &spr_write_generic
,
1791 /* XXX : not implemented */
1792 spr_register(env
, SPR_40x_DBSR
, "DBSR",
1793 SPR_NOACCESS
, SPR_NOACCESS
,
1794 &spr_read_generic
, &spr_write_clear
,
1795 /* Last reset was system reset */
1797 /* XXX : not implemented */
1798 spr_register(env
, SPR_40x_DAC1
, "DAC1",
1799 SPR_NOACCESS
, SPR_NOACCESS
,
1800 &spr_read_generic
, &spr_write_generic
,
1802 spr_register(env
, SPR_40x_DAC2
, "DAC2",
1803 SPR_NOACCESS
, SPR_NOACCESS
,
1804 &spr_read_generic
, &spr_write_generic
,
1806 /* XXX : not implemented */
1807 spr_register(env
, SPR_405_DVC1
, "DVC1",
1808 SPR_NOACCESS
, SPR_NOACCESS
,
1809 &spr_read_generic
, &spr_write_generic
,
1811 /* XXX : not implemented */
1812 spr_register(env
, SPR_405_DVC2
, "DVC2",
1813 SPR_NOACCESS
, SPR_NOACCESS
,
1814 &spr_read_generic
, &spr_write_generic
,
1816 /* XXX : not implemented */
1817 spr_register(env
, SPR_40x_IAC1
, "IAC1",
1818 SPR_NOACCESS
, SPR_NOACCESS
,
1819 &spr_read_generic
, &spr_write_generic
,
1821 spr_register(env
, SPR_40x_IAC2
, "IAC2",
1822 SPR_NOACCESS
, SPR_NOACCESS
,
1823 &spr_read_generic
, &spr_write_generic
,
1825 /* XXX : not implemented */
1826 spr_register(env
, SPR_405_IAC3
, "IAC3",
1827 SPR_NOACCESS
, SPR_NOACCESS
,
1828 &spr_read_generic
, &spr_write_generic
,
1830 /* XXX : not implemented */
1831 spr_register(env
, SPR_405_IAC4
, "IAC4",
1832 SPR_NOACCESS
, SPR_NOACCESS
,
1833 &spr_read_generic
, &spr_write_generic
,
1835 /* Storage control */
1836 spr_register(env
, SPR_405_SLER
, "SLER",
1837 SPR_NOACCESS
, SPR_NOACCESS
,
1838 &spr_read_generic
, &spr_write_40x_sler
,
1840 spr_register(env
, SPR_40x_ZPR
, "ZPR",
1841 SPR_NOACCESS
, SPR_NOACCESS
,
1842 &spr_read_generic
, &spr_write_generic
,
1844 /* XXX : not implemented */
1845 spr_register(env
, SPR_405_SU0R
, "SU0R",
1846 SPR_NOACCESS
, SPR_NOACCESS
,
1847 &spr_read_generic
, &spr_write_generic
,
1850 spr_register(env
, SPR_USPRG0
, "USPRG0",
1851 &spr_read_ureg
, SPR_NOACCESS
,
1852 &spr_read_ureg
, SPR_NOACCESS
,
1854 spr_register(env
, SPR_SPRG4
, "SPRG4",
1855 SPR_NOACCESS
, SPR_NOACCESS
,
1856 &spr_read_generic
, &spr_write_generic
,
1858 spr_register(env
, SPR_USPRG4
, "USPRG4",
1859 &spr_read_ureg
, SPR_NOACCESS
,
1860 &spr_read_ureg
, SPR_NOACCESS
,
1862 spr_register(env
, SPR_SPRG5
, "SPRG5",
1863 SPR_NOACCESS
, SPR_NOACCESS
,
1864 spr_read_generic
, &spr_write_generic
,
1866 spr_register(env
, SPR_USPRG5
, "USPRG5",
1867 &spr_read_ureg
, SPR_NOACCESS
,
1868 &spr_read_ureg
, SPR_NOACCESS
,
1870 spr_register(env
, SPR_SPRG6
, "SPRG6",
1871 SPR_NOACCESS
, SPR_NOACCESS
,
1872 spr_read_generic
, &spr_write_generic
,
1874 spr_register(env
, SPR_USPRG6
, "USPRG6",
1875 &spr_read_ureg
, SPR_NOACCESS
,
1876 &spr_read_ureg
, SPR_NOACCESS
,
1878 spr_register(env
, SPR_SPRG7
, "SPRG7",
1879 SPR_NOACCESS
, SPR_NOACCESS
,
1880 spr_read_generic
, &spr_write_generic
,
1882 spr_register(env
, SPR_USPRG7
, "USPRG7",
1883 &spr_read_ureg
, SPR_NOACCESS
,
1884 &spr_read_ureg
, SPR_NOACCESS
,
1888 /* SPR shared between PowerPC 401 & 403 implementations */
1889 static void gen_spr_401_403 (CPUPPCState
*env
)
1892 spr_register(env
, SPR_403_VTBL
, "TBL",
1893 &spr_read_tbl
, SPR_NOACCESS
,
1894 &spr_read_tbl
, SPR_NOACCESS
,
1896 spr_register(env
, SPR_403_TBL
, "TBL",
1897 SPR_NOACCESS
, SPR_NOACCESS
,
1898 SPR_NOACCESS
, &spr_write_tbl
,
1900 spr_register(env
, SPR_403_VTBU
, "TBU",
1901 &spr_read_tbu
, SPR_NOACCESS
,
1902 &spr_read_tbu
, SPR_NOACCESS
,
1904 spr_register(env
, SPR_403_TBU
, "TBU",
1905 SPR_NOACCESS
, SPR_NOACCESS
,
1906 SPR_NOACCESS
, &spr_write_tbu
,
1909 /* XXX: not implemented */
1910 spr_register(env
, SPR_403_CDBCR
, "CDBCR",
1911 SPR_NOACCESS
, SPR_NOACCESS
,
1912 &spr_read_generic
, &spr_write_generic
,
1916 /* SPR specific to PowerPC 401 implementation */
1917 static void gen_spr_401 (CPUPPCState
*env
)
1919 /* Debug interface */
1920 /* XXX : not implemented */
1921 spr_register(env
, SPR_40x_DBCR0
, "DBCR",
1922 SPR_NOACCESS
, SPR_NOACCESS
,
1923 &spr_read_generic
, &spr_write_40x_dbcr0
,
1925 /* XXX : not implemented */
1926 spr_register(env
, SPR_40x_DBSR
, "DBSR",
1927 SPR_NOACCESS
, SPR_NOACCESS
,
1928 &spr_read_generic
, &spr_write_clear
,
1929 /* Last reset was system reset */
1931 /* XXX : not implemented */
1932 spr_register(env
, SPR_40x_DAC1
, "DAC",
1933 SPR_NOACCESS
, SPR_NOACCESS
,
1934 &spr_read_generic
, &spr_write_generic
,
1936 /* XXX : not implemented */
1937 spr_register(env
, SPR_40x_IAC1
, "IAC",
1938 SPR_NOACCESS
, SPR_NOACCESS
,
1939 &spr_read_generic
, &spr_write_generic
,
1941 /* Storage control */
1942 spr_register(env
, SPR_405_SLER
, "SLER",
1943 SPR_NOACCESS
, SPR_NOACCESS
,
1944 &spr_read_generic
, &spr_write_40x_sler
,
1948 static void gen_spr_401x2 (CPUPPCState
*env
)
1951 spr_register(env
, SPR_40x_PID
, "PID",
1952 SPR_NOACCESS
, SPR_NOACCESS
,
1953 &spr_read_generic
, &spr_write_generic
,
1955 spr_register(env
, SPR_40x_ZPR
, "ZPR",
1956 SPR_NOACCESS
, SPR_NOACCESS
,
1957 &spr_read_generic
, &spr_write_generic
,
1961 /* SPR specific to PowerPC 403 implementation */
1962 static void gen_spr_403 (CPUPPCState
*env
)
1964 /* Debug interface */
1965 /* XXX : not implemented */
1966 spr_register(env
, SPR_40x_DBCR0
, "DBCR0",
1967 SPR_NOACCESS
, SPR_NOACCESS
,
1968 &spr_read_generic
, &spr_write_40x_dbcr0
,
1970 /* XXX : not implemented */
1971 spr_register(env
, SPR_40x_DBSR
, "DBSR",
1972 SPR_NOACCESS
, SPR_NOACCESS
,
1973 &spr_read_generic
, &spr_write_clear
,
1974 /* Last reset was system reset */
1976 /* XXX : not implemented */
1977 spr_register(env
, SPR_40x_DAC1
, "DAC1",
1978 SPR_NOACCESS
, SPR_NOACCESS
,
1979 &spr_read_generic
, &spr_write_generic
,
1981 spr_register(env
, SPR_40x_DAC2
, "DAC2",
1982 SPR_NOACCESS
, SPR_NOACCESS
,
1983 &spr_read_generic
, &spr_write_generic
,
1985 /* XXX : not implemented */
1986 spr_register(env
, SPR_40x_IAC1
, "IAC1",
1987 SPR_NOACCESS
, SPR_NOACCESS
,
1988 &spr_read_generic
, &spr_write_generic
,
1990 spr_register(env
, SPR_40x_IAC2
, "IAC2",
1991 SPR_NOACCESS
, SPR_NOACCESS
,
1992 &spr_read_generic
, &spr_write_generic
,
1996 static void gen_spr_403_real (CPUPPCState
*env
)
1998 spr_register(env
, SPR_403_PBL1
, "PBL1",
1999 SPR_NOACCESS
, SPR_NOACCESS
,
2000 &spr_read_403_pbr
, &spr_write_403_pbr
,
2002 spr_register(env
, SPR_403_PBU1
, "PBU1",
2003 SPR_NOACCESS
, SPR_NOACCESS
,
2004 &spr_read_403_pbr
, &spr_write_403_pbr
,
2006 spr_register(env
, SPR_403_PBL2
, "PBL2",
2007 SPR_NOACCESS
, SPR_NOACCESS
,
2008 &spr_read_403_pbr
, &spr_write_403_pbr
,
2010 spr_register(env
, SPR_403_PBU2
, "PBU2",
2011 SPR_NOACCESS
, SPR_NOACCESS
,
2012 &spr_read_403_pbr
, &spr_write_403_pbr
,
2016 static void gen_spr_403_mmu (CPUPPCState
*env
)
2019 spr_register(env
, SPR_40x_PID
, "PID",
2020 SPR_NOACCESS
, SPR_NOACCESS
,
2021 &spr_read_generic
, &spr_write_generic
,
2023 spr_register(env
, SPR_40x_ZPR
, "ZPR",
2024 SPR_NOACCESS
, SPR_NOACCESS
,
2025 &spr_read_generic
, &spr_write_generic
,
2029 /* SPR specific to PowerPC compression coprocessor extension */
2030 static void gen_spr_compress (CPUPPCState
*env
)
2032 spr_register(env
, SPR_401_SKR
, "SKR",
2033 SPR_NOACCESS
, SPR_NOACCESS
,
2034 &spr_read_generic
, &spr_write_generic
,
2038 #if defined (TARGET_PPC64)
2040 /* SPR specific to PowerPC 620 */
2041 static void gen_spr_620 (CPUPPCState
*env
)
2043 spr_register(env
, SPR_620_PMR0
, "PMR0",
2044 SPR_NOACCESS
, SPR_NOACCESS
,
2045 &spr_read_generic
, &spr_write_generic
,
2047 spr_register(env
, SPR_620_PMR1
, "PMR1",
2048 SPR_NOACCESS
, SPR_NOACCESS
,
2049 &spr_read_generic
, &spr_write_generic
,
2051 spr_register(env
, SPR_620_PMR2
, "PMR2",
2052 SPR_NOACCESS
, SPR_NOACCESS
,
2053 &spr_read_generic
, &spr_write_generic
,
2055 spr_register(env
, SPR_620_PMR3
, "PMR3",
2056 SPR_NOACCESS
, SPR_NOACCESS
,
2057 &spr_read_generic
, &spr_write_generic
,
2059 spr_register(env
, SPR_620_PMR4
, "PMR4",
2060 SPR_NOACCESS
, SPR_NOACCESS
,
2061 &spr_read_generic
, &spr_write_generic
,
2063 spr_register(env
, SPR_620_PMR5
, "PMR5",
2064 SPR_NOACCESS
, SPR_NOACCESS
,
2065 &spr_read_generic
, &spr_write_generic
,
2067 spr_register(env
, SPR_620_PMR6
, "PMR6",
2068 SPR_NOACCESS
, SPR_NOACCESS
,
2069 &spr_read_generic
, &spr_write_generic
,
2071 spr_register(env
, SPR_620_PMR7
, "PMR7",
2072 SPR_NOACCESS
, SPR_NOACCESS
,
2073 &spr_read_generic
, &spr_write_generic
,
2075 spr_register(env
, SPR_620_PMR8
, "PMR8",
2076 SPR_NOACCESS
, SPR_NOACCESS
,
2077 &spr_read_generic
, &spr_write_generic
,
2079 spr_register(env
, SPR_620_PMR9
, "PMR9",
2080 SPR_NOACCESS
, SPR_NOACCESS
,
2081 &spr_read_generic
, &spr_write_generic
,
2083 spr_register(env
, SPR_620_PMRA
, "PMR10",
2084 SPR_NOACCESS
, SPR_NOACCESS
,
2085 &spr_read_generic
, &spr_write_generic
,
2087 spr_register(env
, SPR_620_PMRB
, "PMR11",
2088 SPR_NOACCESS
, SPR_NOACCESS
,
2089 &spr_read_generic
, &spr_write_generic
,
2091 spr_register(env
, SPR_620_PMRC
, "PMR12",
2092 SPR_NOACCESS
, SPR_NOACCESS
,
2093 &spr_read_generic
, &spr_write_generic
,
2095 spr_register(env
, SPR_620_PMRD
, "PMR13",
2096 SPR_NOACCESS
, SPR_NOACCESS
,
2097 &spr_read_generic
, &spr_write_generic
,
2099 spr_register(env
, SPR_620_PMRE
, "PMR14",
2100 SPR_NOACCESS
, SPR_NOACCESS
,
2101 &spr_read_generic
, &spr_write_generic
,
2103 spr_register(env
, SPR_620_PMRF
, "PMR15",
2104 SPR_NOACCESS
, SPR_NOACCESS
,
2105 &spr_read_generic
, &spr_write_generic
,
2107 spr_register(env
, SPR_620_HID8
, "HID8",
2108 SPR_NOACCESS
, SPR_NOACCESS
,
2109 &spr_read_generic
, &spr_write_generic
,
2111 spr_register(env
, SPR_620_HID9
, "HID9",
2112 SPR_NOACCESS
, SPR_NOACCESS
,
2113 &spr_read_generic
, &spr_write_generic
,
2117 #endif /* defined (TARGET_PPC64) */
2121 * AMR => SPR 29 (Power 2.04)
2122 * CTRL => SPR 136 (Power 2.04)
2123 * CTRL => SPR 152 (Power 2.04)
2124 * SCOMC => SPR 276 (64 bits ?)
2125 * SCOMD => SPR 277 (64 bits ?)
2126 * ASR => SPR 280 (64 bits)
2127 * TBU40 => SPR 286 (Power 2.04 hypv)
2128 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2129 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2130 * HDSISR => SPR 306 (Power 2.04 hypv)
2131 * HDAR => SPR 307 (Power 2.04 hypv)
2132 * PURR => SPR 309 (Power 2.04 hypv)
2133 * HDEC => SPR 310 (Power 2.04 hypv)
2134 * HIOR => SPR 311 (hypv)
2135 * RMOR => SPR 312 (970)
2136 * HRMOR => SPR 313 (Power 2.04 hypv)
2137 * HSRR0 => SPR 314 (Power 2.04 hypv)
2138 * HSRR1 => SPR 315 (Power 2.04 hypv)
2139 * LPCR => SPR 316 (970)
2140 * LPIDR => SPR 317 (970)
2141 * SPEFSCR => SPR 512 (Power 2.04 emb)
2142 * ATBL => SPR 526 (Power 2.04 emb)
2143 * ATBU => SPR 527 (Power 2.04 emb)
2144 * EPR => SPR 702 (Power 2.04 emb)
2145 * perf => 768-783 (Power 2.04)
2146 * perf => 784-799 (Power 2.04)
2147 * PPR => SPR 896 (Power 2.04)
2148 * EPLC => SPR 947 (Power 2.04 emb)
2149 * EPSC => SPR 948 (Power 2.04 emb)
2150 * DABRX => 1015 (Power 2.04 hypv)
2151 * FPECR => SPR 1022 (?)
2152 * ... and more (thermal management, performance counters, ...)
2155 /*****************************************************************************/
2156 /* PowerPC implementations definitions */
2158 /* PowerPC 40x instruction set */
2159 #define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_EMB_COMMON)
2162 #define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | \
2163 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2164 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2165 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
2166 #define POWERPC_MMU_401 (POWERPC_MMU_REAL_4xx)
2167 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
2168 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
2169 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
2171 static void init_proc_401 (CPUPPCState
*env
)
2174 gen_spr_401_403(env
);
2176 /* Bus access control */
2177 spr_register(env
, SPR_40x_SGR
, "SGR",
2178 SPR_NOACCESS
, SPR_NOACCESS
,
2179 &spr_read_generic
, &spr_write_generic
,
2181 /* XXX : not implemented */
2182 spr_register(env
, SPR_40x_DCWR
, "DCWR",
2183 SPR_NOACCESS
, SPR_NOACCESS
,
2184 &spr_read_generic
, &spr_write_generic
,
2186 /* XXX: TODO: allocate internal IRQ controller */
2190 #define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | \
2191 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2192 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2193 PPC_CACHE_DCBA | PPC_MFTB | \
2194 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2195 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
2196 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
2197 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
2198 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
2199 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
2201 static void init_proc_401x2 (CPUPPCState
*env
)
2204 gen_spr_401_403(env
);
2206 gen_spr_compress(env
);
2207 /* Bus access control */
2208 spr_register(env
, SPR_40x_SGR
, "SGR",
2209 SPR_NOACCESS
, SPR_NOACCESS
,
2210 &spr_read_generic
, &spr_write_generic
,
2212 /* XXX : not implemented */
2213 spr_register(env
, SPR_40x_DCWR
, "DCWR",
2214 SPR_NOACCESS
, SPR_NOACCESS
,
2215 &spr_read_generic
, &spr_write_generic
,
2217 /* Memory management */
2221 /* XXX: TODO: allocate internal IRQ controller */
2226 #define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | \
2227 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2228 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2229 PPC_CACHE_DCBA | PPC_MFTB | \
2230 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2231 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
2232 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
2233 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
2234 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
2235 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
2237 static void init_proc_401x2 (CPUPPCState
*env
)
2243 #define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | \
2244 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2245 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2247 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2248 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
2249 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
2250 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
2251 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
2252 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
2254 static void init_proc_IOP480 (CPUPPCState
*env
)
2257 gen_spr_401_403(env
);
2259 gen_spr_compress(env
);
2260 /* Bus access control */
2261 spr_register(env
, SPR_40x_SGR
, "SGR",
2262 SPR_NOACCESS
, SPR_NOACCESS
,
2263 &spr_read_generic
, &spr_write_generic
,
2265 /* XXX : not implemented */
2266 spr_register(env
, SPR_40x_DCWR
, "DCWR",
2267 SPR_NOACCESS
, SPR_NOACCESS
,
2268 &spr_read_generic
, &spr_write_generic
,
2270 /* Memory management */
2274 /* XXX: TODO: allocate internal IRQ controller */
2278 #define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | \
2279 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2280 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2281 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2282 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
2283 #define POWERPC_MMU_403 (POWERPC_MMU_REAL_4xx)
2284 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
2285 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
2286 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
2288 static void init_proc_403 (CPUPPCState
*env
)
2291 gen_spr_401_403(env
);
2293 gen_spr_403_real(env
);
2294 /* XXX: TODO: allocate internal IRQ controller */
2297 /* PowerPC 403 GCX */
2298 #define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | \
2299 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2300 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2301 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2302 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
2303 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
2304 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
2305 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
2306 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
2308 static void init_proc_403GCX (CPUPPCState
*env
)
2311 gen_spr_401_403(env
);
2313 gen_spr_403_real(env
);
2314 gen_spr_403_mmu(env
);
2315 /* Bus access control */
2316 spr_register(env
, SPR_40x_SGR
, "SGR",
2317 SPR_NOACCESS
, SPR_NOACCESS
,
2318 &spr_read_generic
, &spr_write_generic
,
2320 /* XXX : not implemented */
2321 spr_register(env
, SPR_40x_DCWR
, "DCWR",
2322 SPR_NOACCESS
, SPR_NOACCESS
,
2323 &spr_read_generic
, &spr_write_generic
,
2325 /* Memory management */
2329 /* XXX: TODO: allocate internal IRQ controller */
2333 #define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_MFTB | \
2334 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2335 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2336 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
2338 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
2339 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
2340 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
2341 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
2342 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
2344 static void init_proc_405 (CPUPPCState
*env
)
2350 /* Bus access control */
2351 spr_register(env
, SPR_40x_SGR
, "SGR",
2352 SPR_NOACCESS
, SPR_NOACCESS
,
2353 &spr_read_generic
, &spr_write_generic
,
2355 /* XXX : not implemented */
2356 spr_register(env
, SPR_40x_DCWR
, "DCWR",
2357 SPR_NOACCESS
, SPR_NOACCESS
,
2358 &spr_read_generic
, &spr_write_generic
,
2360 /* Memory management */
2364 /* Allocate hardware IRQ controller */
2365 ppc405_irq_init(env
);
2368 /* PowerPC 440 EP */
2369 #define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | \
2370 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2371 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2372 PPC_440_SPEC | PPC_RFMCI)
2373 #define POWERPC_MSRM_440EP (0x000000000006D630ULL)
2374 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
2375 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
2376 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
2377 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
2379 static void init_proc_440EP (CPUPPCState
*env
)
2385 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
2386 SPR_NOACCESS
, SPR_NOACCESS
,
2387 &spr_read_generic
, &spr_write_generic
,
2389 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
2390 SPR_NOACCESS
, SPR_NOACCESS
,
2391 &spr_read_generic
, &spr_write_generic
,
2393 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
2394 SPR_NOACCESS
, SPR_NOACCESS
,
2395 &spr_read_generic
, &spr_write_generic
,
2397 spr_register(env
, SPR_440_CCR1
, "CCR1",
2398 SPR_NOACCESS
, SPR_NOACCESS
,
2399 &spr_read_generic
, &spr_write_generic
,
2401 /* Memory management */
2405 /* XXX: TODO: allocate internal IRQ controller */
2408 /* PowerPC 440 GP */
2409 #define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | \
2410 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2411 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2412 PPC_405_MAC | PPC_440_SPEC)
2413 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
2414 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
2415 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
2416 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
2417 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
2419 static void init_proc_440GP (CPUPPCState
*env
)
2425 /* Memory management */
2429 /* XXX: TODO: allocate internal IRQ controller */
2434 #define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | \
2435 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2436 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2438 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
2439 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
2440 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
2441 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
2442 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
2444 static void init_proc_440x4 (CPUPPCState
*env
)
2450 /* Memory management */
2454 /* XXX: TODO: allocate internal IRQ controller */
2459 #define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | \
2460 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2461 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2462 PPC_440_SPEC | PPC_RFMCI)
2463 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
2464 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
2465 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
2466 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
2467 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
2469 static void init_proc_440x5 (CPUPPCState
*env
)
2475 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
2476 SPR_NOACCESS
, SPR_NOACCESS
,
2477 &spr_read_generic
, &spr_write_generic
,
2479 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
2480 SPR_NOACCESS
, SPR_NOACCESS
,
2481 &spr_read_generic
, &spr_write_generic
,
2483 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
2484 SPR_NOACCESS
, SPR_NOACCESS
,
2485 &spr_read_generic
, &spr_write_generic
,
2487 spr_register(env
, SPR_440_CCR1
, "CCR1",
2488 SPR_NOACCESS
, SPR_NOACCESS
,
2489 &spr_read_generic
, &spr_write_generic
,
2491 /* Memory management */
2495 /* XXX: TODO: allocate internal IRQ controller */
2498 /* PowerPC 460 (guessed) */
2500 #define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
2501 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2502 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2503 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
2504 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
2505 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
2506 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
2507 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
2508 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
2510 static void init_proc_460 (CPUPPCState
*env
)
2515 /* PowerPC 460F (guessed) */
2517 #define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
2518 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2519 PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
2520 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
2521 PPC_FLOAT_STFIWX | \
2522 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2523 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
2524 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
2525 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
2526 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
2527 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
2528 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
2530 static void init_proc_460 (CPUPPCState
*env
)
2536 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
2537 SPR_NOACCESS
, SPR_NOACCESS
,
2538 &spr_read_generic
, &spr_write_generic
,
2540 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
2541 SPR_NOACCESS
, SPR_NOACCESS
,
2542 &spr_read_generic
, &spr_write_generic
,
2544 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
2545 SPR_NOACCESS
, SPR_NOACCESS
,
2546 &spr_read_generic
, &spr_write_generic
,
2548 spr_register(env
, SPR_440_CCR1
, "CCR1",
2549 SPR_NOACCESS
, SPR_NOACCESS
,
2550 &spr_read_generic
, &spr_write_generic
,
2552 spr_register(env
, SPR_DCRIPR
, "SPR_DCRIPR",
2553 &spr_read_generic
, &spr_write_generic
,
2554 &spr_read_generic
, &spr_write_generic
,
2556 /* Memory management */
2560 /* XXX: TODO: allocate internal IRQ controller */
2564 /* Generic BookE PowerPC */
2566 #define POWERPC_INSNS_BookE (POWERPC_INSNS_EMB | \
2567 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
2569 PPC_FLOAT | PPC_FLOAT_FSQRT | \
2570 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
2571 PPC_FLOAT_FSEL | PPC_FLOAT_STFIW | \
2573 #define POWERPC_MSRM_BookE (0x000000000006D630ULL)
2574 #define POWERPC_MMU_BookE (POWERPC_MMU_BOOKE)
2575 #define POWERPC_EXCP_BookE (POWERPC_EXCP_BOOKE)
2576 #define POWERPC_INPUT_BookE (PPC_FLAGS_INPUT_BookE)
2577 #define POWERPC_BFDM_BookE (bfd_mach_ppc_403)
2579 static void init_proc_BookE (CPUPPCState
*env
)
2594 #define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | \
2595 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
2597 PPC_BOOKE | PPC_E500_VECTOR)
2598 #define POWERPC_MMU_e500 (POWERPC_MMU_SOFT_4xx)
2599 #define POWERPC_EXCP_e500 (POWERPC_EXCP_40x)
2600 #define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
2601 #define POWERPC_BFDM_e500 (bfd_mach_ppc_403)
2603 static void init_proc_e500 (CPUPPCState
*env
)
2608 /* Memory management */
2609 gen_spr_BookE_FSL(env
);
2613 /* XXX: TODO: allocate internal IRQ controller */
2621 /* Non-embedded PowerPC */
2622 /* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
2623 #define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
2624 PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
2625 /* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */
2626 #define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
2627 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
2628 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
2629 PPC_MEM_TLBSYNC | PPC_MFTB)
2631 /* POWER : same as 601, without mfmsr, mfsr */
2633 #define POWERPC_INSNS_POWER (XXX_TODO)
2634 /* POWER RSC (from RAD6000) */
2635 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
2639 #define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_EXTERN | PPC_POWER_BR)
2640 #define POWERPC_MSRM_601 (0x000000000000FE70ULL)
2641 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
2642 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
2643 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
2644 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
2646 static void init_proc_601 (CPUPPCState
*env
)
2648 gen_spr_ne_601(env
);
2650 /* Hardware implementation registers */
2651 /* XXX : not implemented */
2652 spr_register(env
, SPR_HID0
, "HID0",
2653 SPR_NOACCESS
, SPR_NOACCESS
,
2654 &spr_read_generic
, &spr_write_generic
,
2656 /* XXX : not implemented */
2657 spr_register(env
, SPR_HID1
, "HID1",
2658 SPR_NOACCESS
, SPR_NOACCESS
,
2659 &spr_read_generic
, &spr_write_generic
,
2661 /* XXX : not implemented */
2662 spr_register(env
, SPR_601_HID2
, "HID2",
2663 SPR_NOACCESS
, SPR_NOACCESS
,
2664 &spr_read_generic
, &spr_write_generic
,
2666 /* XXX : not implemented */
2667 spr_register(env
, SPR_601_HID5
, "HID5",
2668 SPR_NOACCESS
, SPR_NOACCESS
,
2669 &spr_read_generic
, &spr_write_generic
,
2671 /* XXX : not implemented */
2672 spr_register(env
, SPR_601_HID15
, "HID15",
2673 SPR_NOACCESS
, SPR_NOACCESS
,
2674 &spr_read_generic
, &spr_write_generic
,
2676 /* Memory management */
2681 /* XXX: TODO: allocate internal IRQ controller */
2685 #define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \
2686 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
2687 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
2688 PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_602_SPEC)
2689 #define POWERPC_MSRM_602 (0x000000000033FF73ULL)
2690 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
2691 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
2692 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
2693 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
2695 static void init_proc_602 (CPUPPCState
*env
)
2697 gen_spr_ne_601(env
);
2701 /* hardware implementation registers */
2702 /* XXX : not implemented */
2703 spr_register(env
, SPR_HID0
, "HID0",
2704 SPR_NOACCESS
, SPR_NOACCESS
,
2705 &spr_read_generic
, &spr_write_generic
,
2707 /* XXX : not implemented */
2708 spr_register(env
, SPR_HID1
, "HID1",
2709 SPR_NOACCESS
, SPR_NOACCESS
,
2710 &spr_read_generic
, &spr_write_generic
,
2712 /* Memory management */
2714 gen_6xx_7xx_soft_tlb(env
, 64, 2);
2715 /* Allocate hardware IRQ controller */
2716 ppc6xx_irq_init(env
);
2720 #define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
2721 #define POWERPC_MSRM_603 (0x000000000001FF73ULL)
2722 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
2723 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
2724 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
2725 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
2727 static void init_proc_603 (CPUPPCState
*env
)
2729 gen_spr_ne_601(env
);
2733 /* hardware implementation registers */
2734 /* XXX : not implemented */
2735 spr_register(env
, SPR_HID0
, "HID0",
2736 SPR_NOACCESS
, SPR_NOACCESS
,
2737 &spr_read_generic
, &spr_write_generic
,
2739 /* XXX : not implemented */
2740 spr_register(env
, SPR_HID1
, "HID1",
2741 SPR_NOACCESS
, SPR_NOACCESS
,
2742 &spr_read_generic
, &spr_write_generic
,
2744 /* Memory management */
2746 gen_6xx_7xx_soft_tlb(env
, 64, 2);
2747 /* Allocate hardware IRQ controller */
2748 ppc6xx_irq_init(env
);
2752 #define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
2753 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
2754 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
2755 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
2756 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
2757 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
2759 static void init_proc_603E (CPUPPCState
*env
)
2761 gen_spr_ne_601(env
);
2765 /* hardware implementation registers */
2766 /* XXX : not implemented */
2767 spr_register(env
, SPR_HID0
, "HID0",
2768 SPR_NOACCESS
, SPR_NOACCESS
,
2769 &spr_read_generic
, &spr_write_generic
,
2771 /* XXX : not implemented */
2772 spr_register(env
, SPR_HID1
, "HID1",
2773 SPR_NOACCESS
, SPR_NOACCESS
,
2774 &spr_read_generic
, &spr_write_generic
,
2776 /* XXX : not implemented */
2777 spr_register(env
, SPR_IABR
, "IABR",
2778 SPR_NOACCESS
, SPR_NOACCESS
,
2779 &spr_read_generic
, &spr_write_generic
,
2781 /* Memory management */
2783 gen_6xx_7xx_soft_tlb(env
, 64, 2);
2784 /* Allocate hardware IRQ controller */
2785 ppc6xx_irq_init(env
);
2789 #define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
2790 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
2791 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
2792 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
2793 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
2794 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
2796 static void init_proc_G2 (CPUPPCState
*env
)
2798 gen_spr_ne_601(env
);
2799 gen_spr_G2_755(env
);
2803 /* Hardware implementation register */
2804 /* XXX : not implemented */
2805 spr_register(env
, SPR_HID0
, "HID0",
2806 SPR_NOACCESS
, SPR_NOACCESS
,
2807 &spr_read_generic
, &spr_write_generic
,
2809 /* XXX : not implemented */
2810 spr_register(env
, SPR_HID1
, "HID1",
2811 SPR_NOACCESS
, SPR_NOACCESS
,
2812 &spr_read_generic
, &spr_write_generic
,
2814 /* XXX : not implemented */
2815 spr_register(env
, SPR_HID2
, "HID2",
2816 SPR_NOACCESS
, SPR_NOACCESS
,
2817 &spr_read_generic
, &spr_write_generic
,
2819 /* Memory management */
2822 gen_6xx_7xx_soft_tlb(env
, 64, 2);
2823 /* Allocate hardware IRQ controller */
2824 ppc6xx_irq_init(env
);
2828 #define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
2829 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
2830 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
2831 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
2832 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
2833 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
2835 static void init_proc_G2LE (CPUPPCState
*env
)
2837 gen_spr_ne_601(env
);
2838 gen_spr_G2_755(env
);
2842 /* Hardware implementation register */
2843 /* XXX : not implemented */
2844 spr_register(env
, SPR_HID0
, "HID0",
2845 SPR_NOACCESS
, SPR_NOACCESS
,
2846 &spr_read_generic
, &spr_write_generic
,
2848 /* XXX : not implemented */
2849 spr_register(env
, SPR_HID1
, "HID1",
2850 SPR_NOACCESS
, SPR_NOACCESS
,
2851 &spr_read_generic
, &spr_write_generic
,
2853 /* XXX : not implemented */
2854 spr_register(env
, SPR_HID2
, "HID2",
2855 SPR_NOACCESS
, SPR_NOACCESS
,
2856 &spr_read_generic
, &spr_write_generic
,
2858 /* Memory management */
2861 gen_6xx_7xx_soft_tlb(env
, 64, 2);
2862 /* Allocate hardware IRQ controller */
2863 ppc6xx_irq_init(env
);
2867 #define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN)
2868 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
2869 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
2870 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
2871 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
2872 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
2874 static void init_proc_604 (CPUPPCState
*env
)
2876 gen_spr_ne_601(env
);
2880 /* Hardware implementation registers */
2881 /* XXX : not implemented */
2882 spr_register(env
, SPR_HID0
, "HID0",
2883 SPR_NOACCESS
, SPR_NOACCESS
,
2884 &spr_read_generic
, &spr_write_generic
,
2886 /* XXX : not implemented */
2887 spr_register(env
, SPR_HID1
, "HID1",
2888 SPR_NOACCESS
, SPR_NOACCESS
,
2889 &spr_read_generic
, &spr_write_generic
,
2891 /* Memory management */
2893 /* Allocate hardware IRQ controller */
2894 ppc6xx_irq_init(env
);
2897 /* PowerPC 740/750 (aka G3) */
2898 #define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN)
2899 #define POWERPC_MSRM_7x0 (0x000000000007FF77ULL)
2900 #define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
2901 //#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
2902 #define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)
2903 #define POWERPC_BFDM_7x0 (bfd_mach_ppc_750)
2905 static void init_proc_7x0 (CPUPPCState
*env
)
2907 gen_spr_ne_601(env
);
2911 /* Thermal management */
2913 /* Hardware implementation registers */
2914 /* XXX : not implemented */
2915 spr_register(env
, SPR_HID0
, "HID0",
2916 SPR_NOACCESS
, SPR_NOACCESS
,
2917 &spr_read_generic
, &spr_write_generic
,
2919 /* XXX : not implemented */
2920 spr_register(env
, SPR_HID1
, "HID1",
2921 SPR_NOACCESS
, SPR_NOACCESS
,
2922 &spr_read_generic
, &spr_write_generic
,
2924 /* Memory management */
2926 /* Allocate hardware IRQ controller */
2927 ppc6xx_irq_init(env
);
2930 /* PowerPC 750FX/GX */
2931 #define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN)
2932 #define POWERPC_MSRM_750fx (0x000000000007FF77ULL)
2933 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
2934 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
2935 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
2936 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
2938 static void init_proc_750fx (CPUPPCState
*env
)
2940 gen_spr_ne_601(env
);
2944 /* Thermal management */
2946 /* Hardware implementation registers */
2947 /* XXX : not implemented */
2948 spr_register(env
, SPR_HID0
, "HID0",
2949 SPR_NOACCESS
, SPR_NOACCESS
,
2950 &spr_read_generic
, &spr_write_generic
,
2952 /* XXX : not implemented */
2953 spr_register(env
, SPR_HID1
, "HID1",
2954 SPR_NOACCESS
, SPR_NOACCESS
,
2955 &spr_read_generic
, &spr_write_generic
,
2957 /* XXX : not implemented */
2958 spr_register(env
, SPR_750_HID2
, "HID2",
2959 SPR_NOACCESS
, SPR_NOACCESS
,
2960 &spr_read_generic
, &spr_write_generic
,
2962 /* Memory management */
2964 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
2966 /* Allocate hardware IRQ controller */
2967 ppc6xx_irq_init(env
);
2970 /* PowerPC 745/755 */
2971 #define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
2972 #define POWERPC_MSRM_7x5 (0x000000000007FF77ULL)
2973 #define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
2974 //#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
2975 #define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)
2976 #define POWERPC_BFDM_7x5 (bfd_mach_ppc_750)
2978 static void init_proc_7x5 (CPUPPCState
*env
)
2980 gen_spr_ne_601(env
);
2981 gen_spr_G2_755(env
);
2984 /* L2 cache control */
2985 /* XXX : not implemented */
2986 spr_register(env
, SPR_ICTC
, "ICTC",
2987 SPR_NOACCESS
, SPR_NOACCESS
,
2988 &spr_read_generic
, &spr_write_generic
,
2990 /* XXX : not implemented */
2991 spr_register(env
, SPR_L2PMCR
, "L2PMCR",
2992 SPR_NOACCESS
, SPR_NOACCESS
,
2993 &spr_read_generic
, &spr_write_generic
,
2995 /* Hardware implementation registers */
2996 /* XXX : not implemented */
2997 spr_register(env
, SPR_HID0
, "HID0",
2998 SPR_NOACCESS
, SPR_NOACCESS
,
2999 &spr_read_generic
, &spr_write_generic
,
3001 /* XXX : not implemented */
3002 spr_register(env
, SPR_HID1
, "HID1",
3003 SPR_NOACCESS
, SPR_NOACCESS
,
3004 &spr_read_generic
, &spr_write_generic
,
3006 /* XXX : not implemented */
3007 spr_register(env
, SPR_HID2
, "HID2",
3008 SPR_NOACCESS
, SPR_NOACCESS
,
3009 &spr_read_generic
, &spr_write_generic
,
3011 /* Memory management */
3014 gen_6xx_7xx_soft_tlb(env
, 64, 2);
3015 /* Allocate hardware IRQ controller */
3016 ppc6xx_irq_init(env
);
3019 /* PowerPC 7400 (aka G4) */
3020 #define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3021 PPC_EXTERN | PPC_MEM_TLBIA | \
3023 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
3024 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
3025 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
3026 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
3027 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
3029 static void init_proc_7400 (CPUPPCState
*env
)
3031 gen_spr_ne_601(env
);
3035 /* 74xx specific SPR */
3037 /* Thermal management */
3039 /* Memory management */
3041 /* Allocate hardware IRQ controller */
3042 ppc6xx_irq_init(env
);
3045 /* PowerPC 7410 (aka G4) */
3046 #define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3047 PPC_EXTERN | PPC_MEM_TLBIA | \
3049 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
3050 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
3051 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
3052 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
3053 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
3055 static void init_proc_7410 (CPUPPCState
*env
)
3057 gen_spr_ne_601(env
);
3061 /* 74xx specific SPR */
3063 /* Thermal management */
3066 /* XXX : not implemented */
3067 spr_register(env
, SPR_L2PMCR
, "L2PMCR",
3068 SPR_NOACCESS
, SPR_NOACCESS
,
3069 &spr_read_generic
, &spr_write_generic
,
3072 /* XXX : not implemented */
3073 spr_register(env
, SPR_LDSTDB
, "LDSTDB",
3074 SPR_NOACCESS
, SPR_NOACCESS
,
3075 &spr_read_generic
, &spr_write_generic
,
3077 /* Memory management */
3079 /* Allocate hardware IRQ controller */
3080 ppc6xx_irq_init(env
);
3083 /* PowerPC 7440 (aka G4) */
3085 #define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3086 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3088 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
3089 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
3090 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
3091 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
3092 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
3094 static void init_proc_7440 (CPUPPCState
*env
)
3096 gen_spr_ne_601(env
);
3100 /* 74xx specific SPR */
3103 /* XXX : not implemented */
3104 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
3105 SPR_NOACCESS
, SPR_NOACCESS
,
3106 &spr_read_generic
, &spr_write_generic
,
3109 /* XXX : not implemented */
3110 spr_register(env
, SPR_ICTRL
, "ICTRL",
3111 SPR_NOACCESS
, SPR_NOACCESS
,
3112 &spr_read_generic
, &spr_write_generic
,
3115 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
3116 SPR_NOACCESS
, SPR_NOACCESS
,
3117 &spr_read_generic
, &spr_write_generic
,
3120 /* XXX : not implemented */
3121 spr_register(env
, SPR_PMC5
, "PMC5",
3122 SPR_NOACCESS
, SPR_NOACCESS
,
3123 &spr_read_generic
, &spr_write_generic
,
3125 spr_register(env
, SPR_UPMC5
, "UPMC5",
3126 &spr_read_ureg
, SPR_NOACCESS
,
3127 &spr_read_ureg
, SPR_NOACCESS
,
3129 spr_register(env
, SPR_PMC6
, "PMC6",
3130 SPR_NOACCESS
, SPR_NOACCESS
,
3131 &spr_read_generic
, &spr_write_generic
,
3133 spr_register(env
, SPR_UPMC6
, "UPMC6",
3134 &spr_read_ureg
, SPR_NOACCESS
,
3135 &spr_read_ureg
, SPR_NOACCESS
,
3137 /* Memory management */
3139 gen_74xx_soft_tlb(env
);
3140 /* Allocate hardware IRQ controller */
3141 ppc6xx_irq_init(env
);
3145 /* PowerPC 7450 (aka G4) */
3147 #define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3148 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3150 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
3151 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
3152 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
3153 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
3154 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
3156 static void init_proc_7450 (CPUPPCState
*env
)
3158 gen_spr_ne_601(env
);
3162 /* 74xx specific SPR */
3164 /* Level 3 cache control */
3167 /* XXX : not implemented */
3168 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
3169 SPR_NOACCESS
, SPR_NOACCESS
,
3170 &spr_read_generic
, &spr_write_generic
,
3173 /* XXX : not implemented */
3174 spr_register(env
, SPR_ICTRL
, "ICTRL",
3175 SPR_NOACCESS
, SPR_NOACCESS
,
3176 &spr_read_generic
, &spr_write_generic
,
3179 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
3180 SPR_NOACCESS
, SPR_NOACCESS
,
3181 &spr_read_generic
, &spr_write_generic
,
3184 /* XXX : not implemented */
3185 spr_register(env
, SPR_PMC5
, "PMC5",
3186 SPR_NOACCESS
, SPR_NOACCESS
,
3187 &spr_read_generic
, &spr_write_generic
,
3189 spr_register(env
, SPR_UPMC5
, "UPMC5",
3190 &spr_read_ureg
, SPR_NOACCESS
,
3191 &spr_read_ureg
, SPR_NOACCESS
,
3193 spr_register(env
, SPR_PMC6
, "PMC6",
3194 SPR_NOACCESS
, SPR_NOACCESS
,
3195 &spr_read_generic
, &spr_write_generic
,
3197 spr_register(env
, SPR_UPMC6
, "UPMC6",
3198 &spr_read_ureg
, SPR_NOACCESS
,
3199 &spr_read_ureg
, SPR_NOACCESS
,
3201 /* Memory management */
3203 gen_74xx_soft_tlb(env
);
3204 /* Allocate hardware IRQ controller */
3205 ppc6xx_irq_init(env
);
3209 /* PowerPC 7445 (aka G4) */
3211 #define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3212 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3214 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
3215 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
3216 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
3217 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
3218 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
3220 static void init_proc_7445 (CPUPPCState
*env
)
3222 gen_spr_ne_601(env
);
3226 /* 74xx specific SPR */
3229 /* XXX : not implemented */
3230 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
3231 SPR_NOACCESS
, SPR_NOACCESS
,
3232 &spr_read_generic
, &spr_write_generic
,
3235 /* XXX : not implemented */
3236 spr_register(env
, SPR_ICTRL
, "ICTRL",
3237 SPR_NOACCESS
, SPR_NOACCESS
,
3238 &spr_read_generic
, &spr_write_generic
,
3241 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
3242 SPR_NOACCESS
, SPR_NOACCESS
,
3243 &spr_read_generic
, &spr_write_generic
,
3246 /* XXX : not implemented */
3247 spr_register(env
, SPR_PMC5
, "PMC5",
3248 SPR_NOACCESS
, SPR_NOACCESS
,
3249 &spr_read_generic
, &spr_write_generic
,
3251 spr_register(env
, SPR_UPMC5
, "UPMC5",
3252 &spr_read_ureg
, SPR_NOACCESS
,
3253 &spr_read_ureg
, SPR_NOACCESS
,
3255 spr_register(env
, SPR_PMC6
, "PMC6",
3256 SPR_NOACCESS
, SPR_NOACCESS
,
3257 &spr_read_generic
, &spr_write_generic
,
3259 spr_register(env
, SPR_UPMC6
, "UPMC6",
3260 &spr_read_ureg
, SPR_NOACCESS
,
3261 &spr_read_ureg
, SPR_NOACCESS
,
3264 spr_register(env
, SPR_SPRG4
, "SPRG4",
3265 SPR_NOACCESS
, SPR_NOACCESS
,
3266 &spr_read_generic
, &spr_write_generic
,
3268 spr_register(env
, SPR_USPRG4
, "USPRG4",
3269 &spr_read_ureg
, SPR_NOACCESS
,
3270 &spr_read_ureg
, SPR_NOACCESS
,
3272 spr_register(env
, SPR_SPRG5
, "SPRG5",
3273 SPR_NOACCESS
, SPR_NOACCESS
,
3274 &spr_read_generic
, &spr_write_generic
,
3276 spr_register(env
, SPR_USPRG5
, "USPRG5",
3277 &spr_read_ureg
, SPR_NOACCESS
,
3278 &spr_read_ureg
, SPR_NOACCESS
,
3280 spr_register(env
, SPR_SPRG6
, "SPRG6",
3281 SPR_NOACCESS
, SPR_NOACCESS
,
3282 &spr_read_generic
, &spr_write_generic
,
3284 spr_register(env
, SPR_USPRG6
, "USPRG6",
3285 &spr_read_ureg
, SPR_NOACCESS
,
3286 &spr_read_ureg
, SPR_NOACCESS
,
3288 spr_register(env
, SPR_SPRG7
, "SPRG7",
3289 SPR_NOACCESS
, SPR_NOACCESS
,
3290 &spr_read_generic
, &spr_write_generic
,
3292 spr_register(env
, SPR_USPRG7
, "USPRG7",
3293 &spr_read_ureg
, SPR_NOACCESS
,
3294 &spr_read_ureg
, SPR_NOACCESS
,
3296 /* Memory management */
3299 gen_74xx_soft_tlb(env
);
3300 /* Allocate hardware IRQ controller */
3301 ppc6xx_irq_init(env
);
3305 /* PowerPC 7455 (aka G4) */
3307 #define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3308 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3310 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
3311 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
3312 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
3313 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
3314 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
3316 static void init_proc_7455 (CPUPPCState
*env
)
3318 gen_spr_ne_601(env
);
3322 /* 74xx specific SPR */
3324 /* Level 3 cache control */
3327 /* XXX : not implemented */
3328 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
3329 SPR_NOACCESS
, SPR_NOACCESS
,
3330 &spr_read_generic
, &spr_write_generic
,
3333 /* XXX : not implemented */
3334 spr_register(env
, SPR_ICTRL
, "ICTRL",
3335 SPR_NOACCESS
, SPR_NOACCESS
,
3336 &spr_read_generic
, &spr_write_generic
,
3339 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
3340 SPR_NOACCESS
, SPR_NOACCESS
,
3341 &spr_read_generic
, &spr_write_generic
,
3344 /* XXX : not implemented */
3345 spr_register(env
, SPR_PMC5
, "PMC5",
3346 SPR_NOACCESS
, SPR_NOACCESS
,
3347 &spr_read_generic
, &spr_write_generic
,
3349 spr_register(env
, SPR_UPMC5
, "UPMC5",
3350 &spr_read_ureg
, SPR_NOACCESS
,
3351 &spr_read_ureg
, SPR_NOACCESS
,
3353 spr_register(env
, SPR_PMC6
, "PMC6",
3354 SPR_NOACCESS
, SPR_NOACCESS
,
3355 &spr_read_generic
, &spr_write_generic
,
3357 spr_register(env
, SPR_UPMC6
, "UPMC6",
3358 &spr_read_ureg
, SPR_NOACCESS
,
3359 &spr_read_ureg
, SPR_NOACCESS
,
3362 spr_register(env
, SPR_SPRG4
, "SPRG4",
3363 SPR_NOACCESS
, SPR_NOACCESS
,
3364 &spr_read_generic
, &spr_write_generic
,
3366 spr_register(env
, SPR_USPRG4
, "USPRG4",
3367 &spr_read_ureg
, SPR_NOACCESS
,
3368 &spr_read_ureg
, SPR_NOACCESS
,
3370 spr_register(env
, SPR_SPRG5
, "SPRG5",
3371 SPR_NOACCESS
, SPR_NOACCESS
,
3372 &spr_read_generic
, &spr_write_generic
,
3374 spr_register(env
, SPR_USPRG5
, "USPRG5",
3375 &spr_read_ureg
, SPR_NOACCESS
,
3376 &spr_read_ureg
, SPR_NOACCESS
,
3378 spr_register(env
, SPR_SPRG6
, "SPRG6",
3379 SPR_NOACCESS
, SPR_NOACCESS
,
3380 &spr_read_generic
, &spr_write_generic
,
3382 spr_register(env
, SPR_USPRG6
, "USPRG6",
3383 &spr_read_ureg
, SPR_NOACCESS
,
3384 &spr_read_ureg
, SPR_NOACCESS
,
3386 spr_register(env
, SPR_SPRG7
, "SPRG7",
3387 SPR_NOACCESS
, SPR_NOACCESS
,
3388 &spr_read_generic
, &spr_write_generic
,
3390 spr_register(env
, SPR_USPRG7
, "USPRG7",
3391 &spr_read_ureg
, SPR_NOACCESS
,
3392 &spr_read_ureg
, SPR_NOACCESS
,
3394 /* Memory management */
3397 gen_74xx_soft_tlb(env
);
3398 /* Allocate hardware IRQ controller */
3399 ppc6xx_irq_init(env
);
3403 #if defined (TARGET_PPC64)
3405 #define POWERPC_INSNS_970 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
3406 PPC_64B | PPC_ALTIVEC | \
3407 PPC_64_BRIDGE | PPC_SLBI)
3408 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
3409 #define POWERPC_MMU_970 (POWERPC_MMU_64BRIDGE)
3410 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
3411 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
3412 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
3414 static void init_proc_970 (CPUPPCState
*env
)
3416 gen_spr_ne_601(env
);
3420 /* Hardware implementation registers */
3421 /* XXX : not implemented */
3422 spr_register(env
, SPR_HID0
, "HID0",
3423 SPR_NOACCESS
, SPR_NOACCESS
,
3424 &spr_read_generic
, &spr_write_generic
,
3426 /* XXX : not implemented */
3427 spr_register(env
, SPR_HID1
, "HID1",
3428 SPR_NOACCESS
, SPR_NOACCESS
,
3429 &spr_read_generic
, &spr_write_generic
,
3431 /* XXX : not implemented */
3432 spr_register(env
, SPR_750_HID2
, "HID2",
3433 SPR_NOACCESS
, SPR_NOACCESS
,
3434 &spr_read_generic
, &spr_write_generic
,
3436 /* Memory management */
3437 /* XXX: not correct */
3442 /* Allocate hardware IRQ controller */
3443 ppc970_irq_init(env
);
3446 /* PowerPC 970FX (aka G5) */
3447 #define POWERPC_INSNS_970FX (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
3448 PPC_64B | PPC_ALTIVEC | \
3449 PPC_64_BRIDGE | PPC_SLBI)
3450 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
3451 #define POWERPC_MMU_970FX (POWERPC_MMU_64BRIDGE)
3452 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
3453 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
3454 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
3456 static void init_proc_970FX (CPUPPCState
*env
)
3458 gen_spr_ne_601(env
);
3462 /* Hardware implementation registers */
3463 /* XXX : not implemented */
3464 spr_register(env
, SPR_HID0
, "HID0",
3465 SPR_NOACCESS
, SPR_NOACCESS
,
3466 &spr_read_generic
, &spr_write_generic
,
3468 /* XXX : not implemented */
3469 spr_register(env
, SPR_HID1
, "HID1",
3470 SPR_NOACCESS
, SPR_NOACCESS
,
3471 &spr_read_generic
, &spr_write_generic
,
3473 /* XXX : not implemented */
3474 spr_register(env
, SPR_750_HID2
, "HID2",
3475 SPR_NOACCESS
, SPR_NOACCESS
,
3476 &spr_read_generic
, &spr_write_generic
,
3478 /* Memory management */
3479 /* XXX: not correct */
3484 /* Allocate hardware IRQ controller */
3485 ppc970_irq_init(env
);
3488 /* PowerPC 970 GX */
3489 #define POWERPC_INSNS_970GX (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
3490 PPC_64B | PPC_ALTIVEC | \
3491 PPC_64_BRIDGE | PPC_SLBI)
3492 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
3493 #define POWERPC_MMU_970GX (POWERPC_MMU_64BRIDGE)
3494 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
3495 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
3496 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
3498 static void init_proc_970GX (CPUPPCState
*env
)
3500 gen_spr_ne_601(env
);
3504 /* Hardware implementation registers */
3505 /* XXX : not implemented */
3506 spr_register(env
, SPR_HID0
, "HID0",
3507 SPR_NOACCESS
, SPR_NOACCESS
,
3508 &spr_read_generic
, &spr_write_generic
,
3510 /* XXX : not implemented */
3511 spr_register(env
, SPR_HID1
, "HID1",
3512 SPR_NOACCESS
, SPR_NOACCESS
,
3513 &spr_read_generic
, &spr_write_generic
,
3515 /* XXX : not implemented */
3516 spr_register(env
, SPR_750_HID2
, "HID2",
3517 SPR_NOACCESS
, SPR_NOACCESS
,
3518 &spr_read_generic
, &spr_write_generic
,
3520 /* Memory management */
3521 /* XXX: not correct */
3526 /* Allocate hardware IRQ controller */
3527 ppc970_irq_init(env
);
3532 #define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
3534 #define POWERPC_MSRM_620 (0x800000000005FF73ULL)
3535 #define POWERPC_MMU_620 (POWERPC_MMU_64B)
3536 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
3537 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_970)
3538 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
3540 static void init_proc_620 (CPUPPCState
*env
)
3542 gen_spr_ne_601(env
);
3546 /* Hardware implementation registers */
3547 /* XXX : not implemented */
3548 spr_register(env
, SPR_HID0
, "HID0",
3549 SPR_NOACCESS
, SPR_NOACCESS
,
3550 &spr_read_generic
, &spr_write_generic
,
3552 /* Memory management */
3555 /* XXX: TODO: initialize internal interrupt controller */
3558 #endif /* defined (TARGET_PPC64) */
3560 /* Default 32 bits PowerPC target will be 604 */
3561 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
3562 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
3563 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
3564 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
3565 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
3566 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
3567 #define init_proc_PPC32 init_proc_604
3568 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
3570 /* Default 64 bits PowerPC target will be 970 FX */
3571 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
3572 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
3573 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
3574 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
3575 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
3576 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
3577 #define init_proc_PPC64 init_proc_970FX
3578 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
3580 /* Default PowerPC target will be PowerPC 32 */
3581 #if defined (TARGET_PPC64) && 0 // XXX: TODO
3582 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
3583 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
3584 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
3585 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
3586 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
3587 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
3588 #define init_proc_DEFAULT init_proc_PPC64
3589 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
3591 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
3592 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
3593 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
3594 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
3595 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
3596 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
3597 #define init_proc_DEFAULT init_proc_PPC32
3598 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
3601 /*****************************************************************************/
3602 /* PVR definitions for most known PowerPC */
3604 /* PowerPC 401 family */
3605 /* Generic PowerPC 401 */
3606 #define CPU_POWERPC_401 CPU_POWERPC_401G2
3607 /* PowerPC 401 cores */
3608 CPU_POWERPC_401A1
= 0x00210000,
3609 CPU_POWERPC_401B2
= 0x00220000,
3611 CPU_POWERPC_401B3
= xxx
,
3613 CPU_POWERPC_401C2
= 0x00230000,
3614 CPU_POWERPC_401D2
= 0x00240000,
3615 CPU_POWERPC_401E2
= 0x00250000,
3616 CPU_POWERPC_401F2
= 0x00260000,
3617 CPU_POWERPC_401G2
= 0x00270000,
3618 /* PowerPC 401 microcontrolers */
3620 CPU_POWERPC_401GF
= xxx
,
3622 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
3623 /* IBM Processor for Network Resources */
3624 CPU_POWERPC_COBRA
= 0x10100000, /* XXX: 405 ? */
3626 CPU_POWERPC_XIPCHIP
= xxx
,
3628 /* PowerPC 403 family */
3629 /* Generic PowerPC 403 */
3630 #define CPU_POWERPC_403 CPU_POWERPC_403GC
3631 /* PowerPC 403 microcontrollers */
3632 CPU_POWERPC_403GA
= 0x00200011,
3633 CPU_POWERPC_403GB
= 0x00200100,
3634 CPU_POWERPC_403GC
= 0x00200200,
3635 CPU_POWERPC_403GCX
= 0x00201400,
3637 CPU_POWERPC_403GP
= xxx
,
3639 /* PowerPC 405 family */
3640 /* Generic PowerPC 405 */
3641 #define CPU_POWERPC_405 CPU_POWERPC_405D4
3642 /* PowerPC 405 cores */
3644 CPU_POWERPC_405A3
= xxx
,
3647 CPU_POWERPC_405A4
= xxx
,
3650 CPU_POWERPC_405B3
= xxx
,
3653 CPU_POWERPC_405B4
= xxx
,
3656 CPU_POWERPC_405C3
= xxx
,
3659 CPU_POWERPC_405C4
= xxx
,
3661 CPU_POWERPC_405D2
= 0x20010000,
3663 CPU_POWERPC_405D3
= xxx
,
3665 CPU_POWERPC_405D4
= 0x41810000,
3667 CPU_POWERPC_405D5
= xxx
,
3670 CPU_POWERPC_405E4
= xxx
,
3673 CPU_POWERPC_405F4
= xxx
,
3676 CPU_POWERPC_405F5
= xxx
,
3679 CPU_POWERPC_405F6
= xxx
,
3681 /* PowerPC 405 microcontrolers */
3682 /* XXX: missing 0x200108a0 */
3683 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
3684 CPU_POWERPC_405CRa
= 0x40110041,
3685 CPU_POWERPC_405CRb
= 0x401100C5,
3686 CPU_POWERPC_405CRc
= 0x40110145,
3687 CPU_POWERPC_405EP
= 0x51210950,
3689 CPU_POWERPC_405EXr
= xxx
,
3691 CPU_POWERPC_405EZ
= 0x41511460, /* 0x51210950 ? */
3693 CPU_POWERPC_405FX
= xxx
,
3695 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
3696 CPU_POWERPC_405GPa
= 0x40110000,
3697 CPU_POWERPC_405GPb
= 0x40110040,
3698 CPU_POWERPC_405GPc
= 0x40110082,
3699 CPU_POWERPC_405GPd
= 0x401100C4,
3700 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
3701 CPU_POWERPC_405GPR
= 0x50910951,
3703 CPU_POWERPC_405H
= xxx
,
3706 CPU_POWERPC_405L
= xxx
,
3708 CPU_POWERPC_405LP
= 0x41F10000,
3710 CPU_POWERPC_405PM
= xxx
,
3713 CPU_POWERPC_405PS
= xxx
,
3716 CPU_POWERPC_405S
= xxx
,
3718 /* IBM network processors */
3719 CPU_POWERPC_NPE405H
= 0x414100C0,
3720 CPU_POWERPC_NPE405H2
= 0x41410140,
3721 CPU_POWERPC_NPE405L
= 0x416100C0,
3722 CPU_POWERPC_NPE4GS3
= 0x40B10000,
3724 CPU_POWERPC_NPCxx1
= xxx
,
3727 CPU_POWERPC_NPR161
= xxx
,
3730 CPU_POWERPC_LC77700
= xxx
,
3732 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
3734 CPU_POWERPC_STB01000
= xxx
,
3737 CPU_POWERPC_STB01010
= xxx
,
3740 CPU_POWERPC_STB0210
= xxx
, /* 401B3 */
3742 CPU_POWERPC_STB03
= 0x40310000, /* 0x40130000 ? */
3744 CPU_POWERPC_STB043
= xxx
,
3747 CPU_POWERPC_STB045
= xxx
,
3749 CPU_POWERPC_STB04
= 0x41810000,
3750 CPU_POWERPC_STB25
= 0x51510950,
3752 CPU_POWERPC_STB130
= xxx
,
3755 CPU_POWERPC_X2VP4
= 0x20010820,
3756 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
3757 CPU_POWERPC_X2VP20
= 0x20010860,
3758 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
3760 CPU_POWERPC_ZL10310
= xxx
,
3763 CPU_POWERPC_ZL10311
= xxx
,
3766 CPU_POWERPC_ZL10320
= xxx
,
3769 CPU_POWERPC_ZL10321
= xxx
,
3771 /* PowerPC 440 family */
3772 /* Generic PowerPC 440 */
3773 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
3774 /* PowerPC 440 cores */
3776 CPU_POWERPC_440A4
= xxx
,
3779 CPU_POWERPC_440A5
= xxx
,
3782 CPU_POWERPC_440B4
= xxx
,
3785 CPU_POWERPC_440F5
= xxx
,
3788 CPU_POWERPC_440G5
= xxx
,
3791 CPU_POWERPC_440H4
= xxx
,
3794 CPU_POWERPC_440H6
= xxx
,
3796 /* PowerPC 440 microcontrolers */
3797 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
3798 CPU_POWERPC_440EPa
= 0x42221850,
3799 CPU_POWERPC_440EPb
= 0x422218D3,
3800 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
3801 CPU_POWERPC_440GPb
= 0x40120440,
3802 CPU_POWERPC_440GPc
= 0x40120481,
3803 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
3804 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
3805 CPU_POWERPC_440GRX
= 0x200008D0,
3806 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
3807 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
3808 CPU_POWERPC_440GXa
= 0x51B21850,
3809 CPU_POWERPC_440GXb
= 0x51B21851,
3810 CPU_POWERPC_440GXc
= 0x51B21892,
3811 CPU_POWERPC_440GXf
= 0x51B21894,
3813 CPU_POWERPC_440S
= xxx
,
3815 CPU_POWERPC_440SP
= 0x53221850,
3816 CPU_POWERPC_440SP2
= 0x53221891,
3817 CPU_POWERPC_440SPE
= 0x53421890,
3818 /* PowerPC 460 family */
3820 /* Generic PowerPC 464 */
3821 #define CPU_POWERPC_464 CPU_POWERPC_464H90
3823 /* PowerPC 464 microcontrolers */
3825 CPU_POWERPC_464H90
= xxx
,
3828 CPU_POWERPC_464H90FP
= xxx
,
3830 /* Freescale embedded PowerPC cores */
3832 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
3834 CPU_POWERPC_e200z0
= xxx
,
3837 CPU_POWERPC_e200z3
= xxx
,
3839 CPU_POWERPC_e200z5
= 0x81000000,
3840 CPU_POWERPC_e200z6
= 0x81120000,
3842 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
3843 CPU_POWERPC_e300c1
= 0x00830000,
3844 CPU_POWERPC_e300c2
= 0x00840000,
3845 CPU_POWERPC_e300c3
= 0x00850000,
3847 #define CPU_POWERPC_e500 CPU_POWERPC_e500_v22
3848 CPU_POWERPC_e500_v11
= 0x80200010,
3849 CPU_POWERPC_e500_v12
= 0x80200020,
3850 CPU_POWERPC_e500_v21
= 0x80210010,
3851 CPU_POWERPC_e500_v22
= 0x80210020,
3853 CPU_POWERPC_e500mc
= xxx
,
3856 CPU_POWERPC_e600
= 0x80040010,
3857 /* PowerPC MPC 5xx cores */
3858 CPU_POWERPC_5xx
= 0x00020020,
3859 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
3860 CPU_POWERPC_8xx
= 0x00500000,
3861 /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
3862 CPU_POWERPC_82xx_HIP3
= 0x00810101,
3863 CPU_POWERPC_82xx_HIP4
= 0x80811014,
3864 CPU_POWERPC_827x
= 0x80822013,
3865 /* PowerPC 6xx cores */
3866 CPU_POWERPC_601
= 0x00010001,
3867 CPU_POWERPC_601a
= 0x00010002,
3868 CPU_POWERPC_602
= 0x00050100,
3869 CPU_POWERPC_603
= 0x00030100,
3870 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
3871 CPU_POWERPC_603E_v11
= 0x00060101,
3872 CPU_POWERPC_603E_v12
= 0x00060102,
3873 CPU_POWERPC_603E_v13
= 0x00060103,
3874 CPU_POWERPC_603E_v14
= 0x00060104,
3875 CPU_POWERPC_603E_v22
= 0x00060202,
3876 CPU_POWERPC_603E_v3
= 0x00060300,
3877 CPU_POWERPC_603E_v4
= 0x00060400,
3878 CPU_POWERPC_603E_v41
= 0x00060401,
3879 CPU_POWERPC_603E7t
= 0x00071201,
3880 CPU_POWERPC_603E7v
= 0x00070100,
3881 CPU_POWERPC_603E7v1
= 0x00070101,
3882 CPU_POWERPC_603E7v2
= 0x00070201,
3883 CPU_POWERPC_603E7
= 0x00070200,
3884 CPU_POWERPC_603P
= 0x00070000,
3885 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
3886 CPU_POWERPC_G2
= 0x00810011,
3887 #if 0 // Linux pretends the MSB is zero...
3888 CPU_POWERPC_G2H4
= 0x80811010,
3889 CPU_POWERPC_G2gp
= 0x80821010,
3890 CPU_POWERPC_G2ls
= 0x90810010,
3891 CPU_POWERPC_G2LE
= 0x80820010,
3892 CPU_POWERPC_G2LEgp
= 0x80822010,
3893 CPU_POWERPC_G2LEls
= 0xA0822010,
3895 CPU_POWERPC_G2H4
= 0x00811010,
3896 CPU_POWERPC_G2gp
= 0x00821010,
3897 CPU_POWERPC_G2ls
= 0x10810010,
3898 CPU_POWERPC_G2LE
= 0x00820010,
3899 CPU_POWERPC_G2LEgp
= 0x00822010,
3900 CPU_POWERPC_G2LEls
= 0x20822010,
3902 CPU_POWERPC_604
= 0x00040103,
3903 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
3904 CPU_POWERPC_604E_v10
= 0x00090100, /* Also 2110 & 2120 */
3905 CPU_POWERPC_604E_v22
= 0x00090202,
3906 CPU_POWERPC_604E_v24
= 0x00090204,
3907 CPU_POWERPC_604R
= 0x000a0101, /* Also 0x00093102 */
3909 CPU_POWERPC_604EV
= xxx
,
3911 /* PowerPC 740/750 cores (aka G3) */
3912 /* XXX: missing 0x00084202 */
3913 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
3914 CPU_POWERPC_7x0_v20
= 0x00080200,
3915 CPU_POWERPC_7x0_v21
= 0x00080201,
3916 CPU_POWERPC_7x0_v22
= 0x00080202,
3917 CPU_POWERPC_7x0_v30
= 0x00080300,
3918 CPU_POWERPC_7x0_v31
= 0x00080301,
3919 CPU_POWERPC_740E
= 0x00080100,
3920 CPU_POWERPC_7x0P
= 0x10080000,
3921 /* XXX: missing 0x00087010 (CL ?) */
3922 CPU_POWERPC_750CL
= 0x00087200,
3923 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
3924 CPU_POWERPC_750CX_v21
= 0x00082201,
3925 CPU_POWERPC_750CX_v22
= 0x00082202,
3926 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
3927 CPU_POWERPC_750CXE_v21
= 0x00082211,
3928 CPU_POWERPC_750CXE_v22
= 0x00082212,
3929 CPU_POWERPC_750CXE_v23
= 0x00082213,
3930 CPU_POWERPC_750CXE_v24
= 0x00082214,
3931 CPU_POWERPC_750CXE_v24b
= 0x00083214,
3932 CPU_POWERPC_750CXE_v31
= 0x00083211,
3933 CPU_POWERPC_750CXE_v31b
= 0x00083311,
3934 CPU_POWERPC_750CXR
= 0x00083410,
3935 CPU_POWERPC_750E
= 0x00080200,
3936 CPU_POWERPC_750FL
= 0x700A0203,
3937 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
3938 CPU_POWERPC_750FX_v10
= 0x70000100,
3939 CPU_POWERPC_750FX_v20
= 0x70000200,
3940 CPU_POWERPC_750FX_v21
= 0x70000201,
3941 CPU_POWERPC_750FX_v22
= 0x70000202,
3942 CPU_POWERPC_750FX_v23
= 0x70000203,
3943 CPU_POWERPC_750GL
= 0x70020102,
3944 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
3945 CPU_POWERPC_750GX_v10
= 0x70020100,
3946 CPU_POWERPC_750GX_v11
= 0x70020101,
3947 CPU_POWERPC_750GX_v12
= 0x70020102,
3948 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
3949 CPU_POWERPC_750L_v22
= 0x00088202,
3950 CPU_POWERPC_750L_v30
= 0x00088300,
3951 CPU_POWERPC_750L_v32
= 0x00088302,
3952 /* PowerPC 745/755 cores */
3953 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
3954 CPU_POWERPC_7x5_v10
= 0x00083100,
3955 CPU_POWERPC_7x5_v11
= 0x00083101,
3956 CPU_POWERPC_7x5_v20
= 0x00083200,
3957 CPU_POWERPC_7x5_v21
= 0x00083201,
3958 CPU_POWERPC_7x5_v22
= 0x00083202, /* aka D */
3959 CPU_POWERPC_7x5_v23
= 0x00083203, /* aka E */
3960 CPU_POWERPC_7x5_v24
= 0x00083204,
3961 CPU_POWERPC_7x5_v25
= 0x00083205,
3962 CPU_POWERPC_7x5_v26
= 0x00083206,
3963 CPU_POWERPC_7x5_v27
= 0x00083207,
3964 CPU_POWERPC_7x5_v28
= 0x00083208,
3966 CPU_POWERPC_7x5P
= xxx
,
3968 /* PowerPC 74xx cores (aka G4) */
3969 /* XXX: missing 0x000C1101 */
3970 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
3971 CPU_POWERPC_7400_v10
= 0x000C0100,
3972 CPU_POWERPC_7400_v11
= 0x000C0101,
3973 CPU_POWERPC_7400_v20
= 0x000C0200,
3974 CPU_POWERPC_7400_v22
= 0x000C0202,
3975 CPU_POWERPC_7400_v26
= 0x000C0206,
3976 CPU_POWERPC_7400_v27
= 0x000C0207,
3977 CPU_POWERPC_7400_v28
= 0x000C0208,
3978 CPU_POWERPC_7400_v29
= 0x000C0209,
3979 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
3980 CPU_POWERPC_7410_v10
= 0x800C1100,
3981 CPU_POWERPC_7410_v11
= 0x800C1101,
3982 CPU_POWERPC_7410_v12
= 0x800C1102, /* aka C */
3983 CPU_POWERPC_7410_v13
= 0x800C1103, /* aka D */
3984 CPU_POWERPC_7410_v14
= 0x800C1104, /* aka E */
3985 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
3986 CPU_POWERPC_7448_v10
= 0x80040100,
3987 CPU_POWERPC_7448_v11
= 0x80040101,
3988 CPU_POWERPC_7448_v20
= 0x80040200,
3989 CPU_POWERPC_7448_v21
= 0x80040201,
3990 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
3991 CPU_POWERPC_7450_v10
= 0x80000100,
3992 CPU_POWERPC_7450_v11
= 0x80000101,
3993 CPU_POWERPC_7450_v12
= 0x80000102,
3994 CPU_POWERPC_7450_v20
= 0x80000200, /* aka D: 2.04 */
3995 CPU_POWERPC_7450_v21
= 0x80000201, /* aka E */
3996 CPU_POWERPC_74x1
= 0x80000203,
3997 CPU_POWERPC_74x1G
= 0x80000210, /* aka G: 2.3 */
3998 /* XXX: missing 0x80010200 */
3999 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
4000 CPU_POWERPC_74x5_v10
= 0x80010100,
4001 CPU_POWERPC_74x5_v21
= 0x80010201, /* aka C: 2.1 */
4002 CPU_POWERPC_74x5_v32
= 0x80010302,
4003 CPU_POWERPC_74x5_v33
= 0x80010303, /* aka F: 3.3 */
4004 CPU_POWERPC_74x5_v34
= 0x80010304, /* aka G: 3.4 */
4005 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
4006 CPU_POWERPC_74x7_v10
= 0x80020100, /* aka A: 1.0 */
4007 CPU_POWERPC_74x7_v11
= 0x80030101, /* aka B: 1.1 */
4008 CPU_POWERPC_74x7_v12
= 0x80020102, /* aka C: 1.2 */
4009 /* 64 bits PowerPC */
4010 CPU_POWERPC_620
= 0x00140000,
4011 CPU_POWERPC_630
= 0x00400000,
4012 CPU_POWERPC_631
= 0x00410104,
4013 CPU_POWERPC_POWER4
= 0x00350000,
4014 CPU_POWERPC_POWER4P
= 0x00380000,
4015 CPU_POWERPC_POWER5
= 0x003A0203,
4016 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
4017 CPU_POWERPC_POWER5P
= 0x003B0000,
4018 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
4019 CPU_POWERPC_POWER6
= 0x003E0000,
4020 CPU_POWERPC_POWER6_5
= 0x0F000001, /* POWER6 running POWER5 mode */
4021 CPU_POWERPC_POWER6A
= 0x0F000002,
4022 CPU_POWERPC_970
= 0x00390202,
4023 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
4024 CPU_POWERPC_970FX_v10
= 0x00391100,
4025 CPU_POWERPC_970FX_v20
= 0x003C0200,
4026 CPU_POWERPC_970FX_v21
= 0x003C0201,
4027 CPU_POWERPC_970FX_v30
= 0x003C0300,
4028 CPU_POWERPC_970FX_v31
= 0x003C0301,
4029 CPU_POWERPC_970GX
= 0x00450000,
4030 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
4031 CPU_POWERPC_970MP_v10
= 0x00440100,
4032 CPU_POWERPC_970MP_v11
= 0x00440101,
4033 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
4034 CPU_POWERPC_CELL_v10
= 0x00700100,
4035 CPU_POWERPC_CELL_v20
= 0x00700400,
4036 CPU_POWERPC_CELL_v30
= 0x00700500,
4037 CPU_POWERPC_CELL_v31
= 0x00700501,
4038 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
4039 CPU_POWERPC_RS64
= 0x00330000,
4040 CPU_POWERPC_RS64II
= 0x00340000,
4041 CPU_POWERPC_RS64III
= 0x00360000,
4042 CPU_POWERPC_RS64IV
= 0x00370000,
4043 /* Original POWER */
4044 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
4045 * POWER2 (RIOS2) & RSC2 (P2SC) here
4048 CPU_POWER
= xxx
, /* 0x20000 ? 0x30000 for RSC ? */
4051 CPU_POWER2
= xxx
, /* 0x40000 ? */
4054 CPU_POWERPC_PA6T
= 0x00900000,
4057 /* System version register (used on MPC 8xxx) */
4059 PPC_SVR_8540
= 0x80300000,
4060 PPC_SVR_8541E
= 0x807A0010,
4061 PPC_SVR_8543v10
= 0x80320010,
4062 PPC_SVR_8543v11
= 0x80320011,
4063 PPC_SVR_8543v20
= 0x80320020,
4064 PPC_SVR_8543Ev10
= 0x803A0010,
4065 PPC_SVR_8543Ev11
= 0x803A0011,
4066 PPC_SVR_8543Ev20
= 0x803A0020,
4067 PPC_SVR_8545
= 0x80310220,
4068 PPC_SVR_8545E
= 0x80390220,
4069 PPC_SVR_8547E
= 0x80390120,
4070 PPC_SCR_8548v10
= 0x80310010,
4071 PPC_SCR_8548v11
= 0x80310011,
4072 PPC_SCR_8548v20
= 0x80310020,
4073 PPC_SVR_8548Ev10
= 0x80390010,
4074 PPC_SVR_8548Ev11
= 0x80390011,
4075 PPC_SVR_8548Ev20
= 0x80390020,
4076 PPC_SVR_8555E
= 0x80790010,
4077 PPC_SVR_8560v10
= 0x80700010,
4078 PPC_SVR_8560v20
= 0x80700020,
4081 /*****************************************************************************/
4082 /* PowerPC CPU definitions */
4083 #define POWERPC_DEF(_name, _pvr, _pvr_mask, _type) \
4087 .pvr_mask = _pvr_mask, \
4088 .insns_flags = glue(POWERPC_INSNS_,_type), \
4089 .msr_mask = glue(POWERPC_MSRM_,_type), \
4090 .mmu_model = glue(POWERPC_MMU_,_type), \
4091 .excp_model = glue(POWERPC_EXCP_,_type), \
4092 .bus_model = glue(POWERPC_INPUT_,_type), \
4093 .bfd_mach = glue(POWERPC_BFDM_,_type), \
4094 .init_proc = &glue(init_proc_,_type), \
4097 static ppc_def_t ppc_defs
[] = {
4098 /* Embedded PowerPC */
4099 /* PowerPC 401 family */
4100 /* Generic PowerPC 401 */
4101 POWERPC_DEF("401", CPU_POWERPC_401
, 0xFFFF0000, 401),
4102 /* PowerPC 401 cores */
4104 POWERPC_DEF("401A1", CPU_POWERPC_401A1
, 0xFFFFFFFF, 401),
4106 POWERPC_DEF("401B2", CPU_POWERPC_401B2
, 0xFFFFFFFF, 401x2
),
4109 POWERPC_DEF("401B3", CPU_POWERPC_401B3
, 0xFFFFFFFF, 401x3
),
4112 POWERPC_DEF("401C2", CPU_POWERPC_401C2
, 0xFFFFFFFF, 401x2
),
4114 POWERPC_DEF("401D2", CPU_POWERPC_401D2
, 0xFFFFFFFF, 401x2
),
4116 POWERPC_DEF("401E2", CPU_POWERPC_401E2
, 0xFFFFFFFF, 401x2
),
4118 POWERPC_DEF("401F2", CPU_POWERPC_401F2
, 0xFFFFFFFF, 401x2
),
4120 /* XXX: to be checked */
4121 POWERPC_DEF("401G2", CPU_POWERPC_401G2
, 0xFFFFFFFF, 401x2
),
4122 /* PowerPC 401 microcontrolers */
4125 POWERPC_DEF("401GF", CPU_POWERPC_401GF
, 0xFFFFFFFF, 401),
4127 /* IOP480 (401 microcontroler) */
4128 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480
, 0xFFFFFFFF, IOP480
),
4129 /* IBM Processor for Network Resources */
4130 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA
, 0xFFFFFFFF, 401),
4132 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP
, 0xFFFFFFFF, 401),
4134 /* PowerPC 403 family */
4135 /* Generic PowerPC 403 */
4136 POWERPC_DEF("403", CPU_POWERPC_403
, 0xFFFF0000, 403),
4137 /* PowerPC 403 microcontrolers */
4138 /* PowerPC 403 GA */
4139 POWERPC_DEF("403GA", CPU_POWERPC_403GA
, 0xFFFFFFFF, 403),
4140 /* PowerPC 403 GB */
4141 POWERPC_DEF("403GB", CPU_POWERPC_403GB
, 0xFFFFFFFF, 403),
4142 /* PowerPC 403 GC */
4143 POWERPC_DEF("403GC", CPU_POWERPC_403GC
, 0xFFFFFFFF, 403),
4144 /* PowerPC 403 GCX */
4145 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX
, 0xFFFFFFFF, 403GCX
),
4147 /* PowerPC 403 GP */
4148 POWERPC_DEF("403GP", CPU_POWERPC_403GP
, 0xFFFFFFFF, 403),
4150 /* PowerPC 405 family */
4151 /* Generic PowerPC 405 */
4152 POWERPC_DEF("405", CPU_POWERPC_405
, 0xFFFF0000, 405),
4153 /* PowerPC 405 cores */
4155 /* PowerPC 405 A3 */
4156 POWERPC_DEF("405A3", CPU_POWERPC_405A3
, 0xFFFFFFFF, 405),
4159 /* PowerPC 405 A4 */
4160 POWERPC_DEF("405A4", CPU_POWERPC_405A4
, 0xFFFFFFFF, 405),
4163 /* PowerPC 405 B3 */
4164 POWERPC_DEF("405B3", CPU_POWERPC_405B3
, 0xFFFFFFFF, 405),
4167 /* PowerPC 405 B4 */
4168 POWERPC_DEF("405B4", CPU_POWERPC_405B4
, 0xFFFFFFFF, 405),
4171 /* PowerPC 405 C3 */
4172 POWERPC_DEF("405C3", CPU_POWERPC_405C3
, 0xFFFFFFFF, 405),
4175 /* PowerPC 405 C4 */
4176 POWERPC_DEF("405C4", CPU_POWERPC_405C4
, 0xFFFFFFFF, 405),
4178 /* PowerPC 405 D2 */
4179 POWERPC_DEF("405D2", CPU_POWERPC_405D2
, 0xFFFFFFFF, 405),
4181 /* PowerPC 405 D3 */
4182 POWERPC_DEF("405D3", CPU_POWERPC_405D3
, 0xFFFFFFFF, 405),
4184 /* PowerPC 405 D4 */
4185 POWERPC_DEF("405D4", CPU_POWERPC_405D4
, 0xFFFFFFFF, 405),
4187 /* PowerPC 405 D5 */
4188 POWERPC_DEF("405D5", CPU_POWERPC_405D5
, 0xFFFFFFFF, 405),
4191 /* PowerPC 405 E4 */
4192 POWERPC_DEF("405E4", CPU_POWERPC_405E4
, 0xFFFFFFFF, 405),
4195 /* PowerPC 405 F4 */
4196 POWERPC_DEF("405F4", CPU_POWERPC_405F4
, 0xFFFFFFFF, 405),
4199 /* PowerPC 405 F5 */
4200 POWERPC_DEF("405F5", CPU_POWERPC_405F5
, 0xFFFFFFFF, 405),
4203 /* PowerPC 405 F6 */
4204 POWERPC_DEF("405F6", CPU_POWERPC_405F6
, 0xFFFFFFFF, 405),
4206 /* PowerPC 405 microcontrolers */
4207 /* PowerPC 405 CR */
4208 POWERPC_DEF("405CR", CPU_POWERPC_405CR
, 0xFFFFFFFF, 405),
4209 /* PowerPC 405 CRa */
4210 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa
, 0xFFFFFFFF, 405),
4211 /* PowerPC 405 CRb */
4212 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb
, 0xFFFFFFFF, 405),
4213 /* PowerPC 405 CRc */
4214 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc
, 0xFFFFFFFF, 405),
4215 /* PowerPC 405 EP */
4216 POWERPC_DEF("405EP", CPU_POWERPC_405EP
, 0xFFFFFFFF, 405),
4218 /* PowerPC 405 EXr */
4219 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr
, 0xFFFFFFFF, 405),
4221 /* PowerPC 405 EZ */
4222 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ
, 0xFFFFFFFF, 405),
4224 /* PowerPC 405 FX */
4225 POWERPC_DEF("405FX", CPU_POWERPC_405FX
, 0xFFFFFFFF, 405),
4227 /* PowerPC 405 GP */
4228 POWERPC_DEF("405GP", CPU_POWERPC_405GP
, 0xFFFFFFFF, 405),
4229 /* PowerPC 405 GPa */
4230 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa
, 0xFFFFFFFF, 405),
4231 /* PowerPC 405 GPb */
4232 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb
, 0xFFFFFFFF, 405),
4233 /* PowerPC 405 GPc */
4234 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc
, 0xFFFFFFFF, 405),
4235 /* PowerPC 405 GPd */
4236 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd
, 0xFFFFFFFF, 405),
4237 /* PowerPC 405 GPe */
4238 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe
, 0xFFFFFFFF, 405),
4239 /* PowerPC 405 GPR */
4240 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR
, 0xFFFFFFFF, 405),
4243 POWERPC_DEF("405H", CPU_POWERPC_405H
, 0xFFFFFFFF, 405),
4247 POWERPC_DEF("405L", CPU_POWERPC_405L
, 0xFFFFFFFF, 405),
4249 /* PowerPC 405 LP */
4250 POWERPC_DEF("405LP", CPU_POWERPC_405LP
, 0xFFFFFFFF, 405),
4252 /* PowerPC 405 PM */
4253 POWERPC_DEF("405PM", CPU_POWERPC_405PM
, 0xFFFFFFFF, 405),
4256 /* PowerPC 405 PS */
4257 POWERPC_DEF("405PS", CPU_POWERPC_405PS
, 0xFFFFFFFF, 405),
4261 POWERPC_DEF("405S", CPU_POWERPC_405S
, 0xFFFFFFFF, 405),
4264 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H
, 0xFFFFFFFF, 405),
4266 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2
, 0xFFFFFFFF, 405),
4268 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L
, 0xFFFFFFFF, 405),
4270 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3
, 0xFFFFFFFF, 405),
4272 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1
, 0xFFFFFFFF, 405),
4275 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161
, 0xFFFFFFFF, 405),
4278 /* PowerPC LC77700 (Sanyo) */
4279 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700
, 0xFFFFFFFF, 405),
4281 /* PowerPC 401/403/405 based set-top-box microcontrolers */
4284 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000
, 0xFFFFFFFF, 401x2
),
4288 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010
, 0xFFFFFFFF, 401x2
),
4292 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210
, 0xFFFFFFFF, 401x3
),
4295 POWERPC_DEF("STB03", CPU_POWERPC_STB03
, 0xFFFFFFFF, 405),
4298 POWERPC_DEF("STB043", CPU_POWERPC_STB043
, 0xFFFFFFFF, 405),
4302 POWERPC_DEF("STB045", CPU_POWERPC_STB045
, 0xFFFFFFFF, 405),
4305 POWERPC_DEF("STB04", CPU_POWERPC_STB04
, 0xFFFF0000, 405),
4307 POWERPC_DEF("STB25", CPU_POWERPC_STB25
, 0xFFFFFFFF, 405),
4310 POWERPC_DEF("STB130", CPU_POWERPC_STB130
, 0xFFFFFFFF, 405),
4312 /* Xilinx PowerPC 405 cores */
4313 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4
, 0xFFFFFFFF, 405),
4314 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7
, 0xFFFFFFFF, 405),
4315 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20
, 0xFFFFFFFF, 405),
4316 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50
, 0xFFFFFFFF, 405),
4318 /* Zarlink ZL10310 */
4319 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310
, 0xFFFFFFFF, 405),
4322 /* Zarlink ZL10311 */
4323 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311
, 0xFFFFFFFF, 405),
4326 /* Zarlink ZL10320 */
4327 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320
, 0xFFFFFFFF, 405),
4330 /* Zarlink ZL10321 */
4331 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321
, 0xFFFFFFFF, 405),
4333 /* PowerPC 440 family */
4334 /* Generic PowerPC 440 */
4335 POWERPC_DEF("440", CPU_POWERPC_440
, 0xFFFFFFFF, 440GP
),
4336 /* PowerPC 440 cores */
4338 /* PowerPC 440 A4 */
4339 POWERPC_DEF("440A4", CPU_POWERPC_440A4
, 0xFFFFFFFF, 440x4
),
4342 /* PowerPC 440 A5 */
4343 POWERPC_DEF("440A5", CPU_POWERPC_440A5
, 0xFFFFFFFF, 440x5
),
4346 /* PowerPC 440 B4 */
4347 POWERPC_DEF("440B4", CPU_POWERPC_440B4
, 0xFFFFFFFF, 440x4
),
4350 /* PowerPC 440 G4 */
4351 POWERPC_DEF("440G4", CPU_POWERPC_440G4
, 0xFFFFFFFF, 440x4
),
4354 /* PowerPC 440 F5 */
4355 POWERPC_DEF("440F5", CPU_POWERPC_440F5
, 0xFFFFFFFF, 440x5
),
4358 /* PowerPC 440 G5 */
4359 POWERPC_DEF("440G5", CPU_POWERPC_440G5
, 0xFFFFFFFF, 440x5
),
4363 POWERPC_DEF("440H4", CPU_POWERPC_440H4
, 0xFFFFFFFF, 440x4
),
4367 POWERPC_DEF("440H6", CPU_POWERPC_440H6
, 0xFFFFFFFF, 440Gx5
),
4369 /* PowerPC 440 microcontrolers */
4370 /* PowerPC 440 EP */
4371 POWERPC_DEF("440EP", CPU_POWERPC_440EP
, 0xFFFFFFFF, 440EP
),
4372 /* PowerPC 440 EPa */
4373 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa
, 0xFFFFFFFF, 440EP
),
4374 /* PowerPC 440 EPb */
4375 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb
, 0xFFFFFFFF, 440EP
),
4376 /* PowerPC 440 EPX */
4377 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX
, 0xFFFFFFFF, 440EP
),
4378 /* PowerPC 440 GP */
4379 POWERPC_DEF("440GP", CPU_POWERPC_440GP
, 0xFFFFFFFF, 440GP
),
4380 /* PowerPC 440 GPb */
4381 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb
, 0xFFFFFFFF, 440GP
),
4382 /* PowerPC 440 GPc */
4383 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc
, 0xFFFFFFFF, 440GP
),
4384 /* PowerPC 440 GR */
4385 POWERPC_DEF("440GR", CPU_POWERPC_440GR
, 0xFFFFFFFF, 440x5
),
4386 /* PowerPC 440 GRa */
4387 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa
, 0xFFFFFFFF, 440x5
),
4388 /* PowerPC 440 GRX */
4389 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX
, 0xFFFFFFFF, 440x5
),
4390 /* PowerPC 440 GX */
4391 POWERPC_DEF("440GX", CPU_POWERPC_440GX
, 0xFFFFFFFF, 440EP
),
4392 /* PowerPC 440 GXa */
4393 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa
, 0xFFFFFFFF, 440EP
),
4394 /* PowerPC 440 GXb */
4395 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb
, 0xFFFFFFFF, 440EP
),
4396 /* PowerPC 440 GXc */
4397 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc
, 0xFFFFFFFF, 440EP
),
4398 /* PowerPC 440 GXf */
4399 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf
, 0xFFFFFFFF, 440EP
),
4402 POWERPC_DEF("440S", CPU_POWERPC_440S
, 0xFFFFFFFF, 440),
4404 /* PowerPC 440 SP */
4405 POWERPC_DEF("440SP", CPU_POWERPC_440SP
, 0xFFFFFFFF, 440EP
),
4406 /* PowerPC 440 SP2 */
4407 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2
, 0xFFFFFFFF, 440EP
),
4408 /* PowerPC 440 SPE */
4409 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE
, 0xFFFFFFFF, 440EP
),
4410 /* PowerPC 460 family */
4412 /* Generic PowerPC 464 */
4413 POWERPC_DEF("464", CPU_POWERPC_464
, 0xFFFFFFFF, 460),
4415 /* PowerPC 464 microcontrolers */
4417 /* PowerPC 464H90 */
4418 POWERPC_DEF("464H90", CPU_POWERPC_464H90
, 0xFFFFFFFF, 460),
4421 /* PowerPC 464H90F */
4422 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F
, 0xFFFFFFFF, 460F
),
4424 /* Freescale embedded PowerPC cores */
4427 /* Generic PowerPC e200 core */
4428 POWERPC_DEF("e200", CPU_POWERPC_e200
, 0xFFFFFFFF, e200
),
4431 /* PowerPC e200z5 core */
4432 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5
, 0xFFFFFFFF, e200
),
4435 /* PowerPC e200z6 core */
4436 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6
, 0xFFFFFFFF, e200
),
4440 /* Generic PowerPC e300 core */
4441 POWERPC_DEF("e300", CPU_POWERPC_e300
, 0xFFFFFFFF, e300
),
4444 /* PowerPC e300c1 core */
4445 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1
, 0xFFFFFFFF, e300
),
4448 /* PowerPC e300c2 core */
4449 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2
, 0xFFFFFFFF, e300
),
4452 /* PowerPC e300c3 core */
4453 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3
, 0xFFFFFFFF, e300
),
4457 /* PowerPC e500 core */
4458 POWERPC_DEF("e500", CPU_POWERPC_e500
, 0xFFFFFFFF, e500
),
4461 /* PowerPC e500 v1.1 core */
4462 POWERPC_DEF("e500v1.1", CPU_POWERPC_e500_v11
, 0xFFFFFFFF, e500
),
4465 /* PowerPC e500 v1.2 core */
4466 POWERPC_DEF("e500v1.2", CPU_POWERPC_e500_v12
, 0xFFFFFFFF, e500
),
4469 /* PowerPC e500 v2.1 core */
4470 POWERPC_DEF("e500v2.1", CPU_POWERPC_e500_v21
, 0xFFFFFFFF, e500
),
4473 /* PowerPC e500 v2.2 core */
4474 POWERPC_DEF("e500v2.2", CPU_POWERPC_e500_v22
, 0xFFFFFFFF, e500
),
4478 /* PowerPC e600 core */
4479 POWERPC_DEF("e600", CPU_POWERPC_e600
, 0xFFFFFFFF, e600
),
4481 /* PowerPC MPC 5xx cores */
4483 /* PowerPC MPC 5xx */
4484 POWERPC_DEF("mpc5xx", CPU_POWERPC_5xx
, 0xFFFFFFFF, 5xx
),
4486 /* PowerPC MPC 8xx cores */
4488 /* PowerPC MPC 8xx */
4489 POWERPC_DEF("mpc8xx", CPU_POWERPC_8xx
, 0xFFFFFFFF, 8xx
),
4491 /* PowerPC MPC 8xxx cores */
4493 /* PowerPC MPC 82xx HIP3 */
4494 POWERPC_DEF("mpc82xxhip3", CPU_POWERPC_82xx_HIP3
, 0xFFFFFFFF, 82xx
),
4497 /* PowerPC MPC 82xx HIP4 */
4498 POWERPC_DEF("mpc82xxhip4", CPU_POWERPC_82xx_HIP4
, 0xFFFFFFFF, 82xx
),
4501 /* PowerPC MPC 827x */
4502 POWERPC_DEF("mpc827x", CPU_POWERPC_827x
, 0xFFFFFFFF, 827x
),
4505 /* 32 bits "classic" PowerPC */
4506 /* PowerPC 6xx family */
4508 POWERPC_DEF("601", CPU_POWERPC_601
, 0xFFFFFFFF, 601),
4510 POWERPC_DEF("601a", CPU_POWERPC_601a
, 0xFFFFFFFF, 601),
4512 POWERPC_DEF("602", CPU_POWERPC_602
, 0xFFFFFFFF, 602),
4514 POWERPC_DEF("603", CPU_POWERPC_603
, 0xFFFFFFFF, 603),
4515 /* Code name for PowerPC 603 */
4516 POWERPC_DEF("Vanilla", CPU_POWERPC_603
, 0xFFFFFFFF, 603),
4518 POWERPC_DEF("603e", CPU_POWERPC_603E
, 0xFFFFFFFF, 603E
),
4519 /* Code name for PowerPC 603e */
4520 POWERPC_DEF("Stretch", CPU_POWERPC_603E
, 0xFFFFFFFF, 603E
),
4521 /* PowerPC 603e v1.1 */
4522 POWERPC_DEF("603e1.1", CPU_POWERPC_603E_v11
, 0xFFFFFFFF, 603E
),
4523 /* PowerPC 603e v1.2 */
4524 POWERPC_DEF("603e1.2", CPU_POWERPC_603E_v12
, 0xFFFFFFFF, 603E
),
4525 /* PowerPC 603e v1.3 */
4526 POWERPC_DEF("603e1.3", CPU_POWERPC_603E_v13
, 0xFFFFFFFF, 603E
),
4527 /* PowerPC 603e v1.4 */
4528 POWERPC_DEF("603e1.4", CPU_POWERPC_603E_v14
, 0xFFFFFFFF, 603E
),
4529 /* PowerPC 603e v2.2 */
4530 POWERPC_DEF("603e2.2", CPU_POWERPC_603E_v22
, 0xFFFFFFFF, 603E
),
4531 /* PowerPC 603e v3 */
4532 POWERPC_DEF("603e3", CPU_POWERPC_603E_v3
, 0xFFFFFFFF, 603E
),
4533 /* PowerPC 603e v4 */
4534 POWERPC_DEF("603e4", CPU_POWERPC_603E_v4
, 0xFFFFFFFF, 603E
),
4535 /* PowerPC 603e v4.1 */
4536 POWERPC_DEF("603e4.1", CPU_POWERPC_603E_v41
, 0xFFFFFFFF, 603E
),
4538 POWERPC_DEF("603e7", CPU_POWERPC_603E7
, 0xFFFFFFFF, 603E
),
4539 /* PowerPC 603e7t */
4540 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t
, 0xFFFFFFFF, 603E
),
4541 /* PowerPC 603e7v */
4542 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v
, 0xFFFFFFFF, 603E
),
4543 /* Code name for PowerPC 603ev */
4544 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v
, 0xFFFFFFFF, 603E
),
4545 /* PowerPC 603e7v1 */
4546 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1
, 0xFFFFFFFF, 603E
),
4547 /* PowerPC 603e7v2 */
4548 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2
, 0xFFFFFFFF, 603E
),
4551 POWERPC_DEF("603p", CPU_POWERPC_603P
, 0xFFFFFFFF, 603),
4553 POWERPC_DEF("603r", CPU_POWERPC_603R
, 0xFFFFFFFF, 603E
),
4554 /* Code name for PowerPC 603r */
4555 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R
, 0xFFFFFFFF, 603E
),
4556 /* PowerPC G2 core */
4557 POWERPC_DEF("G2", CPU_POWERPC_G2
, 0xFFFFFFFF, G2
),
4559 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4
, 0xFFFFFFFF, G2
),
4561 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp
, 0xFFFFFFFF, G2
),
4563 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls
, 0xFFFFFFFF, G2
),
4565 /* Same as G2, with little-endian mode support */
4566 POWERPC_DEF("G2le", CPU_POWERPC_G2LE
, 0xFFFFFFFF, G2LE
),
4567 /* PowerPC G2LE GP */
4568 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp
, 0xFFFFFFFF, G2LE
),
4569 /* PowerPC G2LE LS */
4570 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls
, 0xFFFFFFFF, G2LE
),
4572 POWERPC_DEF("604", CPU_POWERPC_604
, 0xFFFFFFFF, 604),
4574 POWERPC_DEF("604e", CPU_POWERPC_604E
, 0xFFFFFFFF, 604),
4575 /* PowerPC 604e v1.0 */
4576 POWERPC_DEF("604e1.0", CPU_POWERPC_604E_v10
, 0xFFFFFFFF, 604),
4577 /* PowerPC 604e v2.2 */
4578 POWERPC_DEF("604e2.2", CPU_POWERPC_604E_v22
, 0xFFFFFFFF, 604),
4579 /* PowerPC 604e v2.4 */
4580 POWERPC_DEF("604e2.4", CPU_POWERPC_604E_v24
, 0xFFFFFFFF, 604),
4582 POWERPC_DEF("604r", CPU_POWERPC_604R
, 0xFFFFFFFF, 604),
4585 POWERPC_DEF("604ev", CPU_POWERPC_604EV
, 0xFFFFFFFF, 604),
4587 /* PowerPC 7xx family */
4588 /* Generic PowerPC 740 (G3) */
4589 POWERPC_DEF("740", CPU_POWERPC_7x0
, 0xFFFFFFFF, 7x0
),
4590 /* Generic PowerPC 750 (G3) */
4591 POWERPC_DEF("750", CPU_POWERPC_7x0
, 0xFFFFFFFF, 7x0
),
4592 /* Code name for generic PowerPC 740/750 (G3) */
4593 POWERPC_DEF("Arthur", CPU_POWERPC_7x0
, 0xFFFFFFFF, 7x0
),
4594 /* PowerPC 740/750 is also known as G3 */
4595 POWERPC_DEF("G3", CPU_POWERPC_7x0
, 0xFFFFFFFF, 7x0
),
4596 /* PowerPC 740 v2.0 (G3) */
4597 POWERPC_DEF("740v2.0", CPU_POWERPC_7x0_v20
, 0xFFFFFFFF, 7x0
),
4598 /* PowerPC 750 v2.0 (G3) */
4599 POWERPC_DEF("750v2.0", CPU_POWERPC_7x0_v20
, 0xFFFFFFFF, 7x0
),
4600 /* PowerPC 740 v2.1 (G3) */
4601 POWERPC_DEF("740v2.1", CPU_POWERPC_7x0_v21
, 0xFFFFFFFF, 7x0
),
4602 /* PowerPC 750 v2.1 (G3) */
4603 POWERPC_DEF("750v2.1", CPU_POWERPC_7x0_v21
, 0xFFFFFFFF, 7x0
),
4604 /* PowerPC 740 v2.2 (G3) */
4605 POWERPC_DEF("740v2.2", CPU_POWERPC_7x0_v22
, 0xFFFFFFFF, 7x0
),
4606 /* PowerPC 750 v2.2 (G3) */
4607 POWERPC_DEF("750v2.2", CPU_POWERPC_7x0_v22
, 0xFFFFFFFF, 7x0
),
4608 /* PowerPC 740 v3.0 (G3) */
4609 POWERPC_DEF("740v3.0", CPU_POWERPC_7x0_v30
, 0xFFFFFFFF, 7x0
),
4610 /* PowerPC 750 v3.0 (G3) */
4611 POWERPC_DEF("750v3.0", CPU_POWERPC_7x0_v30
, 0xFFFFFFFF, 7x0
),
4612 /* PowerPC 740 v3.1 (G3) */
4613 POWERPC_DEF("740v3.1", CPU_POWERPC_7x0_v31
, 0xFFFFFFFF, 7x0
),
4614 /* PowerPC 750 v3.1 (G3) */
4615 POWERPC_DEF("750v3.1", CPU_POWERPC_7x0_v31
, 0xFFFFFFFF, 7x0
),
4616 /* PowerPC 740E (G3) */
4617 POWERPC_DEF("740e", CPU_POWERPC_740E
, 0xFFFFFFFF, 7x0
),
4618 /* PowerPC 740P (G3) */
4619 POWERPC_DEF("740p", CPU_POWERPC_7x0P
, 0xFFFFFFFF, 7x0
),
4620 /* PowerPC 750P (G3) */
4621 POWERPC_DEF("750p", CPU_POWERPC_7x0P
, 0xFFFFFFFF, 7x0
),
4622 /* Code name for PowerPC 740P/750P (G3) */
4623 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P
, 0xFFFFFFFF, 7x0
),
4624 /* PowerPC 750CL (G3 embedded) */
4625 POWERPC_DEF("750cl", CPU_POWERPC_750CL
, 0xFFFFFFFF, 7x0
),
4626 /* PowerPC 750CX (G3 embedded) */
4627 POWERPC_DEF("750cx", CPU_POWERPC_750CX
, 0xFFFFFFFF, 7x0
),
4628 /* PowerPC 750CX v2.1 (G3 embedded) */
4629 POWERPC_DEF("750cx2.1", CPU_POWERPC_750CX_v21
, 0xFFFFFFFF, 7x0
),
4630 /* PowerPC 750CX v2.2 (G3 embedded) */
4631 POWERPC_DEF("750cx2.2", CPU_POWERPC_750CX_v22
, 0xFFFFFFFF, 7x0
),
4632 /* PowerPC 750CXe (G3 embedded) */
4633 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE
, 0xFFFFFFFF, 7x0
),
4634 /* PowerPC 750CXe v2.1 (G3 embedded) */
4635 POWERPC_DEF("750cxe21", CPU_POWERPC_750CXE_v21
, 0xFFFFFFFF, 7x0
),
4636 /* PowerPC 750CXe v2.2 (G3 embedded) */
4637 POWERPC_DEF("750cxe22", CPU_POWERPC_750CXE_v22
, 0xFFFFFFFF, 7x0
),
4638 /* PowerPC 750CXe v2.3 (G3 embedded) */
4639 POWERPC_DEF("750cxe23", CPU_POWERPC_750CXE_v23
, 0xFFFFFFFF, 7x0
),
4640 /* PowerPC 750CXe v2.4 (G3 embedded) */
4641 POWERPC_DEF("750cxe24", CPU_POWERPC_750CXE_v24
, 0xFFFFFFFF, 7x0
),
4642 /* PowerPC 750CXe v2.4b (G3 embedded) */
4643 POWERPC_DEF("750cxe24b", CPU_POWERPC_750CXE_v24b
, 0xFFFFFFFF, 7x0
),
4644 /* PowerPC 750CXe v3.1 (G3 embedded) */
4645 POWERPC_DEF("750cxe31", CPU_POWERPC_750CXE_v31
, 0xFFFFFFFF, 7x0
),
4646 /* PowerPC 750CXe v3.1b (G3 embedded) */
4647 POWERPC_DEF("750cxe3.1b", CPU_POWERPC_750CXE_v31b
, 0xFFFFFFFF, 7x0
),
4648 /* PowerPC 750CXr (G3 embedded) */
4649 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR
, 0xFFFFFFFF, 7x0
),
4650 /* PowerPC 750E (G3) */
4651 POWERPC_DEF("750e", CPU_POWERPC_750E
, 0xFFFFFFFF, 7x0
),
4652 /* PowerPC 750FL (G3 embedded) */
4653 POWERPC_DEF("750fl", CPU_POWERPC_750FL
, 0xFFFFFFFF, 750fx
),
4654 /* PowerPC 750FX (G3 embedded) */
4655 POWERPC_DEF("750fx", CPU_POWERPC_750FX
, 0xFFFFFFFF, 750fx
),
4656 /* PowerPC 750FX v1.0 (G3 embedded) */
4657 POWERPC_DEF("750fx1.0", CPU_POWERPC_750FX_v10
, 0xFFFFFFFF, 750fx
),
4658 /* PowerPC 750FX v2.0 (G3 embedded) */
4659 POWERPC_DEF("750fx2.0", CPU_POWERPC_750FX_v20
, 0xFFFFFFFF, 750fx
),
4660 /* PowerPC 750FX v2.1 (G3 embedded) */
4661 POWERPC_DEF("750fx2.1", CPU_POWERPC_750FX_v21
, 0xFFFFFFFF, 750fx
),
4662 /* PowerPC 750FX v2.2 (G3 embedded) */
4663 POWERPC_DEF("750fx2.2", CPU_POWERPC_750FX_v22
, 0xFFFFFFFF, 750fx
),
4664 /* PowerPC 750FX v2.3 (G3 embedded) */
4665 POWERPC_DEF("750fx2.3", CPU_POWERPC_750FX_v23
, 0xFFFFFFFF, 750fx
),
4666 /* PowerPC 750GL (G3 embedded) */
4667 POWERPC_DEF("750gl", CPU_POWERPC_750GL
, 0xFFFFFFFF, 750fx
),
4668 /* PowerPC 750GX (G3 embedded) */
4669 POWERPC_DEF("750gx", CPU_POWERPC_750GX
, 0xFFFFFFFF, 750fx
),
4670 /* PowerPC 750GX v1.0 (G3 embedded) */
4671 POWERPC_DEF("750gx1.0", CPU_POWERPC_750GX_v10
, 0xFFFFFFFF, 750fx
),
4672 /* PowerPC 750GX v1.1 (G3 embedded) */
4673 POWERPC_DEF("750gx1.1", CPU_POWERPC_750GX_v11
, 0xFFFFFFFF, 750fx
),
4674 /* PowerPC 750GX v1.2 (G3 embedded) */
4675 POWERPC_DEF("750gx1.2", CPU_POWERPC_750GX_v12
, 0xFFFFFFFF, 750fx
),
4676 /* PowerPC 750L (G3 embedded) */
4677 POWERPC_DEF("750l", CPU_POWERPC_750L
, 0xFFFFFFFF, 7x0
),
4678 /* Code name for PowerPC 750L (G3 embedded) */
4679 POWERPC_DEF("LoneStar", CPU_POWERPC_750L
, 0xFFFFFFFF, 7x0
),
4680 /* PowerPC 750L v2.2 (G3 embedded) */
4681 POWERPC_DEF("750l2.2", CPU_POWERPC_750L_v22
, 0xFFFFFFFF, 7x0
),
4682 /* PowerPC 750L v3.0 (G3 embedded) */
4683 POWERPC_DEF("750l3.0", CPU_POWERPC_750L_v30
, 0xFFFFFFFF, 7x0
),
4684 /* PowerPC 750L v3.2 (G3 embedded) */
4685 POWERPC_DEF("750l3.2", CPU_POWERPC_750L_v32
, 0xFFFFFFFF, 7x0
),
4686 /* Generic PowerPC 745 */
4687 POWERPC_DEF("745", CPU_POWERPC_7x5
, 0xFFFFFFFF, 7x5
),
4688 /* Generic PowerPC 755 */
4689 POWERPC_DEF("755", CPU_POWERPC_7x5
, 0xFFFFFFFF, 7x5
),
4690 /* Code name for PowerPC 745/755 */
4691 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5
, 0xFFFFFFFF, 7x5
),
4692 /* PowerPC 745 v1.0 */
4693 POWERPC_DEF("745v1.0", CPU_POWERPC_7x5_v10
, 0xFFFFFFFF, 7x5
),
4694 /* PowerPC 755 v1.0 */
4695 POWERPC_DEF("755v1.0", CPU_POWERPC_7x5_v10
, 0xFFFFFFFF, 7x5
),
4696 /* PowerPC 745 v1.1 */
4697 POWERPC_DEF("745v1.1", CPU_POWERPC_7x5_v11
, 0xFFFFFFFF, 7x5
),
4698 /* PowerPC 755 v1.1 */
4699 POWERPC_DEF("755v1.1", CPU_POWERPC_7x5_v11
, 0xFFFFFFFF, 7x5
),
4700 /* PowerPC 745 v2.0 */
4701 POWERPC_DEF("745v2.0", CPU_POWERPC_7x5_v20
, 0xFFFFFFFF, 7x5
),
4702 /* PowerPC 755 v2.0 */
4703 POWERPC_DEF("755v2.0", CPU_POWERPC_7x5_v20
, 0xFFFFFFFF, 7x5
),
4704 /* PowerPC 745 v2.1 */
4705 POWERPC_DEF("745v2.1", CPU_POWERPC_7x5_v21
, 0xFFFFFFFF, 7x5
),
4706 /* PowerPC 755 v2.1 */
4707 POWERPC_DEF("755v2.1", CPU_POWERPC_7x5_v21
, 0xFFFFFFFF, 7x5
),
4708 /* PowerPC 745 v2.2 */
4709 POWERPC_DEF("745v2.2", CPU_POWERPC_7x5_v22
, 0xFFFFFFFF, 7x5
),
4710 /* PowerPC 755 v2.2 */
4711 POWERPC_DEF("755v2.2", CPU_POWERPC_7x5_v22
, 0xFFFFFFFF, 7x5
),
4712 /* PowerPC 745 v2.3 */
4713 POWERPC_DEF("745v2.3", CPU_POWERPC_7x5_v23
, 0xFFFFFFFF, 7x5
),
4714 /* PowerPC 755 v2.3 */
4715 POWERPC_DEF("755v2.3", CPU_POWERPC_7x5_v23
, 0xFFFFFFFF, 7x5
),
4716 /* PowerPC 745 v2.4 */
4717 POWERPC_DEF("745v2.4", CPU_POWERPC_7x5_v24
, 0xFFFFFFFF, 7x5
),
4718 /* PowerPC 755 v2.4 */
4719 POWERPC_DEF("755v2.4", CPU_POWERPC_7x5_v24
, 0xFFFFFFFF, 7x5
),
4720 /* PowerPC 745 v2.5 */
4721 POWERPC_DEF("745v2.5", CPU_POWERPC_7x5_v25
, 0xFFFFFFFF, 7x5
),
4722 /* PowerPC 755 v2.5 */
4723 POWERPC_DEF("755v2.5", CPU_POWERPC_7x5_v25
, 0xFFFFFFFF, 7x5
),
4724 /* PowerPC 745 v2.6 */
4725 POWERPC_DEF("745v2.6", CPU_POWERPC_7x5_v26
, 0xFFFFFFFF, 7x5
),
4726 /* PowerPC 755 v2.6 */
4727 POWERPC_DEF("755v2.6", CPU_POWERPC_7x5_v26
, 0xFFFFFFFF, 7x5
),
4728 /* PowerPC 745 v2.7 */
4729 POWERPC_DEF("745v2.7", CPU_POWERPC_7x5_v27
, 0xFFFFFFFF, 7x5
),
4730 /* PowerPC 755 v2.7 */
4731 POWERPC_DEF("755v2.7", CPU_POWERPC_7x5_v27
, 0xFFFFFFFF, 7x5
),
4732 /* PowerPC 745 v2.8 */
4733 POWERPC_DEF("745v2.8", CPU_POWERPC_7x5_v28
, 0xFFFFFFFF, 7x5
),
4734 /* PowerPC 755 v2.8 */
4735 POWERPC_DEF("755v2.8", CPU_POWERPC_7x5_v28
, 0xFFFFFFFF, 7x5
),
4737 /* PowerPC 745P (G3) */
4738 POWERPC_DEF("745p", CPU_POWERPC_7x5P
, 0xFFFFFFFF, 7x5
),
4739 /* PowerPC 755P (G3) */
4740 POWERPC_DEF("755p", CPU_POWERPC_7x5P
, 0xFFFFFFFF, 7x5
),
4742 /* PowerPC 74xx family */
4743 /* PowerPC 7400 (G4) */
4744 POWERPC_DEF("7400", CPU_POWERPC_7400
, 0xFFFFFFFF, 7400),
4745 /* Code name for PowerPC 7400 */
4746 POWERPC_DEF("Max", CPU_POWERPC_7400
, 0xFFFFFFFF, 7400),
4747 /* PowerPC 74xx is also well known as G4 */
4748 POWERPC_DEF("G4", CPU_POWERPC_7400
, 0xFFFFFFFF, 7400),
4749 /* PowerPC 7400 v1.0 (G4) */
4750 POWERPC_DEF("7400v1.0", CPU_POWERPC_7400_v10
, 0xFFFFFFFF, 7400),
4751 /* PowerPC 7400 v1.1 (G4) */
4752 POWERPC_DEF("7400v1.1", CPU_POWERPC_7400_v11
, 0xFFFFFFFF, 7400),
4753 /* PowerPC 7400 v2.0 (G4) */
4754 POWERPC_DEF("7400v2.0", CPU_POWERPC_7400_v20
, 0xFFFFFFFF, 7400),
4755 /* PowerPC 7400 v2.2 (G4) */
4756 POWERPC_DEF("7400v2.2", CPU_POWERPC_7400_v22
, 0xFFFFFFFF, 7400),
4757 /* PowerPC 7400 v2.6 (G4) */
4758 POWERPC_DEF("7400v2.6", CPU_POWERPC_7400_v26
, 0xFFFFFFFF, 7400),
4759 /* PowerPC 7400 v2.7 (G4) */
4760 POWERPC_DEF("7400v2.7", CPU_POWERPC_7400_v27
, 0xFFFFFFFF, 7400),
4761 /* PowerPC 7400 v2.8 (G4) */
4762 POWERPC_DEF("7400v2.8", CPU_POWERPC_7400_v28
, 0xFFFFFFFF, 7400),
4763 /* PowerPC 7400 v2.9 (G4) */
4764 POWERPC_DEF("7400v2.9", CPU_POWERPC_7400_v29
, 0xFFFFFFFF, 7400),
4765 /* PowerPC 7410 (G4) */
4766 POWERPC_DEF("7410", CPU_POWERPC_7410
, 0xFFFFFFFF, 7410),
4767 /* Code name for PowerPC 7410 */
4768 POWERPC_DEF("Nitro", CPU_POWERPC_7410
, 0xFFFFFFFF, 7410),
4769 /* PowerPC 7410 v1.0 (G4) */
4770 POWERPC_DEF("7410v1.0", CPU_POWERPC_7410_v10
, 0xFFFFFFFF, 7410),
4771 /* PowerPC 7410 v1.1 (G4) */
4772 POWERPC_DEF("7410v1.1", CPU_POWERPC_7410_v11
, 0xFFFFFFFF, 7410),
4773 /* PowerPC 7410 v1.2 (G4) */
4774 POWERPC_DEF("7410v1.2", CPU_POWERPC_7410_v12
, 0xFFFFFFFF, 7410),
4775 /* PowerPC 7410 v1.3 (G4) */
4776 POWERPC_DEF("7410v1.3", CPU_POWERPC_7410_v13
, 0xFFFFFFFF, 7410),
4777 /* PowerPC 7410 v1.4 (G4) */
4778 POWERPC_DEF("7410v1.4", CPU_POWERPC_7410_v14
, 0xFFFFFFFF, 7410),
4779 /* PowerPC 7448 (G4) */
4780 POWERPC_DEF("7448", CPU_POWERPC_7448
, 0xFFFFFFFF, 7400),
4781 /* PowerPC 7448 v1.0 (G4) */
4782 POWERPC_DEF("7448v1.0", CPU_POWERPC_7448_v10
, 0xFFFFFFFF, 7400),
4783 /* PowerPC 7448 v1.1 (G4) */
4784 POWERPC_DEF("7448v1.1", CPU_POWERPC_7448_v11
, 0xFFFFFFFF, 7400),
4785 /* PowerPC 7448 v2.0 (G4) */
4786 POWERPC_DEF("7448v2.0", CPU_POWERPC_7448_v20
, 0xFFFFFFFF, 7400),
4787 /* PowerPC 7448 v2.1 (G4) */
4788 POWERPC_DEF("7448v2.1", CPU_POWERPC_7448_v21
, 0xFFFFFFFF, 7400),
4790 /* PowerPC 7450 (G4) */
4791 POWERPC_DEF("7450", CPU_POWERPC_7450
, 0xFFFFFFFF, 7450),
4792 /* Code name for PowerPC 7450 */
4793 POWERPC_DEF("Vger", CPU_POWERPC_7450
, 0xFFFFFFFF, 7450),
4796 /* PowerPC 7450 v1.0 (G4) */
4797 POWERPC_DEF("7450v1.0", CPU_POWERPC_7450_v10
, 0xFFFFFFFF, 7450),
4800 /* PowerPC 7450 v1.1 (G4) */
4801 POWERPC_DEF("7450v1.1", CPU_POWERPC_7450_v11
, 0xFFFFFFFF, 7450),
4804 /* PowerPC 7450 v1.2 (G4) */
4805 POWERPC_DEF("7450v1.2", CPU_POWERPC_7450_v12
, 0xFFFFFFFF, 7450),
4808 /* PowerPC 7450 v2.0 (G4) */
4809 POWERPC_DEF("7450v2.0", CPU_POWERPC_7450_v20
, 0xFFFFFFFF, 7450),
4812 /* PowerPC 7450 v2.1 (G4) */
4813 POWERPC_DEF("7450v2.1", CPU_POWERPC_7450_v21
, 0xFFFFFFFF, 7450),
4816 /* PowerPC 7441 (G4) */
4817 POWERPC_DEF("7441", CPU_POWERPC_74x1
, 0xFFFFFFFF, 7440),
4818 /* PowerPC 7451 (G4) */
4819 POWERPC_DEF("7451", CPU_POWERPC_74x1
, 0xFFFFFFFF, 7450),
4822 /* PowerPC 7441g (G4) */
4823 POWERPC_DEF("7441g", CPU_POWERPC_74x1G
, 0xFFFFFFFF, 7440),
4824 /* PowerPC 7451g (G4) */
4825 POWERPC_DEF("7451g", CPU_POWERPC_74x1G
, 0xFFFFFFFF, 7450),
4828 /* PowerPC 7445 (G4) */
4829 POWERPC_DEF("7445", CPU_POWERPC_74x5
, 0xFFFFFFFF, 7445),
4830 /* PowerPC 7455 (G4) */
4831 POWERPC_DEF("7455", CPU_POWERPC_74x5
, 0xFFFFFFFF, 7455),
4832 /* Code name for PowerPC 7445/7455 */
4833 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5
, 0xFFFFFFFF, 7455),
4836 /* PowerPC 7445 v1.0 (G4) */
4837 POWERPC_DEF("7445v1.0", CPU_POWERPC_74x5_v10
, 0xFFFFFFFF, 7445),
4838 /* PowerPC 7455 v1.0 (G4) */
4839 POWERPC_DEF("7455v1.0", CPU_POWERPC_74x5_v10
, 0xFFFFFFFF, 7455),
4842 /* PowerPC 7445 v2.1 (G4) */
4843 POWERPC_DEF("7445v2.1", CPU_POWERPC_74x5_v21
, 0xFFFFFFFF, 7445),
4844 /* PowerPC 7455 v2.1 (G4) */
4845 POWERPC_DEF("7455v2.1", CPU_POWERPC_74x5_v21
, 0xFFFFFFFF, 7455),
4848 /* PowerPC 7445 v3.2 (G4) */
4849 POWERPC_DEF("7445v3.2", CPU_POWERPC_74x5_v32
, 0xFFFFFFFF, 7445),
4850 /* PowerPC 7455 v3.2 (G4) */
4851 POWERPC_DEF("7455v3.2", CPU_POWERPC_74x5_v32
, 0xFFFFFFFF, 7455),
4854 /* PowerPC 7445 v3.3 (G4) */
4855 POWERPC_DEF("7445v3.3", CPU_POWERPC_74x5_v33
, 0xFFFFFFFF, 7445),
4856 /* PowerPC 7455 v3.3 (G4) */
4857 POWERPC_DEF("7455v3.3", CPU_POWERPC_74x5_v33
, 0xFFFFFFFF, 7455),
4860 /* PowerPC 7445 v3.4 (G4) */
4861 POWERPC_DEF("7445v3.4", CPU_POWERPC_74x5_v34
, 0xFFFFFFFF, 7445),
4862 /* PowerPC 7455 v3.4 (G4) */
4863 POWERPC_DEF("7455v3.4", CPU_POWERPC_74x5_v34
, 0xFFFFFFFF, 7455),
4866 /* PowerPC 7447 (G4) */
4867 POWERPC_DEF("7447", CPU_POWERPC_74x7
, 0xFFFFFFFF, 7445),
4868 /* PowerPC 7457 (G4) */
4869 POWERPC_DEF("7457", CPU_POWERPC_74x7
, 0xFFFFFFFF, 7455),
4870 /* Code name for PowerPC 7447/7457 */
4871 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7
, 0xFFFFFFFF, 7455),
4874 /* PowerPC 7447 v1.0 (G4) */
4875 POWERPC_DEF("7447v1.0", CPU_POWERPC_74x7_v10
, 0xFFFFFFFF, 7445),
4876 /* PowerPC 7457 v1.0 (G4) */
4877 POWERPC_DEF("7457v1.0", CPU_POWERPC_74x7_v10
, 0xFFFFFFFF, 7455),
4878 /* Code name for PowerPC 7447A/7457A */
4879 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10
, 0xFFFFFFFF, 7455),
4882 /* PowerPC 7447 v1.1 (G4) */
4883 POWERPC_DEF("7447v1.1", CPU_POWERPC_74x7_v11
, 0xFFFFFFFF, 7445),
4884 /* PowerPC 7457 v1.1 (G4) */
4885 POWERPC_DEF("7457v1.1", CPU_POWERPC_74x7_v11
, 0xFFFFFFFF, 7455),
4888 /* PowerPC 7447 v1.2 (G4) */
4889 POWERPC_DEF("7447v1.2", CPU_POWERPC_74x7_v12
, 0xFFFFFFFF, 7445),
4890 /* PowerPC 7457 v1.2 (G4) */
4891 POWERPC_DEF("7457v1.2", CPU_POWERPC_74x7_v12
, 0xFFFFFFFF, 7455),
4893 /* 64 bits PowerPC */
4894 #if defined (TARGET_PPC64)
4897 POWERPC_DEF("620", CPU_POWERPC_620
, 0xFFFFFFFF, 620),
4900 /* PowerPC 630 (POWER3) */
4901 POWERPC_DEF("630", CPU_POWERPC_630
, 0xFFFFFFFF, 630),
4902 POWERPC_DEF("POWER3", CPU_POWERPC_630
, 0xFFFFFFFF, 630),
4905 /* PowerPC 631 (Power 3+) */
4906 POWERPC_DEF("631", CPU_POWERPC_631
, 0xFFFFFFFF, 631),
4907 POWERPC_DEF("POWER3+", CPU_POWERPC_631
, 0xFFFFFFFF, 631),
4911 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4
, 0xFFFFFFFF, POWER4
),
4915 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P
, 0xFFFFFFFF, POWER4P
),
4919 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5
, 0xFFFFFFFF, POWER5
),
4921 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR
, 0xFFFFFFFF, POWER5
),
4925 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P
, 0xFFFFFFFF, POWER5P
),
4927 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS
, 0xFFFFFFFF, POWER5P
),
4931 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6
, 0xFFFFFFFF, POWER6
),
4932 /* POWER6 running in POWER5 mode */
4933 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5
, 0xFFFFFFFF, POWER5
),
4935 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A
, 0xFFFFFFFF, POWER6
),
4938 POWERPC_DEF("970", CPU_POWERPC_970
, 0xFFFFFFFF, 970),
4939 /* PowerPC 970FX (G5) */
4940 POWERPC_DEF("970fx", CPU_POWERPC_970FX
, 0xFFFFFFFF, 970FX
),
4941 /* PowerPC 970FX v1.0 (G5) */
4942 POWERPC_DEF("970fx1.0", CPU_POWERPC_970FX_v10
, 0xFFFFFFFF, 970FX
),
4943 /* PowerPC 970FX v2.0 (G5) */
4944 POWERPC_DEF("970fx2.0", CPU_POWERPC_970FX_v20
, 0xFFFFFFFF, 970FX
),
4945 /* PowerPC 970FX v2.1 (G5) */
4946 POWERPC_DEF("970fx2.1", CPU_POWERPC_970FX_v21
, 0xFFFFFFFF, 970FX
),
4947 /* PowerPC 970FX v3.0 (G5) */
4948 POWERPC_DEF("970fx3.0", CPU_POWERPC_970FX_v30
, 0xFFFFFFFF, 970FX
),
4949 /* PowerPC 970FX v3.1 (G5) */
4950 POWERPC_DEF("970fx3.1", CPU_POWERPC_970FX_v31
, 0xFFFFFFFF, 970FX
),
4951 /* PowerPC 970GX (G5) */
4952 POWERPC_DEF("970gx", CPU_POWERPC_970GX
, 0xFFFFFFFF, 970GX
),
4954 POWERPC_DEF("970mp", CPU_POWERPC_970MP
, 0xFFFFFFFF, 970),
4955 /* PowerPC 970MP v1.0 */
4956 POWERPC_DEF("970mp1.0", CPU_POWERPC_970MP_v10
, 0xFFFFFFFF, 970),
4957 /* PowerPC 970MP v1.1 */
4958 POWERPC_DEF("970mp1.1", CPU_POWERPC_970MP_v11
, 0xFFFFFFFF, 970),
4961 POWERPC_DEF("Cell", CPU_POWERPC_CELL
, 0xFFFFFFFF, 970),
4964 /* PowerPC Cell v1.0 */
4965 POWERPC_DEF("Cell1.0", CPU_POWERPC_CELL_v10
, 0xFFFFFFFF, 970),
4968 /* PowerPC Cell v2.0 */
4969 POWERPC_DEF("Cell2.0", CPU_POWERPC_CELL_v20
, 0xFFFFFFFF, 970),
4972 /* PowerPC Cell v3.0 */
4973 POWERPC_DEF("Cell3.0", CPU_POWERPC_CELL_v30
, 0xFFFFFFFF, 970),
4976 /* PowerPC Cell v3.1 */
4977 POWERPC_DEF("Cell3.1", CPU_POWERPC_CELL_v31
, 0xFFFFFFFF, 970),
4980 /* PowerPC Cell v3.2 */
4981 POWERPC_DEF("Cell3.2", CPU_POWERPC_CELL_v32
, 0xFFFFFFFF, 970),
4984 /* RS64 (Apache/A35) */
4985 /* This one seems to support the whole POWER2 instruction set
4986 * and the PowerPC 64 one.
4988 /* What about A10 & A30 ? */
4989 POWERPC_DEF("RS64", CPU_POWERPC_RS64
, 0xFFFFFFFF, RS64
),
4990 POWERPC_DEF("Apache", CPU_POWERPC_RS64
, 0xFFFFFFFF, RS64
),
4991 POWERPC_DEF("A35", CPU_POWERPC_RS64
, 0xFFFFFFFF, RS64
),
4994 /* RS64-II (NorthStar/A50) */
4995 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II
, 0xFFFFFFFF, RS64
),
4996 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II
, 0xFFFFFFFF, RS64
),
4997 POWERPC_DEF("A50", CPU_POWERPC_RS64II
, 0xFFFFFFFF, RS64
),
5000 /* RS64-III (Pulsar) */
5001 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III
, 0xFFFFFFFF, RS64
),
5002 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III
, 0xFFFFFFFF, RS64
),
5005 /* RS64-IV (IceStar/IStar/SStar) */
5006 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV
, 0xFFFFFFFF, RS64
),
5007 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV
, 0xFFFFFFFF, RS64
),
5008 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV
, 0xFFFFFFFF, RS64
),
5009 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV
, 0xFFFFFFFF, RS64
),
5011 #endif /* defined (TARGET_PPC64) */
5014 /* Original POWER */
5015 POWERPC_DEF("POWER", CPU_POWERPC_POWER
, 0xFFFFFFFF, POWER
),
5016 POWERPC_DEF("RIOS", CPU_POWERPC_POWER
, 0xFFFFFFFF, POWER
),
5017 POWERPC_DEF("RSC", CPU_POWERPC_POWER
, 0xFFFFFFFF, POWER
),
5018 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER
, 0xFFFFFFFF, POWER
),
5019 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER
, 0xFFFFFFFF, POWER
),
5023 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2
, 0xFFFFFFFF, POWER
),
5024 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2
, 0xFFFFFFFF, POWER
),
5025 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2
, 0xFFFFFFFF, POWER
),
5030 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T
, 0xFFFFFFFF, PA6T
),
5032 /* Generic PowerPCs */
5033 #if defined (TARGET_PPC64)
5035 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64
, 0xFFFFFFFF, PPC64
),
5038 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32
, 0xFFFFFFFF, PPC32
),
5039 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT
, 0xFFFFFFFF, DEFAULT
),
5041 POWERPC_DEF("default", CPU_POWERPC_DEFAULT
, 0xFFFFFFFF, DEFAULT
),
5044 /*****************************************************************************/
5045 /* Generic CPU instanciation routine */
5046 static void init_ppc_proc (CPUPPCState
*env
, ppc_def_t
*def
)
5048 #if !defined(CONFIG_USER_ONLY)
5049 env
->irq_inputs
= NULL
;
5051 /* Default MMU definitions */
5055 /* Register SPR common to all PowerPC implementations */
5056 gen_spr_generic(env
);
5057 spr_register(env
, SPR_PVR
, "PVR",
5058 SPR_NOACCESS
, SPR_NOACCESS
,
5059 &spr_read_generic
, SPR_NOACCESS
,
5061 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
5062 (*def
->init_proc
)(env
);
5063 /* Allocate TLBs buffer when needed */
5064 if (env
->nb_tlb
!= 0) {
5065 int nb_tlb
= env
->nb_tlb
;
5066 if (env
->id_tlbs
!= 0)
5068 env
->tlb
= qemu_mallocz(nb_tlb
* sizeof(ppc_tlb_t
));
5069 /* Pre-compute some useful values */
5070 env
->tlb_per_way
= env
->nb_tlb
/ env
->nb_ways
;
5072 #if !defined(CONFIG_USER_ONLY)
5073 if (env
->irq_inputs
== NULL
) {
5074 fprintf(stderr
, "WARNING: no internal IRQ controller registered.\n"
5075 " Attempt Qemu to crash very soon !\n");
5080 #if defined(PPC_DUMP_CPU)
5081 static void dump_ppc_sprs (CPUPPCState
*env
)
5084 #if !defined(CONFIG_USER_ONLY)
5090 printf("Special purpose registers:\n");
5091 for (i
= 0; i
< 32; i
++) {
5092 for (j
= 0; j
< 32; j
++) {
5094 spr
= &env
->spr_cb
[n
];
5095 uw
= spr
->uea_write
!= NULL
&& spr
->uea_write
!= SPR_NOACCESS
;
5096 ur
= spr
->uea_read
!= NULL
&& spr
->uea_read
!= SPR_NOACCESS
;
5097 #if !defined(CONFIG_USER_ONLY)
5098 sw
= spr
->oea_write
!= NULL
&& spr
->oea_write
!= SPR_NOACCESS
;
5099 sr
= spr
->oea_read
!= NULL
&& spr
->oea_read
!= SPR_NOACCESS
;
5100 if (sw
|| sr
|| uw
|| ur
) {
5101 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
5102 (i
<< 5) | j
, (i
<< 5) | j
, spr
->name
,
5103 sw
? 'w' : '-', sr
? 'r' : '-',
5104 uw
? 'w' : '-', ur
? 'r' : '-');
5108 printf("SPR: %4d (%03x) %-8s u%c%c\n",
5109 (i
<< 5) | j
, (i
<< 5) | j
, spr
->name
,
5110 uw
? 'w' : '-', ur
? 'r' : '-');
5120 /*****************************************************************************/
5124 int fflush (FILE *stream
);
5128 PPC_DIRECT
= 0, /* Opcode routine */
5129 PPC_INDIRECT
= 1, /* Indirect opcode table */
5132 static inline int is_indirect_opcode (void *handler
)
5134 return ((unsigned long)handler
& 0x03) == PPC_INDIRECT
;
5137 static inline opc_handler_t
**ind_table(void *handler
)
5139 return (opc_handler_t
**)((unsigned long)handler
& ~3);
5142 /* Instruction table creation */
5143 /* Opcodes tables creation */
5144 static void fill_new_table (opc_handler_t
**table
, int len
)
5148 for (i
= 0; i
< len
; i
++)
5149 table
[i
] = &invalid_handler
;
5152 static int create_new_table (opc_handler_t
**table
, unsigned char idx
)
5154 opc_handler_t
**tmp
;
5156 tmp
= malloc(0x20 * sizeof(opc_handler_t
));
5159 fill_new_table(tmp
, 0x20);
5160 table
[idx
] = (opc_handler_t
*)((unsigned long)tmp
| PPC_INDIRECT
);
5165 static int insert_in_table (opc_handler_t
**table
, unsigned char idx
,
5166 opc_handler_t
*handler
)
5168 if (table
[idx
] != &invalid_handler
)
5170 table
[idx
] = handler
;
5175 static int register_direct_insn (opc_handler_t
**ppc_opcodes
,
5176 unsigned char idx
, opc_handler_t
*handler
)
5178 if (insert_in_table(ppc_opcodes
, idx
, handler
) < 0) {
5179 printf("*** ERROR: opcode %02x already assigned in main "
5180 "opcode table\n", idx
);
5187 static int register_ind_in_table (opc_handler_t
**table
,
5188 unsigned char idx1
, unsigned char idx2
,
5189 opc_handler_t
*handler
)
5191 if (table
[idx1
] == &invalid_handler
) {
5192 if (create_new_table(table
, idx1
) < 0) {
5193 printf("*** ERROR: unable to create indirect table "
5194 "idx=%02x\n", idx1
);
5198 if (!is_indirect_opcode(table
[idx1
])) {
5199 printf("*** ERROR: idx %02x already assigned to a direct "
5204 if (handler
!= NULL
&&
5205 insert_in_table(ind_table(table
[idx1
]), idx2
, handler
) < 0) {
5206 printf("*** ERROR: opcode %02x already assigned in "
5207 "opcode table %02x\n", idx2
, idx1
);
5214 static int register_ind_insn (opc_handler_t
**ppc_opcodes
,
5215 unsigned char idx1
, unsigned char idx2
,
5216 opc_handler_t
*handler
)
5220 ret
= register_ind_in_table(ppc_opcodes
, idx1
, idx2
, handler
);
5225 static int register_dblind_insn (opc_handler_t
**ppc_opcodes
,
5226 unsigned char idx1
, unsigned char idx2
,
5227 unsigned char idx3
, opc_handler_t
*handler
)
5229 if (register_ind_in_table(ppc_opcodes
, idx1
, idx2
, NULL
) < 0) {
5230 printf("*** ERROR: unable to join indirect table idx "
5231 "[%02x-%02x]\n", idx1
, idx2
);
5234 if (register_ind_in_table(ind_table(ppc_opcodes
[idx1
]), idx2
, idx3
,
5236 printf("*** ERROR: unable to insert opcode "
5237 "[%02x-%02x-%02x]\n", idx1
, idx2
, idx3
);
5244 static int register_insn (opc_handler_t
**ppc_opcodes
, opcode_t
*insn
)
5246 if (insn
->opc2
!= 0xFF) {
5247 if (insn
->opc3
!= 0xFF) {
5248 if (register_dblind_insn(ppc_opcodes
, insn
->opc1
, insn
->opc2
,
5249 insn
->opc3
, &insn
->handler
) < 0)
5252 if (register_ind_insn(ppc_opcodes
, insn
->opc1
,
5253 insn
->opc2
, &insn
->handler
) < 0)
5257 if (register_direct_insn(ppc_opcodes
, insn
->opc1
, &insn
->handler
) < 0)
5264 static int test_opcode_table (opc_handler_t
**table
, int len
)
5268 for (i
= 0, count
= 0; i
< len
; i
++) {
5269 /* Consistency fixup */
5270 if (table
[i
] == NULL
)
5271 table
[i
] = &invalid_handler
;
5272 if (table
[i
] != &invalid_handler
) {
5273 if (is_indirect_opcode(table
[i
])) {
5274 tmp
= test_opcode_table(ind_table(table
[i
]), 0x20);
5277 table
[i
] = &invalid_handler
;
5290 static void fix_opcode_tables (opc_handler_t
**ppc_opcodes
)
5292 if (test_opcode_table(ppc_opcodes
, 0x40) == 0)
5293 printf("*** WARNING: no opcode defined !\n");
5296 /*****************************************************************************/
5297 static int create_ppc_opcodes (CPUPPCState
*env
, ppc_def_t
*def
)
5299 opcode_t
*opc
, *start
, *end
;
5301 fill_new_table(env
->opcodes
, 0x40);
5302 if (&opc_start
< &opc_end
) {
5309 for (opc
= start
+ 1; opc
!= end
; opc
++) {
5310 if ((opc
->handler
.type
& def
->insns_flags
) != 0) {
5311 if (register_insn(env
->opcodes
, opc
) < 0) {
5312 printf("*** ERROR initializing PowerPC instruction "
5313 "0x%02x 0x%02x 0x%02x\n", opc
->opc1
, opc
->opc2
,
5319 fix_opcode_tables(env
->opcodes
);
5326 #if defined(PPC_DUMP_CPU)
5327 static int dump_ppc_insns (CPUPPCState
*env
)
5329 opc_handler_t
**table
, *handler
;
5330 uint8_t opc1
, opc2
, opc3
;
5332 printf("Instructions set:\n");
5333 /* opc1 is 6 bits long */
5334 for (opc1
= 0x00; opc1
< 0x40; opc1
++) {
5335 table
= env
->opcodes
;
5336 handler
= table
[opc1
];
5337 if (is_indirect_opcode(handler
)) {
5338 /* opc2 is 5 bits long */
5339 for (opc2
= 0; opc2
< 0x20; opc2
++) {
5340 table
= env
->opcodes
;
5341 handler
= env
->opcodes
[opc1
];
5342 table
= ind_table(handler
);
5343 handler
= table
[opc2
];
5344 if (is_indirect_opcode(handler
)) {
5345 table
= ind_table(handler
);
5346 /* opc3 is 5 bits long */
5347 for (opc3
= 0; opc3
< 0x20; opc3
++) {
5348 handler
= table
[opc3
];
5349 if (handler
->handler
!= &gen_invalid
) {
5350 printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
5351 opc1
, opc2
, opc3
, opc1
, (opc3
<< 5) | opc2
,
5356 if (handler
->handler
!= &gen_invalid
) {
5357 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
5358 opc1
, opc2
, opc1
, opc2
, handler
->oname
);
5363 if (handler
->handler
!= &gen_invalid
) {
5364 printf("INSN: %02x -- -- (%02d ----) : %s\n",
5365 opc1
, opc1
, handler
->oname
);
5372 int cpu_ppc_register (CPUPPCState
*env
, ppc_def_t
*def
)
5374 env
->msr_mask
= def
->msr_mask
;
5375 env
->mmu_model
= def
->mmu_model
;
5376 env
->excp_model
= def
->excp_model
;
5377 env
->bus_model
= def
->bus_model
;
5378 env
->bfd_mach
= def
->bfd_mach
;
5379 if (create_ppc_opcodes(env
, def
) < 0)
5381 init_ppc_proc(env
, def
);
5382 #if defined(PPC_DUMP_CPU)
5384 const unsigned char *mmu_model
, *excp_model
, *bus_model
;
5385 switch (env
->mmu_model
) {
5386 case POWERPC_MMU_32B
:
5387 mmu_model
= "PowerPC 32";
5389 case POWERPC_MMU_64B
:
5390 mmu_model
= "PowerPC 64";
5392 case POWERPC_MMU_601
:
5393 mmu_model
= "PowerPC 601";
5395 case POWERPC_MMU_SOFT_6xx
:
5396 mmu_model
= "PowerPC 6xx/7xx with software driven TLBs";
5398 case POWERPC_MMU_SOFT_74xx
:
5399 mmu_model
= "PowerPC 74xx with software driven TLBs";
5401 case POWERPC_MMU_SOFT_4xx
:
5402 mmu_model
= "PowerPC 4xx with software driven TLBs";
5404 case POWERPC_MMU_SOFT_4xx_Z
:
5405 mmu_model
= "PowerPC 4xx with software driven TLBs "
5406 "and zones protections";
5408 case POWERPC_MMU_REAL_4xx
:
5409 mmu_model
= "PowerPC 4xx real mode only";
5411 case POWERPC_MMU_BOOKE
:
5412 mmu_model
= "PowerPC BookE";
5414 case POWERPC_MMU_BOOKE_FSL
:
5415 mmu_model
= "PowerPC BookE FSL";
5417 case POWERPC_MMU_64BRIDGE
:
5418 mmu_model
= "PowerPC 64 bridge";
5421 mmu_model
= "Unknown or invalid";
5424 switch (env
->excp_model
) {
5425 case POWERPC_EXCP_STD
:
5426 excp_model
= "PowerPC";
5428 case POWERPC_EXCP_40x
:
5429 excp_model
= "PowerPC 40x";
5431 case POWERPC_EXCP_601
:
5432 excp_model
= "PowerPC 601";
5434 case POWERPC_EXCP_602
:
5435 excp_model
= "PowerPC 602";
5437 case POWERPC_EXCP_603
:
5438 excp_model
= "PowerPC 603";
5440 case POWERPC_EXCP_603E
:
5441 excp_model
= "PowerPC 603e";
5443 case POWERPC_EXCP_604
:
5444 excp_model
= "PowerPC 604";
5446 case POWERPC_EXCP_7x0
:
5447 excp_model
= "PowerPC 740/750";
5449 case POWERPC_EXCP_7x5
:
5450 excp_model
= "PowerPC 745/755";
5452 case POWERPC_EXCP_74xx
:
5453 excp_model
= "PowerPC 74xx";
5455 case POWERPC_EXCP_970
:
5456 excp_model
= "PowerPC 970";
5458 case POWERPC_EXCP_BOOKE
:
5459 excp_model
= "PowerPC BookE";
5462 excp_model
= "Unknown or invalid";
5465 switch (env
->bus_model
) {
5466 case PPC_FLAGS_INPUT_6xx
:
5467 bus_model
= "PowerPC 6xx";
5469 case PPC_FLAGS_INPUT_BookE
:
5470 bus_model
= "PowerPC BookE";
5472 case PPC_FLAGS_INPUT_405
:
5473 bus_model
= "PowerPC 405";
5475 case PPC_FLAGS_INPUT_970
:
5476 bus_model
= "PowerPC 970";
5478 case PPC_FLAGS_INPUT_401
:
5479 bus_model
= "PowerPC 401/403";
5482 bus_model
= "Unknown or invalid";
5485 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64
"\n"
5486 " MMU model : %s\n",
5487 def
->name
, def
->pvr
, def
->msr_mask
, mmu_model
);
5488 if (env
->tlb
!= NULL
) {
5489 printf(" %d %s TLB in %d ways\n",
5490 env
->nb_tlb
, env
->id_tlbs
? "splitted" : "merged",
5493 printf(" Exceptions model : %s\n"
5494 " Bus model : %s\n",
5495 excp_model
, bus_model
);
5497 dump_ppc_insns(env
);
5505 int ppc_find_by_name (const unsigned char *name
, ppc_def_t
**def
)
5511 for (i
= 0; strcmp(ppc_defs
[i
].name
, "default") != 0; i
++) {
5512 if (strcasecmp(name
, ppc_defs
[i
].name
) == 0) {
5513 *def
= &ppc_defs
[i
];
5522 int ppc_find_by_pvr (uint32_t pvr
, ppc_def_t
**def
)
5528 for (i
= 0; ppc_defs
[i
].name
!= NULL
; i
++) {
5529 if ((pvr
& ppc_defs
[i
].pvr_mask
) ==
5530 (ppc_defs
[i
].pvr
& ppc_defs
[i
].pvr_mask
)) {
5531 *def
= &ppc_defs
[i
];
5540 void ppc_cpu_list (FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...))
5544 for (i
= 0; ; i
++) {
5545 (*cpu_fprintf
)(f
, "PowerPC %-16s PVR %08x\n",
5546 ppc_defs
[i
].name
, ppc_defs
[i
].pvr
);
5547 if (strcmp(ppc_defs
[i
].name
, "default") == 0)