2 * PowerPC CPU initialization for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
28 //#define PPC_DUMP_CPU
29 //#define PPC_DEBUG_SPR
30 //#define PPC_DEBUG_IRQ
33 const unsigned char *name
;
44 void (*init_proc
)(CPUPPCState
*env
);
45 int (*check_pow
)(CPUPPCState
*env
);
48 /* For user-mode emulation, we don't emulate any IRQ controller */
49 #if defined(CONFIG_USER_ONLY)
50 #define PPC_IRQ_INIT_FN(name) \
51 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
55 #define PPC_IRQ_INIT_FN(name) \
56 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
64 * do nothing but store/retrieve spr value
66 #ifdef PPC_DUMP_SPR_ACCESSES
67 static void spr_read_generic (void *opaque
, int sprn
)
69 gen_op_load_dump_spr(sprn
);
72 static void spr_write_generic (void *opaque
, int sprn
)
74 gen_op_store_dump_spr(sprn
);
77 static void spr_read_generic (void *opaque
, int sprn
)
79 gen_op_load_spr(sprn
);
82 static void spr_write_generic (void *opaque
, int sprn
)
84 gen_op_store_spr(sprn
);
88 #if !defined(CONFIG_USER_ONLY)
89 static void spr_write_clear (void *opaque
, int sprn
)
91 gen_op_mask_spr(sprn
);
95 /* SPR common to all PowerPC */
97 static void spr_read_xer (void *opaque
, int sprn
)
102 static void spr_write_xer (void *opaque
, int sprn
)
108 static void spr_read_lr (void *opaque
, int sprn
)
113 static void spr_write_lr (void *opaque
, int sprn
)
119 static void spr_read_ctr (void *opaque
, int sprn
)
124 static void spr_write_ctr (void *opaque
, int sprn
)
129 /* User read access to SPR */
135 static void spr_read_ureg (void *opaque
, int sprn
)
137 gen_op_load_spr(sprn
+ 0x10);
140 /* SPR common to all non-embedded PowerPC */
142 #if !defined(CONFIG_USER_ONLY)
143 static void spr_read_decr (void *opaque
, int sprn
)
148 static void spr_write_decr (void *opaque
, int sprn
)
154 /* SPR common to all non-embedded PowerPC, except 601 */
156 static void spr_read_tbl (void *opaque
, int sprn
)
161 static void spr_read_tbu (void *opaque
, int sprn
)
166 __attribute__ (( unused
))
167 static void spr_read_atbl (void *opaque
, int sprn
)
172 __attribute__ (( unused
))
173 static void spr_read_atbu (void *opaque
, int sprn
)
178 #if !defined(CONFIG_USER_ONLY)
179 static void spr_write_tbl (void *opaque
, int sprn
)
184 static void spr_write_tbu (void *opaque
, int sprn
)
189 __attribute__ (( unused
))
190 static void spr_write_atbl (void *opaque
, int sprn
)
195 __attribute__ (( unused
))
196 static void spr_write_atbu (void *opaque
, int sprn
)
202 #if !defined(CONFIG_USER_ONLY)
203 /* IBAT0U...IBAT0U */
204 /* IBAT0L...IBAT7L */
205 static void spr_read_ibat (void *opaque
, int sprn
)
207 gen_op_load_ibat(sprn
& 1, (sprn
- SPR_IBAT0U
) / 2);
210 static void spr_read_ibat_h (void *opaque
, int sprn
)
212 gen_op_load_ibat(sprn
& 1, (sprn
- SPR_IBAT4U
) / 2);
215 static void spr_write_ibatu (void *opaque
, int sprn
)
217 gen_op_store_ibatu((sprn
- SPR_IBAT0U
) / 2);
220 static void spr_write_ibatu_h (void *opaque
, int sprn
)
222 gen_op_store_ibatu((sprn
- SPR_IBAT4U
) / 2);
225 static void spr_write_ibatl (void *opaque
, int sprn
)
227 gen_op_store_ibatl((sprn
- SPR_IBAT0L
) / 2);
230 static void spr_write_ibatl_h (void *opaque
, int sprn
)
232 gen_op_store_ibatl((sprn
- SPR_IBAT4L
) / 2);
235 /* DBAT0U...DBAT7U */
236 /* DBAT0L...DBAT7L */
237 static void spr_read_dbat (void *opaque
, int sprn
)
239 gen_op_load_dbat(sprn
& 1, (sprn
- SPR_DBAT0U
) / 2);
242 static void spr_read_dbat_h (void *opaque
, int sprn
)
244 gen_op_load_dbat(sprn
& 1, ((sprn
- SPR_DBAT4U
) / 2) + 4);
247 static void spr_write_dbatu (void *opaque
, int sprn
)
249 gen_op_store_dbatu((sprn
- SPR_DBAT0U
) / 2);
252 static void spr_write_dbatu_h (void *opaque
, int sprn
)
254 gen_op_store_dbatu(((sprn
- SPR_DBAT4U
) / 2) + 4);
257 static void spr_write_dbatl (void *opaque
, int sprn
)
259 gen_op_store_dbatl((sprn
- SPR_DBAT0L
) / 2);
262 static void spr_write_dbatl_h (void *opaque
, int sprn
)
264 gen_op_store_dbatl(((sprn
- SPR_DBAT4L
) / 2) + 4);
268 static void spr_read_sdr1 (void *opaque
, int sprn
)
273 static void spr_write_sdr1 (void *opaque
, int sprn
)
278 /* 64 bits PowerPC specific SPRs */
280 #if defined(TARGET_PPC64)
281 __attribute__ (( unused
))
282 static void spr_read_asr (void *opaque
, int sprn
)
287 __attribute__ (( unused
))
288 static void spr_write_asr (void *opaque
, int sprn
)
295 /* PowerPC 601 specific registers */
297 static void spr_read_601_rtcl (void *opaque
, int sprn
)
299 gen_op_load_601_rtcl();
302 static void spr_read_601_rtcu (void *opaque
, int sprn
)
304 gen_op_load_601_rtcu();
307 #if !defined(CONFIG_USER_ONLY)
308 static void spr_write_601_rtcu (void *opaque
, int sprn
)
310 gen_op_store_601_rtcu();
313 static void spr_write_601_rtcl (void *opaque
, int sprn
)
315 gen_op_store_601_rtcl();
318 static void spr_write_hid0_601 (void *opaque
, int sprn
)
320 DisasContext
*ctx
= opaque
;
322 gen_op_store_hid0_601();
323 /* Must stop the translation as endianness may have changed */
329 #if !defined(CONFIG_USER_ONLY)
330 static void spr_read_601_ubat (void *opaque
, int sprn
)
332 gen_op_load_601_bat(sprn
& 1, (sprn
- SPR_IBAT0U
) / 2);
335 static void spr_write_601_ubatu (void *opaque
, int sprn
)
337 gen_op_store_601_batu((sprn
- SPR_IBAT0U
) / 2);
340 static void spr_write_601_ubatl (void *opaque
, int sprn
)
342 gen_op_store_601_batl((sprn
- SPR_IBAT0L
) / 2);
346 /* PowerPC 40x specific registers */
347 #if !defined(CONFIG_USER_ONLY)
348 static void spr_read_40x_pit (void *opaque
, int sprn
)
350 gen_op_load_40x_pit();
353 static void spr_write_40x_pit (void *opaque
, int sprn
)
355 gen_op_store_40x_pit();
358 static void spr_write_40x_dbcr0 (void *opaque
, int sprn
)
360 DisasContext
*ctx
= opaque
;
362 gen_op_store_40x_dbcr0();
363 /* We must stop translation as we may have rebooted */
367 static void spr_write_40x_sler (void *opaque
, int sprn
)
369 gen_op_store_40x_sler();
372 static void spr_write_booke_tcr (void *opaque
, int sprn
)
374 gen_op_store_booke_tcr();
377 static void spr_write_booke_tsr (void *opaque
, int sprn
)
379 gen_op_store_booke_tsr();
383 /* PowerPC 403 specific registers */
384 /* PBL1 / PBU1 / PBL2 / PBU2 */
385 #if !defined(CONFIG_USER_ONLY)
386 static void spr_read_403_pbr (void *opaque
, int sprn
)
388 gen_op_load_403_pb(sprn
- SPR_403_PBL1
);
391 static void spr_write_403_pbr (void *opaque
, int sprn
)
393 gen_op_store_403_pb(sprn
- SPR_403_PBL1
);
396 static void spr_write_pir (void *opaque
, int sprn
)
402 #if !defined(CONFIG_USER_ONLY)
403 /* Callback used to write the exception vector base */
404 static void spr_write_excp_prefix (void *opaque
, int sprn
)
406 gen_op_store_excp_prefix();
407 gen_op_store_spr(sprn
);
410 static void spr_write_excp_vector (void *opaque
, int sprn
)
412 DisasContext
*ctx
= opaque
;
414 if (sprn
>= SPR_BOOKE_IVOR0
&& sprn
<= SPR_BOOKE_IVOR15
) {
415 gen_op_store_excp_vector(sprn
- SPR_BOOKE_IVOR0
);
416 gen_op_store_spr(sprn
);
417 } else if (sprn
>= SPR_BOOKE_IVOR32
&& sprn
<= SPR_BOOKE_IVOR37
) {
418 gen_op_store_excp_vector(sprn
- SPR_BOOKE_IVOR32
+ 32);
419 gen_op_store_spr(sprn
);
421 printf("Trying to write an unknown exception vector %d %03x\n",
423 GEN_EXCP_PRIVREG(ctx
);
428 #if defined(CONFIG_USER_ONLY)
429 #define spr_register(env, num, name, uea_read, uea_write, \
430 oea_read, oea_write, initial_value) \
432 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
434 static inline void _spr_register (CPUPPCState
*env
, int num
,
435 const unsigned char *name
,
436 void (*uea_read
)(void *opaque
, int sprn
),
437 void (*uea_write
)(void *opaque
, int sprn
),
438 target_ulong initial_value
)
440 static inline void spr_register (CPUPPCState
*env
, int num
,
441 const unsigned char *name
,
442 void (*uea_read
)(void *opaque
, int sprn
),
443 void (*uea_write
)(void *opaque
, int sprn
),
444 void (*oea_read
)(void *opaque
, int sprn
),
445 void (*oea_write
)(void *opaque
, int sprn
),
446 target_ulong initial_value
)
451 spr
= &env
->spr_cb
[num
];
452 if (spr
->name
!= NULL
||env
-> spr
[num
] != 0x00000000 ||
453 #if !defined(CONFIG_USER_ONLY)
454 spr
->oea_read
!= NULL
|| spr
->oea_write
!= NULL
||
456 spr
->uea_read
!= NULL
|| spr
->uea_write
!= NULL
) {
457 printf("Error: Trying to register SPR %d (%03x) twice !\n", num
, num
);
460 #if defined(PPC_DEBUG_SPR)
461 printf("*** register spr %d (%03x) %s val " ADDRX
"\n", num
, num
, name
,
465 spr
->uea_read
= uea_read
;
466 spr
->uea_write
= uea_write
;
467 #if !defined(CONFIG_USER_ONLY)
468 spr
->oea_read
= oea_read
;
469 spr
->oea_write
= oea_write
;
471 env
->spr
[num
] = initial_value
;
474 /* Generic PowerPC SPRs */
475 static void gen_spr_generic (CPUPPCState
*env
)
477 /* Integer processing */
478 spr_register(env
, SPR_XER
, "XER",
479 &spr_read_xer
, &spr_write_xer
,
480 &spr_read_xer
, &spr_write_xer
,
483 spr_register(env
, SPR_LR
, "LR",
484 &spr_read_lr
, &spr_write_lr
,
485 &spr_read_lr
, &spr_write_lr
,
487 spr_register(env
, SPR_CTR
, "CTR",
488 &spr_read_ctr
, &spr_write_ctr
,
489 &spr_read_ctr
, &spr_write_ctr
,
491 /* Interrupt processing */
492 spr_register(env
, SPR_SRR0
, "SRR0",
493 SPR_NOACCESS
, SPR_NOACCESS
,
494 &spr_read_generic
, &spr_write_generic
,
496 spr_register(env
, SPR_SRR1
, "SRR1",
497 SPR_NOACCESS
, SPR_NOACCESS
,
498 &spr_read_generic
, &spr_write_generic
,
500 /* Processor control */
501 spr_register(env
, SPR_SPRG0
, "SPRG0",
502 SPR_NOACCESS
, SPR_NOACCESS
,
503 &spr_read_generic
, &spr_write_generic
,
505 spr_register(env
, SPR_SPRG1
, "SPRG1",
506 SPR_NOACCESS
, SPR_NOACCESS
,
507 &spr_read_generic
, &spr_write_generic
,
509 spr_register(env
, SPR_SPRG2
, "SPRG2",
510 SPR_NOACCESS
, SPR_NOACCESS
,
511 &spr_read_generic
, &spr_write_generic
,
513 spr_register(env
, SPR_SPRG3
, "SPRG3",
514 SPR_NOACCESS
, SPR_NOACCESS
,
515 &spr_read_generic
, &spr_write_generic
,
519 /* SPR common to all non-embedded PowerPC, including 601 */
520 static void gen_spr_ne_601 (CPUPPCState
*env
)
522 /* Exception processing */
523 spr_register(env
, SPR_DSISR
, "DSISR",
524 SPR_NOACCESS
, SPR_NOACCESS
,
525 &spr_read_generic
, &spr_write_generic
,
527 spr_register(env
, SPR_DAR
, "DAR",
528 SPR_NOACCESS
, SPR_NOACCESS
,
529 &spr_read_generic
, &spr_write_generic
,
532 spr_register(env
, SPR_DECR
, "DECR",
533 SPR_NOACCESS
, SPR_NOACCESS
,
534 &spr_read_decr
, &spr_write_decr
,
536 /* Memory management */
537 spr_register(env
, SPR_SDR1
, "SDR1",
538 SPR_NOACCESS
, SPR_NOACCESS
,
539 &spr_read_sdr1
, &spr_write_sdr1
,
544 static void gen_low_BATs (CPUPPCState
*env
)
546 #if !defined(CONFIG_USER_ONLY)
547 spr_register(env
, SPR_IBAT0U
, "IBAT0U",
548 SPR_NOACCESS
, SPR_NOACCESS
,
549 &spr_read_ibat
, &spr_write_ibatu
,
551 spr_register(env
, SPR_IBAT0L
, "IBAT0L",
552 SPR_NOACCESS
, SPR_NOACCESS
,
553 &spr_read_ibat
, &spr_write_ibatl
,
555 spr_register(env
, SPR_IBAT1U
, "IBAT1U",
556 SPR_NOACCESS
, SPR_NOACCESS
,
557 &spr_read_ibat
, &spr_write_ibatu
,
559 spr_register(env
, SPR_IBAT1L
, "IBAT1L",
560 SPR_NOACCESS
, SPR_NOACCESS
,
561 &spr_read_ibat
, &spr_write_ibatl
,
563 spr_register(env
, SPR_IBAT2U
, "IBAT2U",
564 SPR_NOACCESS
, SPR_NOACCESS
,
565 &spr_read_ibat
, &spr_write_ibatu
,
567 spr_register(env
, SPR_IBAT2L
, "IBAT2L",
568 SPR_NOACCESS
, SPR_NOACCESS
,
569 &spr_read_ibat
, &spr_write_ibatl
,
571 spr_register(env
, SPR_IBAT3U
, "IBAT3U",
572 SPR_NOACCESS
, SPR_NOACCESS
,
573 &spr_read_ibat
, &spr_write_ibatu
,
575 spr_register(env
, SPR_IBAT3L
, "IBAT3L",
576 SPR_NOACCESS
, SPR_NOACCESS
,
577 &spr_read_ibat
, &spr_write_ibatl
,
579 spr_register(env
, SPR_DBAT0U
, "DBAT0U",
580 SPR_NOACCESS
, SPR_NOACCESS
,
581 &spr_read_dbat
, &spr_write_dbatu
,
583 spr_register(env
, SPR_DBAT0L
, "DBAT0L",
584 SPR_NOACCESS
, SPR_NOACCESS
,
585 &spr_read_dbat
, &spr_write_dbatl
,
587 spr_register(env
, SPR_DBAT1U
, "DBAT1U",
588 SPR_NOACCESS
, SPR_NOACCESS
,
589 &spr_read_dbat
, &spr_write_dbatu
,
591 spr_register(env
, SPR_DBAT1L
, "DBAT1L",
592 SPR_NOACCESS
, SPR_NOACCESS
,
593 &spr_read_dbat
, &spr_write_dbatl
,
595 spr_register(env
, SPR_DBAT2U
, "DBAT2U",
596 SPR_NOACCESS
, SPR_NOACCESS
,
597 &spr_read_dbat
, &spr_write_dbatu
,
599 spr_register(env
, SPR_DBAT2L
, "DBAT2L",
600 SPR_NOACCESS
, SPR_NOACCESS
,
601 &spr_read_dbat
, &spr_write_dbatl
,
603 spr_register(env
, SPR_DBAT3U
, "DBAT3U",
604 SPR_NOACCESS
, SPR_NOACCESS
,
605 &spr_read_dbat
, &spr_write_dbatu
,
607 spr_register(env
, SPR_DBAT3L
, "DBAT3L",
608 SPR_NOACCESS
, SPR_NOACCESS
,
609 &spr_read_dbat
, &spr_write_dbatl
,
616 static void gen_high_BATs (CPUPPCState
*env
)
618 #if !defined(CONFIG_USER_ONLY)
619 spr_register(env
, SPR_IBAT4U
, "IBAT4U",
620 SPR_NOACCESS
, SPR_NOACCESS
,
621 &spr_read_ibat_h
, &spr_write_ibatu_h
,
623 spr_register(env
, SPR_IBAT4L
, "IBAT4L",
624 SPR_NOACCESS
, SPR_NOACCESS
,
625 &spr_read_ibat_h
, &spr_write_ibatl_h
,
627 spr_register(env
, SPR_IBAT5U
, "IBAT5U",
628 SPR_NOACCESS
, SPR_NOACCESS
,
629 &spr_read_ibat_h
, &spr_write_ibatu_h
,
631 spr_register(env
, SPR_IBAT5L
, "IBAT5L",
632 SPR_NOACCESS
, SPR_NOACCESS
,
633 &spr_read_ibat_h
, &spr_write_ibatl_h
,
635 spr_register(env
, SPR_IBAT6U
, "IBAT6U",
636 SPR_NOACCESS
, SPR_NOACCESS
,
637 &spr_read_ibat_h
, &spr_write_ibatu_h
,
639 spr_register(env
, SPR_IBAT6L
, "IBAT6L",
640 SPR_NOACCESS
, SPR_NOACCESS
,
641 &spr_read_ibat_h
, &spr_write_ibatl_h
,
643 spr_register(env
, SPR_IBAT7U
, "IBAT7U",
644 SPR_NOACCESS
, SPR_NOACCESS
,
645 &spr_read_ibat_h
, &spr_write_ibatu_h
,
647 spr_register(env
, SPR_IBAT7L
, "IBAT7L",
648 SPR_NOACCESS
, SPR_NOACCESS
,
649 &spr_read_ibat_h
, &spr_write_ibatl_h
,
651 spr_register(env
, SPR_DBAT4U
, "DBAT4U",
652 SPR_NOACCESS
, SPR_NOACCESS
,
653 &spr_read_dbat_h
, &spr_write_dbatu_h
,
655 spr_register(env
, SPR_DBAT4L
, "DBAT4L",
656 SPR_NOACCESS
, SPR_NOACCESS
,
657 &spr_read_dbat_h
, &spr_write_dbatl_h
,
659 spr_register(env
, SPR_DBAT5U
, "DBAT5U",
660 SPR_NOACCESS
, SPR_NOACCESS
,
661 &spr_read_dbat_h
, &spr_write_dbatu_h
,
663 spr_register(env
, SPR_DBAT5L
, "DBAT5L",
664 SPR_NOACCESS
, SPR_NOACCESS
,
665 &spr_read_dbat_h
, &spr_write_dbatl_h
,
667 spr_register(env
, SPR_DBAT6U
, "DBAT6U",
668 SPR_NOACCESS
, SPR_NOACCESS
,
669 &spr_read_dbat_h
, &spr_write_dbatu_h
,
671 spr_register(env
, SPR_DBAT6L
, "DBAT6L",
672 SPR_NOACCESS
, SPR_NOACCESS
,
673 &spr_read_dbat_h
, &spr_write_dbatl_h
,
675 spr_register(env
, SPR_DBAT7U
, "DBAT7U",
676 SPR_NOACCESS
, SPR_NOACCESS
,
677 &spr_read_dbat_h
, &spr_write_dbatu_h
,
679 spr_register(env
, SPR_DBAT7L
, "DBAT7L",
680 SPR_NOACCESS
, SPR_NOACCESS
,
681 &spr_read_dbat_h
, &spr_write_dbatl_h
,
687 /* Generic PowerPC time base */
688 static void gen_tbl (CPUPPCState
*env
)
690 spr_register(env
, SPR_VTBL
, "TBL",
691 &spr_read_tbl
, SPR_NOACCESS
,
692 &spr_read_tbl
, SPR_NOACCESS
,
694 spr_register(env
, SPR_TBL
, "TBL",
695 SPR_NOACCESS
, SPR_NOACCESS
,
696 SPR_NOACCESS
, &spr_write_tbl
,
698 spr_register(env
, SPR_VTBU
, "TBU",
699 &spr_read_tbu
, SPR_NOACCESS
,
700 &spr_read_tbu
, SPR_NOACCESS
,
702 spr_register(env
, SPR_TBU
, "TBU",
703 SPR_NOACCESS
, SPR_NOACCESS
,
704 SPR_NOACCESS
, &spr_write_tbu
,
708 /* Softare table search registers */
709 static void gen_6xx_7xx_soft_tlb (CPUPPCState
*env
, int nb_tlbs
, int nb_ways
)
711 #if !defined(CONFIG_USER_ONLY)
712 env
->nb_tlb
= nb_tlbs
;
713 env
->nb_ways
= nb_ways
;
715 spr_register(env
, SPR_DMISS
, "DMISS",
716 SPR_NOACCESS
, SPR_NOACCESS
,
717 &spr_read_generic
, SPR_NOACCESS
,
719 spr_register(env
, SPR_DCMP
, "DCMP",
720 SPR_NOACCESS
, SPR_NOACCESS
,
721 &spr_read_generic
, SPR_NOACCESS
,
723 spr_register(env
, SPR_HASH1
, "HASH1",
724 SPR_NOACCESS
, SPR_NOACCESS
,
725 &spr_read_generic
, SPR_NOACCESS
,
727 spr_register(env
, SPR_HASH2
, "HASH2",
728 SPR_NOACCESS
, SPR_NOACCESS
,
729 &spr_read_generic
, SPR_NOACCESS
,
731 spr_register(env
, SPR_IMISS
, "IMISS",
732 SPR_NOACCESS
, SPR_NOACCESS
,
733 &spr_read_generic
, SPR_NOACCESS
,
735 spr_register(env
, SPR_ICMP
, "ICMP",
736 SPR_NOACCESS
, SPR_NOACCESS
,
737 &spr_read_generic
, SPR_NOACCESS
,
739 spr_register(env
, SPR_RPA
, "RPA",
740 SPR_NOACCESS
, SPR_NOACCESS
,
741 &spr_read_generic
, &spr_write_generic
,
746 /* SPR common to MPC755 and G2 */
747 static void gen_spr_G2_755 (CPUPPCState
*env
)
750 spr_register(env
, SPR_SPRG4
, "SPRG4",
751 SPR_NOACCESS
, SPR_NOACCESS
,
752 &spr_read_generic
, &spr_write_generic
,
754 spr_register(env
, SPR_SPRG5
, "SPRG5",
755 SPR_NOACCESS
, SPR_NOACCESS
,
756 &spr_read_generic
, &spr_write_generic
,
758 spr_register(env
, SPR_SPRG6
, "SPRG6",
759 SPR_NOACCESS
, SPR_NOACCESS
,
760 &spr_read_generic
, &spr_write_generic
,
762 spr_register(env
, SPR_SPRG7
, "SPRG7",
763 SPR_NOACCESS
, SPR_NOACCESS
,
764 &spr_read_generic
, &spr_write_generic
,
766 /* External access control */
767 /* XXX : not implemented */
768 spr_register(env
, SPR_EAR
, "EAR",
769 SPR_NOACCESS
, SPR_NOACCESS
,
770 &spr_read_generic
, &spr_write_generic
,
774 /* SPR common to all 7xx PowerPC implementations */
775 static void gen_spr_7xx (CPUPPCState
*env
)
778 /* XXX : not implemented */
779 spr_register(env
, SPR_DABR
, "DABR",
780 SPR_NOACCESS
, SPR_NOACCESS
,
781 &spr_read_generic
, &spr_write_generic
,
783 /* XXX : not implemented */
784 spr_register(env
, SPR_IABR
, "IABR",
785 SPR_NOACCESS
, SPR_NOACCESS
,
786 &spr_read_generic
, &spr_write_generic
,
788 /* Cache management */
789 /* XXX : not implemented */
790 spr_register(env
, SPR_ICTC
, "ICTC",
791 SPR_NOACCESS
, SPR_NOACCESS
,
792 &spr_read_generic
, &spr_write_generic
,
794 /* XXX : not implemented */
795 spr_register(env
, SPR_L2CR
, "L2CR",
796 SPR_NOACCESS
, SPR_NOACCESS
,
797 &spr_read_generic
, &spr_write_generic
,
799 /* Performance monitors */
800 /* XXX : not implemented */
801 spr_register(env
, SPR_MMCR0
, "MMCR0",
802 SPR_NOACCESS
, SPR_NOACCESS
,
803 &spr_read_generic
, &spr_write_generic
,
805 /* XXX : not implemented */
806 spr_register(env
, SPR_MMCR1
, "MMCR1",
807 SPR_NOACCESS
, SPR_NOACCESS
,
808 &spr_read_generic
, &spr_write_generic
,
810 /* XXX : not implemented */
811 spr_register(env
, SPR_PMC1
, "PMC1",
812 SPR_NOACCESS
, SPR_NOACCESS
,
813 &spr_read_generic
, &spr_write_generic
,
815 /* XXX : not implemented */
816 spr_register(env
, SPR_PMC2
, "PMC2",
817 SPR_NOACCESS
, SPR_NOACCESS
,
818 &spr_read_generic
, &spr_write_generic
,
820 /* XXX : not implemented */
821 spr_register(env
, SPR_PMC3
, "PMC3",
822 SPR_NOACCESS
, SPR_NOACCESS
,
823 &spr_read_generic
, &spr_write_generic
,
825 /* XXX : not implemented */
826 spr_register(env
, SPR_PMC4
, "PMC4",
827 SPR_NOACCESS
, SPR_NOACCESS
,
828 &spr_read_generic
, &spr_write_generic
,
830 /* XXX : not implemented */
831 spr_register(env
, SPR_SIAR
, "SIAR",
832 SPR_NOACCESS
, SPR_NOACCESS
,
833 &spr_read_generic
, SPR_NOACCESS
,
835 /* XXX : not implemented */
836 spr_register(env
, SPR_UMMCR0
, "UMMCR0",
837 &spr_read_ureg
, SPR_NOACCESS
,
838 &spr_read_ureg
, SPR_NOACCESS
,
840 /* XXX : not implemented */
841 spr_register(env
, SPR_UMMCR1
, "UMMCR1",
842 &spr_read_ureg
, SPR_NOACCESS
,
843 &spr_read_ureg
, SPR_NOACCESS
,
845 /* XXX : not implemented */
846 spr_register(env
, SPR_UPMC1
, "UPMC1",
847 &spr_read_ureg
, SPR_NOACCESS
,
848 &spr_read_ureg
, SPR_NOACCESS
,
850 /* XXX : not implemented */
851 spr_register(env
, SPR_UPMC2
, "UPMC2",
852 &spr_read_ureg
, SPR_NOACCESS
,
853 &spr_read_ureg
, SPR_NOACCESS
,
855 /* XXX : not implemented */
856 spr_register(env
, SPR_UPMC3
, "UPMC3",
857 &spr_read_ureg
, SPR_NOACCESS
,
858 &spr_read_ureg
, SPR_NOACCESS
,
860 /* XXX : not implemented */
861 spr_register(env
, SPR_UPMC4
, "UPMC4",
862 &spr_read_ureg
, SPR_NOACCESS
,
863 &spr_read_ureg
, SPR_NOACCESS
,
865 /* XXX : not implemented */
866 spr_register(env
, SPR_USIAR
, "USIAR",
867 &spr_read_ureg
, SPR_NOACCESS
,
868 &spr_read_ureg
, SPR_NOACCESS
,
870 /* External access control */
871 /* XXX : not implemented */
872 spr_register(env
, SPR_EAR
, "EAR",
873 SPR_NOACCESS
, SPR_NOACCESS
,
874 &spr_read_generic
, &spr_write_generic
,
878 static void gen_spr_thrm (CPUPPCState
*env
)
880 /* Thermal management */
881 /* XXX : not implemented */
882 spr_register(env
, SPR_THRM1
, "THRM1",
883 SPR_NOACCESS
, SPR_NOACCESS
,
884 &spr_read_generic
, &spr_write_generic
,
886 /* XXX : not implemented */
887 spr_register(env
, SPR_THRM2
, "THRM2",
888 SPR_NOACCESS
, SPR_NOACCESS
,
889 &spr_read_generic
, &spr_write_generic
,
891 /* XXX : not implemented */
892 spr_register(env
, SPR_THRM3
, "THRM3",
893 SPR_NOACCESS
, SPR_NOACCESS
,
894 &spr_read_generic
, &spr_write_generic
,
898 /* SPR specific to PowerPC 604 implementation */
899 static void gen_spr_604 (CPUPPCState
*env
)
901 /* Processor identification */
902 spr_register(env
, SPR_PIR
, "PIR",
903 SPR_NOACCESS
, SPR_NOACCESS
,
904 &spr_read_generic
, &spr_write_pir
,
907 /* XXX : not implemented */
908 spr_register(env
, SPR_IABR
, "IABR",
909 SPR_NOACCESS
, SPR_NOACCESS
,
910 &spr_read_generic
, &spr_write_generic
,
912 /* XXX : not implemented */
913 spr_register(env
, SPR_DABR
, "DABR",
914 SPR_NOACCESS
, SPR_NOACCESS
,
915 &spr_read_generic
, &spr_write_generic
,
917 /* Performance counters */
918 /* XXX : not implemented */
919 spr_register(env
, SPR_MMCR0
, "MMCR0",
920 SPR_NOACCESS
, SPR_NOACCESS
,
921 &spr_read_generic
, &spr_write_generic
,
923 /* XXX : not implemented */
924 spr_register(env
, SPR_MMCR1
, "MMCR1",
925 SPR_NOACCESS
, SPR_NOACCESS
,
926 &spr_read_generic
, &spr_write_generic
,
928 /* XXX : not implemented */
929 spr_register(env
, SPR_PMC1
, "PMC1",
930 SPR_NOACCESS
, SPR_NOACCESS
,
931 &spr_read_generic
, &spr_write_generic
,
933 /* XXX : not implemented */
934 spr_register(env
, SPR_PMC2
, "PMC2",
935 SPR_NOACCESS
, SPR_NOACCESS
,
936 &spr_read_generic
, &spr_write_generic
,
938 /* XXX : not implemented */
939 spr_register(env
, SPR_PMC3
, "PMC3",
940 SPR_NOACCESS
, SPR_NOACCESS
,
941 &spr_read_generic
, &spr_write_generic
,
943 /* XXX : not implemented */
944 spr_register(env
, SPR_PMC4
, "PMC4",
945 SPR_NOACCESS
, SPR_NOACCESS
,
946 &spr_read_generic
, &spr_write_generic
,
948 /* XXX : not implemented */
949 spr_register(env
, SPR_SIAR
, "SIAR",
950 SPR_NOACCESS
, SPR_NOACCESS
,
951 &spr_read_generic
, SPR_NOACCESS
,
953 /* XXX : not implemented */
954 spr_register(env
, SPR_SDA
, "SDA",
955 SPR_NOACCESS
, SPR_NOACCESS
,
956 &spr_read_generic
, SPR_NOACCESS
,
958 /* External access control */
959 /* XXX : not implemented */
960 spr_register(env
, SPR_EAR
, "EAR",
961 SPR_NOACCESS
, SPR_NOACCESS
,
962 &spr_read_generic
, &spr_write_generic
,
966 /* SPR specific to PowerPC 603 implementation */
967 static void gen_spr_603 (CPUPPCState
*env
)
969 /* External access control */
970 /* XXX : not implemented */
971 spr_register(env
, SPR_EAR
, "EAR",
972 SPR_NOACCESS
, SPR_NOACCESS
,
973 &spr_read_generic
, &spr_write_generic
,
977 /* SPR specific to PowerPC G2 implementation */
978 static void gen_spr_G2 (CPUPPCState
*env
)
980 /* Memory base address */
982 /* XXX : not implemented */
983 spr_register(env
, SPR_MBAR
, "MBAR",
984 SPR_NOACCESS
, SPR_NOACCESS
,
985 &spr_read_generic
, &spr_write_generic
,
987 /* System version register */
989 /* XXX : TODO: initialize it to an appropriate value */
990 spr_register(env
, SPR_SVR
, "SVR",
991 SPR_NOACCESS
, SPR_NOACCESS
,
992 &spr_read_generic
, SPR_NOACCESS
,
994 /* Exception processing */
995 spr_register(env
, SPR_BOOKE_CSRR0
, "CSRR0",
996 SPR_NOACCESS
, SPR_NOACCESS
,
997 &spr_read_generic
, &spr_write_generic
,
999 spr_register(env
, SPR_BOOKE_CSRR1
, "CSRR1",
1000 SPR_NOACCESS
, SPR_NOACCESS
,
1001 &spr_read_generic
, &spr_write_generic
,
1004 /* XXX : not implemented */
1005 spr_register(env
, SPR_DABR
, "DABR",
1006 SPR_NOACCESS
, SPR_NOACCESS
,
1007 &spr_read_generic
, &spr_write_generic
,
1009 /* XXX : not implemented */
1010 spr_register(env
, SPR_DABR2
, "DABR2",
1011 SPR_NOACCESS
, SPR_NOACCESS
,
1012 &spr_read_generic
, &spr_write_generic
,
1014 /* XXX : not implemented */
1015 spr_register(env
, SPR_IABR
, "IABR",
1016 SPR_NOACCESS
, SPR_NOACCESS
,
1017 &spr_read_generic
, &spr_write_generic
,
1019 /* XXX : not implemented */
1020 spr_register(env
, SPR_IABR2
, "IABR2",
1021 SPR_NOACCESS
, SPR_NOACCESS
,
1022 &spr_read_generic
, &spr_write_generic
,
1024 /* XXX : not implemented */
1025 spr_register(env
, SPR_IBCR
, "IBCR",
1026 SPR_NOACCESS
, SPR_NOACCESS
,
1027 &spr_read_generic
, &spr_write_generic
,
1029 /* XXX : not implemented */
1030 spr_register(env
, SPR_DBCR
, "DBCR",
1031 SPR_NOACCESS
, SPR_NOACCESS
,
1032 &spr_read_generic
, &spr_write_generic
,
1036 /* SPR specific to PowerPC 602 implementation */
1037 static void gen_spr_602 (CPUPPCState
*env
)
1040 /* XXX : not implemented */
1041 spr_register(env
, SPR_SER
, "SER",
1042 SPR_NOACCESS
, SPR_NOACCESS
,
1043 &spr_read_generic
, &spr_write_generic
,
1045 /* XXX : not implemented */
1046 spr_register(env
, SPR_SEBR
, "SEBR",
1047 SPR_NOACCESS
, SPR_NOACCESS
,
1048 &spr_read_generic
, &spr_write_generic
,
1050 /* XXX : not implemented */
1051 spr_register(env
, SPR_ESASRR
, "ESASRR",
1052 SPR_NOACCESS
, SPR_NOACCESS
,
1053 &spr_read_generic
, &spr_write_generic
,
1055 /* Floating point status */
1056 /* XXX : not implemented */
1057 spr_register(env
, SPR_SP
, "SP",
1058 SPR_NOACCESS
, SPR_NOACCESS
,
1059 &spr_read_generic
, &spr_write_generic
,
1061 /* XXX : not implemented */
1062 spr_register(env
, SPR_LT
, "LT",
1063 SPR_NOACCESS
, SPR_NOACCESS
,
1064 &spr_read_generic
, &spr_write_generic
,
1066 /* Watchdog timer */
1067 /* XXX : not implemented */
1068 spr_register(env
, SPR_TCR
, "TCR",
1069 SPR_NOACCESS
, SPR_NOACCESS
,
1070 &spr_read_generic
, &spr_write_generic
,
1072 /* Interrupt base */
1073 spr_register(env
, SPR_IBR
, "IBR",
1074 SPR_NOACCESS
, SPR_NOACCESS
,
1075 &spr_read_generic
, &spr_write_generic
,
1077 /* XXX : not implemented */
1078 spr_register(env
, SPR_IABR
, "IABR",
1079 SPR_NOACCESS
, SPR_NOACCESS
,
1080 &spr_read_generic
, &spr_write_generic
,
1084 /* SPR specific to PowerPC 601 implementation */
1085 static void gen_spr_601 (CPUPPCState
*env
)
1087 /* Multiplication/division register */
1089 spr_register(env
, SPR_MQ
, "MQ",
1090 &spr_read_generic
, &spr_write_generic
,
1091 &spr_read_generic
, &spr_write_generic
,
1094 spr_register(env
, SPR_601_RTCU
, "RTCU",
1095 SPR_NOACCESS
, SPR_NOACCESS
,
1096 SPR_NOACCESS
, &spr_write_601_rtcu
,
1098 spr_register(env
, SPR_601_VRTCU
, "RTCU",
1099 &spr_read_601_rtcu
, SPR_NOACCESS
,
1100 &spr_read_601_rtcu
, SPR_NOACCESS
,
1102 spr_register(env
, SPR_601_RTCL
, "RTCL",
1103 SPR_NOACCESS
, SPR_NOACCESS
,
1104 SPR_NOACCESS
, &spr_write_601_rtcl
,
1106 spr_register(env
, SPR_601_VRTCL
, "RTCL",
1107 &spr_read_601_rtcl
, SPR_NOACCESS
,
1108 &spr_read_601_rtcl
, SPR_NOACCESS
,
1112 spr_register(env
, SPR_601_UDECR
, "UDECR",
1113 &spr_read_decr
, SPR_NOACCESS
,
1114 &spr_read_decr
, SPR_NOACCESS
,
1117 /* External access control */
1118 /* XXX : not implemented */
1119 spr_register(env
, SPR_EAR
, "EAR",
1120 SPR_NOACCESS
, SPR_NOACCESS
,
1121 &spr_read_generic
, &spr_write_generic
,
1123 /* Memory management */
1124 #if !defined(CONFIG_USER_ONLY)
1125 spr_register(env
, SPR_IBAT0U
, "IBAT0U",
1126 SPR_NOACCESS
, SPR_NOACCESS
,
1127 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1129 spr_register(env
, SPR_IBAT0L
, "IBAT0L",
1130 SPR_NOACCESS
, SPR_NOACCESS
,
1131 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1133 spr_register(env
, SPR_IBAT1U
, "IBAT1U",
1134 SPR_NOACCESS
, SPR_NOACCESS
,
1135 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1137 spr_register(env
, SPR_IBAT1L
, "IBAT1L",
1138 SPR_NOACCESS
, SPR_NOACCESS
,
1139 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1141 spr_register(env
, SPR_IBAT2U
, "IBAT2U",
1142 SPR_NOACCESS
, SPR_NOACCESS
,
1143 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1145 spr_register(env
, SPR_IBAT2L
, "IBAT2L",
1146 SPR_NOACCESS
, SPR_NOACCESS
,
1147 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1149 spr_register(env
, SPR_IBAT3U
, "IBAT3U",
1150 SPR_NOACCESS
, SPR_NOACCESS
,
1151 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1153 spr_register(env
, SPR_IBAT3L
, "IBAT3L",
1154 SPR_NOACCESS
, SPR_NOACCESS
,
1155 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1161 static void gen_spr_74xx (CPUPPCState
*env
)
1163 /* Processor identification */
1164 spr_register(env
, SPR_PIR
, "PIR",
1165 SPR_NOACCESS
, SPR_NOACCESS
,
1166 &spr_read_generic
, &spr_write_pir
,
1168 /* XXX : not implemented */
1169 spr_register(env
, SPR_MMCR2
, "MMCR2",
1170 SPR_NOACCESS
, SPR_NOACCESS
,
1171 &spr_read_generic
, &spr_write_generic
,
1173 /* XXX : not implemented */
1174 spr_register(env
, SPR_UMMCR2
, "UMMCR2",
1175 &spr_read_ureg
, SPR_NOACCESS
,
1176 &spr_read_ureg
, SPR_NOACCESS
,
1178 /* XXX: not implemented */
1179 spr_register(env
, SPR_BAMR
, "BAMR",
1180 SPR_NOACCESS
, SPR_NOACCESS
,
1181 &spr_read_generic
, &spr_write_generic
,
1183 /* XXX : not implemented */
1184 spr_register(env
, SPR_UBAMR
, "UBAMR",
1185 &spr_read_ureg
, SPR_NOACCESS
,
1186 &spr_read_ureg
, SPR_NOACCESS
,
1188 /* XXX : not implemented */
1189 spr_register(env
, SPR_MSSCR0
, "MSSCR0",
1190 SPR_NOACCESS
, SPR_NOACCESS
,
1191 &spr_read_generic
, &spr_write_generic
,
1193 /* Hardware implementation registers */
1194 /* XXX : not implemented */
1195 spr_register(env
, SPR_HID0
, "HID0",
1196 SPR_NOACCESS
, SPR_NOACCESS
,
1197 &spr_read_generic
, &spr_write_generic
,
1199 /* XXX : not implemented */
1200 spr_register(env
, SPR_HID1
, "HID1",
1201 SPR_NOACCESS
, SPR_NOACCESS
,
1202 &spr_read_generic
, &spr_write_generic
,
1205 spr_register(env
, SPR_VRSAVE
, "VRSAVE",
1206 &spr_read_generic
, &spr_write_generic
,
1207 &spr_read_generic
, &spr_write_generic
,
1211 static void gen_l3_ctrl (CPUPPCState
*env
)
1214 /* XXX : not implemented */
1215 spr_register(env
, SPR_L3CR
, "L3CR",
1216 SPR_NOACCESS
, SPR_NOACCESS
,
1217 &spr_read_generic
, &spr_write_generic
,
1220 /* XXX : not implemented */
1221 spr_register(env
, SPR_L3ITCR0
, "L3ITCR0",
1222 SPR_NOACCESS
, SPR_NOACCESS
,
1223 &spr_read_generic
, &spr_write_generic
,
1226 /* XXX : not implemented */
1227 spr_register(env
, SPR_L3ITCR1
, "L3ITCR1",
1228 SPR_NOACCESS
, SPR_NOACCESS
,
1229 &spr_read_generic
, &spr_write_generic
,
1232 /* XXX : not implemented */
1233 spr_register(env
, SPR_L3ITCR2
, "L3ITCR2",
1234 SPR_NOACCESS
, SPR_NOACCESS
,
1235 &spr_read_generic
, &spr_write_generic
,
1238 /* XXX : not implemented */
1239 spr_register(env
, SPR_L3ITCR3
, "L3ITCR3",
1240 SPR_NOACCESS
, SPR_NOACCESS
,
1241 &spr_read_generic
, &spr_write_generic
,
1244 /* XXX : not implemented */
1245 spr_register(env
, SPR_L3OHCR
, "L3OHCR",
1246 SPR_NOACCESS
, SPR_NOACCESS
,
1247 &spr_read_generic
, &spr_write_generic
,
1250 /* XXX : not implemented */
1251 spr_register(env
, SPR_L3PM
, "L3PM",
1252 SPR_NOACCESS
, SPR_NOACCESS
,
1253 &spr_read_generic
, &spr_write_generic
,
1257 static void gen_74xx_soft_tlb (CPUPPCState
*env
, int nb_tlbs
, int nb_ways
)
1259 #if !defined(CONFIG_USER_ONLY)
1260 env
->nb_tlb
= nb_tlbs
;
1261 env
->nb_ways
= nb_ways
;
1263 /* XXX : not implemented */
1264 spr_register(env
, SPR_PTEHI
, "PTEHI",
1265 SPR_NOACCESS
, SPR_NOACCESS
,
1266 &spr_read_generic
, &spr_write_generic
,
1268 /* XXX : not implemented */
1269 spr_register(env
, SPR_PTELO
, "PTELO",
1270 SPR_NOACCESS
, SPR_NOACCESS
,
1271 &spr_read_generic
, &spr_write_generic
,
1273 /* XXX : not implemented */
1274 spr_register(env
, SPR_TLBMISS
, "TLBMISS",
1275 SPR_NOACCESS
, SPR_NOACCESS
,
1276 &spr_read_generic
, &spr_write_generic
,
1281 /* PowerPC BookE SPR */
1282 static void gen_spr_BookE (CPUPPCState
*env
)
1284 /* Processor identification */
1285 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
1286 SPR_NOACCESS
, SPR_NOACCESS
,
1287 &spr_read_generic
, &spr_write_pir
,
1289 /* Interrupt processing */
1290 spr_register(env
, SPR_BOOKE_CSRR0
, "CSRR0",
1291 SPR_NOACCESS
, SPR_NOACCESS
,
1292 &spr_read_generic
, &spr_write_generic
,
1294 spr_register(env
, SPR_BOOKE_CSRR1
, "CSRR1",
1295 SPR_NOACCESS
, SPR_NOACCESS
,
1296 &spr_read_generic
, &spr_write_generic
,
1299 spr_register(env
, SPR_BOOKE_DSRR0
, "DSRR0",
1300 SPR_NOACCESS
, SPR_NOACCESS
,
1301 &spr_read_generic
, &spr_write_generic
,
1303 spr_register(env
, SPR_BOOKE_DSRR1
, "DSRR1",
1304 SPR_NOACCESS
, SPR_NOACCESS
,
1305 &spr_read_generic
, &spr_write_generic
,
1309 /* XXX : not implemented */
1310 spr_register(env
, SPR_BOOKE_IAC1
, "IAC1",
1311 SPR_NOACCESS
, SPR_NOACCESS
,
1312 &spr_read_generic
, &spr_write_generic
,
1314 /* XXX : not implemented */
1315 spr_register(env
, SPR_BOOKE_IAC2
, "IAC2",
1316 SPR_NOACCESS
, SPR_NOACCESS
,
1317 &spr_read_generic
, &spr_write_generic
,
1319 /* XXX : not implemented */
1320 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
1321 SPR_NOACCESS
, SPR_NOACCESS
,
1322 &spr_read_generic
, &spr_write_generic
,
1324 /* XXX : not implemented */
1325 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
1326 SPR_NOACCESS
, SPR_NOACCESS
,
1327 &spr_read_generic
, &spr_write_generic
,
1329 /* XXX : not implemented */
1330 spr_register(env
, SPR_BOOKE_DAC1
, "DAC1",
1331 SPR_NOACCESS
, SPR_NOACCESS
,
1332 &spr_read_generic
, &spr_write_generic
,
1334 /* XXX : not implemented */
1335 spr_register(env
, SPR_BOOKE_DAC2
, "DAC2",
1336 SPR_NOACCESS
, SPR_NOACCESS
,
1337 &spr_read_generic
, &spr_write_generic
,
1339 /* XXX : not implemented */
1340 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
1341 SPR_NOACCESS
, SPR_NOACCESS
,
1342 &spr_read_generic
, &spr_write_generic
,
1344 /* XXX : not implemented */
1345 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
1346 SPR_NOACCESS
, SPR_NOACCESS
,
1347 &spr_read_generic
, &spr_write_generic
,
1349 /* XXX : not implemented */
1350 spr_register(env
, SPR_BOOKE_DBCR0
, "DBCR0",
1351 SPR_NOACCESS
, SPR_NOACCESS
,
1352 &spr_read_generic
, &spr_write_generic
,
1354 /* XXX : not implemented */
1355 spr_register(env
, SPR_BOOKE_DBCR1
, "DBCR1",
1356 SPR_NOACCESS
, SPR_NOACCESS
,
1357 &spr_read_generic
, &spr_write_generic
,
1359 /* XXX : not implemented */
1360 spr_register(env
, SPR_BOOKE_DBCR2
, "DBCR2",
1361 SPR_NOACCESS
, SPR_NOACCESS
,
1362 &spr_read_generic
, &spr_write_generic
,
1364 /* XXX : not implemented */
1365 spr_register(env
, SPR_BOOKE_DBSR
, "DBSR",
1366 SPR_NOACCESS
, SPR_NOACCESS
,
1367 &spr_read_generic
, &spr_write_clear
,
1369 spr_register(env
, SPR_BOOKE_DEAR
, "DEAR",
1370 SPR_NOACCESS
, SPR_NOACCESS
,
1371 &spr_read_generic
, &spr_write_generic
,
1373 spr_register(env
, SPR_BOOKE_ESR
, "ESR",
1374 SPR_NOACCESS
, SPR_NOACCESS
,
1375 &spr_read_generic
, &spr_write_generic
,
1377 spr_register(env
, SPR_BOOKE_IVPR
, "IVPR",
1378 SPR_NOACCESS
, SPR_NOACCESS
,
1379 &spr_read_generic
, &spr_write_excp_prefix
,
1381 /* Exception vectors */
1382 spr_register(env
, SPR_BOOKE_IVOR0
, "IVOR0",
1383 SPR_NOACCESS
, SPR_NOACCESS
,
1384 &spr_read_generic
, &spr_write_excp_vector
,
1386 spr_register(env
, SPR_BOOKE_IVOR1
, "IVOR1",
1387 SPR_NOACCESS
, SPR_NOACCESS
,
1388 &spr_read_generic
, &spr_write_excp_vector
,
1390 spr_register(env
, SPR_BOOKE_IVOR2
, "IVOR2",
1391 SPR_NOACCESS
, SPR_NOACCESS
,
1392 &spr_read_generic
, &spr_write_excp_vector
,
1394 spr_register(env
, SPR_BOOKE_IVOR3
, "IVOR3",
1395 SPR_NOACCESS
, SPR_NOACCESS
,
1396 &spr_read_generic
, &spr_write_excp_vector
,
1398 spr_register(env
, SPR_BOOKE_IVOR4
, "IVOR4",
1399 SPR_NOACCESS
, SPR_NOACCESS
,
1400 &spr_read_generic
, &spr_write_excp_vector
,
1402 spr_register(env
, SPR_BOOKE_IVOR5
, "IVOR5",
1403 SPR_NOACCESS
, SPR_NOACCESS
,
1404 &spr_read_generic
, &spr_write_excp_vector
,
1406 spr_register(env
, SPR_BOOKE_IVOR6
, "IVOR6",
1407 SPR_NOACCESS
, SPR_NOACCESS
,
1408 &spr_read_generic
, &spr_write_excp_vector
,
1410 spr_register(env
, SPR_BOOKE_IVOR7
, "IVOR7",
1411 SPR_NOACCESS
, SPR_NOACCESS
,
1412 &spr_read_generic
, &spr_write_excp_vector
,
1414 spr_register(env
, SPR_BOOKE_IVOR8
, "IVOR8",
1415 SPR_NOACCESS
, SPR_NOACCESS
,
1416 &spr_read_generic
, &spr_write_excp_vector
,
1418 spr_register(env
, SPR_BOOKE_IVOR9
, "IVOR9",
1419 SPR_NOACCESS
, SPR_NOACCESS
,
1420 &spr_read_generic
, &spr_write_excp_vector
,
1422 spr_register(env
, SPR_BOOKE_IVOR10
, "IVOR10",
1423 SPR_NOACCESS
, SPR_NOACCESS
,
1424 &spr_read_generic
, &spr_write_excp_vector
,
1426 spr_register(env
, SPR_BOOKE_IVOR11
, "IVOR11",
1427 SPR_NOACCESS
, SPR_NOACCESS
,
1428 &spr_read_generic
, &spr_write_excp_vector
,
1430 spr_register(env
, SPR_BOOKE_IVOR12
, "IVOR12",
1431 SPR_NOACCESS
, SPR_NOACCESS
,
1432 &spr_read_generic
, &spr_write_excp_vector
,
1434 spr_register(env
, SPR_BOOKE_IVOR13
, "IVOR13",
1435 SPR_NOACCESS
, SPR_NOACCESS
,
1436 &spr_read_generic
, &spr_write_excp_vector
,
1438 spr_register(env
, SPR_BOOKE_IVOR14
, "IVOR14",
1439 SPR_NOACCESS
, SPR_NOACCESS
,
1440 &spr_read_generic
, &spr_write_excp_vector
,
1442 spr_register(env
, SPR_BOOKE_IVOR15
, "IVOR15",
1443 SPR_NOACCESS
, SPR_NOACCESS
,
1444 &spr_read_generic
, &spr_write_excp_vector
,
1447 spr_register(env
, SPR_BOOKE_IVOR32
, "IVOR32",
1448 SPR_NOACCESS
, SPR_NOACCESS
,
1449 &spr_read_generic
, &spr_write_excp_vector
,
1451 spr_register(env
, SPR_BOOKE_IVOR33
, "IVOR33",
1452 SPR_NOACCESS
, SPR_NOACCESS
,
1453 &spr_read_generic
, &spr_write_excp_vector
,
1455 spr_register(env
, SPR_BOOKE_IVOR34
, "IVOR34",
1456 SPR_NOACCESS
, SPR_NOACCESS
,
1457 &spr_read_generic
, &spr_write_excp_vector
,
1459 spr_register(env
, SPR_BOOKE_IVOR35
, "IVOR35",
1460 SPR_NOACCESS
, SPR_NOACCESS
,
1461 &spr_read_generic
, &spr_write_excp_vector
,
1463 spr_register(env
, SPR_BOOKE_IVOR36
, "IVOR36",
1464 SPR_NOACCESS
, SPR_NOACCESS
,
1465 &spr_read_generic
, &spr_write_excp_vector
,
1467 spr_register(env
, SPR_BOOKE_IVOR37
, "IVOR37",
1468 SPR_NOACCESS
, SPR_NOACCESS
,
1469 &spr_read_generic
, &spr_write_excp_vector
,
1472 spr_register(env
, SPR_BOOKE_PID
, "PID",
1473 SPR_NOACCESS
, SPR_NOACCESS
,
1474 &spr_read_generic
, &spr_write_generic
,
1476 spr_register(env
, SPR_BOOKE_TCR
, "TCR",
1477 SPR_NOACCESS
, SPR_NOACCESS
,
1478 &spr_read_generic
, &spr_write_booke_tcr
,
1480 spr_register(env
, SPR_BOOKE_TSR
, "TSR",
1481 SPR_NOACCESS
, SPR_NOACCESS
,
1482 &spr_read_generic
, &spr_write_booke_tsr
,
1485 spr_register(env
, SPR_DECR
, "DECR",
1486 SPR_NOACCESS
, SPR_NOACCESS
,
1487 &spr_read_decr
, &spr_write_decr
,
1489 spr_register(env
, SPR_BOOKE_DECAR
, "DECAR",
1490 SPR_NOACCESS
, SPR_NOACCESS
,
1491 SPR_NOACCESS
, &spr_write_generic
,
1494 spr_register(env
, SPR_USPRG0
, "USPRG0",
1495 &spr_read_generic
, &spr_write_generic
,
1496 &spr_read_generic
, &spr_write_generic
,
1498 spr_register(env
, SPR_SPRG4
, "SPRG4",
1499 SPR_NOACCESS
, SPR_NOACCESS
,
1500 &spr_read_generic
, &spr_write_generic
,
1502 spr_register(env
, SPR_USPRG4
, "USPRG4",
1503 &spr_read_ureg
, SPR_NOACCESS
,
1504 &spr_read_ureg
, SPR_NOACCESS
,
1506 spr_register(env
, SPR_SPRG5
, "SPRG5",
1507 SPR_NOACCESS
, SPR_NOACCESS
,
1508 &spr_read_generic
, &spr_write_generic
,
1510 spr_register(env
, SPR_USPRG5
, "USPRG5",
1511 &spr_read_ureg
, SPR_NOACCESS
,
1512 &spr_read_ureg
, SPR_NOACCESS
,
1514 spr_register(env
, SPR_SPRG6
, "SPRG6",
1515 SPR_NOACCESS
, SPR_NOACCESS
,
1516 &spr_read_generic
, &spr_write_generic
,
1518 spr_register(env
, SPR_USPRG6
, "USPRG6",
1519 &spr_read_ureg
, SPR_NOACCESS
,
1520 &spr_read_ureg
, SPR_NOACCESS
,
1522 spr_register(env
, SPR_SPRG7
, "SPRG7",
1523 SPR_NOACCESS
, SPR_NOACCESS
,
1524 &spr_read_generic
, &spr_write_generic
,
1526 spr_register(env
, SPR_USPRG7
, "USPRG7",
1527 &spr_read_ureg
, SPR_NOACCESS
,
1528 &spr_read_ureg
, SPR_NOACCESS
,
1532 /* FSL storage control registers */
1533 static void gen_spr_BookE_FSL (CPUPPCState
*env
)
1535 #if !defined(CONFIG_USER_ONLY)
1536 /* TLB assist registers */
1537 /* XXX : not implemented */
1538 spr_register(env
, SPR_BOOKE_MAS0
, "MAS0",
1539 SPR_NOACCESS
, SPR_NOACCESS
,
1540 &spr_read_generic
, &spr_write_generic
,
1542 /* XXX : not implemented */
1543 spr_register(env
, SPR_BOOKE_MAS1
, "MAS2",
1544 SPR_NOACCESS
, SPR_NOACCESS
,
1545 &spr_read_generic
, &spr_write_generic
,
1547 /* XXX : not implemented */
1548 spr_register(env
, SPR_BOOKE_MAS2
, "MAS3",
1549 SPR_NOACCESS
, SPR_NOACCESS
,
1550 &spr_read_generic
, &spr_write_generic
,
1552 /* XXX : not implemented */
1553 spr_register(env
, SPR_BOOKE_MAS3
, "MAS4",
1554 SPR_NOACCESS
, SPR_NOACCESS
,
1555 &spr_read_generic
, &spr_write_generic
,
1557 /* XXX : not implemented */
1558 spr_register(env
, SPR_BOOKE_MAS4
, "MAS5",
1559 SPR_NOACCESS
, SPR_NOACCESS
,
1560 &spr_read_generic
, &spr_write_generic
,
1562 /* XXX : not implemented */
1563 spr_register(env
, SPR_BOOKE_MAS6
, "MAS6",
1564 SPR_NOACCESS
, SPR_NOACCESS
,
1565 &spr_read_generic
, &spr_write_generic
,
1567 /* XXX : not implemented */
1568 spr_register(env
, SPR_BOOKE_MAS7
, "MAS7",
1569 SPR_NOACCESS
, SPR_NOACCESS
,
1570 &spr_read_generic
, &spr_write_generic
,
1572 if (env
->nb_pids
> 1) {
1573 /* XXX : not implemented */
1574 spr_register(env
, SPR_BOOKE_PID1
, "PID1",
1575 SPR_NOACCESS
, SPR_NOACCESS
,
1576 &spr_read_generic
, &spr_write_generic
,
1579 if (env
->nb_pids
> 2) {
1580 /* XXX : not implemented */
1581 spr_register(env
, SPR_BOOKE_PID2
, "PID2",
1582 SPR_NOACCESS
, SPR_NOACCESS
,
1583 &spr_read_generic
, &spr_write_generic
,
1586 /* XXX : not implemented */
1587 spr_register(env
, SPR_MMUCFG
, "MMUCFG",
1588 SPR_NOACCESS
, SPR_NOACCESS
,
1589 &spr_read_generic
, SPR_NOACCESS
,
1590 0x00000000); /* TOFIX */
1591 /* XXX : not implemented */
1592 spr_register(env
, SPR_MMUCSR0
, "MMUCSR0",
1593 SPR_NOACCESS
, SPR_NOACCESS
,
1594 &spr_read_generic
, &spr_write_generic
,
1595 0x00000000); /* TOFIX */
1596 switch (env
->nb_ways
) {
1598 /* XXX : not implemented */
1599 spr_register(env
, SPR_BOOKE_TLB3CFG
, "TLB3CFG",
1600 SPR_NOACCESS
, SPR_NOACCESS
,
1601 &spr_read_generic
, SPR_NOACCESS
,
1602 0x00000000); /* TOFIX */
1605 /* XXX : not implemented */
1606 spr_register(env
, SPR_BOOKE_TLB2CFG
, "TLB2CFG",
1607 SPR_NOACCESS
, SPR_NOACCESS
,
1608 &spr_read_generic
, SPR_NOACCESS
,
1609 0x00000000); /* TOFIX */
1612 /* XXX : not implemented */
1613 spr_register(env
, SPR_BOOKE_TLB1CFG
, "TLB1CFG",
1614 SPR_NOACCESS
, SPR_NOACCESS
,
1615 &spr_read_generic
, SPR_NOACCESS
,
1616 0x00000000); /* TOFIX */
1619 /* XXX : not implemented */
1620 spr_register(env
, SPR_BOOKE_TLB0CFG
, "TLB0CFG",
1621 SPR_NOACCESS
, SPR_NOACCESS
,
1622 &spr_read_generic
, SPR_NOACCESS
,
1623 0x00000000); /* TOFIX */
1632 /* SPR specific to PowerPC 440 implementation */
1633 static void gen_spr_440 (CPUPPCState
*env
)
1636 /* XXX : not implemented */
1637 spr_register(env
, SPR_440_DNV0
, "DNV0",
1638 SPR_NOACCESS
, SPR_NOACCESS
,
1639 &spr_read_generic
, &spr_write_generic
,
1641 /* XXX : not implemented */
1642 spr_register(env
, SPR_440_DNV1
, "DNV1",
1643 SPR_NOACCESS
, SPR_NOACCESS
,
1644 &spr_read_generic
, &spr_write_generic
,
1646 /* XXX : not implemented */
1647 spr_register(env
, SPR_440_DNV2
, "DNV2",
1648 SPR_NOACCESS
, SPR_NOACCESS
,
1649 &spr_read_generic
, &spr_write_generic
,
1651 /* XXX : not implemented */
1652 spr_register(env
, SPR_440_DNV3
, "DNV3",
1653 SPR_NOACCESS
, SPR_NOACCESS
,
1654 &spr_read_generic
, &spr_write_generic
,
1656 /* XXX : not implemented */
1657 spr_register(env
, SPR_440_DTV0
, "DTV0",
1658 SPR_NOACCESS
, SPR_NOACCESS
,
1659 &spr_read_generic
, &spr_write_generic
,
1661 /* XXX : not implemented */
1662 spr_register(env
, SPR_440_DTV1
, "DTV1",
1663 SPR_NOACCESS
, SPR_NOACCESS
,
1664 &spr_read_generic
, &spr_write_generic
,
1666 /* XXX : not implemented */
1667 spr_register(env
, SPR_440_DTV2
, "DTV2",
1668 SPR_NOACCESS
, SPR_NOACCESS
,
1669 &spr_read_generic
, &spr_write_generic
,
1671 /* XXX : not implemented */
1672 spr_register(env
, SPR_440_DTV3
, "DTV3",
1673 SPR_NOACCESS
, SPR_NOACCESS
,
1674 &spr_read_generic
, &spr_write_generic
,
1676 /* XXX : not implemented */
1677 spr_register(env
, SPR_440_DVLIM
, "DVLIM",
1678 SPR_NOACCESS
, SPR_NOACCESS
,
1679 &spr_read_generic
, &spr_write_generic
,
1681 /* XXX : not implemented */
1682 spr_register(env
, SPR_440_INV0
, "INV0",
1683 SPR_NOACCESS
, SPR_NOACCESS
,
1684 &spr_read_generic
, &spr_write_generic
,
1686 /* XXX : not implemented */
1687 spr_register(env
, SPR_440_INV1
, "INV1",
1688 SPR_NOACCESS
, SPR_NOACCESS
,
1689 &spr_read_generic
, &spr_write_generic
,
1691 /* XXX : not implemented */
1692 spr_register(env
, SPR_440_INV2
, "INV2",
1693 SPR_NOACCESS
, SPR_NOACCESS
,
1694 &spr_read_generic
, &spr_write_generic
,
1696 /* XXX : not implemented */
1697 spr_register(env
, SPR_440_INV3
, "INV3",
1698 SPR_NOACCESS
, SPR_NOACCESS
,
1699 &spr_read_generic
, &spr_write_generic
,
1701 /* XXX : not implemented */
1702 spr_register(env
, SPR_440_ITV0
, "ITV0",
1703 SPR_NOACCESS
, SPR_NOACCESS
,
1704 &spr_read_generic
, &spr_write_generic
,
1706 /* XXX : not implemented */
1707 spr_register(env
, SPR_440_ITV1
, "ITV1",
1708 SPR_NOACCESS
, SPR_NOACCESS
,
1709 &spr_read_generic
, &spr_write_generic
,
1711 /* XXX : not implemented */
1712 spr_register(env
, SPR_440_ITV2
, "ITV2",
1713 SPR_NOACCESS
, SPR_NOACCESS
,
1714 &spr_read_generic
, &spr_write_generic
,
1716 /* XXX : not implemented */
1717 spr_register(env
, SPR_440_ITV3
, "ITV3",
1718 SPR_NOACCESS
, SPR_NOACCESS
,
1719 &spr_read_generic
, &spr_write_generic
,
1721 /* XXX : not implemented */
1722 spr_register(env
, SPR_440_IVLIM
, "IVLIM",
1723 SPR_NOACCESS
, SPR_NOACCESS
,
1724 &spr_read_generic
, &spr_write_generic
,
1727 /* XXX : not implemented */
1728 spr_register(env
, SPR_BOOKE_DCDBTRH
, "DCDBTRH",
1729 SPR_NOACCESS
, SPR_NOACCESS
,
1730 &spr_read_generic
, SPR_NOACCESS
,
1732 /* XXX : not implemented */
1733 spr_register(env
, SPR_BOOKE_DCDBTRL
, "DCDBTRL",
1734 SPR_NOACCESS
, SPR_NOACCESS
,
1735 &spr_read_generic
, SPR_NOACCESS
,
1737 /* XXX : not implemented */
1738 spr_register(env
, SPR_BOOKE_ICDBDR
, "ICDBDR",
1739 SPR_NOACCESS
, SPR_NOACCESS
,
1740 &spr_read_generic
, SPR_NOACCESS
,
1742 /* XXX : not implemented */
1743 spr_register(env
, SPR_BOOKE_ICDBTRH
, "ICDBTRH",
1744 SPR_NOACCESS
, SPR_NOACCESS
,
1745 &spr_read_generic
, SPR_NOACCESS
,
1747 /* XXX : not implemented */
1748 spr_register(env
, SPR_BOOKE_ICDBTRL
, "ICDBTRL",
1749 SPR_NOACCESS
, SPR_NOACCESS
,
1750 &spr_read_generic
, SPR_NOACCESS
,
1752 /* XXX : not implemented */
1753 spr_register(env
, SPR_440_DBDR
, "DBDR",
1754 SPR_NOACCESS
, SPR_NOACCESS
,
1755 &spr_read_generic
, &spr_write_generic
,
1757 /* Processor control */
1758 spr_register(env
, SPR_4xx_CCR0
, "CCR0",
1759 SPR_NOACCESS
, SPR_NOACCESS
,
1760 &spr_read_generic
, &spr_write_generic
,
1762 spr_register(env
, SPR_440_RSTCFG
, "RSTCFG",
1763 SPR_NOACCESS
, SPR_NOACCESS
,
1764 &spr_read_generic
, SPR_NOACCESS
,
1766 /* Storage control */
1767 spr_register(env
, SPR_440_MMUCR
, "MMUCR",
1768 SPR_NOACCESS
, SPR_NOACCESS
,
1769 &spr_read_generic
, &spr_write_generic
,
1773 /* SPR shared between PowerPC 40x implementations */
1774 static void gen_spr_40x (CPUPPCState
*env
)
1777 /* not emulated, as Qemu do not emulate caches */
1778 spr_register(env
, SPR_40x_DCCR
, "DCCR",
1779 SPR_NOACCESS
, SPR_NOACCESS
,
1780 &spr_read_generic
, &spr_write_generic
,
1782 /* not emulated, as Qemu do not emulate caches */
1783 spr_register(env
, SPR_40x_ICCR
, "ICCR",
1784 SPR_NOACCESS
, SPR_NOACCESS
,
1785 &spr_read_generic
, &spr_write_generic
,
1787 /* not emulated, as Qemu do not emulate caches */
1788 spr_register(env
, SPR_BOOKE_ICDBDR
, "ICDBDR",
1789 SPR_NOACCESS
, SPR_NOACCESS
,
1790 &spr_read_generic
, SPR_NOACCESS
,
1793 spr_register(env
, SPR_40x_DEAR
, "DEAR",
1794 SPR_NOACCESS
, SPR_NOACCESS
,
1795 &spr_read_generic
, &spr_write_generic
,
1797 spr_register(env
, SPR_40x_ESR
, "ESR",
1798 SPR_NOACCESS
, SPR_NOACCESS
,
1799 &spr_read_generic
, &spr_write_generic
,
1801 spr_register(env
, SPR_40x_EVPR
, "EVPR",
1802 SPR_NOACCESS
, SPR_NOACCESS
,
1803 &spr_read_generic
, &spr_write_excp_prefix
,
1805 spr_register(env
, SPR_40x_SRR2
, "SRR2",
1806 &spr_read_generic
, &spr_write_generic
,
1807 &spr_read_generic
, &spr_write_generic
,
1809 spr_register(env
, SPR_40x_SRR3
, "SRR3",
1810 &spr_read_generic
, &spr_write_generic
,
1811 &spr_read_generic
, &spr_write_generic
,
1814 spr_register(env
, SPR_40x_PIT
, "PIT",
1815 SPR_NOACCESS
, SPR_NOACCESS
,
1816 &spr_read_40x_pit
, &spr_write_40x_pit
,
1818 spr_register(env
, SPR_40x_TCR
, "TCR",
1819 SPR_NOACCESS
, SPR_NOACCESS
,
1820 &spr_read_generic
, &spr_write_booke_tcr
,
1822 spr_register(env
, SPR_40x_TSR
, "TSR",
1823 SPR_NOACCESS
, SPR_NOACCESS
,
1824 &spr_read_generic
, &spr_write_booke_tsr
,
1828 /* SPR specific to PowerPC 405 implementation */
1829 static void gen_spr_405 (CPUPPCState
*env
)
1832 spr_register(env
, SPR_40x_PID
, "PID",
1833 SPR_NOACCESS
, SPR_NOACCESS
,
1834 &spr_read_generic
, &spr_write_generic
,
1836 spr_register(env
, SPR_4xx_CCR0
, "CCR0",
1837 SPR_NOACCESS
, SPR_NOACCESS
,
1838 &spr_read_generic
, &spr_write_generic
,
1840 /* Debug interface */
1841 /* XXX : not implemented */
1842 spr_register(env
, SPR_40x_DBCR0
, "DBCR0",
1843 SPR_NOACCESS
, SPR_NOACCESS
,
1844 &spr_read_generic
, &spr_write_40x_dbcr0
,
1846 /* XXX : not implemented */
1847 spr_register(env
, SPR_405_DBCR1
, "DBCR1",
1848 SPR_NOACCESS
, SPR_NOACCESS
,
1849 &spr_read_generic
, &spr_write_generic
,
1851 /* XXX : not implemented */
1852 spr_register(env
, SPR_40x_DBSR
, "DBSR",
1853 SPR_NOACCESS
, SPR_NOACCESS
,
1854 &spr_read_generic
, &spr_write_clear
,
1855 /* Last reset was system reset */
1857 /* XXX : not implemented */
1858 spr_register(env
, SPR_40x_DAC1
, "DAC1",
1859 SPR_NOACCESS
, SPR_NOACCESS
,
1860 &spr_read_generic
, &spr_write_generic
,
1862 spr_register(env
, SPR_40x_DAC2
, "DAC2",
1863 SPR_NOACCESS
, SPR_NOACCESS
,
1864 &spr_read_generic
, &spr_write_generic
,
1866 /* XXX : not implemented */
1867 spr_register(env
, SPR_405_DVC1
, "DVC1",
1868 SPR_NOACCESS
, SPR_NOACCESS
,
1869 &spr_read_generic
, &spr_write_generic
,
1871 /* XXX : not implemented */
1872 spr_register(env
, SPR_405_DVC2
, "DVC2",
1873 SPR_NOACCESS
, SPR_NOACCESS
,
1874 &spr_read_generic
, &spr_write_generic
,
1876 /* XXX : not implemented */
1877 spr_register(env
, SPR_40x_IAC1
, "IAC1",
1878 SPR_NOACCESS
, SPR_NOACCESS
,
1879 &spr_read_generic
, &spr_write_generic
,
1881 spr_register(env
, SPR_40x_IAC2
, "IAC2",
1882 SPR_NOACCESS
, SPR_NOACCESS
,
1883 &spr_read_generic
, &spr_write_generic
,
1885 /* XXX : not implemented */
1886 spr_register(env
, SPR_405_IAC3
, "IAC3",
1887 SPR_NOACCESS
, SPR_NOACCESS
,
1888 &spr_read_generic
, &spr_write_generic
,
1890 /* XXX : not implemented */
1891 spr_register(env
, SPR_405_IAC4
, "IAC4",
1892 SPR_NOACCESS
, SPR_NOACCESS
,
1893 &spr_read_generic
, &spr_write_generic
,
1895 /* Storage control */
1896 /* XXX: TODO: not implemented */
1897 spr_register(env
, SPR_405_SLER
, "SLER",
1898 SPR_NOACCESS
, SPR_NOACCESS
,
1899 &spr_read_generic
, &spr_write_40x_sler
,
1901 spr_register(env
, SPR_40x_ZPR
, "ZPR",
1902 SPR_NOACCESS
, SPR_NOACCESS
,
1903 &spr_read_generic
, &spr_write_generic
,
1905 /* XXX : not implemented */
1906 spr_register(env
, SPR_405_SU0R
, "SU0R",
1907 SPR_NOACCESS
, SPR_NOACCESS
,
1908 &spr_read_generic
, &spr_write_generic
,
1911 spr_register(env
, SPR_USPRG0
, "USPRG0",
1912 &spr_read_ureg
, SPR_NOACCESS
,
1913 &spr_read_ureg
, SPR_NOACCESS
,
1915 spr_register(env
, SPR_SPRG4
, "SPRG4",
1916 SPR_NOACCESS
, SPR_NOACCESS
,
1917 &spr_read_generic
, &spr_write_generic
,
1919 spr_register(env
, SPR_USPRG4
, "USPRG4",
1920 &spr_read_ureg
, SPR_NOACCESS
,
1921 &spr_read_ureg
, SPR_NOACCESS
,
1923 spr_register(env
, SPR_SPRG5
, "SPRG5",
1924 SPR_NOACCESS
, SPR_NOACCESS
,
1925 spr_read_generic
, &spr_write_generic
,
1927 spr_register(env
, SPR_USPRG5
, "USPRG5",
1928 &spr_read_ureg
, SPR_NOACCESS
,
1929 &spr_read_ureg
, SPR_NOACCESS
,
1931 spr_register(env
, SPR_SPRG6
, "SPRG6",
1932 SPR_NOACCESS
, SPR_NOACCESS
,
1933 spr_read_generic
, &spr_write_generic
,
1935 spr_register(env
, SPR_USPRG6
, "USPRG6",
1936 &spr_read_ureg
, SPR_NOACCESS
,
1937 &spr_read_ureg
, SPR_NOACCESS
,
1939 spr_register(env
, SPR_SPRG7
, "SPRG7",
1940 SPR_NOACCESS
, SPR_NOACCESS
,
1941 spr_read_generic
, &spr_write_generic
,
1943 spr_register(env
, SPR_USPRG7
, "USPRG7",
1944 &spr_read_ureg
, SPR_NOACCESS
,
1945 &spr_read_ureg
, SPR_NOACCESS
,
1949 /* SPR shared between PowerPC 401 & 403 implementations */
1950 static void gen_spr_401_403 (CPUPPCState
*env
)
1953 spr_register(env
, SPR_403_VTBL
, "TBL",
1954 &spr_read_tbl
, SPR_NOACCESS
,
1955 &spr_read_tbl
, SPR_NOACCESS
,
1957 spr_register(env
, SPR_403_TBL
, "TBL",
1958 SPR_NOACCESS
, SPR_NOACCESS
,
1959 SPR_NOACCESS
, &spr_write_tbl
,
1961 spr_register(env
, SPR_403_VTBU
, "TBU",
1962 &spr_read_tbu
, SPR_NOACCESS
,
1963 &spr_read_tbu
, SPR_NOACCESS
,
1965 spr_register(env
, SPR_403_TBU
, "TBU",
1966 SPR_NOACCESS
, SPR_NOACCESS
,
1967 SPR_NOACCESS
, &spr_write_tbu
,
1970 /* not emulated, as Qemu do not emulate caches */
1971 spr_register(env
, SPR_403_CDBCR
, "CDBCR",
1972 SPR_NOACCESS
, SPR_NOACCESS
,
1973 &spr_read_generic
, &spr_write_generic
,
1977 /* SPR specific to PowerPC 401 implementation */
1978 static void gen_spr_401 (CPUPPCState
*env
)
1980 /* Debug interface */
1981 /* XXX : not implemented */
1982 spr_register(env
, SPR_40x_DBCR0
, "DBCR",
1983 SPR_NOACCESS
, SPR_NOACCESS
,
1984 &spr_read_generic
, &spr_write_40x_dbcr0
,
1986 /* XXX : not implemented */
1987 spr_register(env
, SPR_40x_DBSR
, "DBSR",
1988 SPR_NOACCESS
, SPR_NOACCESS
,
1989 &spr_read_generic
, &spr_write_clear
,
1990 /* Last reset was system reset */
1992 /* XXX : not implemented */
1993 spr_register(env
, SPR_40x_DAC1
, "DAC",
1994 SPR_NOACCESS
, SPR_NOACCESS
,
1995 &spr_read_generic
, &spr_write_generic
,
1997 /* XXX : not implemented */
1998 spr_register(env
, SPR_40x_IAC1
, "IAC",
1999 SPR_NOACCESS
, SPR_NOACCESS
,
2000 &spr_read_generic
, &spr_write_generic
,
2002 /* Storage control */
2003 /* XXX: TODO: not implemented */
2004 spr_register(env
, SPR_405_SLER
, "SLER",
2005 SPR_NOACCESS
, SPR_NOACCESS
,
2006 &spr_read_generic
, &spr_write_40x_sler
,
2008 /* not emulated, as Qemu never does speculative access */
2009 spr_register(env
, SPR_40x_SGR
, "SGR",
2010 SPR_NOACCESS
, SPR_NOACCESS
,
2011 &spr_read_generic
, &spr_write_generic
,
2013 /* not emulated, as Qemu do not emulate caches */
2014 spr_register(env
, SPR_40x_DCWR
, "DCWR",
2015 SPR_NOACCESS
, SPR_NOACCESS
,
2016 &spr_read_generic
, &spr_write_generic
,
2020 static void gen_spr_401x2 (CPUPPCState
*env
)
2023 spr_register(env
, SPR_40x_PID
, "PID",
2024 SPR_NOACCESS
, SPR_NOACCESS
,
2025 &spr_read_generic
, &spr_write_generic
,
2027 spr_register(env
, SPR_40x_ZPR
, "ZPR",
2028 SPR_NOACCESS
, SPR_NOACCESS
,
2029 &spr_read_generic
, &spr_write_generic
,
2033 /* SPR specific to PowerPC 403 implementation */
2034 static void gen_spr_403 (CPUPPCState
*env
)
2036 /* Debug interface */
2037 /* XXX : not implemented */
2038 spr_register(env
, SPR_40x_DBCR0
, "DBCR0",
2039 SPR_NOACCESS
, SPR_NOACCESS
,
2040 &spr_read_generic
, &spr_write_40x_dbcr0
,
2042 /* XXX : not implemented */
2043 spr_register(env
, SPR_40x_DBSR
, "DBSR",
2044 SPR_NOACCESS
, SPR_NOACCESS
,
2045 &spr_read_generic
, &spr_write_clear
,
2046 /* Last reset was system reset */
2048 /* XXX : not implemented */
2049 spr_register(env
, SPR_40x_DAC1
, "DAC1",
2050 SPR_NOACCESS
, SPR_NOACCESS
,
2051 &spr_read_generic
, &spr_write_generic
,
2053 /* XXX : not implemented */
2054 spr_register(env
, SPR_40x_DAC2
, "DAC2",
2055 SPR_NOACCESS
, SPR_NOACCESS
,
2056 &spr_read_generic
, &spr_write_generic
,
2058 /* XXX : not implemented */
2059 spr_register(env
, SPR_40x_IAC1
, "IAC1",
2060 SPR_NOACCESS
, SPR_NOACCESS
,
2061 &spr_read_generic
, &spr_write_generic
,
2063 /* XXX : not implemented */
2064 spr_register(env
, SPR_40x_IAC2
, "IAC2",
2065 SPR_NOACCESS
, SPR_NOACCESS
,
2066 &spr_read_generic
, &spr_write_generic
,
2070 static void gen_spr_403_real (CPUPPCState
*env
)
2072 spr_register(env
, SPR_403_PBL1
, "PBL1",
2073 SPR_NOACCESS
, SPR_NOACCESS
,
2074 &spr_read_403_pbr
, &spr_write_403_pbr
,
2076 spr_register(env
, SPR_403_PBU1
, "PBU1",
2077 SPR_NOACCESS
, SPR_NOACCESS
,
2078 &spr_read_403_pbr
, &spr_write_403_pbr
,
2080 spr_register(env
, SPR_403_PBL2
, "PBL2",
2081 SPR_NOACCESS
, SPR_NOACCESS
,
2082 &spr_read_403_pbr
, &spr_write_403_pbr
,
2084 spr_register(env
, SPR_403_PBU2
, "PBU2",
2085 SPR_NOACCESS
, SPR_NOACCESS
,
2086 &spr_read_403_pbr
, &spr_write_403_pbr
,
2090 static void gen_spr_403_mmu (CPUPPCState
*env
)
2093 spr_register(env
, SPR_40x_PID
, "PID",
2094 SPR_NOACCESS
, SPR_NOACCESS
,
2095 &spr_read_generic
, &spr_write_generic
,
2097 spr_register(env
, SPR_40x_ZPR
, "ZPR",
2098 SPR_NOACCESS
, SPR_NOACCESS
,
2099 &spr_read_generic
, &spr_write_generic
,
2103 /* SPR specific to PowerPC compression coprocessor extension */
2104 static void gen_spr_compress (CPUPPCState
*env
)
2106 /* XXX : not implemented */
2107 spr_register(env
, SPR_401_SKR
, "SKR",
2108 SPR_NOACCESS
, SPR_NOACCESS
,
2109 &spr_read_generic
, &spr_write_generic
,
2113 #if defined (TARGET_PPC64)
2114 /* SPR specific to PowerPC 620 */
2115 static void gen_spr_620 (CPUPPCState
*env
)
2117 /* XXX : not implemented */
2118 spr_register(env
, SPR_620_PMR0
, "PMR0",
2119 SPR_NOACCESS
, SPR_NOACCESS
,
2120 &spr_read_generic
, &spr_write_generic
,
2122 /* XXX : not implemented */
2123 spr_register(env
, SPR_620_PMR1
, "PMR1",
2124 SPR_NOACCESS
, SPR_NOACCESS
,
2125 &spr_read_generic
, &spr_write_generic
,
2127 /* XXX : not implemented */
2128 spr_register(env
, SPR_620_PMR2
, "PMR2",
2129 SPR_NOACCESS
, SPR_NOACCESS
,
2130 &spr_read_generic
, &spr_write_generic
,
2132 /* XXX : not implemented */
2133 spr_register(env
, SPR_620_PMR3
, "PMR3",
2134 SPR_NOACCESS
, SPR_NOACCESS
,
2135 &spr_read_generic
, &spr_write_generic
,
2137 /* XXX : not implemented */
2138 spr_register(env
, SPR_620_PMR4
, "PMR4",
2139 SPR_NOACCESS
, SPR_NOACCESS
,
2140 &spr_read_generic
, &spr_write_generic
,
2142 /* XXX : not implemented */
2143 spr_register(env
, SPR_620_PMR5
, "PMR5",
2144 SPR_NOACCESS
, SPR_NOACCESS
,
2145 &spr_read_generic
, &spr_write_generic
,
2147 /* XXX : not implemented */
2148 spr_register(env
, SPR_620_PMR6
, "PMR6",
2149 SPR_NOACCESS
, SPR_NOACCESS
,
2150 &spr_read_generic
, &spr_write_generic
,
2152 /* XXX : not implemented */
2153 spr_register(env
, SPR_620_PMR7
, "PMR7",
2154 SPR_NOACCESS
, SPR_NOACCESS
,
2155 &spr_read_generic
, &spr_write_generic
,
2157 /* XXX : not implemented */
2158 spr_register(env
, SPR_620_PMR8
, "PMR8",
2159 SPR_NOACCESS
, SPR_NOACCESS
,
2160 &spr_read_generic
, &spr_write_generic
,
2162 /* XXX : not implemented */
2163 spr_register(env
, SPR_620_PMR9
, "PMR9",
2164 SPR_NOACCESS
, SPR_NOACCESS
,
2165 &spr_read_generic
, &spr_write_generic
,
2167 /* XXX : not implemented */
2168 spr_register(env
, SPR_620_PMRA
, "PMR10",
2169 SPR_NOACCESS
, SPR_NOACCESS
,
2170 &spr_read_generic
, &spr_write_generic
,
2172 /* XXX : not implemented */
2173 spr_register(env
, SPR_620_PMRB
, "PMR11",
2174 SPR_NOACCESS
, SPR_NOACCESS
,
2175 &spr_read_generic
, &spr_write_generic
,
2177 /* XXX : not implemented */
2178 spr_register(env
, SPR_620_PMRC
, "PMR12",
2179 SPR_NOACCESS
, SPR_NOACCESS
,
2180 &spr_read_generic
, &spr_write_generic
,
2182 /* XXX : not implemented */
2183 spr_register(env
, SPR_620_PMRD
, "PMR13",
2184 SPR_NOACCESS
, SPR_NOACCESS
,
2185 &spr_read_generic
, &spr_write_generic
,
2187 /* XXX : not implemented */
2188 spr_register(env
, SPR_620_PMRE
, "PMR14",
2189 SPR_NOACCESS
, SPR_NOACCESS
,
2190 &spr_read_generic
, &spr_write_generic
,
2192 /* XXX : not implemented */
2193 spr_register(env
, SPR_620_PMRF
, "PMR15",
2194 SPR_NOACCESS
, SPR_NOACCESS
,
2195 &spr_read_generic
, &spr_write_generic
,
2197 /* XXX : not implemented */
2198 spr_register(env
, SPR_620_HID8
, "HID8",
2199 SPR_NOACCESS
, SPR_NOACCESS
,
2200 &spr_read_generic
, &spr_write_generic
,
2202 /* XXX : not implemented */
2203 spr_register(env
, SPR_620_HID9
, "HID9",
2204 SPR_NOACCESS
, SPR_NOACCESS
,
2205 &spr_read_generic
, &spr_write_generic
,
2208 #endif /* defined (TARGET_PPC64) */
2212 * AMR => SPR 29 (Power 2.04)
2213 * CTRL => SPR 136 (Power 2.04)
2214 * CTRL => SPR 152 (Power 2.04)
2215 * SCOMC => SPR 276 (64 bits ?)
2216 * SCOMD => SPR 277 (64 bits ?)
2217 * TBU40 => SPR 286 (Power 2.04 hypv)
2218 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2219 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2220 * HDSISR => SPR 306 (Power 2.04 hypv)
2221 * HDAR => SPR 307 (Power 2.04 hypv)
2222 * PURR => SPR 309 (Power 2.04 hypv)
2223 * HDEC => SPR 310 (Power 2.04 hypv)
2224 * HIOR => SPR 311 (hypv)
2225 * RMOR => SPR 312 (970)
2226 * HRMOR => SPR 313 (Power 2.04 hypv)
2227 * HSRR0 => SPR 314 (Power 2.04 hypv)
2228 * HSRR1 => SPR 315 (Power 2.04 hypv)
2229 * LPCR => SPR 316 (970)
2230 * LPIDR => SPR 317 (970)
2231 * SPEFSCR => SPR 512 (Power 2.04 emb)
2232 * EPR => SPR 702 (Power 2.04 emb)
2233 * perf => 768-783 (Power 2.04)
2234 * perf => 784-799 (Power 2.04)
2235 * PPR => SPR 896 (Power 2.04)
2236 * EPLC => SPR 947 (Power 2.04 emb)
2237 * EPSC => SPR 948 (Power 2.04 emb)
2238 * DABRX => 1015 (Power 2.04 hypv)
2239 * FPECR => SPR 1022 (?)
2240 * ... and more (thermal management, performance counters, ...)
2243 /*****************************************************************************/
2244 /* Exception vectors models */
2245 static void init_excp_4xx_real (CPUPPCState
*env
)
2247 #if !defined(CONFIG_USER_ONLY)
2248 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000100;
2249 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2250 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2251 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2252 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2253 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2254 env
->excp_vectors
[POWERPC_EXCP_PIT
] = 0x00001000;
2255 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00001010;
2256 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00001020;
2257 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00002000;
2258 env
->excp_prefix
= 0x00000000UL
;
2259 env
->ivor_mask
= 0x0000FFF0UL
;
2260 env
->ivpr_mask
= 0xFFFF0000UL
;
2261 /* Hardware reset vector */
2262 env
->hreset_vector
= 0xFFFFFFFCUL
;
2266 static void init_excp_4xx_softmmu (CPUPPCState
*env
)
2268 #if !defined(CONFIG_USER_ONLY)
2269 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000100;
2270 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2271 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2272 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2273 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2274 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2275 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2276 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2277 env
->excp_vectors
[POWERPC_EXCP_PIT
] = 0x00001000;
2278 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00001010;
2279 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00001020;
2280 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00001100;
2281 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00001200;
2282 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00002000;
2283 env
->excp_prefix
= 0x00000000UL
;
2284 env
->ivor_mask
= 0x0000FFF0UL
;
2285 env
->ivpr_mask
= 0xFFFF0000UL
;
2286 /* Hardware reset vector */
2287 env
->hreset_vector
= 0xFFFFFFFCUL
;
2291 static void init_excp_BookE (CPUPPCState
*env
)
2293 #if !defined(CONFIG_USER_ONLY)
2294 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000000;
2295 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000000;
2296 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000000;
2297 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000000;
2298 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000000;
2299 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000000;
2300 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000000;
2301 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000000;
2302 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000000;
2303 env
->excp_vectors
[POWERPC_EXCP_APU
] = 0x00000000;
2304 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000000;
2305 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00000000;
2306 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00000000;
2307 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00000000;
2308 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00000000;
2309 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00000000;
2310 env
->excp_prefix
= 0x00000000UL
;
2311 env
->ivor_mask
= 0x0000FFE0UL
;
2312 env
->ivpr_mask
= 0xFFFF0000UL
;
2313 /* Hardware reset vector */
2314 env
->hreset_vector
= 0xFFFFFFFCUL
;
2318 static void init_excp_601 (CPUPPCState
*env
)
2320 #if !defined(CONFIG_USER_ONLY)
2321 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2322 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2323 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2324 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2325 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2326 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2327 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2328 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2329 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2330 env
->excp_vectors
[POWERPC_EXCP_IO
] = 0x00000A00;
2331 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2332 env
->excp_vectors
[POWERPC_EXCP_RUNM
] = 0x00002000;
2333 env
->excp_prefix
= 0xFFF00000UL
;
2334 /* Hardware reset vector */
2335 env
->hreset_vector
= 0x00000100UL
;
2339 static void init_excp_602 (CPUPPCState
*env
)
2341 #if !defined(CONFIG_USER_ONLY)
2342 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2343 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2344 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2345 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2346 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2347 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2348 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2349 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2350 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2351 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2352 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2353 env
->excp_vectors
[POWERPC_EXCP_FPA
] = 0x00000E00;
2354 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2355 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2356 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2357 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2358 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2359 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00001500;
2360 env
->excp_vectors
[POWERPC_EXCP_EMUL
] = 0x00001600;
2361 env
->excp_prefix
= 0xFFF00000UL
;
2362 /* Hardware reset vector */
2363 env
->hreset_vector
= 0xFFFFFFFCUL
;
2367 static void init_excp_603 (CPUPPCState
*env
)
2369 #if !defined(CONFIG_USER_ONLY)
2370 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2371 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2372 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2373 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2374 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2375 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2376 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2377 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2378 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2379 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2380 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2381 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2382 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2383 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2384 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2385 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2386 env
->excp_prefix
= 0x00000000UL
;
2387 /* Hardware reset vector */
2388 env
->hreset_vector
= 0xFFFFFFFCUL
;
2392 static void init_excp_G2 (CPUPPCState
*env
)
2394 #if !defined(CONFIG_USER_ONLY)
2395 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2396 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2397 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2398 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2399 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2400 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2401 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2402 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2403 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2404 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000A00;
2405 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2406 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2407 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2408 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2409 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2410 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2411 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2412 env
->excp_prefix
= 0x00000000UL
;
2413 /* Hardware reset vector */
2414 env
->hreset_vector
= 0xFFFFFFFCUL
;
2418 static void init_excp_604 (CPUPPCState
*env
)
2420 #if !defined(CONFIG_USER_ONLY)
2421 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2422 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2423 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2424 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2425 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2426 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2427 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2428 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2429 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2430 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2431 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2432 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2433 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2434 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2435 env
->excp_prefix
= 0x00000000UL
;
2436 /* Hardware reset vector */
2437 env
->hreset_vector
= 0xFFFFFFFCUL
;
2441 #if defined(TARGET_PPC64)
2442 static void init_excp_620 (CPUPPCState
*env
)
2444 #if !defined(CONFIG_USER_ONLY)
2445 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2446 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2447 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2448 env
->excp_vectors
[POWERPC_EXCP_DSEG
] = 0x00000380;
2449 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2450 env
->excp_vectors
[POWERPC_EXCP_ISEG
] = 0x00000480;
2451 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2452 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2453 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2454 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2455 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2456 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2457 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2458 env
->excp_vectors
[POWERPC_EXCP_FPA
] = 0x00000E00;
2459 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2460 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2461 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2462 env
->excp_prefix
= 0xFFF00000UL
;
2463 /* Hardware reset vector */
2464 env
->hreset_vector
= 0x0000000000000100ULL
;
2467 #endif /* defined(TARGET_PPC64) */
2469 static void init_excp_7x0 (CPUPPCState
*env
)
2471 #if !defined(CONFIG_USER_ONLY)
2472 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2473 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2474 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2475 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2476 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2477 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2478 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2479 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2480 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2481 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2482 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2483 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2484 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2485 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
2486 env
->excp_prefix
= 0x00000000UL
;
2487 /* Hardware reset vector */
2488 env
->hreset_vector
= 0xFFFFFFFCUL
;
2492 static void init_excp_750FX (CPUPPCState
*env
)
2494 #if !defined(CONFIG_USER_ONLY)
2495 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2496 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2497 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2498 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2499 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2500 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2501 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2502 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2503 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2504 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2505 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2506 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2507 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2508 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2509 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
2510 env
->excp_prefix
= 0x00000000UL
;
2511 /* Hardware reset vector */
2512 env
->hreset_vector
= 0xFFFFFFFCUL
;
2516 /* XXX: Check if this is correct */
2517 static void init_excp_7x5 (CPUPPCState
*env
)
2519 #if !defined(CONFIG_USER_ONLY)
2520 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2521 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2522 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2523 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2524 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2525 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2526 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2527 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2528 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2529 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2530 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2531 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2532 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2533 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2534 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2535 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2536 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2537 env
->excp_prefix
= 0x00000000UL
;
2538 /* Hardware reset vector */
2539 env
->hreset_vector
= 0xFFFFFFFCUL
;
2543 static void init_excp_7400 (CPUPPCState
*env
)
2545 #if !defined(CONFIG_USER_ONLY)
2546 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2547 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2548 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2549 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2550 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2551 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2552 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2553 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2554 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2555 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2556 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2557 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2558 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
2559 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2560 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2561 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001600;
2562 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
2563 env
->excp_prefix
= 0x00000000UL
;
2564 /* Hardware reset vector */
2565 env
->hreset_vector
= 0xFFFFFFFCUL
;
2569 static void init_excp_7450 (CPUPPCState
*env
)
2571 #if !defined(CONFIG_USER_ONLY)
2572 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2573 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2574 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2575 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2576 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2577 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2578 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2579 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2580 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2581 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2582 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2583 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2584 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
2585 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2586 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2587 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2588 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2589 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2590 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001600;
2591 env
->excp_prefix
= 0x00000000UL
;
2592 /* Hardware reset vector */
2593 env
->hreset_vector
= 0xFFFFFFFCUL
;
2597 #if defined (TARGET_PPC64)
2598 static void init_excp_970 (CPUPPCState
*env
)
2600 #if !defined(CONFIG_USER_ONLY)
2601 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2602 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2603 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2604 env
->excp_vectors
[POWERPC_EXCP_DSEG
] = 0x00000380;
2605 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2606 env
->excp_vectors
[POWERPC_EXCP_ISEG
] = 0x00000480;
2607 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2608 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2609 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2610 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2611 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2612 #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2613 env
->excp_vectors
[POWERPC_EXCP_HDECR
] = 0x00000980;
2615 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2616 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2617 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2618 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
2619 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2620 env
->excp_vectors
[POWERPC_EXCP_MAINT
] = 0x00001600;
2621 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001700;
2622 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001800;
2623 env
->excp_prefix
= 0x00000000FFF00000ULL
;
2624 /* Hardware reset vector */
2625 env
->hreset_vector
= 0x0000000000000100ULL
;
2630 /*****************************************************************************/
2631 /* Power management enable checks */
2632 static int check_pow_none (CPUPPCState
*env
)
2637 static int check_pow_nocheck (CPUPPCState
*env
)
2642 static int check_pow_hid0 (CPUPPCState
*env
)
2644 if (env
->spr
[SPR_HID0
] & 0x00E00000)
2650 /*****************************************************************************/
2651 /* PowerPC implementations definitions */
2653 /* PowerPC 40x instruction set */
2654 #define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_CACHE_DCBZ | PPC_EMB_COMMON)
2657 #define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | \
2658 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2659 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2660 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
2661 #define POWERPC_MMU_401 (POWERPC_MMU_REAL_4xx)
2662 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
2663 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
2664 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
2665 #define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2666 #define check_pow_401 check_pow_nocheck
2668 static void init_proc_401 (CPUPPCState
*env
)
2671 gen_spr_401_403(env
);
2673 init_excp_4xx_real(env
);
2674 env
->dcache_line_size
= 32;
2675 env
->icache_line_size
= 32;
2676 /* Allocate hardware IRQ controller */
2677 ppc40x_irq_init(env
);
2681 #define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | \
2682 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2683 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2684 PPC_CACHE_DCBA | PPC_MFTB | \
2685 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2686 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
2687 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
2688 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
2689 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
2690 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
2691 #define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2692 #define check_pow_401x2 check_pow_nocheck
2694 static void init_proc_401x2 (CPUPPCState
*env
)
2697 gen_spr_401_403(env
);
2699 gen_spr_compress(env
);
2700 /* Memory management */
2701 #if !defined(CONFIG_USER_ONLY)
2706 init_excp_4xx_softmmu(env
);
2707 env
->dcache_line_size
= 32;
2708 env
->icache_line_size
= 32;
2709 /* Allocate hardware IRQ controller */
2710 ppc40x_irq_init(env
);
2714 #define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | \
2715 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2716 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2717 PPC_CACHE_DCBA | PPC_MFTB | \
2718 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2719 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
2720 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
2721 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
2722 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
2723 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
2724 #define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2725 #define check_pow_401x3 check_pow_nocheck
2727 __attribute__ (( unused
))
2728 static void init_proc_401x3 (CPUPPCState
*env
)
2731 gen_spr_401_403(env
);
2734 gen_spr_compress(env
);
2735 init_excp_4xx_softmmu(env
);
2736 env
->dcache_line_size
= 32;
2737 env
->icache_line_size
= 32;
2738 /* Allocate hardware IRQ controller */
2739 ppc40x_irq_init(env
);
2743 #define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | \
2744 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2745 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2747 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2748 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
2749 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
2750 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
2751 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
2752 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
2753 #define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2754 #define check_pow_IOP480 check_pow_nocheck
2756 static void init_proc_IOP480 (CPUPPCState
*env
)
2759 gen_spr_401_403(env
);
2761 gen_spr_compress(env
);
2762 /* Memory management */
2763 #if !defined(CONFIG_USER_ONLY)
2768 init_excp_4xx_softmmu(env
);
2769 env
->dcache_line_size
= 32;
2770 env
->icache_line_size
= 32;
2771 /* Allocate hardware IRQ controller */
2772 ppc40x_irq_init(env
);
2776 #define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | \
2777 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2778 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2779 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
2780 #define POWERPC_MMU_403 (POWERPC_MMU_REAL_4xx)
2781 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
2782 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
2783 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
2784 #define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2785 #define check_pow_403 check_pow_nocheck
2787 static void init_proc_403 (CPUPPCState
*env
)
2790 gen_spr_401_403(env
);
2792 gen_spr_403_real(env
);
2793 init_excp_4xx_real(env
);
2794 env
->dcache_line_size
= 32;
2795 env
->icache_line_size
= 32;
2796 /* Allocate hardware IRQ controller */
2797 ppc40x_irq_init(env
);
2798 #if !defined(CONFIG_USER_ONLY)
2799 /* Hardware reset vector */
2800 env
->hreset_vector
= 0xFFFFFFFCUL
;
2804 /* PowerPC 403 GCX */
2805 #define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | \
2806 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2807 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2808 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2809 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
2810 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
2811 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
2812 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
2813 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
2814 #define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2815 #define check_pow_403GCX check_pow_nocheck
2817 static void init_proc_403GCX (CPUPPCState
*env
)
2820 gen_spr_401_403(env
);
2822 gen_spr_403_real(env
);
2823 gen_spr_403_mmu(env
);
2824 /* Bus access control */
2825 /* not emulated, as Qemu never does speculative access */
2826 spr_register(env
, SPR_40x_SGR
, "SGR",
2827 SPR_NOACCESS
, SPR_NOACCESS
,
2828 &spr_read_generic
, &spr_write_generic
,
2830 /* not emulated, as Qemu do not emulate caches */
2831 spr_register(env
, SPR_40x_DCWR
, "DCWR",
2832 SPR_NOACCESS
, SPR_NOACCESS
,
2833 &spr_read_generic
, &spr_write_generic
,
2835 /* Memory management */
2836 #if !defined(CONFIG_USER_ONLY)
2841 init_excp_4xx_softmmu(env
);
2842 env
->dcache_line_size
= 32;
2843 env
->icache_line_size
= 32;
2844 /* Allocate hardware IRQ controller */
2845 ppc40x_irq_init(env
);
2849 #define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_MFTB | \
2850 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2851 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2852 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
2854 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
2855 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
2856 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
2857 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
2858 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
2859 #define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2861 #define check_pow_405 check_pow_nocheck
2863 static void init_proc_405 (CPUPPCState
*env
)
2869 /* Bus access control */
2870 /* not emulated, as Qemu never does speculative access */
2871 spr_register(env
, SPR_40x_SGR
, "SGR",
2872 SPR_NOACCESS
, SPR_NOACCESS
,
2873 &spr_read_generic
, &spr_write_generic
,
2875 /* not emulated, as Qemu do not emulate caches */
2876 spr_register(env
, SPR_40x_DCWR
, "DCWR",
2877 SPR_NOACCESS
, SPR_NOACCESS
,
2878 &spr_read_generic
, &spr_write_generic
,
2880 /* Memory management */
2881 #if !defined(CONFIG_USER_ONLY)
2886 init_excp_4xx_softmmu(env
);
2887 env
->dcache_line_size
= 32;
2888 env
->icache_line_size
= 32;
2889 /* Allocate hardware IRQ controller */
2890 ppc40x_irq_init(env
);
2893 /* PowerPC 440 EP */
2894 #define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | \
2895 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2896 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2897 PPC_440_SPEC | PPC_RFMCI)
2898 #define POWERPC_MSRM_440EP (0x000000000006D630ULL)
2899 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
2900 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
2901 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
2902 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
2903 #define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2905 #define check_pow_440EP check_pow_nocheck
2907 static void init_proc_440EP (CPUPPCState
*env
)
2913 /* XXX : not implemented */
2914 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
2915 SPR_NOACCESS
, SPR_NOACCESS
,
2916 &spr_read_generic
, &spr_write_generic
,
2918 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
2919 SPR_NOACCESS
, SPR_NOACCESS
,
2920 &spr_read_generic
, &spr_write_generic
,
2922 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
2923 SPR_NOACCESS
, SPR_NOACCESS
,
2924 &spr_read_generic
, &spr_write_generic
,
2926 /* XXX : not implemented */
2927 spr_register(env
, SPR_440_CCR1
, "CCR1",
2928 SPR_NOACCESS
, SPR_NOACCESS
,
2929 &spr_read_generic
, &spr_write_generic
,
2931 /* Memory management */
2932 #if !defined(CONFIG_USER_ONLY)
2937 init_excp_BookE(env
);
2938 env
->dcache_line_size
= 32;
2939 env
->icache_line_size
= 32;
2940 /* XXX: TODO: allocate internal IRQ controller */
2943 /* PowerPC 440 GP */
2944 #define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | \
2945 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2946 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2947 PPC_405_MAC | PPC_440_SPEC)
2948 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
2949 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
2950 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
2951 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
2952 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
2953 #define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2955 #define check_pow_440GP check_pow_nocheck
2957 static void init_proc_440GP (CPUPPCState
*env
)
2963 /* Memory management */
2964 #if !defined(CONFIG_USER_ONLY)
2969 init_excp_BookE(env
);
2970 env
->dcache_line_size
= 32;
2971 env
->icache_line_size
= 32;
2972 /* XXX: TODO: allocate internal IRQ controller */
2976 #define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | \
2977 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2978 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2980 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
2981 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
2982 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
2983 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
2984 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
2985 #define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2987 #define check_pow_440x4 check_pow_nocheck
2989 __attribute__ (( unused
))
2990 static void init_proc_440x4 (CPUPPCState
*env
)
2996 /* Memory management */
2997 #if !defined(CONFIG_USER_ONLY)
3002 init_excp_BookE(env
);
3003 env
->dcache_line_size
= 32;
3004 env
->icache_line_size
= 32;
3005 /* XXX: TODO: allocate internal IRQ controller */
3009 #define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | \
3010 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3011 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3012 PPC_440_SPEC | PPC_RFMCI)
3013 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3014 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3015 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3016 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3017 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3018 #define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3020 #define check_pow_440x5 check_pow_nocheck
3022 static void init_proc_440x5 (CPUPPCState
*env
)
3028 /* XXX : not implemented */
3029 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
3030 SPR_NOACCESS
, SPR_NOACCESS
,
3031 &spr_read_generic
, &spr_write_generic
,
3033 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
3034 SPR_NOACCESS
, SPR_NOACCESS
,
3035 &spr_read_generic
, &spr_write_generic
,
3037 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
3038 SPR_NOACCESS
, SPR_NOACCESS
,
3039 &spr_read_generic
, &spr_write_generic
,
3041 /* XXX : not implemented */
3042 spr_register(env
, SPR_440_CCR1
, "CCR1",
3043 SPR_NOACCESS
, SPR_NOACCESS
,
3044 &spr_read_generic
, &spr_write_generic
,
3046 /* Memory management */
3047 #if !defined(CONFIG_USER_ONLY)
3052 init_excp_BookE(env
);
3053 env
->dcache_line_size
= 32;
3054 env
->icache_line_size
= 32;
3055 /* XXX: TODO: allocate internal IRQ controller */
3058 /* PowerPC 460 (guessed) */
3059 #define POWERPC_INSNS_460 (POWERPC_INSNS_EMB | \
3060 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3061 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
3062 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3063 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3064 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3065 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3066 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3067 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3068 #define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3070 #define check_pow_460 check_pow_nocheck
3072 __attribute__ (( unused
))
3073 static void init_proc_460 (CPUPPCState
*env
)
3079 /* XXX : not implemented */
3080 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
3081 SPR_NOACCESS
, SPR_NOACCESS
,
3082 &spr_read_generic
, &spr_write_generic
,
3084 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
3085 SPR_NOACCESS
, SPR_NOACCESS
,
3086 &spr_read_generic
, &spr_write_generic
,
3088 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
3089 SPR_NOACCESS
, SPR_NOACCESS
,
3090 &spr_read_generic
, &spr_write_generic
,
3092 /* XXX : not implemented */
3093 spr_register(env
, SPR_440_CCR1
, "CCR1",
3094 SPR_NOACCESS
, SPR_NOACCESS
,
3095 &spr_read_generic
, &spr_write_generic
,
3097 /* XXX : not implemented */
3098 spr_register(env
, SPR_DCRIPR
, "SPR_DCRIPR",
3099 &spr_read_generic
, &spr_write_generic
,
3100 &spr_read_generic
, &spr_write_generic
,
3102 /* Memory management */
3103 #if !defined(CONFIG_USER_ONLY)
3108 init_excp_BookE(env
);
3109 env
->dcache_line_size
= 32;
3110 env
->icache_line_size
= 32;
3111 /* XXX: TODO: allocate internal IRQ controller */
3114 /* PowerPC 460F (guessed) */
3115 #define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
3116 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3117 PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
3118 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
3119 PPC_FLOAT_STFIWX | \
3120 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
3121 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3122 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3123 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3124 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3125 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3126 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3127 #define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3129 #define check_pow_460F check_pow_nocheck
3131 __attribute__ (( unused
))
3132 static void init_proc_460F (CPUPPCState
*env
)
3138 /* XXX : not implemented */
3139 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
3140 SPR_NOACCESS
, SPR_NOACCESS
,
3141 &spr_read_generic
, &spr_write_generic
,
3143 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
3144 SPR_NOACCESS
, SPR_NOACCESS
,
3145 &spr_read_generic
, &spr_write_generic
,
3147 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
3148 SPR_NOACCESS
, SPR_NOACCESS
,
3149 &spr_read_generic
, &spr_write_generic
,
3151 /* XXX : not implemented */
3152 spr_register(env
, SPR_440_CCR1
, "CCR1",
3153 SPR_NOACCESS
, SPR_NOACCESS
,
3154 &spr_read_generic
, &spr_write_generic
,
3156 /* XXX : not implemented */
3157 spr_register(env
, SPR_DCRIPR
, "SPR_DCRIPR",
3158 &spr_read_generic
, &spr_write_generic
,
3159 &spr_read_generic
, &spr_write_generic
,
3161 /* Memory management */
3162 #if !defined(CONFIG_USER_ONLY)
3167 init_excp_BookE(env
);
3168 env
->dcache_line_size
= 32;
3169 env
->icache_line_size
= 32;
3170 /* XXX: TODO: allocate internal IRQ controller */
3173 /* Generic BookE PowerPC */
3174 #define POWERPC_INSNS_BookE (POWERPC_INSNS_EMB | \
3175 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3177 PPC_FLOAT | PPC_FLOAT_FSQRT | \
3178 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3179 PPC_FLOAT_FSEL | PPC_FLOAT_STFIW | \
3181 #define POWERPC_MSRM_BookE (0x000000000006D630ULL)
3182 #define POWERPC_MMU_BookE (POWERPC_MMU_BOOKE)
3183 #define POWERPC_EXCP_BookE (POWERPC_EXCP_BOOKE)
3184 #define POWERPC_INPUT_BookE (PPC_FLAGS_INPUT_BookE)
3185 #define POWERPC_BFDM_BookE (bfd_mach_ppc_403)
3186 #define POWERPC_FLAG_BookE (POWERPC_FLAG_NONE)
3187 #define check_pow_BookE check_pow_nocheck
3189 __attribute__ (( unused
))
3190 static void init_proc_BookE (CPUPPCState
*env
)
3192 init_excp_BookE(env
);
3193 env
->dcache_line_size
= 32;
3194 env
->icache_line_size
= 32;
3202 #define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | \
3203 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3205 PPC_BOOKE | PPC_E500_VECTOR)
3206 #define POWERPC_MMU_e500 (POWERPC_MMU_SOFT_4xx)
3207 #define POWERPC_EXCP_e500 (POWERPC_EXCP_40x)
3208 #define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
3209 #define POWERPC_BFDM_e500 (bfd_mach_ppc_403)
3210 #define POWERPC_FLAG_e500 (POWERPC_FLAG_SPE)
3211 #define check_pow_e500 check_pow_hid0
3213 __attribute__ (( unused
))
3214 static void init_proc_e500 (CPUPPCState
*env
)
3219 /* Memory management */
3220 gen_spr_BookE_FSL(env
);
3221 #if !defined(CONFIG_USER_ONLY)
3226 init_excp_BookE(env
);
3227 env
->dcache_line_size
= 32;
3228 env
->icache_line_size
= 32;
3229 /* XXX: TODO: allocate internal IRQ controller */
3234 /* Non-embedded PowerPC */
3235 /* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
3236 #define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
3237 PPC_MEM_EIEIO | PPC_MEM_TLBIE)
3238 /* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */
3239 #define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
3240 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3241 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3242 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB | \
3245 /* POWER : same as 601, without mfmsr, mfsr */
3247 #define POWERPC_INSNS_POWER (XXX_TODO)
3248 /* POWER RSC (from RAD6000) */
3249 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
3253 #define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ | \
3254 PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR)
3255 #define POWERPC_MSRM_601 (0x000000000000FD70ULL)
3256 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
3257 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
3258 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
3259 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
3260 #define POWERPC_FLAG_601 (POWERPC_FLAG_SE)
3261 #define check_pow_601 check_pow_none
3263 static void init_proc_601 (CPUPPCState
*env
)
3265 gen_spr_ne_601(env
);
3267 /* Hardware implementation registers */
3268 /* XXX : not implemented */
3269 spr_register(env
, SPR_HID0
, "HID0",
3270 SPR_NOACCESS
, SPR_NOACCESS
,
3271 &spr_read_generic
, &spr_write_hid0_601
,
3273 /* XXX : not implemented */
3274 spr_register(env
, SPR_HID1
, "HID1",
3275 SPR_NOACCESS
, SPR_NOACCESS
,
3276 &spr_read_generic
, &spr_write_generic
,
3278 /* XXX : not implemented */
3279 spr_register(env
, SPR_601_HID2
, "HID2",
3280 SPR_NOACCESS
, SPR_NOACCESS
,
3281 &spr_read_generic
, &spr_write_generic
,
3283 /* XXX : not implemented */
3284 spr_register(env
, SPR_601_HID5
, "HID5",
3285 SPR_NOACCESS
, SPR_NOACCESS
,
3286 &spr_read_generic
, &spr_write_generic
,
3288 /* XXX : not implemented */
3289 spr_register(env
, SPR_601_HID15
, "HID15",
3290 SPR_NOACCESS
, SPR_NOACCESS
,
3291 &spr_read_generic
, &spr_write_generic
,
3293 /* Memory management */
3294 #if !defined(CONFIG_USER_ONLY)
3300 env
->dcache_line_size
= 64;
3301 env
->icache_line_size
= 64;
3302 /* Allocate hardware IRQ controller */
3303 ppc6xx_irq_init(env
);
3307 #define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \
3308 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3309 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3310 PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ |\
3311 PPC_SEGMENT | PPC_602_SPEC)
3312 #define POWERPC_MSRM_602 (0x000000000033FF73ULL)
3313 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
3314 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
3315 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
3316 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
3317 #define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3319 #define check_pow_602 check_pow_hid0
3321 static void init_proc_602 (CPUPPCState
*env
)
3323 gen_spr_ne_601(env
);
3327 /* hardware implementation registers */
3328 /* XXX : not implemented */
3329 spr_register(env
, SPR_HID0
, "HID0",
3330 SPR_NOACCESS
, SPR_NOACCESS
,
3331 &spr_read_generic
, &spr_write_generic
,
3333 /* XXX : not implemented */
3334 spr_register(env
, SPR_HID1
, "HID1",
3335 SPR_NOACCESS
, SPR_NOACCESS
,
3336 &spr_read_generic
, &spr_write_generic
,
3338 /* Memory management */
3340 gen_6xx_7xx_soft_tlb(env
, 64, 2);
3342 env
->dcache_line_size
= 32;
3343 env
->icache_line_size
= 32;
3344 /* Allocate hardware IRQ controller */
3345 ppc6xx_irq_init(env
);
3349 #define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3350 #define POWERPC_MSRM_603 (0x000000000007FF73ULL)
3351 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
3352 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
3353 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
3354 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
3355 #define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3357 #define check_pow_603 check_pow_hid0
3359 static void init_proc_603 (CPUPPCState
*env
)
3361 gen_spr_ne_601(env
);
3365 /* hardware implementation registers */
3366 /* XXX : not implemented */
3367 spr_register(env
, SPR_HID0
, "HID0",
3368 SPR_NOACCESS
, SPR_NOACCESS
,
3369 &spr_read_generic
, &spr_write_generic
,
3371 /* XXX : not implemented */
3372 spr_register(env
, SPR_HID1
, "HID1",
3373 SPR_NOACCESS
, SPR_NOACCESS
,
3374 &spr_read_generic
, &spr_write_generic
,
3376 /* Memory management */
3378 gen_6xx_7xx_soft_tlb(env
, 64, 2);
3380 env
->dcache_line_size
= 32;
3381 env
->icache_line_size
= 32;
3382 /* Allocate hardware IRQ controller */
3383 ppc6xx_irq_init(env
);
3387 #define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3388 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
3389 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
3390 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
3391 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
3392 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
3393 #define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3395 #define check_pow_603E check_pow_hid0
3397 static void init_proc_603E (CPUPPCState
*env
)
3399 gen_spr_ne_601(env
);
3403 /* hardware implementation registers */
3404 /* XXX : not implemented */
3405 spr_register(env
, SPR_HID0
, "HID0",
3406 SPR_NOACCESS
, SPR_NOACCESS
,
3407 &spr_read_generic
, &spr_write_generic
,
3409 /* XXX : not implemented */
3410 spr_register(env
, SPR_HID1
, "HID1",
3411 SPR_NOACCESS
, SPR_NOACCESS
,
3412 &spr_read_generic
, &spr_write_generic
,
3414 /* XXX : not implemented */
3415 spr_register(env
, SPR_IABR
, "IABR",
3416 SPR_NOACCESS
, SPR_NOACCESS
,
3417 &spr_read_generic
, &spr_write_generic
,
3419 /* Memory management */
3421 gen_6xx_7xx_soft_tlb(env
, 64, 2);
3423 env
->dcache_line_size
= 32;
3424 env
->icache_line_size
= 32;
3425 /* Allocate hardware IRQ controller */
3426 ppc6xx_irq_init(env
);
3430 #define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3431 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3432 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3433 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3434 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
3435 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
3436 #define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3438 #define check_pow_G2 check_pow_hid0
3440 static void init_proc_G2 (CPUPPCState
*env
)
3442 gen_spr_ne_601(env
);
3443 gen_spr_G2_755(env
);
3447 /* Hardware implementation register */
3448 /* XXX : not implemented */
3449 spr_register(env
, SPR_HID0
, "HID0",
3450 SPR_NOACCESS
, SPR_NOACCESS
,
3451 &spr_read_generic
, &spr_write_generic
,
3453 /* XXX : not implemented */
3454 spr_register(env
, SPR_HID1
, "HID1",
3455 SPR_NOACCESS
, SPR_NOACCESS
,
3456 &spr_read_generic
, &spr_write_generic
,
3458 /* XXX : not implemented */
3459 spr_register(env
, SPR_HID2
, "HID2",
3460 SPR_NOACCESS
, SPR_NOACCESS
,
3461 &spr_read_generic
, &spr_write_generic
,
3463 /* Memory management */
3466 gen_6xx_7xx_soft_tlb(env
, 64, 2);
3468 env
->dcache_line_size
= 32;
3469 env
->icache_line_size
= 32;
3470 /* Allocate hardware IRQ controller */
3471 ppc6xx_irq_init(env
);
3475 #define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3476 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3477 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3478 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3479 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
3480 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
3481 #define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3483 #define check_pow_G2LE check_pow_hid0
3485 static void init_proc_G2LE (CPUPPCState
*env
)
3487 gen_spr_ne_601(env
);
3488 gen_spr_G2_755(env
);
3492 /* Hardware implementation register */
3493 /* XXX : not implemented */
3494 spr_register(env
, SPR_HID0
, "HID0",
3495 SPR_NOACCESS
, SPR_NOACCESS
,
3496 &spr_read_generic
, &spr_write_generic
,
3498 /* XXX : not implemented */
3499 spr_register(env
, SPR_HID1
, "HID1",
3500 SPR_NOACCESS
, SPR_NOACCESS
,
3501 &spr_read_generic
, &spr_write_generic
,
3503 /* XXX : not implemented */
3504 spr_register(env
, SPR_HID2
, "HID2",
3505 SPR_NOACCESS
, SPR_NOACCESS
,
3506 &spr_read_generic
, &spr_write_generic
,
3508 /* Memory management */
3511 gen_6xx_7xx_soft_tlb(env
, 64, 2);
3513 env
->dcache_line_size
= 32;
3514 env
->icache_line_size
= 32;
3515 /* Allocate hardware IRQ controller */
3516 ppc6xx_irq_init(env
);
3520 #define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3521 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
3522 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
3523 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
3524 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
3525 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
3526 #define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3528 #define check_pow_604 check_pow_nocheck
3530 static void init_proc_604 (CPUPPCState
*env
)
3532 gen_spr_ne_601(env
);
3536 /* Hardware implementation registers */
3537 /* XXX : not implemented */
3538 spr_register(env
, SPR_HID0
, "HID0",
3539 SPR_NOACCESS
, SPR_NOACCESS
,
3540 &spr_read_generic
, &spr_write_generic
,
3542 /* XXX : not implemented */
3543 spr_register(env
, SPR_HID1
, "HID1",
3544 SPR_NOACCESS
, SPR_NOACCESS
,
3545 &spr_read_generic
, &spr_write_generic
,
3547 /* Memory management */
3550 env
->dcache_line_size
= 32;
3551 env
->icache_line_size
= 32;
3552 /* Allocate hardware IRQ controller */
3553 ppc6xx_irq_init(env
);
3556 /* PowerPC 740/750 (aka G3) */
3557 #define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3558 #define POWERPC_MSRM_7x0 (0x000000000005FF77ULL)
3559 #define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
3560 //#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
3561 #define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)
3562 #define POWERPC_BFDM_7x0 (bfd_mach_ppc_750)
3563 #define POWERPC_FLAG_7x0 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3565 #define check_pow_7x0 check_pow_hid0
3567 static void init_proc_7x0 (CPUPPCState
*env
)
3569 gen_spr_ne_601(env
);
3573 /* Thermal management */
3575 /* Hardware implementation registers */
3576 /* XXX : not implemented */
3577 spr_register(env
, SPR_HID0
, "HID0",
3578 SPR_NOACCESS
, SPR_NOACCESS
,
3579 &spr_read_generic
, &spr_write_generic
,
3581 /* XXX : not implemented */
3582 spr_register(env
, SPR_HID1
, "HID1",
3583 SPR_NOACCESS
, SPR_NOACCESS
,
3584 &spr_read_generic
, &spr_write_generic
,
3586 /* Memory management */
3589 env
->dcache_line_size
= 32;
3590 env
->icache_line_size
= 32;
3591 /* Allocate hardware IRQ controller */
3592 ppc6xx_irq_init(env
);
3595 /* PowerPC 750FX/GX */
3596 #define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN)
3597 #define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
3598 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
3599 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
3600 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
3601 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
3602 #define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3604 #define check_pow_750fx check_pow_hid0
3606 static void init_proc_750fx (CPUPPCState
*env
)
3608 gen_spr_ne_601(env
);
3612 /* Thermal management */
3614 /* Hardware implementation registers */
3615 /* XXX : not implemented */
3616 spr_register(env
, SPR_HID0
, "HID0",
3617 SPR_NOACCESS
, SPR_NOACCESS
,
3618 &spr_read_generic
, &spr_write_generic
,
3620 /* XXX : not implemented */
3621 spr_register(env
, SPR_HID1
, "HID1",
3622 SPR_NOACCESS
, SPR_NOACCESS
,
3623 &spr_read_generic
, &spr_write_generic
,
3625 /* XXX : not implemented */
3626 spr_register(env
, SPR_750_HID2
, "HID2",
3627 SPR_NOACCESS
, SPR_NOACCESS
,
3628 &spr_read_generic
, &spr_write_generic
,
3630 /* Memory management */
3632 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3634 init_excp_750FX(env
);
3635 env
->dcache_line_size
= 32;
3636 env
->icache_line_size
= 32;
3637 /* Allocate hardware IRQ controller */
3638 ppc6xx_irq_init(env
);
3641 /* PowerPC 745/755 */
3642 #define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
3643 #define POWERPC_MSRM_7x5 (0x000000000005FF77ULL)
3644 #define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
3645 //#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
3646 #define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)
3647 #define POWERPC_BFDM_7x5 (bfd_mach_ppc_750)
3648 #define POWERPC_FLAG_7x5 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3650 #define check_pow_7x5 check_pow_hid0
3652 static void init_proc_7x5 (CPUPPCState
*env
)
3654 gen_spr_ne_601(env
);
3655 gen_spr_G2_755(env
);
3658 /* L2 cache control */
3659 /* XXX : not implemented */
3660 spr_register(env
, SPR_ICTC
, "ICTC",
3661 SPR_NOACCESS
, SPR_NOACCESS
,
3662 &spr_read_generic
, &spr_write_generic
,
3664 /* XXX : not implemented */
3665 spr_register(env
, SPR_L2PMCR
, "L2PMCR",
3666 SPR_NOACCESS
, SPR_NOACCESS
,
3667 &spr_read_generic
, &spr_write_generic
,
3669 /* Hardware implementation registers */
3670 /* XXX : not implemented */
3671 spr_register(env
, SPR_HID0
, "HID0",
3672 SPR_NOACCESS
, SPR_NOACCESS
,
3673 &spr_read_generic
, &spr_write_generic
,
3675 /* XXX : not implemented */
3676 spr_register(env
, SPR_HID1
, "HID1",
3677 SPR_NOACCESS
, SPR_NOACCESS
,
3678 &spr_read_generic
, &spr_write_generic
,
3680 /* XXX : not implemented */
3681 spr_register(env
, SPR_HID2
, "HID2",
3682 SPR_NOACCESS
, SPR_NOACCESS
,
3683 &spr_read_generic
, &spr_write_generic
,
3685 /* Memory management */
3688 gen_6xx_7xx_soft_tlb(env
, 64, 2);
3690 env
->dcache_line_size
= 32;
3691 env
->icache_line_size
= 32;
3692 /* Allocate hardware IRQ controller */
3693 ppc6xx_irq_init(env
);
3694 #if !defined(CONFIG_USER_ONLY)
3695 /* Hardware reset vector */
3696 env
->hreset_vector
= 0xFFFFFFFCUL
;
3700 /* PowerPC 7400 (aka G4) */
3701 #define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3702 PPC_EXTERN | PPC_MEM_TLBIA | \
3704 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
3705 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
3706 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
3707 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
3708 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
3709 #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3710 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3711 #define check_pow_7400 check_pow_hid0
3713 static void init_proc_7400 (CPUPPCState
*env
)
3715 gen_spr_ne_601(env
);
3719 /* 74xx specific SPR */
3721 /* Thermal management */
3723 /* Memory management */
3725 init_excp_7400(env
);
3726 env
->dcache_line_size
= 32;
3727 env
->icache_line_size
= 32;
3728 /* Allocate hardware IRQ controller */
3729 ppc6xx_irq_init(env
);
3732 /* PowerPC 7410 (aka G4) */
3733 #define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3734 PPC_EXTERN | PPC_MEM_TLBIA | \
3736 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
3737 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
3738 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
3739 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
3740 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
3741 #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3742 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3743 #define check_pow_7410 check_pow_hid0
3745 static void init_proc_7410 (CPUPPCState
*env
)
3747 gen_spr_ne_601(env
);
3751 /* 74xx specific SPR */
3753 /* Thermal management */
3756 /* XXX : not implemented */
3757 spr_register(env
, SPR_L2PMCR
, "L2PMCR",
3758 SPR_NOACCESS
, SPR_NOACCESS
,
3759 &spr_read_generic
, &spr_write_generic
,
3762 /* XXX : not implemented */
3763 spr_register(env
, SPR_LDSTDB
, "LDSTDB",
3764 SPR_NOACCESS
, SPR_NOACCESS
,
3765 &spr_read_generic
, &spr_write_generic
,
3767 /* Memory management */
3769 init_excp_7400(env
);
3770 env
->dcache_line_size
= 32;
3771 env
->icache_line_size
= 32;
3772 /* Allocate hardware IRQ controller */
3773 ppc6xx_irq_init(env
);
3776 /* PowerPC 7440 (aka G4) */
3777 #define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3778 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3780 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
3781 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
3782 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
3783 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
3784 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
3785 #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3786 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3787 #define check_pow_7440 check_pow_hid0
3789 __attribute__ (( unused
))
3790 static void init_proc_7440 (CPUPPCState
*env
)
3792 gen_spr_ne_601(env
);
3796 /* 74xx specific SPR */
3799 /* XXX : not implemented */
3800 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
3801 SPR_NOACCESS
, SPR_NOACCESS
,
3802 &spr_read_generic
, &spr_write_generic
,
3805 /* XXX : not implemented */
3806 spr_register(env
, SPR_ICTRL
, "ICTRL",
3807 SPR_NOACCESS
, SPR_NOACCESS
,
3808 &spr_read_generic
, &spr_write_generic
,
3811 /* XXX : not implemented */
3812 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
3813 SPR_NOACCESS
, SPR_NOACCESS
,
3814 &spr_read_generic
, &spr_write_generic
,
3817 /* XXX : not implemented */
3818 spr_register(env
, SPR_PMC5
, "PMC5",
3819 SPR_NOACCESS
, SPR_NOACCESS
,
3820 &spr_read_generic
, &spr_write_generic
,
3822 /* XXX : not implemented */
3823 spr_register(env
, SPR_UPMC5
, "UPMC5",
3824 &spr_read_ureg
, SPR_NOACCESS
,
3825 &spr_read_ureg
, SPR_NOACCESS
,
3827 /* XXX : not implemented */
3828 spr_register(env
, SPR_PMC6
, "PMC6",
3829 SPR_NOACCESS
, SPR_NOACCESS
,
3830 &spr_read_generic
, &spr_write_generic
,
3832 /* XXX : not implemented */
3833 spr_register(env
, SPR_UPMC6
, "UPMC6",
3834 &spr_read_ureg
, SPR_NOACCESS
,
3835 &spr_read_ureg
, SPR_NOACCESS
,
3837 /* Memory management */
3839 gen_74xx_soft_tlb(env
, 128, 2);
3840 init_excp_7450(env
);
3841 env
->dcache_line_size
= 32;
3842 env
->icache_line_size
= 32;
3843 /* Allocate hardware IRQ controller */
3844 ppc6xx_irq_init(env
);
3847 /* PowerPC 7450 (aka G4) */
3848 #define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3849 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3851 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
3852 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
3853 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
3854 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
3855 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
3856 #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3857 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3858 #define check_pow_7450 check_pow_hid0
3860 __attribute__ (( unused
))
3861 static void init_proc_7450 (CPUPPCState
*env
)
3863 gen_spr_ne_601(env
);
3867 /* 74xx specific SPR */
3869 /* Level 3 cache control */
3872 /* XXX : not implemented */
3873 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
3874 SPR_NOACCESS
, SPR_NOACCESS
,
3875 &spr_read_generic
, &spr_write_generic
,
3878 /* XXX : not implemented */
3879 spr_register(env
, SPR_ICTRL
, "ICTRL",
3880 SPR_NOACCESS
, SPR_NOACCESS
,
3881 &spr_read_generic
, &spr_write_generic
,
3884 /* XXX : not implemented */
3885 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
3886 SPR_NOACCESS
, SPR_NOACCESS
,
3887 &spr_read_generic
, &spr_write_generic
,
3890 /* XXX : not implemented */
3891 spr_register(env
, SPR_PMC5
, "PMC5",
3892 SPR_NOACCESS
, SPR_NOACCESS
,
3893 &spr_read_generic
, &spr_write_generic
,
3895 /* XXX : not implemented */
3896 spr_register(env
, SPR_UPMC5
, "UPMC5",
3897 &spr_read_ureg
, SPR_NOACCESS
,
3898 &spr_read_ureg
, SPR_NOACCESS
,
3900 /* XXX : not implemented */
3901 spr_register(env
, SPR_PMC6
, "PMC6",
3902 SPR_NOACCESS
, SPR_NOACCESS
,
3903 &spr_read_generic
, &spr_write_generic
,
3905 /* XXX : not implemented */
3906 spr_register(env
, SPR_UPMC6
, "UPMC6",
3907 &spr_read_ureg
, SPR_NOACCESS
,
3908 &spr_read_ureg
, SPR_NOACCESS
,
3910 /* Memory management */
3912 gen_74xx_soft_tlb(env
, 128, 2);
3913 init_excp_7450(env
);
3914 env
->dcache_line_size
= 32;
3915 env
->icache_line_size
= 32;
3916 /* Allocate hardware IRQ controller */
3917 ppc6xx_irq_init(env
);
3920 /* PowerPC 7445 (aka G4) */
3921 #define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3922 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3924 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
3925 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
3926 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
3927 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
3928 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
3929 #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3930 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3931 #define check_pow_7445 check_pow_hid0
3933 __attribute__ (( unused
))
3934 static void init_proc_7445 (CPUPPCState
*env
)
3936 gen_spr_ne_601(env
);
3940 /* 74xx specific SPR */
3943 /* XXX : not implemented */
3944 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
3945 SPR_NOACCESS
, SPR_NOACCESS
,
3946 &spr_read_generic
, &spr_write_generic
,
3949 /* XXX : not implemented */
3950 spr_register(env
, SPR_ICTRL
, "ICTRL",
3951 SPR_NOACCESS
, SPR_NOACCESS
,
3952 &spr_read_generic
, &spr_write_generic
,
3955 /* XXX : not implemented */
3956 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
3957 SPR_NOACCESS
, SPR_NOACCESS
,
3958 &spr_read_generic
, &spr_write_generic
,
3961 /* XXX : not implemented */
3962 spr_register(env
, SPR_PMC5
, "PMC5",
3963 SPR_NOACCESS
, SPR_NOACCESS
,
3964 &spr_read_generic
, &spr_write_generic
,
3966 /* XXX : not implemented */
3967 spr_register(env
, SPR_UPMC5
, "UPMC5",
3968 &spr_read_ureg
, SPR_NOACCESS
,
3969 &spr_read_ureg
, SPR_NOACCESS
,
3971 /* XXX : not implemented */
3972 spr_register(env
, SPR_PMC6
, "PMC6",
3973 SPR_NOACCESS
, SPR_NOACCESS
,
3974 &spr_read_generic
, &spr_write_generic
,
3976 /* XXX : not implemented */
3977 spr_register(env
, SPR_UPMC6
, "UPMC6",
3978 &spr_read_ureg
, SPR_NOACCESS
,
3979 &spr_read_ureg
, SPR_NOACCESS
,
3982 spr_register(env
, SPR_SPRG4
, "SPRG4",
3983 SPR_NOACCESS
, SPR_NOACCESS
,
3984 &spr_read_generic
, &spr_write_generic
,
3986 spr_register(env
, SPR_USPRG4
, "USPRG4",
3987 &spr_read_ureg
, SPR_NOACCESS
,
3988 &spr_read_ureg
, SPR_NOACCESS
,
3990 spr_register(env
, SPR_SPRG5
, "SPRG5",
3991 SPR_NOACCESS
, SPR_NOACCESS
,
3992 &spr_read_generic
, &spr_write_generic
,
3994 spr_register(env
, SPR_USPRG5
, "USPRG5",
3995 &spr_read_ureg
, SPR_NOACCESS
,
3996 &spr_read_ureg
, SPR_NOACCESS
,
3998 spr_register(env
, SPR_SPRG6
, "SPRG6",
3999 SPR_NOACCESS
, SPR_NOACCESS
,
4000 &spr_read_generic
, &spr_write_generic
,
4002 spr_register(env
, SPR_USPRG6
, "USPRG6",
4003 &spr_read_ureg
, SPR_NOACCESS
,
4004 &spr_read_ureg
, SPR_NOACCESS
,
4006 spr_register(env
, SPR_SPRG7
, "SPRG7",
4007 SPR_NOACCESS
, SPR_NOACCESS
,
4008 &spr_read_generic
, &spr_write_generic
,
4010 spr_register(env
, SPR_USPRG7
, "USPRG7",
4011 &spr_read_ureg
, SPR_NOACCESS
,
4012 &spr_read_ureg
, SPR_NOACCESS
,
4014 /* Memory management */
4017 gen_74xx_soft_tlb(env
, 128, 2);
4018 init_excp_7450(env
);
4019 env
->dcache_line_size
= 32;
4020 env
->icache_line_size
= 32;
4021 /* Allocate hardware IRQ controller */
4022 ppc6xx_irq_init(env
);
4025 /* PowerPC 7455 (aka G4) */
4026 #define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
4027 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
4029 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
4030 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
4031 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
4032 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
4033 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
4034 #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4035 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4036 #define check_pow_7455 check_pow_hid0
4038 __attribute__ (( unused
))
4039 static void init_proc_7455 (CPUPPCState
*env
)
4041 gen_spr_ne_601(env
);
4045 /* 74xx specific SPR */
4047 /* Level 3 cache control */
4050 /* XXX : not implemented */
4051 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
4052 SPR_NOACCESS
, SPR_NOACCESS
,
4053 &spr_read_generic
, &spr_write_generic
,
4056 /* XXX : not implemented */
4057 spr_register(env
, SPR_ICTRL
, "ICTRL",
4058 SPR_NOACCESS
, SPR_NOACCESS
,
4059 &spr_read_generic
, &spr_write_generic
,
4062 /* XXX : not implemented */
4063 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
4064 SPR_NOACCESS
, SPR_NOACCESS
,
4065 &spr_read_generic
, &spr_write_generic
,
4068 /* XXX : not implemented */
4069 spr_register(env
, SPR_PMC5
, "PMC5",
4070 SPR_NOACCESS
, SPR_NOACCESS
,
4071 &spr_read_generic
, &spr_write_generic
,
4073 /* XXX : not implemented */
4074 spr_register(env
, SPR_UPMC5
, "UPMC5",
4075 &spr_read_ureg
, SPR_NOACCESS
,
4076 &spr_read_ureg
, SPR_NOACCESS
,
4078 /* XXX : not implemented */
4079 spr_register(env
, SPR_PMC6
, "PMC6",
4080 SPR_NOACCESS
, SPR_NOACCESS
,
4081 &spr_read_generic
, &spr_write_generic
,
4083 /* XXX : not implemented */
4084 spr_register(env
, SPR_UPMC6
, "UPMC6",
4085 &spr_read_ureg
, SPR_NOACCESS
,
4086 &spr_read_ureg
, SPR_NOACCESS
,
4089 spr_register(env
, SPR_SPRG4
, "SPRG4",
4090 SPR_NOACCESS
, SPR_NOACCESS
,
4091 &spr_read_generic
, &spr_write_generic
,
4093 spr_register(env
, SPR_USPRG4
, "USPRG4",
4094 &spr_read_ureg
, SPR_NOACCESS
,
4095 &spr_read_ureg
, SPR_NOACCESS
,
4097 spr_register(env
, SPR_SPRG5
, "SPRG5",
4098 SPR_NOACCESS
, SPR_NOACCESS
,
4099 &spr_read_generic
, &spr_write_generic
,
4101 spr_register(env
, SPR_USPRG5
, "USPRG5",
4102 &spr_read_ureg
, SPR_NOACCESS
,
4103 &spr_read_ureg
, SPR_NOACCESS
,
4105 spr_register(env
, SPR_SPRG6
, "SPRG6",
4106 SPR_NOACCESS
, SPR_NOACCESS
,
4107 &spr_read_generic
, &spr_write_generic
,
4109 spr_register(env
, SPR_USPRG6
, "USPRG6",
4110 &spr_read_ureg
, SPR_NOACCESS
,
4111 &spr_read_ureg
, SPR_NOACCESS
,
4113 spr_register(env
, SPR_SPRG7
, "SPRG7",
4114 SPR_NOACCESS
, SPR_NOACCESS
,
4115 &spr_read_generic
, &spr_write_generic
,
4117 spr_register(env
, SPR_USPRG7
, "USPRG7",
4118 &spr_read_ureg
, SPR_NOACCESS
,
4119 &spr_read_ureg
, SPR_NOACCESS
,
4121 /* Memory management */
4124 gen_74xx_soft_tlb(env
, 128, 2);
4125 init_excp_7450(env
);
4126 env
->dcache_line_size
= 32;
4127 env
->icache_line_size
= 32;
4128 /* Allocate hardware IRQ controller */
4129 ppc6xx_irq_init(env
);
4132 #if defined (TARGET_PPC64)
4133 #define POWERPC_INSNS_WORK64 (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
4134 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
4135 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
4136 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB)
4138 #define POWERPC_INSNS_970 (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4139 PPC_64B | PPC_ALTIVEC | \
4140 PPC_SEGMENT_64B | PPC_SLBI)
4141 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
4142 #define POWERPC_MMU_970 (POWERPC_MMU_64B)
4143 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
4144 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
4145 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
4146 #define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4147 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4149 #if defined(CONFIG_USER_ONLY)
4150 #define POWERPC970_HID5_INIT 0x00000080
4152 #define POWERPC970_HID5_INIT 0x00000000
4155 static int check_pow_970 (CPUPPCState
*env
)
4157 if (env
->spr
[SPR_HID0
] & 0x00600000)
4163 static void init_proc_970 (CPUPPCState
*env
)
4165 gen_spr_ne_601(env
);
4169 /* Hardware implementation registers */
4170 /* XXX : not implemented */
4171 spr_register(env
, SPR_HID0
, "HID0",
4172 SPR_NOACCESS
, SPR_NOACCESS
,
4173 &spr_read_generic
, &spr_write_clear
,
4175 /* XXX : not implemented */
4176 spr_register(env
, SPR_HID1
, "HID1",
4177 SPR_NOACCESS
, SPR_NOACCESS
,
4178 &spr_read_generic
, &spr_write_generic
,
4180 /* XXX : not implemented */
4181 spr_register(env
, SPR_750_HID2
, "HID2",
4182 SPR_NOACCESS
, SPR_NOACCESS
,
4183 &spr_read_generic
, &spr_write_generic
,
4185 /* XXX : not implemented */
4186 spr_register(env
, SPR_970_HID5
, "HID5",
4187 SPR_NOACCESS
, SPR_NOACCESS
,
4188 &spr_read_generic
, &spr_write_generic
,
4189 POWERPC970_HID5_INIT
);
4190 /* Memory management */
4191 /* XXX: not correct */
4193 /* XXX : not implemented */
4194 spr_register(env
, SPR_MMUCFG
, "MMUCFG",
4195 SPR_NOACCESS
, SPR_NOACCESS
,
4196 &spr_read_generic
, SPR_NOACCESS
,
4197 0x00000000); /* TOFIX */
4198 /* XXX : not implemented */
4199 spr_register(env
, SPR_MMUCSR0
, "MMUCSR0",
4200 SPR_NOACCESS
, SPR_NOACCESS
,
4201 &spr_read_generic
, &spr_write_generic
,
4202 0x00000000); /* TOFIX */
4203 spr_register(env
, SPR_HIOR
, "SPR_HIOR",
4204 SPR_NOACCESS
, SPR_NOACCESS
,
4205 &spr_read_generic
, &spr_write_generic
,
4206 0xFFF00000); /* XXX: This is a hack */
4207 #if !defined(CONFIG_USER_ONLY)
4211 env
->dcache_line_size
= 128;
4212 env
->icache_line_size
= 128;
4213 /* Allocate hardware IRQ controller */
4214 ppc970_irq_init(env
);
4217 /* PowerPC 970FX (aka G5) */
4218 #define POWERPC_INSNS_970FX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4219 PPC_64B | PPC_ALTIVEC | \
4220 PPC_SEGMENT_64B | PPC_SLBI)
4221 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
4222 #define POWERPC_MMU_970FX (POWERPC_MMU_64B)
4223 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
4224 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
4225 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
4226 #define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4227 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4229 static int check_pow_970FX (CPUPPCState
*env
)
4231 if (env
->spr
[SPR_HID0
] & 0x00600000)
4237 static void init_proc_970FX (CPUPPCState
*env
)
4239 gen_spr_ne_601(env
);
4243 /* Hardware implementation registers */
4244 /* XXX : not implemented */
4245 spr_register(env
, SPR_HID0
, "HID0",
4246 SPR_NOACCESS
, SPR_NOACCESS
,
4247 &spr_read_generic
, &spr_write_clear
,
4249 /* XXX : not implemented */
4250 spr_register(env
, SPR_HID1
, "HID1",
4251 SPR_NOACCESS
, SPR_NOACCESS
,
4252 &spr_read_generic
, &spr_write_generic
,
4254 /* XXX : not implemented */
4255 spr_register(env
, SPR_750_HID2
, "HID2",
4256 SPR_NOACCESS
, SPR_NOACCESS
,
4257 &spr_read_generic
, &spr_write_generic
,
4259 /* XXX : not implemented */
4260 spr_register(env
, SPR_970_HID5
, "HID5",
4261 SPR_NOACCESS
, SPR_NOACCESS
,
4262 &spr_read_generic
, &spr_write_generic
,
4263 POWERPC970_HID5_INIT
);
4264 /* Memory management */
4265 /* XXX: not correct */
4267 /* XXX : not implemented */
4268 spr_register(env
, SPR_MMUCFG
, "MMUCFG",
4269 SPR_NOACCESS
, SPR_NOACCESS
,
4270 &spr_read_generic
, SPR_NOACCESS
,
4271 0x00000000); /* TOFIX */
4272 /* XXX : not implemented */
4273 spr_register(env
, SPR_MMUCSR0
, "MMUCSR0",
4274 SPR_NOACCESS
, SPR_NOACCESS
,
4275 &spr_read_generic
, &spr_write_generic
,
4276 0x00000000); /* TOFIX */
4277 spr_register(env
, SPR_HIOR
, "SPR_HIOR",
4278 SPR_NOACCESS
, SPR_NOACCESS
,
4279 &spr_read_generic
, &spr_write_generic
,
4280 0xFFF00000); /* XXX: This is a hack */
4281 #if !defined(CONFIG_USER_ONLY)
4285 env
->dcache_line_size
= 128;
4286 env
->icache_line_size
= 128;
4287 /* Allocate hardware IRQ controller */
4288 ppc970_irq_init(env
);
4291 /* PowerPC 970 GX */
4292 #define POWERPC_INSNS_970GX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4293 PPC_64B | PPC_ALTIVEC | \
4294 PPC_SEGMENT_64B | PPC_SLBI)
4295 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
4296 #define POWERPC_MMU_970GX (POWERPC_MMU_64B)
4297 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
4298 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
4299 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
4300 #define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4301 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4303 static int check_pow_970GX (CPUPPCState
*env
)
4305 if (env
->spr
[SPR_HID0
] & 0x00600000)
4311 static void init_proc_970GX (CPUPPCState
*env
)
4313 gen_spr_ne_601(env
);
4317 /* Hardware implementation registers */
4318 /* XXX : not implemented */
4319 spr_register(env
, SPR_HID0
, "HID0",
4320 SPR_NOACCESS
, SPR_NOACCESS
,
4321 &spr_read_generic
, &spr_write_clear
,
4323 /* XXX : not implemented */
4324 spr_register(env
, SPR_HID1
, "HID1",
4325 SPR_NOACCESS
, SPR_NOACCESS
,
4326 &spr_read_generic
, &spr_write_generic
,
4328 /* XXX : not implemented */
4329 spr_register(env
, SPR_750_HID2
, "HID2",
4330 SPR_NOACCESS
, SPR_NOACCESS
,
4331 &spr_read_generic
, &spr_write_generic
,
4333 /* XXX : not implemented */
4334 spr_register(env
, SPR_970_HID5
, "HID5",
4335 SPR_NOACCESS
, SPR_NOACCESS
,
4336 &spr_read_generic
, &spr_write_generic
,
4337 POWERPC970_HID5_INIT
);
4338 /* Memory management */
4339 /* XXX: not correct */
4341 /* XXX : not implemented */
4342 spr_register(env
, SPR_MMUCFG
, "MMUCFG",
4343 SPR_NOACCESS
, SPR_NOACCESS
,
4344 &spr_read_generic
, SPR_NOACCESS
,
4345 0x00000000); /* TOFIX */
4346 /* XXX : not implemented */
4347 spr_register(env
, SPR_MMUCSR0
, "MMUCSR0",
4348 SPR_NOACCESS
, SPR_NOACCESS
,
4349 &spr_read_generic
, &spr_write_generic
,
4350 0x00000000); /* TOFIX */
4351 spr_register(env
, SPR_HIOR
, "SPR_HIOR",
4352 SPR_NOACCESS
, SPR_NOACCESS
,
4353 &spr_read_generic
, &spr_write_generic
,
4354 0xFFF00000); /* XXX: This is a hack */
4355 #if !defined(CONFIG_USER_ONLY)
4359 env
->dcache_line_size
= 128;
4360 env
->icache_line_size
= 128;
4361 /* Allocate hardware IRQ controller */
4362 ppc970_irq_init(env
);
4365 /* PowerPC 970 MP */
4366 #define POWERPC_INSNS_970MP (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4367 PPC_64B | PPC_ALTIVEC | \
4368 PPC_SEGMENT_64B | PPC_SLBI)
4369 #define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
4370 #define POWERPC_MMU_970MP (POWERPC_MMU_64B)
4371 #define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
4372 #define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
4373 #define POWERPC_BFDM_970MP (bfd_mach_ppc64)
4374 #define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4375 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4377 static int check_pow_970MP (CPUPPCState
*env
)
4379 if (env
->spr
[SPR_HID0
] & 0x01C00000)
4385 static void init_proc_970MP (CPUPPCState
*env
)
4387 gen_spr_ne_601(env
);
4391 /* Hardware implementation registers */
4392 /* XXX : not implemented */
4393 spr_register(env
, SPR_HID0
, "HID0",
4394 SPR_NOACCESS
, SPR_NOACCESS
,
4395 &spr_read_generic
, &spr_write_clear
,
4397 /* XXX : not implemented */
4398 spr_register(env
, SPR_HID1
, "HID1",
4399 SPR_NOACCESS
, SPR_NOACCESS
,
4400 &spr_read_generic
, &spr_write_generic
,
4402 /* XXX : not implemented */
4403 spr_register(env
, SPR_750_HID2
, "HID2",
4404 SPR_NOACCESS
, SPR_NOACCESS
,
4405 &spr_read_generic
, &spr_write_generic
,
4407 /* XXX : not implemented */
4408 spr_register(env
, SPR_970_HID5
, "HID5",
4409 SPR_NOACCESS
, SPR_NOACCESS
,
4410 &spr_read_generic
, &spr_write_generic
,
4411 POWERPC970_HID5_INIT
);
4412 /* Memory management */
4413 /* XXX: not correct */
4415 /* XXX : not implemented */
4416 spr_register(env
, SPR_MMUCFG
, "MMUCFG",
4417 SPR_NOACCESS
, SPR_NOACCESS
,
4418 &spr_read_generic
, SPR_NOACCESS
,
4419 0x00000000); /* TOFIX */
4420 /* XXX : not implemented */
4421 spr_register(env
, SPR_MMUCSR0
, "MMUCSR0",
4422 SPR_NOACCESS
, SPR_NOACCESS
,
4423 &spr_read_generic
, &spr_write_generic
,
4424 0x00000000); /* TOFIX */
4425 spr_register(env
, SPR_HIOR
, "SPR_HIOR",
4426 SPR_NOACCESS
, SPR_NOACCESS
,
4427 &spr_read_generic
, &spr_write_generic
,
4428 0xFFF00000); /* XXX: This is a hack */
4429 #if !defined(CONFIG_USER_ONLY)
4433 env
->dcache_line_size
= 128;
4434 env
->icache_line_size
= 128;
4435 /* Allocate hardware IRQ controller */
4436 ppc970_irq_init(env
);
4440 #define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
4442 #define POWERPC_MSRM_620 (0x800000000005FF73ULL)
4443 #define POWERPC_MMU_620 (POWERPC_MMU_64B)
4444 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
4445 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
4446 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
4447 #define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE)
4448 #define check_pow_620 check_pow_nocheck /* Check this */
4450 __attribute__ (( unused
))
4451 static void init_proc_620 (CPUPPCState
*env
)
4453 gen_spr_ne_601(env
);
4457 /* Hardware implementation registers */
4458 /* XXX : not implemented */
4459 spr_register(env
, SPR_HID0
, "HID0",
4460 SPR_NOACCESS
, SPR_NOACCESS
,
4461 &spr_read_generic
, &spr_write_generic
,
4463 /* Memory management */
4467 env
->dcache_line_size
= 64;
4468 env
->icache_line_size
= 64;
4469 /* Allocate hardware IRQ controller */
4470 ppc6xx_irq_init(env
);
4472 #endif /* defined (TARGET_PPC64) */
4474 /* Default 32 bits PowerPC target will be 604 */
4475 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
4476 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
4477 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
4478 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
4479 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
4480 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
4481 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
4482 #define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
4483 #define check_pow_PPC32 check_pow_604
4484 #define init_proc_PPC32 init_proc_604
4486 /* Default 64 bits PowerPC target will be 970 FX */
4487 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
4488 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
4489 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
4490 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
4491 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
4492 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
4493 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
4494 #define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
4495 #define check_pow_PPC64 check_pow_970FX
4496 #define init_proc_PPC64 init_proc_970FX
4498 /* Default PowerPC target will be PowerPC 32 */
4499 #if defined (TARGET_PPC64) && 0 // XXX: TODO
4500 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
4501 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
4502 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
4503 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
4504 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
4505 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
4506 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
4507 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
4508 #define check_pow_DEFAULT check_pow_PPC64
4509 #define init_proc_DEFAULT init_proc_PPC64
4511 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
4512 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
4513 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
4514 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
4515 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
4516 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
4517 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
4518 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
4519 #define check_pow_DEFAULT check_pow_PPC32
4520 #define init_proc_DEFAULT init_proc_PPC32
4523 /*****************************************************************************/
4524 /* PVR definitions for most known PowerPC */
4526 /* PowerPC 401 family */
4527 /* Generic PowerPC 401 */
4528 #define CPU_POWERPC_401 CPU_POWERPC_401G2
4529 /* PowerPC 401 cores */
4530 CPU_POWERPC_401A1
= 0x00210000,
4531 CPU_POWERPC_401B2
= 0x00220000,
4533 CPU_POWERPC_401B3
= xxx
,
4535 CPU_POWERPC_401C2
= 0x00230000,
4536 CPU_POWERPC_401D2
= 0x00240000,
4537 CPU_POWERPC_401E2
= 0x00250000,
4538 CPU_POWERPC_401F2
= 0x00260000,
4539 CPU_POWERPC_401G2
= 0x00270000,
4540 /* PowerPC 401 microcontrolers */
4542 CPU_POWERPC_401GF
= xxx
,
4544 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
4545 /* IBM Processor for Network Resources */
4546 CPU_POWERPC_COBRA
= 0x10100000, /* XXX: 405 ? */
4548 CPU_POWERPC_XIPCHIP
= xxx
,
4550 /* PowerPC 403 family */
4551 /* Generic PowerPC 403 */
4552 #define CPU_POWERPC_403 CPU_POWERPC_403GC
4553 /* PowerPC 403 microcontrollers */
4554 CPU_POWERPC_403GA
= 0x00200011,
4555 CPU_POWERPC_403GB
= 0x00200100,
4556 CPU_POWERPC_403GC
= 0x00200200,
4557 CPU_POWERPC_403GCX
= 0x00201400,
4559 CPU_POWERPC_403GP
= xxx
,
4561 /* PowerPC 405 family */
4562 /* Generic PowerPC 405 */
4563 #define CPU_POWERPC_405 CPU_POWERPC_405D4
4564 /* PowerPC 405 cores */
4566 CPU_POWERPC_405A3
= xxx
,
4569 CPU_POWERPC_405A4
= xxx
,
4572 CPU_POWERPC_405B3
= xxx
,
4575 CPU_POWERPC_405B4
= xxx
,
4578 CPU_POWERPC_405C3
= xxx
,
4581 CPU_POWERPC_405C4
= xxx
,
4583 CPU_POWERPC_405D2
= 0x20010000,
4585 CPU_POWERPC_405D3
= xxx
,
4587 CPU_POWERPC_405D4
= 0x41810000,
4589 CPU_POWERPC_405D5
= xxx
,
4592 CPU_POWERPC_405E4
= xxx
,
4595 CPU_POWERPC_405F4
= xxx
,
4598 CPU_POWERPC_405F5
= xxx
,
4601 CPU_POWERPC_405F6
= xxx
,
4603 /* PowerPC 405 microcontrolers */
4604 /* XXX: missing 0x200108a0 */
4605 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
4606 CPU_POWERPC_405CRa
= 0x40110041,
4607 CPU_POWERPC_405CRb
= 0x401100C5,
4608 CPU_POWERPC_405CRc
= 0x40110145,
4609 CPU_POWERPC_405EP
= 0x51210950,
4611 CPU_POWERPC_405EXr
= xxx
,
4613 CPU_POWERPC_405EZ
= 0x41511460, /* 0x51210950 ? */
4615 CPU_POWERPC_405FX
= xxx
,
4617 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
4618 CPU_POWERPC_405GPa
= 0x40110000,
4619 CPU_POWERPC_405GPb
= 0x40110040,
4620 CPU_POWERPC_405GPc
= 0x40110082,
4621 CPU_POWERPC_405GPd
= 0x401100C4,
4622 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
4623 CPU_POWERPC_405GPR
= 0x50910951,
4625 CPU_POWERPC_405H
= xxx
,
4628 CPU_POWERPC_405L
= xxx
,
4630 CPU_POWERPC_405LP
= 0x41F10000,
4632 CPU_POWERPC_405PM
= xxx
,
4635 CPU_POWERPC_405PS
= xxx
,
4638 CPU_POWERPC_405S
= xxx
,
4640 /* IBM network processors */
4641 CPU_POWERPC_NPE405H
= 0x414100C0,
4642 CPU_POWERPC_NPE405H2
= 0x41410140,
4643 CPU_POWERPC_NPE405L
= 0x416100C0,
4644 CPU_POWERPC_NPE4GS3
= 0x40B10000,
4646 CPU_POWERPC_NPCxx1
= xxx
,
4649 CPU_POWERPC_NPR161
= xxx
,
4652 CPU_POWERPC_LC77700
= xxx
,
4654 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
4656 CPU_POWERPC_STB01000
= xxx
,
4659 CPU_POWERPC_STB01010
= xxx
,
4662 CPU_POWERPC_STB0210
= xxx
, /* 401B3 */
4664 CPU_POWERPC_STB03
= 0x40310000, /* 0x40130000 ? */
4666 CPU_POWERPC_STB043
= xxx
,
4669 CPU_POWERPC_STB045
= xxx
,
4671 CPU_POWERPC_STB04
= 0x41810000,
4672 CPU_POWERPC_STB25
= 0x51510950,
4674 CPU_POWERPC_STB130
= xxx
,
4677 CPU_POWERPC_X2VP4
= 0x20010820,
4678 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
4679 CPU_POWERPC_X2VP20
= 0x20010860,
4680 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
4682 CPU_POWERPC_ZL10310
= xxx
,
4685 CPU_POWERPC_ZL10311
= xxx
,
4688 CPU_POWERPC_ZL10320
= xxx
,
4691 CPU_POWERPC_ZL10321
= xxx
,
4693 /* PowerPC 440 family */
4694 /* Generic PowerPC 440 */
4695 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
4696 /* PowerPC 440 cores */
4698 CPU_POWERPC_440A4
= xxx
,
4701 CPU_POWERPC_440A5
= xxx
,
4704 CPU_POWERPC_440B4
= xxx
,
4707 CPU_POWERPC_440F5
= xxx
,
4710 CPU_POWERPC_440G5
= xxx
,
4713 CPU_POWERPC_440H4
= xxx
,
4716 CPU_POWERPC_440H6
= xxx
,
4718 /* PowerPC 440 microcontrolers */
4719 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
4720 CPU_POWERPC_440EPa
= 0x42221850,
4721 CPU_POWERPC_440EPb
= 0x422218D3,
4722 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
4723 CPU_POWERPC_440GPb
= 0x40120440,
4724 CPU_POWERPC_440GPc
= 0x40120481,
4725 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
4726 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
4727 CPU_POWERPC_440GRX
= 0x200008D0,
4728 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
4729 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
4730 CPU_POWERPC_440GXa
= 0x51B21850,
4731 CPU_POWERPC_440GXb
= 0x51B21851,
4732 CPU_POWERPC_440GXc
= 0x51B21892,
4733 CPU_POWERPC_440GXf
= 0x51B21894,
4735 CPU_POWERPC_440S
= xxx
,
4737 CPU_POWERPC_440SP
= 0x53221850,
4738 CPU_POWERPC_440SP2
= 0x53221891,
4739 CPU_POWERPC_440SPE
= 0x53421890,
4740 /* PowerPC 460 family */
4742 /* Generic PowerPC 464 */
4743 #define CPU_POWERPC_464 CPU_POWERPC_464H90
4745 /* PowerPC 464 microcontrolers */
4747 CPU_POWERPC_464H90
= xxx
,
4750 CPU_POWERPC_464H90FP
= xxx
,
4752 /* Freescale embedded PowerPC cores */
4754 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
4756 CPU_POWERPC_e200z0
= xxx
,
4759 CPU_POWERPC_e200z3
= xxx
,
4761 CPU_POWERPC_e200z5
= 0x81000000,
4762 CPU_POWERPC_e200z6
= 0x81120000,
4764 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
4765 CPU_POWERPC_e300c1
= 0x00830000,
4766 CPU_POWERPC_e300c2
= 0x00840000,
4767 CPU_POWERPC_e300c3
= 0x00850000,
4769 #define CPU_POWERPC_e500 CPU_POWERPC_e500_v22
4770 CPU_POWERPC_e500_v11
= 0x80200010,
4771 CPU_POWERPC_e500_v12
= 0x80200020,
4772 CPU_POWERPC_e500_v21
= 0x80210010,
4773 CPU_POWERPC_e500_v22
= 0x80210020,
4775 CPU_POWERPC_e500mc
= xxx
,
4778 CPU_POWERPC_e600
= 0x80040010,
4779 /* PowerPC MPC 5xx cores */
4780 CPU_POWERPC_5xx
= 0x00020020,
4781 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
4782 CPU_POWERPC_8xx
= 0x00500000,
4783 /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
4784 CPU_POWERPC_82xx_HIP3
= 0x00810101,
4785 CPU_POWERPC_82xx_HIP4
= 0x80811014,
4786 CPU_POWERPC_827x
= 0x80822013,
4787 /* PowerPC 6xx cores */
4788 CPU_POWERPC_601
= 0x00010001,
4789 CPU_POWERPC_601a
= 0x00010002,
4790 CPU_POWERPC_602
= 0x00050100,
4791 CPU_POWERPC_603
= 0x00030100,
4792 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
4793 CPU_POWERPC_603E_v11
= 0x00060101,
4794 CPU_POWERPC_603E_v12
= 0x00060102,
4795 CPU_POWERPC_603E_v13
= 0x00060103,
4796 CPU_POWERPC_603E_v14
= 0x00060104,
4797 CPU_POWERPC_603E_v22
= 0x00060202,
4798 CPU_POWERPC_603E_v3
= 0x00060300,
4799 CPU_POWERPC_603E_v4
= 0x00060400,
4800 CPU_POWERPC_603E_v41
= 0x00060401,
4801 CPU_POWERPC_603E7t
= 0x00071201,
4802 CPU_POWERPC_603E7v
= 0x00070100,
4803 CPU_POWERPC_603E7v1
= 0x00070101,
4804 CPU_POWERPC_603E7v2
= 0x00070201,
4805 CPU_POWERPC_603E7
= 0x00070200,
4806 CPU_POWERPC_603P
= 0x00070000,
4807 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
4808 CPU_POWERPC_G2
= 0x00810011,
4809 #if 0 // Linux pretends the MSB is zero...
4810 CPU_POWERPC_G2H4
= 0x80811010,
4811 CPU_POWERPC_G2gp
= 0x80821010,
4812 CPU_POWERPC_G2ls
= 0x90810010,
4813 CPU_POWERPC_G2LE
= 0x80820010,
4814 CPU_POWERPC_G2LEgp
= 0x80822010,
4815 CPU_POWERPC_G2LEls
= 0xA0822010,
4817 CPU_POWERPC_G2H4
= 0x00811010,
4818 CPU_POWERPC_G2gp
= 0x00821010,
4819 CPU_POWERPC_G2ls
= 0x10810010,
4820 CPU_POWERPC_G2LE
= 0x00820010,
4821 CPU_POWERPC_G2LEgp
= 0x00822010,
4822 CPU_POWERPC_G2LEls
= 0x20822010,
4824 CPU_POWERPC_604
= 0x00040103,
4825 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
4826 CPU_POWERPC_604E_v10
= 0x00090100, /* Also 2110 & 2120 */
4827 CPU_POWERPC_604E_v22
= 0x00090202,
4828 CPU_POWERPC_604E_v24
= 0x00090204,
4829 CPU_POWERPC_604R
= 0x000a0101, /* Also 0x00093102 */
4831 CPU_POWERPC_604EV
= xxx
,
4833 /* PowerPC 740/750 cores (aka G3) */
4834 /* XXX: missing 0x00084202 */
4835 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
4836 CPU_POWERPC_7x0_v20
= 0x00080200,
4837 CPU_POWERPC_7x0_v21
= 0x00080201,
4838 CPU_POWERPC_7x0_v22
= 0x00080202,
4839 CPU_POWERPC_7x0_v30
= 0x00080300,
4840 CPU_POWERPC_7x0_v31
= 0x00080301,
4841 CPU_POWERPC_740E
= 0x00080100,
4842 CPU_POWERPC_7x0P
= 0x10080000,
4843 /* XXX: missing 0x00087010 (CL ?) */
4844 CPU_POWERPC_750CL
= 0x00087200,
4845 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
4846 CPU_POWERPC_750CX_v21
= 0x00082201,
4847 CPU_POWERPC_750CX_v22
= 0x00082202,
4848 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
4849 CPU_POWERPC_750CXE_v21
= 0x00082211,
4850 CPU_POWERPC_750CXE_v22
= 0x00082212,
4851 CPU_POWERPC_750CXE_v23
= 0x00082213,
4852 CPU_POWERPC_750CXE_v24
= 0x00082214,
4853 CPU_POWERPC_750CXE_v24b
= 0x00083214,
4854 CPU_POWERPC_750CXE_v31
= 0x00083211,
4855 CPU_POWERPC_750CXE_v31b
= 0x00083311,
4856 CPU_POWERPC_750CXR
= 0x00083410,
4857 CPU_POWERPC_750E
= 0x00080200,
4858 CPU_POWERPC_750FL
= 0x700A0203,
4859 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
4860 CPU_POWERPC_750FX_v10
= 0x70000100,
4861 CPU_POWERPC_750FX_v20
= 0x70000200,
4862 CPU_POWERPC_750FX_v21
= 0x70000201,
4863 CPU_POWERPC_750FX_v22
= 0x70000202,
4864 CPU_POWERPC_750FX_v23
= 0x70000203,
4865 CPU_POWERPC_750GL
= 0x70020102,
4866 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
4867 CPU_POWERPC_750GX_v10
= 0x70020100,
4868 CPU_POWERPC_750GX_v11
= 0x70020101,
4869 CPU_POWERPC_750GX_v12
= 0x70020102,
4870 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
4871 CPU_POWERPC_750L_v22
= 0x00088202,
4872 CPU_POWERPC_750L_v30
= 0x00088300,
4873 CPU_POWERPC_750L_v32
= 0x00088302,
4874 /* PowerPC 745/755 cores */
4875 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
4876 CPU_POWERPC_7x5_v10
= 0x00083100,
4877 CPU_POWERPC_7x5_v11
= 0x00083101,
4878 CPU_POWERPC_7x5_v20
= 0x00083200,
4879 CPU_POWERPC_7x5_v21
= 0x00083201,
4880 CPU_POWERPC_7x5_v22
= 0x00083202, /* aka D */
4881 CPU_POWERPC_7x5_v23
= 0x00083203, /* aka E */
4882 CPU_POWERPC_7x5_v24
= 0x00083204,
4883 CPU_POWERPC_7x5_v25
= 0x00083205,
4884 CPU_POWERPC_7x5_v26
= 0x00083206,
4885 CPU_POWERPC_7x5_v27
= 0x00083207,
4886 CPU_POWERPC_7x5_v28
= 0x00083208,
4888 CPU_POWERPC_7x5P
= xxx
,
4890 /* PowerPC 74xx cores (aka G4) */
4891 /* XXX: missing 0x000C1101 */
4892 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
4893 CPU_POWERPC_7400_v10
= 0x000C0100,
4894 CPU_POWERPC_7400_v11
= 0x000C0101,
4895 CPU_POWERPC_7400_v20
= 0x000C0200,
4896 CPU_POWERPC_7400_v22
= 0x000C0202,
4897 CPU_POWERPC_7400_v26
= 0x000C0206,
4898 CPU_POWERPC_7400_v27
= 0x000C0207,
4899 CPU_POWERPC_7400_v28
= 0x000C0208,
4900 CPU_POWERPC_7400_v29
= 0x000C0209,
4901 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
4902 CPU_POWERPC_7410_v10
= 0x800C1100,
4903 CPU_POWERPC_7410_v11
= 0x800C1101,
4904 CPU_POWERPC_7410_v12
= 0x800C1102, /* aka C */
4905 CPU_POWERPC_7410_v13
= 0x800C1103, /* aka D */
4906 CPU_POWERPC_7410_v14
= 0x800C1104, /* aka E */
4907 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
4908 CPU_POWERPC_7448_v10
= 0x80040100,
4909 CPU_POWERPC_7448_v11
= 0x80040101,
4910 CPU_POWERPC_7448_v20
= 0x80040200,
4911 CPU_POWERPC_7448_v21
= 0x80040201,
4912 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
4913 CPU_POWERPC_7450_v10
= 0x80000100,
4914 CPU_POWERPC_7450_v11
= 0x80000101,
4915 CPU_POWERPC_7450_v12
= 0x80000102,
4916 CPU_POWERPC_7450_v20
= 0x80000200, /* aka D: 2.04 */
4917 CPU_POWERPC_7450_v21
= 0x80000201, /* aka E */
4918 CPU_POWERPC_74x1
= 0x80000203,
4919 CPU_POWERPC_74x1G
= 0x80000210, /* aka G: 2.3 */
4920 /* XXX: missing 0x80010200 */
4921 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
4922 CPU_POWERPC_74x5_v10
= 0x80010100,
4923 CPU_POWERPC_74x5_v21
= 0x80010201, /* aka C: 2.1 */
4924 CPU_POWERPC_74x5_v32
= 0x80010302,
4925 CPU_POWERPC_74x5_v33
= 0x80010303, /* aka F: 3.3 */
4926 CPU_POWERPC_74x5_v34
= 0x80010304, /* aka G: 3.4 */
4927 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
4928 CPU_POWERPC_74x7_v10
= 0x80020100, /* aka A: 1.0 */
4929 CPU_POWERPC_74x7_v11
= 0x80030101, /* aka B: 1.1 */
4930 CPU_POWERPC_74x7_v12
= 0x80020102, /* aka C: 1.2 */
4931 /* 64 bits PowerPC */
4932 #if defined(TARGET_PPC64)
4933 CPU_POWERPC_620
= 0x00140000,
4934 CPU_POWERPC_630
= 0x00400000,
4935 CPU_POWERPC_631
= 0x00410104,
4936 CPU_POWERPC_POWER4
= 0x00350000,
4937 CPU_POWERPC_POWER4P
= 0x00380000,
4938 CPU_POWERPC_POWER5
= 0x003A0203,
4939 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
4940 CPU_POWERPC_POWER5P
= 0x003B0000,
4941 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
4942 CPU_POWERPC_POWER6
= 0x003E0000,
4943 CPU_POWERPC_POWER6_5
= 0x0F000001, /* POWER6 running POWER5 mode */
4944 CPU_POWERPC_POWER6A
= 0x0F000002,
4945 CPU_POWERPC_970
= 0x00390202,
4946 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
4947 CPU_POWERPC_970FX_v10
= 0x00391100,
4948 CPU_POWERPC_970FX_v20
= 0x003C0200,
4949 CPU_POWERPC_970FX_v21
= 0x003C0201,
4950 CPU_POWERPC_970FX_v30
= 0x003C0300,
4951 CPU_POWERPC_970FX_v31
= 0x003C0301,
4952 CPU_POWERPC_970GX
= 0x00450000,
4953 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
4954 CPU_POWERPC_970MP_v10
= 0x00440100,
4955 CPU_POWERPC_970MP_v11
= 0x00440101,
4956 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
4957 CPU_POWERPC_CELL_v10
= 0x00700100,
4958 CPU_POWERPC_CELL_v20
= 0x00700400,
4959 CPU_POWERPC_CELL_v30
= 0x00700500,
4960 CPU_POWERPC_CELL_v31
= 0x00700501,
4961 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
4962 CPU_POWERPC_RS64
= 0x00330000,
4963 CPU_POWERPC_RS64II
= 0x00340000,
4964 CPU_POWERPC_RS64III
= 0x00360000,
4965 CPU_POWERPC_RS64IV
= 0x00370000,
4966 #endif /* defined(TARGET_PPC64) */
4967 /* Original POWER */
4968 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
4969 * POWER2 (RIOS2) & RSC2 (P2SC) here
4972 CPU_POWER
= xxx
, /* 0x20000 ? 0x30000 for RSC ? */
4975 CPU_POWER2
= xxx
, /* 0x40000 ? */
4978 CPU_POWERPC_PA6T
= 0x00900000,
4981 /* System version register (used on MPC 8xxx) */
4983 PPC_SVR_8540
= 0x80300000,
4984 PPC_SVR_8541E
= 0x807A0010,
4985 PPC_SVR_8543v10
= 0x80320010,
4986 PPC_SVR_8543v11
= 0x80320011,
4987 PPC_SVR_8543v20
= 0x80320020,
4988 PPC_SVR_8543Ev10
= 0x803A0010,
4989 PPC_SVR_8543Ev11
= 0x803A0011,
4990 PPC_SVR_8543Ev20
= 0x803A0020,
4991 PPC_SVR_8545
= 0x80310220,
4992 PPC_SVR_8545E
= 0x80390220,
4993 PPC_SVR_8547E
= 0x80390120,
4994 PPC_SCR_8548v10
= 0x80310010,
4995 PPC_SCR_8548v11
= 0x80310011,
4996 PPC_SCR_8548v20
= 0x80310020,
4997 PPC_SVR_8548Ev10
= 0x80390010,
4998 PPC_SVR_8548Ev11
= 0x80390011,
4999 PPC_SVR_8548Ev20
= 0x80390020,
5000 PPC_SVR_8555E
= 0x80790010,
5001 PPC_SVR_8560v10
= 0x80700010,
5002 PPC_SVR_8560v20
= 0x80700020,
5005 /*****************************************************************************/
5006 /* PowerPC CPU definitions */
5007 #define POWERPC_DEF(_name, _pvr, _pvr_mask, _type) \
5011 .pvr_mask = _pvr_mask, \
5012 .insns_flags = glue(POWERPC_INSNS_,_type), \
5013 .msr_mask = glue(POWERPC_MSRM_,_type), \
5014 .mmu_model = glue(POWERPC_MMU_,_type), \
5015 .excp_model = glue(POWERPC_EXCP_,_type), \
5016 .bus_model = glue(POWERPC_INPUT_,_type), \
5017 .bfd_mach = glue(POWERPC_BFDM_,_type), \
5018 .flags = glue(POWERPC_FLAG_,_type), \
5019 .init_proc = &glue(init_proc_,_type), \
5020 .check_pow = &glue(check_pow_,_type), \
5023 static ppc_def_t ppc_defs
[] = {
5024 /* Embedded PowerPC */
5025 /* PowerPC 401 family */
5026 /* Generic PowerPC 401 */
5027 POWERPC_DEF("401", CPU_POWERPC_401
, 0xFFFF0000, 401),
5028 /* PowerPC 401 cores */
5030 POWERPC_DEF("401A1", CPU_POWERPC_401A1
, 0xFFFFFFFF, 401),
5032 POWERPC_DEF("401B2", CPU_POWERPC_401B2
, 0xFFFFFFFF, 401x2
),
5035 POWERPC_DEF("401B3", CPU_POWERPC_401B3
, 0xFFFFFFFF, 401x3
),
5038 POWERPC_DEF("401C2", CPU_POWERPC_401C2
, 0xFFFFFFFF, 401x2
),
5040 POWERPC_DEF("401D2", CPU_POWERPC_401D2
, 0xFFFFFFFF, 401x2
),
5042 POWERPC_DEF("401E2", CPU_POWERPC_401E2
, 0xFFFFFFFF, 401x2
),
5044 POWERPC_DEF("401F2", CPU_POWERPC_401F2
, 0xFFFFFFFF, 401x2
),
5046 /* XXX: to be checked */
5047 POWERPC_DEF("401G2", CPU_POWERPC_401G2
, 0xFFFFFFFF, 401x2
),
5048 /* PowerPC 401 microcontrolers */
5051 POWERPC_DEF("401GF", CPU_POWERPC_401GF
, 0xFFFFFFFF, 401),
5053 /* IOP480 (401 microcontroler) */
5054 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480
, 0xFFFFFFFF, IOP480
),
5055 /* IBM Processor for Network Resources */
5056 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA
, 0xFFFFFFFF, 401),
5058 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP
, 0xFFFFFFFF, 401),
5060 /* PowerPC 403 family */
5061 /* Generic PowerPC 403 */
5062 POWERPC_DEF("403", CPU_POWERPC_403
, 0xFFFF0000, 403),
5063 /* PowerPC 403 microcontrolers */
5064 /* PowerPC 403 GA */
5065 POWERPC_DEF("403GA", CPU_POWERPC_403GA
, 0xFFFFFFFF, 403),
5066 /* PowerPC 403 GB */
5067 POWERPC_DEF("403GB", CPU_POWERPC_403GB
, 0xFFFFFFFF, 403),
5068 /* PowerPC 403 GC */
5069 POWERPC_DEF("403GC", CPU_POWERPC_403GC
, 0xFFFFFFFF, 403),
5070 /* PowerPC 403 GCX */
5071 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX
, 0xFFFFFFFF, 403GCX
),
5073 /* PowerPC 403 GP */
5074 POWERPC_DEF("403GP", CPU_POWERPC_403GP
, 0xFFFFFFFF, 403),
5076 /* PowerPC 405 family */
5077 /* Generic PowerPC 405 */
5078 POWERPC_DEF("405", CPU_POWERPC_405
, 0xFFFF0000, 405),
5079 /* PowerPC 405 cores */
5081 /* PowerPC 405 A3 */
5082 POWERPC_DEF("405A3", CPU_POWERPC_405A3
, 0xFFFFFFFF, 405),
5085 /* PowerPC 405 A4 */
5086 POWERPC_DEF("405A4", CPU_POWERPC_405A4
, 0xFFFFFFFF, 405),
5089 /* PowerPC 405 B3 */
5090 POWERPC_DEF("405B3", CPU_POWERPC_405B3
, 0xFFFFFFFF, 405),
5093 /* PowerPC 405 B4 */
5094 POWERPC_DEF("405B4", CPU_POWERPC_405B4
, 0xFFFFFFFF, 405),
5097 /* PowerPC 405 C3 */
5098 POWERPC_DEF("405C3", CPU_POWERPC_405C3
, 0xFFFFFFFF, 405),
5101 /* PowerPC 405 C4 */
5102 POWERPC_DEF("405C4", CPU_POWERPC_405C4
, 0xFFFFFFFF, 405),
5104 /* PowerPC 405 D2 */
5105 POWERPC_DEF("405D2", CPU_POWERPC_405D2
, 0xFFFFFFFF, 405),
5107 /* PowerPC 405 D3 */
5108 POWERPC_DEF("405D3", CPU_POWERPC_405D3
, 0xFFFFFFFF, 405),
5110 /* PowerPC 405 D4 */
5111 POWERPC_DEF("405D4", CPU_POWERPC_405D4
, 0xFFFFFFFF, 405),
5113 /* PowerPC 405 D5 */
5114 POWERPC_DEF("405D5", CPU_POWERPC_405D5
, 0xFFFFFFFF, 405),
5117 /* PowerPC 405 E4 */
5118 POWERPC_DEF("405E4", CPU_POWERPC_405E4
, 0xFFFFFFFF, 405),
5121 /* PowerPC 405 F4 */
5122 POWERPC_DEF("405F4", CPU_POWERPC_405F4
, 0xFFFFFFFF, 405),
5125 /* PowerPC 405 F5 */
5126 POWERPC_DEF("405F5", CPU_POWERPC_405F5
, 0xFFFFFFFF, 405),
5129 /* PowerPC 405 F6 */
5130 POWERPC_DEF("405F6", CPU_POWERPC_405F6
, 0xFFFFFFFF, 405),
5132 /* PowerPC 405 microcontrolers */
5133 /* PowerPC 405 CR */
5134 POWERPC_DEF("405CR", CPU_POWERPC_405CR
, 0xFFFFFFFF, 405),
5135 /* PowerPC 405 CRa */
5136 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa
, 0xFFFFFFFF, 405),
5137 /* PowerPC 405 CRb */
5138 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb
, 0xFFFFFFFF, 405),
5139 /* PowerPC 405 CRc */
5140 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc
, 0xFFFFFFFF, 405),
5141 /* PowerPC 405 EP */
5142 POWERPC_DEF("405EP", CPU_POWERPC_405EP
, 0xFFFFFFFF, 405),
5144 /* PowerPC 405 EXr */
5145 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr
, 0xFFFFFFFF, 405),
5147 /* PowerPC 405 EZ */
5148 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ
, 0xFFFFFFFF, 405),
5150 /* PowerPC 405 FX */
5151 POWERPC_DEF("405FX", CPU_POWERPC_405FX
, 0xFFFFFFFF, 405),
5153 /* PowerPC 405 GP */
5154 POWERPC_DEF("405GP", CPU_POWERPC_405GP
, 0xFFFFFFFF, 405),
5155 /* PowerPC 405 GPa */
5156 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa
, 0xFFFFFFFF, 405),
5157 /* PowerPC 405 GPb */
5158 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb
, 0xFFFFFFFF, 405),
5159 /* PowerPC 405 GPc */
5160 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc
, 0xFFFFFFFF, 405),
5161 /* PowerPC 405 GPd */
5162 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd
, 0xFFFFFFFF, 405),
5163 /* PowerPC 405 GPe */
5164 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe
, 0xFFFFFFFF, 405),
5165 /* PowerPC 405 GPR */
5166 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR
, 0xFFFFFFFF, 405),
5169 POWERPC_DEF("405H", CPU_POWERPC_405H
, 0xFFFFFFFF, 405),
5173 POWERPC_DEF("405L", CPU_POWERPC_405L
, 0xFFFFFFFF, 405),
5175 /* PowerPC 405 LP */
5176 POWERPC_DEF("405LP", CPU_POWERPC_405LP
, 0xFFFFFFFF, 405),
5178 /* PowerPC 405 PM */
5179 POWERPC_DEF("405PM", CPU_POWERPC_405PM
, 0xFFFFFFFF, 405),
5182 /* PowerPC 405 PS */
5183 POWERPC_DEF("405PS", CPU_POWERPC_405PS
, 0xFFFFFFFF, 405),
5187 POWERPC_DEF("405S", CPU_POWERPC_405S
, 0xFFFFFFFF, 405),
5190 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H
, 0xFFFFFFFF, 405),
5192 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2
, 0xFFFFFFFF, 405),
5194 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L
, 0xFFFFFFFF, 405),
5196 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3
, 0xFFFFFFFF, 405),
5198 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1
, 0xFFFFFFFF, 405),
5201 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161
, 0xFFFFFFFF, 405),
5204 /* PowerPC LC77700 (Sanyo) */
5205 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700
, 0xFFFFFFFF, 405),
5207 /* PowerPC 401/403/405 based set-top-box microcontrolers */
5210 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000
, 0xFFFFFFFF, 401x2
),
5214 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010
, 0xFFFFFFFF, 401x2
),
5218 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210
, 0xFFFFFFFF, 401x3
),
5221 POWERPC_DEF("STB03", CPU_POWERPC_STB03
, 0xFFFFFFFF, 405),
5224 POWERPC_DEF("STB043", CPU_POWERPC_STB043
, 0xFFFFFFFF, 405),
5228 POWERPC_DEF("STB045", CPU_POWERPC_STB045
, 0xFFFFFFFF, 405),
5231 POWERPC_DEF("STB04", CPU_POWERPC_STB04
, 0xFFFF0000, 405),
5233 POWERPC_DEF("STB25", CPU_POWERPC_STB25
, 0xFFFFFFFF, 405),
5236 POWERPC_DEF("STB130", CPU_POWERPC_STB130
, 0xFFFFFFFF, 405),
5238 /* Xilinx PowerPC 405 cores */
5239 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4
, 0xFFFFFFFF, 405),
5240 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7
, 0xFFFFFFFF, 405),
5241 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20
, 0xFFFFFFFF, 405),
5242 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50
, 0xFFFFFFFF, 405),
5244 /* Zarlink ZL10310 */
5245 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310
, 0xFFFFFFFF, 405),
5248 /* Zarlink ZL10311 */
5249 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311
, 0xFFFFFFFF, 405),
5252 /* Zarlink ZL10320 */
5253 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320
, 0xFFFFFFFF, 405),
5256 /* Zarlink ZL10321 */
5257 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321
, 0xFFFFFFFF, 405),
5259 /* PowerPC 440 family */
5260 /* Generic PowerPC 440 */
5261 POWERPC_DEF("440", CPU_POWERPC_440
, 0xFFFFFFFF, 440GP
),
5262 /* PowerPC 440 cores */
5264 /* PowerPC 440 A4 */
5265 POWERPC_DEF("440A4", CPU_POWERPC_440A4
, 0xFFFFFFFF, 440x4
),
5268 /* PowerPC 440 A5 */
5269 POWERPC_DEF("440A5", CPU_POWERPC_440A5
, 0xFFFFFFFF, 440x5
),
5272 /* PowerPC 440 B4 */
5273 POWERPC_DEF("440B4", CPU_POWERPC_440B4
, 0xFFFFFFFF, 440x4
),
5276 /* PowerPC 440 G4 */
5277 POWERPC_DEF("440G4", CPU_POWERPC_440G4
, 0xFFFFFFFF, 440x4
),
5280 /* PowerPC 440 F5 */
5281 POWERPC_DEF("440F5", CPU_POWERPC_440F5
, 0xFFFFFFFF, 440x5
),
5284 /* PowerPC 440 G5 */
5285 POWERPC_DEF("440G5", CPU_POWERPC_440G5
, 0xFFFFFFFF, 440x5
),
5289 POWERPC_DEF("440H4", CPU_POWERPC_440H4
, 0xFFFFFFFF, 440x4
),
5293 POWERPC_DEF("440H6", CPU_POWERPC_440H6
, 0xFFFFFFFF, 440Gx5
),
5295 /* PowerPC 440 microcontrolers */
5296 /* PowerPC 440 EP */
5297 POWERPC_DEF("440EP", CPU_POWERPC_440EP
, 0xFFFFFFFF, 440EP
),
5298 /* PowerPC 440 EPa */
5299 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa
, 0xFFFFFFFF, 440EP
),
5300 /* PowerPC 440 EPb */
5301 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb
, 0xFFFFFFFF, 440EP
),
5302 /* PowerPC 440 EPX */
5303 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX
, 0xFFFFFFFF, 440EP
),
5304 /* PowerPC 440 GP */
5305 POWERPC_DEF("440GP", CPU_POWERPC_440GP
, 0xFFFFFFFF, 440GP
),
5306 /* PowerPC 440 GPb */
5307 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb
, 0xFFFFFFFF, 440GP
),
5308 /* PowerPC 440 GPc */
5309 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc
, 0xFFFFFFFF, 440GP
),
5310 /* PowerPC 440 GR */
5311 POWERPC_DEF("440GR", CPU_POWERPC_440GR
, 0xFFFFFFFF, 440x5
),
5312 /* PowerPC 440 GRa */
5313 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa
, 0xFFFFFFFF, 440x5
),
5314 /* PowerPC 440 GRX */
5315 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX
, 0xFFFFFFFF, 440x5
),
5316 /* PowerPC 440 GX */
5317 POWERPC_DEF("440GX", CPU_POWERPC_440GX
, 0xFFFFFFFF, 440EP
),
5318 /* PowerPC 440 GXa */
5319 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa
, 0xFFFFFFFF, 440EP
),
5320 /* PowerPC 440 GXb */
5321 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb
, 0xFFFFFFFF, 440EP
),
5322 /* PowerPC 440 GXc */
5323 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc
, 0xFFFFFFFF, 440EP
),
5324 /* PowerPC 440 GXf */
5325 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf
, 0xFFFFFFFF, 440EP
),
5328 POWERPC_DEF("440S", CPU_POWERPC_440S
, 0xFFFFFFFF, 440),
5330 /* PowerPC 440 SP */
5331 POWERPC_DEF("440SP", CPU_POWERPC_440SP
, 0xFFFFFFFF, 440EP
),
5332 /* PowerPC 440 SP2 */
5333 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2
, 0xFFFFFFFF, 440EP
),
5334 /* PowerPC 440 SPE */
5335 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE
, 0xFFFFFFFF, 440EP
),
5336 /* PowerPC 460 family */
5338 /* Generic PowerPC 464 */
5339 POWERPC_DEF("464", CPU_POWERPC_464
, 0xFFFFFFFF, 460),
5341 /* PowerPC 464 microcontrolers */
5343 /* PowerPC 464H90 */
5344 POWERPC_DEF("464H90", CPU_POWERPC_464H90
, 0xFFFFFFFF, 460),
5347 /* PowerPC 464H90F */
5348 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F
, 0xFFFFFFFF, 460F
),
5350 /* Freescale embedded PowerPC cores */
5353 /* Generic PowerPC e200 core */
5354 POWERPC_DEF("e200", CPU_POWERPC_e200
, 0xFFFFFFFF, e200
),
5357 /* PowerPC e200z5 core */
5358 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5
, 0xFFFFFFFF, e200
),
5361 /* PowerPC e200z6 core */
5362 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6
, 0xFFFFFFFF, e200
),
5366 /* Generic PowerPC e300 core */
5367 POWERPC_DEF("e300", CPU_POWERPC_e300
, 0xFFFFFFFF, e300
),
5370 /* PowerPC e300c1 core */
5371 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1
, 0xFFFFFFFF, e300
),
5374 /* PowerPC e300c2 core */
5375 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2
, 0xFFFFFFFF, e300
),
5378 /* PowerPC e300c3 core */
5379 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3
, 0xFFFFFFFF, e300
),
5383 /* PowerPC e500 core */
5384 POWERPC_DEF("e500", CPU_POWERPC_e500
, 0xFFFFFFFF, e500
),
5387 /* PowerPC e500 v1.1 core */
5388 POWERPC_DEF("e500v1.1", CPU_POWERPC_e500_v11
, 0xFFFFFFFF, e500
),
5391 /* PowerPC e500 v1.2 core */
5392 POWERPC_DEF("e500v1.2", CPU_POWERPC_e500_v12
, 0xFFFFFFFF, e500
),
5395 /* PowerPC e500 v2.1 core */
5396 POWERPC_DEF("e500v2.1", CPU_POWERPC_e500_v21
, 0xFFFFFFFF, e500
),
5399 /* PowerPC e500 v2.2 core */
5400 POWERPC_DEF("e500v2.2", CPU_POWERPC_e500_v22
, 0xFFFFFFFF, e500
),
5404 /* PowerPC e600 core */
5405 POWERPC_DEF("e600", CPU_POWERPC_e600
, 0xFFFFFFFF, e600
),
5407 /* PowerPC MPC 5xx cores */
5409 /* PowerPC MPC 5xx */
5410 POWERPC_DEF("mpc5xx", CPU_POWERPC_5xx
, 0xFFFFFFFF, 5xx
),
5412 /* PowerPC MPC 8xx cores */
5414 /* PowerPC MPC 8xx */
5415 POWERPC_DEF("mpc8xx", CPU_POWERPC_8xx
, 0xFFFFFFFF, 8xx
),
5417 /* PowerPC MPC 8xxx cores */
5419 /* PowerPC MPC 82xx HIP3 */
5420 POWERPC_DEF("mpc82xxhip3", CPU_POWERPC_82xx_HIP3
, 0xFFFFFFFF, 82xx
),
5423 /* PowerPC MPC 82xx HIP4 */
5424 POWERPC_DEF("mpc82xxhip4", CPU_POWERPC_82xx_HIP4
, 0xFFFFFFFF, 82xx
),
5427 /* PowerPC MPC 827x */
5428 POWERPC_DEF("mpc827x", CPU_POWERPC_827x
, 0xFFFFFFFF, 827x
),
5431 /* 32 bits "classic" PowerPC */
5432 /* PowerPC 6xx family */
5434 POWERPC_DEF("601", CPU_POWERPC_601
, 0xFFFFFFFF, 601),
5436 POWERPC_DEF("601a", CPU_POWERPC_601a
, 0xFFFFFFFF, 601),
5438 POWERPC_DEF("602", CPU_POWERPC_602
, 0xFFFFFFFF, 602),
5440 POWERPC_DEF("603", CPU_POWERPC_603
, 0xFFFFFFFF, 603),
5441 /* Code name for PowerPC 603 */
5442 POWERPC_DEF("Vanilla", CPU_POWERPC_603
, 0xFFFFFFFF, 603),
5444 POWERPC_DEF("603e", CPU_POWERPC_603E
, 0xFFFFFFFF, 603E
),
5445 /* Code name for PowerPC 603e */
5446 POWERPC_DEF("Stretch", CPU_POWERPC_603E
, 0xFFFFFFFF, 603E
),
5447 /* PowerPC 603e v1.1 */
5448 POWERPC_DEF("603e1.1", CPU_POWERPC_603E_v11
, 0xFFFFFFFF, 603E
),
5449 /* PowerPC 603e v1.2 */
5450 POWERPC_DEF("603e1.2", CPU_POWERPC_603E_v12
, 0xFFFFFFFF, 603E
),
5451 /* PowerPC 603e v1.3 */
5452 POWERPC_DEF("603e1.3", CPU_POWERPC_603E_v13
, 0xFFFFFFFF, 603E
),
5453 /* PowerPC 603e v1.4 */
5454 POWERPC_DEF("603e1.4", CPU_POWERPC_603E_v14
, 0xFFFFFFFF, 603E
),
5455 /* PowerPC 603e v2.2 */
5456 POWERPC_DEF("603e2.2", CPU_POWERPC_603E_v22
, 0xFFFFFFFF, 603E
),
5457 /* PowerPC 603e v3 */
5458 POWERPC_DEF("603e3", CPU_POWERPC_603E_v3
, 0xFFFFFFFF, 603E
),
5459 /* PowerPC 603e v4 */
5460 POWERPC_DEF("603e4", CPU_POWERPC_603E_v4
, 0xFFFFFFFF, 603E
),
5461 /* PowerPC 603e v4.1 */
5462 POWERPC_DEF("603e4.1", CPU_POWERPC_603E_v41
, 0xFFFFFFFF, 603E
),
5464 POWERPC_DEF("603e7", CPU_POWERPC_603E7
, 0xFFFFFFFF, 603E
),
5465 /* PowerPC 603e7t */
5466 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t
, 0xFFFFFFFF, 603E
),
5467 /* PowerPC 603e7v */
5468 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v
, 0xFFFFFFFF, 603E
),
5469 /* Code name for PowerPC 603ev */
5470 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v
, 0xFFFFFFFF, 603E
),
5471 /* PowerPC 603e7v1 */
5472 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1
, 0xFFFFFFFF, 603E
),
5473 /* PowerPC 603e7v2 */
5474 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2
, 0xFFFFFFFF, 603E
),
5477 POWERPC_DEF("603p", CPU_POWERPC_603P
, 0xFFFFFFFF, 603),
5479 POWERPC_DEF("603r", CPU_POWERPC_603R
, 0xFFFFFFFF, 603E
),
5480 /* Code name for PowerPC 603r */
5481 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R
, 0xFFFFFFFF, 603E
),
5482 /* PowerPC G2 core */
5483 POWERPC_DEF("G2", CPU_POWERPC_G2
, 0xFFFFFFFF, G2
),
5485 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4
, 0xFFFFFFFF, G2
),
5487 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp
, 0xFFFFFFFF, G2
),
5489 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls
, 0xFFFFFFFF, G2
),
5491 /* Same as G2, with little-endian mode support */
5492 POWERPC_DEF("G2le", CPU_POWERPC_G2LE
, 0xFFFFFFFF, G2LE
),
5493 /* PowerPC G2LE GP */
5494 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp
, 0xFFFFFFFF, G2LE
),
5495 /* PowerPC G2LE LS */
5496 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls
, 0xFFFFFFFF, G2LE
),
5498 POWERPC_DEF("604", CPU_POWERPC_604
, 0xFFFFFFFF, 604),
5500 POWERPC_DEF("604e", CPU_POWERPC_604E
, 0xFFFFFFFF, 604),
5501 /* PowerPC 604e v1.0 */
5502 POWERPC_DEF("604e1.0", CPU_POWERPC_604E_v10
, 0xFFFFFFFF, 604),
5503 /* PowerPC 604e v2.2 */
5504 POWERPC_DEF("604e2.2", CPU_POWERPC_604E_v22
, 0xFFFFFFFF, 604),
5505 /* PowerPC 604e v2.4 */
5506 POWERPC_DEF("604e2.4", CPU_POWERPC_604E_v24
, 0xFFFFFFFF, 604),
5508 POWERPC_DEF("604r", CPU_POWERPC_604R
, 0xFFFFFFFF, 604),
5511 POWERPC_DEF("604ev", CPU_POWERPC_604EV
, 0xFFFFFFFF, 604),
5513 /* PowerPC 7xx family */
5514 /* Generic PowerPC 740 (G3) */
5515 POWERPC_DEF("740", CPU_POWERPC_7x0
, 0xFFFFFFFF, 7x0
),
5516 /* Generic PowerPC 750 (G3) */
5517 POWERPC_DEF("750", CPU_POWERPC_7x0
, 0xFFFFFFFF, 7x0
),
5518 /* Code name for generic PowerPC 740/750 (G3) */
5519 POWERPC_DEF("Arthur", CPU_POWERPC_7x0
, 0xFFFFFFFF, 7x0
),
5520 /* PowerPC 740/750 is also known as G3 */
5521 POWERPC_DEF("G3", CPU_POWERPC_7x0
, 0xFFFFFFFF, 7x0
),
5522 /* PowerPC 740 v2.0 (G3) */
5523 POWERPC_DEF("740v2.0", CPU_POWERPC_7x0_v20
, 0xFFFFFFFF, 7x0
),
5524 /* PowerPC 750 v2.0 (G3) */
5525 POWERPC_DEF("750v2.0", CPU_POWERPC_7x0_v20
, 0xFFFFFFFF, 7x0
),
5526 /* PowerPC 740 v2.1 (G3) */
5527 POWERPC_DEF("740v2.1", CPU_POWERPC_7x0_v21
, 0xFFFFFFFF, 7x0
),
5528 /* PowerPC 750 v2.1 (G3) */
5529 POWERPC_DEF("750v2.1", CPU_POWERPC_7x0_v21
, 0xFFFFFFFF, 7x0
),
5530 /* PowerPC 740 v2.2 (G3) */
5531 POWERPC_DEF("740v2.2", CPU_POWERPC_7x0_v22
, 0xFFFFFFFF, 7x0
),
5532 /* PowerPC 750 v2.2 (G3) */
5533 POWERPC_DEF("750v2.2", CPU_POWERPC_7x0_v22
, 0xFFFFFFFF, 7x0
),
5534 /* PowerPC 740 v3.0 (G3) */
5535 POWERPC_DEF("740v3.0", CPU_POWERPC_7x0_v30
, 0xFFFFFFFF, 7x0
),
5536 /* PowerPC 750 v3.0 (G3) */
5537 POWERPC_DEF("750v3.0", CPU_POWERPC_7x0_v30
, 0xFFFFFFFF, 7x0
),
5538 /* PowerPC 740 v3.1 (G3) */
5539 POWERPC_DEF("740v3.1", CPU_POWERPC_7x0_v31
, 0xFFFFFFFF, 7x0
),
5540 /* PowerPC 750 v3.1 (G3) */
5541 POWERPC_DEF("750v3.1", CPU_POWERPC_7x0_v31
, 0xFFFFFFFF, 7x0
),
5542 /* PowerPC 740E (G3) */
5543 POWERPC_DEF("740e", CPU_POWERPC_740E
, 0xFFFFFFFF, 7x0
),
5544 /* PowerPC 740P (G3) */
5545 POWERPC_DEF("740p", CPU_POWERPC_7x0P
, 0xFFFFFFFF, 7x0
),
5546 /* PowerPC 750P (G3) */
5547 POWERPC_DEF("750p", CPU_POWERPC_7x0P
, 0xFFFFFFFF, 7x0
),
5548 /* Code name for PowerPC 740P/750P (G3) */
5549 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P
, 0xFFFFFFFF, 7x0
),
5550 /* PowerPC 750CL (G3 embedded) */
5551 POWERPC_DEF("750cl", CPU_POWERPC_750CL
, 0xFFFFFFFF, 7x0
),
5552 /* PowerPC 750CX (G3 embedded) */
5553 POWERPC_DEF("750cx", CPU_POWERPC_750CX
, 0xFFFFFFFF, 7x0
),
5554 /* PowerPC 750CX v2.1 (G3 embedded) */
5555 POWERPC_DEF("750cx2.1", CPU_POWERPC_750CX_v21
, 0xFFFFFFFF, 7x0
),
5556 /* PowerPC 750CX v2.2 (G3 embedded) */
5557 POWERPC_DEF("750cx2.2", CPU_POWERPC_750CX_v22
, 0xFFFFFFFF, 7x0
),
5558 /* PowerPC 750CXe (G3 embedded) */
5559 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE
, 0xFFFFFFFF, 7x0
),
5560 /* PowerPC 750CXe v2.1 (G3 embedded) */
5561 POWERPC_DEF("750cxe21", CPU_POWERPC_750CXE_v21
, 0xFFFFFFFF, 7x0
),
5562 /* PowerPC 750CXe v2.2 (G3 embedded) */
5563 POWERPC_DEF("750cxe22", CPU_POWERPC_750CXE_v22
, 0xFFFFFFFF, 7x0
),
5564 /* PowerPC 750CXe v2.3 (G3 embedded) */
5565 POWERPC_DEF("750cxe23", CPU_POWERPC_750CXE_v23
, 0xFFFFFFFF, 7x0
),
5566 /* PowerPC 750CXe v2.4 (G3 embedded) */
5567 POWERPC_DEF("750cxe24", CPU_POWERPC_750CXE_v24
, 0xFFFFFFFF, 7x0
),
5568 /* PowerPC 750CXe v2.4b (G3 embedded) */
5569 POWERPC_DEF("750cxe24b", CPU_POWERPC_750CXE_v24b
, 0xFFFFFFFF, 7x0
),
5570 /* PowerPC 750CXe v3.1 (G3 embedded) */
5571 POWERPC_DEF("750cxe31", CPU_POWERPC_750CXE_v31
, 0xFFFFFFFF, 7x0
),
5572 /* PowerPC 750CXe v3.1b (G3 embedded) */
5573 POWERPC_DEF("750cxe3.1b", CPU_POWERPC_750CXE_v31b
, 0xFFFFFFFF, 7x0
),
5574 /* PowerPC 750CXr (G3 embedded) */
5575 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR
, 0xFFFFFFFF, 7x0
),
5576 /* PowerPC 750E (G3) */
5577 POWERPC_DEF("750e", CPU_POWERPC_750E
, 0xFFFFFFFF, 7x0
),
5578 /* PowerPC 750FL (G3 embedded) */
5579 POWERPC_DEF("750fl", CPU_POWERPC_750FL
, 0xFFFFFFFF, 750fx
),
5580 /* PowerPC 750FX (G3 embedded) */
5581 POWERPC_DEF("750fx", CPU_POWERPC_750FX
, 0xFFFFFFFF, 750fx
),
5582 /* PowerPC 750FX v1.0 (G3 embedded) */
5583 POWERPC_DEF("750fx1.0", CPU_POWERPC_750FX_v10
, 0xFFFFFFFF, 750fx
),
5584 /* PowerPC 750FX v2.0 (G3 embedded) */
5585 POWERPC_DEF("750fx2.0", CPU_POWERPC_750FX_v20
, 0xFFFFFFFF, 750fx
),
5586 /* PowerPC 750FX v2.1 (G3 embedded) */
5587 POWERPC_DEF("750fx2.1", CPU_POWERPC_750FX_v21
, 0xFFFFFFFF, 750fx
),
5588 /* PowerPC 750FX v2.2 (G3 embedded) */
5589 POWERPC_DEF("750fx2.2", CPU_POWERPC_750FX_v22
, 0xFFFFFFFF, 750fx
),
5590 /* PowerPC 750FX v2.3 (G3 embedded) */
5591 POWERPC_DEF("750fx2.3", CPU_POWERPC_750FX_v23
, 0xFFFFFFFF, 750fx
),
5592 /* PowerPC 750GL (G3 embedded) */
5593 POWERPC_DEF("750gl", CPU_POWERPC_750GL
, 0xFFFFFFFF, 750fx
),
5594 /* PowerPC 750GX (G3 embedded) */
5595 POWERPC_DEF("750gx", CPU_POWERPC_750GX
, 0xFFFFFFFF, 750fx
),
5596 /* PowerPC 750GX v1.0 (G3 embedded) */
5597 POWERPC_DEF("750gx1.0", CPU_POWERPC_750GX_v10
, 0xFFFFFFFF, 750fx
),
5598 /* PowerPC 750GX v1.1 (G3 embedded) */
5599 POWERPC_DEF("750gx1.1", CPU_POWERPC_750GX_v11
, 0xFFFFFFFF, 750fx
),
5600 /* PowerPC 750GX v1.2 (G3 embedded) */
5601 POWERPC_DEF("750gx1.2", CPU_POWERPC_750GX_v12
, 0xFFFFFFFF, 750fx
),
5602 /* PowerPC 750L (G3 embedded) */
5603 POWERPC_DEF("750l", CPU_POWERPC_750L
, 0xFFFFFFFF, 7x0
),
5604 /* Code name for PowerPC 750L (G3 embedded) */
5605 POWERPC_DEF("LoneStar", CPU_POWERPC_750L
, 0xFFFFFFFF, 7x0
),
5606 /* PowerPC 750L v2.2 (G3 embedded) */
5607 POWERPC_DEF("750l2.2", CPU_POWERPC_750L_v22
, 0xFFFFFFFF, 7x0
),
5608 /* PowerPC 750L v3.0 (G3 embedded) */
5609 POWERPC_DEF("750l3.0", CPU_POWERPC_750L_v30
, 0xFFFFFFFF, 7x0
),
5610 /* PowerPC 750L v3.2 (G3 embedded) */
5611 POWERPC_DEF("750l3.2", CPU_POWERPC_750L_v32
, 0xFFFFFFFF, 7x0
),
5612 /* Generic PowerPC 745 */
5613 POWERPC_DEF("745", CPU_POWERPC_7x5
, 0xFFFFFFFF, 7x5
),
5614 /* Generic PowerPC 755 */
5615 POWERPC_DEF("755", CPU_POWERPC_7x5
, 0xFFFFFFFF, 7x5
),
5616 /* Code name for PowerPC 745/755 */
5617 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5
, 0xFFFFFFFF, 7x5
),
5618 /* PowerPC 745 v1.0 */
5619 POWERPC_DEF("745v1.0", CPU_POWERPC_7x5_v10
, 0xFFFFFFFF, 7x5
),
5620 /* PowerPC 755 v1.0 */
5621 POWERPC_DEF("755v1.0", CPU_POWERPC_7x5_v10
, 0xFFFFFFFF, 7x5
),
5622 /* PowerPC 745 v1.1 */
5623 POWERPC_DEF("745v1.1", CPU_POWERPC_7x5_v11
, 0xFFFFFFFF, 7x5
),
5624 /* PowerPC 755 v1.1 */
5625 POWERPC_DEF("755v1.1", CPU_POWERPC_7x5_v11
, 0xFFFFFFFF, 7x5
),
5626 /* PowerPC 745 v2.0 */
5627 POWERPC_DEF("745v2.0", CPU_POWERPC_7x5_v20
, 0xFFFFFFFF, 7x5
),
5628 /* PowerPC 755 v2.0 */
5629 POWERPC_DEF("755v2.0", CPU_POWERPC_7x5_v20
, 0xFFFFFFFF, 7x5
),
5630 /* PowerPC 745 v2.1 */
5631 POWERPC_DEF("745v2.1", CPU_POWERPC_7x5_v21
, 0xFFFFFFFF, 7x5
),
5632 /* PowerPC 755 v2.1 */
5633 POWERPC_DEF("755v2.1", CPU_POWERPC_7x5_v21
, 0xFFFFFFFF, 7x5
),
5634 /* PowerPC 745 v2.2 */
5635 POWERPC_DEF("745v2.2", CPU_POWERPC_7x5_v22
, 0xFFFFFFFF, 7x5
),
5636 /* PowerPC 755 v2.2 */
5637 POWERPC_DEF("755v2.2", CPU_POWERPC_7x5_v22
, 0xFFFFFFFF, 7x5
),
5638 /* PowerPC 745 v2.3 */
5639 POWERPC_DEF("745v2.3", CPU_POWERPC_7x5_v23
, 0xFFFFFFFF, 7x5
),
5640 /* PowerPC 755 v2.3 */
5641 POWERPC_DEF("755v2.3", CPU_POWERPC_7x5_v23
, 0xFFFFFFFF, 7x5
),
5642 /* PowerPC 745 v2.4 */
5643 POWERPC_DEF("745v2.4", CPU_POWERPC_7x5_v24
, 0xFFFFFFFF, 7x5
),
5644 /* PowerPC 755 v2.4 */
5645 POWERPC_DEF("755v2.4", CPU_POWERPC_7x5_v24
, 0xFFFFFFFF, 7x5
),
5646 /* PowerPC 745 v2.5 */
5647 POWERPC_DEF("745v2.5", CPU_POWERPC_7x5_v25
, 0xFFFFFFFF, 7x5
),
5648 /* PowerPC 755 v2.5 */
5649 POWERPC_DEF("755v2.5", CPU_POWERPC_7x5_v25
, 0xFFFFFFFF, 7x5
),
5650 /* PowerPC 745 v2.6 */
5651 POWERPC_DEF("745v2.6", CPU_POWERPC_7x5_v26
, 0xFFFFFFFF, 7x5
),
5652 /* PowerPC 755 v2.6 */
5653 POWERPC_DEF("755v2.6", CPU_POWERPC_7x5_v26
, 0xFFFFFFFF, 7x5
),
5654 /* PowerPC 745 v2.7 */
5655 POWERPC_DEF("745v2.7", CPU_POWERPC_7x5_v27
, 0xFFFFFFFF, 7x5
),
5656 /* PowerPC 755 v2.7 */
5657 POWERPC_DEF("755v2.7", CPU_POWERPC_7x5_v27
, 0xFFFFFFFF, 7x5
),
5658 /* PowerPC 745 v2.8 */
5659 POWERPC_DEF("745v2.8", CPU_POWERPC_7x5_v28
, 0xFFFFFFFF, 7x5
),
5660 /* PowerPC 755 v2.8 */
5661 POWERPC_DEF("755v2.8", CPU_POWERPC_7x5_v28
, 0xFFFFFFFF, 7x5
),
5663 /* PowerPC 745P (G3) */
5664 POWERPC_DEF("745p", CPU_POWERPC_7x5P
, 0xFFFFFFFF, 7x5
),
5665 /* PowerPC 755P (G3) */
5666 POWERPC_DEF("755p", CPU_POWERPC_7x5P
, 0xFFFFFFFF, 7x5
),
5668 /* PowerPC 74xx family */
5669 /* PowerPC 7400 (G4) */
5670 POWERPC_DEF("7400", CPU_POWERPC_7400
, 0xFFFFFFFF, 7400),
5671 /* Code name for PowerPC 7400 */
5672 POWERPC_DEF("Max", CPU_POWERPC_7400
, 0xFFFFFFFF, 7400),
5673 /* PowerPC 74xx is also well known as G4 */
5674 POWERPC_DEF("G4", CPU_POWERPC_7400
, 0xFFFFFFFF, 7400),
5675 /* PowerPC 7400 v1.0 (G4) */
5676 POWERPC_DEF("7400v1.0", CPU_POWERPC_7400_v10
, 0xFFFFFFFF, 7400),
5677 /* PowerPC 7400 v1.1 (G4) */
5678 POWERPC_DEF("7400v1.1", CPU_POWERPC_7400_v11
, 0xFFFFFFFF, 7400),
5679 /* PowerPC 7400 v2.0 (G4) */
5680 POWERPC_DEF("7400v2.0", CPU_POWERPC_7400_v20
, 0xFFFFFFFF, 7400),
5681 /* PowerPC 7400 v2.2 (G4) */
5682 POWERPC_DEF("7400v2.2", CPU_POWERPC_7400_v22
, 0xFFFFFFFF, 7400),
5683 /* PowerPC 7400 v2.6 (G4) */
5684 POWERPC_DEF("7400v2.6", CPU_POWERPC_7400_v26
, 0xFFFFFFFF, 7400),
5685 /* PowerPC 7400 v2.7 (G4) */
5686 POWERPC_DEF("7400v2.7", CPU_POWERPC_7400_v27
, 0xFFFFFFFF, 7400),
5687 /* PowerPC 7400 v2.8 (G4) */
5688 POWERPC_DEF("7400v2.8", CPU_POWERPC_7400_v28
, 0xFFFFFFFF, 7400),
5689 /* PowerPC 7400 v2.9 (G4) */
5690 POWERPC_DEF("7400v2.9", CPU_POWERPC_7400_v29
, 0xFFFFFFFF, 7400),
5691 /* PowerPC 7410 (G4) */
5692 POWERPC_DEF("7410", CPU_POWERPC_7410
, 0xFFFFFFFF, 7410),
5693 /* Code name for PowerPC 7410 */
5694 POWERPC_DEF("Nitro", CPU_POWERPC_7410
, 0xFFFFFFFF, 7410),
5695 /* PowerPC 7410 v1.0 (G4) */
5696 POWERPC_DEF("7410v1.0", CPU_POWERPC_7410_v10
, 0xFFFFFFFF, 7410),
5697 /* PowerPC 7410 v1.1 (G4) */
5698 POWERPC_DEF("7410v1.1", CPU_POWERPC_7410_v11
, 0xFFFFFFFF, 7410),
5699 /* PowerPC 7410 v1.2 (G4) */
5700 POWERPC_DEF("7410v1.2", CPU_POWERPC_7410_v12
, 0xFFFFFFFF, 7410),
5701 /* PowerPC 7410 v1.3 (G4) */
5702 POWERPC_DEF("7410v1.3", CPU_POWERPC_7410_v13
, 0xFFFFFFFF, 7410),
5703 /* PowerPC 7410 v1.4 (G4) */
5704 POWERPC_DEF("7410v1.4", CPU_POWERPC_7410_v14
, 0xFFFFFFFF, 7410),
5705 /* PowerPC 7448 (G4) */
5706 POWERPC_DEF("7448", CPU_POWERPC_7448
, 0xFFFFFFFF, 7400),
5707 /* PowerPC 7448 v1.0 (G4) */
5708 POWERPC_DEF("7448v1.0", CPU_POWERPC_7448_v10
, 0xFFFFFFFF, 7400),
5709 /* PowerPC 7448 v1.1 (G4) */
5710 POWERPC_DEF("7448v1.1", CPU_POWERPC_7448_v11
, 0xFFFFFFFF, 7400),
5711 /* PowerPC 7448 v2.0 (G4) */
5712 POWERPC_DEF("7448v2.0", CPU_POWERPC_7448_v20
, 0xFFFFFFFF, 7400),
5713 /* PowerPC 7448 v2.1 (G4) */
5714 POWERPC_DEF("7448v2.1", CPU_POWERPC_7448_v21
, 0xFFFFFFFF, 7400),
5715 /* PowerPC 7450 (G4) */
5716 POWERPC_DEF("7450", CPU_POWERPC_7450
, 0xFFFFFFFF, 7450),
5717 /* Code name for PowerPC 7450 */
5718 POWERPC_DEF("Vger", CPU_POWERPC_7450
, 0xFFFFFFFF, 7450),
5719 /* PowerPC 7450 v1.0 (G4) */
5720 POWERPC_DEF("7450v1.0", CPU_POWERPC_7450_v10
, 0xFFFFFFFF, 7450),
5721 /* PowerPC 7450 v1.1 (G4) */
5722 POWERPC_DEF("7450v1.1", CPU_POWERPC_7450_v11
, 0xFFFFFFFF, 7450),
5723 /* PowerPC 7450 v1.2 (G4) */
5724 POWERPC_DEF("7450v1.2", CPU_POWERPC_7450_v12
, 0xFFFFFFFF, 7450),
5725 /* PowerPC 7450 v2.0 (G4) */
5726 POWERPC_DEF("7450v2.0", CPU_POWERPC_7450_v20
, 0xFFFFFFFF, 7450),
5727 /* PowerPC 7450 v2.1 (G4) */
5728 POWERPC_DEF("7450v2.1", CPU_POWERPC_7450_v21
, 0xFFFFFFFF, 7450),
5729 /* PowerPC 7441 (G4) */
5730 POWERPC_DEF("7441", CPU_POWERPC_74x1
, 0xFFFFFFFF, 7440),
5731 /* PowerPC 7451 (G4) */
5732 POWERPC_DEF("7451", CPU_POWERPC_74x1
, 0xFFFFFFFF, 7450),
5733 /* PowerPC 7441g (G4) */
5734 POWERPC_DEF("7441g", CPU_POWERPC_74x1G
, 0xFFFFFFFF, 7440),
5735 /* PowerPC 7451g (G4) */
5736 POWERPC_DEF("7451g", CPU_POWERPC_74x1G
, 0xFFFFFFFF, 7450),
5737 /* PowerPC 7445 (G4) */
5738 POWERPC_DEF("7445", CPU_POWERPC_74x5
, 0xFFFFFFFF, 7445),
5739 /* PowerPC 7455 (G4) */
5740 POWERPC_DEF("7455", CPU_POWERPC_74x5
, 0xFFFFFFFF, 7455),
5741 /* Code name for PowerPC 7445/7455 */
5742 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5
, 0xFFFFFFFF, 7455),
5743 /* PowerPC 7445 v1.0 (G4) */
5744 POWERPC_DEF("7445v1.0", CPU_POWERPC_74x5_v10
, 0xFFFFFFFF, 7445),
5745 /* PowerPC 7455 v1.0 (G4) */
5746 POWERPC_DEF("7455v1.0", CPU_POWERPC_74x5_v10
, 0xFFFFFFFF, 7455),
5747 /* PowerPC 7445 v2.1 (G4) */
5748 POWERPC_DEF("7445v2.1", CPU_POWERPC_74x5_v21
, 0xFFFFFFFF, 7445),
5749 /* PowerPC 7455 v2.1 (G4) */
5750 POWERPC_DEF("7455v2.1", CPU_POWERPC_74x5_v21
, 0xFFFFFFFF, 7455),
5751 /* PowerPC 7445 v3.2 (G4) */
5752 POWERPC_DEF("7445v3.2", CPU_POWERPC_74x5_v32
, 0xFFFFFFFF, 7445),
5753 /* PowerPC 7455 v3.2 (G4) */
5754 POWERPC_DEF("7455v3.2", CPU_POWERPC_74x5_v32
, 0xFFFFFFFF, 7455),
5755 /* PowerPC 7445 v3.3 (G4) */
5756 POWERPC_DEF("7445v3.3", CPU_POWERPC_74x5_v33
, 0xFFFFFFFF, 7445),
5757 /* PowerPC 7455 v3.3 (G4) */
5758 POWERPC_DEF("7455v3.3", CPU_POWERPC_74x5_v33
, 0xFFFFFFFF, 7455),
5759 /* PowerPC 7445 v3.4 (G4) */
5760 POWERPC_DEF("7445v3.4", CPU_POWERPC_74x5_v34
, 0xFFFFFFFF, 7445),
5761 /* PowerPC 7455 v3.4 (G4) */
5762 POWERPC_DEF("7455v3.4", CPU_POWERPC_74x5_v34
, 0xFFFFFFFF, 7455),
5763 /* PowerPC 7447 (G4) */
5764 POWERPC_DEF("7447", CPU_POWERPC_74x7
, 0xFFFFFFFF, 7445),
5765 /* PowerPC 7457 (G4) */
5766 POWERPC_DEF("7457", CPU_POWERPC_74x7
, 0xFFFFFFFF, 7455),
5767 /* Code name for PowerPC 7447/7457 */
5768 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7
, 0xFFFFFFFF, 7455),
5769 /* PowerPC 7447 v1.0 (G4) */
5770 POWERPC_DEF("7447v1.0", CPU_POWERPC_74x7_v10
, 0xFFFFFFFF, 7445),
5771 /* PowerPC 7457 v1.0 (G4) */
5772 POWERPC_DEF("7457v1.0", CPU_POWERPC_74x7_v10
, 0xFFFFFFFF, 7455),
5773 /* Code name for PowerPC 7447A/7457A */
5774 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10
, 0xFFFFFFFF, 7455),
5775 /* PowerPC 7447 v1.1 (G4) */
5776 POWERPC_DEF("7447v1.1", CPU_POWERPC_74x7_v11
, 0xFFFFFFFF, 7445),
5777 /* PowerPC 7457 v1.1 (G4) */
5778 POWERPC_DEF("7457v1.1", CPU_POWERPC_74x7_v11
, 0xFFFFFFFF, 7455),
5779 /* PowerPC 7447 v1.2 (G4) */
5780 POWERPC_DEF("7447v1.2", CPU_POWERPC_74x7_v12
, 0xFFFFFFFF, 7445),
5781 /* PowerPC 7457 v1.2 (G4) */
5782 POWERPC_DEF("7457v1.2", CPU_POWERPC_74x7_v12
, 0xFFFFFFFF, 7455),
5783 /* 64 bits PowerPC */
5784 #if defined (TARGET_PPC64)
5786 POWERPC_DEF("620", CPU_POWERPC_620
, 0xFFFFFFFF, 620),
5788 /* PowerPC 630 (POWER3) */
5789 POWERPC_DEF("630", CPU_POWERPC_630
, 0xFFFFFFFF, 630),
5790 POWERPC_DEF("POWER3", CPU_POWERPC_630
, 0xFFFFFFFF, 630),
5793 /* PowerPC 631 (Power 3+) */
5794 POWERPC_DEF("631", CPU_POWERPC_631
, 0xFFFFFFFF, 631),
5795 POWERPC_DEF("POWER3+", CPU_POWERPC_631
, 0xFFFFFFFF, 631),
5799 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4
, 0xFFFFFFFF, POWER4
),
5803 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P
, 0xFFFFFFFF, POWER4P
),
5807 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5
, 0xFFFFFFFF, POWER5
),
5809 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR
, 0xFFFFFFFF, POWER5
),
5813 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P
, 0xFFFFFFFF, POWER5P
),
5815 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS
, 0xFFFFFFFF, POWER5P
),
5819 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6
, 0xFFFFFFFF, POWER6
),
5820 /* POWER6 running in POWER5 mode */
5821 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5
, 0xFFFFFFFF, POWER5
),
5823 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A
, 0xFFFFFFFF, POWER6
),
5826 POWERPC_DEF("970", CPU_POWERPC_970
, 0xFFFFFFFF, 970),
5827 /* PowerPC 970FX (G5) */
5828 POWERPC_DEF("970fx", CPU_POWERPC_970FX
, 0xFFFFFFFF, 970FX
),
5829 /* PowerPC 970FX v1.0 (G5) */
5830 POWERPC_DEF("970fx1.0", CPU_POWERPC_970FX_v10
, 0xFFFFFFFF, 970FX
),
5831 /* PowerPC 970FX v2.0 (G5) */
5832 POWERPC_DEF("970fx2.0", CPU_POWERPC_970FX_v20
, 0xFFFFFFFF, 970FX
),
5833 /* PowerPC 970FX v2.1 (G5) */
5834 POWERPC_DEF("970fx2.1", CPU_POWERPC_970FX_v21
, 0xFFFFFFFF, 970FX
),
5835 /* PowerPC 970FX v3.0 (G5) */
5836 POWERPC_DEF("970fx3.0", CPU_POWERPC_970FX_v30
, 0xFFFFFFFF, 970FX
),
5837 /* PowerPC 970FX v3.1 (G5) */
5838 POWERPC_DEF("970fx3.1", CPU_POWERPC_970FX_v31
, 0xFFFFFFFF, 970FX
),
5839 /* PowerPC 970GX (G5) */
5840 POWERPC_DEF("970gx", CPU_POWERPC_970GX
, 0xFFFFFFFF, 970GX
),
5842 POWERPC_DEF("970mp", CPU_POWERPC_970MP
, 0xFFFFFFFF, 970MP
),
5843 /* PowerPC 970MP v1.0 */
5844 POWERPC_DEF("970mp1.0", CPU_POWERPC_970MP_v10
, 0xFFFFFFFF, 970MP
),
5845 /* PowerPC 970MP v1.1 */
5846 POWERPC_DEF("970mp1.1", CPU_POWERPC_970MP_v11
, 0xFFFFFFFF, 970MP
),
5849 POWERPC_DEF("Cell", CPU_POWERPC_CELL
, 0xFFFFFFFF, 970),
5852 /* PowerPC Cell v1.0 */
5853 POWERPC_DEF("Cell1.0", CPU_POWERPC_CELL_v10
, 0xFFFFFFFF, 970),
5856 /* PowerPC Cell v2.0 */
5857 POWERPC_DEF("Cell2.0", CPU_POWERPC_CELL_v20
, 0xFFFFFFFF, 970),
5860 /* PowerPC Cell v3.0 */
5861 POWERPC_DEF("Cell3.0", CPU_POWERPC_CELL_v30
, 0xFFFFFFFF, 970),
5864 /* PowerPC Cell v3.1 */
5865 POWERPC_DEF("Cell3.1", CPU_POWERPC_CELL_v31
, 0xFFFFFFFF, 970),
5868 /* PowerPC Cell v3.2 */
5869 POWERPC_DEF("Cell3.2", CPU_POWERPC_CELL_v32
, 0xFFFFFFFF, 970),
5872 /* RS64 (Apache/A35) */
5873 /* This one seems to support the whole POWER2 instruction set
5874 * and the PowerPC 64 one.
5876 /* What about A10 & A30 ? */
5877 POWERPC_DEF("RS64", CPU_POWERPC_RS64
, 0xFFFFFFFF, RS64
),
5878 POWERPC_DEF("Apache", CPU_POWERPC_RS64
, 0xFFFFFFFF, RS64
),
5879 POWERPC_DEF("A35", CPU_POWERPC_RS64
, 0xFFFFFFFF, RS64
),
5882 /* RS64-II (NorthStar/A50) */
5883 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II
, 0xFFFFFFFF, RS64
),
5884 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II
, 0xFFFFFFFF, RS64
),
5885 POWERPC_DEF("A50", CPU_POWERPC_RS64II
, 0xFFFFFFFF, RS64
),
5888 /* RS64-III (Pulsar) */
5889 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III
, 0xFFFFFFFF, RS64
),
5890 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III
, 0xFFFFFFFF, RS64
),
5893 /* RS64-IV (IceStar/IStar/SStar) */
5894 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV
, 0xFFFFFFFF, RS64
),
5895 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV
, 0xFFFFFFFF, RS64
),
5896 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV
, 0xFFFFFFFF, RS64
),
5897 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV
, 0xFFFFFFFF, RS64
),
5899 #endif /* defined (TARGET_PPC64) */
5902 /* Original POWER */
5903 POWERPC_DEF("POWER", CPU_POWERPC_POWER
, 0xFFFFFFFF, POWER
),
5904 POWERPC_DEF("RIOS", CPU_POWERPC_POWER
, 0xFFFFFFFF, POWER
),
5905 POWERPC_DEF("RSC", CPU_POWERPC_POWER
, 0xFFFFFFFF, POWER
),
5906 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER
, 0xFFFFFFFF, POWER
),
5907 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER
, 0xFFFFFFFF, POWER
),
5911 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2
, 0xFFFFFFFF, POWER
),
5912 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2
, 0xFFFFFFFF, POWER
),
5913 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2
, 0xFFFFFFFF, POWER
),
5918 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T
, 0xFFFFFFFF, PA6T
),
5920 /* Generic PowerPCs */
5921 #if defined (TARGET_PPC64)
5923 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64
, 0xFFFFFFFF, PPC64
),
5926 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32
, 0xFFFFFFFF, PPC32
),
5927 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT
, 0xFFFFFFFF, DEFAULT
),
5929 POWERPC_DEF("default", CPU_POWERPC_DEFAULT
, 0xFFFFFFFF, DEFAULT
),
5932 /*****************************************************************************/
5933 /* Generic CPU instanciation routine */
5934 static void init_ppc_proc (CPUPPCState
*env
, ppc_def_t
*def
)
5936 #if !defined(CONFIG_USER_ONLY)
5939 env
->irq_inputs
= NULL
;
5940 /* Set all exception vectors to an invalid address */
5941 for (i
= 0; i
< POWERPC_EXCP_NB
; i
++)
5942 env
->excp_vectors
[i
] = (target_ulong
)(-1ULL);
5943 env
->excp_prefix
= 0x00000000;
5944 env
->ivor_mask
= 0x00000000;
5945 env
->ivpr_mask
= 0x00000000;
5946 /* Default MMU definitions */
5951 /* Register SPR common to all PowerPC implementations */
5952 gen_spr_generic(env
);
5953 spr_register(env
, SPR_PVR
, "PVR",
5954 SPR_NOACCESS
, SPR_NOACCESS
,
5955 &spr_read_generic
, SPR_NOACCESS
,
5957 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
5958 (*def
->init_proc
)(env
);
5959 /* MSR bits & flags consistency checks */
5960 if (env
->msr_mask
& (1 << 25)) {
5961 switch (env
->flags
& (POWERPC_FLAG_SPE
| POWERPC_FLAG_VRE
)) {
5962 case POWERPC_FLAG_SPE
:
5963 case POWERPC_FLAG_VRE
:
5966 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
5967 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
5970 } else if (env
->flags
& (POWERPC_FLAG_SPE
| POWERPC_FLAG_VRE
)) {
5971 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
5972 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
5975 if (env
->msr_mask
& (1 << 17)) {
5976 switch (env
->flags
& (POWERPC_FLAG_TGPR
| POWERPC_FLAG_CE
)) {
5977 case POWERPC_FLAG_TGPR
:
5978 case POWERPC_FLAG_CE
:
5981 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
5982 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
5985 } else if (env
->flags
& (POWERPC_FLAG_TGPR
| POWERPC_FLAG_CE
)) {
5986 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
5987 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
5990 if (env
->msr_mask
& (1 << 10)) {
5991 switch (env
->flags
& (POWERPC_FLAG_SE
| POWERPC_FLAG_DWE
|
5992 POWERPC_FLAG_UBLE
)) {
5993 case POWERPC_FLAG_SE
:
5994 case POWERPC_FLAG_DWE
:
5995 case POWERPC_FLAG_UBLE
:
5998 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
5999 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
6000 "POWERPC_FLAG_UBLE\n");
6003 } else if (env
->flags
& (POWERPC_FLAG_SE
| POWERPC_FLAG_DWE
|
6004 POWERPC_FLAG_UBLE
)) {
6005 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
6006 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
6007 "POWERPC_FLAG_UBLE\n");
6010 if (env
->msr_mask
& (1 << 9)) {
6011 switch (env
->flags
& (POWERPC_FLAG_BE
| POWERPC_FLAG_DE
)) {
6012 case POWERPC_FLAG_BE
:
6013 case POWERPC_FLAG_DE
:
6016 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
6017 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
6020 } else if (env
->flags
& (POWERPC_FLAG_BE
| POWERPC_FLAG_DE
)) {
6021 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
6022 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
6025 if (env
->msr_mask
& (1 << 2)) {
6026 switch (env
->flags
& (POWERPC_FLAG_PX
| POWERPC_FLAG_PMM
)) {
6027 case POWERPC_FLAG_PX
:
6028 case POWERPC_FLAG_PMM
:
6031 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
6032 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
6035 } else if (env
->flags
& (POWERPC_FLAG_PX
| POWERPC_FLAG_PMM
)) {
6036 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
6037 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
6040 /* Allocate TLBs buffer when needed */
6041 #if !defined(CONFIG_USER_ONLY)
6042 if (env
->nb_tlb
!= 0) {
6043 int nb_tlb
= env
->nb_tlb
;
6044 if (env
->id_tlbs
!= 0)
6046 env
->tlb
= qemu_mallocz(nb_tlb
* sizeof(ppc_tlb_t
));
6047 /* Pre-compute some useful values */
6048 env
->tlb_per_way
= env
->nb_tlb
/ env
->nb_ways
;
6050 if (env
->irq_inputs
== NULL
) {
6051 fprintf(stderr
, "WARNING: no internal IRQ controller registered.\n"
6052 " Attempt Qemu to crash very soon !\n");
6055 if (env
->check_pow
== NULL
) {
6056 fprintf(stderr
, "WARNING: no power management check handler "
6058 " Attempt Qemu to crash very soon !\n");
6062 #if defined(PPC_DUMP_CPU)
6063 static void dump_ppc_sprs (CPUPPCState
*env
)
6066 #if !defined(CONFIG_USER_ONLY)
6072 printf("Special purpose registers:\n");
6073 for (i
= 0; i
< 32; i
++) {
6074 for (j
= 0; j
< 32; j
++) {
6076 spr
= &env
->spr_cb
[n
];
6077 uw
= spr
->uea_write
!= NULL
&& spr
->uea_write
!= SPR_NOACCESS
;
6078 ur
= spr
->uea_read
!= NULL
&& spr
->uea_read
!= SPR_NOACCESS
;
6079 #if !defined(CONFIG_USER_ONLY)
6080 sw
= spr
->oea_write
!= NULL
&& spr
->oea_write
!= SPR_NOACCESS
;
6081 sr
= spr
->oea_read
!= NULL
&& spr
->oea_read
!= SPR_NOACCESS
;
6082 if (sw
|| sr
|| uw
|| ur
) {
6083 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
6084 (i
<< 5) | j
, (i
<< 5) | j
, spr
->name
,
6085 sw
? 'w' : '-', sr
? 'r' : '-',
6086 uw
? 'w' : '-', ur
? 'r' : '-');
6090 printf("SPR: %4d (%03x) %-8s u%c%c\n",
6091 (i
<< 5) | j
, (i
<< 5) | j
, spr
->name
,
6092 uw
? 'w' : '-', ur
? 'r' : '-');
6102 /*****************************************************************************/
6106 int fflush (FILE *stream
);
6110 PPC_DIRECT
= 0, /* Opcode routine */
6111 PPC_INDIRECT
= 1, /* Indirect opcode table */
6114 static inline int is_indirect_opcode (void *handler
)
6116 return ((unsigned long)handler
& 0x03) == PPC_INDIRECT
;
6119 static inline opc_handler_t
**ind_table(void *handler
)
6121 return (opc_handler_t
**)((unsigned long)handler
& ~3);
6124 /* Instruction table creation */
6125 /* Opcodes tables creation */
6126 static void fill_new_table (opc_handler_t
**table
, int len
)
6130 for (i
= 0; i
< len
; i
++)
6131 table
[i
] = &invalid_handler
;
6134 static int create_new_table (opc_handler_t
**table
, unsigned char idx
)
6136 opc_handler_t
**tmp
;
6138 tmp
= malloc(0x20 * sizeof(opc_handler_t
));
6141 fill_new_table(tmp
, 0x20);
6142 table
[idx
] = (opc_handler_t
*)((unsigned long)tmp
| PPC_INDIRECT
);
6147 static int insert_in_table (opc_handler_t
**table
, unsigned char idx
,
6148 opc_handler_t
*handler
)
6150 if (table
[idx
] != &invalid_handler
)
6152 table
[idx
] = handler
;
6157 static int register_direct_insn (opc_handler_t
**ppc_opcodes
,
6158 unsigned char idx
, opc_handler_t
*handler
)
6160 if (insert_in_table(ppc_opcodes
, idx
, handler
) < 0) {
6161 printf("*** ERROR: opcode %02x already assigned in main "
6162 "opcode table\n", idx
);
6169 static int register_ind_in_table (opc_handler_t
**table
,
6170 unsigned char idx1
, unsigned char idx2
,
6171 opc_handler_t
*handler
)
6173 if (table
[idx1
] == &invalid_handler
) {
6174 if (create_new_table(table
, idx1
) < 0) {
6175 printf("*** ERROR: unable to create indirect table "
6176 "idx=%02x\n", idx1
);
6180 if (!is_indirect_opcode(table
[idx1
])) {
6181 printf("*** ERROR: idx %02x already assigned to a direct "
6186 if (handler
!= NULL
&&
6187 insert_in_table(ind_table(table
[idx1
]), idx2
, handler
) < 0) {
6188 printf("*** ERROR: opcode %02x already assigned in "
6189 "opcode table %02x\n", idx2
, idx1
);
6196 static int register_ind_insn (opc_handler_t
**ppc_opcodes
,
6197 unsigned char idx1
, unsigned char idx2
,
6198 opc_handler_t
*handler
)
6202 ret
= register_ind_in_table(ppc_opcodes
, idx1
, idx2
, handler
);
6207 static int register_dblind_insn (opc_handler_t
**ppc_opcodes
,
6208 unsigned char idx1
, unsigned char idx2
,
6209 unsigned char idx3
, opc_handler_t
*handler
)
6211 if (register_ind_in_table(ppc_opcodes
, idx1
, idx2
, NULL
) < 0) {
6212 printf("*** ERROR: unable to join indirect table idx "
6213 "[%02x-%02x]\n", idx1
, idx2
);
6216 if (register_ind_in_table(ind_table(ppc_opcodes
[idx1
]), idx2
, idx3
,
6218 printf("*** ERROR: unable to insert opcode "
6219 "[%02x-%02x-%02x]\n", idx1
, idx2
, idx3
);
6226 static int register_insn (opc_handler_t
**ppc_opcodes
, opcode_t
*insn
)
6228 if (insn
->opc2
!= 0xFF) {
6229 if (insn
->opc3
!= 0xFF) {
6230 if (register_dblind_insn(ppc_opcodes
, insn
->opc1
, insn
->opc2
,
6231 insn
->opc3
, &insn
->handler
) < 0)
6234 if (register_ind_insn(ppc_opcodes
, insn
->opc1
,
6235 insn
->opc2
, &insn
->handler
) < 0)
6239 if (register_direct_insn(ppc_opcodes
, insn
->opc1
, &insn
->handler
) < 0)
6246 static int test_opcode_table (opc_handler_t
**table
, int len
)
6250 for (i
= 0, count
= 0; i
< len
; i
++) {
6251 /* Consistency fixup */
6252 if (table
[i
] == NULL
)
6253 table
[i
] = &invalid_handler
;
6254 if (table
[i
] != &invalid_handler
) {
6255 if (is_indirect_opcode(table
[i
])) {
6256 tmp
= test_opcode_table(ind_table(table
[i
]), 0x20);
6259 table
[i
] = &invalid_handler
;
6272 static void fix_opcode_tables (opc_handler_t
**ppc_opcodes
)
6274 if (test_opcode_table(ppc_opcodes
, 0x40) == 0)
6275 printf("*** WARNING: no opcode defined !\n");
6278 /*****************************************************************************/
6279 static int create_ppc_opcodes (CPUPPCState
*env
, ppc_def_t
*def
)
6281 opcode_t
*opc
, *start
, *end
;
6283 fill_new_table(env
->opcodes
, 0x40);
6284 if (&opc_start
< &opc_end
) {
6291 for (opc
= start
+ 1; opc
!= end
; opc
++) {
6292 if ((opc
->handler
.type
& def
->insns_flags
) != 0) {
6293 if (register_insn(env
->opcodes
, opc
) < 0) {
6294 printf("*** ERROR initializing PowerPC instruction "
6295 "0x%02x 0x%02x 0x%02x\n", opc
->opc1
, opc
->opc2
,
6301 fix_opcode_tables(env
->opcodes
);
6308 #if defined(PPC_DUMP_CPU)
6309 static void dump_ppc_insns (CPUPPCState
*env
)
6311 opc_handler_t
**table
, *handler
;
6312 uint8_t opc1
, opc2
, opc3
;
6314 printf("Instructions set:\n");
6315 /* opc1 is 6 bits long */
6316 for (opc1
= 0x00; opc1
< 0x40; opc1
++) {
6317 table
= env
->opcodes
;
6318 handler
= table
[opc1
];
6319 if (is_indirect_opcode(handler
)) {
6320 /* opc2 is 5 bits long */
6321 for (opc2
= 0; opc2
< 0x20; opc2
++) {
6322 table
= env
->opcodes
;
6323 handler
= env
->opcodes
[opc1
];
6324 table
= ind_table(handler
);
6325 handler
= table
[opc2
];
6326 if (is_indirect_opcode(handler
)) {
6327 table
= ind_table(handler
);
6328 /* opc3 is 5 bits long */
6329 for (opc3
= 0; opc3
< 0x20; opc3
++) {
6330 handler
= table
[opc3
];
6331 if (handler
->handler
!= &gen_invalid
) {
6332 printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
6333 opc1
, opc2
, opc3
, opc1
, (opc3
<< 5) | opc2
,
6338 if (handler
->handler
!= &gen_invalid
) {
6339 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
6340 opc1
, opc2
, opc1
, opc2
, handler
->oname
);
6345 if (handler
->handler
!= &gen_invalid
) {
6346 printf("INSN: %02x -- -- (%02d ----) : %s\n",
6347 opc1
, opc1
, handler
->oname
);
6354 int cpu_ppc_register (CPUPPCState
*env
, ppc_def_t
*def
)
6356 env
->msr_mask
= def
->msr_mask
;
6357 env
->mmu_model
= def
->mmu_model
;
6358 env
->excp_model
= def
->excp_model
;
6359 env
->bus_model
= def
->bus_model
;
6360 env
->flags
= def
->flags
;
6361 env
->bfd_mach
= def
->bfd_mach
;
6362 env
->check_pow
= def
->check_pow
;
6363 if (create_ppc_opcodes(env
, def
) < 0)
6365 init_ppc_proc(env
, def
);
6366 #if defined(PPC_DUMP_CPU)
6368 const unsigned char *mmu_model
, *excp_model
, *bus_model
;
6369 switch (env
->mmu_model
) {
6370 case POWERPC_MMU_32B
:
6371 mmu_model
= "PowerPC 32";
6373 case POWERPC_MMU_SOFT_6xx
:
6374 mmu_model
= "PowerPC 6xx/7xx with software driven TLBs";
6376 case POWERPC_MMU_SOFT_74xx
:
6377 mmu_model
= "PowerPC 74xx with software driven TLBs";
6379 case POWERPC_MMU_SOFT_4xx
:
6380 mmu_model
= "PowerPC 4xx with software driven TLBs";
6382 case POWERPC_MMU_SOFT_4xx_Z
:
6383 mmu_model
= "PowerPC 4xx with software driven TLBs "
6384 "and zones protections";
6386 case POWERPC_MMU_REAL_4xx
:
6387 mmu_model
= "PowerPC 4xx real mode only";
6389 case POWERPC_MMU_BOOKE
:
6390 mmu_model
= "PowerPC BookE";
6392 case POWERPC_MMU_BOOKE_FSL
:
6393 mmu_model
= "PowerPC BookE FSL";
6395 #if defined (TARGET_PPC64)
6396 case POWERPC_MMU_64B
:
6397 mmu_model
= "PowerPC 64";
6401 mmu_model
= "Unknown or invalid";
6404 switch (env
->excp_model
) {
6405 case POWERPC_EXCP_STD
:
6406 excp_model
= "PowerPC";
6408 case POWERPC_EXCP_40x
:
6409 excp_model
= "PowerPC 40x";
6411 case POWERPC_EXCP_601
:
6412 excp_model
= "PowerPC 601";
6414 case POWERPC_EXCP_602
:
6415 excp_model
= "PowerPC 602";
6417 case POWERPC_EXCP_603
:
6418 excp_model
= "PowerPC 603";
6420 case POWERPC_EXCP_603E
:
6421 excp_model
= "PowerPC 603e";
6423 case POWERPC_EXCP_604
:
6424 excp_model
= "PowerPC 604";
6426 case POWERPC_EXCP_7x0
:
6427 excp_model
= "PowerPC 740/750";
6429 case POWERPC_EXCP_7x5
:
6430 excp_model
= "PowerPC 745/755";
6432 case POWERPC_EXCP_74xx
:
6433 excp_model
= "PowerPC 74xx";
6435 case POWERPC_EXCP_BOOKE
:
6436 excp_model
= "PowerPC BookE";
6438 #if defined (TARGET_PPC64)
6439 case POWERPC_EXCP_970
:
6440 excp_model
= "PowerPC 970";
6444 excp_model
= "Unknown or invalid";
6447 switch (env
->bus_model
) {
6448 case PPC_FLAGS_INPUT_6xx
:
6449 bus_model
= "PowerPC 6xx";
6451 case PPC_FLAGS_INPUT_BookE
:
6452 bus_model
= "PowerPC BookE";
6454 case PPC_FLAGS_INPUT_405
:
6455 bus_model
= "PowerPC 405";
6457 case PPC_FLAGS_INPUT_401
:
6458 bus_model
= "PowerPC 401/403";
6460 #if defined (TARGET_PPC64)
6461 case PPC_FLAGS_INPUT_970
:
6462 bus_model
= "PowerPC 970";
6466 bus_model
= "Unknown or invalid";
6469 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64
"\n"
6470 " MMU model : %s\n",
6471 def
->name
, def
->pvr
, def
->msr_mask
, mmu_model
);
6472 #if !defined(CONFIG_USER_ONLY)
6473 if (env
->tlb
!= NULL
) {
6474 printf(" %d %s TLB in %d ways\n",
6475 env
->nb_tlb
, env
->id_tlbs
? "splitted" : "merged",
6479 printf(" Exceptions model : %s\n"
6480 " Bus model : %s\n",
6481 excp_model
, bus_model
);
6482 printf(" MSR features :\n");
6483 if (env
->flags
& POWERPC_FLAG_SPE
)
6484 printf(" signal processing engine enable"
6486 else if (env
->flags
& POWERPC_FLAG_VRE
)
6487 printf(" vector processor enable\n");
6488 if (env
->flags
& POWERPC_FLAG_TGPR
)
6489 printf(" temporary GPRs\n");
6490 else if (env
->flags
& POWERPC_FLAG_CE
)
6491 printf(" critical input enable\n");
6492 if (env
->flags
& POWERPC_FLAG_SE
)
6493 printf(" single-step trace mode\n");
6494 else if (env
->flags
& POWERPC_FLAG_DWE
)
6495 printf(" debug wait enable\n");
6496 else if (env
->flags
& POWERPC_FLAG_UBLE
)
6497 printf(" user BTB lock enable\n");
6498 if (env
->flags
& POWERPC_FLAG_BE
)
6499 printf(" branch-step trace mode\n");
6500 else if (env
->flags
& POWERPC_FLAG_DE
)
6501 printf(" debug interrupt enable\n");
6502 if (env
->flags
& POWERPC_FLAG_PX
)
6503 printf(" inclusive protection\n");
6504 else if (env
->flags
& POWERPC_FLAG_PMM
)
6505 printf(" performance monitor mark\n");
6506 if (env
->flags
== POWERPC_FLAG_NONE
)
6509 dump_ppc_insns(env
);
6517 int ppc_find_by_name (const unsigned char *name
, ppc_def_t
**def
)
6523 max
= sizeof(ppc_defs
) / sizeof(ppc_def_t
);
6524 for (i
= 0; i
< max
; i
++) {
6525 if (strcasecmp(name
, ppc_defs
[i
].name
) == 0) {
6526 *def
= &ppc_defs
[i
];
6535 int ppc_find_by_pvr (uint32_t pvr
, ppc_def_t
**def
)
6541 max
= sizeof(ppc_defs
) / sizeof(ppc_def_t
);
6542 for (i
= 0; i
< max
; i
++) {
6543 if ((pvr
& ppc_defs
[i
].pvr_mask
) ==
6544 (ppc_defs
[i
].pvr
& ppc_defs
[i
].pvr_mask
)) {
6545 *def
= &ppc_defs
[i
];
6554 void ppc_cpu_list (FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...))
6558 max
= sizeof(ppc_defs
) / sizeof(ppc_def_t
);
6559 for (i
= 0; i
< max
; i
++) {
6560 (*cpu_fprintf
)(f
, "PowerPC %-16s PVR %08x\n",
6561 ppc_defs
[i
].name
, ppc_defs
[i
].pvr
);