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Merge branch 'ppc-next' of git://repo.or.cz/qemu/agraf
[mirror_qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
26 #include "dis-asm.h"
27 #include "gdbstub.h"
28 #include <kvm.h>
29 #include "kvm_ppc.h"
30
31 //#define PPC_DUMP_CPU
32 //#define PPC_DEBUG_SPR
33 //#define PPC_DUMP_SPR_ACCESSES
34 #if defined(CONFIG_USER_ONLY)
35 #define TODO_USER_ONLY 1
36 #endif
37
38 /* For user-mode emulation, we don't emulate any IRQ controller */
39 #if defined(CONFIG_USER_ONLY)
40 #define PPC_IRQ_INIT_FN(name) \
41 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
42 { \
43 }
44 #else
45 #define PPC_IRQ_INIT_FN(name) \
46 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
47 #endif
48
49 PPC_IRQ_INIT_FN(40x);
50 PPC_IRQ_INIT_FN(6xx);
51 PPC_IRQ_INIT_FN(970);
52 PPC_IRQ_INIT_FN(POWER7);
53 PPC_IRQ_INIT_FN(e500);
54
55 /* Generic callbacks:
56 * do nothing but store/retrieve spr value
57 */
58 static void spr_read_generic (void *opaque, int gprn, int sprn)
59 {
60 gen_load_spr(cpu_gpr[gprn], sprn);
61 #ifdef PPC_DUMP_SPR_ACCESSES
62 {
63 TCGv_i32 t0 = tcg_const_i32(sprn);
64 gen_helper_load_dump_spr(t0);
65 tcg_temp_free_i32(t0);
66 }
67 #endif
68 }
69
70 static void spr_write_generic (void *opaque, int sprn, int gprn)
71 {
72 gen_store_spr(sprn, cpu_gpr[gprn]);
73 #ifdef PPC_DUMP_SPR_ACCESSES
74 {
75 TCGv_i32 t0 = tcg_const_i32(sprn);
76 gen_helper_store_dump_spr(t0);
77 tcg_temp_free_i32(t0);
78 }
79 #endif
80 }
81
82 #if !defined(CONFIG_USER_ONLY)
83 static void spr_write_clear (void *opaque, int sprn, int gprn)
84 {
85 TCGv t0 = tcg_temp_new();
86 TCGv t1 = tcg_temp_new();
87 gen_load_spr(t0, sprn);
88 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
89 tcg_gen_and_tl(t0, t0, t1);
90 gen_store_spr(sprn, t0);
91 tcg_temp_free(t0);
92 tcg_temp_free(t1);
93 }
94 #endif
95
96 /* SPR common to all PowerPC */
97 /* XER */
98 static void spr_read_xer (void *opaque, int gprn, int sprn)
99 {
100 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
101 }
102
103 static void spr_write_xer (void *opaque, int sprn, int gprn)
104 {
105 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
106 }
107
108 /* LR */
109 static void spr_read_lr (void *opaque, int gprn, int sprn)
110 {
111 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
112 }
113
114 static void spr_write_lr (void *opaque, int sprn, int gprn)
115 {
116 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
117 }
118
119 /* CFAR */
120 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
121 static void spr_read_cfar (void *opaque, int gprn, int sprn)
122 {
123 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
124 }
125
126 static void spr_write_cfar (void *opaque, int sprn, int gprn)
127 {
128 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
129 }
130 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
131
132 /* CTR */
133 static void spr_read_ctr (void *opaque, int gprn, int sprn)
134 {
135 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
136 }
137
138 static void spr_write_ctr (void *opaque, int sprn, int gprn)
139 {
140 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
141 }
142
143 /* User read access to SPR */
144 /* USPRx */
145 /* UMMCRx */
146 /* UPMCx */
147 /* USIA */
148 /* UDECR */
149 static void spr_read_ureg (void *opaque, int gprn, int sprn)
150 {
151 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
152 }
153
154 /* SPR common to all non-embedded PowerPC */
155 /* DECR */
156 #if !defined(CONFIG_USER_ONLY)
157 static void spr_read_decr (void *opaque, int gprn, int sprn)
158 {
159 if (use_icount) {
160 gen_io_start();
161 }
162 gen_helper_load_decr(cpu_gpr[gprn]);
163 if (use_icount) {
164 gen_io_end();
165 gen_stop_exception(opaque);
166 }
167 }
168
169 static void spr_write_decr (void *opaque, int sprn, int gprn)
170 {
171 if (use_icount) {
172 gen_io_start();
173 }
174 gen_helper_store_decr(cpu_gpr[gprn]);
175 if (use_icount) {
176 gen_io_end();
177 gen_stop_exception(opaque);
178 }
179 }
180 #endif
181
182 /* SPR common to all non-embedded PowerPC, except 601 */
183 /* Time base */
184 static void spr_read_tbl (void *opaque, int gprn, int sprn)
185 {
186 if (use_icount) {
187 gen_io_start();
188 }
189 gen_helper_load_tbl(cpu_gpr[gprn]);
190 if (use_icount) {
191 gen_io_end();
192 gen_stop_exception(opaque);
193 }
194 }
195
196 static void spr_read_tbu (void *opaque, int gprn, int sprn)
197 {
198 if (use_icount) {
199 gen_io_start();
200 }
201 gen_helper_load_tbu(cpu_gpr[gprn]);
202 if (use_icount) {
203 gen_io_end();
204 gen_stop_exception(opaque);
205 }
206 }
207
208 __attribute__ (( unused ))
209 static void spr_read_atbl (void *opaque, int gprn, int sprn)
210 {
211 gen_helper_load_atbl(cpu_gpr[gprn]);
212 }
213
214 __attribute__ (( unused ))
215 static void spr_read_atbu (void *opaque, int gprn, int sprn)
216 {
217 gen_helper_load_atbu(cpu_gpr[gprn]);
218 }
219
220 #if !defined(CONFIG_USER_ONLY)
221 static void spr_write_tbl (void *opaque, int sprn, int gprn)
222 {
223 if (use_icount) {
224 gen_io_start();
225 }
226 gen_helper_store_tbl(cpu_gpr[gprn]);
227 if (use_icount) {
228 gen_io_end();
229 gen_stop_exception(opaque);
230 }
231 }
232
233 static void spr_write_tbu (void *opaque, int sprn, int gprn)
234 {
235 if (use_icount) {
236 gen_io_start();
237 }
238 gen_helper_store_tbu(cpu_gpr[gprn]);
239 if (use_icount) {
240 gen_io_end();
241 gen_stop_exception(opaque);
242 }
243 }
244
245 __attribute__ (( unused ))
246 static void spr_write_atbl (void *opaque, int sprn, int gprn)
247 {
248 gen_helper_store_atbl(cpu_gpr[gprn]);
249 }
250
251 __attribute__ (( unused ))
252 static void spr_write_atbu (void *opaque, int sprn, int gprn)
253 {
254 gen_helper_store_atbu(cpu_gpr[gprn]);
255 }
256
257 #if defined(TARGET_PPC64)
258 __attribute__ (( unused ))
259 static void spr_read_purr (void *opaque, int gprn, int sprn)
260 {
261 gen_helper_load_purr(cpu_gpr[gprn]);
262 }
263 #endif
264 #endif
265
266 #if !defined(CONFIG_USER_ONLY)
267 /* IBAT0U...IBAT0U */
268 /* IBAT0L...IBAT7L */
269 static void spr_read_ibat (void *opaque, int gprn, int sprn)
270 {
271 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
272 }
273
274 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
275 {
276 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
277 }
278
279 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
280 {
281 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
282 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
283 tcg_temp_free_i32(t0);
284 }
285
286 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
287 {
288 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
289 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
290 tcg_temp_free_i32(t0);
291 }
292
293 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
294 {
295 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
296 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
297 tcg_temp_free_i32(t0);
298 }
299
300 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
301 {
302 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
303 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
304 tcg_temp_free_i32(t0);
305 }
306
307 /* DBAT0U...DBAT7U */
308 /* DBAT0L...DBAT7L */
309 static void spr_read_dbat (void *opaque, int gprn, int sprn)
310 {
311 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
312 }
313
314 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
315 {
316 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
317 }
318
319 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
320 {
321 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
322 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
323 tcg_temp_free_i32(t0);
324 }
325
326 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
327 {
328 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
329 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
330 tcg_temp_free_i32(t0);
331 }
332
333 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
334 {
335 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
336 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
337 tcg_temp_free_i32(t0);
338 }
339
340 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
341 {
342 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
343 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
344 tcg_temp_free_i32(t0);
345 }
346
347 /* SDR1 */
348 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
349 {
350 gen_helper_store_sdr1(cpu_gpr[gprn]);
351 }
352
353 /* 64 bits PowerPC specific SPRs */
354 /* ASR */
355 #if defined(TARGET_PPC64)
356 static void spr_read_hior (void *opaque, int gprn, int sprn)
357 {
358 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
359 }
360
361 static void spr_write_hior (void *opaque, int sprn, int gprn)
362 {
363 TCGv t0 = tcg_temp_new();
364 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
365 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
366 tcg_temp_free(t0);
367 }
368
369 static void spr_read_asr (void *opaque, int gprn, int sprn)
370 {
371 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
372 }
373
374 static void spr_write_asr (void *opaque, int sprn, int gprn)
375 {
376 gen_helper_store_asr(cpu_gpr[gprn]);
377 }
378 #endif
379 #endif
380
381 /* PowerPC 601 specific registers */
382 /* RTC */
383 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
384 {
385 gen_helper_load_601_rtcl(cpu_gpr[gprn]);
386 }
387
388 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
389 {
390 gen_helper_load_601_rtcu(cpu_gpr[gprn]);
391 }
392
393 #if !defined(CONFIG_USER_ONLY)
394 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
395 {
396 gen_helper_store_601_rtcu(cpu_gpr[gprn]);
397 }
398
399 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
400 {
401 gen_helper_store_601_rtcl(cpu_gpr[gprn]);
402 }
403
404 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
405 {
406 DisasContext *ctx = opaque;
407
408 gen_helper_store_hid0_601(cpu_gpr[gprn]);
409 /* Must stop the translation as endianness may have changed */
410 gen_stop_exception(ctx);
411 }
412 #endif
413
414 /* Unified bats */
415 #if !defined(CONFIG_USER_ONLY)
416 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
417 {
418 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
419 }
420
421 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
422 {
423 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
424 gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
425 tcg_temp_free_i32(t0);
426 }
427
428 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
429 {
430 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
431 gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
432 tcg_temp_free_i32(t0);
433 }
434 #endif
435
436 /* PowerPC 40x specific registers */
437 #if !defined(CONFIG_USER_ONLY)
438 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
439 {
440 gen_helper_load_40x_pit(cpu_gpr[gprn]);
441 }
442
443 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
444 {
445 gen_helper_store_40x_pit(cpu_gpr[gprn]);
446 }
447
448 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
449 {
450 DisasContext *ctx = opaque;
451
452 gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
453 /* We must stop translation as we may have rebooted */
454 gen_stop_exception(ctx);
455 }
456
457 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
458 {
459 gen_helper_store_40x_sler(cpu_gpr[gprn]);
460 }
461
462 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
463 {
464 gen_helper_store_booke_tcr(cpu_gpr[gprn]);
465 }
466
467 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
468 {
469 gen_helper_store_booke_tsr(cpu_gpr[gprn]);
470 }
471 #endif
472
473 /* PowerPC 403 specific registers */
474 /* PBL1 / PBU1 / PBL2 / PBU2 */
475 #if !defined(CONFIG_USER_ONLY)
476 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
477 {
478 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
479 }
480
481 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
482 {
483 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
484 gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
485 tcg_temp_free_i32(t0);
486 }
487
488 static void spr_write_pir (void *opaque, int sprn, int gprn)
489 {
490 TCGv t0 = tcg_temp_new();
491 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
492 gen_store_spr(SPR_PIR, t0);
493 tcg_temp_free(t0);
494 }
495 #endif
496
497 /* SPE specific registers */
498 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
499 {
500 TCGv_i32 t0 = tcg_temp_new_i32();
501 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
502 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
503 tcg_temp_free_i32(t0);
504 }
505
506 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
507 {
508 TCGv_i32 t0 = tcg_temp_new_i32();
509 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
510 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
511 tcg_temp_free_i32(t0);
512 }
513
514 #if !defined(CONFIG_USER_ONLY)
515 /* Callback used to write the exception vector base */
516 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
517 {
518 TCGv t0 = tcg_temp_new();
519 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
520 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
521 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
522 gen_store_spr(sprn, t0);
523 tcg_temp_free(t0);
524 }
525
526 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
527 {
528 DisasContext *ctx = opaque;
529
530 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
531 TCGv t0 = tcg_temp_new();
532 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
533 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
534 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
535 gen_store_spr(sprn, t0);
536 tcg_temp_free(t0);
537 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
538 TCGv t0 = tcg_temp_new();
539 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
540 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
541 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
542 gen_store_spr(sprn, t0);
543 tcg_temp_free(t0);
544 } else {
545 printf("Trying to write an unknown exception vector %d %03x\n",
546 sprn, sprn);
547 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
548 }
549 }
550 #endif
551
552 static inline void vscr_init (CPUPPCState *env, uint32_t val)
553 {
554 env->vscr = val;
555 /* Altivec always uses round-to-nearest */
556 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
557 set_flush_to_zero(vscr_nj, &env->vec_status);
558 }
559
560 #if defined(CONFIG_USER_ONLY)
561 #define spr_register(env, num, name, uea_read, uea_write, \
562 oea_read, oea_write, initial_value) \
563 do { \
564 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
565 } while (0)
566 static inline void _spr_register (CPUPPCState *env, int num,
567 const char *name,
568 void (*uea_read)(void *opaque, int gprn, int sprn),
569 void (*uea_write)(void *opaque, int sprn, int gprn),
570 target_ulong initial_value)
571 #else
572 static inline void spr_register (CPUPPCState *env, int num,
573 const char *name,
574 void (*uea_read)(void *opaque, int gprn, int sprn),
575 void (*uea_write)(void *opaque, int sprn, int gprn),
576 void (*oea_read)(void *opaque, int gprn, int sprn),
577 void (*oea_write)(void *opaque, int sprn, int gprn),
578 target_ulong initial_value)
579 #endif
580 {
581 ppc_spr_t *spr;
582
583 spr = &env->spr_cb[num];
584 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
585 #if !defined(CONFIG_USER_ONLY)
586 spr->oea_read != NULL || spr->oea_write != NULL ||
587 #endif
588 spr->uea_read != NULL || spr->uea_write != NULL) {
589 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
590 exit(1);
591 }
592 #if defined(PPC_DEBUG_SPR)
593 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
594 name, initial_value);
595 #endif
596 spr->name = name;
597 spr->uea_read = uea_read;
598 spr->uea_write = uea_write;
599 #if !defined(CONFIG_USER_ONLY)
600 spr->oea_read = oea_read;
601 spr->oea_write = oea_write;
602 #endif
603 env->spr[num] = initial_value;
604 }
605
606 /* Generic PowerPC SPRs */
607 static void gen_spr_generic (CPUPPCState *env)
608 {
609 /* Integer processing */
610 spr_register(env, SPR_XER, "XER",
611 &spr_read_xer, &spr_write_xer,
612 &spr_read_xer, &spr_write_xer,
613 0x00000000);
614 /* Branch contol */
615 spr_register(env, SPR_LR, "LR",
616 &spr_read_lr, &spr_write_lr,
617 &spr_read_lr, &spr_write_lr,
618 0x00000000);
619 spr_register(env, SPR_CTR, "CTR",
620 &spr_read_ctr, &spr_write_ctr,
621 &spr_read_ctr, &spr_write_ctr,
622 0x00000000);
623 /* Interrupt processing */
624 spr_register(env, SPR_SRR0, "SRR0",
625 SPR_NOACCESS, SPR_NOACCESS,
626 &spr_read_generic, &spr_write_generic,
627 0x00000000);
628 spr_register(env, SPR_SRR1, "SRR1",
629 SPR_NOACCESS, SPR_NOACCESS,
630 &spr_read_generic, &spr_write_generic,
631 0x00000000);
632 /* Processor control */
633 spr_register(env, SPR_SPRG0, "SPRG0",
634 SPR_NOACCESS, SPR_NOACCESS,
635 &spr_read_generic, &spr_write_generic,
636 0x00000000);
637 spr_register(env, SPR_SPRG1, "SPRG1",
638 SPR_NOACCESS, SPR_NOACCESS,
639 &spr_read_generic, &spr_write_generic,
640 0x00000000);
641 spr_register(env, SPR_SPRG2, "SPRG2",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_generic, &spr_write_generic,
644 0x00000000);
645 spr_register(env, SPR_SPRG3, "SPRG3",
646 SPR_NOACCESS, SPR_NOACCESS,
647 &spr_read_generic, &spr_write_generic,
648 0x00000000);
649 }
650
651 /* SPR common to all non-embedded PowerPC, including 601 */
652 static void gen_spr_ne_601 (CPUPPCState *env)
653 {
654 /* Exception processing */
655 spr_register(env, SPR_DSISR, "DSISR",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, &spr_write_generic,
658 0x00000000);
659 spr_register(env, SPR_DAR, "DAR",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, &spr_write_generic,
662 0x00000000);
663 /* Timer */
664 spr_register(env, SPR_DECR, "DECR",
665 SPR_NOACCESS, SPR_NOACCESS,
666 &spr_read_decr, &spr_write_decr,
667 0x00000000);
668 /* Memory management */
669 spr_register(env, SPR_SDR1, "SDR1",
670 SPR_NOACCESS, SPR_NOACCESS,
671 &spr_read_generic, &spr_write_sdr1,
672 0x00000000);
673 }
674
675 /* BATs 0-3 */
676 static void gen_low_BATs (CPUPPCState *env)
677 {
678 #if !defined(CONFIG_USER_ONLY)
679 spr_register(env, SPR_IBAT0U, "IBAT0U",
680 SPR_NOACCESS, SPR_NOACCESS,
681 &spr_read_ibat, &spr_write_ibatu,
682 0x00000000);
683 spr_register(env, SPR_IBAT0L, "IBAT0L",
684 SPR_NOACCESS, SPR_NOACCESS,
685 &spr_read_ibat, &spr_write_ibatl,
686 0x00000000);
687 spr_register(env, SPR_IBAT1U, "IBAT1U",
688 SPR_NOACCESS, SPR_NOACCESS,
689 &spr_read_ibat, &spr_write_ibatu,
690 0x00000000);
691 spr_register(env, SPR_IBAT1L, "IBAT1L",
692 SPR_NOACCESS, SPR_NOACCESS,
693 &spr_read_ibat, &spr_write_ibatl,
694 0x00000000);
695 spr_register(env, SPR_IBAT2U, "IBAT2U",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_ibat, &spr_write_ibatu,
698 0x00000000);
699 spr_register(env, SPR_IBAT2L, "IBAT2L",
700 SPR_NOACCESS, SPR_NOACCESS,
701 &spr_read_ibat, &spr_write_ibatl,
702 0x00000000);
703 spr_register(env, SPR_IBAT3U, "IBAT3U",
704 SPR_NOACCESS, SPR_NOACCESS,
705 &spr_read_ibat, &spr_write_ibatu,
706 0x00000000);
707 spr_register(env, SPR_IBAT3L, "IBAT3L",
708 SPR_NOACCESS, SPR_NOACCESS,
709 &spr_read_ibat, &spr_write_ibatl,
710 0x00000000);
711 spr_register(env, SPR_DBAT0U, "DBAT0U",
712 SPR_NOACCESS, SPR_NOACCESS,
713 &spr_read_dbat, &spr_write_dbatu,
714 0x00000000);
715 spr_register(env, SPR_DBAT0L, "DBAT0L",
716 SPR_NOACCESS, SPR_NOACCESS,
717 &spr_read_dbat, &spr_write_dbatl,
718 0x00000000);
719 spr_register(env, SPR_DBAT1U, "DBAT1U",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_dbat, &spr_write_dbatu,
722 0x00000000);
723 spr_register(env, SPR_DBAT1L, "DBAT1L",
724 SPR_NOACCESS, SPR_NOACCESS,
725 &spr_read_dbat, &spr_write_dbatl,
726 0x00000000);
727 spr_register(env, SPR_DBAT2U, "DBAT2U",
728 SPR_NOACCESS, SPR_NOACCESS,
729 &spr_read_dbat, &spr_write_dbatu,
730 0x00000000);
731 spr_register(env, SPR_DBAT2L, "DBAT2L",
732 SPR_NOACCESS, SPR_NOACCESS,
733 &spr_read_dbat, &spr_write_dbatl,
734 0x00000000);
735 spr_register(env, SPR_DBAT3U, "DBAT3U",
736 SPR_NOACCESS, SPR_NOACCESS,
737 &spr_read_dbat, &spr_write_dbatu,
738 0x00000000);
739 spr_register(env, SPR_DBAT3L, "DBAT3L",
740 SPR_NOACCESS, SPR_NOACCESS,
741 &spr_read_dbat, &spr_write_dbatl,
742 0x00000000);
743 env->nb_BATs += 4;
744 #endif
745 }
746
747 /* BATs 4-7 */
748 static void gen_high_BATs (CPUPPCState *env)
749 {
750 #if !defined(CONFIG_USER_ONLY)
751 spr_register(env, SPR_IBAT4U, "IBAT4U",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_ibat_h, &spr_write_ibatu_h,
754 0x00000000);
755 spr_register(env, SPR_IBAT4L, "IBAT4L",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_ibat_h, &spr_write_ibatl_h,
758 0x00000000);
759 spr_register(env, SPR_IBAT5U, "IBAT5U",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_ibat_h, &spr_write_ibatu_h,
762 0x00000000);
763 spr_register(env, SPR_IBAT5L, "IBAT5L",
764 SPR_NOACCESS, SPR_NOACCESS,
765 &spr_read_ibat_h, &spr_write_ibatl_h,
766 0x00000000);
767 spr_register(env, SPR_IBAT6U, "IBAT6U",
768 SPR_NOACCESS, SPR_NOACCESS,
769 &spr_read_ibat_h, &spr_write_ibatu_h,
770 0x00000000);
771 spr_register(env, SPR_IBAT6L, "IBAT6L",
772 SPR_NOACCESS, SPR_NOACCESS,
773 &spr_read_ibat_h, &spr_write_ibatl_h,
774 0x00000000);
775 spr_register(env, SPR_IBAT7U, "IBAT7U",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_ibat_h, &spr_write_ibatu_h,
778 0x00000000);
779 spr_register(env, SPR_IBAT7L, "IBAT7L",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_ibat_h, &spr_write_ibatl_h,
782 0x00000000);
783 spr_register(env, SPR_DBAT4U, "DBAT4U",
784 SPR_NOACCESS, SPR_NOACCESS,
785 &spr_read_dbat_h, &spr_write_dbatu_h,
786 0x00000000);
787 spr_register(env, SPR_DBAT4L, "DBAT4L",
788 SPR_NOACCESS, SPR_NOACCESS,
789 &spr_read_dbat_h, &spr_write_dbatl_h,
790 0x00000000);
791 spr_register(env, SPR_DBAT5U, "DBAT5U",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_dbat_h, &spr_write_dbatu_h,
794 0x00000000);
795 spr_register(env, SPR_DBAT5L, "DBAT5L",
796 SPR_NOACCESS, SPR_NOACCESS,
797 &spr_read_dbat_h, &spr_write_dbatl_h,
798 0x00000000);
799 spr_register(env, SPR_DBAT6U, "DBAT6U",
800 SPR_NOACCESS, SPR_NOACCESS,
801 &spr_read_dbat_h, &spr_write_dbatu_h,
802 0x00000000);
803 spr_register(env, SPR_DBAT6L, "DBAT6L",
804 SPR_NOACCESS, SPR_NOACCESS,
805 &spr_read_dbat_h, &spr_write_dbatl_h,
806 0x00000000);
807 spr_register(env, SPR_DBAT7U, "DBAT7U",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_dbat_h, &spr_write_dbatu_h,
810 0x00000000);
811 spr_register(env, SPR_DBAT7L, "DBAT7L",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_dbat_h, &spr_write_dbatl_h,
814 0x00000000);
815 env->nb_BATs += 4;
816 #endif
817 }
818
819 /* Generic PowerPC time base */
820 static void gen_tbl (CPUPPCState *env)
821 {
822 spr_register(env, SPR_VTBL, "TBL",
823 &spr_read_tbl, SPR_NOACCESS,
824 &spr_read_tbl, SPR_NOACCESS,
825 0x00000000);
826 spr_register(env, SPR_TBL, "TBL",
827 &spr_read_tbl, SPR_NOACCESS,
828 &spr_read_tbl, &spr_write_tbl,
829 0x00000000);
830 spr_register(env, SPR_VTBU, "TBU",
831 &spr_read_tbu, SPR_NOACCESS,
832 &spr_read_tbu, SPR_NOACCESS,
833 0x00000000);
834 spr_register(env, SPR_TBU, "TBU",
835 &spr_read_tbu, SPR_NOACCESS,
836 &spr_read_tbu, &spr_write_tbu,
837 0x00000000);
838 }
839
840 /* Softare table search registers */
841 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
842 {
843 #if !defined(CONFIG_USER_ONLY)
844 env->nb_tlb = nb_tlbs;
845 env->nb_ways = nb_ways;
846 env->id_tlbs = 1;
847 env->tlb_type = TLB_6XX;
848 spr_register(env, SPR_DMISS, "DMISS",
849 SPR_NOACCESS, SPR_NOACCESS,
850 &spr_read_generic, SPR_NOACCESS,
851 0x00000000);
852 spr_register(env, SPR_DCMP, "DCMP",
853 SPR_NOACCESS, SPR_NOACCESS,
854 &spr_read_generic, SPR_NOACCESS,
855 0x00000000);
856 spr_register(env, SPR_HASH1, "HASH1",
857 SPR_NOACCESS, SPR_NOACCESS,
858 &spr_read_generic, SPR_NOACCESS,
859 0x00000000);
860 spr_register(env, SPR_HASH2, "HASH2",
861 SPR_NOACCESS, SPR_NOACCESS,
862 &spr_read_generic, SPR_NOACCESS,
863 0x00000000);
864 spr_register(env, SPR_IMISS, "IMISS",
865 SPR_NOACCESS, SPR_NOACCESS,
866 &spr_read_generic, SPR_NOACCESS,
867 0x00000000);
868 spr_register(env, SPR_ICMP, "ICMP",
869 SPR_NOACCESS, SPR_NOACCESS,
870 &spr_read_generic, SPR_NOACCESS,
871 0x00000000);
872 spr_register(env, SPR_RPA, "RPA",
873 SPR_NOACCESS, SPR_NOACCESS,
874 &spr_read_generic, &spr_write_generic,
875 0x00000000);
876 #endif
877 }
878
879 /* SPR common to MPC755 and G2 */
880 static void gen_spr_G2_755 (CPUPPCState *env)
881 {
882 /* SGPRs */
883 spr_register(env, SPR_SPRG4, "SPRG4",
884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_generic, &spr_write_generic,
886 0x00000000);
887 spr_register(env, SPR_SPRG5, "SPRG5",
888 SPR_NOACCESS, SPR_NOACCESS,
889 &spr_read_generic, &spr_write_generic,
890 0x00000000);
891 spr_register(env, SPR_SPRG6, "SPRG6",
892 SPR_NOACCESS, SPR_NOACCESS,
893 &spr_read_generic, &spr_write_generic,
894 0x00000000);
895 spr_register(env, SPR_SPRG7, "SPRG7",
896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_generic, &spr_write_generic,
898 0x00000000);
899 }
900
901 /* SPR common to all 7xx PowerPC implementations */
902 static void gen_spr_7xx (CPUPPCState *env)
903 {
904 /* Breakpoints */
905 /* XXX : not implemented */
906 spr_register(env, SPR_DABR, "DABR",
907 SPR_NOACCESS, SPR_NOACCESS,
908 &spr_read_generic, &spr_write_generic,
909 0x00000000);
910 /* XXX : not implemented */
911 spr_register(env, SPR_IABR, "IABR",
912 SPR_NOACCESS, SPR_NOACCESS,
913 &spr_read_generic, &spr_write_generic,
914 0x00000000);
915 /* Cache management */
916 /* XXX : not implemented */
917 spr_register(env, SPR_ICTC, "ICTC",
918 SPR_NOACCESS, SPR_NOACCESS,
919 &spr_read_generic, &spr_write_generic,
920 0x00000000);
921 /* Performance monitors */
922 /* XXX : not implemented */
923 spr_register(env, SPR_MMCR0, "MMCR0",
924 SPR_NOACCESS, SPR_NOACCESS,
925 &spr_read_generic, &spr_write_generic,
926 0x00000000);
927 /* XXX : not implemented */
928 spr_register(env, SPR_MMCR1, "MMCR1",
929 SPR_NOACCESS, SPR_NOACCESS,
930 &spr_read_generic, &spr_write_generic,
931 0x00000000);
932 /* XXX : not implemented */
933 spr_register(env, SPR_PMC1, "PMC1",
934 SPR_NOACCESS, SPR_NOACCESS,
935 &spr_read_generic, &spr_write_generic,
936 0x00000000);
937 /* XXX : not implemented */
938 spr_register(env, SPR_PMC2, "PMC2",
939 SPR_NOACCESS, SPR_NOACCESS,
940 &spr_read_generic, &spr_write_generic,
941 0x00000000);
942 /* XXX : not implemented */
943 spr_register(env, SPR_PMC3, "PMC3",
944 SPR_NOACCESS, SPR_NOACCESS,
945 &spr_read_generic, &spr_write_generic,
946 0x00000000);
947 /* XXX : not implemented */
948 spr_register(env, SPR_PMC4, "PMC4",
949 SPR_NOACCESS, SPR_NOACCESS,
950 &spr_read_generic, &spr_write_generic,
951 0x00000000);
952 /* XXX : not implemented */
953 spr_register(env, SPR_SIAR, "SIAR",
954 SPR_NOACCESS, SPR_NOACCESS,
955 &spr_read_generic, SPR_NOACCESS,
956 0x00000000);
957 /* XXX : not implemented */
958 spr_register(env, SPR_UMMCR0, "UMMCR0",
959 &spr_read_ureg, SPR_NOACCESS,
960 &spr_read_ureg, SPR_NOACCESS,
961 0x00000000);
962 /* XXX : not implemented */
963 spr_register(env, SPR_UMMCR1, "UMMCR1",
964 &spr_read_ureg, SPR_NOACCESS,
965 &spr_read_ureg, SPR_NOACCESS,
966 0x00000000);
967 /* XXX : not implemented */
968 spr_register(env, SPR_UPMC1, "UPMC1",
969 &spr_read_ureg, SPR_NOACCESS,
970 &spr_read_ureg, SPR_NOACCESS,
971 0x00000000);
972 /* XXX : not implemented */
973 spr_register(env, SPR_UPMC2, "UPMC2",
974 &spr_read_ureg, SPR_NOACCESS,
975 &spr_read_ureg, SPR_NOACCESS,
976 0x00000000);
977 /* XXX : not implemented */
978 spr_register(env, SPR_UPMC3, "UPMC3",
979 &spr_read_ureg, SPR_NOACCESS,
980 &spr_read_ureg, SPR_NOACCESS,
981 0x00000000);
982 /* XXX : not implemented */
983 spr_register(env, SPR_UPMC4, "UPMC4",
984 &spr_read_ureg, SPR_NOACCESS,
985 &spr_read_ureg, SPR_NOACCESS,
986 0x00000000);
987 /* XXX : not implemented */
988 spr_register(env, SPR_USIAR, "USIAR",
989 &spr_read_ureg, SPR_NOACCESS,
990 &spr_read_ureg, SPR_NOACCESS,
991 0x00000000);
992 /* External access control */
993 /* XXX : not implemented */
994 spr_register(env, SPR_EAR, "EAR",
995 SPR_NOACCESS, SPR_NOACCESS,
996 &spr_read_generic, &spr_write_generic,
997 0x00000000);
998 }
999
1000 static void gen_spr_thrm (CPUPPCState *env)
1001 {
1002 /* Thermal management */
1003 /* XXX : not implemented */
1004 spr_register(env, SPR_THRM1, "THRM1",
1005 SPR_NOACCESS, SPR_NOACCESS,
1006 &spr_read_generic, &spr_write_generic,
1007 0x00000000);
1008 /* XXX : not implemented */
1009 spr_register(env, SPR_THRM2, "THRM2",
1010 SPR_NOACCESS, SPR_NOACCESS,
1011 &spr_read_generic, &spr_write_generic,
1012 0x00000000);
1013 /* XXX : not implemented */
1014 spr_register(env, SPR_THRM3, "THRM3",
1015 SPR_NOACCESS, SPR_NOACCESS,
1016 &spr_read_generic, &spr_write_generic,
1017 0x00000000);
1018 }
1019
1020 /* SPR specific to PowerPC 604 implementation */
1021 static void gen_spr_604 (CPUPPCState *env)
1022 {
1023 /* Processor identification */
1024 spr_register(env, SPR_PIR, "PIR",
1025 SPR_NOACCESS, SPR_NOACCESS,
1026 &spr_read_generic, &spr_write_pir,
1027 0x00000000);
1028 /* Breakpoints */
1029 /* XXX : not implemented */
1030 spr_register(env, SPR_IABR, "IABR",
1031 SPR_NOACCESS, SPR_NOACCESS,
1032 &spr_read_generic, &spr_write_generic,
1033 0x00000000);
1034 /* XXX : not implemented */
1035 spr_register(env, SPR_DABR, "DABR",
1036 SPR_NOACCESS, SPR_NOACCESS,
1037 &spr_read_generic, &spr_write_generic,
1038 0x00000000);
1039 /* Performance counters */
1040 /* XXX : not implemented */
1041 spr_register(env, SPR_MMCR0, "MMCR0",
1042 SPR_NOACCESS, SPR_NOACCESS,
1043 &spr_read_generic, &spr_write_generic,
1044 0x00000000);
1045 /* XXX : not implemented */
1046 spr_register(env, SPR_PMC1, "PMC1",
1047 SPR_NOACCESS, SPR_NOACCESS,
1048 &spr_read_generic, &spr_write_generic,
1049 0x00000000);
1050 /* XXX : not implemented */
1051 spr_register(env, SPR_PMC2, "PMC2",
1052 SPR_NOACCESS, SPR_NOACCESS,
1053 &spr_read_generic, &spr_write_generic,
1054 0x00000000);
1055 /* XXX : not implemented */
1056 spr_register(env, SPR_SIAR, "SIAR",
1057 SPR_NOACCESS, SPR_NOACCESS,
1058 &spr_read_generic, SPR_NOACCESS,
1059 0x00000000);
1060 /* XXX : not implemented */
1061 spr_register(env, SPR_SDA, "SDA",
1062 SPR_NOACCESS, SPR_NOACCESS,
1063 &spr_read_generic, SPR_NOACCESS,
1064 0x00000000);
1065 /* External access control */
1066 /* XXX : not implemented */
1067 spr_register(env, SPR_EAR, "EAR",
1068 SPR_NOACCESS, SPR_NOACCESS,
1069 &spr_read_generic, &spr_write_generic,
1070 0x00000000);
1071 }
1072
1073 /* SPR specific to PowerPC 603 implementation */
1074 static void gen_spr_603 (CPUPPCState *env)
1075 {
1076 /* External access control */
1077 /* XXX : not implemented */
1078 spr_register(env, SPR_EAR, "EAR",
1079 SPR_NOACCESS, SPR_NOACCESS,
1080 &spr_read_generic, &spr_write_generic,
1081 0x00000000);
1082 }
1083
1084 /* SPR specific to PowerPC G2 implementation */
1085 static void gen_spr_G2 (CPUPPCState *env)
1086 {
1087 /* Memory base address */
1088 /* MBAR */
1089 /* XXX : not implemented */
1090 spr_register(env, SPR_MBAR, "MBAR",
1091 SPR_NOACCESS, SPR_NOACCESS,
1092 &spr_read_generic, &spr_write_generic,
1093 0x00000000);
1094 /* Exception processing */
1095 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1096 SPR_NOACCESS, SPR_NOACCESS,
1097 &spr_read_generic, &spr_write_generic,
1098 0x00000000);
1099 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1100 SPR_NOACCESS, SPR_NOACCESS,
1101 &spr_read_generic, &spr_write_generic,
1102 0x00000000);
1103 /* Breakpoints */
1104 /* XXX : not implemented */
1105 spr_register(env, SPR_DABR, "DABR",
1106 SPR_NOACCESS, SPR_NOACCESS,
1107 &spr_read_generic, &spr_write_generic,
1108 0x00000000);
1109 /* XXX : not implemented */
1110 spr_register(env, SPR_DABR2, "DABR2",
1111 SPR_NOACCESS, SPR_NOACCESS,
1112 &spr_read_generic, &spr_write_generic,
1113 0x00000000);
1114 /* XXX : not implemented */
1115 spr_register(env, SPR_IABR, "IABR",
1116 SPR_NOACCESS, SPR_NOACCESS,
1117 &spr_read_generic, &spr_write_generic,
1118 0x00000000);
1119 /* XXX : not implemented */
1120 spr_register(env, SPR_IABR2, "IABR2",
1121 SPR_NOACCESS, SPR_NOACCESS,
1122 &spr_read_generic, &spr_write_generic,
1123 0x00000000);
1124 /* XXX : not implemented */
1125 spr_register(env, SPR_IBCR, "IBCR",
1126 SPR_NOACCESS, SPR_NOACCESS,
1127 &spr_read_generic, &spr_write_generic,
1128 0x00000000);
1129 /* XXX : not implemented */
1130 spr_register(env, SPR_DBCR, "DBCR",
1131 SPR_NOACCESS, SPR_NOACCESS,
1132 &spr_read_generic, &spr_write_generic,
1133 0x00000000);
1134 }
1135
1136 /* SPR specific to PowerPC 602 implementation */
1137 static void gen_spr_602 (CPUPPCState *env)
1138 {
1139 /* ESA registers */
1140 /* XXX : not implemented */
1141 spr_register(env, SPR_SER, "SER",
1142 SPR_NOACCESS, SPR_NOACCESS,
1143 &spr_read_generic, &spr_write_generic,
1144 0x00000000);
1145 /* XXX : not implemented */
1146 spr_register(env, SPR_SEBR, "SEBR",
1147 SPR_NOACCESS, SPR_NOACCESS,
1148 &spr_read_generic, &spr_write_generic,
1149 0x00000000);
1150 /* XXX : not implemented */
1151 spr_register(env, SPR_ESASRR, "ESASRR",
1152 SPR_NOACCESS, SPR_NOACCESS,
1153 &spr_read_generic, &spr_write_generic,
1154 0x00000000);
1155 /* Floating point status */
1156 /* XXX : not implemented */
1157 spr_register(env, SPR_SP, "SP",
1158 SPR_NOACCESS, SPR_NOACCESS,
1159 &spr_read_generic, &spr_write_generic,
1160 0x00000000);
1161 /* XXX : not implemented */
1162 spr_register(env, SPR_LT, "LT",
1163 SPR_NOACCESS, SPR_NOACCESS,
1164 &spr_read_generic, &spr_write_generic,
1165 0x00000000);
1166 /* Watchdog timer */
1167 /* XXX : not implemented */
1168 spr_register(env, SPR_TCR, "TCR",
1169 SPR_NOACCESS, SPR_NOACCESS,
1170 &spr_read_generic, &spr_write_generic,
1171 0x00000000);
1172 /* Interrupt base */
1173 spr_register(env, SPR_IBR, "IBR",
1174 SPR_NOACCESS, SPR_NOACCESS,
1175 &spr_read_generic, &spr_write_generic,
1176 0x00000000);
1177 /* XXX : not implemented */
1178 spr_register(env, SPR_IABR, "IABR",
1179 SPR_NOACCESS, SPR_NOACCESS,
1180 &spr_read_generic, &spr_write_generic,
1181 0x00000000);
1182 }
1183
1184 /* SPR specific to PowerPC 601 implementation */
1185 static void gen_spr_601 (CPUPPCState *env)
1186 {
1187 /* Multiplication/division register */
1188 /* MQ */
1189 spr_register(env, SPR_MQ, "MQ",
1190 &spr_read_generic, &spr_write_generic,
1191 &spr_read_generic, &spr_write_generic,
1192 0x00000000);
1193 /* RTC registers */
1194 spr_register(env, SPR_601_RTCU, "RTCU",
1195 SPR_NOACCESS, SPR_NOACCESS,
1196 SPR_NOACCESS, &spr_write_601_rtcu,
1197 0x00000000);
1198 spr_register(env, SPR_601_VRTCU, "RTCU",
1199 &spr_read_601_rtcu, SPR_NOACCESS,
1200 &spr_read_601_rtcu, SPR_NOACCESS,
1201 0x00000000);
1202 spr_register(env, SPR_601_RTCL, "RTCL",
1203 SPR_NOACCESS, SPR_NOACCESS,
1204 SPR_NOACCESS, &spr_write_601_rtcl,
1205 0x00000000);
1206 spr_register(env, SPR_601_VRTCL, "RTCL",
1207 &spr_read_601_rtcl, SPR_NOACCESS,
1208 &spr_read_601_rtcl, SPR_NOACCESS,
1209 0x00000000);
1210 /* Timer */
1211 #if 0 /* ? */
1212 spr_register(env, SPR_601_UDECR, "UDECR",
1213 &spr_read_decr, SPR_NOACCESS,
1214 &spr_read_decr, SPR_NOACCESS,
1215 0x00000000);
1216 #endif
1217 /* External access control */
1218 /* XXX : not implemented */
1219 spr_register(env, SPR_EAR, "EAR",
1220 SPR_NOACCESS, SPR_NOACCESS,
1221 &spr_read_generic, &spr_write_generic,
1222 0x00000000);
1223 /* Memory management */
1224 #if !defined(CONFIG_USER_ONLY)
1225 spr_register(env, SPR_IBAT0U, "IBAT0U",
1226 SPR_NOACCESS, SPR_NOACCESS,
1227 &spr_read_601_ubat, &spr_write_601_ubatu,
1228 0x00000000);
1229 spr_register(env, SPR_IBAT0L, "IBAT0L",
1230 SPR_NOACCESS, SPR_NOACCESS,
1231 &spr_read_601_ubat, &spr_write_601_ubatl,
1232 0x00000000);
1233 spr_register(env, SPR_IBAT1U, "IBAT1U",
1234 SPR_NOACCESS, SPR_NOACCESS,
1235 &spr_read_601_ubat, &spr_write_601_ubatu,
1236 0x00000000);
1237 spr_register(env, SPR_IBAT1L, "IBAT1L",
1238 SPR_NOACCESS, SPR_NOACCESS,
1239 &spr_read_601_ubat, &spr_write_601_ubatl,
1240 0x00000000);
1241 spr_register(env, SPR_IBAT2U, "IBAT2U",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_601_ubat, &spr_write_601_ubatu,
1244 0x00000000);
1245 spr_register(env, SPR_IBAT2L, "IBAT2L",
1246 SPR_NOACCESS, SPR_NOACCESS,
1247 &spr_read_601_ubat, &spr_write_601_ubatl,
1248 0x00000000);
1249 spr_register(env, SPR_IBAT3U, "IBAT3U",
1250 SPR_NOACCESS, SPR_NOACCESS,
1251 &spr_read_601_ubat, &spr_write_601_ubatu,
1252 0x00000000);
1253 spr_register(env, SPR_IBAT3L, "IBAT3L",
1254 SPR_NOACCESS, SPR_NOACCESS,
1255 &spr_read_601_ubat, &spr_write_601_ubatl,
1256 0x00000000);
1257 env->nb_BATs = 4;
1258 #endif
1259 }
1260
1261 static void gen_spr_74xx (CPUPPCState *env)
1262 {
1263 /* Processor identification */
1264 spr_register(env, SPR_PIR, "PIR",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_pir,
1267 0x00000000);
1268 /* XXX : not implemented */
1269 spr_register(env, SPR_MMCR2, "MMCR2",
1270 SPR_NOACCESS, SPR_NOACCESS,
1271 &spr_read_generic, &spr_write_generic,
1272 0x00000000);
1273 /* XXX : not implemented */
1274 spr_register(env, SPR_UMMCR2, "UMMCR2",
1275 &spr_read_ureg, SPR_NOACCESS,
1276 &spr_read_ureg, SPR_NOACCESS,
1277 0x00000000);
1278 /* XXX: not implemented */
1279 spr_register(env, SPR_BAMR, "BAMR",
1280 SPR_NOACCESS, SPR_NOACCESS,
1281 &spr_read_generic, &spr_write_generic,
1282 0x00000000);
1283 /* XXX : not implemented */
1284 spr_register(env, SPR_MSSCR0, "MSSCR0",
1285 SPR_NOACCESS, SPR_NOACCESS,
1286 &spr_read_generic, &spr_write_generic,
1287 0x00000000);
1288 /* Hardware implementation registers */
1289 /* XXX : not implemented */
1290 spr_register(env, SPR_HID0, "HID0",
1291 SPR_NOACCESS, SPR_NOACCESS,
1292 &spr_read_generic, &spr_write_generic,
1293 0x00000000);
1294 /* XXX : not implemented */
1295 spr_register(env, SPR_HID1, "HID1",
1296 SPR_NOACCESS, SPR_NOACCESS,
1297 &spr_read_generic, &spr_write_generic,
1298 0x00000000);
1299 /* Altivec */
1300 spr_register(env, SPR_VRSAVE, "VRSAVE",
1301 &spr_read_generic, &spr_write_generic,
1302 &spr_read_generic, &spr_write_generic,
1303 0x00000000);
1304 /* XXX : not implemented */
1305 spr_register(env, SPR_L2CR, "L2CR",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, &spr_write_generic,
1308 0x00000000);
1309 /* Not strictly an SPR */
1310 vscr_init(env, 0x00010000);
1311 }
1312
1313 static void gen_l3_ctrl (CPUPPCState *env)
1314 {
1315 /* L3CR */
1316 /* XXX : not implemented */
1317 spr_register(env, SPR_L3CR, "L3CR",
1318 SPR_NOACCESS, SPR_NOACCESS,
1319 &spr_read_generic, &spr_write_generic,
1320 0x00000000);
1321 /* L3ITCR0 */
1322 /* XXX : not implemented */
1323 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1324 SPR_NOACCESS, SPR_NOACCESS,
1325 &spr_read_generic, &spr_write_generic,
1326 0x00000000);
1327 /* L3PM */
1328 /* XXX : not implemented */
1329 spr_register(env, SPR_L3PM, "L3PM",
1330 SPR_NOACCESS, SPR_NOACCESS,
1331 &spr_read_generic, &spr_write_generic,
1332 0x00000000);
1333 }
1334
1335 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1336 {
1337 #if !defined(CONFIG_USER_ONLY)
1338 env->nb_tlb = nb_tlbs;
1339 env->nb_ways = nb_ways;
1340 env->id_tlbs = 1;
1341 env->tlb_type = TLB_6XX;
1342 /* XXX : not implemented */
1343 spr_register(env, SPR_PTEHI, "PTEHI",
1344 SPR_NOACCESS, SPR_NOACCESS,
1345 &spr_read_generic, &spr_write_generic,
1346 0x00000000);
1347 /* XXX : not implemented */
1348 spr_register(env, SPR_PTELO, "PTELO",
1349 SPR_NOACCESS, SPR_NOACCESS,
1350 &spr_read_generic, &spr_write_generic,
1351 0x00000000);
1352 /* XXX : not implemented */
1353 spr_register(env, SPR_TLBMISS, "TLBMISS",
1354 SPR_NOACCESS, SPR_NOACCESS,
1355 &spr_read_generic, &spr_write_generic,
1356 0x00000000);
1357 #endif
1358 }
1359
1360 #if !defined(CONFIG_USER_ONLY)
1361 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1362 {
1363 TCGv t0 = tcg_temp_new();
1364
1365 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1366 gen_store_spr(sprn, t0);
1367 tcg_temp_free(t0);
1368 }
1369
1370 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1371 {
1372 TCGv_i32 t0 = tcg_const_i32(sprn);
1373 gen_helper_booke206_tlbflush(t0);
1374 tcg_temp_free_i32(t0);
1375 }
1376
1377 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1378 {
1379 TCGv_i32 t0 = tcg_const_i32(sprn);
1380 gen_helper_booke_setpid(t0, cpu_gpr[gprn]);
1381 tcg_temp_free_i32(t0);
1382 }
1383 #endif
1384
1385 static void gen_spr_usprgh (CPUPPCState *env)
1386 {
1387 spr_register(env, SPR_USPRG4, "USPRG4",
1388 &spr_read_ureg, SPR_NOACCESS,
1389 &spr_read_ureg, SPR_NOACCESS,
1390 0x00000000);
1391 spr_register(env, SPR_USPRG5, "USPRG5",
1392 &spr_read_ureg, SPR_NOACCESS,
1393 &spr_read_ureg, SPR_NOACCESS,
1394 0x00000000);
1395 spr_register(env, SPR_USPRG6, "USPRG6",
1396 &spr_read_ureg, SPR_NOACCESS,
1397 &spr_read_ureg, SPR_NOACCESS,
1398 0x00000000);
1399 spr_register(env, SPR_USPRG7, "USPRG7",
1400 &spr_read_ureg, SPR_NOACCESS,
1401 &spr_read_ureg, SPR_NOACCESS,
1402 0x00000000);
1403 }
1404
1405 /* PowerPC BookE SPR */
1406 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1407 {
1408 const char *ivor_names[64] = {
1409 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1410 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1411 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1412 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1413 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1414 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1415 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1416 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1417 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1418 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1419 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1420 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1421 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1422 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1423 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1424 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1425 };
1426 #define SPR_BOOKE_IVORxx (-1)
1427 int ivor_sprn[64] = {
1428 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1429 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1430 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1431 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1432 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1433 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1434 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1435 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1436 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1437 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1438 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1439 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1440 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1441 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1442 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1443 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1444 };
1445 int i;
1446
1447 /* Interrupt processing */
1448 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1449 SPR_NOACCESS, SPR_NOACCESS,
1450 &spr_read_generic, &spr_write_generic,
1451 0x00000000);
1452 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1453 SPR_NOACCESS, SPR_NOACCESS,
1454 &spr_read_generic, &spr_write_generic,
1455 0x00000000);
1456 /* Debug */
1457 /* XXX : not implemented */
1458 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1459 SPR_NOACCESS, SPR_NOACCESS,
1460 &spr_read_generic, &spr_write_generic,
1461 0x00000000);
1462 /* XXX : not implemented */
1463 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1464 SPR_NOACCESS, SPR_NOACCESS,
1465 &spr_read_generic, &spr_write_generic,
1466 0x00000000);
1467 /* XXX : not implemented */
1468 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1469 SPR_NOACCESS, SPR_NOACCESS,
1470 &spr_read_generic, &spr_write_generic,
1471 0x00000000);
1472 /* XXX : not implemented */
1473 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1474 SPR_NOACCESS, SPR_NOACCESS,
1475 &spr_read_generic, &spr_write_generic,
1476 0x00000000);
1477 /* XXX : not implemented */
1478 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1479 SPR_NOACCESS, SPR_NOACCESS,
1480 &spr_read_generic, &spr_write_generic,
1481 0x00000000);
1482 /* XXX : not implemented */
1483 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1484 SPR_NOACCESS, SPR_NOACCESS,
1485 &spr_read_generic, &spr_write_generic,
1486 0x00000000);
1487 /* XXX : not implemented */
1488 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1489 SPR_NOACCESS, SPR_NOACCESS,
1490 &spr_read_generic, &spr_write_generic,
1491 0x00000000);
1492 /* XXX : not implemented */
1493 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1494 SPR_NOACCESS, SPR_NOACCESS,
1495 &spr_read_generic, &spr_write_clear,
1496 0x00000000);
1497 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1498 SPR_NOACCESS, SPR_NOACCESS,
1499 &spr_read_generic, &spr_write_generic,
1500 0x00000000);
1501 spr_register(env, SPR_BOOKE_ESR, "ESR",
1502 SPR_NOACCESS, SPR_NOACCESS,
1503 &spr_read_generic, &spr_write_generic,
1504 0x00000000);
1505 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1506 SPR_NOACCESS, SPR_NOACCESS,
1507 &spr_read_generic, &spr_write_excp_prefix,
1508 0x00000000);
1509 /* Exception vectors */
1510 for (i = 0; i < 64; i++) {
1511 if (ivor_mask & (1ULL << i)) {
1512 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1513 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1514 exit(1);
1515 }
1516 spr_register(env, ivor_sprn[i], ivor_names[i],
1517 SPR_NOACCESS, SPR_NOACCESS,
1518 &spr_read_generic, &spr_write_excp_vector,
1519 0x00000000);
1520 }
1521 }
1522 spr_register(env, SPR_BOOKE_PID, "PID",
1523 SPR_NOACCESS, SPR_NOACCESS,
1524 &spr_read_generic, &spr_write_booke_pid,
1525 0x00000000);
1526 spr_register(env, SPR_BOOKE_TCR, "TCR",
1527 SPR_NOACCESS, SPR_NOACCESS,
1528 &spr_read_generic, &spr_write_booke_tcr,
1529 0x00000000);
1530 spr_register(env, SPR_BOOKE_TSR, "TSR",
1531 SPR_NOACCESS, SPR_NOACCESS,
1532 &spr_read_generic, &spr_write_booke_tsr,
1533 0x00000000);
1534 /* Timer */
1535 spr_register(env, SPR_DECR, "DECR",
1536 SPR_NOACCESS, SPR_NOACCESS,
1537 &spr_read_decr, &spr_write_decr,
1538 0x00000000);
1539 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1540 SPR_NOACCESS, SPR_NOACCESS,
1541 SPR_NOACCESS, &spr_write_generic,
1542 0x00000000);
1543 /* SPRGs */
1544 spr_register(env, SPR_USPRG0, "USPRG0",
1545 &spr_read_generic, &spr_write_generic,
1546 &spr_read_generic, &spr_write_generic,
1547 0x00000000);
1548 spr_register(env, SPR_SPRG4, "SPRG4",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_generic,
1551 0x00000000);
1552 spr_register(env, SPR_SPRG5, "SPRG5",
1553 SPR_NOACCESS, SPR_NOACCESS,
1554 &spr_read_generic, &spr_write_generic,
1555 0x00000000);
1556 spr_register(env, SPR_SPRG6, "SPRG6",
1557 SPR_NOACCESS, SPR_NOACCESS,
1558 &spr_read_generic, &spr_write_generic,
1559 0x00000000);
1560 spr_register(env, SPR_SPRG7, "SPRG7",
1561 SPR_NOACCESS, SPR_NOACCESS,
1562 &spr_read_generic, &spr_write_generic,
1563 0x00000000);
1564 }
1565
1566 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1567 uint32_t maxsize, uint32_t flags,
1568 uint32_t nentries)
1569 {
1570 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1571 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1572 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1573 flags | nentries;
1574 }
1575
1576 /* BookE 2.06 storage control registers */
1577 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1578 uint32_t *tlbncfg)
1579 {
1580 #if !defined(CONFIG_USER_ONLY)
1581 const char *mas_names[8] = {
1582 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1583 };
1584 int mas_sprn[8] = {
1585 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1586 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1587 };
1588 int i;
1589
1590 /* TLB assist registers */
1591 /* XXX : not implemented */
1592 for (i = 0; i < 8; i++) {
1593 if (mas_mask & (1 << i)) {
1594 spr_register(env, mas_sprn[i], mas_names[i],
1595 SPR_NOACCESS, SPR_NOACCESS,
1596 &spr_read_generic, &spr_write_generic,
1597 0x00000000);
1598 }
1599 }
1600 if (env->nb_pids > 1) {
1601 /* XXX : not implemented */
1602 spr_register(env, SPR_BOOKE_PID1, "PID1",
1603 SPR_NOACCESS, SPR_NOACCESS,
1604 &spr_read_generic, &spr_write_booke_pid,
1605 0x00000000);
1606 }
1607 if (env->nb_pids > 2) {
1608 /* XXX : not implemented */
1609 spr_register(env, SPR_BOOKE_PID2, "PID2",
1610 SPR_NOACCESS, SPR_NOACCESS,
1611 &spr_read_generic, &spr_write_booke_pid,
1612 0x00000000);
1613 }
1614 /* XXX : not implemented */
1615 spr_register(env, SPR_MMUCFG, "MMUCFG",
1616 SPR_NOACCESS, SPR_NOACCESS,
1617 &spr_read_generic, SPR_NOACCESS,
1618 0x00000000); /* TOFIX */
1619 switch (env->nb_ways) {
1620 case 4:
1621 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1622 SPR_NOACCESS, SPR_NOACCESS,
1623 &spr_read_generic, SPR_NOACCESS,
1624 tlbncfg[3]);
1625 /* Fallthru */
1626 case 3:
1627 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1628 SPR_NOACCESS, SPR_NOACCESS,
1629 &spr_read_generic, SPR_NOACCESS,
1630 tlbncfg[2]);
1631 /* Fallthru */
1632 case 2:
1633 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1634 SPR_NOACCESS, SPR_NOACCESS,
1635 &spr_read_generic, SPR_NOACCESS,
1636 tlbncfg[1]);
1637 /* Fallthru */
1638 case 1:
1639 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1640 SPR_NOACCESS, SPR_NOACCESS,
1641 &spr_read_generic, SPR_NOACCESS,
1642 tlbncfg[0]);
1643 /* Fallthru */
1644 case 0:
1645 default:
1646 break;
1647 }
1648 #endif
1649
1650 gen_spr_usprgh(env);
1651 }
1652
1653 /* SPR specific to PowerPC 440 implementation */
1654 static void gen_spr_440 (CPUPPCState *env)
1655 {
1656 /* Cache control */
1657 /* XXX : not implemented */
1658 spr_register(env, SPR_440_DNV0, "DNV0",
1659 SPR_NOACCESS, SPR_NOACCESS,
1660 &spr_read_generic, &spr_write_generic,
1661 0x00000000);
1662 /* XXX : not implemented */
1663 spr_register(env, SPR_440_DNV1, "DNV1",
1664 SPR_NOACCESS, SPR_NOACCESS,
1665 &spr_read_generic, &spr_write_generic,
1666 0x00000000);
1667 /* XXX : not implemented */
1668 spr_register(env, SPR_440_DNV2, "DNV2",
1669 SPR_NOACCESS, SPR_NOACCESS,
1670 &spr_read_generic, &spr_write_generic,
1671 0x00000000);
1672 /* XXX : not implemented */
1673 spr_register(env, SPR_440_DNV3, "DNV3",
1674 SPR_NOACCESS, SPR_NOACCESS,
1675 &spr_read_generic, &spr_write_generic,
1676 0x00000000);
1677 /* XXX : not implemented */
1678 spr_register(env, SPR_440_DTV0, "DTV0",
1679 SPR_NOACCESS, SPR_NOACCESS,
1680 &spr_read_generic, &spr_write_generic,
1681 0x00000000);
1682 /* XXX : not implemented */
1683 spr_register(env, SPR_440_DTV1, "DTV1",
1684 SPR_NOACCESS, SPR_NOACCESS,
1685 &spr_read_generic, &spr_write_generic,
1686 0x00000000);
1687 /* XXX : not implemented */
1688 spr_register(env, SPR_440_DTV2, "DTV2",
1689 SPR_NOACCESS, SPR_NOACCESS,
1690 &spr_read_generic, &spr_write_generic,
1691 0x00000000);
1692 /* XXX : not implemented */
1693 spr_register(env, SPR_440_DTV3, "DTV3",
1694 SPR_NOACCESS, SPR_NOACCESS,
1695 &spr_read_generic, &spr_write_generic,
1696 0x00000000);
1697 /* XXX : not implemented */
1698 spr_register(env, SPR_440_DVLIM, "DVLIM",
1699 SPR_NOACCESS, SPR_NOACCESS,
1700 &spr_read_generic, &spr_write_generic,
1701 0x00000000);
1702 /* XXX : not implemented */
1703 spr_register(env, SPR_440_INV0, "INV0",
1704 SPR_NOACCESS, SPR_NOACCESS,
1705 &spr_read_generic, &spr_write_generic,
1706 0x00000000);
1707 /* XXX : not implemented */
1708 spr_register(env, SPR_440_INV1, "INV1",
1709 SPR_NOACCESS, SPR_NOACCESS,
1710 &spr_read_generic, &spr_write_generic,
1711 0x00000000);
1712 /* XXX : not implemented */
1713 spr_register(env, SPR_440_INV2, "INV2",
1714 SPR_NOACCESS, SPR_NOACCESS,
1715 &spr_read_generic, &spr_write_generic,
1716 0x00000000);
1717 /* XXX : not implemented */
1718 spr_register(env, SPR_440_INV3, "INV3",
1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, &spr_write_generic,
1721 0x00000000);
1722 /* XXX : not implemented */
1723 spr_register(env, SPR_440_ITV0, "ITV0",
1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_generic, &spr_write_generic,
1726 0x00000000);
1727 /* XXX : not implemented */
1728 spr_register(env, SPR_440_ITV1, "ITV1",
1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, &spr_write_generic,
1731 0x00000000);
1732 /* XXX : not implemented */
1733 spr_register(env, SPR_440_ITV2, "ITV2",
1734 SPR_NOACCESS, SPR_NOACCESS,
1735 &spr_read_generic, &spr_write_generic,
1736 0x00000000);
1737 /* XXX : not implemented */
1738 spr_register(env, SPR_440_ITV3, "ITV3",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, &spr_write_generic,
1741 0x00000000);
1742 /* XXX : not implemented */
1743 spr_register(env, SPR_440_IVLIM, "IVLIM",
1744 SPR_NOACCESS, SPR_NOACCESS,
1745 &spr_read_generic, &spr_write_generic,
1746 0x00000000);
1747 /* Cache debug */
1748 /* XXX : not implemented */
1749 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1750 SPR_NOACCESS, SPR_NOACCESS,
1751 &spr_read_generic, SPR_NOACCESS,
1752 0x00000000);
1753 /* XXX : not implemented */
1754 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1755 SPR_NOACCESS, SPR_NOACCESS,
1756 &spr_read_generic, SPR_NOACCESS,
1757 0x00000000);
1758 /* XXX : not implemented */
1759 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1760 SPR_NOACCESS, SPR_NOACCESS,
1761 &spr_read_generic, SPR_NOACCESS,
1762 0x00000000);
1763 /* XXX : not implemented */
1764 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1765 SPR_NOACCESS, SPR_NOACCESS,
1766 &spr_read_generic, SPR_NOACCESS,
1767 0x00000000);
1768 /* XXX : not implemented */
1769 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1770 SPR_NOACCESS, SPR_NOACCESS,
1771 &spr_read_generic, SPR_NOACCESS,
1772 0x00000000);
1773 /* XXX : not implemented */
1774 spr_register(env, SPR_440_DBDR, "DBDR",
1775 SPR_NOACCESS, SPR_NOACCESS,
1776 &spr_read_generic, &spr_write_generic,
1777 0x00000000);
1778 /* Processor control */
1779 spr_register(env, SPR_4xx_CCR0, "CCR0",
1780 SPR_NOACCESS, SPR_NOACCESS,
1781 &spr_read_generic, &spr_write_generic,
1782 0x00000000);
1783 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1784 SPR_NOACCESS, SPR_NOACCESS,
1785 &spr_read_generic, SPR_NOACCESS,
1786 0x00000000);
1787 /* Storage control */
1788 spr_register(env, SPR_440_MMUCR, "MMUCR",
1789 SPR_NOACCESS, SPR_NOACCESS,
1790 &spr_read_generic, &spr_write_generic,
1791 0x00000000);
1792 }
1793
1794 /* SPR shared between PowerPC 40x implementations */
1795 static void gen_spr_40x (CPUPPCState *env)
1796 {
1797 /* Cache */
1798 /* not emulated, as Qemu do not emulate caches */
1799 spr_register(env, SPR_40x_DCCR, "DCCR",
1800 SPR_NOACCESS, SPR_NOACCESS,
1801 &spr_read_generic, &spr_write_generic,
1802 0x00000000);
1803 /* not emulated, as Qemu do not emulate caches */
1804 spr_register(env, SPR_40x_ICCR, "ICCR",
1805 SPR_NOACCESS, SPR_NOACCESS,
1806 &spr_read_generic, &spr_write_generic,
1807 0x00000000);
1808 /* not emulated, as Qemu do not emulate caches */
1809 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1810 SPR_NOACCESS, SPR_NOACCESS,
1811 &spr_read_generic, SPR_NOACCESS,
1812 0x00000000);
1813 /* Exception */
1814 spr_register(env, SPR_40x_DEAR, "DEAR",
1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_generic, &spr_write_generic,
1817 0x00000000);
1818 spr_register(env, SPR_40x_ESR, "ESR",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, &spr_write_generic,
1821 0x00000000);
1822 spr_register(env, SPR_40x_EVPR, "EVPR",
1823 SPR_NOACCESS, SPR_NOACCESS,
1824 &spr_read_generic, &spr_write_excp_prefix,
1825 0x00000000);
1826 spr_register(env, SPR_40x_SRR2, "SRR2",
1827 &spr_read_generic, &spr_write_generic,
1828 &spr_read_generic, &spr_write_generic,
1829 0x00000000);
1830 spr_register(env, SPR_40x_SRR3, "SRR3",
1831 &spr_read_generic, &spr_write_generic,
1832 &spr_read_generic, &spr_write_generic,
1833 0x00000000);
1834 /* Timers */
1835 spr_register(env, SPR_40x_PIT, "PIT",
1836 SPR_NOACCESS, SPR_NOACCESS,
1837 &spr_read_40x_pit, &spr_write_40x_pit,
1838 0x00000000);
1839 spr_register(env, SPR_40x_TCR, "TCR",
1840 SPR_NOACCESS, SPR_NOACCESS,
1841 &spr_read_generic, &spr_write_booke_tcr,
1842 0x00000000);
1843 spr_register(env, SPR_40x_TSR, "TSR",
1844 SPR_NOACCESS, SPR_NOACCESS,
1845 &spr_read_generic, &spr_write_booke_tsr,
1846 0x00000000);
1847 }
1848
1849 /* SPR specific to PowerPC 405 implementation */
1850 static void gen_spr_405 (CPUPPCState *env)
1851 {
1852 /* MMU */
1853 spr_register(env, SPR_40x_PID, "PID",
1854 SPR_NOACCESS, SPR_NOACCESS,
1855 &spr_read_generic, &spr_write_generic,
1856 0x00000000);
1857 spr_register(env, SPR_4xx_CCR0, "CCR0",
1858 SPR_NOACCESS, SPR_NOACCESS,
1859 &spr_read_generic, &spr_write_generic,
1860 0x00700000);
1861 /* Debug interface */
1862 /* XXX : not implemented */
1863 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1864 SPR_NOACCESS, SPR_NOACCESS,
1865 &spr_read_generic, &spr_write_40x_dbcr0,
1866 0x00000000);
1867 /* XXX : not implemented */
1868 spr_register(env, SPR_405_DBCR1, "DBCR1",
1869 SPR_NOACCESS, SPR_NOACCESS,
1870 &spr_read_generic, &spr_write_generic,
1871 0x00000000);
1872 /* XXX : not implemented */
1873 spr_register(env, SPR_40x_DBSR, "DBSR",
1874 SPR_NOACCESS, SPR_NOACCESS,
1875 &spr_read_generic, &spr_write_clear,
1876 /* Last reset was system reset */
1877 0x00000300);
1878 /* XXX : not implemented */
1879 spr_register(env, SPR_40x_DAC1, "DAC1",
1880 SPR_NOACCESS, SPR_NOACCESS,
1881 &spr_read_generic, &spr_write_generic,
1882 0x00000000);
1883 spr_register(env, SPR_40x_DAC2, "DAC2",
1884 SPR_NOACCESS, SPR_NOACCESS,
1885 &spr_read_generic, &spr_write_generic,
1886 0x00000000);
1887 /* XXX : not implemented */
1888 spr_register(env, SPR_405_DVC1, "DVC1",
1889 SPR_NOACCESS, SPR_NOACCESS,
1890 &spr_read_generic, &spr_write_generic,
1891 0x00000000);
1892 /* XXX : not implemented */
1893 spr_register(env, SPR_405_DVC2, "DVC2",
1894 SPR_NOACCESS, SPR_NOACCESS,
1895 &spr_read_generic, &spr_write_generic,
1896 0x00000000);
1897 /* XXX : not implemented */
1898 spr_register(env, SPR_40x_IAC1, "IAC1",
1899 SPR_NOACCESS, SPR_NOACCESS,
1900 &spr_read_generic, &spr_write_generic,
1901 0x00000000);
1902 spr_register(env, SPR_40x_IAC2, "IAC2",
1903 SPR_NOACCESS, SPR_NOACCESS,
1904 &spr_read_generic, &spr_write_generic,
1905 0x00000000);
1906 /* XXX : not implemented */
1907 spr_register(env, SPR_405_IAC3, "IAC3",
1908 SPR_NOACCESS, SPR_NOACCESS,
1909 &spr_read_generic, &spr_write_generic,
1910 0x00000000);
1911 /* XXX : not implemented */
1912 spr_register(env, SPR_405_IAC4, "IAC4",
1913 SPR_NOACCESS, SPR_NOACCESS,
1914 &spr_read_generic, &spr_write_generic,
1915 0x00000000);
1916 /* Storage control */
1917 /* XXX: TODO: not implemented */
1918 spr_register(env, SPR_405_SLER, "SLER",
1919 SPR_NOACCESS, SPR_NOACCESS,
1920 &spr_read_generic, &spr_write_40x_sler,
1921 0x00000000);
1922 spr_register(env, SPR_40x_ZPR, "ZPR",
1923 SPR_NOACCESS, SPR_NOACCESS,
1924 &spr_read_generic, &spr_write_generic,
1925 0x00000000);
1926 /* XXX : not implemented */
1927 spr_register(env, SPR_405_SU0R, "SU0R",
1928 SPR_NOACCESS, SPR_NOACCESS,
1929 &spr_read_generic, &spr_write_generic,
1930 0x00000000);
1931 /* SPRG */
1932 spr_register(env, SPR_USPRG0, "USPRG0",
1933 &spr_read_ureg, SPR_NOACCESS,
1934 &spr_read_ureg, SPR_NOACCESS,
1935 0x00000000);
1936 spr_register(env, SPR_SPRG4, "SPRG4",
1937 SPR_NOACCESS, SPR_NOACCESS,
1938 &spr_read_generic, &spr_write_generic,
1939 0x00000000);
1940 spr_register(env, SPR_SPRG5, "SPRG5",
1941 SPR_NOACCESS, SPR_NOACCESS,
1942 spr_read_generic, &spr_write_generic,
1943 0x00000000);
1944 spr_register(env, SPR_SPRG6, "SPRG6",
1945 SPR_NOACCESS, SPR_NOACCESS,
1946 spr_read_generic, &spr_write_generic,
1947 0x00000000);
1948 spr_register(env, SPR_SPRG7, "SPRG7",
1949 SPR_NOACCESS, SPR_NOACCESS,
1950 spr_read_generic, &spr_write_generic,
1951 0x00000000);
1952 gen_spr_usprgh(env);
1953 }
1954
1955 /* SPR shared between PowerPC 401 & 403 implementations */
1956 static void gen_spr_401_403 (CPUPPCState *env)
1957 {
1958 /* Time base */
1959 spr_register(env, SPR_403_VTBL, "TBL",
1960 &spr_read_tbl, SPR_NOACCESS,
1961 &spr_read_tbl, SPR_NOACCESS,
1962 0x00000000);
1963 spr_register(env, SPR_403_TBL, "TBL",
1964 SPR_NOACCESS, SPR_NOACCESS,
1965 SPR_NOACCESS, &spr_write_tbl,
1966 0x00000000);
1967 spr_register(env, SPR_403_VTBU, "TBU",
1968 &spr_read_tbu, SPR_NOACCESS,
1969 &spr_read_tbu, SPR_NOACCESS,
1970 0x00000000);
1971 spr_register(env, SPR_403_TBU, "TBU",
1972 SPR_NOACCESS, SPR_NOACCESS,
1973 SPR_NOACCESS, &spr_write_tbu,
1974 0x00000000);
1975 /* Debug */
1976 /* not emulated, as Qemu do not emulate caches */
1977 spr_register(env, SPR_403_CDBCR, "CDBCR",
1978 SPR_NOACCESS, SPR_NOACCESS,
1979 &spr_read_generic, &spr_write_generic,
1980 0x00000000);
1981 }
1982
1983 /* SPR specific to PowerPC 401 implementation */
1984 static void gen_spr_401 (CPUPPCState *env)
1985 {
1986 /* Debug interface */
1987 /* XXX : not implemented */
1988 spr_register(env, SPR_40x_DBCR0, "DBCR",
1989 SPR_NOACCESS, SPR_NOACCESS,
1990 &spr_read_generic, &spr_write_40x_dbcr0,
1991 0x00000000);
1992 /* XXX : not implemented */
1993 spr_register(env, SPR_40x_DBSR, "DBSR",
1994 SPR_NOACCESS, SPR_NOACCESS,
1995 &spr_read_generic, &spr_write_clear,
1996 /* Last reset was system reset */
1997 0x00000300);
1998 /* XXX : not implemented */
1999 spr_register(env, SPR_40x_DAC1, "DAC",
2000 SPR_NOACCESS, SPR_NOACCESS,
2001 &spr_read_generic, &spr_write_generic,
2002 0x00000000);
2003 /* XXX : not implemented */
2004 spr_register(env, SPR_40x_IAC1, "IAC",
2005 SPR_NOACCESS, SPR_NOACCESS,
2006 &spr_read_generic, &spr_write_generic,
2007 0x00000000);
2008 /* Storage control */
2009 /* XXX: TODO: not implemented */
2010 spr_register(env, SPR_405_SLER, "SLER",
2011 SPR_NOACCESS, SPR_NOACCESS,
2012 &spr_read_generic, &spr_write_40x_sler,
2013 0x00000000);
2014 /* not emulated, as Qemu never does speculative access */
2015 spr_register(env, SPR_40x_SGR, "SGR",
2016 SPR_NOACCESS, SPR_NOACCESS,
2017 &spr_read_generic, &spr_write_generic,
2018 0xFFFFFFFF);
2019 /* not emulated, as Qemu do not emulate caches */
2020 spr_register(env, SPR_40x_DCWR, "DCWR",
2021 SPR_NOACCESS, SPR_NOACCESS,
2022 &spr_read_generic, &spr_write_generic,
2023 0x00000000);
2024 }
2025
2026 static void gen_spr_401x2 (CPUPPCState *env)
2027 {
2028 gen_spr_401(env);
2029 spr_register(env, SPR_40x_PID, "PID",
2030 SPR_NOACCESS, SPR_NOACCESS,
2031 &spr_read_generic, &spr_write_generic,
2032 0x00000000);
2033 spr_register(env, SPR_40x_ZPR, "ZPR",
2034 SPR_NOACCESS, SPR_NOACCESS,
2035 &spr_read_generic, &spr_write_generic,
2036 0x00000000);
2037 }
2038
2039 /* SPR specific to PowerPC 403 implementation */
2040 static void gen_spr_403 (CPUPPCState *env)
2041 {
2042 /* Debug interface */
2043 /* XXX : not implemented */
2044 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2045 SPR_NOACCESS, SPR_NOACCESS,
2046 &spr_read_generic, &spr_write_40x_dbcr0,
2047 0x00000000);
2048 /* XXX : not implemented */
2049 spr_register(env, SPR_40x_DBSR, "DBSR",
2050 SPR_NOACCESS, SPR_NOACCESS,
2051 &spr_read_generic, &spr_write_clear,
2052 /* Last reset was system reset */
2053 0x00000300);
2054 /* XXX : not implemented */
2055 spr_register(env, SPR_40x_DAC1, "DAC1",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 &spr_read_generic, &spr_write_generic,
2058 0x00000000);
2059 /* XXX : not implemented */
2060 spr_register(env, SPR_40x_DAC2, "DAC2",
2061 SPR_NOACCESS, SPR_NOACCESS,
2062 &spr_read_generic, &spr_write_generic,
2063 0x00000000);
2064 /* XXX : not implemented */
2065 spr_register(env, SPR_40x_IAC1, "IAC1",
2066 SPR_NOACCESS, SPR_NOACCESS,
2067 &spr_read_generic, &spr_write_generic,
2068 0x00000000);
2069 /* XXX : not implemented */
2070 spr_register(env, SPR_40x_IAC2, "IAC2",
2071 SPR_NOACCESS, SPR_NOACCESS,
2072 &spr_read_generic, &spr_write_generic,
2073 0x00000000);
2074 }
2075
2076 static void gen_spr_403_real (CPUPPCState *env)
2077 {
2078 spr_register(env, SPR_403_PBL1, "PBL1",
2079 SPR_NOACCESS, SPR_NOACCESS,
2080 &spr_read_403_pbr, &spr_write_403_pbr,
2081 0x00000000);
2082 spr_register(env, SPR_403_PBU1, "PBU1",
2083 SPR_NOACCESS, SPR_NOACCESS,
2084 &spr_read_403_pbr, &spr_write_403_pbr,
2085 0x00000000);
2086 spr_register(env, SPR_403_PBL2, "PBL2",
2087 SPR_NOACCESS, SPR_NOACCESS,
2088 &spr_read_403_pbr, &spr_write_403_pbr,
2089 0x00000000);
2090 spr_register(env, SPR_403_PBU2, "PBU2",
2091 SPR_NOACCESS, SPR_NOACCESS,
2092 &spr_read_403_pbr, &spr_write_403_pbr,
2093 0x00000000);
2094 }
2095
2096 static void gen_spr_403_mmu (CPUPPCState *env)
2097 {
2098 /* MMU */
2099 spr_register(env, SPR_40x_PID, "PID",
2100 SPR_NOACCESS, SPR_NOACCESS,
2101 &spr_read_generic, &spr_write_generic,
2102 0x00000000);
2103 spr_register(env, SPR_40x_ZPR, "ZPR",
2104 SPR_NOACCESS, SPR_NOACCESS,
2105 &spr_read_generic, &spr_write_generic,
2106 0x00000000);
2107 }
2108
2109 /* SPR specific to PowerPC compression coprocessor extension */
2110 static void gen_spr_compress (CPUPPCState *env)
2111 {
2112 /* XXX : not implemented */
2113 spr_register(env, SPR_401_SKR, "SKR",
2114 SPR_NOACCESS, SPR_NOACCESS,
2115 &spr_read_generic, &spr_write_generic,
2116 0x00000000);
2117 }
2118
2119 #if defined (TARGET_PPC64)
2120 /* SPR specific to PowerPC 620 */
2121 static void gen_spr_620 (CPUPPCState *env)
2122 {
2123 /* Processor identification */
2124 spr_register(env, SPR_PIR, "PIR",
2125 SPR_NOACCESS, SPR_NOACCESS,
2126 &spr_read_generic, &spr_write_pir,
2127 0x00000000);
2128 spr_register(env, SPR_ASR, "ASR",
2129 SPR_NOACCESS, SPR_NOACCESS,
2130 &spr_read_asr, &spr_write_asr,
2131 0x00000000);
2132 /* Breakpoints */
2133 /* XXX : not implemented */
2134 spr_register(env, SPR_IABR, "IABR",
2135 SPR_NOACCESS, SPR_NOACCESS,
2136 &spr_read_generic, &spr_write_generic,
2137 0x00000000);
2138 /* XXX : not implemented */
2139 spr_register(env, SPR_DABR, "DABR",
2140 SPR_NOACCESS, SPR_NOACCESS,
2141 &spr_read_generic, &spr_write_generic,
2142 0x00000000);
2143 /* XXX : not implemented */
2144 spr_register(env, SPR_SIAR, "SIAR",
2145 SPR_NOACCESS, SPR_NOACCESS,
2146 &spr_read_generic, SPR_NOACCESS,
2147 0x00000000);
2148 /* XXX : not implemented */
2149 spr_register(env, SPR_SDA, "SDA",
2150 SPR_NOACCESS, SPR_NOACCESS,
2151 &spr_read_generic, SPR_NOACCESS,
2152 0x00000000);
2153 /* XXX : not implemented */
2154 spr_register(env, SPR_620_PMC1R, "PMC1",
2155 SPR_NOACCESS, SPR_NOACCESS,
2156 &spr_read_generic, SPR_NOACCESS,
2157 0x00000000);
2158 spr_register(env, SPR_620_PMC1W, "PMC1",
2159 SPR_NOACCESS, SPR_NOACCESS,
2160 SPR_NOACCESS, &spr_write_generic,
2161 0x00000000);
2162 /* XXX : not implemented */
2163 spr_register(env, SPR_620_PMC2R, "PMC2",
2164 SPR_NOACCESS, SPR_NOACCESS,
2165 &spr_read_generic, SPR_NOACCESS,
2166 0x00000000);
2167 spr_register(env, SPR_620_PMC2W, "PMC2",
2168 SPR_NOACCESS, SPR_NOACCESS,
2169 SPR_NOACCESS, &spr_write_generic,
2170 0x00000000);
2171 /* XXX : not implemented */
2172 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2173 SPR_NOACCESS, SPR_NOACCESS,
2174 &spr_read_generic, SPR_NOACCESS,
2175 0x00000000);
2176 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2177 SPR_NOACCESS, SPR_NOACCESS,
2178 SPR_NOACCESS, &spr_write_generic,
2179 0x00000000);
2180 /* External access control */
2181 /* XXX : not implemented */
2182 spr_register(env, SPR_EAR, "EAR",
2183 SPR_NOACCESS, SPR_NOACCESS,
2184 &spr_read_generic, &spr_write_generic,
2185 0x00000000);
2186 #if 0 // XXX: check this
2187 /* XXX : not implemented */
2188 spr_register(env, SPR_620_PMR0, "PMR0",
2189 SPR_NOACCESS, SPR_NOACCESS,
2190 &spr_read_generic, &spr_write_generic,
2191 0x00000000);
2192 /* XXX : not implemented */
2193 spr_register(env, SPR_620_PMR1, "PMR1",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 &spr_read_generic, &spr_write_generic,
2196 0x00000000);
2197 /* XXX : not implemented */
2198 spr_register(env, SPR_620_PMR2, "PMR2",
2199 SPR_NOACCESS, SPR_NOACCESS,
2200 &spr_read_generic, &spr_write_generic,
2201 0x00000000);
2202 /* XXX : not implemented */
2203 spr_register(env, SPR_620_PMR3, "PMR3",
2204 SPR_NOACCESS, SPR_NOACCESS,
2205 &spr_read_generic, &spr_write_generic,
2206 0x00000000);
2207 /* XXX : not implemented */
2208 spr_register(env, SPR_620_PMR4, "PMR4",
2209 SPR_NOACCESS, SPR_NOACCESS,
2210 &spr_read_generic, &spr_write_generic,
2211 0x00000000);
2212 /* XXX : not implemented */
2213 spr_register(env, SPR_620_PMR5, "PMR5",
2214 SPR_NOACCESS, SPR_NOACCESS,
2215 &spr_read_generic, &spr_write_generic,
2216 0x00000000);
2217 /* XXX : not implemented */
2218 spr_register(env, SPR_620_PMR6, "PMR6",
2219 SPR_NOACCESS, SPR_NOACCESS,
2220 &spr_read_generic, &spr_write_generic,
2221 0x00000000);
2222 /* XXX : not implemented */
2223 spr_register(env, SPR_620_PMR7, "PMR7",
2224 SPR_NOACCESS, SPR_NOACCESS,
2225 &spr_read_generic, &spr_write_generic,
2226 0x00000000);
2227 /* XXX : not implemented */
2228 spr_register(env, SPR_620_PMR8, "PMR8",
2229 SPR_NOACCESS, SPR_NOACCESS,
2230 &spr_read_generic, &spr_write_generic,
2231 0x00000000);
2232 /* XXX : not implemented */
2233 spr_register(env, SPR_620_PMR9, "PMR9",
2234 SPR_NOACCESS, SPR_NOACCESS,
2235 &spr_read_generic, &spr_write_generic,
2236 0x00000000);
2237 /* XXX : not implemented */
2238 spr_register(env, SPR_620_PMRA, "PMR10",
2239 SPR_NOACCESS, SPR_NOACCESS,
2240 &spr_read_generic, &spr_write_generic,
2241 0x00000000);
2242 /* XXX : not implemented */
2243 spr_register(env, SPR_620_PMRB, "PMR11",
2244 SPR_NOACCESS, SPR_NOACCESS,
2245 &spr_read_generic, &spr_write_generic,
2246 0x00000000);
2247 /* XXX : not implemented */
2248 spr_register(env, SPR_620_PMRC, "PMR12",
2249 SPR_NOACCESS, SPR_NOACCESS,
2250 &spr_read_generic, &spr_write_generic,
2251 0x00000000);
2252 /* XXX : not implemented */
2253 spr_register(env, SPR_620_PMRD, "PMR13",
2254 SPR_NOACCESS, SPR_NOACCESS,
2255 &spr_read_generic, &spr_write_generic,
2256 0x00000000);
2257 /* XXX : not implemented */
2258 spr_register(env, SPR_620_PMRE, "PMR14",
2259 SPR_NOACCESS, SPR_NOACCESS,
2260 &spr_read_generic, &spr_write_generic,
2261 0x00000000);
2262 /* XXX : not implemented */
2263 spr_register(env, SPR_620_PMRF, "PMR15",
2264 SPR_NOACCESS, SPR_NOACCESS,
2265 &spr_read_generic, &spr_write_generic,
2266 0x00000000);
2267 #endif
2268 /* XXX : not implemented */
2269 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2270 SPR_NOACCESS, SPR_NOACCESS,
2271 &spr_read_generic, &spr_write_generic,
2272 0x00000000);
2273 /* XXX : not implemented */
2274 spr_register(env, SPR_620_L2CR, "L2CR",
2275 SPR_NOACCESS, SPR_NOACCESS,
2276 &spr_read_generic, &spr_write_generic,
2277 0x00000000);
2278 /* XXX : not implemented */
2279 spr_register(env, SPR_620_L2SR, "L2SR",
2280 SPR_NOACCESS, SPR_NOACCESS,
2281 &spr_read_generic, &spr_write_generic,
2282 0x00000000);
2283 }
2284 #endif /* defined (TARGET_PPC64) */
2285
2286 static void gen_spr_5xx_8xx (CPUPPCState *env)
2287 {
2288 /* Exception processing */
2289 spr_register(env, SPR_DSISR, "DSISR",
2290 SPR_NOACCESS, SPR_NOACCESS,
2291 &spr_read_generic, &spr_write_generic,
2292 0x00000000);
2293 spr_register(env, SPR_DAR, "DAR",
2294 SPR_NOACCESS, SPR_NOACCESS,
2295 &spr_read_generic, &spr_write_generic,
2296 0x00000000);
2297 /* Timer */
2298 spr_register(env, SPR_DECR, "DECR",
2299 SPR_NOACCESS, SPR_NOACCESS,
2300 &spr_read_decr, &spr_write_decr,
2301 0x00000000);
2302 /* XXX : not implemented */
2303 spr_register(env, SPR_MPC_EIE, "EIE",
2304 SPR_NOACCESS, SPR_NOACCESS,
2305 &spr_read_generic, &spr_write_generic,
2306 0x00000000);
2307 /* XXX : not implemented */
2308 spr_register(env, SPR_MPC_EID, "EID",
2309 SPR_NOACCESS, SPR_NOACCESS,
2310 &spr_read_generic, &spr_write_generic,
2311 0x00000000);
2312 /* XXX : not implemented */
2313 spr_register(env, SPR_MPC_NRI, "NRI",
2314 SPR_NOACCESS, SPR_NOACCESS,
2315 &spr_read_generic, &spr_write_generic,
2316 0x00000000);
2317 /* XXX : not implemented */
2318 spr_register(env, SPR_MPC_CMPA, "CMPA",
2319 SPR_NOACCESS, SPR_NOACCESS,
2320 &spr_read_generic, &spr_write_generic,
2321 0x00000000);
2322 /* XXX : not implemented */
2323 spr_register(env, SPR_MPC_CMPB, "CMPB",
2324 SPR_NOACCESS, SPR_NOACCESS,
2325 &spr_read_generic, &spr_write_generic,
2326 0x00000000);
2327 /* XXX : not implemented */
2328 spr_register(env, SPR_MPC_CMPC, "CMPC",
2329 SPR_NOACCESS, SPR_NOACCESS,
2330 &spr_read_generic, &spr_write_generic,
2331 0x00000000);
2332 /* XXX : not implemented */
2333 spr_register(env, SPR_MPC_CMPD, "CMPD",
2334 SPR_NOACCESS, SPR_NOACCESS,
2335 &spr_read_generic, &spr_write_generic,
2336 0x00000000);
2337 /* XXX : not implemented */
2338 spr_register(env, SPR_MPC_ECR, "ECR",
2339 SPR_NOACCESS, SPR_NOACCESS,
2340 &spr_read_generic, &spr_write_generic,
2341 0x00000000);
2342 /* XXX : not implemented */
2343 spr_register(env, SPR_MPC_DER, "DER",
2344 SPR_NOACCESS, SPR_NOACCESS,
2345 &spr_read_generic, &spr_write_generic,
2346 0x00000000);
2347 /* XXX : not implemented */
2348 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2349 SPR_NOACCESS, SPR_NOACCESS,
2350 &spr_read_generic, &spr_write_generic,
2351 0x00000000);
2352 /* XXX : not implemented */
2353 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2354 SPR_NOACCESS, SPR_NOACCESS,
2355 &spr_read_generic, &spr_write_generic,
2356 0x00000000);
2357 /* XXX : not implemented */
2358 spr_register(env, SPR_MPC_CMPE, "CMPE",
2359 SPR_NOACCESS, SPR_NOACCESS,
2360 &spr_read_generic, &spr_write_generic,
2361 0x00000000);
2362 /* XXX : not implemented */
2363 spr_register(env, SPR_MPC_CMPF, "CMPF",
2364 SPR_NOACCESS, SPR_NOACCESS,
2365 &spr_read_generic, &spr_write_generic,
2366 0x00000000);
2367 /* XXX : not implemented */
2368 spr_register(env, SPR_MPC_CMPG, "CMPG",
2369 SPR_NOACCESS, SPR_NOACCESS,
2370 &spr_read_generic, &spr_write_generic,
2371 0x00000000);
2372 /* XXX : not implemented */
2373 spr_register(env, SPR_MPC_CMPH, "CMPH",
2374 SPR_NOACCESS, SPR_NOACCESS,
2375 &spr_read_generic, &spr_write_generic,
2376 0x00000000);
2377 /* XXX : not implemented */
2378 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2379 SPR_NOACCESS, SPR_NOACCESS,
2380 &spr_read_generic, &spr_write_generic,
2381 0x00000000);
2382 /* XXX : not implemented */
2383 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2384 SPR_NOACCESS, SPR_NOACCESS,
2385 &spr_read_generic, &spr_write_generic,
2386 0x00000000);
2387 /* XXX : not implemented */
2388 spr_register(env, SPR_MPC_BAR, "BAR",
2389 SPR_NOACCESS, SPR_NOACCESS,
2390 &spr_read_generic, &spr_write_generic,
2391 0x00000000);
2392 /* XXX : not implemented */
2393 spr_register(env, SPR_MPC_DPDR, "DPDR",
2394 SPR_NOACCESS, SPR_NOACCESS,
2395 &spr_read_generic, &spr_write_generic,
2396 0x00000000);
2397 /* XXX : not implemented */
2398 spr_register(env, SPR_MPC_IMMR, "IMMR",
2399 SPR_NOACCESS, SPR_NOACCESS,
2400 &spr_read_generic, &spr_write_generic,
2401 0x00000000);
2402 }
2403
2404 static void gen_spr_5xx (CPUPPCState *env)
2405 {
2406 /* XXX : not implemented */
2407 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2408 SPR_NOACCESS, SPR_NOACCESS,
2409 &spr_read_generic, &spr_write_generic,
2410 0x00000000);
2411 /* XXX : not implemented */
2412 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2413 SPR_NOACCESS, SPR_NOACCESS,
2414 &spr_read_generic, &spr_write_generic,
2415 0x00000000);
2416 /* XXX : not implemented */
2417 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2418 SPR_NOACCESS, SPR_NOACCESS,
2419 &spr_read_generic, &spr_write_generic,
2420 0x00000000);
2421 /* XXX : not implemented */
2422 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2423 SPR_NOACCESS, SPR_NOACCESS,
2424 &spr_read_generic, &spr_write_generic,
2425 0x00000000);
2426 /* XXX : not implemented */
2427 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2428 SPR_NOACCESS, SPR_NOACCESS,
2429 &spr_read_generic, &spr_write_generic,
2430 0x00000000);
2431 /* XXX : not implemented */
2432 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2433 SPR_NOACCESS, SPR_NOACCESS,
2434 &spr_read_generic, &spr_write_generic,
2435 0x00000000);
2436 /* XXX : not implemented */
2437 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2438 SPR_NOACCESS, SPR_NOACCESS,
2439 &spr_read_generic, &spr_write_generic,
2440 0x00000000);
2441 /* XXX : not implemented */
2442 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2443 SPR_NOACCESS, SPR_NOACCESS,
2444 &spr_read_generic, &spr_write_generic,
2445 0x00000000);
2446 /* XXX : not implemented */
2447 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2448 SPR_NOACCESS, SPR_NOACCESS,
2449 &spr_read_generic, &spr_write_generic,
2450 0x00000000);
2451 /* XXX : not implemented */
2452 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2453 SPR_NOACCESS, SPR_NOACCESS,
2454 &spr_read_generic, &spr_write_generic,
2455 0x00000000);
2456 /* XXX : not implemented */
2457 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2458 SPR_NOACCESS, SPR_NOACCESS,
2459 &spr_read_generic, &spr_write_generic,
2460 0x00000000);
2461 /* XXX : not implemented */
2462 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2463 SPR_NOACCESS, SPR_NOACCESS,
2464 &spr_read_generic, &spr_write_generic,
2465 0x00000000);
2466 /* XXX : not implemented */
2467 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2468 SPR_NOACCESS, SPR_NOACCESS,
2469 &spr_read_generic, &spr_write_generic,
2470 0x00000000);
2471 /* XXX : not implemented */
2472 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2473 SPR_NOACCESS, SPR_NOACCESS,
2474 &spr_read_generic, &spr_write_generic,
2475 0x00000000);
2476 /* XXX : not implemented */
2477 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2478 SPR_NOACCESS, SPR_NOACCESS,
2479 &spr_read_generic, &spr_write_generic,
2480 0x00000000);
2481 /* XXX : not implemented */
2482 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2483 SPR_NOACCESS, SPR_NOACCESS,
2484 &spr_read_generic, &spr_write_generic,
2485 0x00000000);
2486 /* XXX : not implemented */
2487 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2488 SPR_NOACCESS, SPR_NOACCESS,
2489 &spr_read_generic, &spr_write_generic,
2490 0x00000000);
2491 /* XXX : not implemented */
2492 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2493 SPR_NOACCESS, SPR_NOACCESS,
2494 &spr_read_generic, &spr_write_generic,
2495 0x00000000);
2496 /* XXX : not implemented */
2497 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2498 SPR_NOACCESS, SPR_NOACCESS,
2499 &spr_read_generic, &spr_write_generic,
2500 0x00000000);
2501 /* XXX : not implemented */
2502 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2503 SPR_NOACCESS, SPR_NOACCESS,
2504 &spr_read_generic, &spr_write_generic,
2505 0x00000000);
2506 /* XXX : not implemented */
2507 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2508 SPR_NOACCESS, SPR_NOACCESS,
2509 &spr_read_generic, &spr_write_generic,
2510 0x00000000);
2511 }
2512
2513 static void gen_spr_8xx (CPUPPCState *env)
2514 {
2515 /* XXX : not implemented */
2516 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2517 SPR_NOACCESS, SPR_NOACCESS,
2518 &spr_read_generic, &spr_write_generic,
2519 0x00000000);
2520 /* XXX : not implemented */
2521 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2522 SPR_NOACCESS, SPR_NOACCESS,
2523 &spr_read_generic, &spr_write_generic,
2524 0x00000000);
2525 /* XXX : not implemented */
2526 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2527 SPR_NOACCESS, SPR_NOACCESS,
2528 &spr_read_generic, &spr_write_generic,
2529 0x00000000);
2530 /* XXX : not implemented */
2531 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2532 SPR_NOACCESS, SPR_NOACCESS,
2533 &spr_read_generic, &spr_write_generic,
2534 0x00000000);
2535 /* XXX : not implemented */
2536 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2537 SPR_NOACCESS, SPR_NOACCESS,
2538 &spr_read_generic, &spr_write_generic,
2539 0x00000000);
2540 /* XXX : not implemented */
2541 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2542 SPR_NOACCESS, SPR_NOACCESS,
2543 &spr_read_generic, &spr_write_generic,
2544 0x00000000);
2545 /* XXX : not implemented */
2546 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2547 SPR_NOACCESS, SPR_NOACCESS,
2548 &spr_read_generic, &spr_write_generic,
2549 0x00000000);
2550 /* XXX : not implemented */
2551 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2552 SPR_NOACCESS, SPR_NOACCESS,
2553 &spr_read_generic, &spr_write_generic,
2554 0x00000000);
2555 /* XXX : not implemented */
2556 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2557 SPR_NOACCESS, SPR_NOACCESS,
2558 &spr_read_generic, &spr_write_generic,
2559 0x00000000);
2560 /* XXX : not implemented */
2561 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2562 SPR_NOACCESS, SPR_NOACCESS,
2563 &spr_read_generic, &spr_write_generic,
2564 0x00000000);
2565 /* XXX : not implemented */
2566 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2567 SPR_NOACCESS, SPR_NOACCESS,
2568 &spr_read_generic, &spr_write_generic,
2569 0x00000000);
2570 /* XXX : not implemented */
2571 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2572 SPR_NOACCESS, SPR_NOACCESS,
2573 &spr_read_generic, &spr_write_generic,
2574 0x00000000);
2575 /* XXX : not implemented */
2576 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2577 SPR_NOACCESS, SPR_NOACCESS,
2578 &spr_read_generic, &spr_write_generic,
2579 0x00000000);
2580 /* XXX : not implemented */
2581 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2582 SPR_NOACCESS, SPR_NOACCESS,
2583 &spr_read_generic, &spr_write_generic,
2584 0x00000000);
2585 /* XXX : not implemented */
2586 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2587 SPR_NOACCESS, SPR_NOACCESS,
2588 &spr_read_generic, &spr_write_generic,
2589 0x00000000);
2590 /* XXX : not implemented */
2591 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2592 SPR_NOACCESS, SPR_NOACCESS,
2593 &spr_read_generic, &spr_write_generic,
2594 0x00000000);
2595 /* XXX : not implemented */
2596 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2597 SPR_NOACCESS, SPR_NOACCESS,
2598 &spr_read_generic, &spr_write_generic,
2599 0x00000000);
2600 /* XXX : not implemented */
2601 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2602 SPR_NOACCESS, SPR_NOACCESS,
2603 &spr_read_generic, &spr_write_generic,
2604 0x00000000);
2605 /* XXX : not implemented */
2606 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2607 SPR_NOACCESS, SPR_NOACCESS,
2608 &spr_read_generic, &spr_write_generic,
2609 0x00000000);
2610 /* XXX : not implemented */
2611 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2612 SPR_NOACCESS, SPR_NOACCESS,
2613 &spr_read_generic, &spr_write_generic,
2614 0x00000000);
2615 /* XXX : not implemented */
2616 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2617 SPR_NOACCESS, SPR_NOACCESS,
2618 &spr_read_generic, &spr_write_generic,
2619 0x00000000);
2620 /* XXX : not implemented */
2621 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2622 SPR_NOACCESS, SPR_NOACCESS,
2623 &spr_read_generic, &spr_write_generic,
2624 0x00000000);
2625 /* XXX : not implemented */
2626 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2627 SPR_NOACCESS, SPR_NOACCESS,
2628 &spr_read_generic, &spr_write_generic,
2629 0x00000000);
2630 /* XXX : not implemented */
2631 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2632 SPR_NOACCESS, SPR_NOACCESS,
2633 &spr_read_generic, &spr_write_generic,
2634 0x00000000);
2635 /* XXX : not implemented */
2636 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2637 SPR_NOACCESS, SPR_NOACCESS,
2638 &spr_read_generic, &spr_write_generic,
2639 0x00000000);
2640 }
2641
2642 // XXX: TODO
2643 /*
2644 * AMR => SPR 29 (Power 2.04)
2645 * CTRL => SPR 136 (Power 2.04)
2646 * CTRL => SPR 152 (Power 2.04)
2647 * SCOMC => SPR 276 (64 bits ?)
2648 * SCOMD => SPR 277 (64 bits ?)
2649 * TBU40 => SPR 286 (Power 2.04 hypv)
2650 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2651 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2652 * HDSISR => SPR 306 (Power 2.04 hypv)
2653 * HDAR => SPR 307 (Power 2.04 hypv)
2654 * PURR => SPR 309 (Power 2.04 hypv)
2655 * HDEC => SPR 310 (Power 2.04 hypv)
2656 * HIOR => SPR 311 (hypv)
2657 * RMOR => SPR 312 (970)
2658 * HRMOR => SPR 313 (Power 2.04 hypv)
2659 * HSRR0 => SPR 314 (Power 2.04 hypv)
2660 * HSRR1 => SPR 315 (Power 2.04 hypv)
2661 * LPCR => SPR 316 (970)
2662 * LPIDR => SPR 317 (970)
2663 * EPR => SPR 702 (Power 2.04 emb)
2664 * perf => 768-783 (Power 2.04)
2665 * perf => 784-799 (Power 2.04)
2666 * PPR => SPR 896 (Power 2.04)
2667 * EPLC => SPR 947 (Power 2.04 emb)
2668 * EPSC => SPR 948 (Power 2.04 emb)
2669 * DABRX => 1015 (Power 2.04 hypv)
2670 * FPECR => SPR 1022 (?)
2671 * ... and more (thermal management, performance counters, ...)
2672 */
2673
2674 /*****************************************************************************/
2675 /* Exception vectors models */
2676 static void init_excp_4xx_real (CPUPPCState *env)
2677 {
2678 #if !defined(CONFIG_USER_ONLY)
2679 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2680 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2681 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2682 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2683 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2684 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2685 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2686 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2687 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2688 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2689 env->hreset_excp_prefix = 0x00000000UL;
2690 env->ivor_mask = 0x0000FFF0UL;
2691 env->ivpr_mask = 0xFFFF0000UL;
2692 /* Hardware reset vector */
2693 env->hreset_vector = 0xFFFFFFFCUL;
2694 #endif
2695 }
2696
2697 static void init_excp_4xx_softmmu (CPUPPCState *env)
2698 {
2699 #if !defined(CONFIG_USER_ONLY)
2700 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2701 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2702 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2703 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2704 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2705 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2706 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2707 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2708 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2709 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2710 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2711 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2712 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2713 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2714 env->hreset_excp_prefix = 0x00000000UL;
2715 env->ivor_mask = 0x0000FFF0UL;
2716 env->ivpr_mask = 0xFFFF0000UL;
2717 /* Hardware reset vector */
2718 env->hreset_vector = 0xFFFFFFFCUL;
2719 #endif
2720 }
2721
2722 static void init_excp_MPC5xx (CPUPPCState *env)
2723 {
2724 #if !defined(CONFIG_USER_ONLY)
2725 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2726 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2727 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2728 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2729 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2730 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2731 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2732 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2733 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2734 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2735 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2736 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2737 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2738 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2739 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2740 env->hreset_excp_prefix = 0x00000000UL;
2741 env->ivor_mask = 0x0000FFF0UL;
2742 env->ivpr_mask = 0xFFFF0000UL;
2743 /* Hardware reset vector */
2744 env->hreset_vector = 0xFFFFFFFCUL;
2745 #endif
2746 }
2747
2748 static void init_excp_MPC8xx (CPUPPCState *env)
2749 {
2750 #if !defined(CONFIG_USER_ONLY)
2751 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2752 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2753 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2754 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2755 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2756 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2757 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2758 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2759 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2760 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2761 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2762 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2763 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2764 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2765 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2766 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2767 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2768 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2769 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2770 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2771 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2772 env->hreset_excp_prefix = 0x00000000UL;
2773 env->ivor_mask = 0x0000FFF0UL;
2774 env->ivpr_mask = 0xFFFF0000UL;
2775 /* Hardware reset vector */
2776 env->hreset_vector = 0xFFFFFFFCUL;
2777 #endif
2778 }
2779
2780 static void init_excp_G2 (CPUPPCState *env)
2781 {
2782 #if !defined(CONFIG_USER_ONLY)
2783 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2784 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2785 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2786 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2787 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2788 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2789 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2790 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2791 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2792 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2793 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2794 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2795 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2796 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2797 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2798 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2799 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2800 env->hreset_excp_prefix = 0x00000000UL;
2801 /* Hardware reset vector */
2802 env->hreset_vector = 0xFFFFFFFCUL;
2803 #endif
2804 }
2805
2806 static void init_excp_e200 (CPUPPCState *env)
2807 {
2808 #if !defined(CONFIG_USER_ONLY)
2809 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2810 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2811 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2812 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2813 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2814 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2815 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2816 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2817 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2818 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2819 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2820 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2821 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2822 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2823 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2824 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2825 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2826 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2827 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2828 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2829 env->hreset_excp_prefix = 0x00000000UL;
2830 env->ivor_mask = 0x0000FFF7UL;
2831 env->ivpr_mask = 0xFFFF0000UL;
2832 /* Hardware reset vector */
2833 env->hreset_vector = 0xFFFFFFFCUL;
2834 #endif
2835 }
2836
2837 static void init_excp_BookE (CPUPPCState *env)
2838 {
2839 #if !defined(CONFIG_USER_ONLY)
2840 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2841 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2842 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2843 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2844 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2845 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2846 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2847 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2848 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2849 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2850 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2851 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2852 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2853 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2854 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2855 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2856 env->hreset_excp_prefix = 0x00000000UL;
2857 env->ivor_mask = 0x0000FFE0UL;
2858 env->ivpr_mask = 0xFFFF0000UL;
2859 /* Hardware reset vector */
2860 env->hreset_vector = 0xFFFFFFFCUL;
2861 #endif
2862 }
2863
2864 static void init_excp_601 (CPUPPCState *env)
2865 {
2866 #if !defined(CONFIG_USER_ONLY)
2867 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2868 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2869 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2870 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2871 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2872 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2873 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2874 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2875 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2876 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2877 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2878 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2879 env->hreset_excp_prefix = 0xFFF00000UL;
2880 /* Hardware reset vector */
2881 env->hreset_vector = 0x00000100UL;
2882 #endif
2883 }
2884
2885 static void init_excp_602 (CPUPPCState *env)
2886 {
2887 #if !defined(CONFIG_USER_ONLY)
2888 /* XXX: exception prefix has a special behavior on 602 */
2889 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2890 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2891 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2892 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2893 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2894 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2895 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2896 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2897 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2898 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2899 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2900 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2901 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2902 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2903 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2904 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2905 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2906 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2907 env->hreset_excp_prefix = 0xFFF00000UL;
2908 /* Hardware reset vector */
2909 env->hreset_vector = 0xFFFFFFFCUL;
2910 #endif
2911 }
2912
2913 static void init_excp_603 (CPUPPCState *env)
2914 {
2915 #if !defined(CONFIG_USER_ONLY)
2916 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2917 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2918 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2919 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2920 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2921 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2922 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2923 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2924 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2925 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2926 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2927 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2928 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2929 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2930 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2931 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2932 env->hreset_excp_prefix = 0x00000000UL;
2933 /* Hardware reset vector */
2934 env->hreset_vector = 0xFFFFFFFCUL;
2935 #endif
2936 }
2937
2938 static void init_excp_604 (CPUPPCState *env)
2939 {
2940 #if !defined(CONFIG_USER_ONLY)
2941 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2942 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2943 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2944 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2945 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2946 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2947 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2948 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2949 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2950 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2951 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2952 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2953 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2954 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2955 env->hreset_excp_prefix = 0xFFF00000UL;
2956 /* Hardware reset vector */
2957 env->hreset_vector = 0x00000100UL;
2958 #endif
2959 }
2960
2961 #if defined(TARGET_PPC64)
2962 static void init_excp_620 (CPUPPCState *env)
2963 {
2964 #if !defined(CONFIG_USER_ONLY)
2965 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2966 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2967 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2968 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2969 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2970 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2971 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2972 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2973 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2974 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2975 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2976 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2977 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2978 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2979 env->hreset_excp_prefix = 0xFFF00000UL;
2980 /* Hardware reset vector */
2981 env->hreset_vector = 0x0000000000000100ULL;
2982 #endif
2983 }
2984 #endif /* defined(TARGET_PPC64) */
2985
2986 static void init_excp_7x0 (CPUPPCState *env)
2987 {
2988 #if !defined(CONFIG_USER_ONLY)
2989 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2990 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2991 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2992 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2993 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2994 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2995 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2996 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2997 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2998 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2999 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3000 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3001 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3002 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3003 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3004 env->hreset_excp_prefix = 0x00000000UL;
3005 /* Hardware reset vector */
3006 env->hreset_vector = 0xFFFFFFFCUL;
3007 #endif
3008 }
3009
3010 static void init_excp_750cl (CPUPPCState *env)
3011 {
3012 #if !defined(CONFIG_USER_ONLY)
3013 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3014 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3015 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3016 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3017 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3018 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3019 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3020 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3021 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3022 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3023 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3024 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3025 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3026 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3027 env->hreset_excp_prefix = 0x00000000UL;
3028 /* Hardware reset vector */
3029 env->hreset_vector = 0xFFFFFFFCUL;
3030 #endif
3031 }
3032
3033 static void init_excp_750cx (CPUPPCState *env)
3034 {
3035 #if !defined(CONFIG_USER_ONLY)
3036 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3037 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3038 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3039 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3040 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3041 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3042 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3043 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3044 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3045 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3046 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3047 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3048 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3049 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3050 env->hreset_excp_prefix = 0x00000000UL;
3051 /* Hardware reset vector */
3052 env->hreset_vector = 0xFFFFFFFCUL;
3053 #endif
3054 }
3055
3056 /* XXX: Check if this is correct */
3057 static void init_excp_7x5 (CPUPPCState *env)
3058 {
3059 #if !defined(CONFIG_USER_ONLY)
3060 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3061 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3062 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3063 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3064 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3065 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3066 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3067 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3068 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3069 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3070 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3071 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3072 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3073 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3074 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3075 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3076 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3077 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3078 env->hreset_excp_prefix = 0x00000000UL;
3079 /* Hardware reset vector */
3080 env->hreset_vector = 0xFFFFFFFCUL;
3081 #endif
3082 }
3083
3084 static void init_excp_7400 (CPUPPCState *env)
3085 {
3086 #if !defined(CONFIG_USER_ONLY)
3087 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3088 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3089 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3090 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3091 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3092 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3093 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3094 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3095 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3096 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3097 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3098 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3099 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3100 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3101 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3102 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3103 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3104 env->hreset_excp_prefix = 0x00000000UL;
3105 /* Hardware reset vector */
3106 env->hreset_vector = 0xFFFFFFFCUL;
3107 #endif
3108 }
3109
3110 static void init_excp_7450 (CPUPPCState *env)
3111 {
3112 #if !defined(CONFIG_USER_ONLY)
3113 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3114 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3115 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3116 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3117 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3118 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3119 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3120 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3121 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3122 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3123 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3124 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3125 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3126 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3127 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3128 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3129 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3130 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3131 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3132 env->hreset_excp_prefix = 0x00000000UL;
3133 /* Hardware reset vector */
3134 env->hreset_vector = 0xFFFFFFFCUL;
3135 #endif
3136 }
3137
3138 #if defined (TARGET_PPC64)
3139 static void init_excp_970 (CPUPPCState *env)
3140 {
3141 #if !defined(CONFIG_USER_ONLY)
3142 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3143 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3144 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3145 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3146 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3147 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3148 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3149 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3150 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3151 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3152 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3153 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3154 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3155 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3156 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3157 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3158 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3159 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3160 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3161 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3162 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
3163 /* Hardware reset vector */
3164 env->hreset_vector = 0x0000000000000100ULL;
3165 #endif
3166 }
3167
3168 static void init_excp_POWER7 (CPUPPCState *env)
3169 {
3170 #if !defined(CONFIG_USER_ONLY)
3171 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3172 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3173 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3174 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3175 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3176 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3177 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3178 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3179 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3180 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3181 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3182 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3183 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3184 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3185 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3186 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3187 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3188 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3189 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3190 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3191 env->hreset_excp_prefix = 0;
3192 /* Hardware reset vector */
3193 env->hreset_vector = 0x0000000000000100ULL;
3194 #endif
3195 }
3196 #endif
3197
3198 /*****************************************************************************/
3199 /* Power management enable checks */
3200 static int check_pow_none (CPUPPCState *env)
3201 {
3202 return 0;
3203 }
3204
3205 static int check_pow_nocheck (CPUPPCState *env)
3206 {
3207 return 1;
3208 }
3209
3210 static int check_pow_hid0 (CPUPPCState *env)
3211 {
3212 if (env->spr[SPR_HID0] & 0x00E00000)
3213 return 1;
3214
3215 return 0;
3216 }
3217
3218 static int check_pow_hid0_74xx (CPUPPCState *env)
3219 {
3220 if (env->spr[SPR_HID0] & 0x00600000)
3221 return 1;
3222
3223 return 0;
3224 }
3225
3226 /*****************************************************************************/
3227 /* PowerPC implementations definitions */
3228
3229 /* PowerPC 401 */
3230 #define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3231 PPC_WRTEE | PPC_DCR | \
3232 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3233 PPC_CACHE_DCBZ | \
3234 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3235 PPC_4xx_COMMON | PPC_40x_EXCP)
3236 #define POWERPC_INSNS2_401 (PPC_NONE)
3237 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
3238 #define POWERPC_MMU_401 (POWERPC_MMU_REAL)
3239 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3240 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
3241 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
3242 #define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3243 POWERPC_FLAG_BUS_CLK)
3244 #define check_pow_401 check_pow_nocheck
3245
3246 static void init_proc_401 (CPUPPCState *env)
3247 {
3248 gen_spr_40x(env);
3249 gen_spr_401_403(env);
3250 gen_spr_401(env);
3251 init_excp_4xx_real(env);
3252 env->dcache_line_size = 32;
3253 env->icache_line_size = 32;
3254 /* Allocate hardware IRQ controller */
3255 ppc40x_irq_init(env);
3256
3257 SET_FIT_PERIOD(12, 16, 20, 24);
3258 SET_WDT_PERIOD(16, 20, 24, 28);
3259 }
3260
3261 /* PowerPC 401x2 */
3262 #define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3263 PPC_DCR | PPC_WRTEE | \
3264 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3265 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3266 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3267 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3268 PPC_4xx_COMMON | PPC_40x_EXCP)
3269 #define POWERPC_INSNS2_401x2 (PPC_NONE)
3270 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3271 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3272 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3273 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
3274 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
3275 #define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3276 POWERPC_FLAG_BUS_CLK)
3277 #define check_pow_401x2 check_pow_nocheck
3278
3279 static void init_proc_401x2 (CPUPPCState *env)
3280 {
3281 gen_spr_40x(env);
3282 gen_spr_401_403(env);
3283 gen_spr_401x2(env);
3284 gen_spr_compress(env);
3285 /* Memory management */
3286 #if !defined(CONFIG_USER_ONLY)
3287 env->nb_tlb = 64;
3288 env->nb_ways = 1;
3289 env->id_tlbs = 0;
3290 env->tlb_type = TLB_EMB;
3291 #endif
3292 init_excp_4xx_softmmu(env);
3293 env->dcache_line_size = 32;
3294 env->icache_line_size = 32;
3295 /* Allocate hardware IRQ controller */
3296 ppc40x_irq_init(env);
3297
3298 SET_FIT_PERIOD(12, 16, 20, 24);
3299 SET_WDT_PERIOD(16, 20, 24, 28);
3300 }
3301
3302 /* PowerPC 401x3 */
3303 #define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3304 PPC_DCR | PPC_WRTEE | \
3305 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3306 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3307 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3308 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3309 PPC_4xx_COMMON | PPC_40x_EXCP)
3310 #define POWERPC_INSNS2_401x3 (PPC_NONE)
3311 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3312 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3313 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3314 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
3315 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
3316 #define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3317 POWERPC_FLAG_BUS_CLK)
3318 #define check_pow_401x3 check_pow_nocheck
3319
3320 __attribute__ (( unused ))
3321 static void init_proc_401x3 (CPUPPCState *env)
3322 {
3323 gen_spr_40x(env);
3324 gen_spr_401_403(env);
3325 gen_spr_401(env);
3326 gen_spr_401x2(env);
3327 gen_spr_compress(env);
3328 init_excp_4xx_softmmu(env);
3329 env->dcache_line_size = 32;
3330 env->icache_line_size = 32;
3331 /* Allocate hardware IRQ controller */
3332 ppc40x_irq_init(env);
3333
3334 SET_FIT_PERIOD(12, 16, 20, 24);
3335 SET_WDT_PERIOD(16, 20, 24, 28);
3336 }
3337
3338 /* IOP480 */
3339 #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3340 PPC_DCR | PPC_WRTEE | \
3341 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3342 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3343 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3344 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3345 PPC_4xx_COMMON | PPC_40x_EXCP)
3346 #define POWERPC_INSNS2_IOP480 (PPC_NONE)
3347 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3348 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3349 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3350 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
3351 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
3352 #define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3353 POWERPC_FLAG_BUS_CLK)
3354 #define check_pow_IOP480 check_pow_nocheck
3355
3356 static void init_proc_IOP480 (CPUPPCState *env)
3357 {
3358 gen_spr_40x(env);
3359 gen_spr_401_403(env);
3360 gen_spr_401x2(env);
3361 gen_spr_compress(env);
3362 /* Memory management */
3363 #if !defined(CONFIG_USER_ONLY)
3364 env->nb_tlb = 64;
3365 env->nb_ways = 1;
3366 env->id_tlbs = 0;
3367 env->tlb_type = TLB_EMB;
3368 #endif
3369 init_excp_4xx_softmmu(env);
3370 env->dcache_line_size = 32;
3371 env->icache_line_size = 32;
3372 /* Allocate hardware IRQ controller */
3373 ppc40x_irq_init(env);
3374
3375 SET_FIT_PERIOD(8, 12, 16, 20);
3376 SET_WDT_PERIOD(16, 20, 24, 28);
3377 }
3378
3379 /* PowerPC 403 */
3380 #define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3381 PPC_DCR | PPC_WRTEE | \
3382 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3383 PPC_CACHE_DCBZ | \
3384 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3385 PPC_4xx_COMMON | PPC_40x_EXCP)
3386 #define POWERPC_INSNS2_403 (PPC_NONE)
3387 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
3388 #define POWERPC_MMU_403 (POWERPC_MMU_REAL)
3389 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3390 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
3391 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
3392 #define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3393 POWERPC_FLAG_BUS_CLK)
3394 #define check_pow_403 check_pow_nocheck
3395
3396 static void init_proc_403 (CPUPPCState *env)
3397 {
3398 gen_spr_40x(env);
3399 gen_spr_401_403(env);
3400 gen_spr_403(env);
3401 gen_spr_403_real(env);
3402 init_excp_4xx_real(env);
3403 env->dcache_line_size = 32;
3404 env->icache_line_size = 32;
3405 /* Allocate hardware IRQ controller */
3406 ppc40x_irq_init(env);
3407
3408 SET_FIT_PERIOD(8, 12, 16, 20);
3409 SET_WDT_PERIOD(16, 20, 24, 28);
3410 }
3411
3412 /* PowerPC 403 GCX */
3413 #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3414 PPC_DCR | PPC_WRTEE | \
3415 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3416 PPC_CACHE_DCBZ | \
3417 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3418 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3419 PPC_4xx_COMMON | PPC_40x_EXCP)
3420 #define POWERPC_INSNS2_403GCX (PPC_NONE)
3421 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3422 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3423 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3424 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
3425 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
3426 #define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3427 POWERPC_FLAG_BUS_CLK)
3428 #define check_pow_403GCX check_pow_nocheck
3429
3430 static void init_proc_403GCX (CPUPPCState *env)
3431 {
3432 gen_spr_40x(env);
3433 gen_spr_401_403(env);
3434 gen_spr_403(env);
3435 gen_spr_403_real(env);
3436 gen_spr_403_mmu(env);
3437 /* Bus access control */
3438 /* not emulated, as Qemu never does speculative access */
3439 spr_register(env, SPR_40x_SGR, "SGR",
3440 SPR_NOACCESS, SPR_NOACCESS,
3441 &spr_read_generic, &spr_write_generic,
3442 0xFFFFFFFF);
3443 /* not emulated, as Qemu do not emulate caches */
3444 spr_register(env, SPR_40x_DCWR, "DCWR",
3445 SPR_NOACCESS, SPR_NOACCESS,
3446 &spr_read_generic, &spr_write_generic,
3447 0x00000000);
3448 /* Memory management */
3449 #if !defined(CONFIG_USER_ONLY)
3450 env->nb_tlb = 64;
3451 env->nb_ways = 1;
3452 env->id_tlbs = 0;
3453 env->tlb_type = TLB_EMB;
3454 #endif
3455 init_excp_4xx_softmmu(env);
3456 env->dcache_line_size = 32;
3457 env->icache_line_size = 32;
3458 /* Allocate hardware IRQ controller */
3459 ppc40x_irq_init(env);
3460
3461 SET_FIT_PERIOD(8, 12, 16, 20);
3462 SET_WDT_PERIOD(16, 20, 24, 28);
3463 }
3464
3465 /* PowerPC 405 */
3466 #define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3467 PPC_DCR | PPC_WRTEE | \
3468 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3469 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3470 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3471 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3472 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3473 #define POWERPC_INSNS2_405 (PPC_NONE)
3474 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
3475 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3476 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3477 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3478 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3479 #define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3480 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3481 #define check_pow_405 check_pow_nocheck
3482
3483 static void init_proc_405 (CPUPPCState *env)
3484 {
3485 /* Time base */
3486 gen_tbl(env);
3487 gen_spr_40x(env);
3488 gen_spr_405(env);
3489 /* Bus access control */
3490 /* not emulated, as Qemu never does speculative access */
3491 spr_register(env, SPR_40x_SGR, "SGR",
3492 SPR_NOACCESS, SPR_NOACCESS,
3493 &spr_read_generic, &spr_write_generic,
3494 0xFFFFFFFF);
3495 /* not emulated, as Qemu do not emulate caches */
3496 spr_register(env, SPR_40x_DCWR, "DCWR",
3497 SPR_NOACCESS, SPR_NOACCESS,
3498 &spr_read_generic, &spr_write_generic,
3499 0x00000000);
3500 /* Memory management */
3501 #if !defined(CONFIG_USER_ONLY)
3502 env->nb_tlb = 64;
3503 env->nb_ways = 1;
3504 env->id_tlbs = 0;
3505 env->tlb_type = TLB_EMB;
3506 #endif
3507 init_excp_4xx_softmmu(env);
3508 env->dcache_line_size = 32;
3509 env->icache_line_size = 32;
3510 /* Allocate hardware IRQ controller */
3511 ppc40x_irq_init(env);
3512
3513 SET_FIT_PERIOD(8, 12, 16, 20);
3514 SET_WDT_PERIOD(16, 20, 24, 28);
3515 }
3516
3517 /* PowerPC 440 EP */
3518 #define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3519 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3520 PPC_CACHE | PPC_CACHE_ICBI | \
3521 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3522 PPC_MEM_TLBSYNC | PPC_MFTB | \
3523 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3524 PPC_440_SPEC)
3525 #define POWERPC_INSNS2_440EP (PPC_NONE)
3526 #define POWERPC_MSRM_440EP (0x000000000006D630ULL)
3527 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3528 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3529 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3530 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3531 #define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3532 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3533 #define check_pow_440EP check_pow_nocheck
3534
3535 __attribute__ (( unused ))
3536 static void init_proc_440EP (CPUPPCState *env)
3537 {
3538 /* Time base */
3539 gen_tbl(env);
3540 gen_spr_BookE(env, 0x000000000000FFFFULL);
3541 gen_spr_440(env);
3542 gen_spr_usprgh(env);
3543 /* Processor identification */
3544 spr_register(env, SPR_BOOKE_PIR, "PIR",
3545 SPR_NOACCESS, SPR_NOACCESS,
3546 &spr_read_generic, &spr_write_pir,
3547 0x00000000);
3548 /* XXX : not implemented */
3549 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3550 SPR_NOACCESS, SPR_NOACCESS,
3551 &spr_read_generic, &spr_write_generic,
3552 0x00000000);
3553 /* XXX : not implemented */
3554 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3555 SPR_NOACCESS, SPR_NOACCESS,
3556 &spr_read_generic, &spr_write_generic,
3557 0x00000000);
3558 /* XXX : not implemented */
3559 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3560 SPR_NOACCESS, SPR_NOACCESS,
3561 &spr_read_generic, &spr_write_generic,
3562 0x00000000);
3563 /* XXX : not implemented */
3564 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3565 SPR_NOACCESS, SPR_NOACCESS,
3566 &spr_read_generic, &spr_write_generic,
3567 0x00000000);
3568 /* XXX : not implemented */
3569 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3570 SPR_NOACCESS, SPR_NOACCESS,
3571 &spr_read_generic, &spr_write_generic,
3572 0x00000000);
3573 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3574 SPR_NOACCESS, SPR_NOACCESS,
3575 &spr_read_generic, &spr_write_generic,
3576 0x00000000);
3577 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3578 SPR_NOACCESS, SPR_NOACCESS,
3579 &spr_read_generic, &spr_write_generic,
3580 0x00000000);
3581 /* XXX : not implemented */
3582 spr_register(env, SPR_440_CCR1, "CCR1",
3583 SPR_NOACCESS, SPR_NOACCESS,
3584 &spr_read_generic, &spr_write_generic,
3585 0x00000000);
3586 /* Memory management */
3587 #if !defined(CONFIG_USER_ONLY)
3588 env->nb_tlb = 64;
3589 env->nb_ways = 1;
3590 env->id_tlbs = 0;
3591 env->tlb_type = TLB_EMB;
3592 #endif
3593 init_excp_BookE(env);
3594 env->dcache_line_size = 32;
3595 env->icache_line_size = 32;
3596 /* XXX: TODO: allocate internal IRQ controller */
3597
3598 SET_FIT_PERIOD(12, 16, 20, 24);
3599 SET_WDT_PERIOD(20, 24, 28, 32);
3600 }
3601
3602 /* PowerPC 440 GP */
3603 #define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3604 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3605 PPC_CACHE | PPC_CACHE_ICBI | \
3606 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3607 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \
3608 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3609 PPC_440_SPEC)
3610 #define POWERPC_INSNS2_440GP (PPC_NONE)
3611 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3612 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3613 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3614 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3615 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3616 #define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3617 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3618 #define check_pow_440GP check_pow_nocheck
3619
3620 __attribute__ (( unused ))
3621 static void init_proc_440GP (CPUPPCState *env)
3622 {
3623 /* Time base */
3624 gen_tbl(env);
3625 gen_spr_BookE(env, 0x000000000000FFFFULL);
3626 gen_spr_440(env);
3627 gen_spr_usprgh(env);
3628 /* Processor identification */
3629 spr_register(env, SPR_BOOKE_PIR, "PIR",
3630 SPR_NOACCESS, SPR_NOACCESS,
3631 &spr_read_generic, &spr_write_pir,
3632 0x00000000);
3633 /* XXX : not implemented */
3634 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3635 SPR_NOACCESS, SPR_NOACCESS,
3636 &spr_read_generic, &spr_write_generic,
3637 0x00000000);
3638 /* XXX : not implemented */
3639 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3640 SPR_NOACCESS, SPR_NOACCESS,
3641 &spr_read_generic, &spr_write_generic,
3642 0x00000000);
3643 /* XXX : not implemented */
3644 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3645 SPR_NOACCESS, SPR_NOACCESS,
3646 &spr_read_generic, &spr_write_generic,
3647 0x00000000);
3648 /* XXX : not implemented */
3649 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3650 SPR_NOACCESS, SPR_NOACCESS,
3651 &spr_read_generic, &spr_write_generic,
3652 0x00000000);
3653 /* Memory management */
3654 #if !defined(CONFIG_USER_ONLY)
3655 env->nb_tlb = 64;
3656 env->nb_ways = 1;
3657 env->id_tlbs = 0;
3658 env->tlb_type = TLB_EMB;
3659 #endif
3660 init_excp_BookE(env);
3661 env->dcache_line_size = 32;
3662 env->icache_line_size = 32;
3663 /* XXX: TODO: allocate internal IRQ controller */
3664
3665 SET_FIT_PERIOD(12, 16, 20, 24);
3666 SET_WDT_PERIOD(20, 24, 28, 32);
3667 }
3668
3669 /* PowerPC 440x4 */
3670 #define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3671 PPC_DCR | PPC_WRTEE | \
3672 PPC_CACHE | PPC_CACHE_ICBI | \
3673 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3674 PPC_MEM_TLBSYNC | PPC_MFTB | \
3675 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3676 PPC_440_SPEC)
3677 #define POWERPC_INSNS2_440x4 (PPC_NONE)
3678 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3679 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3680 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3681 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3682 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3683 #define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3684 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3685 #define check_pow_440x4 check_pow_nocheck
3686
3687 __attribute__ (( unused ))
3688 static void init_proc_440x4 (CPUPPCState *env)
3689 {
3690 /* Time base */
3691 gen_tbl(env);
3692 gen_spr_BookE(env, 0x000000000000FFFFULL);
3693 gen_spr_440(env);
3694 gen_spr_usprgh(env);
3695 /* Processor identification */
3696 spr_register(env, SPR_BOOKE_PIR, "PIR",
3697 SPR_NOACCESS, SPR_NOACCESS,
3698 &spr_read_generic, &spr_write_pir,
3699 0x00000000);
3700 /* XXX : not implemented */
3701 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3702 SPR_NOACCESS, SPR_NOACCESS,
3703 &spr_read_generic, &spr_write_generic,
3704 0x00000000);
3705 /* XXX : not implemented */
3706 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3707 SPR_NOACCESS, SPR_NOACCESS,
3708 &spr_read_generic, &spr_write_generic,
3709 0x00000000);
3710 /* XXX : not implemented */
3711 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3712 SPR_NOACCESS, SPR_NOACCESS,
3713 &spr_read_generic, &spr_write_generic,
3714 0x00000000);
3715 /* XXX : not implemented */
3716 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3717 SPR_NOACCESS, SPR_NOACCESS,
3718 &spr_read_generic, &spr_write_generic,
3719 0x00000000);
3720 /* Memory management */
3721 #if !defined(CONFIG_USER_ONLY)
3722 env->nb_tlb = 64;
3723 env->nb_ways = 1;
3724 env->id_tlbs = 0;
3725 env->tlb_type = TLB_EMB;
3726 #endif
3727 init_excp_BookE(env);
3728 env->dcache_line_size = 32;
3729 env->icache_line_size = 32;
3730 /* XXX: TODO: allocate internal IRQ controller */
3731
3732 SET_FIT_PERIOD(12, 16, 20, 24);
3733 SET_WDT_PERIOD(20, 24, 28, 32);
3734 }
3735
3736 /* PowerPC 440x5 */
3737 #define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3738 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3739 PPC_CACHE | PPC_CACHE_ICBI | \
3740 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3741 PPC_MEM_TLBSYNC | PPC_MFTB | \
3742 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3743 PPC_440_SPEC)
3744 #define POWERPC_INSNS2_440x5 (PPC_NONE)
3745 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3746 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3747 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3748 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3749 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3750 #define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3751 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3752 #define check_pow_440x5 check_pow_nocheck
3753
3754 static void init_proc_440x5 (CPUPPCState *env)
3755 {
3756 /* Time base */
3757 gen_tbl(env);
3758 gen_spr_BookE(env, 0x000000000000FFFFULL);
3759 gen_spr_440(env);
3760 gen_spr_usprgh(env);
3761 /* Processor identification */
3762 spr_register(env, SPR_BOOKE_PIR, "PIR",
3763 SPR_NOACCESS, SPR_NOACCESS,
3764 &spr_read_generic, &spr_write_pir,
3765 0x00000000);
3766 /* XXX : not implemented */
3767 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3768 SPR_NOACCESS, SPR_NOACCESS,
3769 &spr_read_generic, &spr_write_generic,
3770 0x00000000);
3771 /* XXX : not implemented */
3772 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3773 SPR_NOACCESS, SPR_NOACCESS,
3774 &spr_read_generic, &spr_write_generic,
3775 0x00000000);
3776 /* XXX : not implemented */
3777 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3778 SPR_NOACCESS, SPR_NOACCESS,
3779 &spr_read_generic, &spr_write_generic,
3780 0x00000000);
3781 /* XXX : not implemented */
3782 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3783 SPR_NOACCESS, SPR_NOACCESS,
3784 &spr_read_generic, &spr_write_generic,
3785 0x00000000);
3786 /* XXX : not implemented */
3787 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3788 SPR_NOACCESS, SPR_NOACCESS,
3789 &spr_read_generic, &spr_write_generic,
3790 0x00000000);
3791 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3792 SPR_NOACCESS, SPR_NOACCESS,
3793 &spr_read_generic, &spr_write_generic,
3794 0x00000000);
3795 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3796 SPR_NOACCESS, SPR_NOACCESS,
3797 &spr_read_generic, &spr_write_generic,
3798 0x00000000);
3799 /* XXX : not implemented */
3800 spr_register(env, SPR_440_CCR1, "CCR1",
3801 SPR_NOACCESS, SPR_NOACCESS,
3802 &spr_read_generic, &spr_write_generic,
3803 0x00000000);
3804 /* Memory management */
3805 #if !defined(CONFIG_USER_ONLY)
3806 env->nb_tlb = 64;
3807 env->nb_ways = 1;
3808 env->id_tlbs = 0;
3809 env->tlb_type = TLB_EMB;
3810 #endif
3811 init_excp_BookE(env);
3812 env->dcache_line_size = 32;
3813 env->icache_line_size = 32;
3814 ppc40x_irq_init(env);
3815
3816 SET_FIT_PERIOD(12, 16, 20, 24);
3817 SET_WDT_PERIOD(20, 24, 28, 32);
3818 }
3819
3820 /* PowerPC 460 (guessed) */
3821 #define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
3822 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3823 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | \
3824 PPC_CACHE | PPC_CACHE_ICBI | \
3825 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3826 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3827 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3828 PPC_440_SPEC)
3829 #define POWERPC_INSNS2_460 (PPC_NONE)
3830 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3831 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3832 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3833 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3834 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3835 #define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3836 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3837 #define check_pow_460 check_pow_nocheck
3838
3839 __attribute__ (( unused ))
3840 static void init_proc_460 (CPUPPCState *env)
3841 {
3842 /* Time base */
3843 gen_tbl(env);
3844 gen_spr_BookE(env, 0x000000000000FFFFULL);
3845 gen_spr_440(env);
3846 gen_spr_usprgh(env);
3847 /* Processor identification */
3848 spr_register(env, SPR_BOOKE_PIR, "PIR",
3849 SPR_NOACCESS, SPR_NOACCESS,
3850 &spr_read_generic, &spr_write_pir,
3851 0x00000000);
3852 /* XXX : not implemented */
3853 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3854 SPR_NOACCESS, SPR_NOACCESS,
3855 &spr_read_generic, &spr_write_generic,
3856 0x00000000);
3857 /* XXX : not implemented */
3858 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3859 SPR_NOACCESS, SPR_NOACCESS,
3860 &spr_read_generic, &spr_write_generic,
3861 0x00000000);
3862 /* XXX : not implemented */
3863 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3864 SPR_NOACCESS, SPR_NOACCESS,
3865 &spr_read_generic, &spr_write_generic,
3866 0x00000000);
3867 /* XXX : not implemented */
3868 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3869 SPR_NOACCESS, SPR_NOACCESS,
3870 &spr_read_generic, &spr_write_generic,
3871 0x00000000);
3872 /* XXX : not implemented */
3873 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3874 SPR_NOACCESS, SPR_NOACCESS,
3875 &spr_read_generic, &spr_write_generic,
3876 0x00000000);
3877 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3878 SPR_NOACCESS, SPR_NOACCESS,
3879 &spr_read_generic, &spr_write_generic,
3880 0x00000000);
3881 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3882 SPR_NOACCESS, SPR_NOACCESS,
3883 &spr_read_generic, &spr_write_generic,
3884 0x00000000);
3885 /* XXX : not implemented */
3886 spr_register(env, SPR_440_CCR1, "CCR1",
3887 SPR_NOACCESS, SPR_NOACCESS,
3888 &spr_read_generic, &spr_write_generic,
3889 0x00000000);
3890 /* XXX : not implemented */
3891 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3892 &spr_read_generic, &spr_write_generic,
3893 &spr_read_generic, &spr_write_generic,
3894 0x00000000);
3895 /* Memory management */
3896 #if !defined(CONFIG_USER_ONLY)
3897 env->nb_tlb = 64;
3898 env->nb_ways = 1;
3899 env->id_tlbs = 0;
3900 env->tlb_type = TLB_EMB;
3901 #endif
3902 init_excp_BookE(env);
3903 env->dcache_line_size = 32;
3904 env->icache_line_size = 32;
3905 /* XXX: TODO: allocate internal IRQ controller */
3906
3907 SET_FIT_PERIOD(12, 16, 20, 24);
3908 SET_WDT_PERIOD(20, 24, 28, 32);
3909 }
3910
3911 /* PowerPC 460F (guessed) */
3912 #define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3913 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3914 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3915 PPC_FLOAT_STFIWX | PPC_MFTB | \
3916 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3917 PPC_WRTEE | PPC_MFAPIDI | \
3918 PPC_CACHE | PPC_CACHE_ICBI | \
3919 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3920 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3921 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3922 PPC_440_SPEC)
3923 #define POWERPC_INSNS2_460F (PPC_NONE)
3924 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3925 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3926 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3927 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3928 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3929 #define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3930 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3931 #define check_pow_460F check_pow_nocheck
3932
3933 __attribute__ (( unused ))
3934 static void init_proc_460F (CPUPPCState *env)
3935 {
3936 /* Time base */
3937 gen_tbl(env);
3938 gen_spr_BookE(env, 0x000000000000FFFFULL);
3939 gen_spr_440(env);
3940 gen_spr_usprgh(env);
3941 /* Processor identification */
3942 spr_register(env, SPR_BOOKE_PIR, "PIR",
3943 SPR_NOACCESS, SPR_NOACCESS,
3944 &spr_read_generic, &spr_write_pir,
3945 0x00000000);
3946 /* XXX : not implemented */
3947 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3948 SPR_NOACCESS, SPR_NOACCESS,
3949 &spr_read_generic, &spr_write_generic,
3950 0x00000000);
3951 /* XXX : not implemented */
3952 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3953 SPR_NOACCESS, SPR_NOACCESS,
3954 &spr_read_generic, &spr_write_generic,
3955 0x00000000);
3956 /* XXX : not implemented */
3957 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3958 SPR_NOACCESS, SPR_NOACCESS,
3959 &spr_read_generic, &spr_write_generic,
3960 0x00000000);
3961 /* XXX : not implemented */
3962 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3963 SPR_NOACCESS, SPR_NOACCESS,
3964 &spr_read_generic, &spr_write_generic,
3965 0x00000000);
3966 /* XXX : not implemented */
3967 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3968 SPR_NOACCESS, SPR_NOACCESS,
3969 &spr_read_generic, &spr_write_generic,
3970 0x00000000);
3971 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3972 SPR_NOACCESS, SPR_NOACCESS,
3973 &spr_read_generic, &spr_write_generic,
3974 0x00000000);
3975 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3976 SPR_NOACCESS, SPR_NOACCESS,
3977 &spr_read_generic, &spr_write_generic,
3978 0x00000000);
3979 /* XXX : not implemented */
3980 spr_register(env, SPR_440_CCR1, "CCR1",
3981 SPR_NOACCESS, SPR_NOACCESS,
3982 &spr_read_generic, &spr_write_generic,
3983 0x00000000);
3984 /* XXX : not implemented */
3985 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3986 &spr_read_generic, &spr_write_generic,
3987 &spr_read_generic, &spr_write_generic,
3988 0x00000000);
3989 /* Memory management */
3990 #if !defined(CONFIG_USER_ONLY)
3991 env->nb_tlb = 64;
3992 env->nb_ways = 1;
3993 env->id_tlbs = 0;
3994 env->tlb_type = TLB_EMB;
3995 #endif
3996 init_excp_BookE(env);
3997 env->dcache_line_size = 32;
3998 env->icache_line_size = 32;
3999 /* XXX: TODO: allocate internal IRQ controller */
4000
4001 SET_FIT_PERIOD(12, 16, 20, 24);
4002 SET_WDT_PERIOD(20, 24, 28, 32);
4003 }
4004
4005 /* Freescale 5xx cores (aka RCPU) */
4006 #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
4007 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4008 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
4009 PPC_MFTB)
4010 #define POWERPC_INSNS2_MPC5xx (PPC_NONE)
4011 #define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
4012 #define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
4013 #define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
4014 #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
4015 #define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
4016 #define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4017 POWERPC_FLAG_BUS_CLK)
4018 #define check_pow_MPC5xx check_pow_none
4019
4020 __attribute__ (( unused ))
4021 static void init_proc_MPC5xx (CPUPPCState *env)
4022 {
4023 /* Time base */
4024 gen_tbl(env);
4025 gen_spr_5xx_8xx(env);
4026 gen_spr_5xx(env);
4027 init_excp_MPC5xx(env);
4028 env->dcache_line_size = 32;
4029 env->icache_line_size = 32;
4030 /* XXX: TODO: allocate internal IRQ controller */
4031 }
4032
4033 /* Freescale 8xx cores (aka PowerQUICC) */
4034 #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
4035 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4036 PPC_CACHE_ICBI | PPC_MFTB)
4037 #define POWERPC_INSNS2_MPC8xx (PPC_NONE)
4038 #define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
4039 #define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
4040 #define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
4041 #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
4042 #define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4043 #define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4044 POWERPC_FLAG_BUS_CLK)
4045 #define check_pow_MPC8xx check_pow_none
4046
4047 __attribute__ (( unused ))
4048 static void init_proc_MPC8xx (CPUPPCState *env)
4049 {
4050 /* Time base */
4051 gen_tbl(env);
4052 gen_spr_5xx_8xx(env);
4053 gen_spr_8xx(env);
4054 init_excp_MPC8xx(env);
4055 env->dcache_line_size = 32;
4056 env->icache_line_size = 32;
4057 /* XXX: TODO: allocate internal IRQ controller */
4058 }
4059
4060 /* Freescale 82xx cores (aka PowerQUICC-II) */
4061 /* PowerPC G2 */
4062 #define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4063 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4064 PPC_FLOAT_STFIWX | \
4065 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4066 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4067 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4068 PPC_SEGMENT | PPC_EXTERN)
4069 #define POWERPC_INSNS2_G2 (PPC_NONE)
4070 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
4071 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
4072 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
4073 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
4074 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
4075 #define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4076 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4077 #define check_pow_G2 check_pow_hid0
4078
4079 static void init_proc_G2 (CPUPPCState *env)
4080 {
4081 gen_spr_ne_601(env);
4082 gen_spr_G2_755(env);
4083 gen_spr_G2(env);
4084 /* Time base */
4085 gen_tbl(env);
4086 /* External access control */
4087 /* XXX : not implemented */
4088 spr_register(env, SPR_EAR, "EAR",
4089 SPR_NOACCESS, SPR_NOACCESS,
4090 &spr_read_generic, &spr_write_generic,
4091 0x00000000);
4092 /* Hardware implementation register */
4093 /* XXX : not implemented */
4094 spr_register(env, SPR_HID0, "HID0",
4095 SPR_NOACCESS, SPR_NOACCESS,
4096 &spr_read_generic, &spr_write_generic,
4097 0x00000000);
4098 /* XXX : not implemented */
4099 spr_register(env, SPR_HID1, "HID1",
4100 SPR_NOACCESS, SPR_NOACCESS,
4101 &spr_read_generic, &spr_write_generic,
4102 0x00000000);
4103 /* XXX : not implemented */
4104 spr_register(env, SPR_HID2, "HID2",
4105 SPR_NOACCESS, SPR_NOACCESS,
4106 &spr_read_generic, &spr_write_generic,
4107 0x00000000);
4108 /* Memory management */
4109 gen_low_BATs(env);
4110 gen_high_BATs(env);
4111 gen_6xx_7xx_soft_tlb(env, 64, 2);
4112 init_excp_G2(env);
4113 env->dcache_line_size = 32;
4114 env->icache_line_size = 32;
4115 /* Allocate hardware IRQ controller */
4116 ppc6xx_irq_init(env);
4117 }
4118
4119 /* PowerPC G2LE */
4120 #define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4121 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4122 PPC_FLOAT_STFIWX | \
4123 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4124 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4125 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4126 PPC_SEGMENT | PPC_EXTERN)
4127 #define POWERPC_INSNS2_G2LE (PPC_NONE)
4128 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
4129 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
4130 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
4131 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
4132 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
4133 #define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4134 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4135 #define check_pow_G2LE check_pow_hid0
4136
4137 static void init_proc_G2LE (CPUPPCState *env)
4138 {
4139 gen_spr_ne_601(env);
4140 gen_spr_G2_755(env);
4141 gen_spr_G2(env);
4142 /* Time base */
4143 gen_tbl(env);
4144 /* External access control */
4145 /* XXX : not implemented */
4146 spr_register(env, SPR_EAR, "EAR",
4147 SPR_NOACCESS, SPR_NOACCESS,
4148 &spr_read_generic, &spr_write_generic,
4149 0x00000000);
4150 /* Hardware implementation register */
4151 /* XXX : not implemented */
4152 spr_register(env, SPR_HID0, "HID0",
4153 SPR_NOACCESS, SPR_NOACCESS,
4154 &spr_read_generic, &spr_write_generic,
4155 0x00000000);
4156 /* XXX : not implemented */
4157 spr_register(env, SPR_HID1, "HID1",
4158 SPR_NOACCESS, SPR_NOACCESS,
4159 &spr_read_generic, &spr_write_generic,
4160 0x00000000);
4161 /* XXX : not implemented */
4162 spr_register(env, SPR_HID2, "HID2",
4163 SPR_NOACCESS, SPR_NOACCESS,
4164 &spr_read_generic, &spr_write_generic,
4165 0x00000000);
4166 /* Memory management */
4167 gen_low_BATs(env);
4168 gen_high_BATs(env);
4169 gen_6xx_7xx_soft_tlb(env, 64, 2);
4170 init_excp_G2(env);
4171 env->dcache_line_size = 32;
4172 env->icache_line_size = 32;
4173 /* Allocate hardware IRQ controller */
4174 ppc6xx_irq_init(env);
4175 }
4176
4177 /* e200 core */
4178 /* XXX: unimplemented instructions:
4179 * dcblc
4180 * dcbtlst
4181 * dcbtstls
4182 * icblc
4183 * icbtls
4184 * tlbivax
4185 * all SPE multiply-accumulate instructions
4186 */
4187 #define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
4188 PPC_SPE | PPC_SPE_SINGLE | \
4189 PPC_WRTEE | PPC_RFDI | \
4190 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4191 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4192 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4193 PPC_BOOKE)
4194 #define POWERPC_INSNS2_e200 (PPC_NONE)
4195 #define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
4196 #define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE206)
4197 #define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
4198 #define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
4199 #define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
4200 #define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4201 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4202 POWERPC_FLAG_BUS_CLK)
4203 #define check_pow_e200 check_pow_hid0
4204
4205 __attribute__ (( unused ))
4206 static void init_proc_e200 (CPUPPCState *env)
4207 {
4208 /* Time base */
4209 gen_tbl(env);
4210 gen_spr_BookE(env, 0x000000070000FFFFULL);
4211 /* XXX : not implemented */
4212 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4213 &spr_read_spefscr, &spr_write_spefscr,
4214 &spr_read_spefscr, &spr_write_spefscr,
4215 0x00000000);
4216 /* Memory management */
4217 gen_spr_BookE206(env, 0x0000005D, NULL);
4218 /* XXX : not implemented */
4219 spr_register(env, SPR_HID0, "HID0",
4220 SPR_NOACCESS, SPR_NOACCESS,
4221 &spr_read_generic, &spr_write_generic,
4222 0x00000000);
4223 /* XXX : not implemented */
4224 spr_register(env, SPR_HID1, "HID1",
4225 SPR_NOACCESS, SPR_NOACCESS,
4226 &spr_read_generic, &spr_write_generic,
4227 0x00000000);
4228 /* XXX : not implemented */
4229 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4230 SPR_NOACCESS, SPR_NOACCESS,
4231 &spr_read_generic, &spr_write_generic,
4232 0x00000000);
4233 /* XXX : not implemented */
4234 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4235 SPR_NOACCESS, SPR_NOACCESS,
4236 &spr_read_generic, &spr_write_generic,
4237 0x00000000);
4238 /* XXX : not implemented */
4239 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4240 SPR_NOACCESS, SPR_NOACCESS,
4241 &spr_read_generic, &spr_write_generic,
4242 0x00000000);
4243 /* XXX : not implemented */
4244 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4245 SPR_NOACCESS, SPR_NOACCESS,
4246 &spr_read_generic, &spr_write_generic,
4247 0x00000000);
4248 /* XXX : not implemented */
4249 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4250 SPR_NOACCESS, SPR_NOACCESS,
4251 &spr_read_generic, &spr_write_generic,
4252 0x00000000);
4253 /* XXX : not implemented */
4254 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4255 SPR_NOACCESS, SPR_NOACCESS,
4256 &spr_read_generic, &spr_write_generic,
4257 0x00000000);
4258 /* XXX : not implemented */
4259 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4260 SPR_NOACCESS, SPR_NOACCESS,
4261 &spr_read_generic, &spr_write_generic,
4262 0x00000000);
4263 /* XXX : not implemented */
4264 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4265 SPR_NOACCESS, SPR_NOACCESS,
4266 &spr_read_generic, &spr_write_generic,
4267 0x00000000);
4268 /* XXX : not implemented */
4269 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4270 SPR_NOACCESS, SPR_NOACCESS,
4271 &spr_read_generic, &spr_write_generic,
4272 0x00000000);
4273 /* XXX : not implemented */
4274 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4275 SPR_NOACCESS, SPR_NOACCESS,
4276 &spr_read_generic, &spr_write_generic,
4277 0x00000000);
4278 /* XXX : not implemented */
4279 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4280 SPR_NOACCESS, SPR_NOACCESS,
4281 &spr_read_generic, &spr_write_generic,
4282 0x00000000);
4283 /* XXX : not implemented */
4284 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4285 SPR_NOACCESS, SPR_NOACCESS,
4286 &spr_read_generic, &spr_write_generic,
4287 0x00000000);
4288 /* XXX : not implemented */
4289 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4290 SPR_NOACCESS, SPR_NOACCESS,
4291 &spr_read_generic, &spr_write_generic,
4292 0x00000000); /* TOFIX */
4293 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4294 SPR_NOACCESS, SPR_NOACCESS,
4295 &spr_read_generic, &spr_write_generic,
4296 0x00000000);
4297 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4298 SPR_NOACCESS, SPR_NOACCESS,
4299 &spr_read_generic, &spr_write_generic,
4300 0x00000000);
4301 #if !defined(CONFIG_USER_ONLY)
4302 env->nb_tlb = 64;
4303 env->nb_ways = 1;
4304 env->id_tlbs = 0;
4305 env->tlb_type = TLB_EMB;
4306 #endif
4307 init_excp_e200(env);
4308 env->dcache_line_size = 32;
4309 env->icache_line_size = 32;
4310 /* XXX: TODO: allocate internal IRQ controller */
4311 }
4312
4313 /* e300 core */
4314 #define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4315 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4316 PPC_FLOAT_STFIWX | \
4317 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4318 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4319 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4320 PPC_SEGMENT | PPC_EXTERN)
4321 #define POWERPC_INSNS2_e300 (PPC_NONE)
4322 #define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4323 #define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4324 #define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4325 #define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4326 #define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4327 #define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4328 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4329 #define check_pow_e300 check_pow_hid0
4330
4331 __attribute__ (( unused ))
4332 static void init_proc_e300 (CPUPPCState *env)
4333 {
4334 gen_spr_ne_601(env);
4335 gen_spr_603(env);
4336 /* Time base */
4337 gen_tbl(env);
4338 /* hardware implementation registers */
4339 /* XXX : not implemented */
4340 spr_register(env, SPR_HID0, "HID0",
4341 SPR_NOACCESS, SPR_NOACCESS,
4342 &spr_read_generic, &spr_write_generic,
4343 0x00000000);
4344 /* XXX : not implemented */
4345 spr_register(env, SPR_HID1, "HID1",
4346 SPR_NOACCESS, SPR_NOACCESS,
4347 &spr_read_generic, &spr_write_generic,
4348 0x00000000);
4349 /* XXX : not implemented */
4350 spr_register(env, SPR_HID2, "HID2",
4351 SPR_NOACCESS, SPR_NOACCESS,
4352 &spr_read_generic, &spr_write_generic,
4353 0x00000000);
4354 /* Memory management */
4355 gen_low_BATs(env);
4356 gen_high_BATs(env);
4357 gen_6xx_7xx_soft_tlb(env, 64, 2);
4358 init_excp_603(env);
4359 env->dcache_line_size = 32;
4360 env->icache_line_size = 32;
4361 /* Allocate hardware IRQ controller */
4362 ppc6xx_irq_init(env);
4363 }
4364
4365 /* e500v1 core */
4366 #define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
4367 PPC_SPE | PPC_SPE_SINGLE | \
4368 PPC_WRTEE | PPC_RFDI | \
4369 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4370 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4371 PPC_MEM_TLBSYNC | PPC_TLBIVAX)
4372 #define POWERPC_INSNS2_e500v1 (PPC2_BOOKE206)
4373 #define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
4374 #define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206)
4375 #define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4376 #define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4377 #define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4378 #define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4379 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4380 POWERPC_FLAG_BUS_CLK)
4381 #define check_pow_e500v1 check_pow_hid0
4382 #define init_proc_e500v1 init_proc_e500v1
4383
4384 /* e500v2 core */
4385 #define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
4386 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
4387 PPC_WRTEE | PPC_RFDI | \
4388 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4389 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4390 PPC_MEM_TLBSYNC | PPC_TLBIVAX)
4391 #define POWERPC_INSNS2_e500v2 (PPC2_BOOKE206)
4392 #define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
4393 #define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206)
4394 #define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4395 #define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4396 #define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4397 #define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4398 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4399 POWERPC_FLAG_BUS_CLK)
4400 #define check_pow_e500v2 check_pow_hid0
4401 #define init_proc_e500v2 init_proc_e500v2
4402
4403 /* e500mc core */
4404 #define POWERPC_INSNS_e500mc (PPC_INSNS_BASE | PPC_ISEL | \
4405 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | \
4406 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4407 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4408 PPC_FLOAT | PPC_FLOAT_FRES | \
4409 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
4410 PPC_FLOAT_STFIWX | PPC_WAIT | \
4411 PPC_MEM_TLBSYNC | PPC_TLBIVAX)
4412 #define POWERPC_INSNS2_e500mc (PPC2_BOOKE206)
4413 #define POWERPC_MSRM_e500mc (0x000000001402FB36ULL)
4414 #define POWERPC_MMU_e500mc (POWERPC_MMU_BOOKE206)
4415 #define POWERPC_EXCP_e500mc (POWERPC_EXCP_BOOKE)
4416 #define POWERPC_INPUT_e500mc (PPC_FLAGS_INPUT_BookE)
4417 /* Fixme: figure out the correct flag for e500mc */
4418 #define POWERPC_BFDM_e500mc (bfd_mach_ppc_e500)
4419 #define POWERPC_FLAG_e500mc (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
4420 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4421 #define check_pow_e500mc check_pow_none
4422 #define init_proc_e500mc init_proc_e500mc
4423
4424 enum fsl_e500_version {
4425 fsl_e500v1,
4426 fsl_e500v2,
4427 fsl_e500mc,
4428 };
4429
4430 static void init_proc_e500 (CPUPPCState *env, int version)
4431 {
4432 uint32_t tlbncfg[2];
4433 #if !defined(CONFIG_USER_ONLY)
4434 int i;
4435 #endif
4436
4437 /* Time base */
4438 gen_tbl(env);
4439 /*
4440 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4441 * complain when accessing them.
4442 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4443 */
4444 gen_spr_BookE(env, 0x0000000F0000FFFFULL);
4445 /* Processor identification */
4446 spr_register(env, SPR_BOOKE_PIR, "PIR",
4447 SPR_NOACCESS, SPR_NOACCESS,
4448 &spr_read_generic, &spr_write_pir,
4449 0x00000000);
4450 /* XXX : not implemented */
4451 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4452 &spr_read_spefscr, &spr_write_spefscr,
4453 &spr_read_spefscr, &spr_write_spefscr,
4454 0x00000000);
4455 /* Memory management */
4456 #if !defined(CONFIG_USER_ONLY)
4457 env->nb_pids = 3;
4458 env->nb_ways = 2;
4459 env->id_tlbs = 0;
4460 switch (version) {
4461 case fsl_e500v1:
4462 /* e500v1 */
4463 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4464 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4465 env->dcache_line_size = 32;
4466 env->icache_line_size = 32;
4467 break;
4468 case fsl_e500v2:
4469 /* e500v2 */
4470 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4471 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4472 env->dcache_line_size = 32;
4473 env->icache_line_size = 32;
4474 break;
4475 case fsl_e500mc:
4476 /* e500mc */
4477 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4478 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4479 env->dcache_line_size = 64;
4480 env->icache_line_size = 64;
4481 break;
4482 default:
4483 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4484 }
4485 #endif
4486 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4487 /* XXX : not implemented */
4488 spr_register(env, SPR_HID0, "HID0",
4489 SPR_NOACCESS, SPR_NOACCESS,
4490 &spr_read_generic, &spr_write_generic,
4491 0x00000000);
4492 /* XXX : not implemented */
4493 spr_register(env, SPR_HID1, "HID1",
4494 SPR_NOACCESS, SPR_NOACCESS,
4495 &spr_read_generic, &spr_write_generic,
4496 0x00000000);
4497 /* XXX : not implemented */
4498 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4499 SPR_NOACCESS, SPR_NOACCESS,
4500 &spr_read_generic, &spr_write_generic,
4501 0x00000000);
4502 /* XXX : not implemented */
4503 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4504 SPR_NOACCESS, SPR_NOACCESS,
4505 &spr_read_generic, &spr_write_generic,
4506 0x00000000);
4507 /* XXX : not implemented */
4508 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4509 SPR_NOACCESS, SPR_NOACCESS,
4510 &spr_read_generic, &spr_write_generic,
4511 0x00000000);
4512 /* XXX : not implemented */
4513 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4514 SPR_NOACCESS, SPR_NOACCESS,
4515 &spr_read_generic, &spr_write_generic,
4516 0x00000000);
4517 /* XXX : not implemented */
4518 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4519 SPR_NOACCESS, SPR_NOACCESS,
4520 &spr_read_generic, &spr_write_generic,
4521 0x00000000);
4522 /* XXX : not implemented */
4523 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4524 SPR_NOACCESS, SPR_NOACCESS,
4525 &spr_read_generic, &spr_write_generic,
4526 0x00000000);
4527 /* XXX : not implemented */
4528 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4529 SPR_NOACCESS, SPR_NOACCESS,
4530 &spr_read_generic, &spr_write_generic,
4531 0x00000000);
4532 /* XXX : not implemented */
4533 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4534 SPR_NOACCESS, SPR_NOACCESS,
4535 &spr_read_generic, &spr_write_e500_l1csr0,
4536 0x00000000);
4537 /* XXX : not implemented */
4538 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4539 SPR_NOACCESS, SPR_NOACCESS,
4540 &spr_read_generic, &spr_write_generic,
4541 0x00000000);
4542 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4543 SPR_NOACCESS, SPR_NOACCESS,
4544 &spr_read_generic, &spr_write_generic,
4545 0x00000000);
4546 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4547 SPR_NOACCESS, SPR_NOACCESS,
4548 &spr_read_generic, &spr_write_generic,
4549 0x00000000);
4550 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4551 SPR_NOACCESS, SPR_NOACCESS,
4552 &spr_read_generic, &spr_write_booke206_mmucsr0,
4553 0x00000000);
4554
4555 #if !defined(CONFIG_USER_ONLY)
4556 env->nb_tlb = 0;
4557 env->tlb_type = TLB_MAS;
4558 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4559 env->nb_tlb += booke206_tlb_size(env, i);
4560 }
4561 #endif
4562
4563 init_excp_e200(env);
4564 /* Allocate hardware IRQ controller */
4565 ppce500_irq_init(env);
4566 }
4567
4568 static void init_proc_e500v1(CPUPPCState *env)
4569 {
4570 init_proc_e500(env, fsl_e500v1);
4571 }
4572
4573 static void init_proc_e500v2(CPUPPCState *env)
4574 {
4575 init_proc_e500(env, fsl_e500v2);
4576 }
4577
4578 static void init_proc_e500mc(CPUPPCState *env)
4579 {
4580 init_proc_e500(env, fsl_e500mc);
4581 }
4582
4583 /* Non-embedded PowerPC */
4584
4585 /* POWER : same as 601, without mfmsr, mfsr */
4586 #if defined(TODO)
4587 #define POWERPC_INSNS_POWER (XXX_TODO)
4588 /* POWER RSC (from RAD6000) */
4589 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4590 #endif /* TODO */
4591
4592 /* PowerPC 601 */
4593 #define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4594 PPC_FLOAT | \
4595 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4596 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4597 PPC_SEGMENT | PPC_EXTERN)
4598 #define POWERPC_INSNS2_601 (PPC_NONE)
4599 #define POWERPC_MSRM_601 (0x000000000000FD70ULL)
4600 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4601 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
4602 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4603 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
4604 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4605 #define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4606 #define check_pow_601 check_pow_none
4607
4608 static void init_proc_601 (CPUPPCState *env)
4609 {
4610 gen_spr_ne_601(env);
4611 gen_spr_601(env);
4612 /* Hardware implementation registers */
4613 /* XXX : not implemented */
4614 spr_register(env, SPR_HID0, "HID0",
4615 SPR_NOACCESS, SPR_NOACCESS,
4616 &spr_read_generic, &spr_write_hid0_601,
4617 0x80010080);
4618 /* XXX : not implemented */
4619 spr_register(env, SPR_HID1, "HID1",
4620 SPR_NOACCESS, SPR_NOACCESS,
4621 &spr_read_generic, &spr_write_generic,
4622 0x00000000);
4623 /* XXX : not implemented */
4624 spr_register(env, SPR_601_HID2, "HID2",
4625 SPR_NOACCESS, SPR_NOACCESS,
4626 &spr_read_generic, &spr_write_generic,
4627 0x00000000);
4628 /* XXX : not implemented */
4629 spr_register(env, SPR_601_HID5, "HID5",
4630 SPR_NOACCESS, SPR_NOACCESS,
4631 &spr_read_generic, &spr_write_generic,
4632 0x00000000);
4633 /* Memory management */
4634 init_excp_601(env);
4635 /* XXX: beware that dcache line size is 64
4636 * but dcbz uses 32 bytes "sectors"
4637 * XXX: this breaks clcs instruction !
4638 */
4639 env->dcache_line_size = 32;
4640 env->icache_line_size = 64;
4641 /* Allocate hardware IRQ controller */
4642 ppc6xx_irq_init(env);
4643 }
4644
4645 /* PowerPC 601v */
4646 #define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4647 PPC_FLOAT | \
4648 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4649 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4650 PPC_SEGMENT | PPC_EXTERN)
4651 #define POWERPC_INSNS2_601v (PPC_NONE)
4652 #define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4653 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4654 #define POWERPC_MMU_601v (POWERPC_MMU_601)
4655 #define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4656 #define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4657 #define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4658 #define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4659 #define check_pow_601v check_pow_none
4660
4661 static void init_proc_601v (CPUPPCState *env)
4662 {
4663 init_proc_601(env);
4664 /* XXX : not implemented */
4665 spr_register(env, SPR_601_HID15, "HID15",
4666 SPR_NOACCESS, SPR_NOACCESS,
4667 &spr_read_generic, &spr_write_generic,
4668 0x00000000);
4669 }
4670
4671 /* PowerPC 602 */
4672 #define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4673 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4674 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4675 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4676 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4677 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4678 PPC_SEGMENT | PPC_602_SPEC)
4679 #define POWERPC_INSNS2_602 (PPC_NONE)
4680 #define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4681 /* XXX: 602 MMU is quite specific. Should add a special case */
4682 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4683 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4684 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
4685 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
4686 #define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4687 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4688 #define check_pow_602 check_pow_hid0
4689
4690 static void init_proc_602 (CPUPPCState *env)
4691 {
4692 gen_spr_ne_601(env);
4693 gen_spr_602(env);
4694 /* Time base */
4695 gen_tbl(env);
4696 /* hardware implementation registers */
4697 /* XXX : not implemented */
4698 spr_register(env, SPR_HID0, "HID0",
4699 SPR_NOACCESS, SPR_NOACCESS,
4700 &spr_read_generic, &spr_write_generic,
4701 0x00000000);
4702 /* XXX : not implemented */
4703 spr_register(env, SPR_HID1, "HID1",
4704 SPR_NOACCESS, SPR_NOACCESS,
4705 &spr_read_generic, &spr_write_generic,
4706 0x00000000);
4707 /* Memory management */
4708 gen_low_BATs(env);
4709 gen_6xx_7xx_soft_tlb(env, 64, 2);
4710 init_excp_602(env);
4711 env->dcache_line_size = 32;
4712 env->icache_line_size = 32;
4713 /* Allocate hardware IRQ controller */
4714 ppc6xx_irq_init(env);
4715 }
4716
4717 /* PowerPC 603 */
4718 #define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4719 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4720 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4721 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4722 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4723 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4724 PPC_SEGMENT | PPC_EXTERN)
4725 #define POWERPC_INSNS2_603 (PPC_NONE)
4726 #define POWERPC_MSRM_603 (0x000000000007FF73ULL)
4727 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4728 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4729 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
4730 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
4731 #define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4732 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4733 #define check_pow_603 check_pow_hid0
4734
4735 static void init_proc_603 (CPUPPCState *env)
4736 {
4737 gen_spr_ne_601(env);
4738 gen_spr_603(env);
4739 /* Time base */
4740 gen_tbl(env);
4741 /* hardware implementation registers */
4742 /* XXX : not implemented */
4743 spr_register(env, SPR_HID0, "HID0",
4744 SPR_NOACCESS, SPR_NOACCESS,
4745 &spr_read_generic, &spr_write_generic,
4746 0x00000000);
4747 /* XXX : not implemented */
4748 spr_register(env, SPR_HID1, "HID1",
4749 SPR_NOACCESS, SPR_NOACCESS,
4750 &spr_read_generic, &spr_write_generic,
4751 0x00000000);
4752 /* Memory management */
4753 gen_low_BATs(env);
4754 gen_6xx_7xx_soft_tlb(env, 64, 2);
4755 init_excp_603(env);
4756 env->dcache_line_size = 32;
4757 env->icache_line_size = 32;
4758 /* Allocate hardware IRQ controller */
4759 ppc6xx_irq_init(env);
4760 }
4761
4762 /* PowerPC 603e */
4763 #define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4764 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4765 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4766 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4767 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4768 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4769 PPC_SEGMENT | PPC_EXTERN)
4770 #define POWERPC_INSNS2_603E (PPC_NONE)
4771 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4772 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4773 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4774 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
4775 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
4776 #define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4777 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4778 #define check_pow_603E check_pow_hid0
4779
4780 static void init_proc_603E (CPUPPCState *env)
4781 {
4782 gen_spr_ne_601(env);
4783 gen_spr_603(env);
4784 /* Time base */
4785 gen_tbl(env);
4786 /* hardware implementation registers */
4787 /* XXX : not implemented */
4788 spr_register(env, SPR_HID0, "HID0",
4789 SPR_NOACCESS, SPR_NOACCESS,
4790 &spr_read_generic, &spr_write_generic,
4791 0x00000000);
4792 /* XXX : not implemented */
4793 spr_register(env, SPR_HID1, "HID1",
4794 SPR_NOACCESS, SPR_NOACCESS,
4795 &spr_read_generic, &spr_write_generic,
4796 0x00000000);
4797 /* XXX : not implemented */
4798 spr_register(env, SPR_IABR, "IABR",
4799 SPR_NOACCESS, SPR_NOACCESS,
4800 &spr_read_generic, &spr_write_generic,
4801 0x00000000);
4802 /* Memory management */
4803 gen_low_BATs(env);
4804 gen_6xx_7xx_soft_tlb(env, 64, 2);
4805 init_excp_603(env);
4806 env->dcache_line_size = 32;
4807 env->icache_line_size = 32;
4808 /* Allocate hardware IRQ controller */
4809 ppc6xx_irq_init(env);
4810 }
4811
4812 /* PowerPC 604 */
4813 #define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4814 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4815 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4816 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4817 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4818 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4819 PPC_SEGMENT | PPC_EXTERN)
4820 #define POWERPC_INSNS2_604 (PPC_NONE)
4821 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4822 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
4823 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4824 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
4825 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
4826 #define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4827 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4828 #define check_pow_604 check_pow_nocheck
4829
4830 static void init_proc_604 (CPUPPCState *env)
4831 {
4832 gen_spr_ne_601(env);
4833 gen_spr_604(env);
4834 /* Time base */
4835 gen_tbl(env);
4836 /* Hardware implementation registers */
4837 /* XXX : not implemented */
4838 spr_register(env, SPR_HID0, "HID0",
4839 SPR_NOACCESS, SPR_NOACCESS,
4840 &spr_read_generic, &spr_write_generic,
4841 0x00000000);
4842 /* Memory management */
4843 gen_low_BATs(env);
4844 init_excp_604(env);
4845 env->dcache_line_size = 32;
4846 env->icache_line_size = 32;
4847 /* Allocate hardware IRQ controller */
4848 ppc6xx_irq_init(env);
4849 }
4850
4851 /* PowerPC 604E */
4852 #define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4853 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4854 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4855 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4856 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4857 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4858 PPC_SEGMENT | PPC_EXTERN)
4859 #define POWERPC_INSNS2_604E (PPC_NONE)
4860 #define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4861 #define POWERPC_MMU_604E (POWERPC_MMU_32B)
4862 #define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4863 #define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4864 #define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4865 #define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4866 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4867 #define check_pow_604E check_pow_nocheck
4868
4869 static void init_proc_604E (CPUPPCState *env)
4870 {
4871 gen_spr_ne_601(env);
4872 gen_spr_604(env);
4873 /* XXX : not implemented */
4874 spr_register(env, SPR_MMCR1, "MMCR1",
4875 SPR_NOACCESS, SPR_NOACCESS,
4876 &spr_read_generic, &spr_write_generic,
4877 0x00000000);
4878 /* XXX : not implemented */
4879 spr_register(env, SPR_PMC3, "PMC3",
4880 SPR_NOACCESS, SPR_NOACCESS,
4881 &spr_read_generic, &spr_write_generic,
4882 0x00000000);
4883 /* XXX : not implemented */
4884 spr_register(env, SPR_PMC4, "PMC4",
4885 SPR_NOACCESS, SPR_NOACCESS,
4886 &spr_read_generic, &spr_write_generic,
4887 0x00000000);
4888 /* Time base */
4889 gen_tbl(env);
4890 /* Hardware implementation registers */
4891 /* XXX : not implemented */
4892 spr_register(env, SPR_HID0, "HID0",
4893 SPR_NOACCESS, SPR_NOACCESS,
4894 &spr_read_generic, &spr_write_generic,
4895 0x00000000);
4896 /* XXX : not implemented */
4897 spr_register(env, SPR_HID1, "HID1",
4898 SPR_NOACCESS, SPR_NOACCESS,
4899 &spr_read_generic, &spr_write_generic,
4900 0x00000000);
4901 /* Memory management */
4902 gen_low_BATs(env);
4903 init_excp_604(env);
4904 env->dcache_line_size = 32;
4905 env->icache_line_size = 32;
4906 /* Allocate hardware IRQ controller */
4907 ppc6xx_irq_init(env);
4908 }
4909
4910 /* PowerPC 740 */
4911 #define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4912 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4913 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4914 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4915 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4916 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4917 PPC_SEGMENT | PPC_EXTERN)
4918 #define POWERPC_INSNS2_740 (PPC_NONE)
4919 #define POWERPC_MSRM_740 (0x000000000005FF77ULL)
4920 #define POWERPC_MMU_740 (POWERPC_MMU_32B)
4921 #define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
4922 #define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
4923 #define POWERPC_BFDM_740 (bfd_mach_ppc_750)
4924 #define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4925 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4926 #define check_pow_740 check_pow_hid0
4927
4928 static void init_proc_740 (CPUPPCState *env)
4929 {
4930 gen_spr_ne_601(env);
4931 gen_spr_7xx(env);
4932 /* Time base */
4933 gen_tbl(env);
4934 /* Thermal management */
4935 gen_spr_thrm(env);
4936 /* Hardware implementation registers */
4937 /* XXX : not implemented */
4938 spr_register(env, SPR_HID0, "HID0",
4939 SPR_NOACCESS, SPR_NOACCESS,
4940 &spr_read_generic, &spr_write_generic,
4941 0x00000000);
4942 /* XXX : not implemented */
4943 spr_register(env, SPR_HID1, "HID1",
4944 SPR_NOACCESS, SPR_NOACCESS,
4945 &spr_read_generic, &spr_write_generic,
4946 0x00000000);
4947 /* Memory management */
4948 gen_low_BATs(env);
4949 init_excp_7x0(env);
4950 env->dcache_line_size = 32;
4951 env->icache_line_size = 32;
4952 /* Allocate hardware IRQ controller */
4953 ppc6xx_irq_init(env);
4954 }
4955
4956 /* PowerPC 750 */
4957 #define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4958 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4959 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4960 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4961 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4962 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4963 PPC_SEGMENT | PPC_EXTERN)
4964 #define POWERPC_INSNS2_750 (PPC_NONE)
4965 #define POWERPC_MSRM_750 (0x000000000005FF77ULL)
4966 #define POWERPC_MMU_750 (POWERPC_MMU_32B)
4967 #define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
4968 #define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
4969 #define POWERPC_BFDM_750 (bfd_mach_ppc_750)
4970 #define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4971 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4972 #define check_pow_750 check_pow_hid0
4973
4974 static void init_proc_750 (CPUPPCState *env)
4975 {
4976 gen_spr_ne_601(env);
4977 gen_spr_7xx(env);
4978 /* XXX : not implemented */
4979 spr_register(env, SPR_L2CR, "L2CR",
4980 SPR_NOACCESS, SPR_NOACCESS,
4981 &spr_read_generic, &spr_write_generic,
4982 0x00000000);
4983 /* Time base */
4984 gen_tbl(env);
4985 /* Thermal management */
4986 gen_spr_thrm(env);
4987 /* Hardware implementation registers */
4988 /* XXX : not implemented */
4989 spr_register(env, SPR_HID0, "HID0",
4990 SPR_NOACCESS, SPR_NOACCESS,
4991 &spr_read_generic, &spr_write_generic,
4992 0x00000000);
4993 /* XXX : not implemented */
4994 spr_register(env, SPR_HID1, "HID1",
4995 SPR_NOACCESS, SPR_NOACCESS,
4996 &spr_read_generic, &spr_write_generic,
4997 0x00000000);
4998 /* Memory management */
4999 gen_low_BATs(env);
5000 /* XXX: high BATs are also present but are known to be bugged on
5001 * die version 1.x
5002 */
5003 init_excp_7x0(env);
5004 env->dcache_line_size = 32;
5005 env->icache_line_size = 32;
5006 /* Allocate hardware IRQ controller */
5007 ppc6xx_irq_init(env);
5008 }
5009
5010 /* PowerPC 750 CL */
5011 /* XXX: not implemented:
5012 * cache lock instructions:
5013 * dcbz_l
5014 * floating point paired instructions
5015 * psq_lux
5016 * psq_lx
5017 * psq_stux
5018 * psq_stx
5019 * ps_abs
5020 * ps_add
5021 * ps_cmpo0
5022 * ps_cmpo1
5023 * ps_cmpu0
5024 * ps_cmpu1
5025 * ps_div
5026 * ps_madd
5027 * ps_madds0
5028 * ps_madds1
5029 * ps_merge00
5030 * ps_merge01
5031 * ps_merge10
5032 * ps_merge11
5033 * ps_mr
5034 * ps_msub
5035 * ps_mul
5036 * ps_muls0
5037 * ps_muls1
5038 * ps_nabs
5039 * ps_neg
5040 * ps_nmadd
5041 * ps_nmsub
5042 * ps_res
5043 * ps_rsqrte
5044 * ps_sel
5045 * ps_sub
5046 * ps_sum0
5047 * ps_sum1
5048 */
5049 #define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5050 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5051 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5052 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5053 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5054 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5055 PPC_SEGMENT | PPC_EXTERN)
5056 #define POWERPC_INSNS2_750cl (PPC_NONE)
5057 #define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
5058 #define POWERPC_MMU_750cl (POWERPC_MMU_32B)
5059 #define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
5060 #define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
5061 #define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
5062 #define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5063 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5064 #define check_pow_750cl check_pow_hid0
5065
5066 static void init_proc_750cl (CPUPPCState *env)
5067 {
5068 gen_spr_ne_601(env);
5069 gen_spr_7xx(env);
5070 /* XXX : not implemented */
5071 spr_register(env, SPR_L2CR, "L2CR",
5072 SPR_NOACCESS, SPR_NOACCESS,
5073 &spr_read_generic, &spr_write_generic,
5074 0x00000000);
5075 /* Time base */
5076 gen_tbl(env);
5077 /* Thermal management */
5078 /* Those registers are fake on 750CL */
5079 spr_register(env, SPR_THRM1, "THRM1",
5080 SPR_NOACCESS, SPR_NOACCESS,
5081 &spr_read_generic, &spr_write_generic,
5082 0x00000000);
5083 spr_register(env, SPR_THRM2, "THRM2",
5084 SPR_NOACCESS, SPR_NOACCESS,
5085 &spr_read_generic, &spr_write_generic,
5086 0x00000000);
5087 spr_register(env, SPR_THRM3, "THRM3",
5088 SPR_NOACCESS, SPR_NOACCESS,
5089 &spr_read_generic, &spr_write_generic,
5090 0x00000000);
5091 /* XXX: not implemented */
5092 spr_register(env, SPR_750_TDCL, "TDCL",
5093 SPR_NOACCESS, SPR_NOACCESS,
5094 &spr_read_generic, &spr_write_generic,
5095 0x00000000);
5096 spr_register(env, SPR_750_TDCH, "TDCH",
5097 SPR_NOACCESS, SPR_NOACCESS,
5098 &spr_read_generic, &spr_write_generic,
5099 0x00000000);
5100 /* DMA */
5101 /* XXX : not implemented */
5102 spr_register(env, SPR_750_WPAR, "WPAR",
5103 SPR_NOACCESS, SPR_NOACCESS,
5104 &spr_read_generic, &spr_write_generic,
5105 0x00000000);
5106 spr_register(env, SPR_750_DMAL, "DMAL",
5107 SPR_NOACCESS, SPR_NOACCESS,
5108 &spr_read_generic, &spr_write_generic,
5109 0x00000000);
5110 spr_register(env, SPR_750_DMAU, "DMAU",
5111 SPR_NOACCESS, SPR_NOACCESS,
5112 &spr_read_generic, &spr_write_generic,
5113 0x00000000);
5114 /* Hardware implementation registers */
5115 /* XXX : not implemented */
5116 spr_register(env, SPR_HID0, "HID0",
5117 SPR_NOACCESS, SPR_NOACCESS,
5118 &spr_read_generic, &spr_write_generic,
5119 0x00000000);
5120 /* XXX : not implemented */
5121 spr_register(env, SPR_HID1, "HID1",
5122 SPR_NOACCESS, SPR_NOACCESS,
5123 &spr_read_generic, &spr_write_generic,
5124 0x00000000);
5125 /* XXX : not implemented */
5126 spr_register(env, SPR_750CL_HID2, "HID2",
5127 SPR_NOACCESS, SPR_NOACCESS,
5128 &spr_read_generic, &spr_write_generic,
5129 0x00000000);
5130 /* XXX : not implemented */
5131 spr_register(env, SPR_750CL_HID4, "HID4",
5132 SPR_NOACCESS, SPR_NOACCESS,
5133 &spr_read_generic, &spr_write_generic,
5134 0x00000000);
5135 /* Quantization registers */
5136 /* XXX : not implemented */
5137 spr_register(env, SPR_750_GQR0, "GQR0",
5138 SPR_NOACCESS, SPR_NOACCESS,
5139 &spr_read_generic, &spr_write_generic,
5140 0x00000000);
5141 /* XXX : not implemented */
5142 spr_register(env, SPR_750_GQR1, "GQR1",
5143 SPR_NOACCESS, SPR_NOACCESS,
5144 &spr_read_generic, &spr_write_generic,
5145 0x00000000);
5146 /* XXX : not implemented */
5147 spr_register(env, SPR_750_GQR2, "GQR2",
5148 SPR_NOACCESS, SPR_NOACCESS,
5149 &spr_read_generic, &spr_write_generic,
5150 0x00000000);
5151 /* XXX : not implemented */
5152 spr_register(env, SPR_750_GQR3, "GQR3",
5153 SPR_NOACCESS, SPR_NOACCESS,
5154 &spr_read_generic, &spr_write_generic,
5155 0x00000000);
5156 /* XXX : not implemented */
5157 spr_register(env, SPR_750_GQR4, "GQR4",
5158 SPR_NOACCESS, SPR_NOACCESS,
5159 &spr_read_generic, &spr_write_generic,
5160 0x00000000);
5161 /* XXX : not implemented */
5162 spr_register(env, SPR_750_GQR5, "GQR5",
5163 SPR_NOACCESS, SPR_NOACCESS,
5164 &spr_read_generic, &spr_write_generic,
5165 0x00000000);
5166 /* XXX : not implemented */
5167 spr_register(env, SPR_750_GQR6, "GQR6",
5168 SPR_NOACCESS, SPR_NOACCESS,
5169 &spr_read_generic, &spr_write_generic,
5170 0x00000000);
5171 /* XXX : not implemented */
5172 spr_register(env, SPR_750_GQR7, "GQR7",
5173 SPR_NOACCESS, SPR_NOACCESS,
5174 &spr_read_generic, &spr_write_generic,
5175 0x00000000);
5176 /* Memory management */
5177 gen_low_BATs(env);
5178 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5179 gen_high_BATs(env);
5180 init_excp_750cl(env);
5181 env->dcache_line_size = 32;
5182 env->icache_line_size = 32;
5183 /* Allocate hardware IRQ controller */
5184 ppc6xx_irq_init(env);
5185 }
5186
5187 /* PowerPC 750CX */
5188 #define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5189 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5190 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5191 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5192 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5193 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5194 PPC_SEGMENT | PPC_EXTERN)
5195 #define POWERPC_INSNS2_750cx (PPC_NONE)
5196 #define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
5197 #define POWERPC_MMU_750cx (POWERPC_MMU_32B)
5198 #define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
5199 #define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
5200 #define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
5201 #define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5202 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5203 #define check_pow_750cx check_pow_hid0
5204
5205 static void init_proc_750cx (CPUPPCState *env)
5206 {
5207 gen_spr_ne_601(env);
5208 gen_spr_7xx(env);
5209 /* XXX : not implemented */
5210 spr_register(env, SPR_L2CR, "L2CR",
5211 SPR_NOACCESS, SPR_NOACCESS,
5212 &spr_read_generic, &spr_write_generic,
5213 0x00000000);
5214 /* Time base */
5215 gen_tbl(env);
5216 /* Thermal management */
5217 gen_spr_thrm(env);
5218 /* This register is not implemented but is present for compatibility */
5219 spr_register(env, SPR_SDA, "SDA",
5220 SPR_NOACCESS, SPR_NOACCESS,
5221 &spr_read_generic, &spr_write_generic,
5222 0x00000000);
5223 /* Hardware implementation registers */
5224 /* XXX : not implemented */
5225 spr_register(env, SPR_HID0, "HID0",
5226 SPR_NOACCESS, SPR_NOACCESS,
5227 &spr_read_generic, &spr_write_generic,
5228 0x00000000);
5229 /* XXX : not implemented */
5230 spr_register(env, SPR_HID1, "HID1",
5231 SPR_NOACCESS, SPR_NOACCESS,
5232 &spr_read_generic, &spr_write_generic,
5233 0x00000000);
5234 /* Memory management */
5235 gen_low_BATs(env);
5236 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5237 gen_high_BATs(env);
5238 init_excp_750cx(env);
5239 env->dcache_line_size = 32;
5240 env->icache_line_size = 32;
5241 /* Allocate hardware IRQ controller */
5242 ppc6xx_irq_init(env);
5243 }
5244
5245 /* PowerPC 750FX */
5246 #define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5247 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5248 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5249 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5250 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5251 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5252 PPC_SEGMENT | PPC_EXTERN)
5253 #define POWERPC_INSNS2_750fx (PPC_NONE)
5254 #define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
5255 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
5256 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
5257 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
5258 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
5259 #define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5260 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5261 #define check_pow_750fx check_pow_hid0
5262
5263 static void init_proc_750fx (CPUPPCState *env)
5264 {
5265 gen_spr_ne_601(env);
5266 gen_spr_7xx(env);
5267 /* XXX : not implemented */
5268 spr_register(env, SPR_L2CR, "L2CR",
5269 SPR_NOACCESS, SPR_NOACCESS,
5270 &spr_read_generic, &spr_write_generic,
5271 0x00000000);
5272 /* Time base */
5273 gen_tbl(env);
5274 /* Thermal management */
5275 gen_spr_thrm(env);
5276 /* XXX : not implemented */
5277 spr_register(env, SPR_750_THRM4, "THRM4",
5278 SPR_NOACCESS, SPR_NOACCESS,
5279 &spr_read_generic, &spr_write_generic,
5280 0x00000000);
5281 /* Hardware implementation registers */
5282 /* XXX : not implemented */
5283 spr_register(env, SPR_HID0, "HID0",
5284 SPR_NOACCESS, SPR_NOACCESS,
5285 &spr_read_generic, &spr_write_generic,
5286 0x00000000);
5287 /* XXX : not implemented */
5288 spr_register(env, SPR_HID1, "HID1",
5289 SPR_NOACCESS, SPR_NOACCESS,
5290 &spr_read_generic, &spr_write_generic,
5291 0x00000000);
5292 /* XXX : not implemented */
5293 spr_register(env, SPR_750FX_HID2, "HID2",
5294 SPR_NOACCESS, SPR_NOACCESS,
5295 &spr_read_generic, &spr_write_generic,
5296 0x00000000);
5297 /* Memory management */
5298 gen_low_BATs(env);
5299 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5300 gen_high_BATs(env);
5301 init_excp_7x0(env);
5302 env->dcache_line_size = 32;
5303 env->icache_line_size = 32;
5304 /* Allocate hardware IRQ controller */
5305 ppc6xx_irq_init(env);
5306 }
5307
5308 /* PowerPC 750GX */
5309 #define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5310 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5311 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5312 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5313 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5314 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5315 PPC_SEGMENT | PPC_EXTERN)
5316 #define POWERPC_INSNS2_750gx (PPC_NONE)
5317 #define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5318 #define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5319 #define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5320 #define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5321 #define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5322 #define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5323 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5324 #define check_pow_750gx check_pow_hid0
5325
5326 static void init_proc_750gx (CPUPPCState *env)
5327 {
5328 gen_spr_ne_601(env);
5329 gen_spr_7xx(env);
5330 /* XXX : not implemented (XXX: different from 750fx) */
5331 spr_register(env, SPR_L2CR, "L2CR",
5332 SPR_NOACCESS, SPR_NOACCESS,
5333 &spr_read_generic, &spr_write_generic,
5334 0x00000000);
5335 /* Time base */
5336 gen_tbl(env);
5337 /* Thermal management */
5338 gen_spr_thrm(env);
5339 /* XXX : not implemented */
5340 spr_register(env, SPR_750_THRM4, "THRM4",
5341 SPR_NOACCESS, SPR_NOACCESS,
5342 &spr_read_generic, &spr_write_generic,
5343 0x00000000);
5344 /* Hardware implementation registers */
5345 /* XXX : not implemented (XXX: different from 750fx) */
5346 spr_register(env, SPR_HID0, "HID0",
5347 SPR_NOACCESS, SPR_NOACCESS,
5348 &spr_read_generic, &spr_write_generic,
5349 0x00000000);
5350 /* XXX : not implemented */
5351 spr_register(env, SPR_HID1, "HID1",
5352 SPR_NOACCESS, SPR_NOACCESS,
5353 &spr_read_generic, &spr_write_generic,
5354 0x00000000);
5355 /* XXX : not implemented (XXX: different from 750fx) */
5356 spr_register(env, SPR_750FX_HID2, "HID2",
5357 SPR_NOACCESS, SPR_NOACCESS,
5358 &spr_read_generic, &spr_write_generic,
5359 0x00000000);
5360 /* Memory management */
5361 gen_low_BATs(env);
5362 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5363 gen_high_BATs(env);
5364 init_excp_7x0(env);
5365 env->dcache_line_size = 32;
5366 env->icache_line_size = 32;
5367 /* Allocate hardware IRQ controller */
5368 ppc6xx_irq_init(env);
5369 }
5370
5371 /* PowerPC 745 */
5372 #define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5373 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5374 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5375 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5376 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5377 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5378 PPC_SEGMENT | PPC_EXTERN)
5379 #define POWERPC_INSNS2_745 (PPC_NONE)
5380 #define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5381 #define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5382 #define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5383 #define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5384 #define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5385 #define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5386 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5387 #define check_pow_745 check_pow_hid0
5388
5389 static void init_proc_745 (CPUPPCState *env)
5390 {
5391 gen_spr_ne_601(env);
5392 gen_spr_7xx(env);
5393 gen_spr_G2_755(env);
5394 /* Time base */
5395 gen_tbl(env);
5396 /* Thermal management */
5397 gen_spr_thrm(env);
5398 /* Hardware implementation registers */
5399 /* XXX : not implemented */
5400 spr_register(env, SPR_HID0, "HID0",
5401 SPR_NOACCESS, SPR_NOACCESS,
5402 &spr_read_generic, &spr_write_generic,
5403 0x00000000);
5404 /* XXX : not implemented */
5405 spr_register(env, SPR_HID1, "HID1",
5406 SPR_NOACCESS, SPR_NOACCESS,
5407 &spr_read_generic, &spr_write_generic,
5408 0x00000000);
5409 /* XXX : not implemented */
5410 spr_register(env, SPR_HID2, "HID2",
5411 SPR_NOACCESS, SPR_NOACCESS,
5412 &spr_read_generic, &spr_write_generic,
5413 0x00000000);
5414 /* Memory management */
5415 gen_low_BATs(env);
5416 gen_high_BATs(env);
5417 gen_6xx_7xx_soft_tlb(env, 64, 2);
5418 init_excp_7x5(env);
5419 env->dcache_line_size = 32;
5420 env->icache_line_size = 32;
5421 /* Allocate hardware IRQ controller */
5422 ppc6xx_irq_init(env);
5423 }
5424
5425 /* PowerPC 755 */
5426 #define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5427 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5428 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5429 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5430 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5431 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5432 PPC_SEGMENT | PPC_EXTERN)
5433 #define POWERPC_INSNS2_755 (PPC_NONE)
5434 #define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5435 #define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5436 #define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5437 #define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5438 #define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5439 #define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5440 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5441 #define check_pow_755 check_pow_hid0
5442
5443 static void init_proc_755 (CPUPPCState *env)
5444 {
5445 gen_spr_ne_601(env);
5446 gen_spr_7xx(env);
5447 gen_spr_G2_755(env);
5448 /* Time base */
5449 gen_tbl(env);
5450 /* L2 cache control */
5451 /* XXX : not implemented */
5452 spr_register(env, SPR_L2CR, "L2CR",
5453 SPR_NOACCESS, SPR_NOACCESS,
5454 &spr_read_generic, &spr_write_generic,
5455 0x00000000);
5456 /* XXX : not implemented */
5457 spr_register(env, SPR_L2PMCR, "L2PMCR",
5458 SPR_NOACCESS, SPR_NOACCESS,
5459 &spr_read_generic, &spr_write_generic,
5460 0x00000000);
5461 /* Thermal management */
5462 gen_spr_thrm(env);
5463 /* Hardware implementation registers */
5464 /* XXX : not implemented */
5465 spr_register(env, SPR_HID0, "HID0",
5466 SPR_NOACCESS, SPR_NOACCESS,
5467 &spr_read_generic, &spr_write_generic,
5468 0x00000000);
5469 /* XXX : not implemented */
5470 spr_register(env, SPR_HID1, "HID1",
5471 SPR_NOACCESS, SPR_NOACCESS,
5472 &spr_read_generic, &spr_write_generic,
5473 0x00000000);
5474 /* XXX : not implemented */
5475 spr_register(env, SPR_HID2, "HID2",
5476 SPR_NOACCESS, SPR_NOACCESS,
5477 &spr_read_generic, &spr_write_generic,
5478 0x00000000);
5479 /* Memory management */
5480 gen_low_BATs(env);
5481 gen_high_BATs(env);
5482 gen_6xx_7xx_soft_tlb(env, 64, 2);
5483 init_excp_7x5(env);
5484 env->dcache_line_size = 32;
5485 env->icache_line_size = 32;
5486 /* Allocate hardware IRQ controller */
5487 ppc6xx_irq_init(env);
5488 }
5489
5490 /* PowerPC 7400 (aka G4) */
5491 #define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5492 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5493 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5494 PPC_FLOAT_STFIWX | \
5495 PPC_CACHE | PPC_CACHE_ICBI | \
5496 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5497 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5498 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5499 PPC_MEM_TLBIA | \
5500 PPC_SEGMENT | PPC_EXTERN | \
5501 PPC_ALTIVEC)
5502 #define POWERPC_INSNS2_7400 (PPC_NONE)
5503 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5504 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5505 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5506 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
5507 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
5508 #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5509 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5510 POWERPC_FLAG_BUS_CLK)
5511 #define check_pow_7400 check_pow_hid0
5512
5513 static void init_proc_7400 (CPUPPCState *env)
5514 {
5515 gen_spr_ne_601(env);
5516 gen_spr_7xx(env);
5517 /* Time base */
5518 gen_tbl(env);
5519 /* 74xx specific SPR */
5520 gen_spr_74xx(env);
5521 /* XXX : not implemented */
5522 spr_register(env, SPR_UBAMR, "UBAMR",
5523 &spr_read_ureg, SPR_NOACCESS,
5524 &spr_read_ureg, SPR_NOACCESS,
5525 0x00000000);
5526 /* XXX: this seems not implemented on all revisions. */
5527 /* XXX : not implemented */
5528 spr_register(env, SPR_MSSCR1, "MSSCR1",
5529 SPR_NOACCESS, SPR_NOACCESS,
5530 &spr_read_generic, &spr_write_generic,
5531 0x00000000);
5532 /* Thermal management */
5533 gen_spr_thrm(env);
5534 /* Memory management */
5535 gen_low_BATs(env);
5536 init_excp_7400(env);
5537 env->dcache_line_size = 32;
5538 env->icache_line_size = 32;
5539 /* Allocate hardware IRQ controller */
5540 ppc6xx_irq_init(env);
5541 }
5542
5543 /* PowerPC 7410 (aka G4) */
5544 #define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5545 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5546 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5547 PPC_FLOAT_STFIWX | \
5548 PPC_CACHE | PPC_CACHE_ICBI | \
5549 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5550 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5551 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5552 PPC_MEM_TLBIA | \
5553 PPC_SEGMENT | PPC_EXTERN | \
5554 PPC_ALTIVEC)
5555 #define POWERPC_INSNS2_7410 (PPC_NONE)
5556 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5557 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5558 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5559 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
5560 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
5561 #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5562 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5563 POWERPC_FLAG_BUS_CLK)
5564 #define check_pow_7410 check_pow_hid0
5565
5566 static void init_proc_7410 (CPUPPCState *env)
5567 {
5568 gen_spr_ne_601(env);
5569 gen_spr_7xx(env);
5570 /* Time base */
5571 gen_tbl(env);
5572 /* 74xx specific SPR */
5573 gen_spr_74xx(env);
5574 /* XXX : not implemented */
5575 spr_register(env, SPR_UBAMR, "UBAMR",
5576 &spr_read_ureg, SPR_NOACCESS,
5577 &spr_read_ureg, SPR_NOACCESS,
5578 0x00000000);
5579 /* Thermal management */
5580 gen_spr_thrm(env);
5581 /* L2PMCR */
5582 /* XXX : not implemented */
5583 spr_register(env, SPR_L2PMCR, "L2PMCR",
5584 SPR_NOACCESS, SPR_NOACCESS,
5585 &spr_read_generic, &spr_write_generic,
5586 0x00000000);
5587 /* LDSTDB */
5588 /* XXX : not implemented */
5589 spr_register(env, SPR_LDSTDB, "LDSTDB",
5590 SPR_NOACCESS, SPR_NOACCESS,
5591 &spr_read_generic, &spr_write_generic,
5592 0x00000000);
5593 /* Memory management */
5594 gen_low_BATs(env);
5595 init_excp_7400(env);
5596 env->dcache_line_size = 32;
5597 env->icache_line_size = 32;
5598 /* Allocate hardware IRQ controller */
5599 ppc6xx_irq_init(env);
5600 }
5601
5602 /* PowerPC 7440 (aka G4) */
5603 #define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5604 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5605 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5606 PPC_FLOAT_STFIWX | \
5607 PPC_CACHE | PPC_CACHE_ICBI | \
5608 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5609 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5610 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5611 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5612 PPC_SEGMENT | PPC_EXTERN | \
5613 PPC_ALTIVEC)
5614 #define POWERPC_INSNS2_7440 (PPC_NONE)
5615 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5616 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5617 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5618 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
5619 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
5620 #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5621 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5622 POWERPC_FLAG_BUS_CLK)
5623 #define check_pow_7440 check_pow_hid0_74xx
5624
5625 __attribute__ (( unused ))
5626 static void init_proc_7440 (CPUPPCState *env)
5627 {
5628 gen_spr_ne_601(env);
5629 gen_spr_7xx(env);
5630 /* Time base */
5631 gen_tbl(env);
5632 /* 74xx specific SPR */
5633 gen_spr_74xx(env);
5634 /* XXX : not implemented */
5635 spr_register(env, SPR_UBAMR, "UBAMR",
5636 &spr_read_ureg, SPR_NOACCESS,
5637 &spr_read_ureg, SPR_NOACCESS,
5638 0x00000000);
5639 /* LDSTCR */
5640 /* XXX : not implemented */
5641 spr_register(env, SPR_LDSTCR, "LDSTCR",
5642 SPR_NOACCESS, SPR_NOACCESS,
5643 &spr_read_generic, &spr_write_generic,
5644 0x00000000);
5645 /* ICTRL */
5646 /* XXX : not implemented */
5647 spr_register(env, SPR_ICTRL, "ICTRL",
5648 SPR_NOACCESS, SPR_NOACCESS,
5649 &spr_read_generic, &spr_write_generic,
5650 0x00000000);
5651 /* MSSSR0 */
5652 /* XXX : not implemented */
5653 spr_register(env, SPR_MSSSR0, "MSSSR0",
5654 SPR_NOACCESS, SPR_NOACCESS,
5655 &spr_read_generic, &spr_write_generic,
5656 0x00000000);
5657 /* PMC */
5658 /* XXX : not implemented */
5659 spr_register(env, SPR_PMC5, "PMC5",
5660 SPR_NOACCESS, SPR_NOACCESS,
5661 &spr_read_generic, &spr_write_generic,
5662 0x00000000);
5663 /* XXX : not implemented */
5664 spr_register(env, SPR_UPMC5, "UPMC5",
5665 &spr_read_ureg, SPR_NOACCESS,
5666 &spr_read_ureg, SPR_NOACCESS,
5667 0x00000000);
5668 /* XXX : not implemented */
5669 spr_register(env, SPR_PMC6, "PMC6",
5670 SPR_NOACCESS, SPR_NOACCESS,
5671 &spr_read_generic, &spr_write_generic,
5672 0x00000000);
5673 /* XXX : not implemented */
5674 spr_register(env, SPR_UPMC6, "UPMC6",
5675 &spr_read_ureg, SPR_NOACCESS,
5676 &spr_read_ureg, SPR_NOACCESS,
5677 0x00000000);
5678 /* Memory management */
5679 gen_low_BATs(env);
5680 gen_74xx_soft_tlb(env, 128, 2);
5681 init_excp_7450(env);
5682 env->dcache_line_size = 32;
5683 env->icache_line_size = 32;
5684 /* Allocate hardware IRQ controller */
5685 ppc6xx_irq_init(env);
5686 }
5687
5688 /* PowerPC 7450 (aka G4) */
5689 #define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5690 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5691 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5692 PPC_FLOAT_STFIWX | \
5693 PPC_CACHE | PPC_CACHE_ICBI | \
5694 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5695 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5696 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5697 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5698 PPC_SEGMENT | PPC_EXTERN | \
5699 PPC_ALTIVEC)
5700 #define POWERPC_INSNS2_7450 (PPC_NONE)
5701 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5702 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5703 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5704 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
5705 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
5706 #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5707 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5708 POWERPC_FLAG_BUS_CLK)
5709 #define check_pow_7450 check_pow_hid0_74xx
5710
5711 __attribute__ (( unused ))
5712 static void init_proc_7450 (CPUPPCState *env)
5713 {
5714 gen_spr_ne_601(env);
5715 gen_spr_7xx(env);
5716 /* Time base */
5717 gen_tbl(env);
5718 /* 74xx specific SPR */
5719 gen_spr_74xx(env);
5720 /* Level 3 cache control */
5721 gen_l3_ctrl(env);
5722 /* L3ITCR1 */
5723 /* XXX : not implemented */
5724 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5725 SPR_NOACCESS, SPR_NOACCESS,
5726 &spr_read_generic, &spr_write_generic,
5727 0x00000000);
5728 /* L3ITCR2 */
5729 /* XXX : not implemented */
5730 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5731 SPR_NOACCESS, SPR_NOACCESS,
5732 &spr_read_generic, &spr_write_generic,
5733 0x00000000);
5734 /* L3ITCR3 */
5735 /* XXX : not implemented */
5736 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5737 SPR_NOACCESS, SPR_NOACCESS,
5738 &spr_read_generic, &spr_write_generic,
5739 0x00000000);
5740 /* L3OHCR */
5741 /* XXX : not implemented */
5742 spr_register(env, SPR_L3OHCR, "L3OHCR",
5743 SPR_NOACCESS, SPR_NOACCESS,
5744 &spr_read_generic, &spr_write_generic,
5745 0x00000000);
5746 /* XXX : not implemented */
5747 spr_register(env, SPR_UBAMR, "UBAMR",
5748 &spr_read_ureg, SPR_NOACCESS,
5749 &spr_read_ureg, SPR_NOACCESS,
5750 0x00000000);
5751 /* LDSTCR */
5752 /* XXX : not implemented */
5753 spr_register(env, SPR_LDSTCR, "LDSTCR",
5754 SPR_NOACCESS, SPR_NOACCESS,
5755 &spr_read_generic, &spr_write_generic,
5756 0x00000000);
5757 /* ICTRL */
5758 /* XXX : not implemented */
5759 spr_register(env, SPR_ICTRL, "ICTRL",
5760 SPR_NOACCESS, SPR_NOACCESS,
5761 &spr_read_generic, &spr_write_generic,
5762 0x00000000);
5763 /* MSSSR0 */
5764 /* XXX : not implemented */
5765 spr_register(env, SPR_MSSSR0, "MSSSR0",
5766 SPR_NOACCESS, SPR_NOACCESS,
5767 &spr_read_generic, &spr_write_generic,
5768 0x00000000);
5769 /* PMC */
5770 /* XXX : not implemented */
5771 spr_register(env, SPR_PMC5, "PMC5",
5772 SPR_NOACCESS, SPR_NOACCESS,
5773 &spr_read_generic, &spr_write_generic,
5774 0x00000000);
5775 /* XXX : not implemented */
5776 spr_register(env, SPR_UPMC5, "UPMC5",
5777 &spr_read_ureg, SPR_NOACCESS,
5778 &spr_read_ureg, SPR_NOACCESS,
5779 0x00000000);
5780 /* XXX : not implemented */
5781 spr_register(env, SPR_PMC6, "PMC6",
5782 SPR_NOACCESS, SPR_NOACCESS,
5783 &spr_read_generic, &spr_write_generic,
5784 0x00000000);
5785 /* XXX : not implemented */
5786 spr_register(env, SPR_UPMC6, "UPMC6",
5787 &spr_read_ureg, SPR_NOACCESS,
5788 &spr_read_ureg, SPR_NOACCESS,
5789 0x00000000);
5790 /* Memory management */
5791 gen_low_BATs(env);
5792 gen_74xx_soft_tlb(env, 128, 2);
5793 init_excp_7450(env);
5794 env->dcache_line_size = 32;
5795 env->icache_line_size = 32;
5796 /* Allocate hardware IRQ controller */
5797 ppc6xx_irq_init(env);
5798 }
5799
5800 /* PowerPC 7445 (aka G4) */
5801 #define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5802 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5803 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5804 PPC_FLOAT_STFIWX | \
5805 PPC_CACHE | PPC_CACHE_ICBI | \
5806 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5807 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5808 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5809 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5810 PPC_SEGMENT | PPC_EXTERN | \
5811 PPC_ALTIVEC)
5812 #define POWERPC_INSNS2_7445 (PPC_NONE)
5813 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5814 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5815 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5816 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
5817 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
5818 #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5819 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5820 POWERPC_FLAG_BUS_CLK)
5821 #define check_pow_7445 check_pow_hid0_74xx
5822
5823 __attribute__ (( unused ))
5824 static void init_proc_7445 (CPUPPCState *env)
5825 {
5826 gen_spr_ne_601(env);
5827 gen_spr_7xx(env);
5828 /* Time base */
5829 gen_tbl(env);
5830 /* 74xx specific SPR */
5831 gen_spr_74xx(env);
5832 /* LDSTCR */
5833 /* XXX : not implemented */
5834 spr_register(env, SPR_LDSTCR, "LDSTCR",
5835 SPR_NOACCESS, SPR_NOACCESS,
5836 &spr_read_generic, &spr_write_generic,
5837 0x00000000);
5838 /* ICTRL */
5839 /* XXX : not implemented */
5840 spr_register(env, SPR_ICTRL, "ICTRL",
5841 SPR_NOACCESS, SPR_NOACCESS,
5842 &spr_read_generic, &spr_write_generic,
5843 0x00000000);
5844 /* MSSSR0 */
5845 /* XXX : not implemented */
5846 spr_register(env, SPR_MSSSR0, "MSSSR0",
5847 SPR_NOACCESS, SPR_NOACCESS,
5848 &spr_read_generic, &spr_write_generic,
5849 0x00000000);
5850 /* PMC */
5851 /* XXX : not implemented */
5852 spr_register(env, SPR_PMC5, "PMC5",
5853 SPR_NOACCESS, SPR_NOACCESS,
5854 &spr_read_generic, &spr_write_generic,
5855 0x00000000);
5856 /* XXX : not implemented */
5857 spr_register(env, SPR_UPMC5, "UPMC5",
5858 &spr_read_ureg, SPR_NOACCESS,
5859 &spr_read_ureg, SPR_NOACCESS,
5860 0x00000000);
5861 /* XXX : not implemented */
5862 spr_register(env, SPR_PMC6, "PMC6",
5863 SPR_NOACCESS, SPR_NOACCESS,
5864 &spr_read_generic, &spr_write_generic,
5865 0x00000000);
5866 /* XXX : not implemented */
5867 spr_register(env, SPR_UPMC6, "UPMC6",
5868 &spr_read_ureg, SPR_NOACCESS,
5869 &spr_read_ureg, SPR_NOACCESS,
5870 0x00000000);
5871 /* SPRGs */
5872 spr_register(env, SPR_SPRG4, "SPRG4",
5873 SPR_NOACCESS, SPR_NOACCESS,
5874 &spr_read_generic, &spr_write_generic,
5875 0x00000000);
5876 spr_register(env, SPR_USPRG4, "USPRG4",
5877 &spr_read_ureg, SPR_NOACCESS,
5878 &spr_read_ureg, SPR_NOACCESS,
5879 0x00000000);
5880 spr_register(env, SPR_SPRG5, "SPRG5",
5881 SPR_NOACCESS, SPR_NOACCESS,
5882 &spr_read_generic, &spr_write_generic,
5883 0x00000000);
5884 spr_register(env, SPR_USPRG5, "USPRG5",
5885 &spr_read_ureg, SPR_NOACCESS,
5886 &spr_read_ureg, SPR_NOACCESS,
5887 0x00000000);
5888 spr_register(env, SPR_SPRG6, "SPRG6",
5889 SPR_NOACCESS, SPR_NOACCESS,
5890 &spr_read_generic, &spr_write_generic,
5891 0x00000000);
5892 spr_register(env, SPR_USPRG6, "USPRG6",
5893 &spr_read_ureg, SPR_NOACCESS,
5894 &spr_read_ureg, SPR_NOACCESS,
5895 0x00000000);
5896 spr_register(env, SPR_SPRG7, "SPRG7",
5897 SPR_NOACCESS, SPR_NOACCESS,
5898 &spr_read_generic, &spr_write_generic,
5899 0x00000000);
5900 spr_register(env, SPR_USPRG7, "USPRG7",
5901 &spr_read_ureg, SPR_NOACCESS,
5902 &spr_read_ureg, SPR_NOACCESS,
5903 0x00000000);
5904 /* Memory management */
5905 gen_low_BATs(env);
5906 gen_high_BATs(env);
5907 gen_74xx_soft_tlb(env, 128, 2);
5908 init_excp_7450(env);
5909 env->dcache_line_size = 32;
5910 env->icache_line_size = 32;
5911 /* Allocate hardware IRQ controller */
5912 ppc6xx_irq_init(env);
5913 }
5914
5915 /* PowerPC 7455 (aka G4) */
5916 #define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5917 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5918 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5919 PPC_FLOAT_STFIWX | \
5920 PPC_CACHE | PPC_CACHE_ICBI | \
5921 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5922 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5923 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5924 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5925 PPC_SEGMENT | PPC_EXTERN | \
5926 PPC_ALTIVEC)
5927 #define POWERPC_INSNS2_7455 (PPC_NONE)
5928 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
5929 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
5930 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
5931 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
5932 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
5933 #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5934 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5935 POWERPC_FLAG_BUS_CLK)
5936 #define check_pow_7455 check_pow_hid0_74xx
5937
5938 __attribute__ (( unused ))
5939 static void init_proc_7455 (CPUPPCState *env)
5940 {
5941 gen_spr_ne_601(env);
5942 gen_spr_7xx(env);
5943 /* Time base */
5944 gen_tbl(env);
5945 /* 74xx specific SPR */
5946 gen_spr_74xx(env);
5947 /* Level 3 cache control */
5948 gen_l3_ctrl(env);
5949 /* LDSTCR */
5950 /* XXX : not implemented */
5951 spr_register(env, SPR_LDSTCR, "LDSTCR",
5952 SPR_NOACCESS, SPR_NOACCESS,
5953 &spr_read_generic, &spr_write_generic,
5954 0x00000000);
5955 /* ICTRL */
5956 /* XXX : not implemented */
5957 spr_register(env, SPR_ICTRL, "ICTRL",
5958 SPR_NOACCESS, SPR_NOACCESS,
5959 &spr_read_generic, &spr_write_generic,
5960 0x00000000);
5961 /* MSSSR0 */
5962 /* XXX : not implemented */
5963 spr_register(env, SPR_MSSSR0, "MSSSR0",
5964 SPR_NOACCESS, SPR_NOACCESS,
5965 &spr_read_generic, &spr_write_generic,
5966 0x00000000);
5967 /* PMC */
5968 /* XXX : not implemented */
5969 spr_register(env, SPR_PMC5, "PMC5",
5970 SPR_NOACCESS, SPR_NOACCESS,
5971 &spr_read_generic, &spr_write_generic,
5972 0x00000000);
5973 /* XXX : not implemented */
5974 spr_register(env, SPR_UPMC5, "UPMC5",
5975 &spr_read_ureg, SPR_NOACCESS,
5976 &spr_read_ureg, SPR_NOACCESS,
5977 0x00000000);
5978 /* XXX : not implemented */
5979 spr_register(env, SPR_PMC6, "PMC6",
5980 SPR_NOACCESS, SPR_NOACCESS,
5981 &spr_read_generic, &spr_write_generic,
5982 0x00000000);
5983 /* XXX : not implemented */
5984 spr_register(env, SPR_UPMC6, "UPMC6",
5985 &spr_read_ureg, SPR_NOACCESS,
5986 &spr_read_ureg, SPR_NOACCESS,
5987 0x00000000);
5988 /* SPRGs */
5989 spr_register(env, SPR_SPRG4, "SPRG4",
5990 SPR_NOACCESS, SPR_NOACCESS,
5991 &spr_read_generic, &spr_write_generic,
5992 0x00000000);
5993 spr_register(env, SPR_USPRG4, "USPRG4",
5994 &spr_read_ureg, SPR_NOACCESS,
5995 &spr_read_ureg, SPR_NOACCESS,
5996 0x00000000);
5997 spr_register(env, SPR_SPRG5, "SPRG5",
5998 SPR_NOACCESS, SPR_NOACCESS,
5999 &spr_read_generic, &spr_write_generic,
6000 0x00000000);
6001 spr_register(env, SPR_USPRG5, "USPRG5",
6002 &spr_read_ureg, SPR_NOACCESS,
6003 &spr_read_ureg, SPR_NOACCESS,
6004 0x00000000);
6005 spr_register(env, SPR_SPRG6, "SPRG6",
6006 SPR_NOACCESS, SPR_NOACCESS,
6007 &spr_read_generic, &spr_write_generic,
6008 0x00000000);
6009 spr_register(env, SPR_USPRG6, "USPRG6",
6010 &spr_read_ureg, SPR_NOACCESS,
6011 &spr_read_ureg, SPR_NOACCESS,
6012 0x00000000);
6013 spr_register(env, SPR_SPRG7, "SPRG7",
6014 SPR_NOACCESS, SPR_NOACCESS,
6015 &spr_read_generic, &spr_write_generic,
6016 0x00000000);
6017 spr_register(env, SPR_USPRG7, "USPRG7",
6018 &spr_read_ureg, SPR_NOACCESS,
6019 &spr_read_ureg, SPR_NOACCESS,
6020 0x00000000);
6021 /* Memory management */
6022 gen_low_BATs(env);
6023 gen_high_BATs(env);
6024 gen_74xx_soft_tlb(env, 128, 2);
6025 init_excp_7450(env);
6026 env->dcache_line_size = 32;
6027 env->icache_line_size = 32;
6028 /* Allocate hardware IRQ controller */
6029 ppc6xx_irq_init(env);
6030 }
6031
6032 /* PowerPC 7457 (aka G4) */
6033 #define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6034 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6035 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6036 PPC_FLOAT_STFIWX | \
6037 PPC_CACHE | PPC_CACHE_ICBI | \
6038 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
6039 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6040 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6041 PPC_MEM_TLBIA | PPC_74xx_TLB | \
6042 PPC_SEGMENT | PPC_EXTERN | \
6043 PPC_ALTIVEC)
6044 #define POWERPC_INSNS2_7457 (PPC_NONE)
6045 #define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
6046 #define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
6047 #define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
6048 #define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
6049 #define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
6050 #define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6051 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6052 POWERPC_FLAG_BUS_CLK)
6053 #define check_pow_7457 check_pow_hid0_74xx
6054
6055 __attribute__ (( unused ))
6056 static void init_proc_7457 (CPUPPCState *env)
6057 {
6058 gen_spr_ne_601(env);
6059 gen_spr_7xx(env);
6060 /* Time base */
6061 gen_tbl(env);
6062 /* 74xx specific SPR */
6063 gen_spr_74xx(env);
6064 /* Level 3 cache control */
6065 gen_l3_ctrl(env);
6066 /* L3ITCR1 */
6067 /* XXX : not implemented */
6068 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6069 SPR_NOACCESS, SPR_NOACCESS,
6070 &spr_read_generic, &spr_write_generic,
6071 0x00000000);
6072 /* L3ITCR2 */
6073 /* XXX : not implemented */
6074 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6075 SPR_NOACCESS, SPR_NOACCESS,
6076 &spr_read_generic, &spr_write_generic,
6077 0x00000000);
6078 /* L3ITCR3 */
6079 /* XXX : not implemented */
6080 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6081 SPR_NOACCESS, SPR_NOACCESS,
6082 &spr_read_generic, &spr_write_generic,
6083 0x00000000);
6084 /* L3OHCR */
6085 /* XXX : not implemented */
6086 spr_register(env, SPR_L3OHCR, "L3OHCR",
6087 SPR_NOACCESS, SPR_NOACCESS,
6088 &spr_read_generic, &spr_write_generic,
6089 0x00000000);
6090 /* LDSTCR */
6091 /* XXX : not implemented */
6092 spr_register(env, SPR_LDSTCR, "LDSTCR",
6093 SPR_NOACCESS, SPR_NOACCESS,
6094 &spr_read_generic, &spr_write_generic,
6095 0x00000000);
6096 /* ICTRL */
6097 /* XXX : not implemented */
6098 spr_register(env, SPR_ICTRL, "ICTRL",
6099 SPR_NOACCESS, SPR_NOACCESS,
6100 &spr_read_generic, &spr_write_generic,
6101 0x00000000);
6102 /* MSSSR0 */
6103 /* XXX : not implemented */
6104 spr_register(env, SPR_MSSSR0, "MSSSR0",
6105 SPR_NOACCESS, SPR_NOACCESS,
6106 &spr_read_generic, &spr_write_generic,
6107 0x00000000);
6108 /* PMC */
6109 /* XXX : not implemented */
6110 spr_register(env, SPR_PMC5, "PMC5",
6111 SPR_NOACCESS, SPR_NOACCESS,
6112 &spr_read_generic, &spr_write_generic,
6113 0x00000000);
6114 /* XXX : not implemented */
6115 spr_register(env, SPR_UPMC5, "UPMC5",
6116 &spr_read_ureg, SPR_NOACCESS,
6117 &spr_read_ureg, SPR_NOACCESS,
6118 0x00000000);
6119 /* XXX : not implemented */
6120 spr_register(env, SPR_PMC6, "PMC6",
6121 SPR_NOACCESS, SPR_NOACCESS,
6122 &spr_read_generic, &spr_write_generic,
6123 0x00000000);
6124 /* XXX : not implemented */
6125 spr_register(env, SPR_UPMC6, "UPMC6",
6126 &spr_read_ureg, SPR_NOACCESS,
6127 &spr_read_ureg, SPR_NOACCESS,
6128 0x00000000);
6129 /* SPRGs */
6130 spr_register(env, SPR_SPRG4, "SPRG4",
6131 SPR_NOACCESS, SPR_NOACCESS,
6132 &spr_read_generic, &spr_write_generic,
6133 0x00000000);
6134 spr_register(env, SPR_USPRG4, "USPRG4",
6135 &spr_read_ureg, SPR_NOACCESS,
6136 &spr_read_ureg, SPR_NOACCESS,
6137 0x00000000);
6138 spr_register(env, SPR_SPRG5, "SPRG5",
6139 SPR_NOACCESS, SPR_NOACCESS,
6140 &spr_read_generic, &spr_write_generic,
6141 0x00000000);
6142 spr_register(env, SPR_USPRG5, "USPRG5",
6143 &spr_read_ureg, SPR_NOACCESS,
6144 &spr_read_ureg, SPR_NOACCESS,
6145 0x00000000);
6146 spr_register(env, SPR_SPRG6, "SPRG6",
6147 SPR_NOACCESS, SPR_NOACCESS,
6148 &spr_read_generic, &spr_write_generic,
6149 0x00000000);
6150 spr_register(env, SPR_USPRG6, "USPRG6",
6151 &spr_read_ureg, SPR_NOACCESS,
6152 &spr_read_ureg, SPR_NOACCESS,
6153 0x00000000);
6154 spr_register(env, SPR_SPRG7, "SPRG7",
6155 SPR_NOACCESS, SPR_NOACCESS,
6156 &spr_read_generic, &spr_write_generic,
6157 0x00000000);
6158 spr_register(env, SPR_USPRG7, "USPRG7",
6159 &spr_read_ureg, SPR_NOACCESS,
6160 &spr_read_ureg, SPR_NOACCESS,
6161 0x00000000);
6162 /* Memory management */
6163 gen_low_BATs(env);
6164 gen_high_BATs(env);
6165 gen_74xx_soft_tlb(env, 128, 2);
6166 init_excp_7450(env);
6167 env->dcache_line_size = 32;
6168 env->icache_line_size = 32;
6169 /* Allocate hardware IRQ controller */
6170 ppc6xx_irq_init(env);
6171 }
6172
6173 #if defined (TARGET_PPC64)
6174 /* PowerPC 970 */
6175 #define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6176 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6177 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6178 PPC_FLOAT_STFIWX | \
6179 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6180 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6181 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6182 PPC_64B | PPC_ALTIVEC | \
6183 PPC_SEGMENT_64B | PPC_SLBI)
6184 #define POWERPC_INSNS2_970 (PPC_NONE)
6185 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
6186 #define POWERPC_MMU_970 (POWERPC_MMU_64B)
6187 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
6188 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
6189 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
6190 #define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6191 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6192 POWERPC_FLAG_BUS_CLK)
6193
6194 #if defined(CONFIG_USER_ONLY)
6195 #define POWERPC970_HID5_INIT 0x00000080
6196 #else
6197 #define POWERPC970_HID5_INIT 0x00000000
6198 #endif
6199
6200 static int check_pow_970 (CPUPPCState *env)
6201 {
6202 if (env->spr[SPR_HID0] & 0x00600000)
6203 return 1;
6204
6205 return 0;
6206 }
6207
6208 static void init_proc_970 (CPUPPCState *env)
6209 {
6210 gen_spr_ne_601(env);
6211 gen_spr_7xx(env);
6212 /* Time base */
6213 gen_tbl(env);
6214 /* Hardware implementation registers */
6215 /* XXX : not implemented */
6216 spr_register(env, SPR_HID0, "HID0",
6217 SPR_NOACCESS, SPR_NOACCESS,
6218 &spr_read_generic, &spr_write_clear,
6219 0x60000000);
6220 /* XXX : not implemented */
6221 spr_register(env, SPR_HID1, "HID1",
6222 SPR_NOACCESS, SPR_NOACCESS,
6223 &spr_read_generic, &spr_write_generic,
6224 0x00000000);
6225 /* XXX : not implemented */
6226 spr_register(env, SPR_750FX_HID2, "HID2",
6227 SPR_NOACCESS, SPR_NOACCESS,
6228 &spr_read_generic, &spr_write_generic,
6229 0x00000000);
6230 /* XXX : not implemented */
6231 spr_register(env, SPR_970_HID5, "HID5",
6232 SPR_NOACCESS, SPR_NOACCESS,
6233 &spr_read_generic, &spr_write_generic,
6234 POWERPC970_HID5_INIT);
6235 /* XXX : not implemented */
6236 spr_register(env, SPR_L2CR, "L2CR",
6237 SPR_NOACCESS, SPR_NOACCESS,
6238 &spr_read_generic, &spr_write_generic,
6239 0x00000000);
6240 /* Memory management */
6241 /* XXX: not correct */
6242 gen_low_BATs(env);
6243 /* XXX : not implemented */
6244 spr_register(env, SPR_MMUCFG, "MMUCFG",
6245 SPR_NOACCESS, SPR_NOACCESS,
6246 &spr_read_generic, SPR_NOACCESS,
6247 0x00000000); /* TOFIX */
6248 /* XXX : not implemented */
6249 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6250 SPR_NOACCESS, SPR_NOACCESS,
6251 &spr_read_generic, &spr_write_generic,
6252 0x00000000); /* TOFIX */
6253 spr_register(env, SPR_HIOR, "SPR_HIOR",
6254 SPR_NOACCESS, SPR_NOACCESS,
6255 &spr_read_hior, &spr_write_hior,
6256 0x00000000);
6257 #if !defined(CONFIG_USER_ONLY)
6258 env->slb_nr = 32;
6259 #endif
6260 init_excp_970(env);
6261 env->dcache_line_size = 128;
6262 env->icache_line_size = 128;
6263 /* Allocate hardware IRQ controller */
6264 ppc970_irq_init(env);
6265 /* Can't find information on what this should be on reset. This
6266 * value is the one used by 74xx processors. */
6267 vscr_init(env, 0x00010000);
6268 }
6269
6270 /* PowerPC 970FX (aka G5) */
6271 #define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6272 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6273 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6274 PPC_FLOAT_STFIWX | \
6275 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6276 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6277 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6278 PPC_64B | PPC_ALTIVEC | \
6279 PPC_SEGMENT_64B | PPC_SLBI)
6280 #define POWERPC_INSNS2_970FX (PPC_NONE)
6281 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
6282 #define POWERPC_MMU_970FX (POWERPC_MMU_64B)
6283 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
6284 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
6285 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
6286 #define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6287 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6288 POWERPC_FLAG_BUS_CLK)
6289
6290 static int check_pow_970FX (CPUPPCState *env)
6291 {
6292 if (env->spr[SPR_HID0] & 0x00600000)
6293 return 1;
6294
6295 return 0;
6296 }
6297
6298 static void init_proc_970FX (CPUPPCState *env)
6299 {
6300 gen_spr_ne_601(env);
6301 gen_spr_7xx(env);
6302 /* Time base */
6303 gen_tbl(env);
6304 /* Hardware implementation registers */
6305 /* XXX : not implemented */
6306 spr_register(env, SPR_HID0, "HID0",
6307 SPR_NOACCESS, SPR_NOACCESS,
6308 &spr_read_generic, &spr_write_clear,
6309 0x60000000);
6310 /* XXX : not implemented */
6311 spr_register(env, SPR_HID1, "HID1",
6312 SPR_NOACCESS, SPR_NOACCESS,
6313 &spr_read_generic, &spr_write_generic,
6314 0x00000000);
6315 /* XXX : not implemented */
6316 spr_register(env, SPR_750FX_HID2, "HID2",
6317 SPR_NOACCESS, SPR_NOACCESS,
6318 &spr_read_generic, &spr_write_generic,
6319 0x00000000);
6320 /* XXX : not implemented */
6321 spr_register(env, SPR_970_HID5, "HID5",
6322 SPR_NOACCESS, SPR_NOACCESS,
6323 &spr_read_generic, &spr_write_generic,
6324 POWERPC970_HID5_INIT);
6325 /* XXX : not implemented */
6326 spr_register(env, SPR_L2CR, "L2CR",
6327 SPR_NOACCESS, SPR_NOACCESS,
6328 &spr_read_generic, &spr_write_generic,
6329 0x00000000);
6330 /* Memory management */
6331 /* XXX: not correct */
6332 gen_low_BATs(env);
6333 /* XXX : not implemented */
6334 spr_register(env, SPR_MMUCFG, "MMUCFG",
6335 SPR_NOACCESS, SPR_NOACCESS,
6336 &spr_read_generic, SPR_NOACCESS,
6337 0x00000000); /* TOFIX */
6338 /* XXX : not implemented */
6339 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6340 SPR_NOACCESS, SPR_NOACCESS,
6341 &spr_read_generic, &spr_write_generic,
6342 0x00000000); /* TOFIX */
6343 spr_register(env, SPR_HIOR, "SPR_HIOR",
6344 SPR_NOACCESS, SPR_NOACCESS,
6345 &spr_read_hior, &spr_write_hior,
6346 0x00000000);
6347 spr_register(env, SPR_CTRL, "SPR_CTRL",
6348 SPR_NOACCESS, SPR_NOACCESS,
6349 &spr_read_generic, &spr_write_generic,
6350 0x00000000);
6351 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6352 SPR_NOACCESS, SPR_NOACCESS,
6353 &spr_read_generic, &spr_write_generic,
6354 0x00000000);
6355 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6356 &spr_read_generic, &spr_write_generic,
6357 &spr_read_generic, &spr_write_generic,
6358 0x00000000);
6359 #if !defined(CONFIG_USER_ONLY)
6360 env->slb_nr = 64;
6361 #endif
6362 init_excp_970(env);
6363 env->dcache_line_size = 128;
6364 env->icache_line_size = 128;
6365 /* Allocate hardware IRQ controller */
6366 ppc970_irq_init(env);
6367 /* Can't find information on what this should be on reset. This
6368 * value is the one used by 74xx processors. */
6369 vscr_init(env, 0x00010000);
6370 }
6371
6372 /* PowerPC 970 GX */
6373 #define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6374 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6375 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6376 PPC_FLOAT_STFIWX | \
6377 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6378 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6379 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6380 PPC_64B | PPC_ALTIVEC | \
6381 PPC_SEGMENT_64B | PPC_SLBI)
6382 #define POWERPC_INSNS2_970GX (PPC_NONE)
6383 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
6384 #define POWERPC_MMU_970GX (POWERPC_MMU_64B)
6385 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6386 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
6387 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
6388 #define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6389 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6390 POWERPC_FLAG_BUS_CLK)
6391
6392 static int check_pow_970GX (CPUPPCState *env)
6393 {
6394 if (env->spr[SPR_HID0] & 0x00600000)
6395 return 1;
6396
6397 return 0;
6398 }
6399
6400 static void init_proc_970GX (CPUPPCState *env)
6401 {
6402 gen_spr_ne_601(env);
6403 gen_spr_7xx(env);
6404 /* Time base */
6405 gen_tbl(env);
6406 /* Hardware implementation registers */
6407 /* XXX : not implemented */
6408 spr_register(env, SPR_HID0, "HID0",
6409 SPR_NOACCESS, SPR_NOACCESS,
6410 &spr_read_generic, &spr_write_clear,
6411 0x60000000);
6412 /* XXX : not implemented */
6413 spr_register(env, SPR_HID1, "HID1",
6414 SPR_NOACCESS, SPR_NOACCESS,
6415 &spr_read_generic, &spr_write_generic,
6416 0x00000000);
6417 /* XXX : not implemented */
6418 spr_register(env, SPR_750FX_HID2, "HID2",
6419 SPR_NOACCESS, SPR_NOACCESS,
6420 &spr_read_generic, &spr_write_generic,
6421 0x00000000);
6422 /* XXX : not implemented */
6423 spr_register(env, SPR_970_HID5, "HID5",
6424 SPR_NOACCESS, SPR_NOACCESS,
6425 &spr_read_generic, &spr_write_generic,
6426 POWERPC970_HID5_INIT);
6427 /* XXX : not implemented */
6428 spr_register(env, SPR_L2CR, "L2CR",
6429 SPR_NOACCESS, SPR_NOACCESS,
6430 &spr_read_generic, &spr_write_generic,
6431 0x00000000);
6432 /* Memory management */
6433 /* XXX: not correct */
6434 gen_low_BATs(env);
6435 /* XXX : not implemented */
6436 spr_register(env, SPR_MMUCFG, "MMUCFG",
6437 SPR_NOACCESS, SPR_NOACCESS,
6438 &spr_read_generic, SPR_NOACCESS,
6439 0x00000000); /* TOFIX */
6440 /* XXX : not implemented */
6441 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6442 SPR_NOACCESS, SPR_NOACCESS,
6443 &spr_read_generic, &spr_write_generic,
6444 0x00000000); /* TOFIX */
6445 spr_register(env, SPR_HIOR, "SPR_HIOR",
6446 SPR_NOACCESS, SPR_NOACCESS,
6447 &spr_read_hior, &spr_write_hior,
6448 0x00000000);
6449 #if !defined(CONFIG_USER_ONLY)
6450 env->slb_nr = 32;
6451 #endif
6452 init_excp_970(env);
6453 env->dcache_line_size = 128;
6454 env->icache_line_size = 128;
6455 /* Allocate hardware IRQ controller */
6456 ppc970_irq_init(env);
6457 /* Can't find information on what this should be on reset. This
6458 * value is the one used by 74xx processors. */
6459 vscr_init(env, 0x00010000);
6460 }
6461
6462 /* PowerPC 970 MP */
6463 #define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6464 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6465 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6466 PPC_FLOAT_STFIWX | \
6467 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6468 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6469 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6470 PPC_64B | PPC_ALTIVEC | \
6471 PPC_SEGMENT_64B | PPC_SLBI)
6472 #define POWERPC_INSNS2_970MP (PPC_NONE)
6473 #define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6474 #define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6475 #define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6476 #define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6477 #define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6478 #define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6479 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6480 POWERPC_FLAG_BUS_CLK)
6481
6482 static int check_pow_970MP (CPUPPCState *env)
6483 {
6484 if (env->spr[SPR_HID0] & 0x01C00000)
6485 return 1;
6486
6487 return 0;
6488 }
6489
6490 static void init_proc_970MP (CPUPPCState *env)
6491 {
6492 gen_spr_ne_601(env);
6493 gen_spr_7xx(env);
6494 /* Time base */
6495 gen_tbl(env);
6496 /* Hardware implementation registers */
6497 /* XXX : not implemented */
6498 spr_register(env, SPR_HID0, "HID0",
6499 SPR_NOACCESS, SPR_NOACCESS,
6500 &spr_read_generic, &spr_write_clear,
6501 0x60000000);
6502 /* XXX : not implemented */
6503 spr_register(env, SPR_HID1, "HID1",
6504 SPR_NOACCESS, SPR_NOACCESS,
6505 &spr_read_generic, &spr_write_generic,
6506 0x00000000);
6507 /* XXX : not implemented */
6508 spr_register(env, SPR_750FX_HID2, "HID2",
6509 SPR_NOACCESS, SPR_NOACCESS,
6510 &spr_read_generic, &spr_write_generic,
6511 0x00000000);
6512 /* XXX : not implemented */
6513 spr_register(env, SPR_970_HID5, "HID5",
6514 SPR_NOACCESS, SPR_NOACCESS,
6515 &spr_read_generic, &spr_write_generic,
6516 POWERPC970_HID5_INIT);
6517 /* XXX : not implemented */
6518 spr_register(env, SPR_L2CR, "L2CR",
6519 SPR_NOACCESS, SPR_NOACCESS,
6520 &spr_read_generic, &spr_write_generic,
6521 0x00000000);
6522 /* Memory management */
6523 /* XXX: not correct */
6524 gen_low_BATs(env);
6525 /* XXX : not implemented */
6526 spr_register(env, SPR_MMUCFG, "MMUCFG",
6527 SPR_NOACCESS, SPR_NOACCESS,
6528 &spr_read_generic, SPR_NOACCESS,
6529 0x00000000); /* TOFIX */
6530 /* XXX : not implemented */
6531 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6532 SPR_NOACCESS, SPR_NOACCESS,
6533 &spr_read_generic, &spr_write_generic,
6534 0x00000000); /* TOFIX */
6535 spr_register(env, SPR_HIOR, "SPR_HIOR",
6536 SPR_NOACCESS, SPR_NOACCESS,
6537 &spr_read_hior, &spr_write_hior,
6538 0x00000000);
6539 #if !defined(CONFIG_USER_ONLY)
6540 env->slb_nr = 32;
6541 #endif
6542 init_excp_970(env);
6543 env->dcache_line_size = 128;
6544 env->icache_line_size = 128;
6545 /* Allocate hardware IRQ controller */
6546 ppc970_irq_init(env);
6547 /* Can't find information on what this should be on reset. This
6548 * value is the one used by 74xx processors. */
6549 vscr_init(env, 0x00010000);
6550 }
6551
6552 #if defined(TARGET_PPC64)
6553 /* POWER7 */
6554 #define POWERPC_INSNS_POWER7 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6555 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6556 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6557 PPC_FLOAT_STFIWX | \
6558 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6559 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6560 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6561 PPC_64B | PPC_ALTIVEC | \
6562 PPC_SEGMENT_64B | PPC_SLBI | \
6563 PPC_POPCNTB | PPC_POPCNTWD)
6564 #define POWERPC_INSNS2_POWER7 (PPC2_VSX | PPC2_DFP)
6565 #define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
6566 #define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
6567 #define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
6568 #define POWERPC_INPUT_POWER7 (PPC_FLAGS_INPUT_POWER7)
6569 #define POWERPC_BFDM_POWER7 (bfd_mach_ppc64)
6570 #define POWERPC_FLAG_POWER7 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6571 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6572 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR)
6573 #define check_pow_POWER7 check_pow_nocheck
6574
6575 static void init_proc_POWER7 (CPUPPCState *env)
6576 {
6577 gen_spr_ne_601(env);
6578 gen_spr_7xx(env);
6579 /* Time base */
6580 gen_tbl(env);
6581 #if !defined(CONFIG_USER_ONLY)
6582 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6583 spr_register(env, SPR_PURR, "PURR",
6584 &spr_read_purr, SPR_NOACCESS,
6585 &spr_read_purr, SPR_NOACCESS,
6586 0x00000000);
6587 spr_register(env, SPR_SPURR, "SPURR",
6588 &spr_read_purr, SPR_NOACCESS,
6589 &spr_read_purr, SPR_NOACCESS,
6590 0x00000000);
6591 spr_register(env, SPR_CFAR, "SPR_CFAR",
6592 SPR_NOACCESS, SPR_NOACCESS,
6593 &spr_read_cfar, &spr_write_cfar,
6594 0x00000000);
6595 spr_register(env, SPR_DSCR, "SPR_DSCR",
6596 SPR_NOACCESS, SPR_NOACCESS,
6597 &spr_read_generic, &spr_write_generic,
6598 0x00000000);
6599 #endif /* !CONFIG_USER_ONLY */
6600 /* Memory management */
6601 /* XXX : not implemented */
6602 spr_register(env, SPR_MMUCFG, "MMUCFG",
6603 SPR_NOACCESS, SPR_NOACCESS,
6604 &spr_read_generic, SPR_NOACCESS,
6605 0x00000000); /* TOFIX */
6606 /* XXX : not implemented */
6607 spr_register(env, SPR_CTRL, "SPR_CTRLT",
6608 SPR_NOACCESS, SPR_NOACCESS,
6609 &spr_read_generic, &spr_write_generic,
6610 0x80800000);
6611 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
6612 SPR_NOACCESS, SPR_NOACCESS,
6613 &spr_read_generic, &spr_write_generic,
6614 0x80800000);
6615 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6616 &spr_read_generic, &spr_write_generic,
6617 &spr_read_generic, &spr_write_generic,
6618 0x00000000);
6619 #if !defined(CONFIG_USER_ONLY)
6620 env->slb_nr = 32;
6621 #endif
6622 init_excp_POWER7(env);
6623 env->dcache_line_size = 128;
6624 env->icache_line_size = 128;
6625 /* Allocate hardware IRQ controller */
6626 ppcPOWER7_irq_init(env);
6627 /* Can't find information on what this should be on reset. This
6628 * value is the one used by 74xx processors. */
6629 vscr_init(env, 0x00010000);
6630 }
6631 #endif /* TARGET_PPC64 */
6632
6633 /* PowerPC 620 */
6634 #define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6635 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6636 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6637 PPC_FLOAT_STFIWX | \
6638 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6639 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6640 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6641 PPC_SEGMENT | PPC_EXTERN | \
6642 PPC_64B | PPC_SLBI)
6643 #define POWERPC_INSNS2_620 (PPC_NONE)
6644 #define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6645 //#define POWERPC_MMU_620 (POWERPC_MMU_620)
6646 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
6647 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
6648 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
6649 #define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
6650 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
6651 #define check_pow_620 check_pow_nocheck /* Check this */
6652
6653 __attribute__ (( unused ))
6654 static void init_proc_620 (CPUPPCState *env)
6655 {
6656 gen_spr_ne_601(env);
6657 gen_spr_620(env);
6658 /* Time base */
6659 gen_tbl(env);
6660 /* Hardware implementation registers */
6661 /* XXX : not implemented */
6662 spr_register(env, SPR_HID0, "HID0",
6663 SPR_NOACCESS, SPR_NOACCESS,
6664 &spr_read_generic, &spr_write_generic,
6665 0x00000000);
6666 /* Memory management */
6667 gen_low_BATs(env);
6668 init_excp_620(env);
6669 env->dcache_line_size = 64;
6670 env->icache_line_size = 64;
6671 /* Allocate hardware IRQ controller */
6672 ppc6xx_irq_init(env);
6673 }
6674 #endif /* defined (TARGET_PPC64) */
6675
6676 /* Default 32 bits PowerPC target will be 604 */
6677 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
6678 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
6679 #define POWERPC_INSNS2_PPC32 POWERPC_INSNS2_604
6680 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6681 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
6682 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6683 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
6684 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
6685 #define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
6686 #define check_pow_PPC32 check_pow_604
6687 #define init_proc_PPC32 init_proc_604
6688
6689 /* Default 64 bits PowerPC target will be 970 FX */
6690 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6691 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
6692 #define POWERPC_INSNS2_PPC64 POWERPC_INSNS2_970FX
6693 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6694 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6695 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6696 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
6697 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
6698 #define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
6699 #define check_pow_PPC64 check_pow_970FX
6700 #define init_proc_PPC64 init_proc_970FX
6701
6702 /* Default PowerPC target will be PowerPC 32 */
6703 #if defined (TARGET_PPC64) && 0 // XXX: TODO
6704 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6705 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6706 #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC64
6707 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6708 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6709 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6710 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6711 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
6712 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
6713 #define check_pow_DEFAULT check_pow_PPC64
6714 #define init_proc_DEFAULT init_proc_PPC64
6715 #else
6716 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6717 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6718 #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC32
6719 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6720 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6721 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6722 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6723 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
6724 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
6725 #define check_pow_DEFAULT check_pow_PPC32
6726 #define init_proc_DEFAULT init_proc_PPC32
6727 #endif
6728
6729 /*****************************************************************************/
6730 /* PVR definitions for most known PowerPC */
6731 enum {
6732 /* PowerPC 401 family */
6733 /* Generic PowerPC 401 */
6734 #define CPU_POWERPC_401 CPU_POWERPC_401G2
6735 /* PowerPC 401 cores */
6736 CPU_POWERPC_401A1 = 0x00210000,
6737 CPU_POWERPC_401B2 = 0x00220000,
6738 #if 0
6739 CPU_POWERPC_401B3 = xxx,
6740 #endif
6741 CPU_POWERPC_401C2 = 0x00230000,
6742 CPU_POWERPC_401D2 = 0x00240000,
6743 CPU_POWERPC_401E2 = 0x00250000,
6744 CPU_POWERPC_401F2 = 0x00260000,
6745 CPU_POWERPC_401G2 = 0x00270000,
6746 /* PowerPC 401 microcontrolers */
6747 #if 0
6748 CPU_POWERPC_401GF = xxx,
6749 #endif
6750 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
6751 /* IBM Processor for Network Resources */
6752 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
6753 #if 0
6754 CPU_POWERPC_XIPCHIP = xxx,
6755 #endif
6756 /* PowerPC 403 family */
6757 /* Generic PowerPC 403 */
6758 #define CPU_POWERPC_403 CPU_POWERPC_403GC
6759 /* PowerPC 403 microcontrollers */
6760 CPU_POWERPC_403GA = 0x00200011,
6761 CPU_POWERPC_403GB = 0x00200100,
6762 CPU_POWERPC_403GC = 0x00200200,
6763 CPU_POWERPC_403GCX = 0x00201400,
6764 #if 0
6765 CPU_POWERPC_403GP = xxx,
6766 #endif
6767 /* PowerPC 405 family */
6768 /* Generic PowerPC 405 */
6769 #define CPU_POWERPC_405 CPU_POWERPC_405D4
6770 /* PowerPC 405 cores */
6771 #if 0
6772 CPU_POWERPC_405A3 = xxx,
6773 #endif
6774 #if 0
6775 CPU_POWERPC_405A4 = xxx,
6776 #endif
6777 #if 0
6778 CPU_POWERPC_405B3 = xxx,
6779 #endif
6780 #if 0
6781 CPU_POWERPC_405B4 = xxx,
6782 #endif
6783 #if 0
6784 CPU_POWERPC_405C3 = xxx,
6785 #endif
6786 #if 0
6787 CPU_POWERPC_405C4 = xxx,
6788 #endif
6789 CPU_POWERPC_405D2 = 0x20010000,
6790 #if 0
6791 CPU_POWERPC_405D3 = xxx,
6792 #endif
6793 CPU_POWERPC_405D4 = 0x41810000,
6794 #if 0
6795 CPU_POWERPC_405D5 = xxx,
6796 #endif
6797 #if 0
6798 CPU_POWERPC_405E4 = xxx,
6799 #endif
6800 #if 0
6801 CPU_POWERPC_405F4 = xxx,
6802 #endif
6803 #if 0
6804 CPU_POWERPC_405F5 = xxx,
6805 #endif
6806 #if 0
6807 CPU_POWERPC_405F6 = xxx,
6808 #endif
6809 /* PowerPC 405 microcontrolers */
6810 /* XXX: missing 0x200108a0 */
6811 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6812 CPU_POWERPC_405CRa = 0x40110041,
6813 CPU_POWERPC_405CRb = 0x401100C5,
6814 CPU_POWERPC_405CRc = 0x40110145,
6815 CPU_POWERPC_405EP = 0x51210950,
6816 #if 0
6817 CPU_POWERPC_405EXr = xxx,
6818 #endif
6819 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
6820 #if 0
6821 CPU_POWERPC_405FX = xxx,
6822 #endif
6823 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6824 CPU_POWERPC_405GPa = 0x40110000,
6825 CPU_POWERPC_405GPb = 0x40110040,
6826 CPU_POWERPC_405GPc = 0x40110082,
6827 CPU_POWERPC_405GPd = 0x401100C4,
6828 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6829 CPU_POWERPC_405GPR = 0x50910951,
6830 #if 0
6831 CPU_POWERPC_405H = xxx,
6832 #endif
6833 #if 0
6834 CPU_POWERPC_405L = xxx,
6835 #endif
6836 CPU_POWERPC_405LP = 0x41F10000,
6837 #if 0
6838 CPU_POWERPC_405PM = xxx,
6839 #endif
6840 #if 0
6841 CPU_POWERPC_405PS = xxx,
6842 #endif
6843 #if 0
6844 CPU_POWERPC_405S = xxx,
6845 #endif
6846 /* IBM network processors */
6847 CPU_POWERPC_NPE405H = 0x414100C0,
6848 CPU_POWERPC_NPE405H2 = 0x41410140,
6849 CPU_POWERPC_NPE405L = 0x416100C0,
6850 CPU_POWERPC_NPE4GS3 = 0x40B10000,
6851 #if 0
6852 CPU_POWERPC_NPCxx1 = xxx,
6853 #endif
6854 #if 0
6855 CPU_POWERPC_NPR161 = xxx,
6856 #endif
6857 #if 0
6858 CPU_POWERPC_LC77700 = xxx,
6859 #endif
6860 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6861 #if 0
6862 CPU_POWERPC_STB01000 = xxx,
6863 #endif
6864 #if 0
6865 CPU_POWERPC_STB01010 = xxx,
6866 #endif
6867 #if 0
6868 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
6869 #endif
6870 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
6871 #if 0
6872 CPU_POWERPC_STB043 = xxx,
6873 #endif
6874 #if 0
6875 CPU_POWERPC_STB045 = xxx,
6876 #endif
6877 CPU_POWERPC_STB04 = 0x41810000,
6878 CPU_POWERPC_STB25 = 0x51510950,
6879 #if 0
6880 CPU_POWERPC_STB130 = xxx,
6881 #endif
6882 /* Xilinx cores */
6883 CPU_POWERPC_X2VP4 = 0x20010820,
6884 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
6885 CPU_POWERPC_X2VP20 = 0x20010860,
6886 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
6887 #if 0
6888 CPU_POWERPC_ZL10310 = xxx,
6889 #endif
6890 #if 0
6891 CPU_POWERPC_ZL10311 = xxx,
6892 #endif
6893 #if 0
6894 CPU_POWERPC_ZL10320 = xxx,
6895 #endif
6896 #if 0
6897 CPU_POWERPC_ZL10321 = xxx,
6898 #endif
6899 /* PowerPC 440 family */
6900 /* Generic PowerPC 440 */
6901 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
6902 /* PowerPC 440 cores */
6903 #if 0
6904 CPU_POWERPC_440A4 = xxx,
6905 #endif
6906 CPU_POWERPC_440_XILINX = 0x7ff21910,
6907 #if 0
6908 CPU_POWERPC_440A5 = xxx,
6909 #endif
6910 #if 0
6911 CPU_POWERPC_440B4 = xxx,
6912 #endif
6913 #if 0
6914 CPU_POWERPC_440F5 = xxx,
6915 #endif
6916 #if 0
6917 CPU_POWERPC_440G5 = xxx,
6918 #endif
6919 #if 0
6920 CPU_POWERPC_440H4 = xxx,
6921 #endif
6922 #if 0
6923 CPU_POWERPC_440H6 = xxx,
6924 #endif
6925 /* PowerPC 440 microcontrolers */
6926 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
6927 CPU_POWERPC_440EPa = 0x42221850,
6928 CPU_POWERPC_440EPb = 0x422218D3,
6929 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
6930 CPU_POWERPC_440GPb = 0x40120440,
6931 CPU_POWERPC_440GPc = 0x40120481,
6932 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
6933 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
6934 CPU_POWERPC_440GRX = 0x200008D0,
6935 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
6936 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
6937 CPU_POWERPC_440GXa = 0x51B21850,
6938 CPU_POWERPC_440GXb = 0x51B21851,
6939 CPU_POWERPC_440GXc = 0x51B21892,
6940 CPU_POWERPC_440GXf = 0x51B21894,
6941 #if 0
6942 CPU_POWERPC_440S = xxx,
6943 #endif
6944 CPU_POWERPC_440SP = 0x53221850,
6945 CPU_POWERPC_440SP2 = 0x53221891,
6946 CPU_POWERPC_440SPE = 0x53421890,
6947 /* PowerPC 460 family */
6948 #if 0
6949 /* Generic PowerPC 464 */
6950 #define CPU_POWERPC_464 CPU_POWERPC_464H90
6951 #endif
6952 /* PowerPC 464 microcontrolers */
6953 #if 0
6954 CPU_POWERPC_464H90 = xxx,
6955 #endif
6956 #if 0
6957 CPU_POWERPC_464H90FP = xxx,
6958 #endif
6959 /* Freescale embedded PowerPC cores */
6960 /* PowerPC MPC 5xx cores (aka RCPU) */
6961 CPU_POWERPC_MPC5xx = 0x00020020,
6962 #define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
6963 #define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
6964 #define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
6965 #define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
6966 #define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
6967 #define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
6968 #define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
6969 #define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
6970 #define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
6971 #define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
6972 #define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
6973 #define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
6974 #define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
6975 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
6976 CPU_POWERPC_MPC8xx = 0x00500000,
6977 #define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
6978 #define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
6979 #define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
6980 #define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
6981 #define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
6982 #define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
6983 #define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
6984 #define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
6985 #define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
6986 #define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
6987 #define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
6988 #define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
6989 #define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
6990 #define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
6991 #define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
6992 /* G2 cores (aka PowerQUICC-II) */
6993 CPU_POWERPC_G2 = 0x00810011,
6994 CPU_POWERPC_G2H4 = 0x80811010,
6995 CPU_POWERPC_G2gp = 0x80821010,
6996 CPU_POWERPC_G2ls = 0x90810010,
6997 CPU_POWERPC_MPC603 = 0x00810100,
6998 CPU_POWERPC_G2_HIP3 = 0x00810101,
6999 CPU_POWERPC_G2_HIP4 = 0x80811014,
7000 /* G2_LE core (aka PowerQUICC-II) */
7001 CPU_POWERPC_G2LE = 0x80820010,
7002 CPU_POWERPC_G2LEgp = 0x80822010,
7003 CPU_POWERPC_G2LEls = 0xA0822010,
7004 CPU_POWERPC_G2LEgp1 = 0x80822011,
7005 CPU_POWERPC_G2LEgp3 = 0x80822013,
7006 /* MPC52xx microcontrollers */
7007 /* XXX: MPC 5121 ? */
7008 #define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
7009 #define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
7010 #define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
7011 #define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
7012 #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
7013 #define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
7014 #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
7015 #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
7016 /* MPC82xx microcontrollers */
7017 #define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
7018 #define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
7019 #define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
7020 #define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
7021 #define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
7022 #define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
7023 #define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
7024 #define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
7025 #define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
7026 #define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
7027 #define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
7028 #define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
7029 #define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
7030 #define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
7031 #define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
7032 #define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
7033 #define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
7034 #define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
7035 #define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
7036 #define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
7037 #define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
7038 #define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
7039 #define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
7040 #define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
7041 #define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
7042 #define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
7043 #define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
7044 #define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
7045 #define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
7046 /* e200 family */
7047 /* e200 cores */
7048 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
7049 #if 0
7050 CPU_POWERPC_e200z0 = xxx,
7051 #endif
7052 #if 0
7053 CPU_POWERPC_e200z1 = xxx,
7054 #endif
7055 #if 0 /* ? */
7056 CPU_POWERPC_e200z3 = 0x81120000,
7057 #endif
7058 CPU_POWERPC_e200z5 = 0x81000000,
7059 CPU_POWERPC_e200z6 = 0x81120000,
7060 /* MPC55xx microcontrollers */
7061 #define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
7062 #if 0
7063 #define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
7064 #define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
7065 #define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
7066 #define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
7067 #define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
7068 #define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
7069 #define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
7070 #define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
7071 #define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
7072 #define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
7073 #define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
7074 #define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
7075 #define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
7076 #define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
7077 #endif
7078 #if 0
7079 #define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
7080 #define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
7081 #endif
7082 #define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
7083 #define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
7084 #define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
7085 #define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
7086 #define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
7087 #define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
7088 /* e300 family */
7089 /* e300 cores */
7090 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
7091 CPU_POWERPC_e300c1 = 0x00830010,
7092 CPU_POWERPC_e300c2 = 0x00840010,
7093 CPU_POWERPC_e300c3 = 0x00850010,
7094 CPU_POWERPC_e300c4 = 0x00860010,
7095 /* MPC83xx microcontrollers */
7096 #define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
7097 #define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
7098 #define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
7099 #define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
7100 #define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
7101 #define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
7102 /* e500 family */
7103 /* e500 cores */
7104 #define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
7105 #define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
7106 #define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
7107 CPU_POWERPC_e500v1_v10 = 0x80200010,
7108 CPU_POWERPC_e500v1_v20 = 0x80200020,
7109 CPU_POWERPC_e500v2_v10 = 0x80210010,
7110 CPU_POWERPC_e500v2_v11 = 0x80210011,
7111 CPU_POWERPC_e500v2_v20 = 0x80210020,
7112 CPU_POWERPC_e500v2_v21 = 0x80210021,
7113 CPU_POWERPC_e500v2_v22 = 0x80210022,
7114 CPU_POWERPC_e500v2_v30 = 0x80210030,
7115 CPU_POWERPC_e500mc = 0x80230020,
7116 /* MPC85xx microcontrollers */
7117 #define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
7118 #define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
7119 #define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
7120 #define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
7121 #define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
7122 #define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
7123 #define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
7124 #define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
7125 #define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
7126 #define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
7127 #define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
7128 #define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
7129 #define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
7130 #define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
7131 #define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
7132 #define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
7133 #define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
7134 #define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
7135 #define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
7136 #define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
7137 #define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
7138 #define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
7139 #define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
7140 #define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
7141 #define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
7142 #define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
7143 #define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
7144 #define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
7145 #define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
7146 #define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
7147 #define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
7148 #define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
7149 #define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
7150 #define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
7151 #define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
7152 #define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
7153 #define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
7154 #define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
7155 #define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
7156 #define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
7157 #define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
7158 #define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
7159 #define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
7160 #define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
7161 #define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
7162 #define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
7163 #define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
7164 #define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
7165 #define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
7166 #define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
7167 #define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
7168 #define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
7169 #define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
7170 #define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
7171 #define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
7172 #define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
7173 #define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
7174 #define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
7175 #define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
7176 #define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
7177 #define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
7178 #define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
7179 #define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
7180 #define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
7181 #define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
7182 #define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
7183 #define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
7184 #define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
7185 #define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
7186 #define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
7187 /* e600 family */
7188 /* e600 cores */
7189 CPU_POWERPC_e600 = 0x80040010,
7190 /* MPC86xx microcontrollers */
7191 #define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
7192 #define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
7193 #define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
7194 /* PowerPC 6xx cores */
7195 #define CPU_POWERPC_601 CPU_POWERPC_601_v2
7196 CPU_POWERPC_601_v0 = 0x00010001,
7197 CPU_POWERPC_601_v1 = 0x00010001,
7198 #define CPU_POWERPC_601v CPU_POWERPC_601_v2
7199 CPU_POWERPC_601_v2 = 0x00010002,
7200 CPU_POWERPC_602 = 0x00050100,
7201 CPU_POWERPC_603 = 0x00030100,
7202 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
7203 CPU_POWERPC_603E_v11 = 0x00060101,
7204 CPU_POWERPC_603E_v12 = 0x00060102,
7205 CPU_POWERPC_603E_v13 = 0x00060103,
7206 CPU_POWERPC_603E_v14 = 0x00060104,
7207 CPU_POWERPC_603E_v22 = 0x00060202,
7208 CPU_POWERPC_603E_v3 = 0x00060300,
7209 CPU_POWERPC_603E_v4 = 0x00060400,
7210 CPU_POWERPC_603E_v41 = 0x00060401,
7211 CPU_POWERPC_603E7t = 0x00071201,
7212 CPU_POWERPC_603E7v = 0x00070100,
7213 CPU_POWERPC_603E7v1 = 0x00070101,
7214 CPU_POWERPC_603E7v2 = 0x00070201,
7215 CPU_POWERPC_603E7 = 0x00070200,
7216 CPU_POWERPC_603P = 0x00070000,
7217 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
7218 /* XXX: missing 0x00040303 (604) */
7219 CPU_POWERPC_604 = 0x00040103,
7220 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
7221 /* XXX: missing 0x00091203 */
7222 /* XXX: missing 0x00092110 */
7223 /* XXX: missing 0x00092120 */
7224 CPU_POWERPC_604E_v10 = 0x00090100,
7225 CPU_POWERPC_604E_v22 = 0x00090202,
7226 CPU_POWERPC_604E_v24 = 0x00090204,
7227 /* XXX: missing 0x000a0100 */
7228 /* XXX: missing 0x00093102 */
7229 CPU_POWERPC_604R = 0x000a0101,
7230 #if 0
7231 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
7232 #endif
7233 /* PowerPC 740/750 cores (aka G3) */
7234 /* XXX: missing 0x00084202 */
7235 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
7236 CPU_POWERPC_7x0_v10 = 0x00080100,
7237 CPU_POWERPC_7x0_v20 = 0x00080200,
7238 CPU_POWERPC_7x0_v21 = 0x00080201,
7239 CPU_POWERPC_7x0_v22 = 0x00080202,
7240 CPU_POWERPC_7x0_v30 = 0x00080300,
7241 CPU_POWERPC_7x0_v31 = 0x00080301,
7242 CPU_POWERPC_740E = 0x00080100,
7243 CPU_POWERPC_750E = 0x00080200,
7244 CPU_POWERPC_7x0P = 0x10080000,
7245 /* XXX: missing 0x00087010 (CL ?) */
7246 #define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
7247 CPU_POWERPC_750CL_v10 = 0x00087200,
7248 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
7249 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
7250 CPU_POWERPC_750CX_v10 = 0x00082100,
7251 CPU_POWERPC_750CX_v20 = 0x00082200,
7252 CPU_POWERPC_750CX_v21 = 0x00082201,
7253 CPU_POWERPC_750CX_v22 = 0x00082202,
7254 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
7255 CPU_POWERPC_750CXE_v21 = 0x00082211,
7256 CPU_POWERPC_750CXE_v22 = 0x00082212,
7257 CPU_POWERPC_750CXE_v23 = 0x00082213,
7258 CPU_POWERPC_750CXE_v24 = 0x00082214,
7259 CPU_POWERPC_750CXE_v24b = 0x00083214,
7260 CPU_POWERPC_750CXE_v30 = 0x00082310,
7261 CPU_POWERPC_750CXE_v31 = 0x00082311,
7262 CPU_POWERPC_750CXE_v31b = 0x00083311,
7263 CPU_POWERPC_750CXR = 0x00083410,
7264 CPU_POWERPC_750FL = 0x70000203,
7265 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
7266 CPU_POWERPC_750FX_v10 = 0x70000100,
7267 CPU_POWERPC_750FX_v20 = 0x70000200,
7268 CPU_POWERPC_750FX_v21 = 0x70000201,
7269 CPU_POWERPC_750FX_v22 = 0x70000202,
7270 CPU_POWERPC_750FX_v23 = 0x70000203,
7271 CPU_POWERPC_750GL = 0x70020102,
7272 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
7273 CPU_POWERPC_750GX_v10 = 0x70020100,
7274 CPU_POWERPC_750GX_v11 = 0x70020101,
7275 CPU_POWERPC_750GX_v12 = 0x70020102,
7276 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
7277 CPU_POWERPC_750L_v20 = 0x00088200,
7278 CPU_POWERPC_750L_v21 = 0x00088201,
7279 CPU_POWERPC_750L_v22 = 0x00088202,
7280 CPU_POWERPC_750L_v30 = 0x00088300,
7281 CPU_POWERPC_750L_v32 = 0x00088302,
7282 /* PowerPC 745/755 cores */
7283 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
7284 CPU_POWERPC_7x5_v10 = 0x00083100,
7285 CPU_POWERPC_7x5_v11 = 0x00083101,
7286 CPU_POWERPC_7x5_v20 = 0x00083200,
7287 CPU_POWERPC_7x5_v21 = 0x00083201,
7288 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
7289 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
7290 CPU_POWERPC_7x5_v24 = 0x00083204,
7291 CPU_POWERPC_7x5_v25 = 0x00083205,
7292 CPU_POWERPC_7x5_v26 = 0x00083206,
7293 CPU_POWERPC_7x5_v27 = 0x00083207,
7294 CPU_POWERPC_7x5_v28 = 0x00083208,
7295 #if 0
7296 CPU_POWERPC_7x5P = xxx,
7297 #endif
7298 /* PowerPC 74xx cores (aka G4) */
7299 /* XXX: missing 0x000C1101 */
7300 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
7301 CPU_POWERPC_7400_v10 = 0x000C0100,
7302 CPU_POWERPC_7400_v11 = 0x000C0101,
7303 CPU_POWERPC_7400_v20 = 0x000C0200,
7304 CPU_POWERPC_7400_v21 = 0x000C0201,
7305 CPU_POWERPC_7400_v22 = 0x000C0202,
7306 CPU_POWERPC_7400_v26 = 0x000C0206,
7307 CPU_POWERPC_7400_v27 = 0x000C0207,
7308 CPU_POWERPC_7400_v28 = 0x000C0208,
7309 CPU_POWERPC_7400_v29 = 0x000C0209,
7310 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
7311 CPU_POWERPC_7410_v10 = 0x800C1100,
7312 CPU_POWERPC_7410_v11 = 0x800C1101,
7313 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
7314 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
7315 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
7316 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
7317 CPU_POWERPC_7448_v10 = 0x80040100,
7318 CPU_POWERPC_7448_v11 = 0x80040101,
7319 CPU_POWERPC_7448_v20 = 0x80040200,
7320 CPU_POWERPC_7448_v21 = 0x80040201,
7321 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
7322 CPU_POWERPC_7450_v10 = 0x80000100,
7323 CPU_POWERPC_7450_v11 = 0x80000101,
7324 CPU_POWERPC_7450_v12 = 0x80000102,
7325 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
7326 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
7327 #define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
7328 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
7329 /* XXX: this entry might be a bug in some documentation */
7330 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
7331 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
7332 CPU_POWERPC_74x5_v10 = 0x80010100,
7333 /* XXX: missing 0x80010200 */
7334 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
7335 CPU_POWERPC_74x5_v32 = 0x80010302,
7336 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
7337 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
7338 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
7339 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
7340 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
7341 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
7342 #define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
7343 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
7344 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
7345 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
7346 /* 64 bits PowerPC */
7347 #if defined(TARGET_PPC64)
7348 CPU_POWERPC_620 = 0x00140000,
7349 CPU_POWERPC_630 = 0x00400000,
7350 CPU_POWERPC_631 = 0x00410104,
7351 CPU_POWERPC_POWER4 = 0x00350000,
7352 CPU_POWERPC_POWER4P = 0x00380000,
7353 /* XXX: missing 0x003A0201 */
7354 CPU_POWERPC_POWER5 = 0x003A0203,
7355 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
7356 CPU_POWERPC_POWER5P = 0x003B0000,
7357 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
7358 CPU_POWERPC_POWER6 = 0x003E0000,
7359 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
7360 CPU_POWERPC_POWER6A = 0x0F000002,
7361 #define CPU_POWERPC_POWER7 CPU_POWERPC_POWER7_v20
7362 CPU_POWERPC_POWER7_v20 = 0x003F0200,
7363 CPU_POWERPC_POWER7_v21 = 0x003F0201,
7364 CPU_POWERPC_POWER7_v23 = 0x003F0203,
7365 CPU_POWERPC_970 = 0x00390202,
7366 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
7367 CPU_POWERPC_970FX_v10 = 0x00391100,
7368 CPU_POWERPC_970FX_v20 = 0x003C0200,
7369 CPU_POWERPC_970FX_v21 = 0x003C0201,
7370 CPU_POWERPC_970FX_v30 = 0x003C0300,
7371 CPU_POWERPC_970FX_v31 = 0x003C0301,
7372 CPU_POWERPC_970GX = 0x00450000,
7373 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
7374 CPU_POWERPC_970MP_v10 = 0x00440100,
7375 CPU_POWERPC_970MP_v11 = 0x00440101,
7376 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
7377 CPU_POWERPC_CELL_v10 = 0x00700100,
7378 CPU_POWERPC_CELL_v20 = 0x00700400,
7379 CPU_POWERPC_CELL_v30 = 0x00700500,
7380 CPU_POWERPC_CELL_v31 = 0x00700501,
7381 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
7382 CPU_POWERPC_RS64 = 0x00330000,
7383 CPU_POWERPC_RS64II = 0x00340000,
7384 CPU_POWERPC_RS64III = 0x00360000,
7385 CPU_POWERPC_RS64IV = 0x00370000,
7386 #endif /* defined(TARGET_PPC64) */
7387 /* Original POWER */
7388 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7389 * POWER2 (RIOS2) & RSC2 (P2SC) here
7390 */
7391 #if 0
7392 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
7393 #endif
7394 #if 0
7395 CPU_POWER2 = xxx, /* 0x40000 ? */
7396 #endif
7397 /* PA Semi core */
7398 CPU_POWERPC_PA6T = 0x00900000,
7399 };
7400
7401 /* System version register (used on MPC 8xxx) */
7402 enum {
7403 POWERPC_SVR_NONE = 0x00000000,
7404 #define POWERPC_SVR_52xx POWERPC_SVR_5200
7405 #define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
7406 POWERPC_SVR_5200_v10 = 0x80110010,
7407 POWERPC_SVR_5200_v11 = 0x80110011,
7408 POWERPC_SVR_5200_v12 = 0x80110012,
7409 #define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
7410 POWERPC_SVR_5200B_v20 = 0x80110020,
7411 POWERPC_SVR_5200B_v21 = 0x80110021,
7412 #define POWERPC_SVR_55xx POWERPC_SVR_5567
7413 #if 0
7414 POWERPC_SVR_5533 = xxx,
7415 #endif
7416 #if 0
7417 POWERPC_SVR_5534 = xxx,
7418 #endif
7419 #if 0
7420 POWERPC_SVR_5553 = xxx,
7421 #endif
7422 #if 0
7423 POWERPC_SVR_5554 = xxx,
7424 #endif
7425 #if 0
7426 POWERPC_SVR_5561 = xxx,
7427 #endif
7428 #if 0
7429 POWERPC_SVR_5565 = xxx,
7430 #endif
7431 #if 0
7432 POWERPC_SVR_5566 = xxx,
7433 #endif
7434 #if 0
7435 POWERPC_SVR_5567 = xxx,
7436 #endif
7437 #if 0
7438 POWERPC_SVR_8313 = xxx,
7439 #endif
7440 #if 0
7441 POWERPC_SVR_8313E = xxx,
7442 #endif
7443 #if 0
7444 POWERPC_SVR_8314 = xxx,
7445 #endif
7446 #if 0
7447 POWERPC_SVR_8314E = xxx,
7448 #endif
7449 #if 0
7450 POWERPC_SVR_8315 = xxx,
7451 #endif
7452 #if 0
7453 POWERPC_SVR_8315E = xxx,
7454 #endif
7455 #if 0
7456 POWERPC_SVR_8321 = xxx,
7457 #endif
7458 #if 0
7459 POWERPC_SVR_8321E = xxx,
7460 #endif
7461 #if 0
7462 POWERPC_SVR_8323 = xxx,
7463 #endif
7464 #if 0
7465 POWERPC_SVR_8323E = xxx,
7466 #endif
7467 POWERPC_SVR_8343 = 0x80570010,
7468 POWERPC_SVR_8343A = 0x80570030,
7469 POWERPC_SVR_8343E = 0x80560010,
7470 POWERPC_SVR_8343EA = 0x80560030,
7471 #define POWERPC_SVR_8347 POWERPC_SVR_8347T
7472 POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
7473 POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
7474 #define POWERPC_SVR_8347A POWERPC_SVR_8347AT
7475 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7476 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
7477 #define POWERPC_SVR_8347E POWERPC_SVR_8347ET
7478 POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
7479 POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
7480 #define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
7481 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7482 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7483 POWERPC_SVR_8349 = 0x80510010,
7484 POWERPC_SVR_8349A = 0x80510030,
7485 POWERPC_SVR_8349E = 0x80500010,
7486 POWERPC_SVR_8349EA = 0x80500030,
7487 #if 0
7488 POWERPC_SVR_8358E = xxx,
7489 #endif
7490 #if 0
7491 POWERPC_SVR_8360E = xxx,
7492 #endif
7493 #define POWERPC_SVR_E500 0x40000000
7494 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7495 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7496 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7497 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7498 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7499 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
7500 #define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
7501 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7502 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
7503 #define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
7504 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7505 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
7506 #define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
7507 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7508 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7509 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
7510 #define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
7511 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7512 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
7513 #define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
7514 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7515 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
7516 #define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
7517 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7518 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7519 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7520 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
7521 #define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
7522 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7523 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7524 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7525 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
7526 #define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
7527 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7528 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
7529 #define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
7530 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7531 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
7532 #define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
7533 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7534 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
7535 #define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
7536 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7537 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
7538 #define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
7539 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7540 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
7541 #define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
7542 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7543 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7544 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7545 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
7546 #define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
7547 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7548 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7549 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7550 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
7551 #define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
7552 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7553 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
7554 #define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
7555 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7556 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
7557 #define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
7558 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7559 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7560 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7561 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7562 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7563 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7564 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7565 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7566 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
7567 #if 0
7568 POWERPC_SVR_8610 = xxx,
7569 #endif
7570 POWERPC_SVR_8641 = 0x80900021,
7571 POWERPC_SVR_8641D = 0x80900121,
7572 };
7573
7574 /*****************************************************************************/
7575 /* PowerPC CPU definitions */
7576 #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
7577 { \
7578 .name = _name, \
7579 .pvr = _pvr, \
7580 .svr = _svr, \
7581 .insns_flags = glue(POWERPC_INSNS_,_type), \
7582 .insns_flags2 = glue(POWERPC_INSNS2_,_type), \
7583 .msr_mask = glue(POWERPC_MSRM_,_type), \
7584 .mmu_model = glue(POWERPC_MMU_,_type), \
7585 .excp_model = glue(POWERPC_EXCP_,_type), \
7586 .bus_model = glue(POWERPC_INPUT_,_type), \
7587 .bfd_mach = glue(POWERPC_BFDM_,_type), \
7588 .flags = glue(POWERPC_FLAG_,_type), \
7589 .init_proc = &glue(init_proc_,_type), \
7590 .check_pow = &glue(check_pow_,_type), \
7591 }
7592 #define POWERPC_DEF(_name, _pvr, _type) \
7593 POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
7594
7595 static const ppc_def_t ppc_defs[] = {
7596 /* Embedded PowerPC */
7597 /* PowerPC 401 family */
7598 /* Generic PowerPC 401 */
7599 POWERPC_DEF("401", CPU_POWERPC_401, 401),
7600 /* PowerPC 401 cores */
7601 /* PowerPC 401A1 */
7602 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
7603 /* PowerPC 401B2 */
7604 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
7605 #if defined (TODO)
7606 /* PowerPC 401B3 */
7607 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
7608 #endif
7609 /* PowerPC 401C2 */
7610 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
7611 /* PowerPC 401D2 */
7612 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
7613 /* PowerPC 401E2 */
7614 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
7615 /* PowerPC 401F2 */
7616 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
7617 /* PowerPC 401G2 */
7618 /* XXX: to be checked */
7619 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
7620 /* PowerPC 401 microcontrolers */
7621 #if defined (TODO)
7622 /* PowerPC 401GF */
7623 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
7624 #endif
7625 /* IOP480 (401 microcontroler) */
7626 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
7627 /* IBM Processor for Network Resources */
7628 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
7629 #if defined (TODO)
7630 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
7631 #endif
7632 /* PowerPC 403 family */
7633 /* Generic PowerPC 403 */
7634 POWERPC_DEF("403", CPU_POWERPC_403, 403),
7635 /* PowerPC 403 microcontrolers */
7636 /* PowerPC 403 GA */
7637 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
7638 /* PowerPC 403 GB */
7639 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
7640 /* PowerPC 403 GC */
7641 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
7642 /* PowerPC 403 GCX */
7643 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
7644 #if defined (TODO)
7645 /* PowerPC 403 GP */
7646 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
7647 #endif
7648 /* PowerPC 405 family */
7649 /* Generic PowerPC 405 */
7650 POWERPC_DEF("405", CPU_POWERPC_405, 405),
7651 /* PowerPC 405 cores */
7652 #if defined (TODO)
7653 /* PowerPC 405 A3 */
7654 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
7655 #endif
7656 #if defined (TODO)
7657 /* PowerPC 405 A4 */
7658 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
7659 #endif
7660 #if defined (TODO)
7661 /* PowerPC 405 B3 */
7662 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
7663 #endif
7664 #if defined (TODO)
7665 /* PowerPC 405 B4 */
7666 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
7667 #endif
7668 #if defined (TODO)
7669 /* PowerPC 405 C3 */
7670 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
7671 #endif
7672 #if defined (TODO)
7673 /* PowerPC 405 C4 */
7674 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
7675 #endif
7676 /* PowerPC 405 D2 */
7677 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
7678 #if defined (TODO)
7679 /* PowerPC 405 D3 */
7680 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
7681 #endif
7682 /* PowerPC 405 D4 */
7683 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
7684 #if defined (TODO)
7685 /* PowerPC 405 D5 */
7686 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
7687 #endif
7688 #if defined (TODO)
7689 /* PowerPC 405 E4 */
7690 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
7691 #endif
7692 #if defined (TODO)
7693 /* PowerPC 405 F4 */
7694 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
7695 #endif
7696 #if defined (TODO)
7697 /* PowerPC 405 F5 */
7698 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
7699 #endif
7700 #if defined (TODO)
7701 /* PowerPC 405 F6 */
7702 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
7703 #endif
7704 /* PowerPC 405 microcontrolers */
7705 /* PowerPC 405 CR */
7706 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
7707 /* PowerPC 405 CRa */
7708 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
7709 /* PowerPC 405 CRb */
7710 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
7711 /* PowerPC 405 CRc */
7712 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
7713 /* PowerPC 405 EP */
7714 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
7715 #if defined(TODO)
7716 /* PowerPC 405 EXr */
7717 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
7718 #endif
7719 /* PowerPC 405 EZ */
7720 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
7721 #if defined(TODO)
7722 /* PowerPC 405 FX */
7723 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
7724 #endif
7725 /* PowerPC 405 GP */
7726 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
7727 /* PowerPC 405 GPa */
7728 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
7729 /* PowerPC 405 GPb */
7730 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
7731 /* PowerPC 405 GPc */
7732 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
7733 /* PowerPC 405 GPd */
7734 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
7735 /* PowerPC 405 GPe */
7736 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
7737 /* PowerPC 405 GPR */
7738 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
7739 #if defined(TODO)
7740 /* PowerPC 405 H */
7741 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
7742 #endif
7743 #if defined(TODO)
7744 /* PowerPC 405 L */
7745 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
7746 #endif
7747 /* PowerPC 405 LP */
7748 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
7749 #if defined(TODO)
7750 /* PowerPC 405 PM */
7751 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
7752 #endif
7753 #if defined(TODO)
7754 /* PowerPC 405 PS */
7755 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
7756 #endif
7757 #if defined(TODO)
7758 /* PowerPC 405 S */
7759 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
7760 #endif
7761 /* Npe405 H */
7762 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
7763 /* Npe405 H2 */
7764 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
7765 /* Npe405 L */
7766 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
7767 /* Npe4GS3 */
7768 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
7769 #if defined (TODO)
7770 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
7771 #endif
7772 #if defined (TODO)
7773 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
7774 #endif
7775 #if defined (TODO)
7776 /* PowerPC LC77700 (Sanyo) */
7777 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
7778 #endif
7779 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7780 #if defined (TODO)
7781 /* STB010000 */
7782 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
7783 #endif
7784 #if defined (TODO)
7785 /* STB01010 */
7786 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
7787 #endif
7788 #if defined (TODO)
7789 /* STB0210 */
7790 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
7791 #endif
7792 /* STB03xx */
7793 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
7794 #if defined (TODO)
7795 /* STB043x */
7796 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
7797 #endif
7798 #if defined (TODO)
7799 /* STB045x */
7800 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
7801 #endif
7802 /* STB04xx */
7803 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
7804 /* STB25xx */
7805 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
7806 #if defined (TODO)
7807 /* STB130 */
7808 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
7809 #endif
7810 /* Xilinx PowerPC 405 cores */
7811 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
7812 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
7813 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
7814 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
7815 #if defined (TODO)
7816 /* Zarlink ZL10310 */
7817 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
7818 #endif
7819 #if defined (TODO)
7820 /* Zarlink ZL10311 */
7821 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
7822 #endif
7823 #if defined (TODO)
7824 /* Zarlink ZL10320 */
7825 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
7826 #endif
7827 #if defined (TODO)
7828 /* Zarlink ZL10321 */
7829 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
7830 #endif
7831 /* PowerPC 440 family */
7832 #if defined(TODO_USER_ONLY)
7833 /* Generic PowerPC 440 */
7834 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
7835 #endif
7836 /* PowerPC 440 cores */
7837 #if defined (TODO)
7838 /* PowerPC 440 A4 */
7839 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
7840 #endif
7841 /* PowerPC 440 Xilinx 5 */
7842 POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5),
7843 #if defined (TODO)
7844 /* PowerPC 440 A5 */
7845 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
7846 #endif
7847 #if defined (TODO)
7848 /* PowerPC 440 B4 */
7849 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
7850 #endif
7851 #if defined (TODO)
7852 /* PowerPC 440 G4 */
7853 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
7854 #endif
7855 #if defined (TODO)
7856 /* PowerPC 440 F5 */
7857 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
7858 #endif
7859 #if defined (TODO)
7860 /* PowerPC 440 G5 */
7861 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
7862 #endif
7863 #if defined (TODO)
7864 /* PowerPC 440H4 */
7865 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
7866 #endif
7867 #if defined (TODO)
7868 /* PowerPC 440H6 */
7869 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
7870 #endif
7871 /* PowerPC 440 microcontrolers */
7872 #if defined(TODO_USER_ONLY)
7873 /* PowerPC 440 EP */
7874 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
7875 #endif
7876 #if defined(TODO_USER_ONLY)
7877 /* PowerPC 440 EPa */
7878 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
7879 #endif
7880 #if defined(TODO_USER_ONLY)
7881 /* PowerPC 440 EPb */
7882 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
7883 #endif
7884 #if defined(TODO_USER_ONLY)
7885 /* PowerPC 440 EPX */
7886 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
7887 #endif
7888 #if defined(TODO_USER_ONLY)
7889 /* PowerPC 440 GP */
7890 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
7891 #endif
7892 #if defined(TODO_USER_ONLY)
7893 /* PowerPC 440 GPb */
7894 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
7895 #endif
7896 #if defined(TODO_USER_ONLY)
7897 /* PowerPC 440 GPc */
7898 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
7899 #endif
7900 #if defined(TODO_USER_ONLY)
7901 /* PowerPC 440 GR */
7902 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
7903 #endif
7904 #if defined(TODO_USER_ONLY)
7905 /* PowerPC 440 GRa */
7906 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
7907 #endif
7908 #if defined(TODO_USER_ONLY)
7909 /* PowerPC 440 GRX */
7910 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
7911 #endif
7912 #if defined(TODO_USER_ONLY)
7913 /* PowerPC 440 GX */
7914 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
7915 #endif
7916 #if defined(TODO_USER_ONLY)
7917 /* PowerPC 440 GXa */
7918 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
7919 #endif
7920 #if defined(TODO_USER_ONLY)
7921 /* PowerPC 440 GXb */
7922 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
7923 #endif
7924 #if defined(TODO_USER_ONLY)
7925 /* PowerPC 440 GXc */
7926 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
7927 #endif
7928 #if defined(TODO_USER_ONLY)
7929 /* PowerPC 440 GXf */
7930 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
7931 #endif
7932 #if defined(TODO)
7933 /* PowerPC 440 S */
7934 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
7935 #endif
7936 #if defined(TODO_USER_ONLY)
7937 /* PowerPC 440 SP */
7938 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
7939 #endif
7940 #if defined(TODO_USER_ONLY)
7941 /* PowerPC 440 SP2 */
7942 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
7943 #endif
7944 #if defined(TODO_USER_ONLY)
7945 /* PowerPC 440 SPE */
7946 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
7947 #endif
7948 /* PowerPC 460 family */
7949 #if defined (TODO)
7950 /* Generic PowerPC 464 */
7951 POWERPC_DEF("464", CPU_POWERPC_464, 460),
7952 #endif
7953 /* PowerPC 464 microcontrolers */
7954 #if defined (TODO)
7955 /* PowerPC 464H90 */
7956 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
7957 #endif
7958 #if defined (TODO)
7959 /* PowerPC 464H90F */
7960 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
7961 #endif
7962 /* Freescale embedded PowerPC cores */
7963 /* MPC5xx family (aka RCPU) */
7964 #if defined(TODO_USER_ONLY)
7965 /* Generic MPC5xx core */
7966 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
7967 #endif
7968 #if defined(TODO_USER_ONLY)
7969 /* Codename for MPC5xx core */
7970 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
7971 #endif
7972 /* MPC5xx microcontrollers */
7973 #if defined(TODO_USER_ONLY)
7974 /* MGT560 */
7975 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
7976 #endif
7977 #if defined(TODO_USER_ONLY)
7978 /* MPC509 */
7979 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
7980 #endif
7981 #if defined(TODO_USER_ONLY)
7982 /* MPC533 */
7983 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
7984 #endif
7985 #if defined(TODO_USER_ONLY)
7986 /* MPC534 */
7987 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
7988 #endif
7989 #if defined(TODO_USER_ONLY)
7990 /* MPC555 */
7991 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
7992 #endif
7993 #if defined(TODO_USER_ONLY)
7994 /* MPC556 */
7995 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
7996 #endif
7997 #if defined(TODO_USER_ONLY)
7998 /* MPC560 */
7999 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
8000 #endif
8001 #if defined(TODO_USER_ONLY)
8002 /* MPC561 */
8003 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
8004 #endif
8005 #if defined(TODO_USER_ONLY)
8006 /* MPC562 */
8007 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
8008 #endif
8009 #if defined(TODO_USER_ONLY)
8010 /* MPC563 */
8011 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
8012 #endif
8013 #if defined(TODO_USER_ONLY)
8014 /* MPC564 */
8015 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
8016 #endif
8017 #if defined(TODO_USER_ONLY)
8018 /* MPC565 */
8019 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
8020 #endif
8021 #if defined(TODO_USER_ONLY)
8022 /* MPC566 */
8023 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
8024 #endif
8025 /* MPC8xx family (aka PowerQUICC) */
8026 #if defined(TODO_USER_ONLY)
8027 /* Generic MPC8xx core */
8028 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
8029 #endif
8030 #if defined(TODO_USER_ONLY)
8031 /* Codename for MPC8xx core */
8032 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
8033 #endif
8034 /* MPC8xx microcontrollers */
8035 #if defined(TODO_USER_ONLY)
8036 /* MGT823 */
8037 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
8038 #endif
8039 #if defined(TODO_USER_ONLY)
8040 /* MPC821 */
8041 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
8042 #endif
8043 #if defined(TODO_USER_ONLY)
8044 /* MPC823 */
8045 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
8046 #endif
8047 #if defined(TODO_USER_ONLY)
8048 /* MPC850 */
8049 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
8050 #endif
8051 #if defined(TODO_USER_ONLY)
8052 /* MPC852T */
8053 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
8054 #endif
8055 #if defined(TODO_USER_ONLY)
8056 /* MPC855T */
8057 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
8058 #endif
8059 #if defined(TODO_USER_ONLY)
8060 /* MPC857 */
8061 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
8062 #endif
8063 #if defined(TODO_USER_ONLY)
8064 /* MPC859 */
8065 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
8066 #endif
8067 #if defined(TODO_USER_ONLY)
8068 /* MPC860 */
8069 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
8070 #endif
8071 #if defined(TODO_USER_ONLY)
8072 /* MPC862 */
8073 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
8074 #endif
8075 #if defined(TODO_USER_ONLY)
8076 /* MPC866 */
8077 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
8078 #endif
8079 #if defined(TODO_USER_ONLY)
8080 /* MPC870 */
8081 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
8082 #endif
8083 #if defined(TODO_USER_ONLY)
8084 /* MPC875 */
8085 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
8086 #endif
8087 #if defined(TODO_USER_ONLY)
8088 /* MPC880 */
8089 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
8090 #endif
8091 #if defined(TODO_USER_ONLY)
8092 /* MPC885 */
8093 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
8094 #endif
8095 /* MPC82xx family (aka PowerQUICC-II) */
8096 /* Generic MPC52xx core */
8097 POWERPC_DEF_SVR("MPC52xx",
8098 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
8099 /* Generic MPC82xx core */
8100 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
8101 /* Codename for MPC82xx */
8102 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
8103 /* PowerPC G2 core */
8104 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
8105 /* PowerPC G2 H4 core */
8106 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
8107 /* PowerPC G2 GP core */
8108 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
8109 /* PowerPC G2 LS core */
8110 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
8111 /* PowerPC G2 HiP3 core */
8112 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
8113 /* PowerPC G2 HiP4 core */
8114 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
8115 /* PowerPC MPC603 core */
8116 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
8117 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
8118 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
8119 /* PowerPC G2LE GP core */
8120 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
8121 /* PowerPC G2LE LS core */
8122 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
8123 /* PowerPC G2LE GP1 core */
8124 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
8125 /* PowerPC G2LE GP3 core */
8126 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
8127 /* PowerPC MPC603 microcontrollers */
8128 /* MPC8240 */
8129 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
8130 /* PowerPC G2 microcontrollers */
8131 #if defined(TODO)
8132 /* MPC5121 */
8133 POWERPC_DEF_SVR("MPC5121",
8134 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
8135 #endif
8136 /* MPC5200 */
8137 POWERPC_DEF_SVR("MPC5200",
8138 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
8139 /* MPC5200 v1.0 */
8140 POWERPC_DEF_SVR("MPC5200_v10",
8141 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
8142 /* MPC5200 v1.1 */
8143 POWERPC_DEF_SVR("MPC5200_v11",
8144 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
8145 /* MPC5200 v1.2 */
8146 POWERPC_DEF_SVR("MPC5200_v12",
8147 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
8148 /* MPC5200B */
8149 POWERPC_DEF_SVR("MPC5200B",
8150 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
8151 /* MPC5200B v2.0 */
8152 POWERPC_DEF_SVR("MPC5200B_v20",
8153 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
8154 /* MPC5200B v2.1 */
8155 POWERPC_DEF_SVR("MPC5200B_v21",
8156 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
8157 /* MPC8241 */
8158 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
8159 /* MPC8245 */
8160 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
8161 /* MPC8247 */
8162 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
8163 /* MPC8248 */
8164 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
8165 /* MPC8250 */
8166 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
8167 /* MPC8250 HiP3 */
8168 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
8169 /* MPC8250 HiP4 */
8170 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
8171 /* MPC8255 */
8172 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
8173 /* MPC8255 HiP3 */
8174 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
8175 /* MPC8255 HiP4 */
8176 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
8177 /* MPC8260 */
8178 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
8179 /* MPC8260 HiP3 */
8180 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
8181 /* MPC8260 HiP4 */
8182 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
8183 /* MPC8264 */
8184 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
8185 /* MPC8264 HiP3 */
8186 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
8187 /* MPC8264 HiP4 */
8188 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
8189 /* MPC8265 */
8190 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
8191 /* MPC8265 HiP3 */
8192 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
8193 /* MPC8265 HiP4 */
8194 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
8195 /* MPC8266 */
8196 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
8197 /* MPC8266 HiP3 */
8198 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
8199 /* MPC8266 HiP4 */
8200 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
8201 /* MPC8270 */
8202 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
8203 /* MPC8271 */
8204 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
8205 /* MPC8272 */
8206 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
8207 /* MPC8275 */
8208 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
8209 /* MPC8280 */
8210 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
8211 /* e200 family */
8212 /* Generic PowerPC e200 core */
8213 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
8214 /* Generic MPC55xx core */
8215 #if defined (TODO)
8216 POWERPC_DEF_SVR("MPC55xx",
8217 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
8218 #endif
8219 #if defined (TODO)
8220 /* PowerPC e200z0 core */
8221 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
8222 #endif
8223 #if defined (TODO)
8224 /* PowerPC e200z1 core */
8225 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
8226 #endif
8227 #if defined (TODO)
8228 /* PowerPC e200z3 core */
8229 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
8230 #endif
8231 /* PowerPC e200z5 core */
8232 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
8233 /* PowerPC e200z6 core */
8234 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
8235 /* PowerPC e200 microcontrollers */
8236 #if defined (TODO)
8237 /* MPC5514E */
8238 POWERPC_DEF_SVR("MPC5514E",
8239 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
8240 #endif
8241 #if defined (TODO)
8242 /* MPC5514E v0 */
8243 POWERPC_DEF_SVR("MPC5514E_v0",
8244 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
8245 #endif
8246 #if defined (TODO)
8247 /* MPC5514E v1 */
8248 POWERPC_DEF_SVR("MPC5514E_v1",
8249 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
8250 #endif
8251 #if defined (TODO)
8252 /* MPC5514G */
8253 POWERPC_DEF_SVR("MPC5514G",
8254 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
8255 #endif
8256 #if defined (TODO)
8257 /* MPC5514G v0 */
8258 POWERPC_DEF_SVR("MPC5514G_v0",
8259 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
8260 #endif
8261 #if defined (TODO)
8262 /* MPC5514G v1 */
8263 POWERPC_DEF_SVR("MPC5514G_v1",
8264 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
8265 #endif
8266 #if defined (TODO)
8267 /* MPC5515S */
8268 POWERPC_DEF_SVR("MPC5515S",
8269 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
8270 #endif
8271 #if defined (TODO)
8272 /* MPC5516E */
8273 POWERPC_DEF_SVR("MPC5516E",
8274 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
8275 #endif
8276 #if defined (TODO)
8277 /* MPC5516E v0 */
8278 POWERPC_DEF_SVR("MPC5516E_v0",
8279 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
8280 #endif
8281 #if defined (TODO)
8282 /* MPC5516E v1 */
8283 POWERPC_DEF_SVR("MPC5516E_v1",
8284 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
8285 #endif
8286 #if defined (TODO)
8287 /* MPC5516G */
8288 POWERPC_DEF_SVR("MPC5516G",
8289 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
8290 #endif
8291 #if defined (TODO)
8292 /* MPC5516G v0 */
8293 POWERPC_DEF_SVR("MPC5516G_v0",
8294 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
8295 #endif
8296 #if defined (TODO)
8297 /* MPC5516G v1 */
8298 POWERPC_DEF_SVR("MPC5516G_v1",
8299 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
8300 #endif
8301 #if defined (TODO)
8302 /* MPC5516S */
8303 POWERPC_DEF_SVR("MPC5516S",
8304 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
8305 #endif
8306 #if defined (TODO)
8307 /* MPC5533 */
8308 POWERPC_DEF_SVR("MPC5533",
8309 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
8310 #endif
8311 #if defined (TODO)
8312 /* MPC5534 */
8313 POWERPC_DEF_SVR("MPC5534",
8314 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
8315 #endif
8316 #if defined (TODO)
8317 /* MPC5553 */
8318 POWERPC_DEF_SVR("MPC5553",
8319 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
8320 #endif
8321 #if defined (TODO)
8322 /* MPC5554 */
8323 POWERPC_DEF_SVR("MPC5554",
8324 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
8325 #endif
8326 #if defined (TODO)
8327 /* MPC5561 */
8328 POWERPC_DEF_SVR("MPC5561",
8329 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
8330 #endif
8331 #if defined (TODO)
8332 /* MPC5565 */
8333 POWERPC_DEF_SVR("MPC5565",
8334 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
8335 #endif
8336 #if defined (TODO)
8337 /* MPC5566 */
8338 POWERPC_DEF_SVR("MPC5566",
8339 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
8340 #endif
8341 #if defined (TODO)
8342 /* MPC5567 */
8343 POWERPC_DEF_SVR("MPC5567",
8344 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
8345 #endif
8346 /* e300 family */
8347 /* Generic PowerPC e300 core */
8348 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
8349 /* PowerPC e300c1 core */
8350 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
8351 /* PowerPC e300c2 core */
8352 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
8353 /* PowerPC e300c3 core */
8354 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
8355 /* PowerPC e300c4 core */
8356 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
8357 /* PowerPC e300 microcontrollers */
8358 #if defined (TODO)
8359 /* MPC8313 */
8360 POWERPC_DEF_SVR("MPC8313",
8361 CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300),
8362 #endif
8363 #if defined (TODO)
8364 /* MPC8313E */
8365 POWERPC_DEF_SVR("MPC8313E",
8366 CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300),
8367 #endif
8368 #if defined (TODO)
8369 /* MPC8314 */
8370 POWERPC_DEF_SVR("MPC8314",
8371 CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300),
8372 #endif
8373 #if defined (TODO)
8374 /* MPC8314E */
8375 POWERPC_DEF_SVR("MPC8314E",
8376 CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300),
8377 #endif
8378 #if defined (TODO)
8379 /* MPC8315 */
8380 POWERPC_DEF_SVR("MPC8315",
8381 CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300),
8382 #endif
8383 #if defined (TODO)
8384 /* MPC8315E */
8385 POWERPC_DEF_SVR("MPC8315E",
8386 CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300),
8387 #endif
8388 #if defined (TODO)
8389 /* MPC8321 */
8390 POWERPC_DEF_SVR("MPC8321",
8391 CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300),
8392 #endif
8393 #if defined (TODO)
8394 /* MPC8321E */
8395 POWERPC_DEF_SVR("MPC8321E",
8396 CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300),
8397 #endif
8398 #if defined (TODO)
8399 /* MPC8323 */
8400 POWERPC_DEF_SVR("MPC8323",
8401 CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300),
8402 #endif
8403 #if defined (TODO)
8404 /* MPC8323E */
8405 POWERPC_DEF_SVR("MPC8323E",
8406 CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300),
8407 #endif
8408 /* MPC8343 */
8409 POWERPC_DEF_SVR("MPC8343",
8410 CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300),
8411 /* MPC8343A */
8412 POWERPC_DEF_SVR("MPC8343A",
8413 CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300),
8414 /* MPC8343E */
8415 POWERPC_DEF_SVR("MPC8343E",
8416 CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300),
8417 /* MPC8343EA */
8418 POWERPC_DEF_SVR("MPC8343EA",
8419 CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300),
8420 /* MPC8347 */
8421 POWERPC_DEF_SVR("MPC8347",
8422 CPU_POWERPC_MPC834x, POWERPC_SVR_8347, e300),
8423 /* MPC8347T */
8424 POWERPC_DEF_SVR("MPC8347T",
8425 CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300),
8426 /* MPC8347P */
8427 POWERPC_DEF_SVR("MPC8347P",
8428 CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300),
8429 /* MPC8347A */
8430 POWERPC_DEF_SVR("MPC8347A",
8431 CPU_POWERPC_MPC834x, POWERPC_SVR_8347A, e300),
8432 /* MPC8347AT */
8433 POWERPC_DEF_SVR("MPC8347AT",
8434 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300),
8435 /* MPC8347AP */
8436 POWERPC_DEF_SVR("MPC8347AP",
8437 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300),
8438 /* MPC8347E */
8439 POWERPC_DEF_SVR("MPC8347E",
8440 CPU_POWERPC_MPC834x, POWERPC_SVR_8347E, e300),
8441 /* MPC8347ET */
8442 POWERPC_DEF_SVR("MPC8347ET",
8443 CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300),
8444 /* MPC8343EP */
8445 POWERPC_DEF_SVR("MPC8347EP",
8446 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300),
8447 /* MPC8347EA */
8448 POWERPC_DEF_SVR("MPC8347EA",
8449 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EA, e300),
8450 /* MPC8347EAT */
8451 POWERPC_DEF_SVR("MPC8347EAT",
8452 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300),
8453 /* MPC8343EAP */
8454 POWERPC_DEF_SVR("MPC8347EAP",
8455 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300),
8456 /* MPC8349 */
8457 POWERPC_DEF_SVR("MPC8349",
8458 CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300),
8459 /* MPC8349A */
8460 POWERPC_DEF_SVR("MPC8349A",
8461 CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300),
8462 /* MPC8349E */
8463 POWERPC_DEF_SVR("MPC8349E",
8464 CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300),
8465 /* MPC8349EA */
8466 POWERPC_DEF_SVR("MPC8349EA",
8467 CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300),
8468 #if defined (TODO)
8469 /* MPC8358E */
8470 POWERPC_DEF_SVR("MPC8358E",
8471 CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300),
8472 #endif
8473 #if defined (TODO)
8474 /* MPC8360E */
8475 POWERPC_DEF_SVR("MPC8360E",
8476 CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300),
8477 #endif
8478 /* MPC8377 */
8479 POWERPC_DEF_SVR("MPC8377",
8480 CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300),
8481 /* MPC8377E */
8482 POWERPC_DEF_SVR("MPC8377E",
8483 CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300),
8484 /* MPC8378 */
8485 POWERPC_DEF_SVR("MPC8378",
8486 CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300),
8487 /* MPC8378E */
8488 POWERPC_DEF_SVR("MPC8378E",
8489 CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300),
8490 /* MPC8379 */
8491 POWERPC_DEF_SVR("MPC8379",
8492 CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300),
8493 /* MPC8379E */
8494 POWERPC_DEF_SVR("MPC8379E",
8495 CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300),
8496 /* e500 family */
8497 /* PowerPC e500 core */
8498 POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2),
8499 /* PowerPC e500v1 core */
8500 POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1),
8501 /* PowerPC e500 v1.0 core */
8502 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1),
8503 /* PowerPC e500 v2.0 core */
8504 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1),
8505 /* PowerPC e500v2 core */
8506 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2),
8507 /* PowerPC e500v2 v1.0 core */
8508 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2),
8509 /* PowerPC e500v2 v2.0 core */
8510 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2),
8511 /* PowerPC e500v2 v2.1 core */
8512 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2),
8513 /* PowerPC e500v2 v2.2 core */
8514 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2),
8515 /* PowerPC e500v2 v3.0 core */
8516 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
8517 POWERPC_DEF("e500mc", CPU_POWERPC_e500mc, e500mc),
8518 /* PowerPC e500 microcontrollers */
8519 /* MPC8533 */
8520 POWERPC_DEF_SVR("MPC8533",
8521 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2),
8522 /* MPC8533 v1.0 */
8523 POWERPC_DEF_SVR("MPC8533_v10",
8524 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2),
8525 /* MPC8533 v1.1 */
8526 POWERPC_DEF_SVR("MPC8533_v11",
8527 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2),
8528 /* MPC8533E */
8529 POWERPC_DEF_SVR("MPC8533E",
8530 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2),
8531 /* MPC8533E v1.0 */
8532 POWERPC_DEF_SVR("MPC8533E_v10",
8533 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
8534 POWERPC_DEF_SVR("MPC8533E_v11",
8535 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
8536 /* MPC8540 */
8537 POWERPC_DEF_SVR("MPC8540",
8538 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1),
8539 /* MPC8540 v1.0 */
8540 POWERPC_DEF_SVR("MPC8540_v10",
8541 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1),
8542 /* MPC8540 v2.0 */
8543 POWERPC_DEF_SVR("MPC8540_v20",
8544 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1),
8545 /* MPC8540 v2.1 */
8546 POWERPC_DEF_SVR("MPC8540_v21",
8547 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1),
8548 /* MPC8541 */
8549 POWERPC_DEF_SVR("MPC8541",
8550 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1),
8551 /* MPC8541 v1.0 */
8552 POWERPC_DEF_SVR("MPC8541_v10",
8553 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1),
8554 /* MPC8541 v1.1 */
8555 POWERPC_DEF_SVR("MPC8541_v11",
8556 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1),
8557 /* MPC8541E */
8558 POWERPC_DEF_SVR("MPC8541E",
8559 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1),
8560 /* MPC8541E v1.0 */
8561 POWERPC_DEF_SVR("MPC8541E_v10",
8562 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
8563 /* MPC8541E v1.1 */
8564 POWERPC_DEF_SVR("MPC8541E_v11",
8565 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
8566 /* MPC8543 */
8567 POWERPC_DEF_SVR("MPC8543",
8568 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2),
8569 /* MPC8543 v1.0 */
8570 POWERPC_DEF_SVR("MPC8543_v10",
8571 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2),
8572 /* MPC8543 v1.1 */
8573 POWERPC_DEF_SVR("MPC8543_v11",
8574 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2),
8575 /* MPC8543 v2.0 */
8576 POWERPC_DEF_SVR("MPC8543_v20",
8577 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2),
8578 /* MPC8543 v2.1 */
8579 POWERPC_DEF_SVR("MPC8543_v21",
8580 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2),
8581 /* MPC8543E */
8582 POWERPC_DEF_SVR("MPC8543E",
8583 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2),
8584 /* MPC8543E v1.0 */
8585 POWERPC_DEF_SVR("MPC8543E_v10",
8586 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
8587 /* MPC8543E v1.1 */
8588 POWERPC_DEF_SVR("MPC8543E_v11",
8589 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
8590 /* MPC8543E v2.0 */
8591 POWERPC_DEF_SVR("MPC8543E_v20",
8592 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
8593 /* MPC8543E v2.1 */
8594 POWERPC_DEF_SVR("MPC8543E_v21",
8595 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
8596 /* MPC8544 */
8597 POWERPC_DEF_SVR("MPC8544",
8598 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2),
8599 /* MPC8544 v1.0 */
8600 POWERPC_DEF_SVR("MPC8544_v10",
8601 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2),
8602 /* MPC8544 v1.1 */
8603 POWERPC_DEF_SVR("MPC8544_v11",
8604 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2),
8605 /* MPC8544E */
8606 POWERPC_DEF_SVR("MPC8544E",
8607 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2),
8608 /* MPC8544E v1.0 */
8609 POWERPC_DEF_SVR("MPC8544E_v10",
8610 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
8611 /* MPC8544E v1.1 */
8612 POWERPC_DEF_SVR("MPC8544E_v11",
8613 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
8614 /* MPC8545 */
8615 POWERPC_DEF_SVR("MPC8545",
8616 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2),
8617 /* MPC8545 v2.0 */
8618 POWERPC_DEF_SVR("MPC8545_v20",
8619 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2),
8620 /* MPC8545 v2.1 */
8621 POWERPC_DEF_SVR("MPC8545_v21",
8622 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2),
8623 /* MPC8545E */
8624 POWERPC_DEF_SVR("MPC8545E",
8625 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2),
8626 /* MPC8545E v2.0 */
8627 POWERPC_DEF_SVR("MPC8545E_v20",
8628 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
8629 /* MPC8545E v2.1 */
8630 POWERPC_DEF_SVR("MPC8545E_v21",
8631 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
8632 /* MPC8547E */
8633 POWERPC_DEF_SVR("MPC8547E",
8634 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2),
8635 /* MPC8547E v2.0 */
8636 POWERPC_DEF_SVR("MPC8547E_v20",
8637 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
8638 /* MPC8547E v2.1 */
8639 POWERPC_DEF_SVR("MPC8547E_v21",
8640 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
8641 /* MPC8548 */
8642 POWERPC_DEF_SVR("MPC8548",
8643 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2),
8644 /* MPC8548 v1.0 */
8645 POWERPC_DEF_SVR("MPC8548_v10",
8646 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2),
8647 /* MPC8548 v1.1 */
8648 POWERPC_DEF_SVR("MPC8548_v11",
8649 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2),
8650 /* MPC8548 v2.0 */
8651 POWERPC_DEF_SVR("MPC8548_v20",
8652 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2),
8653 /* MPC8548 v2.1 */
8654 POWERPC_DEF_SVR("MPC8548_v21",
8655 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2),
8656 /* MPC8548E */
8657 POWERPC_DEF_SVR("MPC8548E",
8658 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2),
8659 /* MPC8548E v1.0 */
8660 POWERPC_DEF_SVR("MPC8548E_v10",
8661 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
8662 /* MPC8548E v1.1 */
8663 POWERPC_DEF_SVR("MPC8548E_v11",
8664 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
8665 /* MPC8548E v2.0 */
8666 POWERPC_DEF_SVR("MPC8548E_v20",
8667 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
8668 /* MPC8548E v2.1 */
8669 POWERPC_DEF_SVR("MPC8548E_v21",
8670 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
8671 /* MPC8555 */
8672 POWERPC_DEF_SVR("MPC8555",
8673 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2),
8674 /* MPC8555 v1.0 */
8675 POWERPC_DEF_SVR("MPC8555_v10",
8676 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2),
8677 /* MPC8555 v1.1 */
8678 POWERPC_DEF_SVR("MPC8555_v11",
8679 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2),
8680 /* MPC8555E */
8681 POWERPC_DEF_SVR("MPC8555E",
8682 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2),
8683 /* MPC8555E v1.0 */
8684 POWERPC_DEF_SVR("MPC8555E_v10",
8685 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
8686 /* MPC8555E v1.1 */
8687 POWERPC_DEF_SVR("MPC8555E_v11",
8688 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
8689 /* MPC8560 */
8690 POWERPC_DEF_SVR("MPC8560",
8691 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2),
8692 /* MPC8560 v1.0 */
8693 POWERPC_DEF_SVR("MPC8560_v10",
8694 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2),
8695 /* MPC8560 v2.0 */
8696 POWERPC_DEF_SVR("MPC8560_v20",
8697 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2),
8698 /* MPC8560 v2.1 */
8699 POWERPC_DEF_SVR("MPC8560_v21",
8700 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2),
8701 /* MPC8567 */
8702 POWERPC_DEF_SVR("MPC8567",
8703 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2),
8704 /* MPC8567E */
8705 POWERPC_DEF_SVR("MPC8567E",
8706 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2),
8707 /* MPC8568 */
8708 POWERPC_DEF_SVR("MPC8568",
8709 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2),
8710 /* MPC8568E */
8711 POWERPC_DEF_SVR("MPC8568E",
8712 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2),
8713 /* MPC8572 */
8714 POWERPC_DEF_SVR("MPC8572",
8715 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2),
8716 /* MPC8572E */
8717 POWERPC_DEF_SVR("MPC8572E",
8718 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2),
8719 /* e600 family */
8720 /* PowerPC e600 core */
8721 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
8722 /* PowerPC e600 microcontrollers */
8723 #if defined (TODO)
8724 /* MPC8610 */
8725 POWERPC_DEF_SVR("MPC8610",
8726 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
8727 #endif
8728 /* MPC8641 */
8729 POWERPC_DEF_SVR("MPC8641",
8730 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
8731 /* MPC8641D */
8732 POWERPC_DEF_SVR("MPC8641D",
8733 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
8734 /* 32 bits "classic" PowerPC */
8735 /* PowerPC 6xx family */
8736 /* PowerPC 601 */
8737 POWERPC_DEF("601", CPU_POWERPC_601, 601v),
8738 /* PowerPC 601v0 */
8739 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
8740 /* PowerPC 601v1 */
8741 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
8742 /* PowerPC 601v */
8743 POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
8744 /* PowerPC 601v2 */
8745 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
8746 /* PowerPC 602 */
8747 POWERPC_DEF("602", CPU_POWERPC_602, 602),
8748 /* PowerPC 603 */
8749 POWERPC_DEF("603", CPU_POWERPC_603, 603),
8750 /* Code name for PowerPC 603 */
8751 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
8752 /* PowerPC 603e (aka PID6) */
8753 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
8754 /* Code name for PowerPC 603e */
8755 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
8756 /* PowerPC 603e v1.1 */
8757 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
8758 /* PowerPC 603e v1.2 */
8759 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
8760 /* PowerPC 603e v1.3 */
8761 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
8762 /* PowerPC 603e v1.4 */
8763 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
8764 /* PowerPC 603e v2.2 */
8765 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
8766 /* PowerPC 603e v3 */
8767 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
8768 /* PowerPC 603e v4 */
8769 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
8770 /* PowerPC 603e v4.1 */
8771 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
8772 /* PowerPC 603e (aka PID7) */
8773 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
8774 /* PowerPC 603e7t */
8775 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
8776 /* PowerPC 603e7v */
8777 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
8778 /* Code name for PowerPC 603ev */
8779 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
8780 /* PowerPC 603e7v1 */
8781 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
8782 /* PowerPC 603e7v2 */
8783 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
8784 /* PowerPC 603p (aka PID7v) */
8785 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
8786 /* PowerPC 603r (aka PID7t) */
8787 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
8788 /* Code name for PowerPC 603r */
8789 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
8790 /* PowerPC 604 */
8791 POWERPC_DEF("604", CPU_POWERPC_604, 604),
8792 /* PowerPC 604e (aka PID9) */
8793 POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
8794 /* Code name for PowerPC 604e */
8795 POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
8796 /* PowerPC 604e v1.0 */
8797 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
8798 /* PowerPC 604e v2.2 */
8799 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
8800 /* PowerPC 604e v2.4 */
8801 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
8802 /* PowerPC 604r (aka PIDA) */
8803 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
8804 /* Code name for PowerPC 604r */
8805 POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
8806 #if defined(TODO)
8807 /* PowerPC 604ev */
8808 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
8809 #endif
8810 /* PowerPC 7xx family */
8811 /* Generic PowerPC 740 (G3) */
8812 POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
8813 /* Code name for PowerPC 740 */
8814 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
8815 /* Generic PowerPC 750 (G3) */
8816 POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
8817 /* Code name for PowerPC 750 */
8818 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
8819 /* PowerPC 740/750 is also known as G3 */
8820 POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
8821 /* PowerPC 740 v1.0 (G3) */
8822 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
8823 /* PowerPC 750 v1.0 (G3) */
8824 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
8825 /* PowerPC 740 v2.0 (G3) */
8826 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
8827 /* PowerPC 750 v2.0 (G3) */
8828 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
8829 /* PowerPC 740 v2.1 (G3) */
8830 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
8831 /* PowerPC 750 v2.1 (G3) */
8832 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
8833 /* PowerPC 740 v2.2 (G3) */
8834 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
8835 /* PowerPC 750 v2.2 (G3) */
8836 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
8837 /* PowerPC 740 v3.0 (G3) */
8838 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
8839 /* PowerPC 750 v3.0 (G3) */
8840 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
8841 /* PowerPC 740 v3.1 (G3) */
8842 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
8843 /* PowerPC 750 v3.1 (G3) */
8844 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
8845 /* PowerPC 740E (G3) */
8846 POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
8847 /* PowerPC 750E (G3) */
8848 POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
8849 /* PowerPC 740P (G3) */
8850 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
8851 /* PowerPC 750P (G3) */
8852 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
8853 /* Code name for PowerPC 740P/750P (G3) */
8854 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
8855 /* PowerPC 750CL (G3 embedded) */
8856 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
8857 /* PowerPC 750CL v1.0 */
8858 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
8859 /* PowerPC 750CL v2.0 */
8860 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
8861 /* PowerPC 750CX (G3 embedded) */
8862 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
8863 /* PowerPC 750CX v1.0 (G3 embedded) */
8864 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
8865 /* PowerPC 750CX v2.1 (G3 embedded) */
8866 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
8867 /* PowerPC 750CX v2.1 (G3 embedded) */
8868 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
8869 /* PowerPC 750CX v2.2 (G3 embedded) */
8870 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
8871 /* PowerPC 750CXe (G3 embedded) */
8872 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
8873 /* PowerPC 750CXe v2.1 (G3 embedded) */
8874 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
8875 /* PowerPC 750CXe v2.2 (G3 embedded) */
8876 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
8877 /* PowerPC 750CXe v2.3 (G3 embedded) */
8878 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
8879 /* PowerPC 750CXe v2.4 (G3 embedded) */
8880 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
8881 /* PowerPC 750CXe v2.4b (G3 embedded) */
8882 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
8883 /* PowerPC 750CXe v3.0 (G3 embedded) */
8884 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
8885 /* PowerPC 750CXe v3.1 (G3 embedded) */
8886 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
8887 /* PowerPC 750CXe v3.1b (G3 embedded) */
8888 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
8889 /* PowerPC 750CXr (G3 embedded) */
8890 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
8891 /* PowerPC 750FL (G3 embedded) */
8892 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
8893 /* PowerPC 750FX (G3 embedded) */
8894 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
8895 /* PowerPC 750FX v1.0 (G3 embedded) */
8896 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
8897 /* PowerPC 750FX v2.0 (G3 embedded) */
8898 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
8899 /* PowerPC 750FX v2.1 (G3 embedded) */
8900 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
8901 /* PowerPC 750FX v2.2 (G3 embedded) */
8902 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
8903 /* PowerPC 750FX v2.3 (G3 embedded) */
8904 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
8905 /* PowerPC 750GL (G3 embedded) */
8906 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
8907 /* PowerPC 750GX (G3 embedded) */
8908 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
8909 /* PowerPC 750GX v1.0 (G3 embedded) */
8910 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
8911 /* PowerPC 750GX v1.1 (G3 embedded) */
8912 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
8913 /* PowerPC 750GX v1.2 (G3 embedded) */
8914 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
8915 /* PowerPC 750L (G3 embedded) */
8916 POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
8917 /* Code name for PowerPC 750L (G3 embedded) */
8918 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
8919 /* PowerPC 750L v2.0 (G3 embedded) */
8920 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
8921 /* PowerPC 750L v2.1 (G3 embedded) */
8922 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
8923 /* PowerPC 750L v2.2 (G3 embedded) */
8924 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
8925 /* PowerPC 750L v3.0 (G3 embedded) */
8926 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
8927 /* PowerPC 750L v3.2 (G3 embedded) */
8928 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
8929 /* Generic PowerPC 745 */
8930 POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
8931 /* Generic PowerPC 755 */
8932 POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
8933 /* Code name for PowerPC 745/755 */
8934 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
8935 /* PowerPC 745 v1.0 */
8936 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
8937 /* PowerPC 755 v1.0 */
8938 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
8939 /* PowerPC 745 v1.1 */
8940 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
8941 /* PowerPC 755 v1.1 */
8942 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
8943 /* PowerPC 745 v2.0 */
8944 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
8945 /* PowerPC 755 v2.0 */
8946 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
8947 /* PowerPC 745 v2.1 */
8948 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
8949 /* PowerPC 755 v2.1 */
8950 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
8951 /* PowerPC 745 v2.2 */
8952 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
8953 /* PowerPC 755 v2.2 */
8954 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
8955 /* PowerPC 745 v2.3 */
8956 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
8957 /* PowerPC 755 v2.3 */
8958 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
8959 /* PowerPC 745 v2.4 */
8960 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
8961 /* PowerPC 755 v2.4 */
8962 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
8963 /* PowerPC 745 v2.5 */
8964 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
8965 /* PowerPC 755 v2.5 */
8966 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
8967 /* PowerPC 745 v2.6 */
8968 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
8969 /* PowerPC 755 v2.6 */
8970 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
8971 /* PowerPC 745 v2.7 */
8972 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
8973 /* PowerPC 755 v2.7 */
8974 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
8975 /* PowerPC 745 v2.8 */
8976 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
8977 /* PowerPC 755 v2.8 */
8978 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
8979 #if defined (TODO)
8980 /* PowerPC 745P (G3) */
8981 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
8982 /* PowerPC 755P (G3) */
8983 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
8984 #endif
8985 /* PowerPC 74xx family */
8986 /* PowerPC 7400 (G4) */
8987 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
8988 /* Code name for PowerPC 7400 */
8989 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
8990 /* PowerPC 74xx is also well known as G4 */
8991 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
8992 /* PowerPC 7400 v1.0 (G4) */
8993 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
8994 /* PowerPC 7400 v1.1 (G4) */
8995 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
8996 /* PowerPC 7400 v2.0 (G4) */
8997 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
8998 /* PowerPC 7400 v2.1 (G4) */
8999 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
9000 /* PowerPC 7400 v2.2 (G4) */
9001 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
9002 /* PowerPC 7400 v2.6 (G4) */
9003 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
9004 /* PowerPC 7400 v2.7 (G4) */
9005 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
9006 /* PowerPC 7400 v2.8 (G4) */
9007 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
9008 /* PowerPC 7400 v2.9 (G4) */
9009 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
9010 /* PowerPC 7410 (G4) */
9011 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
9012 /* Code name for PowerPC 7410 */
9013 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
9014 /* PowerPC 7410 v1.0 (G4) */
9015 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
9016 /* PowerPC 7410 v1.1 (G4) */
9017 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
9018 /* PowerPC 7410 v1.2 (G4) */
9019 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
9020 /* PowerPC 7410 v1.3 (G4) */
9021 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
9022 /* PowerPC 7410 v1.4 (G4) */
9023 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
9024 /* PowerPC 7448 (G4) */
9025 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
9026 /* PowerPC 7448 v1.0 (G4) */
9027 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
9028 /* PowerPC 7448 v1.1 (G4) */
9029 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
9030 /* PowerPC 7448 v2.0 (G4) */
9031 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
9032 /* PowerPC 7448 v2.1 (G4) */
9033 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
9034 /* PowerPC 7450 (G4) */
9035 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
9036 /* Code name for PowerPC 7450 */
9037 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
9038 /* PowerPC 7450 v1.0 (G4) */
9039 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
9040 /* PowerPC 7450 v1.1 (G4) */
9041 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
9042 /* PowerPC 7450 v1.2 (G4) */
9043 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
9044 /* PowerPC 7450 v2.0 (G4) */
9045 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
9046 /* PowerPC 7450 v2.1 (G4) */
9047 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
9048 /* PowerPC 7441 (G4) */
9049 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
9050 /* PowerPC 7451 (G4) */
9051 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
9052 /* PowerPC 7441 v2.1 (G4) */
9053 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
9054 /* PowerPC 7441 v2.3 (G4) */
9055 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
9056 /* PowerPC 7451 v2.3 (G4) */
9057 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
9058 /* PowerPC 7441 v2.10 (G4) */
9059 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
9060 /* PowerPC 7451 v2.10 (G4) */
9061 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
9062 /* PowerPC 7445 (G4) */
9063 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
9064 /* PowerPC 7455 (G4) */
9065 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
9066 /* Code name for PowerPC 7445/7455 */
9067 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
9068 /* PowerPC 7445 v1.0 (G4) */
9069 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
9070 /* PowerPC 7455 v1.0 (G4) */
9071 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
9072 /* PowerPC 7445 v2.1 (G4) */
9073 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
9074 /* PowerPC 7455 v2.1 (G4) */
9075 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
9076 /* PowerPC 7445 v3.2 (G4) */
9077 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
9078 /* PowerPC 7455 v3.2 (G4) */
9079 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
9080 /* PowerPC 7445 v3.3 (G4) */
9081 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
9082 /* PowerPC 7455 v3.3 (G4) */
9083 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
9084 /* PowerPC 7445 v3.4 (G4) */
9085 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
9086 /* PowerPC 7455 v3.4 (G4) */
9087 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
9088 /* PowerPC 7447 (G4) */
9089 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
9090 /* PowerPC 7457 (G4) */
9091 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
9092 /* Code name for PowerPC 7447/7457 */
9093 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
9094 /* PowerPC 7447 v1.0 (G4) */
9095 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
9096 /* PowerPC 7457 v1.0 (G4) */
9097 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
9098 /* PowerPC 7447 v1.1 (G4) */
9099 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
9100 /* PowerPC 7457 v1.1 (G4) */
9101 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
9102 /* PowerPC 7457 v1.2 (G4) */
9103 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
9104 /* PowerPC 7447A (G4) */
9105 POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
9106 /* PowerPC 7457A (G4) */
9107 POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
9108 /* PowerPC 7447A v1.0 (G4) */
9109 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
9110 /* PowerPC 7457A v1.0 (G4) */
9111 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
9112 /* Code name for PowerPC 7447A/7457A */
9113 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
9114 /* PowerPC 7447A v1.1 (G4) */
9115 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
9116 /* PowerPC 7457A v1.1 (G4) */
9117 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
9118 /* PowerPC 7447A v1.2 (G4) */
9119 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
9120 /* PowerPC 7457A v1.2 (G4) */
9121 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
9122 /* 64 bits PowerPC */
9123 #if defined (TARGET_PPC64)
9124 /* PowerPC 620 */
9125 POWERPC_DEF("620", CPU_POWERPC_620, 620),
9126 /* Code name for PowerPC 620 */
9127 POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
9128 #if defined (TODO)
9129 /* PowerPC 630 (POWER3) */
9130 POWERPC_DEF("630", CPU_POWERPC_630, 630),
9131 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
9132 /* Code names for POWER3 */
9133 POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
9134 POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
9135 #endif
9136 #if defined (TODO)
9137 /* PowerPC 631 (Power 3+) */
9138 POWERPC_DEF("631", CPU_POWERPC_631, 631),
9139 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
9140 #endif
9141 #if defined (TODO)
9142 /* POWER4 */
9143 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
9144 #endif
9145 #if defined (TODO)
9146 /* POWER4p */
9147 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
9148 #endif
9149 #if defined (TODO)
9150 /* POWER5 */
9151 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
9152 /* POWER5GR */
9153 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
9154 #endif
9155 #if defined (TODO)
9156 /* POWER5+ */
9157 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
9158 /* POWER5GS */
9159 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
9160 #endif
9161 #if defined (TODO)
9162 /* POWER6 */
9163 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
9164 /* POWER6 running in POWER5 mode */
9165 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
9166 /* POWER6A */
9167 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
9168 #endif
9169 /* POWER7 */
9170 POWERPC_DEF("POWER7", CPU_POWERPC_POWER7, POWER7),
9171 POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7),
9172 POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21, POWER7),
9173 POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7),
9174 /* PowerPC 970 */
9175 POWERPC_DEF("970", CPU_POWERPC_970, 970),
9176 /* PowerPC 970FX (G5) */
9177 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
9178 /* PowerPC 970FX v1.0 (G5) */
9179 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
9180 /* PowerPC 970FX v2.0 (G5) */
9181 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
9182 /* PowerPC 970FX v2.1 (G5) */
9183 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
9184 /* PowerPC 970FX v3.0 (G5) */
9185 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
9186 /* PowerPC 970FX v3.1 (G5) */
9187 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
9188 /* PowerPC 970GX (G5) */
9189 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
9190 /* PowerPC 970MP */
9191 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
9192 /* PowerPC 970MP v1.0 */
9193 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
9194 /* PowerPC 970MP v1.1 */
9195 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
9196 #if defined (TODO)
9197 /* PowerPC Cell */
9198 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
9199 #endif
9200 #if defined (TODO)
9201 /* PowerPC Cell v1.0 */
9202 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
9203 #endif
9204 #if defined (TODO)
9205 /* PowerPC Cell v2.0 */
9206 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
9207 #endif
9208 #if defined (TODO)
9209 /* PowerPC Cell v3.0 */
9210 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
9211 #endif
9212 #if defined (TODO)
9213 /* PowerPC Cell v3.1 */
9214 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
9215 #endif
9216 #if defined (TODO)
9217 /* PowerPC Cell v3.2 */
9218 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
9219 #endif
9220 #if defined (TODO)
9221 /* RS64 (Apache/A35) */
9222 /* This one seems to support the whole POWER2 instruction set
9223 * and the PowerPC 64 one.
9224 */
9225 /* What about A10 & A30 ? */
9226 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
9227 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
9228 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
9229 #endif
9230 #if defined (TODO)
9231 /* RS64-II (NorthStar/A50) */
9232 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
9233 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
9234 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
9235 #endif
9236 #if defined (TODO)
9237 /* RS64-III (Pulsar) */
9238 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
9239 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
9240 #endif
9241 #if defined (TODO)
9242 /* RS64-IV (IceStar/IStar/SStar) */
9243 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
9244 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
9245 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
9246 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
9247 #endif
9248 #endif /* defined (TARGET_PPC64) */
9249 /* POWER */
9250 #if defined (TODO)
9251 /* Original POWER */
9252 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
9253 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
9254 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
9255 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
9256 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
9257 #endif
9258 #if defined (TODO)
9259 /* POWER2 */
9260 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
9261 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
9262 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
9263 #endif
9264 /* PA semi cores */
9265 #if defined (TODO)
9266 /* PA PA6T */
9267 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
9268 #endif
9269 /* Generic PowerPCs */
9270 #if defined (TARGET_PPC64)
9271 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
9272 #endif
9273 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
9274 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
9275 /* Fallback */
9276 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
9277 };
9278
9279 /*****************************************************************************/
9280 /* Generic CPU instantiation routine */
9281 static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
9282 {
9283 #if !defined(CONFIG_USER_ONLY)
9284 int i;
9285
9286 env->irq_inputs = NULL;
9287 /* Set all exception vectors to an invalid address */
9288 for (i = 0; i < POWERPC_EXCP_NB; i++)
9289 env->excp_vectors[i] = (target_ulong)(-1ULL);
9290 env->hreset_excp_prefix = 0x00000000;
9291 env->ivor_mask = 0x00000000;
9292 env->ivpr_mask = 0x00000000;
9293 /* Default MMU definitions */
9294 env->nb_BATs = 0;
9295 env->nb_tlb = 0;
9296 env->nb_ways = 0;
9297 env->tlb_type = TLB_NONE;
9298 #endif
9299 /* Register SPR common to all PowerPC implementations */
9300 gen_spr_generic(env);
9301 spr_register(env, SPR_PVR, "PVR",
9302 /* Linux permits userspace to read PVR */
9303 #if defined(CONFIG_LINUX_USER)
9304 &spr_read_generic,
9305 #else
9306 SPR_NOACCESS,
9307 #endif
9308 SPR_NOACCESS,
9309 &spr_read_generic, SPR_NOACCESS,
9310 def->pvr);
9311 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
9312 if (def->svr != POWERPC_SVR_NONE) {
9313 if (def->svr & POWERPC_SVR_E500) {
9314 spr_register(env, SPR_E500_SVR, "SVR",
9315 SPR_NOACCESS, SPR_NOACCESS,
9316 &spr_read_generic, SPR_NOACCESS,
9317 def->svr & ~POWERPC_SVR_E500);
9318 } else {
9319 spr_register(env, SPR_SVR, "SVR",
9320 SPR_NOACCESS, SPR_NOACCESS,
9321 &spr_read_generic, SPR_NOACCESS,
9322 def->svr);
9323 }
9324 }
9325 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
9326 (*def->init_proc)(env);
9327 #if !defined(CONFIG_USER_ONLY)
9328 env->excp_prefix = env->hreset_excp_prefix;
9329 #endif
9330 /* MSR bits & flags consistency checks */
9331 if (env->msr_mask & (1 << 25)) {
9332 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9333 case POWERPC_FLAG_SPE:
9334 case POWERPC_FLAG_VRE:
9335 break;
9336 default:
9337 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9338 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9339 exit(1);
9340 }
9341 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9342 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9343 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9344 exit(1);
9345 }
9346 if (env->msr_mask & (1 << 17)) {
9347 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9348 case POWERPC_FLAG_TGPR:
9349 case POWERPC_FLAG_CE:
9350 break;
9351 default:
9352 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9353 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9354 exit(1);
9355 }
9356 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9357 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9358 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9359 exit(1);
9360 }
9361 if (env->msr_mask & (1 << 10)) {
9362 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9363 POWERPC_FLAG_UBLE)) {
9364 case POWERPC_FLAG_SE:
9365 case POWERPC_FLAG_DWE:
9366 case POWERPC_FLAG_UBLE:
9367 break;
9368 default:
9369 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9370 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9371 "POWERPC_FLAG_UBLE\n");
9372 exit(1);
9373 }
9374 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9375 POWERPC_FLAG_UBLE)) {
9376 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9377 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9378 "POWERPC_FLAG_UBLE\n");
9379 exit(1);
9380 }
9381 if (env->msr_mask & (1 << 9)) {
9382 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9383 case POWERPC_FLAG_BE:
9384 case POWERPC_FLAG_DE:
9385 break;
9386 default:
9387 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9388 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9389 exit(1);
9390 }
9391 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9392 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9393 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9394 exit(1);
9395 }
9396 if (env->msr_mask & (1 << 2)) {
9397 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9398 case POWERPC_FLAG_PX:
9399 case POWERPC_FLAG_PMM:
9400 break;
9401 default:
9402 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9403 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9404 exit(1);
9405 }
9406 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9407 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9408 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9409 exit(1);
9410 }
9411 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9412 fprintf(stderr, "PowerPC flags inconsistency\n"
9413 "Should define the time-base and decrementer clock source\n");
9414 exit(1);
9415 }
9416 /* Allocate TLBs buffer when needed */
9417 #if !defined(CONFIG_USER_ONLY)
9418 if (env->nb_tlb != 0) {
9419 int nb_tlb = env->nb_tlb;
9420 if (env->id_tlbs != 0)
9421 nb_tlb *= 2;
9422 switch (env->tlb_type) {
9423 case TLB_6XX:
9424 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
9425 break;
9426 case TLB_EMB:
9427 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
9428 break;
9429 case TLB_MAS:
9430 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
9431 break;
9432 }
9433 /* Pre-compute some useful values */
9434 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9435 }
9436 if (env->irq_inputs == NULL) {
9437 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
9438 " Attempt Qemu to crash very soon !\n");
9439 }
9440 #endif
9441 if (env->check_pow == NULL) {
9442 fprintf(stderr, "WARNING: no power management check handler "
9443 "registered.\n"
9444 " Attempt Qemu to crash very soon !\n");
9445 }
9446 }
9447
9448 #if defined(PPC_DUMP_CPU)
9449 static void dump_ppc_sprs (CPUPPCState *env)
9450 {
9451 ppc_spr_t *spr;
9452 #if !defined(CONFIG_USER_ONLY)
9453 uint32_t sr, sw;
9454 #endif
9455 uint32_t ur, uw;
9456 int i, j, n;
9457
9458 printf("Special purpose registers:\n");
9459 for (i = 0; i < 32; i++) {
9460 for (j = 0; j < 32; j++) {
9461 n = (i << 5) | j;
9462 spr = &env->spr_cb[n];
9463 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9464 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9465 #if !defined(CONFIG_USER_ONLY)
9466 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9467 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9468 if (sw || sr || uw || ur) {
9469 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9470 (i << 5) | j, (i << 5) | j, spr->name,
9471 sw ? 'w' : '-', sr ? 'r' : '-',
9472 uw ? 'w' : '-', ur ? 'r' : '-');
9473 }
9474 #else
9475 if (uw || ur) {
9476 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9477 (i << 5) | j, (i << 5) | j, spr->name,
9478 uw ? 'w' : '-', ur ? 'r' : '-');
9479 }
9480 #endif
9481 }
9482 }
9483 fflush(stdout);
9484 fflush(stderr);
9485 }
9486 #endif
9487
9488 /*****************************************************************************/
9489 #include <stdlib.h>
9490 #include <string.h>
9491
9492 /* Opcode types */
9493 enum {
9494 PPC_DIRECT = 0, /* Opcode routine */
9495 PPC_INDIRECT = 1, /* Indirect opcode table */
9496 };
9497
9498 static inline int is_indirect_opcode (void *handler)
9499 {
9500 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
9501 }
9502
9503 static inline opc_handler_t **ind_table(void *handler)
9504 {
9505 return (opc_handler_t **)((unsigned long)handler & ~3);
9506 }
9507
9508 /* Instruction table creation */
9509 /* Opcodes tables creation */
9510 static void fill_new_table (opc_handler_t **table, int len)
9511 {
9512 int i;
9513
9514 for (i = 0; i < len; i++)
9515 table[i] = &invalid_handler;
9516 }
9517
9518 static int create_new_table (opc_handler_t **table, unsigned char idx)
9519 {
9520 opc_handler_t **tmp;
9521
9522 tmp = malloc(0x20 * sizeof(opc_handler_t));
9523 fill_new_table(tmp, 0x20);
9524 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
9525
9526 return 0;
9527 }
9528
9529 static int insert_in_table (opc_handler_t **table, unsigned char idx,
9530 opc_handler_t *handler)
9531 {
9532 if (table[idx] != &invalid_handler)
9533 return -1;
9534 table[idx] = handler;
9535
9536 return 0;
9537 }
9538
9539 static int register_direct_insn (opc_handler_t **ppc_opcodes,
9540 unsigned char idx, opc_handler_t *handler)
9541 {
9542 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9543 printf("*** ERROR: opcode %02x already assigned in main "
9544 "opcode table\n", idx);
9545 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9546 printf(" Registered handler '%s' - new handler '%s'\n",
9547 ppc_opcodes[idx]->oname, handler->oname);
9548 #endif
9549 return -1;
9550 }
9551
9552 return 0;
9553 }
9554
9555 static int register_ind_in_table (opc_handler_t **table,
9556 unsigned char idx1, unsigned char idx2,
9557 opc_handler_t *handler)
9558 {
9559 if (table[idx1] == &invalid_handler) {
9560 if (create_new_table(table, idx1) < 0) {
9561 printf("*** ERROR: unable to create indirect table "
9562 "idx=%02x\n", idx1);
9563 return -1;
9564 }
9565 } else {
9566 if (!is_indirect_opcode(table[idx1])) {
9567 printf("*** ERROR: idx %02x already assigned to a direct "
9568 "opcode\n", idx1);
9569 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9570 printf(" Registered handler '%s' - new handler '%s'\n",
9571 ind_table(table[idx1])[idx2]->oname, handler->oname);
9572 #endif
9573 return -1;
9574 }
9575 }
9576 if (handler != NULL &&
9577 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9578 printf("*** ERROR: opcode %02x already assigned in "
9579 "opcode table %02x\n", idx2, idx1);
9580 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9581 printf(" Registered handler '%s' - new handler '%s'\n",
9582 ind_table(table[idx1])[idx2]->oname, handler->oname);
9583 #endif
9584 return -1;
9585 }
9586
9587 return 0;
9588 }
9589
9590 static int register_ind_insn (opc_handler_t **ppc_opcodes,
9591 unsigned char idx1, unsigned char idx2,
9592 opc_handler_t *handler)
9593 {
9594 int ret;
9595
9596 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9597
9598 return ret;
9599 }
9600
9601 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
9602 unsigned char idx1, unsigned char idx2,
9603 unsigned char idx3, opc_handler_t *handler)
9604 {
9605 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9606 printf("*** ERROR: unable to join indirect table idx "
9607 "[%02x-%02x]\n", idx1, idx2);
9608 return -1;
9609 }
9610 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9611 handler) < 0) {
9612 printf("*** ERROR: unable to insert opcode "
9613 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9614 return -1;
9615 }
9616
9617 return 0;
9618 }
9619
9620 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
9621 {
9622 if (insn->opc2 != 0xFF) {
9623 if (insn->opc3 != 0xFF) {
9624 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9625 insn->opc3, &insn->handler) < 0)
9626 return -1;
9627 } else {
9628 if (register_ind_insn(ppc_opcodes, insn->opc1,
9629 insn->opc2, &insn->handler) < 0)
9630 return -1;
9631 }
9632 } else {
9633 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9634 return -1;
9635 }
9636
9637 return 0;
9638 }
9639
9640 static int test_opcode_table (opc_handler_t **table, int len)
9641 {
9642 int i, count, tmp;
9643
9644 for (i = 0, count = 0; i < len; i++) {
9645 /* Consistency fixup */
9646 if (table[i] == NULL)
9647 table[i] = &invalid_handler;
9648 if (table[i] != &invalid_handler) {
9649 if (is_indirect_opcode(table[i])) {
9650 tmp = test_opcode_table(ind_table(table[i]), 0x20);
9651 if (tmp == 0) {
9652 free(table[i]);
9653 table[i] = &invalid_handler;
9654 } else {
9655 count++;
9656 }
9657 } else {
9658 count++;
9659 }
9660 }
9661 }
9662
9663 return count;
9664 }
9665
9666 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
9667 {
9668 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9669 printf("*** WARNING: no opcode defined !\n");
9670 }
9671
9672 /*****************************************************************************/
9673 static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
9674 {
9675 opcode_t *opc;
9676
9677 fill_new_table(env->opcodes, 0x40);
9678 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
9679 if (((opc->handler.type & def->insns_flags) != 0) ||
9680 ((opc->handler.type2 & def->insns_flags2) != 0)) {
9681 if (register_insn(env->opcodes, opc) < 0) {
9682 printf("*** ERROR initializing PowerPC instruction "
9683 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9684 opc->opc3);
9685 return -1;
9686 }
9687 }
9688 }
9689 fix_opcode_tables(env->opcodes);
9690 fflush(stdout);
9691 fflush(stderr);
9692
9693 return 0;
9694 }
9695
9696 #if defined(PPC_DUMP_CPU)
9697 static void dump_ppc_insns (CPUPPCState *env)
9698 {
9699 opc_handler_t **table, *handler;
9700 const char *p, *q;
9701 uint8_t opc1, opc2, opc3;
9702
9703 printf("Instructions set:\n");
9704 /* opc1 is 6 bits long */
9705 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9706 table = env->opcodes;
9707 handler = table[opc1];
9708 if (is_indirect_opcode(handler)) {
9709 /* opc2 is 5 bits long */
9710 for (opc2 = 0; opc2 < 0x20; opc2++) {
9711 table = env->opcodes;
9712 handler = env->opcodes[opc1];
9713 table = ind_table(handler);
9714 handler = table[opc2];
9715 if (is_indirect_opcode(handler)) {
9716 table = ind_table(handler);
9717 /* opc3 is 5 bits long */
9718 for (opc3 = 0; opc3 < 0x20; opc3++) {
9719 handler = table[opc3];
9720 if (handler->handler != &gen_invalid) {
9721 /* Special hack to properly dump SPE insns */
9722 p = strchr(handler->oname, '_');
9723 if (p == NULL) {
9724 printf("INSN: %02x %02x %02x (%02d %04d) : "
9725 "%s\n",
9726 opc1, opc2, opc3, opc1,
9727 (opc3 << 5) | opc2,
9728 handler->oname);
9729 } else {
9730 q = "speundef";
9731 if ((p - handler->oname) != strlen(q) ||
9732 memcmp(handler->oname, q, strlen(q)) != 0) {
9733 /* First instruction */
9734 printf("INSN: %02x %02x %02x (%02d %04d) : "
9735 "%.*s\n",
9736 opc1, opc2 << 1, opc3, opc1,
9737 (opc3 << 6) | (opc2 << 1),
9738 (int)(p - handler->oname),
9739 handler->oname);
9740 }
9741 if (strcmp(p + 1, q) != 0) {
9742 /* Second instruction */
9743 printf("INSN: %02x %02x %02x (%02d %04d) : "
9744 "%s\n",
9745 opc1, (opc2 << 1) | 1, opc3, opc1,
9746 (opc3 << 6) | (opc2 << 1) | 1,
9747 p + 1);
9748 }
9749 }
9750 }
9751 }
9752 } else {
9753 if (handler->handler != &gen_invalid) {
9754 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9755 opc1, opc2, opc1, opc2, handler->oname);
9756 }
9757 }
9758 }
9759 } else {
9760 if (handler->handler != &gen_invalid) {
9761 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9762 opc1, opc1, handler->oname);
9763 }
9764 }
9765 }
9766 }
9767 #endif
9768
9769 static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9770 {
9771 if (n < 32) {
9772 stfq_p(mem_buf, env->fpr[n]);
9773 return 8;
9774 }
9775 if (n == 32) {
9776 stl_p(mem_buf, env->fpscr);
9777 return 4;
9778 }
9779 return 0;
9780 }
9781
9782 static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9783 {
9784 if (n < 32) {
9785 env->fpr[n] = ldfq_p(mem_buf);
9786 return 8;
9787 }
9788 if (n == 32) {
9789 /* FPSCR not implemented */
9790 return 4;
9791 }
9792 return 0;
9793 }
9794
9795 static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9796 {
9797 if (n < 32) {
9798 #ifdef HOST_WORDS_BIGENDIAN
9799 stq_p(mem_buf, env->avr[n].u64[0]);
9800 stq_p(mem_buf+8, env->avr[n].u64[1]);
9801 #else
9802 stq_p(mem_buf, env->avr[n].u64[1]);
9803 stq_p(mem_buf+8, env->avr[n].u64[0]);
9804 #endif
9805 return 16;
9806 }
9807 if (n == 32) {
9808 stl_p(mem_buf, env->vscr);
9809 return 4;
9810 }
9811 if (n == 33) {
9812 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9813 return 4;
9814 }
9815 return 0;
9816 }
9817
9818 static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9819 {
9820 if (n < 32) {
9821 #ifdef HOST_WORDS_BIGENDIAN
9822 env->avr[n].u64[0] = ldq_p(mem_buf);
9823 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9824 #else
9825 env->avr[n].u64[1] = ldq_p(mem_buf);
9826 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9827 #endif
9828 return 16;
9829 }
9830 if (n == 32) {
9831 env->vscr = ldl_p(mem_buf);
9832 return 4;
9833 }
9834 if (n == 33) {
9835 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9836 return 4;
9837 }
9838 return 0;
9839 }
9840
9841 static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9842 {
9843 if (n < 32) {
9844 #if defined(TARGET_PPC64)
9845 stl_p(mem_buf, env->gpr[n] >> 32);
9846 #else
9847 stl_p(mem_buf, env->gprh[n]);
9848 #endif
9849 return 4;
9850 }
9851 if (n == 32) {
9852 stq_p(mem_buf, env->spe_acc);
9853 return 8;
9854 }
9855 if (n == 33) {
9856 stl_p(mem_buf, env->spe_fscr);
9857 return 4;
9858 }
9859 return 0;
9860 }
9861
9862 static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9863 {
9864 if (n < 32) {
9865 #if defined(TARGET_PPC64)
9866 target_ulong lo = (uint32_t)env->gpr[n];
9867 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9868 env->gpr[n] = lo | hi;
9869 #else
9870 env->gprh[n] = ldl_p(mem_buf);
9871 #endif
9872 return 4;
9873 }
9874 if (n == 32) {
9875 env->spe_acc = ldq_p(mem_buf);
9876 return 8;
9877 }
9878 if (n == 33) {
9879 env->spe_fscr = ldl_p(mem_buf);
9880 return 4;
9881 }
9882 return 0;
9883 }
9884
9885 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
9886 {
9887 env->msr_mask = def->msr_mask;
9888 env->mmu_model = def->mmu_model;
9889 env->excp_model = def->excp_model;
9890 env->bus_model = def->bus_model;
9891 env->insns_flags = def->insns_flags;
9892 env->insns_flags2 = def->insns_flags2;
9893 if (!kvm_enabled()) {
9894 /* TCG doesn't (yet) emulate some groups of instructions that
9895 * are implemented on some otherwise supported CPUs (e.g. VSX
9896 * and decimal floating point instructions on POWER7). We
9897 * remove unsupported instruction groups from the cpu state's
9898 * instruction masks and hope the guest can cope. For at
9899 * least the pseries machine, the unavailability of these
9900 * instructions can be advertise to the guest via the device
9901 * tree.
9902 *
9903 * FIXME: we should have a similar masking for CPU features
9904 * not accessible under KVM, but so far, there aren't any of
9905 * those. */
9906 env->insns_flags &= PPC_TCG_INSNS;
9907 env->insns_flags2 &= PPC_TCG_INSNS2;
9908 }
9909 env->flags = def->flags;
9910 env->bfd_mach = def->bfd_mach;
9911 env->check_pow = def->check_pow;
9912 if (create_ppc_opcodes(env, def) < 0)
9913 return -1;
9914 init_ppc_proc(env, def);
9915
9916 if (def->insns_flags & PPC_FLOAT) {
9917 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9918 33, "power-fpu.xml", 0);
9919 }
9920 if (def->insns_flags & PPC_ALTIVEC) {
9921 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9922 34, "power-altivec.xml", 0);
9923 }
9924 if (def->insns_flags & PPC_SPE) {
9925 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
9926 34, "power-spe.xml", 0);
9927 }
9928
9929 #if defined(PPC_DUMP_CPU)
9930 {
9931 const char *mmu_model, *excp_model, *bus_model;
9932 switch (env->mmu_model) {
9933 case POWERPC_MMU_32B:
9934 mmu_model = "PowerPC 32";
9935 break;
9936 case POWERPC_MMU_SOFT_6xx:
9937 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9938 break;
9939 case POWERPC_MMU_SOFT_74xx:
9940 mmu_model = "PowerPC 74xx with software driven TLBs";
9941 break;
9942 case POWERPC_MMU_SOFT_4xx:
9943 mmu_model = "PowerPC 4xx with software driven TLBs";
9944 break;
9945 case POWERPC_MMU_SOFT_4xx_Z:
9946 mmu_model = "PowerPC 4xx with software driven TLBs "
9947 "and zones protections";
9948 break;
9949 case POWERPC_MMU_REAL:
9950 mmu_model = "PowerPC real mode only";
9951 break;
9952 case POWERPC_MMU_MPC8xx:
9953 mmu_model = "PowerPC MPC8xx";
9954 break;
9955 case POWERPC_MMU_BOOKE:
9956 mmu_model = "PowerPC BookE";
9957 break;
9958 case POWERPC_MMU_BOOKE206:
9959 mmu_model = "PowerPC BookE 2.06";
9960 break;
9961 case POWERPC_MMU_601:
9962 mmu_model = "PowerPC 601";
9963 break;
9964 #if defined (TARGET_PPC64)
9965 case POWERPC_MMU_64B:
9966 mmu_model = "PowerPC 64";
9967 break;
9968 case POWERPC_MMU_620:
9969 mmu_model = "PowerPC 620";
9970 break;
9971 #endif
9972 default:
9973 mmu_model = "Unknown or invalid";
9974 break;
9975 }
9976 switch (env->excp_model) {
9977 case POWERPC_EXCP_STD:
9978 excp_model = "PowerPC";
9979 break;
9980 case POWERPC_EXCP_40x:
9981 excp_model = "PowerPC 40x";
9982 break;
9983 case POWERPC_EXCP_601:
9984 excp_model = "PowerPC 601";
9985 break;
9986 case POWERPC_EXCP_602:
9987 excp_model = "PowerPC 602";
9988 break;
9989 case POWERPC_EXCP_603:
9990 excp_model = "PowerPC 603";
9991 break;
9992 case POWERPC_EXCP_603E:
9993 excp_model = "PowerPC 603e";
9994 break;
9995 case POWERPC_EXCP_604:
9996 excp_model = "PowerPC 604";
9997 break;
9998 case POWERPC_EXCP_7x0:
9999 excp_model = "PowerPC 740/750";
10000 break;
10001 case POWERPC_EXCP_7x5:
10002 excp_model = "PowerPC 745/755";
10003 break;
10004 case POWERPC_EXCP_74xx:
10005 excp_model = "PowerPC 74xx";
10006 break;
10007 case POWERPC_EXCP_BOOKE:
10008 excp_model = "PowerPC BookE";
10009 break;
10010 #if defined (TARGET_PPC64)
10011 case POWERPC_EXCP_970:
10012 excp_model = "PowerPC 970";
10013 break;
10014 #endif
10015 default:
10016 excp_model = "Unknown or invalid";
10017 break;
10018 }
10019 switch (env->bus_model) {
10020 case PPC_FLAGS_INPUT_6xx:
10021 bus_model = "PowerPC 6xx";
10022 break;
10023 case PPC_FLAGS_INPUT_BookE:
10024 bus_model = "PowerPC BookE";
10025 break;
10026 case PPC_FLAGS_INPUT_405:
10027 bus_model = "PowerPC 405";
10028 break;
10029 case PPC_FLAGS_INPUT_401:
10030 bus_model = "PowerPC 401/403";
10031 break;
10032 case PPC_FLAGS_INPUT_RCPU:
10033 bus_model = "RCPU / MPC8xx";
10034 break;
10035 #if defined (TARGET_PPC64)
10036 case PPC_FLAGS_INPUT_970:
10037 bus_model = "PowerPC 970";
10038 break;
10039 #endif
10040 default:
10041 bus_model = "Unknown or invalid";
10042 break;
10043 }
10044 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
10045 " MMU model : %s\n",
10046 def->name, def->pvr, def->msr_mask, mmu_model);
10047 #if !defined(CONFIG_USER_ONLY)
10048 if (env->tlb != NULL) {
10049 printf(" %d %s TLB in %d ways\n",
10050 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
10051 env->nb_ways);
10052 }
10053 #endif
10054 printf(" Exceptions model : %s\n"
10055 " Bus model : %s\n",
10056 excp_model, bus_model);
10057 printf(" MSR features :\n");
10058 if (env->flags & POWERPC_FLAG_SPE)
10059 printf(" signal processing engine enable"
10060 "\n");
10061 else if (env->flags & POWERPC_FLAG_VRE)
10062 printf(" vector processor enable\n");
10063 if (env->flags & POWERPC_FLAG_TGPR)
10064 printf(" temporary GPRs\n");
10065 else if (env->flags & POWERPC_FLAG_CE)
10066 printf(" critical input enable\n");
10067 if (env->flags & POWERPC_FLAG_SE)
10068 printf(" single-step trace mode\n");
10069 else if (env->flags & POWERPC_FLAG_DWE)
10070 printf(" debug wait enable\n");
10071 else if (env->flags & POWERPC_FLAG_UBLE)
10072 printf(" user BTB lock enable\n");
10073 if (env->flags & POWERPC_FLAG_BE)
10074 printf(" branch-step trace mode\n");
10075 else if (env->flags & POWERPC_FLAG_DE)
10076 printf(" debug interrupt enable\n");
10077 if (env->flags & POWERPC_FLAG_PX)
10078 printf(" inclusive protection\n");
10079 else if (env->flags & POWERPC_FLAG_PMM)
10080 printf(" performance monitor mark\n");
10081 if (env->flags == POWERPC_FLAG_NONE)
10082 printf(" none\n");
10083 printf(" Time-base/decrementer clock source: %s\n",
10084 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
10085 }
10086 dump_ppc_insns(env);
10087 dump_ppc_sprs(env);
10088 fflush(stdout);
10089 #endif
10090
10091 return 0;
10092 }
10093
10094 static bool ppc_cpu_usable(const ppc_def_t *def)
10095 {
10096 #if defined(TARGET_PPCEMB)
10097 /* When using the ppcemb target, we only support 440 style cores */
10098 if (def->mmu_model != POWERPC_MMU_BOOKE) {
10099 return false;
10100 }
10101 #endif
10102
10103 return true;
10104 }
10105
10106 const ppc_def_t *ppc_find_by_pvr(uint32_t pvr)
10107 {
10108 int i;
10109
10110 for (i = 0; i < ARRAY_SIZE(ppc_defs); i++) {
10111 if (!ppc_cpu_usable(&ppc_defs[i])) {
10112 continue;
10113 }
10114
10115 /* If we have an exact match, we're done */
10116 if (pvr == ppc_defs[i].pvr) {
10117 return &ppc_defs[i];
10118 }
10119 }
10120
10121 return NULL;
10122 }
10123
10124 #include <ctype.h>
10125
10126 const ppc_def_t *cpu_ppc_find_by_name (const char *name)
10127 {
10128 const ppc_def_t *ret;
10129 const char *p;
10130 int i, max, len;
10131
10132 if (kvm_enabled() && (strcasecmp(name, "host") == 0)) {
10133 return kvmppc_host_cpu_def();
10134 }
10135
10136 /* Check if the given name is a PVR */
10137 len = strlen(name);
10138 if (len == 10 && name[0] == '0' && name[1] == 'x') {
10139 p = name + 2;
10140 goto check_pvr;
10141 } else if (len == 8) {
10142 p = name;
10143 check_pvr:
10144 for (i = 0; i < 8; i++) {
10145 if (!qemu_isxdigit(*p++))
10146 break;
10147 }
10148 if (i == 8)
10149 return ppc_find_by_pvr(strtoul(name, NULL, 16));
10150 }
10151 ret = NULL;
10152 max = ARRAY_SIZE(ppc_defs);
10153 for (i = 0; i < max; i++) {
10154 if (!ppc_cpu_usable(&ppc_defs[i])) {
10155 continue;
10156 }
10157
10158 if (strcasecmp(name, ppc_defs[i].name) == 0) {
10159 ret = &ppc_defs[i];
10160 break;
10161 }
10162 }
10163
10164 return ret;
10165 }
10166
10167 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
10168 {
10169 int i, max;
10170
10171 max = ARRAY_SIZE(ppc_defs);
10172 for (i = 0; i < max; i++) {
10173 if (!ppc_cpu_usable(&ppc_defs[i])) {
10174 continue;
10175 }
10176
10177 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
10178 ppc_defs[i].name, ppc_defs[i].pvr);
10179 }
10180 }
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