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More PowerPC definitions, from POWER 2.04 specifications and misc sources.
[mirror_qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
26 //#define PPC_DUMP_CPU
27 //#define PPC_DEBUG_SPR
28 //#define PPC_DEBUG_IRQ
29
30 struct ppc_def_t {
31 const unsigned char *name;
32 uint32_t pvr;
33 uint32_t pvr_mask;
34 uint64_t insns_flags;
35 uint32_t flags;
36 uint64_t msr_mask;
37 };
38
39 /* For user-mode emulation, we don't emulate any IRQ controller */
40 #if defined(CONFIG_USER_ONLY)
41 #define PPC_IRQ_INIT_FN(name) \
42 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
43 { \
44 }
45 #else
46 #define PPC_IRQ_INIT_FN(name) \
47 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
48 #endif
49 PPC_IRQ_INIT_FN(405);
50 PPC_IRQ_INIT_FN(6xx);
51 PPC_IRQ_INIT_FN(970);
52
53 /* Generic callbacks:
54 * do nothing but store/retrieve spr value
55 */
56 #ifdef PPC_DUMP_SPR_ACCESSES
57 static void spr_read_generic (void *opaque, int sprn)
58 {
59 gen_op_load_dump_spr(sprn);
60 }
61
62 static void spr_write_generic (void *opaque, int sprn)
63 {
64 gen_op_store_dump_spr(sprn);
65 }
66 #else
67 static void spr_read_generic (void *opaque, int sprn)
68 {
69 gen_op_load_spr(sprn);
70 }
71
72 static void spr_write_generic (void *opaque, int sprn)
73 {
74 gen_op_store_spr(sprn);
75 }
76 #endif
77
78 #if !defined(CONFIG_USER_ONLY)
79 static void spr_write_clear (void *opaque, int sprn)
80 {
81 gen_op_mask_spr(sprn);
82 }
83 #endif
84
85 /* SPR common to all PowerPC */
86 /* XER */
87 static void spr_read_xer (void *opaque, int sprn)
88 {
89 gen_op_load_xer();
90 }
91
92 static void spr_write_xer (void *opaque, int sprn)
93 {
94 gen_op_store_xer();
95 }
96
97 /* LR */
98 static void spr_read_lr (void *opaque, int sprn)
99 {
100 gen_op_load_lr();
101 }
102
103 static void spr_write_lr (void *opaque, int sprn)
104 {
105 gen_op_store_lr();
106 }
107
108 /* CTR */
109 static void spr_read_ctr (void *opaque, int sprn)
110 {
111 gen_op_load_ctr();
112 }
113
114 static void spr_write_ctr (void *opaque, int sprn)
115 {
116 gen_op_store_ctr();
117 }
118
119 /* User read access to SPR */
120 /* USPRx */
121 /* UMMCRx */
122 /* UPMCx */
123 /* USIA */
124 /* UDECR */
125 static void spr_read_ureg (void *opaque, int sprn)
126 {
127 gen_op_load_spr(sprn + 0x10);
128 }
129
130 /* SPR common to all non-embedded PowerPC */
131 /* DECR */
132 #if !defined(CONFIG_USER_ONLY)
133 static void spr_read_decr (void *opaque, int sprn)
134 {
135 gen_op_load_decr();
136 }
137
138 static void spr_write_decr (void *opaque, int sprn)
139 {
140 gen_op_store_decr();
141 }
142 #endif
143
144 /* SPR common to all non-embedded PowerPC, except 601 */
145 /* Time base */
146 static void spr_read_tbl (void *opaque, int sprn)
147 {
148 gen_op_load_tbl();
149 }
150
151 static void spr_read_tbu (void *opaque, int sprn)
152 {
153 gen_op_load_tbu();
154 }
155
156 #if !defined(CONFIG_USER_ONLY)
157 static void spr_write_tbl (void *opaque, int sprn)
158 {
159 gen_op_store_tbl();
160 }
161
162 static void spr_write_tbu (void *opaque, int sprn)
163 {
164 gen_op_store_tbu();
165 }
166 #endif
167
168 #if !defined(CONFIG_USER_ONLY)
169 /* IBAT0U...IBAT0U */
170 /* IBAT0L...IBAT7L */
171 static void spr_read_ibat (void *opaque, int sprn)
172 {
173 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
174 }
175
176 static void spr_read_ibat_h (void *opaque, int sprn)
177 {
178 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
179 }
180
181 static void spr_write_ibatu (void *opaque, int sprn)
182 {
183 DisasContext *ctx = opaque;
184
185 gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
186 RET_STOP(ctx);
187 }
188
189 static void spr_write_ibatu_h (void *opaque, int sprn)
190 {
191 DisasContext *ctx = opaque;
192
193 gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
194 RET_STOP(ctx);
195 }
196
197 static void spr_write_ibatl (void *opaque, int sprn)
198 {
199 DisasContext *ctx = opaque;
200
201 gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
202 RET_STOP(ctx);
203 }
204
205 static void spr_write_ibatl_h (void *opaque, int sprn)
206 {
207 DisasContext *ctx = opaque;
208
209 gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
210 RET_STOP(ctx);
211 }
212
213 /* DBAT0U...DBAT7U */
214 /* DBAT0L...DBAT7L */
215 static void spr_read_dbat (void *opaque, int sprn)
216 {
217 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
218 }
219
220 static void spr_read_dbat_h (void *opaque, int sprn)
221 {
222 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
223 }
224
225 static void spr_write_dbatu (void *opaque, int sprn)
226 {
227 DisasContext *ctx = opaque;
228
229 gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
230 RET_STOP(ctx);
231 }
232
233 static void spr_write_dbatu_h (void *opaque, int sprn)
234 {
235 DisasContext *ctx = opaque;
236
237 gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
238 RET_STOP(ctx);
239 }
240
241 static void spr_write_dbatl (void *opaque, int sprn)
242 {
243 DisasContext *ctx = opaque;
244
245 gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
246 RET_STOP(ctx);
247 }
248
249 static void spr_write_dbatl_h (void *opaque, int sprn)
250 {
251 DisasContext *ctx = opaque;
252
253 gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
254 RET_STOP(ctx);
255 }
256
257 /* SDR1 */
258 static void spr_read_sdr1 (void *opaque, int sprn)
259 {
260 gen_op_load_sdr1();
261 }
262
263 static void spr_write_sdr1 (void *opaque, int sprn)
264 {
265 DisasContext *ctx = opaque;
266
267 gen_op_store_sdr1();
268 RET_STOP(ctx);
269 }
270
271 /* 64 bits PowerPC specific SPRs */
272 /* ASR */
273 /* Currently unused */
274 #if 0 && defined(TARGET_PPC64)
275 static void spr_read_asr (void *opaque, int sprn)
276 {
277 gen_op_load_asr();
278 }
279
280 static void spr_write_asr (void *opaque, int sprn)
281 {
282 DisasContext *ctx = opaque;
283
284 gen_op_store_asr();
285 RET_STOP(ctx);
286 }
287 #endif
288 #endif /* !defined(CONFIG_USER_ONLY) */
289
290 /* PowerPC 601 specific registers */
291 /* RTC */
292 static void spr_read_601_rtcl (void *opaque, int sprn)
293 {
294 gen_op_load_601_rtcl();
295 }
296
297 static void spr_read_601_rtcu (void *opaque, int sprn)
298 {
299 gen_op_load_601_rtcu();
300 }
301
302 #if !defined(CONFIG_USER_ONLY)
303 static void spr_write_601_rtcu (void *opaque, int sprn)
304 {
305 gen_op_store_601_rtcu();
306 }
307
308 static void spr_write_601_rtcl (void *opaque, int sprn)
309 {
310 gen_op_store_601_rtcl();
311 }
312 #endif
313
314 /* Unified bats */
315 #if !defined(CONFIG_USER_ONLY)
316 static void spr_read_601_ubat (void *opaque, int sprn)
317 {
318 gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
319 }
320
321 static void spr_write_601_ubatu (void *opaque, int sprn)
322 {
323 DisasContext *ctx = opaque;
324
325 gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
326 RET_STOP(ctx);
327 }
328
329 static void spr_write_601_ubatl (void *opaque, int sprn)
330 {
331 DisasContext *ctx = opaque;
332
333 gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
334 RET_STOP(ctx);
335 }
336 #endif
337
338 /* PowerPC 40x specific registers */
339 #if !defined(CONFIG_USER_ONLY)
340 static void spr_read_40x_pit (void *opaque, int sprn)
341 {
342 gen_op_load_40x_pit();
343 }
344
345 static void spr_write_40x_pit (void *opaque, int sprn)
346 {
347 gen_op_store_40x_pit();
348 }
349
350 static void spr_write_40x_dbcr0 (void *opaque, int sprn)
351 {
352 DisasContext *ctx = opaque;
353
354 gen_op_store_40x_dbcr0();
355 /* We must stop translation as we may have rebooted */
356 RET_STOP(ctx);
357 }
358
359 static void spr_write_40x_sler (void *opaque, int sprn)
360 {
361 DisasContext *ctx = opaque;
362
363 gen_op_store_40x_sler();
364 /* We must stop the translation as we may have changed
365 * some regions endianness
366 */
367 RET_STOP(ctx);
368 }
369
370 static void spr_write_booke_tcr (void *opaque, int sprn)
371 {
372 gen_op_store_booke_tcr();
373 }
374
375 static void spr_write_booke_tsr (void *opaque, int sprn)
376 {
377 gen_op_store_booke_tsr();
378 }
379 #endif
380
381 /* PowerPC 403 specific registers */
382 /* PBL1 / PBU1 / PBL2 / PBU2 */
383 #if !defined(CONFIG_USER_ONLY)
384 static void spr_read_403_pbr (void *opaque, int sprn)
385 {
386 gen_op_load_403_pb(sprn - SPR_403_PBL1);
387 }
388
389 static void spr_write_403_pbr (void *opaque, int sprn)
390 {
391 DisasContext *ctx = opaque;
392
393 gen_op_store_403_pb(sprn - SPR_403_PBL1);
394 RET_STOP(ctx);
395 }
396
397 static void spr_write_pir (void *opaque, int sprn)
398 {
399 gen_op_store_pir();
400 }
401 #endif
402
403 #if defined(CONFIG_USER_ONLY)
404 #define spr_register(env, num, name, uea_read, uea_write, \
405 oea_read, oea_write, initial_value) \
406 do { \
407 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
408 } while (0)
409 static inline void _spr_register (CPUPPCState *env, int num,
410 const unsigned char *name,
411 void (*uea_read)(void *opaque, int sprn),
412 void (*uea_write)(void *opaque, int sprn),
413 target_ulong initial_value)
414 #else
415 static inline void spr_register (CPUPPCState *env, int num,
416 const unsigned char *name,
417 void (*uea_read)(void *opaque, int sprn),
418 void (*uea_write)(void *opaque, int sprn),
419 void (*oea_read)(void *opaque, int sprn),
420 void (*oea_write)(void *opaque, int sprn),
421 target_ulong initial_value)
422 #endif
423 {
424 ppc_spr_t *spr;
425
426 spr = &env->spr_cb[num];
427 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
428 #if !defined(CONFIG_USER_ONLY)
429 spr->oea_read != NULL || spr->oea_write != NULL ||
430 #endif
431 spr->uea_read != NULL || spr->uea_write != NULL) {
432 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
433 exit(1);
434 }
435 #if defined(PPC_DEBUG_SPR)
436 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
437 initial_value);
438 #endif
439 spr->name = name;
440 spr->uea_read = uea_read;
441 spr->uea_write = uea_write;
442 #if !defined(CONFIG_USER_ONLY)
443 spr->oea_read = oea_read;
444 spr->oea_write = oea_write;
445 #endif
446 env->spr[num] = initial_value;
447 }
448
449 /* Generic PowerPC SPRs */
450 static void gen_spr_generic (CPUPPCState *env)
451 {
452 /* Integer processing */
453 spr_register(env, SPR_XER, "XER",
454 &spr_read_xer, &spr_write_xer,
455 &spr_read_xer, &spr_write_xer,
456 0x00000000);
457 /* Branch contol */
458 spr_register(env, SPR_LR, "LR",
459 &spr_read_lr, &spr_write_lr,
460 &spr_read_lr, &spr_write_lr,
461 0x00000000);
462 spr_register(env, SPR_CTR, "CTR",
463 &spr_read_ctr, &spr_write_ctr,
464 &spr_read_ctr, &spr_write_ctr,
465 0x00000000);
466 /* Interrupt processing */
467 spr_register(env, SPR_SRR0, "SRR0",
468 SPR_NOACCESS, SPR_NOACCESS,
469 &spr_read_generic, &spr_write_generic,
470 0x00000000);
471 spr_register(env, SPR_SRR1, "SRR1",
472 SPR_NOACCESS, SPR_NOACCESS,
473 &spr_read_generic, &spr_write_generic,
474 0x00000000);
475 /* Processor control */
476 spr_register(env, SPR_SPRG0, "SPRG0",
477 SPR_NOACCESS, SPR_NOACCESS,
478 &spr_read_generic, &spr_write_generic,
479 0x00000000);
480 spr_register(env, SPR_SPRG1, "SPRG1",
481 SPR_NOACCESS, SPR_NOACCESS,
482 &spr_read_generic, &spr_write_generic,
483 0x00000000);
484 spr_register(env, SPR_SPRG2, "SPRG2",
485 SPR_NOACCESS, SPR_NOACCESS,
486 &spr_read_generic, &spr_write_generic,
487 0x00000000);
488 spr_register(env, SPR_SPRG3, "SPRG3",
489 SPR_NOACCESS, SPR_NOACCESS,
490 &spr_read_generic, &spr_write_generic,
491 0x00000000);
492 }
493
494 /* SPR common to all non-embedded PowerPC, including 601 */
495 static void gen_spr_ne_601 (CPUPPCState *env)
496 {
497 /* Exception processing */
498 spr_register(env, SPR_DSISR, "DSISR",
499 SPR_NOACCESS, SPR_NOACCESS,
500 &spr_read_generic, &spr_write_generic,
501 0x00000000);
502 spr_register(env, SPR_DAR, "DAR",
503 SPR_NOACCESS, SPR_NOACCESS,
504 &spr_read_generic, &spr_write_generic,
505 0x00000000);
506 /* Timer */
507 spr_register(env, SPR_DECR, "DECR",
508 SPR_NOACCESS, SPR_NOACCESS,
509 &spr_read_decr, &spr_write_decr,
510 0x00000000);
511 /* Memory management */
512 spr_register(env, SPR_SDR1, "SDR1",
513 SPR_NOACCESS, SPR_NOACCESS,
514 &spr_read_sdr1, &spr_write_sdr1,
515 0x00000000);
516 }
517
518 /* BATs 0-3 */
519 static void gen_low_BATs (CPUPPCState *env)
520 {
521 spr_register(env, SPR_IBAT0U, "IBAT0U",
522 SPR_NOACCESS, SPR_NOACCESS,
523 &spr_read_ibat, &spr_write_ibatu,
524 0x00000000);
525 spr_register(env, SPR_IBAT0L, "IBAT0L",
526 SPR_NOACCESS, SPR_NOACCESS,
527 &spr_read_ibat, &spr_write_ibatl,
528 0x00000000);
529 spr_register(env, SPR_IBAT1U, "IBAT1U",
530 SPR_NOACCESS, SPR_NOACCESS,
531 &spr_read_ibat, &spr_write_ibatu,
532 0x00000000);
533 spr_register(env, SPR_IBAT1L, "IBAT1L",
534 SPR_NOACCESS, SPR_NOACCESS,
535 &spr_read_ibat, &spr_write_ibatl,
536 0x00000000);
537 spr_register(env, SPR_IBAT2U, "IBAT2U",
538 SPR_NOACCESS, SPR_NOACCESS,
539 &spr_read_ibat, &spr_write_ibatu,
540 0x00000000);
541 spr_register(env, SPR_IBAT2L, "IBAT2L",
542 SPR_NOACCESS, SPR_NOACCESS,
543 &spr_read_ibat, &spr_write_ibatl,
544 0x00000000);
545 spr_register(env, SPR_IBAT3U, "IBAT3U",
546 SPR_NOACCESS, SPR_NOACCESS,
547 &spr_read_ibat, &spr_write_ibatu,
548 0x00000000);
549 spr_register(env, SPR_IBAT3L, "IBAT3L",
550 SPR_NOACCESS, SPR_NOACCESS,
551 &spr_read_ibat, &spr_write_ibatl,
552 0x00000000);
553 spr_register(env, SPR_DBAT0U, "DBAT0U",
554 SPR_NOACCESS, SPR_NOACCESS,
555 &spr_read_dbat, &spr_write_dbatu,
556 0x00000000);
557 spr_register(env, SPR_DBAT0L, "DBAT0L",
558 SPR_NOACCESS, SPR_NOACCESS,
559 &spr_read_dbat, &spr_write_dbatl,
560 0x00000000);
561 spr_register(env, SPR_DBAT1U, "DBAT1U",
562 SPR_NOACCESS, SPR_NOACCESS,
563 &spr_read_dbat, &spr_write_dbatu,
564 0x00000000);
565 spr_register(env, SPR_DBAT1L, "DBAT1L",
566 SPR_NOACCESS, SPR_NOACCESS,
567 &spr_read_dbat, &spr_write_dbatl,
568 0x00000000);
569 spr_register(env, SPR_DBAT2U, "DBAT2U",
570 SPR_NOACCESS, SPR_NOACCESS,
571 &spr_read_dbat, &spr_write_dbatu,
572 0x00000000);
573 spr_register(env, SPR_DBAT2L, "DBAT2L",
574 SPR_NOACCESS, SPR_NOACCESS,
575 &spr_read_dbat, &spr_write_dbatl,
576 0x00000000);
577 spr_register(env, SPR_DBAT3U, "DBAT3U",
578 SPR_NOACCESS, SPR_NOACCESS,
579 &spr_read_dbat, &spr_write_dbatu,
580 0x00000000);
581 spr_register(env, SPR_DBAT3L, "DBAT3L",
582 SPR_NOACCESS, SPR_NOACCESS,
583 &spr_read_dbat, &spr_write_dbatl,
584 0x00000000);
585 env->nb_BATs = 4;
586 }
587
588 /* BATs 4-7 */
589 static void gen_high_BATs (CPUPPCState *env)
590 {
591 spr_register(env, SPR_IBAT4U, "IBAT4U",
592 SPR_NOACCESS, SPR_NOACCESS,
593 &spr_read_ibat_h, &spr_write_ibatu_h,
594 0x00000000);
595 spr_register(env, SPR_IBAT4L, "IBAT4L",
596 SPR_NOACCESS, SPR_NOACCESS,
597 &spr_read_ibat_h, &spr_write_ibatl_h,
598 0x00000000);
599 spr_register(env, SPR_IBAT5U, "IBAT5U",
600 SPR_NOACCESS, SPR_NOACCESS,
601 &spr_read_ibat_h, &spr_write_ibatu_h,
602 0x00000000);
603 spr_register(env, SPR_IBAT5L, "IBAT5L",
604 SPR_NOACCESS, SPR_NOACCESS,
605 &spr_read_ibat_h, &spr_write_ibatl_h,
606 0x00000000);
607 spr_register(env, SPR_IBAT6U, "IBAT6U",
608 SPR_NOACCESS, SPR_NOACCESS,
609 &spr_read_ibat_h, &spr_write_ibatu_h,
610 0x00000000);
611 spr_register(env, SPR_IBAT6L, "IBAT6L",
612 SPR_NOACCESS, SPR_NOACCESS,
613 &spr_read_ibat_h, &spr_write_ibatl_h,
614 0x00000000);
615 spr_register(env, SPR_IBAT7U, "IBAT7U",
616 SPR_NOACCESS, SPR_NOACCESS,
617 &spr_read_ibat_h, &spr_write_ibatu_h,
618 0x00000000);
619 spr_register(env, SPR_IBAT7L, "IBAT7L",
620 SPR_NOACCESS, SPR_NOACCESS,
621 &spr_read_ibat_h, &spr_write_ibatl_h,
622 0x00000000);
623 spr_register(env, SPR_DBAT4U, "DBAT4U",
624 SPR_NOACCESS, SPR_NOACCESS,
625 &spr_read_dbat_h, &spr_write_dbatu_h,
626 0x00000000);
627 spr_register(env, SPR_DBAT4L, "DBAT4L",
628 SPR_NOACCESS, SPR_NOACCESS,
629 &spr_read_dbat_h, &spr_write_dbatl_h,
630 0x00000000);
631 spr_register(env, SPR_DBAT5U, "DBAT5U",
632 SPR_NOACCESS, SPR_NOACCESS,
633 &spr_read_dbat_h, &spr_write_dbatu_h,
634 0x00000000);
635 spr_register(env, SPR_DBAT5L, "DBAT5L",
636 SPR_NOACCESS, SPR_NOACCESS,
637 &spr_read_dbat_h, &spr_write_dbatl_h,
638 0x00000000);
639 spr_register(env, SPR_DBAT6U, "DBAT6U",
640 SPR_NOACCESS, SPR_NOACCESS,
641 &spr_read_dbat_h, &spr_write_dbatu_h,
642 0x00000000);
643 spr_register(env, SPR_DBAT6L, "DBAT6L",
644 SPR_NOACCESS, SPR_NOACCESS,
645 &spr_read_dbat_h, &spr_write_dbatl_h,
646 0x00000000);
647 spr_register(env, SPR_DBAT7U, "DBAT7U",
648 SPR_NOACCESS, SPR_NOACCESS,
649 &spr_read_dbat_h, &spr_write_dbatu_h,
650 0x00000000);
651 spr_register(env, SPR_DBAT7L, "DBAT7L",
652 SPR_NOACCESS, SPR_NOACCESS,
653 &spr_read_dbat_h, &spr_write_dbatl_h,
654 0x00000000);
655 env->nb_BATs = 8;
656 }
657
658 /* Generic PowerPC time base */
659 static void gen_tbl (CPUPPCState *env)
660 {
661 spr_register(env, SPR_VTBL, "TBL",
662 &spr_read_tbl, SPR_NOACCESS,
663 &spr_read_tbl, SPR_NOACCESS,
664 0x00000000);
665 spr_register(env, SPR_TBL, "TBL",
666 SPR_NOACCESS, SPR_NOACCESS,
667 SPR_NOACCESS, &spr_write_tbl,
668 0x00000000);
669 spr_register(env, SPR_VTBU, "TBU",
670 &spr_read_tbu, SPR_NOACCESS,
671 &spr_read_tbu, SPR_NOACCESS,
672 0x00000000);
673 spr_register(env, SPR_TBU, "TBU",
674 SPR_NOACCESS, SPR_NOACCESS,
675 SPR_NOACCESS, &spr_write_tbu,
676 0x00000000);
677 }
678
679 /* Softare table search registers */
680 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
681 {
682 env->nb_tlb = nb_tlbs;
683 env->nb_ways = nb_ways;
684 env->id_tlbs = 1;
685 spr_register(env, SPR_DMISS, "DMISS",
686 SPR_NOACCESS, SPR_NOACCESS,
687 &spr_read_generic, SPR_NOACCESS,
688 0x00000000);
689 spr_register(env, SPR_DCMP, "DCMP",
690 SPR_NOACCESS, SPR_NOACCESS,
691 &spr_read_generic, SPR_NOACCESS,
692 0x00000000);
693 spr_register(env, SPR_HASH1, "HASH1",
694 SPR_NOACCESS, SPR_NOACCESS,
695 &spr_read_generic, SPR_NOACCESS,
696 0x00000000);
697 spr_register(env, SPR_HASH2, "HASH2",
698 SPR_NOACCESS, SPR_NOACCESS,
699 &spr_read_generic, SPR_NOACCESS,
700 0x00000000);
701 spr_register(env, SPR_IMISS, "IMISS",
702 SPR_NOACCESS, SPR_NOACCESS,
703 &spr_read_generic, SPR_NOACCESS,
704 0x00000000);
705 spr_register(env, SPR_ICMP, "ICMP",
706 SPR_NOACCESS, SPR_NOACCESS,
707 &spr_read_generic, SPR_NOACCESS,
708 0x00000000);
709 spr_register(env, SPR_RPA, "RPA",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_generic, &spr_write_generic,
712 0x00000000);
713 }
714
715 /* SPR common to MPC755 and G2 */
716 static void gen_spr_G2_755 (CPUPPCState *env)
717 {
718 /* SGPRs */
719 spr_register(env, SPR_SPRG4, "SPRG4",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_generic, &spr_write_generic,
722 0x00000000);
723 spr_register(env, SPR_SPRG5, "SPRG5",
724 SPR_NOACCESS, SPR_NOACCESS,
725 &spr_read_generic, &spr_write_generic,
726 0x00000000);
727 spr_register(env, SPR_SPRG6, "SPRG6",
728 SPR_NOACCESS, SPR_NOACCESS,
729 &spr_read_generic, &spr_write_generic,
730 0x00000000);
731 spr_register(env, SPR_SPRG7, "SPRG7",
732 SPR_NOACCESS, SPR_NOACCESS,
733 &spr_read_generic, &spr_write_generic,
734 0x00000000);
735 /* External access control */
736 /* XXX : not implemented */
737 spr_register(env, SPR_EAR, "EAR",
738 SPR_NOACCESS, SPR_NOACCESS,
739 &spr_read_generic, &spr_write_generic,
740 0x00000000);
741 }
742
743 /* SPR common to all 7xx PowerPC implementations */
744 static void gen_spr_7xx (CPUPPCState *env)
745 {
746 /* Breakpoints */
747 /* XXX : not implemented */
748 spr_register(env, SPR_DABR, "DABR",
749 SPR_NOACCESS, SPR_NOACCESS,
750 &spr_read_generic, &spr_write_generic,
751 0x00000000);
752 /* XXX : not implemented */
753 spr_register(env, SPR_IABR, "IABR",
754 SPR_NOACCESS, SPR_NOACCESS,
755 &spr_read_generic, &spr_write_generic,
756 0x00000000);
757 /* Cache management */
758 /* XXX : not implemented */
759 spr_register(env, SPR_ICTC, "ICTC",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_generic, &spr_write_generic,
762 0x00000000);
763 /* XXX : not implemented */
764 spr_register(env, SPR_L2CR, "L2CR",
765 SPR_NOACCESS, SPR_NOACCESS,
766 &spr_read_generic, &spr_write_generic,
767 0x00000000);
768 /* Performance monitors */
769 /* XXX : not implemented */
770 spr_register(env, SPR_MMCR0, "MMCR0",
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_generic, &spr_write_generic,
773 0x00000000);
774 /* XXX : not implemented */
775 spr_register(env, SPR_MMCR1, "MMCR1",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_generic, &spr_write_generic,
778 0x00000000);
779 /* XXX : not implemented */
780 spr_register(env, SPR_PMC1, "PMC1",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_generic, &spr_write_generic,
783 0x00000000);
784 /* XXX : not implemented */
785 spr_register(env, SPR_PMC2, "PMC2",
786 SPR_NOACCESS, SPR_NOACCESS,
787 &spr_read_generic, &spr_write_generic,
788 0x00000000);
789 /* XXX : not implemented */
790 spr_register(env, SPR_PMC3, "PMC3",
791 SPR_NOACCESS, SPR_NOACCESS,
792 &spr_read_generic, &spr_write_generic,
793 0x00000000);
794 /* XXX : not implemented */
795 spr_register(env, SPR_PMC4, "PMC4",
796 SPR_NOACCESS, SPR_NOACCESS,
797 &spr_read_generic, &spr_write_generic,
798 0x00000000);
799 /* XXX : not implemented */
800 spr_register(env, SPR_SIA, "SIA",
801 SPR_NOACCESS, SPR_NOACCESS,
802 &spr_read_generic, SPR_NOACCESS,
803 0x00000000);
804 spr_register(env, SPR_UMMCR0, "UMMCR0",
805 &spr_read_ureg, SPR_NOACCESS,
806 &spr_read_ureg, SPR_NOACCESS,
807 0x00000000);
808 spr_register(env, SPR_UMMCR1, "UMMCR1",
809 &spr_read_ureg, SPR_NOACCESS,
810 &spr_read_ureg, SPR_NOACCESS,
811 0x00000000);
812 spr_register(env, SPR_UPMC1, "UPMC1",
813 &spr_read_ureg, SPR_NOACCESS,
814 &spr_read_ureg, SPR_NOACCESS,
815 0x00000000);
816 spr_register(env, SPR_UPMC2, "UPMC2",
817 &spr_read_ureg, SPR_NOACCESS,
818 &spr_read_ureg, SPR_NOACCESS,
819 0x00000000);
820 spr_register(env, SPR_UPMC3, "UPMC3",
821 &spr_read_ureg, SPR_NOACCESS,
822 &spr_read_ureg, SPR_NOACCESS,
823 0x00000000);
824 spr_register(env, SPR_UPMC4, "UPMC4",
825 &spr_read_ureg, SPR_NOACCESS,
826 &spr_read_ureg, SPR_NOACCESS,
827 0x00000000);
828 spr_register(env, SPR_USIA, "USIA",
829 &spr_read_ureg, SPR_NOACCESS,
830 &spr_read_ureg, SPR_NOACCESS,
831 0x00000000);
832 /* Thermal management */
833 /* XXX : not implemented */
834 spr_register(env, SPR_THRM1, "THRM1",
835 SPR_NOACCESS, SPR_NOACCESS,
836 &spr_read_generic, &spr_write_generic,
837 0x00000000);
838 /* XXX : not implemented */
839 spr_register(env, SPR_THRM2, "THRM2",
840 SPR_NOACCESS, SPR_NOACCESS,
841 &spr_read_generic, &spr_write_generic,
842 0x00000000);
843 /* XXX : not implemented */
844 spr_register(env, SPR_THRM3, "THRM3",
845 SPR_NOACCESS, SPR_NOACCESS,
846 &spr_read_generic, &spr_write_generic,
847 0x00000000);
848 /* External access control */
849 /* XXX : not implemented */
850 spr_register(env, SPR_EAR, "EAR",
851 SPR_NOACCESS, SPR_NOACCESS,
852 &spr_read_generic, &spr_write_generic,
853 0x00000000);
854 }
855
856 /* SPR specific to PowerPC 604 implementation */
857 static void gen_spr_604 (CPUPPCState *env)
858 {
859 /* Processor identification */
860 spr_register(env, SPR_PIR, "PIR",
861 SPR_NOACCESS, SPR_NOACCESS,
862 &spr_read_generic, &spr_write_pir,
863 0x00000000);
864 /* Breakpoints */
865 /* XXX : not implemented */
866 spr_register(env, SPR_IABR, "IABR",
867 SPR_NOACCESS, SPR_NOACCESS,
868 &spr_read_generic, &spr_write_generic,
869 0x00000000);
870 /* XXX : not implemented */
871 spr_register(env, SPR_DABR, "DABR",
872 SPR_NOACCESS, SPR_NOACCESS,
873 &spr_read_generic, &spr_write_generic,
874 0x00000000);
875 /* Performance counters */
876 /* XXX : not implemented */
877 spr_register(env, SPR_MMCR0, "MMCR0",
878 SPR_NOACCESS, SPR_NOACCESS,
879 &spr_read_generic, &spr_write_generic,
880 0x00000000);
881 /* XXX : not implemented */
882 spr_register(env, SPR_MMCR1, "MMCR1",
883 SPR_NOACCESS, SPR_NOACCESS,
884 &spr_read_generic, &spr_write_generic,
885 0x00000000);
886 /* XXX : not implemented */
887 spr_register(env, SPR_PMC1, "PMC1",
888 SPR_NOACCESS, SPR_NOACCESS,
889 &spr_read_generic, &spr_write_generic,
890 0x00000000);
891 /* XXX : not implemented */
892 spr_register(env, SPR_PMC2, "PMC2",
893 SPR_NOACCESS, SPR_NOACCESS,
894 &spr_read_generic, &spr_write_generic,
895 0x00000000);
896 /* XXX : not implemented */
897 spr_register(env, SPR_PMC3, "PMC3",
898 SPR_NOACCESS, SPR_NOACCESS,
899 &spr_read_generic, &spr_write_generic,
900 0x00000000);
901 /* XXX : not implemented */
902 spr_register(env, SPR_PMC4, "PMC4",
903 SPR_NOACCESS, SPR_NOACCESS,
904 &spr_read_generic, &spr_write_generic,
905 0x00000000);
906 /* XXX : not implemented */
907 spr_register(env, SPR_SIA, "SIA",
908 SPR_NOACCESS, SPR_NOACCESS,
909 &spr_read_generic, SPR_NOACCESS,
910 0x00000000);
911 /* XXX : not implemented */
912 spr_register(env, SPR_SDA, "SDA",
913 SPR_NOACCESS, SPR_NOACCESS,
914 &spr_read_generic, SPR_NOACCESS,
915 0x00000000);
916 /* External access control */
917 /* XXX : not implemented */
918 spr_register(env, SPR_EAR, "EAR",
919 SPR_NOACCESS, SPR_NOACCESS,
920 &spr_read_generic, &spr_write_generic,
921 0x00000000);
922 }
923
924 /* SPR specific to PowerPC 603 implementation */
925 static void gen_spr_603 (CPUPPCState *env)
926 {
927 /* External access control */
928 /* XXX : not implemented */
929 spr_register(env, SPR_EAR, "EAR",
930 SPR_NOACCESS, SPR_NOACCESS,
931 &spr_read_generic, &spr_write_generic,
932 0x00000000);
933 }
934
935 /* SPR specific to PowerPC G2 implementation */
936 static void gen_spr_G2 (CPUPPCState *env)
937 {
938 /* Memory base address */
939 /* MBAR */
940 spr_register(env, SPR_MBAR, "MBAR",
941 SPR_NOACCESS, SPR_NOACCESS,
942 &spr_read_generic, &spr_write_generic,
943 0x00000000);
944 /* System version register */
945 /* SVR */
946 spr_register(env, SPR_SVR, "SVR",
947 SPR_NOACCESS, SPR_NOACCESS,
948 &spr_read_generic, SPR_NOACCESS,
949 0x00000000);
950 /* Exception processing */
951 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
952 SPR_NOACCESS, SPR_NOACCESS,
953 &spr_read_generic, &spr_write_generic,
954 0x00000000);
955 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
956 SPR_NOACCESS, SPR_NOACCESS,
957 &spr_read_generic, &spr_write_generic,
958 0x00000000);
959 /* Breakpoints */
960 /* XXX : not implemented */
961 spr_register(env, SPR_DABR, "DABR",
962 SPR_NOACCESS, SPR_NOACCESS,
963 &spr_read_generic, &spr_write_generic,
964 0x00000000);
965 /* XXX : not implemented */
966 spr_register(env, SPR_DABR2, "DABR2",
967 SPR_NOACCESS, SPR_NOACCESS,
968 &spr_read_generic, &spr_write_generic,
969 0x00000000);
970 /* XXX : not implemented */
971 spr_register(env, SPR_IABR, "IABR",
972 SPR_NOACCESS, SPR_NOACCESS,
973 &spr_read_generic, &spr_write_generic,
974 0x00000000);
975 /* XXX : not implemented */
976 spr_register(env, SPR_IABR2, "IABR2",
977 SPR_NOACCESS, SPR_NOACCESS,
978 &spr_read_generic, &spr_write_generic,
979 0x00000000);
980 /* XXX : not implemented */
981 spr_register(env, SPR_IBCR, "IBCR",
982 SPR_NOACCESS, SPR_NOACCESS,
983 &spr_read_generic, &spr_write_generic,
984 0x00000000);
985 /* XXX : not implemented */
986 spr_register(env, SPR_DBCR, "DBCR",
987 SPR_NOACCESS, SPR_NOACCESS,
988 &spr_read_generic, &spr_write_generic,
989 0x00000000);
990 }
991
992 /* SPR specific to PowerPC 602 implementation */
993 static void gen_spr_602 (CPUPPCState *env)
994 {
995 /* ESA registers */
996 /* XXX : not implemented */
997 spr_register(env, SPR_SER, "SER",
998 SPR_NOACCESS, SPR_NOACCESS,
999 &spr_read_generic, &spr_write_generic,
1000 0x00000000);
1001 /* XXX : not implemented */
1002 spr_register(env, SPR_SEBR, "SEBR",
1003 SPR_NOACCESS, SPR_NOACCESS,
1004 &spr_read_generic, &spr_write_generic,
1005 0x00000000);
1006 /* XXX : not implemented */
1007 spr_register(env, SPR_ESASR, "ESASR",
1008 SPR_NOACCESS, SPR_NOACCESS,
1009 &spr_read_generic, &spr_write_generic,
1010 0x00000000);
1011 /* Floating point status */
1012 /* XXX : not implemented */
1013 spr_register(env, SPR_SP, "SP",
1014 SPR_NOACCESS, SPR_NOACCESS,
1015 &spr_read_generic, &spr_write_generic,
1016 0x00000000);
1017 /* XXX : not implemented */
1018 spr_register(env, SPR_LT, "LT",
1019 SPR_NOACCESS, SPR_NOACCESS,
1020 &spr_read_generic, &spr_write_generic,
1021 0x00000000);
1022 /* Watchdog timer */
1023 /* XXX : not implemented */
1024 spr_register(env, SPR_TCR, "TCR",
1025 SPR_NOACCESS, SPR_NOACCESS,
1026 &spr_read_generic, &spr_write_generic,
1027 0x00000000);
1028 /* Interrupt base */
1029 spr_register(env, SPR_IBR, "IBR",
1030 SPR_NOACCESS, SPR_NOACCESS,
1031 &spr_read_generic, &spr_write_generic,
1032 0x00000000);
1033 }
1034
1035 /* SPR specific to PowerPC 601 implementation */
1036 static void gen_spr_601 (CPUPPCState *env)
1037 {
1038 /* Multiplication/division register */
1039 /* MQ */
1040 spr_register(env, SPR_MQ, "MQ",
1041 &spr_read_generic, &spr_write_generic,
1042 &spr_read_generic, &spr_write_generic,
1043 0x00000000);
1044 /* RTC registers */
1045 spr_register(env, SPR_601_RTCU, "RTCU",
1046 SPR_NOACCESS, SPR_NOACCESS,
1047 SPR_NOACCESS, &spr_write_601_rtcu,
1048 0x00000000);
1049 spr_register(env, SPR_601_VRTCU, "RTCU",
1050 &spr_read_601_rtcu, SPR_NOACCESS,
1051 &spr_read_601_rtcu, SPR_NOACCESS,
1052 0x00000000);
1053 spr_register(env, SPR_601_RTCL, "RTCL",
1054 SPR_NOACCESS, SPR_NOACCESS,
1055 SPR_NOACCESS, &spr_write_601_rtcl,
1056 0x00000000);
1057 spr_register(env, SPR_601_VRTCL, "RTCL",
1058 &spr_read_601_rtcl, SPR_NOACCESS,
1059 &spr_read_601_rtcl, SPR_NOACCESS,
1060 0x00000000);
1061 /* Timer */
1062 #if 0 /* ? */
1063 spr_register(env, SPR_601_UDECR, "UDECR",
1064 &spr_read_decr, SPR_NOACCESS,
1065 &spr_read_decr, SPR_NOACCESS,
1066 0x00000000);
1067 #endif
1068 /* External access control */
1069 /* XXX : not implemented */
1070 spr_register(env, SPR_EAR, "EAR",
1071 SPR_NOACCESS, SPR_NOACCESS,
1072 &spr_read_generic, &spr_write_generic,
1073 0x00000000);
1074 /* Memory management */
1075 spr_register(env, SPR_IBAT0U, "IBAT0U",
1076 SPR_NOACCESS, SPR_NOACCESS,
1077 &spr_read_601_ubat, &spr_write_601_ubatu,
1078 0x00000000);
1079 spr_register(env, SPR_IBAT0L, "IBAT0L",
1080 SPR_NOACCESS, SPR_NOACCESS,
1081 &spr_read_601_ubat, &spr_write_601_ubatl,
1082 0x00000000);
1083 spr_register(env, SPR_IBAT1U, "IBAT1U",
1084 SPR_NOACCESS, SPR_NOACCESS,
1085 &spr_read_601_ubat, &spr_write_601_ubatu,
1086 0x00000000);
1087 spr_register(env, SPR_IBAT1L, "IBAT1L",
1088 SPR_NOACCESS, SPR_NOACCESS,
1089 &spr_read_601_ubat, &spr_write_601_ubatl,
1090 0x00000000);
1091 spr_register(env, SPR_IBAT2U, "IBAT2U",
1092 SPR_NOACCESS, SPR_NOACCESS,
1093 &spr_read_601_ubat, &spr_write_601_ubatu,
1094 0x00000000);
1095 spr_register(env, SPR_IBAT2L, "IBAT2L",
1096 SPR_NOACCESS, SPR_NOACCESS,
1097 &spr_read_601_ubat, &spr_write_601_ubatl,
1098 0x00000000);
1099 spr_register(env, SPR_IBAT3U, "IBAT3U",
1100 SPR_NOACCESS, SPR_NOACCESS,
1101 &spr_read_601_ubat, &spr_write_601_ubatu,
1102 0x00000000);
1103 spr_register(env, SPR_IBAT3L, "IBAT3L",
1104 SPR_NOACCESS, SPR_NOACCESS,
1105 &spr_read_601_ubat, &spr_write_601_ubatl,
1106 0x00000000);
1107 }
1108
1109 /* PowerPC BookE SPR */
1110 static void gen_spr_BookE (CPUPPCState *env)
1111 {
1112 /* Processor identification */
1113 spr_register(env, SPR_BOOKE_PIR, "PIR",
1114 SPR_NOACCESS, SPR_NOACCESS,
1115 &spr_read_generic, &spr_write_pir,
1116 0x00000000);
1117 /* Interrupt processing */
1118 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1119 SPR_NOACCESS, SPR_NOACCESS,
1120 &spr_read_generic, &spr_write_generic,
1121 0x00000000);
1122 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1123 SPR_NOACCESS, SPR_NOACCESS,
1124 &spr_read_generic, &spr_write_generic,
1125 0x00000000);
1126 #if 0
1127 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1128 SPR_NOACCESS, SPR_NOACCESS,
1129 &spr_read_generic, &spr_write_generic,
1130 0x00000000);
1131 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1132 SPR_NOACCESS, SPR_NOACCESS,
1133 &spr_read_generic, &spr_write_generic,
1134 0x00000000);
1135 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
1136 SPR_NOACCESS, SPR_NOACCESS,
1137 &spr_read_generic, &spr_write_generic,
1138 0x00000000);
1139 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
1140 SPR_NOACCESS, SPR_NOACCESS,
1141 &spr_read_generic, &spr_write_generic,
1142 0x00000000);
1143 #endif
1144 /* Debug */
1145 /* XXX : not implemented */
1146 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1147 SPR_NOACCESS, SPR_NOACCESS,
1148 &spr_read_generic, &spr_write_generic,
1149 0x00000000);
1150 /* XXX : not implemented */
1151 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1152 SPR_NOACCESS, SPR_NOACCESS,
1153 &spr_read_generic, &spr_write_generic,
1154 0x00000000);
1155 /* XXX : not implemented */
1156 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1157 SPR_NOACCESS, SPR_NOACCESS,
1158 &spr_read_generic, &spr_write_generic,
1159 0x00000000);
1160 /* XXX : not implemented */
1161 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1162 SPR_NOACCESS, SPR_NOACCESS,
1163 &spr_read_generic, &spr_write_generic,
1164 0x00000000);
1165 /* XXX : not implemented */
1166 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1167 SPR_NOACCESS, SPR_NOACCESS,
1168 &spr_read_generic, &spr_write_generic,
1169 0x00000000);
1170 /* XXX : not implemented */
1171 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1172 SPR_NOACCESS, SPR_NOACCESS,
1173 &spr_read_generic, &spr_write_generic,
1174 0x00000000);
1175 /* XXX : not implemented */
1176 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1177 SPR_NOACCESS, SPR_NOACCESS,
1178 &spr_read_generic, &spr_write_generic,
1179 0x00000000);
1180 /* XXX : not implemented */
1181 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1182 SPR_NOACCESS, SPR_NOACCESS,
1183 &spr_read_generic, &spr_write_generic,
1184 0x00000000);
1185 /* XXX : not implemented */
1186 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1187 SPR_NOACCESS, SPR_NOACCESS,
1188 &spr_read_generic, &spr_write_generic,
1189 0x00000000);
1190 /* XXX : not implemented */
1191 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
1195 /* XXX : not implemented */
1196 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1197 SPR_NOACCESS, SPR_NOACCESS,
1198 &spr_read_generic, &spr_write_generic,
1199 0x00000000);
1200 /* XXX : not implemented */
1201 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1202 SPR_NOACCESS, SPR_NOACCESS,
1203 &spr_read_generic, &spr_write_clear,
1204 0x00000000);
1205 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1206 SPR_NOACCESS, SPR_NOACCESS,
1207 &spr_read_generic, &spr_write_generic,
1208 0x00000000);
1209 spr_register(env, SPR_BOOKE_ESR, "ESR",
1210 SPR_NOACCESS, SPR_NOACCESS,
1211 &spr_read_generic, &spr_write_generic,
1212 0x00000000);
1213 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1214 SPR_NOACCESS, SPR_NOACCESS,
1215 &spr_read_generic, &spr_write_generic,
1216 0x00000000);
1217 /* Exception vectors */
1218 spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1219 SPR_NOACCESS, SPR_NOACCESS,
1220 &spr_read_generic, &spr_write_generic,
1221 0x00000000);
1222 spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1223 SPR_NOACCESS, SPR_NOACCESS,
1224 &spr_read_generic, &spr_write_generic,
1225 0x00000000);
1226 spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1227 SPR_NOACCESS, SPR_NOACCESS,
1228 &spr_read_generic, &spr_write_generic,
1229 0x00000000);
1230 spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1231 SPR_NOACCESS, SPR_NOACCESS,
1232 &spr_read_generic, &spr_write_generic,
1233 0x00000000);
1234 spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1235 SPR_NOACCESS, SPR_NOACCESS,
1236 &spr_read_generic, &spr_write_generic,
1237 0x00000000);
1238 spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1239 SPR_NOACCESS, SPR_NOACCESS,
1240 &spr_read_generic, &spr_write_generic,
1241 0x00000000);
1242 spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1243 SPR_NOACCESS, SPR_NOACCESS,
1244 &spr_read_generic, &spr_write_generic,
1245 0x00000000);
1246 spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1247 SPR_NOACCESS, SPR_NOACCESS,
1248 &spr_read_generic, &spr_write_generic,
1249 0x00000000);
1250 spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1251 SPR_NOACCESS, SPR_NOACCESS,
1252 &spr_read_generic, &spr_write_generic,
1253 0x00000000);
1254 spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_generic, &spr_write_generic,
1257 0x00000000);
1258 spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1259 SPR_NOACCESS, SPR_NOACCESS,
1260 &spr_read_generic, &spr_write_generic,
1261 0x00000000);
1262 spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1263 SPR_NOACCESS, SPR_NOACCESS,
1264 &spr_read_generic, &spr_write_generic,
1265 0x00000000);
1266 spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1267 SPR_NOACCESS, SPR_NOACCESS,
1268 &spr_read_generic, &spr_write_generic,
1269 0x00000000);
1270 spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1271 SPR_NOACCESS, SPR_NOACCESS,
1272 &spr_read_generic, &spr_write_generic,
1273 0x00000000);
1274 spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1275 SPR_NOACCESS, SPR_NOACCESS,
1276 &spr_read_generic, &spr_write_generic,
1277 0x00000000);
1278 spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1279 SPR_NOACCESS, SPR_NOACCESS,
1280 &spr_read_generic, &spr_write_generic,
1281 0x00000000);
1282 #if 0
1283 spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1284 SPR_NOACCESS, SPR_NOACCESS,
1285 &spr_read_generic, &spr_write_generic,
1286 0x00000000);
1287 spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1288 SPR_NOACCESS, SPR_NOACCESS,
1289 &spr_read_generic, &spr_write_generic,
1290 0x00000000);
1291 spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1292 SPR_NOACCESS, SPR_NOACCESS,
1293 &spr_read_generic, &spr_write_generic,
1294 0x00000000);
1295 spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1296 SPR_NOACCESS, SPR_NOACCESS,
1297 &spr_read_generic, &spr_write_generic,
1298 0x00000000);
1299 spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1300 SPR_NOACCESS, SPR_NOACCESS,
1301 &spr_read_generic, &spr_write_generic,
1302 0x00000000);
1303 spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1304 SPR_NOACCESS, SPR_NOACCESS,
1305 &spr_read_generic, &spr_write_generic,
1306 0x00000000);
1307 #endif
1308 spr_register(env, SPR_BOOKE_PID, "PID",
1309 SPR_NOACCESS, SPR_NOACCESS,
1310 &spr_read_generic, &spr_write_generic,
1311 0x00000000);
1312 spr_register(env, SPR_BOOKE_TCR, "TCR",
1313 SPR_NOACCESS, SPR_NOACCESS,
1314 &spr_read_generic, &spr_write_booke_tcr,
1315 0x00000000);
1316 spr_register(env, SPR_BOOKE_TSR, "TSR",
1317 SPR_NOACCESS, SPR_NOACCESS,
1318 &spr_read_generic, &spr_write_booke_tsr,
1319 0x00000000);
1320 /* Timer */
1321 spr_register(env, SPR_DECR, "DECR",
1322 SPR_NOACCESS, SPR_NOACCESS,
1323 &spr_read_decr, &spr_write_decr,
1324 0x00000000);
1325 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1326 SPR_NOACCESS, SPR_NOACCESS,
1327 SPR_NOACCESS, &spr_write_generic,
1328 0x00000000);
1329 /* SPRGs */
1330 spr_register(env, SPR_USPRG0, "USPRG0",
1331 &spr_read_generic, &spr_write_generic,
1332 &spr_read_generic, &spr_write_generic,
1333 0x00000000);
1334 spr_register(env, SPR_SPRG4, "SPRG4",
1335 SPR_NOACCESS, SPR_NOACCESS,
1336 &spr_read_generic, &spr_write_generic,
1337 0x00000000);
1338 spr_register(env, SPR_USPRG4, "USPRG4",
1339 &spr_read_ureg, SPR_NOACCESS,
1340 &spr_read_ureg, SPR_NOACCESS,
1341 0x00000000);
1342 spr_register(env, SPR_SPRG5, "SPRG5",
1343 SPR_NOACCESS, SPR_NOACCESS,
1344 &spr_read_generic, &spr_write_generic,
1345 0x00000000);
1346 spr_register(env, SPR_USPRG5, "USPRG5",
1347 &spr_read_ureg, SPR_NOACCESS,
1348 &spr_read_ureg, SPR_NOACCESS,
1349 0x00000000);
1350 spr_register(env, SPR_SPRG6, "SPRG6",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_generic,
1353 0x00000000);
1354 spr_register(env, SPR_USPRG6, "USPRG6",
1355 &spr_read_ureg, SPR_NOACCESS,
1356 &spr_read_ureg, SPR_NOACCESS,
1357 0x00000000);
1358 spr_register(env, SPR_SPRG7, "SPRG7",
1359 SPR_NOACCESS, SPR_NOACCESS,
1360 &spr_read_generic, &spr_write_generic,
1361 0x00000000);
1362 spr_register(env, SPR_USPRG7, "USPRG7",
1363 &spr_read_ureg, SPR_NOACCESS,
1364 &spr_read_ureg, SPR_NOACCESS,
1365 0x00000000);
1366 }
1367
1368 /* FSL storage control registers */
1369 static void gen_spr_BookE_FSL (CPUPPCState *env)
1370 {
1371 /* TLB assist registers */
1372 spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1373 SPR_NOACCESS, SPR_NOACCESS,
1374 &spr_read_generic, &spr_write_generic,
1375 0x00000000);
1376 spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1377 SPR_NOACCESS, SPR_NOACCESS,
1378 &spr_read_generic, &spr_write_generic,
1379 0x00000000);
1380 spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1381 SPR_NOACCESS, SPR_NOACCESS,
1382 &spr_read_generic, &spr_write_generic,
1383 0x00000000);
1384 spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1385 SPR_NOACCESS, SPR_NOACCESS,
1386 &spr_read_generic, &spr_write_generic,
1387 0x00000000);
1388 spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1389 SPR_NOACCESS, SPR_NOACCESS,
1390 &spr_read_generic, &spr_write_generic,
1391 0x00000000);
1392 spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1393 SPR_NOACCESS, SPR_NOACCESS,
1394 &spr_read_generic, &spr_write_generic,
1395 0x00000000);
1396 spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1397 SPR_NOACCESS, SPR_NOACCESS,
1398 &spr_read_generic, &spr_write_generic,
1399 0x00000000);
1400 if (env->nb_pids > 1) {
1401 spr_register(env, SPR_BOOKE_PID1, "PID1",
1402 SPR_NOACCESS, SPR_NOACCESS,
1403 &spr_read_generic, &spr_write_generic,
1404 0x00000000);
1405 }
1406 if (env->nb_pids > 2) {
1407 spr_register(env, SPR_BOOKE_PID2, "PID2",
1408 SPR_NOACCESS, SPR_NOACCESS,
1409 &spr_read_generic, &spr_write_generic,
1410 0x00000000);
1411 }
1412 spr_register(env, SPR_BOOKE_MMUCFG, "MMUCFG",
1413 SPR_NOACCESS, SPR_NOACCESS,
1414 &spr_read_generic, SPR_NOACCESS,
1415 0x00000000); /* TOFIX */
1416 spr_register(env, SPR_BOOKE_MMUCSR0, "MMUCSR0",
1417 SPR_NOACCESS, SPR_NOACCESS,
1418 &spr_read_generic, &spr_write_generic,
1419 0x00000000); /* TOFIX */
1420 switch (env->nb_ways) {
1421 case 4:
1422 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1423 SPR_NOACCESS, SPR_NOACCESS,
1424 &spr_read_generic, SPR_NOACCESS,
1425 0x00000000); /* TOFIX */
1426 /* Fallthru */
1427 case 3:
1428 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1429 SPR_NOACCESS, SPR_NOACCESS,
1430 &spr_read_generic, SPR_NOACCESS,
1431 0x00000000); /* TOFIX */
1432 /* Fallthru */
1433 case 2:
1434 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1435 SPR_NOACCESS, SPR_NOACCESS,
1436 &spr_read_generic, SPR_NOACCESS,
1437 0x00000000); /* TOFIX */
1438 /* Fallthru */
1439 case 1:
1440 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1441 SPR_NOACCESS, SPR_NOACCESS,
1442 &spr_read_generic, SPR_NOACCESS,
1443 0x00000000); /* TOFIX */
1444 /* Fallthru */
1445 case 0:
1446 default:
1447 break;
1448 }
1449 }
1450
1451 /* SPR specific to PowerPC 440 implementation */
1452 static void gen_spr_440 (CPUPPCState *env)
1453 {
1454 /* Cache control */
1455 /* XXX : not implemented */
1456 spr_register(env, SPR_440_DNV0, "DNV0",
1457 SPR_NOACCESS, SPR_NOACCESS,
1458 &spr_read_generic, &spr_write_generic,
1459 0x00000000);
1460 /* XXX : not implemented */
1461 spr_register(env, SPR_440_DNV1, "DNV1",
1462 SPR_NOACCESS, SPR_NOACCESS,
1463 &spr_read_generic, &spr_write_generic,
1464 0x00000000);
1465 /* XXX : not implemented */
1466 spr_register(env, SPR_440_DNV2, "DNV2",
1467 SPR_NOACCESS, SPR_NOACCESS,
1468 &spr_read_generic, &spr_write_generic,
1469 0x00000000);
1470 /* XXX : not implemented */
1471 spr_register(env, SPR_440_DNV3, "DNV3",
1472 SPR_NOACCESS, SPR_NOACCESS,
1473 &spr_read_generic, &spr_write_generic,
1474 0x00000000);
1475 /* XXX : not implemented */
1476 spr_register(env, SPR_440_DTV0, "DTV0",
1477 SPR_NOACCESS, SPR_NOACCESS,
1478 &spr_read_generic, &spr_write_generic,
1479 0x00000000);
1480 /* XXX : not implemented */
1481 spr_register(env, SPR_440_DTV1, "DTV1",
1482 SPR_NOACCESS, SPR_NOACCESS,
1483 &spr_read_generic, &spr_write_generic,
1484 0x00000000);
1485 /* XXX : not implemented */
1486 spr_register(env, SPR_440_DTV2, "DTV2",
1487 SPR_NOACCESS, SPR_NOACCESS,
1488 &spr_read_generic, &spr_write_generic,
1489 0x00000000);
1490 /* XXX : not implemented */
1491 spr_register(env, SPR_440_DTV3, "DTV3",
1492 SPR_NOACCESS, SPR_NOACCESS,
1493 &spr_read_generic, &spr_write_generic,
1494 0x00000000);
1495 /* XXX : not implemented */
1496 spr_register(env, SPR_440_DVLIM, "DVLIM",
1497 SPR_NOACCESS, SPR_NOACCESS,
1498 &spr_read_generic, &spr_write_generic,
1499 0x00000000);
1500 /* XXX : not implemented */
1501 spr_register(env, SPR_440_INV0, "INV0",
1502 SPR_NOACCESS, SPR_NOACCESS,
1503 &spr_read_generic, &spr_write_generic,
1504 0x00000000);
1505 /* XXX : not implemented */
1506 spr_register(env, SPR_440_INV1, "INV1",
1507 SPR_NOACCESS, SPR_NOACCESS,
1508 &spr_read_generic, &spr_write_generic,
1509 0x00000000);
1510 /* XXX : not implemented */
1511 spr_register(env, SPR_440_INV2, "INV2",
1512 SPR_NOACCESS, SPR_NOACCESS,
1513 &spr_read_generic, &spr_write_generic,
1514 0x00000000);
1515 /* XXX : not implemented */
1516 spr_register(env, SPR_440_INV3, "INV3",
1517 SPR_NOACCESS, SPR_NOACCESS,
1518 &spr_read_generic, &spr_write_generic,
1519 0x00000000);
1520 /* XXX : not implemented */
1521 spr_register(env, SPR_440_ITV0, "ITV0",
1522 SPR_NOACCESS, SPR_NOACCESS,
1523 &spr_read_generic, &spr_write_generic,
1524 0x00000000);
1525 /* XXX : not implemented */
1526 spr_register(env, SPR_440_ITV1, "ITV1",
1527 SPR_NOACCESS, SPR_NOACCESS,
1528 &spr_read_generic, &spr_write_generic,
1529 0x00000000);
1530 /* XXX : not implemented */
1531 spr_register(env, SPR_440_ITV2, "ITV2",
1532 SPR_NOACCESS, SPR_NOACCESS,
1533 &spr_read_generic, &spr_write_generic,
1534 0x00000000);
1535 /* XXX : not implemented */
1536 spr_register(env, SPR_440_ITV3, "ITV3",
1537 SPR_NOACCESS, SPR_NOACCESS,
1538 &spr_read_generic, &spr_write_generic,
1539 0x00000000);
1540 /* XXX : not implemented */
1541 spr_register(env, SPR_440_IVLIM, "IVLIM",
1542 SPR_NOACCESS, SPR_NOACCESS,
1543 &spr_read_generic, &spr_write_generic,
1544 0x00000000);
1545 /* Cache debug */
1546 /* XXX : not implemented */
1547 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1548 SPR_NOACCESS, SPR_NOACCESS,
1549 &spr_read_generic, SPR_NOACCESS,
1550 0x00000000);
1551 /* XXX : not implemented */
1552 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1553 SPR_NOACCESS, SPR_NOACCESS,
1554 &spr_read_generic, SPR_NOACCESS,
1555 0x00000000);
1556 /* XXX : not implemented */
1557 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1558 SPR_NOACCESS, SPR_NOACCESS,
1559 &spr_read_generic, SPR_NOACCESS,
1560 0x00000000);
1561 /* XXX : not implemented */
1562 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1563 SPR_NOACCESS, SPR_NOACCESS,
1564 &spr_read_generic, SPR_NOACCESS,
1565 0x00000000);
1566 /* XXX : not implemented */
1567 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1568 SPR_NOACCESS, SPR_NOACCESS,
1569 &spr_read_generic, SPR_NOACCESS,
1570 0x00000000);
1571 /* XXX : not implemented */
1572 spr_register(env, SPR_440_DBDR, "DBDR",
1573 SPR_NOACCESS, SPR_NOACCESS,
1574 &spr_read_generic, &spr_write_generic,
1575 0x00000000);
1576 /* Processor control */
1577 spr_register(env, SPR_4xx_CCR0, "CCR0",
1578 SPR_NOACCESS, SPR_NOACCESS,
1579 &spr_read_generic, &spr_write_generic,
1580 0x00000000);
1581 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1582 SPR_NOACCESS, SPR_NOACCESS,
1583 &spr_read_generic, SPR_NOACCESS,
1584 0x00000000);
1585 /* Storage control */
1586 spr_register(env, SPR_440_MMUCR, "MMUCR",
1587 SPR_NOACCESS, SPR_NOACCESS,
1588 &spr_read_generic, &spr_write_generic,
1589 0x00000000);
1590 }
1591
1592 /* SPR shared between PowerPC 40x implementations */
1593 static void gen_spr_40x (CPUPPCState *env)
1594 {
1595 /* Cache */
1596 /* XXX : not implemented */
1597 spr_register(env, SPR_40x_DCCR, "DCCR",
1598 SPR_NOACCESS, SPR_NOACCESS,
1599 &spr_read_generic, &spr_write_generic,
1600 0x00000000);
1601 /* XXX : not implemented */
1602 spr_register(env, SPR_40x_DCWR, "DCWR",
1603 SPR_NOACCESS, SPR_NOACCESS,
1604 &spr_read_generic, &spr_write_generic,
1605 0x00000000);
1606 /* XXX : not implemented */
1607 spr_register(env, SPR_40x_ICCR, "ICCR",
1608 SPR_NOACCESS, SPR_NOACCESS,
1609 &spr_read_generic, &spr_write_generic,
1610 0x00000000);
1611 /* XXX : not implemented */
1612 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1613 SPR_NOACCESS, SPR_NOACCESS,
1614 &spr_read_generic, SPR_NOACCESS,
1615 0x00000000);
1616 /* Bus access control */
1617 spr_register(env, SPR_40x_SGR, "SGR",
1618 SPR_NOACCESS, SPR_NOACCESS,
1619 &spr_read_generic, &spr_write_generic,
1620 0xFFFFFFFF);
1621 /* Exception */
1622 spr_register(env, SPR_40x_DEAR, "DEAR",
1623 SPR_NOACCESS, SPR_NOACCESS,
1624 &spr_read_generic, &spr_write_generic,
1625 0x00000000);
1626 spr_register(env, SPR_40x_ESR, "ESR",
1627 SPR_NOACCESS, SPR_NOACCESS,
1628 &spr_read_generic, &spr_write_generic,
1629 0x00000000);
1630 spr_register(env, SPR_40x_EVPR, "EVPR",
1631 SPR_NOACCESS, SPR_NOACCESS,
1632 &spr_read_generic, &spr_write_generic,
1633 0x00000000);
1634 spr_register(env, SPR_40x_SRR2, "SRR2",
1635 &spr_read_generic, &spr_write_generic,
1636 &spr_read_generic, &spr_write_generic,
1637 0x00000000);
1638 spr_register(env, SPR_40x_SRR3, "SRR3",
1639 &spr_read_generic, &spr_write_generic,
1640 &spr_read_generic, &spr_write_generic,
1641 0x00000000);
1642 /* Timers */
1643 spr_register(env, SPR_40x_PIT, "PIT",
1644 SPR_NOACCESS, SPR_NOACCESS,
1645 &spr_read_40x_pit, &spr_write_40x_pit,
1646 0x00000000);
1647 spr_register(env, SPR_40x_TCR, "TCR",
1648 SPR_NOACCESS, SPR_NOACCESS,
1649 &spr_read_generic, &spr_write_booke_tcr,
1650 0x00000000);
1651 spr_register(env, SPR_40x_TSR, "TSR",
1652 SPR_NOACCESS, SPR_NOACCESS,
1653 &spr_read_generic, &spr_write_booke_tsr,
1654 0x00000000);
1655 }
1656
1657 /* SPR specific to PowerPC 405 implementation */
1658 static void gen_spr_405 (CPUPPCState *env)
1659 {
1660 /* MMU */
1661 spr_register(env, SPR_40x_PID, "PID",
1662 SPR_NOACCESS, SPR_NOACCESS,
1663 &spr_read_generic, &spr_write_generic,
1664 0x00000000);
1665 spr_register(env, SPR_4xx_CCR0, "CCR0",
1666 SPR_NOACCESS, SPR_NOACCESS,
1667 &spr_read_generic, &spr_write_generic,
1668 0x00700000);
1669 /* Debug interface */
1670 /* XXX : not implemented */
1671 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1672 SPR_NOACCESS, SPR_NOACCESS,
1673 &spr_read_generic, &spr_write_40x_dbcr0,
1674 0x00000000);
1675 /* XXX : not implemented */
1676 spr_register(env, SPR_405_DBCR1, "DBCR1",
1677 SPR_NOACCESS, SPR_NOACCESS,
1678 &spr_read_generic, &spr_write_generic,
1679 0x00000000);
1680 /* XXX : not implemented */
1681 spr_register(env, SPR_40x_DBSR, "DBSR",
1682 SPR_NOACCESS, SPR_NOACCESS,
1683 &spr_read_generic, &spr_write_clear,
1684 /* Last reset was system reset */
1685 0x00000300);
1686 /* XXX : not implemented */
1687 spr_register(env, SPR_40x_DAC1, "DAC1",
1688 SPR_NOACCESS, SPR_NOACCESS,
1689 &spr_read_generic, &spr_write_generic,
1690 0x00000000);
1691 spr_register(env, SPR_40x_DAC2, "DAC2",
1692 SPR_NOACCESS, SPR_NOACCESS,
1693 &spr_read_generic, &spr_write_generic,
1694 0x00000000);
1695 /* XXX : not implemented */
1696 spr_register(env, SPR_405_DVC1, "DVC1",
1697 SPR_NOACCESS, SPR_NOACCESS,
1698 &spr_read_generic, &spr_write_generic,
1699 0x00000000);
1700 /* XXX : not implemented */
1701 spr_register(env, SPR_405_DVC2, "DVC2",
1702 SPR_NOACCESS, SPR_NOACCESS,
1703 &spr_read_generic, &spr_write_generic,
1704 0x00000000);
1705 /* XXX : not implemented */
1706 spr_register(env, SPR_40x_IAC1, "IAC1",
1707 SPR_NOACCESS, SPR_NOACCESS,
1708 &spr_read_generic, &spr_write_generic,
1709 0x00000000);
1710 spr_register(env, SPR_40x_IAC2, "IAC2",
1711 SPR_NOACCESS, SPR_NOACCESS,
1712 &spr_read_generic, &spr_write_generic,
1713 0x00000000);
1714 /* XXX : not implemented */
1715 spr_register(env, SPR_405_IAC3, "IAC3",
1716 SPR_NOACCESS, SPR_NOACCESS,
1717 &spr_read_generic, &spr_write_generic,
1718 0x00000000);
1719 /* XXX : not implemented */
1720 spr_register(env, SPR_405_IAC4, "IAC4",
1721 SPR_NOACCESS, SPR_NOACCESS,
1722 &spr_read_generic, &spr_write_generic,
1723 0x00000000);
1724 /* Storage control */
1725 spr_register(env, SPR_405_SLER, "SLER",
1726 SPR_NOACCESS, SPR_NOACCESS,
1727 &spr_read_generic, &spr_write_40x_sler,
1728 0x00000000);
1729 spr_register(env, SPR_40x_ZPR, "ZPR",
1730 SPR_NOACCESS, SPR_NOACCESS,
1731 &spr_read_generic, &spr_write_generic,
1732 0x00000000);
1733 /* XXX : not implemented */
1734 spr_register(env, SPR_405_SU0R, "SU0R",
1735 SPR_NOACCESS, SPR_NOACCESS,
1736 &spr_read_generic, &spr_write_generic,
1737 0x00000000);
1738 /* SPRG */
1739 spr_register(env, SPR_USPRG0, "USPRG0",
1740 &spr_read_ureg, SPR_NOACCESS,
1741 &spr_read_ureg, SPR_NOACCESS,
1742 0x00000000);
1743 spr_register(env, SPR_SPRG4, "SPRG4",
1744 SPR_NOACCESS, SPR_NOACCESS,
1745 &spr_read_generic, &spr_write_generic,
1746 0x00000000);
1747 spr_register(env, SPR_USPRG4, "USPRG4",
1748 &spr_read_ureg, SPR_NOACCESS,
1749 &spr_read_ureg, SPR_NOACCESS,
1750 0x00000000);
1751 spr_register(env, SPR_SPRG5, "SPRG5",
1752 SPR_NOACCESS, SPR_NOACCESS,
1753 spr_read_generic, &spr_write_generic,
1754 0x00000000);
1755 spr_register(env, SPR_USPRG5, "USPRG5",
1756 &spr_read_ureg, SPR_NOACCESS,
1757 &spr_read_ureg, SPR_NOACCESS,
1758 0x00000000);
1759 spr_register(env, SPR_SPRG6, "SPRG6",
1760 SPR_NOACCESS, SPR_NOACCESS,
1761 spr_read_generic, &spr_write_generic,
1762 0x00000000);
1763 spr_register(env, SPR_USPRG6, "USPRG6",
1764 &spr_read_ureg, SPR_NOACCESS,
1765 &spr_read_ureg, SPR_NOACCESS,
1766 0x00000000);
1767 spr_register(env, SPR_SPRG7, "SPRG7",
1768 SPR_NOACCESS, SPR_NOACCESS,
1769 spr_read_generic, &spr_write_generic,
1770 0x00000000);
1771 spr_register(env, SPR_USPRG7, "USPRG7",
1772 &spr_read_ureg, SPR_NOACCESS,
1773 &spr_read_ureg, SPR_NOACCESS,
1774 0x00000000);
1775 }
1776
1777 /* SPR shared between PowerPC 401 & 403 implementations */
1778 static void gen_spr_401_403 (CPUPPCState *env)
1779 {
1780 /* Time base */
1781 spr_register(env, SPR_403_VTBL, "TBL",
1782 &spr_read_tbl, SPR_NOACCESS,
1783 &spr_read_tbl, SPR_NOACCESS,
1784 0x00000000);
1785 spr_register(env, SPR_403_TBL, "TBL",
1786 SPR_NOACCESS, SPR_NOACCESS,
1787 SPR_NOACCESS, &spr_write_tbl,
1788 0x00000000);
1789 spr_register(env, SPR_403_VTBU, "TBU",
1790 &spr_read_tbu, SPR_NOACCESS,
1791 &spr_read_tbu, SPR_NOACCESS,
1792 0x00000000);
1793 spr_register(env, SPR_403_TBU, "TBU",
1794 SPR_NOACCESS, SPR_NOACCESS,
1795 SPR_NOACCESS, &spr_write_tbu,
1796 0x00000000);
1797 /* Debug */
1798 /* XXX: not implemented */
1799 spr_register(env, SPR_403_CDBCR, "CDBCR",
1800 SPR_NOACCESS, SPR_NOACCESS,
1801 &spr_read_generic, &spr_write_generic,
1802 0x00000000);
1803 }
1804
1805 /* SPR specific to PowerPC 401 implementation */
1806 static void gen_spr_401 (CPUPPCState *env)
1807 {
1808 /* Debug interface */
1809 /* XXX : not implemented */
1810 spr_register(env, SPR_40x_DBCR0, "DBCR",
1811 SPR_NOACCESS, SPR_NOACCESS,
1812 &spr_read_generic, &spr_write_40x_dbcr0,
1813 0x00000000);
1814 /* XXX : not implemented */
1815 spr_register(env, SPR_40x_DBSR, "DBSR",
1816 SPR_NOACCESS, SPR_NOACCESS,
1817 &spr_read_generic, &spr_write_clear,
1818 /* Last reset was system reset */
1819 0x00000300);
1820 /* XXX : not implemented */
1821 spr_register(env, SPR_40x_DAC1, "DAC",
1822 SPR_NOACCESS, SPR_NOACCESS,
1823 &spr_read_generic, &spr_write_generic,
1824 0x00000000);
1825 /* XXX : not implemented */
1826 spr_register(env, SPR_40x_IAC1, "IAC",
1827 SPR_NOACCESS, SPR_NOACCESS,
1828 &spr_read_generic, &spr_write_generic,
1829 0x00000000);
1830 /* Storage control */
1831 spr_register(env, SPR_405_SLER, "SLER",
1832 SPR_NOACCESS, SPR_NOACCESS,
1833 &spr_read_generic, &spr_write_40x_sler,
1834 0x00000000);
1835 }
1836
1837 /* SPR specific to PowerPC 403 implementation */
1838 static void gen_spr_403 (CPUPPCState *env)
1839 {
1840 /* Debug interface */
1841 /* XXX : not implemented */
1842 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1843 SPR_NOACCESS, SPR_NOACCESS,
1844 &spr_read_generic, &spr_write_40x_dbcr0,
1845 0x00000000);
1846 /* XXX : not implemented */
1847 spr_register(env, SPR_40x_DBSR, "DBSR",
1848 SPR_NOACCESS, SPR_NOACCESS,
1849 &spr_read_generic, &spr_write_clear,
1850 /* Last reset was system reset */
1851 0x00000300);
1852 /* XXX : not implemented */
1853 spr_register(env, SPR_40x_DAC1, "DAC1",
1854 SPR_NOACCESS, SPR_NOACCESS,
1855 &spr_read_generic, &spr_write_generic,
1856 0x00000000);
1857 spr_register(env, SPR_40x_DAC2, "DAC2",
1858 SPR_NOACCESS, SPR_NOACCESS,
1859 &spr_read_generic, &spr_write_generic,
1860 0x00000000);
1861 /* XXX : not implemented */
1862 spr_register(env, SPR_40x_IAC1, "IAC1",
1863 SPR_NOACCESS, SPR_NOACCESS,
1864 &spr_read_generic, &spr_write_generic,
1865 0x00000000);
1866 spr_register(env, SPR_40x_IAC2, "IAC2",
1867 SPR_NOACCESS, SPR_NOACCESS,
1868 &spr_read_generic, &spr_write_generic,
1869 0x00000000);
1870 /* MMU */
1871 spr_register(env, SPR_40x_PID, "PID",
1872 SPR_NOACCESS, SPR_NOACCESS,
1873 &spr_read_generic, &spr_write_generic,
1874 0x00000000);
1875 spr_register(env, SPR_403_PBL1, "PBL1",
1876 SPR_NOACCESS, SPR_NOACCESS,
1877 &spr_read_403_pbr, &spr_write_403_pbr,
1878 0x00000000);
1879 spr_register(env, SPR_403_PBU1, "PBU1",
1880 SPR_NOACCESS, SPR_NOACCESS,
1881 &spr_read_403_pbr, &spr_write_403_pbr,
1882 0x00000000);
1883 spr_register(env, SPR_403_PBL2, "PBL2",
1884 SPR_NOACCESS, SPR_NOACCESS,
1885 &spr_read_403_pbr, &spr_write_403_pbr,
1886 0x00000000);
1887 spr_register(env, SPR_403_PBU2, "PBU2",
1888 SPR_NOACCESS, SPR_NOACCESS,
1889 &spr_read_403_pbr, &spr_write_403_pbr,
1890 0x00000000);
1891 spr_register(env, SPR_40x_ZPR, "ZPR",
1892 SPR_NOACCESS, SPR_NOACCESS,
1893 &spr_read_generic, &spr_write_generic,
1894 0x00000000);
1895 }
1896
1897 /* SPR specific to PowerPC compression coprocessor extension */
1898 #if defined (TODO)
1899 static void gen_spr_compress (CPUPPCState *env)
1900 {
1901 spr_register(env, SPR_401_SKR, "SKR",
1902 SPR_NOACCESS, SPR_NOACCESS,
1903 &spr_read_generic, &spr_write_generic,
1904 0x00000000);
1905 }
1906 #endif
1907
1908 // XXX: TODO
1909 /*
1910 * AMR => SPR 29 (Power 2.04)
1911 * CTRL => SPR 136 (Power 2.04)
1912 * CTRL => SPR 152 (Power 2.04)
1913 * VRSAVE => SPR 256 (Altivec)
1914 * SCOMC => SPR 276 (64 bits ?)
1915 * SCOMD => SPR 277 (64 bits ?)
1916 * ASR => SPR 280 (64 bits)
1917 * TBU40 => SPR 286 (Power 2.04 hypv)
1918 * HSPRG0 => SPR 304 (Power 2.04 hypv)
1919 * HSPRG1 => SPR 305 (Power 2.04 hypv)
1920 * HDSISR => SPR 306 (Power 2.04 hypv)
1921 * HDAR => SPR 307 (Power 2.04 hypv)
1922 * PURR => SPR 309 (Power 2.04 hypv)
1923 * HDEC => SPR 310 (Power 2.04 hypv)
1924 * HIOR => SPR 311 (hypv)
1925 * RMOR => SPR 312 (970)
1926 * HRMOR => SPR 313 (Power 2.04 hypv)
1927 * HSRR0 => SPR 314 (Power 2.04 hypv)
1928 * HSRR1 => SPR 315 (Power 2.04 hypv)
1929 * LPCR => SPR 316 (970)
1930 * LPIDR => SPR 317 (970)
1931 * SPEFSCR => SPR 512 (Power 2.04 emb)
1932 * ATBL => SPR 526 (Power 2.04 emb)
1933 * ATBU => SPR 527 (Power 2.04 emb)
1934 * EPR => SPR 702 (Power 2.04 emb)
1935 * perf => 768-783 (Power 2.04)
1936 * perf => 784-799 (Power 2.04)
1937 * PPR => SPR 896 (Power 2.04)
1938 * EPLC => SPR 947 (Power 2.04 emb)
1939 * EPSC => SPR 948 (Power 2.04 emb)
1940 * DABRX => 1015 (Power 2.04 hypv)
1941 * FPECR => SPR 1022 (?)
1942 * ... and more (thermal management, performance counters, ...)
1943 */
1944
1945 static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
1946 {
1947 env->reserve = -1;
1948 /* Default MMU definitions */
1949 env->nb_BATs = -1;
1950 env->nb_tlb = 0;
1951 env->nb_ways = 0;
1952 /* XXX: missing:
1953 * 32 bits PowerPC:
1954 * - MPC5xx(x)
1955 * - MPC8xx(x)
1956 * - RCPU (same as MPC5xx ?)
1957 */
1958 spr_register(env, SPR_PVR, "PVR",
1959 SPR_NOACCESS, SPR_NOACCESS,
1960 &spr_read_generic, SPR_NOACCESS,
1961 def->pvr);
1962 printf("%s: PVR %08x mask %08x => %08x\n", __func__,
1963 def->pvr, def->pvr_mask, def->pvr & def->pvr_mask);
1964 switch (def->pvr) {
1965 /* Embedded PowerPC from IBM */
1966 case CPU_PPC_401A1: /* 401 A1 family */
1967 case CPU_PPC_401B2: /* 401 B2 family */
1968 #if 0
1969 case CPU_PPC_401B3: /* 401 B3 family */
1970 #endif
1971 case CPU_PPC_401C2: /* 401 C2 family */
1972 case CPU_PPC_401D2: /* 401 D2 family */
1973 case CPU_PPC_401E2: /* 401 E2 family */
1974 case CPU_PPC_401F2: /* 401 F2 family */
1975 case CPU_PPC_401G2: /* 401 G2 family */
1976 case CPU_PPC_IOP480: /* IOP 480 family */
1977 case CPU_PPC_COBRA: /* IBM Processor for Network Resources */
1978 gen_spr_generic(env);
1979 gen_spr_40x(env);
1980 gen_spr_401_403(env);
1981 gen_spr_401(env);
1982 #if defined (TODO)
1983 /* XXX: optional ? */
1984 gen_spr_compress(env);
1985 #endif
1986 env->nb_BATs = 0;
1987 env->nb_tlb = 64;
1988 env->nb_ways = 1;
1989 env->id_tlbs = 0;
1990 /* XXX: TODO: allocate internal IRQ controller */
1991 break;
1992
1993 case CPU_PPC_403GA: /* 403 GA family */
1994 case CPU_PPC_403GB: /* 403 GB family */
1995 case CPU_PPC_403GC: /* 403 GC family */
1996 case CPU_PPC_403GCX: /* 403 GCX family */
1997 gen_spr_generic(env);
1998 gen_spr_40x(env);
1999 gen_spr_401_403(env);
2000 gen_spr_403(env);
2001 env->nb_BATs = 0;
2002 env->nb_tlb = 64;
2003 env->nb_ways = 1;
2004 env->id_tlbs = 0;
2005 /* XXX: TODO: allocate internal IRQ controller */
2006 break;
2007
2008 case CPU_PPC_405CR: /* 405 GP/CR family */
2009 case CPU_PPC_405EP: /* 405 EP family */
2010 case CPU_PPC_405GPR: /* 405 GPR family */
2011 case CPU_PPC_405D2: /* 405 D2 family */
2012 case CPU_PPC_405D4: /* 405 D4 family */
2013 gen_spr_generic(env);
2014 /* Time base */
2015 gen_tbl(env);
2016 gen_spr_40x(env);
2017 gen_spr_405(env);
2018 env->nb_BATs = 0;
2019 env->nb_tlb = 64;
2020 env->nb_ways = 1;
2021 env->id_tlbs = 0;
2022 /* Allocate hardware IRQ controller */
2023 ppc405_irq_init(env);
2024 break;
2025
2026 case CPU_PPC_NPE405H: /* NPe405 H family */
2027 case CPU_PPC_NPE405H2:
2028 case CPU_PPC_NPE405L: /* Npe405 L family */
2029 gen_spr_generic(env);
2030 /* Time base */
2031 gen_tbl(env);
2032 gen_spr_40x(env);
2033 gen_spr_405(env);
2034 env->nb_BATs = 0;
2035 env->nb_tlb = 64;
2036 env->nb_ways = 1;
2037 env->id_tlbs = 0;
2038 /* Allocate hardware IRQ controller */
2039 ppc405_irq_init(env);
2040 break;
2041
2042 #if defined (TODO)
2043 case CPU_PPC_STB01000:
2044 #endif
2045 #if defined (TODO)
2046 case CPU_PPC_STB01010:
2047 #endif
2048 #if defined (TODO)
2049 case CPU_PPC_STB0210:
2050 #endif
2051 case CPU_PPC_STB03: /* STB03 family */
2052 #if defined (TODO)
2053 case CPU_PPC_STB043: /* STB043 family */
2054 #endif
2055 #if defined (TODO)
2056 case CPU_PPC_STB045: /* STB045 family */
2057 #endif
2058 case CPU_PPC_STB25: /* STB25 family */
2059 #if defined (TODO)
2060 case CPU_PPC_STB130: /* STB130 family */
2061 #endif
2062 gen_spr_generic(env);
2063 /* Time base */
2064 gen_tbl(env);
2065 gen_spr_40x(env);
2066 gen_spr_405(env);
2067 env->nb_BATs = 0;
2068 env->nb_tlb = 64;
2069 env->nb_ways = 1;
2070 env->id_tlbs = 0;
2071 /* Allocate hardware IRQ controller */
2072 ppc405_irq_init(env);
2073 break;
2074
2075 case CPU_PPC_440EP: /* 440 EP family */
2076 case CPU_PPC_440GP: /* 440 GP family */
2077 case CPU_PPC_440GX: /* 440 GX family */
2078 case CPU_PPC_440GXc: /* 440 GXc family */
2079 case CPU_PPC_440GXf: /* 440 GXf family */
2080 case CPU_PPC_440SP: /* 440 SP family */
2081 case CPU_PPC_440SP2:
2082 case CPU_PPC_440SPE: /* 440 SPE family */
2083 gen_spr_generic(env);
2084 /* Time base */
2085 gen_tbl(env);
2086 gen_spr_BookE(env);
2087 gen_spr_440(env);
2088 env->nb_BATs = 0;
2089 env->nb_tlb = 64;
2090 env->nb_ways = 1;
2091 env->id_tlbs = 0;
2092 /* XXX: TODO: allocate internal IRQ controller */
2093 break;
2094
2095 /* Embedded PowerPC from Freescale */
2096 #if defined (TODO)
2097 case CPU_PPC_5xx:
2098 break;
2099 #endif
2100 #if defined (TODO)
2101 case CPU_PPC_8xx: /* MPC821 / 823 / 850 / 860 */
2102 break;
2103 #endif
2104 #if defined (TODO)
2105 case CPU_PPC_82xx_HIP3: /* MPC8240 / 8260 */
2106 case CPU_PPC_82xx_HIP4: /* MPC8240 / 8260 */
2107 break;
2108 #endif
2109 #if defined (TODO)
2110 case CPU_PPC_827x: /* MPC 827x / 828x */
2111 break;
2112 #endif
2113
2114 /* XXX: Use MPC8540 PVR to implement a test PowerPC BookE target */
2115 case CPU_PPC_e500v110:
2116 case CPU_PPC_e500v120:
2117 case CPU_PPC_e500v210:
2118 case CPU_PPC_e500v220:
2119 gen_spr_generic(env);
2120 /* Time base */
2121 gen_tbl(env);
2122 gen_spr_BookE(env);
2123 gen_spr_BookE_FSL(env);
2124 env->nb_BATs = 0;
2125 env->nb_tlb = 64;
2126 env->nb_ways = 1;
2127 env->id_tlbs = 0;
2128 /* XXX: TODO: allocate internal IRQ controller */
2129 break;
2130
2131 #if defined (TODO)
2132 case CPU_PPC_e600:
2133 break;
2134 #endif
2135
2136 /* 32 bits PowerPC */
2137 case CPU_PPC_601: /* PowerPC 601 */
2138 gen_spr_generic(env);
2139 gen_spr_ne_601(env);
2140 gen_spr_601(env);
2141 /* Hardware implementation registers */
2142 /* XXX : not implemented */
2143 spr_register(env, SPR_HID0, "HID0",
2144 SPR_NOACCESS, SPR_NOACCESS,
2145 &spr_read_generic, &spr_write_generic,
2146 0x00000000);
2147 /* XXX : not implemented */
2148 spr_register(env, SPR_HID1, "HID1",
2149 SPR_NOACCESS, SPR_NOACCESS,
2150 &spr_read_generic, &spr_write_generic,
2151 0x00000000);
2152 /* XXX : not implemented */
2153 spr_register(env, SPR_601_HID2, "HID2",
2154 SPR_NOACCESS, SPR_NOACCESS,
2155 &spr_read_generic, &spr_write_generic,
2156 0x00000000);
2157 /* XXX : not implemented */
2158 spr_register(env, SPR_601_HID5, "HID5",
2159 SPR_NOACCESS, SPR_NOACCESS,
2160 &spr_read_generic, &spr_write_generic,
2161 0x00000000);
2162 /* XXX : not implemented */
2163 #if 0 /* ? */
2164 spr_register(env, SPR_601_HID15, "HID15",
2165 SPR_NOACCESS, SPR_NOACCESS,
2166 &spr_read_generic, &spr_write_generic,
2167 0x00000000);
2168 #endif
2169 env->nb_tlb = 64;
2170 env->nb_ways = 2;
2171 env->id_tlbs = 0;
2172 env->id_tlbs = 0;
2173 /* XXX: TODO: allocate internal IRQ controller */
2174 break;
2175
2176 case CPU_PPC_602: /* PowerPC 602 */
2177 gen_spr_generic(env);
2178 gen_spr_ne_601(env);
2179 /* Memory management */
2180 gen_low_BATs(env);
2181 /* Time base */
2182 gen_tbl(env);
2183 gen_6xx_7xx_soft_tlb(env, 64, 2);
2184 gen_spr_602(env);
2185 /* hardware implementation registers */
2186 /* XXX : not implemented */
2187 spr_register(env, SPR_HID0, "HID0",
2188 SPR_NOACCESS, SPR_NOACCESS,
2189 &spr_read_generic, &spr_write_generic,
2190 0x00000000);
2191 /* XXX : not implemented */
2192 spr_register(env, SPR_HID1, "HID1",
2193 SPR_NOACCESS, SPR_NOACCESS,
2194 &spr_read_generic, &spr_write_generic,
2195 0x00000000);
2196 /* Allocate hardware IRQ controller */
2197 ppc6xx_irq_init(env);
2198 break;
2199
2200 case CPU_PPC_603: /* PowerPC 603 */
2201 case CPU_PPC_603E: /* PowerPC 603e */
2202 case CPU_PPC_603E7v:
2203 case CPU_PPC_603E7v2:
2204 case CPU_PPC_603P: /* PowerPC 603p */
2205 case CPU_PPC_603R: /* PowerPC 603r */
2206 gen_spr_generic(env);
2207 gen_spr_ne_601(env);
2208 /* Memory management */
2209 gen_low_BATs(env);
2210 /* Time base */
2211 gen_tbl(env);
2212 gen_6xx_7xx_soft_tlb(env, 64, 2);
2213 gen_spr_603(env);
2214 /* hardware implementation registers */
2215 /* XXX : not implemented */
2216 spr_register(env, SPR_HID0, "HID0",
2217 SPR_NOACCESS, SPR_NOACCESS,
2218 &spr_read_generic, &spr_write_generic,
2219 0x00000000);
2220 /* XXX : not implemented */
2221 spr_register(env, SPR_HID1, "HID1",
2222 SPR_NOACCESS, SPR_NOACCESS,
2223 &spr_read_generic, &spr_write_generic,
2224 0x00000000);
2225 /* Allocate hardware IRQ controller */
2226 ppc6xx_irq_init(env);
2227 break;
2228
2229 case CPU_PPC_G2: /* PowerPC G2 family */
2230 case CPU_PPC_G2H4:
2231 case CPU_PPC_G2gp:
2232 case CPU_PPC_G2ls:
2233 case CPU_PPC_G2LE: /* PowerPC G2LE family */
2234 case CPU_PPC_G2LEgp:
2235 case CPU_PPC_G2LEls:
2236 gen_spr_generic(env);
2237 gen_spr_ne_601(env);
2238 /* Memory management */
2239 gen_low_BATs(env);
2240 /* Time base */
2241 gen_tbl(env);
2242 /* Memory management */
2243 gen_high_BATs(env);
2244 gen_6xx_7xx_soft_tlb(env, 64, 2);
2245 gen_spr_G2_755(env);
2246 gen_spr_G2(env);
2247 /* Hardware implementation register */
2248 /* XXX : not implemented */
2249 spr_register(env, SPR_HID0, "HID0",
2250 SPR_NOACCESS, SPR_NOACCESS,
2251 &spr_read_generic, &spr_write_generic,
2252 0x00000000);
2253 /* XXX : not implemented */
2254 spr_register(env, SPR_HID1, "HID1",
2255 SPR_NOACCESS, SPR_NOACCESS,
2256 &spr_read_generic, &spr_write_generic,
2257 0x00000000);
2258 /* XXX : not implemented */
2259 spr_register(env, SPR_HID2, "HID2",
2260 SPR_NOACCESS, SPR_NOACCESS,
2261 &spr_read_generic, &spr_write_generic,
2262 0x00000000);
2263 /* Allocate hardware IRQ controller */
2264 ppc6xx_irq_init(env);
2265 break;
2266
2267 case CPU_PPC_604: /* PowerPC 604 */
2268 case CPU_PPC_604E: /* PowerPC 604e */
2269 case CPU_PPC_604R: /* PowerPC 604r */
2270 gen_spr_generic(env);
2271 gen_spr_ne_601(env);
2272 /* Memory management */
2273 gen_low_BATs(env);
2274 /* Time base */
2275 gen_tbl(env);
2276 gen_spr_604(env);
2277 /* Hardware implementation registers */
2278 /* XXX : not implemented */
2279 spr_register(env, SPR_HID0, "HID0",
2280 SPR_NOACCESS, SPR_NOACCESS,
2281 &spr_read_generic, &spr_write_generic,
2282 0x00000000);
2283 /* XXX : not implemented */
2284 spr_register(env, SPR_HID1, "HID1",
2285 SPR_NOACCESS, SPR_NOACCESS,
2286 &spr_read_generic, &spr_write_generic,
2287 0x00000000);
2288 /* Allocate hardware IRQ controller */
2289 ppc6xx_irq_init(env);
2290 break;
2291
2292 case CPU_PPC_74x: /* PowerPC 740 / 750 */
2293 case CPU_PPC_740E:
2294 case CPU_PPC_750E:
2295 case CPU_PPC_74xP: /* PowerPC 740P / 750P */
2296 case CPU_PPC_750CXE21: /* IBM PowerPC 750cxe */
2297 case CPU_PPC_750CXE22:
2298 case CPU_PPC_750CXE23:
2299 case CPU_PPC_750CXE24:
2300 case CPU_PPC_750CXE24b:
2301 case CPU_PPC_750CXE31:
2302 case CPU_PPC_750CXE31b:
2303 case CPU_PPC_750CXR:
2304 gen_spr_generic(env);
2305 gen_spr_ne_601(env);
2306 /* Memory management */
2307 gen_low_BATs(env);
2308 /* Time base */
2309 gen_tbl(env);
2310 gen_spr_7xx(env);
2311 /* Hardware implementation registers */
2312 /* XXX : not implemented */
2313 spr_register(env, SPR_HID0, "HID0",
2314 SPR_NOACCESS, SPR_NOACCESS,
2315 &spr_read_generic, &spr_write_generic,
2316 0x00000000);
2317 /* XXX : not implemented */
2318 spr_register(env, SPR_HID1, "HID1",
2319 SPR_NOACCESS, SPR_NOACCESS,
2320 &spr_read_generic, &spr_write_generic,
2321 0x00000000);
2322 /* Allocate hardware IRQ controller */
2323 ppc6xx_irq_init(env);
2324 break;
2325
2326 case CPU_PPC_750FX10: /* IBM PowerPC 750 FX */
2327 case CPU_PPC_750FX20:
2328 case CPU_PPC_750FX21:
2329 case CPU_PPC_750FX22:
2330 case CPU_PPC_750FX23:
2331 case CPU_PPC_750GX10: /* IBM PowerPC 750 GX */
2332 case CPU_PPC_750GX11:
2333 case CPU_PPC_750GX12:
2334 gen_spr_generic(env);
2335 gen_spr_ne_601(env);
2336 /* Memory management */
2337 gen_low_BATs(env);
2338 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
2339 gen_high_BATs(env);
2340 /* Time base */
2341 gen_tbl(env);
2342 gen_spr_7xx(env);
2343 /* Hardware implementation registers */
2344 /* XXX : not implemented */
2345 spr_register(env, SPR_HID0, "HID0",
2346 SPR_NOACCESS, SPR_NOACCESS,
2347 &spr_read_generic, &spr_write_generic,
2348 0x00000000);
2349 /* XXX : not implemented */
2350 spr_register(env, SPR_HID1, "HID1",
2351 SPR_NOACCESS, SPR_NOACCESS,
2352 &spr_read_generic, &spr_write_generic,
2353 0x00000000);
2354 /* XXX : not implemented */
2355 spr_register(env, SPR_750_HID2, "HID2",
2356 SPR_NOACCESS, SPR_NOACCESS,
2357 &spr_read_generic, &spr_write_generic,
2358 0x00000000);
2359 /* Allocate hardware IRQ controller */
2360 ppc6xx_irq_init(env);
2361 break;
2362
2363 case CPU_PPC_755_10: /* PowerPC 755 */
2364 case CPU_PPC_755_11:
2365 case CPU_PPC_755_20:
2366 case CPU_PPC_755D:
2367 case CPU_PPC_755E:
2368 gen_spr_generic(env);
2369 gen_spr_ne_601(env);
2370 /* Memory management */
2371 gen_low_BATs(env);
2372 /* Time base */
2373 gen_tbl(env);
2374 /* Memory management */
2375 gen_high_BATs(env);
2376 gen_6xx_7xx_soft_tlb(env, 64, 2);
2377 gen_spr_G2_755(env);
2378 /* L2 cache control */
2379 /* XXX : not implemented */
2380 spr_register(env, SPR_ICTC, "ICTC",
2381 SPR_NOACCESS, SPR_NOACCESS,
2382 &spr_read_generic, &spr_write_generic,
2383 0x00000000);
2384 /* XXX : not implemented */
2385 spr_register(env, SPR_L2PM, "L2PM",
2386 SPR_NOACCESS, SPR_NOACCESS,
2387 &spr_read_generic, &spr_write_generic,
2388 0x00000000);
2389 /* Hardware implementation registers */
2390 /* XXX : not implemented */
2391 spr_register(env, SPR_HID0, "HID0",
2392 SPR_NOACCESS, SPR_NOACCESS,
2393 &spr_read_generic, &spr_write_generic,
2394 0x00000000);
2395 /* XXX : not implemented */
2396 spr_register(env, SPR_HID1, "HID1",
2397 SPR_NOACCESS, SPR_NOACCESS,
2398 &spr_read_generic, &spr_write_generic,
2399 0x00000000);
2400 /* XXX : not implemented */
2401 spr_register(env, SPR_HID2, "HID2",
2402 SPR_NOACCESS, SPR_NOACCESS,
2403 &spr_read_generic, &spr_write_generic,
2404 0x00000000);
2405 /* Allocate hardware IRQ controller */
2406 ppc6xx_irq_init(env);
2407 break;
2408
2409 #if defined (TODO)
2410 /* G4 family */
2411 case CPU_PPC_7400: /* PowerPC 7400 */
2412 case CPU_PPC_7410C: /* PowerPC 7410 */
2413 case CPU_PPC_7410D:
2414 case CPU_PPC_7410E:
2415 case CPU_PPC_7441: /* PowerPC 7441 */
2416 case CPU_PPC_7445: /* PowerPC 7445 */
2417 case CPU_PPC_7447: /* PowerPC 7447 */
2418 case CPU_PPC_7447A: /* PowerPC 7447A */
2419 case CPU_PPC_7448: /* PowerPC 7448 */
2420 case CPU_PPC_7450: /* PowerPC 7450 */
2421 case CPU_PPC_7450b:
2422 case CPU_PPC_7451: /* PowerPC 7451 */
2423 case CPU_PPC_7451G:
2424 case CPU_PPC_7455: /* PowerPC 7455 */
2425 case CPU_PPC_7455F:
2426 case CPU_PPC_7455G:
2427 case CPU_PPC_7457: /* PowerPC 7457 */
2428 case CPU_PPC_7457C:
2429 case CPU_PPC_7457A: /* PowerPC 7457A */
2430 break;
2431 #endif
2432
2433 /* 64 bits PowerPC */
2434 #if defined (TARGET_PPC64)
2435 #if defined (TODO)
2436 case CPU_PPC_620: /* PowerPC 620 */
2437 case CPU_PPC_630: /* PowerPC 630 (Power 3) */
2438 case CPU_PPC_631: /* PowerPC 631 (Power 3+) */
2439 case CPU_PPC_POWER4: /* Power 4 */
2440 case CPU_PPC_POWER4P: /* Power 4+ */
2441 case CPU_PPC_POWER5: /* Power 5 */
2442 case CPU_PPC_POWER5P: /* Power 5+ */
2443 #endif
2444 break;
2445
2446 case CPU_PPC_970: /* PowerPC 970 */
2447 case CPU_PPC_970FX10: /* PowerPC 970 FX */
2448 case CPU_PPC_970FX20:
2449 case CPU_PPC_970FX21:
2450 case CPU_PPC_970FX30:
2451 case CPU_PPC_970FX31:
2452 case CPU_PPC_970MP10: /* PowerPC 970 MP */
2453 case CPU_PPC_970MP11:
2454 gen_spr_generic(env);
2455 gen_spr_ne_601(env);
2456 /* XXX: not correct */
2457 gen_low_BATs(env);
2458 /* Time base */
2459 gen_tbl(env);
2460 gen_spr_7xx(env);
2461 /* Hardware implementation registers */
2462 /* XXX : not implemented */
2463 spr_register(env, SPR_HID0, "HID0",
2464 SPR_NOACCESS, SPR_NOACCESS,
2465 &spr_read_generic, &spr_write_generic,
2466 0x00000000);
2467 /* XXX : not implemented */
2468 spr_register(env, SPR_HID1, "HID1",
2469 SPR_NOACCESS, SPR_NOACCESS,
2470 &spr_read_generic, &spr_write_generic,
2471 0x00000000);
2472 /* XXX : not implemented */
2473 spr_register(env, SPR_750_HID2, "HID2",
2474 SPR_NOACCESS, SPR_NOACCESS,
2475 &spr_read_generic, &spr_write_generic,
2476 0x00000000);
2477 /* Allocate hardware IRQ controller */
2478 ppc970_irq_init(env);
2479 break;
2480
2481 #if defined (TODO)
2482 case CPU_PPC_CELL10: /* Cell family */
2483 case CPU_PPC_CELL20:
2484 case CPU_PPC_CELL30:
2485 case CPU_PPC_CELL31:
2486 #endif
2487 break;
2488
2489 #if defined (TODO)
2490 case CPU_PPC_RS64: /* Apache (RS64/A35) */
2491 case CPU_PPC_RS64II: /* NorthStar (RS64-II/A50) */
2492 case CPU_PPC_RS64III: /* Pulsar (RS64-III) */
2493 case CPU_PPC_RS64IV: /* IceStar/IStar/SStar (RS64-IV) */
2494 #endif
2495 break;
2496 #endif /* defined (TARGET_PPC64) */
2497
2498 #if defined (TODO)
2499 /* POWER */
2500 case CPU_POWER: /* POWER */
2501 case CPU_POWER2: /* POWER2 */
2502 break;
2503 #endif
2504
2505 default:
2506 gen_spr_generic(env);
2507 /* XXX: TODO: allocate internal IRQ controller */
2508 break;
2509 }
2510 if (env->nb_BATs == -1)
2511 env->nb_BATs = 4;
2512 /* Allocate TLBs buffer when needed */
2513 if (env->nb_tlb != 0) {
2514 int nb_tlb = env->nb_tlb;
2515 if (env->id_tlbs != 0)
2516 nb_tlb *= 2;
2517 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
2518 /* Pre-compute some useful values */
2519 env->tlb_per_way = env->nb_tlb / env->nb_ways;
2520 }
2521 }
2522
2523 #if defined(PPC_DUMP_CPU)
2524 static void dump_sprs (CPUPPCState *env)
2525 {
2526 ppc_spr_t *spr;
2527 uint32_t pvr = env->spr[SPR_PVR];
2528 uint32_t sr, sw, ur, uw;
2529 int i, j, n;
2530
2531 printf("* SPRs for PVR=%08x\n", pvr);
2532 for (i = 0; i < 32; i++) {
2533 for (j = 0; j < 32; j++) {
2534 n = (i << 5) | j;
2535 spr = &env->spr_cb[n];
2536 #if !defined(CONFIG_USER_ONLY)
2537 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
2538 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
2539 #else
2540 sw = 0;
2541 sr = 0;
2542 #endif
2543 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
2544 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
2545 if (sw || sr || uw || ur) {
2546 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
2547 (i << 5) | j, (i << 5) | j, spr->name,
2548 sw ? 'w' : '-', sr ? 'r' : '-',
2549 uw ? 'w' : '-', ur ? 'r' : '-');
2550 }
2551 }
2552 }
2553 fflush(stdout);
2554 fflush(stderr);
2555 }
2556 #endif
2557
2558 /*****************************************************************************/
2559 #include <stdlib.h>
2560 #include <string.h>
2561
2562 int fflush (FILE *stream);
2563
2564 /* Opcode types */
2565 enum {
2566 PPC_DIRECT = 0, /* Opcode routine */
2567 PPC_INDIRECT = 1, /* Indirect opcode table */
2568 };
2569
2570 static inline int is_indirect_opcode (void *handler)
2571 {
2572 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
2573 }
2574
2575 static inline opc_handler_t **ind_table(void *handler)
2576 {
2577 return (opc_handler_t **)((unsigned long)handler & ~3);
2578 }
2579
2580 /* Instruction table creation */
2581 /* Opcodes tables creation */
2582 static void fill_new_table (opc_handler_t **table, int len)
2583 {
2584 int i;
2585
2586 for (i = 0; i < len; i++)
2587 table[i] = &invalid_handler;
2588 }
2589
2590 static int create_new_table (opc_handler_t **table, unsigned char idx)
2591 {
2592 opc_handler_t **tmp;
2593
2594 tmp = malloc(0x20 * sizeof(opc_handler_t));
2595 if (tmp == NULL)
2596 return -1;
2597 fill_new_table(tmp, 0x20);
2598 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
2599
2600 return 0;
2601 }
2602
2603 static int insert_in_table (opc_handler_t **table, unsigned char idx,
2604 opc_handler_t *handler)
2605 {
2606 if (table[idx] != &invalid_handler)
2607 return -1;
2608 table[idx] = handler;
2609
2610 return 0;
2611 }
2612
2613 static int register_direct_insn (opc_handler_t **ppc_opcodes,
2614 unsigned char idx, opc_handler_t *handler)
2615 {
2616 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
2617 printf("*** ERROR: opcode %02x already assigned in main "
2618 "opcode table\n", idx);
2619 return -1;
2620 }
2621
2622 return 0;
2623 }
2624
2625 static int register_ind_in_table (opc_handler_t **table,
2626 unsigned char idx1, unsigned char idx2,
2627 opc_handler_t *handler)
2628 {
2629 if (table[idx1] == &invalid_handler) {
2630 if (create_new_table(table, idx1) < 0) {
2631 printf("*** ERROR: unable to create indirect table "
2632 "idx=%02x\n", idx1);
2633 return -1;
2634 }
2635 } else {
2636 if (!is_indirect_opcode(table[idx1])) {
2637 printf("*** ERROR: idx %02x already assigned to a direct "
2638 "opcode\n", idx1);
2639 return -1;
2640 }
2641 }
2642 if (handler != NULL &&
2643 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
2644 printf("*** ERROR: opcode %02x already assigned in "
2645 "opcode table %02x\n", idx2, idx1);
2646 return -1;
2647 }
2648
2649 return 0;
2650 }
2651
2652 static int register_ind_insn (opc_handler_t **ppc_opcodes,
2653 unsigned char idx1, unsigned char idx2,
2654 opc_handler_t *handler)
2655 {
2656 int ret;
2657
2658 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
2659
2660 return ret;
2661 }
2662
2663 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
2664 unsigned char idx1, unsigned char idx2,
2665 unsigned char idx3, opc_handler_t *handler)
2666 {
2667 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
2668 printf("*** ERROR: unable to join indirect table idx "
2669 "[%02x-%02x]\n", idx1, idx2);
2670 return -1;
2671 }
2672 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
2673 handler) < 0) {
2674 printf("*** ERROR: unable to insert opcode "
2675 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
2676 return -1;
2677 }
2678
2679 return 0;
2680 }
2681
2682 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
2683 {
2684 if (insn->opc2 != 0xFF) {
2685 if (insn->opc3 != 0xFF) {
2686 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
2687 insn->opc3, &insn->handler) < 0)
2688 return -1;
2689 } else {
2690 if (register_ind_insn(ppc_opcodes, insn->opc1,
2691 insn->opc2, &insn->handler) < 0)
2692 return -1;
2693 }
2694 } else {
2695 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
2696 return -1;
2697 }
2698
2699 return 0;
2700 }
2701
2702 static int test_opcode_table (opc_handler_t **table, int len)
2703 {
2704 int i, count, tmp;
2705
2706 for (i = 0, count = 0; i < len; i++) {
2707 /* Consistency fixup */
2708 if (table[i] == NULL)
2709 table[i] = &invalid_handler;
2710 if (table[i] != &invalid_handler) {
2711 if (is_indirect_opcode(table[i])) {
2712 tmp = test_opcode_table(ind_table(table[i]), 0x20);
2713 if (tmp == 0) {
2714 free(table[i]);
2715 table[i] = &invalid_handler;
2716 } else {
2717 count++;
2718 }
2719 } else {
2720 count++;
2721 }
2722 }
2723 }
2724
2725 return count;
2726 }
2727
2728 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
2729 {
2730 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
2731 printf("*** WARNING: no opcode defined !\n");
2732 }
2733
2734 /*****************************************************************************/
2735 static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def)
2736 {
2737 opcode_t *opc, *start, *end;
2738
2739 fill_new_table(env->opcodes, 0x40);
2740 #if defined(PPC_DUMP_CPU)
2741 printf("* PowerPC instructions for PVR %08x: %s flags %016" PRIx64
2742 " %08x\n",
2743 def->pvr, def->name, def->insns_flags, def->flags);
2744 #endif
2745 if (&opc_start < &opc_end) {
2746 start = &opc_start;
2747 end = &opc_end;
2748 } else {
2749 start = &opc_end;
2750 end = &opc_start;
2751 }
2752 for (opc = start + 1; opc != end; opc++) {
2753 if ((opc->handler.type & def->insns_flags) != 0) {
2754 if (register_insn(env->opcodes, opc) < 0) {
2755 printf("*** ERROR initializing PowerPC instruction "
2756 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
2757 opc->opc3);
2758 return -1;
2759 }
2760 #if defined(PPC_DUMP_CPU)
2761 if (opc1 != 0x00) {
2762 if (opc->opc3 == 0xFF) {
2763 if (opc->opc2 == 0xFF) {
2764 printf("INSN: %02x -- -- (%02d ----) : %s\n",
2765 opc->opc1, opc->opc1, opc->oname);
2766 } else {
2767 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
2768 opc->opc1, opc->opc2, opc->opc1, opc->opc2,
2769 opc->oname);
2770 }
2771 } else {
2772 printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
2773 opc->opc1, opc->opc2, opc->opc3,
2774 opc->opc1, (opc->opc3 << 5) | opc->opc2,
2775 opc->oname);
2776 }
2777 }
2778 #endif
2779 }
2780 }
2781 fix_opcode_tables(env->opcodes);
2782 fflush(stdout);
2783 fflush(stderr);
2784
2785 return 0;
2786 }
2787
2788 int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
2789 {
2790 env->msr_mask = def->msr_mask;
2791 env->flags = def->flags;
2792 if (create_ppc_opcodes(env, def) < 0)
2793 return -1;
2794 init_ppc_proc(env, def);
2795 #if defined(PPC_DUMP_CPU)
2796 dump_sprs(env);
2797 if (env->tlb != NULL) {
2798 printf("%d %s TLB in %d ways\n", env->nb_tlb,
2799 env->id_tlbs ? "splitted" : "merged", env->nb_ways);
2800 }
2801 #endif
2802
2803 return 0;
2804 }
2805
2806 /*****************************************************************************/
2807 /* PowerPC CPU definitions */
2808 static ppc_def_t ppc_defs[] = {
2809 /* Embedded PowerPC */
2810 /* Generic PowerPC 401 */
2811 {
2812 .name = "401",
2813 .pvr = CPU_PPC_401,
2814 .pvr_mask = 0xFFFFFFFF,
2815 .insns_flags = PPC_INSNS_401,
2816 .flags = PPC_FLAGS_401,
2817 .msr_mask = 0x000FD201,
2818 },
2819 /* PowerPC 401A1 */
2820 {
2821 .name = "401a1",
2822 .pvr = CPU_PPC_401A1,
2823 .pvr_mask = 0xFFFFFFFF,
2824 .insns_flags = PPC_INSNS_401,
2825 .flags = PPC_FLAGS_401,
2826 .msr_mask = 0x000FD201,
2827 },
2828 /* PowerPC 401B2 */
2829 {
2830 .name = "401b2",
2831 .pvr = CPU_PPC_401B2,
2832 .pvr_mask = 0xFFFFFFFF,
2833 .insns_flags = PPC_INSNS_401,
2834 .flags = PPC_FLAGS_401,
2835 .msr_mask = 0x000FD201,
2836 },
2837 #if defined (TODO)
2838 /* PowerPC 401B3 */
2839 {
2840 .name = "401b3",
2841 .pvr = CPU_PPC_401B3,
2842 .pvr_mask = 0xFFFFFFFF,
2843 .insns_flags = PPC_INSNS_401,
2844 .flags = PPC_FLAGS_401,
2845 .msr_mask = 0x000FD201,
2846 },
2847 #endif
2848 /* PowerPC 401C2 */
2849 {
2850 .name = "401c2",
2851 .pvr = CPU_PPC_401C2,
2852 .pvr_mask = 0xFFFFFFFF,
2853 .insns_flags = PPC_INSNS_401,
2854 .flags = PPC_FLAGS_401,
2855 .msr_mask = 0x000FD201,
2856 },
2857 /* PowerPC 401D2 */
2858 {
2859 .name = "401d2",
2860 .pvr = CPU_PPC_401D2,
2861 .pvr_mask = 0xFFFFFFFF,
2862 .insns_flags = PPC_INSNS_401,
2863 .flags = PPC_FLAGS_401,
2864 .msr_mask = 0x000FD201,
2865 },
2866 /* PowerPC 401E2 */
2867 {
2868 .name = "401e2",
2869 .pvr = CPU_PPC_401E2,
2870 .pvr_mask = 0xFFFFFFFF,
2871 .insns_flags = PPC_INSNS_401,
2872 .flags = PPC_FLAGS_401,
2873 .msr_mask = 0x000FD201,
2874 },
2875 /* PowerPC 401F2 */
2876 {
2877 .name = "401f2",
2878 .pvr = CPU_PPC_401F2,
2879 .pvr_mask = 0xFFFFFFFF,
2880 .insns_flags = PPC_INSNS_401,
2881 .flags = PPC_FLAGS_401,
2882 .msr_mask = 0x000FD201,
2883 },
2884 /* PowerPC 401G2 */
2885 {
2886 .name = "401g2",
2887 .pvr = CPU_PPC_401G2,
2888 .pvr_mask = 0xFFFFFFFF,
2889 .insns_flags = PPC_INSNS_401,
2890 .flags = PPC_FLAGS_401,
2891 .msr_mask = 0x000FD201,
2892 },
2893 #if defined (TODO)
2894 /* PowerPC 401G2 */
2895 {
2896 .name = "401gf",
2897 .pvr = CPU_PPC_401GF,
2898 .pvr_mask = 0xFFFFFFFF,
2899 .insns_flags = PPC_INSNS_401,
2900 .flags = PPC_FLAGS_401,
2901 .msr_mask = 0x000FD201,
2902 },
2903 #endif
2904 #if defined (TODO)
2905 /* IOP480 (401 microcontroler) */
2906 {
2907 .name = "iop480",
2908 .pvr = CPU_PPC_IOP480,
2909 .pvr_mask = 0xFFFFFFFF,
2910 .insns_flags = PPC_INSNS_401,
2911 .flags = PPC_FLAGS_401,
2912 .msr_mask = 0x000FD201,
2913 },
2914 #endif
2915 #if defined (TODO)
2916 /* IBM Processor for Network Resources */
2917 {
2918 .name = "Cobra",
2919 .pvr = CPU_PPC_COBRA,
2920 .pvr_mask = 0xFFFFFFFF,
2921 .insns_flags = PPC_INSNS_401,
2922 .flags = PPC_FLAGS_401,
2923 .msr_mask = 0x000FD201,
2924 },
2925 #endif
2926 /* Generic PowerPC 403 */
2927 {
2928 .name = "403",
2929 .pvr = CPU_PPC_403,
2930 .pvr_mask = 0xFFFFFFFF,
2931 .insns_flags = PPC_INSNS_403,
2932 .flags = PPC_FLAGS_403,
2933 .msr_mask = 0x000000000007D23DULL,
2934 },
2935 /* PowerPC 403 GA */
2936 {
2937 .name = "403ga",
2938 .pvr = CPU_PPC_403GA,
2939 .pvr_mask = 0xFFFFFFFF,
2940 .insns_flags = PPC_INSNS_403,
2941 .flags = PPC_FLAGS_403,
2942 .msr_mask = 0x000000000007D23DULL,
2943 },
2944 /* PowerPC 403 GB */
2945 {
2946 .name = "403gb",
2947 .pvr = CPU_PPC_403GB,
2948 .pvr_mask = 0xFFFFFFFF,
2949 .insns_flags = PPC_INSNS_403,
2950 .flags = PPC_FLAGS_403,
2951 .msr_mask = 0x000000000007D23DULL,
2952 },
2953 /* PowerPC 403 GC */
2954 {
2955 .name = "403gc",
2956 .pvr = CPU_PPC_403GC,
2957 .pvr_mask = 0xFFFFFFFF,
2958 .insns_flags = PPC_INSNS_403,
2959 .flags = PPC_FLAGS_403,
2960 .msr_mask = 0x000000000007D23DULL,
2961 },
2962 /* PowerPC 403 GCX */
2963 {
2964 .name = "403gcx",
2965 .pvr = CPU_PPC_403GCX,
2966 .pvr_mask = 0xFFFFFFFF,
2967 .insns_flags = PPC_INSNS_403,
2968 .flags = PPC_FLAGS_403,
2969 .msr_mask = 0x000000000007D23DULL,
2970 },
2971 #if defined (TODO)
2972 /* PowerPC 403 GP */
2973 {
2974 .name = "403gp",
2975 .pvr = CPU_PPC_403GP,
2976 .pvr_mask = 0xFFFFFFFF,
2977 .insns_flags = PPC_INSNS_403,
2978 .flags = PPC_FLAGS_403,
2979 .msr_mask = 0x000000000007D23DULL,
2980 },
2981 #endif
2982 /* Generic PowerPC 405 */
2983 {
2984 .name = "405",
2985 .pvr = CPU_PPC_405,
2986 .pvr_mask = 0xFFFFFFFF,
2987 .insns_flags = PPC_INSNS_405,
2988 .flags = PPC_FLAGS_405,
2989 .msr_mask = 0x00000000020EFF30ULL,
2990 },
2991 #if defined (TODO)
2992 /* PowerPC 405 A3 */
2993 {
2994 .name = "405a3",
2995 .pvr = CPU_PPC_405A3,
2996 .pvr_mask = 0xFFFFFFFF,
2997 .insns_flags = PPC_INSNS_405,
2998 .flags = PPC_FLAGS_405,
2999 .msr_mask = 0x00000000020EFF30ULL,
3000 },
3001 #endif
3002 #if defined (TODO)
3003 /* PowerPC 405 A4 */
3004 {
3005 .name = "405a4",
3006 .pvr = CPU_PPC_405A4,
3007 .pvr_mask = 0xFFFFFFFF,
3008 .insns_flags = PPC_INSNS_405,
3009 .flags = PPC_FLAGS_405,
3010 .msr_mask = 0x00000000020EFF30ULL,
3011 },
3012 #endif
3013 #if defined (TODO)
3014 /* PowerPC 405 B3 */
3015 {
3016 .name = "405b3",
3017 .pvr = CPU_PPC_405B3,
3018 .pvr_mask = 0xFFFFFFFF,
3019 .insns_flags = PPC_INSNS_405,
3020 .flags = PPC_FLAGS_405,
3021 .msr_mask = 0x00000000020EFF30ULL,
3022 },
3023 #endif
3024 /* PowerPC 405 D2 */
3025 {
3026 .name = "405d2",
3027 .pvr = CPU_PPC_405D2,
3028 .pvr_mask = 0xFFFFFFFF,
3029 .insns_flags = PPC_INSNS_405,
3030 .flags = PPC_FLAGS_405,
3031 .msr_mask = 0x00000000020EFF30ULL,
3032 },
3033 /* PowerPC 405 D4 */
3034 {
3035 .name = "405d4",
3036 .pvr = CPU_PPC_405D4,
3037 .pvr_mask = 0xFFFFFFFF,
3038 .insns_flags = PPC_INSNS_405,
3039 .flags = PPC_FLAGS_405,
3040 .msr_mask = 0x00000000020EFF30ULL,
3041 },
3042 /* PowerPC 405 CR */
3043 {
3044 .name = "405cr",
3045 .pvr = CPU_PPC_405CR,
3046 .pvr_mask = 0xFFFFFFFF,
3047 .insns_flags = PPC_INSNS_405,
3048 .flags = PPC_FLAGS_405,
3049 .msr_mask = 0x00000000020EFF30ULL,
3050 },
3051 /* PowerPC 405 GP */
3052 {
3053 .name = "405gp",
3054 .pvr = CPU_PPC_405GP,
3055 .pvr_mask = 0xFFFFFFFF,
3056 .insns_flags = PPC_INSNS_405,
3057 .flags = PPC_FLAGS_405,
3058 .msr_mask = 0x00000000020EFF30ULL,
3059 },
3060 /* PowerPC 405 EP */
3061 {
3062 .name = "405ep",
3063 .pvr = CPU_PPC_405EP,
3064 .pvr_mask = 0xFFFFFFFF,
3065 .insns_flags = PPC_INSNS_405,
3066 .flags = PPC_FLAGS_405,
3067 .msr_mask = 0x00000000000ED630ULL,
3068 },
3069 #if defined (TODO)
3070 /* PowerPC 405 EZ */
3071 {
3072 .name = "405ez",
3073 .pvr = CPU_PPC_405EZ,
3074 .pvr_mask = 0xFFFFFFFF,
3075 .insns_flags = PPC_INSNS_405,
3076 .flags = PPC_FLAGS_405,
3077 .msr_mask = 0x00000000020EFF30ULL,
3078 },
3079 #endif
3080 #if defined (TODO)
3081 /* PowerPC 405 GPR */
3082 {
3083 .name = "405gpr",
3084 .pvr = CPU_PPC_405GPR,
3085 .pvr_mask = 0xFFFFFFFF,
3086 .insns_flags = PPC_INSNS_405,
3087 .flags = PPC_FLAGS_405,
3088 .msr_mask = 0x00000000020EFF30ULL,
3089 },
3090 #endif
3091 #if defined (TODO)
3092 /* PowerPC 405 LP */
3093 {
3094 .name = "405lp",
3095 .pvr = CPU_PPC_405EZ,
3096 .pvr_mask = 0xFFFFFFFF,
3097 .insns_flags = PPC_INSNS_405,
3098 .flags = PPC_FLAGS_405,
3099 .msr_mask = 0x00000000020EFF30ULL,
3100 },
3101 #endif
3102 /* Npe405 H */
3103 {
3104 .name = "Npe405H",
3105 .pvr = CPU_PPC_NPE405H,
3106 .pvr_mask = 0xFFFFFFFF,
3107 .insns_flags = PPC_INSNS_405,
3108 .flags = PPC_FLAGS_405,
3109 .msr_mask = 0x00000000020EFF30ULL,
3110 },
3111 /* Npe405 H2 */
3112 {
3113 .name = "Npe405H2",
3114 .pvr = CPU_PPC_NPE405H2,
3115 .pvr_mask = 0xFFFFFFFF,
3116 .insns_flags = PPC_INSNS_405,
3117 .flags = PPC_FLAGS_405,
3118 .msr_mask = 0x00000000020EFF30ULL,
3119 },
3120 /* Npe405 L */
3121 {
3122 .name = "Npe405L",
3123 .pvr = CPU_PPC_NPE405L,
3124 .pvr_mask = 0xFFFFFFFF,
3125 .insns_flags = PPC_INSNS_405,
3126 .flags = PPC_FLAGS_405,
3127 .msr_mask = 0x00000000020EFF30ULL,
3128 },
3129 #if defined (TODO)
3130 /* PowerPC LP777000 */
3131 {
3132 .name = "lp777000",
3133 .pvr = CPU_PPC_LP777000,
3134 .pvr_mask = 0xFFFFFFFF,
3135 .insns_flags = PPC_INSNS_405,
3136 .flags = PPC_FLAGS_405,
3137 .msr_mask = 0x00000000020EFF30ULL,
3138 },
3139 #endif
3140 #if defined (TODO)
3141 /* STB010000 */
3142 {
3143 .name = "STB01000",
3144 .pvr = CPU_PPC_STB01000,
3145 .pvr_mask = 0xFFFFFFFF,
3146 .insns_flags = PPC_INSNS_405,
3147 .flags = PPC_FLAGS_405,
3148 .msr_mask = 0x00000000020EFF30ULL,
3149 },
3150 #endif
3151 #if defined (TODO)
3152 /* STB01010 */
3153 {
3154 .name = "STB01010",
3155 .pvr = CPU_PPC_STB01010,
3156 .pvr_mask = 0xFFFFFFFF,
3157 .insns_flags = PPC_INSNS_405,
3158 .flags = PPC_FLAGS_405,
3159 .msr_mask = 0x00000000020EFF30ULL,
3160 },
3161 #endif
3162 #if defined (TODO)
3163 /* STB0210 */
3164 {
3165 .name = "STB0210",
3166 .pvr = CPU_PPC_STB0210,
3167 .pvr_mask = 0xFFFFFFFF,
3168 .insns_flags = PPC_INSNS_405,
3169 .flags = PPC_FLAGS_405,
3170 .msr_mask = 0x00000000020EFF30ULL,
3171 },
3172 #endif
3173 #if defined (TODO)
3174 /* STB03xx */
3175 {
3176 .name = "STB03",
3177 .pvr = CPU_PPC_STB03,
3178 .pvr_mask = 0xFFFFFFFF,
3179 .insns_flags = PPC_INSNS_405,
3180 .flags = PPC_FLAGS_405,
3181 .msr_mask = 0x00000000020EFF30ULL,
3182 },
3183 #endif
3184 #if defined (TODO)
3185 /* STB043x */
3186 {
3187 .name = "STB043",
3188 .pvr = CPU_PPC_STB043,
3189 .pvr_mask = 0xFFFFFFFF,
3190 .insns_flags = PPC_INSNS_405,
3191 .flags = PPC_FLAGS_405,
3192 .msr_mask = 0x00000000020EFF30ULL,
3193 },
3194 #endif
3195 #if defined (TODO)
3196 /* STB045x */
3197 {
3198 .name = "STB045",
3199 .pvr = CPU_PPC_STB045,
3200 .pvr_mask = 0xFFFFFFFF,
3201 .insns_flags = PPC_INSNS_405,
3202 .flags = PPC_FLAGS_405,
3203 .msr_mask = 0x00000000020EFF30ULL,
3204 },
3205 #endif
3206 #if defined (TODO) || 1
3207 /* STB25xx */
3208 {
3209 .name = "STB25",
3210 .pvr = CPU_PPC_STB25,
3211 .pvr_mask = 0xFFFFFFFF,
3212 .insns_flags = PPC_INSNS_405,
3213 .flags = PPC_FLAGS_405,
3214 .msr_mask = 0x00000000020EFF30ULL,
3215 },
3216 #endif
3217 #if defined (TODO)
3218 /* STB130 */
3219 {
3220 .name = "STB130",
3221 .pvr = CPU_PPC_STB130,
3222 .pvr_mask = 0xFFFFFFFF,
3223 .insns_flags = PPC_INSNS_405,
3224 .flags = PPC_FLAGS_405,
3225 .msr_mask = 0x00000000020EFF30ULL,
3226 },
3227 #endif
3228 /* Xilinx PowerPC 405 cores */
3229 #if defined (TODO)
3230 {
3231 .name = "x2vp4",
3232 .pvr = CPU_PPC_X2VP4,
3233 .pvr_mask = 0xFFFFFFFF,
3234 .insns_flags = PPC_INSNS_405,
3235 .flags = PPC_FLAGS_405,
3236 .msr_mask = 0x00000000020EFF30ULL,
3237 },
3238 {
3239 .name = "x2vp7",
3240 .pvr = CPU_PPC_X2VP7,
3241 .pvr_mask = 0xFFFFFFFF,
3242 .insns_flags = PPC_INSNS_405,
3243 .flags = PPC_FLAGS_405,
3244 .msr_mask = 0x00000000020EFF30ULL,
3245 },
3246 {
3247 .name = "x2vp20",
3248 .pvr = CPU_PPC_X2VP20,
3249 .pvr_mask = 0xFFFFFFFF,
3250 .insns_flags = PPC_INSNS_405,
3251 .flags = PPC_FLAGS_405,
3252 .msr_mask = 0x00000000020EFF30ULL,
3253 },
3254 {
3255 .name = "x2vp50",
3256 .pvr = CPU_PPC_X2VP50,
3257 .pvr_mask = 0xFFFFFFFF,
3258 .insns_flags = PPC_INSNS_405,
3259 .flags = PPC_FLAGS_405,
3260 .msr_mask = 0x00000000020EFF30ULL,
3261 },
3262 #endif
3263 /* PowerPC 440 EP */
3264 {
3265 .name = "440ep",
3266 .pvr = CPU_PPC_440EP,
3267 .pvr_mask = 0xFFFFFFFF,
3268 .insns_flags = PPC_INSNS_440,
3269 .flags = PPC_FLAGS_440,
3270 .msr_mask = 0x000000000006D630ULL,
3271 },
3272 /* PowerPC 440 GR */
3273 {
3274 .name = "440gr",
3275 .pvr = CPU_PPC_440GR,
3276 .pvr_mask = 0xFFFFFFFF,
3277 .insns_flags = PPC_INSNS_440,
3278 .flags = PPC_FLAGS_440,
3279 .msr_mask = 0x000000000006D630ULL,
3280 },
3281 /* PowerPC 440 GP */
3282 {
3283 .name = "440gp",
3284 .pvr = CPU_PPC_440GP,
3285 .pvr_mask = 0xFFFFFFFF,
3286 .insns_flags = PPC_INSNS_440,
3287 .flags = PPC_FLAGS_440,
3288 .msr_mask = 0x000000000006D630ULL,
3289 },
3290 #if defined (TODO)
3291 /* PowerPC 440 GRX */
3292 {
3293 .name = "440grx",
3294 .pvr = CPU_PPC_440GRX,
3295 .pvr_mask = 0xFFFFFFFF,
3296 .insns_flags = PPC_INSNS_440,
3297 .flags = PPC_FLAGS_440,
3298 .msr_mask = 0x000000000006D630ULL,
3299 },
3300 #endif
3301 /* PowerPC 440 GX */
3302 {
3303 .name = "440gx",
3304 .pvr = CPU_PPC_440GX,
3305 .pvr_mask = 0xFFFFFFFF,
3306 .insns_flags = PPC_INSNS_440,
3307 .flags = PPC_FLAGS_440,
3308 .msr_mask = 0x000000000006D630ULL,
3309 },
3310 /* PowerPC 440 GXc */
3311 {
3312 .name = "440gxc",
3313 .pvr = CPU_PPC_440GXc,
3314 .pvr_mask = 0xFFFFFFFF,
3315 .insns_flags = PPC_INSNS_440,
3316 .flags = PPC_FLAGS_440,
3317 .msr_mask = 0x000000000006D630ULL,
3318 },
3319 /* PowerPC 440 GXf */
3320 {
3321 .name = "440gxf",
3322 .pvr = CPU_PPC_440GXf,
3323 .pvr_mask = 0xFFFFFFFF,
3324 .insns_flags = PPC_INSNS_440,
3325 .flags = PPC_FLAGS_440,
3326 .msr_mask = 0x000000000006D630ULL,
3327 },
3328 /* PowerPC 440 SP */
3329 {
3330 .name = "440sp",
3331 .pvr = CPU_PPC_440SP,
3332 .pvr_mask = 0xFFFFFFFF,
3333 .insns_flags = PPC_INSNS_440,
3334 .flags = PPC_FLAGS_440,
3335 .msr_mask = 0x000000000006D630ULL,
3336 },
3337 /* PowerPC 440 SP2 */
3338 {
3339 .name = "440sp2",
3340 .pvr = CPU_PPC_440SP2,
3341 .pvr_mask = 0xFFFFFFFF,
3342 .insns_flags = PPC_INSNS_440,
3343 .flags = PPC_FLAGS_440,
3344 .msr_mask = 0x000000000006D630ULL,
3345 },
3346 /* PowerPC 440 SPE */
3347 {
3348 .name = "440spe",
3349 .pvr = CPU_PPC_440SPE,
3350 .pvr_mask = 0xFFFFFFFF,
3351 .insns_flags = PPC_INSNS_440,
3352 .flags = PPC_FLAGS_440,
3353 .msr_mask = 0x000000000006D630ULL,
3354 },
3355 /* Fake generic BookE PowerPC */
3356 {
3357 .name = "BookE",
3358 .pvr = CPU_PPC_e500,
3359 .pvr_mask = 0xFFFFFFFF,
3360 .insns_flags = PPC_INSNS_BOOKE,
3361 .flags = PPC_FLAGS_BOOKE,
3362 .msr_mask = 0x000000000006D630ULL,
3363 },
3364 /* PowerPC 460 cores - TODO */
3365 /* PowerPC MPC 5xx cores - TODO */
3366 /* PowerPC MPC 8xx cores - TODO */
3367 /* PowerPC MPC 8xxx cores - TODO */
3368 /* e200 cores - TODO */
3369 /* e500 cores - TODO */
3370 /* e600 cores - TODO */
3371
3372 /* 32 bits "classic" PowerPC */
3373 #if defined (TODO)
3374 /* PowerPC 601 */
3375 {
3376 .name = "601",
3377 .pvr = CPU_PPC_601,
3378 .pvr_mask = 0xFFFFFFFF,
3379 .insns_flags = PPC_INSNS_601,
3380 .flags = PPC_FLAGS_601,
3381 .msr_mask = 0x000000000000FD70ULL,
3382 },
3383 #endif
3384 #if defined (TODO)
3385 /* PowerPC 602 */
3386 {
3387 .name = "602",
3388 .pvr = CPU_PPC_602,
3389 .pvr_mask = 0xFFFFFFFF,
3390 .insns_flags = PPC_INSNS_602,
3391 .flags = PPC_FLAGS_602,
3392 .msr_mask = 0x0000000000C7FF73ULL,
3393 },
3394 #endif
3395 /* PowerPC 603 */
3396 {
3397 .name = "603",
3398 .pvr = CPU_PPC_603,
3399 .pvr_mask = 0xFFFFFFFF,
3400 .insns_flags = PPC_INSNS_603,
3401 .flags = PPC_FLAGS_603,
3402 .msr_mask = 0x000000000007FF73ULL,
3403 },
3404 /* PowerPC 603e */
3405 {
3406 .name = "603e",
3407 .pvr = CPU_PPC_603E,
3408 .pvr_mask = 0xFFFFFFFF,
3409 .insns_flags = PPC_INSNS_603,
3410 .flags = PPC_FLAGS_603,
3411 .msr_mask = 0x000000000007FF73ULL,
3412 },
3413 {
3414 .name = "Stretch",
3415 .pvr = CPU_PPC_603E,
3416 .pvr_mask = 0xFFFFFFFF,
3417 .insns_flags = PPC_INSNS_603,
3418 .flags = PPC_FLAGS_603,
3419 .msr_mask = 0x000000000007FF73ULL,
3420 },
3421 /* PowerPC 603p */
3422 {
3423 .name = "603p",
3424 .pvr = CPU_PPC_603P,
3425 .pvr_mask = 0xFFFFFFFF,
3426 .insns_flags = PPC_INSNS_603,
3427 .flags = PPC_FLAGS_603,
3428 .msr_mask = 0x000000000007FF73ULL,
3429 },
3430 /* PowerPC 603e7 */
3431 {
3432 .name = "603e7",
3433 .pvr = CPU_PPC_603E7,
3434 .pvr_mask = 0xFFFFFFFF,
3435 .insns_flags = PPC_INSNS_603,
3436 .flags = PPC_FLAGS_603,
3437 .msr_mask = 0x000000000007FF73ULL,
3438 },
3439 /* PowerPC 603e7v */
3440 {
3441 .name = "603e7v",
3442 .pvr = CPU_PPC_603E7v,
3443 .pvr_mask = 0xFFFFFFFF,
3444 .insns_flags = PPC_INSNS_603,
3445 .flags = PPC_FLAGS_603,
3446 .msr_mask = 0x000000000007FF73ULL,
3447 },
3448 /* PowerPC 603e7v2 */
3449 {
3450 .name = "603e7v2",
3451 .pvr = CPU_PPC_603E7v2,
3452 .pvr_mask = 0xFFFFFFFF,
3453 .insns_flags = PPC_INSNS_603,
3454 .flags = PPC_FLAGS_603,
3455 .msr_mask = 0x000000000007FF73ULL,
3456 },
3457 /* PowerPC 603r */
3458 {
3459 .name = "603r",
3460 .pvr = CPU_PPC_603R,
3461 .pvr_mask = 0xFFFFFFFF,
3462 .insns_flags = PPC_INSNS_603,
3463 .flags = PPC_FLAGS_603,
3464 .msr_mask = 0x000000000007FF73ULL,
3465 },
3466 {
3467 .name = "Goldeneye",
3468 .pvr = CPU_PPC_603R,
3469 .pvr_mask = 0xFFFFFFFF,
3470 .insns_flags = PPC_INSNS_603,
3471 .flags = PPC_FLAGS_603,
3472 .msr_mask = 0x000000000007FF73ULL,
3473 },
3474 #if defined (TODO)
3475 /* XXX: TODO: according to Motorola UM, this is a derivative to 603e */
3476 {
3477 .name = "G2",
3478 .pvr = CPU_PPC_G2,
3479 .pvr_mask = 0xFFFFFFFF,
3480 .insns_flags = PPC_INSNS_G2,
3481 .flags = PPC_FLAGS_G2,
3482 .msr_mask = 0x000000000006FFF2ULL,
3483 },
3484 {
3485 .name = "G2h4",
3486 .pvr = CPU_PPC_G2H4,
3487 .pvr_mask = 0xFFFFFFFF,
3488 .insns_flags = PPC_INSNS_G2,
3489 .flags = PPC_FLAGS_G2,
3490 .msr_mask = 0x000000000006FFF2ULL,
3491 },
3492 {
3493 .name = "G2gp",
3494 .pvr = CPU_PPC_G2gp,
3495 .pvr_mask = 0xFFFFFFFF,
3496 .insns_flags = PPC_INSNS_G2,
3497 .flags = PPC_FLAGS_G2,
3498 .msr_mask = 0x000000000006FFF2ULL,
3499 },
3500 {
3501 .name = "G2ls",
3502 .pvr = CPU_PPC_G2ls,
3503 .pvr_mask = 0xFFFFFFFF,
3504 .insns_flags = PPC_INSNS_G2,
3505 .flags = PPC_FLAGS_G2,
3506 .msr_mask = 0x000000000006FFF2ULL,
3507 },
3508 { /* Same as G2, with LE mode support */
3509 .name = "G2le",
3510 .pvr = CPU_PPC_G2LE,
3511 .pvr_mask = 0xFFFFFFFF,
3512 .insns_flags = PPC_INSNS_G2,
3513 .flags = PPC_FLAGS_G2,
3514 .msr_mask = 0x000000000007FFF3ULL,
3515 },
3516 {
3517 .name = "G2legp",
3518 .pvr = CPU_PPC_G2LEgp,
3519 .pvr_mask = 0xFFFFFFFF,
3520 .insns_flags = PPC_INSNS_G2,
3521 .flags = PPC_FLAGS_G2,
3522 .msr_mask = 0x000000000007FFF3ULL,
3523 },
3524 {
3525 .name = "G2lels",
3526 .pvr = CPU_PPC_G2LEls,
3527 .pvr_mask = 0xFFFFFFFF,
3528 .insns_flags = PPC_INSNS_G2,
3529 .flags = PPC_FLAGS_G2,
3530 .msr_mask = 0x000000000007FFF3ULL,
3531 },
3532 #endif
3533 /* PowerPC 604 */
3534 {
3535 .name = "604",
3536 .pvr = CPU_PPC_604,
3537 .pvr_mask = 0xFFFFFFFF,
3538 .insns_flags = PPC_INSNS_604,
3539 .flags = PPC_FLAGS_604,
3540 .msr_mask = 0x000000000005FF77ULL,
3541 },
3542 /* PowerPC 604e */
3543 {
3544 .name = "604e",
3545 .pvr = CPU_PPC_604E,
3546 .pvr_mask = 0xFFFFFFFF,
3547 .insns_flags = PPC_INSNS_604,
3548 .flags = PPC_FLAGS_604,
3549 .msr_mask = 0x000000000005FF77ULL,
3550 },
3551 /* PowerPC 604r */
3552 {
3553 .name = "604r",
3554 .pvr = CPU_PPC_604R,
3555 .pvr_mask = 0xFFFFFFFF,
3556 .insns_flags = PPC_INSNS_604,
3557 .flags = PPC_FLAGS_604,
3558 .msr_mask = 0x000000000005FF77ULL,
3559 },
3560 /* generic G3 */
3561 {
3562 .name = "G3",
3563 .pvr = CPU_PPC_74x,
3564 .pvr_mask = 0xFFFFFFFF,
3565 .insns_flags = PPC_INSNS_7x0,
3566 .flags = PPC_FLAGS_7x0,
3567 .msr_mask = 0x000000000007FF77ULL,
3568 },
3569 /* MPC740 (G3) */
3570 {
3571 .name = "740",
3572 .pvr = CPU_PPC_74x,
3573 .pvr_mask = 0xFFFFFFFF,
3574 .insns_flags = PPC_INSNS_7x0,
3575 .flags = PPC_FLAGS_7x0,
3576 .msr_mask = 0x000000000007FF77ULL,
3577 },
3578 {
3579 .name = "Arthur",
3580 .pvr = CPU_PPC_74x,
3581 .pvr_mask = 0xFFFFFFFF,
3582 .insns_flags = PPC_INSNS_7x0,
3583 .flags = PPC_FLAGS_7x0,
3584 .msr_mask = 0x000000000007FF77ULL,
3585 },
3586 /* 740E (G3) */
3587 {
3588 .name = "740e",
3589 .pvr = CPU_PPC_740E,
3590 .pvr_mask = 0xFFFFFFFF,
3591 .insns_flags = PPC_INSNS_7x0,
3592 .flags = PPC_FLAGS_7x0,
3593 .msr_mask = 0x000000000007FF77ULL,
3594 },
3595 /* MPC740P (G3) */
3596 {
3597 .name = "740p",
3598 .pvr = CPU_PPC_74xP,
3599 .pvr_mask = 0xFFFFFFFF,
3600 .insns_flags = PPC_INSNS_7x0,
3601 .flags = PPC_FLAGS_7x0,
3602 .msr_mask = 0x000000000007FF77ULL,
3603 },
3604 {
3605 .name = "Conan/Doyle",
3606 .pvr = CPU_PPC_74xP,
3607 .pvr_mask = 0xFFFFFFFF,
3608 .insns_flags = PPC_INSNS_7x0,
3609 .flags = PPC_FLAGS_7x0,
3610 .msr_mask = 0x000000000007FF77ULL,
3611 },
3612 #if defined (TODO)
3613 /* MPC745 (G3) */
3614 {
3615 .name = "745",
3616 .pvr = CPU_PPC_74x,
3617 .pvr_mask = 0xFFFFFFFF,
3618 .insns_flags = PPC_INSNS_7x5,
3619 .flags = PPC_FLAGS_7x5,
3620 .msr_mask = 0x000000000007FF77ULL,
3621 },
3622 {
3623 .name = "Goldfinger",
3624 .pvr = CPU_PPC_74x,
3625 .pvr_mask = 0xFFFFFFFF,
3626 .insns_flags = PPC_INSNS_7x5,
3627 .flags = PPC_FLAGS_7x5,
3628 .msr_mask = 0x000000000007FF77ULL,
3629 },
3630 #endif
3631 #if defined (TODO)
3632 /* MPC745P (G3) */
3633 {
3634 .name = "745p",
3635 .pvr = CPU_PPC_74xP,
3636 .pvr_mask = 0xFFFFFFFF,
3637 .insns_flags = PPC_INSNS_7x5,
3638 .flags = PPC_FLAGS_7x5,
3639 .msr_mask = 0x000000000007FF77ULL,
3640 },
3641 #endif
3642 /* MPC750 (G3) */
3643 {
3644 .name = "750",
3645 .pvr = CPU_PPC_74x,
3646 .pvr_mask = 0xFFFFFFFF,
3647 .insns_flags = PPC_INSNS_7x0,
3648 .flags = PPC_FLAGS_7x0,
3649 .msr_mask = 0x000000000007FF77ULL,
3650 },
3651 /* MPC750P (G3) */
3652 {
3653 .name = "750p",
3654 .pvr = CPU_PPC_74xP,
3655 .pvr_mask = 0xFFFFFFFF,
3656 .insns_flags = PPC_INSNS_7x0,
3657 .flags = PPC_FLAGS_7x0,
3658 .msr_mask = 0x000000000007FF77ULL,
3659 },
3660 /* 750E (G3) */
3661 {
3662 .name = "750e",
3663 .pvr = CPU_PPC_750E,
3664 .pvr_mask = 0xFFFFFFFF,
3665 .insns_flags = PPC_INSNS_7x0,
3666 .flags = PPC_FLAGS_7x0,
3667 .msr_mask = 0x000000000007FF77ULL,
3668 },
3669 /* IBM 750CXe (G3 embedded) */
3670 {
3671 .name = "750cxe",
3672 .pvr = CPU_PPC_750CXE,
3673 .pvr_mask = 0xFFFFFFFF,
3674 .insns_flags = PPC_INSNS_7x0,
3675 .flags = PPC_FLAGS_7x0,
3676 .msr_mask = 0x000000000007FF77ULL,
3677 },
3678 /* IBM 750CXr (G3 embedded) */
3679 {
3680 .name = "750cxr",
3681 .pvr = CPU_PPC_750CXR,
3682 .pvr_mask = 0xFFFFFFFF,
3683 .insns_flags = PPC_INSNS_7x0,
3684 .flags = PPC_FLAGS_7x0,
3685 .msr_mask = 0x000000000007FF77ULL,
3686 },
3687 /* IBM 750FX (G3 embedded) */
3688 {
3689 .name = "750fx",
3690 .pvr = CPU_PPC_750FX,
3691 .pvr_mask = 0xFFFFFFFF,
3692 .insns_flags = PPC_INSNS_7x0,
3693 .flags = PPC_FLAGS_7x0,
3694 .msr_mask = 0x000000000007FF77ULL,
3695 },
3696 /* IBM 750FL (G3 embedded) */
3697 {
3698 .name = "750fl",
3699 .pvr = CPU_PPC_750FL,
3700 .pvr_mask = 0xFFFFFFFF,
3701 .insns_flags = PPC_INSNS_7x0,
3702 .flags = PPC_FLAGS_7x0,
3703 .msr_mask = 0x000000000007FF77ULL,
3704 },
3705 /* IBM 750GX (G3 embedded) */
3706 {
3707 .name = "750gx",
3708 .pvr = CPU_PPC_750GX,
3709 .pvr_mask = 0xFFFFFFFF,
3710 .insns_flags = PPC_INSNS_7x0,
3711 .flags = PPC_FLAGS_7x0,
3712 .msr_mask = 0x000000000007FF77ULL,
3713 },
3714 /* IBM 750L (G3 embedded) */
3715 {
3716 .name = "750l",
3717 .pvr = CPU_PPC_750L,
3718 .pvr_mask = 0xFFFFFFFF,
3719 .insns_flags = PPC_INSNS_7x0,
3720 .flags = PPC_FLAGS_7x0,
3721 .msr_mask = 0x000000000007FF77ULL,
3722 },
3723 /* IBM 750CL (G3 embedded) */
3724 {
3725 .name = "750cl",
3726 .pvr = CPU_PPC_750CL,
3727 .pvr_mask = 0xFFFFFFFF,
3728 .insns_flags = PPC_INSNS_7x0,
3729 .flags = PPC_FLAGS_7x0,
3730 .msr_mask = 0x000000000007FF77ULL,
3731 },
3732 #if defined (TODO)
3733 /* MPC755 (G3) */
3734 {
3735 .name = "755",
3736 .pvr = CPU_PPC_755,
3737 .pvr_mask = 0xFFFFFFFF,
3738 .insns_flags = PPC_INSNS_7x5,
3739 .flags = PPC_FLAGS_7x5,
3740 .msr_mask = 0x000000000007FF77ULL,
3741 },
3742 #endif
3743 #if defined (TODO)
3744 /* MPC755D (G3) */
3745 {
3746 .name = "755d",
3747 .pvr = CPU_PPC_755D,
3748 .pvr_mask = 0xFFFFFFFF,
3749 .insns_flags = PPC_INSNS_7x5,
3750 .flags = PPC_FLAGS_7x5,
3751 .msr_mask = 0x000000000007FF77ULL,
3752 },
3753 #endif
3754 #if defined (TODO)
3755 /* MPC755E (G3) */
3756 {
3757 .name = "755e",
3758 .pvr = CPU_PPC_755E,
3759 .pvr_mask = 0xFFFFFFFF,
3760 .insns_flags = PPC_INSNS_7x5,
3761 .flags = PPC_FLAGS_7x5,
3762 .msr_mask = 0x000000000007FF77ULL,
3763 },
3764 #endif
3765 #if defined (TODO)
3766 /* MPC755P (G3) */
3767 {
3768 .name = "755p",
3769 .pvr = CPU_PPC_74xP,
3770 .pvr_mask = 0xFFFFFFFF,
3771 .insns_flags = PPC_INSNS_7x5,
3772 .flags = PPC_FLAGS_7x5,
3773 .msr_mask = 0x000000000007FF77ULL,
3774 },
3775 #endif
3776 #if defined (TODO)
3777 /* generic G4 */
3778 {
3779 .name = "G4",
3780 .pvr = CPU_PPC_7400,
3781 .pvr_mask = 0xFFFFFFFF,
3782 .insns_flags = PPC_INSNS_74xx,
3783 .flags = PPC_FLAGS_74xx,
3784 .msr_mask = 0x000000000205FF77ULL,
3785 },
3786 #endif
3787 #if defined (TODO)
3788 /* PowerPC 7400 (G4) */
3789 {
3790 .name = "7400",
3791 .pvr = CPU_PPC_7400,
3792 .pvr_mask = 0xFFFFFFFF,
3793 .insns_flags = PPC_INSNS_74xx,
3794 .flags = PPC_FLAGS_74xx,
3795 .msr_mask = 0x000000000205FF77ULL,
3796 },
3797 {
3798 .name = "Max",
3799 .pvr = CPU_PPC_7400,
3800 .pvr_mask = 0xFFFFFFFF,
3801 .insns_flags = PPC_INSNS_74xx,
3802 .flags = PPC_FLAGS_74xx,
3803 .msr_mask = 0x000000000205FF77ULL,
3804 },
3805 #endif
3806 #if defined (TODO)
3807 /* PowerPC 7410 (G4) */
3808 {
3809 .name = "7410",
3810 .pvr = CPU_PPC_7410,
3811 .pvr_mask = 0xFFFFFFFF,
3812 .insns_flags = PPC_INSNS_74xx,
3813 .flags = PPC_FLAGS_74xx,
3814 .msr_mask = 0x000000000205FF77ULL,
3815 },
3816 {
3817 .name = "Nitro",
3818 .pvr = CPU_PPC_7410,
3819 .pvr_mask = 0xFFFFFFFF,
3820 .insns_flags = PPC_INSNS_74xx,
3821 .flags = PPC_FLAGS_74xx,
3822 .msr_mask = 0x000000000205FF77ULL,
3823 },
3824 #endif
3825 #if defined (TODO)
3826 /* PowerPC 7441 (G4) */
3827 {
3828 .name = "7441",
3829 .pvr = CPU_PPC_7441,
3830 .pvr_mask = 0xFFFFFFFF,
3831 .insns_flags = PPC_INSNS_74xx,
3832 .flags = PPC_FLAGS_74xx,
3833 .msr_mask = 0x000000000205FF77ULL,
3834 },
3835 #endif
3836 #if defined (TODO)
3837 /* PowerPC 7445 (G4) */
3838 {
3839 .name = "7445",
3840 .pvr = CPU_PPC_7445,
3841 .pvr_mask = 0xFFFFFFFF,
3842 .insns_flags = PPC_INSNS_74xx,
3843 .flags = PPC_FLAGS_74xx,
3844 .msr_mask = 0x000000000205FF77ULL,
3845 },
3846 #endif
3847 #if defined (TODO)
3848 /* PowerPC 7447 (G4) */
3849 {
3850 .name = "7447",
3851 .pvr = CPU_PPC_7447,
3852 .pvr_mask = 0xFFFFFFFF,
3853 .insns_flags = PPC_INSNS_74xx,
3854 .flags = PPC_FLAGS_74xx,
3855 .msr_mask = 0x000000000205FF77ULL,
3856 },
3857 #endif
3858 #if defined (TODO)
3859 /* PowerPC 7447A (G4) */
3860 {
3861 .name = "7447A",
3862 .pvr = CPU_PPC_7447A,
3863 .pvr_mask = 0xFFFFFFFF,
3864 .insns_flags = PPC_INSNS_74xx,
3865 .flags = PPC_FLAGS_74xx,
3866 .msr_mask = 0x000000000205FF77ULL,
3867 },
3868 #endif
3869 #if defined (TODO)
3870 /* PowerPC 7448 (G4) */
3871 {
3872 .name = "7448",
3873 .pvr = CPU_PPC_7448,
3874 .pvr_mask = 0xFFFFFFFF,
3875 .insns_flags = PPC_INSNS_74xx,
3876 .flags = PPC_FLAGS_74xx,
3877 .msr_mask = 0x000000000205FF77ULL,
3878 },
3879 #endif
3880 #if defined (TODO)
3881 /* PowerPC 7450 (G4) */
3882 {
3883 .name = "7450",
3884 .pvr = CPU_PPC_7450,
3885 .pvr_mask = 0xFFFFFFFF,
3886 .insns_flags = PPC_INSNS_74xx,
3887 .flags = PPC_FLAGS_74xx,
3888 .msr_mask = 0x000000000205FF77ULL,
3889 },
3890 {
3891 .name = "Vger",
3892 .pvr = CPU_PPC_7450,
3893 .pvr_mask = 0xFFFFFFFF,
3894 .insns_flags = PPC_INSNS_74xx,
3895 .flags = PPC_FLAGS_74xx,
3896 .msr_mask = 0x000000000205FF77ULL,
3897 },
3898 #endif
3899 #if defined (TODO)
3900 /* PowerPC 7450b (G4) */
3901 {
3902 .name = "7450b",
3903 .pvr = CPU_PPC_7450B,
3904 .pvr_mask = 0xFFFFFFFF,
3905 .insns_flags = PPC_INSNS_74xx,
3906 .flags = PPC_FLAGS_74xx,
3907 .msr_mask = 0x000000000205FF77ULL,
3908 },
3909 #endif
3910 #if defined (TODO)
3911 /* PowerPC 7451 (G4) */
3912 {
3913 .name = "7451",
3914 .pvr = CPU_PPC_7451,
3915 .pvr_mask = 0xFFFFFFFF,
3916 .insns_flags = PPC_INSNS_74xx,
3917 .flags = PPC_FLAGS_74xx,
3918 .msr_mask = 0x000000000205FF77ULL,
3919 },
3920 #endif
3921 #if defined (TODO)
3922 /* PowerPC 7451g (G4) */
3923 {
3924 .name = "7451g",
3925 .pvr = CPU_PPC_7451G,
3926 .pvr_mask = 0xFFFFFFFF,
3927 .insns_flags = PPC_INSNS_74xx,
3928 .flags = PPC_FLAGS_74xx,
3929 .msr_mask = 0x000000000205FF77ULL,
3930 },
3931 #endif
3932 #if defined (TODO)
3933 /* PowerPC 7455 (G4) */
3934 {
3935 .name = "7455",
3936 .pvr = CPU_PPC_7455,
3937 .pvr_mask = 0xFFFFFFFF,
3938 .insns_flags = PPC_INSNS_74xx,
3939 .flags = PPC_FLAGS_74xx,
3940 .msr_mask = 0x000000000205FF77ULL,
3941 },
3942 {
3943 .name = "Apollo 6",
3944 .pvr = CPU_PPC_7455,
3945 .pvr_mask = 0xFFFFFFFF,
3946 .insns_flags = PPC_INSNS_74xx,
3947 .flags = PPC_FLAGS_74xx,
3948 .msr_mask = 0x000000000205FF77ULL,
3949 },
3950 #endif
3951 #if defined (TODO)
3952 /* PowerPC 7455F (G4) */
3953 {
3954 .name = "7455f",
3955 .pvr = CPU_PPC_7455F,
3956 .pvr_mask = 0xFFFFFFFF,
3957 .insns_flags = PPC_INSNS_74xx,
3958 .flags = PPC_FLAGS_74xx,
3959 .msr_mask = 0x000000000205FF77ULL,
3960 },
3961 #endif
3962 #if defined (TODO)
3963 /* PowerPC 7455G (G4) */
3964 {
3965 .name = "7455g",
3966 .pvr = CPU_PPC_7455G,
3967 .pvr_mask = 0xFFFFFFFF,
3968 .insns_flags = PPC_INSNS_74xx,
3969 .flags = PPC_FLAGS_74xx,
3970 .msr_mask = 0x000000000205FF77ULL,
3971 },
3972 #endif
3973 #if defined (TODO)
3974 /* PowerPC 7457 (G4) */
3975 {
3976 .name = "7457",
3977 .pvr = CPU_PPC_7457,
3978 .pvr_mask = 0xFFFFFFFF,
3979 .insns_flags = PPC_INSNS_74xx,
3980 .flags = PPC_FLAGS_74xx,
3981 .msr_mask = 0x000000000205FF77ULL,
3982 },
3983 {
3984 .name = "Apollo 7",
3985 .pvr = CPU_PPC_7457,
3986 .pvr_mask = 0xFFFFFFFF,
3987 .insns_flags = PPC_INSNS_74xx,
3988 .flags = PPC_FLAGS_74xx,
3989 .msr_mask = 0x000000000205FF77ULL,
3990 },
3991 #endif
3992 #if defined (TODO)
3993 /* PowerPC 7457A (G4) */
3994 {
3995 .name = "7457A",
3996 .pvr = CPU_PPC_7457A,
3997 .pvr_mask = 0xFFFFFFFF,
3998 .insns_flags = PPC_INSNS_74xx,
3999 .flags = PPC_FLAGS_74xx,
4000 .msr_mask = 0x000000000205FF77ULL,
4001 },
4002 {
4003 .name = "Apollo 7 PM",
4004 .pvr = CPU_PPC_7457A,
4005 .pvr_mask = 0xFFFFFFFF,
4006 .insns_flags = PPC_INSNS_74xx,
4007 .flags = PPC_FLAGS_74xx,
4008 .msr_mask = 0x000000000205FF77ULL,
4009 },
4010 #endif
4011 #if defined (TODO)
4012 /* PowerPC 7457C (G4) */
4013 {
4014 .name = "7457c",
4015 .pvr = CPU_PPC_7457C,
4016 .pvr_mask = 0xFFFFFFFF,
4017 .insns_flags = PPC_INSNS_74xx,
4018 .flags = PPC_FLAGS_74xx,
4019 .msr_mask = 0x000000000205FF77ULL,
4020 },
4021 #endif
4022 /* 64 bits PowerPC */
4023 #if defined (TARGET_PPC64)
4024 #if defined (TODO)
4025 /* PowerPC 620 */
4026 {
4027 .name = "620",
4028 .pvr = CPU_PPC_620,
4029 .pvr_mask = 0xFFFFFFFF,
4030 .insns_flags = PPC_INSNS_620,
4031 .flags = PPC_FLAGS_620,
4032 .msr_mask = 0x800000000005FF73ULL,
4033 },
4034 #endif
4035 #if defined (TODO)
4036 /* PowerPC 630 (POWER3) */
4037 {
4038 .name = "630",
4039 .pvr = CPU_PPC_630,
4040 .pvr_mask = 0xFFFFFFFF,
4041 .insns_flags = PPC_INSNS_630,
4042 .flags = PPC_FLAGS_630,
4043 .msr_mask = xxx,
4044 }
4045 {
4046 .name = "POWER3",
4047 .pvr = CPU_PPC_630,
4048 .pvr_mask = 0xFFFFFFFF,
4049 .insns_flags = PPC_INSNS_630,
4050 .flags = PPC_FLAGS_630,
4051 .msr_mask = xxx,
4052 }
4053 #endif
4054 #if defined (TODO)
4055 /* PowerPC 631 (Power 3+)*/
4056 {
4057 .name = "631",
4058 .pvr = CPU_PPC_631,
4059 .pvr_mask = 0xFFFFFFFF,
4060 .insns_flags = PPC_INSNS_631,
4061 .flags = PPC_FLAGS_631,
4062 .msr_mask = xxx,
4063 },
4064 {
4065 .name = "POWER3+",
4066 .pvr = CPU_PPC_631,
4067 .pvr_mask = 0xFFFFFFFF,
4068 .insns_flags = PPC_INSNS_631,
4069 .flags = PPC_FLAGS_631,
4070 .msr_mask = xxx,
4071 },
4072 #endif
4073 #if defined (TODO)
4074 /* POWER4 */
4075 {
4076 .name = "POWER4",
4077 .pvr = CPU_PPC_POWER4,
4078 .pvr_mask = 0xFFFFFFFF,
4079 .insns_flags = PPC_INSNS_POWER4,
4080 .flags = PPC_FLAGS_POWER4,
4081 .msr_mask = xxx,
4082 },
4083 #endif
4084 #if defined (TODO)
4085 /* POWER4p */
4086 {
4087 .name = "POWER4+",
4088 .pvr = CPU_PPC_POWER4P,
4089 .pvr_mask = 0xFFFFFFFF,
4090 .insns_flags = PPC_INSNS_POWER4,
4091 .flags = PPC_FLAGS_POWER4,
4092 .msr_mask = xxx,
4093 },
4094 #endif
4095 #if defined (TODO)
4096 /* POWER5 */
4097 {
4098 .name = "POWER5",
4099 .pvr = CPU_PPC_POWER5,
4100 .pvr_mask = 0xFFFFFFFF,
4101 .insns_flags = PPC_INSNS_POWER5,
4102 .flags = PPC_FLAGS_POWER5,
4103 .msr_mask = xxx,
4104 },
4105 #endif
4106 #if defined (TODO)
4107 /* POWER5+ */
4108 {
4109 .name = "POWER5+",
4110 .pvr = CPU_PPC_POWER5P,
4111 .pvr_mask = 0xFFFFFFFF,
4112 .insns_flags = PPC_INSNS_POWER5,
4113 .flags = PPC_FLAGS_POWER5,
4114 .msr_mask = xxx,
4115 },
4116 #endif
4117 #if defined (TODO)
4118 /* POWER6 */
4119 {
4120 .name = "POWER6",
4121 .pvr = CPU_PPC_POWER6,
4122 .pvr_mask = 0xFFFFFFFF,
4123 .insns_flags = PPC_INSNS_POWER6,
4124 .flags = PPC_FLAGS_POWER6,
4125 .msr_mask = xxx,
4126 },
4127 #endif
4128 #if defined (TODO)
4129 /* PowerPC 970 */
4130 {
4131 .name = "970",
4132 .pvr = CPU_PPC_970,
4133 .pvr_mask = 0xFFFFFFFF,
4134 .insns_flags = PPC_INSNS_970,
4135 .flags = PPC_FLAGS_970,
4136 .msr_mask = 0x900000000204FF36ULL,
4137 },
4138 #endif
4139 #if defined (TODO)
4140 /* PowerPC 970FX (G5) */
4141 {
4142 .name = "970fx",
4143 .pvr = CPU_PPC_970FX,
4144 .pvr_mask = 0xFFFFFFFF,
4145 .insns_flags = PPC_INSNS_970FX,
4146 .flags = PPC_FLAGS_970FX,
4147 .msr_mask = 0x800000000204FF36ULL,
4148 },
4149 #endif
4150 #if defined (TODO)
4151 /* PowerPC 970MP */
4152 {
4153 .name = "970MP",
4154 .pvr = CPU_PPC_970MP,
4155 .pvr_mask = 0xFFFFFFFF,
4156 .insns_flags = PPC_INSNS_970,
4157 .flags = PPC_FLAGS_970,
4158 .msr_mask = 0x900000000204FF36ULL,
4159 },
4160 #endif
4161 #if defined (TODO)
4162 /* PowerPC Cell */
4163 {
4164 .name = "Cell",
4165 .pvr = CPU_PPC_CELL,
4166 .pvr_mask = 0xFFFFFFFF,
4167 .insns_flags = PPC_INSNS_970,
4168 .flags = PPC_FLAGS_970,
4169 .msr_mask = 0x900000000204FF36ULL,
4170 },
4171 #endif
4172 #if defined (TODO)
4173 /* RS64 (Apache/A35) */
4174 /* This one seems to support the whole POWER2 instruction set
4175 * and the PowerPC 64 one.
4176 */
4177 {
4178 .name = "RS64",
4179 .pvr = CPU_PPC_RS64,
4180 .pvr_mask = 0xFFFFFFFF,
4181 .insns_flags = PPC_INSNS_RS64,
4182 .flags = PPC_FLAGS_RS64,
4183 .msr_mask = xxx,
4184 },
4185 {
4186 .name = "Apache",
4187 .pvr = CPU_PPC_RS64,
4188 .pvr_mask = 0xFFFFFFFF,
4189 .insns_flags = PPC_INSNS_RS64,
4190 .flags = PPC_FLAGS_RS64,
4191 .msr_mask = xxx,
4192 },
4193 {
4194 .name = "A35",
4195 .pvr = CPU_PPC_RS64,
4196 .pvr_mask = 0xFFFFFFFF,
4197 .insns_flags = PPC_INSNS_RS64,
4198 .flags = PPC_FLAGS_RS64,
4199 .msr_mask = xxx,
4200 },
4201 #endif
4202 #if defined (TODO)
4203 /* RS64-II (NorthStar/A50) */
4204 {
4205 .name = "RS64-II",
4206 .pvr = CPU_PPC_RS64II,
4207 .pvr_mask = 0xFFFFFFFF,
4208 .insns_flags = PPC_INSNS_RS64,
4209 .flags = PPC_FLAGS_RS64,
4210 .msr_mask = xxx,
4211 },
4212 {
4213 .name = "NortStar",
4214 .pvr = CPU_PPC_RS64II,
4215 .pvr_mask = 0xFFFFFFFF,
4216 .insns_flags = PPC_INSNS_RS64,
4217 .flags = PPC_FLAGS_RS64,
4218 .msr_mask = xxx,
4219 },
4220 {
4221 .name = "A50",
4222 .pvr = CPU_PPC_RS64II,
4223 .pvr_mask = 0xFFFFFFFF,
4224 .insns_flags = PPC_INSNS_RS64,
4225 .flags = PPC_FLAGS_RS64,
4226 .msr_mask = xxx,
4227 },
4228 #endif
4229 #if defined (TODO)
4230 /* RS64-III (Pulsar) */
4231 {
4232 .name = "RS64-III",
4233 .pvr = CPU_PPC_RS64III,
4234 .pvr_mask = 0xFFFFFFFF,
4235 .insns_flags = PPC_INSNS_RS64,
4236 .flags = PPC_FLAGS_RS64,
4237 .msr_mask = xxx,
4238 },
4239 {
4240 .name = "Pulsar",
4241 .pvr = CPU_PPC_RS64III,
4242 .pvr_mask = 0xFFFFFFFF,
4243 .insns_flags = PPC_INSNS_RS64,
4244 .flags = PPC_FLAGS_RS64,
4245 .msr_mask = xxx,
4246 },
4247 #endif
4248 #if defined (TODO)
4249 /* RS64-IV (IceStar/IStar/SStar) */
4250 {
4251 .name = "RS64-IV",
4252 .pvr = CPU_PPC_RS64IV,
4253 .pvr_mask = 0xFFFFFFFF,
4254 .insns_flags = PPC_INSNS_RS64,
4255 .flags = PPC_FLAGS_RS64,
4256 .msr_mask = xxx,
4257 },
4258 {
4259 .name = "IceStar",
4260 .pvr = CPU_PPC_RS64IV,
4261 .pvr_mask = 0xFFFFFFFF,
4262 .insns_flags = PPC_INSNS_RS64,
4263 .flags = PPC_FLAGS_RS64,
4264 .msr_mask = xxx,
4265 },
4266 {
4267 .name = "IStar",
4268 .pvr = CPU_PPC_RS64IV,
4269 .pvr_mask = 0xFFFFFFFF,
4270 .insns_flags = PPC_INSNS_RS64,
4271 .flags = PPC_FLAGS_RS64,
4272 .msr_mask = xxx,
4273 },
4274 {
4275 .name = "SStar",
4276 .pvr = CPU_PPC_RS64IV,
4277 .pvr_mask = 0xFFFFFFFF,
4278 .insns_flags = PPC_INSNS_RS64,
4279 .flags = PPC_FLAGS_RS64,
4280 .msr_mask = xxx,
4281 },
4282 #endif
4283 /* POWER */
4284 #if defined (TODO)
4285 /* Original POWER */
4286 {
4287 .name = "POWER",
4288 .pvr = CPU_POWER,
4289 .pvr_mask = 0xFFFFFFFF,
4290 .insns_flags = PPC_INSNS_POWER,
4291 .flags = PPC_FLAGS_POWER,
4292 .msr_mask = xxx,
4293 },
4294 #endif
4295 #endif /* defined (TARGET_PPC64) */
4296 #if defined (TODO)
4297 /* POWER2 */
4298 {
4299 .name = "POWER2",
4300 .pvr = CPU_POWER2,
4301 .pvr_mask = 0xFFFFFFFF,
4302 .insns_flags = PPC_INSNS_POWER,
4303 .flags = PPC_FLAGS_POWER,
4304 .msr_mask = xxx,
4305 },
4306 #endif
4307 /* Generic PowerPCs */
4308 #if defined (TODO)
4309 {
4310 .name = "ppc64",
4311 .pvr = CPU_PPC_970FX,
4312 .pvr_mask = 0xFFFFFFFF,
4313 .insns_flags = PPC_INSNS_PPC64,
4314 .flags = PPC_FLAGS_PPC64,
4315 .msr_mask = 0xA00000000204FF36ULL,
4316 },
4317 #endif
4318 {
4319 .name = "ppc32",
4320 .pvr = CPU_PPC_604,
4321 .pvr_mask = 0xFFFFFFFF,
4322 .insns_flags = PPC_INSNS_PPC32,
4323 .flags = PPC_FLAGS_PPC32,
4324 .msr_mask = 0x000000000005FF77ULL,
4325 },
4326 /* Fallback */
4327 {
4328 .name = "ppc",
4329 .pvr = CPU_PPC_604,
4330 .pvr_mask = 0xFFFFFFFF,
4331 .insns_flags = PPC_INSNS_PPC32,
4332 .flags = PPC_FLAGS_PPC32,
4333 .msr_mask = 0x000000000005FF77ULL,
4334 },
4335 };
4336
4337 int ppc_find_by_name (const unsigned char *name, ppc_def_t **def)
4338 {
4339 int i, ret;
4340
4341 ret = -1;
4342 *def = NULL;
4343 for (i = 0; strcmp(ppc_defs[i].name, "ppc") != 0; i++) {
4344 if (strcasecmp(name, ppc_defs[i].name) == 0) {
4345 *def = &ppc_defs[i];
4346 ret = 0;
4347 break;
4348 }
4349 }
4350
4351 return ret;
4352 }
4353
4354 int ppc_find_by_pvr (uint32_t pvr, ppc_def_t **def)
4355 {
4356 int i, ret;
4357
4358 ret = -1;
4359 *def = NULL;
4360 for (i = 0; ppc_defs[i].name != NULL; i++) {
4361 if ((pvr & ppc_defs[i].pvr_mask) ==
4362 (ppc_defs[i].pvr & ppc_defs[i].pvr_mask)) {
4363 *def = &ppc_defs[i];
4364 ret = 0;
4365 break;
4366 }
4367 }
4368
4369 return ret;
4370 }
4371
4372 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
4373 {
4374 int i;
4375
4376 for (i = 0; ; i++) {
4377 (*cpu_fprintf)(f, "PowerPC %16s PVR %08x mask %08x\n",
4378 ppc_defs[i].name,
4379 ppc_defs[i].pvr, ppc_defs[i].pvr_mask);
4380 if (strcmp(ppc_defs[i].name, "ppc") == 0)
4381 break;
4382 }
4383 }
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