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PPC: Extract SPR dump generation into its own function
[mirror_qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
26 #include "dis-asm.h"
27 #include "gdbstub.h"
28 #include <kvm.h>
29 #include "kvm_ppc.h"
30
31 //#define PPC_DUMP_CPU
32 //#define PPC_DEBUG_SPR
33 //#define PPC_DUMP_SPR_ACCESSES
34 #if defined(CONFIG_USER_ONLY)
35 #define TODO_USER_ONLY 1
36 #endif
37
38 /* For user-mode emulation, we don't emulate any IRQ controller */
39 #if defined(CONFIG_USER_ONLY)
40 #define PPC_IRQ_INIT_FN(name) \
41 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
42 { \
43 }
44 #else
45 #define PPC_IRQ_INIT_FN(name) \
46 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
47 #endif
48
49 PPC_IRQ_INIT_FN(40x);
50 PPC_IRQ_INIT_FN(6xx);
51 PPC_IRQ_INIT_FN(970);
52 PPC_IRQ_INIT_FN(POWER7);
53 PPC_IRQ_INIT_FN(e500);
54
55 /* Generic callbacks:
56 * do nothing but store/retrieve spr value
57 */
58 static void spr_load_dump_spr(int sprn)
59 {
60 #ifdef PPC_DUMP_SPR_ACCESSES
61 TCGv_i32 t0 = tcg_const_i32(sprn);
62 gen_helper_load_dump_spr(t0);
63 tcg_temp_free_i32(t0);
64 #endif
65 }
66
67 static void spr_read_generic (void *opaque, int gprn, int sprn)
68 {
69 gen_load_spr(cpu_gpr[gprn], sprn);
70 spr_load_dump_spr(sprn);
71 }
72
73 static void spr_store_dump_spr(int sprn)
74 {
75 #ifdef PPC_DUMP_SPR_ACCESSES
76 TCGv_i32 t0 = tcg_const_i32(sprn);
77 gen_helper_store_dump_spr(t0);
78 tcg_temp_free_i32(t0);
79 #endif
80 }
81
82 static void spr_write_generic (void *opaque, int sprn, int gprn)
83 {
84 gen_store_spr(sprn, cpu_gpr[gprn]);
85 spr_store_dump_spr(sprn);
86 }
87
88 #if !defined(CONFIG_USER_ONLY)
89 static void spr_write_clear (void *opaque, int sprn, int gprn)
90 {
91 TCGv t0 = tcg_temp_new();
92 TCGv t1 = tcg_temp_new();
93 gen_load_spr(t0, sprn);
94 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
95 tcg_gen_and_tl(t0, t0, t1);
96 gen_store_spr(sprn, t0);
97 tcg_temp_free(t0);
98 tcg_temp_free(t1);
99 }
100 #endif
101
102 /* SPR common to all PowerPC */
103 /* XER */
104 static void spr_read_xer (void *opaque, int gprn, int sprn)
105 {
106 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
107 }
108
109 static void spr_write_xer (void *opaque, int sprn, int gprn)
110 {
111 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
112 }
113
114 /* LR */
115 static void spr_read_lr (void *opaque, int gprn, int sprn)
116 {
117 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
118 }
119
120 static void spr_write_lr (void *opaque, int sprn, int gprn)
121 {
122 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
123 }
124
125 /* CFAR */
126 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
127 static void spr_read_cfar (void *opaque, int gprn, int sprn)
128 {
129 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
130 }
131
132 static void spr_write_cfar (void *opaque, int sprn, int gprn)
133 {
134 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
135 }
136 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
137
138 /* CTR */
139 static void spr_read_ctr (void *opaque, int gprn, int sprn)
140 {
141 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
142 }
143
144 static void spr_write_ctr (void *opaque, int sprn, int gprn)
145 {
146 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
147 }
148
149 /* User read access to SPR */
150 /* USPRx */
151 /* UMMCRx */
152 /* UPMCx */
153 /* USIA */
154 /* UDECR */
155 static void spr_read_ureg (void *opaque, int gprn, int sprn)
156 {
157 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
158 }
159
160 /* SPR common to all non-embedded PowerPC */
161 /* DECR */
162 #if !defined(CONFIG_USER_ONLY)
163 static void spr_read_decr (void *opaque, int gprn, int sprn)
164 {
165 if (use_icount) {
166 gen_io_start();
167 }
168 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
169 if (use_icount) {
170 gen_io_end();
171 gen_stop_exception(opaque);
172 }
173 }
174
175 static void spr_write_decr (void *opaque, int sprn, int gprn)
176 {
177 if (use_icount) {
178 gen_io_start();
179 }
180 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
181 if (use_icount) {
182 gen_io_end();
183 gen_stop_exception(opaque);
184 }
185 }
186 #endif
187
188 /* SPR common to all non-embedded PowerPC, except 601 */
189 /* Time base */
190 static void spr_read_tbl (void *opaque, int gprn, int sprn)
191 {
192 if (use_icount) {
193 gen_io_start();
194 }
195 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
196 if (use_icount) {
197 gen_io_end();
198 gen_stop_exception(opaque);
199 }
200 }
201
202 static void spr_read_tbu (void *opaque, int gprn, int sprn)
203 {
204 if (use_icount) {
205 gen_io_start();
206 }
207 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
208 if (use_icount) {
209 gen_io_end();
210 gen_stop_exception(opaque);
211 }
212 }
213
214 __attribute__ (( unused ))
215 static void spr_read_atbl (void *opaque, int gprn, int sprn)
216 {
217 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
218 }
219
220 __attribute__ (( unused ))
221 static void spr_read_atbu (void *opaque, int gprn, int sprn)
222 {
223 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
224 }
225
226 #if !defined(CONFIG_USER_ONLY)
227 static void spr_write_tbl (void *opaque, int sprn, int gprn)
228 {
229 if (use_icount) {
230 gen_io_start();
231 }
232 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
233 if (use_icount) {
234 gen_io_end();
235 gen_stop_exception(opaque);
236 }
237 }
238
239 static void spr_write_tbu (void *opaque, int sprn, int gprn)
240 {
241 if (use_icount) {
242 gen_io_start();
243 }
244 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
245 if (use_icount) {
246 gen_io_end();
247 gen_stop_exception(opaque);
248 }
249 }
250
251 __attribute__ (( unused ))
252 static void spr_write_atbl (void *opaque, int sprn, int gprn)
253 {
254 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
255 }
256
257 __attribute__ (( unused ))
258 static void spr_write_atbu (void *opaque, int sprn, int gprn)
259 {
260 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
261 }
262
263 #if defined(TARGET_PPC64)
264 __attribute__ (( unused ))
265 static void spr_read_purr (void *opaque, int gprn, int sprn)
266 {
267 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
268 }
269 #endif
270 #endif
271
272 #if !defined(CONFIG_USER_ONLY)
273 /* IBAT0U...IBAT0U */
274 /* IBAT0L...IBAT7L */
275 static void spr_read_ibat (void *opaque, int gprn, int sprn)
276 {
277 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
278 }
279
280 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
281 {
282 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
283 }
284
285 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
286 {
287 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
288 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
289 tcg_temp_free_i32(t0);
290 }
291
292 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
293 {
294 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
295 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
296 tcg_temp_free_i32(t0);
297 }
298
299 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
300 {
301 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
302 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
303 tcg_temp_free_i32(t0);
304 }
305
306 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
307 {
308 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
309 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
310 tcg_temp_free_i32(t0);
311 }
312
313 /* DBAT0U...DBAT7U */
314 /* DBAT0L...DBAT7L */
315 static void spr_read_dbat (void *opaque, int gprn, int sprn)
316 {
317 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
318 }
319
320 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
321 {
322 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
323 }
324
325 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
326 {
327 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
328 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
329 tcg_temp_free_i32(t0);
330 }
331
332 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
333 {
334 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
335 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
336 tcg_temp_free_i32(t0);
337 }
338
339 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
340 {
341 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
342 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
343 tcg_temp_free_i32(t0);
344 }
345
346 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
347 {
348 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
349 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
350 tcg_temp_free_i32(t0);
351 }
352
353 /* SDR1 */
354 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
355 {
356 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
357 }
358
359 /* 64 bits PowerPC specific SPRs */
360 /* ASR */
361 #if defined(TARGET_PPC64)
362 static void spr_read_hior (void *opaque, int gprn, int sprn)
363 {
364 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
365 }
366
367 static void spr_write_hior (void *opaque, int sprn, int gprn)
368 {
369 TCGv t0 = tcg_temp_new();
370 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
371 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
372 tcg_temp_free(t0);
373 }
374
375 static void spr_read_asr (void *opaque, int gprn, int sprn)
376 {
377 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, asr));
378 }
379
380 static void spr_write_asr (void *opaque, int sprn, int gprn)
381 {
382 gen_helper_store_asr(cpu_env, cpu_gpr[gprn]);
383 }
384 #endif
385 #endif
386
387 /* PowerPC 601 specific registers */
388 /* RTC */
389 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
390 {
391 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
392 }
393
394 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
395 {
396 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
397 }
398
399 #if !defined(CONFIG_USER_ONLY)
400 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
401 {
402 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
403 }
404
405 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
406 {
407 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
408 }
409
410 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
411 {
412 DisasContext *ctx = opaque;
413
414 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
415 /* Must stop the translation as endianness may have changed */
416 gen_stop_exception(ctx);
417 }
418 #endif
419
420 /* Unified bats */
421 #if !defined(CONFIG_USER_ONLY)
422 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
423 {
424 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
425 }
426
427 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
428 {
429 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
430 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
431 tcg_temp_free_i32(t0);
432 }
433
434 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
435 {
436 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
437 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
438 tcg_temp_free_i32(t0);
439 }
440 #endif
441
442 /* PowerPC 40x specific registers */
443 #if !defined(CONFIG_USER_ONLY)
444 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
445 {
446 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
447 }
448
449 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
450 {
451 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
452 }
453
454 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
455 {
456 DisasContext *ctx = opaque;
457
458 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
459 /* We must stop translation as we may have rebooted */
460 gen_stop_exception(ctx);
461 }
462
463 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
464 {
465 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
466 }
467
468 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
469 {
470 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
471 }
472
473 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
474 {
475 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
476 }
477 #endif
478
479 /* PowerPC 403 specific registers */
480 /* PBL1 / PBU1 / PBL2 / PBU2 */
481 #if !defined(CONFIG_USER_ONLY)
482 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
483 {
484 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
485 }
486
487 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
488 {
489 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
490 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
491 tcg_temp_free_i32(t0);
492 }
493
494 static void spr_write_pir (void *opaque, int sprn, int gprn)
495 {
496 TCGv t0 = tcg_temp_new();
497 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
498 gen_store_spr(SPR_PIR, t0);
499 tcg_temp_free(t0);
500 }
501 #endif
502
503 /* SPE specific registers */
504 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
505 {
506 TCGv_i32 t0 = tcg_temp_new_i32();
507 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
508 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
509 tcg_temp_free_i32(t0);
510 }
511
512 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
513 {
514 TCGv_i32 t0 = tcg_temp_new_i32();
515 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
516 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
517 tcg_temp_free_i32(t0);
518 }
519
520 #if !defined(CONFIG_USER_ONLY)
521 /* Callback used to write the exception vector base */
522 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
523 {
524 TCGv t0 = tcg_temp_new();
525 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
526 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
527 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
528 gen_store_spr(sprn, t0);
529 tcg_temp_free(t0);
530 }
531
532 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
533 {
534 DisasContext *ctx = opaque;
535 int sprn_offs;
536
537 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
538 sprn_offs = sprn - SPR_BOOKE_IVOR0;
539 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
540 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
541 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
542 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
543 } else {
544 printf("Trying to write an unknown exception vector %d %03x\n",
545 sprn, sprn);
546 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
547 return;
548 }
549
550 TCGv t0 = tcg_temp_new();
551 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
552 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
553 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
554 gen_store_spr(sprn, t0);
555 tcg_temp_free(t0);
556 }
557 #endif
558
559 static inline void vscr_init (CPUPPCState *env, uint32_t val)
560 {
561 env->vscr = val;
562 /* Altivec always uses round-to-nearest */
563 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
564 set_flush_to_zero(vscr_nj, &env->vec_status);
565 }
566
567 #if defined(CONFIG_USER_ONLY)
568 #define spr_register(env, num, name, uea_read, uea_write, \
569 oea_read, oea_write, initial_value) \
570 do { \
571 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
572 } while (0)
573 static inline void _spr_register (CPUPPCState *env, int num,
574 const char *name,
575 void (*uea_read)(void *opaque, int gprn, int sprn),
576 void (*uea_write)(void *opaque, int sprn, int gprn),
577 target_ulong initial_value)
578 #else
579 static inline void spr_register (CPUPPCState *env, int num,
580 const char *name,
581 void (*uea_read)(void *opaque, int gprn, int sprn),
582 void (*uea_write)(void *opaque, int sprn, int gprn),
583 void (*oea_read)(void *opaque, int gprn, int sprn),
584 void (*oea_write)(void *opaque, int sprn, int gprn),
585 target_ulong initial_value)
586 #endif
587 {
588 ppc_spr_t *spr;
589
590 spr = &env->spr_cb[num];
591 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
592 #if !defined(CONFIG_USER_ONLY)
593 spr->oea_read != NULL || spr->oea_write != NULL ||
594 #endif
595 spr->uea_read != NULL || spr->uea_write != NULL) {
596 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
597 exit(1);
598 }
599 #if defined(PPC_DEBUG_SPR)
600 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
601 name, initial_value);
602 #endif
603 spr->name = name;
604 spr->uea_read = uea_read;
605 spr->uea_write = uea_write;
606 #if !defined(CONFIG_USER_ONLY)
607 spr->oea_read = oea_read;
608 spr->oea_write = oea_write;
609 #endif
610 env->spr[num] = initial_value;
611 }
612
613 /* Generic PowerPC SPRs */
614 static void gen_spr_generic (CPUPPCState *env)
615 {
616 /* Integer processing */
617 spr_register(env, SPR_XER, "XER",
618 &spr_read_xer, &spr_write_xer,
619 &spr_read_xer, &spr_write_xer,
620 0x00000000);
621 /* Branch contol */
622 spr_register(env, SPR_LR, "LR",
623 &spr_read_lr, &spr_write_lr,
624 &spr_read_lr, &spr_write_lr,
625 0x00000000);
626 spr_register(env, SPR_CTR, "CTR",
627 &spr_read_ctr, &spr_write_ctr,
628 &spr_read_ctr, &spr_write_ctr,
629 0x00000000);
630 /* Interrupt processing */
631 spr_register(env, SPR_SRR0, "SRR0",
632 SPR_NOACCESS, SPR_NOACCESS,
633 &spr_read_generic, &spr_write_generic,
634 0x00000000);
635 spr_register(env, SPR_SRR1, "SRR1",
636 SPR_NOACCESS, SPR_NOACCESS,
637 &spr_read_generic, &spr_write_generic,
638 0x00000000);
639 /* Processor control */
640 spr_register(env, SPR_SPRG0, "SPRG0",
641 SPR_NOACCESS, SPR_NOACCESS,
642 &spr_read_generic, &spr_write_generic,
643 0x00000000);
644 spr_register(env, SPR_SPRG1, "SPRG1",
645 SPR_NOACCESS, SPR_NOACCESS,
646 &spr_read_generic, &spr_write_generic,
647 0x00000000);
648 spr_register(env, SPR_SPRG2, "SPRG2",
649 SPR_NOACCESS, SPR_NOACCESS,
650 &spr_read_generic, &spr_write_generic,
651 0x00000000);
652 spr_register(env, SPR_SPRG3, "SPRG3",
653 SPR_NOACCESS, SPR_NOACCESS,
654 &spr_read_generic, &spr_write_generic,
655 0x00000000);
656 }
657
658 /* SPR common to all non-embedded PowerPC, including 601 */
659 static void gen_spr_ne_601 (CPUPPCState *env)
660 {
661 /* Exception processing */
662 spr_register(env, SPR_DSISR, "DSISR",
663 SPR_NOACCESS, SPR_NOACCESS,
664 &spr_read_generic, &spr_write_generic,
665 0x00000000);
666 spr_register(env, SPR_DAR, "DAR",
667 SPR_NOACCESS, SPR_NOACCESS,
668 &spr_read_generic, &spr_write_generic,
669 0x00000000);
670 /* Timer */
671 spr_register(env, SPR_DECR, "DECR",
672 SPR_NOACCESS, SPR_NOACCESS,
673 &spr_read_decr, &spr_write_decr,
674 0x00000000);
675 /* Memory management */
676 spr_register(env, SPR_SDR1, "SDR1",
677 SPR_NOACCESS, SPR_NOACCESS,
678 &spr_read_generic, &spr_write_sdr1,
679 0x00000000);
680 }
681
682 /* BATs 0-3 */
683 static void gen_low_BATs (CPUPPCState *env)
684 {
685 #if !defined(CONFIG_USER_ONLY)
686 spr_register(env, SPR_IBAT0U, "IBAT0U",
687 SPR_NOACCESS, SPR_NOACCESS,
688 &spr_read_ibat, &spr_write_ibatu,
689 0x00000000);
690 spr_register(env, SPR_IBAT0L, "IBAT0L",
691 SPR_NOACCESS, SPR_NOACCESS,
692 &spr_read_ibat, &spr_write_ibatl,
693 0x00000000);
694 spr_register(env, SPR_IBAT1U, "IBAT1U",
695 SPR_NOACCESS, SPR_NOACCESS,
696 &spr_read_ibat, &spr_write_ibatu,
697 0x00000000);
698 spr_register(env, SPR_IBAT1L, "IBAT1L",
699 SPR_NOACCESS, SPR_NOACCESS,
700 &spr_read_ibat, &spr_write_ibatl,
701 0x00000000);
702 spr_register(env, SPR_IBAT2U, "IBAT2U",
703 SPR_NOACCESS, SPR_NOACCESS,
704 &spr_read_ibat, &spr_write_ibatu,
705 0x00000000);
706 spr_register(env, SPR_IBAT2L, "IBAT2L",
707 SPR_NOACCESS, SPR_NOACCESS,
708 &spr_read_ibat, &spr_write_ibatl,
709 0x00000000);
710 spr_register(env, SPR_IBAT3U, "IBAT3U",
711 SPR_NOACCESS, SPR_NOACCESS,
712 &spr_read_ibat, &spr_write_ibatu,
713 0x00000000);
714 spr_register(env, SPR_IBAT3L, "IBAT3L",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_ibat, &spr_write_ibatl,
717 0x00000000);
718 spr_register(env, SPR_DBAT0U, "DBAT0U",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_dbat, &spr_write_dbatu,
721 0x00000000);
722 spr_register(env, SPR_DBAT0L, "DBAT0L",
723 SPR_NOACCESS, SPR_NOACCESS,
724 &spr_read_dbat, &spr_write_dbatl,
725 0x00000000);
726 spr_register(env, SPR_DBAT1U, "DBAT1U",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_dbat, &spr_write_dbatu,
729 0x00000000);
730 spr_register(env, SPR_DBAT1L, "DBAT1L",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_dbat, &spr_write_dbatl,
733 0x00000000);
734 spr_register(env, SPR_DBAT2U, "DBAT2U",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_dbat, &spr_write_dbatu,
737 0x00000000);
738 spr_register(env, SPR_DBAT2L, "DBAT2L",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_dbat, &spr_write_dbatl,
741 0x00000000);
742 spr_register(env, SPR_DBAT3U, "DBAT3U",
743 SPR_NOACCESS, SPR_NOACCESS,
744 &spr_read_dbat, &spr_write_dbatu,
745 0x00000000);
746 spr_register(env, SPR_DBAT3L, "DBAT3L",
747 SPR_NOACCESS, SPR_NOACCESS,
748 &spr_read_dbat, &spr_write_dbatl,
749 0x00000000);
750 env->nb_BATs += 4;
751 #endif
752 }
753
754 /* BATs 4-7 */
755 static void gen_high_BATs (CPUPPCState *env)
756 {
757 #if !defined(CONFIG_USER_ONLY)
758 spr_register(env, SPR_IBAT4U, "IBAT4U",
759 SPR_NOACCESS, SPR_NOACCESS,
760 &spr_read_ibat_h, &spr_write_ibatu_h,
761 0x00000000);
762 spr_register(env, SPR_IBAT4L, "IBAT4L",
763 SPR_NOACCESS, SPR_NOACCESS,
764 &spr_read_ibat_h, &spr_write_ibatl_h,
765 0x00000000);
766 spr_register(env, SPR_IBAT5U, "IBAT5U",
767 SPR_NOACCESS, SPR_NOACCESS,
768 &spr_read_ibat_h, &spr_write_ibatu_h,
769 0x00000000);
770 spr_register(env, SPR_IBAT5L, "IBAT5L",
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_ibat_h, &spr_write_ibatl_h,
773 0x00000000);
774 spr_register(env, SPR_IBAT6U, "IBAT6U",
775 SPR_NOACCESS, SPR_NOACCESS,
776 &spr_read_ibat_h, &spr_write_ibatu_h,
777 0x00000000);
778 spr_register(env, SPR_IBAT6L, "IBAT6L",
779 SPR_NOACCESS, SPR_NOACCESS,
780 &spr_read_ibat_h, &spr_write_ibatl_h,
781 0x00000000);
782 spr_register(env, SPR_IBAT7U, "IBAT7U",
783 SPR_NOACCESS, SPR_NOACCESS,
784 &spr_read_ibat_h, &spr_write_ibatu_h,
785 0x00000000);
786 spr_register(env, SPR_IBAT7L, "IBAT7L",
787 SPR_NOACCESS, SPR_NOACCESS,
788 &spr_read_ibat_h, &spr_write_ibatl_h,
789 0x00000000);
790 spr_register(env, SPR_DBAT4U, "DBAT4U",
791 SPR_NOACCESS, SPR_NOACCESS,
792 &spr_read_dbat_h, &spr_write_dbatu_h,
793 0x00000000);
794 spr_register(env, SPR_DBAT4L, "DBAT4L",
795 SPR_NOACCESS, SPR_NOACCESS,
796 &spr_read_dbat_h, &spr_write_dbatl_h,
797 0x00000000);
798 spr_register(env, SPR_DBAT5U, "DBAT5U",
799 SPR_NOACCESS, SPR_NOACCESS,
800 &spr_read_dbat_h, &spr_write_dbatu_h,
801 0x00000000);
802 spr_register(env, SPR_DBAT5L, "DBAT5L",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_dbat_h, &spr_write_dbatl_h,
805 0x00000000);
806 spr_register(env, SPR_DBAT6U, "DBAT6U",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_dbat_h, &spr_write_dbatu_h,
809 0x00000000);
810 spr_register(env, SPR_DBAT6L, "DBAT6L",
811 SPR_NOACCESS, SPR_NOACCESS,
812 &spr_read_dbat_h, &spr_write_dbatl_h,
813 0x00000000);
814 spr_register(env, SPR_DBAT7U, "DBAT7U",
815 SPR_NOACCESS, SPR_NOACCESS,
816 &spr_read_dbat_h, &spr_write_dbatu_h,
817 0x00000000);
818 spr_register(env, SPR_DBAT7L, "DBAT7L",
819 SPR_NOACCESS, SPR_NOACCESS,
820 &spr_read_dbat_h, &spr_write_dbatl_h,
821 0x00000000);
822 env->nb_BATs += 4;
823 #endif
824 }
825
826 /* Generic PowerPC time base */
827 static void gen_tbl (CPUPPCState *env)
828 {
829 spr_register(env, SPR_VTBL, "TBL",
830 &spr_read_tbl, SPR_NOACCESS,
831 &spr_read_tbl, SPR_NOACCESS,
832 0x00000000);
833 spr_register(env, SPR_TBL, "TBL",
834 &spr_read_tbl, SPR_NOACCESS,
835 &spr_read_tbl, &spr_write_tbl,
836 0x00000000);
837 spr_register(env, SPR_VTBU, "TBU",
838 &spr_read_tbu, SPR_NOACCESS,
839 &spr_read_tbu, SPR_NOACCESS,
840 0x00000000);
841 spr_register(env, SPR_TBU, "TBU",
842 &spr_read_tbu, SPR_NOACCESS,
843 &spr_read_tbu, &spr_write_tbu,
844 0x00000000);
845 }
846
847 /* Softare table search registers */
848 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
849 {
850 #if !defined(CONFIG_USER_ONLY)
851 env->nb_tlb = nb_tlbs;
852 env->nb_ways = nb_ways;
853 env->id_tlbs = 1;
854 env->tlb_type = TLB_6XX;
855 spr_register(env, SPR_DMISS, "DMISS",
856 SPR_NOACCESS, SPR_NOACCESS,
857 &spr_read_generic, SPR_NOACCESS,
858 0x00000000);
859 spr_register(env, SPR_DCMP, "DCMP",
860 SPR_NOACCESS, SPR_NOACCESS,
861 &spr_read_generic, SPR_NOACCESS,
862 0x00000000);
863 spr_register(env, SPR_HASH1, "HASH1",
864 SPR_NOACCESS, SPR_NOACCESS,
865 &spr_read_generic, SPR_NOACCESS,
866 0x00000000);
867 spr_register(env, SPR_HASH2, "HASH2",
868 SPR_NOACCESS, SPR_NOACCESS,
869 &spr_read_generic, SPR_NOACCESS,
870 0x00000000);
871 spr_register(env, SPR_IMISS, "IMISS",
872 SPR_NOACCESS, SPR_NOACCESS,
873 &spr_read_generic, SPR_NOACCESS,
874 0x00000000);
875 spr_register(env, SPR_ICMP, "ICMP",
876 SPR_NOACCESS, SPR_NOACCESS,
877 &spr_read_generic, SPR_NOACCESS,
878 0x00000000);
879 spr_register(env, SPR_RPA, "RPA",
880 SPR_NOACCESS, SPR_NOACCESS,
881 &spr_read_generic, &spr_write_generic,
882 0x00000000);
883 #endif
884 }
885
886 /* SPR common to MPC755 and G2 */
887 static void gen_spr_G2_755 (CPUPPCState *env)
888 {
889 /* SGPRs */
890 spr_register(env, SPR_SPRG4, "SPRG4",
891 SPR_NOACCESS, SPR_NOACCESS,
892 &spr_read_generic, &spr_write_generic,
893 0x00000000);
894 spr_register(env, SPR_SPRG5, "SPRG5",
895 SPR_NOACCESS, SPR_NOACCESS,
896 &spr_read_generic, &spr_write_generic,
897 0x00000000);
898 spr_register(env, SPR_SPRG6, "SPRG6",
899 SPR_NOACCESS, SPR_NOACCESS,
900 &spr_read_generic, &spr_write_generic,
901 0x00000000);
902 spr_register(env, SPR_SPRG7, "SPRG7",
903 SPR_NOACCESS, SPR_NOACCESS,
904 &spr_read_generic, &spr_write_generic,
905 0x00000000);
906 }
907
908 /* SPR common to all 7xx PowerPC implementations */
909 static void gen_spr_7xx (CPUPPCState *env)
910 {
911 /* Breakpoints */
912 /* XXX : not implemented */
913 spr_register(env, SPR_DABR, "DABR",
914 SPR_NOACCESS, SPR_NOACCESS,
915 &spr_read_generic, &spr_write_generic,
916 0x00000000);
917 /* XXX : not implemented */
918 spr_register(env, SPR_IABR, "IABR",
919 SPR_NOACCESS, SPR_NOACCESS,
920 &spr_read_generic, &spr_write_generic,
921 0x00000000);
922 /* Cache management */
923 /* XXX : not implemented */
924 spr_register(env, SPR_ICTC, "ICTC",
925 SPR_NOACCESS, SPR_NOACCESS,
926 &spr_read_generic, &spr_write_generic,
927 0x00000000);
928 /* Performance monitors */
929 /* XXX : not implemented */
930 spr_register(env, SPR_MMCR0, "MMCR0",
931 SPR_NOACCESS, SPR_NOACCESS,
932 &spr_read_generic, &spr_write_generic,
933 0x00000000);
934 /* XXX : not implemented */
935 spr_register(env, SPR_MMCR1, "MMCR1",
936 SPR_NOACCESS, SPR_NOACCESS,
937 &spr_read_generic, &spr_write_generic,
938 0x00000000);
939 /* XXX : not implemented */
940 spr_register(env, SPR_PMC1, "PMC1",
941 SPR_NOACCESS, SPR_NOACCESS,
942 &spr_read_generic, &spr_write_generic,
943 0x00000000);
944 /* XXX : not implemented */
945 spr_register(env, SPR_PMC2, "PMC2",
946 SPR_NOACCESS, SPR_NOACCESS,
947 &spr_read_generic, &spr_write_generic,
948 0x00000000);
949 /* XXX : not implemented */
950 spr_register(env, SPR_PMC3, "PMC3",
951 SPR_NOACCESS, SPR_NOACCESS,
952 &spr_read_generic, &spr_write_generic,
953 0x00000000);
954 /* XXX : not implemented */
955 spr_register(env, SPR_PMC4, "PMC4",
956 SPR_NOACCESS, SPR_NOACCESS,
957 &spr_read_generic, &spr_write_generic,
958 0x00000000);
959 /* XXX : not implemented */
960 spr_register(env, SPR_SIAR, "SIAR",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_generic, SPR_NOACCESS,
963 0x00000000);
964 /* XXX : not implemented */
965 spr_register(env, SPR_UMMCR0, "UMMCR0",
966 &spr_read_ureg, SPR_NOACCESS,
967 &spr_read_ureg, SPR_NOACCESS,
968 0x00000000);
969 /* XXX : not implemented */
970 spr_register(env, SPR_UMMCR1, "UMMCR1",
971 &spr_read_ureg, SPR_NOACCESS,
972 &spr_read_ureg, SPR_NOACCESS,
973 0x00000000);
974 /* XXX : not implemented */
975 spr_register(env, SPR_UPMC1, "UPMC1",
976 &spr_read_ureg, SPR_NOACCESS,
977 &spr_read_ureg, SPR_NOACCESS,
978 0x00000000);
979 /* XXX : not implemented */
980 spr_register(env, SPR_UPMC2, "UPMC2",
981 &spr_read_ureg, SPR_NOACCESS,
982 &spr_read_ureg, SPR_NOACCESS,
983 0x00000000);
984 /* XXX : not implemented */
985 spr_register(env, SPR_UPMC3, "UPMC3",
986 &spr_read_ureg, SPR_NOACCESS,
987 &spr_read_ureg, SPR_NOACCESS,
988 0x00000000);
989 /* XXX : not implemented */
990 spr_register(env, SPR_UPMC4, "UPMC4",
991 &spr_read_ureg, SPR_NOACCESS,
992 &spr_read_ureg, SPR_NOACCESS,
993 0x00000000);
994 /* XXX : not implemented */
995 spr_register(env, SPR_USIAR, "USIAR",
996 &spr_read_ureg, SPR_NOACCESS,
997 &spr_read_ureg, SPR_NOACCESS,
998 0x00000000);
999 /* External access control */
1000 /* XXX : not implemented */
1001 spr_register(env, SPR_EAR, "EAR",
1002 SPR_NOACCESS, SPR_NOACCESS,
1003 &spr_read_generic, &spr_write_generic,
1004 0x00000000);
1005 }
1006
1007 static void gen_spr_thrm (CPUPPCState *env)
1008 {
1009 /* Thermal management */
1010 /* XXX : not implemented */
1011 spr_register(env, SPR_THRM1, "THRM1",
1012 SPR_NOACCESS, SPR_NOACCESS,
1013 &spr_read_generic, &spr_write_generic,
1014 0x00000000);
1015 /* XXX : not implemented */
1016 spr_register(env, SPR_THRM2, "THRM2",
1017 SPR_NOACCESS, SPR_NOACCESS,
1018 &spr_read_generic, &spr_write_generic,
1019 0x00000000);
1020 /* XXX : not implemented */
1021 spr_register(env, SPR_THRM3, "THRM3",
1022 SPR_NOACCESS, SPR_NOACCESS,
1023 &spr_read_generic, &spr_write_generic,
1024 0x00000000);
1025 }
1026
1027 /* SPR specific to PowerPC 604 implementation */
1028 static void gen_spr_604 (CPUPPCState *env)
1029 {
1030 /* Processor identification */
1031 spr_register(env, SPR_PIR, "PIR",
1032 SPR_NOACCESS, SPR_NOACCESS,
1033 &spr_read_generic, &spr_write_pir,
1034 0x00000000);
1035 /* Breakpoints */
1036 /* XXX : not implemented */
1037 spr_register(env, SPR_IABR, "IABR",
1038 SPR_NOACCESS, SPR_NOACCESS,
1039 &spr_read_generic, &spr_write_generic,
1040 0x00000000);
1041 /* XXX : not implemented */
1042 spr_register(env, SPR_DABR, "DABR",
1043 SPR_NOACCESS, SPR_NOACCESS,
1044 &spr_read_generic, &spr_write_generic,
1045 0x00000000);
1046 /* Performance counters */
1047 /* XXX : not implemented */
1048 spr_register(env, SPR_MMCR0, "MMCR0",
1049 SPR_NOACCESS, SPR_NOACCESS,
1050 &spr_read_generic, &spr_write_generic,
1051 0x00000000);
1052 /* XXX : not implemented */
1053 spr_register(env, SPR_PMC1, "PMC1",
1054 SPR_NOACCESS, SPR_NOACCESS,
1055 &spr_read_generic, &spr_write_generic,
1056 0x00000000);
1057 /* XXX : not implemented */
1058 spr_register(env, SPR_PMC2, "PMC2",
1059 SPR_NOACCESS, SPR_NOACCESS,
1060 &spr_read_generic, &spr_write_generic,
1061 0x00000000);
1062 /* XXX : not implemented */
1063 spr_register(env, SPR_SIAR, "SIAR",
1064 SPR_NOACCESS, SPR_NOACCESS,
1065 &spr_read_generic, SPR_NOACCESS,
1066 0x00000000);
1067 /* XXX : not implemented */
1068 spr_register(env, SPR_SDA, "SDA",
1069 SPR_NOACCESS, SPR_NOACCESS,
1070 &spr_read_generic, SPR_NOACCESS,
1071 0x00000000);
1072 /* External access control */
1073 /* XXX : not implemented */
1074 spr_register(env, SPR_EAR, "EAR",
1075 SPR_NOACCESS, SPR_NOACCESS,
1076 &spr_read_generic, &spr_write_generic,
1077 0x00000000);
1078 }
1079
1080 /* SPR specific to PowerPC 603 implementation */
1081 static void gen_spr_603 (CPUPPCState *env)
1082 {
1083 /* External access control */
1084 /* XXX : not implemented */
1085 spr_register(env, SPR_EAR, "EAR",
1086 SPR_NOACCESS, SPR_NOACCESS,
1087 &spr_read_generic, &spr_write_generic,
1088 0x00000000);
1089 }
1090
1091 /* SPR specific to PowerPC G2 implementation */
1092 static void gen_spr_G2 (CPUPPCState *env)
1093 {
1094 /* Memory base address */
1095 /* MBAR */
1096 /* XXX : not implemented */
1097 spr_register(env, SPR_MBAR, "MBAR",
1098 SPR_NOACCESS, SPR_NOACCESS,
1099 &spr_read_generic, &spr_write_generic,
1100 0x00000000);
1101 /* Exception processing */
1102 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1103 SPR_NOACCESS, SPR_NOACCESS,
1104 &spr_read_generic, &spr_write_generic,
1105 0x00000000);
1106 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1107 SPR_NOACCESS, SPR_NOACCESS,
1108 &spr_read_generic, &spr_write_generic,
1109 0x00000000);
1110 /* Breakpoints */
1111 /* XXX : not implemented */
1112 spr_register(env, SPR_DABR, "DABR",
1113 SPR_NOACCESS, SPR_NOACCESS,
1114 &spr_read_generic, &spr_write_generic,
1115 0x00000000);
1116 /* XXX : not implemented */
1117 spr_register(env, SPR_DABR2, "DABR2",
1118 SPR_NOACCESS, SPR_NOACCESS,
1119 &spr_read_generic, &spr_write_generic,
1120 0x00000000);
1121 /* XXX : not implemented */
1122 spr_register(env, SPR_IABR, "IABR",
1123 SPR_NOACCESS, SPR_NOACCESS,
1124 &spr_read_generic, &spr_write_generic,
1125 0x00000000);
1126 /* XXX : not implemented */
1127 spr_register(env, SPR_IABR2, "IABR2",
1128 SPR_NOACCESS, SPR_NOACCESS,
1129 &spr_read_generic, &spr_write_generic,
1130 0x00000000);
1131 /* XXX : not implemented */
1132 spr_register(env, SPR_IBCR, "IBCR",
1133 SPR_NOACCESS, SPR_NOACCESS,
1134 &spr_read_generic, &spr_write_generic,
1135 0x00000000);
1136 /* XXX : not implemented */
1137 spr_register(env, SPR_DBCR, "DBCR",
1138 SPR_NOACCESS, SPR_NOACCESS,
1139 &spr_read_generic, &spr_write_generic,
1140 0x00000000);
1141 }
1142
1143 /* SPR specific to PowerPC 602 implementation */
1144 static void gen_spr_602 (CPUPPCState *env)
1145 {
1146 /* ESA registers */
1147 /* XXX : not implemented */
1148 spr_register(env, SPR_SER, "SER",
1149 SPR_NOACCESS, SPR_NOACCESS,
1150 &spr_read_generic, &spr_write_generic,
1151 0x00000000);
1152 /* XXX : not implemented */
1153 spr_register(env, SPR_SEBR, "SEBR",
1154 SPR_NOACCESS, SPR_NOACCESS,
1155 &spr_read_generic, &spr_write_generic,
1156 0x00000000);
1157 /* XXX : not implemented */
1158 spr_register(env, SPR_ESASRR, "ESASRR",
1159 SPR_NOACCESS, SPR_NOACCESS,
1160 &spr_read_generic, &spr_write_generic,
1161 0x00000000);
1162 /* Floating point status */
1163 /* XXX : not implemented */
1164 spr_register(env, SPR_SP, "SP",
1165 SPR_NOACCESS, SPR_NOACCESS,
1166 &spr_read_generic, &spr_write_generic,
1167 0x00000000);
1168 /* XXX : not implemented */
1169 spr_register(env, SPR_LT, "LT",
1170 SPR_NOACCESS, SPR_NOACCESS,
1171 &spr_read_generic, &spr_write_generic,
1172 0x00000000);
1173 /* Watchdog timer */
1174 /* XXX : not implemented */
1175 spr_register(env, SPR_TCR, "TCR",
1176 SPR_NOACCESS, SPR_NOACCESS,
1177 &spr_read_generic, &spr_write_generic,
1178 0x00000000);
1179 /* Interrupt base */
1180 spr_register(env, SPR_IBR, "IBR",
1181 SPR_NOACCESS, SPR_NOACCESS,
1182 &spr_read_generic, &spr_write_generic,
1183 0x00000000);
1184 /* XXX : not implemented */
1185 spr_register(env, SPR_IABR, "IABR",
1186 SPR_NOACCESS, SPR_NOACCESS,
1187 &spr_read_generic, &spr_write_generic,
1188 0x00000000);
1189 }
1190
1191 /* SPR specific to PowerPC 601 implementation */
1192 static void gen_spr_601 (CPUPPCState *env)
1193 {
1194 /* Multiplication/division register */
1195 /* MQ */
1196 spr_register(env, SPR_MQ, "MQ",
1197 &spr_read_generic, &spr_write_generic,
1198 &spr_read_generic, &spr_write_generic,
1199 0x00000000);
1200 /* RTC registers */
1201 spr_register(env, SPR_601_RTCU, "RTCU",
1202 SPR_NOACCESS, SPR_NOACCESS,
1203 SPR_NOACCESS, &spr_write_601_rtcu,
1204 0x00000000);
1205 spr_register(env, SPR_601_VRTCU, "RTCU",
1206 &spr_read_601_rtcu, SPR_NOACCESS,
1207 &spr_read_601_rtcu, SPR_NOACCESS,
1208 0x00000000);
1209 spr_register(env, SPR_601_RTCL, "RTCL",
1210 SPR_NOACCESS, SPR_NOACCESS,
1211 SPR_NOACCESS, &spr_write_601_rtcl,
1212 0x00000000);
1213 spr_register(env, SPR_601_VRTCL, "RTCL",
1214 &spr_read_601_rtcl, SPR_NOACCESS,
1215 &spr_read_601_rtcl, SPR_NOACCESS,
1216 0x00000000);
1217 /* Timer */
1218 #if 0 /* ? */
1219 spr_register(env, SPR_601_UDECR, "UDECR",
1220 &spr_read_decr, SPR_NOACCESS,
1221 &spr_read_decr, SPR_NOACCESS,
1222 0x00000000);
1223 #endif
1224 /* External access control */
1225 /* XXX : not implemented */
1226 spr_register(env, SPR_EAR, "EAR",
1227 SPR_NOACCESS, SPR_NOACCESS,
1228 &spr_read_generic, &spr_write_generic,
1229 0x00000000);
1230 /* Memory management */
1231 #if !defined(CONFIG_USER_ONLY)
1232 spr_register(env, SPR_IBAT0U, "IBAT0U",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_601_ubat, &spr_write_601_ubatu,
1235 0x00000000);
1236 spr_register(env, SPR_IBAT0L, "IBAT0L",
1237 SPR_NOACCESS, SPR_NOACCESS,
1238 &spr_read_601_ubat, &spr_write_601_ubatl,
1239 0x00000000);
1240 spr_register(env, SPR_IBAT1U, "IBAT1U",
1241 SPR_NOACCESS, SPR_NOACCESS,
1242 &spr_read_601_ubat, &spr_write_601_ubatu,
1243 0x00000000);
1244 spr_register(env, SPR_IBAT1L, "IBAT1L",
1245 SPR_NOACCESS, SPR_NOACCESS,
1246 &spr_read_601_ubat, &spr_write_601_ubatl,
1247 0x00000000);
1248 spr_register(env, SPR_IBAT2U, "IBAT2U",
1249 SPR_NOACCESS, SPR_NOACCESS,
1250 &spr_read_601_ubat, &spr_write_601_ubatu,
1251 0x00000000);
1252 spr_register(env, SPR_IBAT2L, "IBAT2L",
1253 SPR_NOACCESS, SPR_NOACCESS,
1254 &spr_read_601_ubat, &spr_write_601_ubatl,
1255 0x00000000);
1256 spr_register(env, SPR_IBAT3U, "IBAT3U",
1257 SPR_NOACCESS, SPR_NOACCESS,
1258 &spr_read_601_ubat, &spr_write_601_ubatu,
1259 0x00000000);
1260 spr_register(env, SPR_IBAT3L, "IBAT3L",
1261 SPR_NOACCESS, SPR_NOACCESS,
1262 &spr_read_601_ubat, &spr_write_601_ubatl,
1263 0x00000000);
1264 env->nb_BATs = 4;
1265 #endif
1266 }
1267
1268 static void gen_spr_74xx (CPUPPCState *env)
1269 {
1270 /* Processor identification */
1271 spr_register(env, SPR_PIR, "PIR",
1272 SPR_NOACCESS, SPR_NOACCESS,
1273 &spr_read_generic, &spr_write_pir,
1274 0x00000000);
1275 /* XXX : not implemented */
1276 spr_register(env, SPR_MMCR2, "MMCR2",
1277 SPR_NOACCESS, SPR_NOACCESS,
1278 &spr_read_generic, &spr_write_generic,
1279 0x00000000);
1280 /* XXX : not implemented */
1281 spr_register(env, SPR_UMMCR2, "UMMCR2",
1282 &spr_read_ureg, SPR_NOACCESS,
1283 &spr_read_ureg, SPR_NOACCESS,
1284 0x00000000);
1285 /* XXX: not implemented */
1286 spr_register(env, SPR_BAMR, "BAMR",
1287 SPR_NOACCESS, SPR_NOACCESS,
1288 &spr_read_generic, &spr_write_generic,
1289 0x00000000);
1290 /* XXX : not implemented */
1291 spr_register(env, SPR_MSSCR0, "MSSCR0",
1292 SPR_NOACCESS, SPR_NOACCESS,
1293 &spr_read_generic, &spr_write_generic,
1294 0x00000000);
1295 /* Hardware implementation registers */
1296 /* XXX : not implemented */
1297 spr_register(env, SPR_HID0, "HID0",
1298 SPR_NOACCESS, SPR_NOACCESS,
1299 &spr_read_generic, &spr_write_generic,
1300 0x00000000);
1301 /* XXX : not implemented */
1302 spr_register(env, SPR_HID1, "HID1",
1303 SPR_NOACCESS, SPR_NOACCESS,
1304 &spr_read_generic, &spr_write_generic,
1305 0x00000000);
1306 /* Altivec */
1307 spr_register(env, SPR_VRSAVE, "VRSAVE",
1308 &spr_read_generic, &spr_write_generic,
1309 &spr_read_generic, &spr_write_generic,
1310 0x00000000);
1311 /* XXX : not implemented */
1312 spr_register(env, SPR_L2CR, "L2CR",
1313 SPR_NOACCESS, SPR_NOACCESS,
1314 &spr_read_generic, &spr_write_generic,
1315 0x00000000);
1316 /* Not strictly an SPR */
1317 vscr_init(env, 0x00010000);
1318 }
1319
1320 static void gen_l3_ctrl (CPUPPCState *env)
1321 {
1322 /* L3CR */
1323 /* XXX : not implemented */
1324 spr_register(env, SPR_L3CR, "L3CR",
1325 SPR_NOACCESS, SPR_NOACCESS,
1326 &spr_read_generic, &spr_write_generic,
1327 0x00000000);
1328 /* L3ITCR0 */
1329 /* XXX : not implemented */
1330 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_generic,
1333 0x00000000);
1334 /* L3PM */
1335 /* XXX : not implemented */
1336 spr_register(env, SPR_L3PM, "L3PM",
1337 SPR_NOACCESS, SPR_NOACCESS,
1338 &spr_read_generic, &spr_write_generic,
1339 0x00000000);
1340 }
1341
1342 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1343 {
1344 #if !defined(CONFIG_USER_ONLY)
1345 env->nb_tlb = nb_tlbs;
1346 env->nb_ways = nb_ways;
1347 env->id_tlbs = 1;
1348 env->tlb_type = TLB_6XX;
1349 /* XXX : not implemented */
1350 spr_register(env, SPR_PTEHI, "PTEHI",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_generic,
1353 0x00000000);
1354 /* XXX : not implemented */
1355 spr_register(env, SPR_PTELO, "PTELO",
1356 SPR_NOACCESS, SPR_NOACCESS,
1357 &spr_read_generic, &spr_write_generic,
1358 0x00000000);
1359 /* XXX : not implemented */
1360 spr_register(env, SPR_TLBMISS, "TLBMISS",
1361 SPR_NOACCESS, SPR_NOACCESS,
1362 &spr_read_generic, &spr_write_generic,
1363 0x00000000);
1364 #endif
1365 }
1366
1367 #if !defined(CONFIG_USER_ONLY)
1368 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1369 {
1370 TCGv t0 = tcg_temp_new();
1371
1372 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1373 gen_store_spr(sprn, t0);
1374 tcg_temp_free(t0);
1375 }
1376
1377 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1378 {
1379 TCGv_i32 t0 = tcg_const_i32(sprn);
1380 gen_helper_booke206_tlbflush(cpu_env, t0);
1381 tcg_temp_free_i32(t0);
1382 }
1383
1384 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1385 {
1386 TCGv_i32 t0 = tcg_const_i32(sprn);
1387 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1388 tcg_temp_free_i32(t0);
1389 }
1390 #endif
1391
1392 static void gen_spr_usprgh (CPUPPCState *env)
1393 {
1394 spr_register(env, SPR_USPRG4, "USPRG4",
1395 &spr_read_ureg, SPR_NOACCESS,
1396 &spr_read_ureg, SPR_NOACCESS,
1397 0x00000000);
1398 spr_register(env, SPR_USPRG5, "USPRG5",
1399 &spr_read_ureg, SPR_NOACCESS,
1400 &spr_read_ureg, SPR_NOACCESS,
1401 0x00000000);
1402 spr_register(env, SPR_USPRG6, "USPRG6",
1403 &spr_read_ureg, SPR_NOACCESS,
1404 &spr_read_ureg, SPR_NOACCESS,
1405 0x00000000);
1406 spr_register(env, SPR_USPRG7, "USPRG7",
1407 &spr_read_ureg, SPR_NOACCESS,
1408 &spr_read_ureg, SPR_NOACCESS,
1409 0x00000000);
1410 }
1411
1412 /* PowerPC BookE SPR */
1413 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1414 {
1415 const char *ivor_names[64] = {
1416 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1417 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1418 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1419 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1420 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1421 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1422 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1423 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1424 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1425 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1426 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1427 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1428 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1429 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1430 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1431 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1432 };
1433 #define SPR_BOOKE_IVORxx (-1)
1434 int ivor_sprn[64] = {
1435 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1436 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1437 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1438 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1439 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1440 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1441 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1442 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1443 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1444 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1445 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1446 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1447 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1448 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1449 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1450 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1451 };
1452 int i;
1453
1454 /* Interrupt processing */
1455 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1456 SPR_NOACCESS, SPR_NOACCESS,
1457 &spr_read_generic, &spr_write_generic,
1458 0x00000000);
1459 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1460 SPR_NOACCESS, SPR_NOACCESS,
1461 &spr_read_generic, &spr_write_generic,
1462 0x00000000);
1463 /* Debug */
1464 /* XXX : not implemented */
1465 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1466 SPR_NOACCESS, SPR_NOACCESS,
1467 &spr_read_generic, &spr_write_generic,
1468 0x00000000);
1469 /* XXX : not implemented */
1470 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1471 SPR_NOACCESS, SPR_NOACCESS,
1472 &spr_read_generic, &spr_write_generic,
1473 0x00000000);
1474 /* XXX : not implemented */
1475 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1476 SPR_NOACCESS, SPR_NOACCESS,
1477 &spr_read_generic, &spr_write_generic,
1478 0x00000000);
1479 /* XXX : not implemented */
1480 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1481 SPR_NOACCESS, SPR_NOACCESS,
1482 &spr_read_generic, &spr_write_generic,
1483 0x00000000);
1484 /* XXX : not implemented */
1485 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1486 SPR_NOACCESS, SPR_NOACCESS,
1487 &spr_read_generic, &spr_write_generic,
1488 0x00000000);
1489 /* XXX : not implemented */
1490 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1491 SPR_NOACCESS, SPR_NOACCESS,
1492 &spr_read_generic, &spr_write_generic,
1493 0x00000000);
1494 /* XXX : not implemented */
1495 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1496 SPR_NOACCESS, SPR_NOACCESS,
1497 &spr_read_generic, &spr_write_generic,
1498 0x00000000);
1499 /* XXX : not implemented */
1500 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1501 SPR_NOACCESS, SPR_NOACCESS,
1502 &spr_read_generic, &spr_write_clear,
1503 0x00000000);
1504 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1505 SPR_NOACCESS, SPR_NOACCESS,
1506 &spr_read_generic, &spr_write_generic,
1507 0x00000000);
1508 spr_register(env, SPR_BOOKE_ESR, "ESR",
1509 SPR_NOACCESS, SPR_NOACCESS,
1510 &spr_read_generic, &spr_write_generic,
1511 0x00000000);
1512 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1513 SPR_NOACCESS, SPR_NOACCESS,
1514 &spr_read_generic, &spr_write_excp_prefix,
1515 0x00000000);
1516 /* Exception vectors */
1517 for (i = 0; i < 64; i++) {
1518 if (ivor_mask & (1ULL << i)) {
1519 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1520 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1521 exit(1);
1522 }
1523 spr_register(env, ivor_sprn[i], ivor_names[i],
1524 SPR_NOACCESS, SPR_NOACCESS,
1525 &spr_read_generic, &spr_write_excp_vector,
1526 0x00000000);
1527 }
1528 }
1529 spr_register(env, SPR_BOOKE_PID, "PID",
1530 SPR_NOACCESS, SPR_NOACCESS,
1531 &spr_read_generic, &spr_write_booke_pid,
1532 0x00000000);
1533 spr_register(env, SPR_BOOKE_TCR, "TCR",
1534 SPR_NOACCESS, SPR_NOACCESS,
1535 &spr_read_generic, &spr_write_booke_tcr,
1536 0x00000000);
1537 spr_register(env, SPR_BOOKE_TSR, "TSR",
1538 SPR_NOACCESS, SPR_NOACCESS,
1539 &spr_read_generic, &spr_write_booke_tsr,
1540 0x00000000);
1541 /* Timer */
1542 spr_register(env, SPR_DECR, "DECR",
1543 SPR_NOACCESS, SPR_NOACCESS,
1544 &spr_read_decr, &spr_write_decr,
1545 0x00000000);
1546 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1547 SPR_NOACCESS, SPR_NOACCESS,
1548 SPR_NOACCESS, &spr_write_generic,
1549 0x00000000);
1550 /* SPRGs */
1551 spr_register(env, SPR_USPRG0, "USPRG0",
1552 &spr_read_generic, &spr_write_generic,
1553 &spr_read_generic, &spr_write_generic,
1554 0x00000000);
1555 spr_register(env, SPR_SPRG4, "SPRG4",
1556 SPR_NOACCESS, SPR_NOACCESS,
1557 &spr_read_generic, &spr_write_generic,
1558 0x00000000);
1559 spr_register(env, SPR_SPRG5, "SPRG5",
1560 SPR_NOACCESS, SPR_NOACCESS,
1561 &spr_read_generic, &spr_write_generic,
1562 0x00000000);
1563 spr_register(env, SPR_SPRG6, "SPRG6",
1564 SPR_NOACCESS, SPR_NOACCESS,
1565 &spr_read_generic, &spr_write_generic,
1566 0x00000000);
1567 spr_register(env, SPR_SPRG7, "SPRG7",
1568 SPR_NOACCESS, SPR_NOACCESS,
1569 &spr_read_generic, &spr_write_generic,
1570 0x00000000);
1571 }
1572
1573 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1574 uint32_t maxsize, uint32_t flags,
1575 uint32_t nentries)
1576 {
1577 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1578 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1579 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1580 flags | nentries;
1581 }
1582
1583 /* BookE 2.06 storage control registers */
1584 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1585 uint32_t *tlbncfg)
1586 {
1587 #if !defined(CONFIG_USER_ONLY)
1588 const char *mas_names[8] = {
1589 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1590 };
1591 int mas_sprn[8] = {
1592 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1593 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1594 };
1595 int i;
1596
1597 /* TLB assist registers */
1598 /* XXX : not implemented */
1599 for (i = 0; i < 8; i++) {
1600 if (mas_mask & (1 << i)) {
1601 spr_register(env, mas_sprn[i], mas_names[i],
1602 SPR_NOACCESS, SPR_NOACCESS,
1603 &spr_read_generic, &spr_write_generic,
1604 0x00000000);
1605 }
1606 }
1607 if (env->nb_pids > 1) {
1608 /* XXX : not implemented */
1609 spr_register(env, SPR_BOOKE_PID1, "PID1",
1610 SPR_NOACCESS, SPR_NOACCESS,
1611 &spr_read_generic, &spr_write_booke_pid,
1612 0x00000000);
1613 }
1614 if (env->nb_pids > 2) {
1615 /* XXX : not implemented */
1616 spr_register(env, SPR_BOOKE_PID2, "PID2",
1617 SPR_NOACCESS, SPR_NOACCESS,
1618 &spr_read_generic, &spr_write_booke_pid,
1619 0x00000000);
1620 }
1621 /* XXX : not implemented */
1622 spr_register(env, SPR_MMUCFG, "MMUCFG",
1623 SPR_NOACCESS, SPR_NOACCESS,
1624 &spr_read_generic, SPR_NOACCESS,
1625 0x00000000); /* TOFIX */
1626 switch (env->nb_ways) {
1627 case 4:
1628 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1629 SPR_NOACCESS, SPR_NOACCESS,
1630 &spr_read_generic, SPR_NOACCESS,
1631 tlbncfg[3]);
1632 /* Fallthru */
1633 case 3:
1634 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 &spr_read_generic, SPR_NOACCESS,
1637 tlbncfg[2]);
1638 /* Fallthru */
1639 case 2:
1640 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1641 SPR_NOACCESS, SPR_NOACCESS,
1642 &spr_read_generic, SPR_NOACCESS,
1643 tlbncfg[1]);
1644 /* Fallthru */
1645 case 1:
1646 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1647 SPR_NOACCESS, SPR_NOACCESS,
1648 &spr_read_generic, SPR_NOACCESS,
1649 tlbncfg[0]);
1650 /* Fallthru */
1651 case 0:
1652 default:
1653 break;
1654 }
1655 #endif
1656
1657 gen_spr_usprgh(env);
1658 }
1659
1660 /* SPR specific to PowerPC 440 implementation */
1661 static void gen_spr_440 (CPUPPCState *env)
1662 {
1663 /* Cache control */
1664 /* XXX : not implemented */
1665 spr_register(env, SPR_440_DNV0, "DNV0",
1666 SPR_NOACCESS, SPR_NOACCESS,
1667 &spr_read_generic, &spr_write_generic,
1668 0x00000000);
1669 /* XXX : not implemented */
1670 spr_register(env, SPR_440_DNV1, "DNV1",
1671 SPR_NOACCESS, SPR_NOACCESS,
1672 &spr_read_generic, &spr_write_generic,
1673 0x00000000);
1674 /* XXX : not implemented */
1675 spr_register(env, SPR_440_DNV2, "DNV2",
1676 SPR_NOACCESS, SPR_NOACCESS,
1677 &spr_read_generic, &spr_write_generic,
1678 0x00000000);
1679 /* XXX : not implemented */
1680 spr_register(env, SPR_440_DNV3, "DNV3",
1681 SPR_NOACCESS, SPR_NOACCESS,
1682 &spr_read_generic, &spr_write_generic,
1683 0x00000000);
1684 /* XXX : not implemented */
1685 spr_register(env, SPR_440_DTV0, "DTV0",
1686 SPR_NOACCESS, SPR_NOACCESS,
1687 &spr_read_generic, &spr_write_generic,
1688 0x00000000);
1689 /* XXX : not implemented */
1690 spr_register(env, SPR_440_DTV1, "DTV1",
1691 SPR_NOACCESS, SPR_NOACCESS,
1692 &spr_read_generic, &spr_write_generic,
1693 0x00000000);
1694 /* XXX : not implemented */
1695 spr_register(env, SPR_440_DTV2, "DTV2",
1696 SPR_NOACCESS, SPR_NOACCESS,
1697 &spr_read_generic, &spr_write_generic,
1698 0x00000000);
1699 /* XXX : not implemented */
1700 spr_register(env, SPR_440_DTV3, "DTV3",
1701 SPR_NOACCESS, SPR_NOACCESS,
1702 &spr_read_generic, &spr_write_generic,
1703 0x00000000);
1704 /* XXX : not implemented */
1705 spr_register(env, SPR_440_DVLIM, "DVLIM",
1706 SPR_NOACCESS, SPR_NOACCESS,
1707 &spr_read_generic, &spr_write_generic,
1708 0x00000000);
1709 /* XXX : not implemented */
1710 spr_register(env, SPR_440_INV0, "INV0",
1711 SPR_NOACCESS, SPR_NOACCESS,
1712 &spr_read_generic, &spr_write_generic,
1713 0x00000000);
1714 /* XXX : not implemented */
1715 spr_register(env, SPR_440_INV1, "INV1",
1716 SPR_NOACCESS, SPR_NOACCESS,
1717 &spr_read_generic, &spr_write_generic,
1718 0x00000000);
1719 /* XXX : not implemented */
1720 spr_register(env, SPR_440_INV2, "INV2",
1721 SPR_NOACCESS, SPR_NOACCESS,
1722 &spr_read_generic, &spr_write_generic,
1723 0x00000000);
1724 /* XXX : not implemented */
1725 spr_register(env, SPR_440_INV3, "INV3",
1726 SPR_NOACCESS, SPR_NOACCESS,
1727 &spr_read_generic, &spr_write_generic,
1728 0x00000000);
1729 /* XXX : not implemented */
1730 spr_register(env, SPR_440_ITV0, "ITV0",
1731 SPR_NOACCESS, SPR_NOACCESS,
1732 &spr_read_generic, &spr_write_generic,
1733 0x00000000);
1734 /* XXX : not implemented */
1735 spr_register(env, SPR_440_ITV1, "ITV1",
1736 SPR_NOACCESS, SPR_NOACCESS,
1737 &spr_read_generic, &spr_write_generic,
1738 0x00000000);
1739 /* XXX : not implemented */
1740 spr_register(env, SPR_440_ITV2, "ITV2",
1741 SPR_NOACCESS, SPR_NOACCESS,
1742 &spr_read_generic, &spr_write_generic,
1743 0x00000000);
1744 /* XXX : not implemented */
1745 spr_register(env, SPR_440_ITV3, "ITV3",
1746 SPR_NOACCESS, SPR_NOACCESS,
1747 &spr_read_generic, &spr_write_generic,
1748 0x00000000);
1749 /* XXX : not implemented */
1750 spr_register(env, SPR_440_IVLIM, "IVLIM",
1751 SPR_NOACCESS, SPR_NOACCESS,
1752 &spr_read_generic, &spr_write_generic,
1753 0x00000000);
1754 /* Cache debug */
1755 /* XXX : not implemented */
1756 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1757 SPR_NOACCESS, SPR_NOACCESS,
1758 &spr_read_generic, SPR_NOACCESS,
1759 0x00000000);
1760 /* XXX : not implemented */
1761 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1762 SPR_NOACCESS, SPR_NOACCESS,
1763 &spr_read_generic, SPR_NOACCESS,
1764 0x00000000);
1765 /* XXX : not implemented */
1766 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1767 SPR_NOACCESS, SPR_NOACCESS,
1768 &spr_read_generic, SPR_NOACCESS,
1769 0x00000000);
1770 /* XXX : not implemented */
1771 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1772 SPR_NOACCESS, SPR_NOACCESS,
1773 &spr_read_generic, SPR_NOACCESS,
1774 0x00000000);
1775 /* XXX : not implemented */
1776 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1777 SPR_NOACCESS, SPR_NOACCESS,
1778 &spr_read_generic, SPR_NOACCESS,
1779 0x00000000);
1780 /* XXX : not implemented */
1781 spr_register(env, SPR_440_DBDR, "DBDR",
1782 SPR_NOACCESS, SPR_NOACCESS,
1783 &spr_read_generic, &spr_write_generic,
1784 0x00000000);
1785 /* Processor control */
1786 spr_register(env, SPR_4xx_CCR0, "CCR0",
1787 SPR_NOACCESS, SPR_NOACCESS,
1788 &spr_read_generic, &spr_write_generic,
1789 0x00000000);
1790 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1791 SPR_NOACCESS, SPR_NOACCESS,
1792 &spr_read_generic, SPR_NOACCESS,
1793 0x00000000);
1794 /* Storage control */
1795 spr_register(env, SPR_440_MMUCR, "MMUCR",
1796 SPR_NOACCESS, SPR_NOACCESS,
1797 &spr_read_generic, &spr_write_generic,
1798 0x00000000);
1799 }
1800
1801 /* SPR shared between PowerPC 40x implementations */
1802 static void gen_spr_40x (CPUPPCState *env)
1803 {
1804 /* Cache */
1805 /* not emulated, as QEMU do not emulate caches */
1806 spr_register(env, SPR_40x_DCCR, "DCCR",
1807 SPR_NOACCESS, SPR_NOACCESS,
1808 &spr_read_generic, &spr_write_generic,
1809 0x00000000);
1810 /* not emulated, as QEMU do not emulate caches */
1811 spr_register(env, SPR_40x_ICCR, "ICCR",
1812 SPR_NOACCESS, SPR_NOACCESS,
1813 &spr_read_generic, &spr_write_generic,
1814 0x00000000);
1815 /* not emulated, as QEMU do not emulate caches */
1816 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1817 SPR_NOACCESS, SPR_NOACCESS,
1818 &spr_read_generic, SPR_NOACCESS,
1819 0x00000000);
1820 /* Exception */
1821 spr_register(env, SPR_40x_DEAR, "DEAR",
1822 SPR_NOACCESS, SPR_NOACCESS,
1823 &spr_read_generic, &spr_write_generic,
1824 0x00000000);
1825 spr_register(env, SPR_40x_ESR, "ESR",
1826 SPR_NOACCESS, SPR_NOACCESS,
1827 &spr_read_generic, &spr_write_generic,
1828 0x00000000);
1829 spr_register(env, SPR_40x_EVPR, "EVPR",
1830 SPR_NOACCESS, SPR_NOACCESS,
1831 &spr_read_generic, &spr_write_excp_prefix,
1832 0x00000000);
1833 spr_register(env, SPR_40x_SRR2, "SRR2",
1834 &spr_read_generic, &spr_write_generic,
1835 &spr_read_generic, &spr_write_generic,
1836 0x00000000);
1837 spr_register(env, SPR_40x_SRR3, "SRR3",
1838 &spr_read_generic, &spr_write_generic,
1839 &spr_read_generic, &spr_write_generic,
1840 0x00000000);
1841 /* Timers */
1842 spr_register(env, SPR_40x_PIT, "PIT",
1843 SPR_NOACCESS, SPR_NOACCESS,
1844 &spr_read_40x_pit, &spr_write_40x_pit,
1845 0x00000000);
1846 spr_register(env, SPR_40x_TCR, "TCR",
1847 SPR_NOACCESS, SPR_NOACCESS,
1848 &spr_read_generic, &spr_write_booke_tcr,
1849 0x00000000);
1850 spr_register(env, SPR_40x_TSR, "TSR",
1851 SPR_NOACCESS, SPR_NOACCESS,
1852 &spr_read_generic, &spr_write_booke_tsr,
1853 0x00000000);
1854 }
1855
1856 /* SPR specific to PowerPC 405 implementation */
1857 static void gen_spr_405 (CPUPPCState *env)
1858 {
1859 /* MMU */
1860 spr_register(env, SPR_40x_PID, "PID",
1861 SPR_NOACCESS, SPR_NOACCESS,
1862 &spr_read_generic, &spr_write_generic,
1863 0x00000000);
1864 spr_register(env, SPR_4xx_CCR0, "CCR0",
1865 SPR_NOACCESS, SPR_NOACCESS,
1866 &spr_read_generic, &spr_write_generic,
1867 0x00700000);
1868 /* Debug interface */
1869 /* XXX : not implemented */
1870 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1871 SPR_NOACCESS, SPR_NOACCESS,
1872 &spr_read_generic, &spr_write_40x_dbcr0,
1873 0x00000000);
1874 /* XXX : not implemented */
1875 spr_register(env, SPR_405_DBCR1, "DBCR1",
1876 SPR_NOACCESS, SPR_NOACCESS,
1877 &spr_read_generic, &spr_write_generic,
1878 0x00000000);
1879 /* XXX : not implemented */
1880 spr_register(env, SPR_40x_DBSR, "DBSR",
1881 SPR_NOACCESS, SPR_NOACCESS,
1882 &spr_read_generic, &spr_write_clear,
1883 /* Last reset was system reset */
1884 0x00000300);
1885 /* XXX : not implemented */
1886 spr_register(env, SPR_40x_DAC1, "DAC1",
1887 SPR_NOACCESS, SPR_NOACCESS,
1888 &spr_read_generic, &spr_write_generic,
1889 0x00000000);
1890 spr_register(env, SPR_40x_DAC2, "DAC2",
1891 SPR_NOACCESS, SPR_NOACCESS,
1892 &spr_read_generic, &spr_write_generic,
1893 0x00000000);
1894 /* XXX : not implemented */
1895 spr_register(env, SPR_405_DVC1, "DVC1",
1896 SPR_NOACCESS, SPR_NOACCESS,
1897 &spr_read_generic, &spr_write_generic,
1898 0x00000000);
1899 /* XXX : not implemented */
1900 spr_register(env, SPR_405_DVC2, "DVC2",
1901 SPR_NOACCESS, SPR_NOACCESS,
1902 &spr_read_generic, &spr_write_generic,
1903 0x00000000);
1904 /* XXX : not implemented */
1905 spr_register(env, SPR_40x_IAC1, "IAC1",
1906 SPR_NOACCESS, SPR_NOACCESS,
1907 &spr_read_generic, &spr_write_generic,
1908 0x00000000);
1909 spr_register(env, SPR_40x_IAC2, "IAC2",
1910 SPR_NOACCESS, SPR_NOACCESS,
1911 &spr_read_generic, &spr_write_generic,
1912 0x00000000);
1913 /* XXX : not implemented */
1914 spr_register(env, SPR_405_IAC3, "IAC3",
1915 SPR_NOACCESS, SPR_NOACCESS,
1916 &spr_read_generic, &spr_write_generic,
1917 0x00000000);
1918 /* XXX : not implemented */
1919 spr_register(env, SPR_405_IAC4, "IAC4",
1920 SPR_NOACCESS, SPR_NOACCESS,
1921 &spr_read_generic, &spr_write_generic,
1922 0x00000000);
1923 /* Storage control */
1924 /* XXX: TODO: not implemented */
1925 spr_register(env, SPR_405_SLER, "SLER",
1926 SPR_NOACCESS, SPR_NOACCESS,
1927 &spr_read_generic, &spr_write_40x_sler,
1928 0x00000000);
1929 spr_register(env, SPR_40x_ZPR, "ZPR",
1930 SPR_NOACCESS, SPR_NOACCESS,
1931 &spr_read_generic, &spr_write_generic,
1932 0x00000000);
1933 /* XXX : not implemented */
1934 spr_register(env, SPR_405_SU0R, "SU0R",
1935 SPR_NOACCESS, SPR_NOACCESS,
1936 &spr_read_generic, &spr_write_generic,
1937 0x00000000);
1938 /* SPRG */
1939 spr_register(env, SPR_USPRG0, "USPRG0",
1940 &spr_read_ureg, SPR_NOACCESS,
1941 &spr_read_ureg, SPR_NOACCESS,
1942 0x00000000);
1943 spr_register(env, SPR_SPRG4, "SPRG4",
1944 SPR_NOACCESS, SPR_NOACCESS,
1945 &spr_read_generic, &spr_write_generic,
1946 0x00000000);
1947 spr_register(env, SPR_SPRG5, "SPRG5",
1948 SPR_NOACCESS, SPR_NOACCESS,
1949 spr_read_generic, &spr_write_generic,
1950 0x00000000);
1951 spr_register(env, SPR_SPRG6, "SPRG6",
1952 SPR_NOACCESS, SPR_NOACCESS,
1953 spr_read_generic, &spr_write_generic,
1954 0x00000000);
1955 spr_register(env, SPR_SPRG7, "SPRG7",
1956 SPR_NOACCESS, SPR_NOACCESS,
1957 spr_read_generic, &spr_write_generic,
1958 0x00000000);
1959 gen_spr_usprgh(env);
1960 }
1961
1962 /* SPR shared between PowerPC 401 & 403 implementations */
1963 static void gen_spr_401_403 (CPUPPCState *env)
1964 {
1965 /* Time base */
1966 spr_register(env, SPR_403_VTBL, "TBL",
1967 &spr_read_tbl, SPR_NOACCESS,
1968 &spr_read_tbl, SPR_NOACCESS,
1969 0x00000000);
1970 spr_register(env, SPR_403_TBL, "TBL",
1971 SPR_NOACCESS, SPR_NOACCESS,
1972 SPR_NOACCESS, &spr_write_tbl,
1973 0x00000000);
1974 spr_register(env, SPR_403_VTBU, "TBU",
1975 &spr_read_tbu, SPR_NOACCESS,
1976 &spr_read_tbu, SPR_NOACCESS,
1977 0x00000000);
1978 spr_register(env, SPR_403_TBU, "TBU",
1979 SPR_NOACCESS, SPR_NOACCESS,
1980 SPR_NOACCESS, &spr_write_tbu,
1981 0x00000000);
1982 /* Debug */
1983 /* not emulated, as QEMU do not emulate caches */
1984 spr_register(env, SPR_403_CDBCR, "CDBCR",
1985 SPR_NOACCESS, SPR_NOACCESS,
1986 &spr_read_generic, &spr_write_generic,
1987 0x00000000);
1988 }
1989
1990 /* SPR specific to PowerPC 401 implementation */
1991 static void gen_spr_401 (CPUPPCState *env)
1992 {
1993 /* Debug interface */
1994 /* XXX : not implemented */
1995 spr_register(env, SPR_40x_DBCR0, "DBCR",
1996 SPR_NOACCESS, SPR_NOACCESS,
1997 &spr_read_generic, &spr_write_40x_dbcr0,
1998 0x00000000);
1999 /* XXX : not implemented */
2000 spr_register(env, SPR_40x_DBSR, "DBSR",
2001 SPR_NOACCESS, SPR_NOACCESS,
2002 &spr_read_generic, &spr_write_clear,
2003 /* Last reset was system reset */
2004 0x00000300);
2005 /* XXX : not implemented */
2006 spr_register(env, SPR_40x_DAC1, "DAC",
2007 SPR_NOACCESS, SPR_NOACCESS,
2008 &spr_read_generic, &spr_write_generic,
2009 0x00000000);
2010 /* XXX : not implemented */
2011 spr_register(env, SPR_40x_IAC1, "IAC",
2012 SPR_NOACCESS, SPR_NOACCESS,
2013 &spr_read_generic, &spr_write_generic,
2014 0x00000000);
2015 /* Storage control */
2016 /* XXX: TODO: not implemented */
2017 spr_register(env, SPR_405_SLER, "SLER",
2018 SPR_NOACCESS, SPR_NOACCESS,
2019 &spr_read_generic, &spr_write_40x_sler,
2020 0x00000000);
2021 /* not emulated, as QEMU never does speculative access */
2022 spr_register(env, SPR_40x_SGR, "SGR",
2023 SPR_NOACCESS, SPR_NOACCESS,
2024 &spr_read_generic, &spr_write_generic,
2025 0xFFFFFFFF);
2026 /* not emulated, as QEMU do not emulate caches */
2027 spr_register(env, SPR_40x_DCWR, "DCWR",
2028 SPR_NOACCESS, SPR_NOACCESS,
2029 &spr_read_generic, &spr_write_generic,
2030 0x00000000);
2031 }
2032
2033 static void gen_spr_401x2 (CPUPPCState *env)
2034 {
2035 gen_spr_401(env);
2036 spr_register(env, SPR_40x_PID, "PID",
2037 SPR_NOACCESS, SPR_NOACCESS,
2038 &spr_read_generic, &spr_write_generic,
2039 0x00000000);
2040 spr_register(env, SPR_40x_ZPR, "ZPR",
2041 SPR_NOACCESS, SPR_NOACCESS,
2042 &spr_read_generic, &spr_write_generic,
2043 0x00000000);
2044 }
2045
2046 /* SPR specific to PowerPC 403 implementation */
2047 static void gen_spr_403 (CPUPPCState *env)
2048 {
2049 /* Debug interface */
2050 /* XXX : not implemented */
2051 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2052 SPR_NOACCESS, SPR_NOACCESS,
2053 &spr_read_generic, &spr_write_40x_dbcr0,
2054 0x00000000);
2055 /* XXX : not implemented */
2056 spr_register(env, SPR_40x_DBSR, "DBSR",
2057 SPR_NOACCESS, SPR_NOACCESS,
2058 &spr_read_generic, &spr_write_clear,
2059 /* Last reset was system reset */
2060 0x00000300);
2061 /* XXX : not implemented */
2062 spr_register(env, SPR_40x_DAC1, "DAC1",
2063 SPR_NOACCESS, SPR_NOACCESS,
2064 &spr_read_generic, &spr_write_generic,
2065 0x00000000);
2066 /* XXX : not implemented */
2067 spr_register(env, SPR_40x_DAC2, "DAC2",
2068 SPR_NOACCESS, SPR_NOACCESS,
2069 &spr_read_generic, &spr_write_generic,
2070 0x00000000);
2071 /* XXX : not implemented */
2072 spr_register(env, SPR_40x_IAC1, "IAC1",
2073 SPR_NOACCESS, SPR_NOACCESS,
2074 &spr_read_generic, &spr_write_generic,
2075 0x00000000);
2076 /* XXX : not implemented */
2077 spr_register(env, SPR_40x_IAC2, "IAC2",
2078 SPR_NOACCESS, SPR_NOACCESS,
2079 &spr_read_generic, &spr_write_generic,
2080 0x00000000);
2081 }
2082
2083 static void gen_spr_403_real (CPUPPCState *env)
2084 {
2085 spr_register(env, SPR_403_PBL1, "PBL1",
2086 SPR_NOACCESS, SPR_NOACCESS,
2087 &spr_read_403_pbr, &spr_write_403_pbr,
2088 0x00000000);
2089 spr_register(env, SPR_403_PBU1, "PBU1",
2090 SPR_NOACCESS, SPR_NOACCESS,
2091 &spr_read_403_pbr, &spr_write_403_pbr,
2092 0x00000000);
2093 spr_register(env, SPR_403_PBL2, "PBL2",
2094 SPR_NOACCESS, SPR_NOACCESS,
2095 &spr_read_403_pbr, &spr_write_403_pbr,
2096 0x00000000);
2097 spr_register(env, SPR_403_PBU2, "PBU2",
2098 SPR_NOACCESS, SPR_NOACCESS,
2099 &spr_read_403_pbr, &spr_write_403_pbr,
2100 0x00000000);
2101 }
2102
2103 static void gen_spr_403_mmu (CPUPPCState *env)
2104 {
2105 /* MMU */
2106 spr_register(env, SPR_40x_PID, "PID",
2107 SPR_NOACCESS, SPR_NOACCESS,
2108 &spr_read_generic, &spr_write_generic,
2109 0x00000000);
2110 spr_register(env, SPR_40x_ZPR, "ZPR",
2111 SPR_NOACCESS, SPR_NOACCESS,
2112 &spr_read_generic, &spr_write_generic,
2113 0x00000000);
2114 }
2115
2116 /* SPR specific to PowerPC compression coprocessor extension */
2117 static void gen_spr_compress (CPUPPCState *env)
2118 {
2119 /* XXX : not implemented */
2120 spr_register(env, SPR_401_SKR, "SKR",
2121 SPR_NOACCESS, SPR_NOACCESS,
2122 &spr_read_generic, &spr_write_generic,
2123 0x00000000);
2124 }
2125
2126 #if defined (TARGET_PPC64)
2127 /* SPR specific to PowerPC 620 */
2128 static void gen_spr_620 (CPUPPCState *env)
2129 {
2130 /* Processor identification */
2131 spr_register(env, SPR_PIR, "PIR",
2132 SPR_NOACCESS, SPR_NOACCESS,
2133 &spr_read_generic, &spr_write_pir,
2134 0x00000000);
2135 spr_register(env, SPR_ASR, "ASR",
2136 SPR_NOACCESS, SPR_NOACCESS,
2137 &spr_read_asr, &spr_write_asr,
2138 0x00000000);
2139 /* Breakpoints */
2140 /* XXX : not implemented */
2141 spr_register(env, SPR_IABR, "IABR",
2142 SPR_NOACCESS, SPR_NOACCESS,
2143 &spr_read_generic, &spr_write_generic,
2144 0x00000000);
2145 /* XXX : not implemented */
2146 spr_register(env, SPR_DABR, "DABR",
2147 SPR_NOACCESS, SPR_NOACCESS,
2148 &spr_read_generic, &spr_write_generic,
2149 0x00000000);
2150 /* XXX : not implemented */
2151 spr_register(env, SPR_SIAR, "SIAR",
2152 SPR_NOACCESS, SPR_NOACCESS,
2153 &spr_read_generic, SPR_NOACCESS,
2154 0x00000000);
2155 /* XXX : not implemented */
2156 spr_register(env, SPR_SDA, "SDA",
2157 SPR_NOACCESS, SPR_NOACCESS,
2158 &spr_read_generic, SPR_NOACCESS,
2159 0x00000000);
2160 /* XXX : not implemented */
2161 spr_register(env, SPR_620_PMC1R, "PMC1",
2162 SPR_NOACCESS, SPR_NOACCESS,
2163 &spr_read_generic, SPR_NOACCESS,
2164 0x00000000);
2165 spr_register(env, SPR_620_PMC1W, "PMC1",
2166 SPR_NOACCESS, SPR_NOACCESS,
2167 SPR_NOACCESS, &spr_write_generic,
2168 0x00000000);
2169 /* XXX : not implemented */
2170 spr_register(env, SPR_620_PMC2R, "PMC2",
2171 SPR_NOACCESS, SPR_NOACCESS,
2172 &spr_read_generic, SPR_NOACCESS,
2173 0x00000000);
2174 spr_register(env, SPR_620_PMC2W, "PMC2",
2175 SPR_NOACCESS, SPR_NOACCESS,
2176 SPR_NOACCESS, &spr_write_generic,
2177 0x00000000);
2178 /* XXX : not implemented */
2179 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2180 SPR_NOACCESS, SPR_NOACCESS,
2181 &spr_read_generic, SPR_NOACCESS,
2182 0x00000000);
2183 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2184 SPR_NOACCESS, SPR_NOACCESS,
2185 SPR_NOACCESS, &spr_write_generic,
2186 0x00000000);
2187 /* External access control */
2188 /* XXX : not implemented */
2189 spr_register(env, SPR_EAR, "EAR",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 &spr_read_generic, &spr_write_generic,
2192 0x00000000);
2193 #if 0 // XXX: check this
2194 /* XXX : not implemented */
2195 spr_register(env, SPR_620_PMR0, "PMR0",
2196 SPR_NOACCESS, SPR_NOACCESS,
2197 &spr_read_generic, &spr_write_generic,
2198 0x00000000);
2199 /* XXX : not implemented */
2200 spr_register(env, SPR_620_PMR1, "PMR1",
2201 SPR_NOACCESS, SPR_NOACCESS,
2202 &spr_read_generic, &spr_write_generic,
2203 0x00000000);
2204 /* XXX : not implemented */
2205 spr_register(env, SPR_620_PMR2, "PMR2",
2206 SPR_NOACCESS, SPR_NOACCESS,
2207 &spr_read_generic, &spr_write_generic,
2208 0x00000000);
2209 /* XXX : not implemented */
2210 spr_register(env, SPR_620_PMR3, "PMR3",
2211 SPR_NOACCESS, SPR_NOACCESS,
2212 &spr_read_generic, &spr_write_generic,
2213 0x00000000);
2214 /* XXX : not implemented */
2215 spr_register(env, SPR_620_PMR4, "PMR4",
2216 SPR_NOACCESS, SPR_NOACCESS,
2217 &spr_read_generic, &spr_write_generic,
2218 0x00000000);
2219 /* XXX : not implemented */
2220 spr_register(env, SPR_620_PMR5, "PMR5",
2221 SPR_NOACCESS, SPR_NOACCESS,
2222 &spr_read_generic, &spr_write_generic,
2223 0x00000000);
2224 /* XXX : not implemented */
2225 spr_register(env, SPR_620_PMR6, "PMR6",
2226 SPR_NOACCESS, SPR_NOACCESS,
2227 &spr_read_generic, &spr_write_generic,
2228 0x00000000);
2229 /* XXX : not implemented */
2230 spr_register(env, SPR_620_PMR7, "PMR7",
2231 SPR_NOACCESS, SPR_NOACCESS,
2232 &spr_read_generic, &spr_write_generic,
2233 0x00000000);
2234 /* XXX : not implemented */
2235 spr_register(env, SPR_620_PMR8, "PMR8",
2236 SPR_NOACCESS, SPR_NOACCESS,
2237 &spr_read_generic, &spr_write_generic,
2238 0x00000000);
2239 /* XXX : not implemented */
2240 spr_register(env, SPR_620_PMR9, "PMR9",
2241 SPR_NOACCESS, SPR_NOACCESS,
2242 &spr_read_generic, &spr_write_generic,
2243 0x00000000);
2244 /* XXX : not implemented */
2245 spr_register(env, SPR_620_PMRA, "PMR10",
2246 SPR_NOACCESS, SPR_NOACCESS,
2247 &spr_read_generic, &spr_write_generic,
2248 0x00000000);
2249 /* XXX : not implemented */
2250 spr_register(env, SPR_620_PMRB, "PMR11",
2251 SPR_NOACCESS, SPR_NOACCESS,
2252 &spr_read_generic, &spr_write_generic,
2253 0x00000000);
2254 /* XXX : not implemented */
2255 spr_register(env, SPR_620_PMRC, "PMR12",
2256 SPR_NOACCESS, SPR_NOACCESS,
2257 &spr_read_generic, &spr_write_generic,
2258 0x00000000);
2259 /* XXX : not implemented */
2260 spr_register(env, SPR_620_PMRD, "PMR13",
2261 SPR_NOACCESS, SPR_NOACCESS,
2262 &spr_read_generic, &spr_write_generic,
2263 0x00000000);
2264 /* XXX : not implemented */
2265 spr_register(env, SPR_620_PMRE, "PMR14",
2266 SPR_NOACCESS, SPR_NOACCESS,
2267 &spr_read_generic, &spr_write_generic,
2268 0x00000000);
2269 /* XXX : not implemented */
2270 spr_register(env, SPR_620_PMRF, "PMR15",
2271 SPR_NOACCESS, SPR_NOACCESS,
2272 &spr_read_generic, &spr_write_generic,
2273 0x00000000);
2274 #endif
2275 /* XXX : not implemented */
2276 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2277 SPR_NOACCESS, SPR_NOACCESS,
2278 &spr_read_generic, &spr_write_generic,
2279 0x00000000);
2280 /* XXX : not implemented */
2281 spr_register(env, SPR_620_L2CR, "L2CR",
2282 SPR_NOACCESS, SPR_NOACCESS,
2283 &spr_read_generic, &spr_write_generic,
2284 0x00000000);
2285 /* XXX : not implemented */
2286 spr_register(env, SPR_620_L2SR, "L2SR",
2287 SPR_NOACCESS, SPR_NOACCESS,
2288 &spr_read_generic, &spr_write_generic,
2289 0x00000000);
2290 }
2291 #endif /* defined (TARGET_PPC64) */
2292
2293 static void gen_spr_5xx_8xx (CPUPPCState *env)
2294 {
2295 /* Exception processing */
2296 spr_register(env, SPR_DSISR, "DSISR",
2297 SPR_NOACCESS, SPR_NOACCESS,
2298 &spr_read_generic, &spr_write_generic,
2299 0x00000000);
2300 spr_register(env, SPR_DAR, "DAR",
2301 SPR_NOACCESS, SPR_NOACCESS,
2302 &spr_read_generic, &spr_write_generic,
2303 0x00000000);
2304 /* Timer */
2305 spr_register(env, SPR_DECR, "DECR",
2306 SPR_NOACCESS, SPR_NOACCESS,
2307 &spr_read_decr, &spr_write_decr,
2308 0x00000000);
2309 /* XXX : not implemented */
2310 spr_register(env, SPR_MPC_EIE, "EIE",
2311 SPR_NOACCESS, SPR_NOACCESS,
2312 &spr_read_generic, &spr_write_generic,
2313 0x00000000);
2314 /* XXX : not implemented */
2315 spr_register(env, SPR_MPC_EID, "EID",
2316 SPR_NOACCESS, SPR_NOACCESS,
2317 &spr_read_generic, &spr_write_generic,
2318 0x00000000);
2319 /* XXX : not implemented */
2320 spr_register(env, SPR_MPC_NRI, "NRI",
2321 SPR_NOACCESS, SPR_NOACCESS,
2322 &spr_read_generic, &spr_write_generic,
2323 0x00000000);
2324 /* XXX : not implemented */
2325 spr_register(env, SPR_MPC_CMPA, "CMPA",
2326 SPR_NOACCESS, SPR_NOACCESS,
2327 &spr_read_generic, &spr_write_generic,
2328 0x00000000);
2329 /* XXX : not implemented */
2330 spr_register(env, SPR_MPC_CMPB, "CMPB",
2331 SPR_NOACCESS, SPR_NOACCESS,
2332 &spr_read_generic, &spr_write_generic,
2333 0x00000000);
2334 /* XXX : not implemented */
2335 spr_register(env, SPR_MPC_CMPC, "CMPC",
2336 SPR_NOACCESS, SPR_NOACCESS,
2337 &spr_read_generic, &spr_write_generic,
2338 0x00000000);
2339 /* XXX : not implemented */
2340 spr_register(env, SPR_MPC_CMPD, "CMPD",
2341 SPR_NOACCESS, SPR_NOACCESS,
2342 &spr_read_generic, &spr_write_generic,
2343 0x00000000);
2344 /* XXX : not implemented */
2345 spr_register(env, SPR_MPC_ECR, "ECR",
2346 SPR_NOACCESS, SPR_NOACCESS,
2347 &spr_read_generic, &spr_write_generic,
2348 0x00000000);
2349 /* XXX : not implemented */
2350 spr_register(env, SPR_MPC_DER, "DER",
2351 SPR_NOACCESS, SPR_NOACCESS,
2352 &spr_read_generic, &spr_write_generic,
2353 0x00000000);
2354 /* XXX : not implemented */
2355 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2356 SPR_NOACCESS, SPR_NOACCESS,
2357 &spr_read_generic, &spr_write_generic,
2358 0x00000000);
2359 /* XXX : not implemented */
2360 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2361 SPR_NOACCESS, SPR_NOACCESS,
2362 &spr_read_generic, &spr_write_generic,
2363 0x00000000);
2364 /* XXX : not implemented */
2365 spr_register(env, SPR_MPC_CMPE, "CMPE",
2366 SPR_NOACCESS, SPR_NOACCESS,
2367 &spr_read_generic, &spr_write_generic,
2368 0x00000000);
2369 /* XXX : not implemented */
2370 spr_register(env, SPR_MPC_CMPF, "CMPF",
2371 SPR_NOACCESS, SPR_NOACCESS,
2372 &spr_read_generic, &spr_write_generic,
2373 0x00000000);
2374 /* XXX : not implemented */
2375 spr_register(env, SPR_MPC_CMPG, "CMPG",
2376 SPR_NOACCESS, SPR_NOACCESS,
2377 &spr_read_generic, &spr_write_generic,
2378 0x00000000);
2379 /* XXX : not implemented */
2380 spr_register(env, SPR_MPC_CMPH, "CMPH",
2381 SPR_NOACCESS, SPR_NOACCESS,
2382 &spr_read_generic, &spr_write_generic,
2383 0x00000000);
2384 /* XXX : not implemented */
2385 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2386 SPR_NOACCESS, SPR_NOACCESS,
2387 &spr_read_generic, &spr_write_generic,
2388 0x00000000);
2389 /* XXX : not implemented */
2390 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2391 SPR_NOACCESS, SPR_NOACCESS,
2392 &spr_read_generic, &spr_write_generic,
2393 0x00000000);
2394 /* XXX : not implemented */
2395 spr_register(env, SPR_MPC_BAR, "BAR",
2396 SPR_NOACCESS, SPR_NOACCESS,
2397 &spr_read_generic, &spr_write_generic,
2398 0x00000000);
2399 /* XXX : not implemented */
2400 spr_register(env, SPR_MPC_DPDR, "DPDR",
2401 SPR_NOACCESS, SPR_NOACCESS,
2402 &spr_read_generic, &spr_write_generic,
2403 0x00000000);
2404 /* XXX : not implemented */
2405 spr_register(env, SPR_MPC_IMMR, "IMMR",
2406 SPR_NOACCESS, SPR_NOACCESS,
2407 &spr_read_generic, &spr_write_generic,
2408 0x00000000);
2409 }
2410
2411 static void gen_spr_5xx (CPUPPCState *env)
2412 {
2413 /* XXX : not implemented */
2414 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2415 SPR_NOACCESS, SPR_NOACCESS,
2416 &spr_read_generic, &spr_write_generic,
2417 0x00000000);
2418 /* XXX : not implemented */
2419 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2420 SPR_NOACCESS, SPR_NOACCESS,
2421 &spr_read_generic, &spr_write_generic,
2422 0x00000000);
2423 /* XXX : not implemented */
2424 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2425 SPR_NOACCESS, SPR_NOACCESS,
2426 &spr_read_generic, &spr_write_generic,
2427 0x00000000);
2428 /* XXX : not implemented */
2429 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2430 SPR_NOACCESS, SPR_NOACCESS,
2431 &spr_read_generic, &spr_write_generic,
2432 0x00000000);
2433 /* XXX : not implemented */
2434 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2435 SPR_NOACCESS, SPR_NOACCESS,
2436 &spr_read_generic, &spr_write_generic,
2437 0x00000000);
2438 /* XXX : not implemented */
2439 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2440 SPR_NOACCESS, SPR_NOACCESS,
2441 &spr_read_generic, &spr_write_generic,
2442 0x00000000);
2443 /* XXX : not implemented */
2444 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2445 SPR_NOACCESS, SPR_NOACCESS,
2446 &spr_read_generic, &spr_write_generic,
2447 0x00000000);
2448 /* XXX : not implemented */
2449 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2450 SPR_NOACCESS, SPR_NOACCESS,
2451 &spr_read_generic, &spr_write_generic,
2452 0x00000000);
2453 /* XXX : not implemented */
2454 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2455 SPR_NOACCESS, SPR_NOACCESS,
2456 &spr_read_generic, &spr_write_generic,
2457 0x00000000);
2458 /* XXX : not implemented */
2459 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2460 SPR_NOACCESS, SPR_NOACCESS,
2461 &spr_read_generic, &spr_write_generic,
2462 0x00000000);
2463 /* XXX : not implemented */
2464 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2465 SPR_NOACCESS, SPR_NOACCESS,
2466 &spr_read_generic, &spr_write_generic,
2467 0x00000000);
2468 /* XXX : not implemented */
2469 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2470 SPR_NOACCESS, SPR_NOACCESS,
2471 &spr_read_generic, &spr_write_generic,
2472 0x00000000);
2473 /* XXX : not implemented */
2474 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2475 SPR_NOACCESS, SPR_NOACCESS,
2476 &spr_read_generic, &spr_write_generic,
2477 0x00000000);
2478 /* XXX : not implemented */
2479 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2480 SPR_NOACCESS, SPR_NOACCESS,
2481 &spr_read_generic, &spr_write_generic,
2482 0x00000000);
2483 /* XXX : not implemented */
2484 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2485 SPR_NOACCESS, SPR_NOACCESS,
2486 &spr_read_generic, &spr_write_generic,
2487 0x00000000);
2488 /* XXX : not implemented */
2489 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2490 SPR_NOACCESS, SPR_NOACCESS,
2491 &spr_read_generic, &spr_write_generic,
2492 0x00000000);
2493 /* XXX : not implemented */
2494 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2495 SPR_NOACCESS, SPR_NOACCESS,
2496 &spr_read_generic, &spr_write_generic,
2497 0x00000000);
2498 /* XXX : not implemented */
2499 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2500 SPR_NOACCESS, SPR_NOACCESS,
2501 &spr_read_generic, &spr_write_generic,
2502 0x00000000);
2503 /* XXX : not implemented */
2504 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2505 SPR_NOACCESS, SPR_NOACCESS,
2506 &spr_read_generic, &spr_write_generic,
2507 0x00000000);
2508 /* XXX : not implemented */
2509 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2510 SPR_NOACCESS, SPR_NOACCESS,
2511 &spr_read_generic, &spr_write_generic,
2512 0x00000000);
2513 /* XXX : not implemented */
2514 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2515 SPR_NOACCESS, SPR_NOACCESS,
2516 &spr_read_generic, &spr_write_generic,
2517 0x00000000);
2518 }
2519
2520 static void gen_spr_8xx (CPUPPCState *env)
2521 {
2522 /* XXX : not implemented */
2523 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2524 SPR_NOACCESS, SPR_NOACCESS,
2525 &spr_read_generic, &spr_write_generic,
2526 0x00000000);
2527 /* XXX : not implemented */
2528 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2529 SPR_NOACCESS, SPR_NOACCESS,
2530 &spr_read_generic, &spr_write_generic,
2531 0x00000000);
2532 /* XXX : not implemented */
2533 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2534 SPR_NOACCESS, SPR_NOACCESS,
2535 &spr_read_generic, &spr_write_generic,
2536 0x00000000);
2537 /* XXX : not implemented */
2538 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2539 SPR_NOACCESS, SPR_NOACCESS,
2540 &spr_read_generic, &spr_write_generic,
2541 0x00000000);
2542 /* XXX : not implemented */
2543 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2544 SPR_NOACCESS, SPR_NOACCESS,
2545 &spr_read_generic, &spr_write_generic,
2546 0x00000000);
2547 /* XXX : not implemented */
2548 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2549 SPR_NOACCESS, SPR_NOACCESS,
2550 &spr_read_generic, &spr_write_generic,
2551 0x00000000);
2552 /* XXX : not implemented */
2553 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2554 SPR_NOACCESS, SPR_NOACCESS,
2555 &spr_read_generic, &spr_write_generic,
2556 0x00000000);
2557 /* XXX : not implemented */
2558 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2559 SPR_NOACCESS, SPR_NOACCESS,
2560 &spr_read_generic, &spr_write_generic,
2561 0x00000000);
2562 /* XXX : not implemented */
2563 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2564 SPR_NOACCESS, SPR_NOACCESS,
2565 &spr_read_generic, &spr_write_generic,
2566 0x00000000);
2567 /* XXX : not implemented */
2568 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2569 SPR_NOACCESS, SPR_NOACCESS,
2570 &spr_read_generic, &spr_write_generic,
2571 0x00000000);
2572 /* XXX : not implemented */
2573 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2574 SPR_NOACCESS, SPR_NOACCESS,
2575 &spr_read_generic, &spr_write_generic,
2576 0x00000000);
2577 /* XXX : not implemented */
2578 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2579 SPR_NOACCESS, SPR_NOACCESS,
2580 &spr_read_generic, &spr_write_generic,
2581 0x00000000);
2582 /* XXX : not implemented */
2583 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2584 SPR_NOACCESS, SPR_NOACCESS,
2585 &spr_read_generic, &spr_write_generic,
2586 0x00000000);
2587 /* XXX : not implemented */
2588 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2589 SPR_NOACCESS, SPR_NOACCESS,
2590 &spr_read_generic, &spr_write_generic,
2591 0x00000000);
2592 /* XXX : not implemented */
2593 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2594 SPR_NOACCESS, SPR_NOACCESS,
2595 &spr_read_generic, &spr_write_generic,
2596 0x00000000);
2597 /* XXX : not implemented */
2598 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2599 SPR_NOACCESS, SPR_NOACCESS,
2600 &spr_read_generic, &spr_write_generic,
2601 0x00000000);
2602 /* XXX : not implemented */
2603 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2604 SPR_NOACCESS, SPR_NOACCESS,
2605 &spr_read_generic, &spr_write_generic,
2606 0x00000000);
2607 /* XXX : not implemented */
2608 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2609 SPR_NOACCESS, SPR_NOACCESS,
2610 &spr_read_generic, &spr_write_generic,
2611 0x00000000);
2612 /* XXX : not implemented */
2613 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2614 SPR_NOACCESS, SPR_NOACCESS,
2615 &spr_read_generic, &spr_write_generic,
2616 0x00000000);
2617 /* XXX : not implemented */
2618 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2619 SPR_NOACCESS, SPR_NOACCESS,
2620 &spr_read_generic, &spr_write_generic,
2621 0x00000000);
2622 /* XXX : not implemented */
2623 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2624 SPR_NOACCESS, SPR_NOACCESS,
2625 &spr_read_generic, &spr_write_generic,
2626 0x00000000);
2627 /* XXX : not implemented */
2628 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2629 SPR_NOACCESS, SPR_NOACCESS,
2630 &spr_read_generic, &spr_write_generic,
2631 0x00000000);
2632 /* XXX : not implemented */
2633 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2634 SPR_NOACCESS, SPR_NOACCESS,
2635 &spr_read_generic, &spr_write_generic,
2636 0x00000000);
2637 /* XXX : not implemented */
2638 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2639 SPR_NOACCESS, SPR_NOACCESS,
2640 &spr_read_generic, &spr_write_generic,
2641 0x00000000);
2642 /* XXX : not implemented */
2643 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2644 SPR_NOACCESS, SPR_NOACCESS,
2645 &spr_read_generic, &spr_write_generic,
2646 0x00000000);
2647 }
2648
2649 // XXX: TODO
2650 /*
2651 * AMR => SPR 29 (Power 2.04)
2652 * CTRL => SPR 136 (Power 2.04)
2653 * CTRL => SPR 152 (Power 2.04)
2654 * SCOMC => SPR 276 (64 bits ?)
2655 * SCOMD => SPR 277 (64 bits ?)
2656 * TBU40 => SPR 286 (Power 2.04 hypv)
2657 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2658 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2659 * HDSISR => SPR 306 (Power 2.04 hypv)
2660 * HDAR => SPR 307 (Power 2.04 hypv)
2661 * PURR => SPR 309 (Power 2.04 hypv)
2662 * HDEC => SPR 310 (Power 2.04 hypv)
2663 * HIOR => SPR 311 (hypv)
2664 * RMOR => SPR 312 (970)
2665 * HRMOR => SPR 313 (Power 2.04 hypv)
2666 * HSRR0 => SPR 314 (Power 2.04 hypv)
2667 * HSRR1 => SPR 315 (Power 2.04 hypv)
2668 * LPCR => SPR 316 (970)
2669 * LPIDR => SPR 317 (970)
2670 * EPR => SPR 702 (Power 2.04 emb)
2671 * perf => 768-783 (Power 2.04)
2672 * perf => 784-799 (Power 2.04)
2673 * PPR => SPR 896 (Power 2.04)
2674 * EPLC => SPR 947 (Power 2.04 emb)
2675 * EPSC => SPR 948 (Power 2.04 emb)
2676 * DABRX => 1015 (Power 2.04 hypv)
2677 * FPECR => SPR 1022 (?)
2678 * ... and more (thermal management, performance counters, ...)
2679 */
2680
2681 /*****************************************************************************/
2682 /* Exception vectors models */
2683 static void init_excp_4xx_real (CPUPPCState *env)
2684 {
2685 #if !defined(CONFIG_USER_ONLY)
2686 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2687 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2688 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2689 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2690 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2691 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2692 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2693 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2694 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2695 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2696 env->hreset_excp_prefix = 0x00000000UL;
2697 env->ivor_mask = 0x0000FFF0UL;
2698 env->ivpr_mask = 0xFFFF0000UL;
2699 /* Hardware reset vector */
2700 env->hreset_vector = 0xFFFFFFFCUL;
2701 #endif
2702 }
2703
2704 static void init_excp_4xx_softmmu (CPUPPCState *env)
2705 {
2706 #if !defined(CONFIG_USER_ONLY)
2707 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2708 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2709 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2710 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2711 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2712 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2713 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2714 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2715 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2716 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2717 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2718 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2719 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2720 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2721 env->hreset_excp_prefix = 0x00000000UL;
2722 env->ivor_mask = 0x0000FFF0UL;
2723 env->ivpr_mask = 0xFFFF0000UL;
2724 /* Hardware reset vector */
2725 env->hreset_vector = 0xFFFFFFFCUL;
2726 #endif
2727 }
2728
2729 static void init_excp_MPC5xx (CPUPPCState *env)
2730 {
2731 #if !defined(CONFIG_USER_ONLY)
2732 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2733 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2734 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2735 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2736 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2737 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2738 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2739 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2740 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2741 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2742 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2743 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2744 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2745 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2746 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2747 env->hreset_excp_prefix = 0x00000000UL;
2748 env->ivor_mask = 0x0000FFF0UL;
2749 env->ivpr_mask = 0xFFFF0000UL;
2750 /* Hardware reset vector */
2751 env->hreset_vector = 0xFFFFFFFCUL;
2752 #endif
2753 }
2754
2755 static void init_excp_MPC8xx (CPUPPCState *env)
2756 {
2757 #if !defined(CONFIG_USER_ONLY)
2758 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2759 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2760 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2761 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2762 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2763 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2764 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2765 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2766 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2767 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2768 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2769 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2770 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2771 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2772 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2773 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2774 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2775 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2776 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2777 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2778 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2779 env->hreset_excp_prefix = 0x00000000UL;
2780 env->ivor_mask = 0x0000FFF0UL;
2781 env->ivpr_mask = 0xFFFF0000UL;
2782 /* Hardware reset vector */
2783 env->hreset_vector = 0xFFFFFFFCUL;
2784 #endif
2785 }
2786
2787 static void init_excp_G2 (CPUPPCState *env)
2788 {
2789 #if !defined(CONFIG_USER_ONLY)
2790 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2791 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2792 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2793 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2794 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2795 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2796 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2797 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2798 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2799 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2800 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2801 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2802 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2803 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2804 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2805 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2806 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2807 env->hreset_excp_prefix = 0x00000000UL;
2808 /* Hardware reset vector */
2809 env->hreset_vector = 0xFFFFFFFCUL;
2810 #endif
2811 }
2812
2813 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2814 {
2815 #if !defined(CONFIG_USER_ONLY)
2816 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2817 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2818 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2819 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2820 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2821 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2822 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2823 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2824 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2825 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2826 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2827 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2828 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2829 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2830 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2831 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2832 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2833 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2834 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2835 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2836 env->hreset_excp_prefix = 0x00000000UL;
2837 env->ivor_mask = 0x0000FFF7UL;
2838 env->ivpr_mask = ivpr_mask;
2839 /* Hardware reset vector */
2840 env->hreset_vector = 0xFFFFFFFCUL;
2841 #endif
2842 }
2843
2844 static void init_excp_BookE (CPUPPCState *env)
2845 {
2846 #if !defined(CONFIG_USER_ONLY)
2847 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2848 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2849 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2850 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2851 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2852 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2853 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2854 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2855 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2856 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2857 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2858 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2859 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2860 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2861 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2862 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2863 env->hreset_excp_prefix = 0x00000000UL;
2864 env->ivor_mask = 0x0000FFE0UL;
2865 env->ivpr_mask = 0xFFFF0000UL;
2866 /* Hardware reset vector */
2867 env->hreset_vector = 0xFFFFFFFCUL;
2868 #endif
2869 }
2870
2871 static void init_excp_601 (CPUPPCState *env)
2872 {
2873 #if !defined(CONFIG_USER_ONLY)
2874 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2875 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2876 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2877 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2878 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2879 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2880 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2881 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2882 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2883 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2884 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2885 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2886 env->hreset_excp_prefix = 0xFFF00000UL;
2887 /* Hardware reset vector */
2888 env->hreset_vector = 0x00000100UL;
2889 #endif
2890 }
2891
2892 static void init_excp_602 (CPUPPCState *env)
2893 {
2894 #if !defined(CONFIG_USER_ONLY)
2895 /* XXX: exception prefix has a special behavior on 602 */
2896 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2897 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2898 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2899 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2900 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2901 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2902 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2903 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2904 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2905 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2906 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2907 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2908 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2909 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2910 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2911 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2912 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2913 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2914 env->hreset_excp_prefix = 0xFFF00000UL;
2915 /* Hardware reset vector */
2916 env->hreset_vector = 0xFFFFFFFCUL;
2917 #endif
2918 }
2919
2920 static void init_excp_603 (CPUPPCState *env)
2921 {
2922 #if !defined(CONFIG_USER_ONLY)
2923 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2924 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2925 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2926 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2927 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2928 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2929 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2930 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2931 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2932 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2933 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2934 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2935 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2936 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2937 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2938 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2939 env->hreset_excp_prefix = 0x00000000UL;
2940 /* Hardware reset vector */
2941 env->hreset_vector = 0xFFFFFFFCUL;
2942 #endif
2943 }
2944
2945 static void init_excp_604 (CPUPPCState *env)
2946 {
2947 #if !defined(CONFIG_USER_ONLY)
2948 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2949 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2950 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2951 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2952 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2953 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2954 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2955 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2956 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2957 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2958 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2959 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2960 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2961 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2962 env->hreset_excp_prefix = 0xFFF00000UL;
2963 /* Hardware reset vector */
2964 env->hreset_vector = 0x00000100UL;
2965 #endif
2966 }
2967
2968 #if defined(TARGET_PPC64)
2969 static void init_excp_620 (CPUPPCState *env)
2970 {
2971 #if !defined(CONFIG_USER_ONLY)
2972 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2973 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2974 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2975 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2976 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2977 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2978 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2979 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2980 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2981 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2982 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2983 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2984 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2985 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2986 env->hreset_excp_prefix = 0xFFF00000UL;
2987 /* Hardware reset vector */
2988 env->hreset_vector = 0x0000000000000100ULL;
2989 #endif
2990 }
2991 #endif /* defined(TARGET_PPC64) */
2992
2993 static void init_excp_7x0 (CPUPPCState *env)
2994 {
2995 #if !defined(CONFIG_USER_ONLY)
2996 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2997 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2998 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2999 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3000 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3001 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3002 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3003 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3004 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3005 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3006 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3007 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3008 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3009 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3010 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3011 env->hreset_excp_prefix = 0x00000000UL;
3012 /* Hardware reset vector */
3013 env->hreset_vector = 0xFFFFFFFCUL;
3014 #endif
3015 }
3016
3017 static void init_excp_750cl (CPUPPCState *env)
3018 {
3019 #if !defined(CONFIG_USER_ONLY)
3020 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3021 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3022 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3023 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3024 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3025 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3026 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3027 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3028 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3029 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3030 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3031 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3032 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3033 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3034 env->hreset_excp_prefix = 0x00000000UL;
3035 /* Hardware reset vector */
3036 env->hreset_vector = 0xFFFFFFFCUL;
3037 #endif
3038 }
3039
3040 static void init_excp_750cx (CPUPPCState *env)
3041 {
3042 #if !defined(CONFIG_USER_ONLY)
3043 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3044 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3045 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3046 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3047 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3048 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3049 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3050 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3051 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3052 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3053 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3054 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3055 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3056 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3057 env->hreset_excp_prefix = 0x00000000UL;
3058 /* Hardware reset vector */
3059 env->hreset_vector = 0xFFFFFFFCUL;
3060 #endif
3061 }
3062
3063 /* XXX: Check if this is correct */
3064 static void init_excp_7x5 (CPUPPCState *env)
3065 {
3066 #if !defined(CONFIG_USER_ONLY)
3067 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3068 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3069 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3070 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3071 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3072 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3073 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3074 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3075 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3076 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3077 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3078 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3079 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3080 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3081 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3082 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3083 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3084 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3085 env->hreset_excp_prefix = 0x00000000UL;
3086 /* Hardware reset vector */
3087 env->hreset_vector = 0xFFFFFFFCUL;
3088 #endif
3089 }
3090
3091 static void init_excp_7400 (CPUPPCState *env)
3092 {
3093 #if !defined(CONFIG_USER_ONLY)
3094 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3095 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3096 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3097 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3098 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3099 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3100 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3101 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3102 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3103 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3104 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3105 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3106 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3107 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3108 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3109 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3110 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3111 env->hreset_excp_prefix = 0x00000000UL;
3112 /* Hardware reset vector */
3113 env->hreset_vector = 0xFFFFFFFCUL;
3114 #endif
3115 }
3116
3117 static void init_excp_7450 (CPUPPCState *env)
3118 {
3119 #if !defined(CONFIG_USER_ONLY)
3120 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3121 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3122 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3123 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3124 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3125 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3126 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3127 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3128 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3129 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3130 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3131 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3132 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3133 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3134 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3135 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3136 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3137 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3138 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3139 env->hreset_excp_prefix = 0x00000000UL;
3140 /* Hardware reset vector */
3141 env->hreset_vector = 0xFFFFFFFCUL;
3142 #endif
3143 }
3144
3145 #if defined (TARGET_PPC64)
3146 static void init_excp_970 (CPUPPCState *env)
3147 {
3148 #if !defined(CONFIG_USER_ONLY)
3149 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3150 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3151 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3152 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3153 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3154 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3155 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3156 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3157 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3158 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3159 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3160 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3161 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3162 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3163 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3164 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3165 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3166 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3167 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3168 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3169 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
3170 /* Hardware reset vector */
3171 env->hreset_vector = 0x0000000000000100ULL;
3172 #endif
3173 }
3174
3175 static void init_excp_POWER7 (CPUPPCState *env)
3176 {
3177 #if !defined(CONFIG_USER_ONLY)
3178 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3179 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3180 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3181 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3182 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3183 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3184 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3185 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3186 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3187 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3188 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3189 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3190 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3191 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3192 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3193 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3194 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3195 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3196 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3197 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3198 env->hreset_excp_prefix = 0;
3199 /* Hardware reset vector */
3200 env->hreset_vector = 0x0000000000000100ULL;
3201 #endif
3202 }
3203 #endif
3204
3205 /*****************************************************************************/
3206 /* Power management enable checks */
3207 static int check_pow_none (CPUPPCState *env)
3208 {
3209 return 0;
3210 }
3211
3212 static int check_pow_nocheck (CPUPPCState *env)
3213 {
3214 return 1;
3215 }
3216
3217 static int check_pow_hid0 (CPUPPCState *env)
3218 {
3219 if (env->spr[SPR_HID0] & 0x00E00000)
3220 return 1;
3221
3222 return 0;
3223 }
3224
3225 static int check_pow_hid0_74xx (CPUPPCState *env)
3226 {
3227 if (env->spr[SPR_HID0] & 0x00600000)
3228 return 1;
3229
3230 return 0;
3231 }
3232
3233 /*****************************************************************************/
3234 /* PowerPC implementations definitions */
3235
3236 /* PowerPC 401 */
3237 #define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3238 PPC_WRTEE | PPC_DCR | \
3239 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3240 PPC_CACHE_DCBZ | \
3241 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3242 PPC_4xx_COMMON | PPC_40x_EXCP)
3243 #define POWERPC_INSNS2_401 (PPC_NONE)
3244 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
3245 #define POWERPC_MMU_401 (POWERPC_MMU_REAL)
3246 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3247 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
3248 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
3249 #define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3250 POWERPC_FLAG_BUS_CLK)
3251 #define check_pow_401 check_pow_nocheck
3252
3253 static void init_proc_401 (CPUPPCState *env)
3254 {
3255 gen_spr_40x(env);
3256 gen_spr_401_403(env);
3257 gen_spr_401(env);
3258 init_excp_4xx_real(env);
3259 env->dcache_line_size = 32;
3260 env->icache_line_size = 32;
3261 /* Allocate hardware IRQ controller */
3262 ppc40x_irq_init(env);
3263
3264 SET_FIT_PERIOD(12, 16, 20, 24);
3265 SET_WDT_PERIOD(16, 20, 24, 28);
3266 }
3267
3268 /* PowerPC 401x2 */
3269 #define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3270 PPC_DCR | PPC_WRTEE | \
3271 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3272 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3273 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3274 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3275 PPC_4xx_COMMON | PPC_40x_EXCP)
3276 #define POWERPC_INSNS2_401x2 (PPC_NONE)
3277 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3278 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3279 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3280 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
3281 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
3282 #define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3283 POWERPC_FLAG_BUS_CLK)
3284 #define check_pow_401x2 check_pow_nocheck
3285
3286 static void init_proc_401x2 (CPUPPCState *env)
3287 {
3288 gen_spr_40x(env);
3289 gen_spr_401_403(env);
3290 gen_spr_401x2(env);
3291 gen_spr_compress(env);
3292 /* Memory management */
3293 #if !defined(CONFIG_USER_ONLY)
3294 env->nb_tlb = 64;
3295 env->nb_ways = 1;
3296 env->id_tlbs = 0;
3297 env->tlb_type = TLB_EMB;
3298 #endif
3299 init_excp_4xx_softmmu(env);
3300 env->dcache_line_size = 32;
3301 env->icache_line_size = 32;
3302 /* Allocate hardware IRQ controller */
3303 ppc40x_irq_init(env);
3304
3305 SET_FIT_PERIOD(12, 16, 20, 24);
3306 SET_WDT_PERIOD(16, 20, 24, 28);
3307 }
3308
3309 /* PowerPC 401x3 */
3310 #define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3311 PPC_DCR | PPC_WRTEE | \
3312 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3313 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3314 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3315 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3316 PPC_4xx_COMMON | PPC_40x_EXCP)
3317 #define POWERPC_INSNS2_401x3 (PPC_NONE)
3318 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3319 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3320 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3321 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
3322 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
3323 #define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3324 POWERPC_FLAG_BUS_CLK)
3325 #define check_pow_401x3 check_pow_nocheck
3326
3327 __attribute__ (( unused ))
3328 static void init_proc_401x3 (CPUPPCState *env)
3329 {
3330 gen_spr_40x(env);
3331 gen_spr_401_403(env);
3332 gen_spr_401(env);
3333 gen_spr_401x2(env);
3334 gen_spr_compress(env);
3335 init_excp_4xx_softmmu(env);
3336 env->dcache_line_size = 32;
3337 env->icache_line_size = 32;
3338 /* Allocate hardware IRQ controller */
3339 ppc40x_irq_init(env);
3340
3341 SET_FIT_PERIOD(12, 16, 20, 24);
3342 SET_WDT_PERIOD(16, 20, 24, 28);
3343 }
3344
3345 /* IOP480 */
3346 #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3347 PPC_DCR | PPC_WRTEE | \
3348 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3349 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3350 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3351 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3352 PPC_4xx_COMMON | PPC_40x_EXCP)
3353 #define POWERPC_INSNS2_IOP480 (PPC_NONE)
3354 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3355 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3356 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3357 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
3358 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
3359 #define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3360 POWERPC_FLAG_BUS_CLK)
3361 #define check_pow_IOP480 check_pow_nocheck
3362
3363 static void init_proc_IOP480 (CPUPPCState *env)
3364 {
3365 gen_spr_40x(env);
3366 gen_spr_401_403(env);
3367 gen_spr_401x2(env);
3368 gen_spr_compress(env);
3369 /* Memory management */
3370 #if !defined(CONFIG_USER_ONLY)
3371 env->nb_tlb = 64;
3372 env->nb_ways = 1;
3373 env->id_tlbs = 0;
3374 env->tlb_type = TLB_EMB;
3375 #endif
3376 init_excp_4xx_softmmu(env);
3377 env->dcache_line_size = 32;
3378 env->icache_line_size = 32;
3379 /* Allocate hardware IRQ controller */
3380 ppc40x_irq_init(env);
3381
3382 SET_FIT_PERIOD(8, 12, 16, 20);
3383 SET_WDT_PERIOD(16, 20, 24, 28);
3384 }
3385
3386 /* PowerPC 403 */
3387 #define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3388 PPC_DCR | PPC_WRTEE | \
3389 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3390 PPC_CACHE_DCBZ | \
3391 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3392 PPC_4xx_COMMON | PPC_40x_EXCP)
3393 #define POWERPC_INSNS2_403 (PPC_NONE)
3394 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
3395 #define POWERPC_MMU_403 (POWERPC_MMU_REAL)
3396 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3397 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
3398 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
3399 #define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3400 POWERPC_FLAG_BUS_CLK)
3401 #define check_pow_403 check_pow_nocheck
3402
3403 static void init_proc_403 (CPUPPCState *env)
3404 {
3405 gen_spr_40x(env);
3406 gen_spr_401_403(env);
3407 gen_spr_403(env);
3408 gen_spr_403_real(env);
3409 init_excp_4xx_real(env);
3410 env->dcache_line_size = 32;
3411 env->icache_line_size = 32;
3412 /* Allocate hardware IRQ controller */
3413 ppc40x_irq_init(env);
3414
3415 SET_FIT_PERIOD(8, 12, 16, 20);
3416 SET_WDT_PERIOD(16, 20, 24, 28);
3417 }
3418
3419 /* PowerPC 403 GCX */
3420 #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3421 PPC_DCR | PPC_WRTEE | \
3422 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3423 PPC_CACHE_DCBZ | \
3424 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3425 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3426 PPC_4xx_COMMON | PPC_40x_EXCP)
3427 #define POWERPC_INSNS2_403GCX (PPC_NONE)
3428 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3429 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3430 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3431 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
3432 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
3433 #define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3434 POWERPC_FLAG_BUS_CLK)
3435 #define check_pow_403GCX check_pow_nocheck
3436
3437 static void init_proc_403GCX (CPUPPCState *env)
3438 {
3439 gen_spr_40x(env);
3440 gen_spr_401_403(env);
3441 gen_spr_403(env);
3442 gen_spr_403_real(env);
3443 gen_spr_403_mmu(env);
3444 /* Bus access control */
3445 /* not emulated, as QEMU never does speculative access */
3446 spr_register(env, SPR_40x_SGR, "SGR",
3447 SPR_NOACCESS, SPR_NOACCESS,
3448 &spr_read_generic, &spr_write_generic,
3449 0xFFFFFFFF);
3450 /* not emulated, as QEMU do not emulate caches */
3451 spr_register(env, SPR_40x_DCWR, "DCWR",
3452 SPR_NOACCESS, SPR_NOACCESS,
3453 &spr_read_generic, &spr_write_generic,
3454 0x00000000);
3455 /* Memory management */
3456 #if !defined(CONFIG_USER_ONLY)
3457 env->nb_tlb = 64;
3458 env->nb_ways = 1;
3459 env->id_tlbs = 0;
3460 env->tlb_type = TLB_EMB;
3461 #endif
3462 init_excp_4xx_softmmu(env);
3463 env->dcache_line_size = 32;
3464 env->icache_line_size = 32;
3465 /* Allocate hardware IRQ controller */
3466 ppc40x_irq_init(env);
3467
3468 SET_FIT_PERIOD(8, 12, 16, 20);
3469 SET_WDT_PERIOD(16, 20, 24, 28);
3470 }
3471
3472 /* PowerPC 405 */
3473 #define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3474 PPC_DCR | PPC_WRTEE | \
3475 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3476 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3477 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3478 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3479 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3480 #define POWERPC_INSNS2_405 (PPC_NONE)
3481 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
3482 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3483 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3484 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3485 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3486 #define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3487 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3488 #define check_pow_405 check_pow_nocheck
3489
3490 static void init_proc_405 (CPUPPCState *env)
3491 {
3492 /* Time base */
3493 gen_tbl(env);
3494 gen_spr_40x(env);
3495 gen_spr_405(env);
3496 /* Bus access control */
3497 /* not emulated, as QEMU never does speculative access */
3498 spr_register(env, SPR_40x_SGR, "SGR",
3499 SPR_NOACCESS, SPR_NOACCESS,
3500 &spr_read_generic, &spr_write_generic,
3501 0xFFFFFFFF);
3502 /* not emulated, as QEMU do not emulate caches */
3503 spr_register(env, SPR_40x_DCWR, "DCWR",
3504 SPR_NOACCESS, SPR_NOACCESS,
3505 &spr_read_generic, &spr_write_generic,
3506 0x00000000);
3507 /* Memory management */
3508 #if !defined(CONFIG_USER_ONLY)
3509 env->nb_tlb = 64;
3510 env->nb_ways = 1;
3511 env->id_tlbs = 0;
3512 env->tlb_type = TLB_EMB;
3513 #endif
3514 init_excp_4xx_softmmu(env);
3515 env->dcache_line_size = 32;
3516 env->icache_line_size = 32;
3517 /* Allocate hardware IRQ controller */
3518 ppc40x_irq_init(env);
3519
3520 SET_FIT_PERIOD(8, 12, 16, 20);
3521 SET_WDT_PERIOD(16, 20, 24, 28);
3522 }
3523
3524 /* PowerPC 440 EP */
3525 #define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3526 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3527 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3528 PPC_FLOAT_STFIWX | \
3529 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3530 PPC_CACHE | PPC_CACHE_ICBI | \
3531 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3532 PPC_MEM_TLBSYNC | PPC_MFTB | \
3533 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3534 PPC_440_SPEC)
3535 #define POWERPC_INSNS2_440EP (PPC_NONE)
3536 #define POWERPC_MSRM_440EP (0x000000000006FF30ULL)
3537 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3538 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3539 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3540 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3541 #define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3542 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3543 #define check_pow_440EP check_pow_nocheck
3544
3545 static void init_proc_440EP (CPUPPCState *env)
3546 {
3547 /* Time base */
3548 gen_tbl(env);
3549 gen_spr_BookE(env, 0x000000000000FFFFULL);
3550 gen_spr_440(env);
3551 gen_spr_usprgh(env);
3552 /* Processor identification */
3553 spr_register(env, SPR_BOOKE_PIR, "PIR",
3554 SPR_NOACCESS, SPR_NOACCESS,
3555 &spr_read_generic, &spr_write_pir,
3556 0x00000000);
3557 /* XXX : not implemented */
3558 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3559 SPR_NOACCESS, SPR_NOACCESS,
3560 &spr_read_generic, &spr_write_generic,
3561 0x00000000);
3562 /* XXX : not implemented */
3563 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3564 SPR_NOACCESS, SPR_NOACCESS,
3565 &spr_read_generic, &spr_write_generic,
3566 0x00000000);
3567 /* XXX : not implemented */
3568 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3569 SPR_NOACCESS, SPR_NOACCESS,
3570 &spr_read_generic, &spr_write_generic,
3571 0x00000000);
3572 /* XXX : not implemented */
3573 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3574 SPR_NOACCESS, SPR_NOACCESS,
3575 &spr_read_generic, &spr_write_generic,
3576 0x00000000);
3577 /* XXX : not implemented */
3578 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3579 SPR_NOACCESS, SPR_NOACCESS,
3580 &spr_read_generic, &spr_write_generic,
3581 0x00000000);
3582 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3583 SPR_NOACCESS, SPR_NOACCESS,
3584 &spr_read_generic, &spr_write_generic,
3585 0x00000000);
3586 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3587 SPR_NOACCESS, SPR_NOACCESS,
3588 &spr_read_generic, &spr_write_generic,
3589 0x00000000);
3590 /* XXX : not implemented */
3591 spr_register(env, SPR_440_CCR1, "CCR1",
3592 SPR_NOACCESS, SPR_NOACCESS,
3593 &spr_read_generic, &spr_write_generic,
3594 0x00000000);
3595 /* Memory management */
3596 #if !defined(CONFIG_USER_ONLY)
3597 env->nb_tlb = 64;
3598 env->nb_ways = 1;
3599 env->id_tlbs = 0;
3600 env->tlb_type = TLB_EMB;
3601 #endif
3602 init_excp_BookE(env);
3603 env->dcache_line_size = 32;
3604 env->icache_line_size = 32;
3605 ppc40x_irq_init(env);
3606
3607 SET_FIT_PERIOD(12, 16, 20, 24);
3608 SET_WDT_PERIOD(20, 24, 28, 32);
3609 }
3610
3611 /* PowerPC 440 GP */
3612 #define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3613 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3614 PPC_CACHE | PPC_CACHE_ICBI | \
3615 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3616 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \
3617 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3618 PPC_440_SPEC)
3619 #define POWERPC_INSNS2_440GP (PPC_NONE)
3620 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3621 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3622 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3623 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3624 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3625 #define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3626 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3627 #define check_pow_440GP check_pow_nocheck
3628
3629 __attribute__ (( unused ))
3630 static void init_proc_440GP (CPUPPCState *env)
3631 {
3632 /* Time base */
3633 gen_tbl(env);
3634 gen_spr_BookE(env, 0x000000000000FFFFULL);
3635 gen_spr_440(env);
3636 gen_spr_usprgh(env);
3637 /* Processor identification */
3638 spr_register(env, SPR_BOOKE_PIR, "PIR",
3639 SPR_NOACCESS, SPR_NOACCESS,
3640 &spr_read_generic, &spr_write_pir,
3641 0x00000000);
3642 /* XXX : not implemented */
3643 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3644 SPR_NOACCESS, SPR_NOACCESS,
3645 &spr_read_generic, &spr_write_generic,
3646 0x00000000);
3647 /* XXX : not implemented */
3648 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3649 SPR_NOACCESS, SPR_NOACCESS,
3650 &spr_read_generic, &spr_write_generic,
3651 0x00000000);
3652 /* XXX : not implemented */
3653 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3654 SPR_NOACCESS, SPR_NOACCESS,
3655 &spr_read_generic, &spr_write_generic,
3656 0x00000000);
3657 /* XXX : not implemented */
3658 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3659 SPR_NOACCESS, SPR_NOACCESS,
3660 &spr_read_generic, &spr_write_generic,
3661 0x00000000);
3662 /* Memory management */
3663 #if !defined(CONFIG_USER_ONLY)
3664 env->nb_tlb = 64;
3665 env->nb_ways = 1;
3666 env->id_tlbs = 0;
3667 env->tlb_type = TLB_EMB;
3668 #endif
3669 init_excp_BookE(env);
3670 env->dcache_line_size = 32;
3671 env->icache_line_size = 32;
3672 /* XXX: TODO: allocate internal IRQ controller */
3673
3674 SET_FIT_PERIOD(12, 16, 20, 24);
3675 SET_WDT_PERIOD(20, 24, 28, 32);
3676 }
3677
3678 /* PowerPC 440x4 */
3679 #define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3680 PPC_DCR | PPC_WRTEE | \
3681 PPC_CACHE | PPC_CACHE_ICBI | \
3682 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3683 PPC_MEM_TLBSYNC | PPC_MFTB | \
3684 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3685 PPC_440_SPEC)
3686 #define POWERPC_INSNS2_440x4 (PPC_NONE)
3687 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3688 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3689 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3690 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3691 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3692 #define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3693 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3694 #define check_pow_440x4 check_pow_nocheck
3695
3696 __attribute__ (( unused ))
3697 static void init_proc_440x4 (CPUPPCState *env)
3698 {
3699 /* Time base */
3700 gen_tbl(env);
3701 gen_spr_BookE(env, 0x000000000000FFFFULL);
3702 gen_spr_440(env);
3703 gen_spr_usprgh(env);
3704 /* Processor identification */
3705 spr_register(env, SPR_BOOKE_PIR, "PIR",
3706 SPR_NOACCESS, SPR_NOACCESS,
3707 &spr_read_generic, &spr_write_pir,
3708 0x00000000);
3709 /* XXX : not implemented */
3710 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3711 SPR_NOACCESS, SPR_NOACCESS,
3712 &spr_read_generic, &spr_write_generic,
3713 0x00000000);
3714 /* XXX : not implemented */
3715 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3716 SPR_NOACCESS, SPR_NOACCESS,
3717 &spr_read_generic, &spr_write_generic,
3718 0x00000000);
3719 /* XXX : not implemented */
3720 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3721 SPR_NOACCESS, SPR_NOACCESS,
3722 &spr_read_generic, &spr_write_generic,
3723 0x00000000);
3724 /* XXX : not implemented */
3725 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3726 SPR_NOACCESS, SPR_NOACCESS,
3727 &spr_read_generic, &spr_write_generic,
3728 0x00000000);
3729 /* Memory management */
3730 #if !defined(CONFIG_USER_ONLY)
3731 env->nb_tlb = 64;
3732 env->nb_ways = 1;
3733 env->id_tlbs = 0;
3734 env->tlb_type = TLB_EMB;
3735 #endif
3736 init_excp_BookE(env);
3737 env->dcache_line_size = 32;
3738 env->icache_line_size = 32;
3739 /* XXX: TODO: allocate internal IRQ controller */
3740
3741 SET_FIT_PERIOD(12, 16, 20, 24);
3742 SET_WDT_PERIOD(20, 24, 28, 32);
3743 }
3744
3745 /* PowerPC 440x5 */
3746 #define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3747 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3748 PPC_CACHE | PPC_CACHE_ICBI | \
3749 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3750 PPC_MEM_TLBSYNC | PPC_MFTB | \
3751 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3752 PPC_440_SPEC)
3753 #define POWERPC_INSNS2_440x5 (PPC_NONE)
3754 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3755 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3756 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3757 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3758 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3759 #define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3760 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3761 #define check_pow_440x5 check_pow_nocheck
3762
3763 static void init_proc_440x5 (CPUPPCState *env)
3764 {
3765 /* Time base */
3766 gen_tbl(env);
3767 gen_spr_BookE(env, 0x000000000000FFFFULL);
3768 gen_spr_440(env);
3769 gen_spr_usprgh(env);
3770 /* Processor identification */
3771 spr_register(env, SPR_BOOKE_PIR, "PIR",
3772 SPR_NOACCESS, SPR_NOACCESS,
3773 &spr_read_generic, &spr_write_pir,
3774 0x00000000);
3775 /* XXX : not implemented */
3776 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3777 SPR_NOACCESS, SPR_NOACCESS,
3778 &spr_read_generic, &spr_write_generic,
3779 0x00000000);
3780 /* XXX : not implemented */
3781 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3782 SPR_NOACCESS, SPR_NOACCESS,
3783 &spr_read_generic, &spr_write_generic,
3784 0x00000000);
3785 /* XXX : not implemented */
3786 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3787 SPR_NOACCESS, SPR_NOACCESS,
3788 &spr_read_generic, &spr_write_generic,
3789 0x00000000);
3790 /* XXX : not implemented */
3791 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3792 SPR_NOACCESS, SPR_NOACCESS,
3793 &spr_read_generic, &spr_write_generic,
3794 0x00000000);
3795 /* XXX : not implemented */
3796 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3797 SPR_NOACCESS, SPR_NOACCESS,
3798 &spr_read_generic, &spr_write_generic,
3799 0x00000000);
3800 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3801 SPR_NOACCESS, SPR_NOACCESS,
3802 &spr_read_generic, &spr_write_generic,
3803 0x00000000);
3804 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3805 SPR_NOACCESS, SPR_NOACCESS,
3806 &spr_read_generic, &spr_write_generic,
3807 0x00000000);
3808 /* XXX : not implemented */
3809 spr_register(env, SPR_440_CCR1, "CCR1",
3810 SPR_NOACCESS, SPR_NOACCESS,
3811 &spr_read_generic, &spr_write_generic,
3812 0x00000000);
3813 /* Memory management */
3814 #if !defined(CONFIG_USER_ONLY)
3815 env->nb_tlb = 64;
3816 env->nb_ways = 1;
3817 env->id_tlbs = 0;
3818 env->tlb_type = TLB_EMB;
3819 #endif
3820 init_excp_BookE(env);
3821 env->dcache_line_size = 32;
3822 env->icache_line_size = 32;
3823 ppc40x_irq_init(env);
3824
3825 SET_FIT_PERIOD(12, 16, 20, 24);
3826 SET_WDT_PERIOD(20, 24, 28, 32);
3827 }
3828
3829 /* PowerPC 460 (guessed) */
3830 #define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
3831 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3832 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | \
3833 PPC_CACHE | PPC_CACHE_ICBI | \
3834 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3835 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3836 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3837 PPC_440_SPEC)
3838 #define POWERPC_INSNS2_460 (PPC_NONE)
3839 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3840 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3841 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3842 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3843 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3844 #define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3845 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3846 #define check_pow_460 check_pow_nocheck
3847
3848 __attribute__ (( unused ))
3849 static void init_proc_460 (CPUPPCState *env)
3850 {
3851 /* Time base */
3852 gen_tbl(env);
3853 gen_spr_BookE(env, 0x000000000000FFFFULL);
3854 gen_spr_440(env);
3855 gen_spr_usprgh(env);
3856 /* Processor identification */
3857 spr_register(env, SPR_BOOKE_PIR, "PIR",
3858 SPR_NOACCESS, SPR_NOACCESS,
3859 &spr_read_generic, &spr_write_pir,
3860 0x00000000);
3861 /* XXX : not implemented */
3862 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3863 SPR_NOACCESS, SPR_NOACCESS,
3864 &spr_read_generic, &spr_write_generic,
3865 0x00000000);
3866 /* XXX : not implemented */
3867 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3868 SPR_NOACCESS, SPR_NOACCESS,
3869 &spr_read_generic, &spr_write_generic,
3870 0x00000000);
3871 /* XXX : not implemented */
3872 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3873 SPR_NOACCESS, SPR_NOACCESS,
3874 &spr_read_generic, &spr_write_generic,
3875 0x00000000);
3876 /* XXX : not implemented */
3877 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3878 SPR_NOACCESS, SPR_NOACCESS,
3879 &spr_read_generic, &spr_write_generic,
3880 0x00000000);
3881 /* XXX : not implemented */
3882 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3883 SPR_NOACCESS, SPR_NOACCESS,
3884 &spr_read_generic, &spr_write_generic,
3885 0x00000000);
3886 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3887 SPR_NOACCESS, SPR_NOACCESS,
3888 &spr_read_generic, &spr_write_generic,
3889 0x00000000);
3890 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3891 SPR_NOACCESS, SPR_NOACCESS,
3892 &spr_read_generic, &spr_write_generic,
3893 0x00000000);
3894 /* XXX : not implemented */
3895 spr_register(env, SPR_440_CCR1, "CCR1",
3896 SPR_NOACCESS, SPR_NOACCESS,
3897 &spr_read_generic, &spr_write_generic,
3898 0x00000000);
3899 /* XXX : not implemented */
3900 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3901 &spr_read_generic, &spr_write_generic,
3902 &spr_read_generic, &spr_write_generic,
3903 0x00000000);
3904 /* Memory management */
3905 #if !defined(CONFIG_USER_ONLY)
3906 env->nb_tlb = 64;
3907 env->nb_ways = 1;
3908 env->id_tlbs = 0;
3909 env->tlb_type = TLB_EMB;
3910 #endif
3911 init_excp_BookE(env);
3912 env->dcache_line_size = 32;
3913 env->icache_line_size = 32;
3914 /* XXX: TODO: allocate internal IRQ controller */
3915
3916 SET_FIT_PERIOD(12, 16, 20, 24);
3917 SET_WDT_PERIOD(20, 24, 28, 32);
3918 }
3919
3920 /* PowerPC 460F (guessed) */
3921 #define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3922 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3923 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3924 PPC_FLOAT_STFIWX | PPC_MFTB | \
3925 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3926 PPC_WRTEE | PPC_MFAPIDI | \
3927 PPC_CACHE | PPC_CACHE_ICBI | \
3928 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3929 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3930 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3931 PPC_440_SPEC)
3932 #define POWERPC_INSNS2_460F (PPC_NONE)
3933 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3934 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3935 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3936 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3937 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3938 #define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3939 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3940 #define check_pow_460F check_pow_nocheck
3941
3942 __attribute__ (( unused ))
3943 static void init_proc_460F (CPUPPCState *env)
3944 {
3945 /* Time base */
3946 gen_tbl(env);
3947 gen_spr_BookE(env, 0x000000000000FFFFULL);
3948 gen_spr_440(env);
3949 gen_spr_usprgh(env);
3950 /* Processor identification */
3951 spr_register(env, SPR_BOOKE_PIR, "PIR",
3952 SPR_NOACCESS, SPR_NOACCESS,
3953 &spr_read_generic, &spr_write_pir,
3954 0x00000000);
3955 /* XXX : not implemented */
3956 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3957 SPR_NOACCESS, SPR_NOACCESS,
3958 &spr_read_generic, &spr_write_generic,
3959 0x00000000);
3960 /* XXX : not implemented */
3961 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3962 SPR_NOACCESS, SPR_NOACCESS,
3963 &spr_read_generic, &spr_write_generic,
3964 0x00000000);
3965 /* XXX : not implemented */
3966 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3967 SPR_NOACCESS, SPR_NOACCESS,
3968 &spr_read_generic, &spr_write_generic,
3969 0x00000000);
3970 /* XXX : not implemented */
3971 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3972 SPR_NOACCESS, SPR_NOACCESS,
3973 &spr_read_generic, &spr_write_generic,
3974 0x00000000);
3975 /* XXX : not implemented */
3976 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3977 SPR_NOACCESS, SPR_NOACCESS,
3978 &spr_read_generic, &spr_write_generic,
3979 0x00000000);
3980 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3981 SPR_NOACCESS, SPR_NOACCESS,
3982 &spr_read_generic, &spr_write_generic,
3983 0x00000000);
3984 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3985 SPR_NOACCESS, SPR_NOACCESS,
3986 &spr_read_generic, &spr_write_generic,
3987 0x00000000);
3988 /* XXX : not implemented */
3989 spr_register(env, SPR_440_CCR1, "CCR1",
3990 SPR_NOACCESS, SPR_NOACCESS,
3991 &spr_read_generic, &spr_write_generic,
3992 0x00000000);
3993 /* XXX : not implemented */
3994 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3995 &spr_read_generic, &spr_write_generic,
3996 &spr_read_generic, &spr_write_generic,
3997 0x00000000);
3998 /* Memory management */
3999 #if !defined(CONFIG_USER_ONLY)
4000 env->nb_tlb = 64;
4001 env->nb_ways = 1;
4002 env->id_tlbs = 0;
4003 env->tlb_type = TLB_EMB;
4004 #endif
4005 init_excp_BookE(env);
4006 env->dcache_line_size = 32;
4007 env->icache_line_size = 32;
4008 /* XXX: TODO: allocate internal IRQ controller */
4009
4010 SET_FIT_PERIOD(12, 16, 20, 24);
4011 SET_WDT_PERIOD(20, 24, 28, 32);
4012 }
4013
4014 /* Freescale 5xx cores (aka RCPU) */
4015 #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
4016 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4017 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
4018 PPC_MFTB)
4019 #define POWERPC_INSNS2_MPC5xx (PPC_NONE)
4020 #define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
4021 #define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
4022 #define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
4023 #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
4024 #define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
4025 #define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4026 POWERPC_FLAG_BUS_CLK)
4027 #define check_pow_MPC5xx check_pow_none
4028
4029 __attribute__ (( unused ))
4030 static void init_proc_MPC5xx (CPUPPCState *env)
4031 {
4032 /* Time base */
4033 gen_tbl(env);
4034 gen_spr_5xx_8xx(env);
4035 gen_spr_5xx(env);
4036 init_excp_MPC5xx(env);
4037 env->dcache_line_size = 32;
4038 env->icache_line_size = 32;
4039 /* XXX: TODO: allocate internal IRQ controller */
4040 }
4041
4042 /* Freescale 8xx cores (aka PowerQUICC) */
4043 #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
4044 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4045 PPC_CACHE_ICBI | PPC_MFTB)
4046 #define POWERPC_INSNS2_MPC8xx (PPC_NONE)
4047 #define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
4048 #define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
4049 #define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
4050 #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
4051 #define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4052 #define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4053 POWERPC_FLAG_BUS_CLK)
4054 #define check_pow_MPC8xx check_pow_none
4055
4056 __attribute__ (( unused ))
4057 static void init_proc_MPC8xx (CPUPPCState *env)
4058 {
4059 /* Time base */
4060 gen_tbl(env);
4061 gen_spr_5xx_8xx(env);
4062 gen_spr_8xx(env);
4063 init_excp_MPC8xx(env);
4064 env->dcache_line_size = 32;
4065 env->icache_line_size = 32;
4066 /* XXX: TODO: allocate internal IRQ controller */
4067 }
4068
4069 /* Freescale 82xx cores (aka PowerQUICC-II) */
4070 /* PowerPC G2 */
4071 #define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4072 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4073 PPC_FLOAT_STFIWX | \
4074 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4075 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4076 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4077 PPC_SEGMENT | PPC_EXTERN)
4078 #define POWERPC_INSNS2_G2 (PPC_NONE)
4079 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
4080 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
4081 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
4082 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
4083 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
4084 #define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4085 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4086 #define check_pow_G2 check_pow_hid0
4087
4088 static void init_proc_G2 (CPUPPCState *env)
4089 {
4090 gen_spr_ne_601(env);
4091 gen_spr_G2_755(env);
4092 gen_spr_G2(env);
4093 /* Time base */
4094 gen_tbl(env);
4095 /* External access control */
4096 /* XXX : not implemented */
4097 spr_register(env, SPR_EAR, "EAR",
4098 SPR_NOACCESS, SPR_NOACCESS,
4099 &spr_read_generic, &spr_write_generic,
4100 0x00000000);
4101 /* Hardware implementation register */
4102 /* XXX : not implemented */
4103 spr_register(env, SPR_HID0, "HID0",
4104 SPR_NOACCESS, SPR_NOACCESS,
4105 &spr_read_generic, &spr_write_generic,
4106 0x00000000);
4107 /* XXX : not implemented */
4108 spr_register(env, SPR_HID1, "HID1",
4109 SPR_NOACCESS, SPR_NOACCESS,
4110 &spr_read_generic, &spr_write_generic,
4111 0x00000000);
4112 /* XXX : not implemented */
4113 spr_register(env, SPR_HID2, "HID2",
4114 SPR_NOACCESS, SPR_NOACCESS,
4115 &spr_read_generic, &spr_write_generic,
4116 0x00000000);
4117 /* Memory management */
4118 gen_low_BATs(env);
4119 gen_high_BATs(env);
4120 gen_6xx_7xx_soft_tlb(env, 64, 2);
4121 init_excp_G2(env);
4122 env->dcache_line_size = 32;
4123 env->icache_line_size = 32;
4124 /* Allocate hardware IRQ controller */
4125 ppc6xx_irq_init(env);
4126 }
4127
4128 /* PowerPC G2LE */
4129 #define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4130 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4131 PPC_FLOAT_STFIWX | \
4132 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4133 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4134 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4135 PPC_SEGMENT | PPC_EXTERN)
4136 #define POWERPC_INSNS2_G2LE (PPC_NONE)
4137 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
4138 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
4139 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
4140 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
4141 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
4142 #define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4143 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4144 #define check_pow_G2LE check_pow_hid0
4145
4146 static void init_proc_G2LE (CPUPPCState *env)
4147 {
4148 gen_spr_ne_601(env);
4149 gen_spr_G2_755(env);
4150 gen_spr_G2(env);
4151 /* Time base */
4152 gen_tbl(env);
4153 /* External access control */
4154 /* XXX : not implemented */
4155 spr_register(env, SPR_EAR, "EAR",
4156 SPR_NOACCESS, SPR_NOACCESS,
4157 &spr_read_generic, &spr_write_generic,
4158 0x00000000);
4159 /* Hardware implementation register */
4160 /* XXX : not implemented */
4161 spr_register(env, SPR_HID0, "HID0",
4162 SPR_NOACCESS, SPR_NOACCESS,
4163 &spr_read_generic, &spr_write_generic,
4164 0x00000000);
4165 /* XXX : not implemented */
4166 spr_register(env, SPR_HID1, "HID1",
4167 SPR_NOACCESS, SPR_NOACCESS,
4168 &spr_read_generic, &spr_write_generic,
4169 0x00000000);
4170 /* XXX : not implemented */
4171 spr_register(env, SPR_HID2, "HID2",
4172 SPR_NOACCESS, SPR_NOACCESS,
4173 &spr_read_generic, &spr_write_generic,
4174 0x00000000);
4175 /* Memory management */
4176 gen_low_BATs(env);
4177 gen_high_BATs(env);
4178 gen_6xx_7xx_soft_tlb(env, 64, 2);
4179 init_excp_G2(env);
4180 env->dcache_line_size = 32;
4181 env->icache_line_size = 32;
4182 /* Allocate hardware IRQ controller */
4183 ppc6xx_irq_init(env);
4184 }
4185
4186 /* e200 core */
4187 /* XXX: unimplemented instructions:
4188 * dcblc
4189 * dcbtlst
4190 * dcbtstls
4191 * icblc
4192 * icbtls
4193 * tlbivax
4194 * all SPE multiply-accumulate instructions
4195 */
4196 #define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
4197 PPC_SPE | PPC_SPE_SINGLE | \
4198 PPC_WRTEE | PPC_RFDI | \
4199 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4200 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4201 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4202 PPC_BOOKE)
4203 #define POWERPC_INSNS2_e200 (PPC_NONE)
4204 #define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
4205 #define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE206)
4206 #define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
4207 #define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
4208 #define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
4209 #define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4210 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4211 POWERPC_FLAG_BUS_CLK)
4212 #define check_pow_e200 check_pow_hid0
4213
4214 __attribute__ (( unused ))
4215 static void init_proc_e200 (CPUPPCState *env)
4216 {
4217 /* Time base */
4218 gen_tbl(env);
4219 gen_spr_BookE(env, 0x000000070000FFFFULL);
4220 /* XXX : not implemented */
4221 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4222 &spr_read_spefscr, &spr_write_spefscr,
4223 &spr_read_spefscr, &spr_write_spefscr,
4224 0x00000000);
4225 /* Memory management */
4226 gen_spr_BookE206(env, 0x0000005D, NULL);
4227 /* XXX : not implemented */
4228 spr_register(env, SPR_HID0, "HID0",
4229 SPR_NOACCESS, SPR_NOACCESS,
4230 &spr_read_generic, &spr_write_generic,
4231 0x00000000);
4232 /* XXX : not implemented */
4233 spr_register(env, SPR_HID1, "HID1",
4234 SPR_NOACCESS, SPR_NOACCESS,
4235 &spr_read_generic, &spr_write_generic,
4236 0x00000000);
4237 /* XXX : not implemented */
4238 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4239 SPR_NOACCESS, SPR_NOACCESS,
4240 &spr_read_generic, &spr_write_generic,
4241 0x00000000);
4242 /* XXX : not implemented */
4243 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4244 SPR_NOACCESS, SPR_NOACCESS,
4245 &spr_read_generic, &spr_write_generic,
4246 0x00000000);
4247 /* XXX : not implemented */
4248 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4249 SPR_NOACCESS, SPR_NOACCESS,
4250 &spr_read_generic, &spr_write_generic,
4251 0x00000000);
4252 /* XXX : not implemented */
4253 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4254 SPR_NOACCESS, SPR_NOACCESS,
4255 &spr_read_generic, &spr_write_generic,
4256 0x00000000);
4257 /* XXX : not implemented */
4258 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4259 SPR_NOACCESS, SPR_NOACCESS,
4260 &spr_read_generic, &spr_write_generic,
4261 0x00000000);
4262 /* XXX : not implemented */
4263 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4264 SPR_NOACCESS, SPR_NOACCESS,
4265 &spr_read_generic, &spr_write_generic,
4266 0x00000000);
4267 /* XXX : not implemented */
4268 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4269 SPR_NOACCESS, SPR_NOACCESS,
4270 &spr_read_generic, &spr_write_generic,
4271 0x00000000);
4272 /* XXX : not implemented */
4273 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4274 SPR_NOACCESS, SPR_NOACCESS,
4275 &spr_read_generic, &spr_write_generic,
4276 0x00000000);
4277 /* XXX : not implemented */
4278 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4279 SPR_NOACCESS, SPR_NOACCESS,
4280 &spr_read_generic, &spr_write_generic,
4281 0x00000000);
4282 /* XXX : not implemented */
4283 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4284 SPR_NOACCESS, SPR_NOACCESS,
4285 &spr_read_generic, &spr_write_generic,
4286 0x00000000);
4287 /* XXX : not implemented */
4288 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4289 SPR_NOACCESS, SPR_NOACCESS,
4290 &spr_read_generic, &spr_write_generic,
4291 0x00000000);
4292 /* XXX : not implemented */
4293 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4294 SPR_NOACCESS, SPR_NOACCESS,
4295 &spr_read_generic, &spr_write_generic,
4296 0x00000000);
4297 /* XXX : not implemented */
4298 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4299 SPR_NOACCESS, SPR_NOACCESS,
4300 &spr_read_generic, &spr_write_generic,
4301 0x00000000); /* TOFIX */
4302 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4303 SPR_NOACCESS, SPR_NOACCESS,
4304 &spr_read_generic, &spr_write_generic,
4305 0x00000000);
4306 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4307 SPR_NOACCESS, SPR_NOACCESS,
4308 &spr_read_generic, &spr_write_generic,
4309 0x00000000);
4310 #if !defined(CONFIG_USER_ONLY)
4311 env->nb_tlb = 64;
4312 env->nb_ways = 1;
4313 env->id_tlbs = 0;
4314 env->tlb_type = TLB_EMB;
4315 #endif
4316 init_excp_e200(env, 0xFFFF0000UL);
4317 env->dcache_line_size = 32;
4318 env->icache_line_size = 32;
4319 /* XXX: TODO: allocate internal IRQ controller */
4320 }
4321
4322 /* e300 core */
4323 #define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4324 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4325 PPC_FLOAT_STFIWX | \
4326 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4327 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4328 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4329 PPC_SEGMENT | PPC_EXTERN)
4330 #define POWERPC_INSNS2_e300 (PPC_NONE)
4331 #define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4332 #define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4333 #define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4334 #define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4335 #define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4336 #define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4337 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4338 #define check_pow_e300 check_pow_hid0
4339
4340 __attribute__ (( unused ))
4341 static void init_proc_e300 (CPUPPCState *env)
4342 {
4343 gen_spr_ne_601(env);
4344 gen_spr_603(env);
4345 /* Time base */
4346 gen_tbl(env);
4347 /* hardware implementation registers */
4348 /* XXX : not implemented */
4349 spr_register(env, SPR_HID0, "HID0",
4350 SPR_NOACCESS, SPR_NOACCESS,
4351 &spr_read_generic, &spr_write_generic,
4352 0x00000000);
4353 /* XXX : not implemented */
4354 spr_register(env, SPR_HID1, "HID1",
4355 SPR_NOACCESS, SPR_NOACCESS,
4356 &spr_read_generic, &spr_write_generic,
4357 0x00000000);
4358 /* XXX : not implemented */
4359 spr_register(env, SPR_HID2, "HID2",
4360 SPR_NOACCESS, SPR_NOACCESS,
4361 &spr_read_generic, &spr_write_generic,
4362 0x00000000);
4363 /* Memory management */
4364 gen_low_BATs(env);
4365 gen_high_BATs(env);
4366 gen_6xx_7xx_soft_tlb(env, 64, 2);
4367 init_excp_603(env);
4368 env->dcache_line_size = 32;
4369 env->icache_line_size = 32;
4370 /* Allocate hardware IRQ controller */
4371 ppc6xx_irq_init(env);
4372 }
4373
4374 /* e500v1 core */
4375 #define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
4376 PPC_SPE | PPC_SPE_SINGLE | \
4377 PPC_WRTEE | PPC_RFDI | \
4378 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4379 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4380 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
4381 #define POWERPC_INSNS2_e500v1 (PPC2_BOOKE206)
4382 #define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
4383 #define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206)
4384 #define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4385 #define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4386 #define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4387 #define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4388 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4389 POWERPC_FLAG_BUS_CLK)
4390 #define check_pow_e500v1 check_pow_hid0
4391 #define init_proc_e500v1 init_proc_e500v1
4392
4393 /* e500v2 core */
4394 #define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
4395 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
4396 PPC_WRTEE | PPC_RFDI | \
4397 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4398 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4399 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
4400 #define POWERPC_INSNS2_e500v2 (PPC2_BOOKE206)
4401 #define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
4402 #define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206)
4403 #define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4404 #define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4405 #define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4406 #define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4407 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4408 POWERPC_FLAG_BUS_CLK)
4409 #define check_pow_e500v2 check_pow_hid0
4410 #define init_proc_e500v2 init_proc_e500v2
4411
4412 /* e500mc core */
4413 #define POWERPC_INSNS_e500mc (PPC_INSNS_BASE | PPC_ISEL | \
4414 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | \
4415 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4416 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4417 PPC_FLOAT | PPC_FLOAT_FRES | \
4418 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
4419 PPC_FLOAT_STFIWX | PPC_WAIT | \
4420 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
4421 #define POWERPC_INSNS2_e500mc (PPC2_BOOKE206 | PPC2_PRCNTL)
4422 #define POWERPC_MSRM_e500mc (0x000000001402FB36ULL)
4423 #define POWERPC_MMU_e500mc (POWERPC_MMU_BOOKE206)
4424 #define POWERPC_EXCP_e500mc (POWERPC_EXCP_BOOKE)
4425 #define POWERPC_INPUT_e500mc (PPC_FLAGS_INPUT_BookE)
4426 /* Fixme: figure out the correct flag for e500mc */
4427 #define POWERPC_BFDM_e500mc (bfd_mach_ppc_e500)
4428 #define POWERPC_FLAG_e500mc (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
4429 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4430 #define check_pow_e500mc check_pow_none
4431 #define init_proc_e500mc init_proc_e500mc
4432
4433 /* e5500 core */
4434 #define POWERPC_INSNS_e5500 (PPC_INSNS_BASE | PPC_ISEL | \
4435 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | \
4436 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4437 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4438 PPC_FLOAT | PPC_FLOAT_FRES | \
4439 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
4440 PPC_FLOAT_STFIWX | PPC_WAIT | \
4441 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | \
4442 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD)
4443 #define POWERPC_INSNS2_e5500 (PPC2_BOOKE206 | PPC2_PRCNTL)
4444 #define POWERPC_MSRM_e5500 (0x000000009402FB36ULL)
4445 #define POWERPC_MMU_e5500 (POWERPC_MMU_BOOKE206)
4446 #define POWERPC_EXCP_e5500 (POWERPC_EXCP_BOOKE)
4447 #define POWERPC_INPUT_e5500 (PPC_FLAGS_INPUT_BookE)
4448 /* Fixme: figure out the correct flag for e5500 */
4449 #define POWERPC_BFDM_e5500 (bfd_mach_ppc_e500)
4450 #define POWERPC_FLAG_e5500 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
4451 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4452 #define check_pow_e5500 check_pow_none
4453 #define init_proc_e5500 init_proc_e5500
4454
4455 #if !defined(CONFIG_USER_ONLY)
4456 static void spr_write_mas73(void *opaque, int sprn, int gprn)
4457 {
4458 TCGv val = tcg_temp_new();
4459 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4460 gen_store_spr(SPR_BOOKE_MAS3, val);
4461 tcg_gen_shri_tl(val, gprn, 32);
4462 gen_store_spr(SPR_BOOKE_MAS7, val);
4463 tcg_temp_free(val);
4464 }
4465
4466 static void spr_read_mas73(void *opaque, int gprn, int sprn)
4467 {
4468 TCGv mas7 = tcg_temp_new();
4469 TCGv mas3 = tcg_temp_new();
4470 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4471 tcg_gen_shli_tl(mas7, mas7, 32);
4472 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4473 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4474 tcg_temp_free(mas3);
4475 tcg_temp_free(mas7);
4476 }
4477
4478 static void spr_load_epr(void *opaque, int gprn, int sprn)
4479 {
4480 gen_helper_load_epr(cpu_gpr[gprn], cpu_env);
4481 }
4482
4483 #endif
4484
4485 enum fsl_e500_version {
4486 fsl_e500v1,
4487 fsl_e500v2,
4488 fsl_e500mc,
4489 fsl_e5500,
4490 };
4491
4492 static void init_proc_e500 (CPUPPCState *env, int version)
4493 {
4494 uint32_t tlbncfg[2];
4495 uint64_t ivor_mask;
4496 uint64_t ivpr_mask = 0xFFFF0000ULL;
4497 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4498 | 0x0020; /* 32 kb */
4499 #if !defined(CONFIG_USER_ONLY)
4500 int i;
4501 #endif
4502
4503 /* Time base */
4504 gen_tbl(env);
4505 /*
4506 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4507 * complain when accessing them.
4508 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4509 */
4510 switch (version) {
4511 case fsl_e500v1:
4512 case fsl_e500v2:
4513 default:
4514 ivor_mask = 0x0000000F0000FFFFULL;
4515 break;
4516 case fsl_e500mc:
4517 case fsl_e5500:
4518 ivor_mask = 0x000003FE0000FFFFULL;
4519 break;
4520 }
4521 gen_spr_BookE(env, ivor_mask);
4522 /* Processor identification */
4523 spr_register(env, SPR_BOOKE_PIR, "PIR",
4524 SPR_NOACCESS, SPR_NOACCESS,
4525 &spr_read_generic, &spr_write_pir,
4526 0x00000000);
4527 /* XXX : not implemented */
4528 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4529 &spr_read_spefscr, &spr_write_spefscr,
4530 &spr_read_spefscr, &spr_write_spefscr,
4531 0x00000000);
4532 #if !defined(CONFIG_USER_ONLY)
4533 /* Memory management */
4534 env->nb_pids = 3;
4535 env->nb_ways = 2;
4536 env->id_tlbs = 0;
4537 switch (version) {
4538 case fsl_e500v1:
4539 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4540 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4541 break;
4542 case fsl_e500v2:
4543 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4544 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4545 break;
4546 case fsl_e500mc:
4547 case fsl_e5500:
4548 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4549 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4550 break;
4551 default:
4552 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4553 }
4554 #endif
4555 /* Cache sizes */
4556 switch (version) {
4557 case fsl_e500v1:
4558 case fsl_e500v2:
4559 env->dcache_line_size = 32;
4560 env->icache_line_size = 32;
4561 break;
4562 case fsl_e500mc:
4563 case fsl_e5500:
4564 env->dcache_line_size = 64;
4565 env->icache_line_size = 64;
4566 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4567 break;
4568 default:
4569 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4570 }
4571 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4572 /* XXX : not implemented */
4573 spr_register(env, SPR_HID0, "HID0",
4574 SPR_NOACCESS, SPR_NOACCESS,
4575 &spr_read_generic, &spr_write_generic,
4576 0x00000000);
4577 /* XXX : not implemented */
4578 spr_register(env, SPR_HID1, "HID1",
4579 SPR_NOACCESS, SPR_NOACCESS,
4580 &spr_read_generic, &spr_write_generic,
4581 0x00000000);
4582 /* XXX : not implemented */
4583 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4584 SPR_NOACCESS, SPR_NOACCESS,
4585 &spr_read_generic, &spr_write_generic,
4586 0x00000000);
4587 /* XXX : not implemented */
4588 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4589 SPR_NOACCESS, SPR_NOACCESS,
4590 &spr_read_generic, &spr_write_generic,
4591 0x00000000);
4592 /* XXX : not implemented */
4593 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4594 SPR_NOACCESS, SPR_NOACCESS,
4595 &spr_read_generic, &spr_write_generic,
4596 0x00000000);
4597 /* XXX : not implemented */
4598 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4599 SPR_NOACCESS, SPR_NOACCESS,
4600 &spr_read_generic, &spr_write_generic,
4601 0x00000000);
4602 /* XXX : not implemented */
4603 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4604 SPR_NOACCESS, SPR_NOACCESS,
4605 &spr_read_generic, &spr_write_generic,
4606 0x00000000);
4607 /* XXX : not implemented */
4608 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4609 SPR_NOACCESS, SPR_NOACCESS,
4610 &spr_read_generic, &spr_write_generic,
4611 0x00000000);
4612 /* XXX : not implemented */
4613 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4614 SPR_NOACCESS, SPR_NOACCESS,
4615 &spr_read_generic, &spr_write_generic,
4616 l1cfg0);
4617 /* XXX : not implemented */
4618 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4619 SPR_NOACCESS, SPR_NOACCESS,
4620 &spr_read_generic, &spr_write_e500_l1csr0,
4621 0x00000000);
4622 /* XXX : not implemented */
4623 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4624 SPR_NOACCESS, SPR_NOACCESS,
4625 &spr_read_generic, &spr_write_generic,
4626 0x00000000);
4627 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4628 SPR_NOACCESS, SPR_NOACCESS,
4629 &spr_read_generic, &spr_write_generic,
4630 0x00000000);
4631 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4632 SPR_NOACCESS, SPR_NOACCESS,
4633 &spr_read_generic, &spr_write_generic,
4634 0x00000000);
4635 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4636 SPR_NOACCESS, SPR_NOACCESS,
4637 &spr_read_generic, &spr_write_booke206_mmucsr0,
4638 0x00000000);
4639 spr_register(env, SPR_BOOKE_EPR, "EPR",
4640 SPR_NOACCESS, SPR_NOACCESS,
4641 &spr_load_epr, SPR_NOACCESS,
4642 0x00000000);
4643 /* XXX better abstract into Emb.xxx features */
4644 if (version == fsl_e5500) {
4645 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4646 SPR_NOACCESS, SPR_NOACCESS,
4647 &spr_read_generic, &spr_write_generic,
4648 0x00000000);
4649 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4650 SPR_NOACCESS, SPR_NOACCESS,
4651 &spr_read_mas73, &spr_write_mas73,
4652 0x00000000);
4653 ivpr_mask = (target_ulong)~0xFFFFULL;
4654 }
4655
4656 #if !defined(CONFIG_USER_ONLY)
4657 env->nb_tlb = 0;
4658 env->tlb_type = TLB_MAS;
4659 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4660 env->nb_tlb += booke206_tlb_size(env, i);
4661 }
4662 #endif
4663
4664 init_excp_e200(env, ivpr_mask);
4665 /* Allocate hardware IRQ controller */
4666 ppce500_irq_init(env);
4667 }
4668
4669 static void init_proc_e500v1(CPUPPCState *env)
4670 {
4671 init_proc_e500(env, fsl_e500v1);
4672 }
4673
4674 static void init_proc_e500v2(CPUPPCState *env)
4675 {
4676 init_proc_e500(env, fsl_e500v2);
4677 }
4678
4679 static void init_proc_e500mc(CPUPPCState *env)
4680 {
4681 init_proc_e500(env, fsl_e500mc);
4682 }
4683
4684 #ifdef TARGET_PPC64
4685 static void init_proc_e5500(CPUPPCState *env)
4686 {
4687 init_proc_e500(env, fsl_e5500);
4688 }
4689 #endif
4690
4691 /* Non-embedded PowerPC */
4692
4693 /* POWER : same as 601, without mfmsr, mfsr */
4694 #if defined(TODO)
4695 #define POWERPC_INSNS_POWER (XXX_TODO)
4696 /* POWER RSC (from RAD6000) */
4697 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4698 #endif /* TODO */
4699
4700 /* PowerPC 601 */
4701 #define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4702 PPC_FLOAT | \
4703 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4704 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4705 PPC_SEGMENT | PPC_EXTERN)
4706 #define POWERPC_INSNS2_601 (PPC_NONE)
4707 #define POWERPC_MSRM_601 (0x000000000000FD70ULL)
4708 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4709 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
4710 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4711 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
4712 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4713 #define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4714 #define check_pow_601 check_pow_none
4715
4716 static void init_proc_601 (CPUPPCState *env)
4717 {
4718 gen_spr_ne_601(env);
4719 gen_spr_601(env);
4720 /* Hardware implementation registers */
4721 /* XXX : not implemented */
4722 spr_register(env, SPR_HID0, "HID0",
4723 SPR_NOACCESS, SPR_NOACCESS,
4724 &spr_read_generic, &spr_write_hid0_601,
4725 0x80010080);
4726 /* XXX : not implemented */
4727 spr_register(env, SPR_HID1, "HID1",
4728 SPR_NOACCESS, SPR_NOACCESS,
4729 &spr_read_generic, &spr_write_generic,
4730 0x00000000);
4731 /* XXX : not implemented */
4732 spr_register(env, SPR_601_HID2, "HID2",
4733 SPR_NOACCESS, SPR_NOACCESS,
4734 &spr_read_generic, &spr_write_generic,
4735 0x00000000);
4736 /* XXX : not implemented */
4737 spr_register(env, SPR_601_HID5, "HID5",
4738 SPR_NOACCESS, SPR_NOACCESS,
4739 &spr_read_generic, &spr_write_generic,
4740 0x00000000);
4741 /* Memory management */
4742 init_excp_601(env);
4743 /* XXX: beware that dcache line size is 64
4744 * but dcbz uses 32 bytes "sectors"
4745 * XXX: this breaks clcs instruction !
4746 */
4747 env->dcache_line_size = 32;
4748 env->icache_line_size = 64;
4749 /* Allocate hardware IRQ controller */
4750 ppc6xx_irq_init(env);
4751 }
4752
4753 /* PowerPC 601v */
4754 #define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4755 PPC_FLOAT | \
4756 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4757 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4758 PPC_SEGMENT | PPC_EXTERN)
4759 #define POWERPC_INSNS2_601v (PPC_NONE)
4760 #define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4761 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4762 #define POWERPC_MMU_601v (POWERPC_MMU_601)
4763 #define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4764 #define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4765 #define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4766 #define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4767 #define check_pow_601v check_pow_none
4768
4769 static void init_proc_601v (CPUPPCState *env)
4770 {
4771 init_proc_601(env);
4772 /* XXX : not implemented */
4773 spr_register(env, SPR_601_HID15, "HID15",
4774 SPR_NOACCESS, SPR_NOACCESS,
4775 &spr_read_generic, &spr_write_generic,
4776 0x00000000);
4777 }
4778
4779 /* PowerPC 602 */
4780 #define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4781 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4782 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4783 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4784 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4785 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4786 PPC_SEGMENT | PPC_602_SPEC)
4787 #define POWERPC_INSNS2_602 (PPC_NONE)
4788 #define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4789 /* XXX: 602 MMU is quite specific. Should add a special case */
4790 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4791 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4792 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
4793 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
4794 #define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4795 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4796 #define check_pow_602 check_pow_hid0
4797
4798 static void init_proc_602 (CPUPPCState *env)
4799 {
4800 gen_spr_ne_601(env);
4801 gen_spr_602(env);
4802 /* Time base */
4803 gen_tbl(env);
4804 /* hardware implementation registers */
4805 /* XXX : not implemented */
4806 spr_register(env, SPR_HID0, "HID0",
4807 SPR_NOACCESS, SPR_NOACCESS,
4808 &spr_read_generic, &spr_write_generic,
4809 0x00000000);
4810 /* XXX : not implemented */
4811 spr_register(env, SPR_HID1, "HID1",
4812 SPR_NOACCESS, SPR_NOACCESS,
4813 &spr_read_generic, &spr_write_generic,
4814 0x00000000);
4815 /* Memory management */
4816 gen_low_BATs(env);
4817 gen_6xx_7xx_soft_tlb(env, 64, 2);
4818 init_excp_602(env);
4819 env->dcache_line_size = 32;
4820 env->icache_line_size = 32;
4821 /* Allocate hardware IRQ controller */
4822 ppc6xx_irq_init(env);
4823 }
4824
4825 /* PowerPC 603 */
4826 #define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4827 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4828 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4829 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4830 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4831 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4832 PPC_SEGMENT | PPC_EXTERN)
4833 #define POWERPC_INSNS2_603 (PPC_NONE)
4834 #define POWERPC_MSRM_603 (0x000000000007FF73ULL)
4835 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4836 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4837 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
4838 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
4839 #define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4840 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4841 #define check_pow_603 check_pow_hid0
4842
4843 static void init_proc_603 (CPUPPCState *env)
4844 {
4845 gen_spr_ne_601(env);
4846 gen_spr_603(env);
4847 /* Time base */
4848 gen_tbl(env);
4849 /* hardware implementation registers */
4850 /* XXX : not implemented */
4851 spr_register(env, SPR_HID0, "HID0",
4852 SPR_NOACCESS, SPR_NOACCESS,
4853 &spr_read_generic, &spr_write_generic,
4854 0x00000000);
4855 /* XXX : not implemented */
4856 spr_register(env, SPR_HID1, "HID1",
4857 SPR_NOACCESS, SPR_NOACCESS,
4858 &spr_read_generic, &spr_write_generic,
4859 0x00000000);
4860 /* Memory management */
4861 gen_low_BATs(env);
4862 gen_6xx_7xx_soft_tlb(env, 64, 2);
4863 init_excp_603(env);
4864 env->dcache_line_size = 32;
4865 env->icache_line_size = 32;
4866 /* Allocate hardware IRQ controller */
4867 ppc6xx_irq_init(env);
4868 }
4869
4870 /* PowerPC 603e */
4871 #define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4872 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4873 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4874 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4875 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4876 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4877 PPC_SEGMENT | PPC_EXTERN)
4878 #define POWERPC_INSNS2_603E (PPC_NONE)
4879 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4880 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4881 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4882 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
4883 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
4884 #define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4885 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4886 #define check_pow_603E check_pow_hid0
4887
4888 static void init_proc_603E (CPUPPCState *env)
4889 {
4890 gen_spr_ne_601(env);
4891 gen_spr_603(env);
4892 /* Time base */
4893 gen_tbl(env);
4894 /* hardware implementation registers */
4895 /* XXX : not implemented */
4896 spr_register(env, SPR_HID0, "HID0",
4897 SPR_NOACCESS, SPR_NOACCESS,
4898 &spr_read_generic, &spr_write_generic,
4899 0x00000000);
4900 /* XXX : not implemented */
4901 spr_register(env, SPR_HID1, "HID1",
4902 SPR_NOACCESS, SPR_NOACCESS,
4903 &spr_read_generic, &spr_write_generic,
4904 0x00000000);
4905 /* XXX : not implemented */
4906 spr_register(env, SPR_IABR, "IABR",
4907 SPR_NOACCESS, SPR_NOACCESS,
4908 &spr_read_generic, &spr_write_generic,
4909 0x00000000);
4910 /* Memory management */
4911 gen_low_BATs(env);
4912 gen_6xx_7xx_soft_tlb(env, 64, 2);
4913 init_excp_603(env);
4914 env->dcache_line_size = 32;
4915 env->icache_line_size = 32;
4916 /* Allocate hardware IRQ controller */
4917 ppc6xx_irq_init(env);
4918 }
4919
4920 /* PowerPC 604 */
4921 #define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4922 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4923 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4924 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4925 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4926 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4927 PPC_SEGMENT | PPC_EXTERN)
4928 #define POWERPC_INSNS2_604 (PPC_NONE)
4929 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4930 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
4931 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4932 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
4933 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
4934 #define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4935 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4936 #define check_pow_604 check_pow_nocheck
4937
4938 static void init_proc_604 (CPUPPCState *env)
4939 {
4940 gen_spr_ne_601(env);
4941 gen_spr_604(env);
4942 /* Time base */
4943 gen_tbl(env);
4944 /* Hardware implementation registers */
4945 /* XXX : not implemented */
4946 spr_register(env, SPR_HID0, "HID0",
4947 SPR_NOACCESS, SPR_NOACCESS,
4948 &spr_read_generic, &spr_write_generic,
4949 0x00000000);
4950 /* Memory management */
4951 gen_low_BATs(env);
4952 init_excp_604(env);
4953 env->dcache_line_size = 32;
4954 env->icache_line_size = 32;
4955 /* Allocate hardware IRQ controller */
4956 ppc6xx_irq_init(env);
4957 }
4958
4959 /* PowerPC 604E */
4960 #define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4961 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4962 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4963 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4964 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4965 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4966 PPC_SEGMENT | PPC_EXTERN)
4967 #define POWERPC_INSNS2_604E (PPC_NONE)
4968 #define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4969 #define POWERPC_MMU_604E (POWERPC_MMU_32B)
4970 #define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4971 #define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4972 #define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4973 #define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4974 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4975 #define check_pow_604E check_pow_nocheck
4976
4977 static void init_proc_604E (CPUPPCState *env)
4978 {
4979 gen_spr_ne_601(env);
4980 gen_spr_604(env);
4981 /* XXX : not implemented */
4982 spr_register(env, SPR_MMCR1, "MMCR1",
4983 SPR_NOACCESS, SPR_NOACCESS,
4984 &spr_read_generic, &spr_write_generic,
4985 0x00000000);
4986 /* XXX : not implemented */
4987 spr_register(env, SPR_PMC3, "PMC3",
4988 SPR_NOACCESS, SPR_NOACCESS,
4989 &spr_read_generic, &spr_write_generic,
4990 0x00000000);
4991 /* XXX : not implemented */
4992 spr_register(env, SPR_PMC4, "PMC4",
4993 SPR_NOACCESS, SPR_NOACCESS,
4994 &spr_read_generic, &spr_write_generic,
4995 0x00000000);
4996 /* Time base */
4997 gen_tbl(env);
4998 /* Hardware implementation registers */
4999 /* XXX : not implemented */
5000 spr_register(env, SPR_HID0, "HID0",
5001 SPR_NOACCESS, SPR_NOACCESS,
5002 &spr_read_generic, &spr_write_generic,
5003 0x00000000);
5004 /* XXX : not implemented */
5005 spr_register(env, SPR_HID1, "HID1",
5006 SPR_NOACCESS, SPR_NOACCESS,
5007 &spr_read_generic, &spr_write_generic,
5008 0x00000000);
5009 /* Memory management */
5010 gen_low_BATs(env);
5011 init_excp_604(env);
5012 env->dcache_line_size = 32;
5013 env->icache_line_size = 32;
5014 /* Allocate hardware IRQ controller */
5015 ppc6xx_irq_init(env);
5016 }
5017
5018 /* PowerPC 740 */
5019 #define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5020 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5021 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5022 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5023 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5024 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5025 PPC_SEGMENT | PPC_EXTERN)
5026 #define POWERPC_INSNS2_740 (PPC_NONE)
5027 #define POWERPC_MSRM_740 (0x000000000005FF77ULL)
5028 #define POWERPC_MMU_740 (POWERPC_MMU_32B)
5029 #define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
5030 #define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
5031 #define POWERPC_BFDM_740 (bfd_mach_ppc_750)
5032 #define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5033 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5034 #define check_pow_740 check_pow_hid0
5035
5036 static void init_proc_740 (CPUPPCState *env)
5037 {
5038 gen_spr_ne_601(env);
5039 gen_spr_7xx(env);
5040 /* Time base */
5041 gen_tbl(env);
5042 /* Thermal management */
5043 gen_spr_thrm(env);
5044 /* Hardware implementation registers */
5045 /* XXX : not implemented */
5046 spr_register(env, SPR_HID0, "HID0",
5047 SPR_NOACCESS, SPR_NOACCESS,
5048 &spr_read_generic, &spr_write_generic,
5049 0x00000000);
5050 /* XXX : not implemented */
5051 spr_register(env, SPR_HID1, "HID1",
5052 SPR_NOACCESS, SPR_NOACCESS,
5053 &spr_read_generic, &spr_write_generic,
5054 0x00000000);
5055 /* Memory management */
5056 gen_low_BATs(env);
5057 init_excp_7x0(env);
5058 env->dcache_line_size = 32;
5059 env->icache_line_size = 32;
5060 /* Allocate hardware IRQ controller */
5061 ppc6xx_irq_init(env);
5062 }
5063
5064 /* PowerPC 750 */
5065 #define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5066 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5067 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5068 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5069 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5070 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5071 PPC_SEGMENT | PPC_EXTERN)
5072 #define POWERPC_INSNS2_750 (PPC_NONE)
5073 #define POWERPC_MSRM_750 (0x000000000005FF77ULL)
5074 #define POWERPC_MMU_750 (POWERPC_MMU_32B)
5075 #define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
5076 #define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
5077 #define POWERPC_BFDM_750 (bfd_mach_ppc_750)
5078 #define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5079 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5080 #define check_pow_750 check_pow_hid0
5081
5082 static void init_proc_750 (CPUPPCState *env)
5083 {
5084 gen_spr_ne_601(env);
5085 gen_spr_7xx(env);
5086 /* XXX : not implemented */
5087 spr_register(env, SPR_L2CR, "L2CR",
5088 SPR_NOACCESS, SPR_NOACCESS,
5089 &spr_read_generic, &spr_write_generic,
5090 0x00000000);
5091 /* Time base */
5092 gen_tbl(env);
5093 /* Thermal management */
5094 gen_spr_thrm(env);
5095 /* Hardware implementation registers */
5096 /* XXX : not implemented */
5097 spr_register(env, SPR_HID0, "HID0",
5098 SPR_NOACCESS, SPR_NOACCESS,
5099 &spr_read_generic, &spr_write_generic,
5100 0x00000000);
5101 /* XXX : not implemented */
5102 spr_register(env, SPR_HID1, "HID1",
5103 SPR_NOACCESS, SPR_NOACCESS,
5104 &spr_read_generic, &spr_write_generic,
5105 0x00000000);
5106 /* Memory management */
5107 gen_low_BATs(env);
5108 /* XXX: high BATs are also present but are known to be bugged on
5109 * die version 1.x
5110 */
5111 init_excp_7x0(env);
5112 env->dcache_line_size = 32;
5113 env->icache_line_size = 32;
5114 /* Allocate hardware IRQ controller */
5115 ppc6xx_irq_init(env);
5116 }
5117
5118 /* PowerPC 750 CL */
5119 /* XXX: not implemented:
5120 * cache lock instructions:
5121 * dcbz_l
5122 * floating point paired instructions
5123 * psq_lux
5124 * psq_lx
5125 * psq_stux
5126 * psq_stx
5127 * ps_abs
5128 * ps_add
5129 * ps_cmpo0
5130 * ps_cmpo1
5131 * ps_cmpu0
5132 * ps_cmpu1
5133 * ps_div
5134 * ps_madd
5135 * ps_madds0
5136 * ps_madds1
5137 * ps_merge00
5138 * ps_merge01
5139 * ps_merge10
5140 * ps_merge11
5141 * ps_mr
5142 * ps_msub
5143 * ps_mul
5144 * ps_muls0
5145 * ps_muls1
5146 * ps_nabs
5147 * ps_neg
5148 * ps_nmadd
5149 * ps_nmsub
5150 * ps_res
5151 * ps_rsqrte
5152 * ps_sel
5153 * ps_sub
5154 * ps_sum0
5155 * ps_sum1
5156 */
5157 #define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5158 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5159 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5160 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5161 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5162 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5163 PPC_SEGMENT | PPC_EXTERN)
5164 #define POWERPC_INSNS2_750cl (PPC_NONE)
5165 #define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
5166 #define POWERPC_MMU_750cl (POWERPC_MMU_32B)
5167 #define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
5168 #define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
5169 #define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
5170 #define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5171 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5172 #define check_pow_750cl check_pow_hid0
5173
5174 static void init_proc_750cl (CPUPPCState *env)
5175 {
5176 gen_spr_ne_601(env);
5177 gen_spr_7xx(env);
5178 /* XXX : not implemented */
5179 spr_register(env, SPR_L2CR, "L2CR",
5180 SPR_NOACCESS, SPR_NOACCESS,
5181 &spr_read_generic, &spr_write_generic,
5182 0x00000000);
5183 /* Time base */
5184 gen_tbl(env);
5185 /* Thermal management */
5186 /* Those registers are fake on 750CL */
5187 spr_register(env, SPR_THRM1, "THRM1",
5188 SPR_NOACCESS, SPR_NOACCESS,
5189 &spr_read_generic, &spr_write_generic,
5190 0x00000000);
5191 spr_register(env, SPR_THRM2, "THRM2",
5192 SPR_NOACCESS, SPR_NOACCESS,
5193 &spr_read_generic, &spr_write_generic,
5194 0x00000000);
5195 spr_register(env, SPR_THRM3, "THRM3",
5196 SPR_NOACCESS, SPR_NOACCESS,
5197 &spr_read_generic, &spr_write_generic,
5198 0x00000000);
5199 /* XXX: not implemented */
5200 spr_register(env, SPR_750_TDCL, "TDCL",
5201 SPR_NOACCESS, SPR_NOACCESS,
5202 &spr_read_generic, &spr_write_generic,
5203 0x00000000);
5204 spr_register(env, SPR_750_TDCH, "TDCH",
5205 SPR_NOACCESS, SPR_NOACCESS,
5206 &spr_read_generic, &spr_write_generic,
5207 0x00000000);
5208 /* DMA */
5209 /* XXX : not implemented */
5210 spr_register(env, SPR_750_WPAR, "WPAR",
5211 SPR_NOACCESS, SPR_NOACCESS,
5212 &spr_read_generic, &spr_write_generic,
5213 0x00000000);
5214 spr_register(env, SPR_750_DMAL, "DMAL",
5215 SPR_NOACCESS, SPR_NOACCESS,
5216 &spr_read_generic, &spr_write_generic,
5217 0x00000000);
5218 spr_register(env, SPR_750_DMAU, "DMAU",
5219 SPR_NOACCESS, SPR_NOACCESS,
5220 &spr_read_generic, &spr_write_generic,
5221 0x00000000);
5222 /* Hardware implementation registers */
5223 /* XXX : not implemented */
5224 spr_register(env, SPR_HID0, "HID0",
5225 SPR_NOACCESS, SPR_NOACCESS,
5226 &spr_read_generic, &spr_write_generic,
5227 0x00000000);
5228 /* XXX : not implemented */
5229 spr_register(env, SPR_HID1, "HID1",
5230 SPR_NOACCESS, SPR_NOACCESS,
5231 &spr_read_generic, &spr_write_generic,
5232 0x00000000);
5233 /* XXX : not implemented */
5234 spr_register(env, SPR_750CL_HID2, "HID2",
5235 SPR_NOACCESS, SPR_NOACCESS,
5236 &spr_read_generic, &spr_write_generic,
5237 0x00000000);
5238 /* XXX : not implemented */
5239 spr_register(env, SPR_750CL_HID4, "HID4",
5240 SPR_NOACCESS, SPR_NOACCESS,
5241 &spr_read_generic, &spr_write_generic,
5242 0x00000000);
5243 /* Quantization registers */
5244 /* XXX : not implemented */
5245 spr_register(env, SPR_750_GQR0, "GQR0",
5246 SPR_NOACCESS, SPR_NOACCESS,
5247 &spr_read_generic, &spr_write_generic,
5248 0x00000000);
5249 /* XXX : not implemented */
5250 spr_register(env, SPR_750_GQR1, "GQR1",
5251 SPR_NOACCESS, SPR_NOACCESS,
5252 &spr_read_generic, &spr_write_generic,
5253 0x00000000);
5254 /* XXX : not implemented */
5255 spr_register(env, SPR_750_GQR2, "GQR2",
5256 SPR_NOACCESS, SPR_NOACCESS,
5257 &spr_read_generic, &spr_write_generic,
5258 0x00000000);
5259 /* XXX : not implemented */
5260 spr_register(env, SPR_750_GQR3, "GQR3",
5261 SPR_NOACCESS, SPR_NOACCESS,
5262 &spr_read_generic, &spr_write_generic,
5263 0x00000000);
5264 /* XXX : not implemented */
5265 spr_register(env, SPR_750_GQR4, "GQR4",
5266 SPR_NOACCESS, SPR_NOACCESS,
5267 &spr_read_generic, &spr_write_generic,
5268 0x00000000);
5269 /* XXX : not implemented */
5270 spr_register(env, SPR_750_GQR5, "GQR5",
5271 SPR_NOACCESS, SPR_NOACCESS,
5272 &spr_read_generic, &spr_write_generic,
5273 0x00000000);
5274 /* XXX : not implemented */
5275 spr_register(env, SPR_750_GQR6, "GQR6",
5276 SPR_NOACCESS, SPR_NOACCESS,
5277 &spr_read_generic, &spr_write_generic,
5278 0x00000000);
5279 /* XXX : not implemented */
5280 spr_register(env, SPR_750_GQR7, "GQR7",
5281 SPR_NOACCESS, SPR_NOACCESS,
5282 &spr_read_generic, &spr_write_generic,
5283 0x00000000);
5284 /* Memory management */
5285 gen_low_BATs(env);
5286 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5287 gen_high_BATs(env);
5288 init_excp_750cl(env);
5289 env->dcache_line_size = 32;
5290 env->icache_line_size = 32;
5291 /* Allocate hardware IRQ controller */
5292 ppc6xx_irq_init(env);
5293 }
5294
5295 /* PowerPC 750CX */
5296 #define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5297 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5298 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5299 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5300 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5301 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5302 PPC_SEGMENT | PPC_EXTERN)
5303 #define POWERPC_INSNS2_750cx (PPC_NONE)
5304 #define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
5305 #define POWERPC_MMU_750cx (POWERPC_MMU_32B)
5306 #define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
5307 #define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
5308 #define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
5309 #define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5310 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5311 #define check_pow_750cx check_pow_hid0
5312
5313 static void init_proc_750cx (CPUPPCState *env)
5314 {
5315 gen_spr_ne_601(env);
5316 gen_spr_7xx(env);
5317 /* XXX : not implemented */
5318 spr_register(env, SPR_L2CR, "L2CR",
5319 SPR_NOACCESS, SPR_NOACCESS,
5320 &spr_read_generic, &spr_write_generic,
5321 0x00000000);
5322 /* Time base */
5323 gen_tbl(env);
5324 /* Thermal management */
5325 gen_spr_thrm(env);
5326 /* This register is not implemented but is present for compatibility */
5327 spr_register(env, SPR_SDA, "SDA",
5328 SPR_NOACCESS, SPR_NOACCESS,
5329 &spr_read_generic, &spr_write_generic,
5330 0x00000000);
5331 /* Hardware implementation registers */
5332 /* XXX : not implemented */
5333 spr_register(env, SPR_HID0, "HID0",
5334 SPR_NOACCESS, SPR_NOACCESS,
5335 &spr_read_generic, &spr_write_generic,
5336 0x00000000);
5337 /* XXX : not implemented */
5338 spr_register(env, SPR_HID1, "HID1",
5339 SPR_NOACCESS, SPR_NOACCESS,
5340 &spr_read_generic, &spr_write_generic,
5341 0x00000000);
5342 /* Memory management */
5343 gen_low_BATs(env);
5344 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5345 gen_high_BATs(env);
5346 init_excp_750cx(env);
5347 env->dcache_line_size = 32;
5348 env->icache_line_size = 32;
5349 /* Allocate hardware IRQ controller */
5350 ppc6xx_irq_init(env);
5351 }
5352
5353 /* PowerPC 750FX */
5354 #define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5355 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5356 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5357 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5358 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5359 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5360 PPC_SEGMENT | PPC_EXTERN)
5361 #define POWERPC_INSNS2_750fx (PPC_NONE)
5362 #define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
5363 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
5364 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
5365 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
5366 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
5367 #define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5368 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5369 #define check_pow_750fx check_pow_hid0
5370
5371 static void init_proc_750fx (CPUPPCState *env)
5372 {
5373 gen_spr_ne_601(env);
5374 gen_spr_7xx(env);
5375 /* XXX : not implemented */
5376 spr_register(env, SPR_L2CR, "L2CR",
5377 SPR_NOACCESS, SPR_NOACCESS,
5378 &spr_read_generic, &spr_write_generic,
5379 0x00000000);
5380 /* Time base */
5381 gen_tbl(env);
5382 /* Thermal management */
5383 gen_spr_thrm(env);
5384 /* XXX : not implemented */
5385 spr_register(env, SPR_750_THRM4, "THRM4",
5386 SPR_NOACCESS, SPR_NOACCESS,
5387 &spr_read_generic, &spr_write_generic,
5388 0x00000000);
5389 /* Hardware implementation registers */
5390 /* XXX : not implemented */
5391 spr_register(env, SPR_HID0, "HID0",
5392 SPR_NOACCESS, SPR_NOACCESS,
5393 &spr_read_generic, &spr_write_generic,
5394 0x00000000);
5395 /* XXX : not implemented */
5396 spr_register(env, SPR_HID1, "HID1",
5397 SPR_NOACCESS, SPR_NOACCESS,
5398 &spr_read_generic, &spr_write_generic,
5399 0x00000000);
5400 /* XXX : not implemented */
5401 spr_register(env, SPR_750FX_HID2, "HID2",
5402 SPR_NOACCESS, SPR_NOACCESS,
5403 &spr_read_generic, &spr_write_generic,
5404 0x00000000);
5405 /* Memory management */
5406 gen_low_BATs(env);
5407 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5408 gen_high_BATs(env);
5409 init_excp_7x0(env);
5410 env->dcache_line_size = 32;
5411 env->icache_line_size = 32;
5412 /* Allocate hardware IRQ controller */
5413 ppc6xx_irq_init(env);
5414 }
5415
5416 /* PowerPC 750GX */
5417 #define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5418 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5419 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5420 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5421 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5422 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5423 PPC_SEGMENT | PPC_EXTERN)
5424 #define POWERPC_INSNS2_750gx (PPC_NONE)
5425 #define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5426 #define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5427 #define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5428 #define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5429 #define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5430 #define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5431 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5432 #define check_pow_750gx check_pow_hid0
5433
5434 static void init_proc_750gx (CPUPPCState *env)
5435 {
5436 gen_spr_ne_601(env);
5437 gen_spr_7xx(env);
5438 /* XXX : not implemented (XXX: different from 750fx) */
5439 spr_register(env, SPR_L2CR, "L2CR",
5440 SPR_NOACCESS, SPR_NOACCESS,
5441 &spr_read_generic, &spr_write_generic,
5442 0x00000000);
5443 /* Time base */
5444 gen_tbl(env);
5445 /* Thermal management */
5446 gen_spr_thrm(env);
5447 /* XXX : not implemented */
5448 spr_register(env, SPR_750_THRM4, "THRM4",
5449 SPR_NOACCESS, SPR_NOACCESS,
5450 &spr_read_generic, &spr_write_generic,
5451 0x00000000);
5452 /* Hardware implementation registers */
5453 /* XXX : not implemented (XXX: different from 750fx) */
5454 spr_register(env, SPR_HID0, "HID0",
5455 SPR_NOACCESS, SPR_NOACCESS,
5456 &spr_read_generic, &spr_write_generic,
5457 0x00000000);
5458 /* XXX : not implemented */
5459 spr_register(env, SPR_HID1, "HID1",
5460 SPR_NOACCESS, SPR_NOACCESS,
5461 &spr_read_generic, &spr_write_generic,
5462 0x00000000);
5463 /* XXX : not implemented (XXX: different from 750fx) */
5464 spr_register(env, SPR_750FX_HID2, "HID2",
5465 SPR_NOACCESS, SPR_NOACCESS,
5466 &spr_read_generic, &spr_write_generic,
5467 0x00000000);
5468 /* Memory management */
5469 gen_low_BATs(env);
5470 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5471 gen_high_BATs(env);
5472 init_excp_7x0(env);
5473 env->dcache_line_size = 32;
5474 env->icache_line_size = 32;
5475 /* Allocate hardware IRQ controller */
5476 ppc6xx_irq_init(env);
5477 }
5478
5479 /* PowerPC 745 */
5480 #define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5481 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5482 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5483 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5484 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5485 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5486 PPC_SEGMENT | PPC_EXTERN)
5487 #define POWERPC_INSNS2_745 (PPC_NONE)
5488 #define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5489 #define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5490 #define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5491 #define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5492 #define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5493 #define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5494 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5495 #define check_pow_745 check_pow_hid0
5496
5497 static void init_proc_745 (CPUPPCState *env)
5498 {
5499 gen_spr_ne_601(env);
5500 gen_spr_7xx(env);
5501 gen_spr_G2_755(env);
5502 /* Time base */
5503 gen_tbl(env);
5504 /* Thermal management */
5505 gen_spr_thrm(env);
5506 /* Hardware implementation registers */
5507 /* XXX : not implemented */
5508 spr_register(env, SPR_HID0, "HID0",
5509 SPR_NOACCESS, SPR_NOACCESS,
5510 &spr_read_generic, &spr_write_generic,
5511 0x00000000);
5512 /* XXX : not implemented */
5513 spr_register(env, SPR_HID1, "HID1",
5514 SPR_NOACCESS, SPR_NOACCESS,
5515 &spr_read_generic, &spr_write_generic,
5516 0x00000000);
5517 /* XXX : not implemented */
5518 spr_register(env, SPR_HID2, "HID2",
5519 SPR_NOACCESS, SPR_NOACCESS,
5520 &spr_read_generic, &spr_write_generic,
5521 0x00000000);
5522 /* Memory management */
5523 gen_low_BATs(env);
5524 gen_high_BATs(env);
5525 gen_6xx_7xx_soft_tlb(env, 64, 2);
5526 init_excp_7x5(env);
5527 env->dcache_line_size = 32;
5528 env->icache_line_size = 32;
5529 /* Allocate hardware IRQ controller */
5530 ppc6xx_irq_init(env);
5531 }
5532
5533 /* PowerPC 755 */
5534 #define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5535 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5536 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5537 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5538 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5539 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5540 PPC_SEGMENT | PPC_EXTERN)
5541 #define POWERPC_INSNS2_755 (PPC_NONE)
5542 #define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5543 #define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5544 #define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5545 #define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5546 #define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5547 #define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5548 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5549 #define check_pow_755 check_pow_hid0
5550
5551 static void init_proc_755 (CPUPPCState *env)
5552 {
5553 gen_spr_ne_601(env);
5554 gen_spr_7xx(env);
5555 gen_spr_G2_755(env);
5556 /* Time base */
5557 gen_tbl(env);
5558 /* L2 cache control */
5559 /* XXX : not implemented */
5560 spr_register(env, SPR_L2CR, "L2CR",
5561 SPR_NOACCESS, SPR_NOACCESS,
5562 &spr_read_generic, &spr_write_generic,
5563 0x00000000);
5564 /* XXX : not implemented */
5565 spr_register(env, SPR_L2PMCR, "L2PMCR",
5566 SPR_NOACCESS, SPR_NOACCESS,
5567 &spr_read_generic, &spr_write_generic,
5568 0x00000000);
5569 /* Thermal management */
5570 gen_spr_thrm(env);
5571 /* Hardware implementation registers */
5572 /* XXX : not implemented */
5573 spr_register(env, SPR_HID0, "HID0",
5574 SPR_NOACCESS, SPR_NOACCESS,
5575 &spr_read_generic, &spr_write_generic,
5576 0x00000000);
5577 /* XXX : not implemented */
5578 spr_register(env, SPR_HID1, "HID1",
5579 SPR_NOACCESS, SPR_NOACCESS,
5580 &spr_read_generic, &spr_write_generic,
5581 0x00000000);
5582 /* XXX : not implemented */
5583 spr_register(env, SPR_HID2, "HID2",
5584 SPR_NOACCESS, SPR_NOACCESS,
5585 &spr_read_generic, &spr_write_generic,
5586 0x00000000);
5587 /* Memory management */
5588 gen_low_BATs(env);
5589 gen_high_BATs(env);
5590 gen_6xx_7xx_soft_tlb(env, 64, 2);
5591 init_excp_7x5(env);
5592 env->dcache_line_size = 32;
5593 env->icache_line_size = 32;
5594 /* Allocate hardware IRQ controller */
5595 ppc6xx_irq_init(env);
5596 }
5597
5598 /* PowerPC 7400 (aka G4) */
5599 #define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5600 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5601 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5602 PPC_FLOAT_STFIWX | \
5603 PPC_CACHE | PPC_CACHE_ICBI | \
5604 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5605 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5606 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5607 PPC_MEM_TLBIA | \
5608 PPC_SEGMENT | PPC_EXTERN | \
5609 PPC_ALTIVEC)
5610 #define POWERPC_INSNS2_7400 (PPC_NONE)
5611 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5612 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5613 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5614 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
5615 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
5616 #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5617 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5618 POWERPC_FLAG_BUS_CLK)
5619 #define check_pow_7400 check_pow_hid0
5620
5621 static void init_proc_7400 (CPUPPCState *env)
5622 {
5623 gen_spr_ne_601(env);
5624 gen_spr_7xx(env);
5625 /* Time base */
5626 gen_tbl(env);
5627 /* 74xx specific SPR */
5628 gen_spr_74xx(env);
5629 /* XXX : not implemented */
5630 spr_register(env, SPR_UBAMR, "UBAMR",
5631 &spr_read_ureg, SPR_NOACCESS,
5632 &spr_read_ureg, SPR_NOACCESS,
5633 0x00000000);
5634 /* XXX: this seems not implemented on all revisions. */
5635 /* XXX : not implemented */
5636 spr_register(env, SPR_MSSCR1, "MSSCR1",
5637 SPR_NOACCESS, SPR_NOACCESS,
5638 &spr_read_generic, &spr_write_generic,
5639 0x00000000);
5640 /* Thermal management */
5641 gen_spr_thrm(env);
5642 /* Memory management */
5643 gen_low_BATs(env);
5644 init_excp_7400(env);
5645 env->dcache_line_size = 32;
5646 env->icache_line_size = 32;
5647 /* Allocate hardware IRQ controller */
5648 ppc6xx_irq_init(env);
5649 }
5650
5651 /* PowerPC 7410 (aka G4) */
5652 #define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5653 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5654 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5655 PPC_FLOAT_STFIWX | \
5656 PPC_CACHE | PPC_CACHE_ICBI | \
5657 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5658 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5659 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5660 PPC_MEM_TLBIA | \
5661 PPC_SEGMENT | PPC_EXTERN | \
5662 PPC_ALTIVEC)
5663 #define POWERPC_INSNS2_7410 (PPC_NONE)
5664 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5665 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5666 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5667 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
5668 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
5669 #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5670 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5671 POWERPC_FLAG_BUS_CLK)
5672 #define check_pow_7410 check_pow_hid0
5673
5674 static void init_proc_7410 (CPUPPCState *env)
5675 {
5676 gen_spr_ne_601(env);
5677 gen_spr_7xx(env);
5678 /* Time base */
5679 gen_tbl(env);
5680 /* 74xx specific SPR */
5681 gen_spr_74xx(env);
5682 /* XXX : not implemented */
5683 spr_register(env, SPR_UBAMR, "UBAMR",
5684 &spr_read_ureg, SPR_NOACCESS,
5685 &spr_read_ureg, SPR_NOACCESS,
5686 0x00000000);
5687 /* Thermal management */
5688 gen_spr_thrm(env);
5689 /* L2PMCR */
5690 /* XXX : not implemented */
5691 spr_register(env, SPR_L2PMCR, "L2PMCR",
5692 SPR_NOACCESS, SPR_NOACCESS,
5693 &spr_read_generic, &spr_write_generic,
5694 0x00000000);
5695 /* LDSTDB */
5696 /* XXX : not implemented */
5697 spr_register(env, SPR_LDSTDB, "LDSTDB",
5698 SPR_NOACCESS, SPR_NOACCESS,
5699 &spr_read_generic, &spr_write_generic,
5700 0x00000000);
5701 /* Memory management */
5702 gen_low_BATs(env);
5703 init_excp_7400(env);
5704 env->dcache_line_size = 32;
5705 env->icache_line_size = 32;
5706 /* Allocate hardware IRQ controller */
5707 ppc6xx_irq_init(env);
5708 }
5709
5710 /* PowerPC 7440 (aka G4) */
5711 #define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5712 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5713 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5714 PPC_FLOAT_STFIWX | \
5715 PPC_CACHE | PPC_CACHE_ICBI | \
5716 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5717 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5718 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5719 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5720 PPC_SEGMENT | PPC_EXTERN | \
5721 PPC_ALTIVEC)
5722 #define POWERPC_INSNS2_7440 (PPC_NONE)
5723 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5724 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5725 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5726 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
5727 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
5728 #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5729 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5730 POWERPC_FLAG_BUS_CLK)
5731 #define check_pow_7440 check_pow_hid0_74xx
5732
5733 __attribute__ (( unused ))
5734 static void init_proc_7440 (CPUPPCState *env)
5735 {
5736 gen_spr_ne_601(env);
5737 gen_spr_7xx(env);
5738 /* Time base */
5739 gen_tbl(env);
5740 /* 74xx specific SPR */
5741 gen_spr_74xx(env);
5742 /* XXX : not implemented */
5743 spr_register(env, SPR_UBAMR, "UBAMR",
5744 &spr_read_ureg, SPR_NOACCESS,
5745 &spr_read_ureg, SPR_NOACCESS,
5746 0x00000000);
5747 /* LDSTCR */
5748 /* XXX : not implemented */
5749 spr_register(env, SPR_LDSTCR, "LDSTCR",
5750 SPR_NOACCESS, SPR_NOACCESS,
5751 &spr_read_generic, &spr_write_generic,
5752 0x00000000);
5753 /* ICTRL */
5754 /* XXX : not implemented */
5755 spr_register(env, SPR_ICTRL, "ICTRL",
5756 SPR_NOACCESS, SPR_NOACCESS,
5757 &spr_read_generic, &spr_write_generic,
5758 0x00000000);
5759 /* MSSSR0 */
5760 /* XXX : not implemented */
5761 spr_register(env, SPR_MSSSR0, "MSSSR0",
5762 SPR_NOACCESS, SPR_NOACCESS,
5763 &spr_read_generic, &spr_write_generic,
5764 0x00000000);
5765 /* PMC */
5766 /* XXX : not implemented */
5767 spr_register(env, SPR_PMC5, "PMC5",
5768 SPR_NOACCESS, SPR_NOACCESS,
5769 &spr_read_generic, &spr_write_generic,
5770 0x00000000);
5771 /* XXX : not implemented */
5772 spr_register(env, SPR_UPMC5, "UPMC5",
5773 &spr_read_ureg, SPR_NOACCESS,
5774 &spr_read_ureg, SPR_NOACCESS,
5775 0x00000000);
5776 /* XXX : not implemented */
5777 spr_register(env, SPR_PMC6, "PMC6",
5778 SPR_NOACCESS, SPR_NOACCESS,
5779 &spr_read_generic, &spr_write_generic,
5780 0x00000000);
5781 /* XXX : not implemented */
5782 spr_register(env, SPR_UPMC6, "UPMC6",
5783 &spr_read_ureg, SPR_NOACCESS,
5784 &spr_read_ureg, SPR_NOACCESS,
5785 0x00000000);
5786 /* Memory management */
5787 gen_low_BATs(env);
5788 gen_74xx_soft_tlb(env, 128, 2);
5789 init_excp_7450(env);
5790 env->dcache_line_size = 32;
5791 env->icache_line_size = 32;
5792 /* Allocate hardware IRQ controller */
5793 ppc6xx_irq_init(env);
5794 }
5795
5796 /* PowerPC 7450 (aka G4) */
5797 #define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5798 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5799 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5800 PPC_FLOAT_STFIWX | \
5801 PPC_CACHE | PPC_CACHE_ICBI | \
5802 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5803 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5804 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5805 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5806 PPC_SEGMENT | PPC_EXTERN | \
5807 PPC_ALTIVEC)
5808 #define POWERPC_INSNS2_7450 (PPC_NONE)
5809 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5810 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5811 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5812 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
5813 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
5814 #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5815 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5816 POWERPC_FLAG_BUS_CLK)
5817 #define check_pow_7450 check_pow_hid0_74xx
5818
5819 __attribute__ (( unused ))
5820 static void init_proc_7450 (CPUPPCState *env)
5821 {
5822 gen_spr_ne_601(env);
5823 gen_spr_7xx(env);
5824 /* Time base */
5825 gen_tbl(env);
5826 /* 74xx specific SPR */
5827 gen_spr_74xx(env);
5828 /* Level 3 cache control */
5829 gen_l3_ctrl(env);
5830 /* L3ITCR1 */
5831 /* XXX : not implemented */
5832 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5833 SPR_NOACCESS, SPR_NOACCESS,
5834 &spr_read_generic, &spr_write_generic,
5835 0x00000000);
5836 /* L3ITCR2 */
5837 /* XXX : not implemented */
5838 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5839 SPR_NOACCESS, SPR_NOACCESS,
5840 &spr_read_generic, &spr_write_generic,
5841 0x00000000);
5842 /* L3ITCR3 */
5843 /* XXX : not implemented */
5844 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5845 SPR_NOACCESS, SPR_NOACCESS,
5846 &spr_read_generic, &spr_write_generic,
5847 0x00000000);
5848 /* L3OHCR */
5849 /* XXX : not implemented */
5850 spr_register(env, SPR_L3OHCR, "L3OHCR",
5851 SPR_NOACCESS, SPR_NOACCESS,
5852 &spr_read_generic, &spr_write_generic,
5853 0x00000000);
5854 /* XXX : not implemented */
5855 spr_register(env, SPR_UBAMR, "UBAMR",
5856 &spr_read_ureg, SPR_NOACCESS,
5857 &spr_read_ureg, SPR_NOACCESS,
5858 0x00000000);
5859 /* LDSTCR */
5860 /* XXX : not implemented */
5861 spr_register(env, SPR_LDSTCR, "LDSTCR",
5862 SPR_NOACCESS, SPR_NOACCESS,
5863 &spr_read_generic, &spr_write_generic,
5864 0x00000000);
5865 /* ICTRL */
5866 /* XXX : not implemented */
5867 spr_register(env, SPR_ICTRL, "ICTRL",
5868 SPR_NOACCESS, SPR_NOACCESS,
5869 &spr_read_generic, &spr_write_generic,
5870 0x00000000);
5871 /* MSSSR0 */
5872 /* XXX : not implemented */
5873 spr_register(env, SPR_MSSSR0, "MSSSR0",
5874 SPR_NOACCESS, SPR_NOACCESS,
5875 &spr_read_generic, &spr_write_generic,
5876 0x00000000);
5877 /* PMC */
5878 /* XXX : not implemented */
5879 spr_register(env, SPR_PMC5, "PMC5",
5880 SPR_NOACCESS, SPR_NOACCESS,
5881 &spr_read_generic, &spr_write_generic,
5882 0x00000000);
5883 /* XXX : not implemented */
5884 spr_register(env, SPR_UPMC5, "UPMC5",
5885 &spr_read_ureg, SPR_NOACCESS,
5886 &spr_read_ureg, SPR_NOACCESS,
5887 0x00000000);
5888 /* XXX : not implemented */
5889 spr_register(env, SPR_PMC6, "PMC6",
5890 SPR_NOACCESS, SPR_NOACCESS,
5891 &spr_read_generic, &spr_write_generic,
5892 0x00000000);
5893 /* XXX : not implemented */
5894 spr_register(env, SPR_UPMC6, "UPMC6",
5895 &spr_read_ureg, SPR_NOACCESS,
5896 &spr_read_ureg, SPR_NOACCESS,
5897 0x00000000);
5898 /* Memory management */
5899 gen_low_BATs(env);
5900 gen_74xx_soft_tlb(env, 128, 2);
5901 init_excp_7450(env);
5902 env->dcache_line_size = 32;
5903 env->icache_line_size = 32;
5904 /* Allocate hardware IRQ controller */
5905 ppc6xx_irq_init(env);
5906 }
5907
5908 /* PowerPC 7445 (aka G4) */
5909 #define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5910 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5911 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5912 PPC_FLOAT_STFIWX | \
5913 PPC_CACHE | PPC_CACHE_ICBI | \
5914 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5915 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5916 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5917 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5918 PPC_SEGMENT | PPC_EXTERN | \
5919 PPC_ALTIVEC)
5920 #define POWERPC_INSNS2_7445 (PPC_NONE)
5921 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5922 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5923 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5924 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
5925 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
5926 #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5927 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5928 POWERPC_FLAG_BUS_CLK)
5929 #define check_pow_7445 check_pow_hid0_74xx
5930
5931 __attribute__ (( unused ))
5932 static void init_proc_7445 (CPUPPCState *env)
5933 {
5934 gen_spr_ne_601(env);
5935 gen_spr_7xx(env);
5936 /* Time base */
5937 gen_tbl(env);
5938 /* 74xx specific SPR */
5939 gen_spr_74xx(env);
5940 /* LDSTCR */
5941 /* XXX : not implemented */
5942 spr_register(env, SPR_LDSTCR, "LDSTCR",
5943 SPR_NOACCESS, SPR_NOACCESS,
5944 &spr_read_generic, &spr_write_generic,
5945 0x00000000);
5946 /* ICTRL */
5947 /* XXX : not implemented */
5948 spr_register(env, SPR_ICTRL, "ICTRL",
5949 SPR_NOACCESS, SPR_NOACCESS,
5950 &spr_read_generic, &spr_write_generic,
5951 0x00000000);
5952 /* MSSSR0 */
5953 /* XXX : not implemented */
5954 spr_register(env, SPR_MSSSR0, "MSSSR0",
5955 SPR_NOACCESS, SPR_NOACCESS,
5956 &spr_read_generic, &spr_write_generic,
5957 0x00000000);
5958 /* PMC */
5959 /* XXX : not implemented */
5960 spr_register(env, SPR_PMC5, "PMC5",
5961 SPR_NOACCESS, SPR_NOACCESS,
5962 &spr_read_generic, &spr_write_generic,
5963 0x00000000);
5964 /* XXX : not implemented */
5965 spr_register(env, SPR_UPMC5, "UPMC5",
5966 &spr_read_ureg, SPR_NOACCESS,
5967 &spr_read_ureg, SPR_NOACCESS,
5968 0x00000000);
5969 /* XXX : not implemented */
5970 spr_register(env, SPR_PMC6, "PMC6",
5971 SPR_NOACCESS, SPR_NOACCESS,
5972 &spr_read_generic, &spr_write_generic,
5973 0x00000000);
5974 /* XXX : not implemented */
5975 spr_register(env, SPR_UPMC6, "UPMC6",
5976 &spr_read_ureg, SPR_NOACCESS,
5977 &spr_read_ureg, SPR_NOACCESS,
5978 0x00000000);
5979 /* SPRGs */
5980 spr_register(env, SPR_SPRG4, "SPRG4",
5981 SPR_NOACCESS, SPR_NOACCESS,
5982 &spr_read_generic, &spr_write_generic,
5983 0x00000000);
5984 spr_register(env, SPR_USPRG4, "USPRG4",
5985 &spr_read_ureg, SPR_NOACCESS,
5986 &spr_read_ureg, SPR_NOACCESS,
5987 0x00000000);
5988 spr_register(env, SPR_SPRG5, "SPRG5",
5989 SPR_NOACCESS, SPR_NOACCESS,
5990 &spr_read_generic, &spr_write_generic,
5991 0x00000000);
5992 spr_register(env, SPR_USPRG5, "USPRG5",
5993 &spr_read_ureg, SPR_NOACCESS,
5994 &spr_read_ureg, SPR_NOACCESS,
5995 0x00000000);
5996 spr_register(env, SPR_SPRG6, "SPRG6",
5997 SPR_NOACCESS, SPR_NOACCESS,
5998 &spr_read_generic, &spr_write_generic,
5999 0x00000000);
6000 spr_register(env, SPR_USPRG6, "USPRG6",
6001 &spr_read_ureg, SPR_NOACCESS,
6002 &spr_read_ureg, SPR_NOACCESS,
6003 0x00000000);
6004 spr_register(env, SPR_SPRG7, "SPRG7",
6005 SPR_NOACCESS, SPR_NOACCESS,
6006 &spr_read_generic, &spr_write_generic,
6007 0x00000000);
6008 spr_register(env, SPR_USPRG7, "USPRG7",
6009 &spr_read_ureg, SPR_NOACCESS,
6010 &spr_read_ureg, SPR_NOACCESS,
6011 0x00000000);
6012 /* Memory management */
6013 gen_low_BATs(env);
6014 gen_high_BATs(env);
6015 gen_74xx_soft_tlb(env, 128, 2);
6016 init_excp_7450(env);
6017 env->dcache_line_size = 32;
6018 env->icache_line_size = 32;
6019 /* Allocate hardware IRQ controller */
6020 ppc6xx_irq_init(env);
6021 }
6022
6023 /* PowerPC 7455 (aka G4) */
6024 #define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6025 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6026 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6027 PPC_FLOAT_STFIWX | \
6028 PPC_CACHE | PPC_CACHE_ICBI | \
6029 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
6030 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6031 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6032 PPC_MEM_TLBIA | PPC_74xx_TLB | \
6033 PPC_SEGMENT | PPC_EXTERN | \
6034 PPC_ALTIVEC)
6035 #define POWERPC_INSNS2_7455 (PPC_NONE)
6036 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
6037 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
6038 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
6039 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
6040 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
6041 #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6042 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6043 POWERPC_FLAG_BUS_CLK)
6044 #define check_pow_7455 check_pow_hid0_74xx
6045
6046 __attribute__ (( unused ))
6047 static void init_proc_7455 (CPUPPCState *env)
6048 {
6049 gen_spr_ne_601(env);
6050 gen_spr_7xx(env);
6051 /* Time base */
6052 gen_tbl(env);
6053 /* 74xx specific SPR */
6054 gen_spr_74xx(env);
6055 /* Level 3 cache control */
6056 gen_l3_ctrl(env);
6057 /* LDSTCR */
6058 /* XXX : not implemented */
6059 spr_register(env, SPR_LDSTCR, "LDSTCR",
6060 SPR_NOACCESS, SPR_NOACCESS,
6061 &spr_read_generic, &spr_write_generic,
6062 0x00000000);
6063 /* ICTRL */
6064 /* XXX : not implemented */
6065 spr_register(env, SPR_ICTRL, "ICTRL",
6066 SPR_NOACCESS, SPR_NOACCESS,
6067 &spr_read_generic, &spr_write_generic,
6068 0x00000000);
6069 /* MSSSR0 */
6070 /* XXX : not implemented */
6071 spr_register(env, SPR_MSSSR0, "MSSSR0",
6072 SPR_NOACCESS, SPR_NOACCESS,
6073 &spr_read_generic, &spr_write_generic,
6074 0x00000000);
6075 /* PMC */
6076 /* XXX : not implemented */
6077 spr_register(env, SPR_PMC5, "PMC5",
6078 SPR_NOACCESS, SPR_NOACCESS,
6079 &spr_read_generic, &spr_write_generic,
6080 0x00000000);
6081 /* XXX : not implemented */
6082 spr_register(env, SPR_UPMC5, "UPMC5",
6083 &spr_read_ureg, SPR_NOACCESS,
6084 &spr_read_ureg, SPR_NOACCESS,
6085 0x00000000);
6086 /* XXX : not implemented */
6087 spr_register(env, SPR_PMC6, "PMC6",
6088 SPR_NOACCESS, SPR_NOACCESS,
6089 &spr_read_generic, &spr_write_generic,
6090 0x00000000);
6091 /* XXX : not implemented */
6092 spr_register(env, SPR_UPMC6, "UPMC6",
6093 &spr_read_ureg, SPR_NOACCESS,
6094 &spr_read_ureg, SPR_NOACCESS,
6095 0x00000000);
6096 /* SPRGs */
6097 spr_register(env, SPR_SPRG4, "SPRG4",
6098 SPR_NOACCESS, SPR_NOACCESS,
6099 &spr_read_generic, &spr_write_generic,
6100 0x00000000);
6101 spr_register(env, SPR_USPRG4, "USPRG4",
6102 &spr_read_ureg, SPR_NOACCESS,
6103 &spr_read_ureg, SPR_NOACCESS,
6104 0x00000000);
6105 spr_register(env, SPR_SPRG5, "SPRG5",
6106 SPR_NOACCESS, SPR_NOACCESS,
6107 &spr_read_generic, &spr_write_generic,
6108 0x00000000);
6109 spr_register(env, SPR_USPRG5, "USPRG5",
6110 &spr_read_ureg, SPR_NOACCESS,
6111 &spr_read_ureg, SPR_NOACCESS,
6112 0x00000000);
6113 spr_register(env, SPR_SPRG6, "SPRG6",
6114 SPR_NOACCESS, SPR_NOACCESS,
6115 &spr_read_generic, &spr_write_generic,
6116 0x00000000);
6117 spr_register(env, SPR_USPRG6, "USPRG6",
6118 &spr_read_ureg, SPR_NOACCESS,
6119 &spr_read_ureg, SPR_NOACCESS,
6120 0x00000000);
6121 spr_register(env, SPR_SPRG7, "SPRG7",
6122 SPR_NOACCESS, SPR_NOACCESS,
6123 &spr_read_generic, &spr_write_generic,
6124 0x00000000);
6125 spr_register(env, SPR_USPRG7, "USPRG7",
6126 &spr_read_ureg, SPR_NOACCESS,
6127 &spr_read_ureg, SPR_NOACCESS,
6128 0x00000000);
6129 /* Memory management */
6130 gen_low_BATs(env);
6131 gen_high_BATs(env);
6132 gen_74xx_soft_tlb(env, 128, 2);
6133 init_excp_7450(env);
6134 env->dcache_line_size = 32;
6135 env->icache_line_size = 32;
6136 /* Allocate hardware IRQ controller */
6137 ppc6xx_irq_init(env);
6138 }
6139
6140 /* PowerPC 7457 (aka G4) */
6141 #define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6142 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6143 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6144 PPC_FLOAT_STFIWX | \
6145 PPC_CACHE | PPC_CACHE_ICBI | \
6146 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
6147 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6148 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6149 PPC_MEM_TLBIA | PPC_74xx_TLB | \
6150 PPC_SEGMENT | PPC_EXTERN | \
6151 PPC_ALTIVEC)
6152 #define POWERPC_INSNS2_7457 (PPC_NONE)
6153 #define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
6154 #define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
6155 #define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
6156 #define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
6157 #define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
6158 #define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6159 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6160 POWERPC_FLAG_BUS_CLK)
6161 #define check_pow_7457 check_pow_hid0_74xx
6162
6163 __attribute__ (( unused ))
6164 static void init_proc_7457 (CPUPPCState *env)
6165 {
6166 gen_spr_ne_601(env);
6167 gen_spr_7xx(env);
6168 /* Time base */
6169 gen_tbl(env);
6170 /* 74xx specific SPR */
6171 gen_spr_74xx(env);
6172 /* Level 3 cache control */
6173 gen_l3_ctrl(env);
6174 /* L3ITCR1 */
6175 /* XXX : not implemented */
6176 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6177 SPR_NOACCESS, SPR_NOACCESS,
6178 &spr_read_generic, &spr_write_generic,
6179 0x00000000);
6180 /* L3ITCR2 */
6181 /* XXX : not implemented */
6182 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6183 SPR_NOACCESS, SPR_NOACCESS,
6184 &spr_read_generic, &spr_write_generic,
6185 0x00000000);
6186 /* L3ITCR3 */
6187 /* XXX : not implemented */
6188 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6189 SPR_NOACCESS, SPR_NOACCESS,
6190 &spr_read_generic, &spr_write_generic,
6191 0x00000000);
6192 /* L3OHCR */
6193 /* XXX : not implemented */
6194 spr_register(env, SPR_L3OHCR, "L3OHCR",
6195 SPR_NOACCESS, SPR_NOACCESS,
6196 &spr_read_generic, &spr_write_generic,
6197 0x00000000);
6198 /* LDSTCR */
6199 /* XXX : not implemented */
6200 spr_register(env, SPR_LDSTCR, "LDSTCR",
6201 SPR_NOACCESS, SPR_NOACCESS,
6202 &spr_read_generic, &spr_write_generic,
6203 0x00000000);
6204 /* ICTRL */
6205 /* XXX : not implemented */
6206 spr_register(env, SPR_ICTRL, "ICTRL",
6207 SPR_NOACCESS, SPR_NOACCESS,
6208 &spr_read_generic, &spr_write_generic,
6209 0x00000000);
6210 /* MSSSR0 */
6211 /* XXX : not implemented */
6212 spr_register(env, SPR_MSSSR0, "MSSSR0",
6213 SPR_NOACCESS, SPR_NOACCESS,
6214 &spr_read_generic, &spr_write_generic,
6215 0x00000000);
6216 /* PMC */
6217 /* XXX : not implemented */
6218 spr_register(env, SPR_PMC5, "PMC5",
6219 SPR_NOACCESS, SPR_NOACCESS,
6220 &spr_read_generic, &spr_write_generic,
6221 0x00000000);
6222 /* XXX : not implemented */
6223 spr_register(env, SPR_UPMC5, "UPMC5",
6224 &spr_read_ureg, SPR_NOACCESS,
6225 &spr_read_ureg, SPR_NOACCESS,
6226 0x00000000);
6227 /* XXX : not implemented */
6228 spr_register(env, SPR_PMC6, "PMC6",
6229 SPR_NOACCESS, SPR_NOACCESS,
6230 &spr_read_generic, &spr_write_generic,
6231 0x00000000);
6232 /* XXX : not implemented */
6233 spr_register(env, SPR_UPMC6, "UPMC6",
6234 &spr_read_ureg, SPR_NOACCESS,
6235 &spr_read_ureg, SPR_NOACCESS,
6236 0x00000000);
6237 /* SPRGs */
6238 spr_register(env, SPR_SPRG4, "SPRG4",
6239 SPR_NOACCESS, SPR_NOACCESS,
6240 &spr_read_generic, &spr_write_generic,
6241 0x00000000);
6242 spr_register(env, SPR_USPRG4, "USPRG4",
6243 &spr_read_ureg, SPR_NOACCESS,
6244 &spr_read_ureg, SPR_NOACCESS,
6245 0x00000000);
6246 spr_register(env, SPR_SPRG5, "SPRG5",
6247 SPR_NOACCESS, SPR_NOACCESS,
6248 &spr_read_generic, &spr_write_generic,
6249 0x00000000);
6250 spr_register(env, SPR_USPRG5, "USPRG5",
6251 &spr_read_ureg, SPR_NOACCESS,
6252 &spr_read_ureg, SPR_NOACCESS,
6253 0x00000000);
6254 spr_register(env, SPR_SPRG6, "SPRG6",
6255 SPR_NOACCESS, SPR_NOACCESS,
6256 &spr_read_generic, &spr_write_generic,
6257 0x00000000);
6258 spr_register(env, SPR_USPRG6, "USPRG6",
6259 &spr_read_ureg, SPR_NOACCESS,
6260 &spr_read_ureg, SPR_NOACCESS,
6261 0x00000000);
6262 spr_register(env, SPR_SPRG7, "SPRG7",
6263 SPR_NOACCESS, SPR_NOACCESS,
6264 &spr_read_generic, &spr_write_generic,
6265 0x00000000);
6266 spr_register(env, SPR_USPRG7, "USPRG7",
6267 &spr_read_ureg, SPR_NOACCESS,
6268 &spr_read_ureg, SPR_NOACCESS,
6269 0x00000000);
6270 /* Memory management */
6271 gen_low_BATs(env);
6272 gen_high_BATs(env);
6273 gen_74xx_soft_tlb(env, 128, 2);
6274 init_excp_7450(env);
6275 env->dcache_line_size = 32;
6276 env->icache_line_size = 32;
6277 /* Allocate hardware IRQ controller */
6278 ppc6xx_irq_init(env);
6279 }
6280
6281 #if defined (TARGET_PPC64)
6282 /* PowerPC 970 */
6283 #define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6284 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6285 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6286 PPC_FLOAT_STFIWX | \
6287 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6288 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6289 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6290 PPC_64B | PPC_ALTIVEC | \
6291 PPC_SEGMENT_64B | PPC_SLBI)
6292 #define POWERPC_INSNS2_970 (PPC_NONE)
6293 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
6294 #define POWERPC_MMU_970 (POWERPC_MMU_64B)
6295 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
6296 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
6297 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
6298 #define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6299 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6300 POWERPC_FLAG_BUS_CLK)
6301
6302 #if defined(CONFIG_USER_ONLY)
6303 #define POWERPC970_HID5_INIT 0x00000080
6304 #else
6305 #define POWERPC970_HID5_INIT 0x00000000
6306 #endif
6307
6308 static int check_pow_970 (CPUPPCState *env)
6309 {
6310 if (env->spr[SPR_HID0] & 0x00600000)
6311 return 1;
6312
6313 return 0;
6314 }
6315
6316 static void init_proc_970 (CPUPPCState *env)
6317 {
6318 gen_spr_ne_601(env);
6319 gen_spr_7xx(env);
6320 /* Time base */
6321 gen_tbl(env);
6322 /* Hardware implementation registers */
6323 /* XXX : not implemented */
6324 spr_register(env, SPR_HID0, "HID0",
6325 SPR_NOACCESS, SPR_NOACCESS,
6326 &spr_read_generic, &spr_write_clear,
6327 0x60000000);
6328 /* XXX : not implemented */
6329 spr_register(env, SPR_HID1, "HID1",
6330 SPR_NOACCESS, SPR_NOACCESS,
6331 &spr_read_generic, &spr_write_generic,
6332 0x00000000);
6333 /* XXX : not implemented */
6334 spr_register(env, SPR_750FX_HID2, "HID2",
6335 SPR_NOACCESS, SPR_NOACCESS,
6336 &spr_read_generic, &spr_write_generic,
6337 0x00000000);
6338 /* XXX : not implemented */
6339 spr_register(env, SPR_970_HID5, "HID5",
6340 SPR_NOACCESS, SPR_NOACCESS,
6341 &spr_read_generic, &spr_write_generic,
6342 POWERPC970_HID5_INIT);
6343 /* XXX : not implemented */
6344 spr_register(env, SPR_L2CR, "L2CR",
6345 SPR_NOACCESS, SPR_NOACCESS,
6346 &spr_read_generic, &spr_write_generic,
6347 0x00000000);
6348 /* Memory management */
6349 /* XXX: not correct */
6350 gen_low_BATs(env);
6351 /* XXX : not implemented */
6352 spr_register(env, SPR_MMUCFG, "MMUCFG",
6353 SPR_NOACCESS, SPR_NOACCESS,
6354 &spr_read_generic, SPR_NOACCESS,
6355 0x00000000); /* TOFIX */
6356 /* XXX : not implemented */
6357 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6358 SPR_NOACCESS, SPR_NOACCESS,
6359 &spr_read_generic, &spr_write_generic,
6360 0x00000000); /* TOFIX */
6361 spr_register(env, SPR_HIOR, "SPR_HIOR",
6362 SPR_NOACCESS, SPR_NOACCESS,
6363 &spr_read_hior, &spr_write_hior,
6364 0x00000000);
6365 #if !defined(CONFIG_USER_ONLY)
6366 env->slb_nr = 32;
6367 #endif
6368 init_excp_970(env);
6369 env->dcache_line_size = 128;
6370 env->icache_line_size = 128;
6371 /* Allocate hardware IRQ controller */
6372 ppc970_irq_init(env);
6373 /* Can't find information on what this should be on reset. This
6374 * value is the one used by 74xx processors. */
6375 vscr_init(env, 0x00010000);
6376 }
6377
6378 /* PowerPC 970FX (aka G5) */
6379 #define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6380 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6381 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6382 PPC_FLOAT_STFIWX | \
6383 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6384 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6385 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6386 PPC_64B | PPC_ALTIVEC | \
6387 PPC_SEGMENT_64B | PPC_SLBI)
6388 #define POWERPC_INSNS2_970FX (PPC_NONE)
6389 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
6390 #define POWERPC_MMU_970FX (POWERPC_MMU_64B)
6391 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
6392 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
6393 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
6394 #define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6395 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6396 POWERPC_FLAG_BUS_CLK)
6397
6398 static int check_pow_970FX (CPUPPCState *env)
6399 {
6400 if (env->spr[SPR_HID0] & 0x00600000)
6401 return 1;
6402
6403 return 0;
6404 }
6405
6406 static void init_proc_970FX (CPUPPCState *env)
6407 {
6408 gen_spr_ne_601(env);
6409 gen_spr_7xx(env);
6410 /* Time base */
6411 gen_tbl(env);
6412 /* Hardware implementation registers */
6413 /* XXX : not implemented */
6414 spr_register(env, SPR_HID0, "HID0",
6415 SPR_NOACCESS, SPR_NOACCESS,
6416 &spr_read_generic, &spr_write_clear,
6417 0x60000000);
6418 /* XXX : not implemented */
6419 spr_register(env, SPR_HID1, "HID1",
6420 SPR_NOACCESS, SPR_NOACCESS,
6421 &spr_read_generic, &spr_write_generic,
6422 0x00000000);
6423 /* XXX : not implemented */
6424 spr_register(env, SPR_750FX_HID2, "HID2",
6425 SPR_NOACCESS, SPR_NOACCESS,
6426 &spr_read_generic, &spr_write_generic,
6427 0x00000000);
6428 /* XXX : not implemented */
6429 spr_register(env, SPR_970_HID5, "HID5",
6430 SPR_NOACCESS, SPR_NOACCESS,
6431 &spr_read_generic, &spr_write_generic,
6432 POWERPC970_HID5_INIT);
6433 /* XXX : not implemented */
6434 spr_register(env, SPR_L2CR, "L2CR",
6435 SPR_NOACCESS, SPR_NOACCESS,
6436 &spr_read_generic, &spr_write_generic,
6437 0x00000000);
6438 /* Memory management */
6439 /* XXX: not correct */
6440 gen_low_BATs(env);
6441 /* XXX : not implemented */
6442 spr_register(env, SPR_MMUCFG, "MMUCFG",
6443 SPR_NOACCESS, SPR_NOACCESS,
6444 &spr_read_generic, SPR_NOACCESS,
6445 0x00000000); /* TOFIX */
6446 /* XXX : not implemented */
6447 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6448 SPR_NOACCESS, SPR_NOACCESS,
6449 &spr_read_generic, &spr_write_generic,
6450 0x00000000); /* TOFIX */
6451 spr_register(env, SPR_HIOR, "SPR_HIOR",
6452 SPR_NOACCESS, SPR_NOACCESS,
6453 &spr_read_hior, &spr_write_hior,
6454 0x00000000);
6455 spr_register(env, SPR_CTRL, "SPR_CTRL",
6456 SPR_NOACCESS, SPR_NOACCESS,
6457 &spr_read_generic, &spr_write_generic,
6458 0x00000000);
6459 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6460 SPR_NOACCESS, SPR_NOACCESS,
6461 &spr_read_generic, &spr_write_generic,
6462 0x00000000);
6463 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6464 &spr_read_generic, &spr_write_generic,
6465 &spr_read_generic, &spr_write_generic,
6466 0x00000000);
6467 #if !defined(CONFIG_USER_ONLY)
6468 env->slb_nr = 64;
6469 #endif
6470 init_excp_970(env);
6471 env->dcache_line_size = 128;
6472 env->icache_line_size = 128;
6473 /* Allocate hardware IRQ controller */
6474 ppc970_irq_init(env);
6475 /* Can't find information on what this should be on reset. This
6476 * value is the one used by 74xx processors. */
6477 vscr_init(env, 0x00010000);
6478 }
6479
6480 /* PowerPC 970 GX */
6481 #define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6482 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6483 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6484 PPC_FLOAT_STFIWX | \
6485 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6486 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6487 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6488 PPC_64B | PPC_ALTIVEC | \
6489 PPC_SEGMENT_64B | PPC_SLBI)
6490 #define POWERPC_INSNS2_970GX (PPC_NONE)
6491 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
6492 #define POWERPC_MMU_970GX (POWERPC_MMU_64B)
6493 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6494 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
6495 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
6496 #define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6497 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6498 POWERPC_FLAG_BUS_CLK)
6499
6500 static int check_pow_970GX (CPUPPCState *env)
6501 {
6502 if (env->spr[SPR_HID0] & 0x00600000)
6503 return 1;
6504
6505 return 0;
6506 }
6507
6508 static void init_proc_970GX (CPUPPCState *env)
6509 {
6510 gen_spr_ne_601(env);
6511 gen_spr_7xx(env);
6512 /* Time base */
6513 gen_tbl(env);
6514 /* Hardware implementation registers */
6515 /* XXX : not implemented */
6516 spr_register(env, SPR_HID0, "HID0",
6517 SPR_NOACCESS, SPR_NOACCESS,
6518 &spr_read_generic, &spr_write_clear,
6519 0x60000000);
6520 /* XXX : not implemented */
6521 spr_register(env, SPR_HID1, "HID1",
6522 SPR_NOACCESS, SPR_NOACCESS,
6523 &spr_read_generic, &spr_write_generic,
6524 0x00000000);
6525 /* XXX : not implemented */
6526 spr_register(env, SPR_750FX_HID2, "HID2",
6527 SPR_NOACCESS, SPR_NOACCESS,
6528 &spr_read_generic, &spr_write_generic,
6529 0x00000000);
6530 /* XXX : not implemented */
6531 spr_register(env, SPR_970_HID5, "HID5",
6532 SPR_NOACCESS, SPR_NOACCESS,
6533 &spr_read_generic, &spr_write_generic,
6534 POWERPC970_HID5_INIT);
6535 /* XXX : not implemented */
6536 spr_register(env, SPR_L2CR, "L2CR",
6537 SPR_NOACCESS, SPR_NOACCESS,
6538 &spr_read_generic, &spr_write_generic,
6539 0x00000000);
6540 /* Memory management */
6541 /* XXX: not correct */
6542 gen_low_BATs(env);
6543 /* XXX : not implemented */
6544 spr_register(env, SPR_MMUCFG, "MMUCFG",
6545 SPR_NOACCESS, SPR_NOACCESS,
6546 &spr_read_generic, SPR_NOACCESS,
6547 0x00000000); /* TOFIX */
6548 /* XXX : not implemented */
6549 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6550 SPR_NOACCESS, SPR_NOACCESS,
6551 &spr_read_generic, &spr_write_generic,
6552 0x00000000); /* TOFIX */
6553 spr_register(env, SPR_HIOR, "SPR_HIOR",
6554 SPR_NOACCESS, SPR_NOACCESS,
6555 &spr_read_hior, &spr_write_hior,
6556 0x00000000);
6557 #if !defined(CONFIG_USER_ONLY)
6558 env->slb_nr = 32;
6559 #endif
6560 init_excp_970(env);
6561 env->dcache_line_size = 128;
6562 env->icache_line_size = 128;
6563 /* Allocate hardware IRQ controller */
6564 ppc970_irq_init(env);
6565 /* Can't find information on what this should be on reset. This
6566 * value is the one used by 74xx processors. */
6567 vscr_init(env, 0x00010000);
6568 }
6569
6570 /* PowerPC 970 MP */
6571 #define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6572 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6573 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6574 PPC_FLOAT_STFIWX | \
6575 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6576 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6577 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6578 PPC_64B | PPC_ALTIVEC | \
6579 PPC_SEGMENT_64B | PPC_SLBI)
6580 #define POWERPC_INSNS2_970MP (PPC_NONE)
6581 #define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6582 #define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6583 #define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6584 #define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6585 #define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6586 #define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6587 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6588 POWERPC_FLAG_BUS_CLK)
6589
6590 static int check_pow_970MP (CPUPPCState *env)
6591 {
6592 if (env->spr[SPR_HID0] & 0x01C00000)
6593 return 1;
6594
6595 return 0;
6596 }
6597
6598 static void init_proc_970MP (CPUPPCState *env)
6599 {
6600 gen_spr_ne_601(env);
6601 gen_spr_7xx(env);
6602 /* Time base */
6603 gen_tbl(env);
6604 /* Hardware implementation registers */
6605 /* XXX : not implemented */
6606 spr_register(env, SPR_HID0, "HID0",
6607 SPR_NOACCESS, SPR_NOACCESS,
6608 &spr_read_generic, &spr_write_clear,
6609 0x60000000);
6610 /* XXX : not implemented */
6611 spr_register(env, SPR_HID1, "HID1",
6612 SPR_NOACCESS, SPR_NOACCESS,
6613 &spr_read_generic, &spr_write_generic,
6614 0x00000000);
6615 /* XXX : not implemented */
6616 spr_register(env, SPR_750FX_HID2, "HID2",
6617 SPR_NOACCESS, SPR_NOACCESS,
6618 &spr_read_generic, &spr_write_generic,
6619 0x00000000);
6620 /* XXX : not implemented */
6621 spr_register(env, SPR_970_HID5, "HID5",
6622 SPR_NOACCESS, SPR_NOACCESS,
6623 &spr_read_generic, &spr_write_generic,
6624 POWERPC970_HID5_INIT);
6625 /* XXX : not implemented */
6626 spr_register(env, SPR_L2CR, "L2CR",
6627 SPR_NOACCESS, SPR_NOACCESS,
6628 &spr_read_generic, &spr_write_generic,
6629 0x00000000);
6630 /* Memory management */
6631 /* XXX: not correct */
6632 gen_low_BATs(env);
6633 /* XXX : not implemented */
6634 spr_register(env, SPR_MMUCFG, "MMUCFG",
6635 SPR_NOACCESS, SPR_NOACCESS,
6636 &spr_read_generic, SPR_NOACCESS,
6637 0x00000000); /* TOFIX */
6638 /* XXX : not implemented */
6639 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6640 SPR_NOACCESS, SPR_NOACCESS,
6641 &spr_read_generic, &spr_write_generic,
6642 0x00000000); /* TOFIX */
6643 spr_register(env, SPR_HIOR, "SPR_HIOR",
6644 SPR_NOACCESS, SPR_NOACCESS,
6645 &spr_read_hior, &spr_write_hior,
6646 0x00000000);
6647 #if !defined(CONFIG_USER_ONLY)
6648 env->slb_nr = 32;
6649 #endif
6650 init_excp_970(env);
6651 env->dcache_line_size = 128;
6652 env->icache_line_size = 128;
6653 /* Allocate hardware IRQ controller */
6654 ppc970_irq_init(env);
6655 /* Can't find information on what this should be on reset. This
6656 * value is the one used by 74xx processors. */
6657 vscr_init(env, 0x00010000);
6658 }
6659
6660 #if defined(TARGET_PPC64)
6661 /* POWER7 */
6662 #define POWERPC_INSNS_POWER7 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6663 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6664 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6665 PPC_FLOAT_STFIWX | \
6666 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6667 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6668 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6669 PPC_64B | PPC_ALTIVEC | \
6670 PPC_SEGMENT_64B | PPC_SLBI | \
6671 PPC_POPCNTB | PPC_POPCNTWD)
6672 #define POWERPC_INSNS2_POWER7 (PPC2_VSX | PPC2_DFP | PPC2_DBRX)
6673 #define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
6674 #define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
6675 #define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
6676 #define POWERPC_INPUT_POWER7 (PPC_FLAGS_INPUT_POWER7)
6677 #define POWERPC_BFDM_POWER7 (bfd_mach_ppc64)
6678 #define POWERPC_FLAG_POWER7 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6679 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6680 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR)
6681 #define check_pow_POWER7 check_pow_nocheck
6682
6683 static void init_proc_POWER7 (CPUPPCState *env)
6684 {
6685 gen_spr_ne_601(env);
6686 gen_spr_7xx(env);
6687 /* Time base */
6688 gen_tbl(env);
6689 /* Processor identification */
6690 spr_register(env, SPR_PIR, "PIR",
6691 SPR_NOACCESS, SPR_NOACCESS,
6692 &spr_read_generic, &spr_write_pir,
6693 0x00000000);
6694 #if !defined(CONFIG_USER_ONLY)
6695 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6696 spr_register(env, SPR_PURR, "PURR",
6697 &spr_read_purr, SPR_NOACCESS,
6698 &spr_read_purr, SPR_NOACCESS,
6699 0x00000000);
6700 spr_register(env, SPR_SPURR, "SPURR",
6701 &spr_read_purr, SPR_NOACCESS,
6702 &spr_read_purr, SPR_NOACCESS,
6703 0x00000000);
6704 spr_register(env, SPR_CFAR, "SPR_CFAR",
6705 SPR_NOACCESS, SPR_NOACCESS,
6706 &spr_read_cfar, &spr_write_cfar,
6707 0x00000000);
6708 spr_register(env, SPR_DSCR, "SPR_DSCR",
6709 SPR_NOACCESS, SPR_NOACCESS,
6710 &spr_read_generic, &spr_write_generic,
6711 0x00000000);
6712 #endif /* !CONFIG_USER_ONLY */
6713 /* Memory management */
6714 /* XXX : not implemented */
6715 spr_register(env, SPR_MMUCFG, "MMUCFG",
6716 SPR_NOACCESS, SPR_NOACCESS,
6717 &spr_read_generic, SPR_NOACCESS,
6718 0x00000000); /* TOFIX */
6719 /* XXX : not implemented */
6720 spr_register(env, SPR_CTRL, "SPR_CTRLT",
6721 SPR_NOACCESS, SPR_NOACCESS,
6722 &spr_read_generic, &spr_write_generic,
6723 0x80800000);
6724 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
6725 SPR_NOACCESS, SPR_NOACCESS,
6726 &spr_read_generic, &spr_write_generic,
6727 0x80800000);
6728 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6729 &spr_read_generic, &spr_write_generic,
6730 &spr_read_generic, &spr_write_generic,
6731 0x00000000);
6732 #if !defined(CONFIG_USER_ONLY)
6733 env->slb_nr = 32;
6734 #endif
6735 init_excp_POWER7(env);
6736 env->dcache_line_size = 128;
6737 env->icache_line_size = 128;
6738 /* Allocate hardware IRQ controller */
6739 ppcPOWER7_irq_init(env);
6740 /* Can't find information on what this should be on reset. This
6741 * value is the one used by 74xx processors. */
6742 vscr_init(env, 0x00010000);
6743 }
6744 #endif /* TARGET_PPC64 */
6745
6746 /* PowerPC 620 */
6747 #define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6748 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6749 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6750 PPC_FLOAT_STFIWX | \
6751 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6752 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6753 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6754 PPC_SEGMENT | PPC_EXTERN | \
6755 PPC_64B | PPC_SLBI)
6756 #define POWERPC_INSNS2_620 (PPC_NONE)
6757 #define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6758 //#define POWERPC_MMU_620 (POWERPC_MMU_620)
6759 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
6760 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
6761 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
6762 #define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
6763 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
6764 #define check_pow_620 check_pow_nocheck /* Check this */
6765
6766 __attribute__ (( unused ))
6767 static void init_proc_620 (CPUPPCState *env)
6768 {
6769 gen_spr_ne_601(env);
6770 gen_spr_620(env);
6771 /* Time base */
6772 gen_tbl(env);
6773 /* Hardware implementation registers */
6774 /* XXX : not implemented */
6775 spr_register(env, SPR_HID0, "HID0",
6776 SPR_NOACCESS, SPR_NOACCESS,
6777 &spr_read_generic, &spr_write_generic,
6778 0x00000000);
6779 /* Memory management */
6780 gen_low_BATs(env);
6781 init_excp_620(env);
6782 env->dcache_line_size = 64;
6783 env->icache_line_size = 64;
6784 /* Allocate hardware IRQ controller */
6785 ppc6xx_irq_init(env);
6786 }
6787 #endif /* defined (TARGET_PPC64) */
6788
6789 /* Default 32 bits PowerPC target will be 604 */
6790 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
6791 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
6792 #define POWERPC_INSNS2_PPC32 POWERPC_INSNS2_604
6793 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6794 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
6795 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6796 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
6797 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
6798 #define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
6799 #define check_pow_PPC32 check_pow_604
6800 #define init_proc_PPC32 init_proc_604
6801
6802 /* Default 64 bits PowerPC target will be 970 FX */
6803 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6804 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
6805 #define POWERPC_INSNS2_PPC64 POWERPC_INSNS2_970FX
6806 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6807 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6808 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6809 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
6810 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
6811 #define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
6812 #define check_pow_PPC64 check_pow_970FX
6813 #define init_proc_PPC64 init_proc_970FX
6814
6815 /* Default PowerPC target will be PowerPC 32 */
6816 #if defined (TARGET_PPC64) && 0 // XXX: TODO
6817 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6818 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6819 #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS2_PPC64
6820 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6821 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6822 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6823 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6824 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
6825 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
6826 #define check_pow_DEFAULT check_pow_PPC64
6827 #define init_proc_DEFAULT init_proc_PPC64
6828 #else
6829 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6830 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6831 #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS2_PPC32
6832 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6833 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6834 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6835 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6836 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
6837 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
6838 #define check_pow_DEFAULT check_pow_PPC32
6839 #define init_proc_DEFAULT init_proc_PPC32
6840 #endif
6841
6842 /*****************************************************************************/
6843 /* PVR definitions for most known PowerPC */
6844 enum {
6845 /* PowerPC 401 family */
6846 /* Generic PowerPC 401 */
6847 #define CPU_POWERPC_401 CPU_POWERPC_401G2
6848 /* PowerPC 401 cores */
6849 CPU_POWERPC_401A1 = 0x00210000,
6850 CPU_POWERPC_401B2 = 0x00220000,
6851 #if 0
6852 CPU_POWERPC_401B3 = xxx,
6853 #endif
6854 CPU_POWERPC_401C2 = 0x00230000,
6855 CPU_POWERPC_401D2 = 0x00240000,
6856 CPU_POWERPC_401E2 = 0x00250000,
6857 CPU_POWERPC_401F2 = 0x00260000,
6858 CPU_POWERPC_401G2 = 0x00270000,
6859 /* PowerPC 401 microcontrolers */
6860 #if 0
6861 CPU_POWERPC_401GF = xxx,
6862 #endif
6863 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
6864 /* IBM Processor for Network Resources */
6865 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
6866 #if 0
6867 CPU_POWERPC_XIPCHIP = xxx,
6868 #endif
6869 /* PowerPC 403 family */
6870 /* Generic PowerPC 403 */
6871 #define CPU_POWERPC_403 CPU_POWERPC_403GC
6872 /* PowerPC 403 microcontrollers */
6873 CPU_POWERPC_403GA = 0x00200011,
6874 CPU_POWERPC_403GB = 0x00200100,
6875 CPU_POWERPC_403GC = 0x00200200,
6876 CPU_POWERPC_403GCX = 0x00201400,
6877 #if 0
6878 CPU_POWERPC_403GP = xxx,
6879 #endif
6880 /* PowerPC 405 family */
6881 /* Generic PowerPC 405 */
6882 #define CPU_POWERPC_405 CPU_POWERPC_405D4
6883 /* PowerPC 405 cores */
6884 #if 0
6885 CPU_POWERPC_405A3 = xxx,
6886 #endif
6887 #if 0
6888 CPU_POWERPC_405A4 = xxx,
6889 #endif
6890 #if 0
6891 CPU_POWERPC_405B3 = xxx,
6892 #endif
6893 #if 0
6894 CPU_POWERPC_405B4 = xxx,
6895 #endif
6896 #if 0
6897 CPU_POWERPC_405C3 = xxx,
6898 #endif
6899 #if 0
6900 CPU_POWERPC_405C4 = xxx,
6901 #endif
6902 CPU_POWERPC_405D2 = 0x20010000,
6903 #if 0
6904 CPU_POWERPC_405D3 = xxx,
6905 #endif
6906 CPU_POWERPC_405D4 = 0x41810000,
6907 #if 0
6908 CPU_POWERPC_405D5 = xxx,
6909 #endif
6910 #if 0
6911 CPU_POWERPC_405E4 = xxx,
6912 #endif
6913 #if 0
6914 CPU_POWERPC_405F4 = xxx,
6915 #endif
6916 #if 0
6917 CPU_POWERPC_405F5 = xxx,
6918 #endif
6919 #if 0
6920 CPU_POWERPC_405F6 = xxx,
6921 #endif
6922 /* PowerPC 405 microcontrolers */
6923 /* XXX: missing 0x200108a0 */
6924 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6925 CPU_POWERPC_405CRa = 0x40110041,
6926 CPU_POWERPC_405CRb = 0x401100C5,
6927 CPU_POWERPC_405CRc = 0x40110145,
6928 CPU_POWERPC_405EP = 0x51210950,
6929 #if 0
6930 CPU_POWERPC_405EXr = xxx,
6931 #endif
6932 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
6933 #if 0
6934 CPU_POWERPC_405FX = xxx,
6935 #endif
6936 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6937 CPU_POWERPC_405GPa = 0x40110000,
6938 CPU_POWERPC_405GPb = 0x40110040,
6939 CPU_POWERPC_405GPc = 0x40110082,
6940 CPU_POWERPC_405GPd = 0x401100C4,
6941 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6942 CPU_POWERPC_405GPR = 0x50910951,
6943 #if 0
6944 CPU_POWERPC_405H = xxx,
6945 #endif
6946 #if 0
6947 CPU_POWERPC_405L = xxx,
6948 #endif
6949 CPU_POWERPC_405LP = 0x41F10000,
6950 #if 0
6951 CPU_POWERPC_405PM = xxx,
6952 #endif
6953 #if 0
6954 CPU_POWERPC_405PS = xxx,
6955 #endif
6956 #if 0
6957 CPU_POWERPC_405S = xxx,
6958 #endif
6959 /* IBM network processors */
6960 CPU_POWERPC_NPE405H = 0x414100C0,
6961 CPU_POWERPC_NPE405H2 = 0x41410140,
6962 CPU_POWERPC_NPE405L = 0x416100C0,
6963 CPU_POWERPC_NPE4GS3 = 0x40B10000,
6964 #if 0
6965 CPU_POWERPC_NPCxx1 = xxx,
6966 #endif
6967 #if 0
6968 CPU_POWERPC_NPR161 = xxx,
6969 #endif
6970 #if 0
6971 CPU_POWERPC_LC77700 = xxx,
6972 #endif
6973 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6974 #if 0
6975 CPU_POWERPC_STB01000 = xxx,
6976 #endif
6977 #if 0
6978 CPU_POWERPC_STB01010 = xxx,
6979 #endif
6980 #if 0
6981 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
6982 #endif
6983 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
6984 #if 0
6985 CPU_POWERPC_STB043 = xxx,
6986 #endif
6987 #if 0
6988 CPU_POWERPC_STB045 = xxx,
6989 #endif
6990 CPU_POWERPC_STB04 = 0x41810000,
6991 CPU_POWERPC_STB25 = 0x51510950,
6992 #if 0
6993 CPU_POWERPC_STB130 = xxx,
6994 #endif
6995 /* Xilinx cores */
6996 CPU_POWERPC_X2VP4 = 0x20010820,
6997 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
6998 CPU_POWERPC_X2VP20 = 0x20010860,
6999 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
7000 #if 0
7001 CPU_POWERPC_ZL10310 = xxx,
7002 #endif
7003 #if 0
7004 CPU_POWERPC_ZL10311 = xxx,
7005 #endif
7006 #if 0
7007 CPU_POWERPC_ZL10320 = xxx,
7008 #endif
7009 #if 0
7010 CPU_POWERPC_ZL10321 = xxx,
7011 #endif
7012 /* PowerPC 440 family */
7013 /* Generic PowerPC 440 */
7014 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
7015 /* PowerPC 440 cores */
7016 #if 0
7017 CPU_POWERPC_440A4 = xxx,
7018 #endif
7019 CPU_POWERPC_440_XILINX = 0x7ff21910,
7020 #if 0
7021 CPU_POWERPC_440A5 = xxx,
7022 #endif
7023 #if 0
7024 CPU_POWERPC_440B4 = xxx,
7025 #endif
7026 #if 0
7027 CPU_POWERPC_440F5 = xxx,
7028 #endif
7029 #if 0
7030 CPU_POWERPC_440G5 = xxx,
7031 #endif
7032 #if 0
7033 CPU_POWERPC_440H4 = xxx,
7034 #endif
7035 #if 0
7036 CPU_POWERPC_440H6 = xxx,
7037 #endif
7038 /* PowerPC 440 microcontrolers */
7039 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
7040 CPU_POWERPC_440EPa = 0x42221850,
7041 CPU_POWERPC_440EPb = 0x422218D3,
7042 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
7043 CPU_POWERPC_440GPb = 0x40120440,
7044 CPU_POWERPC_440GPc = 0x40120481,
7045 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
7046 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
7047 CPU_POWERPC_440GRX = 0x200008D0,
7048 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
7049 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
7050 CPU_POWERPC_440GXa = 0x51B21850,
7051 CPU_POWERPC_440GXb = 0x51B21851,
7052 CPU_POWERPC_440GXc = 0x51B21892,
7053 CPU_POWERPC_440GXf = 0x51B21894,
7054 #if 0
7055 CPU_POWERPC_440S = xxx,
7056 #endif
7057 CPU_POWERPC_440SP = 0x53221850,
7058 CPU_POWERPC_440SP2 = 0x53221891,
7059 CPU_POWERPC_440SPE = 0x53421890,
7060 /* PowerPC 460 family */
7061 #if 0
7062 /* Generic PowerPC 464 */
7063 #define CPU_POWERPC_464 CPU_POWERPC_464H90
7064 #endif
7065 /* PowerPC 464 microcontrolers */
7066 #if 0
7067 CPU_POWERPC_464H90 = xxx,
7068 #endif
7069 #if 0
7070 CPU_POWERPC_464H90FP = xxx,
7071 #endif
7072 /* Freescale embedded PowerPC cores */
7073 /* PowerPC MPC 5xx cores (aka RCPU) */
7074 CPU_POWERPC_MPC5xx = 0x00020020,
7075 #define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
7076 #define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
7077 #define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
7078 #define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
7079 #define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
7080 #define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
7081 #define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
7082 #define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
7083 #define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
7084 #define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
7085 #define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
7086 #define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
7087 #define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
7088 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
7089 CPU_POWERPC_MPC8xx = 0x00500000,
7090 #define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
7091 #define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
7092 #define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
7093 #define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
7094 #define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
7095 #define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
7096 #define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
7097 #define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
7098 #define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
7099 #define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
7100 #define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
7101 #define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
7102 #define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
7103 #define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
7104 #define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
7105 /* G2 cores (aka PowerQUICC-II) */
7106 CPU_POWERPC_G2 = 0x00810011,
7107 CPU_POWERPC_G2H4 = 0x80811010,
7108 CPU_POWERPC_G2gp = 0x80821010,
7109 CPU_POWERPC_G2ls = 0x90810010,
7110 CPU_POWERPC_MPC603 = 0x00810100,
7111 CPU_POWERPC_G2_HIP3 = 0x00810101,
7112 CPU_POWERPC_G2_HIP4 = 0x80811014,
7113 /* G2_LE core (aka PowerQUICC-II) */
7114 CPU_POWERPC_G2LE = 0x80820010,
7115 CPU_POWERPC_G2LEgp = 0x80822010,
7116 CPU_POWERPC_G2LEls = 0xA0822010,
7117 CPU_POWERPC_G2LEgp1 = 0x80822011,
7118 CPU_POWERPC_G2LEgp3 = 0x80822013,
7119 /* MPC52xx microcontrollers */
7120 /* XXX: MPC 5121 ? */
7121 #define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
7122 #define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
7123 #define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
7124 #define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
7125 #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
7126 #define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
7127 #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
7128 #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
7129 /* MPC82xx microcontrollers */
7130 #define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
7131 #define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
7132 #define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
7133 #define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
7134 #define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
7135 #define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
7136 #define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
7137 #define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
7138 #define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
7139 #define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
7140 #define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
7141 #define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
7142 #define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
7143 #define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
7144 #define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
7145 #define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
7146 #define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
7147 #define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
7148 #define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
7149 #define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
7150 #define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
7151 #define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
7152 #define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
7153 #define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
7154 #define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
7155 #define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
7156 #define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
7157 #define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
7158 #define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
7159 /* e200 family */
7160 /* e200 cores */
7161 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
7162 #if 0
7163 CPU_POWERPC_e200z0 = xxx,
7164 #endif
7165 #if 0
7166 CPU_POWERPC_e200z1 = xxx,
7167 #endif
7168 #if 0 /* ? */
7169 CPU_POWERPC_e200z3 = 0x81120000,
7170 #endif
7171 CPU_POWERPC_e200z5 = 0x81000000,
7172 CPU_POWERPC_e200z6 = 0x81120000,
7173 /* MPC55xx microcontrollers */
7174 #define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
7175 #if 0
7176 #define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
7177 #define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
7178 #define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
7179 #define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
7180 #define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
7181 #define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
7182 #define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
7183 #define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
7184 #define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
7185 #define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
7186 #define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
7187 #define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
7188 #define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
7189 #define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
7190 #endif
7191 #if 0
7192 #define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
7193 #define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
7194 #endif
7195 #define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
7196 #define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
7197 #define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
7198 #define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
7199 #define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
7200 #define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
7201 /* e300 family */
7202 /* e300 cores */
7203 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
7204 CPU_POWERPC_e300c1 = 0x00830010,
7205 CPU_POWERPC_e300c2 = 0x00840010,
7206 CPU_POWERPC_e300c3 = 0x00850010,
7207 CPU_POWERPC_e300c4 = 0x00860010,
7208 /* MPC83xx microcontrollers */
7209 #define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
7210 #define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
7211 #define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
7212 #define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
7213 #define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
7214 #define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
7215 /* e500 family */
7216 /* e500 cores */
7217 #define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
7218 #define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
7219 #define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
7220 CPU_POWERPC_e500v1_v10 = 0x80200010,
7221 CPU_POWERPC_e500v1_v20 = 0x80200020,
7222 CPU_POWERPC_e500v2_v10 = 0x80210010,
7223 CPU_POWERPC_e500v2_v11 = 0x80210011,
7224 CPU_POWERPC_e500v2_v20 = 0x80210020,
7225 CPU_POWERPC_e500v2_v21 = 0x80210021,
7226 CPU_POWERPC_e500v2_v22 = 0x80210022,
7227 CPU_POWERPC_e500v2_v30 = 0x80210030,
7228 CPU_POWERPC_e500mc = 0x80230020,
7229 CPU_POWERPC_e5500 = 0x80240020,
7230 /* MPC85xx microcontrollers */
7231 #define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
7232 #define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
7233 #define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
7234 #define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
7235 #define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
7236 #define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
7237 #define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
7238 #define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
7239 #define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
7240 #define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
7241 #define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
7242 #define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
7243 #define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
7244 #define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
7245 #define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
7246 #define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
7247 #define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
7248 #define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
7249 #define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
7250 #define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
7251 #define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
7252 #define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
7253 #define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
7254 #define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
7255 #define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
7256 #define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
7257 #define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
7258 #define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
7259 #define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
7260 #define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
7261 #define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
7262 #define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
7263 #define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
7264 #define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
7265 #define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
7266 #define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
7267 #define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
7268 #define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
7269 #define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
7270 #define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
7271 #define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
7272 #define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
7273 #define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
7274 #define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
7275 #define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
7276 #define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
7277 #define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
7278 #define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
7279 #define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
7280 #define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
7281 #define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
7282 #define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
7283 #define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
7284 #define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
7285 #define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
7286 #define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
7287 #define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
7288 #define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
7289 #define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
7290 #define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
7291 #define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
7292 #define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
7293 #define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
7294 #define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
7295 #define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
7296 #define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
7297 #define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
7298 #define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
7299 #define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
7300 #define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
7301 /* e600 family */
7302 /* e600 cores */
7303 CPU_POWERPC_e600 = 0x80040010,
7304 /* MPC86xx microcontrollers */
7305 #define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
7306 #define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
7307 #define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
7308 /* PowerPC 6xx cores */
7309 #define CPU_POWERPC_601 CPU_POWERPC_601_v2
7310 CPU_POWERPC_601_v0 = 0x00010001,
7311 CPU_POWERPC_601_v1 = 0x00010001,
7312 #define CPU_POWERPC_601v CPU_POWERPC_601_v2
7313 CPU_POWERPC_601_v2 = 0x00010002,
7314 CPU_POWERPC_602 = 0x00050100,
7315 CPU_POWERPC_603 = 0x00030100,
7316 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
7317 CPU_POWERPC_603E_v11 = 0x00060101,
7318 CPU_POWERPC_603E_v12 = 0x00060102,
7319 CPU_POWERPC_603E_v13 = 0x00060103,
7320 CPU_POWERPC_603E_v14 = 0x00060104,
7321 CPU_POWERPC_603E_v22 = 0x00060202,
7322 CPU_POWERPC_603E_v3 = 0x00060300,
7323 CPU_POWERPC_603E_v4 = 0x00060400,
7324 CPU_POWERPC_603E_v41 = 0x00060401,
7325 CPU_POWERPC_603E7t = 0x00071201,
7326 CPU_POWERPC_603E7v = 0x00070100,
7327 CPU_POWERPC_603E7v1 = 0x00070101,
7328 CPU_POWERPC_603E7v2 = 0x00070201,
7329 CPU_POWERPC_603E7 = 0x00070200,
7330 CPU_POWERPC_603P = 0x00070000,
7331 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
7332 /* XXX: missing 0x00040303 (604) */
7333 CPU_POWERPC_604 = 0x00040103,
7334 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
7335 /* XXX: missing 0x00091203 */
7336 /* XXX: missing 0x00092110 */
7337 /* XXX: missing 0x00092120 */
7338 CPU_POWERPC_604E_v10 = 0x00090100,
7339 CPU_POWERPC_604E_v22 = 0x00090202,
7340 CPU_POWERPC_604E_v24 = 0x00090204,
7341 /* XXX: missing 0x000a0100 */
7342 /* XXX: missing 0x00093102 */
7343 CPU_POWERPC_604R = 0x000a0101,
7344 #if 0
7345 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
7346 #endif
7347 /* PowerPC 740/750 cores (aka G3) */
7348 /* XXX: missing 0x00084202 */
7349 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
7350 CPU_POWERPC_7x0_v10 = 0x00080100,
7351 CPU_POWERPC_7x0_v20 = 0x00080200,
7352 CPU_POWERPC_7x0_v21 = 0x00080201,
7353 CPU_POWERPC_7x0_v22 = 0x00080202,
7354 CPU_POWERPC_7x0_v30 = 0x00080300,
7355 CPU_POWERPC_7x0_v31 = 0x00080301,
7356 CPU_POWERPC_740E = 0x00080100,
7357 CPU_POWERPC_750E = 0x00080200,
7358 CPU_POWERPC_7x0P = 0x10080000,
7359 /* XXX: missing 0x00087010 (CL ?) */
7360 #define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
7361 CPU_POWERPC_750CL_v10 = 0x00087200,
7362 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
7363 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
7364 CPU_POWERPC_750CX_v10 = 0x00082100,
7365 CPU_POWERPC_750CX_v20 = 0x00082200,
7366 CPU_POWERPC_750CX_v21 = 0x00082201,
7367 CPU_POWERPC_750CX_v22 = 0x00082202,
7368 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
7369 CPU_POWERPC_750CXE_v21 = 0x00082211,
7370 CPU_POWERPC_750CXE_v22 = 0x00082212,
7371 CPU_POWERPC_750CXE_v23 = 0x00082213,
7372 CPU_POWERPC_750CXE_v24 = 0x00082214,
7373 CPU_POWERPC_750CXE_v24b = 0x00083214,
7374 CPU_POWERPC_750CXE_v30 = 0x00082310,
7375 CPU_POWERPC_750CXE_v31 = 0x00082311,
7376 CPU_POWERPC_750CXE_v31b = 0x00083311,
7377 CPU_POWERPC_750CXR = 0x00083410,
7378 CPU_POWERPC_750FL = 0x70000203,
7379 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
7380 CPU_POWERPC_750FX_v10 = 0x70000100,
7381 CPU_POWERPC_750FX_v20 = 0x70000200,
7382 CPU_POWERPC_750FX_v21 = 0x70000201,
7383 CPU_POWERPC_750FX_v22 = 0x70000202,
7384 CPU_POWERPC_750FX_v23 = 0x70000203,
7385 CPU_POWERPC_750GL = 0x70020102,
7386 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
7387 CPU_POWERPC_750GX_v10 = 0x70020100,
7388 CPU_POWERPC_750GX_v11 = 0x70020101,
7389 CPU_POWERPC_750GX_v12 = 0x70020102,
7390 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
7391 CPU_POWERPC_750L_v20 = 0x00088200,
7392 CPU_POWERPC_750L_v21 = 0x00088201,
7393 CPU_POWERPC_750L_v22 = 0x00088202,
7394 CPU_POWERPC_750L_v30 = 0x00088300,
7395 CPU_POWERPC_750L_v32 = 0x00088302,
7396 /* PowerPC 745/755 cores */
7397 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
7398 CPU_POWERPC_7x5_v10 = 0x00083100,
7399 CPU_POWERPC_7x5_v11 = 0x00083101,
7400 CPU_POWERPC_7x5_v20 = 0x00083200,
7401 CPU_POWERPC_7x5_v21 = 0x00083201,
7402 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
7403 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
7404 CPU_POWERPC_7x5_v24 = 0x00083204,
7405 CPU_POWERPC_7x5_v25 = 0x00083205,
7406 CPU_POWERPC_7x5_v26 = 0x00083206,
7407 CPU_POWERPC_7x5_v27 = 0x00083207,
7408 CPU_POWERPC_7x5_v28 = 0x00083208,
7409 #if 0
7410 CPU_POWERPC_7x5P = xxx,
7411 #endif
7412 /* PowerPC 74xx cores (aka G4) */
7413 /* XXX: missing 0x000C1101 */
7414 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
7415 CPU_POWERPC_7400_v10 = 0x000C0100,
7416 CPU_POWERPC_7400_v11 = 0x000C0101,
7417 CPU_POWERPC_7400_v20 = 0x000C0200,
7418 CPU_POWERPC_7400_v21 = 0x000C0201,
7419 CPU_POWERPC_7400_v22 = 0x000C0202,
7420 CPU_POWERPC_7400_v26 = 0x000C0206,
7421 CPU_POWERPC_7400_v27 = 0x000C0207,
7422 CPU_POWERPC_7400_v28 = 0x000C0208,
7423 CPU_POWERPC_7400_v29 = 0x000C0209,
7424 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
7425 CPU_POWERPC_7410_v10 = 0x800C1100,
7426 CPU_POWERPC_7410_v11 = 0x800C1101,
7427 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
7428 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
7429 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
7430 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
7431 CPU_POWERPC_7448_v10 = 0x80040100,
7432 CPU_POWERPC_7448_v11 = 0x80040101,
7433 CPU_POWERPC_7448_v20 = 0x80040200,
7434 CPU_POWERPC_7448_v21 = 0x80040201,
7435 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
7436 CPU_POWERPC_7450_v10 = 0x80000100,
7437 CPU_POWERPC_7450_v11 = 0x80000101,
7438 CPU_POWERPC_7450_v12 = 0x80000102,
7439 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
7440 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
7441 #define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
7442 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
7443 /* XXX: this entry might be a bug in some documentation */
7444 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
7445 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
7446 CPU_POWERPC_74x5_v10 = 0x80010100,
7447 /* XXX: missing 0x80010200 */
7448 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
7449 CPU_POWERPC_74x5_v32 = 0x80010302,
7450 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
7451 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
7452 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
7453 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
7454 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
7455 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
7456 #define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
7457 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
7458 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
7459 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
7460 /* 64 bits PowerPC */
7461 #if defined(TARGET_PPC64)
7462 CPU_POWERPC_620 = 0x00140000,
7463 CPU_POWERPC_630 = 0x00400000,
7464 CPU_POWERPC_631 = 0x00410104,
7465 CPU_POWERPC_POWER4 = 0x00350000,
7466 CPU_POWERPC_POWER4P = 0x00380000,
7467 /* XXX: missing 0x003A0201 */
7468 CPU_POWERPC_POWER5 = 0x003A0203,
7469 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
7470 CPU_POWERPC_POWER5P = 0x003B0000,
7471 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
7472 CPU_POWERPC_POWER6 = 0x003E0000,
7473 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
7474 CPU_POWERPC_POWER6A = 0x0F000002,
7475 #define CPU_POWERPC_POWER7 CPU_POWERPC_POWER7_v20
7476 CPU_POWERPC_POWER7_v20 = 0x003F0200,
7477 CPU_POWERPC_POWER7_v21 = 0x003F0201,
7478 CPU_POWERPC_POWER7_v23 = 0x003F0203,
7479 CPU_POWERPC_970 = 0x00390202,
7480 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
7481 CPU_POWERPC_970FX_v10 = 0x00391100,
7482 CPU_POWERPC_970FX_v20 = 0x003C0200,
7483 CPU_POWERPC_970FX_v21 = 0x003C0201,
7484 CPU_POWERPC_970FX_v30 = 0x003C0300,
7485 CPU_POWERPC_970FX_v31 = 0x003C0301,
7486 CPU_POWERPC_970GX = 0x00450000,
7487 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
7488 CPU_POWERPC_970MP_v10 = 0x00440100,
7489 CPU_POWERPC_970MP_v11 = 0x00440101,
7490 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
7491 CPU_POWERPC_CELL_v10 = 0x00700100,
7492 CPU_POWERPC_CELL_v20 = 0x00700400,
7493 CPU_POWERPC_CELL_v30 = 0x00700500,
7494 CPU_POWERPC_CELL_v31 = 0x00700501,
7495 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
7496 CPU_POWERPC_RS64 = 0x00330000,
7497 CPU_POWERPC_RS64II = 0x00340000,
7498 CPU_POWERPC_RS64III = 0x00360000,
7499 CPU_POWERPC_RS64IV = 0x00370000,
7500 #endif /* defined(TARGET_PPC64) */
7501 /* Original POWER */
7502 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7503 * POWER2 (RIOS2) & RSC2 (P2SC) here
7504 */
7505 #if 0
7506 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
7507 #endif
7508 #if 0
7509 CPU_POWER2 = xxx, /* 0x40000 ? */
7510 #endif
7511 /* PA Semi core */
7512 CPU_POWERPC_PA6T = 0x00900000,
7513 };
7514
7515 /* System version register (used on MPC 8xxx) */
7516 enum {
7517 POWERPC_SVR_NONE = 0x00000000,
7518 #define POWERPC_SVR_52xx POWERPC_SVR_5200
7519 #define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
7520 POWERPC_SVR_5200_v10 = 0x80110010,
7521 POWERPC_SVR_5200_v11 = 0x80110011,
7522 POWERPC_SVR_5200_v12 = 0x80110012,
7523 #define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
7524 POWERPC_SVR_5200B_v20 = 0x80110020,
7525 POWERPC_SVR_5200B_v21 = 0x80110021,
7526 #define POWERPC_SVR_55xx POWERPC_SVR_5567
7527 #if 0
7528 POWERPC_SVR_5533 = xxx,
7529 #endif
7530 #if 0
7531 POWERPC_SVR_5534 = xxx,
7532 #endif
7533 #if 0
7534 POWERPC_SVR_5553 = xxx,
7535 #endif
7536 #if 0
7537 POWERPC_SVR_5554 = xxx,
7538 #endif
7539 #if 0
7540 POWERPC_SVR_5561 = xxx,
7541 #endif
7542 #if 0
7543 POWERPC_SVR_5565 = xxx,
7544 #endif
7545 #if 0
7546 POWERPC_SVR_5566 = xxx,
7547 #endif
7548 #if 0
7549 POWERPC_SVR_5567 = xxx,
7550 #endif
7551 #if 0
7552 POWERPC_SVR_8313 = xxx,
7553 #endif
7554 #if 0
7555 POWERPC_SVR_8313E = xxx,
7556 #endif
7557 #if 0
7558 POWERPC_SVR_8314 = xxx,
7559 #endif
7560 #if 0
7561 POWERPC_SVR_8314E = xxx,
7562 #endif
7563 #if 0
7564 POWERPC_SVR_8315 = xxx,
7565 #endif
7566 #if 0
7567 POWERPC_SVR_8315E = xxx,
7568 #endif
7569 #if 0
7570 POWERPC_SVR_8321 = xxx,
7571 #endif
7572 #if 0
7573 POWERPC_SVR_8321E = xxx,
7574 #endif
7575 #if 0
7576 POWERPC_SVR_8323 = xxx,
7577 #endif
7578 #if 0
7579 POWERPC_SVR_8323E = xxx,
7580 #endif
7581 POWERPC_SVR_8343 = 0x80570010,
7582 POWERPC_SVR_8343A = 0x80570030,
7583 POWERPC_SVR_8343E = 0x80560010,
7584 POWERPC_SVR_8343EA = 0x80560030,
7585 #define POWERPC_SVR_8347 POWERPC_SVR_8347T
7586 POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
7587 POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
7588 #define POWERPC_SVR_8347A POWERPC_SVR_8347AT
7589 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7590 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
7591 #define POWERPC_SVR_8347E POWERPC_SVR_8347ET
7592 POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
7593 POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
7594 #define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
7595 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7596 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7597 POWERPC_SVR_8349 = 0x80510010,
7598 POWERPC_SVR_8349A = 0x80510030,
7599 POWERPC_SVR_8349E = 0x80500010,
7600 POWERPC_SVR_8349EA = 0x80500030,
7601 #if 0
7602 POWERPC_SVR_8358E = xxx,
7603 #endif
7604 #if 0
7605 POWERPC_SVR_8360E = xxx,
7606 #endif
7607 #define POWERPC_SVR_E500 0x40000000
7608 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7609 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7610 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7611 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7612 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7613 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
7614 #define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
7615 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7616 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
7617 #define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
7618 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7619 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
7620 #define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
7621 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7622 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7623 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
7624 #define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
7625 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7626 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
7627 #define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
7628 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7629 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
7630 #define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
7631 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7632 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7633 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7634 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
7635 #define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
7636 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7637 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7638 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7639 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
7640 #define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
7641 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7642 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
7643 #define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
7644 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7645 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
7646 #define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
7647 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7648 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
7649 #define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
7650 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7651 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
7652 #define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
7653 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7654 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
7655 #define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
7656 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7657 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7658 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7659 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
7660 #define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
7661 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7662 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7663 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7664 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
7665 #define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
7666 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7667 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
7668 #define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
7669 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7670 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
7671 #define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
7672 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7673 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7674 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7675 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7676 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7677 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7678 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7679 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7680 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
7681 #if 0
7682 POWERPC_SVR_8610 = xxx,
7683 #endif
7684 POWERPC_SVR_8641 = 0x80900021,
7685 POWERPC_SVR_8641D = 0x80900121,
7686 };
7687
7688 /*****************************************************************************/
7689 /* PowerPC CPU definitions */
7690 #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
7691 { \
7692 .name = _name, \
7693 .pvr = _pvr, \
7694 .svr = _svr, \
7695 .insns_flags = glue(POWERPC_INSNS_,_type), \
7696 .insns_flags2 = glue(POWERPC_INSNS2_,_type), \
7697 .msr_mask = glue(POWERPC_MSRM_,_type), \
7698 .mmu_model = glue(POWERPC_MMU_,_type), \
7699 .excp_model = glue(POWERPC_EXCP_,_type), \
7700 .bus_model = glue(POWERPC_INPUT_,_type), \
7701 .bfd_mach = glue(POWERPC_BFDM_,_type), \
7702 .flags = glue(POWERPC_FLAG_,_type), \
7703 .init_proc = &glue(init_proc_,_type), \
7704 .check_pow = &glue(check_pow_,_type), \
7705 }
7706 #define POWERPC_DEF(_name, _pvr, _type) \
7707 POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
7708
7709 static const ppc_def_t ppc_defs[] = {
7710 /* Embedded PowerPC */
7711 /* PowerPC 401 family */
7712 /* Generic PowerPC 401 */
7713 POWERPC_DEF("401", CPU_POWERPC_401, 401),
7714 /* PowerPC 401 cores */
7715 /* PowerPC 401A1 */
7716 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
7717 /* PowerPC 401B2 */
7718 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
7719 #if defined (TODO)
7720 /* PowerPC 401B3 */
7721 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
7722 #endif
7723 /* PowerPC 401C2 */
7724 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
7725 /* PowerPC 401D2 */
7726 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
7727 /* PowerPC 401E2 */
7728 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
7729 /* PowerPC 401F2 */
7730 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
7731 /* PowerPC 401G2 */
7732 /* XXX: to be checked */
7733 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
7734 /* PowerPC 401 microcontrolers */
7735 #if defined (TODO)
7736 /* PowerPC 401GF */
7737 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
7738 #endif
7739 /* IOP480 (401 microcontroler) */
7740 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
7741 /* IBM Processor for Network Resources */
7742 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
7743 #if defined (TODO)
7744 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
7745 #endif
7746 /* PowerPC 403 family */
7747 /* Generic PowerPC 403 */
7748 POWERPC_DEF("403", CPU_POWERPC_403, 403),
7749 /* PowerPC 403 microcontrolers */
7750 /* PowerPC 403 GA */
7751 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
7752 /* PowerPC 403 GB */
7753 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
7754 /* PowerPC 403 GC */
7755 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
7756 /* PowerPC 403 GCX */
7757 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
7758 #if defined (TODO)
7759 /* PowerPC 403 GP */
7760 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
7761 #endif
7762 /* PowerPC 405 family */
7763 /* Generic PowerPC 405 */
7764 POWERPC_DEF("405", CPU_POWERPC_405, 405),
7765 /* PowerPC 405 cores */
7766 #if defined (TODO)
7767 /* PowerPC 405 A3 */
7768 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
7769 #endif
7770 #if defined (TODO)
7771 /* PowerPC 405 A4 */
7772 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
7773 #endif
7774 #if defined (TODO)
7775 /* PowerPC 405 B3 */
7776 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
7777 #endif
7778 #if defined (TODO)
7779 /* PowerPC 405 B4 */
7780 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
7781 #endif
7782 #if defined (TODO)
7783 /* PowerPC 405 C3 */
7784 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
7785 #endif
7786 #if defined (TODO)
7787 /* PowerPC 405 C4 */
7788 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
7789 #endif
7790 /* PowerPC 405 D2 */
7791 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
7792 #if defined (TODO)
7793 /* PowerPC 405 D3 */
7794 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
7795 #endif
7796 /* PowerPC 405 D4 */
7797 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
7798 #if defined (TODO)
7799 /* PowerPC 405 D5 */
7800 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
7801 #endif
7802 #if defined (TODO)
7803 /* PowerPC 405 E4 */
7804 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
7805 #endif
7806 #if defined (TODO)
7807 /* PowerPC 405 F4 */
7808 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
7809 #endif
7810 #if defined (TODO)
7811 /* PowerPC 405 F5 */
7812 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
7813 #endif
7814 #if defined (TODO)
7815 /* PowerPC 405 F6 */
7816 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
7817 #endif
7818 /* PowerPC 405 microcontrolers */
7819 /* PowerPC 405 CR */
7820 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
7821 /* PowerPC 405 CRa */
7822 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
7823 /* PowerPC 405 CRb */
7824 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
7825 /* PowerPC 405 CRc */
7826 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
7827 /* PowerPC 405 EP */
7828 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
7829 #if defined(TODO)
7830 /* PowerPC 405 EXr */
7831 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
7832 #endif
7833 /* PowerPC 405 EZ */
7834 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
7835 #if defined(TODO)
7836 /* PowerPC 405 FX */
7837 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
7838 #endif
7839 /* PowerPC 405 GP */
7840 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
7841 /* PowerPC 405 GPa */
7842 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
7843 /* PowerPC 405 GPb */
7844 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
7845 /* PowerPC 405 GPc */
7846 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
7847 /* PowerPC 405 GPd */
7848 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
7849 /* PowerPC 405 GPe */
7850 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
7851 /* PowerPC 405 GPR */
7852 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
7853 #if defined(TODO)
7854 /* PowerPC 405 H */
7855 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
7856 #endif
7857 #if defined(TODO)
7858 /* PowerPC 405 L */
7859 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
7860 #endif
7861 /* PowerPC 405 LP */
7862 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
7863 #if defined(TODO)
7864 /* PowerPC 405 PM */
7865 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
7866 #endif
7867 #if defined(TODO)
7868 /* PowerPC 405 PS */
7869 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
7870 #endif
7871 #if defined(TODO)
7872 /* PowerPC 405 S */
7873 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
7874 #endif
7875 /* Npe405 H */
7876 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
7877 /* Npe405 H2 */
7878 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
7879 /* Npe405 L */
7880 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
7881 /* Npe4GS3 */
7882 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
7883 #if defined (TODO)
7884 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
7885 #endif
7886 #if defined (TODO)
7887 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
7888 #endif
7889 #if defined (TODO)
7890 /* PowerPC LC77700 (Sanyo) */
7891 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
7892 #endif
7893 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7894 #if defined (TODO)
7895 /* STB010000 */
7896 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
7897 #endif
7898 #if defined (TODO)
7899 /* STB01010 */
7900 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
7901 #endif
7902 #if defined (TODO)
7903 /* STB0210 */
7904 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
7905 #endif
7906 /* STB03xx */
7907 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
7908 #if defined (TODO)
7909 /* STB043x */
7910 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
7911 #endif
7912 #if defined (TODO)
7913 /* STB045x */
7914 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
7915 #endif
7916 /* STB04xx */
7917 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
7918 /* STB25xx */
7919 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
7920 #if defined (TODO)
7921 /* STB130 */
7922 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
7923 #endif
7924 /* Xilinx PowerPC 405 cores */
7925 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
7926 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
7927 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
7928 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
7929 #if defined (TODO)
7930 /* Zarlink ZL10310 */
7931 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
7932 #endif
7933 #if defined (TODO)
7934 /* Zarlink ZL10311 */
7935 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
7936 #endif
7937 #if defined (TODO)
7938 /* Zarlink ZL10320 */
7939 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
7940 #endif
7941 #if defined (TODO)
7942 /* Zarlink ZL10321 */
7943 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
7944 #endif
7945 /* PowerPC 440 family */
7946 #if defined(TODO_USER_ONLY)
7947 /* Generic PowerPC 440 */
7948 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
7949 #endif
7950 /* PowerPC 440 cores */
7951 #if defined (TODO)
7952 /* PowerPC 440 A4 */
7953 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
7954 #endif
7955 /* PowerPC 440 Xilinx 5 */
7956 POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5),
7957 #if defined (TODO)
7958 /* PowerPC 440 A5 */
7959 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
7960 #endif
7961 #if defined (TODO)
7962 /* PowerPC 440 B4 */
7963 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
7964 #endif
7965 #if defined (TODO)
7966 /* PowerPC 440 G4 */
7967 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
7968 #endif
7969 #if defined (TODO)
7970 /* PowerPC 440 F5 */
7971 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
7972 #endif
7973 #if defined (TODO)
7974 /* PowerPC 440 G5 */
7975 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
7976 #endif
7977 #if defined (TODO)
7978 /* PowerPC 440H4 */
7979 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
7980 #endif
7981 #if defined (TODO)
7982 /* PowerPC 440H6 */
7983 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
7984 #endif
7985 /* PowerPC 440 microcontrolers */
7986 /* PowerPC 440 EP */
7987 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
7988 /* PowerPC 440 EPa */
7989 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
7990 /* PowerPC 440 EPb */
7991 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
7992 /* PowerPC 440 EPX */
7993 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
7994 #if defined(TODO_USER_ONLY)
7995 /* PowerPC 440 GP */
7996 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
7997 #endif
7998 #if defined(TODO_USER_ONLY)
7999 /* PowerPC 440 GPb */
8000 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
8001 #endif
8002 #if defined(TODO_USER_ONLY)
8003 /* PowerPC 440 GPc */
8004 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
8005 #endif
8006 #if defined(TODO_USER_ONLY)
8007 /* PowerPC 440 GR */
8008 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
8009 #endif
8010 #if defined(TODO_USER_ONLY)
8011 /* PowerPC 440 GRa */
8012 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
8013 #endif
8014 #if defined(TODO_USER_ONLY)
8015 /* PowerPC 440 GRX */
8016 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
8017 #endif
8018 #if defined(TODO_USER_ONLY)
8019 /* PowerPC 440 GX */
8020 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
8021 #endif
8022 #if defined(TODO_USER_ONLY)
8023 /* PowerPC 440 GXa */
8024 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
8025 #endif
8026 #if defined(TODO_USER_ONLY)
8027 /* PowerPC 440 GXb */
8028 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
8029 #endif
8030 #if defined(TODO_USER_ONLY)
8031 /* PowerPC 440 GXc */
8032 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
8033 #endif
8034 #if defined(TODO_USER_ONLY)
8035 /* PowerPC 440 GXf */
8036 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
8037 #endif
8038 #if defined(TODO)
8039 /* PowerPC 440 S */
8040 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
8041 #endif
8042 #if defined(TODO_USER_ONLY)
8043 /* PowerPC 440 SP */
8044 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
8045 #endif
8046 #if defined(TODO_USER_ONLY)
8047 /* PowerPC 440 SP2 */
8048 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
8049 #endif
8050 #if defined(TODO_USER_ONLY)
8051 /* PowerPC 440 SPE */
8052 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
8053 #endif
8054 /* PowerPC 460 family */
8055 #if defined (TODO)
8056 /* Generic PowerPC 464 */
8057 POWERPC_DEF("464", CPU_POWERPC_464, 460),
8058 #endif
8059 /* PowerPC 464 microcontrolers */
8060 #if defined (TODO)
8061 /* PowerPC 464H90 */
8062 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
8063 #endif
8064 #if defined (TODO)
8065 /* PowerPC 464H90F */
8066 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
8067 #endif
8068 /* Freescale embedded PowerPC cores */
8069 /* MPC5xx family (aka RCPU) */
8070 #if defined(TODO_USER_ONLY)
8071 /* Generic MPC5xx core */
8072 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
8073 #endif
8074 #if defined(TODO_USER_ONLY)
8075 /* Codename for MPC5xx core */
8076 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
8077 #endif
8078 /* MPC5xx microcontrollers */
8079 #if defined(TODO_USER_ONLY)
8080 /* MGT560 */
8081 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
8082 #endif
8083 #if defined(TODO_USER_ONLY)
8084 /* MPC509 */
8085 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
8086 #endif
8087 #if defined(TODO_USER_ONLY)
8088 /* MPC533 */
8089 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
8090 #endif
8091 #if defined(TODO_USER_ONLY)
8092 /* MPC534 */
8093 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
8094 #endif
8095 #if defined(TODO_USER_ONLY)
8096 /* MPC555 */
8097 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
8098 #endif
8099 #if defined(TODO_USER_ONLY)
8100 /* MPC556 */
8101 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
8102 #endif
8103 #if defined(TODO_USER_ONLY)
8104 /* MPC560 */
8105 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
8106 #endif
8107 #if defined(TODO_USER_ONLY)
8108 /* MPC561 */
8109 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
8110 #endif
8111 #if defined(TODO_USER_ONLY)
8112 /* MPC562 */
8113 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
8114 #endif
8115 #if defined(TODO_USER_ONLY)
8116 /* MPC563 */
8117 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
8118 #endif
8119 #if defined(TODO_USER_ONLY)
8120 /* MPC564 */
8121 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
8122 #endif
8123 #if defined(TODO_USER_ONLY)
8124 /* MPC565 */
8125 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
8126 #endif
8127 #if defined(TODO_USER_ONLY)
8128 /* MPC566 */
8129 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
8130 #endif
8131 /* MPC8xx family (aka PowerQUICC) */
8132 #if defined(TODO_USER_ONLY)
8133 /* Generic MPC8xx core */
8134 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
8135 #endif
8136 #if defined(TODO_USER_ONLY)
8137 /* Codename for MPC8xx core */
8138 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
8139 #endif
8140 /* MPC8xx microcontrollers */
8141 #if defined(TODO_USER_ONLY)
8142 /* MGT823 */
8143 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
8144 #endif
8145 #if defined(TODO_USER_ONLY)
8146 /* MPC821 */
8147 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
8148 #endif
8149 #if defined(TODO_USER_ONLY)
8150 /* MPC823 */
8151 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
8152 #endif
8153 #if defined(TODO_USER_ONLY)
8154 /* MPC850 */
8155 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
8156 #endif
8157 #if defined(TODO_USER_ONLY)
8158 /* MPC852T */
8159 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
8160 #endif
8161 #if defined(TODO_USER_ONLY)
8162 /* MPC855T */
8163 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
8164 #endif
8165 #if defined(TODO_USER_ONLY)
8166 /* MPC857 */
8167 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
8168 #endif
8169 #if defined(TODO_USER_ONLY)
8170 /* MPC859 */
8171 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
8172 #endif
8173 #if defined(TODO_USER_ONLY)
8174 /* MPC860 */
8175 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
8176 #endif
8177 #if defined(TODO_USER_ONLY)
8178 /* MPC862 */
8179 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
8180 #endif
8181 #if defined(TODO_USER_ONLY)
8182 /* MPC866 */
8183 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
8184 #endif
8185 #if defined(TODO_USER_ONLY)
8186 /* MPC870 */
8187 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
8188 #endif
8189 #if defined(TODO_USER_ONLY)
8190 /* MPC875 */
8191 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
8192 #endif
8193 #if defined(TODO_USER_ONLY)
8194 /* MPC880 */
8195 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
8196 #endif
8197 #if defined(TODO_USER_ONLY)
8198 /* MPC885 */
8199 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
8200 #endif
8201 /* MPC82xx family (aka PowerQUICC-II) */
8202 /* Generic MPC52xx core */
8203 POWERPC_DEF_SVR("MPC52xx",
8204 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
8205 /* Generic MPC82xx core */
8206 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
8207 /* Codename for MPC82xx */
8208 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
8209 /* PowerPC G2 core */
8210 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
8211 /* PowerPC G2 H4 core */
8212 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
8213 /* PowerPC G2 GP core */
8214 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
8215 /* PowerPC G2 LS core */
8216 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
8217 /* PowerPC G2 HiP3 core */
8218 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
8219 /* PowerPC G2 HiP4 core */
8220 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
8221 /* PowerPC MPC603 core */
8222 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
8223 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
8224 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
8225 /* PowerPC G2LE GP core */
8226 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
8227 /* PowerPC G2LE LS core */
8228 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
8229 /* PowerPC G2LE GP1 core */
8230 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
8231 /* PowerPC G2LE GP3 core */
8232 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
8233 /* PowerPC MPC603 microcontrollers */
8234 /* MPC8240 */
8235 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
8236 /* PowerPC G2 microcontrollers */
8237 #if defined(TODO)
8238 /* MPC5121 */
8239 POWERPC_DEF_SVR("MPC5121",
8240 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
8241 #endif
8242 /* MPC5200 */
8243 POWERPC_DEF_SVR("MPC5200",
8244 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
8245 /* MPC5200 v1.0 */
8246 POWERPC_DEF_SVR("MPC5200_v10",
8247 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
8248 /* MPC5200 v1.1 */
8249 POWERPC_DEF_SVR("MPC5200_v11",
8250 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
8251 /* MPC5200 v1.2 */
8252 POWERPC_DEF_SVR("MPC5200_v12",
8253 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
8254 /* MPC5200B */
8255 POWERPC_DEF_SVR("MPC5200B",
8256 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
8257 /* MPC5200B v2.0 */
8258 POWERPC_DEF_SVR("MPC5200B_v20",
8259 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
8260 /* MPC5200B v2.1 */
8261 POWERPC_DEF_SVR("MPC5200B_v21",
8262 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
8263 /* MPC8241 */
8264 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
8265 /* MPC8245 */
8266 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
8267 /* MPC8247 */
8268 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
8269 /* MPC8248 */
8270 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
8271 /* MPC8250 */
8272 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
8273 /* MPC8250 HiP3 */
8274 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
8275 /* MPC8250 HiP4 */
8276 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
8277 /* MPC8255 */
8278 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
8279 /* MPC8255 HiP3 */
8280 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
8281 /* MPC8255 HiP4 */
8282 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
8283 /* MPC8260 */
8284 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
8285 /* MPC8260 HiP3 */
8286 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
8287 /* MPC8260 HiP4 */
8288 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
8289 /* MPC8264 */
8290 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
8291 /* MPC8264 HiP3 */
8292 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
8293 /* MPC8264 HiP4 */
8294 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
8295 /* MPC8265 */
8296 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
8297 /* MPC8265 HiP3 */
8298 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
8299 /* MPC8265 HiP4 */
8300 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
8301 /* MPC8266 */
8302 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
8303 /* MPC8266 HiP3 */
8304 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
8305 /* MPC8266 HiP4 */
8306 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
8307 /* MPC8270 */
8308 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
8309 /* MPC8271 */
8310 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
8311 /* MPC8272 */
8312 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
8313 /* MPC8275 */
8314 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
8315 /* MPC8280 */
8316 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
8317 /* e200 family */
8318 /* Generic PowerPC e200 core */
8319 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
8320 /* Generic MPC55xx core */
8321 #if defined (TODO)
8322 POWERPC_DEF_SVR("MPC55xx",
8323 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
8324 #endif
8325 #if defined (TODO)
8326 /* PowerPC e200z0 core */
8327 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
8328 #endif
8329 #if defined (TODO)
8330 /* PowerPC e200z1 core */
8331 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
8332 #endif
8333 #if defined (TODO)
8334 /* PowerPC e200z3 core */
8335 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
8336 #endif
8337 /* PowerPC e200z5 core */
8338 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
8339 /* PowerPC e200z6 core */
8340 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
8341 /* PowerPC e200 microcontrollers */
8342 #if defined (TODO)
8343 /* MPC5514E */
8344 POWERPC_DEF_SVR("MPC5514E",
8345 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
8346 #endif
8347 #if defined (TODO)
8348 /* MPC5514E v0 */
8349 POWERPC_DEF_SVR("MPC5514E_v0",
8350 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
8351 #endif
8352 #if defined (TODO)
8353 /* MPC5514E v1 */
8354 POWERPC_DEF_SVR("MPC5514E_v1",
8355 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
8356 #endif
8357 #if defined (TODO)
8358 /* MPC5514G */
8359 POWERPC_DEF_SVR("MPC5514G",
8360 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
8361 #endif
8362 #if defined (TODO)
8363 /* MPC5514G v0 */
8364 POWERPC_DEF_SVR("MPC5514G_v0",
8365 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
8366 #endif
8367 #if defined (TODO)
8368 /* MPC5514G v1 */
8369 POWERPC_DEF_SVR("MPC5514G_v1",
8370 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
8371 #endif
8372 #if defined (TODO)
8373 /* MPC5515S */
8374 POWERPC_DEF_SVR("MPC5515S",
8375 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
8376 #endif
8377 #if defined (TODO)
8378 /* MPC5516E */
8379 POWERPC_DEF_SVR("MPC5516E",
8380 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
8381 #endif
8382 #if defined (TODO)
8383 /* MPC5516E v0 */
8384 POWERPC_DEF_SVR("MPC5516E_v0",
8385 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
8386 #endif
8387 #if defined (TODO)
8388 /* MPC5516E v1 */
8389 POWERPC_DEF_SVR("MPC5516E_v1",
8390 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
8391 #endif
8392 #if defined (TODO)
8393 /* MPC5516G */
8394 POWERPC_DEF_SVR("MPC5516G",
8395 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
8396 #endif
8397 #if defined (TODO)
8398 /* MPC5516G v0 */
8399 POWERPC_DEF_SVR("MPC5516G_v0",
8400 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
8401 #endif
8402 #if defined (TODO)
8403 /* MPC5516G v1 */
8404 POWERPC_DEF_SVR("MPC5516G_v1",
8405 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
8406 #endif
8407 #if defined (TODO)
8408 /* MPC5516S */
8409 POWERPC_DEF_SVR("MPC5516S",
8410 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
8411 #endif
8412 #if defined (TODO)
8413 /* MPC5533 */
8414 POWERPC_DEF_SVR("MPC5533",
8415 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
8416 #endif
8417 #if defined (TODO)
8418 /* MPC5534 */
8419 POWERPC_DEF_SVR("MPC5534",
8420 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
8421 #endif
8422 #if defined (TODO)
8423 /* MPC5553 */
8424 POWERPC_DEF_SVR("MPC5553",
8425 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
8426 #endif
8427 #if defined (TODO)
8428 /* MPC5554 */
8429 POWERPC_DEF_SVR("MPC5554",
8430 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
8431 #endif
8432 #if defined (TODO)
8433 /* MPC5561 */
8434 POWERPC_DEF_SVR("MPC5561",
8435 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
8436 #endif
8437 #if defined (TODO)
8438 /* MPC5565 */
8439 POWERPC_DEF_SVR("MPC5565",
8440 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
8441 #endif
8442 #if defined (TODO)
8443 /* MPC5566 */
8444 POWERPC_DEF_SVR("MPC5566",
8445 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
8446 #endif
8447 #if defined (TODO)
8448 /* MPC5567 */
8449 POWERPC_DEF_SVR("MPC5567",
8450 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
8451 #endif
8452 /* e300 family */
8453 /* Generic PowerPC e300 core */
8454 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
8455 /* PowerPC e300c1 core */
8456 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
8457 /* PowerPC e300c2 core */
8458 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
8459 /* PowerPC e300c3 core */
8460 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
8461 /* PowerPC e300c4 core */
8462 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
8463 /* PowerPC e300 microcontrollers */
8464 #if defined (TODO)
8465 /* MPC8313 */
8466 POWERPC_DEF_SVR("MPC8313",
8467 CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300),
8468 #endif
8469 #if defined (TODO)
8470 /* MPC8313E */
8471 POWERPC_DEF_SVR("MPC8313E",
8472 CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300),
8473 #endif
8474 #if defined (TODO)
8475 /* MPC8314 */
8476 POWERPC_DEF_SVR("MPC8314",
8477 CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300),
8478 #endif
8479 #if defined (TODO)
8480 /* MPC8314E */
8481 POWERPC_DEF_SVR("MPC8314E",
8482 CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300),
8483 #endif
8484 #if defined (TODO)
8485 /* MPC8315 */
8486 POWERPC_DEF_SVR("MPC8315",
8487 CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300),
8488 #endif
8489 #if defined (TODO)
8490 /* MPC8315E */
8491 POWERPC_DEF_SVR("MPC8315E",
8492 CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300),
8493 #endif
8494 #if defined (TODO)
8495 /* MPC8321 */
8496 POWERPC_DEF_SVR("MPC8321",
8497 CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300),
8498 #endif
8499 #if defined (TODO)
8500 /* MPC8321E */
8501 POWERPC_DEF_SVR("MPC8321E",
8502 CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300),
8503 #endif
8504 #if defined (TODO)
8505 /* MPC8323 */
8506 POWERPC_DEF_SVR("MPC8323",
8507 CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300),
8508 #endif
8509 #if defined (TODO)
8510 /* MPC8323E */
8511 POWERPC_DEF_SVR("MPC8323E",
8512 CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300),
8513 #endif
8514 /* MPC8343 */
8515 POWERPC_DEF_SVR("MPC8343",
8516 CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300),
8517 /* MPC8343A */
8518 POWERPC_DEF_SVR("MPC8343A",
8519 CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300),
8520 /* MPC8343E */
8521 POWERPC_DEF_SVR("MPC8343E",
8522 CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300),
8523 /* MPC8343EA */
8524 POWERPC_DEF_SVR("MPC8343EA",
8525 CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300),
8526 /* MPC8347 */
8527 POWERPC_DEF_SVR("MPC8347",
8528 CPU_POWERPC_MPC834x, POWERPC_SVR_8347, e300),
8529 /* MPC8347T */
8530 POWERPC_DEF_SVR("MPC8347T",
8531 CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300),
8532 /* MPC8347P */
8533 POWERPC_DEF_SVR("MPC8347P",
8534 CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300),
8535 /* MPC8347A */
8536 POWERPC_DEF_SVR("MPC8347A",
8537 CPU_POWERPC_MPC834x, POWERPC_SVR_8347A, e300),
8538 /* MPC8347AT */
8539 POWERPC_DEF_SVR("MPC8347AT",
8540 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300),
8541 /* MPC8347AP */
8542 POWERPC_DEF_SVR("MPC8347AP",
8543 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300),
8544 /* MPC8347E */
8545 POWERPC_DEF_SVR("MPC8347E",
8546 CPU_POWERPC_MPC834x, POWERPC_SVR_8347E, e300),
8547 /* MPC8347ET */
8548 POWERPC_DEF_SVR("MPC8347ET",
8549 CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300),
8550 /* MPC8343EP */
8551 POWERPC_DEF_SVR("MPC8347EP",
8552 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300),
8553 /* MPC8347EA */
8554 POWERPC_DEF_SVR("MPC8347EA",
8555 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EA, e300),
8556 /* MPC8347EAT */
8557 POWERPC_DEF_SVR("MPC8347EAT",
8558 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300),
8559 /* MPC8343EAP */
8560 POWERPC_DEF_SVR("MPC8347EAP",
8561 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300),
8562 /* MPC8349 */
8563 POWERPC_DEF_SVR("MPC8349",
8564 CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300),
8565 /* MPC8349A */
8566 POWERPC_DEF_SVR("MPC8349A",
8567 CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300),
8568 /* MPC8349E */
8569 POWERPC_DEF_SVR("MPC8349E",
8570 CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300),
8571 /* MPC8349EA */
8572 POWERPC_DEF_SVR("MPC8349EA",
8573 CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300),
8574 #if defined (TODO)
8575 /* MPC8358E */
8576 POWERPC_DEF_SVR("MPC8358E",
8577 CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300),
8578 #endif
8579 #if defined (TODO)
8580 /* MPC8360E */
8581 POWERPC_DEF_SVR("MPC8360E",
8582 CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300),
8583 #endif
8584 /* MPC8377 */
8585 POWERPC_DEF_SVR("MPC8377",
8586 CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300),
8587 /* MPC8377E */
8588 POWERPC_DEF_SVR("MPC8377E",
8589 CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300),
8590 /* MPC8378 */
8591 POWERPC_DEF_SVR("MPC8378",
8592 CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300),
8593 /* MPC8378E */
8594 POWERPC_DEF_SVR("MPC8378E",
8595 CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300),
8596 /* MPC8379 */
8597 POWERPC_DEF_SVR("MPC8379",
8598 CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300),
8599 /* MPC8379E */
8600 POWERPC_DEF_SVR("MPC8379E",
8601 CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300),
8602 /* e500 family */
8603 /* PowerPC e500 core */
8604 POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2),
8605 /* PowerPC e500v1 core */
8606 POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1),
8607 /* PowerPC e500 v1.0 core */
8608 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1),
8609 /* PowerPC e500 v2.0 core */
8610 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1),
8611 /* PowerPC e500v2 core */
8612 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2),
8613 /* PowerPC e500v2 v1.0 core */
8614 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2),
8615 /* PowerPC e500v2 v2.0 core */
8616 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2),
8617 /* PowerPC e500v2 v2.1 core */
8618 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2),
8619 /* PowerPC e500v2 v2.2 core */
8620 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2),
8621 /* PowerPC e500v2 v3.0 core */
8622 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
8623 POWERPC_DEF("e500mc", CPU_POWERPC_e500mc, e500mc),
8624 #ifdef TARGET_PPC64
8625 POWERPC_DEF("e5500", CPU_POWERPC_e5500, e5500),
8626 #endif
8627 /* PowerPC e500 microcontrollers */
8628 /* MPC8533 */
8629 POWERPC_DEF_SVR("MPC8533",
8630 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2),
8631 /* MPC8533 v1.0 */
8632 POWERPC_DEF_SVR("MPC8533_v10",
8633 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2),
8634 /* MPC8533 v1.1 */
8635 POWERPC_DEF_SVR("MPC8533_v11",
8636 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2),
8637 /* MPC8533E */
8638 POWERPC_DEF_SVR("MPC8533E",
8639 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2),
8640 /* MPC8533E v1.0 */
8641 POWERPC_DEF_SVR("MPC8533E_v10",
8642 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
8643 POWERPC_DEF_SVR("MPC8533E_v11",
8644 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
8645 /* MPC8540 */
8646 POWERPC_DEF_SVR("MPC8540",
8647 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1),
8648 /* MPC8540 v1.0 */
8649 POWERPC_DEF_SVR("MPC8540_v10",
8650 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1),
8651 /* MPC8540 v2.0 */
8652 POWERPC_DEF_SVR("MPC8540_v20",
8653 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1),
8654 /* MPC8540 v2.1 */
8655 POWERPC_DEF_SVR("MPC8540_v21",
8656 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1),
8657 /* MPC8541 */
8658 POWERPC_DEF_SVR("MPC8541",
8659 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1),
8660 /* MPC8541 v1.0 */
8661 POWERPC_DEF_SVR("MPC8541_v10",
8662 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1),
8663 /* MPC8541 v1.1 */
8664 POWERPC_DEF_SVR("MPC8541_v11",
8665 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1),
8666 /* MPC8541E */
8667 POWERPC_DEF_SVR("MPC8541E",
8668 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1),
8669 /* MPC8541E v1.0 */
8670 POWERPC_DEF_SVR("MPC8541E_v10",
8671 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
8672 /* MPC8541E v1.1 */
8673 POWERPC_DEF_SVR("MPC8541E_v11",
8674 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
8675 /* MPC8543 */
8676 POWERPC_DEF_SVR("MPC8543",
8677 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2),
8678 /* MPC8543 v1.0 */
8679 POWERPC_DEF_SVR("MPC8543_v10",
8680 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2),
8681 /* MPC8543 v1.1 */
8682 POWERPC_DEF_SVR("MPC8543_v11",
8683 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2),
8684 /* MPC8543 v2.0 */
8685 POWERPC_DEF_SVR("MPC8543_v20",
8686 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2),
8687 /* MPC8543 v2.1 */
8688 POWERPC_DEF_SVR("MPC8543_v21",
8689 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2),
8690 /* MPC8543E */
8691 POWERPC_DEF_SVR("MPC8543E",
8692 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2),
8693 /* MPC8543E v1.0 */
8694 POWERPC_DEF_SVR("MPC8543E_v10",
8695 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
8696 /* MPC8543E v1.1 */
8697 POWERPC_DEF_SVR("MPC8543E_v11",
8698 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
8699 /* MPC8543E v2.0 */
8700 POWERPC_DEF_SVR("MPC8543E_v20",
8701 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
8702 /* MPC8543E v2.1 */
8703 POWERPC_DEF_SVR("MPC8543E_v21",
8704 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
8705 /* MPC8544 */
8706 POWERPC_DEF_SVR("MPC8544",
8707 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2),
8708 /* MPC8544 v1.0 */
8709 POWERPC_DEF_SVR("MPC8544_v10",
8710 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2),
8711 /* MPC8544 v1.1 */
8712 POWERPC_DEF_SVR("MPC8544_v11",
8713 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2),
8714 /* MPC8544E */
8715 POWERPC_DEF_SVR("MPC8544E",
8716 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2),
8717 /* MPC8544E v1.0 */
8718 POWERPC_DEF_SVR("MPC8544E_v10",
8719 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
8720 /* MPC8544E v1.1 */
8721 POWERPC_DEF_SVR("MPC8544E_v11",
8722 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
8723 /* MPC8545 */
8724 POWERPC_DEF_SVR("MPC8545",
8725 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2),
8726 /* MPC8545 v2.0 */
8727 POWERPC_DEF_SVR("MPC8545_v20",
8728 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2),
8729 /* MPC8545 v2.1 */
8730 POWERPC_DEF_SVR("MPC8545_v21",
8731 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2),
8732 /* MPC8545E */
8733 POWERPC_DEF_SVR("MPC8545E",
8734 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2),
8735 /* MPC8545E v2.0 */
8736 POWERPC_DEF_SVR("MPC8545E_v20",
8737 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
8738 /* MPC8545E v2.1 */
8739 POWERPC_DEF_SVR("MPC8545E_v21",
8740 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
8741 /* MPC8547E */
8742 POWERPC_DEF_SVR("MPC8547E",
8743 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2),
8744 /* MPC8547E v2.0 */
8745 POWERPC_DEF_SVR("MPC8547E_v20",
8746 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
8747 /* MPC8547E v2.1 */
8748 POWERPC_DEF_SVR("MPC8547E_v21",
8749 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
8750 /* MPC8548 */
8751 POWERPC_DEF_SVR("MPC8548",
8752 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2),
8753 /* MPC8548 v1.0 */
8754 POWERPC_DEF_SVR("MPC8548_v10",
8755 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2),
8756 /* MPC8548 v1.1 */
8757 POWERPC_DEF_SVR("MPC8548_v11",
8758 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2),
8759 /* MPC8548 v2.0 */
8760 POWERPC_DEF_SVR("MPC8548_v20",
8761 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2),
8762 /* MPC8548 v2.1 */
8763 POWERPC_DEF_SVR("MPC8548_v21",
8764 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2),
8765 /* MPC8548E */
8766 POWERPC_DEF_SVR("MPC8548E",
8767 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2),
8768 /* MPC8548E v1.0 */
8769 POWERPC_DEF_SVR("MPC8548E_v10",
8770 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
8771 /* MPC8548E v1.1 */
8772 POWERPC_DEF_SVR("MPC8548E_v11",
8773 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
8774 /* MPC8548E v2.0 */
8775 POWERPC_DEF_SVR("MPC8548E_v20",
8776 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
8777 /* MPC8548E v2.1 */
8778 POWERPC_DEF_SVR("MPC8548E_v21",
8779 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
8780 /* MPC8555 */
8781 POWERPC_DEF_SVR("MPC8555",
8782 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2),
8783 /* MPC8555 v1.0 */
8784 POWERPC_DEF_SVR("MPC8555_v10",
8785 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2),
8786 /* MPC8555 v1.1 */
8787 POWERPC_DEF_SVR("MPC8555_v11",
8788 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2),
8789 /* MPC8555E */
8790 POWERPC_DEF_SVR("MPC8555E",
8791 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2),
8792 /* MPC8555E v1.0 */
8793 POWERPC_DEF_SVR("MPC8555E_v10",
8794 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
8795 /* MPC8555E v1.1 */
8796 POWERPC_DEF_SVR("MPC8555E_v11",
8797 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
8798 /* MPC8560 */
8799 POWERPC_DEF_SVR("MPC8560",
8800 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2),
8801 /* MPC8560 v1.0 */
8802 POWERPC_DEF_SVR("MPC8560_v10",
8803 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2),
8804 /* MPC8560 v2.0 */
8805 POWERPC_DEF_SVR("MPC8560_v20",
8806 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2),
8807 /* MPC8560 v2.1 */
8808 POWERPC_DEF_SVR("MPC8560_v21",
8809 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2),
8810 /* MPC8567 */
8811 POWERPC_DEF_SVR("MPC8567",
8812 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2),
8813 /* MPC8567E */
8814 POWERPC_DEF_SVR("MPC8567E",
8815 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2),
8816 /* MPC8568 */
8817 POWERPC_DEF_SVR("MPC8568",
8818 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2),
8819 /* MPC8568E */
8820 POWERPC_DEF_SVR("MPC8568E",
8821 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2),
8822 /* MPC8572 */
8823 POWERPC_DEF_SVR("MPC8572",
8824 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2),
8825 /* MPC8572E */
8826 POWERPC_DEF_SVR("MPC8572E",
8827 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2),
8828 /* e600 family */
8829 /* PowerPC e600 core */
8830 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
8831 /* PowerPC e600 microcontrollers */
8832 #if defined (TODO)
8833 /* MPC8610 */
8834 POWERPC_DEF_SVR("MPC8610",
8835 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
8836 #endif
8837 /* MPC8641 */
8838 POWERPC_DEF_SVR("MPC8641",
8839 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
8840 /* MPC8641D */
8841 POWERPC_DEF_SVR("MPC8641D",
8842 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
8843 /* 32 bits "classic" PowerPC */
8844 /* PowerPC 6xx family */
8845 /* PowerPC 601 */
8846 POWERPC_DEF("601", CPU_POWERPC_601, 601v),
8847 /* PowerPC 601v0 */
8848 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
8849 /* PowerPC 601v1 */
8850 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
8851 /* PowerPC 601v */
8852 POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
8853 /* PowerPC 601v2 */
8854 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
8855 /* PowerPC 602 */
8856 POWERPC_DEF("602", CPU_POWERPC_602, 602),
8857 /* PowerPC 603 */
8858 POWERPC_DEF("603", CPU_POWERPC_603, 603),
8859 /* Code name for PowerPC 603 */
8860 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
8861 /* PowerPC 603e (aka PID6) */
8862 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
8863 /* Code name for PowerPC 603e */
8864 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
8865 /* PowerPC 603e v1.1 */
8866 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
8867 /* PowerPC 603e v1.2 */
8868 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
8869 /* PowerPC 603e v1.3 */
8870 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
8871 /* PowerPC 603e v1.4 */
8872 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
8873 /* PowerPC 603e v2.2 */
8874 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
8875 /* PowerPC 603e v3 */
8876 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
8877 /* PowerPC 603e v4 */
8878 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
8879 /* PowerPC 603e v4.1 */
8880 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
8881 /* PowerPC 603e (aka PID7) */
8882 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
8883 /* PowerPC 603e7t */
8884 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
8885 /* PowerPC 603e7v */
8886 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
8887 /* Code name for PowerPC 603ev */
8888 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
8889 /* PowerPC 603e7v1 */
8890 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
8891 /* PowerPC 603e7v2 */
8892 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
8893 /* PowerPC 603p (aka PID7v) */
8894 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
8895 /* PowerPC 603r (aka PID7t) */
8896 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
8897 /* Code name for PowerPC 603r */
8898 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
8899 /* PowerPC 604 */
8900 POWERPC_DEF("604", CPU_POWERPC_604, 604),
8901 /* PowerPC 604e (aka PID9) */
8902 POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
8903 /* Code name for PowerPC 604e */
8904 POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
8905 /* PowerPC 604e v1.0 */
8906 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
8907 /* PowerPC 604e v2.2 */
8908 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
8909 /* PowerPC 604e v2.4 */
8910 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
8911 /* PowerPC 604r (aka PIDA) */
8912 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
8913 /* Code name for PowerPC 604r */
8914 POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
8915 #if defined(TODO)
8916 /* PowerPC 604ev */
8917 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
8918 #endif
8919 /* PowerPC 7xx family */
8920 /* Generic PowerPC 740 (G3) */
8921 POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
8922 /* Code name for PowerPC 740 */
8923 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
8924 /* Generic PowerPC 750 (G3) */
8925 POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
8926 /* Code name for PowerPC 750 */
8927 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
8928 /* PowerPC 740/750 is also known as G3 */
8929 POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
8930 /* PowerPC 740 v1.0 (G3) */
8931 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
8932 /* PowerPC 750 v1.0 (G3) */
8933 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
8934 /* PowerPC 740 v2.0 (G3) */
8935 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
8936 /* PowerPC 750 v2.0 (G3) */
8937 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
8938 /* PowerPC 740 v2.1 (G3) */
8939 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
8940 /* PowerPC 750 v2.1 (G3) */
8941 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
8942 /* PowerPC 740 v2.2 (G3) */
8943 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
8944 /* PowerPC 750 v2.2 (G3) */
8945 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
8946 /* PowerPC 740 v3.0 (G3) */
8947 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
8948 /* PowerPC 750 v3.0 (G3) */
8949 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
8950 /* PowerPC 740 v3.1 (G3) */
8951 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
8952 /* PowerPC 750 v3.1 (G3) */
8953 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
8954 /* PowerPC 740E (G3) */
8955 POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
8956 /* PowerPC 750E (G3) */
8957 POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
8958 /* PowerPC 740P (G3) */
8959 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
8960 /* PowerPC 750P (G3) */
8961 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
8962 /* Code name for PowerPC 740P/750P (G3) */
8963 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
8964 /* PowerPC 750CL (G3 embedded) */
8965 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
8966 /* PowerPC 750CL v1.0 */
8967 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
8968 /* PowerPC 750CL v2.0 */
8969 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
8970 /* PowerPC 750CX (G3 embedded) */
8971 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
8972 /* PowerPC 750CX v1.0 (G3 embedded) */
8973 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
8974 /* PowerPC 750CX v2.1 (G3 embedded) */
8975 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
8976 /* PowerPC 750CX v2.1 (G3 embedded) */
8977 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
8978 /* PowerPC 750CX v2.2 (G3 embedded) */
8979 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
8980 /* PowerPC 750CXe (G3 embedded) */
8981 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
8982 /* PowerPC 750CXe v2.1 (G3 embedded) */
8983 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
8984 /* PowerPC 750CXe v2.2 (G3 embedded) */
8985 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
8986 /* PowerPC 750CXe v2.3 (G3 embedded) */
8987 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
8988 /* PowerPC 750CXe v2.4 (G3 embedded) */
8989 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
8990 /* PowerPC 750CXe v2.4b (G3 embedded) */
8991 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
8992 /* PowerPC 750CXe v3.0 (G3 embedded) */
8993 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
8994 /* PowerPC 750CXe v3.1 (G3 embedded) */
8995 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
8996 /* PowerPC 750CXe v3.1b (G3 embedded) */
8997 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
8998 /* PowerPC 750CXr (G3 embedded) */
8999 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
9000 /* PowerPC 750FL (G3 embedded) */
9001 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
9002 /* PowerPC 750FX (G3 embedded) */
9003 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
9004 /* PowerPC 750FX v1.0 (G3 embedded) */
9005 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
9006 /* PowerPC 750FX v2.0 (G3 embedded) */
9007 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
9008 /* PowerPC 750FX v2.1 (G3 embedded) */
9009 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
9010 /* PowerPC 750FX v2.2 (G3 embedded) */
9011 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
9012 /* PowerPC 750FX v2.3 (G3 embedded) */
9013 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
9014 /* PowerPC 750GL (G3 embedded) */
9015 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
9016 /* PowerPC 750GX (G3 embedded) */
9017 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
9018 /* PowerPC 750GX v1.0 (G3 embedded) */
9019 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
9020 /* PowerPC 750GX v1.1 (G3 embedded) */
9021 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
9022 /* PowerPC 750GX v1.2 (G3 embedded) */
9023 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
9024 /* PowerPC 750L (G3 embedded) */
9025 POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
9026 /* Code name for PowerPC 750L (G3 embedded) */
9027 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
9028 /* PowerPC 750L v2.0 (G3 embedded) */
9029 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
9030 /* PowerPC 750L v2.1 (G3 embedded) */
9031 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
9032 /* PowerPC 750L v2.2 (G3 embedded) */
9033 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
9034 /* PowerPC 750L v3.0 (G3 embedded) */
9035 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
9036 /* PowerPC 750L v3.2 (G3 embedded) */
9037 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
9038 /* Generic PowerPC 745 */
9039 POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
9040 /* Generic PowerPC 755 */
9041 POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
9042 /* Code name for PowerPC 745/755 */
9043 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
9044 /* PowerPC 745 v1.0 */
9045 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
9046 /* PowerPC 755 v1.0 */
9047 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
9048 /* PowerPC 745 v1.1 */
9049 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
9050 /* PowerPC 755 v1.1 */
9051 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
9052 /* PowerPC 745 v2.0 */
9053 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
9054 /* PowerPC 755 v2.0 */
9055 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
9056 /* PowerPC 745 v2.1 */
9057 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
9058 /* PowerPC 755 v2.1 */
9059 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
9060 /* PowerPC 745 v2.2 */
9061 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
9062 /* PowerPC 755 v2.2 */
9063 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
9064 /* PowerPC 745 v2.3 */
9065 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
9066 /* PowerPC 755 v2.3 */
9067 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
9068 /* PowerPC 745 v2.4 */
9069 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
9070 /* PowerPC 755 v2.4 */
9071 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
9072 /* PowerPC 745 v2.5 */
9073 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
9074 /* PowerPC 755 v2.5 */
9075 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
9076 /* PowerPC 745 v2.6 */
9077 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
9078 /* PowerPC 755 v2.6 */
9079 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
9080 /* PowerPC 745 v2.7 */
9081 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
9082 /* PowerPC 755 v2.7 */
9083 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
9084 /* PowerPC 745 v2.8 */
9085 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
9086 /* PowerPC 755 v2.8 */
9087 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
9088 #if defined (TODO)
9089 /* PowerPC 745P (G3) */
9090 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
9091 /* PowerPC 755P (G3) */
9092 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
9093 #endif
9094 /* PowerPC 74xx family */
9095 /* PowerPC 7400 (G4) */
9096 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
9097 /* Code name for PowerPC 7400 */
9098 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
9099 /* PowerPC 74xx is also well known as G4 */
9100 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
9101 /* PowerPC 7400 v1.0 (G4) */
9102 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
9103 /* PowerPC 7400 v1.1 (G4) */
9104 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
9105 /* PowerPC 7400 v2.0 (G4) */
9106 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
9107 /* PowerPC 7400 v2.1 (G4) */
9108 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
9109 /* PowerPC 7400 v2.2 (G4) */
9110 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
9111 /* PowerPC 7400 v2.6 (G4) */
9112 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
9113 /* PowerPC 7400 v2.7 (G4) */
9114 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
9115 /* PowerPC 7400 v2.8 (G4) */
9116 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
9117 /* PowerPC 7400 v2.9 (G4) */
9118 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
9119 /* PowerPC 7410 (G4) */
9120 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
9121 /* Code name for PowerPC 7410 */
9122 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
9123 /* PowerPC 7410 v1.0 (G4) */
9124 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
9125 /* PowerPC 7410 v1.1 (G4) */
9126 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
9127 /* PowerPC 7410 v1.2 (G4) */
9128 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
9129 /* PowerPC 7410 v1.3 (G4) */
9130 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
9131 /* PowerPC 7410 v1.4 (G4) */
9132 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
9133 /* PowerPC 7448 (G4) */
9134 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
9135 /* PowerPC 7448 v1.0 (G4) */
9136 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
9137 /* PowerPC 7448 v1.1 (G4) */
9138 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
9139 /* PowerPC 7448 v2.0 (G4) */
9140 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
9141 /* PowerPC 7448 v2.1 (G4) */
9142 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
9143 /* PowerPC 7450 (G4) */
9144 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
9145 /* Code name for PowerPC 7450 */
9146 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
9147 /* PowerPC 7450 v1.0 (G4) */
9148 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
9149 /* PowerPC 7450 v1.1 (G4) */
9150 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
9151 /* PowerPC 7450 v1.2 (G4) */
9152 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
9153 /* PowerPC 7450 v2.0 (G4) */
9154 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
9155 /* PowerPC 7450 v2.1 (G4) */
9156 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
9157 /* PowerPC 7441 (G4) */
9158 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
9159 /* PowerPC 7451 (G4) */
9160 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
9161 /* PowerPC 7441 v2.1 (G4) */
9162 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
9163 /* PowerPC 7441 v2.3 (G4) */
9164 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
9165 /* PowerPC 7451 v2.3 (G4) */
9166 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
9167 /* PowerPC 7441 v2.10 (G4) */
9168 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
9169 /* PowerPC 7451 v2.10 (G4) */
9170 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
9171 /* PowerPC 7445 (G4) */
9172 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
9173 /* PowerPC 7455 (G4) */
9174 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
9175 /* Code name for PowerPC 7445/7455 */
9176 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
9177 /* PowerPC 7445 v1.0 (G4) */
9178 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
9179 /* PowerPC 7455 v1.0 (G4) */
9180 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
9181 /* PowerPC 7445 v2.1 (G4) */
9182 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
9183 /* PowerPC 7455 v2.1 (G4) */
9184 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
9185 /* PowerPC 7445 v3.2 (G4) */
9186 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
9187 /* PowerPC 7455 v3.2 (G4) */
9188 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
9189 /* PowerPC 7445 v3.3 (G4) */
9190 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
9191 /* PowerPC 7455 v3.3 (G4) */
9192 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
9193 /* PowerPC 7445 v3.4 (G4) */
9194 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
9195 /* PowerPC 7455 v3.4 (G4) */
9196 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
9197 /* PowerPC 7447 (G4) */
9198 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
9199 /* PowerPC 7457 (G4) */
9200 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
9201 /* Code name for PowerPC 7447/7457 */
9202 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
9203 /* PowerPC 7447 v1.0 (G4) */
9204 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
9205 /* PowerPC 7457 v1.0 (G4) */
9206 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
9207 /* PowerPC 7447 v1.1 (G4) */
9208 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
9209 /* PowerPC 7457 v1.1 (G4) */
9210 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
9211 /* PowerPC 7457 v1.2 (G4) */
9212 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
9213 /* PowerPC 7447A (G4) */
9214 POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
9215 /* PowerPC 7457A (G4) */
9216 POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
9217 /* PowerPC 7447A v1.0 (G4) */
9218 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
9219 /* PowerPC 7457A v1.0 (G4) */
9220 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
9221 /* Code name for PowerPC 7447A/7457A */
9222 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
9223 /* PowerPC 7447A v1.1 (G4) */
9224 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
9225 /* PowerPC 7457A v1.1 (G4) */
9226 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
9227 /* PowerPC 7447A v1.2 (G4) */
9228 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
9229 /* PowerPC 7457A v1.2 (G4) */
9230 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
9231 /* 64 bits PowerPC */
9232 #if defined (TARGET_PPC64)
9233 /* PowerPC 620 */
9234 POWERPC_DEF("620", CPU_POWERPC_620, 620),
9235 /* Code name for PowerPC 620 */
9236 POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
9237 #if defined (TODO)
9238 /* PowerPC 630 (POWER3) */
9239 POWERPC_DEF("630", CPU_POWERPC_630, 630),
9240 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
9241 /* Code names for POWER3 */
9242 POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
9243 POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
9244 #endif
9245 #if defined (TODO)
9246 /* PowerPC 631 (Power 3+) */
9247 POWERPC_DEF("631", CPU_POWERPC_631, 631),
9248 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
9249 #endif
9250 #if defined (TODO)
9251 /* POWER4 */
9252 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
9253 #endif
9254 #if defined (TODO)
9255 /* POWER4p */
9256 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
9257 #endif
9258 #if defined (TODO)
9259 /* POWER5 */
9260 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
9261 /* POWER5GR */
9262 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
9263 #endif
9264 #if defined (TODO)
9265 /* POWER5+ */
9266 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
9267 /* POWER5GS */
9268 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
9269 #endif
9270 #if defined (TODO)
9271 /* POWER6 */
9272 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
9273 /* POWER6 running in POWER5 mode */
9274 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
9275 /* POWER6A */
9276 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
9277 #endif
9278 /* POWER7 */
9279 POWERPC_DEF("POWER7", CPU_POWERPC_POWER7, POWER7),
9280 POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7),
9281 POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21, POWER7),
9282 POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7),
9283 /* PowerPC 970 */
9284 POWERPC_DEF("970", CPU_POWERPC_970, 970),
9285 /* PowerPC 970FX (G5) */
9286 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
9287 /* PowerPC 970FX v1.0 (G5) */
9288 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
9289 /* PowerPC 970FX v2.0 (G5) */
9290 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
9291 /* PowerPC 970FX v2.1 (G5) */
9292 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
9293 /* PowerPC 970FX v3.0 (G5) */
9294 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
9295 /* PowerPC 970FX v3.1 (G5) */
9296 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
9297 /* PowerPC 970GX (G5) */
9298 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
9299 /* PowerPC 970MP */
9300 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
9301 /* PowerPC 970MP v1.0 */
9302 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
9303 /* PowerPC 970MP v1.1 */
9304 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
9305 #if defined (TODO)
9306 /* PowerPC Cell */
9307 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
9308 #endif
9309 #if defined (TODO)
9310 /* PowerPC Cell v1.0 */
9311 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
9312 #endif
9313 #if defined (TODO)
9314 /* PowerPC Cell v2.0 */
9315 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
9316 #endif
9317 #if defined (TODO)
9318 /* PowerPC Cell v3.0 */
9319 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
9320 #endif
9321 #if defined (TODO)
9322 /* PowerPC Cell v3.1 */
9323 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
9324 #endif
9325 #if defined (TODO)
9326 /* PowerPC Cell v3.2 */
9327 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
9328 #endif
9329 #if defined (TODO)
9330 /* RS64 (Apache/A35) */
9331 /* This one seems to support the whole POWER2 instruction set
9332 * and the PowerPC 64 one.
9333 */
9334 /* What about A10 & A30 ? */
9335 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
9336 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
9337 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
9338 #endif
9339 #if defined (TODO)
9340 /* RS64-II (NorthStar/A50) */
9341 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
9342 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
9343 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
9344 #endif
9345 #if defined (TODO)
9346 /* RS64-III (Pulsar) */
9347 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
9348 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
9349 #endif
9350 #if defined (TODO)
9351 /* RS64-IV (IceStar/IStar/SStar) */
9352 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
9353 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
9354 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
9355 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
9356 #endif
9357 #endif /* defined (TARGET_PPC64) */
9358 /* POWER */
9359 #if defined (TODO)
9360 /* Original POWER */
9361 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
9362 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
9363 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
9364 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
9365 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
9366 #endif
9367 #if defined (TODO)
9368 /* POWER2 */
9369 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
9370 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
9371 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
9372 #endif
9373 /* PA semi cores */
9374 #if defined (TODO)
9375 /* PA PA6T */
9376 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
9377 #endif
9378 /* Generic PowerPCs */
9379 #if defined (TARGET_PPC64)
9380 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
9381 #endif
9382 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
9383 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
9384 /* Fallback */
9385 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
9386 };
9387
9388 /*****************************************************************************/
9389 /* Generic CPU instantiation routine */
9390 static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
9391 {
9392 #if !defined(CONFIG_USER_ONLY)
9393 int i;
9394
9395 env->irq_inputs = NULL;
9396 /* Set all exception vectors to an invalid address */
9397 for (i = 0; i < POWERPC_EXCP_NB; i++)
9398 env->excp_vectors[i] = (target_ulong)(-1ULL);
9399 env->hreset_excp_prefix = 0x00000000;
9400 env->ivor_mask = 0x00000000;
9401 env->ivpr_mask = 0x00000000;
9402 /* Default MMU definitions */
9403 env->nb_BATs = 0;
9404 env->nb_tlb = 0;
9405 env->nb_ways = 0;
9406 env->tlb_type = TLB_NONE;
9407 #endif
9408 /* Register SPR common to all PowerPC implementations */
9409 gen_spr_generic(env);
9410 spr_register(env, SPR_PVR, "PVR",
9411 /* Linux permits userspace to read PVR */
9412 #if defined(CONFIG_LINUX_USER)
9413 &spr_read_generic,
9414 #else
9415 SPR_NOACCESS,
9416 #endif
9417 SPR_NOACCESS,
9418 &spr_read_generic, SPR_NOACCESS,
9419 def->pvr);
9420 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
9421 if (def->svr != POWERPC_SVR_NONE) {
9422 if (def->svr & POWERPC_SVR_E500) {
9423 spr_register(env, SPR_E500_SVR, "SVR",
9424 SPR_NOACCESS, SPR_NOACCESS,
9425 &spr_read_generic, SPR_NOACCESS,
9426 def->svr & ~POWERPC_SVR_E500);
9427 } else {
9428 spr_register(env, SPR_SVR, "SVR",
9429 SPR_NOACCESS, SPR_NOACCESS,
9430 &spr_read_generic, SPR_NOACCESS,
9431 def->svr);
9432 }
9433 }
9434 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
9435 (*def->init_proc)(env);
9436 #if !defined(CONFIG_USER_ONLY)
9437 env->excp_prefix = env->hreset_excp_prefix;
9438 #endif
9439 /* MSR bits & flags consistency checks */
9440 if (env->msr_mask & (1 << 25)) {
9441 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9442 case POWERPC_FLAG_SPE:
9443 case POWERPC_FLAG_VRE:
9444 break;
9445 default:
9446 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9447 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9448 exit(1);
9449 }
9450 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9451 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9452 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9453 exit(1);
9454 }
9455 if (env->msr_mask & (1 << 17)) {
9456 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9457 case POWERPC_FLAG_TGPR:
9458 case POWERPC_FLAG_CE:
9459 break;
9460 default:
9461 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9462 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9463 exit(1);
9464 }
9465 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9466 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9467 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9468 exit(1);
9469 }
9470 if (env->msr_mask & (1 << 10)) {
9471 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9472 POWERPC_FLAG_UBLE)) {
9473 case POWERPC_FLAG_SE:
9474 case POWERPC_FLAG_DWE:
9475 case POWERPC_FLAG_UBLE:
9476 break;
9477 default:
9478 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9479 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9480 "POWERPC_FLAG_UBLE\n");
9481 exit(1);
9482 }
9483 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9484 POWERPC_FLAG_UBLE)) {
9485 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9486 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9487 "POWERPC_FLAG_UBLE\n");
9488 exit(1);
9489 }
9490 if (env->msr_mask & (1 << 9)) {
9491 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9492 case POWERPC_FLAG_BE:
9493 case POWERPC_FLAG_DE:
9494 break;
9495 default:
9496 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9497 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9498 exit(1);
9499 }
9500 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9501 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9502 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9503 exit(1);
9504 }
9505 if (env->msr_mask & (1 << 2)) {
9506 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9507 case POWERPC_FLAG_PX:
9508 case POWERPC_FLAG_PMM:
9509 break;
9510 default:
9511 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9512 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9513 exit(1);
9514 }
9515 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9516 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9517 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9518 exit(1);
9519 }
9520 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9521 fprintf(stderr, "PowerPC flags inconsistency\n"
9522 "Should define the time-base and decrementer clock source\n");
9523 exit(1);
9524 }
9525 /* Allocate TLBs buffer when needed */
9526 #if !defined(CONFIG_USER_ONLY)
9527 if (env->nb_tlb != 0) {
9528 int nb_tlb = env->nb_tlb;
9529 if (env->id_tlbs != 0)
9530 nb_tlb *= 2;
9531 switch (env->tlb_type) {
9532 case TLB_6XX:
9533 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
9534 break;
9535 case TLB_EMB:
9536 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
9537 break;
9538 case TLB_MAS:
9539 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
9540 break;
9541 }
9542 /* Pre-compute some useful values */
9543 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9544 }
9545 if (env->irq_inputs == NULL) {
9546 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
9547 " Attempt QEMU to crash very soon !\n");
9548 }
9549 #endif
9550 if (env->check_pow == NULL) {
9551 fprintf(stderr, "WARNING: no power management check handler "
9552 "registered.\n"
9553 " Attempt QEMU to crash very soon !\n");
9554 }
9555 }
9556
9557 #if defined(PPC_DUMP_CPU)
9558 static void dump_ppc_sprs (CPUPPCState *env)
9559 {
9560 ppc_spr_t *spr;
9561 #if !defined(CONFIG_USER_ONLY)
9562 uint32_t sr, sw;
9563 #endif
9564 uint32_t ur, uw;
9565 int i, j, n;
9566
9567 printf("Special purpose registers:\n");
9568 for (i = 0; i < 32; i++) {
9569 for (j = 0; j < 32; j++) {
9570 n = (i << 5) | j;
9571 spr = &env->spr_cb[n];
9572 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9573 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9574 #if !defined(CONFIG_USER_ONLY)
9575 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9576 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9577 if (sw || sr || uw || ur) {
9578 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9579 (i << 5) | j, (i << 5) | j, spr->name,
9580 sw ? 'w' : '-', sr ? 'r' : '-',
9581 uw ? 'w' : '-', ur ? 'r' : '-');
9582 }
9583 #else
9584 if (uw || ur) {
9585 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9586 (i << 5) | j, (i << 5) | j, spr->name,
9587 uw ? 'w' : '-', ur ? 'r' : '-');
9588 }
9589 #endif
9590 }
9591 }
9592 fflush(stdout);
9593 fflush(stderr);
9594 }
9595 #endif
9596
9597 /*****************************************************************************/
9598 #include <stdlib.h>
9599 #include <string.h>
9600
9601 /* Opcode types */
9602 enum {
9603 PPC_DIRECT = 0, /* Opcode routine */
9604 PPC_INDIRECT = 1, /* Indirect opcode table */
9605 };
9606
9607 static inline int is_indirect_opcode (void *handler)
9608 {
9609 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
9610 }
9611
9612 static inline opc_handler_t **ind_table(void *handler)
9613 {
9614 return (opc_handler_t **)((uintptr_t)handler & ~3);
9615 }
9616
9617 /* Instruction table creation */
9618 /* Opcodes tables creation */
9619 static void fill_new_table (opc_handler_t **table, int len)
9620 {
9621 int i;
9622
9623 for (i = 0; i < len; i++)
9624 table[i] = &invalid_handler;
9625 }
9626
9627 static int create_new_table (opc_handler_t **table, unsigned char idx)
9628 {
9629 opc_handler_t **tmp;
9630
9631 tmp = malloc(0x20 * sizeof(opc_handler_t));
9632 fill_new_table(tmp, 0x20);
9633 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
9634
9635 return 0;
9636 }
9637
9638 static int insert_in_table (opc_handler_t **table, unsigned char idx,
9639 opc_handler_t *handler)
9640 {
9641 if (table[idx] != &invalid_handler)
9642 return -1;
9643 table[idx] = handler;
9644
9645 return 0;
9646 }
9647
9648 static int register_direct_insn (opc_handler_t **ppc_opcodes,
9649 unsigned char idx, opc_handler_t *handler)
9650 {
9651 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9652 printf("*** ERROR: opcode %02x already assigned in main "
9653 "opcode table\n", idx);
9654 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9655 printf(" Registered handler '%s' - new handler '%s'\n",
9656 ppc_opcodes[idx]->oname, handler->oname);
9657 #endif
9658 return -1;
9659 }
9660
9661 return 0;
9662 }
9663
9664 static int register_ind_in_table (opc_handler_t **table,
9665 unsigned char idx1, unsigned char idx2,
9666 opc_handler_t *handler)
9667 {
9668 if (table[idx1] == &invalid_handler) {
9669 if (create_new_table(table, idx1) < 0) {
9670 printf("*** ERROR: unable to create indirect table "
9671 "idx=%02x\n", idx1);
9672 return -1;
9673 }
9674 } else {
9675 if (!is_indirect_opcode(table[idx1])) {
9676 printf("*** ERROR: idx %02x already assigned to a direct "
9677 "opcode\n", idx1);
9678 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9679 printf(" Registered handler '%s' - new handler '%s'\n",
9680 ind_table(table[idx1])[idx2]->oname, handler->oname);
9681 #endif
9682 return -1;
9683 }
9684 }
9685 if (handler != NULL &&
9686 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9687 printf("*** ERROR: opcode %02x already assigned in "
9688 "opcode table %02x\n", idx2, idx1);
9689 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9690 printf(" Registered handler '%s' - new handler '%s'\n",
9691 ind_table(table[idx1])[idx2]->oname, handler->oname);
9692 #endif
9693 return -1;
9694 }
9695
9696 return 0;
9697 }
9698
9699 static int register_ind_insn (opc_handler_t **ppc_opcodes,
9700 unsigned char idx1, unsigned char idx2,
9701 opc_handler_t *handler)
9702 {
9703 int ret;
9704
9705 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9706
9707 return ret;
9708 }
9709
9710 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
9711 unsigned char idx1, unsigned char idx2,
9712 unsigned char idx3, opc_handler_t *handler)
9713 {
9714 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9715 printf("*** ERROR: unable to join indirect table idx "
9716 "[%02x-%02x]\n", idx1, idx2);
9717 return -1;
9718 }
9719 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9720 handler) < 0) {
9721 printf("*** ERROR: unable to insert opcode "
9722 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9723 return -1;
9724 }
9725
9726 return 0;
9727 }
9728
9729 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
9730 {
9731 if (insn->opc2 != 0xFF) {
9732 if (insn->opc3 != 0xFF) {
9733 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9734 insn->opc3, &insn->handler) < 0)
9735 return -1;
9736 } else {
9737 if (register_ind_insn(ppc_opcodes, insn->opc1,
9738 insn->opc2, &insn->handler) < 0)
9739 return -1;
9740 }
9741 } else {
9742 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9743 return -1;
9744 }
9745
9746 return 0;
9747 }
9748
9749 static int test_opcode_table (opc_handler_t **table, int len)
9750 {
9751 int i, count, tmp;
9752
9753 for (i = 0, count = 0; i < len; i++) {
9754 /* Consistency fixup */
9755 if (table[i] == NULL)
9756 table[i] = &invalid_handler;
9757 if (table[i] != &invalid_handler) {
9758 if (is_indirect_opcode(table[i])) {
9759 tmp = test_opcode_table(ind_table(table[i]), 0x20);
9760 if (tmp == 0) {
9761 free(table[i]);
9762 table[i] = &invalid_handler;
9763 } else {
9764 count++;
9765 }
9766 } else {
9767 count++;
9768 }
9769 }
9770 }
9771
9772 return count;
9773 }
9774
9775 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
9776 {
9777 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9778 printf("*** WARNING: no opcode defined !\n");
9779 }
9780
9781 /*****************************************************************************/
9782 static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
9783 {
9784 opcode_t *opc;
9785
9786 fill_new_table(env->opcodes, 0x40);
9787 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
9788 if (((opc->handler.type & def->insns_flags) != 0) ||
9789 ((opc->handler.type2 & def->insns_flags2) != 0)) {
9790 if (register_insn(env->opcodes, opc) < 0) {
9791 printf("*** ERROR initializing PowerPC instruction "
9792 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9793 opc->opc3);
9794 return -1;
9795 }
9796 }
9797 }
9798 fix_opcode_tables(env->opcodes);
9799 fflush(stdout);
9800 fflush(stderr);
9801
9802 return 0;
9803 }
9804
9805 #if defined(PPC_DUMP_CPU)
9806 static void dump_ppc_insns (CPUPPCState *env)
9807 {
9808 opc_handler_t **table, *handler;
9809 const char *p, *q;
9810 uint8_t opc1, opc2, opc3;
9811
9812 printf("Instructions set:\n");
9813 /* opc1 is 6 bits long */
9814 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9815 table = env->opcodes;
9816 handler = table[opc1];
9817 if (is_indirect_opcode(handler)) {
9818 /* opc2 is 5 bits long */
9819 for (opc2 = 0; opc2 < 0x20; opc2++) {
9820 table = env->opcodes;
9821 handler = env->opcodes[opc1];
9822 table = ind_table(handler);
9823 handler = table[opc2];
9824 if (is_indirect_opcode(handler)) {
9825 table = ind_table(handler);
9826 /* opc3 is 5 bits long */
9827 for (opc3 = 0; opc3 < 0x20; opc3++) {
9828 handler = table[opc3];
9829 if (handler->handler != &gen_invalid) {
9830 /* Special hack to properly dump SPE insns */
9831 p = strchr(handler->oname, '_');
9832 if (p == NULL) {
9833 printf("INSN: %02x %02x %02x (%02d %04d) : "
9834 "%s\n",
9835 opc1, opc2, opc3, opc1,
9836 (opc3 << 5) | opc2,
9837 handler->oname);
9838 } else {
9839 q = "speundef";
9840 if ((p - handler->oname) != strlen(q) ||
9841 memcmp(handler->oname, q, strlen(q)) != 0) {
9842 /* First instruction */
9843 printf("INSN: %02x %02x %02x (%02d %04d) : "
9844 "%.*s\n",
9845 opc1, opc2 << 1, opc3, opc1,
9846 (opc3 << 6) | (opc2 << 1),
9847 (int)(p - handler->oname),
9848 handler->oname);
9849 }
9850 if (strcmp(p + 1, q) != 0) {
9851 /* Second instruction */
9852 printf("INSN: %02x %02x %02x (%02d %04d) : "
9853 "%s\n",
9854 opc1, (opc2 << 1) | 1, opc3, opc1,
9855 (opc3 << 6) | (opc2 << 1) | 1,
9856 p + 1);
9857 }
9858 }
9859 }
9860 }
9861 } else {
9862 if (handler->handler != &gen_invalid) {
9863 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9864 opc1, opc2, opc1, opc2, handler->oname);
9865 }
9866 }
9867 }
9868 } else {
9869 if (handler->handler != &gen_invalid) {
9870 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9871 opc1, opc1, handler->oname);
9872 }
9873 }
9874 }
9875 }
9876 #endif
9877
9878 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9879 {
9880 if (n < 32) {
9881 stfq_p(mem_buf, env->fpr[n]);
9882 return 8;
9883 }
9884 if (n == 32) {
9885 stl_p(mem_buf, env->fpscr);
9886 return 4;
9887 }
9888 return 0;
9889 }
9890
9891 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9892 {
9893 if (n < 32) {
9894 env->fpr[n] = ldfq_p(mem_buf);
9895 return 8;
9896 }
9897 if (n == 32) {
9898 /* FPSCR not implemented */
9899 return 4;
9900 }
9901 return 0;
9902 }
9903
9904 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9905 {
9906 if (n < 32) {
9907 #ifdef HOST_WORDS_BIGENDIAN
9908 stq_p(mem_buf, env->avr[n].u64[0]);
9909 stq_p(mem_buf+8, env->avr[n].u64[1]);
9910 #else
9911 stq_p(mem_buf, env->avr[n].u64[1]);
9912 stq_p(mem_buf+8, env->avr[n].u64[0]);
9913 #endif
9914 return 16;
9915 }
9916 if (n == 32) {
9917 stl_p(mem_buf, env->vscr);
9918 return 4;
9919 }
9920 if (n == 33) {
9921 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9922 return 4;
9923 }
9924 return 0;
9925 }
9926
9927 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9928 {
9929 if (n < 32) {
9930 #ifdef HOST_WORDS_BIGENDIAN
9931 env->avr[n].u64[0] = ldq_p(mem_buf);
9932 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9933 #else
9934 env->avr[n].u64[1] = ldq_p(mem_buf);
9935 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9936 #endif
9937 return 16;
9938 }
9939 if (n == 32) {
9940 env->vscr = ldl_p(mem_buf);
9941 return 4;
9942 }
9943 if (n == 33) {
9944 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9945 return 4;
9946 }
9947 return 0;
9948 }
9949
9950 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9951 {
9952 if (n < 32) {
9953 #if defined(TARGET_PPC64)
9954 stl_p(mem_buf, env->gpr[n] >> 32);
9955 #else
9956 stl_p(mem_buf, env->gprh[n]);
9957 #endif
9958 return 4;
9959 }
9960 if (n == 32) {
9961 stq_p(mem_buf, env->spe_acc);
9962 return 8;
9963 }
9964 if (n == 33) {
9965 stl_p(mem_buf, env->spe_fscr);
9966 return 4;
9967 }
9968 return 0;
9969 }
9970
9971 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9972 {
9973 if (n < 32) {
9974 #if defined(TARGET_PPC64)
9975 target_ulong lo = (uint32_t)env->gpr[n];
9976 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9977 env->gpr[n] = lo | hi;
9978 #else
9979 env->gprh[n] = ldl_p(mem_buf);
9980 #endif
9981 return 4;
9982 }
9983 if (n == 32) {
9984 env->spe_acc = ldq_p(mem_buf);
9985 return 8;
9986 }
9987 if (n == 33) {
9988 env->spe_fscr = ldl_p(mem_buf);
9989 return 4;
9990 }
9991 return 0;
9992 }
9993
9994 static int ppc_fixup_cpu(CPUPPCState *env)
9995 {
9996 /* TCG doesn't (yet) emulate some groups of instructions that
9997 * are implemented on some otherwise supported CPUs (e.g. VSX
9998 * and decimal floating point instructions on POWER7). We
9999 * remove unsupported instruction groups from the cpu state's
10000 * instruction masks and hope the guest can cope. For at
10001 * least the pseries machine, the unavailability of these
10002 * instructions can be advertised to the guest via the device
10003 * tree. */
10004 if ((env->insns_flags & ~PPC_TCG_INSNS)
10005 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
10006 fprintf(stderr, "Warning: Disabling some instructions which are not "
10007 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
10008 env->insns_flags & ~PPC_TCG_INSNS,
10009 env->insns_flags2 & ~PPC_TCG_INSNS2);
10010 }
10011 env->insns_flags &= PPC_TCG_INSNS;
10012 env->insns_flags2 &= PPC_TCG_INSNS2;
10013 return 0;
10014 }
10015
10016 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
10017 {
10018 env->msr_mask = def->msr_mask;
10019 env->mmu_model = def->mmu_model;
10020 env->excp_model = def->excp_model;
10021 env->bus_model = def->bus_model;
10022 env->insns_flags = def->insns_flags;
10023 env->insns_flags2 = def->insns_flags2;
10024 env->flags = def->flags;
10025 env->bfd_mach = def->bfd_mach;
10026 env->check_pow = def->check_pow;
10027
10028 #if defined(TARGET_PPC64)
10029 if (def->sps)
10030 env->sps = *def->sps;
10031 else if (env->mmu_model & POWERPC_MMU_64) {
10032 /* Use default sets of page sizes */
10033 static const struct ppc_segment_page_sizes defsps = {
10034 .sps = {
10035 { .page_shift = 12, /* 4K */
10036 .slb_enc = 0,
10037 .enc = { { .page_shift = 12, .pte_enc = 0 } }
10038 },
10039 { .page_shift = 24, /* 16M */
10040 .slb_enc = 0x100,
10041 .enc = { { .page_shift = 24, .pte_enc = 0 } }
10042 },
10043 },
10044 };
10045 env->sps = defsps;
10046 }
10047 #endif /* defined(TARGET_PPC64) */
10048
10049 if (kvm_enabled()) {
10050 if (kvmppc_fixup_cpu(env) != 0) {
10051 fprintf(stderr, "Unable to virtualize selected CPU with KVM\n");
10052 exit(1);
10053 }
10054 } else {
10055 if (ppc_fixup_cpu(env) != 0) {
10056 fprintf(stderr, "Unable to emulate selected CPU with TCG\n");
10057 exit(1);
10058 }
10059 }
10060
10061 if (create_ppc_opcodes(env, def) < 0)
10062 return -1;
10063 init_ppc_proc(env, def);
10064
10065 if (def->insns_flags & PPC_FLOAT) {
10066 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
10067 33, "power-fpu.xml", 0);
10068 }
10069 if (def->insns_flags & PPC_ALTIVEC) {
10070 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
10071 34, "power-altivec.xml", 0);
10072 }
10073 if (def->insns_flags & PPC_SPE) {
10074 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
10075 34, "power-spe.xml", 0);
10076 }
10077
10078 #if defined(PPC_DUMP_CPU)
10079 {
10080 const char *mmu_model, *excp_model, *bus_model;
10081 switch (env->mmu_model) {
10082 case POWERPC_MMU_32B:
10083 mmu_model = "PowerPC 32";
10084 break;
10085 case POWERPC_MMU_SOFT_6xx:
10086 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
10087 break;
10088 case POWERPC_MMU_SOFT_74xx:
10089 mmu_model = "PowerPC 74xx with software driven TLBs";
10090 break;
10091 case POWERPC_MMU_SOFT_4xx:
10092 mmu_model = "PowerPC 4xx with software driven TLBs";
10093 break;
10094 case POWERPC_MMU_SOFT_4xx_Z:
10095 mmu_model = "PowerPC 4xx with software driven TLBs "
10096 "and zones protections";
10097 break;
10098 case POWERPC_MMU_REAL:
10099 mmu_model = "PowerPC real mode only";
10100 break;
10101 case POWERPC_MMU_MPC8xx:
10102 mmu_model = "PowerPC MPC8xx";
10103 break;
10104 case POWERPC_MMU_BOOKE:
10105 mmu_model = "PowerPC BookE";
10106 break;
10107 case POWERPC_MMU_BOOKE206:
10108 mmu_model = "PowerPC BookE 2.06";
10109 break;
10110 case POWERPC_MMU_601:
10111 mmu_model = "PowerPC 601";
10112 break;
10113 #if defined (TARGET_PPC64)
10114 case POWERPC_MMU_64B:
10115 mmu_model = "PowerPC 64";
10116 break;
10117 case POWERPC_MMU_620:
10118 mmu_model = "PowerPC 620";
10119 break;
10120 #endif
10121 default:
10122 mmu_model = "Unknown or invalid";
10123 break;
10124 }
10125 switch (env->excp_model) {
10126 case POWERPC_EXCP_STD:
10127 excp_model = "PowerPC";
10128 break;
10129 case POWERPC_EXCP_40x:
10130 excp_model = "PowerPC 40x";
10131 break;
10132 case POWERPC_EXCP_601:
10133 excp_model = "PowerPC 601";
10134 break;
10135 case POWERPC_EXCP_602:
10136 excp_model = "PowerPC 602";
10137 break;
10138 case POWERPC_EXCP_603:
10139 excp_model = "PowerPC 603";
10140 break;
10141 case POWERPC_EXCP_603E:
10142 excp_model = "PowerPC 603e";
10143 break;
10144 case POWERPC_EXCP_604:
10145 excp_model = "PowerPC 604";
10146 break;
10147 case POWERPC_EXCP_7x0:
10148 excp_model = "PowerPC 740/750";
10149 break;
10150 case POWERPC_EXCP_7x5:
10151 excp_model = "PowerPC 745/755";
10152 break;
10153 case POWERPC_EXCP_74xx:
10154 excp_model = "PowerPC 74xx";
10155 break;
10156 case POWERPC_EXCP_BOOKE:
10157 excp_model = "PowerPC BookE";
10158 break;
10159 #if defined (TARGET_PPC64)
10160 case POWERPC_EXCP_970:
10161 excp_model = "PowerPC 970";
10162 break;
10163 #endif
10164 default:
10165 excp_model = "Unknown or invalid";
10166 break;
10167 }
10168 switch (env->bus_model) {
10169 case PPC_FLAGS_INPUT_6xx:
10170 bus_model = "PowerPC 6xx";
10171 break;
10172 case PPC_FLAGS_INPUT_BookE:
10173 bus_model = "PowerPC BookE";
10174 break;
10175 case PPC_FLAGS_INPUT_405:
10176 bus_model = "PowerPC 405";
10177 break;
10178 case PPC_FLAGS_INPUT_401:
10179 bus_model = "PowerPC 401/403";
10180 break;
10181 case PPC_FLAGS_INPUT_RCPU:
10182 bus_model = "RCPU / MPC8xx";
10183 break;
10184 #if defined (TARGET_PPC64)
10185 case PPC_FLAGS_INPUT_970:
10186 bus_model = "PowerPC 970";
10187 break;
10188 #endif
10189 default:
10190 bus_model = "Unknown or invalid";
10191 break;
10192 }
10193 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
10194 " MMU model : %s\n",
10195 def->name, def->pvr, def->msr_mask, mmu_model);
10196 #if !defined(CONFIG_USER_ONLY)
10197 if (env->tlb != NULL) {
10198 printf(" %d %s TLB in %d ways\n",
10199 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
10200 env->nb_ways);
10201 }
10202 #endif
10203 printf(" Exceptions model : %s\n"
10204 " Bus model : %s\n",
10205 excp_model, bus_model);
10206 printf(" MSR features :\n");
10207 if (env->flags & POWERPC_FLAG_SPE)
10208 printf(" signal processing engine enable"
10209 "\n");
10210 else if (env->flags & POWERPC_FLAG_VRE)
10211 printf(" vector processor enable\n");
10212 if (env->flags & POWERPC_FLAG_TGPR)
10213 printf(" temporary GPRs\n");
10214 else if (env->flags & POWERPC_FLAG_CE)
10215 printf(" critical input enable\n");
10216 if (env->flags & POWERPC_FLAG_SE)
10217 printf(" single-step trace mode\n");
10218 else if (env->flags & POWERPC_FLAG_DWE)
10219 printf(" debug wait enable\n");
10220 else if (env->flags & POWERPC_FLAG_UBLE)
10221 printf(" user BTB lock enable\n");
10222 if (env->flags & POWERPC_FLAG_BE)
10223 printf(" branch-step trace mode\n");
10224 else if (env->flags & POWERPC_FLAG_DE)
10225 printf(" debug interrupt enable\n");
10226 if (env->flags & POWERPC_FLAG_PX)
10227 printf(" inclusive protection\n");
10228 else if (env->flags & POWERPC_FLAG_PMM)
10229 printf(" performance monitor mark\n");
10230 if (env->flags == POWERPC_FLAG_NONE)
10231 printf(" none\n");
10232 printf(" Time-base/decrementer clock source: %s\n",
10233 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
10234 }
10235 dump_ppc_insns(env);
10236 dump_ppc_sprs(env);
10237 fflush(stdout);
10238 #endif
10239
10240 return 0;
10241 }
10242
10243 static bool ppc_cpu_usable(const ppc_def_t *def)
10244 {
10245 #if defined(TARGET_PPCEMB)
10246 /* When using the ppcemb target, we only support 440 style cores */
10247 if (def->mmu_model != POWERPC_MMU_BOOKE) {
10248 return false;
10249 }
10250 #endif
10251
10252 return true;
10253 }
10254
10255 const ppc_def_t *ppc_find_by_pvr(uint32_t pvr)
10256 {
10257 int i;
10258
10259 for (i = 0; i < ARRAY_SIZE(ppc_defs); i++) {
10260 if (!ppc_cpu_usable(&ppc_defs[i])) {
10261 continue;
10262 }
10263
10264 /* If we have an exact match, we're done */
10265 if (pvr == ppc_defs[i].pvr) {
10266 return &ppc_defs[i];
10267 }
10268 }
10269
10270 return NULL;
10271 }
10272
10273 #include <ctype.h>
10274
10275 const ppc_def_t *cpu_ppc_find_by_name (const char *name)
10276 {
10277 const ppc_def_t *ret;
10278 const char *p;
10279 int i, max, len;
10280
10281 if (kvm_enabled() && (strcasecmp(name, "host") == 0)) {
10282 return kvmppc_host_cpu_def();
10283 }
10284
10285 /* Check if the given name is a PVR */
10286 len = strlen(name);
10287 if (len == 10 && name[0] == '0' && name[1] == 'x') {
10288 p = name + 2;
10289 goto check_pvr;
10290 } else if (len == 8) {
10291 p = name;
10292 check_pvr:
10293 for (i = 0; i < 8; i++) {
10294 if (!qemu_isxdigit(*p++))
10295 break;
10296 }
10297 if (i == 8)
10298 return ppc_find_by_pvr(strtoul(name, NULL, 16));
10299 }
10300 ret = NULL;
10301 max = ARRAY_SIZE(ppc_defs);
10302 for (i = 0; i < max; i++) {
10303 if (!ppc_cpu_usable(&ppc_defs[i])) {
10304 continue;
10305 }
10306
10307 if (strcasecmp(name, ppc_defs[i].name) == 0) {
10308 ret = &ppc_defs[i];
10309 break;
10310 }
10311 }
10312
10313 return ret;
10314 }
10315
10316 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
10317 {
10318 int i, max;
10319
10320 max = ARRAY_SIZE(ppc_defs);
10321 for (i = 0; i < max; i++) {
10322 if (!ppc_cpu_usable(&ppc_defs[i])) {
10323 continue;
10324 }
10325
10326 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
10327 ppc_defs[i].name, ppc_defs[i].pvr);
10328 }
10329 }
10330
10331 /* CPUClass::reset() */
10332 static void ppc_cpu_reset(CPUState *s)
10333 {
10334 PowerPCCPU *cpu = POWERPC_CPU(s);
10335 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10336 CPUPPCState *env = &cpu->env;
10337 target_ulong msr;
10338
10339 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
10340 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
10341 log_cpu_state(env, 0);
10342 }
10343
10344 pcc->parent_reset(s);
10345
10346 msr = (target_ulong)0;
10347 if (0) {
10348 /* XXX: find a suitable condition to enable the hypervisor mode */
10349 msr |= (target_ulong)MSR_HVB;
10350 }
10351 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
10352 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
10353 msr |= (target_ulong)1 << MSR_EP;
10354 #if defined(DO_SINGLE_STEP) && 0
10355 /* Single step trace mode */
10356 msr |= (target_ulong)1 << MSR_SE;
10357 msr |= (target_ulong)1 << MSR_BE;
10358 #endif
10359 #if defined(CONFIG_USER_ONLY)
10360 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
10361 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
10362 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
10363 msr |= (target_ulong)1 << MSR_PR;
10364 #else
10365 env->excp_prefix = env->hreset_excp_prefix;
10366 env->nip = env->hreset_vector | env->excp_prefix;
10367 if (env->mmu_model != POWERPC_MMU_REAL) {
10368 ppc_tlb_invalidate_all(env);
10369 }
10370 #endif
10371 env->msr = msr & env->msr_mask;
10372 #if defined(TARGET_PPC64)
10373 if (env->mmu_model & POWERPC_MMU_64) {
10374 env->msr |= (1ULL << MSR_SF);
10375 }
10376 #endif
10377 hreg_compute_hflags(env);
10378 env->reserve_addr = (target_ulong)-1ULL;
10379 /* Be sure no exception or interrupt is pending */
10380 env->pending_interrupts = 0;
10381 env->exception_index = POWERPC_EXCP_NONE;
10382 env->error_code = 0;
10383 /* Flush all TLBs */
10384 tlb_flush(env, 1);
10385 }
10386
10387 static void ppc_cpu_initfn(Object *obj)
10388 {
10389 PowerPCCPU *cpu = POWERPC_CPU(obj);
10390 CPUPPCState *env = &cpu->env;
10391
10392 cpu_exec_init(env);
10393 }
10394
10395 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
10396 {
10397 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10398 CPUClass *cc = CPU_CLASS(oc);
10399
10400 pcc->parent_reset = cc->reset;
10401 cc->reset = ppc_cpu_reset;
10402 }
10403
10404 static const TypeInfo ppc_cpu_type_info = {
10405 .name = TYPE_POWERPC_CPU,
10406 .parent = TYPE_CPU,
10407 .instance_size = sizeof(PowerPCCPU),
10408 .instance_init = ppc_cpu_initfn,
10409 .abstract = false,
10410 .class_size = sizeof(PowerPCCPUClass),
10411 .class_init = ppc_cpu_class_init,
10412 };
10413
10414 static void ppc_cpu_register_types(void)
10415 {
10416 type_register_static(&ppc_cpu_type_info);
10417 }
10418
10419 type_init(ppc_cpu_register_types)
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