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ppc: First cut implementation of -cpu host
[mirror_qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 /* A lot of PowerPC definition have been included here.
21 * Most of them are not usable for now but have been kept
22 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
23 */
24
25 #include "dis-asm.h"
26 #include "gdbstub.h"
27 #include <kvm.h>
28 #include "kvm_ppc.h"
29
30 //#define PPC_DUMP_CPU
31 //#define PPC_DEBUG_SPR
32 //#define PPC_DUMP_SPR_ACCESSES
33 #if defined(CONFIG_USER_ONLY)
34 #define TODO_USER_ONLY 1
35 #endif
36
37 struct ppc_def_t {
38 const char *name;
39 uint32_t pvr;
40 uint32_t svr;
41 uint64_t insns_flags;
42 uint64_t insns_flags2;
43 uint64_t msr_mask;
44 powerpc_mmu_t mmu_model;
45 powerpc_excp_t excp_model;
46 powerpc_input_t bus_model;
47 uint32_t flags;
48 int bfd_mach;
49 void (*init_proc)(CPUPPCState *env);
50 int (*check_pow)(CPUPPCState *env);
51 };
52
53 /* For user-mode emulation, we don't emulate any IRQ controller */
54 #if defined(CONFIG_USER_ONLY)
55 #define PPC_IRQ_INIT_FN(name) \
56 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
57 { \
58 }
59 #else
60 #define PPC_IRQ_INIT_FN(name) \
61 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
62 #endif
63
64 PPC_IRQ_INIT_FN(40x);
65 PPC_IRQ_INIT_FN(6xx);
66 PPC_IRQ_INIT_FN(970);
67 PPC_IRQ_INIT_FN(POWER7);
68 PPC_IRQ_INIT_FN(e500);
69
70 /* Generic callbacks:
71 * do nothing but store/retrieve spr value
72 */
73 static void spr_read_generic (void *opaque, int gprn, int sprn)
74 {
75 gen_load_spr(cpu_gpr[gprn], sprn);
76 #ifdef PPC_DUMP_SPR_ACCESSES
77 {
78 TCGv_i32 t0 = tcg_const_i32(sprn);
79 gen_helper_load_dump_spr(t0);
80 tcg_temp_free_i32(t0);
81 }
82 #endif
83 }
84
85 static void spr_write_generic (void *opaque, int sprn, int gprn)
86 {
87 gen_store_spr(sprn, cpu_gpr[gprn]);
88 #ifdef PPC_DUMP_SPR_ACCESSES
89 {
90 TCGv_i32 t0 = tcg_const_i32(sprn);
91 gen_helper_store_dump_spr(t0);
92 tcg_temp_free_i32(t0);
93 }
94 #endif
95 }
96
97 #if !defined(CONFIG_USER_ONLY)
98 static void spr_write_clear (void *opaque, int sprn, int gprn)
99 {
100 TCGv t0 = tcg_temp_new();
101 TCGv t1 = tcg_temp_new();
102 gen_load_spr(t0, sprn);
103 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
104 tcg_gen_and_tl(t0, t0, t1);
105 gen_store_spr(sprn, t0);
106 tcg_temp_free(t0);
107 tcg_temp_free(t1);
108 }
109 #endif
110
111 /* SPR common to all PowerPC */
112 /* XER */
113 static void spr_read_xer (void *opaque, int gprn, int sprn)
114 {
115 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
116 }
117
118 static void spr_write_xer (void *opaque, int sprn, int gprn)
119 {
120 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
121 }
122
123 /* LR */
124 static void spr_read_lr (void *opaque, int gprn, int sprn)
125 {
126 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
127 }
128
129 static void spr_write_lr (void *opaque, int sprn, int gprn)
130 {
131 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
132 }
133
134 /* CFAR */
135 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
136 static void spr_read_cfar (void *opaque, int gprn, int sprn)
137 {
138 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
139 }
140
141 static void spr_write_cfar (void *opaque, int sprn, int gprn)
142 {
143 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
144 }
145 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
146
147 /* CTR */
148 static void spr_read_ctr (void *opaque, int gprn, int sprn)
149 {
150 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
151 }
152
153 static void spr_write_ctr (void *opaque, int sprn, int gprn)
154 {
155 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
156 }
157
158 /* User read access to SPR */
159 /* USPRx */
160 /* UMMCRx */
161 /* UPMCx */
162 /* USIA */
163 /* UDECR */
164 static void spr_read_ureg (void *opaque, int gprn, int sprn)
165 {
166 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
167 }
168
169 /* SPR common to all non-embedded PowerPC */
170 /* DECR */
171 #if !defined(CONFIG_USER_ONLY)
172 static void spr_read_decr (void *opaque, int gprn, int sprn)
173 {
174 if (use_icount) {
175 gen_io_start();
176 }
177 gen_helper_load_decr(cpu_gpr[gprn]);
178 if (use_icount) {
179 gen_io_end();
180 gen_stop_exception(opaque);
181 }
182 }
183
184 static void spr_write_decr (void *opaque, int sprn, int gprn)
185 {
186 if (use_icount) {
187 gen_io_start();
188 }
189 gen_helper_store_decr(cpu_gpr[gprn]);
190 if (use_icount) {
191 gen_io_end();
192 gen_stop_exception(opaque);
193 }
194 }
195 #endif
196
197 /* SPR common to all non-embedded PowerPC, except 601 */
198 /* Time base */
199 static void spr_read_tbl (void *opaque, int gprn, int sprn)
200 {
201 if (use_icount) {
202 gen_io_start();
203 }
204 gen_helper_load_tbl(cpu_gpr[gprn]);
205 if (use_icount) {
206 gen_io_end();
207 gen_stop_exception(opaque);
208 }
209 }
210
211 static void spr_read_tbu (void *opaque, int gprn, int sprn)
212 {
213 if (use_icount) {
214 gen_io_start();
215 }
216 gen_helper_load_tbu(cpu_gpr[gprn]);
217 if (use_icount) {
218 gen_io_end();
219 gen_stop_exception(opaque);
220 }
221 }
222
223 __attribute__ (( unused ))
224 static void spr_read_atbl (void *opaque, int gprn, int sprn)
225 {
226 gen_helper_load_atbl(cpu_gpr[gprn]);
227 }
228
229 __attribute__ (( unused ))
230 static void spr_read_atbu (void *opaque, int gprn, int sprn)
231 {
232 gen_helper_load_atbu(cpu_gpr[gprn]);
233 }
234
235 #if !defined(CONFIG_USER_ONLY)
236 static void spr_write_tbl (void *opaque, int sprn, int gprn)
237 {
238 if (use_icount) {
239 gen_io_start();
240 }
241 gen_helper_store_tbl(cpu_gpr[gprn]);
242 if (use_icount) {
243 gen_io_end();
244 gen_stop_exception(opaque);
245 }
246 }
247
248 static void spr_write_tbu (void *opaque, int sprn, int gprn)
249 {
250 if (use_icount) {
251 gen_io_start();
252 }
253 gen_helper_store_tbu(cpu_gpr[gprn]);
254 if (use_icount) {
255 gen_io_end();
256 gen_stop_exception(opaque);
257 }
258 }
259
260 __attribute__ (( unused ))
261 static void spr_write_atbl (void *opaque, int sprn, int gprn)
262 {
263 gen_helper_store_atbl(cpu_gpr[gprn]);
264 }
265
266 __attribute__ (( unused ))
267 static void spr_write_atbu (void *opaque, int sprn, int gprn)
268 {
269 gen_helper_store_atbu(cpu_gpr[gprn]);
270 }
271
272 #if defined(TARGET_PPC64)
273 __attribute__ (( unused ))
274 static void spr_read_purr (void *opaque, int gprn, int sprn)
275 {
276 gen_helper_load_purr(cpu_gpr[gprn]);
277 }
278 #endif
279 #endif
280
281 #if !defined(CONFIG_USER_ONLY)
282 /* IBAT0U...IBAT0U */
283 /* IBAT0L...IBAT7L */
284 static void spr_read_ibat (void *opaque, int gprn, int sprn)
285 {
286 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
287 }
288
289 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
290 {
291 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
292 }
293
294 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
295 {
296 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
297 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
298 tcg_temp_free_i32(t0);
299 }
300
301 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
302 {
303 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
304 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
305 tcg_temp_free_i32(t0);
306 }
307
308 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
309 {
310 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
311 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
312 tcg_temp_free_i32(t0);
313 }
314
315 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
316 {
317 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
318 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
319 tcg_temp_free_i32(t0);
320 }
321
322 /* DBAT0U...DBAT7U */
323 /* DBAT0L...DBAT7L */
324 static void spr_read_dbat (void *opaque, int gprn, int sprn)
325 {
326 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
327 }
328
329 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
330 {
331 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
332 }
333
334 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
335 {
336 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
337 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
338 tcg_temp_free_i32(t0);
339 }
340
341 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
342 {
343 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
344 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
345 tcg_temp_free_i32(t0);
346 }
347
348 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
349 {
350 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
351 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
352 tcg_temp_free_i32(t0);
353 }
354
355 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
356 {
357 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
358 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
359 tcg_temp_free_i32(t0);
360 }
361
362 /* SDR1 */
363 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
364 {
365 gen_helper_store_sdr1(cpu_gpr[gprn]);
366 }
367
368 /* 64 bits PowerPC specific SPRs */
369 /* ASR */
370 #if defined(TARGET_PPC64)
371 static void spr_read_hior (void *opaque, int gprn, int sprn)
372 {
373 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
374 }
375
376 static void spr_write_hior (void *opaque, int sprn, int gprn)
377 {
378 TCGv t0 = tcg_temp_new();
379 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
380 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
381 tcg_temp_free(t0);
382 }
383
384 static void spr_read_asr (void *opaque, int gprn, int sprn)
385 {
386 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
387 }
388
389 static void spr_write_asr (void *opaque, int sprn, int gprn)
390 {
391 gen_helper_store_asr(cpu_gpr[gprn]);
392 }
393 #endif
394 #endif
395
396 /* PowerPC 601 specific registers */
397 /* RTC */
398 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
399 {
400 gen_helper_load_601_rtcl(cpu_gpr[gprn]);
401 }
402
403 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
404 {
405 gen_helper_load_601_rtcu(cpu_gpr[gprn]);
406 }
407
408 #if !defined(CONFIG_USER_ONLY)
409 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
410 {
411 gen_helper_store_601_rtcu(cpu_gpr[gprn]);
412 }
413
414 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
415 {
416 gen_helper_store_601_rtcl(cpu_gpr[gprn]);
417 }
418
419 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
420 {
421 DisasContext *ctx = opaque;
422
423 gen_helper_store_hid0_601(cpu_gpr[gprn]);
424 /* Must stop the translation as endianness may have changed */
425 gen_stop_exception(ctx);
426 }
427 #endif
428
429 /* Unified bats */
430 #if !defined(CONFIG_USER_ONLY)
431 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
432 {
433 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
434 }
435
436 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
437 {
438 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
439 gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
440 tcg_temp_free_i32(t0);
441 }
442
443 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
444 {
445 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
446 gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
447 tcg_temp_free_i32(t0);
448 }
449 #endif
450
451 /* PowerPC 40x specific registers */
452 #if !defined(CONFIG_USER_ONLY)
453 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
454 {
455 gen_helper_load_40x_pit(cpu_gpr[gprn]);
456 }
457
458 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
459 {
460 gen_helper_store_40x_pit(cpu_gpr[gprn]);
461 }
462
463 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
464 {
465 DisasContext *ctx = opaque;
466
467 gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
468 /* We must stop translation as we may have rebooted */
469 gen_stop_exception(ctx);
470 }
471
472 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
473 {
474 gen_helper_store_40x_sler(cpu_gpr[gprn]);
475 }
476
477 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
478 {
479 gen_helper_store_booke_tcr(cpu_gpr[gprn]);
480 }
481
482 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
483 {
484 gen_helper_store_booke_tsr(cpu_gpr[gprn]);
485 }
486 #endif
487
488 /* PowerPC 403 specific registers */
489 /* PBL1 / PBU1 / PBL2 / PBU2 */
490 #if !defined(CONFIG_USER_ONLY)
491 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
492 {
493 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
494 }
495
496 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
497 {
498 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
499 gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
500 tcg_temp_free_i32(t0);
501 }
502
503 static void spr_write_pir (void *opaque, int sprn, int gprn)
504 {
505 TCGv t0 = tcg_temp_new();
506 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
507 gen_store_spr(SPR_PIR, t0);
508 tcg_temp_free(t0);
509 }
510 #endif
511
512 /* SPE specific registers */
513 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
514 {
515 TCGv_i32 t0 = tcg_temp_new_i32();
516 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
517 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
518 tcg_temp_free_i32(t0);
519 }
520
521 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
522 {
523 TCGv_i32 t0 = tcg_temp_new_i32();
524 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
525 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
526 tcg_temp_free_i32(t0);
527 }
528
529 #if !defined(CONFIG_USER_ONLY)
530 /* Callback used to write the exception vector base */
531 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
532 {
533 TCGv t0 = tcg_temp_new();
534 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
535 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
536 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
537 gen_store_spr(sprn, t0);
538 tcg_temp_free(t0);
539 }
540
541 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
542 {
543 DisasContext *ctx = opaque;
544
545 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
546 TCGv t0 = tcg_temp_new();
547 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
548 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
549 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
550 gen_store_spr(sprn, t0);
551 tcg_temp_free(t0);
552 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
553 TCGv t0 = tcg_temp_new();
554 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
555 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
556 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
557 gen_store_spr(sprn, t0);
558 tcg_temp_free(t0);
559 } else {
560 printf("Trying to write an unknown exception vector %d %03x\n",
561 sprn, sprn);
562 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
563 }
564 }
565 #endif
566
567 static inline void vscr_init (CPUPPCState *env, uint32_t val)
568 {
569 env->vscr = val;
570 /* Altivec always uses round-to-nearest */
571 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
572 set_flush_to_zero(vscr_nj, &env->vec_status);
573 }
574
575 #if defined(CONFIG_USER_ONLY)
576 #define spr_register(env, num, name, uea_read, uea_write, \
577 oea_read, oea_write, initial_value) \
578 do { \
579 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
580 } while (0)
581 static inline void _spr_register (CPUPPCState *env, int num,
582 const char *name,
583 void (*uea_read)(void *opaque, int gprn, int sprn),
584 void (*uea_write)(void *opaque, int sprn, int gprn),
585 target_ulong initial_value)
586 #else
587 static inline void spr_register (CPUPPCState *env, int num,
588 const char *name,
589 void (*uea_read)(void *opaque, int gprn, int sprn),
590 void (*uea_write)(void *opaque, int sprn, int gprn),
591 void (*oea_read)(void *opaque, int gprn, int sprn),
592 void (*oea_write)(void *opaque, int sprn, int gprn),
593 target_ulong initial_value)
594 #endif
595 {
596 ppc_spr_t *spr;
597
598 spr = &env->spr_cb[num];
599 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
600 #if !defined(CONFIG_USER_ONLY)
601 spr->oea_read != NULL || spr->oea_write != NULL ||
602 #endif
603 spr->uea_read != NULL || spr->uea_write != NULL) {
604 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
605 exit(1);
606 }
607 #if defined(PPC_DEBUG_SPR)
608 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
609 name, initial_value);
610 #endif
611 spr->name = name;
612 spr->uea_read = uea_read;
613 spr->uea_write = uea_write;
614 #if !defined(CONFIG_USER_ONLY)
615 spr->oea_read = oea_read;
616 spr->oea_write = oea_write;
617 #endif
618 env->spr[num] = initial_value;
619 }
620
621 /* Generic PowerPC SPRs */
622 static void gen_spr_generic (CPUPPCState *env)
623 {
624 /* Integer processing */
625 spr_register(env, SPR_XER, "XER",
626 &spr_read_xer, &spr_write_xer,
627 &spr_read_xer, &spr_write_xer,
628 0x00000000);
629 /* Branch contol */
630 spr_register(env, SPR_LR, "LR",
631 &spr_read_lr, &spr_write_lr,
632 &spr_read_lr, &spr_write_lr,
633 0x00000000);
634 spr_register(env, SPR_CTR, "CTR",
635 &spr_read_ctr, &spr_write_ctr,
636 &spr_read_ctr, &spr_write_ctr,
637 0x00000000);
638 /* Interrupt processing */
639 spr_register(env, SPR_SRR0, "SRR0",
640 SPR_NOACCESS, SPR_NOACCESS,
641 &spr_read_generic, &spr_write_generic,
642 0x00000000);
643 spr_register(env, SPR_SRR1, "SRR1",
644 SPR_NOACCESS, SPR_NOACCESS,
645 &spr_read_generic, &spr_write_generic,
646 0x00000000);
647 /* Processor control */
648 spr_register(env, SPR_SPRG0, "SPRG0",
649 SPR_NOACCESS, SPR_NOACCESS,
650 &spr_read_generic, &spr_write_generic,
651 0x00000000);
652 spr_register(env, SPR_SPRG1, "SPRG1",
653 SPR_NOACCESS, SPR_NOACCESS,
654 &spr_read_generic, &spr_write_generic,
655 0x00000000);
656 spr_register(env, SPR_SPRG2, "SPRG2",
657 SPR_NOACCESS, SPR_NOACCESS,
658 &spr_read_generic, &spr_write_generic,
659 0x00000000);
660 spr_register(env, SPR_SPRG3, "SPRG3",
661 SPR_NOACCESS, SPR_NOACCESS,
662 &spr_read_generic, &spr_write_generic,
663 0x00000000);
664 }
665
666 /* SPR common to all non-embedded PowerPC, including 601 */
667 static void gen_spr_ne_601 (CPUPPCState *env)
668 {
669 /* Exception processing */
670 spr_register(env, SPR_DSISR, "DSISR",
671 SPR_NOACCESS, SPR_NOACCESS,
672 &spr_read_generic, &spr_write_generic,
673 0x00000000);
674 spr_register(env, SPR_DAR, "DAR",
675 SPR_NOACCESS, SPR_NOACCESS,
676 &spr_read_generic, &spr_write_generic,
677 0x00000000);
678 /* Timer */
679 spr_register(env, SPR_DECR, "DECR",
680 SPR_NOACCESS, SPR_NOACCESS,
681 &spr_read_decr, &spr_write_decr,
682 0x00000000);
683 /* Memory management */
684 spr_register(env, SPR_SDR1, "SDR1",
685 SPR_NOACCESS, SPR_NOACCESS,
686 &spr_read_generic, &spr_write_sdr1,
687 0x00000000);
688 }
689
690 /* BATs 0-3 */
691 static void gen_low_BATs (CPUPPCState *env)
692 {
693 #if !defined(CONFIG_USER_ONLY)
694 spr_register(env, SPR_IBAT0U, "IBAT0U",
695 SPR_NOACCESS, SPR_NOACCESS,
696 &spr_read_ibat, &spr_write_ibatu,
697 0x00000000);
698 spr_register(env, SPR_IBAT0L, "IBAT0L",
699 SPR_NOACCESS, SPR_NOACCESS,
700 &spr_read_ibat, &spr_write_ibatl,
701 0x00000000);
702 spr_register(env, SPR_IBAT1U, "IBAT1U",
703 SPR_NOACCESS, SPR_NOACCESS,
704 &spr_read_ibat, &spr_write_ibatu,
705 0x00000000);
706 spr_register(env, SPR_IBAT1L, "IBAT1L",
707 SPR_NOACCESS, SPR_NOACCESS,
708 &spr_read_ibat, &spr_write_ibatl,
709 0x00000000);
710 spr_register(env, SPR_IBAT2U, "IBAT2U",
711 SPR_NOACCESS, SPR_NOACCESS,
712 &spr_read_ibat, &spr_write_ibatu,
713 0x00000000);
714 spr_register(env, SPR_IBAT2L, "IBAT2L",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_ibat, &spr_write_ibatl,
717 0x00000000);
718 spr_register(env, SPR_IBAT3U, "IBAT3U",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_ibat, &spr_write_ibatu,
721 0x00000000);
722 spr_register(env, SPR_IBAT3L, "IBAT3L",
723 SPR_NOACCESS, SPR_NOACCESS,
724 &spr_read_ibat, &spr_write_ibatl,
725 0x00000000);
726 spr_register(env, SPR_DBAT0U, "DBAT0U",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_dbat, &spr_write_dbatu,
729 0x00000000);
730 spr_register(env, SPR_DBAT0L, "DBAT0L",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_dbat, &spr_write_dbatl,
733 0x00000000);
734 spr_register(env, SPR_DBAT1U, "DBAT1U",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_dbat, &spr_write_dbatu,
737 0x00000000);
738 spr_register(env, SPR_DBAT1L, "DBAT1L",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_dbat, &spr_write_dbatl,
741 0x00000000);
742 spr_register(env, SPR_DBAT2U, "DBAT2U",
743 SPR_NOACCESS, SPR_NOACCESS,
744 &spr_read_dbat, &spr_write_dbatu,
745 0x00000000);
746 spr_register(env, SPR_DBAT2L, "DBAT2L",
747 SPR_NOACCESS, SPR_NOACCESS,
748 &spr_read_dbat, &spr_write_dbatl,
749 0x00000000);
750 spr_register(env, SPR_DBAT3U, "DBAT3U",
751 SPR_NOACCESS, SPR_NOACCESS,
752 &spr_read_dbat, &spr_write_dbatu,
753 0x00000000);
754 spr_register(env, SPR_DBAT3L, "DBAT3L",
755 SPR_NOACCESS, SPR_NOACCESS,
756 &spr_read_dbat, &spr_write_dbatl,
757 0x00000000);
758 env->nb_BATs += 4;
759 #endif
760 }
761
762 /* BATs 4-7 */
763 static void gen_high_BATs (CPUPPCState *env)
764 {
765 #if !defined(CONFIG_USER_ONLY)
766 spr_register(env, SPR_IBAT4U, "IBAT4U",
767 SPR_NOACCESS, SPR_NOACCESS,
768 &spr_read_ibat_h, &spr_write_ibatu_h,
769 0x00000000);
770 spr_register(env, SPR_IBAT4L, "IBAT4L",
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_ibat_h, &spr_write_ibatl_h,
773 0x00000000);
774 spr_register(env, SPR_IBAT5U, "IBAT5U",
775 SPR_NOACCESS, SPR_NOACCESS,
776 &spr_read_ibat_h, &spr_write_ibatu_h,
777 0x00000000);
778 spr_register(env, SPR_IBAT5L, "IBAT5L",
779 SPR_NOACCESS, SPR_NOACCESS,
780 &spr_read_ibat_h, &spr_write_ibatl_h,
781 0x00000000);
782 spr_register(env, SPR_IBAT6U, "IBAT6U",
783 SPR_NOACCESS, SPR_NOACCESS,
784 &spr_read_ibat_h, &spr_write_ibatu_h,
785 0x00000000);
786 spr_register(env, SPR_IBAT6L, "IBAT6L",
787 SPR_NOACCESS, SPR_NOACCESS,
788 &spr_read_ibat_h, &spr_write_ibatl_h,
789 0x00000000);
790 spr_register(env, SPR_IBAT7U, "IBAT7U",
791 SPR_NOACCESS, SPR_NOACCESS,
792 &spr_read_ibat_h, &spr_write_ibatu_h,
793 0x00000000);
794 spr_register(env, SPR_IBAT7L, "IBAT7L",
795 SPR_NOACCESS, SPR_NOACCESS,
796 &spr_read_ibat_h, &spr_write_ibatl_h,
797 0x00000000);
798 spr_register(env, SPR_DBAT4U, "DBAT4U",
799 SPR_NOACCESS, SPR_NOACCESS,
800 &spr_read_dbat_h, &spr_write_dbatu_h,
801 0x00000000);
802 spr_register(env, SPR_DBAT4L, "DBAT4L",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_dbat_h, &spr_write_dbatl_h,
805 0x00000000);
806 spr_register(env, SPR_DBAT5U, "DBAT5U",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_dbat_h, &spr_write_dbatu_h,
809 0x00000000);
810 spr_register(env, SPR_DBAT5L, "DBAT5L",
811 SPR_NOACCESS, SPR_NOACCESS,
812 &spr_read_dbat_h, &spr_write_dbatl_h,
813 0x00000000);
814 spr_register(env, SPR_DBAT6U, "DBAT6U",
815 SPR_NOACCESS, SPR_NOACCESS,
816 &spr_read_dbat_h, &spr_write_dbatu_h,
817 0x00000000);
818 spr_register(env, SPR_DBAT6L, "DBAT6L",
819 SPR_NOACCESS, SPR_NOACCESS,
820 &spr_read_dbat_h, &spr_write_dbatl_h,
821 0x00000000);
822 spr_register(env, SPR_DBAT7U, "DBAT7U",
823 SPR_NOACCESS, SPR_NOACCESS,
824 &spr_read_dbat_h, &spr_write_dbatu_h,
825 0x00000000);
826 spr_register(env, SPR_DBAT7L, "DBAT7L",
827 SPR_NOACCESS, SPR_NOACCESS,
828 &spr_read_dbat_h, &spr_write_dbatl_h,
829 0x00000000);
830 env->nb_BATs += 4;
831 #endif
832 }
833
834 /* Generic PowerPC time base */
835 static void gen_tbl (CPUPPCState *env)
836 {
837 spr_register(env, SPR_VTBL, "TBL",
838 &spr_read_tbl, SPR_NOACCESS,
839 &spr_read_tbl, SPR_NOACCESS,
840 0x00000000);
841 spr_register(env, SPR_TBL, "TBL",
842 &spr_read_tbl, SPR_NOACCESS,
843 &spr_read_tbl, &spr_write_tbl,
844 0x00000000);
845 spr_register(env, SPR_VTBU, "TBU",
846 &spr_read_tbu, SPR_NOACCESS,
847 &spr_read_tbu, SPR_NOACCESS,
848 0x00000000);
849 spr_register(env, SPR_TBU, "TBU",
850 &spr_read_tbu, SPR_NOACCESS,
851 &spr_read_tbu, &spr_write_tbu,
852 0x00000000);
853 }
854
855 /* Softare table search registers */
856 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
857 {
858 #if !defined(CONFIG_USER_ONLY)
859 env->nb_tlb = nb_tlbs;
860 env->nb_ways = nb_ways;
861 env->id_tlbs = 1;
862 env->tlb_type = TLB_6XX;
863 spr_register(env, SPR_DMISS, "DMISS",
864 SPR_NOACCESS, SPR_NOACCESS,
865 &spr_read_generic, SPR_NOACCESS,
866 0x00000000);
867 spr_register(env, SPR_DCMP, "DCMP",
868 SPR_NOACCESS, SPR_NOACCESS,
869 &spr_read_generic, SPR_NOACCESS,
870 0x00000000);
871 spr_register(env, SPR_HASH1, "HASH1",
872 SPR_NOACCESS, SPR_NOACCESS,
873 &spr_read_generic, SPR_NOACCESS,
874 0x00000000);
875 spr_register(env, SPR_HASH2, "HASH2",
876 SPR_NOACCESS, SPR_NOACCESS,
877 &spr_read_generic, SPR_NOACCESS,
878 0x00000000);
879 spr_register(env, SPR_IMISS, "IMISS",
880 SPR_NOACCESS, SPR_NOACCESS,
881 &spr_read_generic, SPR_NOACCESS,
882 0x00000000);
883 spr_register(env, SPR_ICMP, "ICMP",
884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_generic, SPR_NOACCESS,
886 0x00000000);
887 spr_register(env, SPR_RPA, "RPA",
888 SPR_NOACCESS, SPR_NOACCESS,
889 &spr_read_generic, &spr_write_generic,
890 0x00000000);
891 #endif
892 }
893
894 /* SPR common to MPC755 and G2 */
895 static void gen_spr_G2_755 (CPUPPCState *env)
896 {
897 /* SGPRs */
898 spr_register(env, SPR_SPRG4, "SPRG4",
899 SPR_NOACCESS, SPR_NOACCESS,
900 &spr_read_generic, &spr_write_generic,
901 0x00000000);
902 spr_register(env, SPR_SPRG5, "SPRG5",
903 SPR_NOACCESS, SPR_NOACCESS,
904 &spr_read_generic, &spr_write_generic,
905 0x00000000);
906 spr_register(env, SPR_SPRG6, "SPRG6",
907 SPR_NOACCESS, SPR_NOACCESS,
908 &spr_read_generic, &spr_write_generic,
909 0x00000000);
910 spr_register(env, SPR_SPRG7, "SPRG7",
911 SPR_NOACCESS, SPR_NOACCESS,
912 &spr_read_generic, &spr_write_generic,
913 0x00000000);
914 }
915
916 /* SPR common to all 7xx PowerPC implementations */
917 static void gen_spr_7xx (CPUPPCState *env)
918 {
919 /* Breakpoints */
920 /* XXX : not implemented */
921 spr_register(env, SPR_DABR, "DABR",
922 SPR_NOACCESS, SPR_NOACCESS,
923 &spr_read_generic, &spr_write_generic,
924 0x00000000);
925 /* XXX : not implemented */
926 spr_register(env, SPR_IABR, "IABR",
927 SPR_NOACCESS, SPR_NOACCESS,
928 &spr_read_generic, &spr_write_generic,
929 0x00000000);
930 /* Cache management */
931 /* XXX : not implemented */
932 spr_register(env, SPR_ICTC, "ICTC",
933 SPR_NOACCESS, SPR_NOACCESS,
934 &spr_read_generic, &spr_write_generic,
935 0x00000000);
936 /* Performance monitors */
937 /* XXX : not implemented */
938 spr_register(env, SPR_MMCR0, "MMCR0",
939 SPR_NOACCESS, SPR_NOACCESS,
940 &spr_read_generic, &spr_write_generic,
941 0x00000000);
942 /* XXX : not implemented */
943 spr_register(env, SPR_MMCR1, "MMCR1",
944 SPR_NOACCESS, SPR_NOACCESS,
945 &spr_read_generic, &spr_write_generic,
946 0x00000000);
947 /* XXX : not implemented */
948 spr_register(env, SPR_PMC1, "PMC1",
949 SPR_NOACCESS, SPR_NOACCESS,
950 &spr_read_generic, &spr_write_generic,
951 0x00000000);
952 /* XXX : not implemented */
953 spr_register(env, SPR_PMC2, "PMC2",
954 SPR_NOACCESS, SPR_NOACCESS,
955 &spr_read_generic, &spr_write_generic,
956 0x00000000);
957 /* XXX : not implemented */
958 spr_register(env, SPR_PMC3, "PMC3",
959 SPR_NOACCESS, SPR_NOACCESS,
960 &spr_read_generic, &spr_write_generic,
961 0x00000000);
962 /* XXX : not implemented */
963 spr_register(env, SPR_PMC4, "PMC4",
964 SPR_NOACCESS, SPR_NOACCESS,
965 &spr_read_generic, &spr_write_generic,
966 0x00000000);
967 /* XXX : not implemented */
968 spr_register(env, SPR_SIAR, "SIAR",
969 SPR_NOACCESS, SPR_NOACCESS,
970 &spr_read_generic, SPR_NOACCESS,
971 0x00000000);
972 /* XXX : not implemented */
973 spr_register(env, SPR_UMMCR0, "UMMCR0",
974 &spr_read_ureg, SPR_NOACCESS,
975 &spr_read_ureg, SPR_NOACCESS,
976 0x00000000);
977 /* XXX : not implemented */
978 spr_register(env, SPR_UMMCR1, "UMMCR1",
979 &spr_read_ureg, SPR_NOACCESS,
980 &spr_read_ureg, SPR_NOACCESS,
981 0x00000000);
982 /* XXX : not implemented */
983 spr_register(env, SPR_UPMC1, "UPMC1",
984 &spr_read_ureg, SPR_NOACCESS,
985 &spr_read_ureg, SPR_NOACCESS,
986 0x00000000);
987 /* XXX : not implemented */
988 spr_register(env, SPR_UPMC2, "UPMC2",
989 &spr_read_ureg, SPR_NOACCESS,
990 &spr_read_ureg, SPR_NOACCESS,
991 0x00000000);
992 /* XXX : not implemented */
993 spr_register(env, SPR_UPMC3, "UPMC3",
994 &spr_read_ureg, SPR_NOACCESS,
995 &spr_read_ureg, SPR_NOACCESS,
996 0x00000000);
997 /* XXX : not implemented */
998 spr_register(env, SPR_UPMC4, "UPMC4",
999 &spr_read_ureg, SPR_NOACCESS,
1000 &spr_read_ureg, SPR_NOACCESS,
1001 0x00000000);
1002 /* XXX : not implemented */
1003 spr_register(env, SPR_USIAR, "USIAR",
1004 &spr_read_ureg, SPR_NOACCESS,
1005 &spr_read_ureg, SPR_NOACCESS,
1006 0x00000000);
1007 /* External access control */
1008 /* XXX : not implemented */
1009 spr_register(env, SPR_EAR, "EAR",
1010 SPR_NOACCESS, SPR_NOACCESS,
1011 &spr_read_generic, &spr_write_generic,
1012 0x00000000);
1013 }
1014
1015 static void gen_spr_thrm (CPUPPCState *env)
1016 {
1017 /* Thermal management */
1018 /* XXX : not implemented */
1019 spr_register(env, SPR_THRM1, "THRM1",
1020 SPR_NOACCESS, SPR_NOACCESS,
1021 &spr_read_generic, &spr_write_generic,
1022 0x00000000);
1023 /* XXX : not implemented */
1024 spr_register(env, SPR_THRM2, "THRM2",
1025 SPR_NOACCESS, SPR_NOACCESS,
1026 &spr_read_generic, &spr_write_generic,
1027 0x00000000);
1028 /* XXX : not implemented */
1029 spr_register(env, SPR_THRM3, "THRM3",
1030 SPR_NOACCESS, SPR_NOACCESS,
1031 &spr_read_generic, &spr_write_generic,
1032 0x00000000);
1033 }
1034
1035 /* SPR specific to PowerPC 604 implementation */
1036 static void gen_spr_604 (CPUPPCState *env)
1037 {
1038 /* Processor identification */
1039 spr_register(env, SPR_PIR, "PIR",
1040 SPR_NOACCESS, SPR_NOACCESS,
1041 &spr_read_generic, &spr_write_pir,
1042 0x00000000);
1043 /* Breakpoints */
1044 /* XXX : not implemented */
1045 spr_register(env, SPR_IABR, "IABR",
1046 SPR_NOACCESS, SPR_NOACCESS,
1047 &spr_read_generic, &spr_write_generic,
1048 0x00000000);
1049 /* XXX : not implemented */
1050 spr_register(env, SPR_DABR, "DABR",
1051 SPR_NOACCESS, SPR_NOACCESS,
1052 &spr_read_generic, &spr_write_generic,
1053 0x00000000);
1054 /* Performance counters */
1055 /* XXX : not implemented */
1056 spr_register(env, SPR_MMCR0, "MMCR0",
1057 SPR_NOACCESS, SPR_NOACCESS,
1058 &spr_read_generic, &spr_write_generic,
1059 0x00000000);
1060 /* XXX : not implemented */
1061 spr_register(env, SPR_PMC1, "PMC1",
1062 SPR_NOACCESS, SPR_NOACCESS,
1063 &spr_read_generic, &spr_write_generic,
1064 0x00000000);
1065 /* XXX : not implemented */
1066 spr_register(env, SPR_PMC2, "PMC2",
1067 SPR_NOACCESS, SPR_NOACCESS,
1068 &spr_read_generic, &spr_write_generic,
1069 0x00000000);
1070 /* XXX : not implemented */
1071 spr_register(env, SPR_SIAR, "SIAR",
1072 SPR_NOACCESS, SPR_NOACCESS,
1073 &spr_read_generic, SPR_NOACCESS,
1074 0x00000000);
1075 /* XXX : not implemented */
1076 spr_register(env, SPR_SDA, "SDA",
1077 SPR_NOACCESS, SPR_NOACCESS,
1078 &spr_read_generic, SPR_NOACCESS,
1079 0x00000000);
1080 /* External access control */
1081 /* XXX : not implemented */
1082 spr_register(env, SPR_EAR, "EAR",
1083 SPR_NOACCESS, SPR_NOACCESS,
1084 &spr_read_generic, &spr_write_generic,
1085 0x00000000);
1086 }
1087
1088 /* SPR specific to PowerPC 603 implementation */
1089 static void gen_spr_603 (CPUPPCState *env)
1090 {
1091 /* External access control */
1092 /* XXX : not implemented */
1093 spr_register(env, SPR_EAR, "EAR",
1094 SPR_NOACCESS, SPR_NOACCESS,
1095 &spr_read_generic, &spr_write_generic,
1096 0x00000000);
1097 }
1098
1099 /* SPR specific to PowerPC G2 implementation */
1100 static void gen_spr_G2 (CPUPPCState *env)
1101 {
1102 /* Memory base address */
1103 /* MBAR */
1104 /* XXX : not implemented */
1105 spr_register(env, SPR_MBAR, "MBAR",
1106 SPR_NOACCESS, SPR_NOACCESS,
1107 &spr_read_generic, &spr_write_generic,
1108 0x00000000);
1109 /* Exception processing */
1110 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1111 SPR_NOACCESS, SPR_NOACCESS,
1112 &spr_read_generic, &spr_write_generic,
1113 0x00000000);
1114 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1115 SPR_NOACCESS, SPR_NOACCESS,
1116 &spr_read_generic, &spr_write_generic,
1117 0x00000000);
1118 /* Breakpoints */
1119 /* XXX : not implemented */
1120 spr_register(env, SPR_DABR, "DABR",
1121 SPR_NOACCESS, SPR_NOACCESS,
1122 &spr_read_generic, &spr_write_generic,
1123 0x00000000);
1124 /* XXX : not implemented */
1125 spr_register(env, SPR_DABR2, "DABR2",
1126 SPR_NOACCESS, SPR_NOACCESS,
1127 &spr_read_generic, &spr_write_generic,
1128 0x00000000);
1129 /* XXX : not implemented */
1130 spr_register(env, SPR_IABR, "IABR",
1131 SPR_NOACCESS, SPR_NOACCESS,
1132 &spr_read_generic, &spr_write_generic,
1133 0x00000000);
1134 /* XXX : not implemented */
1135 spr_register(env, SPR_IABR2, "IABR2",
1136 SPR_NOACCESS, SPR_NOACCESS,
1137 &spr_read_generic, &spr_write_generic,
1138 0x00000000);
1139 /* XXX : not implemented */
1140 spr_register(env, SPR_IBCR, "IBCR",
1141 SPR_NOACCESS, SPR_NOACCESS,
1142 &spr_read_generic, &spr_write_generic,
1143 0x00000000);
1144 /* XXX : not implemented */
1145 spr_register(env, SPR_DBCR, "DBCR",
1146 SPR_NOACCESS, SPR_NOACCESS,
1147 &spr_read_generic, &spr_write_generic,
1148 0x00000000);
1149 }
1150
1151 /* SPR specific to PowerPC 602 implementation */
1152 static void gen_spr_602 (CPUPPCState *env)
1153 {
1154 /* ESA registers */
1155 /* XXX : not implemented */
1156 spr_register(env, SPR_SER, "SER",
1157 SPR_NOACCESS, SPR_NOACCESS,
1158 &spr_read_generic, &spr_write_generic,
1159 0x00000000);
1160 /* XXX : not implemented */
1161 spr_register(env, SPR_SEBR, "SEBR",
1162 SPR_NOACCESS, SPR_NOACCESS,
1163 &spr_read_generic, &spr_write_generic,
1164 0x00000000);
1165 /* XXX : not implemented */
1166 spr_register(env, SPR_ESASRR, "ESASRR",
1167 SPR_NOACCESS, SPR_NOACCESS,
1168 &spr_read_generic, &spr_write_generic,
1169 0x00000000);
1170 /* Floating point status */
1171 /* XXX : not implemented */
1172 spr_register(env, SPR_SP, "SP",
1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_generic, &spr_write_generic,
1175 0x00000000);
1176 /* XXX : not implemented */
1177 spr_register(env, SPR_LT, "LT",
1178 SPR_NOACCESS, SPR_NOACCESS,
1179 &spr_read_generic, &spr_write_generic,
1180 0x00000000);
1181 /* Watchdog timer */
1182 /* XXX : not implemented */
1183 spr_register(env, SPR_TCR, "TCR",
1184 SPR_NOACCESS, SPR_NOACCESS,
1185 &spr_read_generic, &spr_write_generic,
1186 0x00000000);
1187 /* Interrupt base */
1188 spr_register(env, SPR_IBR, "IBR",
1189 SPR_NOACCESS, SPR_NOACCESS,
1190 &spr_read_generic, &spr_write_generic,
1191 0x00000000);
1192 /* XXX : not implemented */
1193 spr_register(env, SPR_IABR, "IABR",
1194 SPR_NOACCESS, SPR_NOACCESS,
1195 &spr_read_generic, &spr_write_generic,
1196 0x00000000);
1197 }
1198
1199 /* SPR specific to PowerPC 601 implementation */
1200 static void gen_spr_601 (CPUPPCState *env)
1201 {
1202 /* Multiplication/division register */
1203 /* MQ */
1204 spr_register(env, SPR_MQ, "MQ",
1205 &spr_read_generic, &spr_write_generic,
1206 &spr_read_generic, &spr_write_generic,
1207 0x00000000);
1208 /* RTC registers */
1209 spr_register(env, SPR_601_RTCU, "RTCU",
1210 SPR_NOACCESS, SPR_NOACCESS,
1211 SPR_NOACCESS, &spr_write_601_rtcu,
1212 0x00000000);
1213 spr_register(env, SPR_601_VRTCU, "RTCU",
1214 &spr_read_601_rtcu, SPR_NOACCESS,
1215 &spr_read_601_rtcu, SPR_NOACCESS,
1216 0x00000000);
1217 spr_register(env, SPR_601_RTCL, "RTCL",
1218 SPR_NOACCESS, SPR_NOACCESS,
1219 SPR_NOACCESS, &spr_write_601_rtcl,
1220 0x00000000);
1221 spr_register(env, SPR_601_VRTCL, "RTCL",
1222 &spr_read_601_rtcl, SPR_NOACCESS,
1223 &spr_read_601_rtcl, SPR_NOACCESS,
1224 0x00000000);
1225 /* Timer */
1226 #if 0 /* ? */
1227 spr_register(env, SPR_601_UDECR, "UDECR",
1228 &spr_read_decr, SPR_NOACCESS,
1229 &spr_read_decr, SPR_NOACCESS,
1230 0x00000000);
1231 #endif
1232 /* External access control */
1233 /* XXX : not implemented */
1234 spr_register(env, SPR_EAR, "EAR",
1235 SPR_NOACCESS, SPR_NOACCESS,
1236 &spr_read_generic, &spr_write_generic,
1237 0x00000000);
1238 /* Memory management */
1239 #if !defined(CONFIG_USER_ONLY)
1240 spr_register(env, SPR_IBAT0U, "IBAT0U",
1241 SPR_NOACCESS, SPR_NOACCESS,
1242 &spr_read_601_ubat, &spr_write_601_ubatu,
1243 0x00000000);
1244 spr_register(env, SPR_IBAT0L, "IBAT0L",
1245 SPR_NOACCESS, SPR_NOACCESS,
1246 &spr_read_601_ubat, &spr_write_601_ubatl,
1247 0x00000000);
1248 spr_register(env, SPR_IBAT1U, "IBAT1U",
1249 SPR_NOACCESS, SPR_NOACCESS,
1250 &spr_read_601_ubat, &spr_write_601_ubatu,
1251 0x00000000);
1252 spr_register(env, SPR_IBAT1L, "IBAT1L",
1253 SPR_NOACCESS, SPR_NOACCESS,
1254 &spr_read_601_ubat, &spr_write_601_ubatl,
1255 0x00000000);
1256 spr_register(env, SPR_IBAT2U, "IBAT2U",
1257 SPR_NOACCESS, SPR_NOACCESS,
1258 &spr_read_601_ubat, &spr_write_601_ubatu,
1259 0x00000000);
1260 spr_register(env, SPR_IBAT2L, "IBAT2L",
1261 SPR_NOACCESS, SPR_NOACCESS,
1262 &spr_read_601_ubat, &spr_write_601_ubatl,
1263 0x00000000);
1264 spr_register(env, SPR_IBAT3U, "IBAT3U",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_601_ubat, &spr_write_601_ubatu,
1267 0x00000000);
1268 spr_register(env, SPR_IBAT3L, "IBAT3L",
1269 SPR_NOACCESS, SPR_NOACCESS,
1270 &spr_read_601_ubat, &spr_write_601_ubatl,
1271 0x00000000);
1272 env->nb_BATs = 4;
1273 #endif
1274 }
1275
1276 static void gen_spr_74xx (CPUPPCState *env)
1277 {
1278 /* Processor identification */
1279 spr_register(env, SPR_PIR, "PIR",
1280 SPR_NOACCESS, SPR_NOACCESS,
1281 &spr_read_generic, &spr_write_pir,
1282 0x00000000);
1283 /* XXX : not implemented */
1284 spr_register(env, SPR_MMCR2, "MMCR2",
1285 SPR_NOACCESS, SPR_NOACCESS,
1286 &spr_read_generic, &spr_write_generic,
1287 0x00000000);
1288 /* XXX : not implemented */
1289 spr_register(env, SPR_UMMCR2, "UMMCR2",
1290 &spr_read_ureg, SPR_NOACCESS,
1291 &spr_read_ureg, SPR_NOACCESS,
1292 0x00000000);
1293 /* XXX: not implemented */
1294 spr_register(env, SPR_BAMR, "BAMR",
1295 SPR_NOACCESS, SPR_NOACCESS,
1296 &spr_read_generic, &spr_write_generic,
1297 0x00000000);
1298 /* XXX : not implemented */
1299 spr_register(env, SPR_MSSCR0, "MSSCR0",
1300 SPR_NOACCESS, SPR_NOACCESS,
1301 &spr_read_generic, &spr_write_generic,
1302 0x00000000);
1303 /* Hardware implementation registers */
1304 /* XXX : not implemented */
1305 spr_register(env, SPR_HID0, "HID0",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, &spr_write_generic,
1308 0x00000000);
1309 /* XXX : not implemented */
1310 spr_register(env, SPR_HID1, "HID1",
1311 SPR_NOACCESS, SPR_NOACCESS,
1312 &spr_read_generic, &spr_write_generic,
1313 0x00000000);
1314 /* Altivec */
1315 spr_register(env, SPR_VRSAVE, "VRSAVE",
1316 &spr_read_generic, &spr_write_generic,
1317 &spr_read_generic, &spr_write_generic,
1318 0x00000000);
1319 /* XXX : not implemented */
1320 spr_register(env, SPR_L2CR, "L2CR",
1321 SPR_NOACCESS, SPR_NOACCESS,
1322 &spr_read_generic, &spr_write_generic,
1323 0x00000000);
1324 /* Not strictly an SPR */
1325 vscr_init(env, 0x00010000);
1326 }
1327
1328 static void gen_l3_ctrl (CPUPPCState *env)
1329 {
1330 /* L3CR */
1331 /* XXX : not implemented */
1332 spr_register(env, SPR_L3CR, "L3CR",
1333 SPR_NOACCESS, SPR_NOACCESS,
1334 &spr_read_generic, &spr_write_generic,
1335 0x00000000);
1336 /* L3ITCR0 */
1337 /* XXX : not implemented */
1338 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1339 SPR_NOACCESS, SPR_NOACCESS,
1340 &spr_read_generic, &spr_write_generic,
1341 0x00000000);
1342 /* L3PM */
1343 /* XXX : not implemented */
1344 spr_register(env, SPR_L3PM, "L3PM",
1345 SPR_NOACCESS, SPR_NOACCESS,
1346 &spr_read_generic, &spr_write_generic,
1347 0x00000000);
1348 }
1349
1350 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1351 {
1352 #if !defined(CONFIG_USER_ONLY)
1353 env->nb_tlb = nb_tlbs;
1354 env->nb_ways = nb_ways;
1355 env->id_tlbs = 1;
1356 env->tlb_type = TLB_6XX;
1357 /* XXX : not implemented */
1358 spr_register(env, SPR_PTEHI, "PTEHI",
1359 SPR_NOACCESS, SPR_NOACCESS,
1360 &spr_read_generic, &spr_write_generic,
1361 0x00000000);
1362 /* XXX : not implemented */
1363 spr_register(env, SPR_PTELO, "PTELO",
1364 SPR_NOACCESS, SPR_NOACCESS,
1365 &spr_read_generic, &spr_write_generic,
1366 0x00000000);
1367 /* XXX : not implemented */
1368 spr_register(env, SPR_TLBMISS, "TLBMISS",
1369 SPR_NOACCESS, SPR_NOACCESS,
1370 &spr_read_generic, &spr_write_generic,
1371 0x00000000);
1372 #endif
1373 }
1374
1375 #if !defined(CONFIG_USER_ONLY)
1376 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1377 {
1378 TCGv t0 = tcg_temp_new();
1379
1380 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1381 gen_store_spr(sprn, t0);
1382 tcg_temp_free(t0);
1383 }
1384
1385 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1386 {
1387 TCGv_i32 t0 = tcg_const_i32(sprn);
1388 gen_helper_booke206_tlbflush(t0);
1389 tcg_temp_free_i32(t0);
1390 }
1391
1392 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1393 {
1394 TCGv_i32 t0 = tcg_const_i32(sprn);
1395 gen_helper_booke_setpid(t0, cpu_gpr[gprn]);
1396 tcg_temp_free_i32(t0);
1397 }
1398 #endif
1399
1400 static void gen_spr_usprgh (CPUPPCState *env)
1401 {
1402 spr_register(env, SPR_USPRG4, "USPRG4",
1403 &spr_read_ureg, SPR_NOACCESS,
1404 &spr_read_ureg, SPR_NOACCESS,
1405 0x00000000);
1406 spr_register(env, SPR_USPRG5, "USPRG5",
1407 &spr_read_ureg, SPR_NOACCESS,
1408 &spr_read_ureg, SPR_NOACCESS,
1409 0x00000000);
1410 spr_register(env, SPR_USPRG6, "USPRG6",
1411 &spr_read_ureg, SPR_NOACCESS,
1412 &spr_read_ureg, SPR_NOACCESS,
1413 0x00000000);
1414 spr_register(env, SPR_USPRG7, "USPRG7",
1415 &spr_read_ureg, SPR_NOACCESS,
1416 &spr_read_ureg, SPR_NOACCESS,
1417 0x00000000);
1418 }
1419
1420 /* PowerPC BookE SPR */
1421 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1422 {
1423 const char *ivor_names[64] = {
1424 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1425 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1426 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1427 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1428 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1429 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1430 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1431 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1432 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1433 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1434 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1435 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1436 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1437 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1438 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1439 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1440 };
1441 #define SPR_BOOKE_IVORxx (-1)
1442 int ivor_sprn[64] = {
1443 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1444 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1445 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1446 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1447 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1448 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1449 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1450 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1451 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1452 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1453 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1454 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1455 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1456 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1457 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1458 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1459 };
1460 int i;
1461
1462 /* Interrupt processing */
1463 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1464 SPR_NOACCESS, SPR_NOACCESS,
1465 &spr_read_generic, &spr_write_generic,
1466 0x00000000);
1467 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1468 SPR_NOACCESS, SPR_NOACCESS,
1469 &spr_read_generic, &spr_write_generic,
1470 0x00000000);
1471 /* Debug */
1472 /* XXX : not implemented */
1473 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1474 SPR_NOACCESS, SPR_NOACCESS,
1475 &spr_read_generic, &spr_write_generic,
1476 0x00000000);
1477 /* XXX : not implemented */
1478 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1479 SPR_NOACCESS, SPR_NOACCESS,
1480 &spr_read_generic, &spr_write_generic,
1481 0x00000000);
1482 /* XXX : not implemented */
1483 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1484 SPR_NOACCESS, SPR_NOACCESS,
1485 &spr_read_generic, &spr_write_generic,
1486 0x00000000);
1487 /* XXX : not implemented */
1488 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1489 SPR_NOACCESS, SPR_NOACCESS,
1490 &spr_read_generic, &spr_write_generic,
1491 0x00000000);
1492 /* XXX : not implemented */
1493 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1494 SPR_NOACCESS, SPR_NOACCESS,
1495 &spr_read_generic, &spr_write_generic,
1496 0x00000000);
1497 /* XXX : not implemented */
1498 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1499 SPR_NOACCESS, SPR_NOACCESS,
1500 &spr_read_generic, &spr_write_generic,
1501 0x00000000);
1502 /* XXX : not implemented */
1503 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1504 SPR_NOACCESS, SPR_NOACCESS,
1505 &spr_read_generic, &spr_write_generic,
1506 0x00000000);
1507 /* XXX : not implemented */
1508 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1509 SPR_NOACCESS, SPR_NOACCESS,
1510 &spr_read_generic, &spr_write_clear,
1511 0x00000000);
1512 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1513 SPR_NOACCESS, SPR_NOACCESS,
1514 &spr_read_generic, &spr_write_generic,
1515 0x00000000);
1516 spr_register(env, SPR_BOOKE_ESR, "ESR",
1517 SPR_NOACCESS, SPR_NOACCESS,
1518 &spr_read_generic, &spr_write_generic,
1519 0x00000000);
1520 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1521 SPR_NOACCESS, SPR_NOACCESS,
1522 &spr_read_generic, &spr_write_excp_prefix,
1523 0x00000000);
1524 /* Exception vectors */
1525 for (i = 0; i < 64; i++) {
1526 if (ivor_mask & (1ULL << i)) {
1527 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1528 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1529 exit(1);
1530 }
1531 spr_register(env, ivor_sprn[i], ivor_names[i],
1532 SPR_NOACCESS, SPR_NOACCESS,
1533 &spr_read_generic, &spr_write_excp_vector,
1534 0x00000000);
1535 }
1536 }
1537 spr_register(env, SPR_BOOKE_PID, "PID",
1538 SPR_NOACCESS, SPR_NOACCESS,
1539 &spr_read_generic, &spr_write_booke_pid,
1540 0x00000000);
1541 spr_register(env, SPR_BOOKE_TCR, "TCR",
1542 SPR_NOACCESS, SPR_NOACCESS,
1543 &spr_read_generic, &spr_write_booke_tcr,
1544 0x00000000);
1545 spr_register(env, SPR_BOOKE_TSR, "TSR",
1546 SPR_NOACCESS, SPR_NOACCESS,
1547 &spr_read_generic, &spr_write_booke_tsr,
1548 0x00000000);
1549 /* Timer */
1550 spr_register(env, SPR_DECR, "DECR",
1551 SPR_NOACCESS, SPR_NOACCESS,
1552 &spr_read_decr, &spr_write_decr,
1553 0x00000000);
1554 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1555 SPR_NOACCESS, SPR_NOACCESS,
1556 SPR_NOACCESS, &spr_write_generic,
1557 0x00000000);
1558 /* SPRGs */
1559 spr_register(env, SPR_USPRG0, "USPRG0",
1560 &spr_read_generic, &spr_write_generic,
1561 &spr_read_generic, &spr_write_generic,
1562 0x00000000);
1563 spr_register(env, SPR_SPRG4, "SPRG4",
1564 SPR_NOACCESS, SPR_NOACCESS,
1565 &spr_read_generic, &spr_write_generic,
1566 0x00000000);
1567 spr_register(env, SPR_SPRG5, "SPRG5",
1568 SPR_NOACCESS, SPR_NOACCESS,
1569 &spr_read_generic, &spr_write_generic,
1570 0x00000000);
1571 spr_register(env, SPR_SPRG6, "SPRG6",
1572 SPR_NOACCESS, SPR_NOACCESS,
1573 &spr_read_generic, &spr_write_generic,
1574 0x00000000);
1575 spr_register(env, SPR_SPRG7, "SPRG7",
1576 SPR_NOACCESS, SPR_NOACCESS,
1577 &spr_read_generic, &spr_write_generic,
1578 0x00000000);
1579 }
1580
1581 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1582 uint32_t maxsize, uint32_t flags,
1583 uint32_t nentries)
1584 {
1585 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1586 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1587 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1588 flags | nentries;
1589 }
1590
1591 /* BookE 2.06 storage control registers */
1592 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1593 uint32_t *tlbncfg)
1594 {
1595 #if !defined(CONFIG_USER_ONLY)
1596 const char *mas_names[8] = {
1597 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1598 };
1599 int mas_sprn[8] = {
1600 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1601 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1602 };
1603 int i;
1604
1605 /* TLB assist registers */
1606 /* XXX : not implemented */
1607 for (i = 0; i < 8; i++) {
1608 if (mas_mask & (1 << i)) {
1609 spr_register(env, mas_sprn[i], mas_names[i],
1610 SPR_NOACCESS, SPR_NOACCESS,
1611 &spr_read_generic, &spr_write_generic,
1612 0x00000000);
1613 }
1614 }
1615 if (env->nb_pids > 1) {
1616 /* XXX : not implemented */
1617 spr_register(env, SPR_BOOKE_PID1, "PID1",
1618 SPR_NOACCESS, SPR_NOACCESS,
1619 &spr_read_generic, &spr_write_booke_pid,
1620 0x00000000);
1621 }
1622 if (env->nb_pids > 2) {
1623 /* XXX : not implemented */
1624 spr_register(env, SPR_BOOKE_PID2, "PID2",
1625 SPR_NOACCESS, SPR_NOACCESS,
1626 &spr_read_generic, &spr_write_booke_pid,
1627 0x00000000);
1628 }
1629 /* XXX : not implemented */
1630 spr_register(env, SPR_MMUCFG, "MMUCFG",
1631 SPR_NOACCESS, SPR_NOACCESS,
1632 &spr_read_generic, SPR_NOACCESS,
1633 0x00000000); /* TOFIX */
1634 switch (env->nb_ways) {
1635 case 4:
1636 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1637 SPR_NOACCESS, SPR_NOACCESS,
1638 &spr_read_generic, SPR_NOACCESS,
1639 tlbncfg[3]);
1640 /* Fallthru */
1641 case 3:
1642 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1643 SPR_NOACCESS, SPR_NOACCESS,
1644 &spr_read_generic, SPR_NOACCESS,
1645 tlbncfg[2]);
1646 /* Fallthru */
1647 case 2:
1648 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1649 SPR_NOACCESS, SPR_NOACCESS,
1650 &spr_read_generic, SPR_NOACCESS,
1651 tlbncfg[1]);
1652 /* Fallthru */
1653 case 1:
1654 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1655 SPR_NOACCESS, SPR_NOACCESS,
1656 &spr_read_generic, SPR_NOACCESS,
1657 tlbncfg[0]);
1658 /* Fallthru */
1659 case 0:
1660 default:
1661 break;
1662 }
1663 #endif
1664
1665 gen_spr_usprgh(env);
1666 }
1667
1668 /* SPR specific to PowerPC 440 implementation */
1669 static void gen_spr_440 (CPUPPCState *env)
1670 {
1671 /* Cache control */
1672 /* XXX : not implemented */
1673 spr_register(env, SPR_440_DNV0, "DNV0",
1674 SPR_NOACCESS, SPR_NOACCESS,
1675 &spr_read_generic, &spr_write_generic,
1676 0x00000000);
1677 /* XXX : not implemented */
1678 spr_register(env, SPR_440_DNV1, "DNV1",
1679 SPR_NOACCESS, SPR_NOACCESS,
1680 &spr_read_generic, &spr_write_generic,
1681 0x00000000);
1682 /* XXX : not implemented */
1683 spr_register(env, SPR_440_DNV2, "DNV2",
1684 SPR_NOACCESS, SPR_NOACCESS,
1685 &spr_read_generic, &spr_write_generic,
1686 0x00000000);
1687 /* XXX : not implemented */
1688 spr_register(env, SPR_440_DNV3, "DNV3",
1689 SPR_NOACCESS, SPR_NOACCESS,
1690 &spr_read_generic, &spr_write_generic,
1691 0x00000000);
1692 /* XXX : not implemented */
1693 spr_register(env, SPR_440_DTV0, "DTV0",
1694 SPR_NOACCESS, SPR_NOACCESS,
1695 &spr_read_generic, &spr_write_generic,
1696 0x00000000);
1697 /* XXX : not implemented */
1698 spr_register(env, SPR_440_DTV1, "DTV1",
1699 SPR_NOACCESS, SPR_NOACCESS,
1700 &spr_read_generic, &spr_write_generic,
1701 0x00000000);
1702 /* XXX : not implemented */
1703 spr_register(env, SPR_440_DTV2, "DTV2",
1704 SPR_NOACCESS, SPR_NOACCESS,
1705 &spr_read_generic, &spr_write_generic,
1706 0x00000000);
1707 /* XXX : not implemented */
1708 spr_register(env, SPR_440_DTV3, "DTV3",
1709 SPR_NOACCESS, SPR_NOACCESS,
1710 &spr_read_generic, &spr_write_generic,
1711 0x00000000);
1712 /* XXX : not implemented */
1713 spr_register(env, SPR_440_DVLIM, "DVLIM",
1714 SPR_NOACCESS, SPR_NOACCESS,
1715 &spr_read_generic, &spr_write_generic,
1716 0x00000000);
1717 /* XXX : not implemented */
1718 spr_register(env, SPR_440_INV0, "INV0",
1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, &spr_write_generic,
1721 0x00000000);
1722 /* XXX : not implemented */
1723 spr_register(env, SPR_440_INV1, "INV1",
1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_generic, &spr_write_generic,
1726 0x00000000);
1727 /* XXX : not implemented */
1728 spr_register(env, SPR_440_INV2, "INV2",
1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, &spr_write_generic,
1731 0x00000000);
1732 /* XXX : not implemented */
1733 spr_register(env, SPR_440_INV3, "INV3",
1734 SPR_NOACCESS, SPR_NOACCESS,
1735 &spr_read_generic, &spr_write_generic,
1736 0x00000000);
1737 /* XXX : not implemented */
1738 spr_register(env, SPR_440_ITV0, "ITV0",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, &spr_write_generic,
1741 0x00000000);
1742 /* XXX : not implemented */
1743 spr_register(env, SPR_440_ITV1, "ITV1",
1744 SPR_NOACCESS, SPR_NOACCESS,
1745 &spr_read_generic, &spr_write_generic,
1746 0x00000000);
1747 /* XXX : not implemented */
1748 spr_register(env, SPR_440_ITV2, "ITV2",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752 /* XXX : not implemented */
1753 spr_register(env, SPR_440_ITV3, "ITV3",
1754 SPR_NOACCESS, SPR_NOACCESS,
1755 &spr_read_generic, &spr_write_generic,
1756 0x00000000);
1757 /* XXX : not implemented */
1758 spr_register(env, SPR_440_IVLIM, "IVLIM",
1759 SPR_NOACCESS, SPR_NOACCESS,
1760 &spr_read_generic, &spr_write_generic,
1761 0x00000000);
1762 /* Cache debug */
1763 /* XXX : not implemented */
1764 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1765 SPR_NOACCESS, SPR_NOACCESS,
1766 &spr_read_generic, SPR_NOACCESS,
1767 0x00000000);
1768 /* XXX : not implemented */
1769 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1770 SPR_NOACCESS, SPR_NOACCESS,
1771 &spr_read_generic, SPR_NOACCESS,
1772 0x00000000);
1773 /* XXX : not implemented */
1774 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1775 SPR_NOACCESS, SPR_NOACCESS,
1776 &spr_read_generic, SPR_NOACCESS,
1777 0x00000000);
1778 /* XXX : not implemented */
1779 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1780 SPR_NOACCESS, SPR_NOACCESS,
1781 &spr_read_generic, SPR_NOACCESS,
1782 0x00000000);
1783 /* XXX : not implemented */
1784 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1785 SPR_NOACCESS, SPR_NOACCESS,
1786 &spr_read_generic, SPR_NOACCESS,
1787 0x00000000);
1788 /* XXX : not implemented */
1789 spr_register(env, SPR_440_DBDR, "DBDR",
1790 SPR_NOACCESS, SPR_NOACCESS,
1791 &spr_read_generic, &spr_write_generic,
1792 0x00000000);
1793 /* Processor control */
1794 spr_register(env, SPR_4xx_CCR0, "CCR0",
1795 SPR_NOACCESS, SPR_NOACCESS,
1796 &spr_read_generic, &spr_write_generic,
1797 0x00000000);
1798 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1799 SPR_NOACCESS, SPR_NOACCESS,
1800 &spr_read_generic, SPR_NOACCESS,
1801 0x00000000);
1802 /* Storage control */
1803 spr_register(env, SPR_440_MMUCR, "MMUCR",
1804 SPR_NOACCESS, SPR_NOACCESS,
1805 &spr_read_generic, &spr_write_generic,
1806 0x00000000);
1807 }
1808
1809 /* SPR shared between PowerPC 40x implementations */
1810 static void gen_spr_40x (CPUPPCState *env)
1811 {
1812 /* Cache */
1813 /* not emulated, as Qemu do not emulate caches */
1814 spr_register(env, SPR_40x_DCCR, "DCCR",
1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_generic, &spr_write_generic,
1817 0x00000000);
1818 /* not emulated, as Qemu do not emulate caches */
1819 spr_register(env, SPR_40x_ICCR, "ICCR",
1820 SPR_NOACCESS, SPR_NOACCESS,
1821 &spr_read_generic, &spr_write_generic,
1822 0x00000000);
1823 /* not emulated, as Qemu do not emulate caches */
1824 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1825 SPR_NOACCESS, SPR_NOACCESS,
1826 &spr_read_generic, SPR_NOACCESS,
1827 0x00000000);
1828 /* Exception */
1829 spr_register(env, SPR_40x_DEAR, "DEAR",
1830 SPR_NOACCESS, SPR_NOACCESS,
1831 &spr_read_generic, &spr_write_generic,
1832 0x00000000);
1833 spr_register(env, SPR_40x_ESR, "ESR",
1834 SPR_NOACCESS, SPR_NOACCESS,
1835 &spr_read_generic, &spr_write_generic,
1836 0x00000000);
1837 spr_register(env, SPR_40x_EVPR, "EVPR",
1838 SPR_NOACCESS, SPR_NOACCESS,
1839 &spr_read_generic, &spr_write_excp_prefix,
1840 0x00000000);
1841 spr_register(env, SPR_40x_SRR2, "SRR2",
1842 &spr_read_generic, &spr_write_generic,
1843 &spr_read_generic, &spr_write_generic,
1844 0x00000000);
1845 spr_register(env, SPR_40x_SRR3, "SRR3",
1846 &spr_read_generic, &spr_write_generic,
1847 &spr_read_generic, &spr_write_generic,
1848 0x00000000);
1849 /* Timers */
1850 spr_register(env, SPR_40x_PIT, "PIT",
1851 SPR_NOACCESS, SPR_NOACCESS,
1852 &spr_read_40x_pit, &spr_write_40x_pit,
1853 0x00000000);
1854 spr_register(env, SPR_40x_TCR, "TCR",
1855 SPR_NOACCESS, SPR_NOACCESS,
1856 &spr_read_generic, &spr_write_booke_tcr,
1857 0x00000000);
1858 spr_register(env, SPR_40x_TSR, "TSR",
1859 SPR_NOACCESS, SPR_NOACCESS,
1860 &spr_read_generic, &spr_write_booke_tsr,
1861 0x00000000);
1862 }
1863
1864 /* SPR specific to PowerPC 405 implementation */
1865 static void gen_spr_405 (CPUPPCState *env)
1866 {
1867 /* MMU */
1868 spr_register(env, SPR_40x_PID, "PID",
1869 SPR_NOACCESS, SPR_NOACCESS,
1870 &spr_read_generic, &spr_write_generic,
1871 0x00000000);
1872 spr_register(env, SPR_4xx_CCR0, "CCR0",
1873 SPR_NOACCESS, SPR_NOACCESS,
1874 &spr_read_generic, &spr_write_generic,
1875 0x00700000);
1876 /* Debug interface */
1877 /* XXX : not implemented */
1878 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1879 SPR_NOACCESS, SPR_NOACCESS,
1880 &spr_read_generic, &spr_write_40x_dbcr0,
1881 0x00000000);
1882 /* XXX : not implemented */
1883 spr_register(env, SPR_405_DBCR1, "DBCR1",
1884 SPR_NOACCESS, SPR_NOACCESS,
1885 &spr_read_generic, &spr_write_generic,
1886 0x00000000);
1887 /* XXX : not implemented */
1888 spr_register(env, SPR_40x_DBSR, "DBSR",
1889 SPR_NOACCESS, SPR_NOACCESS,
1890 &spr_read_generic, &spr_write_clear,
1891 /* Last reset was system reset */
1892 0x00000300);
1893 /* XXX : not implemented */
1894 spr_register(env, SPR_40x_DAC1, "DAC1",
1895 SPR_NOACCESS, SPR_NOACCESS,
1896 &spr_read_generic, &spr_write_generic,
1897 0x00000000);
1898 spr_register(env, SPR_40x_DAC2, "DAC2",
1899 SPR_NOACCESS, SPR_NOACCESS,
1900 &spr_read_generic, &spr_write_generic,
1901 0x00000000);
1902 /* XXX : not implemented */
1903 spr_register(env, SPR_405_DVC1, "DVC1",
1904 SPR_NOACCESS, SPR_NOACCESS,
1905 &spr_read_generic, &spr_write_generic,
1906 0x00000000);
1907 /* XXX : not implemented */
1908 spr_register(env, SPR_405_DVC2, "DVC2",
1909 SPR_NOACCESS, SPR_NOACCESS,
1910 &spr_read_generic, &spr_write_generic,
1911 0x00000000);
1912 /* XXX : not implemented */
1913 spr_register(env, SPR_40x_IAC1, "IAC1",
1914 SPR_NOACCESS, SPR_NOACCESS,
1915 &spr_read_generic, &spr_write_generic,
1916 0x00000000);
1917 spr_register(env, SPR_40x_IAC2, "IAC2",
1918 SPR_NOACCESS, SPR_NOACCESS,
1919 &spr_read_generic, &spr_write_generic,
1920 0x00000000);
1921 /* XXX : not implemented */
1922 spr_register(env, SPR_405_IAC3, "IAC3",
1923 SPR_NOACCESS, SPR_NOACCESS,
1924 &spr_read_generic, &spr_write_generic,
1925 0x00000000);
1926 /* XXX : not implemented */
1927 spr_register(env, SPR_405_IAC4, "IAC4",
1928 SPR_NOACCESS, SPR_NOACCESS,
1929 &spr_read_generic, &spr_write_generic,
1930 0x00000000);
1931 /* Storage control */
1932 /* XXX: TODO: not implemented */
1933 spr_register(env, SPR_405_SLER, "SLER",
1934 SPR_NOACCESS, SPR_NOACCESS,
1935 &spr_read_generic, &spr_write_40x_sler,
1936 0x00000000);
1937 spr_register(env, SPR_40x_ZPR, "ZPR",
1938 SPR_NOACCESS, SPR_NOACCESS,
1939 &spr_read_generic, &spr_write_generic,
1940 0x00000000);
1941 /* XXX : not implemented */
1942 spr_register(env, SPR_405_SU0R, "SU0R",
1943 SPR_NOACCESS, SPR_NOACCESS,
1944 &spr_read_generic, &spr_write_generic,
1945 0x00000000);
1946 /* SPRG */
1947 spr_register(env, SPR_USPRG0, "USPRG0",
1948 &spr_read_ureg, SPR_NOACCESS,
1949 &spr_read_ureg, SPR_NOACCESS,
1950 0x00000000);
1951 spr_register(env, SPR_SPRG4, "SPRG4",
1952 SPR_NOACCESS, SPR_NOACCESS,
1953 &spr_read_generic, &spr_write_generic,
1954 0x00000000);
1955 spr_register(env, SPR_SPRG5, "SPRG5",
1956 SPR_NOACCESS, SPR_NOACCESS,
1957 spr_read_generic, &spr_write_generic,
1958 0x00000000);
1959 spr_register(env, SPR_SPRG6, "SPRG6",
1960 SPR_NOACCESS, SPR_NOACCESS,
1961 spr_read_generic, &spr_write_generic,
1962 0x00000000);
1963 spr_register(env, SPR_SPRG7, "SPRG7",
1964 SPR_NOACCESS, SPR_NOACCESS,
1965 spr_read_generic, &spr_write_generic,
1966 0x00000000);
1967 gen_spr_usprgh(env);
1968 }
1969
1970 /* SPR shared between PowerPC 401 & 403 implementations */
1971 static void gen_spr_401_403 (CPUPPCState *env)
1972 {
1973 /* Time base */
1974 spr_register(env, SPR_403_VTBL, "TBL",
1975 &spr_read_tbl, SPR_NOACCESS,
1976 &spr_read_tbl, SPR_NOACCESS,
1977 0x00000000);
1978 spr_register(env, SPR_403_TBL, "TBL",
1979 SPR_NOACCESS, SPR_NOACCESS,
1980 SPR_NOACCESS, &spr_write_tbl,
1981 0x00000000);
1982 spr_register(env, SPR_403_VTBU, "TBU",
1983 &spr_read_tbu, SPR_NOACCESS,
1984 &spr_read_tbu, SPR_NOACCESS,
1985 0x00000000);
1986 spr_register(env, SPR_403_TBU, "TBU",
1987 SPR_NOACCESS, SPR_NOACCESS,
1988 SPR_NOACCESS, &spr_write_tbu,
1989 0x00000000);
1990 /* Debug */
1991 /* not emulated, as Qemu do not emulate caches */
1992 spr_register(env, SPR_403_CDBCR, "CDBCR",
1993 SPR_NOACCESS, SPR_NOACCESS,
1994 &spr_read_generic, &spr_write_generic,
1995 0x00000000);
1996 }
1997
1998 /* SPR specific to PowerPC 401 implementation */
1999 static void gen_spr_401 (CPUPPCState *env)
2000 {
2001 /* Debug interface */
2002 /* XXX : not implemented */
2003 spr_register(env, SPR_40x_DBCR0, "DBCR",
2004 SPR_NOACCESS, SPR_NOACCESS,
2005 &spr_read_generic, &spr_write_40x_dbcr0,
2006 0x00000000);
2007 /* XXX : not implemented */
2008 spr_register(env, SPR_40x_DBSR, "DBSR",
2009 SPR_NOACCESS, SPR_NOACCESS,
2010 &spr_read_generic, &spr_write_clear,
2011 /* Last reset was system reset */
2012 0x00000300);
2013 /* XXX : not implemented */
2014 spr_register(env, SPR_40x_DAC1, "DAC",
2015 SPR_NOACCESS, SPR_NOACCESS,
2016 &spr_read_generic, &spr_write_generic,
2017 0x00000000);
2018 /* XXX : not implemented */
2019 spr_register(env, SPR_40x_IAC1, "IAC",
2020 SPR_NOACCESS, SPR_NOACCESS,
2021 &spr_read_generic, &spr_write_generic,
2022 0x00000000);
2023 /* Storage control */
2024 /* XXX: TODO: not implemented */
2025 spr_register(env, SPR_405_SLER, "SLER",
2026 SPR_NOACCESS, SPR_NOACCESS,
2027 &spr_read_generic, &spr_write_40x_sler,
2028 0x00000000);
2029 /* not emulated, as Qemu never does speculative access */
2030 spr_register(env, SPR_40x_SGR, "SGR",
2031 SPR_NOACCESS, SPR_NOACCESS,
2032 &spr_read_generic, &spr_write_generic,
2033 0xFFFFFFFF);
2034 /* not emulated, as Qemu do not emulate caches */
2035 spr_register(env, SPR_40x_DCWR, "DCWR",
2036 SPR_NOACCESS, SPR_NOACCESS,
2037 &spr_read_generic, &spr_write_generic,
2038 0x00000000);
2039 }
2040
2041 static void gen_spr_401x2 (CPUPPCState *env)
2042 {
2043 gen_spr_401(env);
2044 spr_register(env, SPR_40x_PID, "PID",
2045 SPR_NOACCESS, SPR_NOACCESS,
2046 &spr_read_generic, &spr_write_generic,
2047 0x00000000);
2048 spr_register(env, SPR_40x_ZPR, "ZPR",
2049 SPR_NOACCESS, SPR_NOACCESS,
2050 &spr_read_generic, &spr_write_generic,
2051 0x00000000);
2052 }
2053
2054 /* SPR specific to PowerPC 403 implementation */
2055 static void gen_spr_403 (CPUPPCState *env)
2056 {
2057 /* Debug interface */
2058 /* XXX : not implemented */
2059 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2060 SPR_NOACCESS, SPR_NOACCESS,
2061 &spr_read_generic, &spr_write_40x_dbcr0,
2062 0x00000000);
2063 /* XXX : not implemented */
2064 spr_register(env, SPR_40x_DBSR, "DBSR",
2065 SPR_NOACCESS, SPR_NOACCESS,
2066 &spr_read_generic, &spr_write_clear,
2067 /* Last reset was system reset */
2068 0x00000300);
2069 /* XXX : not implemented */
2070 spr_register(env, SPR_40x_DAC1, "DAC1",
2071 SPR_NOACCESS, SPR_NOACCESS,
2072 &spr_read_generic, &spr_write_generic,
2073 0x00000000);
2074 /* XXX : not implemented */
2075 spr_register(env, SPR_40x_DAC2, "DAC2",
2076 SPR_NOACCESS, SPR_NOACCESS,
2077 &spr_read_generic, &spr_write_generic,
2078 0x00000000);
2079 /* XXX : not implemented */
2080 spr_register(env, SPR_40x_IAC1, "IAC1",
2081 SPR_NOACCESS, SPR_NOACCESS,
2082 &spr_read_generic, &spr_write_generic,
2083 0x00000000);
2084 /* XXX : not implemented */
2085 spr_register(env, SPR_40x_IAC2, "IAC2",
2086 SPR_NOACCESS, SPR_NOACCESS,
2087 &spr_read_generic, &spr_write_generic,
2088 0x00000000);
2089 }
2090
2091 static void gen_spr_403_real (CPUPPCState *env)
2092 {
2093 spr_register(env, SPR_403_PBL1, "PBL1",
2094 SPR_NOACCESS, SPR_NOACCESS,
2095 &spr_read_403_pbr, &spr_write_403_pbr,
2096 0x00000000);
2097 spr_register(env, SPR_403_PBU1, "PBU1",
2098 SPR_NOACCESS, SPR_NOACCESS,
2099 &spr_read_403_pbr, &spr_write_403_pbr,
2100 0x00000000);
2101 spr_register(env, SPR_403_PBL2, "PBL2",
2102 SPR_NOACCESS, SPR_NOACCESS,
2103 &spr_read_403_pbr, &spr_write_403_pbr,
2104 0x00000000);
2105 spr_register(env, SPR_403_PBU2, "PBU2",
2106 SPR_NOACCESS, SPR_NOACCESS,
2107 &spr_read_403_pbr, &spr_write_403_pbr,
2108 0x00000000);
2109 }
2110
2111 static void gen_spr_403_mmu (CPUPPCState *env)
2112 {
2113 /* MMU */
2114 spr_register(env, SPR_40x_PID, "PID",
2115 SPR_NOACCESS, SPR_NOACCESS,
2116 &spr_read_generic, &spr_write_generic,
2117 0x00000000);
2118 spr_register(env, SPR_40x_ZPR, "ZPR",
2119 SPR_NOACCESS, SPR_NOACCESS,
2120 &spr_read_generic, &spr_write_generic,
2121 0x00000000);
2122 }
2123
2124 /* SPR specific to PowerPC compression coprocessor extension */
2125 static void gen_spr_compress (CPUPPCState *env)
2126 {
2127 /* XXX : not implemented */
2128 spr_register(env, SPR_401_SKR, "SKR",
2129 SPR_NOACCESS, SPR_NOACCESS,
2130 &spr_read_generic, &spr_write_generic,
2131 0x00000000);
2132 }
2133
2134 #if defined (TARGET_PPC64)
2135 /* SPR specific to PowerPC 620 */
2136 static void gen_spr_620 (CPUPPCState *env)
2137 {
2138 /* Processor identification */
2139 spr_register(env, SPR_PIR, "PIR",
2140 SPR_NOACCESS, SPR_NOACCESS,
2141 &spr_read_generic, &spr_write_pir,
2142 0x00000000);
2143 spr_register(env, SPR_ASR, "ASR",
2144 SPR_NOACCESS, SPR_NOACCESS,
2145 &spr_read_asr, &spr_write_asr,
2146 0x00000000);
2147 /* Breakpoints */
2148 /* XXX : not implemented */
2149 spr_register(env, SPR_IABR, "IABR",
2150 SPR_NOACCESS, SPR_NOACCESS,
2151 &spr_read_generic, &spr_write_generic,
2152 0x00000000);
2153 /* XXX : not implemented */
2154 spr_register(env, SPR_DABR, "DABR",
2155 SPR_NOACCESS, SPR_NOACCESS,
2156 &spr_read_generic, &spr_write_generic,
2157 0x00000000);
2158 /* XXX : not implemented */
2159 spr_register(env, SPR_SIAR, "SIAR",
2160 SPR_NOACCESS, SPR_NOACCESS,
2161 &spr_read_generic, SPR_NOACCESS,
2162 0x00000000);
2163 /* XXX : not implemented */
2164 spr_register(env, SPR_SDA, "SDA",
2165 SPR_NOACCESS, SPR_NOACCESS,
2166 &spr_read_generic, SPR_NOACCESS,
2167 0x00000000);
2168 /* XXX : not implemented */
2169 spr_register(env, SPR_620_PMC1R, "PMC1",
2170 SPR_NOACCESS, SPR_NOACCESS,
2171 &spr_read_generic, SPR_NOACCESS,
2172 0x00000000);
2173 spr_register(env, SPR_620_PMC1W, "PMC1",
2174 SPR_NOACCESS, SPR_NOACCESS,
2175 SPR_NOACCESS, &spr_write_generic,
2176 0x00000000);
2177 /* XXX : not implemented */
2178 spr_register(env, SPR_620_PMC2R, "PMC2",
2179 SPR_NOACCESS, SPR_NOACCESS,
2180 &spr_read_generic, SPR_NOACCESS,
2181 0x00000000);
2182 spr_register(env, SPR_620_PMC2W, "PMC2",
2183 SPR_NOACCESS, SPR_NOACCESS,
2184 SPR_NOACCESS, &spr_write_generic,
2185 0x00000000);
2186 /* XXX : not implemented */
2187 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2188 SPR_NOACCESS, SPR_NOACCESS,
2189 &spr_read_generic, SPR_NOACCESS,
2190 0x00000000);
2191 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2192 SPR_NOACCESS, SPR_NOACCESS,
2193 SPR_NOACCESS, &spr_write_generic,
2194 0x00000000);
2195 /* External access control */
2196 /* XXX : not implemented */
2197 spr_register(env, SPR_EAR, "EAR",
2198 SPR_NOACCESS, SPR_NOACCESS,
2199 &spr_read_generic, &spr_write_generic,
2200 0x00000000);
2201 #if 0 // XXX: check this
2202 /* XXX : not implemented */
2203 spr_register(env, SPR_620_PMR0, "PMR0",
2204 SPR_NOACCESS, SPR_NOACCESS,
2205 &spr_read_generic, &spr_write_generic,
2206 0x00000000);
2207 /* XXX : not implemented */
2208 spr_register(env, SPR_620_PMR1, "PMR1",
2209 SPR_NOACCESS, SPR_NOACCESS,
2210 &spr_read_generic, &spr_write_generic,
2211 0x00000000);
2212 /* XXX : not implemented */
2213 spr_register(env, SPR_620_PMR2, "PMR2",
2214 SPR_NOACCESS, SPR_NOACCESS,
2215 &spr_read_generic, &spr_write_generic,
2216 0x00000000);
2217 /* XXX : not implemented */
2218 spr_register(env, SPR_620_PMR3, "PMR3",
2219 SPR_NOACCESS, SPR_NOACCESS,
2220 &spr_read_generic, &spr_write_generic,
2221 0x00000000);
2222 /* XXX : not implemented */
2223 spr_register(env, SPR_620_PMR4, "PMR4",
2224 SPR_NOACCESS, SPR_NOACCESS,
2225 &spr_read_generic, &spr_write_generic,
2226 0x00000000);
2227 /* XXX : not implemented */
2228 spr_register(env, SPR_620_PMR5, "PMR5",
2229 SPR_NOACCESS, SPR_NOACCESS,
2230 &spr_read_generic, &spr_write_generic,
2231 0x00000000);
2232 /* XXX : not implemented */
2233 spr_register(env, SPR_620_PMR6, "PMR6",
2234 SPR_NOACCESS, SPR_NOACCESS,
2235 &spr_read_generic, &spr_write_generic,
2236 0x00000000);
2237 /* XXX : not implemented */
2238 spr_register(env, SPR_620_PMR7, "PMR7",
2239 SPR_NOACCESS, SPR_NOACCESS,
2240 &spr_read_generic, &spr_write_generic,
2241 0x00000000);
2242 /* XXX : not implemented */
2243 spr_register(env, SPR_620_PMR8, "PMR8",
2244 SPR_NOACCESS, SPR_NOACCESS,
2245 &spr_read_generic, &spr_write_generic,
2246 0x00000000);
2247 /* XXX : not implemented */
2248 spr_register(env, SPR_620_PMR9, "PMR9",
2249 SPR_NOACCESS, SPR_NOACCESS,
2250 &spr_read_generic, &spr_write_generic,
2251 0x00000000);
2252 /* XXX : not implemented */
2253 spr_register(env, SPR_620_PMRA, "PMR10",
2254 SPR_NOACCESS, SPR_NOACCESS,
2255 &spr_read_generic, &spr_write_generic,
2256 0x00000000);
2257 /* XXX : not implemented */
2258 spr_register(env, SPR_620_PMRB, "PMR11",
2259 SPR_NOACCESS, SPR_NOACCESS,
2260 &spr_read_generic, &spr_write_generic,
2261 0x00000000);
2262 /* XXX : not implemented */
2263 spr_register(env, SPR_620_PMRC, "PMR12",
2264 SPR_NOACCESS, SPR_NOACCESS,
2265 &spr_read_generic, &spr_write_generic,
2266 0x00000000);
2267 /* XXX : not implemented */
2268 spr_register(env, SPR_620_PMRD, "PMR13",
2269 SPR_NOACCESS, SPR_NOACCESS,
2270 &spr_read_generic, &spr_write_generic,
2271 0x00000000);
2272 /* XXX : not implemented */
2273 spr_register(env, SPR_620_PMRE, "PMR14",
2274 SPR_NOACCESS, SPR_NOACCESS,
2275 &spr_read_generic, &spr_write_generic,
2276 0x00000000);
2277 /* XXX : not implemented */
2278 spr_register(env, SPR_620_PMRF, "PMR15",
2279 SPR_NOACCESS, SPR_NOACCESS,
2280 &spr_read_generic, &spr_write_generic,
2281 0x00000000);
2282 #endif
2283 /* XXX : not implemented */
2284 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2285 SPR_NOACCESS, SPR_NOACCESS,
2286 &spr_read_generic, &spr_write_generic,
2287 0x00000000);
2288 /* XXX : not implemented */
2289 spr_register(env, SPR_620_L2CR, "L2CR",
2290 SPR_NOACCESS, SPR_NOACCESS,
2291 &spr_read_generic, &spr_write_generic,
2292 0x00000000);
2293 /* XXX : not implemented */
2294 spr_register(env, SPR_620_L2SR, "L2SR",
2295 SPR_NOACCESS, SPR_NOACCESS,
2296 &spr_read_generic, &spr_write_generic,
2297 0x00000000);
2298 }
2299 #endif /* defined (TARGET_PPC64) */
2300
2301 static void gen_spr_5xx_8xx (CPUPPCState *env)
2302 {
2303 /* Exception processing */
2304 spr_register(env, SPR_DSISR, "DSISR",
2305 SPR_NOACCESS, SPR_NOACCESS,
2306 &spr_read_generic, &spr_write_generic,
2307 0x00000000);
2308 spr_register(env, SPR_DAR, "DAR",
2309 SPR_NOACCESS, SPR_NOACCESS,
2310 &spr_read_generic, &spr_write_generic,
2311 0x00000000);
2312 /* Timer */
2313 spr_register(env, SPR_DECR, "DECR",
2314 SPR_NOACCESS, SPR_NOACCESS,
2315 &spr_read_decr, &spr_write_decr,
2316 0x00000000);
2317 /* XXX : not implemented */
2318 spr_register(env, SPR_MPC_EIE, "EIE",
2319 SPR_NOACCESS, SPR_NOACCESS,
2320 &spr_read_generic, &spr_write_generic,
2321 0x00000000);
2322 /* XXX : not implemented */
2323 spr_register(env, SPR_MPC_EID, "EID",
2324 SPR_NOACCESS, SPR_NOACCESS,
2325 &spr_read_generic, &spr_write_generic,
2326 0x00000000);
2327 /* XXX : not implemented */
2328 spr_register(env, SPR_MPC_NRI, "NRI",
2329 SPR_NOACCESS, SPR_NOACCESS,
2330 &spr_read_generic, &spr_write_generic,
2331 0x00000000);
2332 /* XXX : not implemented */
2333 spr_register(env, SPR_MPC_CMPA, "CMPA",
2334 SPR_NOACCESS, SPR_NOACCESS,
2335 &spr_read_generic, &spr_write_generic,
2336 0x00000000);
2337 /* XXX : not implemented */
2338 spr_register(env, SPR_MPC_CMPB, "CMPB",
2339 SPR_NOACCESS, SPR_NOACCESS,
2340 &spr_read_generic, &spr_write_generic,
2341 0x00000000);
2342 /* XXX : not implemented */
2343 spr_register(env, SPR_MPC_CMPC, "CMPC",
2344 SPR_NOACCESS, SPR_NOACCESS,
2345 &spr_read_generic, &spr_write_generic,
2346 0x00000000);
2347 /* XXX : not implemented */
2348 spr_register(env, SPR_MPC_CMPD, "CMPD",
2349 SPR_NOACCESS, SPR_NOACCESS,
2350 &spr_read_generic, &spr_write_generic,
2351 0x00000000);
2352 /* XXX : not implemented */
2353 spr_register(env, SPR_MPC_ECR, "ECR",
2354 SPR_NOACCESS, SPR_NOACCESS,
2355 &spr_read_generic, &spr_write_generic,
2356 0x00000000);
2357 /* XXX : not implemented */
2358 spr_register(env, SPR_MPC_DER, "DER",
2359 SPR_NOACCESS, SPR_NOACCESS,
2360 &spr_read_generic, &spr_write_generic,
2361 0x00000000);
2362 /* XXX : not implemented */
2363 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2364 SPR_NOACCESS, SPR_NOACCESS,
2365 &spr_read_generic, &spr_write_generic,
2366 0x00000000);
2367 /* XXX : not implemented */
2368 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2369 SPR_NOACCESS, SPR_NOACCESS,
2370 &spr_read_generic, &spr_write_generic,
2371 0x00000000);
2372 /* XXX : not implemented */
2373 spr_register(env, SPR_MPC_CMPE, "CMPE",
2374 SPR_NOACCESS, SPR_NOACCESS,
2375 &spr_read_generic, &spr_write_generic,
2376 0x00000000);
2377 /* XXX : not implemented */
2378 spr_register(env, SPR_MPC_CMPF, "CMPF",
2379 SPR_NOACCESS, SPR_NOACCESS,
2380 &spr_read_generic, &spr_write_generic,
2381 0x00000000);
2382 /* XXX : not implemented */
2383 spr_register(env, SPR_MPC_CMPG, "CMPG",
2384 SPR_NOACCESS, SPR_NOACCESS,
2385 &spr_read_generic, &spr_write_generic,
2386 0x00000000);
2387 /* XXX : not implemented */
2388 spr_register(env, SPR_MPC_CMPH, "CMPH",
2389 SPR_NOACCESS, SPR_NOACCESS,
2390 &spr_read_generic, &spr_write_generic,
2391 0x00000000);
2392 /* XXX : not implemented */
2393 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2394 SPR_NOACCESS, SPR_NOACCESS,
2395 &spr_read_generic, &spr_write_generic,
2396 0x00000000);
2397 /* XXX : not implemented */
2398 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2399 SPR_NOACCESS, SPR_NOACCESS,
2400 &spr_read_generic, &spr_write_generic,
2401 0x00000000);
2402 /* XXX : not implemented */
2403 spr_register(env, SPR_MPC_BAR, "BAR",
2404 SPR_NOACCESS, SPR_NOACCESS,
2405 &spr_read_generic, &spr_write_generic,
2406 0x00000000);
2407 /* XXX : not implemented */
2408 spr_register(env, SPR_MPC_DPDR, "DPDR",
2409 SPR_NOACCESS, SPR_NOACCESS,
2410 &spr_read_generic, &spr_write_generic,
2411 0x00000000);
2412 /* XXX : not implemented */
2413 spr_register(env, SPR_MPC_IMMR, "IMMR",
2414 SPR_NOACCESS, SPR_NOACCESS,
2415 &spr_read_generic, &spr_write_generic,
2416 0x00000000);
2417 }
2418
2419 static void gen_spr_5xx (CPUPPCState *env)
2420 {
2421 /* XXX : not implemented */
2422 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2423 SPR_NOACCESS, SPR_NOACCESS,
2424 &spr_read_generic, &spr_write_generic,
2425 0x00000000);
2426 /* XXX : not implemented */
2427 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2428 SPR_NOACCESS, SPR_NOACCESS,
2429 &spr_read_generic, &spr_write_generic,
2430 0x00000000);
2431 /* XXX : not implemented */
2432 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2433 SPR_NOACCESS, SPR_NOACCESS,
2434 &spr_read_generic, &spr_write_generic,
2435 0x00000000);
2436 /* XXX : not implemented */
2437 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2438 SPR_NOACCESS, SPR_NOACCESS,
2439 &spr_read_generic, &spr_write_generic,
2440 0x00000000);
2441 /* XXX : not implemented */
2442 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2443 SPR_NOACCESS, SPR_NOACCESS,
2444 &spr_read_generic, &spr_write_generic,
2445 0x00000000);
2446 /* XXX : not implemented */
2447 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2448 SPR_NOACCESS, SPR_NOACCESS,
2449 &spr_read_generic, &spr_write_generic,
2450 0x00000000);
2451 /* XXX : not implemented */
2452 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2453 SPR_NOACCESS, SPR_NOACCESS,
2454 &spr_read_generic, &spr_write_generic,
2455 0x00000000);
2456 /* XXX : not implemented */
2457 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2458 SPR_NOACCESS, SPR_NOACCESS,
2459 &spr_read_generic, &spr_write_generic,
2460 0x00000000);
2461 /* XXX : not implemented */
2462 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2463 SPR_NOACCESS, SPR_NOACCESS,
2464 &spr_read_generic, &spr_write_generic,
2465 0x00000000);
2466 /* XXX : not implemented */
2467 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2468 SPR_NOACCESS, SPR_NOACCESS,
2469 &spr_read_generic, &spr_write_generic,
2470 0x00000000);
2471 /* XXX : not implemented */
2472 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2473 SPR_NOACCESS, SPR_NOACCESS,
2474 &spr_read_generic, &spr_write_generic,
2475 0x00000000);
2476 /* XXX : not implemented */
2477 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2478 SPR_NOACCESS, SPR_NOACCESS,
2479 &spr_read_generic, &spr_write_generic,
2480 0x00000000);
2481 /* XXX : not implemented */
2482 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2483 SPR_NOACCESS, SPR_NOACCESS,
2484 &spr_read_generic, &spr_write_generic,
2485 0x00000000);
2486 /* XXX : not implemented */
2487 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2488 SPR_NOACCESS, SPR_NOACCESS,
2489 &spr_read_generic, &spr_write_generic,
2490 0x00000000);
2491 /* XXX : not implemented */
2492 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2493 SPR_NOACCESS, SPR_NOACCESS,
2494 &spr_read_generic, &spr_write_generic,
2495 0x00000000);
2496 /* XXX : not implemented */
2497 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2498 SPR_NOACCESS, SPR_NOACCESS,
2499 &spr_read_generic, &spr_write_generic,
2500 0x00000000);
2501 /* XXX : not implemented */
2502 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2503 SPR_NOACCESS, SPR_NOACCESS,
2504 &spr_read_generic, &spr_write_generic,
2505 0x00000000);
2506 /* XXX : not implemented */
2507 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2508 SPR_NOACCESS, SPR_NOACCESS,
2509 &spr_read_generic, &spr_write_generic,
2510 0x00000000);
2511 /* XXX : not implemented */
2512 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2513 SPR_NOACCESS, SPR_NOACCESS,
2514 &spr_read_generic, &spr_write_generic,
2515 0x00000000);
2516 /* XXX : not implemented */
2517 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2518 SPR_NOACCESS, SPR_NOACCESS,
2519 &spr_read_generic, &spr_write_generic,
2520 0x00000000);
2521 /* XXX : not implemented */
2522 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2523 SPR_NOACCESS, SPR_NOACCESS,
2524 &spr_read_generic, &spr_write_generic,
2525 0x00000000);
2526 }
2527
2528 static void gen_spr_8xx (CPUPPCState *env)
2529 {
2530 /* XXX : not implemented */
2531 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2532 SPR_NOACCESS, SPR_NOACCESS,
2533 &spr_read_generic, &spr_write_generic,
2534 0x00000000);
2535 /* XXX : not implemented */
2536 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2537 SPR_NOACCESS, SPR_NOACCESS,
2538 &spr_read_generic, &spr_write_generic,
2539 0x00000000);
2540 /* XXX : not implemented */
2541 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2542 SPR_NOACCESS, SPR_NOACCESS,
2543 &spr_read_generic, &spr_write_generic,
2544 0x00000000);
2545 /* XXX : not implemented */
2546 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2547 SPR_NOACCESS, SPR_NOACCESS,
2548 &spr_read_generic, &spr_write_generic,
2549 0x00000000);
2550 /* XXX : not implemented */
2551 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2552 SPR_NOACCESS, SPR_NOACCESS,
2553 &spr_read_generic, &spr_write_generic,
2554 0x00000000);
2555 /* XXX : not implemented */
2556 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2557 SPR_NOACCESS, SPR_NOACCESS,
2558 &spr_read_generic, &spr_write_generic,
2559 0x00000000);
2560 /* XXX : not implemented */
2561 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2562 SPR_NOACCESS, SPR_NOACCESS,
2563 &spr_read_generic, &spr_write_generic,
2564 0x00000000);
2565 /* XXX : not implemented */
2566 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2567 SPR_NOACCESS, SPR_NOACCESS,
2568 &spr_read_generic, &spr_write_generic,
2569 0x00000000);
2570 /* XXX : not implemented */
2571 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2572 SPR_NOACCESS, SPR_NOACCESS,
2573 &spr_read_generic, &spr_write_generic,
2574 0x00000000);
2575 /* XXX : not implemented */
2576 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2577 SPR_NOACCESS, SPR_NOACCESS,
2578 &spr_read_generic, &spr_write_generic,
2579 0x00000000);
2580 /* XXX : not implemented */
2581 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2582 SPR_NOACCESS, SPR_NOACCESS,
2583 &spr_read_generic, &spr_write_generic,
2584 0x00000000);
2585 /* XXX : not implemented */
2586 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2587 SPR_NOACCESS, SPR_NOACCESS,
2588 &spr_read_generic, &spr_write_generic,
2589 0x00000000);
2590 /* XXX : not implemented */
2591 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2592 SPR_NOACCESS, SPR_NOACCESS,
2593 &spr_read_generic, &spr_write_generic,
2594 0x00000000);
2595 /* XXX : not implemented */
2596 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2597 SPR_NOACCESS, SPR_NOACCESS,
2598 &spr_read_generic, &spr_write_generic,
2599 0x00000000);
2600 /* XXX : not implemented */
2601 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2602 SPR_NOACCESS, SPR_NOACCESS,
2603 &spr_read_generic, &spr_write_generic,
2604 0x00000000);
2605 /* XXX : not implemented */
2606 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2607 SPR_NOACCESS, SPR_NOACCESS,
2608 &spr_read_generic, &spr_write_generic,
2609 0x00000000);
2610 /* XXX : not implemented */
2611 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2612 SPR_NOACCESS, SPR_NOACCESS,
2613 &spr_read_generic, &spr_write_generic,
2614 0x00000000);
2615 /* XXX : not implemented */
2616 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2617 SPR_NOACCESS, SPR_NOACCESS,
2618 &spr_read_generic, &spr_write_generic,
2619 0x00000000);
2620 /* XXX : not implemented */
2621 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2622 SPR_NOACCESS, SPR_NOACCESS,
2623 &spr_read_generic, &spr_write_generic,
2624 0x00000000);
2625 /* XXX : not implemented */
2626 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2627 SPR_NOACCESS, SPR_NOACCESS,
2628 &spr_read_generic, &spr_write_generic,
2629 0x00000000);
2630 /* XXX : not implemented */
2631 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2632 SPR_NOACCESS, SPR_NOACCESS,
2633 &spr_read_generic, &spr_write_generic,
2634 0x00000000);
2635 /* XXX : not implemented */
2636 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2637 SPR_NOACCESS, SPR_NOACCESS,
2638 &spr_read_generic, &spr_write_generic,
2639 0x00000000);
2640 /* XXX : not implemented */
2641 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2642 SPR_NOACCESS, SPR_NOACCESS,
2643 &spr_read_generic, &spr_write_generic,
2644 0x00000000);
2645 /* XXX : not implemented */
2646 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2647 SPR_NOACCESS, SPR_NOACCESS,
2648 &spr_read_generic, &spr_write_generic,
2649 0x00000000);
2650 /* XXX : not implemented */
2651 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2652 SPR_NOACCESS, SPR_NOACCESS,
2653 &spr_read_generic, &spr_write_generic,
2654 0x00000000);
2655 }
2656
2657 // XXX: TODO
2658 /*
2659 * AMR => SPR 29 (Power 2.04)
2660 * CTRL => SPR 136 (Power 2.04)
2661 * CTRL => SPR 152 (Power 2.04)
2662 * SCOMC => SPR 276 (64 bits ?)
2663 * SCOMD => SPR 277 (64 bits ?)
2664 * TBU40 => SPR 286 (Power 2.04 hypv)
2665 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2666 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2667 * HDSISR => SPR 306 (Power 2.04 hypv)
2668 * HDAR => SPR 307 (Power 2.04 hypv)
2669 * PURR => SPR 309 (Power 2.04 hypv)
2670 * HDEC => SPR 310 (Power 2.04 hypv)
2671 * HIOR => SPR 311 (hypv)
2672 * RMOR => SPR 312 (970)
2673 * HRMOR => SPR 313 (Power 2.04 hypv)
2674 * HSRR0 => SPR 314 (Power 2.04 hypv)
2675 * HSRR1 => SPR 315 (Power 2.04 hypv)
2676 * LPCR => SPR 316 (970)
2677 * LPIDR => SPR 317 (970)
2678 * EPR => SPR 702 (Power 2.04 emb)
2679 * perf => 768-783 (Power 2.04)
2680 * perf => 784-799 (Power 2.04)
2681 * PPR => SPR 896 (Power 2.04)
2682 * EPLC => SPR 947 (Power 2.04 emb)
2683 * EPSC => SPR 948 (Power 2.04 emb)
2684 * DABRX => 1015 (Power 2.04 hypv)
2685 * FPECR => SPR 1022 (?)
2686 * ... and more (thermal management, performance counters, ...)
2687 */
2688
2689 /*****************************************************************************/
2690 /* Exception vectors models */
2691 static void init_excp_4xx_real (CPUPPCState *env)
2692 {
2693 #if !defined(CONFIG_USER_ONLY)
2694 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2695 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2696 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2697 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2698 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2699 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2700 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2701 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2702 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2703 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2704 env->hreset_excp_prefix = 0x00000000UL;
2705 env->ivor_mask = 0x0000FFF0UL;
2706 env->ivpr_mask = 0xFFFF0000UL;
2707 /* Hardware reset vector */
2708 env->hreset_vector = 0xFFFFFFFCUL;
2709 #endif
2710 }
2711
2712 static void init_excp_4xx_softmmu (CPUPPCState *env)
2713 {
2714 #if !defined(CONFIG_USER_ONLY)
2715 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2716 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2717 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2718 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2719 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2720 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2721 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2722 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2723 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2724 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2725 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2726 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2727 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2728 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2729 env->hreset_excp_prefix = 0x00000000UL;
2730 env->ivor_mask = 0x0000FFF0UL;
2731 env->ivpr_mask = 0xFFFF0000UL;
2732 /* Hardware reset vector */
2733 env->hreset_vector = 0xFFFFFFFCUL;
2734 #endif
2735 }
2736
2737 static void init_excp_MPC5xx (CPUPPCState *env)
2738 {
2739 #if !defined(CONFIG_USER_ONLY)
2740 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2741 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2742 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2743 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2744 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2745 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2746 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2747 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2748 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2749 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2750 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2751 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2752 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2753 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2754 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2755 env->hreset_excp_prefix = 0x00000000UL;
2756 env->ivor_mask = 0x0000FFF0UL;
2757 env->ivpr_mask = 0xFFFF0000UL;
2758 /* Hardware reset vector */
2759 env->hreset_vector = 0xFFFFFFFCUL;
2760 #endif
2761 }
2762
2763 static void init_excp_MPC8xx (CPUPPCState *env)
2764 {
2765 #if !defined(CONFIG_USER_ONLY)
2766 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2767 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2768 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2769 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2770 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2771 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2772 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2773 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2774 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2775 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2776 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2777 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2778 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2779 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2780 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2781 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2782 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2783 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2784 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2785 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2786 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2787 env->hreset_excp_prefix = 0x00000000UL;
2788 env->ivor_mask = 0x0000FFF0UL;
2789 env->ivpr_mask = 0xFFFF0000UL;
2790 /* Hardware reset vector */
2791 env->hreset_vector = 0xFFFFFFFCUL;
2792 #endif
2793 }
2794
2795 static void init_excp_G2 (CPUPPCState *env)
2796 {
2797 #if !defined(CONFIG_USER_ONLY)
2798 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2799 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2800 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2801 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2802 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2803 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2804 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2805 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2806 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2807 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2808 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2809 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2810 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2811 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2812 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2813 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2814 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2815 env->hreset_excp_prefix = 0x00000000UL;
2816 /* Hardware reset vector */
2817 env->hreset_vector = 0xFFFFFFFCUL;
2818 #endif
2819 }
2820
2821 static void init_excp_e200 (CPUPPCState *env)
2822 {
2823 #if !defined(CONFIG_USER_ONLY)
2824 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2825 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2826 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2827 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2828 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2829 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2830 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2831 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2832 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2833 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2834 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2835 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2836 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2837 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2838 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2839 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2840 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2841 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2842 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2843 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2844 env->hreset_excp_prefix = 0x00000000UL;
2845 env->ivor_mask = 0x0000FFF7UL;
2846 env->ivpr_mask = 0xFFFF0000UL;
2847 /* Hardware reset vector */
2848 env->hreset_vector = 0xFFFFFFFCUL;
2849 #endif
2850 }
2851
2852 static void init_excp_BookE (CPUPPCState *env)
2853 {
2854 #if !defined(CONFIG_USER_ONLY)
2855 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2856 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2857 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2858 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2859 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2860 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2861 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2862 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2863 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2864 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2865 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2866 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2867 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2868 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2869 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2870 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2871 env->hreset_excp_prefix = 0x00000000UL;
2872 env->ivor_mask = 0x0000FFE0UL;
2873 env->ivpr_mask = 0xFFFF0000UL;
2874 /* Hardware reset vector */
2875 env->hreset_vector = 0xFFFFFFFCUL;
2876 #endif
2877 }
2878
2879 static void init_excp_601 (CPUPPCState *env)
2880 {
2881 #if !defined(CONFIG_USER_ONLY)
2882 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2883 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2884 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2885 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2886 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2887 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2888 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2889 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2890 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2891 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2892 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2893 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2894 env->hreset_excp_prefix = 0xFFF00000UL;
2895 /* Hardware reset vector */
2896 env->hreset_vector = 0x00000100UL;
2897 #endif
2898 }
2899
2900 static void init_excp_602 (CPUPPCState *env)
2901 {
2902 #if !defined(CONFIG_USER_ONLY)
2903 /* XXX: exception prefix has a special behavior on 602 */
2904 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2905 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2906 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2907 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2908 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2909 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2910 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2911 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2912 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2913 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2914 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2915 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2916 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2917 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2918 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2919 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2920 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2921 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2922 env->hreset_excp_prefix = 0xFFF00000UL;
2923 /* Hardware reset vector */
2924 env->hreset_vector = 0xFFFFFFFCUL;
2925 #endif
2926 }
2927
2928 static void init_excp_603 (CPUPPCState *env)
2929 {
2930 #if !defined(CONFIG_USER_ONLY)
2931 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2932 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2933 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2934 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2935 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2936 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2937 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2938 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2939 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2940 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2941 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2942 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2943 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2944 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2945 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2946 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2947 env->hreset_excp_prefix = 0x00000000UL;
2948 /* Hardware reset vector */
2949 env->hreset_vector = 0xFFFFFFFCUL;
2950 #endif
2951 }
2952
2953 static void init_excp_604 (CPUPPCState *env)
2954 {
2955 #if !defined(CONFIG_USER_ONLY)
2956 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2957 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2958 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2959 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2960 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2961 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2962 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2963 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2964 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2965 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2966 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2967 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2968 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2969 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2970 env->hreset_excp_prefix = 0xFFF00000UL;
2971 /* Hardware reset vector */
2972 env->hreset_vector = 0x00000100UL;
2973 #endif
2974 }
2975
2976 #if defined(TARGET_PPC64)
2977 static void init_excp_620 (CPUPPCState *env)
2978 {
2979 #if !defined(CONFIG_USER_ONLY)
2980 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2981 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2982 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2983 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2984 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2985 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2986 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2987 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2988 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2989 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2990 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2991 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2992 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2993 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2994 env->hreset_excp_prefix = 0xFFF00000UL;
2995 /* Hardware reset vector */
2996 env->hreset_vector = 0x0000000000000100ULL;
2997 #endif
2998 }
2999 #endif /* defined(TARGET_PPC64) */
3000
3001 static void init_excp_7x0 (CPUPPCState *env)
3002 {
3003 #if !defined(CONFIG_USER_ONLY)
3004 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3005 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3006 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3007 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3008 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3009 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3010 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3011 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3012 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3013 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3014 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3015 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3016 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3017 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3018 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3019 env->hreset_excp_prefix = 0x00000000UL;
3020 /* Hardware reset vector */
3021 env->hreset_vector = 0xFFFFFFFCUL;
3022 #endif
3023 }
3024
3025 static void init_excp_750cl (CPUPPCState *env)
3026 {
3027 #if !defined(CONFIG_USER_ONLY)
3028 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3029 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3030 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3031 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3032 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3033 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3034 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3035 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3036 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3037 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3038 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3039 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3040 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3041 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3042 env->hreset_excp_prefix = 0x00000000UL;
3043 /* Hardware reset vector */
3044 env->hreset_vector = 0xFFFFFFFCUL;
3045 #endif
3046 }
3047
3048 static void init_excp_750cx (CPUPPCState *env)
3049 {
3050 #if !defined(CONFIG_USER_ONLY)
3051 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3052 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3053 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3054 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3055 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3056 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3057 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3058 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3059 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3060 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3061 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3062 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3063 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3064 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3065 env->hreset_excp_prefix = 0x00000000UL;
3066 /* Hardware reset vector */
3067 env->hreset_vector = 0xFFFFFFFCUL;
3068 #endif
3069 }
3070
3071 /* XXX: Check if this is correct */
3072 static void init_excp_7x5 (CPUPPCState *env)
3073 {
3074 #if !defined(CONFIG_USER_ONLY)
3075 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3076 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3077 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3078 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3079 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3080 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3081 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3082 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3083 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3084 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3085 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3086 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3087 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3088 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3089 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3090 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3091 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3092 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3093 env->hreset_excp_prefix = 0x00000000UL;
3094 /* Hardware reset vector */
3095 env->hreset_vector = 0xFFFFFFFCUL;
3096 #endif
3097 }
3098
3099 static void init_excp_7400 (CPUPPCState *env)
3100 {
3101 #if !defined(CONFIG_USER_ONLY)
3102 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3103 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3104 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3105 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3106 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3107 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3108 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3109 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3110 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3111 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3112 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3113 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3114 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3115 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3116 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3117 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3118 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3119 env->hreset_excp_prefix = 0x00000000UL;
3120 /* Hardware reset vector */
3121 env->hreset_vector = 0xFFFFFFFCUL;
3122 #endif
3123 }
3124
3125 static void init_excp_7450 (CPUPPCState *env)
3126 {
3127 #if !defined(CONFIG_USER_ONLY)
3128 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3129 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3130 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3131 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3132 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3133 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3134 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3135 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3136 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3137 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3138 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3139 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3140 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3141 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3142 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3143 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3144 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3145 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3146 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3147 env->hreset_excp_prefix = 0x00000000UL;
3148 /* Hardware reset vector */
3149 env->hreset_vector = 0xFFFFFFFCUL;
3150 #endif
3151 }
3152
3153 #if defined (TARGET_PPC64)
3154 static void init_excp_970 (CPUPPCState *env)
3155 {
3156 #if !defined(CONFIG_USER_ONLY)
3157 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3158 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3159 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3160 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3161 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3162 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3163 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3164 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3165 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3166 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3167 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3168 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3169 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3170 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3171 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3172 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3173 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3174 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3175 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3176 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3177 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
3178 /* Hardware reset vector */
3179 env->hreset_vector = 0x0000000000000100ULL;
3180 #endif
3181 }
3182
3183 static void init_excp_POWER7 (CPUPPCState *env)
3184 {
3185 #if !defined(CONFIG_USER_ONLY)
3186 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3187 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3188 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3189 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3190 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3191 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3192 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3193 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3194 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3195 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3196 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3197 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3198 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3199 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3200 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3201 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3202 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3203 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3204 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3205 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3206 env->hreset_excp_prefix = 0;
3207 /* Hardware reset vector */
3208 env->hreset_vector = 0x0000000000000100ULL;
3209 #endif
3210 }
3211 #endif
3212
3213 /*****************************************************************************/
3214 /* Power management enable checks */
3215 static int check_pow_none (CPUPPCState *env)
3216 {
3217 return 0;
3218 }
3219
3220 static int check_pow_nocheck (CPUPPCState *env)
3221 {
3222 return 1;
3223 }
3224
3225 static int check_pow_hid0 (CPUPPCState *env)
3226 {
3227 if (env->spr[SPR_HID0] & 0x00E00000)
3228 return 1;
3229
3230 return 0;
3231 }
3232
3233 static int check_pow_hid0_74xx (CPUPPCState *env)
3234 {
3235 if (env->spr[SPR_HID0] & 0x00600000)
3236 return 1;
3237
3238 return 0;
3239 }
3240
3241 /*****************************************************************************/
3242 /* PowerPC implementations definitions */
3243
3244 /* PowerPC 401 */
3245 #define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3246 PPC_WRTEE | PPC_DCR | \
3247 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3248 PPC_CACHE_DCBZ | \
3249 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3250 PPC_4xx_COMMON | PPC_40x_EXCP)
3251 #define POWERPC_INSNS2_401 (PPC_NONE)
3252 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
3253 #define POWERPC_MMU_401 (POWERPC_MMU_REAL)
3254 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3255 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
3256 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
3257 #define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3258 POWERPC_FLAG_BUS_CLK)
3259 #define check_pow_401 check_pow_nocheck
3260
3261 static void init_proc_401 (CPUPPCState *env)
3262 {
3263 gen_spr_40x(env);
3264 gen_spr_401_403(env);
3265 gen_spr_401(env);
3266 init_excp_4xx_real(env);
3267 env->dcache_line_size = 32;
3268 env->icache_line_size = 32;
3269 /* Allocate hardware IRQ controller */
3270 ppc40x_irq_init(env);
3271
3272 SET_FIT_PERIOD(12, 16, 20, 24);
3273 SET_WDT_PERIOD(16, 20, 24, 28);
3274 }
3275
3276 /* PowerPC 401x2 */
3277 #define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3278 PPC_DCR | PPC_WRTEE | \
3279 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3280 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3281 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3282 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3283 PPC_4xx_COMMON | PPC_40x_EXCP)
3284 #define POWERPC_INSNS2_401x2 (PPC_NONE)
3285 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3286 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3287 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3288 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
3289 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
3290 #define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3291 POWERPC_FLAG_BUS_CLK)
3292 #define check_pow_401x2 check_pow_nocheck
3293
3294 static void init_proc_401x2 (CPUPPCState *env)
3295 {
3296 gen_spr_40x(env);
3297 gen_spr_401_403(env);
3298 gen_spr_401x2(env);
3299 gen_spr_compress(env);
3300 /* Memory management */
3301 #if !defined(CONFIG_USER_ONLY)
3302 env->nb_tlb = 64;
3303 env->nb_ways = 1;
3304 env->id_tlbs = 0;
3305 env->tlb_type = TLB_EMB;
3306 #endif
3307 init_excp_4xx_softmmu(env);
3308 env->dcache_line_size = 32;
3309 env->icache_line_size = 32;
3310 /* Allocate hardware IRQ controller */
3311 ppc40x_irq_init(env);
3312
3313 SET_FIT_PERIOD(12, 16, 20, 24);
3314 SET_WDT_PERIOD(16, 20, 24, 28);
3315 }
3316
3317 /* PowerPC 401x3 */
3318 #define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3319 PPC_DCR | PPC_WRTEE | \
3320 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3321 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3322 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3323 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3324 PPC_4xx_COMMON | PPC_40x_EXCP)
3325 #define POWERPC_INSNS2_401x3 (PPC_NONE)
3326 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3327 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3328 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3329 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
3330 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
3331 #define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3332 POWERPC_FLAG_BUS_CLK)
3333 #define check_pow_401x3 check_pow_nocheck
3334
3335 __attribute__ (( unused ))
3336 static void init_proc_401x3 (CPUPPCState *env)
3337 {
3338 gen_spr_40x(env);
3339 gen_spr_401_403(env);
3340 gen_spr_401(env);
3341 gen_spr_401x2(env);
3342 gen_spr_compress(env);
3343 init_excp_4xx_softmmu(env);
3344 env->dcache_line_size = 32;
3345 env->icache_line_size = 32;
3346 /* Allocate hardware IRQ controller */
3347 ppc40x_irq_init(env);
3348
3349 SET_FIT_PERIOD(12, 16, 20, 24);
3350 SET_WDT_PERIOD(16, 20, 24, 28);
3351 }
3352
3353 /* IOP480 */
3354 #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3355 PPC_DCR | PPC_WRTEE | \
3356 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3357 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3358 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3359 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3360 PPC_4xx_COMMON | PPC_40x_EXCP)
3361 #define POWERPC_INSNS2_IOP480 (PPC_NONE)
3362 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3363 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3364 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3365 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
3366 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
3367 #define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3368 POWERPC_FLAG_BUS_CLK)
3369 #define check_pow_IOP480 check_pow_nocheck
3370
3371 static void init_proc_IOP480 (CPUPPCState *env)
3372 {
3373 gen_spr_40x(env);
3374 gen_spr_401_403(env);
3375 gen_spr_401x2(env);
3376 gen_spr_compress(env);
3377 /* Memory management */
3378 #if !defined(CONFIG_USER_ONLY)
3379 env->nb_tlb = 64;
3380 env->nb_ways = 1;
3381 env->id_tlbs = 0;
3382 env->tlb_type = TLB_EMB;
3383 #endif
3384 init_excp_4xx_softmmu(env);
3385 env->dcache_line_size = 32;
3386 env->icache_line_size = 32;
3387 /* Allocate hardware IRQ controller */
3388 ppc40x_irq_init(env);
3389
3390 SET_FIT_PERIOD(8, 12, 16, 20);
3391 SET_WDT_PERIOD(16, 20, 24, 28);
3392 }
3393
3394 /* PowerPC 403 */
3395 #define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3396 PPC_DCR | PPC_WRTEE | \
3397 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3398 PPC_CACHE_DCBZ | \
3399 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3400 PPC_4xx_COMMON | PPC_40x_EXCP)
3401 #define POWERPC_INSNS2_403 (PPC_NONE)
3402 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
3403 #define POWERPC_MMU_403 (POWERPC_MMU_REAL)
3404 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3405 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
3406 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
3407 #define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3408 POWERPC_FLAG_BUS_CLK)
3409 #define check_pow_403 check_pow_nocheck
3410
3411 static void init_proc_403 (CPUPPCState *env)
3412 {
3413 gen_spr_40x(env);
3414 gen_spr_401_403(env);
3415 gen_spr_403(env);
3416 gen_spr_403_real(env);
3417 init_excp_4xx_real(env);
3418 env->dcache_line_size = 32;
3419 env->icache_line_size = 32;
3420 /* Allocate hardware IRQ controller */
3421 ppc40x_irq_init(env);
3422
3423 SET_FIT_PERIOD(8, 12, 16, 20);
3424 SET_WDT_PERIOD(16, 20, 24, 28);
3425 }
3426
3427 /* PowerPC 403 GCX */
3428 #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3429 PPC_DCR | PPC_WRTEE | \
3430 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3431 PPC_CACHE_DCBZ | \
3432 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3433 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3434 PPC_4xx_COMMON | PPC_40x_EXCP)
3435 #define POWERPC_INSNS2_403GCX (PPC_NONE)
3436 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3437 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3438 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3439 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
3440 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
3441 #define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3442 POWERPC_FLAG_BUS_CLK)
3443 #define check_pow_403GCX check_pow_nocheck
3444
3445 static void init_proc_403GCX (CPUPPCState *env)
3446 {
3447 gen_spr_40x(env);
3448 gen_spr_401_403(env);
3449 gen_spr_403(env);
3450 gen_spr_403_real(env);
3451 gen_spr_403_mmu(env);
3452 /* Bus access control */
3453 /* not emulated, as Qemu never does speculative access */
3454 spr_register(env, SPR_40x_SGR, "SGR",
3455 SPR_NOACCESS, SPR_NOACCESS,
3456 &spr_read_generic, &spr_write_generic,
3457 0xFFFFFFFF);
3458 /* not emulated, as Qemu do not emulate caches */
3459 spr_register(env, SPR_40x_DCWR, "DCWR",
3460 SPR_NOACCESS, SPR_NOACCESS,
3461 &spr_read_generic, &spr_write_generic,
3462 0x00000000);
3463 /* Memory management */
3464 #if !defined(CONFIG_USER_ONLY)
3465 env->nb_tlb = 64;
3466 env->nb_ways = 1;
3467 env->id_tlbs = 0;
3468 env->tlb_type = TLB_EMB;
3469 #endif
3470 init_excp_4xx_softmmu(env);
3471 env->dcache_line_size = 32;
3472 env->icache_line_size = 32;
3473 /* Allocate hardware IRQ controller */
3474 ppc40x_irq_init(env);
3475
3476 SET_FIT_PERIOD(8, 12, 16, 20);
3477 SET_WDT_PERIOD(16, 20, 24, 28);
3478 }
3479
3480 /* PowerPC 405 */
3481 #define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3482 PPC_DCR | PPC_WRTEE | \
3483 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3484 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3485 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3486 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3487 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3488 #define POWERPC_INSNS2_405 (PPC_NONE)
3489 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
3490 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3491 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3492 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3493 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3494 #define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3495 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3496 #define check_pow_405 check_pow_nocheck
3497
3498 static void init_proc_405 (CPUPPCState *env)
3499 {
3500 /* Time base */
3501 gen_tbl(env);
3502 gen_spr_40x(env);
3503 gen_spr_405(env);
3504 /* Bus access control */
3505 /* not emulated, as Qemu never does speculative access */
3506 spr_register(env, SPR_40x_SGR, "SGR",
3507 SPR_NOACCESS, SPR_NOACCESS,
3508 &spr_read_generic, &spr_write_generic,
3509 0xFFFFFFFF);
3510 /* not emulated, as Qemu do not emulate caches */
3511 spr_register(env, SPR_40x_DCWR, "DCWR",
3512 SPR_NOACCESS, SPR_NOACCESS,
3513 &spr_read_generic, &spr_write_generic,
3514 0x00000000);
3515 /* Memory management */
3516 #if !defined(CONFIG_USER_ONLY)
3517 env->nb_tlb = 64;
3518 env->nb_ways = 1;
3519 env->id_tlbs = 0;
3520 env->tlb_type = TLB_EMB;
3521 #endif
3522 init_excp_4xx_softmmu(env);
3523 env->dcache_line_size = 32;
3524 env->icache_line_size = 32;
3525 /* Allocate hardware IRQ controller */
3526 ppc40x_irq_init(env);
3527
3528 SET_FIT_PERIOD(8, 12, 16, 20);
3529 SET_WDT_PERIOD(16, 20, 24, 28);
3530 }
3531
3532 /* PowerPC 440 EP */
3533 #define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3534 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3535 PPC_CACHE | PPC_CACHE_ICBI | \
3536 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3537 PPC_MEM_TLBSYNC | PPC_MFTB | \
3538 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3539 PPC_440_SPEC)
3540 #define POWERPC_INSNS2_440EP (PPC_NONE)
3541 #define POWERPC_MSRM_440EP (0x000000000006D630ULL)
3542 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3543 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3544 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3545 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3546 #define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3547 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3548 #define check_pow_440EP check_pow_nocheck
3549
3550 __attribute__ (( unused ))
3551 static void init_proc_440EP (CPUPPCState *env)
3552 {
3553 /* Time base */
3554 gen_tbl(env);
3555 gen_spr_BookE(env, 0x000000000000FFFFULL);
3556 gen_spr_440(env);
3557 gen_spr_usprgh(env);
3558 /* Processor identification */
3559 spr_register(env, SPR_BOOKE_PIR, "PIR",
3560 SPR_NOACCESS, SPR_NOACCESS,
3561 &spr_read_generic, &spr_write_pir,
3562 0x00000000);
3563 /* XXX : not implemented */
3564 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3565 SPR_NOACCESS, SPR_NOACCESS,
3566 &spr_read_generic, &spr_write_generic,
3567 0x00000000);
3568 /* XXX : not implemented */
3569 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3570 SPR_NOACCESS, SPR_NOACCESS,
3571 &spr_read_generic, &spr_write_generic,
3572 0x00000000);
3573 /* XXX : not implemented */
3574 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3575 SPR_NOACCESS, SPR_NOACCESS,
3576 &spr_read_generic, &spr_write_generic,
3577 0x00000000);
3578 /* XXX : not implemented */
3579 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3580 SPR_NOACCESS, SPR_NOACCESS,
3581 &spr_read_generic, &spr_write_generic,
3582 0x00000000);
3583 /* XXX : not implemented */
3584 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3585 SPR_NOACCESS, SPR_NOACCESS,
3586 &spr_read_generic, &spr_write_generic,
3587 0x00000000);
3588 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3589 SPR_NOACCESS, SPR_NOACCESS,
3590 &spr_read_generic, &spr_write_generic,
3591 0x00000000);
3592 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3593 SPR_NOACCESS, SPR_NOACCESS,
3594 &spr_read_generic, &spr_write_generic,
3595 0x00000000);
3596 /* XXX : not implemented */
3597 spr_register(env, SPR_440_CCR1, "CCR1",
3598 SPR_NOACCESS, SPR_NOACCESS,
3599 &spr_read_generic, &spr_write_generic,
3600 0x00000000);
3601 /* Memory management */
3602 #if !defined(CONFIG_USER_ONLY)
3603 env->nb_tlb = 64;
3604 env->nb_ways = 1;
3605 env->id_tlbs = 0;
3606 env->tlb_type = TLB_EMB;
3607 #endif
3608 init_excp_BookE(env);
3609 env->dcache_line_size = 32;
3610 env->icache_line_size = 32;
3611 /* XXX: TODO: allocate internal IRQ controller */
3612
3613 SET_FIT_PERIOD(12, 16, 20, 24);
3614 SET_WDT_PERIOD(20, 24, 28, 32);
3615 }
3616
3617 /* PowerPC 440 GP */
3618 #define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3619 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3620 PPC_CACHE | PPC_CACHE_ICBI | \
3621 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3622 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \
3623 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3624 PPC_440_SPEC)
3625 #define POWERPC_INSNS2_440GP (PPC_NONE)
3626 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3627 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3628 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3629 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3630 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3631 #define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3632 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3633 #define check_pow_440GP check_pow_nocheck
3634
3635 __attribute__ (( unused ))
3636 static void init_proc_440GP (CPUPPCState *env)
3637 {
3638 /* Time base */
3639 gen_tbl(env);
3640 gen_spr_BookE(env, 0x000000000000FFFFULL);
3641 gen_spr_440(env);
3642 gen_spr_usprgh(env);
3643 /* Processor identification */
3644 spr_register(env, SPR_BOOKE_PIR, "PIR",
3645 SPR_NOACCESS, SPR_NOACCESS,
3646 &spr_read_generic, &spr_write_pir,
3647 0x00000000);
3648 /* XXX : not implemented */
3649 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3650 SPR_NOACCESS, SPR_NOACCESS,
3651 &spr_read_generic, &spr_write_generic,
3652 0x00000000);
3653 /* XXX : not implemented */
3654 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3655 SPR_NOACCESS, SPR_NOACCESS,
3656 &spr_read_generic, &spr_write_generic,
3657 0x00000000);
3658 /* XXX : not implemented */
3659 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3660 SPR_NOACCESS, SPR_NOACCESS,
3661 &spr_read_generic, &spr_write_generic,
3662 0x00000000);
3663 /* XXX : not implemented */
3664 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3665 SPR_NOACCESS, SPR_NOACCESS,
3666 &spr_read_generic, &spr_write_generic,
3667 0x00000000);
3668 /* Memory management */
3669 #if !defined(CONFIG_USER_ONLY)
3670 env->nb_tlb = 64;
3671 env->nb_ways = 1;
3672 env->id_tlbs = 0;
3673 env->tlb_type = TLB_EMB;
3674 #endif
3675 init_excp_BookE(env);
3676 env->dcache_line_size = 32;
3677 env->icache_line_size = 32;
3678 /* XXX: TODO: allocate internal IRQ controller */
3679
3680 SET_FIT_PERIOD(12, 16, 20, 24);
3681 SET_WDT_PERIOD(20, 24, 28, 32);
3682 }
3683
3684 /* PowerPC 440x4 */
3685 #define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3686 PPC_DCR | PPC_WRTEE | \
3687 PPC_CACHE | PPC_CACHE_ICBI | \
3688 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3689 PPC_MEM_TLBSYNC | PPC_MFTB | \
3690 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3691 PPC_440_SPEC)
3692 #define POWERPC_INSNS2_440x4 (PPC_NONE)
3693 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3694 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3695 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3696 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3697 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3698 #define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3699 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3700 #define check_pow_440x4 check_pow_nocheck
3701
3702 __attribute__ (( unused ))
3703 static void init_proc_440x4 (CPUPPCState *env)
3704 {
3705 /* Time base */
3706 gen_tbl(env);
3707 gen_spr_BookE(env, 0x000000000000FFFFULL);
3708 gen_spr_440(env);
3709 gen_spr_usprgh(env);
3710 /* Processor identification */
3711 spr_register(env, SPR_BOOKE_PIR, "PIR",
3712 SPR_NOACCESS, SPR_NOACCESS,
3713 &spr_read_generic, &spr_write_pir,
3714 0x00000000);
3715 /* XXX : not implemented */
3716 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3717 SPR_NOACCESS, SPR_NOACCESS,
3718 &spr_read_generic, &spr_write_generic,
3719 0x00000000);
3720 /* XXX : not implemented */
3721 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3722 SPR_NOACCESS, SPR_NOACCESS,
3723 &spr_read_generic, &spr_write_generic,
3724 0x00000000);
3725 /* XXX : not implemented */
3726 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3727 SPR_NOACCESS, SPR_NOACCESS,
3728 &spr_read_generic, &spr_write_generic,
3729 0x00000000);
3730 /* XXX : not implemented */
3731 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3732 SPR_NOACCESS, SPR_NOACCESS,
3733 &spr_read_generic, &spr_write_generic,
3734 0x00000000);
3735 /* Memory management */
3736 #if !defined(CONFIG_USER_ONLY)
3737 env->nb_tlb = 64;
3738 env->nb_ways = 1;
3739 env->id_tlbs = 0;
3740 env->tlb_type = TLB_EMB;
3741 #endif
3742 init_excp_BookE(env);
3743 env->dcache_line_size = 32;
3744 env->icache_line_size = 32;
3745 /* XXX: TODO: allocate internal IRQ controller */
3746
3747 SET_FIT_PERIOD(12, 16, 20, 24);
3748 SET_WDT_PERIOD(20, 24, 28, 32);
3749 }
3750
3751 /* PowerPC 440x5 */
3752 #define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3753 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3754 PPC_CACHE | PPC_CACHE_ICBI | \
3755 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3756 PPC_MEM_TLBSYNC | PPC_MFTB | \
3757 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3758 PPC_440_SPEC)
3759 #define POWERPC_INSNS2_440x5 (PPC_NONE)
3760 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3761 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3762 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3763 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3764 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3765 #define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3766 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3767 #define check_pow_440x5 check_pow_nocheck
3768
3769 static void init_proc_440x5 (CPUPPCState *env)
3770 {
3771 /* Time base */
3772 gen_tbl(env);
3773 gen_spr_BookE(env, 0x000000000000FFFFULL);
3774 gen_spr_440(env);
3775 gen_spr_usprgh(env);
3776 /* Processor identification */
3777 spr_register(env, SPR_BOOKE_PIR, "PIR",
3778 SPR_NOACCESS, SPR_NOACCESS,
3779 &spr_read_generic, &spr_write_pir,
3780 0x00000000);
3781 /* XXX : not implemented */
3782 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3783 SPR_NOACCESS, SPR_NOACCESS,
3784 &spr_read_generic, &spr_write_generic,
3785 0x00000000);
3786 /* XXX : not implemented */
3787 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3788 SPR_NOACCESS, SPR_NOACCESS,
3789 &spr_read_generic, &spr_write_generic,
3790 0x00000000);
3791 /* XXX : not implemented */
3792 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3793 SPR_NOACCESS, SPR_NOACCESS,
3794 &spr_read_generic, &spr_write_generic,
3795 0x00000000);
3796 /* XXX : not implemented */
3797 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3798 SPR_NOACCESS, SPR_NOACCESS,
3799 &spr_read_generic, &spr_write_generic,
3800 0x00000000);
3801 /* XXX : not implemented */
3802 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3803 SPR_NOACCESS, SPR_NOACCESS,
3804 &spr_read_generic, &spr_write_generic,
3805 0x00000000);
3806 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3807 SPR_NOACCESS, SPR_NOACCESS,
3808 &spr_read_generic, &spr_write_generic,
3809 0x00000000);
3810 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3811 SPR_NOACCESS, SPR_NOACCESS,
3812 &spr_read_generic, &spr_write_generic,
3813 0x00000000);
3814 /* XXX : not implemented */
3815 spr_register(env, SPR_440_CCR1, "CCR1",
3816 SPR_NOACCESS, SPR_NOACCESS,
3817 &spr_read_generic, &spr_write_generic,
3818 0x00000000);
3819 /* Memory management */
3820 #if !defined(CONFIG_USER_ONLY)
3821 env->nb_tlb = 64;
3822 env->nb_ways = 1;
3823 env->id_tlbs = 0;
3824 env->tlb_type = TLB_EMB;
3825 #endif
3826 init_excp_BookE(env);
3827 env->dcache_line_size = 32;
3828 env->icache_line_size = 32;
3829 ppc40x_irq_init(env);
3830
3831 SET_FIT_PERIOD(12, 16, 20, 24);
3832 SET_WDT_PERIOD(20, 24, 28, 32);
3833 }
3834
3835 /* PowerPC 460 (guessed) */
3836 #define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
3837 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3838 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | \
3839 PPC_CACHE | PPC_CACHE_ICBI | \
3840 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3841 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3842 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3843 PPC_440_SPEC)
3844 #define POWERPC_INSNS2_460 (PPC_NONE)
3845 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3846 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3847 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3848 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3849 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3850 #define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3851 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3852 #define check_pow_460 check_pow_nocheck
3853
3854 __attribute__ (( unused ))
3855 static void init_proc_460 (CPUPPCState *env)
3856 {
3857 /* Time base */
3858 gen_tbl(env);
3859 gen_spr_BookE(env, 0x000000000000FFFFULL);
3860 gen_spr_440(env);
3861 gen_spr_usprgh(env);
3862 /* Processor identification */
3863 spr_register(env, SPR_BOOKE_PIR, "PIR",
3864 SPR_NOACCESS, SPR_NOACCESS,
3865 &spr_read_generic, &spr_write_pir,
3866 0x00000000);
3867 /* XXX : not implemented */
3868 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3869 SPR_NOACCESS, SPR_NOACCESS,
3870 &spr_read_generic, &spr_write_generic,
3871 0x00000000);
3872 /* XXX : not implemented */
3873 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3874 SPR_NOACCESS, SPR_NOACCESS,
3875 &spr_read_generic, &spr_write_generic,
3876 0x00000000);
3877 /* XXX : not implemented */
3878 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3879 SPR_NOACCESS, SPR_NOACCESS,
3880 &spr_read_generic, &spr_write_generic,
3881 0x00000000);
3882 /* XXX : not implemented */
3883 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3884 SPR_NOACCESS, SPR_NOACCESS,
3885 &spr_read_generic, &spr_write_generic,
3886 0x00000000);
3887 /* XXX : not implemented */
3888 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3889 SPR_NOACCESS, SPR_NOACCESS,
3890 &spr_read_generic, &spr_write_generic,
3891 0x00000000);
3892 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3893 SPR_NOACCESS, SPR_NOACCESS,
3894 &spr_read_generic, &spr_write_generic,
3895 0x00000000);
3896 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3897 SPR_NOACCESS, SPR_NOACCESS,
3898 &spr_read_generic, &spr_write_generic,
3899 0x00000000);
3900 /* XXX : not implemented */
3901 spr_register(env, SPR_440_CCR1, "CCR1",
3902 SPR_NOACCESS, SPR_NOACCESS,
3903 &spr_read_generic, &spr_write_generic,
3904 0x00000000);
3905 /* XXX : not implemented */
3906 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3907 &spr_read_generic, &spr_write_generic,
3908 &spr_read_generic, &spr_write_generic,
3909 0x00000000);
3910 /* Memory management */
3911 #if !defined(CONFIG_USER_ONLY)
3912 env->nb_tlb = 64;
3913 env->nb_ways = 1;
3914 env->id_tlbs = 0;
3915 env->tlb_type = TLB_EMB;
3916 #endif
3917 init_excp_BookE(env);
3918 env->dcache_line_size = 32;
3919 env->icache_line_size = 32;
3920 /* XXX: TODO: allocate internal IRQ controller */
3921
3922 SET_FIT_PERIOD(12, 16, 20, 24);
3923 SET_WDT_PERIOD(20, 24, 28, 32);
3924 }
3925
3926 /* PowerPC 460F (guessed) */
3927 #define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3928 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3929 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3930 PPC_FLOAT_STFIWX | PPC_MFTB | \
3931 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3932 PPC_WRTEE | PPC_MFAPIDI | \
3933 PPC_CACHE | PPC_CACHE_ICBI | \
3934 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3935 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3936 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3937 PPC_440_SPEC)
3938 #define POWERPC_INSNS2_460F (PPC_NONE)
3939 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3940 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3941 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3942 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3943 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3944 #define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3945 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3946 #define check_pow_460F check_pow_nocheck
3947
3948 __attribute__ (( unused ))
3949 static void init_proc_460F (CPUPPCState *env)
3950 {
3951 /* Time base */
3952 gen_tbl(env);
3953 gen_spr_BookE(env, 0x000000000000FFFFULL);
3954 gen_spr_440(env);
3955 gen_spr_usprgh(env);
3956 /* Processor identification */
3957 spr_register(env, SPR_BOOKE_PIR, "PIR",
3958 SPR_NOACCESS, SPR_NOACCESS,
3959 &spr_read_generic, &spr_write_pir,
3960 0x00000000);
3961 /* XXX : not implemented */
3962 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3963 SPR_NOACCESS, SPR_NOACCESS,
3964 &spr_read_generic, &spr_write_generic,
3965 0x00000000);
3966 /* XXX : not implemented */
3967 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3968 SPR_NOACCESS, SPR_NOACCESS,
3969 &spr_read_generic, &spr_write_generic,
3970 0x00000000);
3971 /* XXX : not implemented */
3972 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3973 SPR_NOACCESS, SPR_NOACCESS,
3974 &spr_read_generic, &spr_write_generic,
3975 0x00000000);
3976 /* XXX : not implemented */
3977 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3978 SPR_NOACCESS, SPR_NOACCESS,
3979 &spr_read_generic, &spr_write_generic,
3980 0x00000000);
3981 /* XXX : not implemented */
3982 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3983 SPR_NOACCESS, SPR_NOACCESS,
3984 &spr_read_generic, &spr_write_generic,
3985 0x00000000);
3986 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3987 SPR_NOACCESS, SPR_NOACCESS,
3988 &spr_read_generic, &spr_write_generic,
3989 0x00000000);
3990 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3991 SPR_NOACCESS, SPR_NOACCESS,
3992 &spr_read_generic, &spr_write_generic,
3993 0x00000000);
3994 /* XXX : not implemented */
3995 spr_register(env, SPR_440_CCR1, "CCR1",
3996 SPR_NOACCESS, SPR_NOACCESS,
3997 &spr_read_generic, &spr_write_generic,
3998 0x00000000);
3999 /* XXX : not implemented */
4000 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4001 &spr_read_generic, &spr_write_generic,
4002 &spr_read_generic, &spr_write_generic,
4003 0x00000000);
4004 /* Memory management */
4005 #if !defined(CONFIG_USER_ONLY)
4006 env->nb_tlb = 64;
4007 env->nb_ways = 1;
4008 env->id_tlbs = 0;
4009 env->tlb_type = TLB_EMB;
4010 #endif
4011 init_excp_BookE(env);
4012 env->dcache_line_size = 32;
4013 env->icache_line_size = 32;
4014 /* XXX: TODO: allocate internal IRQ controller */
4015
4016 SET_FIT_PERIOD(12, 16, 20, 24);
4017 SET_WDT_PERIOD(20, 24, 28, 32);
4018 }
4019
4020 /* Freescale 5xx cores (aka RCPU) */
4021 #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
4022 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4023 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
4024 PPC_MFTB)
4025 #define POWERPC_INSNS2_MPC5xx (PPC_NONE)
4026 #define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
4027 #define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
4028 #define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
4029 #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
4030 #define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
4031 #define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4032 POWERPC_FLAG_BUS_CLK)
4033 #define check_pow_MPC5xx check_pow_none
4034
4035 __attribute__ (( unused ))
4036 static void init_proc_MPC5xx (CPUPPCState *env)
4037 {
4038 /* Time base */
4039 gen_tbl(env);
4040 gen_spr_5xx_8xx(env);
4041 gen_spr_5xx(env);
4042 init_excp_MPC5xx(env);
4043 env->dcache_line_size = 32;
4044 env->icache_line_size = 32;
4045 /* XXX: TODO: allocate internal IRQ controller */
4046 }
4047
4048 /* Freescale 8xx cores (aka PowerQUICC) */
4049 #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
4050 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4051 PPC_CACHE_ICBI | PPC_MFTB)
4052 #define POWERPC_INSNS2_MPC8xx (PPC_NONE)
4053 #define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
4054 #define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
4055 #define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
4056 #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
4057 #define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4058 #define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4059 POWERPC_FLAG_BUS_CLK)
4060 #define check_pow_MPC8xx check_pow_none
4061
4062 __attribute__ (( unused ))
4063 static void init_proc_MPC8xx (CPUPPCState *env)
4064 {
4065 /* Time base */
4066 gen_tbl(env);
4067 gen_spr_5xx_8xx(env);
4068 gen_spr_8xx(env);
4069 init_excp_MPC8xx(env);
4070 env->dcache_line_size = 32;
4071 env->icache_line_size = 32;
4072 /* XXX: TODO: allocate internal IRQ controller */
4073 }
4074
4075 /* Freescale 82xx cores (aka PowerQUICC-II) */
4076 /* PowerPC G2 */
4077 #define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4078 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4079 PPC_FLOAT_STFIWX | \
4080 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4081 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4082 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4083 PPC_SEGMENT | PPC_EXTERN)
4084 #define POWERPC_INSNS2_G2 (PPC_NONE)
4085 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
4086 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
4087 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
4088 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
4089 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
4090 #define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4091 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4092 #define check_pow_G2 check_pow_hid0
4093
4094 static void init_proc_G2 (CPUPPCState *env)
4095 {
4096 gen_spr_ne_601(env);
4097 gen_spr_G2_755(env);
4098 gen_spr_G2(env);
4099 /* Time base */
4100 gen_tbl(env);
4101 /* External access control */
4102 /* XXX : not implemented */
4103 spr_register(env, SPR_EAR, "EAR",
4104 SPR_NOACCESS, SPR_NOACCESS,
4105 &spr_read_generic, &spr_write_generic,
4106 0x00000000);
4107 /* Hardware implementation register */
4108 /* XXX : not implemented */
4109 spr_register(env, SPR_HID0, "HID0",
4110 SPR_NOACCESS, SPR_NOACCESS,
4111 &spr_read_generic, &spr_write_generic,
4112 0x00000000);
4113 /* XXX : not implemented */
4114 spr_register(env, SPR_HID1, "HID1",
4115 SPR_NOACCESS, SPR_NOACCESS,
4116 &spr_read_generic, &spr_write_generic,
4117 0x00000000);
4118 /* XXX : not implemented */
4119 spr_register(env, SPR_HID2, "HID2",
4120 SPR_NOACCESS, SPR_NOACCESS,
4121 &spr_read_generic, &spr_write_generic,
4122 0x00000000);
4123 /* Memory management */
4124 gen_low_BATs(env);
4125 gen_high_BATs(env);
4126 gen_6xx_7xx_soft_tlb(env, 64, 2);
4127 init_excp_G2(env);
4128 env->dcache_line_size = 32;
4129 env->icache_line_size = 32;
4130 /* Allocate hardware IRQ controller */
4131 ppc6xx_irq_init(env);
4132 }
4133
4134 /* PowerPC G2LE */
4135 #define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4136 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4137 PPC_FLOAT_STFIWX | \
4138 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4139 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4140 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4141 PPC_SEGMENT | PPC_EXTERN)
4142 #define POWERPC_INSNS2_G2LE (PPC_NONE)
4143 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
4144 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
4145 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
4146 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
4147 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
4148 #define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4149 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4150 #define check_pow_G2LE check_pow_hid0
4151
4152 static void init_proc_G2LE (CPUPPCState *env)
4153 {
4154 gen_spr_ne_601(env);
4155 gen_spr_G2_755(env);
4156 gen_spr_G2(env);
4157 /* Time base */
4158 gen_tbl(env);
4159 /* External access control */
4160 /* XXX : not implemented */
4161 spr_register(env, SPR_EAR, "EAR",
4162 SPR_NOACCESS, SPR_NOACCESS,
4163 &spr_read_generic, &spr_write_generic,
4164 0x00000000);
4165 /* Hardware implementation register */
4166 /* XXX : not implemented */
4167 spr_register(env, SPR_HID0, "HID0",
4168 SPR_NOACCESS, SPR_NOACCESS,
4169 &spr_read_generic, &spr_write_generic,
4170 0x00000000);
4171 /* XXX : not implemented */
4172 spr_register(env, SPR_HID1, "HID1",
4173 SPR_NOACCESS, SPR_NOACCESS,
4174 &spr_read_generic, &spr_write_generic,
4175 0x00000000);
4176 /* XXX : not implemented */
4177 spr_register(env, SPR_HID2, "HID2",
4178 SPR_NOACCESS, SPR_NOACCESS,
4179 &spr_read_generic, &spr_write_generic,
4180 0x00000000);
4181 /* Memory management */
4182 gen_low_BATs(env);
4183 gen_high_BATs(env);
4184 gen_6xx_7xx_soft_tlb(env, 64, 2);
4185 init_excp_G2(env);
4186 env->dcache_line_size = 32;
4187 env->icache_line_size = 32;
4188 /* Allocate hardware IRQ controller */
4189 ppc6xx_irq_init(env);
4190 }
4191
4192 /* e200 core */
4193 /* XXX: unimplemented instructions:
4194 * dcblc
4195 * dcbtlst
4196 * dcbtstls
4197 * icblc
4198 * icbtls
4199 * tlbivax
4200 * all SPE multiply-accumulate instructions
4201 */
4202 #define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
4203 PPC_SPE | PPC_SPE_SINGLE | \
4204 PPC_WRTEE | PPC_RFDI | \
4205 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4206 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4207 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4208 PPC_BOOKE)
4209 #define POWERPC_INSNS2_e200 (PPC_NONE)
4210 #define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
4211 #define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE206)
4212 #define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
4213 #define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
4214 #define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
4215 #define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4216 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4217 POWERPC_FLAG_BUS_CLK)
4218 #define check_pow_e200 check_pow_hid0
4219
4220 __attribute__ (( unused ))
4221 static void init_proc_e200 (CPUPPCState *env)
4222 {
4223 /* Time base */
4224 gen_tbl(env);
4225 gen_spr_BookE(env, 0x000000070000FFFFULL);
4226 /* XXX : not implemented */
4227 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4228 &spr_read_spefscr, &spr_write_spefscr,
4229 &spr_read_spefscr, &spr_write_spefscr,
4230 0x00000000);
4231 /* Memory management */
4232 gen_spr_BookE206(env, 0x0000005D, NULL);
4233 /* XXX : not implemented */
4234 spr_register(env, SPR_HID0, "HID0",
4235 SPR_NOACCESS, SPR_NOACCESS,
4236 &spr_read_generic, &spr_write_generic,
4237 0x00000000);
4238 /* XXX : not implemented */
4239 spr_register(env, SPR_HID1, "HID1",
4240 SPR_NOACCESS, SPR_NOACCESS,
4241 &spr_read_generic, &spr_write_generic,
4242 0x00000000);
4243 /* XXX : not implemented */
4244 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4245 SPR_NOACCESS, SPR_NOACCESS,
4246 &spr_read_generic, &spr_write_generic,
4247 0x00000000);
4248 /* XXX : not implemented */
4249 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4250 SPR_NOACCESS, SPR_NOACCESS,
4251 &spr_read_generic, &spr_write_generic,
4252 0x00000000);
4253 /* XXX : not implemented */
4254 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4255 SPR_NOACCESS, SPR_NOACCESS,
4256 &spr_read_generic, &spr_write_generic,
4257 0x00000000);
4258 /* XXX : not implemented */
4259 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4260 SPR_NOACCESS, SPR_NOACCESS,
4261 &spr_read_generic, &spr_write_generic,
4262 0x00000000);
4263 /* XXX : not implemented */
4264 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4265 SPR_NOACCESS, SPR_NOACCESS,
4266 &spr_read_generic, &spr_write_generic,
4267 0x00000000);
4268 /* XXX : not implemented */
4269 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4270 SPR_NOACCESS, SPR_NOACCESS,
4271 &spr_read_generic, &spr_write_generic,
4272 0x00000000);
4273 /* XXX : not implemented */
4274 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4275 SPR_NOACCESS, SPR_NOACCESS,
4276 &spr_read_generic, &spr_write_generic,
4277 0x00000000);
4278 /* XXX : not implemented */
4279 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4280 SPR_NOACCESS, SPR_NOACCESS,
4281 &spr_read_generic, &spr_write_generic,
4282 0x00000000);
4283 /* XXX : not implemented */
4284 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4285 SPR_NOACCESS, SPR_NOACCESS,
4286 &spr_read_generic, &spr_write_generic,
4287 0x00000000);
4288 /* XXX : not implemented */
4289 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4290 SPR_NOACCESS, SPR_NOACCESS,
4291 &spr_read_generic, &spr_write_generic,
4292 0x00000000);
4293 /* XXX : not implemented */
4294 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4295 SPR_NOACCESS, SPR_NOACCESS,
4296 &spr_read_generic, &spr_write_generic,
4297 0x00000000);
4298 /* XXX : not implemented */
4299 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4300 SPR_NOACCESS, SPR_NOACCESS,
4301 &spr_read_generic, &spr_write_generic,
4302 0x00000000);
4303 /* XXX : not implemented */
4304 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4305 SPR_NOACCESS, SPR_NOACCESS,
4306 &spr_read_generic, &spr_write_generic,
4307 0x00000000); /* TOFIX */
4308 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4309 SPR_NOACCESS, SPR_NOACCESS,
4310 &spr_read_generic, &spr_write_generic,
4311 0x00000000);
4312 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4313 SPR_NOACCESS, SPR_NOACCESS,
4314 &spr_read_generic, &spr_write_generic,
4315 0x00000000);
4316 #if !defined(CONFIG_USER_ONLY)
4317 env->nb_tlb = 64;
4318 env->nb_ways = 1;
4319 env->id_tlbs = 0;
4320 env->tlb_type = TLB_EMB;
4321 #endif
4322 init_excp_e200(env);
4323 env->dcache_line_size = 32;
4324 env->icache_line_size = 32;
4325 /* XXX: TODO: allocate internal IRQ controller */
4326 }
4327
4328 /* e300 core */
4329 #define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4330 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4331 PPC_FLOAT_STFIWX | \
4332 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4333 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4334 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4335 PPC_SEGMENT | PPC_EXTERN)
4336 #define POWERPC_INSNS2_e300 (PPC_NONE)
4337 #define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4338 #define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4339 #define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4340 #define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4341 #define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4342 #define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4343 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4344 #define check_pow_e300 check_pow_hid0
4345
4346 __attribute__ (( unused ))
4347 static void init_proc_e300 (CPUPPCState *env)
4348 {
4349 gen_spr_ne_601(env);
4350 gen_spr_603(env);
4351 /* Time base */
4352 gen_tbl(env);
4353 /* hardware implementation registers */
4354 /* XXX : not implemented */
4355 spr_register(env, SPR_HID0, "HID0",
4356 SPR_NOACCESS, SPR_NOACCESS,
4357 &spr_read_generic, &spr_write_generic,
4358 0x00000000);
4359 /* XXX : not implemented */
4360 spr_register(env, SPR_HID1, "HID1",
4361 SPR_NOACCESS, SPR_NOACCESS,
4362 &spr_read_generic, &spr_write_generic,
4363 0x00000000);
4364 /* XXX : not implemented */
4365 spr_register(env, SPR_HID2, "HID2",
4366 SPR_NOACCESS, SPR_NOACCESS,
4367 &spr_read_generic, &spr_write_generic,
4368 0x00000000);
4369 /* Memory management */
4370 gen_low_BATs(env);
4371 gen_high_BATs(env);
4372 gen_6xx_7xx_soft_tlb(env, 64, 2);
4373 init_excp_603(env);
4374 env->dcache_line_size = 32;
4375 env->icache_line_size = 32;
4376 /* Allocate hardware IRQ controller */
4377 ppc6xx_irq_init(env);
4378 }
4379
4380 /* e500v1 core */
4381 #define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
4382 PPC_SPE | PPC_SPE_SINGLE | \
4383 PPC_WRTEE | PPC_RFDI | \
4384 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4385 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4386 PPC_MEM_TLBSYNC | PPC_TLBIVAX)
4387 #define POWERPC_INSNS2_e500v1 (PPC2_BOOKE206)
4388 #define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
4389 #define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206)
4390 #define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4391 #define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4392 #define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4393 #define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4394 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4395 POWERPC_FLAG_BUS_CLK)
4396 #define check_pow_e500v1 check_pow_hid0
4397 #define init_proc_e500v1 init_proc_e500v1
4398
4399 /* e500v2 core */
4400 #define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
4401 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
4402 PPC_WRTEE | PPC_RFDI | \
4403 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4404 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4405 PPC_MEM_TLBSYNC | PPC_TLBIVAX)
4406 #define POWERPC_INSNS2_e500v2 (PPC2_BOOKE206)
4407 #define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
4408 #define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206)
4409 #define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4410 #define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4411 #define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4412 #define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4413 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4414 POWERPC_FLAG_BUS_CLK)
4415 #define check_pow_e500v2 check_pow_hid0
4416 #define init_proc_e500v2 init_proc_e500v2
4417
4418 static void init_proc_e500 (CPUPPCState *env, int version)
4419 {
4420 uint32_t tlbncfg[2];
4421 #if !defined(CONFIG_USER_ONLY)
4422 int i;
4423 #endif
4424
4425 /* Time base */
4426 gen_tbl(env);
4427 /*
4428 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4429 * complain when accessing them.
4430 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4431 */
4432 gen_spr_BookE(env, 0x0000000F0000FFFFULL);
4433 /* Processor identification */
4434 spr_register(env, SPR_BOOKE_PIR, "PIR",
4435 SPR_NOACCESS, SPR_NOACCESS,
4436 &spr_read_generic, &spr_write_pir,
4437 0x00000000);
4438 /* XXX : not implemented */
4439 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4440 &spr_read_spefscr, &spr_write_spefscr,
4441 &spr_read_spefscr, &spr_write_spefscr,
4442 0x00000000);
4443 /* Memory management */
4444 #if !defined(CONFIG_USER_ONLY)
4445 env->nb_pids = 3;
4446 env->nb_ways = 2;
4447 env->id_tlbs = 0;
4448 switch (version) {
4449 case 1:
4450 /* e500v1 */
4451 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4452 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4453 break;
4454 case 2:
4455 /* e500v2 */
4456 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4457 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4458 break;
4459 default:
4460 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4461 }
4462 #endif
4463 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4464 /* XXX : not implemented */
4465 spr_register(env, SPR_HID0, "HID0",
4466 SPR_NOACCESS, SPR_NOACCESS,
4467 &spr_read_generic, &spr_write_generic,
4468 0x00000000);
4469 /* XXX : not implemented */
4470 spr_register(env, SPR_HID1, "HID1",
4471 SPR_NOACCESS, SPR_NOACCESS,
4472 &spr_read_generic, &spr_write_generic,
4473 0x00000000);
4474 /* XXX : not implemented */
4475 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4476 SPR_NOACCESS, SPR_NOACCESS,
4477 &spr_read_generic, &spr_write_generic,
4478 0x00000000);
4479 /* XXX : not implemented */
4480 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4481 SPR_NOACCESS, SPR_NOACCESS,
4482 &spr_read_generic, &spr_write_generic,
4483 0x00000000);
4484 /* XXX : not implemented */
4485 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4486 SPR_NOACCESS, SPR_NOACCESS,
4487 &spr_read_generic, &spr_write_generic,
4488 0x00000000);
4489 /* XXX : not implemented */
4490 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4491 SPR_NOACCESS, SPR_NOACCESS,
4492 &spr_read_generic, &spr_write_generic,
4493 0x00000000);
4494 /* XXX : not implemented */
4495 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4496 SPR_NOACCESS, SPR_NOACCESS,
4497 &spr_read_generic, &spr_write_generic,
4498 0x00000000);
4499 /* XXX : not implemented */
4500 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4501 SPR_NOACCESS, SPR_NOACCESS,
4502 &spr_read_generic, &spr_write_generic,
4503 0x00000000);
4504 /* XXX : not implemented */
4505 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4506 SPR_NOACCESS, SPR_NOACCESS,
4507 &spr_read_generic, &spr_write_generic,
4508 0x00000000);
4509 /* XXX : not implemented */
4510 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4511 SPR_NOACCESS, SPR_NOACCESS,
4512 &spr_read_generic, &spr_write_e500_l1csr0,
4513 0x00000000);
4514 /* XXX : not implemented */
4515 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4516 SPR_NOACCESS, SPR_NOACCESS,
4517 &spr_read_generic, &spr_write_generic,
4518 0x00000000);
4519 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4520 SPR_NOACCESS, SPR_NOACCESS,
4521 &spr_read_generic, &spr_write_generic,
4522 0x00000000);
4523 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4524 SPR_NOACCESS, SPR_NOACCESS,
4525 &spr_read_generic, &spr_write_generic,
4526 0x00000000);
4527 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4528 SPR_NOACCESS, SPR_NOACCESS,
4529 &spr_read_generic, &spr_write_booke206_mmucsr0,
4530 0x00000000);
4531
4532 #if !defined(CONFIG_USER_ONLY)
4533 env->nb_tlb = 0;
4534 env->tlb_type = TLB_MAS;
4535 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4536 env->nb_tlb += booke206_tlb_size(env, i);
4537 }
4538 #endif
4539
4540 init_excp_e200(env);
4541 env->dcache_line_size = 32;
4542 env->icache_line_size = 32;
4543 /* Allocate hardware IRQ controller */
4544 ppce500_irq_init(env);
4545 }
4546
4547 static void init_proc_e500v1(CPUPPCState *env)
4548 {
4549 init_proc_e500(env, 1);
4550 }
4551
4552 static void init_proc_e500v2(CPUPPCState *env)
4553 {
4554 init_proc_e500(env, 2);
4555 }
4556
4557 /* Non-embedded PowerPC */
4558
4559 /* POWER : same as 601, without mfmsr, mfsr */
4560 #if defined(TODO)
4561 #define POWERPC_INSNS_POWER (XXX_TODO)
4562 /* POWER RSC (from RAD6000) */
4563 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4564 #endif /* TODO */
4565
4566 /* PowerPC 601 */
4567 #define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4568 PPC_FLOAT | \
4569 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4570 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4571 PPC_SEGMENT | PPC_EXTERN)
4572 #define POWERPC_INSNS2_601 (PPC_NONE)
4573 #define POWERPC_MSRM_601 (0x000000000000FD70ULL)
4574 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4575 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
4576 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4577 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
4578 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4579 #define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4580 #define check_pow_601 check_pow_none
4581
4582 static void init_proc_601 (CPUPPCState *env)
4583 {
4584 gen_spr_ne_601(env);
4585 gen_spr_601(env);
4586 /* Hardware implementation registers */
4587 /* XXX : not implemented */
4588 spr_register(env, SPR_HID0, "HID0",
4589 SPR_NOACCESS, SPR_NOACCESS,
4590 &spr_read_generic, &spr_write_hid0_601,
4591 0x80010080);
4592 /* XXX : not implemented */
4593 spr_register(env, SPR_HID1, "HID1",
4594 SPR_NOACCESS, SPR_NOACCESS,
4595 &spr_read_generic, &spr_write_generic,
4596 0x00000000);
4597 /* XXX : not implemented */
4598 spr_register(env, SPR_601_HID2, "HID2",
4599 SPR_NOACCESS, SPR_NOACCESS,
4600 &spr_read_generic, &spr_write_generic,
4601 0x00000000);
4602 /* XXX : not implemented */
4603 spr_register(env, SPR_601_HID5, "HID5",
4604 SPR_NOACCESS, SPR_NOACCESS,
4605 &spr_read_generic, &spr_write_generic,
4606 0x00000000);
4607 /* Memory management */
4608 init_excp_601(env);
4609 /* XXX: beware that dcache line size is 64
4610 * but dcbz uses 32 bytes "sectors"
4611 * XXX: this breaks clcs instruction !
4612 */
4613 env->dcache_line_size = 32;
4614 env->icache_line_size = 64;
4615 /* Allocate hardware IRQ controller */
4616 ppc6xx_irq_init(env);
4617 }
4618
4619 /* PowerPC 601v */
4620 #define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4621 PPC_FLOAT | \
4622 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4623 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4624 PPC_SEGMENT | PPC_EXTERN)
4625 #define POWERPC_INSNS2_601v (PPC_NONE)
4626 #define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4627 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4628 #define POWERPC_MMU_601v (POWERPC_MMU_601)
4629 #define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4630 #define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4631 #define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4632 #define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4633 #define check_pow_601v check_pow_none
4634
4635 static void init_proc_601v (CPUPPCState *env)
4636 {
4637 init_proc_601(env);
4638 /* XXX : not implemented */
4639 spr_register(env, SPR_601_HID15, "HID15",
4640 SPR_NOACCESS, SPR_NOACCESS,
4641 &spr_read_generic, &spr_write_generic,
4642 0x00000000);
4643 }
4644
4645 /* PowerPC 602 */
4646 #define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4647 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4648 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4649 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4650 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4651 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4652 PPC_SEGMENT | PPC_602_SPEC)
4653 #define POWERPC_INSNS2_602 (PPC_NONE)
4654 #define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4655 /* XXX: 602 MMU is quite specific. Should add a special case */
4656 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4657 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4658 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
4659 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
4660 #define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4661 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4662 #define check_pow_602 check_pow_hid0
4663
4664 static void init_proc_602 (CPUPPCState *env)
4665 {
4666 gen_spr_ne_601(env);
4667 gen_spr_602(env);
4668 /* Time base */
4669 gen_tbl(env);
4670 /* hardware implementation registers */
4671 /* XXX : not implemented */
4672 spr_register(env, SPR_HID0, "HID0",
4673 SPR_NOACCESS, SPR_NOACCESS,
4674 &spr_read_generic, &spr_write_generic,
4675 0x00000000);
4676 /* XXX : not implemented */
4677 spr_register(env, SPR_HID1, "HID1",
4678 SPR_NOACCESS, SPR_NOACCESS,
4679 &spr_read_generic, &spr_write_generic,
4680 0x00000000);
4681 /* Memory management */
4682 gen_low_BATs(env);
4683 gen_6xx_7xx_soft_tlb(env, 64, 2);
4684 init_excp_602(env);
4685 env->dcache_line_size = 32;
4686 env->icache_line_size = 32;
4687 /* Allocate hardware IRQ controller */
4688 ppc6xx_irq_init(env);
4689 }
4690
4691 /* PowerPC 603 */
4692 #define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4693 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4694 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4695 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4696 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4697 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4698 PPC_SEGMENT | PPC_EXTERN)
4699 #define POWERPC_INSNS2_603 (PPC_NONE)
4700 #define POWERPC_MSRM_603 (0x000000000007FF73ULL)
4701 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4702 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4703 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
4704 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
4705 #define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4706 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4707 #define check_pow_603 check_pow_hid0
4708
4709 static void init_proc_603 (CPUPPCState *env)
4710 {
4711 gen_spr_ne_601(env);
4712 gen_spr_603(env);
4713 /* Time base */
4714 gen_tbl(env);
4715 /* hardware implementation registers */
4716 /* XXX : not implemented */
4717 spr_register(env, SPR_HID0, "HID0",
4718 SPR_NOACCESS, SPR_NOACCESS,
4719 &spr_read_generic, &spr_write_generic,
4720 0x00000000);
4721 /* XXX : not implemented */
4722 spr_register(env, SPR_HID1, "HID1",
4723 SPR_NOACCESS, SPR_NOACCESS,
4724 &spr_read_generic, &spr_write_generic,
4725 0x00000000);
4726 /* Memory management */
4727 gen_low_BATs(env);
4728 gen_6xx_7xx_soft_tlb(env, 64, 2);
4729 init_excp_603(env);
4730 env->dcache_line_size = 32;
4731 env->icache_line_size = 32;
4732 /* Allocate hardware IRQ controller */
4733 ppc6xx_irq_init(env);
4734 }
4735
4736 /* PowerPC 603e */
4737 #define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4738 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4739 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4740 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4741 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4742 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4743 PPC_SEGMENT | PPC_EXTERN)
4744 #define POWERPC_INSNS2_603E (PPC_NONE)
4745 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4746 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4747 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4748 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
4749 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
4750 #define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4751 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4752 #define check_pow_603E check_pow_hid0
4753
4754 static void init_proc_603E (CPUPPCState *env)
4755 {
4756 gen_spr_ne_601(env);
4757 gen_spr_603(env);
4758 /* Time base */
4759 gen_tbl(env);
4760 /* hardware implementation registers */
4761 /* XXX : not implemented */
4762 spr_register(env, SPR_HID0, "HID0",
4763 SPR_NOACCESS, SPR_NOACCESS,
4764 &spr_read_generic, &spr_write_generic,
4765 0x00000000);
4766 /* XXX : not implemented */
4767 spr_register(env, SPR_HID1, "HID1",
4768 SPR_NOACCESS, SPR_NOACCESS,
4769 &spr_read_generic, &spr_write_generic,
4770 0x00000000);
4771 /* XXX : not implemented */
4772 spr_register(env, SPR_IABR, "IABR",
4773 SPR_NOACCESS, SPR_NOACCESS,
4774 &spr_read_generic, &spr_write_generic,
4775 0x00000000);
4776 /* Memory management */
4777 gen_low_BATs(env);
4778 gen_6xx_7xx_soft_tlb(env, 64, 2);
4779 init_excp_603(env);
4780 env->dcache_line_size = 32;
4781 env->icache_line_size = 32;
4782 /* Allocate hardware IRQ controller */
4783 ppc6xx_irq_init(env);
4784 }
4785
4786 /* PowerPC 604 */
4787 #define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4788 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4789 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4790 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4791 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4792 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4793 PPC_SEGMENT | PPC_EXTERN)
4794 #define POWERPC_INSNS2_604 (PPC_NONE)
4795 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4796 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
4797 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4798 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
4799 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
4800 #define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4801 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4802 #define check_pow_604 check_pow_nocheck
4803
4804 static void init_proc_604 (CPUPPCState *env)
4805 {
4806 gen_spr_ne_601(env);
4807 gen_spr_604(env);
4808 /* Time base */
4809 gen_tbl(env);
4810 /* Hardware implementation registers */
4811 /* XXX : not implemented */
4812 spr_register(env, SPR_HID0, "HID0",
4813 SPR_NOACCESS, SPR_NOACCESS,
4814 &spr_read_generic, &spr_write_generic,
4815 0x00000000);
4816 /* Memory management */
4817 gen_low_BATs(env);
4818 init_excp_604(env);
4819 env->dcache_line_size = 32;
4820 env->icache_line_size = 32;
4821 /* Allocate hardware IRQ controller */
4822 ppc6xx_irq_init(env);
4823 }
4824
4825 /* PowerPC 604E */
4826 #define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4827 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4828 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4829 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4830 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4831 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4832 PPC_SEGMENT | PPC_EXTERN)
4833 #define POWERPC_INSNS2_604E (PPC_NONE)
4834 #define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4835 #define POWERPC_MMU_604E (POWERPC_MMU_32B)
4836 #define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4837 #define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4838 #define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4839 #define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4840 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4841 #define check_pow_604E check_pow_nocheck
4842
4843 static void init_proc_604E (CPUPPCState *env)
4844 {
4845 gen_spr_ne_601(env);
4846 gen_spr_604(env);
4847 /* XXX : not implemented */
4848 spr_register(env, SPR_MMCR1, "MMCR1",
4849 SPR_NOACCESS, SPR_NOACCESS,
4850 &spr_read_generic, &spr_write_generic,
4851 0x00000000);
4852 /* XXX : not implemented */
4853 spr_register(env, SPR_PMC3, "PMC3",
4854 SPR_NOACCESS, SPR_NOACCESS,
4855 &spr_read_generic, &spr_write_generic,
4856 0x00000000);
4857 /* XXX : not implemented */
4858 spr_register(env, SPR_PMC4, "PMC4",
4859 SPR_NOACCESS, SPR_NOACCESS,
4860 &spr_read_generic, &spr_write_generic,
4861 0x00000000);
4862 /* Time base */
4863 gen_tbl(env);
4864 /* Hardware implementation registers */
4865 /* XXX : not implemented */
4866 spr_register(env, SPR_HID0, "HID0",
4867 SPR_NOACCESS, SPR_NOACCESS,
4868 &spr_read_generic, &spr_write_generic,
4869 0x00000000);
4870 /* XXX : not implemented */
4871 spr_register(env, SPR_HID1, "HID1",
4872 SPR_NOACCESS, SPR_NOACCESS,
4873 &spr_read_generic, &spr_write_generic,
4874 0x00000000);
4875 /* Memory management */
4876 gen_low_BATs(env);
4877 init_excp_604(env);
4878 env->dcache_line_size = 32;
4879 env->icache_line_size = 32;
4880 /* Allocate hardware IRQ controller */
4881 ppc6xx_irq_init(env);
4882 }
4883
4884 /* PowerPC 740 */
4885 #define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4886 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4887 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4888 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4889 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4890 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4891 PPC_SEGMENT | PPC_EXTERN)
4892 #define POWERPC_INSNS2_740 (PPC_NONE)
4893 #define POWERPC_MSRM_740 (0x000000000005FF77ULL)
4894 #define POWERPC_MMU_740 (POWERPC_MMU_32B)
4895 #define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
4896 #define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
4897 #define POWERPC_BFDM_740 (bfd_mach_ppc_750)
4898 #define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4899 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4900 #define check_pow_740 check_pow_hid0
4901
4902 static void init_proc_740 (CPUPPCState *env)
4903 {
4904 gen_spr_ne_601(env);
4905 gen_spr_7xx(env);
4906 /* Time base */
4907 gen_tbl(env);
4908 /* Thermal management */
4909 gen_spr_thrm(env);
4910 /* Hardware implementation registers */
4911 /* XXX : not implemented */
4912 spr_register(env, SPR_HID0, "HID0",
4913 SPR_NOACCESS, SPR_NOACCESS,
4914 &spr_read_generic, &spr_write_generic,
4915 0x00000000);
4916 /* XXX : not implemented */
4917 spr_register(env, SPR_HID1, "HID1",
4918 SPR_NOACCESS, SPR_NOACCESS,
4919 &spr_read_generic, &spr_write_generic,
4920 0x00000000);
4921 /* Memory management */
4922 gen_low_BATs(env);
4923 init_excp_7x0(env);
4924 env->dcache_line_size = 32;
4925 env->icache_line_size = 32;
4926 /* Allocate hardware IRQ controller */
4927 ppc6xx_irq_init(env);
4928 }
4929
4930 /* PowerPC 750 */
4931 #define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4932 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4933 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4934 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4935 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4936 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4937 PPC_SEGMENT | PPC_EXTERN)
4938 #define POWERPC_INSNS2_750 (PPC_NONE)
4939 #define POWERPC_MSRM_750 (0x000000000005FF77ULL)
4940 #define POWERPC_MMU_750 (POWERPC_MMU_32B)
4941 #define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
4942 #define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
4943 #define POWERPC_BFDM_750 (bfd_mach_ppc_750)
4944 #define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4945 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4946 #define check_pow_750 check_pow_hid0
4947
4948 static void init_proc_750 (CPUPPCState *env)
4949 {
4950 gen_spr_ne_601(env);
4951 gen_spr_7xx(env);
4952 /* XXX : not implemented */
4953 spr_register(env, SPR_L2CR, "L2CR",
4954 SPR_NOACCESS, SPR_NOACCESS,
4955 &spr_read_generic, &spr_write_generic,
4956 0x00000000);
4957 /* Time base */
4958 gen_tbl(env);
4959 /* Thermal management */
4960 gen_spr_thrm(env);
4961 /* Hardware implementation registers */
4962 /* XXX : not implemented */
4963 spr_register(env, SPR_HID0, "HID0",
4964 SPR_NOACCESS, SPR_NOACCESS,
4965 &spr_read_generic, &spr_write_generic,
4966 0x00000000);
4967 /* XXX : not implemented */
4968 spr_register(env, SPR_HID1, "HID1",
4969 SPR_NOACCESS, SPR_NOACCESS,
4970 &spr_read_generic, &spr_write_generic,
4971 0x00000000);
4972 /* Memory management */
4973 gen_low_BATs(env);
4974 /* XXX: high BATs are also present but are known to be bugged on
4975 * die version 1.x
4976 */
4977 init_excp_7x0(env);
4978 env->dcache_line_size = 32;
4979 env->icache_line_size = 32;
4980 /* Allocate hardware IRQ controller */
4981 ppc6xx_irq_init(env);
4982 }
4983
4984 /* PowerPC 750 CL */
4985 /* XXX: not implemented:
4986 * cache lock instructions:
4987 * dcbz_l
4988 * floating point paired instructions
4989 * psq_lux
4990 * psq_lx
4991 * psq_stux
4992 * psq_stx
4993 * ps_abs
4994 * ps_add
4995 * ps_cmpo0
4996 * ps_cmpo1
4997 * ps_cmpu0
4998 * ps_cmpu1
4999 * ps_div
5000 * ps_madd
5001 * ps_madds0
5002 * ps_madds1
5003 * ps_merge00
5004 * ps_merge01
5005 * ps_merge10
5006 * ps_merge11
5007 * ps_mr
5008 * ps_msub
5009 * ps_mul
5010 * ps_muls0
5011 * ps_muls1
5012 * ps_nabs
5013 * ps_neg
5014 * ps_nmadd
5015 * ps_nmsub
5016 * ps_res
5017 * ps_rsqrte
5018 * ps_sel
5019 * ps_sub
5020 * ps_sum0
5021 * ps_sum1
5022 */
5023 #define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5024 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5025 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5026 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5027 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5028 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5029 PPC_SEGMENT | PPC_EXTERN)
5030 #define POWERPC_INSNS2_750cl (PPC_NONE)
5031 #define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
5032 #define POWERPC_MMU_750cl (POWERPC_MMU_32B)
5033 #define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
5034 #define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
5035 #define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
5036 #define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5037 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5038 #define check_pow_750cl check_pow_hid0
5039
5040 static void init_proc_750cl (CPUPPCState *env)
5041 {
5042 gen_spr_ne_601(env);
5043 gen_spr_7xx(env);
5044 /* XXX : not implemented */
5045 spr_register(env, SPR_L2CR, "L2CR",
5046 SPR_NOACCESS, SPR_NOACCESS,
5047 &spr_read_generic, &spr_write_generic,
5048 0x00000000);
5049 /* Time base */
5050 gen_tbl(env);
5051 /* Thermal management */
5052 /* Those registers are fake on 750CL */
5053 spr_register(env, SPR_THRM1, "THRM1",
5054 SPR_NOACCESS, SPR_NOACCESS,
5055 &spr_read_generic, &spr_write_generic,
5056 0x00000000);
5057 spr_register(env, SPR_THRM2, "THRM2",
5058 SPR_NOACCESS, SPR_NOACCESS,
5059 &spr_read_generic, &spr_write_generic,
5060 0x00000000);
5061 spr_register(env, SPR_THRM3, "THRM3",
5062 SPR_NOACCESS, SPR_NOACCESS,
5063 &spr_read_generic, &spr_write_generic,
5064 0x00000000);
5065 /* XXX: not implemented */
5066 spr_register(env, SPR_750_TDCL, "TDCL",
5067 SPR_NOACCESS, SPR_NOACCESS,
5068 &spr_read_generic, &spr_write_generic,
5069 0x00000000);
5070 spr_register(env, SPR_750_TDCH, "TDCH",
5071 SPR_NOACCESS, SPR_NOACCESS,
5072 &spr_read_generic, &spr_write_generic,
5073 0x00000000);
5074 /* DMA */
5075 /* XXX : not implemented */
5076 spr_register(env, SPR_750_WPAR, "WPAR",
5077 SPR_NOACCESS, SPR_NOACCESS,
5078 &spr_read_generic, &spr_write_generic,
5079 0x00000000);
5080 spr_register(env, SPR_750_DMAL, "DMAL",
5081 SPR_NOACCESS, SPR_NOACCESS,
5082 &spr_read_generic, &spr_write_generic,
5083 0x00000000);
5084 spr_register(env, SPR_750_DMAU, "DMAU",
5085 SPR_NOACCESS, SPR_NOACCESS,
5086 &spr_read_generic, &spr_write_generic,
5087 0x00000000);
5088 /* Hardware implementation registers */
5089 /* XXX : not implemented */
5090 spr_register(env, SPR_HID0, "HID0",
5091 SPR_NOACCESS, SPR_NOACCESS,
5092 &spr_read_generic, &spr_write_generic,
5093 0x00000000);
5094 /* XXX : not implemented */
5095 spr_register(env, SPR_HID1, "HID1",
5096 SPR_NOACCESS, SPR_NOACCESS,
5097 &spr_read_generic, &spr_write_generic,
5098 0x00000000);
5099 /* XXX : not implemented */
5100 spr_register(env, SPR_750CL_HID2, "HID2",
5101 SPR_NOACCESS, SPR_NOACCESS,
5102 &spr_read_generic, &spr_write_generic,
5103 0x00000000);
5104 /* XXX : not implemented */
5105 spr_register(env, SPR_750CL_HID4, "HID4",
5106 SPR_NOACCESS, SPR_NOACCESS,
5107 &spr_read_generic, &spr_write_generic,
5108 0x00000000);
5109 /* Quantization registers */
5110 /* XXX : not implemented */
5111 spr_register(env, SPR_750_GQR0, "GQR0",
5112 SPR_NOACCESS, SPR_NOACCESS,
5113 &spr_read_generic, &spr_write_generic,
5114 0x00000000);
5115 /* XXX : not implemented */
5116 spr_register(env, SPR_750_GQR1, "GQR1",
5117 SPR_NOACCESS, SPR_NOACCESS,
5118 &spr_read_generic, &spr_write_generic,
5119 0x00000000);
5120 /* XXX : not implemented */
5121 spr_register(env, SPR_750_GQR2, "GQR2",
5122 SPR_NOACCESS, SPR_NOACCESS,
5123 &spr_read_generic, &spr_write_generic,
5124 0x00000000);
5125 /* XXX : not implemented */
5126 spr_register(env, SPR_750_GQR3, "GQR3",
5127 SPR_NOACCESS, SPR_NOACCESS,
5128 &spr_read_generic, &spr_write_generic,
5129 0x00000000);
5130 /* XXX : not implemented */
5131 spr_register(env, SPR_750_GQR4, "GQR4",
5132 SPR_NOACCESS, SPR_NOACCESS,
5133 &spr_read_generic, &spr_write_generic,
5134 0x00000000);
5135 /* XXX : not implemented */
5136 spr_register(env, SPR_750_GQR5, "GQR5",
5137 SPR_NOACCESS, SPR_NOACCESS,
5138 &spr_read_generic, &spr_write_generic,
5139 0x00000000);
5140 /* XXX : not implemented */
5141 spr_register(env, SPR_750_GQR6, "GQR6",
5142 SPR_NOACCESS, SPR_NOACCESS,
5143 &spr_read_generic, &spr_write_generic,
5144 0x00000000);
5145 /* XXX : not implemented */
5146 spr_register(env, SPR_750_GQR7, "GQR7",
5147 SPR_NOACCESS, SPR_NOACCESS,
5148 &spr_read_generic, &spr_write_generic,
5149 0x00000000);
5150 /* Memory management */
5151 gen_low_BATs(env);
5152 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5153 gen_high_BATs(env);
5154 init_excp_750cl(env);
5155 env->dcache_line_size = 32;
5156 env->icache_line_size = 32;
5157 /* Allocate hardware IRQ controller */
5158 ppc6xx_irq_init(env);
5159 }
5160
5161 /* PowerPC 750CX */
5162 #define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5163 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5164 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5165 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5166 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5167 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5168 PPC_SEGMENT | PPC_EXTERN)
5169 #define POWERPC_INSNS2_750cx (PPC_NONE)
5170 #define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
5171 #define POWERPC_MMU_750cx (POWERPC_MMU_32B)
5172 #define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
5173 #define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
5174 #define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
5175 #define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5176 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5177 #define check_pow_750cx check_pow_hid0
5178
5179 static void init_proc_750cx (CPUPPCState *env)
5180 {
5181 gen_spr_ne_601(env);
5182 gen_spr_7xx(env);
5183 /* XXX : not implemented */
5184 spr_register(env, SPR_L2CR, "L2CR",
5185 SPR_NOACCESS, SPR_NOACCESS,
5186 &spr_read_generic, &spr_write_generic,
5187 0x00000000);
5188 /* Time base */
5189 gen_tbl(env);
5190 /* Thermal management */
5191 gen_spr_thrm(env);
5192 /* This register is not implemented but is present for compatibility */
5193 spr_register(env, SPR_SDA, "SDA",
5194 SPR_NOACCESS, SPR_NOACCESS,
5195 &spr_read_generic, &spr_write_generic,
5196 0x00000000);
5197 /* Hardware implementation registers */
5198 /* XXX : not implemented */
5199 spr_register(env, SPR_HID0, "HID0",
5200 SPR_NOACCESS, SPR_NOACCESS,
5201 &spr_read_generic, &spr_write_generic,
5202 0x00000000);
5203 /* XXX : not implemented */
5204 spr_register(env, SPR_HID1, "HID1",
5205 SPR_NOACCESS, SPR_NOACCESS,
5206 &spr_read_generic, &spr_write_generic,
5207 0x00000000);
5208 /* Memory management */
5209 gen_low_BATs(env);
5210 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5211 gen_high_BATs(env);
5212 init_excp_750cx(env);
5213 env->dcache_line_size = 32;
5214 env->icache_line_size = 32;
5215 /* Allocate hardware IRQ controller */
5216 ppc6xx_irq_init(env);
5217 }
5218
5219 /* PowerPC 750FX */
5220 #define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5221 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5222 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5223 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5224 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5225 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5226 PPC_SEGMENT | PPC_EXTERN)
5227 #define POWERPC_INSNS2_750fx (PPC_NONE)
5228 #define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
5229 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
5230 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
5231 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
5232 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
5233 #define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5234 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5235 #define check_pow_750fx check_pow_hid0
5236
5237 static void init_proc_750fx (CPUPPCState *env)
5238 {
5239 gen_spr_ne_601(env);
5240 gen_spr_7xx(env);
5241 /* XXX : not implemented */
5242 spr_register(env, SPR_L2CR, "L2CR",
5243 SPR_NOACCESS, SPR_NOACCESS,
5244 &spr_read_generic, &spr_write_generic,
5245 0x00000000);
5246 /* Time base */
5247 gen_tbl(env);
5248 /* Thermal management */
5249 gen_spr_thrm(env);
5250 /* XXX : not implemented */
5251 spr_register(env, SPR_750_THRM4, "THRM4",
5252 SPR_NOACCESS, SPR_NOACCESS,
5253 &spr_read_generic, &spr_write_generic,
5254 0x00000000);
5255 /* Hardware implementation registers */
5256 /* XXX : not implemented */
5257 spr_register(env, SPR_HID0, "HID0",
5258 SPR_NOACCESS, SPR_NOACCESS,
5259 &spr_read_generic, &spr_write_generic,
5260 0x00000000);
5261 /* XXX : not implemented */
5262 spr_register(env, SPR_HID1, "HID1",
5263 SPR_NOACCESS, SPR_NOACCESS,
5264 &spr_read_generic, &spr_write_generic,
5265 0x00000000);
5266 /* XXX : not implemented */
5267 spr_register(env, SPR_750FX_HID2, "HID2",
5268 SPR_NOACCESS, SPR_NOACCESS,
5269 &spr_read_generic, &spr_write_generic,
5270 0x00000000);
5271 /* Memory management */
5272 gen_low_BATs(env);
5273 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5274 gen_high_BATs(env);
5275 init_excp_7x0(env);
5276 env->dcache_line_size = 32;
5277 env->icache_line_size = 32;
5278 /* Allocate hardware IRQ controller */
5279 ppc6xx_irq_init(env);
5280 }
5281
5282 /* PowerPC 750GX */
5283 #define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5284 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5285 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5286 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5287 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5288 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5289 PPC_SEGMENT | PPC_EXTERN)
5290 #define POWERPC_INSNS2_750gx (PPC_NONE)
5291 #define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5292 #define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5293 #define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5294 #define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5295 #define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5296 #define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5297 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5298 #define check_pow_750gx check_pow_hid0
5299
5300 static void init_proc_750gx (CPUPPCState *env)
5301 {
5302 gen_spr_ne_601(env);
5303 gen_spr_7xx(env);
5304 /* XXX : not implemented (XXX: different from 750fx) */
5305 spr_register(env, SPR_L2CR, "L2CR",
5306 SPR_NOACCESS, SPR_NOACCESS,
5307 &spr_read_generic, &spr_write_generic,
5308 0x00000000);
5309 /* Time base */
5310 gen_tbl(env);
5311 /* Thermal management */
5312 gen_spr_thrm(env);
5313 /* XXX : not implemented */
5314 spr_register(env, SPR_750_THRM4, "THRM4",
5315 SPR_NOACCESS, SPR_NOACCESS,
5316 &spr_read_generic, &spr_write_generic,
5317 0x00000000);
5318 /* Hardware implementation registers */
5319 /* XXX : not implemented (XXX: different from 750fx) */
5320 spr_register(env, SPR_HID0, "HID0",
5321 SPR_NOACCESS, SPR_NOACCESS,
5322 &spr_read_generic, &spr_write_generic,
5323 0x00000000);
5324 /* XXX : not implemented */
5325 spr_register(env, SPR_HID1, "HID1",
5326 SPR_NOACCESS, SPR_NOACCESS,
5327 &spr_read_generic, &spr_write_generic,
5328 0x00000000);
5329 /* XXX : not implemented (XXX: different from 750fx) */
5330 spr_register(env, SPR_750FX_HID2, "HID2",
5331 SPR_NOACCESS, SPR_NOACCESS,
5332 &spr_read_generic, &spr_write_generic,
5333 0x00000000);
5334 /* Memory management */
5335 gen_low_BATs(env);
5336 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5337 gen_high_BATs(env);
5338 init_excp_7x0(env);
5339 env->dcache_line_size = 32;
5340 env->icache_line_size = 32;
5341 /* Allocate hardware IRQ controller */
5342 ppc6xx_irq_init(env);
5343 }
5344
5345 /* PowerPC 745 */
5346 #define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5347 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5348 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5349 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5350 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5351 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5352 PPC_SEGMENT | PPC_EXTERN)
5353 #define POWERPC_INSNS2_745 (PPC_NONE)
5354 #define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5355 #define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5356 #define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5357 #define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5358 #define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5359 #define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5360 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5361 #define check_pow_745 check_pow_hid0
5362
5363 static void init_proc_745 (CPUPPCState *env)
5364 {
5365 gen_spr_ne_601(env);
5366 gen_spr_7xx(env);
5367 gen_spr_G2_755(env);
5368 /* Time base */
5369 gen_tbl(env);
5370 /* Thermal management */
5371 gen_spr_thrm(env);
5372 /* Hardware implementation registers */
5373 /* XXX : not implemented */
5374 spr_register(env, SPR_HID0, "HID0",
5375 SPR_NOACCESS, SPR_NOACCESS,
5376 &spr_read_generic, &spr_write_generic,
5377 0x00000000);
5378 /* XXX : not implemented */
5379 spr_register(env, SPR_HID1, "HID1",
5380 SPR_NOACCESS, SPR_NOACCESS,
5381 &spr_read_generic, &spr_write_generic,
5382 0x00000000);
5383 /* XXX : not implemented */
5384 spr_register(env, SPR_HID2, "HID2",
5385 SPR_NOACCESS, SPR_NOACCESS,
5386 &spr_read_generic, &spr_write_generic,
5387 0x00000000);
5388 /* Memory management */
5389 gen_low_BATs(env);
5390 gen_high_BATs(env);
5391 gen_6xx_7xx_soft_tlb(env, 64, 2);
5392 init_excp_7x5(env);
5393 env->dcache_line_size = 32;
5394 env->icache_line_size = 32;
5395 /* Allocate hardware IRQ controller */
5396 ppc6xx_irq_init(env);
5397 }
5398
5399 /* PowerPC 755 */
5400 #define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5401 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5402 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5403 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5404 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5405 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5406 PPC_SEGMENT | PPC_EXTERN)
5407 #define POWERPC_INSNS2_755 (PPC_NONE)
5408 #define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5409 #define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5410 #define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5411 #define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5412 #define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5413 #define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5414 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5415 #define check_pow_755 check_pow_hid0
5416
5417 static void init_proc_755 (CPUPPCState *env)
5418 {
5419 gen_spr_ne_601(env);
5420 gen_spr_7xx(env);
5421 gen_spr_G2_755(env);
5422 /* Time base */
5423 gen_tbl(env);
5424 /* L2 cache control */
5425 /* XXX : not implemented */
5426 spr_register(env, SPR_L2CR, "L2CR",
5427 SPR_NOACCESS, SPR_NOACCESS,
5428 &spr_read_generic, &spr_write_generic,
5429 0x00000000);
5430 /* XXX : not implemented */
5431 spr_register(env, SPR_L2PMCR, "L2PMCR",
5432 SPR_NOACCESS, SPR_NOACCESS,
5433 &spr_read_generic, &spr_write_generic,
5434 0x00000000);
5435 /* Thermal management */
5436 gen_spr_thrm(env);
5437 /* Hardware implementation registers */
5438 /* XXX : not implemented */
5439 spr_register(env, SPR_HID0, "HID0",
5440 SPR_NOACCESS, SPR_NOACCESS,
5441 &spr_read_generic, &spr_write_generic,
5442 0x00000000);
5443 /* XXX : not implemented */
5444 spr_register(env, SPR_HID1, "HID1",
5445 SPR_NOACCESS, SPR_NOACCESS,
5446 &spr_read_generic, &spr_write_generic,
5447 0x00000000);
5448 /* XXX : not implemented */
5449 spr_register(env, SPR_HID2, "HID2",
5450 SPR_NOACCESS, SPR_NOACCESS,
5451 &spr_read_generic, &spr_write_generic,
5452 0x00000000);
5453 /* Memory management */
5454 gen_low_BATs(env);
5455 gen_high_BATs(env);
5456 gen_6xx_7xx_soft_tlb(env, 64, 2);
5457 init_excp_7x5(env);
5458 env->dcache_line_size = 32;
5459 env->icache_line_size = 32;
5460 /* Allocate hardware IRQ controller */
5461 ppc6xx_irq_init(env);
5462 }
5463
5464 /* PowerPC 7400 (aka G4) */
5465 #define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5466 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5467 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5468 PPC_FLOAT_STFIWX | \
5469 PPC_CACHE | PPC_CACHE_ICBI | \
5470 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5471 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5472 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5473 PPC_MEM_TLBIA | \
5474 PPC_SEGMENT | PPC_EXTERN | \
5475 PPC_ALTIVEC)
5476 #define POWERPC_INSNS2_7400 (PPC_NONE)
5477 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5478 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5479 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5480 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
5481 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
5482 #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5483 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5484 POWERPC_FLAG_BUS_CLK)
5485 #define check_pow_7400 check_pow_hid0
5486
5487 static void init_proc_7400 (CPUPPCState *env)
5488 {
5489 gen_spr_ne_601(env);
5490 gen_spr_7xx(env);
5491 /* Time base */
5492 gen_tbl(env);
5493 /* 74xx specific SPR */
5494 gen_spr_74xx(env);
5495 /* XXX : not implemented */
5496 spr_register(env, SPR_UBAMR, "UBAMR",
5497 &spr_read_ureg, SPR_NOACCESS,
5498 &spr_read_ureg, SPR_NOACCESS,
5499 0x00000000);
5500 /* XXX: this seems not implemented on all revisions. */
5501 /* XXX : not implemented */
5502 spr_register(env, SPR_MSSCR1, "MSSCR1",
5503 SPR_NOACCESS, SPR_NOACCESS,
5504 &spr_read_generic, &spr_write_generic,
5505 0x00000000);
5506 /* Thermal management */
5507 gen_spr_thrm(env);
5508 /* Memory management */
5509 gen_low_BATs(env);
5510 init_excp_7400(env);
5511 env->dcache_line_size = 32;
5512 env->icache_line_size = 32;
5513 /* Allocate hardware IRQ controller */
5514 ppc6xx_irq_init(env);
5515 }
5516
5517 /* PowerPC 7410 (aka G4) */
5518 #define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5519 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5520 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5521 PPC_FLOAT_STFIWX | \
5522 PPC_CACHE | PPC_CACHE_ICBI | \
5523 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5524 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5525 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5526 PPC_MEM_TLBIA | \
5527 PPC_SEGMENT | PPC_EXTERN | \
5528 PPC_ALTIVEC)
5529 #define POWERPC_INSNS2_7410 (PPC_NONE)
5530 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5531 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5532 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5533 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
5534 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
5535 #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5536 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5537 POWERPC_FLAG_BUS_CLK)
5538 #define check_pow_7410 check_pow_hid0
5539
5540 static void init_proc_7410 (CPUPPCState *env)
5541 {
5542 gen_spr_ne_601(env);
5543 gen_spr_7xx(env);
5544 /* Time base */
5545 gen_tbl(env);
5546 /* 74xx specific SPR */
5547 gen_spr_74xx(env);
5548 /* XXX : not implemented */
5549 spr_register(env, SPR_UBAMR, "UBAMR",
5550 &spr_read_ureg, SPR_NOACCESS,
5551 &spr_read_ureg, SPR_NOACCESS,
5552 0x00000000);
5553 /* Thermal management */
5554 gen_spr_thrm(env);
5555 /* L2PMCR */
5556 /* XXX : not implemented */
5557 spr_register(env, SPR_L2PMCR, "L2PMCR",
5558 SPR_NOACCESS, SPR_NOACCESS,
5559 &spr_read_generic, &spr_write_generic,
5560 0x00000000);
5561 /* LDSTDB */
5562 /* XXX : not implemented */
5563 spr_register(env, SPR_LDSTDB, "LDSTDB",
5564 SPR_NOACCESS, SPR_NOACCESS,
5565 &spr_read_generic, &spr_write_generic,
5566 0x00000000);
5567 /* Memory management */
5568 gen_low_BATs(env);
5569 init_excp_7400(env);
5570 env->dcache_line_size = 32;
5571 env->icache_line_size = 32;
5572 /* Allocate hardware IRQ controller */
5573 ppc6xx_irq_init(env);
5574 }
5575
5576 /* PowerPC 7440 (aka G4) */
5577 #define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5578 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5579 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5580 PPC_FLOAT_STFIWX | \
5581 PPC_CACHE | PPC_CACHE_ICBI | \
5582 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5583 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5584 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5585 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5586 PPC_SEGMENT | PPC_EXTERN | \
5587 PPC_ALTIVEC)
5588 #define POWERPC_INSNS2_7440 (PPC_NONE)
5589 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5590 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5591 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5592 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
5593 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
5594 #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5595 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5596 POWERPC_FLAG_BUS_CLK)
5597 #define check_pow_7440 check_pow_hid0_74xx
5598
5599 __attribute__ (( unused ))
5600 static void init_proc_7440 (CPUPPCState *env)
5601 {
5602 gen_spr_ne_601(env);
5603 gen_spr_7xx(env);
5604 /* Time base */
5605 gen_tbl(env);
5606 /* 74xx specific SPR */
5607 gen_spr_74xx(env);
5608 /* XXX : not implemented */
5609 spr_register(env, SPR_UBAMR, "UBAMR",
5610 &spr_read_ureg, SPR_NOACCESS,
5611 &spr_read_ureg, SPR_NOACCESS,
5612 0x00000000);
5613 /* LDSTCR */
5614 /* XXX : not implemented */
5615 spr_register(env, SPR_LDSTCR, "LDSTCR",
5616 SPR_NOACCESS, SPR_NOACCESS,
5617 &spr_read_generic, &spr_write_generic,
5618 0x00000000);
5619 /* ICTRL */
5620 /* XXX : not implemented */
5621 spr_register(env, SPR_ICTRL, "ICTRL",
5622 SPR_NOACCESS, SPR_NOACCESS,
5623 &spr_read_generic, &spr_write_generic,
5624 0x00000000);
5625 /* MSSSR0 */
5626 /* XXX : not implemented */
5627 spr_register(env, SPR_MSSSR0, "MSSSR0",
5628 SPR_NOACCESS, SPR_NOACCESS,
5629 &spr_read_generic, &spr_write_generic,
5630 0x00000000);
5631 /* PMC */
5632 /* XXX : not implemented */
5633 spr_register(env, SPR_PMC5, "PMC5",
5634 SPR_NOACCESS, SPR_NOACCESS,
5635 &spr_read_generic, &spr_write_generic,
5636 0x00000000);
5637 /* XXX : not implemented */
5638 spr_register(env, SPR_UPMC5, "UPMC5",
5639 &spr_read_ureg, SPR_NOACCESS,
5640 &spr_read_ureg, SPR_NOACCESS,
5641 0x00000000);
5642 /* XXX : not implemented */
5643 spr_register(env, SPR_PMC6, "PMC6",
5644 SPR_NOACCESS, SPR_NOACCESS,
5645 &spr_read_generic, &spr_write_generic,
5646 0x00000000);
5647 /* XXX : not implemented */
5648 spr_register(env, SPR_UPMC6, "UPMC6",
5649 &spr_read_ureg, SPR_NOACCESS,
5650 &spr_read_ureg, SPR_NOACCESS,
5651 0x00000000);
5652 /* Memory management */
5653 gen_low_BATs(env);
5654 gen_74xx_soft_tlb(env, 128, 2);
5655 init_excp_7450(env);
5656 env->dcache_line_size = 32;
5657 env->icache_line_size = 32;
5658 /* Allocate hardware IRQ controller */
5659 ppc6xx_irq_init(env);
5660 }
5661
5662 /* PowerPC 7450 (aka G4) */
5663 #define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5664 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5665 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5666 PPC_FLOAT_STFIWX | \
5667 PPC_CACHE | PPC_CACHE_ICBI | \
5668 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5669 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5670 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5671 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5672 PPC_SEGMENT | PPC_EXTERN | \
5673 PPC_ALTIVEC)
5674 #define POWERPC_INSNS2_7450 (PPC_NONE)
5675 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5676 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5677 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5678 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
5679 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
5680 #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5681 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5682 POWERPC_FLAG_BUS_CLK)
5683 #define check_pow_7450 check_pow_hid0_74xx
5684
5685 __attribute__ (( unused ))
5686 static void init_proc_7450 (CPUPPCState *env)
5687 {
5688 gen_spr_ne_601(env);
5689 gen_spr_7xx(env);
5690 /* Time base */
5691 gen_tbl(env);
5692 /* 74xx specific SPR */
5693 gen_spr_74xx(env);
5694 /* Level 3 cache control */
5695 gen_l3_ctrl(env);
5696 /* L3ITCR1 */
5697 /* XXX : not implemented */
5698 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5699 SPR_NOACCESS, SPR_NOACCESS,
5700 &spr_read_generic, &spr_write_generic,
5701 0x00000000);
5702 /* L3ITCR2 */
5703 /* XXX : not implemented */
5704 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5705 SPR_NOACCESS, SPR_NOACCESS,
5706 &spr_read_generic, &spr_write_generic,
5707 0x00000000);
5708 /* L3ITCR3 */
5709 /* XXX : not implemented */
5710 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5711 SPR_NOACCESS, SPR_NOACCESS,
5712 &spr_read_generic, &spr_write_generic,
5713 0x00000000);
5714 /* L3OHCR */
5715 /* XXX : not implemented */
5716 spr_register(env, SPR_L3OHCR, "L3OHCR",
5717 SPR_NOACCESS, SPR_NOACCESS,
5718 &spr_read_generic, &spr_write_generic,
5719 0x00000000);
5720 /* XXX : not implemented */
5721 spr_register(env, SPR_UBAMR, "UBAMR",
5722 &spr_read_ureg, SPR_NOACCESS,
5723 &spr_read_ureg, SPR_NOACCESS,
5724 0x00000000);
5725 /* LDSTCR */
5726 /* XXX : not implemented */
5727 spr_register(env, SPR_LDSTCR, "LDSTCR",
5728 SPR_NOACCESS, SPR_NOACCESS,
5729 &spr_read_generic, &spr_write_generic,
5730 0x00000000);
5731 /* ICTRL */
5732 /* XXX : not implemented */
5733 spr_register(env, SPR_ICTRL, "ICTRL",
5734 SPR_NOACCESS, SPR_NOACCESS,
5735 &spr_read_generic, &spr_write_generic,
5736 0x00000000);
5737 /* MSSSR0 */
5738 /* XXX : not implemented */
5739 spr_register(env, SPR_MSSSR0, "MSSSR0",
5740 SPR_NOACCESS, SPR_NOACCESS,
5741 &spr_read_generic, &spr_write_generic,
5742 0x00000000);
5743 /* PMC */
5744 /* XXX : not implemented */
5745 spr_register(env, SPR_PMC5, "PMC5",
5746 SPR_NOACCESS, SPR_NOACCESS,
5747 &spr_read_generic, &spr_write_generic,
5748 0x00000000);
5749 /* XXX : not implemented */
5750 spr_register(env, SPR_UPMC5, "UPMC5",
5751 &spr_read_ureg, SPR_NOACCESS,
5752 &spr_read_ureg, SPR_NOACCESS,
5753 0x00000000);
5754 /* XXX : not implemented */
5755 spr_register(env, SPR_PMC6, "PMC6",
5756 SPR_NOACCESS, SPR_NOACCESS,
5757 &spr_read_generic, &spr_write_generic,
5758 0x00000000);
5759 /* XXX : not implemented */
5760 spr_register(env, SPR_UPMC6, "UPMC6",
5761 &spr_read_ureg, SPR_NOACCESS,
5762 &spr_read_ureg, SPR_NOACCESS,
5763 0x00000000);
5764 /* Memory management */
5765 gen_low_BATs(env);
5766 gen_74xx_soft_tlb(env, 128, 2);
5767 init_excp_7450(env);
5768 env->dcache_line_size = 32;
5769 env->icache_line_size = 32;
5770 /* Allocate hardware IRQ controller */
5771 ppc6xx_irq_init(env);
5772 }
5773
5774 /* PowerPC 7445 (aka G4) */
5775 #define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5776 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5777 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5778 PPC_FLOAT_STFIWX | \
5779 PPC_CACHE | PPC_CACHE_ICBI | \
5780 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5781 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5782 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5783 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5784 PPC_SEGMENT | PPC_EXTERN | \
5785 PPC_ALTIVEC)
5786 #define POWERPC_INSNS2_7445 (PPC_NONE)
5787 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5788 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5789 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5790 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
5791 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
5792 #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5793 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5794 POWERPC_FLAG_BUS_CLK)
5795 #define check_pow_7445 check_pow_hid0_74xx
5796
5797 __attribute__ (( unused ))
5798 static void init_proc_7445 (CPUPPCState *env)
5799 {
5800 gen_spr_ne_601(env);
5801 gen_spr_7xx(env);
5802 /* Time base */
5803 gen_tbl(env);
5804 /* 74xx specific SPR */
5805 gen_spr_74xx(env);
5806 /* LDSTCR */
5807 /* XXX : not implemented */
5808 spr_register(env, SPR_LDSTCR, "LDSTCR",
5809 SPR_NOACCESS, SPR_NOACCESS,
5810 &spr_read_generic, &spr_write_generic,
5811 0x00000000);
5812 /* ICTRL */
5813 /* XXX : not implemented */
5814 spr_register(env, SPR_ICTRL, "ICTRL",
5815 SPR_NOACCESS, SPR_NOACCESS,
5816 &spr_read_generic, &spr_write_generic,
5817 0x00000000);
5818 /* MSSSR0 */
5819 /* XXX : not implemented */
5820 spr_register(env, SPR_MSSSR0, "MSSSR0",
5821 SPR_NOACCESS, SPR_NOACCESS,
5822 &spr_read_generic, &spr_write_generic,
5823 0x00000000);
5824 /* PMC */
5825 /* XXX : not implemented */
5826 spr_register(env, SPR_PMC5, "PMC5",
5827 SPR_NOACCESS, SPR_NOACCESS,
5828 &spr_read_generic, &spr_write_generic,
5829 0x00000000);
5830 /* XXX : not implemented */
5831 spr_register(env, SPR_UPMC5, "UPMC5",
5832 &spr_read_ureg, SPR_NOACCESS,
5833 &spr_read_ureg, SPR_NOACCESS,
5834 0x00000000);
5835 /* XXX : not implemented */
5836 spr_register(env, SPR_PMC6, "PMC6",
5837 SPR_NOACCESS, SPR_NOACCESS,
5838 &spr_read_generic, &spr_write_generic,
5839 0x00000000);
5840 /* XXX : not implemented */
5841 spr_register(env, SPR_UPMC6, "UPMC6",
5842 &spr_read_ureg, SPR_NOACCESS,
5843 &spr_read_ureg, SPR_NOACCESS,
5844 0x00000000);
5845 /* SPRGs */
5846 spr_register(env, SPR_SPRG4, "SPRG4",
5847 SPR_NOACCESS, SPR_NOACCESS,
5848 &spr_read_generic, &spr_write_generic,
5849 0x00000000);
5850 spr_register(env, SPR_USPRG4, "USPRG4",
5851 &spr_read_ureg, SPR_NOACCESS,
5852 &spr_read_ureg, SPR_NOACCESS,
5853 0x00000000);
5854 spr_register(env, SPR_SPRG5, "SPRG5",
5855 SPR_NOACCESS, SPR_NOACCESS,
5856 &spr_read_generic, &spr_write_generic,
5857 0x00000000);
5858 spr_register(env, SPR_USPRG5, "USPRG5",
5859 &spr_read_ureg, SPR_NOACCESS,
5860 &spr_read_ureg, SPR_NOACCESS,
5861 0x00000000);
5862 spr_register(env, SPR_SPRG6, "SPRG6",
5863 SPR_NOACCESS, SPR_NOACCESS,
5864 &spr_read_generic, &spr_write_generic,
5865 0x00000000);
5866 spr_register(env, SPR_USPRG6, "USPRG6",
5867 &spr_read_ureg, SPR_NOACCESS,
5868 &spr_read_ureg, SPR_NOACCESS,
5869 0x00000000);
5870 spr_register(env, SPR_SPRG7, "SPRG7",
5871 SPR_NOACCESS, SPR_NOACCESS,
5872 &spr_read_generic, &spr_write_generic,
5873 0x00000000);
5874 spr_register(env, SPR_USPRG7, "USPRG7",
5875 &spr_read_ureg, SPR_NOACCESS,
5876 &spr_read_ureg, SPR_NOACCESS,
5877 0x00000000);
5878 /* Memory management */
5879 gen_low_BATs(env);
5880 gen_high_BATs(env);
5881 gen_74xx_soft_tlb(env, 128, 2);
5882 init_excp_7450(env);
5883 env->dcache_line_size = 32;
5884 env->icache_line_size = 32;
5885 /* Allocate hardware IRQ controller */
5886 ppc6xx_irq_init(env);
5887 }
5888
5889 /* PowerPC 7455 (aka G4) */
5890 #define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5891 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5892 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5893 PPC_FLOAT_STFIWX | \
5894 PPC_CACHE | PPC_CACHE_ICBI | \
5895 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5896 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5897 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5898 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5899 PPC_SEGMENT | PPC_EXTERN | \
5900 PPC_ALTIVEC)
5901 #define POWERPC_INSNS2_7455 (PPC_NONE)
5902 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
5903 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
5904 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
5905 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
5906 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
5907 #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5908 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5909 POWERPC_FLAG_BUS_CLK)
5910 #define check_pow_7455 check_pow_hid0_74xx
5911
5912 __attribute__ (( unused ))
5913 static void init_proc_7455 (CPUPPCState *env)
5914 {
5915 gen_spr_ne_601(env);
5916 gen_spr_7xx(env);
5917 /* Time base */
5918 gen_tbl(env);
5919 /* 74xx specific SPR */
5920 gen_spr_74xx(env);
5921 /* Level 3 cache control */
5922 gen_l3_ctrl(env);
5923 /* LDSTCR */
5924 /* XXX : not implemented */
5925 spr_register(env, SPR_LDSTCR, "LDSTCR",
5926 SPR_NOACCESS, SPR_NOACCESS,
5927 &spr_read_generic, &spr_write_generic,
5928 0x00000000);
5929 /* ICTRL */
5930 /* XXX : not implemented */
5931 spr_register(env, SPR_ICTRL, "ICTRL",
5932 SPR_NOACCESS, SPR_NOACCESS,
5933 &spr_read_generic, &spr_write_generic,
5934 0x00000000);
5935 /* MSSSR0 */
5936 /* XXX : not implemented */
5937 spr_register(env, SPR_MSSSR0, "MSSSR0",
5938 SPR_NOACCESS, SPR_NOACCESS,
5939 &spr_read_generic, &spr_write_generic,
5940 0x00000000);
5941 /* PMC */
5942 /* XXX : not implemented */
5943 spr_register(env, SPR_PMC5, "PMC5",
5944 SPR_NOACCESS, SPR_NOACCESS,
5945 &spr_read_generic, &spr_write_generic,
5946 0x00000000);
5947 /* XXX : not implemented */
5948 spr_register(env, SPR_UPMC5, "UPMC5",
5949 &spr_read_ureg, SPR_NOACCESS,
5950 &spr_read_ureg, SPR_NOACCESS,
5951 0x00000000);
5952 /* XXX : not implemented */
5953 spr_register(env, SPR_PMC6, "PMC6",
5954 SPR_NOACCESS, SPR_NOACCESS,
5955 &spr_read_generic, &spr_write_generic,
5956 0x00000000);
5957 /* XXX : not implemented */
5958 spr_register(env, SPR_UPMC6, "UPMC6",
5959 &spr_read_ureg, SPR_NOACCESS,
5960 &spr_read_ureg, SPR_NOACCESS,
5961 0x00000000);
5962 /* SPRGs */
5963 spr_register(env, SPR_SPRG4, "SPRG4",
5964 SPR_NOACCESS, SPR_NOACCESS,
5965 &spr_read_generic, &spr_write_generic,
5966 0x00000000);
5967 spr_register(env, SPR_USPRG4, "USPRG4",
5968 &spr_read_ureg, SPR_NOACCESS,
5969 &spr_read_ureg, SPR_NOACCESS,
5970 0x00000000);
5971 spr_register(env, SPR_SPRG5, "SPRG5",
5972 SPR_NOACCESS, SPR_NOACCESS,
5973 &spr_read_generic, &spr_write_generic,
5974 0x00000000);
5975 spr_register(env, SPR_USPRG5, "USPRG5",
5976 &spr_read_ureg, SPR_NOACCESS,
5977 &spr_read_ureg, SPR_NOACCESS,
5978 0x00000000);
5979 spr_register(env, SPR_SPRG6, "SPRG6",
5980 SPR_NOACCESS, SPR_NOACCESS,
5981 &spr_read_generic, &spr_write_generic,
5982 0x00000000);
5983 spr_register(env, SPR_USPRG6, "USPRG6",
5984 &spr_read_ureg, SPR_NOACCESS,
5985 &spr_read_ureg, SPR_NOACCESS,
5986 0x00000000);
5987 spr_register(env, SPR_SPRG7, "SPRG7",
5988 SPR_NOACCESS, SPR_NOACCESS,
5989 &spr_read_generic, &spr_write_generic,
5990 0x00000000);
5991 spr_register(env, SPR_USPRG7, "USPRG7",
5992 &spr_read_ureg, SPR_NOACCESS,
5993 &spr_read_ureg, SPR_NOACCESS,
5994 0x00000000);
5995 /* Memory management */
5996 gen_low_BATs(env);
5997 gen_high_BATs(env);
5998 gen_74xx_soft_tlb(env, 128, 2);
5999 init_excp_7450(env);
6000 env->dcache_line_size = 32;
6001 env->icache_line_size = 32;
6002 /* Allocate hardware IRQ controller */
6003 ppc6xx_irq_init(env);
6004 }
6005
6006 /* PowerPC 7457 (aka G4) */
6007 #define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6008 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6009 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6010 PPC_FLOAT_STFIWX | \
6011 PPC_CACHE | PPC_CACHE_ICBI | \
6012 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
6013 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6014 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6015 PPC_MEM_TLBIA | PPC_74xx_TLB | \
6016 PPC_SEGMENT | PPC_EXTERN | \
6017 PPC_ALTIVEC)
6018 #define POWERPC_INSNS2_7457 (PPC_NONE)
6019 #define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
6020 #define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
6021 #define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
6022 #define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
6023 #define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
6024 #define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6025 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6026 POWERPC_FLAG_BUS_CLK)
6027 #define check_pow_7457 check_pow_hid0_74xx
6028
6029 __attribute__ (( unused ))
6030 static void init_proc_7457 (CPUPPCState *env)
6031 {
6032 gen_spr_ne_601(env);
6033 gen_spr_7xx(env);
6034 /* Time base */
6035 gen_tbl(env);
6036 /* 74xx specific SPR */
6037 gen_spr_74xx(env);
6038 /* Level 3 cache control */
6039 gen_l3_ctrl(env);
6040 /* L3ITCR1 */
6041 /* XXX : not implemented */
6042 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6043 SPR_NOACCESS, SPR_NOACCESS,
6044 &spr_read_generic, &spr_write_generic,
6045 0x00000000);
6046 /* L3ITCR2 */
6047 /* XXX : not implemented */
6048 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6049 SPR_NOACCESS, SPR_NOACCESS,
6050 &spr_read_generic, &spr_write_generic,
6051 0x00000000);
6052 /* L3ITCR3 */
6053 /* XXX : not implemented */
6054 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6055 SPR_NOACCESS, SPR_NOACCESS,
6056 &spr_read_generic, &spr_write_generic,
6057 0x00000000);
6058 /* L3OHCR */
6059 /* XXX : not implemented */
6060 spr_register(env, SPR_L3OHCR, "L3OHCR",
6061 SPR_NOACCESS, SPR_NOACCESS,
6062 &spr_read_generic, &spr_write_generic,
6063 0x00000000);
6064 /* LDSTCR */
6065 /* XXX : not implemented */
6066 spr_register(env, SPR_LDSTCR, "LDSTCR",
6067 SPR_NOACCESS, SPR_NOACCESS,
6068 &spr_read_generic, &spr_write_generic,
6069 0x00000000);
6070 /* ICTRL */
6071 /* XXX : not implemented */
6072 spr_register(env, SPR_ICTRL, "ICTRL",
6073 SPR_NOACCESS, SPR_NOACCESS,
6074 &spr_read_generic, &spr_write_generic,
6075 0x00000000);
6076 /* MSSSR0 */
6077 /* XXX : not implemented */
6078 spr_register(env, SPR_MSSSR0, "MSSSR0",
6079 SPR_NOACCESS, SPR_NOACCESS,
6080 &spr_read_generic, &spr_write_generic,
6081 0x00000000);
6082 /* PMC */
6083 /* XXX : not implemented */
6084 spr_register(env, SPR_PMC5, "PMC5",
6085 SPR_NOACCESS, SPR_NOACCESS,
6086 &spr_read_generic, &spr_write_generic,
6087 0x00000000);
6088 /* XXX : not implemented */
6089 spr_register(env, SPR_UPMC5, "UPMC5",
6090 &spr_read_ureg, SPR_NOACCESS,
6091 &spr_read_ureg, SPR_NOACCESS,
6092 0x00000000);
6093 /* XXX : not implemented */
6094 spr_register(env, SPR_PMC6, "PMC6",
6095 SPR_NOACCESS, SPR_NOACCESS,
6096 &spr_read_generic, &spr_write_generic,
6097 0x00000000);
6098 /* XXX : not implemented */
6099 spr_register(env, SPR_UPMC6, "UPMC6",
6100 &spr_read_ureg, SPR_NOACCESS,
6101 &spr_read_ureg, SPR_NOACCESS,
6102 0x00000000);
6103 /* SPRGs */
6104 spr_register(env, SPR_SPRG4, "SPRG4",
6105 SPR_NOACCESS, SPR_NOACCESS,
6106 &spr_read_generic, &spr_write_generic,
6107 0x00000000);
6108 spr_register(env, SPR_USPRG4, "USPRG4",
6109 &spr_read_ureg, SPR_NOACCESS,
6110 &spr_read_ureg, SPR_NOACCESS,
6111 0x00000000);
6112 spr_register(env, SPR_SPRG5, "SPRG5",
6113 SPR_NOACCESS, SPR_NOACCESS,
6114 &spr_read_generic, &spr_write_generic,
6115 0x00000000);
6116 spr_register(env, SPR_USPRG5, "USPRG5",
6117 &spr_read_ureg, SPR_NOACCESS,
6118 &spr_read_ureg, SPR_NOACCESS,
6119 0x00000000);
6120 spr_register(env, SPR_SPRG6, "SPRG6",
6121 SPR_NOACCESS, SPR_NOACCESS,
6122 &spr_read_generic, &spr_write_generic,
6123 0x00000000);
6124 spr_register(env, SPR_USPRG6, "USPRG6",
6125 &spr_read_ureg, SPR_NOACCESS,
6126 &spr_read_ureg, SPR_NOACCESS,
6127 0x00000000);
6128 spr_register(env, SPR_SPRG7, "SPRG7",
6129 SPR_NOACCESS, SPR_NOACCESS,
6130 &spr_read_generic, &spr_write_generic,
6131 0x00000000);
6132 spr_register(env, SPR_USPRG7, "USPRG7",
6133 &spr_read_ureg, SPR_NOACCESS,
6134 &spr_read_ureg, SPR_NOACCESS,
6135 0x00000000);
6136 /* Memory management */
6137 gen_low_BATs(env);
6138 gen_high_BATs(env);
6139 gen_74xx_soft_tlb(env, 128, 2);
6140 init_excp_7450(env);
6141 env->dcache_line_size = 32;
6142 env->icache_line_size = 32;
6143 /* Allocate hardware IRQ controller */
6144 ppc6xx_irq_init(env);
6145 }
6146
6147 #if defined (TARGET_PPC64)
6148 /* PowerPC 970 */
6149 #define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6150 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6151 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6152 PPC_FLOAT_STFIWX | \
6153 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6154 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6155 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6156 PPC_64B | PPC_ALTIVEC | \
6157 PPC_SEGMENT_64B | PPC_SLBI)
6158 #define POWERPC_INSNS2_970 (PPC_NONE)
6159 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
6160 #define POWERPC_MMU_970 (POWERPC_MMU_64B)
6161 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
6162 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
6163 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
6164 #define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6165 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6166 POWERPC_FLAG_BUS_CLK)
6167
6168 #if defined(CONFIG_USER_ONLY)
6169 #define POWERPC970_HID5_INIT 0x00000080
6170 #else
6171 #define POWERPC970_HID5_INIT 0x00000000
6172 #endif
6173
6174 static int check_pow_970 (CPUPPCState *env)
6175 {
6176 if (env->spr[SPR_HID0] & 0x00600000)
6177 return 1;
6178
6179 return 0;
6180 }
6181
6182 static void init_proc_970 (CPUPPCState *env)
6183 {
6184 gen_spr_ne_601(env);
6185 gen_spr_7xx(env);
6186 /* Time base */
6187 gen_tbl(env);
6188 /* Hardware implementation registers */
6189 /* XXX : not implemented */
6190 spr_register(env, SPR_HID0, "HID0",
6191 SPR_NOACCESS, SPR_NOACCESS,
6192 &spr_read_generic, &spr_write_clear,
6193 0x60000000);
6194 /* XXX : not implemented */
6195 spr_register(env, SPR_HID1, "HID1",
6196 SPR_NOACCESS, SPR_NOACCESS,
6197 &spr_read_generic, &spr_write_generic,
6198 0x00000000);
6199 /* XXX : not implemented */
6200 spr_register(env, SPR_750FX_HID2, "HID2",
6201 SPR_NOACCESS, SPR_NOACCESS,
6202 &spr_read_generic, &spr_write_generic,
6203 0x00000000);
6204 /* XXX : not implemented */
6205 spr_register(env, SPR_970_HID5, "HID5",
6206 SPR_NOACCESS, SPR_NOACCESS,
6207 &spr_read_generic, &spr_write_generic,
6208 POWERPC970_HID5_INIT);
6209 /* XXX : not implemented */
6210 spr_register(env, SPR_L2CR, "L2CR",
6211 SPR_NOACCESS, SPR_NOACCESS,
6212 &spr_read_generic, &spr_write_generic,
6213 0x00000000);
6214 /* Memory management */
6215 /* XXX: not correct */
6216 gen_low_BATs(env);
6217 /* XXX : not implemented */
6218 spr_register(env, SPR_MMUCFG, "MMUCFG",
6219 SPR_NOACCESS, SPR_NOACCESS,
6220 &spr_read_generic, SPR_NOACCESS,
6221 0x00000000); /* TOFIX */
6222 /* XXX : not implemented */
6223 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6224 SPR_NOACCESS, SPR_NOACCESS,
6225 &spr_read_generic, &spr_write_generic,
6226 0x00000000); /* TOFIX */
6227 spr_register(env, SPR_HIOR, "SPR_HIOR",
6228 SPR_NOACCESS, SPR_NOACCESS,
6229 &spr_read_hior, &spr_write_hior,
6230 0x00000000);
6231 #if !defined(CONFIG_USER_ONLY)
6232 env->slb_nr = 32;
6233 #endif
6234 init_excp_970(env);
6235 env->dcache_line_size = 128;
6236 env->icache_line_size = 128;
6237 /* Allocate hardware IRQ controller */
6238 ppc970_irq_init(env);
6239 /* Can't find information on what this should be on reset. This
6240 * value is the one used by 74xx processors. */
6241 vscr_init(env, 0x00010000);
6242 }
6243
6244 /* PowerPC 970FX (aka G5) */
6245 #define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6246 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6247 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6248 PPC_FLOAT_STFIWX | \
6249 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6250 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6251 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6252 PPC_64B | PPC_ALTIVEC | \
6253 PPC_SEGMENT_64B | PPC_SLBI)
6254 #define POWERPC_INSNS2_970FX (PPC_NONE)
6255 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
6256 #define POWERPC_MMU_970FX (POWERPC_MMU_64B)
6257 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
6258 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
6259 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
6260 #define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6261 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6262 POWERPC_FLAG_BUS_CLK)
6263
6264 static int check_pow_970FX (CPUPPCState *env)
6265 {
6266 if (env->spr[SPR_HID0] & 0x00600000)
6267 return 1;
6268
6269 return 0;
6270 }
6271
6272 static void init_proc_970FX (CPUPPCState *env)
6273 {
6274 gen_spr_ne_601(env);
6275 gen_spr_7xx(env);
6276 /* Time base */
6277 gen_tbl(env);
6278 /* Hardware implementation registers */
6279 /* XXX : not implemented */
6280 spr_register(env, SPR_HID0, "HID0",
6281 SPR_NOACCESS, SPR_NOACCESS,
6282 &spr_read_generic, &spr_write_clear,
6283 0x60000000);
6284 /* XXX : not implemented */
6285 spr_register(env, SPR_HID1, "HID1",
6286 SPR_NOACCESS, SPR_NOACCESS,
6287 &spr_read_generic, &spr_write_generic,
6288 0x00000000);
6289 /* XXX : not implemented */
6290 spr_register(env, SPR_750FX_HID2, "HID2",
6291 SPR_NOACCESS, SPR_NOACCESS,
6292 &spr_read_generic, &spr_write_generic,
6293 0x00000000);
6294 /* XXX : not implemented */
6295 spr_register(env, SPR_970_HID5, "HID5",
6296 SPR_NOACCESS, SPR_NOACCESS,
6297 &spr_read_generic, &spr_write_generic,
6298 POWERPC970_HID5_INIT);
6299 /* XXX : not implemented */
6300 spr_register(env, SPR_L2CR, "L2CR",
6301 SPR_NOACCESS, SPR_NOACCESS,
6302 &spr_read_generic, &spr_write_generic,
6303 0x00000000);
6304 /* Memory management */
6305 /* XXX: not correct */
6306 gen_low_BATs(env);
6307 /* XXX : not implemented */
6308 spr_register(env, SPR_MMUCFG, "MMUCFG",
6309 SPR_NOACCESS, SPR_NOACCESS,
6310 &spr_read_generic, SPR_NOACCESS,
6311 0x00000000); /* TOFIX */
6312 /* XXX : not implemented */
6313 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6314 SPR_NOACCESS, SPR_NOACCESS,
6315 &spr_read_generic, &spr_write_generic,
6316 0x00000000); /* TOFIX */
6317 spr_register(env, SPR_HIOR, "SPR_HIOR",
6318 SPR_NOACCESS, SPR_NOACCESS,
6319 &spr_read_hior, &spr_write_hior,
6320 0x00000000);
6321 spr_register(env, SPR_CTRL, "SPR_CTRL",
6322 SPR_NOACCESS, SPR_NOACCESS,
6323 &spr_read_generic, &spr_write_generic,
6324 0x00000000);
6325 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6326 SPR_NOACCESS, SPR_NOACCESS,
6327 &spr_read_generic, &spr_write_generic,
6328 0x00000000);
6329 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6330 &spr_read_generic, &spr_write_generic,
6331 &spr_read_generic, &spr_write_generic,
6332 0x00000000);
6333 #if !defined(CONFIG_USER_ONLY)
6334 env->slb_nr = 64;
6335 #endif
6336 init_excp_970(env);
6337 env->dcache_line_size = 128;
6338 env->icache_line_size = 128;
6339 /* Allocate hardware IRQ controller */
6340 ppc970_irq_init(env);
6341 /* Can't find information on what this should be on reset. This
6342 * value is the one used by 74xx processors. */
6343 vscr_init(env, 0x00010000);
6344 }
6345
6346 /* PowerPC 970 GX */
6347 #define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6348 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6349 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6350 PPC_FLOAT_STFIWX | \
6351 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6352 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6353 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6354 PPC_64B | PPC_ALTIVEC | \
6355 PPC_SEGMENT_64B | PPC_SLBI)
6356 #define POWERPC_INSNS2_970GX (PPC_NONE)
6357 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
6358 #define POWERPC_MMU_970GX (POWERPC_MMU_64B)
6359 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6360 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
6361 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
6362 #define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6363 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6364 POWERPC_FLAG_BUS_CLK)
6365
6366 static int check_pow_970GX (CPUPPCState *env)
6367 {
6368 if (env->spr[SPR_HID0] & 0x00600000)
6369 return 1;
6370
6371 return 0;
6372 }
6373
6374 static void init_proc_970GX (CPUPPCState *env)
6375 {
6376 gen_spr_ne_601(env);
6377 gen_spr_7xx(env);
6378 /* Time base */
6379 gen_tbl(env);
6380 /* Hardware implementation registers */
6381 /* XXX : not implemented */
6382 spr_register(env, SPR_HID0, "HID0",
6383 SPR_NOACCESS, SPR_NOACCESS,
6384 &spr_read_generic, &spr_write_clear,
6385 0x60000000);
6386 /* XXX : not implemented */
6387 spr_register(env, SPR_HID1, "HID1",
6388 SPR_NOACCESS, SPR_NOACCESS,
6389 &spr_read_generic, &spr_write_generic,
6390 0x00000000);
6391 /* XXX : not implemented */
6392 spr_register(env, SPR_750FX_HID2, "HID2",
6393 SPR_NOACCESS, SPR_NOACCESS,
6394 &spr_read_generic, &spr_write_generic,
6395 0x00000000);
6396 /* XXX : not implemented */
6397 spr_register(env, SPR_970_HID5, "HID5",
6398 SPR_NOACCESS, SPR_NOACCESS,
6399 &spr_read_generic, &spr_write_generic,
6400 POWERPC970_HID5_INIT);
6401 /* XXX : not implemented */
6402 spr_register(env, SPR_L2CR, "L2CR",
6403 SPR_NOACCESS, SPR_NOACCESS,
6404 &spr_read_generic, &spr_write_generic,
6405 0x00000000);
6406 /* Memory management */
6407 /* XXX: not correct */
6408 gen_low_BATs(env);
6409 /* XXX : not implemented */
6410 spr_register(env, SPR_MMUCFG, "MMUCFG",
6411 SPR_NOACCESS, SPR_NOACCESS,
6412 &spr_read_generic, SPR_NOACCESS,
6413 0x00000000); /* TOFIX */
6414 /* XXX : not implemented */
6415 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6416 SPR_NOACCESS, SPR_NOACCESS,
6417 &spr_read_generic, &spr_write_generic,
6418 0x00000000); /* TOFIX */
6419 spr_register(env, SPR_HIOR, "SPR_HIOR",
6420 SPR_NOACCESS, SPR_NOACCESS,
6421 &spr_read_hior, &spr_write_hior,
6422 0x00000000);
6423 #if !defined(CONFIG_USER_ONLY)
6424 env->slb_nr = 32;
6425 #endif
6426 init_excp_970(env);
6427 env->dcache_line_size = 128;
6428 env->icache_line_size = 128;
6429 /* Allocate hardware IRQ controller */
6430 ppc970_irq_init(env);
6431 /* Can't find information on what this should be on reset. This
6432 * value is the one used by 74xx processors. */
6433 vscr_init(env, 0x00010000);
6434 }
6435
6436 /* PowerPC 970 MP */
6437 #define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6438 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6439 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6440 PPC_FLOAT_STFIWX | \
6441 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6442 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6443 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6444 PPC_64B | PPC_ALTIVEC | \
6445 PPC_SEGMENT_64B | PPC_SLBI)
6446 #define POWERPC_INSNS2_970MP (PPC_NONE)
6447 #define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6448 #define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6449 #define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6450 #define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6451 #define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6452 #define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6453 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6454 POWERPC_FLAG_BUS_CLK)
6455
6456 static int check_pow_970MP (CPUPPCState *env)
6457 {
6458 if (env->spr[SPR_HID0] & 0x01C00000)
6459 return 1;
6460
6461 return 0;
6462 }
6463
6464 static void init_proc_970MP (CPUPPCState *env)
6465 {
6466 gen_spr_ne_601(env);
6467 gen_spr_7xx(env);
6468 /* Time base */
6469 gen_tbl(env);
6470 /* Hardware implementation registers */
6471 /* XXX : not implemented */
6472 spr_register(env, SPR_HID0, "HID0",
6473 SPR_NOACCESS, SPR_NOACCESS,
6474 &spr_read_generic, &spr_write_clear,
6475 0x60000000);
6476 /* XXX : not implemented */
6477 spr_register(env, SPR_HID1, "HID1",
6478 SPR_NOACCESS, SPR_NOACCESS,
6479 &spr_read_generic, &spr_write_generic,
6480 0x00000000);
6481 /* XXX : not implemented */
6482 spr_register(env, SPR_750FX_HID2, "HID2",
6483 SPR_NOACCESS, SPR_NOACCESS,
6484 &spr_read_generic, &spr_write_generic,
6485 0x00000000);
6486 /* XXX : not implemented */
6487 spr_register(env, SPR_970_HID5, "HID5",
6488 SPR_NOACCESS, SPR_NOACCESS,
6489 &spr_read_generic, &spr_write_generic,
6490 POWERPC970_HID5_INIT);
6491 /* XXX : not implemented */
6492 spr_register(env, SPR_L2CR, "L2CR",
6493 SPR_NOACCESS, SPR_NOACCESS,
6494 &spr_read_generic, &spr_write_generic,
6495 0x00000000);
6496 /* Memory management */
6497 /* XXX: not correct */
6498 gen_low_BATs(env);
6499 /* XXX : not implemented */
6500 spr_register(env, SPR_MMUCFG, "MMUCFG",
6501 SPR_NOACCESS, SPR_NOACCESS,
6502 &spr_read_generic, SPR_NOACCESS,
6503 0x00000000); /* TOFIX */
6504 /* XXX : not implemented */
6505 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6506 SPR_NOACCESS, SPR_NOACCESS,
6507 &spr_read_generic, &spr_write_generic,
6508 0x00000000); /* TOFIX */
6509 spr_register(env, SPR_HIOR, "SPR_HIOR",
6510 SPR_NOACCESS, SPR_NOACCESS,
6511 &spr_read_hior, &spr_write_hior,
6512 0x00000000);
6513 #if !defined(CONFIG_USER_ONLY)
6514 env->slb_nr = 32;
6515 #endif
6516 init_excp_970(env);
6517 env->dcache_line_size = 128;
6518 env->icache_line_size = 128;
6519 /* Allocate hardware IRQ controller */
6520 ppc970_irq_init(env);
6521 /* Can't find information on what this should be on reset. This
6522 * value is the one used by 74xx processors. */
6523 vscr_init(env, 0x00010000);
6524 }
6525
6526 #if defined(TARGET_PPC64)
6527 /* POWER7 */
6528 #define POWERPC_INSNS_POWER7 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6529 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6530 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6531 PPC_FLOAT_STFIWX | \
6532 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6533 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6534 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6535 PPC_64B | PPC_ALTIVEC | \
6536 PPC_SEGMENT_64B | PPC_SLBI | \
6537 PPC_POPCNTB | PPC_POPCNTWD)
6538 #define POWERPC_INSNS2_POWER7 (PPC_NONE)
6539 #define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
6540 #define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
6541 #define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
6542 #define POWERPC_INPUT_POWER7 (PPC_FLAGS_INPUT_POWER7)
6543 #define POWERPC_BFDM_POWER7 (bfd_mach_ppc64)
6544 #define POWERPC_FLAG_POWER7 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6545 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6546 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR)
6547 #define check_pow_POWER7 check_pow_nocheck
6548
6549 static void init_proc_POWER7 (CPUPPCState *env)
6550 {
6551 gen_spr_ne_601(env);
6552 gen_spr_7xx(env);
6553 /* Time base */
6554 gen_tbl(env);
6555 #if !defined(CONFIG_USER_ONLY)
6556 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6557 spr_register(env, SPR_PURR, "PURR",
6558 &spr_read_purr, SPR_NOACCESS,
6559 &spr_read_purr, SPR_NOACCESS,
6560 0x00000000);
6561 spr_register(env, SPR_SPURR, "SPURR",
6562 &spr_read_purr, SPR_NOACCESS,
6563 &spr_read_purr, SPR_NOACCESS,
6564 0x00000000);
6565 spr_register(env, SPR_CFAR, "SPR_CFAR",
6566 SPR_NOACCESS, SPR_NOACCESS,
6567 &spr_read_cfar, &spr_write_cfar,
6568 0x00000000);
6569 spr_register(env, SPR_DSCR, "SPR_DSCR",
6570 SPR_NOACCESS, SPR_NOACCESS,
6571 &spr_read_generic, &spr_write_generic,
6572 0x00000000);
6573 #endif /* !CONFIG_USER_ONLY */
6574 /* Memory management */
6575 /* XXX : not implemented */
6576 spr_register(env, SPR_MMUCFG, "MMUCFG",
6577 SPR_NOACCESS, SPR_NOACCESS,
6578 &spr_read_generic, SPR_NOACCESS,
6579 0x00000000); /* TOFIX */
6580 /* XXX : not implemented */
6581 spr_register(env, SPR_CTRL, "SPR_CTRLT",
6582 SPR_NOACCESS, SPR_NOACCESS,
6583 &spr_read_generic, &spr_write_generic,
6584 0x80800000);
6585 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
6586 SPR_NOACCESS, SPR_NOACCESS,
6587 &spr_read_generic, &spr_write_generic,
6588 0x80800000);
6589 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6590 &spr_read_generic, &spr_write_generic,
6591 &spr_read_generic, &spr_write_generic,
6592 0x00000000);
6593 #if !defined(CONFIG_USER_ONLY)
6594 env->slb_nr = 32;
6595 #endif
6596 init_excp_POWER7(env);
6597 env->dcache_line_size = 128;
6598 env->icache_line_size = 128;
6599 /* Allocate hardware IRQ controller */
6600 ppcPOWER7_irq_init(env);
6601 /* Can't find information on what this should be on reset. This
6602 * value is the one used by 74xx processors. */
6603 vscr_init(env, 0x00010000);
6604 }
6605 #endif /* TARGET_PPC64 */
6606
6607 /* PowerPC 620 */
6608 #define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6609 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6610 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6611 PPC_FLOAT_STFIWX | \
6612 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6613 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6614 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6615 PPC_SEGMENT | PPC_EXTERN | \
6616 PPC_64B | PPC_SLBI)
6617 #define POWERPC_INSNS2_620 (PPC_NONE)
6618 #define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6619 //#define POWERPC_MMU_620 (POWERPC_MMU_620)
6620 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
6621 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
6622 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
6623 #define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
6624 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
6625 #define check_pow_620 check_pow_nocheck /* Check this */
6626
6627 __attribute__ (( unused ))
6628 static void init_proc_620 (CPUPPCState *env)
6629 {
6630 gen_spr_ne_601(env);
6631 gen_spr_620(env);
6632 /* Time base */
6633 gen_tbl(env);
6634 /* Hardware implementation registers */
6635 /* XXX : not implemented */
6636 spr_register(env, SPR_HID0, "HID0",
6637 SPR_NOACCESS, SPR_NOACCESS,
6638 &spr_read_generic, &spr_write_generic,
6639 0x00000000);
6640 /* Memory management */
6641 gen_low_BATs(env);
6642 init_excp_620(env);
6643 env->dcache_line_size = 64;
6644 env->icache_line_size = 64;
6645 /* Allocate hardware IRQ controller */
6646 ppc6xx_irq_init(env);
6647 }
6648 #endif /* defined (TARGET_PPC64) */
6649
6650 /* Default 32 bits PowerPC target will be 604 */
6651 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
6652 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
6653 #define POWERPC_INSNS2_PPC32 POWERPC_INSNS2_604
6654 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6655 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
6656 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6657 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
6658 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
6659 #define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
6660 #define check_pow_PPC32 check_pow_604
6661 #define init_proc_PPC32 init_proc_604
6662
6663 /* Default 64 bits PowerPC target will be 970 FX */
6664 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6665 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
6666 #define POWERPC_INSNS2_PPC64 POWERPC_INSNS2_970FX
6667 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6668 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6669 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6670 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
6671 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
6672 #define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
6673 #define check_pow_PPC64 check_pow_970FX
6674 #define init_proc_PPC64 init_proc_970FX
6675
6676 /* Default PowerPC target will be PowerPC 32 */
6677 #if defined (TARGET_PPC64) && 0 // XXX: TODO
6678 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6679 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6680 #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC64
6681 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6682 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6683 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6684 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6685 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
6686 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
6687 #define check_pow_DEFAULT check_pow_PPC64
6688 #define init_proc_DEFAULT init_proc_PPC64
6689 #else
6690 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6691 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6692 #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC32
6693 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6694 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6695 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6696 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6697 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
6698 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
6699 #define check_pow_DEFAULT check_pow_PPC32
6700 #define init_proc_DEFAULT init_proc_PPC32
6701 #endif
6702
6703 /*****************************************************************************/
6704 /* PVR definitions for most known PowerPC */
6705 enum {
6706 /* PowerPC 401 family */
6707 /* Generic PowerPC 401 */
6708 #define CPU_POWERPC_401 CPU_POWERPC_401G2
6709 /* PowerPC 401 cores */
6710 CPU_POWERPC_401A1 = 0x00210000,
6711 CPU_POWERPC_401B2 = 0x00220000,
6712 #if 0
6713 CPU_POWERPC_401B3 = xxx,
6714 #endif
6715 CPU_POWERPC_401C2 = 0x00230000,
6716 CPU_POWERPC_401D2 = 0x00240000,
6717 CPU_POWERPC_401E2 = 0x00250000,
6718 CPU_POWERPC_401F2 = 0x00260000,
6719 CPU_POWERPC_401G2 = 0x00270000,
6720 /* PowerPC 401 microcontrolers */
6721 #if 0
6722 CPU_POWERPC_401GF = xxx,
6723 #endif
6724 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
6725 /* IBM Processor for Network Resources */
6726 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
6727 #if 0
6728 CPU_POWERPC_XIPCHIP = xxx,
6729 #endif
6730 /* PowerPC 403 family */
6731 /* Generic PowerPC 403 */
6732 #define CPU_POWERPC_403 CPU_POWERPC_403GC
6733 /* PowerPC 403 microcontrollers */
6734 CPU_POWERPC_403GA = 0x00200011,
6735 CPU_POWERPC_403GB = 0x00200100,
6736 CPU_POWERPC_403GC = 0x00200200,
6737 CPU_POWERPC_403GCX = 0x00201400,
6738 #if 0
6739 CPU_POWERPC_403GP = xxx,
6740 #endif
6741 /* PowerPC 405 family */
6742 /* Generic PowerPC 405 */
6743 #define CPU_POWERPC_405 CPU_POWERPC_405D4
6744 /* PowerPC 405 cores */
6745 #if 0
6746 CPU_POWERPC_405A3 = xxx,
6747 #endif
6748 #if 0
6749 CPU_POWERPC_405A4 = xxx,
6750 #endif
6751 #if 0
6752 CPU_POWERPC_405B3 = xxx,
6753 #endif
6754 #if 0
6755 CPU_POWERPC_405B4 = xxx,
6756 #endif
6757 #if 0
6758 CPU_POWERPC_405C3 = xxx,
6759 #endif
6760 #if 0
6761 CPU_POWERPC_405C4 = xxx,
6762 #endif
6763 CPU_POWERPC_405D2 = 0x20010000,
6764 #if 0
6765 CPU_POWERPC_405D3 = xxx,
6766 #endif
6767 CPU_POWERPC_405D4 = 0x41810000,
6768 #if 0
6769 CPU_POWERPC_405D5 = xxx,
6770 #endif
6771 #if 0
6772 CPU_POWERPC_405E4 = xxx,
6773 #endif
6774 #if 0
6775 CPU_POWERPC_405F4 = xxx,
6776 #endif
6777 #if 0
6778 CPU_POWERPC_405F5 = xxx,
6779 #endif
6780 #if 0
6781 CPU_POWERPC_405F6 = xxx,
6782 #endif
6783 /* PowerPC 405 microcontrolers */
6784 /* XXX: missing 0x200108a0 */
6785 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6786 CPU_POWERPC_405CRa = 0x40110041,
6787 CPU_POWERPC_405CRb = 0x401100C5,
6788 CPU_POWERPC_405CRc = 0x40110145,
6789 CPU_POWERPC_405EP = 0x51210950,
6790 #if 0
6791 CPU_POWERPC_405EXr = xxx,
6792 #endif
6793 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
6794 #if 0
6795 CPU_POWERPC_405FX = xxx,
6796 #endif
6797 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6798 CPU_POWERPC_405GPa = 0x40110000,
6799 CPU_POWERPC_405GPb = 0x40110040,
6800 CPU_POWERPC_405GPc = 0x40110082,
6801 CPU_POWERPC_405GPd = 0x401100C4,
6802 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6803 CPU_POWERPC_405GPR = 0x50910951,
6804 #if 0
6805 CPU_POWERPC_405H = xxx,
6806 #endif
6807 #if 0
6808 CPU_POWERPC_405L = xxx,
6809 #endif
6810 CPU_POWERPC_405LP = 0x41F10000,
6811 #if 0
6812 CPU_POWERPC_405PM = xxx,
6813 #endif
6814 #if 0
6815 CPU_POWERPC_405PS = xxx,
6816 #endif
6817 #if 0
6818 CPU_POWERPC_405S = xxx,
6819 #endif
6820 /* IBM network processors */
6821 CPU_POWERPC_NPE405H = 0x414100C0,
6822 CPU_POWERPC_NPE405H2 = 0x41410140,
6823 CPU_POWERPC_NPE405L = 0x416100C0,
6824 CPU_POWERPC_NPE4GS3 = 0x40B10000,
6825 #if 0
6826 CPU_POWERPC_NPCxx1 = xxx,
6827 #endif
6828 #if 0
6829 CPU_POWERPC_NPR161 = xxx,
6830 #endif
6831 #if 0
6832 CPU_POWERPC_LC77700 = xxx,
6833 #endif
6834 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6835 #if 0
6836 CPU_POWERPC_STB01000 = xxx,
6837 #endif
6838 #if 0
6839 CPU_POWERPC_STB01010 = xxx,
6840 #endif
6841 #if 0
6842 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
6843 #endif
6844 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
6845 #if 0
6846 CPU_POWERPC_STB043 = xxx,
6847 #endif
6848 #if 0
6849 CPU_POWERPC_STB045 = xxx,
6850 #endif
6851 CPU_POWERPC_STB04 = 0x41810000,
6852 CPU_POWERPC_STB25 = 0x51510950,
6853 #if 0
6854 CPU_POWERPC_STB130 = xxx,
6855 #endif
6856 /* Xilinx cores */
6857 CPU_POWERPC_X2VP4 = 0x20010820,
6858 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
6859 CPU_POWERPC_X2VP20 = 0x20010860,
6860 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
6861 #if 0
6862 CPU_POWERPC_ZL10310 = xxx,
6863 #endif
6864 #if 0
6865 CPU_POWERPC_ZL10311 = xxx,
6866 #endif
6867 #if 0
6868 CPU_POWERPC_ZL10320 = xxx,
6869 #endif
6870 #if 0
6871 CPU_POWERPC_ZL10321 = xxx,
6872 #endif
6873 /* PowerPC 440 family */
6874 /* Generic PowerPC 440 */
6875 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
6876 /* PowerPC 440 cores */
6877 #if 0
6878 CPU_POWERPC_440A4 = xxx,
6879 #endif
6880 CPU_POWERPC_440_XILINX = 0x7ff21910,
6881 #if 0
6882 CPU_POWERPC_440A5 = xxx,
6883 #endif
6884 #if 0
6885 CPU_POWERPC_440B4 = xxx,
6886 #endif
6887 #if 0
6888 CPU_POWERPC_440F5 = xxx,
6889 #endif
6890 #if 0
6891 CPU_POWERPC_440G5 = xxx,
6892 #endif
6893 #if 0
6894 CPU_POWERPC_440H4 = xxx,
6895 #endif
6896 #if 0
6897 CPU_POWERPC_440H6 = xxx,
6898 #endif
6899 /* PowerPC 440 microcontrolers */
6900 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
6901 CPU_POWERPC_440EPa = 0x42221850,
6902 CPU_POWERPC_440EPb = 0x422218D3,
6903 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
6904 CPU_POWERPC_440GPb = 0x40120440,
6905 CPU_POWERPC_440GPc = 0x40120481,
6906 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
6907 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
6908 CPU_POWERPC_440GRX = 0x200008D0,
6909 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
6910 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
6911 CPU_POWERPC_440GXa = 0x51B21850,
6912 CPU_POWERPC_440GXb = 0x51B21851,
6913 CPU_POWERPC_440GXc = 0x51B21892,
6914 CPU_POWERPC_440GXf = 0x51B21894,
6915 #if 0
6916 CPU_POWERPC_440S = xxx,
6917 #endif
6918 CPU_POWERPC_440SP = 0x53221850,
6919 CPU_POWERPC_440SP2 = 0x53221891,
6920 CPU_POWERPC_440SPE = 0x53421890,
6921 /* PowerPC 460 family */
6922 #if 0
6923 /* Generic PowerPC 464 */
6924 #define CPU_POWERPC_464 CPU_POWERPC_464H90
6925 #endif
6926 /* PowerPC 464 microcontrolers */
6927 #if 0
6928 CPU_POWERPC_464H90 = xxx,
6929 #endif
6930 #if 0
6931 CPU_POWERPC_464H90FP = xxx,
6932 #endif
6933 /* Freescale embedded PowerPC cores */
6934 /* PowerPC MPC 5xx cores (aka RCPU) */
6935 CPU_POWERPC_MPC5xx = 0x00020020,
6936 #define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
6937 #define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
6938 #define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
6939 #define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
6940 #define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
6941 #define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
6942 #define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
6943 #define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
6944 #define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
6945 #define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
6946 #define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
6947 #define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
6948 #define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
6949 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
6950 CPU_POWERPC_MPC8xx = 0x00500000,
6951 #define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
6952 #define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
6953 #define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
6954 #define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
6955 #define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
6956 #define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
6957 #define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
6958 #define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
6959 #define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
6960 #define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
6961 #define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
6962 #define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
6963 #define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
6964 #define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
6965 #define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
6966 /* G2 cores (aka PowerQUICC-II) */
6967 CPU_POWERPC_G2 = 0x00810011,
6968 CPU_POWERPC_G2H4 = 0x80811010,
6969 CPU_POWERPC_G2gp = 0x80821010,
6970 CPU_POWERPC_G2ls = 0x90810010,
6971 CPU_POWERPC_MPC603 = 0x00810100,
6972 CPU_POWERPC_G2_HIP3 = 0x00810101,
6973 CPU_POWERPC_G2_HIP4 = 0x80811014,
6974 /* G2_LE core (aka PowerQUICC-II) */
6975 CPU_POWERPC_G2LE = 0x80820010,
6976 CPU_POWERPC_G2LEgp = 0x80822010,
6977 CPU_POWERPC_G2LEls = 0xA0822010,
6978 CPU_POWERPC_G2LEgp1 = 0x80822011,
6979 CPU_POWERPC_G2LEgp3 = 0x80822013,
6980 /* MPC52xx microcontrollers */
6981 /* XXX: MPC 5121 ? */
6982 #define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
6983 #define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
6984 #define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
6985 #define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
6986 #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
6987 #define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
6988 #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
6989 #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
6990 /* MPC82xx microcontrollers */
6991 #define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
6992 #define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
6993 #define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
6994 #define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
6995 #define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
6996 #define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
6997 #define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
6998 #define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
6999 #define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
7000 #define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
7001 #define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
7002 #define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
7003 #define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
7004 #define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
7005 #define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
7006 #define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
7007 #define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
7008 #define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
7009 #define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
7010 #define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
7011 #define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
7012 #define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
7013 #define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
7014 #define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
7015 #define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
7016 #define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
7017 #define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
7018 #define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
7019 #define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
7020 /* e200 family */
7021 /* e200 cores */
7022 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
7023 #if 0
7024 CPU_POWERPC_e200z0 = xxx,
7025 #endif
7026 #if 0
7027 CPU_POWERPC_e200z1 = xxx,
7028 #endif
7029 #if 0 /* ? */
7030 CPU_POWERPC_e200z3 = 0x81120000,
7031 #endif
7032 CPU_POWERPC_e200z5 = 0x81000000,
7033 CPU_POWERPC_e200z6 = 0x81120000,
7034 /* MPC55xx microcontrollers */
7035 #define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
7036 #if 0
7037 #define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
7038 #define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
7039 #define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
7040 #define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
7041 #define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
7042 #define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
7043 #define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
7044 #define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
7045 #define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
7046 #define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
7047 #define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
7048 #define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
7049 #define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
7050 #define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
7051 #endif
7052 #if 0
7053 #define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
7054 #define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
7055 #endif
7056 #define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
7057 #define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
7058 #define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
7059 #define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
7060 #define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
7061 #define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
7062 /* e300 family */
7063 /* e300 cores */
7064 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
7065 CPU_POWERPC_e300c1 = 0x00830010,
7066 CPU_POWERPC_e300c2 = 0x00840010,
7067 CPU_POWERPC_e300c3 = 0x00850010,
7068 CPU_POWERPC_e300c4 = 0x00860010,
7069 /* MPC83xx microcontrollers */
7070 #define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
7071 #define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
7072 #define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
7073 #define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
7074 #define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
7075 #define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
7076 /* e500 family */
7077 /* e500 cores */
7078 #define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
7079 #define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
7080 #define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
7081 CPU_POWERPC_e500v1_v10 = 0x80200010,
7082 CPU_POWERPC_e500v1_v20 = 0x80200020,
7083 CPU_POWERPC_e500v2_v10 = 0x80210010,
7084 CPU_POWERPC_e500v2_v11 = 0x80210011,
7085 CPU_POWERPC_e500v2_v20 = 0x80210020,
7086 CPU_POWERPC_e500v2_v21 = 0x80210021,
7087 CPU_POWERPC_e500v2_v22 = 0x80210022,
7088 CPU_POWERPC_e500v2_v30 = 0x80210030,
7089 /* MPC85xx microcontrollers */
7090 #define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
7091 #define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
7092 #define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
7093 #define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
7094 #define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
7095 #define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
7096 #define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
7097 #define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
7098 #define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
7099 #define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
7100 #define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
7101 #define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
7102 #define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
7103 #define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
7104 #define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
7105 #define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
7106 #define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
7107 #define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
7108 #define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
7109 #define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
7110 #define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
7111 #define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
7112 #define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
7113 #define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
7114 #define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
7115 #define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
7116 #define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
7117 #define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
7118 #define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
7119 #define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
7120 #define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
7121 #define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
7122 #define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
7123 #define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
7124 #define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
7125 #define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
7126 #define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
7127 #define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
7128 #define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
7129 #define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
7130 #define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
7131 #define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
7132 #define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
7133 #define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
7134 #define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
7135 #define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
7136 #define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
7137 #define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
7138 #define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
7139 #define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
7140 #define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
7141 #define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
7142 #define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
7143 #define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
7144 #define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
7145 #define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
7146 #define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
7147 #define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
7148 #define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
7149 #define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
7150 #define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
7151 #define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
7152 #define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
7153 #define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
7154 #define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
7155 #define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
7156 #define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
7157 #define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
7158 #define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
7159 #define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
7160 /* e600 family */
7161 /* e600 cores */
7162 CPU_POWERPC_e600 = 0x80040010,
7163 /* MPC86xx microcontrollers */
7164 #define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
7165 #define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
7166 #define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
7167 /* PowerPC 6xx cores */
7168 #define CPU_POWERPC_601 CPU_POWERPC_601_v2
7169 CPU_POWERPC_601_v0 = 0x00010001,
7170 CPU_POWERPC_601_v1 = 0x00010001,
7171 #define CPU_POWERPC_601v CPU_POWERPC_601_v2
7172 CPU_POWERPC_601_v2 = 0x00010002,
7173 CPU_POWERPC_602 = 0x00050100,
7174 CPU_POWERPC_603 = 0x00030100,
7175 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
7176 CPU_POWERPC_603E_v11 = 0x00060101,
7177 CPU_POWERPC_603E_v12 = 0x00060102,
7178 CPU_POWERPC_603E_v13 = 0x00060103,
7179 CPU_POWERPC_603E_v14 = 0x00060104,
7180 CPU_POWERPC_603E_v22 = 0x00060202,
7181 CPU_POWERPC_603E_v3 = 0x00060300,
7182 CPU_POWERPC_603E_v4 = 0x00060400,
7183 CPU_POWERPC_603E_v41 = 0x00060401,
7184 CPU_POWERPC_603E7t = 0x00071201,
7185 CPU_POWERPC_603E7v = 0x00070100,
7186 CPU_POWERPC_603E7v1 = 0x00070101,
7187 CPU_POWERPC_603E7v2 = 0x00070201,
7188 CPU_POWERPC_603E7 = 0x00070200,
7189 CPU_POWERPC_603P = 0x00070000,
7190 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
7191 /* XXX: missing 0x00040303 (604) */
7192 CPU_POWERPC_604 = 0x00040103,
7193 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
7194 /* XXX: missing 0x00091203 */
7195 /* XXX: missing 0x00092110 */
7196 /* XXX: missing 0x00092120 */
7197 CPU_POWERPC_604E_v10 = 0x00090100,
7198 CPU_POWERPC_604E_v22 = 0x00090202,
7199 CPU_POWERPC_604E_v24 = 0x00090204,
7200 /* XXX: missing 0x000a0100 */
7201 /* XXX: missing 0x00093102 */
7202 CPU_POWERPC_604R = 0x000a0101,
7203 #if 0
7204 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
7205 #endif
7206 /* PowerPC 740/750 cores (aka G3) */
7207 /* XXX: missing 0x00084202 */
7208 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
7209 CPU_POWERPC_7x0_v10 = 0x00080100,
7210 CPU_POWERPC_7x0_v20 = 0x00080200,
7211 CPU_POWERPC_7x0_v21 = 0x00080201,
7212 CPU_POWERPC_7x0_v22 = 0x00080202,
7213 CPU_POWERPC_7x0_v30 = 0x00080300,
7214 CPU_POWERPC_7x0_v31 = 0x00080301,
7215 CPU_POWERPC_740E = 0x00080100,
7216 CPU_POWERPC_750E = 0x00080200,
7217 CPU_POWERPC_7x0P = 0x10080000,
7218 /* XXX: missing 0x00087010 (CL ?) */
7219 #define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
7220 CPU_POWERPC_750CL_v10 = 0x00087200,
7221 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
7222 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
7223 CPU_POWERPC_750CX_v10 = 0x00082100,
7224 CPU_POWERPC_750CX_v20 = 0x00082200,
7225 CPU_POWERPC_750CX_v21 = 0x00082201,
7226 CPU_POWERPC_750CX_v22 = 0x00082202,
7227 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
7228 CPU_POWERPC_750CXE_v21 = 0x00082211,
7229 CPU_POWERPC_750CXE_v22 = 0x00082212,
7230 CPU_POWERPC_750CXE_v23 = 0x00082213,
7231 CPU_POWERPC_750CXE_v24 = 0x00082214,
7232 CPU_POWERPC_750CXE_v24b = 0x00083214,
7233 CPU_POWERPC_750CXE_v30 = 0x00082310,
7234 CPU_POWERPC_750CXE_v31 = 0x00082311,
7235 CPU_POWERPC_750CXE_v31b = 0x00083311,
7236 CPU_POWERPC_750CXR = 0x00083410,
7237 CPU_POWERPC_750FL = 0x70000203,
7238 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
7239 CPU_POWERPC_750FX_v10 = 0x70000100,
7240 CPU_POWERPC_750FX_v20 = 0x70000200,
7241 CPU_POWERPC_750FX_v21 = 0x70000201,
7242 CPU_POWERPC_750FX_v22 = 0x70000202,
7243 CPU_POWERPC_750FX_v23 = 0x70000203,
7244 CPU_POWERPC_750GL = 0x70020102,
7245 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
7246 CPU_POWERPC_750GX_v10 = 0x70020100,
7247 CPU_POWERPC_750GX_v11 = 0x70020101,
7248 CPU_POWERPC_750GX_v12 = 0x70020102,
7249 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
7250 CPU_POWERPC_750L_v20 = 0x00088200,
7251 CPU_POWERPC_750L_v21 = 0x00088201,
7252 CPU_POWERPC_750L_v22 = 0x00088202,
7253 CPU_POWERPC_750L_v30 = 0x00088300,
7254 CPU_POWERPC_750L_v32 = 0x00088302,
7255 /* PowerPC 745/755 cores */
7256 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
7257 CPU_POWERPC_7x5_v10 = 0x00083100,
7258 CPU_POWERPC_7x5_v11 = 0x00083101,
7259 CPU_POWERPC_7x5_v20 = 0x00083200,
7260 CPU_POWERPC_7x5_v21 = 0x00083201,
7261 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
7262 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
7263 CPU_POWERPC_7x5_v24 = 0x00083204,
7264 CPU_POWERPC_7x5_v25 = 0x00083205,
7265 CPU_POWERPC_7x5_v26 = 0x00083206,
7266 CPU_POWERPC_7x5_v27 = 0x00083207,
7267 CPU_POWERPC_7x5_v28 = 0x00083208,
7268 #if 0
7269 CPU_POWERPC_7x5P = xxx,
7270 #endif
7271 /* PowerPC 74xx cores (aka G4) */
7272 /* XXX: missing 0x000C1101 */
7273 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
7274 CPU_POWERPC_7400_v10 = 0x000C0100,
7275 CPU_POWERPC_7400_v11 = 0x000C0101,
7276 CPU_POWERPC_7400_v20 = 0x000C0200,
7277 CPU_POWERPC_7400_v21 = 0x000C0201,
7278 CPU_POWERPC_7400_v22 = 0x000C0202,
7279 CPU_POWERPC_7400_v26 = 0x000C0206,
7280 CPU_POWERPC_7400_v27 = 0x000C0207,
7281 CPU_POWERPC_7400_v28 = 0x000C0208,
7282 CPU_POWERPC_7400_v29 = 0x000C0209,
7283 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
7284 CPU_POWERPC_7410_v10 = 0x800C1100,
7285 CPU_POWERPC_7410_v11 = 0x800C1101,
7286 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
7287 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
7288 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
7289 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
7290 CPU_POWERPC_7448_v10 = 0x80040100,
7291 CPU_POWERPC_7448_v11 = 0x80040101,
7292 CPU_POWERPC_7448_v20 = 0x80040200,
7293 CPU_POWERPC_7448_v21 = 0x80040201,
7294 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
7295 CPU_POWERPC_7450_v10 = 0x80000100,
7296 CPU_POWERPC_7450_v11 = 0x80000101,
7297 CPU_POWERPC_7450_v12 = 0x80000102,
7298 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
7299 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
7300 #define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
7301 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
7302 /* XXX: this entry might be a bug in some documentation */
7303 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
7304 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
7305 CPU_POWERPC_74x5_v10 = 0x80010100,
7306 /* XXX: missing 0x80010200 */
7307 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
7308 CPU_POWERPC_74x5_v32 = 0x80010302,
7309 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
7310 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
7311 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
7312 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
7313 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
7314 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
7315 #define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
7316 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
7317 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
7318 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
7319 /* 64 bits PowerPC */
7320 #if defined(TARGET_PPC64)
7321 CPU_POWERPC_620 = 0x00140000,
7322 CPU_POWERPC_630 = 0x00400000,
7323 CPU_POWERPC_631 = 0x00410104,
7324 CPU_POWERPC_POWER4 = 0x00350000,
7325 CPU_POWERPC_POWER4P = 0x00380000,
7326 /* XXX: missing 0x003A0201 */
7327 CPU_POWERPC_POWER5 = 0x003A0203,
7328 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
7329 CPU_POWERPC_POWER5P = 0x003B0000,
7330 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
7331 CPU_POWERPC_POWER6 = 0x003E0000,
7332 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
7333 CPU_POWERPC_POWER6A = 0x0F000002,
7334 #define CPU_POWERPC_POWER7 CPU_POWERPC_POWER7_v20
7335 CPU_POWERPC_POWER7_v20 = 0x003F0200,
7336 CPU_POWERPC_970 = 0x00390202,
7337 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
7338 CPU_POWERPC_970FX_v10 = 0x00391100,
7339 CPU_POWERPC_970FX_v20 = 0x003C0200,
7340 CPU_POWERPC_970FX_v21 = 0x003C0201,
7341 CPU_POWERPC_970FX_v30 = 0x003C0300,
7342 CPU_POWERPC_970FX_v31 = 0x003C0301,
7343 CPU_POWERPC_970GX = 0x00450000,
7344 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
7345 CPU_POWERPC_970MP_v10 = 0x00440100,
7346 CPU_POWERPC_970MP_v11 = 0x00440101,
7347 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
7348 CPU_POWERPC_CELL_v10 = 0x00700100,
7349 CPU_POWERPC_CELL_v20 = 0x00700400,
7350 CPU_POWERPC_CELL_v30 = 0x00700500,
7351 CPU_POWERPC_CELL_v31 = 0x00700501,
7352 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
7353 CPU_POWERPC_RS64 = 0x00330000,
7354 CPU_POWERPC_RS64II = 0x00340000,
7355 CPU_POWERPC_RS64III = 0x00360000,
7356 CPU_POWERPC_RS64IV = 0x00370000,
7357 #endif /* defined(TARGET_PPC64) */
7358 /* Original POWER */
7359 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7360 * POWER2 (RIOS2) & RSC2 (P2SC) here
7361 */
7362 #if 0
7363 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
7364 #endif
7365 #if 0
7366 CPU_POWER2 = xxx, /* 0x40000 ? */
7367 #endif
7368 /* PA Semi core */
7369 CPU_POWERPC_PA6T = 0x00900000,
7370 };
7371
7372 /* System version register (used on MPC 8xxx) */
7373 enum {
7374 POWERPC_SVR_NONE = 0x00000000,
7375 #define POWERPC_SVR_52xx POWERPC_SVR_5200
7376 #define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
7377 POWERPC_SVR_5200_v10 = 0x80110010,
7378 POWERPC_SVR_5200_v11 = 0x80110011,
7379 POWERPC_SVR_5200_v12 = 0x80110012,
7380 #define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
7381 POWERPC_SVR_5200B_v20 = 0x80110020,
7382 POWERPC_SVR_5200B_v21 = 0x80110021,
7383 #define POWERPC_SVR_55xx POWERPC_SVR_5567
7384 #if 0
7385 POWERPC_SVR_5533 = xxx,
7386 #endif
7387 #if 0
7388 POWERPC_SVR_5534 = xxx,
7389 #endif
7390 #if 0
7391 POWERPC_SVR_5553 = xxx,
7392 #endif
7393 #if 0
7394 POWERPC_SVR_5554 = xxx,
7395 #endif
7396 #if 0
7397 POWERPC_SVR_5561 = xxx,
7398 #endif
7399 #if 0
7400 POWERPC_SVR_5565 = xxx,
7401 #endif
7402 #if 0
7403 POWERPC_SVR_5566 = xxx,
7404 #endif
7405 #if 0
7406 POWERPC_SVR_5567 = xxx,
7407 #endif
7408 #if 0
7409 POWERPC_SVR_8313 = xxx,
7410 #endif
7411 #if 0
7412 POWERPC_SVR_8313E = xxx,
7413 #endif
7414 #if 0
7415 POWERPC_SVR_8314 = xxx,
7416 #endif
7417 #if 0
7418 POWERPC_SVR_8314E = xxx,
7419 #endif
7420 #if 0
7421 POWERPC_SVR_8315 = xxx,
7422 #endif
7423 #if 0
7424 POWERPC_SVR_8315E = xxx,
7425 #endif
7426 #if 0
7427 POWERPC_SVR_8321 = xxx,
7428 #endif
7429 #if 0
7430 POWERPC_SVR_8321E = xxx,
7431 #endif
7432 #if 0
7433 POWERPC_SVR_8323 = xxx,
7434 #endif
7435 #if 0
7436 POWERPC_SVR_8323E = xxx,
7437 #endif
7438 POWERPC_SVR_8343 = 0x80570010,
7439 POWERPC_SVR_8343A = 0x80570030,
7440 POWERPC_SVR_8343E = 0x80560010,
7441 POWERPC_SVR_8343EA = 0x80560030,
7442 #define POWERPC_SVR_8347 POWERPC_SVR_8347T
7443 POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
7444 POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
7445 #define POWERPC_SVR_8347A POWERPC_SVR_8347AT
7446 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7447 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
7448 #define POWERPC_SVR_8347E POWERPC_SVR_8347ET
7449 POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
7450 POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
7451 #define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
7452 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7453 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7454 POWERPC_SVR_8349 = 0x80510010,
7455 POWERPC_SVR_8349A = 0x80510030,
7456 POWERPC_SVR_8349E = 0x80500010,
7457 POWERPC_SVR_8349EA = 0x80500030,
7458 #if 0
7459 POWERPC_SVR_8358E = xxx,
7460 #endif
7461 #if 0
7462 POWERPC_SVR_8360E = xxx,
7463 #endif
7464 #define POWERPC_SVR_E500 0x40000000
7465 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7466 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7467 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7468 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7469 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7470 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
7471 #define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
7472 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7473 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
7474 #define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
7475 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7476 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
7477 #define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
7478 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7479 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7480 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
7481 #define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
7482 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7483 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
7484 #define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
7485 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7486 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
7487 #define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
7488 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7489 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7490 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7491 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
7492 #define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
7493 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7494 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7495 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7496 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
7497 #define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
7498 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7499 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
7500 #define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
7501 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7502 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
7503 #define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
7504 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7505 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
7506 #define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
7507 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7508 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
7509 #define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
7510 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7511 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
7512 #define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
7513 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7514 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7515 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7516 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
7517 #define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
7518 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7519 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7520 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7521 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
7522 #define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
7523 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7524 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
7525 #define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
7526 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7527 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
7528 #define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
7529 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7530 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7531 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7532 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7533 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7534 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7535 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7536 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7537 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
7538 #if 0
7539 POWERPC_SVR_8610 = xxx,
7540 #endif
7541 POWERPC_SVR_8641 = 0x80900021,
7542 POWERPC_SVR_8641D = 0x80900121,
7543 };
7544
7545 /*****************************************************************************/
7546 /* PowerPC CPU definitions */
7547 #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
7548 { \
7549 .name = _name, \
7550 .pvr = _pvr, \
7551 .svr = _svr, \
7552 .insns_flags = glue(POWERPC_INSNS_,_type), \
7553 .insns_flags2 = glue(POWERPC_INSNS2_,_type), \
7554 .msr_mask = glue(POWERPC_MSRM_,_type), \
7555 .mmu_model = glue(POWERPC_MMU_,_type), \
7556 .excp_model = glue(POWERPC_EXCP_,_type), \
7557 .bus_model = glue(POWERPC_INPUT_,_type), \
7558 .bfd_mach = glue(POWERPC_BFDM_,_type), \
7559 .flags = glue(POWERPC_FLAG_,_type), \
7560 .init_proc = &glue(init_proc_,_type), \
7561 .check_pow = &glue(check_pow_,_type), \
7562 }
7563 #define POWERPC_DEF(_name, _pvr, _type) \
7564 POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
7565
7566 static const ppc_def_t ppc_defs[] = {
7567 /* Embedded PowerPC */
7568 /* PowerPC 401 family */
7569 /* Generic PowerPC 401 */
7570 POWERPC_DEF("401", CPU_POWERPC_401, 401),
7571 /* PowerPC 401 cores */
7572 /* PowerPC 401A1 */
7573 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
7574 /* PowerPC 401B2 */
7575 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
7576 #if defined (TODO)
7577 /* PowerPC 401B3 */
7578 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
7579 #endif
7580 /* PowerPC 401C2 */
7581 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
7582 /* PowerPC 401D2 */
7583 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
7584 /* PowerPC 401E2 */
7585 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
7586 /* PowerPC 401F2 */
7587 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
7588 /* PowerPC 401G2 */
7589 /* XXX: to be checked */
7590 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
7591 /* PowerPC 401 microcontrolers */
7592 #if defined (TODO)
7593 /* PowerPC 401GF */
7594 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
7595 #endif
7596 /* IOP480 (401 microcontroler) */
7597 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
7598 /* IBM Processor for Network Resources */
7599 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
7600 #if defined (TODO)
7601 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
7602 #endif
7603 /* PowerPC 403 family */
7604 /* Generic PowerPC 403 */
7605 POWERPC_DEF("403", CPU_POWERPC_403, 403),
7606 /* PowerPC 403 microcontrolers */
7607 /* PowerPC 403 GA */
7608 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
7609 /* PowerPC 403 GB */
7610 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
7611 /* PowerPC 403 GC */
7612 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
7613 /* PowerPC 403 GCX */
7614 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
7615 #if defined (TODO)
7616 /* PowerPC 403 GP */
7617 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
7618 #endif
7619 /* PowerPC 405 family */
7620 /* Generic PowerPC 405 */
7621 POWERPC_DEF("405", CPU_POWERPC_405, 405),
7622 /* PowerPC 405 cores */
7623 #if defined (TODO)
7624 /* PowerPC 405 A3 */
7625 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
7626 #endif
7627 #if defined (TODO)
7628 /* PowerPC 405 A4 */
7629 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
7630 #endif
7631 #if defined (TODO)
7632 /* PowerPC 405 B3 */
7633 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
7634 #endif
7635 #if defined (TODO)
7636 /* PowerPC 405 B4 */
7637 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
7638 #endif
7639 #if defined (TODO)
7640 /* PowerPC 405 C3 */
7641 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
7642 #endif
7643 #if defined (TODO)
7644 /* PowerPC 405 C4 */
7645 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
7646 #endif
7647 /* PowerPC 405 D2 */
7648 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
7649 #if defined (TODO)
7650 /* PowerPC 405 D3 */
7651 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
7652 #endif
7653 /* PowerPC 405 D4 */
7654 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
7655 #if defined (TODO)
7656 /* PowerPC 405 D5 */
7657 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
7658 #endif
7659 #if defined (TODO)
7660 /* PowerPC 405 E4 */
7661 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
7662 #endif
7663 #if defined (TODO)
7664 /* PowerPC 405 F4 */
7665 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
7666 #endif
7667 #if defined (TODO)
7668 /* PowerPC 405 F5 */
7669 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
7670 #endif
7671 #if defined (TODO)
7672 /* PowerPC 405 F6 */
7673 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
7674 #endif
7675 /* PowerPC 405 microcontrolers */
7676 /* PowerPC 405 CR */
7677 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
7678 /* PowerPC 405 CRa */
7679 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
7680 /* PowerPC 405 CRb */
7681 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
7682 /* PowerPC 405 CRc */
7683 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
7684 /* PowerPC 405 EP */
7685 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
7686 #if defined(TODO)
7687 /* PowerPC 405 EXr */
7688 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
7689 #endif
7690 /* PowerPC 405 EZ */
7691 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
7692 #if defined(TODO)
7693 /* PowerPC 405 FX */
7694 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
7695 #endif
7696 /* PowerPC 405 GP */
7697 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
7698 /* PowerPC 405 GPa */
7699 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
7700 /* PowerPC 405 GPb */
7701 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
7702 /* PowerPC 405 GPc */
7703 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
7704 /* PowerPC 405 GPd */
7705 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
7706 /* PowerPC 405 GPe */
7707 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
7708 /* PowerPC 405 GPR */
7709 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
7710 #if defined(TODO)
7711 /* PowerPC 405 H */
7712 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
7713 #endif
7714 #if defined(TODO)
7715 /* PowerPC 405 L */
7716 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
7717 #endif
7718 /* PowerPC 405 LP */
7719 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
7720 #if defined(TODO)
7721 /* PowerPC 405 PM */
7722 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
7723 #endif
7724 #if defined(TODO)
7725 /* PowerPC 405 PS */
7726 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
7727 #endif
7728 #if defined(TODO)
7729 /* PowerPC 405 S */
7730 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
7731 #endif
7732 /* Npe405 H */
7733 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
7734 /* Npe405 H2 */
7735 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
7736 /* Npe405 L */
7737 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
7738 /* Npe4GS3 */
7739 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
7740 #if defined (TODO)
7741 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
7742 #endif
7743 #if defined (TODO)
7744 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
7745 #endif
7746 #if defined (TODO)
7747 /* PowerPC LC77700 (Sanyo) */
7748 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
7749 #endif
7750 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7751 #if defined (TODO)
7752 /* STB010000 */
7753 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
7754 #endif
7755 #if defined (TODO)
7756 /* STB01010 */
7757 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
7758 #endif
7759 #if defined (TODO)
7760 /* STB0210 */
7761 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
7762 #endif
7763 /* STB03xx */
7764 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
7765 #if defined (TODO)
7766 /* STB043x */
7767 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
7768 #endif
7769 #if defined (TODO)
7770 /* STB045x */
7771 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
7772 #endif
7773 /* STB04xx */
7774 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
7775 /* STB25xx */
7776 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
7777 #if defined (TODO)
7778 /* STB130 */
7779 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
7780 #endif
7781 /* Xilinx PowerPC 405 cores */
7782 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
7783 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
7784 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
7785 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
7786 #if defined (TODO)
7787 /* Zarlink ZL10310 */
7788 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
7789 #endif
7790 #if defined (TODO)
7791 /* Zarlink ZL10311 */
7792 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
7793 #endif
7794 #if defined (TODO)
7795 /* Zarlink ZL10320 */
7796 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
7797 #endif
7798 #if defined (TODO)
7799 /* Zarlink ZL10321 */
7800 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
7801 #endif
7802 /* PowerPC 440 family */
7803 #if defined(TODO_USER_ONLY)
7804 /* Generic PowerPC 440 */
7805 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
7806 #endif
7807 /* PowerPC 440 cores */
7808 #if defined (TODO)
7809 /* PowerPC 440 A4 */
7810 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
7811 #endif
7812 /* PowerPC 440 Xilinx 5 */
7813 POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5),
7814 #if defined (TODO)
7815 /* PowerPC 440 A5 */
7816 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
7817 #endif
7818 #if defined (TODO)
7819 /* PowerPC 440 B4 */
7820 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
7821 #endif
7822 #if defined (TODO)
7823 /* PowerPC 440 G4 */
7824 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
7825 #endif
7826 #if defined (TODO)
7827 /* PowerPC 440 F5 */
7828 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
7829 #endif
7830 #if defined (TODO)
7831 /* PowerPC 440 G5 */
7832 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
7833 #endif
7834 #if defined (TODO)
7835 /* PowerPC 440H4 */
7836 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
7837 #endif
7838 #if defined (TODO)
7839 /* PowerPC 440H6 */
7840 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
7841 #endif
7842 /* PowerPC 440 microcontrolers */
7843 #if defined(TODO_USER_ONLY)
7844 /* PowerPC 440 EP */
7845 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
7846 #endif
7847 #if defined(TODO_USER_ONLY)
7848 /* PowerPC 440 EPa */
7849 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
7850 #endif
7851 #if defined(TODO_USER_ONLY)
7852 /* PowerPC 440 EPb */
7853 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
7854 #endif
7855 #if defined(TODO_USER_ONLY)
7856 /* PowerPC 440 EPX */
7857 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
7858 #endif
7859 #if defined(TODO_USER_ONLY)
7860 /* PowerPC 440 GP */
7861 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
7862 #endif
7863 #if defined(TODO_USER_ONLY)
7864 /* PowerPC 440 GPb */
7865 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
7866 #endif
7867 #if defined(TODO_USER_ONLY)
7868 /* PowerPC 440 GPc */
7869 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
7870 #endif
7871 #if defined(TODO_USER_ONLY)
7872 /* PowerPC 440 GR */
7873 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
7874 #endif
7875 #if defined(TODO_USER_ONLY)
7876 /* PowerPC 440 GRa */
7877 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
7878 #endif
7879 #if defined(TODO_USER_ONLY)
7880 /* PowerPC 440 GRX */
7881 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
7882 #endif
7883 #if defined(TODO_USER_ONLY)
7884 /* PowerPC 440 GX */
7885 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
7886 #endif
7887 #if defined(TODO_USER_ONLY)
7888 /* PowerPC 440 GXa */
7889 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
7890 #endif
7891 #if defined(TODO_USER_ONLY)
7892 /* PowerPC 440 GXb */
7893 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
7894 #endif
7895 #if defined(TODO_USER_ONLY)
7896 /* PowerPC 440 GXc */
7897 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
7898 #endif
7899 #if defined(TODO_USER_ONLY)
7900 /* PowerPC 440 GXf */
7901 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
7902 #endif
7903 #if defined(TODO)
7904 /* PowerPC 440 S */
7905 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
7906 #endif
7907 #if defined(TODO_USER_ONLY)
7908 /* PowerPC 440 SP */
7909 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
7910 #endif
7911 #if defined(TODO_USER_ONLY)
7912 /* PowerPC 440 SP2 */
7913 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
7914 #endif
7915 #if defined(TODO_USER_ONLY)
7916 /* PowerPC 440 SPE */
7917 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
7918 #endif
7919 /* PowerPC 460 family */
7920 #if defined (TODO)
7921 /* Generic PowerPC 464 */
7922 POWERPC_DEF("464", CPU_POWERPC_464, 460),
7923 #endif
7924 /* PowerPC 464 microcontrolers */
7925 #if defined (TODO)
7926 /* PowerPC 464H90 */
7927 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
7928 #endif
7929 #if defined (TODO)
7930 /* PowerPC 464H90F */
7931 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
7932 #endif
7933 /* Freescale embedded PowerPC cores */
7934 /* MPC5xx family (aka RCPU) */
7935 #if defined(TODO_USER_ONLY)
7936 /* Generic MPC5xx core */
7937 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
7938 #endif
7939 #if defined(TODO_USER_ONLY)
7940 /* Codename for MPC5xx core */
7941 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
7942 #endif
7943 /* MPC5xx microcontrollers */
7944 #if defined(TODO_USER_ONLY)
7945 /* MGT560 */
7946 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
7947 #endif
7948 #if defined(TODO_USER_ONLY)
7949 /* MPC509 */
7950 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
7951 #endif
7952 #if defined(TODO_USER_ONLY)
7953 /* MPC533 */
7954 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
7955 #endif
7956 #if defined(TODO_USER_ONLY)
7957 /* MPC534 */
7958 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
7959 #endif
7960 #if defined(TODO_USER_ONLY)
7961 /* MPC555 */
7962 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
7963 #endif
7964 #if defined(TODO_USER_ONLY)
7965 /* MPC556 */
7966 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
7967 #endif
7968 #if defined(TODO_USER_ONLY)
7969 /* MPC560 */
7970 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
7971 #endif
7972 #if defined(TODO_USER_ONLY)
7973 /* MPC561 */
7974 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
7975 #endif
7976 #if defined(TODO_USER_ONLY)
7977 /* MPC562 */
7978 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
7979 #endif
7980 #if defined(TODO_USER_ONLY)
7981 /* MPC563 */
7982 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
7983 #endif
7984 #if defined(TODO_USER_ONLY)
7985 /* MPC564 */
7986 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
7987 #endif
7988 #if defined(TODO_USER_ONLY)
7989 /* MPC565 */
7990 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
7991 #endif
7992 #if defined(TODO_USER_ONLY)
7993 /* MPC566 */
7994 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
7995 #endif
7996 /* MPC8xx family (aka PowerQUICC) */
7997 #if defined(TODO_USER_ONLY)
7998 /* Generic MPC8xx core */
7999 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
8000 #endif
8001 #if defined(TODO_USER_ONLY)
8002 /* Codename for MPC8xx core */
8003 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
8004 #endif
8005 /* MPC8xx microcontrollers */
8006 #if defined(TODO_USER_ONLY)
8007 /* MGT823 */
8008 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
8009 #endif
8010 #if defined(TODO_USER_ONLY)
8011 /* MPC821 */
8012 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
8013 #endif
8014 #if defined(TODO_USER_ONLY)
8015 /* MPC823 */
8016 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
8017 #endif
8018 #if defined(TODO_USER_ONLY)
8019 /* MPC850 */
8020 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
8021 #endif
8022 #if defined(TODO_USER_ONLY)
8023 /* MPC852T */
8024 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
8025 #endif
8026 #if defined(TODO_USER_ONLY)
8027 /* MPC855T */
8028 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
8029 #endif
8030 #if defined(TODO_USER_ONLY)
8031 /* MPC857 */
8032 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
8033 #endif
8034 #if defined(TODO_USER_ONLY)
8035 /* MPC859 */
8036 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
8037 #endif
8038 #if defined(TODO_USER_ONLY)
8039 /* MPC860 */
8040 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
8041 #endif
8042 #if defined(TODO_USER_ONLY)
8043 /* MPC862 */
8044 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
8045 #endif
8046 #if defined(TODO_USER_ONLY)
8047 /* MPC866 */
8048 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
8049 #endif
8050 #if defined(TODO_USER_ONLY)
8051 /* MPC870 */
8052 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
8053 #endif
8054 #if defined(TODO_USER_ONLY)
8055 /* MPC875 */
8056 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
8057 #endif
8058 #if defined(TODO_USER_ONLY)
8059 /* MPC880 */
8060 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
8061 #endif
8062 #if defined(TODO_USER_ONLY)
8063 /* MPC885 */
8064 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
8065 #endif
8066 /* MPC82xx family (aka PowerQUICC-II) */
8067 /* Generic MPC52xx core */
8068 POWERPC_DEF_SVR("MPC52xx",
8069 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
8070 /* Generic MPC82xx core */
8071 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
8072 /* Codename for MPC82xx */
8073 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
8074 /* PowerPC G2 core */
8075 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
8076 /* PowerPC G2 H4 core */
8077 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
8078 /* PowerPC G2 GP core */
8079 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
8080 /* PowerPC G2 LS core */
8081 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
8082 /* PowerPC G2 HiP3 core */
8083 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
8084 /* PowerPC G2 HiP4 core */
8085 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
8086 /* PowerPC MPC603 core */
8087 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
8088 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
8089 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
8090 /* PowerPC G2LE GP core */
8091 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
8092 /* PowerPC G2LE LS core */
8093 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
8094 /* PowerPC G2LE GP1 core */
8095 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
8096 /* PowerPC G2LE GP3 core */
8097 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
8098 /* PowerPC MPC603 microcontrollers */
8099 /* MPC8240 */
8100 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
8101 /* PowerPC G2 microcontrollers */
8102 #if defined(TODO)
8103 /* MPC5121 */
8104 POWERPC_DEF_SVR("MPC5121",
8105 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
8106 #endif
8107 /* MPC5200 */
8108 POWERPC_DEF_SVR("MPC5200",
8109 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
8110 /* MPC5200 v1.0 */
8111 POWERPC_DEF_SVR("MPC5200_v10",
8112 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
8113 /* MPC5200 v1.1 */
8114 POWERPC_DEF_SVR("MPC5200_v11",
8115 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
8116 /* MPC5200 v1.2 */
8117 POWERPC_DEF_SVR("MPC5200_v12",
8118 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
8119 /* MPC5200B */
8120 POWERPC_DEF_SVR("MPC5200B",
8121 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
8122 /* MPC5200B v2.0 */
8123 POWERPC_DEF_SVR("MPC5200B_v20",
8124 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
8125 /* MPC5200B v2.1 */
8126 POWERPC_DEF_SVR("MPC5200B_v21",
8127 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
8128 /* MPC8241 */
8129 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
8130 /* MPC8245 */
8131 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
8132 /* MPC8247 */
8133 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
8134 /* MPC8248 */
8135 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
8136 /* MPC8250 */
8137 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
8138 /* MPC8250 HiP3 */
8139 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
8140 /* MPC8250 HiP4 */
8141 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
8142 /* MPC8255 */
8143 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
8144 /* MPC8255 HiP3 */
8145 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
8146 /* MPC8255 HiP4 */
8147 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
8148 /* MPC8260 */
8149 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
8150 /* MPC8260 HiP3 */
8151 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
8152 /* MPC8260 HiP4 */
8153 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
8154 /* MPC8264 */
8155 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
8156 /* MPC8264 HiP3 */
8157 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
8158 /* MPC8264 HiP4 */
8159 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
8160 /* MPC8265 */
8161 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
8162 /* MPC8265 HiP3 */
8163 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
8164 /* MPC8265 HiP4 */
8165 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
8166 /* MPC8266 */
8167 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
8168 /* MPC8266 HiP3 */
8169 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
8170 /* MPC8266 HiP4 */
8171 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
8172 /* MPC8270 */
8173 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
8174 /* MPC8271 */
8175 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
8176 /* MPC8272 */
8177 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
8178 /* MPC8275 */
8179 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
8180 /* MPC8280 */
8181 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
8182 /* e200 family */
8183 /* Generic PowerPC e200 core */
8184 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
8185 /* Generic MPC55xx core */
8186 #if defined (TODO)
8187 POWERPC_DEF_SVR("MPC55xx",
8188 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
8189 #endif
8190 #if defined (TODO)
8191 /* PowerPC e200z0 core */
8192 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
8193 #endif
8194 #if defined (TODO)
8195 /* PowerPC e200z1 core */
8196 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
8197 #endif
8198 #if defined (TODO)
8199 /* PowerPC e200z3 core */
8200 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
8201 #endif
8202 /* PowerPC e200z5 core */
8203 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
8204 /* PowerPC e200z6 core */
8205 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
8206 /* PowerPC e200 microcontrollers */
8207 #if defined (TODO)
8208 /* MPC5514E */
8209 POWERPC_DEF_SVR("MPC5514E",
8210 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
8211 #endif
8212 #if defined (TODO)
8213 /* MPC5514E v0 */
8214 POWERPC_DEF_SVR("MPC5514E_v0",
8215 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
8216 #endif
8217 #if defined (TODO)
8218 /* MPC5514E v1 */
8219 POWERPC_DEF_SVR("MPC5514E_v1",
8220 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
8221 #endif
8222 #if defined (TODO)
8223 /* MPC5514G */
8224 POWERPC_DEF_SVR("MPC5514G",
8225 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
8226 #endif
8227 #if defined (TODO)
8228 /* MPC5514G v0 */
8229 POWERPC_DEF_SVR("MPC5514G_v0",
8230 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
8231 #endif
8232 #if defined (TODO)
8233 /* MPC5514G v1 */
8234 POWERPC_DEF_SVR("MPC5514G_v1",
8235 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
8236 #endif
8237 #if defined (TODO)
8238 /* MPC5515S */
8239 POWERPC_DEF_SVR("MPC5515S",
8240 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
8241 #endif
8242 #if defined (TODO)
8243 /* MPC5516E */
8244 POWERPC_DEF_SVR("MPC5516E",
8245 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
8246 #endif
8247 #if defined (TODO)
8248 /* MPC5516E v0 */
8249 POWERPC_DEF_SVR("MPC5516E_v0",
8250 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
8251 #endif
8252 #if defined (TODO)
8253 /* MPC5516E v1 */
8254 POWERPC_DEF_SVR("MPC5516E_v1",
8255 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
8256 #endif
8257 #if defined (TODO)
8258 /* MPC5516G */
8259 POWERPC_DEF_SVR("MPC5516G",
8260 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
8261 #endif
8262 #if defined (TODO)
8263 /* MPC5516G v0 */
8264 POWERPC_DEF_SVR("MPC5516G_v0",
8265 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
8266 #endif
8267 #if defined (TODO)
8268 /* MPC5516G v1 */
8269 POWERPC_DEF_SVR("MPC5516G_v1",
8270 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
8271 #endif
8272 #if defined (TODO)
8273 /* MPC5516S */
8274 POWERPC_DEF_SVR("MPC5516S",
8275 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
8276 #endif
8277 #if defined (TODO)
8278 /* MPC5533 */
8279 POWERPC_DEF_SVR("MPC5533",
8280 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
8281 #endif
8282 #if defined (TODO)
8283 /* MPC5534 */
8284 POWERPC_DEF_SVR("MPC5534",
8285 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
8286 #endif
8287 #if defined (TODO)
8288 /* MPC5553 */
8289 POWERPC_DEF_SVR("MPC5553",
8290 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
8291 #endif
8292 #if defined (TODO)
8293 /* MPC5554 */
8294 POWERPC_DEF_SVR("MPC5554",
8295 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
8296 #endif
8297 #if defined (TODO)
8298 /* MPC5561 */
8299 POWERPC_DEF_SVR("MPC5561",
8300 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
8301 #endif
8302 #if defined (TODO)
8303 /* MPC5565 */
8304 POWERPC_DEF_SVR("MPC5565",
8305 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
8306 #endif
8307 #if defined (TODO)
8308 /* MPC5566 */
8309 POWERPC_DEF_SVR("MPC5566",
8310 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
8311 #endif
8312 #if defined (TODO)
8313 /* MPC5567 */
8314 POWERPC_DEF_SVR("MPC5567",
8315 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
8316 #endif
8317 /* e300 family */
8318 /* Generic PowerPC e300 core */
8319 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
8320 /* PowerPC e300c1 core */
8321 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
8322 /* PowerPC e300c2 core */
8323 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
8324 /* PowerPC e300c3 core */
8325 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
8326 /* PowerPC e300c4 core */
8327 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
8328 /* PowerPC e300 microcontrollers */
8329 #if defined (TODO)
8330 /* MPC8313 */
8331 POWERPC_DEF_SVR("MPC8313",
8332 CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300),
8333 #endif
8334 #if defined (TODO)
8335 /* MPC8313E */
8336 POWERPC_DEF_SVR("MPC8313E",
8337 CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300),
8338 #endif
8339 #if defined (TODO)
8340 /* MPC8314 */
8341 POWERPC_DEF_SVR("MPC8314",
8342 CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300),
8343 #endif
8344 #if defined (TODO)
8345 /* MPC8314E */
8346 POWERPC_DEF_SVR("MPC8314E",
8347 CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300),
8348 #endif
8349 #if defined (TODO)
8350 /* MPC8315 */
8351 POWERPC_DEF_SVR("MPC8315",
8352 CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300),
8353 #endif
8354 #if defined (TODO)
8355 /* MPC8315E */
8356 POWERPC_DEF_SVR("MPC8315E",
8357 CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300),
8358 #endif
8359 #if defined (TODO)
8360 /* MPC8321 */
8361 POWERPC_DEF_SVR("MPC8321",
8362 CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300),
8363 #endif
8364 #if defined (TODO)
8365 /* MPC8321E */
8366 POWERPC_DEF_SVR("MPC8321E",
8367 CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300),
8368 #endif
8369 #if defined (TODO)
8370 /* MPC8323 */
8371 POWERPC_DEF_SVR("MPC8323",
8372 CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300),
8373 #endif
8374 #if defined (TODO)
8375 /* MPC8323E */
8376 POWERPC_DEF_SVR("MPC8323E",
8377 CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300),
8378 #endif
8379 /* MPC8343 */
8380 POWERPC_DEF_SVR("MPC8343",
8381 CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300),
8382 /* MPC8343A */
8383 POWERPC_DEF_SVR("MPC8343A",
8384 CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300),
8385 /* MPC8343E */
8386 POWERPC_DEF_SVR("MPC8343E",
8387 CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300),
8388 /* MPC8343EA */
8389 POWERPC_DEF_SVR("MPC8343EA",
8390 CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300),
8391 /* MPC8347 */
8392 POWERPC_DEF_SVR("MPC8347",
8393 CPU_POWERPC_MPC834x, POWERPC_SVR_8347, e300),
8394 /* MPC8347T */
8395 POWERPC_DEF_SVR("MPC8347T",
8396 CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300),
8397 /* MPC8347P */
8398 POWERPC_DEF_SVR("MPC8347P",
8399 CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300),
8400 /* MPC8347A */
8401 POWERPC_DEF_SVR("MPC8347A",
8402 CPU_POWERPC_MPC834x, POWERPC_SVR_8347A, e300),
8403 /* MPC8347AT */
8404 POWERPC_DEF_SVR("MPC8347AT",
8405 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300),
8406 /* MPC8347AP */
8407 POWERPC_DEF_SVR("MPC8347AP",
8408 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300),
8409 /* MPC8347E */
8410 POWERPC_DEF_SVR("MPC8347E",
8411 CPU_POWERPC_MPC834x, POWERPC_SVR_8347E, e300),
8412 /* MPC8347ET */
8413 POWERPC_DEF_SVR("MPC8347ET",
8414 CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300),
8415 /* MPC8343EP */
8416 POWERPC_DEF_SVR("MPC8347EP",
8417 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300),
8418 /* MPC8347EA */
8419 POWERPC_DEF_SVR("MPC8347EA",
8420 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EA, e300),
8421 /* MPC8347EAT */
8422 POWERPC_DEF_SVR("MPC8347EAT",
8423 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300),
8424 /* MPC8343EAP */
8425 POWERPC_DEF_SVR("MPC8347EAP",
8426 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300),
8427 /* MPC8349 */
8428 POWERPC_DEF_SVR("MPC8349",
8429 CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300),
8430 /* MPC8349A */
8431 POWERPC_DEF_SVR("MPC8349A",
8432 CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300),
8433 /* MPC8349E */
8434 POWERPC_DEF_SVR("MPC8349E",
8435 CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300),
8436 /* MPC8349EA */
8437 POWERPC_DEF_SVR("MPC8349EA",
8438 CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300),
8439 #if defined (TODO)
8440 /* MPC8358E */
8441 POWERPC_DEF_SVR("MPC8358E",
8442 CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300),
8443 #endif
8444 #if defined (TODO)
8445 /* MPC8360E */
8446 POWERPC_DEF_SVR("MPC8360E",
8447 CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300),
8448 #endif
8449 /* MPC8377 */
8450 POWERPC_DEF_SVR("MPC8377",
8451 CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300),
8452 /* MPC8377E */
8453 POWERPC_DEF_SVR("MPC8377E",
8454 CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300),
8455 /* MPC8378 */
8456 POWERPC_DEF_SVR("MPC8378",
8457 CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300),
8458 /* MPC8378E */
8459 POWERPC_DEF_SVR("MPC8378E",
8460 CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300),
8461 /* MPC8379 */
8462 POWERPC_DEF_SVR("MPC8379",
8463 CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300),
8464 /* MPC8379E */
8465 POWERPC_DEF_SVR("MPC8379E",
8466 CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300),
8467 /* e500 family */
8468 /* PowerPC e500 core */
8469 POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2),
8470 /* PowerPC e500v1 core */
8471 POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1),
8472 /* PowerPC e500 v1.0 core */
8473 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1),
8474 /* PowerPC e500 v2.0 core */
8475 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1),
8476 /* PowerPC e500v2 core */
8477 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2),
8478 /* PowerPC e500v2 v1.0 core */
8479 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2),
8480 /* PowerPC e500v2 v2.0 core */
8481 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2),
8482 /* PowerPC e500v2 v2.1 core */
8483 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2),
8484 /* PowerPC e500v2 v2.2 core */
8485 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2),
8486 /* PowerPC e500v2 v3.0 core */
8487 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
8488 /* PowerPC e500 microcontrollers */
8489 /* MPC8533 */
8490 POWERPC_DEF_SVR("MPC8533",
8491 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2),
8492 /* MPC8533 v1.0 */
8493 POWERPC_DEF_SVR("MPC8533_v10",
8494 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2),
8495 /* MPC8533 v1.1 */
8496 POWERPC_DEF_SVR("MPC8533_v11",
8497 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2),
8498 /* MPC8533E */
8499 POWERPC_DEF_SVR("MPC8533E",
8500 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2),
8501 /* MPC8533E v1.0 */
8502 POWERPC_DEF_SVR("MPC8533E_v10",
8503 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
8504 POWERPC_DEF_SVR("MPC8533E_v11",
8505 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
8506 /* MPC8540 */
8507 POWERPC_DEF_SVR("MPC8540",
8508 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1),
8509 /* MPC8540 v1.0 */
8510 POWERPC_DEF_SVR("MPC8540_v10",
8511 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1),
8512 /* MPC8540 v2.0 */
8513 POWERPC_DEF_SVR("MPC8540_v20",
8514 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1),
8515 /* MPC8540 v2.1 */
8516 POWERPC_DEF_SVR("MPC8540_v21",
8517 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1),
8518 /* MPC8541 */
8519 POWERPC_DEF_SVR("MPC8541",
8520 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1),
8521 /* MPC8541 v1.0 */
8522 POWERPC_DEF_SVR("MPC8541_v10",
8523 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1),
8524 /* MPC8541 v1.1 */
8525 POWERPC_DEF_SVR("MPC8541_v11",
8526 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1),
8527 /* MPC8541E */
8528 POWERPC_DEF_SVR("MPC8541E",
8529 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1),
8530 /* MPC8541E v1.0 */
8531 POWERPC_DEF_SVR("MPC8541E_v10",
8532 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
8533 /* MPC8541E v1.1 */
8534 POWERPC_DEF_SVR("MPC8541E_v11",
8535 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
8536 /* MPC8543 */
8537 POWERPC_DEF_SVR("MPC8543",
8538 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2),
8539 /* MPC8543 v1.0 */
8540 POWERPC_DEF_SVR("MPC8543_v10",
8541 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2),
8542 /* MPC8543 v1.1 */
8543 POWERPC_DEF_SVR("MPC8543_v11",
8544 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2),
8545 /* MPC8543 v2.0 */
8546 POWERPC_DEF_SVR("MPC8543_v20",
8547 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2),
8548 /* MPC8543 v2.1 */
8549 POWERPC_DEF_SVR("MPC8543_v21",
8550 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2),
8551 /* MPC8543E */
8552 POWERPC_DEF_SVR("MPC8543E",
8553 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2),
8554 /* MPC8543E v1.0 */
8555 POWERPC_DEF_SVR("MPC8543E_v10",
8556 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
8557 /* MPC8543E v1.1 */
8558 POWERPC_DEF_SVR("MPC8543E_v11",
8559 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
8560 /* MPC8543E v2.0 */
8561 POWERPC_DEF_SVR("MPC8543E_v20",
8562 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
8563 /* MPC8543E v2.1 */
8564 POWERPC_DEF_SVR("MPC8543E_v21",
8565 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
8566 /* MPC8544 */
8567 POWERPC_DEF_SVR("MPC8544",
8568 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2),
8569 /* MPC8544 v1.0 */
8570 POWERPC_DEF_SVR("MPC8544_v10",
8571 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2),
8572 /* MPC8544 v1.1 */
8573 POWERPC_DEF_SVR("MPC8544_v11",
8574 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2),
8575 /* MPC8544E */
8576 POWERPC_DEF_SVR("MPC8544E",
8577 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2),
8578 /* MPC8544E v1.0 */
8579 POWERPC_DEF_SVR("MPC8544E_v10",
8580 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
8581 /* MPC8544E v1.1 */
8582 POWERPC_DEF_SVR("MPC8544E_v11",
8583 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
8584 /* MPC8545 */
8585 POWERPC_DEF_SVR("MPC8545",
8586 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2),
8587 /* MPC8545 v2.0 */
8588 POWERPC_DEF_SVR("MPC8545_v20",
8589 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2),
8590 /* MPC8545 v2.1 */
8591 POWERPC_DEF_SVR("MPC8545_v21",
8592 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2),
8593 /* MPC8545E */
8594 POWERPC_DEF_SVR("MPC8545E",
8595 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2),
8596 /* MPC8545E v2.0 */
8597 POWERPC_DEF_SVR("MPC8545E_v20",
8598 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
8599 /* MPC8545E v2.1 */
8600 POWERPC_DEF_SVR("MPC8545E_v21",
8601 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
8602 /* MPC8547E */
8603 POWERPC_DEF_SVR("MPC8547E",
8604 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2),
8605 /* MPC8547E v2.0 */
8606 POWERPC_DEF_SVR("MPC8547E_v20",
8607 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
8608 /* MPC8547E v2.1 */
8609 POWERPC_DEF_SVR("MPC8547E_v21",
8610 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
8611 /* MPC8548 */
8612 POWERPC_DEF_SVR("MPC8548",
8613 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2),
8614 /* MPC8548 v1.0 */
8615 POWERPC_DEF_SVR("MPC8548_v10",
8616 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2),
8617 /* MPC8548 v1.1 */
8618 POWERPC_DEF_SVR("MPC8548_v11",
8619 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2),
8620 /* MPC8548 v2.0 */
8621 POWERPC_DEF_SVR("MPC8548_v20",
8622 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2),
8623 /* MPC8548 v2.1 */
8624 POWERPC_DEF_SVR("MPC8548_v21",
8625 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2),
8626 /* MPC8548E */
8627 POWERPC_DEF_SVR("MPC8548E",
8628 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2),
8629 /* MPC8548E v1.0 */
8630 POWERPC_DEF_SVR("MPC8548E_v10",
8631 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
8632 /* MPC8548E v1.1 */
8633 POWERPC_DEF_SVR("MPC8548E_v11",
8634 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
8635 /* MPC8548E v2.0 */
8636 POWERPC_DEF_SVR("MPC8548E_v20",
8637 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
8638 /* MPC8548E v2.1 */
8639 POWERPC_DEF_SVR("MPC8548E_v21",
8640 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
8641 /* MPC8555 */
8642 POWERPC_DEF_SVR("MPC8555",
8643 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2),
8644 /* MPC8555 v1.0 */
8645 POWERPC_DEF_SVR("MPC8555_v10",
8646 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2),
8647 /* MPC8555 v1.1 */
8648 POWERPC_DEF_SVR("MPC8555_v11",
8649 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2),
8650 /* MPC8555E */
8651 POWERPC_DEF_SVR("MPC8555E",
8652 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2),
8653 /* MPC8555E v1.0 */
8654 POWERPC_DEF_SVR("MPC8555E_v10",
8655 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
8656 /* MPC8555E v1.1 */
8657 POWERPC_DEF_SVR("MPC8555E_v11",
8658 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
8659 /* MPC8560 */
8660 POWERPC_DEF_SVR("MPC8560",
8661 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2),
8662 /* MPC8560 v1.0 */
8663 POWERPC_DEF_SVR("MPC8560_v10",
8664 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2),
8665 /* MPC8560 v2.0 */
8666 POWERPC_DEF_SVR("MPC8560_v20",
8667 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2),
8668 /* MPC8560 v2.1 */
8669 POWERPC_DEF_SVR("MPC8560_v21",
8670 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2),
8671 /* MPC8567 */
8672 POWERPC_DEF_SVR("MPC8567",
8673 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2),
8674 /* MPC8567E */
8675 POWERPC_DEF_SVR("MPC8567E",
8676 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2),
8677 /* MPC8568 */
8678 POWERPC_DEF_SVR("MPC8568",
8679 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2),
8680 /* MPC8568E */
8681 POWERPC_DEF_SVR("MPC8568E",
8682 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2),
8683 /* MPC8572 */
8684 POWERPC_DEF_SVR("MPC8572",
8685 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2),
8686 /* MPC8572E */
8687 POWERPC_DEF_SVR("MPC8572E",
8688 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2),
8689 /* e600 family */
8690 /* PowerPC e600 core */
8691 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
8692 /* PowerPC e600 microcontrollers */
8693 #if defined (TODO)
8694 /* MPC8610 */
8695 POWERPC_DEF_SVR("MPC8610",
8696 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
8697 #endif
8698 /* MPC8641 */
8699 POWERPC_DEF_SVR("MPC8641",
8700 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
8701 /* MPC8641D */
8702 POWERPC_DEF_SVR("MPC8641D",
8703 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
8704 /* 32 bits "classic" PowerPC */
8705 /* PowerPC 6xx family */
8706 /* PowerPC 601 */
8707 POWERPC_DEF("601", CPU_POWERPC_601, 601v),
8708 /* PowerPC 601v0 */
8709 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
8710 /* PowerPC 601v1 */
8711 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
8712 /* PowerPC 601v */
8713 POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
8714 /* PowerPC 601v2 */
8715 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
8716 /* PowerPC 602 */
8717 POWERPC_DEF("602", CPU_POWERPC_602, 602),
8718 /* PowerPC 603 */
8719 POWERPC_DEF("603", CPU_POWERPC_603, 603),
8720 /* Code name for PowerPC 603 */
8721 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
8722 /* PowerPC 603e (aka PID6) */
8723 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
8724 /* Code name for PowerPC 603e */
8725 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
8726 /* PowerPC 603e v1.1 */
8727 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
8728 /* PowerPC 603e v1.2 */
8729 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
8730 /* PowerPC 603e v1.3 */
8731 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
8732 /* PowerPC 603e v1.4 */
8733 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
8734 /* PowerPC 603e v2.2 */
8735 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
8736 /* PowerPC 603e v3 */
8737 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
8738 /* PowerPC 603e v4 */
8739 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
8740 /* PowerPC 603e v4.1 */
8741 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
8742 /* PowerPC 603e (aka PID7) */
8743 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
8744 /* PowerPC 603e7t */
8745 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
8746 /* PowerPC 603e7v */
8747 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
8748 /* Code name for PowerPC 603ev */
8749 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
8750 /* PowerPC 603e7v1 */
8751 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
8752 /* PowerPC 603e7v2 */
8753 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
8754 /* PowerPC 603p (aka PID7v) */
8755 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
8756 /* PowerPC 603r (aka PID7t) */
8757 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
8758 /* Code name for PowerPC 603r */
8759 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
8760 /* PowerPC 604 */
8761 POWERPC_DEF("604", CPU_POWERPC_604, 604),
8762 /* PowerPC 604e (aka PID9) */
8763 POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
8764 /* Code name for PowerPC 604e */
8765 POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
8766 /* PowerPC 604e v1.0 */
8767 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
8768 /* PowerPC 604e v2.2 */
8769 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
8770 /* PowerPC 604e v2.4 */
8771 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
8772 /* PowerPC 604r (aka PIDA) */
8773 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
8774 /* Code name for PowerPC 604r */
8775 POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
8776 #if defined(TODO)
8777 /* PowerPC 604ev */
8778 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
8779 #endif
8780 /* PowerPC 7xx family */
8781 /* Generic PowerPC 740 (G3) */
8782 POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
8783 /* Code name for PowerPC 740 */
8784 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
8785 /* Generic PowerPC 750 (G3) */
8786 POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
8787 /* Code name for PowerPC 750 */
8788 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
8789 /* PowerPC 740/750 is also known as G3 */
8790 POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
8791 /* PowerPC 740 v1.0 (G3) */
8792 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
8793 /* PowerPC 750 v1.0 (G3) */
8794 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
8795 /* PowerPC 740 v2.0 (G3) */
8796 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
8797 /* PowerPC 750 v2.0 (G3) */
8798 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
8799 /* PowerPC 740 v2.1 (G3) */
8800 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
8801 /* PowerPC 750 v2.1 (G3) */
8802 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
8803 /* PowerPC 740 v2.2 (G3) */
8804 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
8805 /* PowerPC 750 v2.2 (G3) */
8806 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
8807 /* PowerPC 740 v3.0 (G3) */
8808 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
8809 /* PowerPC 750 v3.0 (G3) */
8810 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
8811 /* PowerPC 740 v3.1 (G3) */
8812 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
8813 /* PowerPC 750 v3.1 (G3) */
8814 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
8815 /* PowerPC 740E (G3) */
8816 POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
8817 /* PowerPC 750E (G3) */
8818 POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
8819 /* PowerPC 740P (G3) */
8820 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
8821 /* PowerPC 750P (G3) */
8822 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
8823 /* Code name for PowerPC 740P/750P (G3) */
8824 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
8825 /* PowerPC 750CL (G3 embedded) */
8826 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
8827 /* PowerPC 750CL v1.0 */
8828 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
8829 /* PowerPC 750CL v2.0 */
8830 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
8831 /* PowerPC 750CX (G3 embedded) */
8832 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
8833 /* PowerPC 750CX v1.0 (G3 embedded) */
8834 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
8835 /* PowerPC 750CX v2.1 (G3 embedded) */
8836 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
8837 /* PowerPC 750CX v2.1 (G3 embedded) */
8838 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
8839 /* PowerPC 750CX v2.2 (G3 embedded) */
8840 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
8841 /* PowerPC 750CXe (G3 embedded) */
8842 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
8843 /* PowerPC 750CXe v2.1 (G3 embedded) */
8844 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
8845 /* PowerPC 750CXe v2.2 (G3 embedded) */
8846 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
8847 /* PowerPC 750CXe v2.3 (G3 embedded) */
8848 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
8849 /* PowerPC 750CXe v2.4 (G3 embedded) */
8850 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
8851 /* PowerPC 750CXe v2.4b (G3 embedded) */
8852 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
8853 /* PowerPC 750CXe v3.0 (G3 embedded) */
8854 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
8855 /* PowerPC 750CXe v3.1 (G3 embedded) */
8856 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
8857 /* PowerPC 750CXe v3.1b (G3 embedded) */
8858 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
8859 /* PowerPC 750CXr (G3 embedded) */
8860 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
8861 /* PowerPC 750FL (G3 embedded) */
8862 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
8863 /* PowerPC 750FX (G3 embedded) */
8864 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
8865 /* PowerPC 750FX v1.0 (G3 embedded) */
8866 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
8867 /* PowerPC 750FX v2.0 (G3 embedded) */
8868 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
8869 /* PowerPC 750FX v2.1 (G3 embedded) */
8870 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
8871 /* PowerPC 750FX v2.2 (G3 embedded) */
8872 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
8873 /* PowerPC 750FX v2.3 (G3 embedded) */
8874 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
8875 /* PowerPC 750GL (G3 embedded) */
8876 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
8877 /* PowerPC 750GX (G3 embedded) */
8878 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
8879 /* PowerPC 750GX v1.0 (G3 embedded) */
8880 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
8881 /* PowerPC 750GX v1.1 (G3 embedded) */
8882 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
8883 /* PowerPC 750GX v1.2 (G3 embedded) */
8884 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
8885 /* PowerPC 750L (G3 embedded) */
8886 POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
8887 /* Code name for PowerPC 750L (G3 embedded) */
8888 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
8889 /* PowerPC 750L v2.0 (G3 embedded) */
8890 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
8891 /* PowerPC 750L v2.1 (G3 embedded) */
8892 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
8893 /* PowerPC 750L v2.2 (G3 embedded) */
8894 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
8895 /* PowerPC 750L v3.0 (G3 embedded) */
8896 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
8897 /* PowerPC 750L v3.2 (G3 embedded) */
8898 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
8899 /* Generic PowerPC 745 */
8900 POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
8901 /* Generic PowerPC 755 */
8902 POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
8903 /* Code name for PowerPC 745/755 */
8904 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
8905 /* PowerPC 745 v1.0 */
8906 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
8907 /* PowerPC 755 v1.0 */
8908 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
8909 /* PowerPC 745 v1.1 */
8910 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
8911 /* PowerPC 755 v1.1 */
8912 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
8913 /* PowerPC 745 v2.0 */
8914 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
8915 /* PowerPC 755 v2.0 */
8916 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
8917 /* PowerPC 745 v2.1 */
8918 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
8919 /* PowerPC 755 v2.1 */
8920 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
8921 /* PowerPC 745 v2.2 */
8922 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
8923 /* PowerPC 755 v2.2 */
8924 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
8925 /* PowerPC 745 v2.3 */
8926 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
8927 /* PowerPC 755 v2.3 */
8928 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
8929 /* PowerPC 745 v2.4 */
8930 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
8931 /* PowerPC 755 v2.4 */
8932 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
8933 /* PowerPC 745 v2.5 */
8934 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
8935 /* PowerPC 755 v2.5 */
8936 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
8937 /* PowerPC 745 v2.6 */
8938 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
8939 /* PowerPC 755 v2.6 */
8940 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
8941 /* PowerPC 745 v2.7 */
8942 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
8943 /* PowerPC 755 v2.7 */
8944 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
8945 /* PowerPC 745 v2.8 */
8946 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
8947 /* PowerPC 755 v2.8 */
8948 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
8949 #if defined (TODO)
8950 /* PowerPC 745P (G3) */
8951 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
8952 /* PowerPC 755P (G3) */
8953 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
8954 #endif
8955 /* PowerPC 74xx family */
8956 /* PowerPC 7400 (G4) */
8957 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
8958 /* Code name for PowerPC 7400 */
8959 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
8960 /* PowerPC 74xx is also well known as G4 */
8961 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
8962 /* PowerPC 7400 v1.0 (G4) */
8963 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
8964 /* PowerPC 7400 v1.1 (G4) */
8965 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
8966 /* PowerPC 7400 v2.0 (G4) */
8967 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
8968 /* PowerPC 7400 v2.1 (G4) */
8969 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
8970 /* PowerPC 7400 v2.2 (G4) */
8971 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
8972 /* PowerPC 7400 v2.6 (G4) */
8973 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
8974 /* PowerPC 7400 v2.7 (G4) */
8975 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
8976 /* PowerPC 7400 v2.8 (G4) */
8977 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
8978 /* PowerPC 7400 v2.9 (G4) */
8979 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
8980 /* PowerPC 7410 (G4) */
8981 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
8982 /* Code name for PowerPC 7410 */
8983 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
8984 /* PowerPC 7410 v1.0 (G4) */
8985 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
8986 /* PowerPC 7410 v1.1 (G4) */
8987 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
8988 /* PowerPC 7410 v1.2 (G4) */
8989 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
8990 /* PowerPC 7410 v1.3 (G4) */
8991 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
8992 /* PowerPC 7410 v1.4 (G4) */
8993 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
8994 /* PowerPC 7448 (G4) */
8995 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
8996 /* PowerPC 7448 v1.0 (G4) */
8997 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
8998 /* PowerPC 7448 v1.1 (G4) */
8999 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
9000 /* PowerPC 7448 v2.0 (G4) */
9001 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
9002 /* PowerPC 7448 v2.1 (G4) */
9003 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
9004 /* PowerPC 7450 (G4) */
9005 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
9006 /* Code name for PowerPC 7450 */
9007 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
9008 /* PowerPC 7450 v1.0 (G4) */
9009 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
9010 /* PowerPC 7450 v1.1 (G4) */
9011 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
9012 /* PowerPC 7450 v1.2 (G4) */
9013 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
9014 /* PowerPC 7450 v2.0 (G4) */
9015 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
9016 /* PowerPC 7450 v2.1 (G4) */
9017 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
9018 /* PowerPC 7441 (G4) */
9019 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
9020 /* PowerPC 7451 (G4) */
9021 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
9022 /* PowerPC 7441 v2.1 (G4) */
9023 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
9024 /* PowerPC 7441 v2.3 (G4) */
9025 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
9026 /* PowerPC 7451 v2.3 (G4) */
9027 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
9028 /* PowerPC 7441 v2.10 (G4) */
9029 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
9030 /* PowerPC 7451 v2.10 (G4) */
9031 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
9032 /* PowerPC 7445 (G4) */
9033 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
9034 /* PowerPC 7455 (G4) */
9035 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
9036 /* Code name for PowerPC 7445/7455 */
9037 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
9038 /* PowerPC 7445 v1.0 (G4) */
9039 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
9040 /* PowerPC 7455 v1.0 (G4) */
9041 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
9042 /* PowerPC 7445 v2.1 (G4) */
9043 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
9044 /* PowerPC 7455 v2.1 (G4) */
9045 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
9046 /* PowerPC 7445 v3.2 (G4) */
9047 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
9048 /* PowerPC 7455 v3.2 (G4) */
9049 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
9050 /* PowerPC 7445 v3.3 (G4) */
9051 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
9052 /* PowerPC 7455 v3.3 (G4) */
9053 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
9054 /* PowerPC 7445 v3.4 (G4) */
9055 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
9056 /* PowerPC 7455 v3.4 (G4) */
9057 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
9058 /* PowerPC 7447 (G4) */
9059 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
9060 /* PowerPC 7457 (G4) */
9061 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
9062 /* Code name for PowerPC 7447/7457 */
9063 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
9064 /* PowerPC 7447 v1.0 (G4) */
9065 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
9066 /* PowerPC 7457 v1.0 (G4) */
9067 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
9068 /* PowerPC 7447 v1.1 (G4) */
9069 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
9070 /* PowerPC 7457 v1.1 (G4) */
9071 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
9072 /* PowerPC 7457 v1.2 (G4) */
9073 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
9074 /* PowerPC 7447A (G4) */
9075 POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
9076 /* PowerPC 7457A (G4) */
9077 POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
9078 /* PowerPC 7447A v1.0 (G4) */
9079 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
9080 /* PowerPC 7457A v1.0 (G4) */
9081 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
9082 /* Code name for PowerPC 7447A/7457A */
9083 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
9084 /* PowerPC 7447A v1.1 (G4) */
9085 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
9086 /* PowerPC 7457A v1.1 (G4) */
9087 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
9088 /* PowerPC 7447A v1.2 (G4) */
9089 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
9090 /* PowerPC 7457A v1.2 (G4) */
9091 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
9092 /* 64 bits PowerPC */
9093 #if defined (TARGET_PPC64)
9094 /* PowerPC 620 */
9095 POWERPC_DEF("620", CPU_POWERPC_620, 620),
9096 /* Code name for PowerPC 620 */
9097 POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
9098 #if defined (TODO)
9099 /* PowerPC 630 (POWER3) */
9100 POWERPC_DEF("630", CPU_POWERPC_630, 630),
9101 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
9102 /* Code names for POWER3 */
9103 POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
9104 POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
9105 #endif
9106 #if defined (TODO)
9107 /* PowerPC 631 (Power 3+) */
9108 POWERPC_DEF("631", CPU_POWERPC_631, 631),
9109 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
9110 #endif
9111 #if defined (TODO)
9112 /* POWER4 */
9113 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
9114 #endif
9115 #if defined (TODO)
9116 /* POWER4p */
9117 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
9118 #endif
9119 #if defined (TODO)
9120 /* POWER5 */
9121 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
9122 /* POWER5GR */
9123 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
9124 #endif
9125 #if defined (TODO)
9126 /* POWER5+ */
9127 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
9128 /* POWER5GS */
9129 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
9130 #endif
9131 #if defined (TODO)
9132 /* POWER6 */
9133 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
9134 /* POWER6 running in POWER5 mode */
9135 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
9136 /* POWER6A */
9137 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
9138 #endif
9139 /* POWER7 */
9140 POWERPC_DEF("POWER7", CPU_POWERPC_POWER7, POWER7),
9141 POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7),
9142 /* PowerPC 970 */
9143 POWERPC_DEF("970", CPU_POWERPC_970, 970),
9144 /* PowerPC 970FX (G5) */
9145 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
9146 /* PowerPC 970FX v1.0 (G5) */
9147 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
9148 /* PowerPC 970FX v2.0 (G5) */
9149 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
9150 /* PowerPC 970FX v2.1 (G5) */
9151 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
9152 /* PowerPC 970FX v3.0 (G5) */
9153 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
9154 /* PowerPC 970FX v3.1 (G5) */
9155 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
9156 /* PowerPC 970GX (G5) */
9157 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
9158 /* PowerPC 970MP */
9159 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
9160 /* PowerPC 970MP v1.0 */
9161 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
9162 /* PowerPC 970MP v1.1 */
9163 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
9164 #if defined (TODO)
9165 /* PowerPC Cell */
9166 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
9167 #endif
9168 #if defined (TODO)
9169 /* PowerPC Cell v1.0 */
9170 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
9171 #endif
9172 #if defined (TODO)
9173 /* PowerPC Cell v2.0 */
9174 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
9175 #endif
9176 #if defined (TODO)
9177 /* PowerPC Cell v3.0 */
9178 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
9179 #endif
9180 #if defined (TODO)
9181 /* PowerPC Cell v3.1 */
9182 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
9183 #endif
9184 #if defined (TODO)
9185 /* PowerPC Cell v3.2 */
9186 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
9187 #endif
9188 #if defined (TODO)
9189 /* RS64 (Apache/A35) */
9190 /* This one seems to support the whole POWER2 instruction set
9191 * and the PowerPC 64 one.
9192 */
9193 /* What about A10 & A30 ? */
9194 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
9195 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
9196 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
9197 #endif
9198 #if defined (TODO)
9199 /* RS64-II (NorthStar/A50) */
9200 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
9201 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
9202 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
9203 #endif
9204 #if defined (TODO)
9205 /* RS64-III (Pulsar) */
9206 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
9207 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
9208 #endif
9209 #if defined (TODO)
9210 /* RS64-IV (IceStar/IStar/SStar) */
9211 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
9212 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
9213 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
9214 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
9215 #endif
9216 #endif /* defined (TARGET_PPC64) */
9217 /* POWER */
9218 #if defined (TODO)
9219 /* Original POWER */
9220 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
9221 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
9222 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
9223 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
9224 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
9225 #endif
9226 #if defined (TODO)
9227 /* POWER2 */
9228 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
9229 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
9230 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
9231 #endif
9232 /* PA semi cores */
9233 #if defined (TODO)
9234 /* PA PA6T */
9235 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
9236 #endif
9237 /* Generic PowerPCs */
9238 #if defined (TARGET_PPC64)
9239 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
9240 #endif
9241 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
9242 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
9243 /* Fallback */
9244 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
9245 };
9246
9247 /*****************************************************************************/
9248 /* Generic CPU instantiation routine */
9249 static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
9250 {
9251 #if !defined(CONFIG_USER_ONLY)
9252 int i;
9253
9254 env->irq_inputs = NULL;
9255 /* Set all exception vectors to an invalid address */
9256 for (i = 0; i < POWERPC_EXCP_NB; i++)
9257 env->excp_vectors[i] = (target_ulong)(-1ULL);
9258 env->hreset_excp_prefix = 0x00000000;
9259 env->ivor_mask = 0x00000000;
9260 env->ivpr_mask = 0x00000000;
9261 /* Default MMU definitions */
9262 env->nb_BATs = 0;
9263 env->nb_tlb = 0;
9264 env->nb_ways = 0;
9265 env->tlb_type = TLB_NONE;
9266 #endif
9267 /* Register SPR common to all PowerPC implementations */
9268 gen_spr_generic(env);
9269 spr_register(env, SPR_PVR, "PVR",
9270 /* Linux permits userspace to read PVR */
9271 #if defined(CONFIG_LINUX_USER)
9272 &spr_read_generic,
9273 #else
9274 SPR_NOACCESS,
9275 #endif
9276 SPR_NOACCESS,
9277 &spr_read_generic, SPR_NOACCESS,
9278 def->pvr);
9279 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
9280 if (def->svr != POWERPC_SVR_NONE) {
9281 if (def->svr & POWERPC_SVR_E500) {
9282 spr_register(env, SPR_E500_SVR, "SVR",
9283 SPR_NOACCESS, SPR_NOACCESS,
9284 &spr_read_generic, SPR_NOACCESS,
9285 def->svr & ~POWERPC_SVR_E500);
9286 } else {
9287 spr_register(env, SPR_SVR, "SVR",
9288 SPR_NOACCESS, SPR_NOACCESS,
9289 &spr_read_generic, SPR_NOACCESS,
9290 def->svr);
9291 }
9292 }
9293 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
9294 (*def->init_proc)(env);
9295 #if !defined(CONFIG_USER_ONLY)
9296 env->excp_prefix = env->hreset_excp_prefix;
9297 #endif
9298 /* MSR bits & flags consistency checks */
9299 if (env->msr_mask & (1 << 25)) {
9300 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9301 case POWERPC_FLAG_SPE:
9302 case POWERPC_FLAG_VRE:
9303 break;
9304 default:
9305 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9306 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9307 exit(1);
9308 }
9309 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9310 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9311 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9312 exit(1);
9313 }
9314 if (env->msr_mask & (1 << 17)) {
9315 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9316 case POWERPC_FLAG_TGPR:
9317 case POWERPC_FLAG_CE:
9318 break;
9319 default:
9320 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9321 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9322 exit(1);
9323 }
9324 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9325 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9326 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9327 exit(1);
9328 }
9329 if (env->msr_mask & (1 << 10)) {
9330 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9331 POWERPC_FLAG_UBLE)) {
9332 case POWERPC_FLAG_SE:
9333 case POWERPC_FLAG_DWE:
9334 case POWERPC_FLAG_UBLE:
9335 break;
9336 default:
9337 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9338 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9339 "POWERPC_FLAG_UBLE\n");
9340 exit(1);
9341 }
9342 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9343 POWERPC_FLAG_UBLE)) {
9344 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9345 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9346 "POWERPC_FLAG_UBLE\n");
9347 exit(1);
9348 }
9349 if (env->msr_mask & (1 << 9)) {
9350 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9351 case POWERPC_FLAG_BE:
9352 case POWERPC_FLAG_DE:
9353 break;
9354 default:
9355 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9356 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9357 exit(1);
9358 }
9359 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9360 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9361 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9362 exit(1);
9363 }
9364 if (env->msr_mask & (1 << 2)) {
9365 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9366 case POWERPC_FLAG_PX:
9367 case POWERPC_FLAG_PMM:
9368 break;
9369 default:
9370 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9371 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9372 exit(1);
9373 }
9374 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9375 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9376 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9377 exit(1);
9378 }
9379 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9380 fprintf(stderr, "PowerPC flags inconsistency\n"
9381 "Should define the time-base and decrementer clock source\n");
9382 exit(1);
9383 }
9384 /* Allocate TLBs buffer when needed */
9385 #if !defined(CONFIG_USER_ONLY)
9386 if (env->nb_tlb != 0) {
9387 int nb_tlb = env->nb_tlb;
9388 if (env->id_tlbs != 0)
9389 nb_tlb *= 2;
9390 switch (env->tlb_type) {
9391 case TLB_6XX:
9392 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
9393 break;
9394 case TLB_EMB:
9395 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
9396 break;
9397 case TLB_MAS:
9398 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
9399 break;
9400 }
9401 /* Pre-compute some useful values */
9402 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9403 }
9404 if (env->irq_inputs == NULL) {
9405 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
9406 " Attempt Qemu to crash very soon !\n");
9407 }
9408 #endif
9409 if (env->check_pow == NULL) {
9410 fprintf(stderr, "WARNING: no power management check handler "
9411 "registered.\n"
9412 " Attempt Qemu to crash very soon !\n");
9413 }
9414 }
9415
9416 #if defined(PPC_DUMP_CPU)
9417 static void dump_ppc_sprs (CPUPPCState *env)
9418 {
9419 ppc_spr_t *spr;
9420 #if !defined(CONFIG_USER_ONLY)
9421 uint32_t sr, sw;
9422 #endif
9423 uint32_t ur, uw;
9424 int i, j, n;
9425
9426 printf("Special purpose registers:\n");
9427 for (i = 0; i < 32; i++) {
9428 for (j = 0; j < 32; j++) {
9429 n = (i << 5) | j;
9430 spr = &env->spr_cb[n];
9431 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9432 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9433 #if !defined(CONFIG_USER_ONLY)
9434 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9435 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9436 if (sw || sr || uw || ur) {
9437 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9438 (i << 5) | j, (i << 5) | j, spr->name,
9439 sw ? 'w' : '-', sr ? 'r' : '-',
9440 uw ? 'w' : '-', ur ? 'r' : '-');
9441 }
9442 #else
9443 if (uw || ur) {
9444 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9445 (i << 5) | j, (i << 5) | j, spr->name,
9446 uw ? 'w' : '-', ur ? 'r' : '-');
9447 }
9448 #endif
9449 }
9450 }
9451 fflush(stdout);
9452 fflush(stderr);
9453 }
9454 #endif
9455
9456 /*****************************************************************************/
9457 #include <stdlib.h>
9458 #include <string.h>
9459
9460 /* Opcode types */
9461 enum {
9462 PPC_DIRECT = 0, /* Opcode routine */
9463 PPC_INDIRECT = 1, /* Indirect opcode table */
9464 };
9465
9466 static inline int is_indirect_opcode (void *handler)
9467 {
9468 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
9469 }
9470
9471 static inline opc_handler_t **ind_table(void *handler)
9472 {
9473 return (opc_handler_t **)((unsigned long)handler & ~3);
9474 }
9475
9476 /* Instruction table creation */
9477 /* Opcodes tables creation */
9478 static void fill_new_table (opc_handler_t **table, int len)
9479 {
9480 int i;
9481
9482 for (i = 0; i < len; i++)
9483 table[i] = &invalid_handler;
9484 }
9485
9486 static int create_new_table (opc_handler_t **table, unsigned char idx)
9487 {
9488 opc_handler_t **tmp;
9489
9490 tmp = malloc(0x20 * sizeof(opc_handler_t));
9491 fill_new_table(tmp, 0x20);
9492 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
9493
9494 return 0;
9495 }
9496
9497 static int insert_in_table (opc_handler_t **table, unsigned char idx,
9498 opc_handler_t *handler)
9499 {
9500 if (table[idx] != &invalid_handler)
9501 return -1;
9502 table[idx] = handler;
9503
9504 return 0;
9505 }
9506
9507 static int register_direct_insn (opc_handler_t **ppc_opcodes,
9508 unsigned char idx, opc_handler_t *handler)
9509 {
9510 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9511 printf("*** ERROR: opcode %02x already assigned in main "
9512 "opcode table\n", idx);
9513 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9514 printf(" Registered handler '%s' - new handler '%s'\n",
9515 ppc_opcodes[idx]->oname, handler->oname);
9516 #endif
9517 return -1;
9518 }
9519
9520 return 0;
9521 }
9522
9523 static int register_ind_in_table (opc_handler_t **table,
9524 unsigned char idx1, unsigned char idx2,
9525 opc_handler_t *handler)
9526 {
9527 if (table[idx1] == &invalid_handler) {
9528 if (create_new_table(table, idx1) < 0) {
9529 printf("*** ERROR: unable to create indirect table "
9530 "idx=%02x\n", idx1);
9531 return -1;
9532 }
9533 } else {
9534 if (!is_indirect_opcode(table[idx1])) {
9535 printf("*** ERROR: idx %02x already assigned to a direct "
9536 "opcode\n", idx1);
9537 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9538 printf(" Registered handler '%s' - new handler '%s'\n",
9539 ind_table(table[idx1])[idx2]->oname, handler->oname);
9540 #endif
9541 return -1;
9542 }
9543 }
9544 if (handler != NULL &&
9545 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9546 printf("*** ERROR: opcode %02x already assigned in "
9547 "opcode table %02x\n", idx2, idx1);
9548 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9549 printf(" Registered handler '%s' - new handler '%s'\n",
9550 ind_table(table[idx1])[idx2]->oname, handler->oname);
9551 #endif
9552 return -1;
9553 }
9554
9555 return 0;
9556 }
9557
9558 static int register_ind_insn (opc_handler_t **ppc_opcodes,
9559 unsigned char idx1, unsigned char idx2,
9560 opc_handler_t *handler)
9561 {
9562 int ret;
9563
9564 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9565
9566 return ret;
9567 }
9568
9569 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
9570 unsigned char idx1, unsigned char idx2,
9571 unsigned char idx3, opc_handler_t *handler)
9572 {
9573 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9574 printf("*** ERROR: unable to join indirect table idx "
9575 "[%02x-%02x]\n", idx1, idx2);
9576 return -1;
9577 }
9578 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9579 handler) < 0) {
9580 printf("*** ERROR: unable to insert opcode "
9581 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9582 return -1;
9583 }
9584
9585 return 0;
9586 }
9587
9588 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
9589 {
9590 if (insn->opc2 != 0xFF) {
9591 if (insn->opc3 != 0xFF) {
9592 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9593 insn->opc3, &insn->handler) < 0)
9594 return -1;
9595 } else {
9596 if (register_ind_insn(ppc_opcodes, insn->opc1,
9597 insn->opc2, &insn->handler) < 0)
9598 return -1;
9599 }
9600 } else {
9601 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9602 return -1;
9603 }
9604
9605 return 0;
9606 }
9607
9608 static int test_opcode_table (opc_handler_t **table, int len)
9609 {
9610 int i, count, tmp;
9611
9612 for (i = 0, count = 0; i < len; i++) {
9613 /* Consistency fixup */
9614 if (table[i] == NULL)
9615 table[i] = &invalid_handler;
9616 if (table[i] != &invalid_handler) {
9617 if (is_indirect_opcode(table[i])) {
9618 tmp = test_opcode_table(ind_table(table[i]), 0x20);
9619 if (tmp == 0) {
9620 free(table[i]);
9621 table[i] = &invalid_handler;
9622 } else {
9623 count++;
9624 }
9625 } else {
9626 count++;
9627 }
9628 }
9629 }
9630
9631 return count;
9632 }
9633
9634 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
9635 {
9636 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9637 printf("*** WARNING: no opcode defined !\n");
9638 }
9639
9640 /*****************************************************************************/
9641 static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
9642 {
9643 opcode_t *opc;
9644
9645 fill_new_table(env->opcodes, 0x40);
9646 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
9647 if (((opc->handler.type & def->insns_flags) != 0) ||
9648 ((opc->handler.type2 & def->insns_flags2) != 0)) {
9649 if (register_insn(env->opcodes, opc) < 0) {
9650 printf("*** ERROR initializing PowerPC instruction "
9651 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9652 opc->opc3);
9653 return -1;
9654 }
9655 }
9656 }
9657 fix_opcode_tables(env->opcodes);
9658 fflush(stdout);
9659 fflush(stderr);
9660
9661 return 0;
9662 }
9663
9664 #if defined(PPC_DUMP_CPU)
9665 static void dump_ppc_insns (CPUPPCState *env)
9666 {
9667 opc_handler_t **table, *handler;
9668 const char *p, *q;
9669 uint8_t opc1, opc2, opc3;
9670
9671 printf("Instructions set:\n");
9672 /* opc1 is 6 bits long */
9673 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9674 table = env->opcodes;
9675 handler = table[opc1];
9676 if (is_indirect_opcode(handler)) {
9677 /* opc2 is 5 bits long */
9678 for (opc2 = 0; opc2 < 0x20; opc2++) {
9679 table = env->opcodes;
9680 handler = env->opcodes[opc1];
9681 table = ind_table(handler);
9682 handler = table[opc2];
9683 if (is_indirect_opcode(handler)) {
9684 table = ind_table(handler);
9685 /* opc3 is 5 bits long */
9686 for (opc3 = 0; opc3 < 0x20; opc3++) {
9687 handler = table[opc3];
9688 if (handler->handler != &gen_invalid) {
9689 /* Special hack to properly dump SPE insns */
9690 p = strchr(handler->oname, '_');
9691 if (p == NULL) {
9692 printf("INSN: %02x %02x %02x (%02d %04d) : "
9693 "%s\n",
9694 opc1, opc2, opc3, opc1,
9695 (opc3 << 5) | opc2,
9696 handler->oname);
9697 } else {
9698 q = "speundef";
9699 if ((p - handler->oname) != strlen(q) ||
9700 memcmp(handler->oname, q, strlen(q)) != 0) {
9701 /* First instruction */
9702 printf("INSN: %02x %02x %02x (%02d %04d) : "
9703 "%.*s\n",
9704 opc1, opc2 << 1, opc3, opc1,
9705 (opc3 << 6) | (opc2 << 1),
9706 (int)(p - handler->oname),
9707 handler->oname);
9708 }
9709 if (strcmp(p + 1, q) != 0) {
9710 /* Second instruction */
9711 printf("INSN: %02x %02x %02x (%02d %04d) : "
9712 "%s\n",
9713 opc1, (opc2 << 1) | 1, opc3, opc1,
9714 (opc3 << 6) | (opc2 << 1) | 1,
9715 p + 1);
9716 }
9717 }
9718 }
9719 }
9720 } else {
9721 if (handler->handler != &gen_invalid) {
9722 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9723 opc1, opc2, opc1, opc2, handler->oname);
9724 }
9725 }
9726 }
9727 } else {
9728 if (handler->handler != &gen_invalid) {
9729 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9730 opc1, opc1, handler->oname);
9731 }
9732 }
9733 }
9734 }
9735 #endif
9736
9737 static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9738 {
9739 if (n < 32) {
9740 stfq_p(mem_buf, env->fpr[n]);
9741 return 8;
9742 }
9743 if (n == 32) {
9744 stl_p(mem_buf, env->fpscr);
9745 return 4;
9746 }
9747 return 0;
9748 }
9749
9750 static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9751 {
9752 if (n < 32) {
9753 env->fpr[n] = ldfq_p(mem_buf);
9754 return 8;
9755 }
9756 if (n == 32) {
9757 /* FPSCR not implemented */
9758 return 4;
9759 }
9760 return 0;
9761 }
9762
9763 static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9764 {
9765 if (n < 32) {
9766 #ifdef HOST_WORDS_BIGENDIAN
9767 stq_p(mem_buf, env->avr[n].u64[0]);
9768 stq_p(mem_buf+8, env->avr[n].u64[1]);
9769 #else
9770 stq_p(mem_buf, env->avr[n].u64[1]);
9771 stq_p(mem_buf+8, env->avr[n].u64[0]);
9772 #endif
9773 return 16;
9774 }
9775 if (n == 32) {
9776 stl_p(mem_buf, env->vscr);
9777 return 4;
9778 }
9779 if (n == 33) {
9780 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9781 return 4;
9782 }
9783 return 0;
9784 }
9785
9786 static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9787 {
9788 if (n < 32) {
9789 #ifdef HOST_WORDS_BIGENDIAN
9790 env->avr[n].u64[0] = ldq_p(mem_buf);
9791 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9792 #else
9793 env->avr[n].u64[1] = ldq_p(mem_buf);
9794 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9795 #endif
9796 return 16;
9797 }
9798 if (n == 32) {
9799 env->vscr = ldl_p(mem_buf);
9800 return 4;
9801 }
9802 if (n == 33) {
9803 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9804 return 4;
9805 }
9806 return 0;
9807 }
9808
9809 static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9810 {
9811 if (n < 32) {
9812 #if defined(TARGET_PPC64)
9813 stl_p(mem_buf, env->gpr[n] >> 32);
9814 #else
9815 stl_p(mem_buf, env->gprh[n]);
9816 #endif
9817 return 4;
9818 }
9819 if (n == 32) {
9820 stq_p(mem_buf, env->spe_acc);
9821 return 8;
9822 }
9823 if (n == 33) {
9824 stl_p(mem_buf, env->spe_fscr);
9825 return 4;
9826 }
9827 return 0;
9828 }
9829
9830 static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9831 {
9832 if (n < 32) {
9833 #if defined(TARGET_PPC64)
9834 target_ulong lo = (uint32_t)env->gpr[n];
9835 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9836 env->gpr[n] = lo | hi;
9837 #else
9838 env->gprh[n] = ldl_p(mem_buf);
9839 #endif
9840 return 4;
9841 }
9842 if (n == 32) {
9843 env->spe_acc = ldq_p(mem_buf);
9844 return 8;
9845 }
9846 if (n == 33) {
9847 env->spe_fscr = ldl_p(mem_buf);
9848 return 4;
9849 }
9850 return 0;
9851 }
9852
9853 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
9854 {
9855 env->msr_mask = def->msr_mask;
9856 env->mmu_model = def->mmu_model;
9857 env->excp_model = def->excp_model;
9858 env->bus_model = def->bus_model;
9859 env->insns_flags = def->insns_flags;
9860 env->insns_flags2 = def->insns_flags2;
9861 env->flags = def->flags;
9862 env->bfd_mach = def->bfd_mach;
9863 env->check_pow = def->check_pow;
9864 if (create_ppc_opcodes(env, def) < 0)
9865 return -1;
9866 init_ppc_proc(env, def);
9867
9868 if (def->insns_flags & PPC_FLOAT) {
9869 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9870 33, "power-fpu.xml", 0);
9871 }
9872 if (def->insns_flags & PPC_ALTIVEC) {
9873 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9874 34, "power-altivec.xml", 0);
9875 }
9876 if (def->insns_flags & PPC_SPE) {
9877 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
9878 34, "power-spe.xml", 0);
9879 }
9880
9881 #if defined(PPC_DUMP_CPU)
9882 {
9883 const char *mmu_model, *excp_model, *bus_model;
9884 switch (env->mmu_model) {
9885 case POWERPC_MMU_32B:
9886 mmu_model = "PowerPC 32";
9887 break;
9888 case POWERPC_MMU_SOFT_6xx:
9889 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9890 break;
9891 case POWERPC_MMU_SOFT_74xx:
9892 mmu_model = "PowerPC 74xx with software driven TLBs";
9893 break;
9894 case POWERPC_MMU_SOFT_4xx:
9895 mmu_model = "PowerPC 4xx with software driven TLBs";
9896 break;
9897 case POWERPC_MMU_SOFT_4xx_Z:
9898 mmu_model = "PowerPC 4xx with software driven TLBs "
9899 "and zones protections";
9900 break;
9901 case POWERPC_MMU_REAL:
9902 mmu_model = "PowerPC real mode only";
9903 break;
9904 case POWERPC_MMU_MPC8xx:
9905 mmu_model = "PowerPC MPC8xx";
9906 break;
9907 case POWERPC_MMU_BOOKE:
9908 mmu_model = "PowerPC BookE";
9909 break;
9910 case POWERPC_MMU_BOOKE206:
9911 mmu_model = "PowerPC BookE 2.06";
9912 break;
9913 case POWERPC_MMU_601:
9914 mmu_model = "PowerPC 601";
9915 break;
9916 #if defined (TARGET_PPC64)
9917 case POWERPC_MMU_64B:
9918 mmu_model = "PowerPC 64";
9919 break;
9920 case POWERPC_MMU_620:
9921 mmu_model = "PowerPC 620";
9922 break;
9923 #endif
9924 default:
9925 mmu_model = "Unknown or invalid";
9926 break;
9927 }
9928 switch (env->excp_model) {
9929 case POWERPC_EXCP_STD:
9930 excp_model = "PowerPC";
9931 break;
9932 case POWERPC_EXCP_40x:
9933 excp_model = "PowerPC 40x";
9934 break;
9935 case POWERPC_EXCP_601:
9936 excp_model = "PowerPC 601";
9937 break;
9938 case POWERPC_EXCP_602:
9939 excp_model = "PowerPC 602";
9940 break;
9941 case POWERPC_EXCP_603:
9942 excp_model = "PowerPC 603";
9943 break;
9944 case POWERPC_EXCP_603E:
9945 excp_model = "PowerPC 603e";
9946 break;
9947 case POWERPC_EXCP_604:
9948 excp_model = "PowerPC 604";
9949 break;
9950 case POWERPC_EXCP_7x0:
9951 excp_model = "PowerPC 740/750";
9952 break;
9953 case POWERPC_EXCP_7x5:
9954 excp_model = "PowerPC 745/755";
9955 break;
9956 case POWERPC_EXCP_74xx:
9957 excp_model = "PowerPC 74xx";
9958 break;
9959 case POWERPC_EXCP_BOOKE:
9960 excp_model = "PowerPC BookE";
9961 break;
9962 #if defined (TARGET_PPC64)
9963 case POWERPC_EXCP_970:
9964 excp_model = "PowerPC 970";
9965 break;
9966 #endif
9967 default:
9968 excp_model = "Unknown or invalid";
9969 break;
9970 }
9971 switch (env->bus_model) {
9972 case PPC_FLAGS_INPUT_6xx:
9973 bus_model = "PowerPC 6xx";
9974 break;
9975 case PPC_FLAGS_INPUT_BookE:
9976 bus_model = "PowerPC BookE";
9977 break;
9978 case PPC_FLAGS_INPUT_405:
9979 bus_model = "PowerPC 405";
9980 break;
9981 case PPC_FLAGS_INPUT_401:
9982 bus_model = "PowerPC 401/403";
9983 break;
9984 case PPC_FLAGS_INPUT_RCPU:
9985 bus_model = "RCPU / MPC8xx";
9986 break;
9987 #if defined (TARGET_PPC64)
9988 case PPC_FLAGS_INPUT_970:
9989 bus_model = "PowerPC 970";
9990 break;
9991 #endif
9992 default:
9993 bus_model = "Unknown or invalid";
9994 break;
9995 }
9996 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9997 " MMU model : %s\n",
9998 def->name, def->pvr, def->msr_mask, mmu_model);
9999 #if !defined(CONFIG_USER_ONLY)
10000 if (env->tlb != NULL) {
10001 printf(" %d %s TLB in %d ways\n",
10002 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
10003 env->nb_ways);
10004 }
10005 #endif
10006 printf(" Exceptions model : %s\n"
10007 " Bus model : %s\n",
10008 excp_model, bus_model);
10009 printf(" MSR features :\n");
10010 if (env->flags & POWERPC_FLAG_SPE)
10011 printf(" signal processing engine enable"
10012 "\n");
10013 else if (env->flags & POWERPC_FLAG_VRE)
10014 printf(" vector processor enable\n");
10015 if (env->flags & POWERPC_FLAG_TGPR)
10016 printf(" temporary GPRs\n");
10017 else if (env->flags & POWERPC_FLAG_CE)
10018 printf(" critical input enable\n");
10019 if (env->flags & POWERPC_FLAG_SE)
10020 printf(" single-step trace mode\n");
10021 else if (env->flags & POWERPC_FLAG_DWE)
10022 printf(" debug wait enable\n");
10023 else if (env->flags & POWERPC_FLAG_UBLE)
10024 printf(" user BTB lock enable\n");
10025 if (env->flags & POWERPC_FLAG_BE)
10026 printf(" branch-step trace mode\n");
10027 else if (env->flags & POWERPC_FLAG_DE)
10028 printf(" debug interrupt enable\n");
10029 if (env->flags & POWERPC_FLAG_PX)
10030 printf(" inclusive protection\n");
10031 else if (env->flags & POWERPC_FLAG_PMM)
10032 printf(" performance monitor mark\n");
10033 if (env->flags == POWERPC_FLAG_NONE)
10034 printf(" none\n");
10035 printf(" Time-base/decrementer clock source: %s\n",
10036 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
10037 }
10038 dump_ppc_insns(env);
10039 dump_ppc_sprs(env);
10040 fflush(stdout);
10041 #endif
10042
10043 return 0;
10044 }
10045
10046 const ppc_def_t *ppc_find_by_pvr(uint32_t pvr)
10047 {
10048 int i;
10049
10050 for (i = 0; i < ARRAY_SIZE(ppc_defs); i++) {
10051 /* If we have an exact match, we're done */
10052 if (pvr == ppc_defs[i].pvr) {
10053 return &ppc_defs[i];
10054 }
10055 }
10056
10057 return NULL;
10058 }
10059
10060 #include <ctype.h>
10061
10062 const ppc_def_t *cpu_ppc_find_by_name (const char *name)
10063 {
10064 const ppc_def_t *ret;
10065 const char *p;
10066 int i, max, len;
10067
10068 if (kvm_enabled() && (strcasecmp(name, "host") == 0)) {
10069 return kvmppc_host_cpu_def();
10070 }
10071
10072 /* Check if the given name is a PVR */
10073 len = strlen(name);
10074 if (len == 10 && name[0] == '0' && name[1] == 'x') {
10075 p = name + 2;
10076 goto check_pvr;
10077 } else if (len == 8) {
10078 p = name;
10079 check_pvr:
10080 for (i = 0; i < 8; i++) {
10081 if (!qemu_isxdigit(*p++))
10082 break;
10083 }
10084 if (i == 8)
10085 return ppc_find_by_pvr(strtoul(name, NULL, 16));
10086 }
10087 ret = NULL;
10088 max = ARRAY_SIZE(ppc_defs);
10089 for (i = 0; i < max; i++) {
10090 if (strcasecmp(name, ppc_defs[i].name) == 0) {
10091 ret = &ppc_defs[i];
10092 break;
10093 }
10094 }
10095
10096 return ret;
10097 }
10098
10099 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
10100 {
10101 int i, max;
10102
10103 max = ARRAY_SIZE(ppc_defs);
10104 for (i = 0; i < max; i++) {
10105 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
10106 ppc_defs[i].name, ppc_defs[i].pvr);
10107 }
10108 }
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