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PPC: Enable 440EP CPU target
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1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
26 #include "dis-asm.h"
27 #include "gdbstub.h"
28 #include <kvm.h>
29 #include "kvm_ppc.h"
30
31 //#define PPC_DUMP_CPU
32 //#define PPC_DEBUG_SPR
33 //#define PPC_DUMP_SPR_ACCESSES
34 #if defined(CONFIG_USER_ONLY)
35 #define TODO_USER_ONLY 1
36 #endif
37
38 /* For user-mode emulation, we don't emulate any IRQ controller */
39 #if defined(CONFIG_USER_ONLY)
40 #define PPC_IRQ_INIT_FN(name) \
41 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
42 { \
43 }
44 #else
45 #define PPC_IRQ_INIT_FN(name) \
46 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
47 #endif
48
49 PPC_IRQ_INIT_FN(40x);
50 PPC_IRQ_INIT_FN(6xx);
51 PPC_IRQ_INIT_FN(970);
52 PPC_IRQ_INIT_FN(POWER7);
53 PPC_IRQ_INIT_FN(e500);
54
55 /* Generic callbacks:
56 * do nothing but store/retrieve spr value
57 */
58 static void spr_read_generic (void *opaque, int gprn, int sprn)
59 {
60 gen_load_spr(cpu_gpr[gprn], sprn);
61 #ifdef PPC_DUMP_SPR_ACCESSES
62 {
63 TCGv_i32 t0 = tcg_const_i32(sprn);
64 gen_helper_load_dump_spr(t0);
65 tcg_temp_free_i32(t0);
66 }
67 #endif
68 }
69
70 static void spr_write_generic (void *opaque, int sprn, int gprn)
71 {
72 gen_store_spr(sprn, cpu_gpr[gprn]);
73 #ifdef PPC_DUMP_SPR_ACCESSES
74 {
75 TCGv_i32 t0 = tcg_const_i32(sprn);
76 gen_helper_store_dump_spr(t0);
77 tcg_temp_free_i32(t0);
78 }
79 #endif
80 }
81
82 #if !defined(CONFIG_USER_ONLY)
83 static void spr_write_clear (void *opaque, int sprn, int gprn)
84 {
85 TCGv t0 = tcg_temp_new();
86 TCGv t1 = tcg_temp_new();
87 gen_load_spr(t0, sprn);
88 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
89 tcg_gen_and_tl(t0, t0, t1);
90 gen_store_spr(sprn, t0);
91 tcg_temp_free(t0);
92 tcg_temp_free(t1);
93 }
94 #endif
95
96 /* SPR common to all PowerPC */
97 /* XER */
98 static void spr_read_xer (void *opaque, int gprn, int sprn)
99 {
100 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
101 }
102
103 static void spr_write_xer (void *opaque, int sprn, int gprn)
104 {
105 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
106 }
107
108 /* LR */
109 static void spr_read_lr (void *opaque, int gprn, int sprn)
110 {
111 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
112 }
113
114 static void spr_write_lr (void *opaque, int sprn, int gprn)
115 {
116 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
117 }
118
119 /* CFAR */
120 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
121 static void spr_read_cfar (void *opaque, int gprn, int sprn)
122 {
123 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
124 }
125
126 static void spr_write_cfar (void *opaque, int sprn, int gprn)
127 {
128 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
129 }
130 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
131
132 /* CTR */
133 static void spr_read_ctr (void *opaque, int gprn, int sprn)
134 {
135 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
136 }
137
138 static void spr_write_ctr (void *opaque, int sprn, int gprn)
139 {
140 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
141 }
142
143 /* User read access to SPR */
144 /* USPRx */
145 /* UMMCRx */
146 /* UPMCx */
147 /* USIA */
148 /* UDECR */
149 static void spr_read_ureg (void *opaque, int gprn, int sprn)
150 {
151 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
152 }
153
154 /* SPR common to all non-embedded PowerPC */
155 /* DECR */
156 #if !defined(CONFIG_USER_ONLY)
157 static void spr_read_decr (void *opaque, int gprn, int sprn)
158 {
159 if (use_icount) {
160 gen_io_start();
161 }
162 gen_helper_load_decr(cpu_gpr[gprn]);
163 if (use_icount) {
164 gen_io_end();
165 gen_stop_exception(opaque);
166 }
167 }
168
169 static void spr_write_decr (void *opaque, int sprn, int gprn)
170 {
171 if (use_icount) {
172 gen_io_start();
173 }
174 gen_helper_store_decr(cpu_gpr[gprn]);
175 if (use_icount) {
176 gen_io_end();
177 gen_stop_exception(opaque);
178 }
179 }
180 #endif
181
182 /* SPR common to all non-embedded PowerPC, except 601 */
183 /* Time base */
184 static void spr_read_tbl (void *opaque, int gprn, int sprn)
185 {
186 if (use_icount) {
187 gen_io_start();
188 }
189 gen_helper_load_tbl(cpu_gpr[gprn]);
190 if (use_icount) {
191 gen_io_end();
192 gen_stop_exception(opaque);
193 }
194 }
195
196 static void spr_read_tbu (void *opaque, int gprn, int sprn)
197 {
198 if (use_icount) {
199 gen_io_start();
200 }
201 gen_helper_load_tbu(cpu_gpr[gprn]);
202 if (use_icount) {
203 gen_io_end();
204 gen_stop_exception(opaque);
205 }
206 }
207
208 __attribute__ (( unused ))
209 static void spr_read_atbl (void *opaque, int gprn, int sprn)
210 {
211 gen_helper_load_atbl(cpu_gpr[gprn]);
212 }
213
214 __attribute__ (( unused ))
215 static void spr_read_atbu (void *opaque, int gprn, int sprn)
216 {
217 gen_helper_load_atbu(cpu_gpr[gprn]);
218 }
219
220 #if !defined(CONFIG_USER_ONLY)
221 static void spr_write_tbl (void *opaque, int sprn, int gprn)
222 {
223 if (use_icount) {
224 gen_io_start();
225 }
226 gen_helper_store_tbl(cpu_gpr[gprn]);
227 if (use_icount) {
228 gen_io_end();
229 gen_stop_exception(opaque);
230 }
231 }
232
233 static void spr_write_tbu (void *opaque, int sprn, int gprn)
234 {
235 if (use_icount) {
236 gen_io_start();
237 }
238 gen_helper_store_tbu(cpu_gpr[gprn]);
239 if (use_icount) {
240 gen_io_end();
241 gen_stop_exception(opaque);
242 }
243 }
244
245 __attribute__ (( unused ))
246 static void spr_write_atbl (void *opaque, int sprn, int gprn)
247 {
248 gen_helper_store_atbl(cpu_gpr[gprn]);
249 }
250
251 __attribute__ (( unused ))
252 static void spr_write_atbu (void *opaque, int sprn, int gprn)
253 {
254 gen_helper_store_atbu(cpu_gpr[gprn]);
255 }
256
257 #if defined(TARGET_PPC64)
258 __attribute__ (( unused ))
259 static void spr_read_purr (void *opaque, int gprn, int sprn)
260 {
261 gen_helper_load_purr(cpu_gpr[gprn]);
262 }
263 #endif
264 #endif
265
266 #if !defined(CONFIG_USER_ONLY)
267 /* IBAT0U...IBAT0U */
268 /* IBAT0L...IBAT7L */
269 static void spr_read_ibat (void *opaque, int gprn, int sprn)
270 {
271 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
272 }
273
274 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
275 {
276 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
277 }
278
279 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
280 {
281 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
282 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
283 tcg_temp_free_i32(t0);
284 }
285
286 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
287 {
288 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
289 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
290 tcg_temp_free_i32(t0);
291 }
292
293 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
294 {
295 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
296 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
297 tcg_temp_free_i32(t0);
298 }
299
300 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
301 {
302 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
303 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
304 tcg_temp_free_i32(t0);
305 }
306
307 /* DBAT0U...DBAT7U */
308 /* DBAT0L...DBAT7L */
309 static void spr_read_dbat (void *opaque, int gprn, int sprn)
310 {
311 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
312 }
313
314 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
315 {
316 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
317 }
318
319 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
320 {
321 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
322 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
323 tcg_temp_free_i32(t0);
324 }
325
326 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
327 {
328 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
329 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
330 tcg_temp_free_i32(t0);
331 }
332
333 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
334 {
335 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
336 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
337 tcg_temp_free_i32(t0);
338 }
339
340 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
341 {
342 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
343 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
344 tcg_temp_free_i32(t0);
345 }
346
347 /* SDR1 */
348 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
349 {
350 gen_helper_store_sdr1(cpu_gpr[gprn]);
351 }
352
353 /* 64 bits PowerPC specific SPRs */
354 /* ASR */
355 #if defined(TARGET_PPC64)
356 static void spr_read_hior (void *opaque, int gprn, int sprn)
357 {
358 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
359 }
360
361 static void spr_write_hior (void *opaque, int sprn, int gprn)
362 {
363 TCGv t0 = tcg_temp_new();
364 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
365 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
366 tcg_temp_free(t0);
367 }
368
369 static void spr_read_asr (void *opaque, int gprn, int sprn)
370 {
371 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
372 }
373
374 static void spr_write_asr (void *opaque, int sprn, int gprn)
375 {
376 gen_helper_store_asr(cpu_gpr[gprn]);
377 }
378 #endif
379 #endif
380
381 /* PowerPC 601 specific registers */
382 /* RTC */
383 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
384 {
385 gen_helper_load_601_rtcl(cpu_gpr[gprn]);
386 }
387
388 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
389 {
390 gen_helper_load_601_rtcu(cpu_gpr[gprn]);
391 }
392
393 #if !defined(CONFIG_USER_ONLY)
394 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
395 {
396 gen_helper_store_601_rtcu(cpu_gpr[gprn]);
397 }
398
399 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
400 {
401 gen_helper_store_601_rtcl(cpu_gpr[gprn]);
402 }
403
404 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
405 {
406 DisasContext *ctx = opaque;
407
408 gen_helper_store_hid0_601(cpu_gpr[gprn]);
409 /* Must stop the translation as endianness may have changed */
410 gen_stop_exception(ctx);
411 }
412 #endif
413
414 /* Unified bats */
415 #if !defined(CONFIG_USER_ONLY)
416 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
417 {
418 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
419 }
420
421 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
422 {
423 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
424 gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
425 tcg_temp_free_i32(t0);
426 }
427
428 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
429 {
430 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
431 gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
432 tcg_temp_free_i32(t0);
433 }
434 #endif
435
436 /* PowerPC 40x specific registers */
437 #if !defined(CONFIG_USER_ONLY)
438 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
439 {
440 gen_helper_load_40x_pit(cpu_gpr[gprn]);
441 }
442
443 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
444 {
445 gen_helper_store_40x_pit(cpu_gpr[gprn]);
446 }
447
448 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
449 {
450 DisasContext *ctx = opaque;
451
452 gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
453 /* We must stop translation as we may have rebooted */
454 gen_stop_exception(ctx);
455 }
456
457 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
458 {
459 gen_helper_store_40x_sler(cpu_gpr[gprn]);
460 }
461
462 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
463 {
464 gen_helper_store_booke_tcr(cpu_gpr[gprn]);
465 }
466
467 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
468 {
469 gen_helper_store_booke_tsr(cpu_gpr[gprn]);
470 }
471 #endif
472
473 /* PowerPC 403 specific registers */
474 /* PBL1 / PBU1 / PBL2 / PBU2 */
475 #if !defined(CONFIG_USER_ONLY)
476 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
477 {
478 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
479 }
480
481 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
482 {
483 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
484 gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
485 tcg_temp_free_i32(t0);
486 }
487
488 static void spr_write_pir (void *opaque, int sprn, int gprn)
489 {
490 TCGv t0 = tcg_temp_new();
491 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
492 gen_store_spr(SPR_PIR, t0);
493 tcg_temp_free(t0);
494 }
495 #endif
496
497 /* SPE specific registers */
498 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
499 {
500 TCGv_i32 t0 = tcg_temp_new_i32();
501 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
502 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
503 tcg_temp_free_i32(t0);
504 }
505
506 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
507 {
508 TCGv_i32 t0 = tcg_temp_new_i32();
509 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
510 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
511 tcg_temp_free_i32(t0);
512 }
513
514 #if !defined(CONFIG_USER_ONLY)
515 /* Callback used to write the exception vector base */
516 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
517 {
518 TCGv t0 = tcg_temp_new();
519 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
520 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
521 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
522 gen_store_spr(sprn, t0);
523 tcg_temp_free(t0);
524 }
525
526 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
527 {
528 DisasContext *ctx = opaque;
529
530 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
531 TCGv t0 = tcg_temp_new();
532 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
533 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
534 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
535 gen_store_spr(sprn, t0);
536 tcg_temp_free(t0);
537 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
538 TCGv t0 = tcg_temp_new();
539 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
540 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
541 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
542 gen_store_spr(sprn, t0);
543 tcg_temp_free(t0);
544 } else {
545 printf("Trying to write an unknown exception vector %d %03x\n",
546 sprn, sprn);
547 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
548 }
549 }
550 #endif
551
552 static inline void vscr_init (CPUPPCState *env, uint32_t val)
553 {
554 env->vscr = val;
555 /* Altivec always uses round-to-nearest */
556 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
557 set_flush_to_zero(vscr_nj, &env->vec_status);
558 }
559
560 #if defined(CONFIG_USER_ONLY)
561 #define spr_register(env, num, name, uea_read, uea_write, \
562 oea_read, oea_write, initial_value) \
563 do { \
564 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
565 } while (0)
566 static inline void _spr_register (CPUPPCState *env, int num,
567 const char *name,
568 void (*uea_read)(void *opaque, int gprn, int sprn),
569 void (*uea_write)(void *opaque, int sprn, int gprn),
570 target_ulong initial_value)
571 #else
572 static inline void spr_register (CPUPPCState *env, int num,
573 const char *name,
574 void (*uea_read)(void *opaque, int gprn, int sprn),
575 void (*uea_write)(void *opaque, int sprn, int gprn),
576 void (*oea_read)(void *opaque, int gprn, int sprn),
577 void (*oea_write)(void *opaque, int sprn, int gprn),
578 target_ulong initial_value)
579 #endif
580 {
581 ppc_spr_t *spr;
582
583 spr = &env->spr_cb[num];
584 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
585 #if !defined(CONFIG_USER_ONLY)
586 spr->oea_read != NULL || spr->oea_write != NULL ||
587 #endif
588 spr->uea_read != NULL || spr->uea_write != NULL) {
589 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
590 exit(1);
591 }
592 #if defined(PPC_DEBUG_SPR)
593 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
594 name, initial_value);
595 #endif
596 spr->name = name;
597 spr->uea_read = uea_read;
598 spr->uea_write = uea_write;
599 #if !defined(CONFIG_USER_ONLY)
600 spr->oea_read = oea_read;
601 spr->oea_write = oea_write;
602 #endif
603 env->spr[num] = initial_value;
604 }
605
606 /* Generic PowerPC SPRs */
607 static void gen_spr_generic (CPUPPCState *env)
608 {
609 /* Integer processing */
610 spr_register(env, SPR_XER, "XER",
611 &spr_read_xer, &spr_write_xer,
612 &spr_read_xer, &spr_write_xer,
613 0x00000000);
614 /* Branch contol */
615 spr_register(env, SPR_LR, "LR",
616 &spr_read_lr, &spr_write_lr,
617 &spr_read_lr, &spr_write_lr,
618 0x00000000);
619 spr_register(env, SPR_CTR, "CTR",
620 &spr_read_ctr, &spr_write_ctr,
621 &spr_read_ctr, &spr_write_ctr,
622 0x00000000);
623 /* Interrupt processing */
624 spr_register(env, SPR_SRR0, "SRR0",
625 SPR_NOACCESS, SPR_NOACCESS,
626 &spr_read_generic, &spr_write_generic,
627 0x00000000);
628 spr_register(env, SPR_SRR1, "SRR1",
629 SPR_NOACCESS, SPR_NOACCESS,
630 &spr_read_generic, &spr_write_generic,
631 0x00000000);
632 /* Processor control */
633 spr_register(env, SPR_SPRG0, "SPRG0",
634 SPR_NOACCESS, SPR_NOACCESS,
635 &spr_read_generic, &spr_write_generic,
636 0x00000000);
637 spr_register(env, SPR_SPRG1, "SPRG1",
638 SPR_NOACCESS, SPR_NOACCESS,
639 &spr_read_generic, &spr_write_generic,
640 0x00000000);
641 spr_register(env, SPR_SPRG2, "SPRG2",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_generic, &spr_write_generic,
644 0x00000000);
645 spr_register(env, SPR_SPRG3, "SPRG3",
646 SPR_NOACCESS, SPR_NOACCESS,
647 &spr_read_generic, &spr_write_generic,
648 0x00000000);
649 }
650
651 /* SPR common to all non-embedded PowerPC, including 601 */
652 static void gen_spr_ne_601 (CPUPPCState *env)
653 {
654 /* Exception processing */
655 spr_register(env, SPR_DSISR, "DSISR",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, &spr_write_generic,
658 0x00000000);
659 spr_register(env, SPR_DAR, "DAR",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, &spr_write_generic,
662 0x00000000);
663 /* Timer */
664 spr_register(env, SPR_DECR, "DECR",
665 SPR_NOACCESS, SPR_NOACCESS,
666 &spr_read_decr, &spr_write_decr,
667 0x00000000);
668 /* Memory management */
669 spr_register(env, SPR_SDR1, "SDR1",
670 SPR_NOACCESS, SPR_NOACCESS,
671 &spr_read_generic, &spr_write_sdr1,
672 0x00000000);
673 }
674
675 /* BATs 0-3 */
676 static void gen_low_BATs (CPUPPCState *env)
677 {
678 #if !defined(CONFIG_USER_ONLY)
679 spr_register(env, SPR_IBAT0U, "IBAT0U",
680 SPR_NOACCESS, SPR_NOACCESS,
681 &spr_read_ibat, &spr_write_ibatu,
682 0x00000000);
683 spr_register(env, SPR_IBAT0L, "IBAT0L",
684 SPR_NOACCESS, SPR_NOACCESS,
685 &spr_read_ibat, &spr_write_ibatl,
686 0x00000000);
687 spr_register(env, SPR_IBAT1U, "IBAT1U",
688 SPR_NOACCESS, SPR_NOACCESS,
689 &spr_read_ibat, &spr_write_ibatu,
690 0x00000000);
691 spr_register(env, SPR_IBAT1L, "IBAT1L",
692 SPR_NOACCESS, SPR_NOACCESS,
693 &spr_read_ibat, &spr_write_ibatl,
694 0x00000000);
695 spr_register(env, SPR_IBAT2U, "IBAT2U",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_ibat, &spr_write_ibatu,
698 0x00000000);
699 spr_register(env, SPR_IBAT2L, "IBAT2L",
700 SPR_NOACCESS, SPR_NOACCESS,
701 &spr_read_ibat, &spr_write_ibatl,
702 0x00000000);
703 spr_register(env, SPR_IBAT3U, "IBAT3U",
704 SPR_NOACCESS, SPR_NOACCESS,
705 &spr_read_ibat, &spr_write_ibatu,
706 0x00000000);
707 spr_register(env, SPR_IBAT3L, "IBAT3L",
708 SPR_NOACCESS, SPR_NOACCESS,
709 &spr_read_ibat, &spr_write_ibatl,
710 0x00000000);
711 spr_register(env, SPR_DBAT0U, "DBAT0U",
712 SPR_NOACCESS, SPR_NOACCESS,
713 &spr_read_dbat, &spr_write_dbatu,
714 0x00000000);
715 spr_register(env, SPR_DBAT0L, "DBAT0L",
716 SPR_NOACCESS, SPR_NOACCESS,
717 &spr_read_dbat, &spr_write_dbatl,
718 0x00000000);
719 spr_register(env, SPR_DBAT1U, "DBAT1U",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_dbat, &spr_write_dbatu,
722 0x00000000);
723 spr_register(env, SPR_DBAT1L, "DBAT1L",
724 SPR_NOACCESS, SPR_NOACCESS,
725 &spr_read_dbat, &spr_write_dbatl,
726 0x00000000);
727 spr_register(env, SPR_DBAT2U, "DBAT2U",
728 SPR_NOACCESS, SPR_NOACCESS,
729 &spr_read_dbat, &spr_write_dbatu,
730 0x00000000);
731 spr_register(env, SPR_DBAT2L, "DBAT2L",
732 SPR_NOACCESS, SPR_NOACCESS,
733 &spr_read_dbat, &spr_write_dbatl,
734 0x00000000);
735 spr_register(env, SPR_DBAT3U, "DBAT3U",
736 SPR_NOACCESS, SPR_NOACCESS,
737 &spr_read_dbat, &spr_write_dbatu,
738 0x00000000);
739 spr_register(env, SPR_DBAT3L, "DBAT3L",
740 SPR_NOACCESS, SPR_NOACCESS,
741 &spr_read_dbat, &spr_write_dbatl,
742 0x00000000);
743 env->nb_BATs += 4;
744 #endif
745 }
746
747 /* BATs 4-7 */
748 static void gen_high_BATs (CPUPPCState *env)
749 {
750 #if !defined(CONFIG_USER_ONLY)
751 spr_register(env, SPR_IBAT4U, "IBAT4U",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_ibat_h, &spr_write_ibatu_h,
754 0x00000000);
755 spr_register(env, SPR_IBAT4L, "IBAT4L",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_ibat_h, &spr_write_ibatl_h,
758 0x00000000);
759 spr_register(env, SPR_IBAT5U, "IBAT5U",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_ibat_h, &spr_write_ibatu_h,
762 0x00000000);
763 spr_register(env, SPR_IBAT5L, "IBAT5L",
764 SPR_NOACCESS, SPR_NOACCESS,
765 &spr_read_ibat_h, &spr_write_ibatl_h,
766 0x00000000);
767 spr_register(env, SPR_IBAT6U, "IBAT6U",
768 SPR_NOACCESS, SPR_NOACCESS,
769 &spr_read_ibat_h, &spr_write_ibatu_h,
770 0x00000000);
771 spr_register(env, SPR_IBAT6L, "IBAT6L",
772 SPR_NOACCESS, SPR_NOACCESS,
773 &spr_read_ibat_h, &spr_write_ibatl_h,
774 0x00000000);
775 spr_register(env, SPR_IBAT7U, "IBAT7U",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_ibat_h, &spr_write_ibatu_h,
778 0x00000000);
779 spr_register(env, SPR_IBAT7L, "IBAT7L",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_ibat_h, &spr_write_ibatl_h,
782 0x00000000);
783 spr_register(env, SPR_DBAT4U, "DBAT4U",
784 SPR_NOACCESS, SPR_NOACCESS,
785 &spr_read_dbat_h, &spr_write_dbatu_h,
786 0x00000000);
787 spr_register(env, SPR_DBAT4L, "DBAT4L",
788 SPR_NOACCESS, SPR_NOACCESS,
789 &spr_read_dbat_h, &spr_write_dbatl_h,
790 0x00000000);
791 spr_register(env, SPR_DBAT5U, "DBAT5U",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_dbat_h, &spr_write_dbatu_h,
794 0x00000000);
795 spr_register(env, SPR_DBAT5L, "DBAT5L",
796 SPR_NOACCESS, SPR_NOACCESS,
797 &spr_read_dbat_h, &spr_write_dbatl_h,
798 0x00000000);
799 spr_register(env, SPR_DBAT6U, "DBAT6U",
800 SPR_NOACCESS, SPR_NOACCESS,
801 &spr_read_dbat_h, &spr_write_dbatu_h,
802 0x00000000);
803 spr_register(env, SPR_DBAT6L, "DBAT6L",
804 SPR_NOACCESS, SPR_NOACCESS,
805 &spr_read_dbat_h, &spr_write_dbatl_h,
806 0x00000000);
807 spr_register(env, SPR_DBAT7U, "DBAT7U",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_dbat_h, &spr_write_dbatu_h,
810 0x00000000);
811 spr_register(env, SPR_DBAT7L, "DBAT7L",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_dbat_h, &spr_write_dbatl_h,
814 0x00000000);
815 env->nb_BATs += 4;
816 #endif
817 }
818
819 /* Generic PowerPC time base */
820 static void gen_tbl (CPUPPCState *env)
821 {
822 spr_register(env, SPR_VTBL, "TBL",
823 &spr_read_tbl, SPR_NOACCESS,
824 &spr_read_tbl, SPR_NOACCESS,
825 0x00000000);
826 spr_register(env, SPR_TBL, "TBL",
827 &spr_read_tbl, SPR_NOACCESS,
828 &spr_read_tbl, &spr_write_tbl,
829 0x00000000);
830 spr_register(env, SPR_VTBU, "TBU",
831 &spr_read_tbu, SPR_NOACCESS,
832 &spr_read_tbu, SPR_NOACCESS,
833 0x00000000);
834 spr_register(env, SPR_TBU, "TBU",
835 &spr_read_tbu, SPR_NOACCESS,
836 &spr_read_tbu, &spr_write_tbu,
837 0x00000000);
838 }
839
840 /* Softare table search registers */
841 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
842 {
843 #if !defined(CONFIG_USER_ONLY)
844 env->nb_tlb = nb_tlbs;
845 env->nb_ways = nb_ways;
846 env->id_tlbs = 1;
847 env->tlb_type = TLB_6XX;
848 spr_register(env, SPR_DMISS, "DMISS",
849 SPR_NOACCESS, SPR_NOACCESS,
850 &spr_read_generic, SPR_NOACCESS,
851 0x00000000);
852 spr_register(env, SPR_DCMP, "DCMP",
853 SPR_NOACCESS, SPR_NOACCESS,
854 &spr_read_generic, SPR_NOACCESS,
855 0x00000000);
856 spr_register(env, SPR_HASH1, "HASH1",
857 SPR_NOACCESS, SPR_NOACCESS,
858 &spr_read_generic, SPR_NOACCESS,
859 0x00000000);
860 spr_register(env, SPR_HASH2, "HASH2",
861 SPR_NOACCESS, SPR_NOACCESS,
862 &spr_read_generic, SPR_NOACCESS,
863 0x00000000);
864 spr_register(env, SPR_IMISS, "IMISS",
865 SPR_NOACCESS, SPR_NOACCESS,
866 &spr_read_generic, SPR_NOACCESS,
867 0x00000000);
868 spr_register(env, SPR_ICMP, "ICMP",
869 SPR_NOACCESS, SPR_NOACCESS,
870 &spr_read_generic, SPR_NOACCESS,
871 0x00000000);
872 spr_register(env, SPR_RPA, "RPA",
873 SPR_NOACCESS, SPR_NOACCESS,
874 &spr_read_generic, &spr_write_generic,
875 0x00000000);
876 #endif
877 }
878
879 /* SPR common to MPC755 and G2 */
880 static void gen_spr_G2_755 (CPUPPCState *env)
881 {
882 /* SGPRs */
883 spr_register(env, SPR_SPRG4, "SPRG4",
884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_generic, &spr_write_generic,
886 0x00000000);
887 spr_register(env, SPR_SPRG5, "SPRG5",
888 SPR_NOACCESS, SPR_NOACCESS,
889 &spr_read_generic, &spr_write_generic,
890 0x00000000);
891 spr_register(env, SPR_SPRG6, "SPRG6",
892 SPR_NOACCESS, SPR_NOACCESS,
893 &spr_read_generic, &spr_write_generic,
894 0x00000000);
895 spr_register(env, SPR_SPRG7, "SPRG7",
896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_generic, &spr_write_generic,
898 0x00000000);
899 }
900
901 /* SPR common to all 7xx PowerPC implementations */
902 static void gen_spr_7xx (CPUPPCState *env)
903 {
904 /* Breakpoints */
905 /* XXX : not implemented */
906 spr_register(env, SPR_DABR, "DABR",
907 SPR_NOACCESS, SPR_NOACCESS,
908 &spr_read_generic, &spr_write_generic,
909 0x00000000);
910 /* XXX : not implemented */
911 spr_register(env, SPR_IABR, "IABR",
912 SPR_NOACCESS, SPR_NOACCESS,
913 &spr_read_generic, &spr_write_generic,
914 0x00000000);
915 /* Cache management */
916 /* XXX : not implemented */
917 spr_register(env, SPR_ICTC, "ICTC",
918 SPR_NOACCESS, SPR_NOACCESS,
919 &spr_read_generic, &spr_write_generic,
920 0x00000000);
921 /* Performance monitors */
922 /* XXX : not implemented */
923 spr_register(env, SPR_MMCR0, "MMCR0",
924 SPR_NOACCESS, SPR_NOACCESS,
925 &spr_read_generic, &spr_write_generic,
926 0x00000000);
927 /* XXX : not implemented */
928 spr_register(env, SPR_MMCR1, "MMCR1",
929 SPR_NOACCESS, SPR_NOACCESS,
930 &spr_read_generic, &spr_write_generic,
931 0x00000000);
932 /* XXX : not implemented */
933 spr_register(env, SPR_PMC1, "PMC1",
934 SPR_NOACCESS, SPR_NOACCESS,
935 &spr_read_generic, &spr_write_generic,
936 0x00000000);
937 /* XXX : not implemented */
938 spr_register(env, SPR_PMC2, "PMC2",
939 SPR_NOACCESS, SPR_NOACCESS,
940 &spr_read_generic, &spr_write_generic,
941 0x00000000);
942 /* XXX : not implemented */
943 spr_register(env, SPR_PMC3, "PMC3",
944 SPR_NOACCESS, SPR_NOACCESS,
945 &spr_read_generic, &spr_write_generic,
946 0x00000000);
947 /* XXX : not implemented */
948 spr_register(env, SPR_PMC4, "PMC4",
949 SPR_NOACCESS, SPR_NOACCESS,
950 &spr_read_generic, &spr_write_generic,
951 0x00000000);
952 /* XXX : not implemented */
953 spr_register(env, SPR_SIAR, "SIAR",
954 SPR_NOACCESS, SPR_NOACCESS,
955 &spr_read_generic, SPR_NOACCESS,
956 0x00000000);
957 /* XXX : not implemented */
958 spr_register(env, SPR_UMMCR0, "UMMCR0",
959 &spr_read_ureg, SPR_NOACCESS,
960 &spr_read_ureg, SPR_NOACCESS,
961 0x00000000);
962 /* XXX : not implemented */
963 spr_register(env, SPR_UMMCR1, "UMMCR1",
964 &spr_read_ureg, SPR_NOACCESS,
965 &spr_read_ureg, SPR_NOACCESS,
966 0x00000000);
967 /* XXX : not implemented */
968 spr_register(env, SPR_UPMC1, "UPMC1",
969 &spr_read_ureg, SPR_NOACCESS,
970 &spr_read_ureg, SPR_NOACCESS,
971 0x00000000);
972 /* XXX : not implemented */
973 spr_register(env, SPR_UPMC2, "UPMC2",
974 &spr_read_ureg, SPR_NOACCESS,
975 &spr_read_ureg, SPR_NOACCESS,
976 0x00000000);
977 /* XXX : not implemented */
978 spr_register(env, SPR_UPMC3, "UPMC3",
979 &spr_read_ureg, SPR_NOACCESS,
980 &spr_read_ureg, SPR_NOACCESS,
981 0x00000000);
982 /* XXX : not implemented */
983 spr_register(env, SPR_UPMC4, "UPMC4",
984 &spr_read_ureg, SPR_NOACCESS,
985 &spr_read_ureg, SPR_NOACCESS,
986 0x00000000);
987 /* XXX : not implemented */
988 spr_register(env, SPR_USIAR, "USIAR",
989 &spr_read_ureg, SPR_NOACCESS,
990 &spr_read_ureg, SPR_NOACCESS,
991 0x00000000);
992 /* External access control */
993 /* XXX : not implemented */
994 spr_register(env, SPR_EAR, "EAR",
995 SPR_NOACCESS, SPR_NOACCESS,
996 &spr_read_generic, &spr_write_generic,
997 0x00000000);
998 }
999
1000 static void gen_spr_thrm (CPUPPCState *env)
1001 {
1002 /* Thermal management */
1003 /* XXX : not implemented */
1004 spr_register(env, SPR_THRM1, "THRM1",
1005 SPR_NOACCESS, SPR_NOACCESS,
1006 &spr_read_generic, &spr_write_generic,
1007 0x00000000);
1008 /* XXX : not implemented */
1009 spr_register(env, SPR_THRM2, "THRM2",
1010 SPR_NOACCESS, SPR_NOACCESS,
1011 &spr_read_generic, &spr_write_generic,
1012 0x00000000);
1013 /* XXX : not implemented */
1014 spr_register(env, SPR_THRM3, "THRM3",
1015 SPR_NOACCESS, SPR_NOACCESS,
1016 &spr_read_generic, &spr_write_generic,
1017 0x00000000);
1018 }
1019
1020 /* SPR specific to PowerPC 604 implementation */
1021 static void gen_spr_604 (CPUPPCState *env)
1022 {
1023 /* Processor identification */
1024 spr_register(env, SPR_PIR, "PIR",
1025 SPR_NOACCESS, SPR_NOACCESS,
1026 &spr_read_generic, &spr_write_pir,
1027 0x00000000);
1028 /* Breakpoints */
1029 /* XXX : not implemented */
1030 spr_register(env, SPR_IABR, "IABR",
1031 SPR_NOACCESS, SPR_NOACCESS,
1032 &spr_read_generic, &spr_write_generic,
1033 0x00000000);
1034 /* XXX : not implemented */
1035 spr_register(env, SPR_DABR, "DABR",
1036 SPR_NOACCESS, SPR_NOACCESS,
1037 &spr_read_generic, &spr_write_generic,
1038 0x00000000);
1039 /* Performance counters */
1040 /* XXX : not implemented */
1041 spr_register(env, SPR_MMCR0, "MMCR0",
1042 SPR_NOACCESS, SPR_NOACCESS,
1043 &spr_read_generic, &spr_write_generic,
1044 0x00000000);
1045 /* XXX : not implemented */
1046 spr_register(env, SPR_PMC1, "PMC1",
1047 SPR_NOACCESS, SPR_NOACCESS,
1048 &spr_read_generic, &spr_write_generic,
1049 0x00000000);
1050 /* XXX : not implemented */
1051 spr_register(env, SPR_PMC2, "PMC2",
1052 SPR_NOACCESS, SPR_NOACCESS,
1053 &spr_read_generic, &spr_write_generic,
1054 0x00000000);
1055 /* XXX : not implemented */
1056 spr_register(env, SPR_SIAR, "SIAR",
1057 SPR_NOACCESS, SPR_NOACCESS,
1058 &spr_read_generic, SPR_NOACCESS,
1059 0x00000000);
1060 /* XXX : not implemented */
1061 spr_register(env, SPR_SDA, "SDA",
1062 SPR_NOACCESS, SPR_NOACCESS,
1063 &spr_read_generic, SPR_NOACCESS,
1064 0x00000000);
1065 /* External access control */
1066 /* XXX : not implemented */
1067 spr_register(env, SPR_EAR, "EAR",
1068 SPR_NOACCESS, SPR_NOACCESS,
1069 &spr_read_generic, &spr_write_generic,
1070 0x00000000);
1071 }
1072
1073 /* SPR specific to PowerPC 603 implementation */
1074 static void gen_spr_603 (CPUPPCState *env)
1075 {
1076 /* External access control */
1077 /* XXX : not implemented */
1078 spr_register(env, SPR_EAR, "EAR",
1079 SPR_NOACCESS, SPR_NOACCESS,
1080 &spr_read_generic, &spr_write_generic,
1081 0x00000000);
1082 }
1083
1084 /* SPR specific to PowerPC G2 implementation */
1085 static void gen_spr_G2 (CPUPPCState *env)
1086 {
1087 /* Memory base address */
1088 /* MBAR */
1089 /* XXX : not implemented */
1090 spr_register(env, SPR_MBAR, "MBAR",
1091 SPR_NOACCESS, SPR_NOACCESS,
1092 &spr_read_generic, &spr_write_generic,
1093 0x00000000);
1094 /* Exception processing */
1095 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1096 SPR_NOACCESS, SPR_NOACCESS,
1097 &spr_read_generic, &spr_write_generic,
1098 0x00000000);
1099 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1100 SPR_NOACCESS, SPR_NOACCESS,
1101 &spr_read_generic, &spr_write_generic,
1102 0x00000000);
1103 /* Breakpoints */
1104 /* XXX : not implemented */
1105 spr_register(env, SPR_DABR, "DABR",
1106 SPR_NOACCESS, SPR_NOACCESS,
1107 &spr_read_generic, &spr_write_generic,
1108 0x00000000);
1109 /* XXX : not implemented */
1110 spr_register(env, SPR_DABR2, "DABR2",
1111 SPR_NOACCESS, SPR_NOACCESS,
1112 &spr_read_generic, &spr_write_generic,
1113 0x00000000);
1114 /* XXX : not implemented */
1115 spr_register(env, SPR_IABR, "IABR",
1116 SPR_NOACCESS, SPR_NOACCESS,
1117 &spr_read_generic, &spr_write_generic,
1118 0x00000000);
1119 /* XXX : not implemented */
1120 spr_register(env, SPR_IABR2, "IABR2",
1121 SPR_NOACCESS, SPR_NOACCESS,
1122 &spr_read_generic, &spr_write_generic,
1123 0x00000000);
1124 /* XXX : not implemented */
1125 spr_register(env, SPR_IBCR, "IBCR",
1126 SPR_NOACCESS, SPR_NOACCESS,
1127 &spr_read_generic, &spr_write_generic,
1128 0x00000000);
1129 /* XXX : not implemented */
1130 spr_register(env, SPR_DBCR, "DBCR",
1131 SPR_NOACCESS, SPR_NOACCESS,
1132 &spr_read_generic, &spr_write_generic,
1133 0x00000000);
1134 }
1135
1136 /* SPR specific to PowerPC 602 implementation */
1137 static void gen_spr_602 (CPUPPCState *env)
1138 {
1139 /* ESA registers */
1140 /* XXX : not implemented */
1141 spr_register(env, SPR_SER, "SER",
1142 SPR_NOACCESS, SPR_NOACCESS,
1143 &spr_read_generic, &spr_write_generic,
1144 0x00000000);
1145 /* XXX : not implemented */
1146 spr_register(env, SPR_SEBR, "SEBR",
1147 SPR_NOACCESS, SPR_NOACCESS,
1148 &spr_read_generic, &spr_write_generic,
1149 0x00000000);
1150 /* XXX : not implemented */
1151 spr_register(env, SPR_ESASRR, "ESASRR",
1152 SPR_NOACCESS, SPR_NOACCESS,
1153 &spr_read_generic, &spr_write_generic,
1154 0x00000000);
1155 /* Floating point status */
1156 /* XXX : not implemented */
1157 spr_register(env, SPR_SP, "SP",
1158 SPR_NOACCESS, SPR_NOACCESS,
1159 &spr_read_generic, &spr_write_generic,
1160 0x00000000);
1161 /* XXX : not implemented */
1162 spr_register(env, SPR_LT, "LT",
1163 SPR_NOACCESS, SPR_NOACCESS,
1164 &spr_read_generic, &spr_write_generic,
1165 0x00000000);
1166 /* Watchdog timer */
1167 /* XXX : not implemented */
1168 spr_register(env, SPR_TCR, "TCR",
1169 SPR_NOACCESS, SPR_NOACCESS,
1170 &spr_read_generic, &spr_write_generic,
1171 0x00000000);
1172 /* Interrupt base */
1173 spr_register(env, SPR_IBR, "IBR",
1174 SPR_NOACCESS, SPR_NOACCESS,
1175 &spr_read_generic, &spr_write_generic,
1176 0x00000000);
1177 /* XXX : not implemented */
1178 spr_register(env, SPR_IABR, "IABR",
1179 SPR_NOACCESS, SPR_NOACCESS,
1180 &spr_read_generic, &spr_write_generic,
1181 0x00000000);
1182 }
1183
1184 /* SPR specific to PowerPC 601 implementation */
1185 static void gen_spr_601 (CPUPPCState *env)
1186 {
1187 /* Multiplication/division register */
1188 /* MQ */
1189 spr_register(env, SPR_MQ, "MQ",
1190 &spr_read_generic, &spr_write_generic,
1191 &spr_read_generic, &spr_write_generic,
1192 0x00000000);
1193 /* RTC registers */
1194 spr_register(env, SPR_601_RTCU, "RTCU",
1195 SPR_NOACCESS, SPR_NOACCESS,
1196 SPR_NOACCESS, &spr_write_601_rtcu,
1197 0x00000000);
1198 spr_register(env, SPR_601_VRTCU, "RTCU",
1199 &spr_read_601_rtcu, SPR_NOACCESS,
1200 &spr_read_601_rtcu, SPR_NOACCESS,
1201 0x00000000);
1202 spr_register(env, SPR_601_RTCL, "RTCL",
1203 SPR_NOACCESS, SPR_NOACCESS,
1204 SPR_NOACCESS, &spr_write_601_rtcl,
1205 0x00000000);
1206 spr_register(env, SPR_601_VRTCL, "RTCL",
1207 &spr_read_601_rtcl, SPR_NOACCESS,
1208 &spr_read_601_rtcl, SPR_NOACCESS,
1209 0x00000000);
1210 /* Timer */
1211 #if 0 /* ? */
1212 spr_register(env, SPR_601_UDECR, "UDECR",
1213 &spr_read_decr, SPR_NOACCESS,
1214 &spr_read_decr, SPR_NOACCESS,
1215 0x00000000);
1216 #endif
1217 /* External access control */
1218 /* XXX : not implemented */
1219 spr_register(env, SPR_EAR, "EAR",
1220 SPR_NOACCESS, SPR_NOACCESS,
1221 &spr_read_generic, &spr_write_generic,
1222 0x00000000);
1223 /* Memory management */
1224 #if !defined(CONFIG_USER_ONLY)
1225 spr_register(env, SPR_IBAT0U, "IBAT0U",
1226 SPR_NOACCESS, SPR_NOACCESS,
1227 &spr_read_601_ubat, &spr_write_601_ubatu,
1228 0x00000000);
1229 spr_register(env, SPR_IBAT0L, "IBAT0L",
1230 SPR_NOACCESS, SPR_NOACCESS,
1231 &spr_read_601_ubat, &spr_write_601_ubatl,
1232 0x00000000);
1233 spr_register(env, SPR_IBAT1U, "IBAT1U",
1234 SPR_NOACCESS, SPR_NOACCESS,
1235 &spr_read_601_ubat, &spr_write_601_ubatu,
1236 0x00000000);
1237 spr_register(env, SPR_IBAT1L, "IBAT1L",
1238 SPR_NOACCESS, SPR_NOACCESS,
1239 &spr_read_601_ubat, &spr_write_601_ubatl,
1240 0x00000000);
1241 spr_register(env, SPR_IBAT2U, "IBAT2U",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_601_ubat, &spr_write_601_ubatu,
1244 0x00000000);
1245 spr_register(env, SPR_IBAT2L, "IBAT2L",
1246 SPR_NOACCESS, SPR_NOACCESS,
1247 &spr_read_601_ubat, &spr_write_601_ubatl,
1248 0x00000000);
1249 spr_register(env, SPR_IBAT3U, "IBAT3U",
1250 SPR_NOACCESS, SPR_NOACCESS,
1251 &spr_read_601_ubat, &spr_write_601_ubatu,
1252 0x00000000);
1253 spr_register(env, SPR_IBAT3L, "IBAT3L",
1254 SPR_NOACCESS, SPR_NOACCESS,
1255 &spr_read_601_ubat, &spr_write_601_ubatl,
1256 0x00000000);
1257 env->nb_BATs = 4;
1258 #endif
1259 }
1260
1261 static void gen_spr_74xx (CPUPPCState *env)
1262 {
1263 /* Processor identification */
1264 spr_register(env, SPR_PIR, "PIR",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_pir,
1267 0x00000000);
1268 /* XXX : not implemented */
1269 spr_register(env, SPR_MMCR2, "MMCR2",
1270 SPR_NOACCESS, SPR_NOACCESS,
1271 &spr_read_generic, &spr_write_generic,
1272 0x00000000);
1273 /* XXX : not implemented */
1274 spr_register(env, SPR_UMMCR2, "UMMCR2",
1275 &spr_read_ureg, SPR_NOACCESS,
1276 &spr_read_ureg, SPR_NOACCESS,
1277 0x00000000);
1278 /* XXX: not implemented */
1279 spr_register(env, SPR_BAMR, "BAMR",
1280 SPR_NOACCESS, SPR_NOACCESS,
1281 &spr_read_generic, &spr_write_generic,
1282 0x00000000);
1283 /* XXX : not implemented */
1284 spr_register(env, SPR_MSSCR0, "MSSCR0",
1285 SPR_NOACCESS, SPR_NOACCESS,
1286 &spr_read_generic, &spr_write_generic,
1287 0x00000000);
1288 /* Hardware implementation registers */
1289 /* XXX : not implemented */
1290 spr_register(env, SPR_HID0, "HID0",
1291 SPR_NOACCESS, SPR_NOACCESS,
1292 &spr_read_generic, &spr_write_generic,
1293 0x00000000);
1294 /* XXX : not implemented */
1295 spr_register(env, SPR_HID1, "HID1",
1296 SPR_NOACCESS, SPR_NOACCESS,
1297 &spr_read_generic, &spr_write_generic,
1298 0x00000000);
1299 /* Altivec */
1300 spr_register(env, SPR_VRSAVE, "VRSAVE",
1301 &spr_read_generic, &spr_write_generic,
1302 &spr_read_generic, &spr_write_generic,
1303 0x00000000);
1304 /* XXX : not implemented */
1305 spr_register(env, SPR_L2CR, "L2CR",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, &spr_write_generic,
1308 0x00000000);
1309 /* Not strictly an SPR */
1310 vscr_init(env, 0x00010000);
1311 }
1312
1313 static void gen_l3_ctrl (CPUPPCState *env)
1314 {
1315 /* L3CR */
1316 /* XXX : not implemented */
1317 spr_register(env, SPR_L3CR, "L3CR",
1318 SPR_NOACCESS, SPR_NOACCESS,
1319 &spr_read_generic, &spr_write_generic,
1320 0x00000000);
1321 /* L3ITCR0 */
1322 /* XXX : not implemented */
1323 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1324 SPR_NOACCESS, SPR_NOACCESS,
1325 &spr_read_generic, &spr_write_generic,
1326 0x00000000);
1327 /* L3PM */
1328 /* XXX : not implemented */
1329 spr_register(env, SPR_L3PM, "L3PM",
1330 SPR_NOACCESS, SPR_NOACCESS,
1331 &spr_read_generic, &spr_write_generic,
1332 0x00000000);
1333 }
1334
1335 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1336 {
1337 #if !defined(CONFIG_USER_ONLY)
1338 env->nb_tlb = nb_tlbs;
1339 env->nb_ways = nb_ways;
1340 env->id_tlbs = 1;
1341 env->tlb_type = TLB_6XX;
1342 /* XXX : not implemented */
1343 spr_register(env, SPR_PTEHI, "PTEHI",
1344 SPR_NOACCESS, SPR_NOACCESS,
1345 &spr_read_generic, &spr_write_generic,
1346 0x00000000);
1347 /* XXX : not implemented */
1348 spr_register(env, SPR_PTELO, "PTELO",
1349 SPR_NOACCESS, SPR_NOACCESS,
1350 &spr_read_generic, &spr_write_generic,
1351 0x00000000);
1352 /* XXX : not implemented */
1353 spr_register(env, SPR_TLBMISS, "TLBMISS",
1354 SPR_NOACCESS, SPR_NOACCESS,
1355 &spr_read_generic, &spr_write_generic,
1356 0x00000000);
1357 #endif
1358 }
1359
1360 #if !defined(CONFIG_USER_ONLY)
1361 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1362 {
1363 TCGv t0 = tcg_temp_new();
1364
1365 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1366 gen_store_spr(sprn, t0);
1367 tcg_temp_free(t0);
1368 }
1369
1370 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1371 {
1372 TCGv_i32 t0 = tcg_const_i32(sprn);
1373 gen_helper_booke206_tlbflush(t0);
1374 tcg_temp_free_i32(t0);
1375 }
1376
1377 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1378 {
1379 TCGv_i32 t0 = tcg_const_i32(sprn);
1380 gen_helper_booke_setpid(t0, cpu_gpr[gprn]);
1381 tcg_temp_free_i32(t0);
1382 }
1383 #endif
1384
1385 static void gen_spr_usprgh (CPUPPCState *env)
1386 {
1387 spr_register(env, SPR_USPRG4, "USPRG4",
1388 &spr_read_ureg, SPR_NOACCESS,
1389 &spr_read_ureg, SPR_NOACCESS,
1390 0x00000000);
1391 spr_register(env, SPR_USPRG5, "USPRG5",
1392 &spr_read_ureg, SPR_NOACCESS,
1393 &spr_read_ureg, SPR_NOACCESS,
1394 0x00000000);
1395 spr_register(env, SPR_USPRG6, "USPRG6",
1396 &spr_read_ureg, SPR_NOACCESS,
1397 &spr_read_ureg, SPR_NOACCESS,
1398 0x00000000);
1399 spr_register(env, SPR_USPRG7, "USPRG7",
1400 &spr_read_ureg, SPR_NOACCESS,
1401 &spr_read_ureg, SPR_NOACCESS,
1402 0x00000000);
1403 }
1404
1405 /* PowerPC BookE SPR */
1406 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1407 {
1408 const char *ivor_names[64] = {
1409 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1410 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1411 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1412 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1413 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1414 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1415 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1416 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1417 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1418 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1419 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1420 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1421 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1422 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1423 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1424 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1425 };
1426 #define SPR_BOOKE_IVORxx (-1)
1427 int ivor_sprn[64] = {
1428 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1429 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1430 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1431 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1432 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1433 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1434 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1435 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1436 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1437 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1438 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1439 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1440 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1441 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1442 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1443 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1444 };
1445 int i;
1446
1447 /* Interrupt processing */
1448 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1449 SPR_NOACCESS, SPR_NOACCESS,
1450 &spr_read_generic, &spr_write_generic,
1451 0x00000000);
1452 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1453 SPR_NOACCESS, SPR_NOACCESS,
1454 &spr_read_generic, &spr_write_generic,
1455 0x00000000);
1456 /* Debug */
1457 /* XXX : not implemented */
1458 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1459 SPR_NOACCESS, SPR_NOACCESS,
1460 &spr_read_generic, &spr_write_generic,
1461 0x00000000);
1462 /* XXX : not implemented */
1463 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1464 SPR_NOACCESS, SPR_NOACCESS,
1465 &spr_read_generic, &spr_write_generic,
1466 0x00000000);
1467 /* XXX : not implemented */
1468 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1469 SPR_NOACCESS, SPR_NOACCESS,
1470 &spr_read_generic, &spr_write_generic,
1471 0x00000000);
1472 /* XXX : not implemented */
1473 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1474 SPR_NOACCESS, SPR_NOACCESS,
1475 &spr_read_generic, &spr_write_generic,
1476 0x00000000);
1477 /* XXX : not implemented */
1478 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1479 SPR_NOACCESS, SPR_NOACCESS,
1480 &spr_read_generic, &spr_write_generic,
1481 0x00000000);
1482 /* XXX : not implemented */
1483 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1484 SPR_NOACCESS, SPR_NOACCESS,
1485 &spr_read_generic, &spr_write_generic,
1486 0x00000000);
1487 /* XXX : not implemented */
1488 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1489 SPR_NOACCESS, SPR_NOACCESS,
1490 &spr_read_generic, &spr_write_generic,
1491 0x00000000);
1492 /* XXX : not implemented */
1493 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1494 SPR_NOACCESS, SPR_NOACCESS,
1495 &spr_read_generic, &spr_write_clear,
1496 0x00000000);
1497 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1498 SPR_NOACCESS, SPR_NOACCESS,
1499 &spr_read_generic, &spr_write_generic,
1500 0x00000000);
1501 spr_register(env, SPR_BOOKE_ESR, "ESR",
1502 SPR_NOACCESS, SPR_NOACCESS,
1503 &spr_read_generic, &spr_write_generic,
1504 0x00000000);
1505 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1506 SPR_NOACCESS, SPR_NOACCESS,
1507 &spr_read_generic, &spr_write_excp_prefix,
1508 0x00000000);
1509 /* Exception vectors */
1510 for (i = 0; i < 64; i++) {
1511 if (ivor_mask & (1ULL << i)) {
1512 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1513 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1514 exit(1);
1515 }
1516 spr_register(env, ivor_sprn[i], ivor_names[i],
1517 SPR_NOACCESS, SPR_NOACCESS,
1518 &spr_read_generic, &spr_write_excp_vector,
1519 0x00000000);
1520 }
1521 }
1522 spr_register(env, SPR_BOOKE_PID, "PID",
1523 SPR_NOACCESS, SPR_NOACCESS,
1524 &spr_read_generic, &spr_write_booke_pid,
1525 0x00000000);
1526 spr_register(env, SPR_BOOKE_TCR, "TCR",
1527 SPR_NOACCESS, SPR_NOACCESS,
1528 &spr_read_generic, &spr_write_booke_tcr,
1529 0x00000000);
1530 spr_register(env, SPR_BOOKE_TSR, "TSR",
1531 SPR_NOACCESS, SPR_NOACCESS,
1532 &spr_read_generic, &spr_write_booke_tsr,
1533 0x00000000);
1534 /* Timer */
1535 spr_register(env, SPR_DECR, "DECR",
1536 SPR_NOACCESS, SPR_NOACCESS,
1537 &spr_read_decr, &spr_write_decr,
1538 0x00000000);
1539 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1540 SPR_NOACCESS, SPR_NOACCESS,
1541 SPR_NOACCESS, &spr_write_generic,
1542 0x00000000);
1543 /* SPRGs */
1544 spr_register(env, SPR_USPRG0, "USPRG0",
1545 &spr_read_generic, &spr_write_generic,
1546 &spr_read_generic, &spr_write_generic,
1547 0x00000000);
1548 spr_register(env, SPR_SPRG4, "SPRG4",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_generic,
1551 0x00000000);
1552 spr_register(env, SPR_SPRG5, "SPRG5",
1553 SPR_NOACCESS, SPR_NOACCESS,
1554 &spr_read_generic, &spr_write_generic,
1555 0x00000000);
1556 spr_register(env, SPR_SPRG6, "SPRG6",
1557 SPR_NOACCESS, SPR_NOACCESS,
1558 &spr_read_generic, &spr_write_generic,
1559 0x00000000);
1560 spr_register(env, SPR_SPRG7, "SPRG7",
1561 SPR_NOACCESS, SPR_NOACCESS,
1562 &spr_read_generic, &spr_write_generic,
1563 0x00000000);
1564 }
1565
1566 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1567 uint32_t maxsize, uint32_t flags,
1568 uint32_t nentries)
1569 {
1570 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1571 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1572 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1573 flags | nentries;
1574 }
1575
1576 /* BookE 2.06 storage control registers */
1577 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1578 uint32_t *tlbncfg)
1579 {
1580 #if !defined(CONFIG_USER_ONLY)
1581 const char *mas_names[8] = {
1582 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1583 };
1584 int mas_sprn[8] = {
1585 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1586 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1587 };
1588 int i;
1589
1590 /* TLB assist registers */
1591 /* XXX : not implemented */
1592 for (i = 0; i < 8; i++) {
1593 if (mas_mask & (1 << i)) {
1594 spr_register(env, mas_sprn[i], mas_names[i],
1595 SPR_NOACCESS, SPR_NOACCESS,
1596 &spr_read_generic, &spr_write_generic,
1597 0x00000000);
1598 }
1599 }
1600 if (env->nb_pids > 1) {
1601 /* XXX : not implemented */
1602 spr_register(env, SPR_BOOKE_PID1, "PID1",
1603 SPR_NOACCESS, SPR_NOACCESS,
1604 &spr_read_generic, &spr_write_booke_pid,
1605 0x00000000);
1606 }
1607 if (env->nb_pids > 2) {
1608 /* XXX : not implemented */
1609 spr_register(env, SPR_BOOKE_PID2, "PID2",
1610 SPR_NOACCESS, SPR_NOACCESS,
1611 &spr_read_generic, &spr_write_booke_pid,
1612 0x00000000);
1613 }
1614 /* XXX : not implemented */
1615 spr_register(env, SPR_MMUCFG, "MMUCFG",
1616 SPR_NOACCESS, SPR_NOACCESS,
1617 &spr_read_generic, SPR_NOACCESS,
1618 0x00000000); /* TOFIX */
1619 switch (env->nb_ways) {
1620 case 4:
1621 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1622 SPR_NOACCESS, SPR_NOACCESS,
1623 &spr_read_generic, SPR_NOACCESS,
1624 tlbncfg[3]);
1625 /* Fallthru */
1626 case 3:
1627 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1628 SPR_NOACCESS, SPR_NOACCESS,
1629 &spr_read_generic, SPR_NOACCESS,
1630 tlbncfg[2]);
1631 /* Fallthru */
1632 case 2:
1633 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1634 SPR_NOACCESS, SPR_NOACCESS,
1635 &spr_read_generic, SPR_NOACCESS,
1636 tlbncfg[1]);
1637 /* Fallthru */
1638 case 1:
1639 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1640 SPR_NOACCESS, SPR_NOACCESS,
1641 &spr_read_generic, SPR_NOACCESS,
1642 tlbncfg[0]);
1643 /* Fallthru */
1644 case 0:
1645 default:
1646 break;
1647 }
1648 #endif
1649
1650 gen_spr_usprgh(env);
1651 }
1652
1653 /* SPR specific to PowerPC 440 implementation */
1654 static void gen_spr_440 (CPUPPCState *env)
1655 {
1656 /* Cache control */
1657 /* XXX : not implemented */
1658 spr_register(env, SPR_440_DNV0, "DNV0",
1659 SPR_NOACCESS, SPR_NOACCESS,
1660 &spr_read_generic, &spr_write_generic,
1661 0x00000000);
1662 /* XXX : not implemented */
1663 spr_register(env, SPR_440_DNV1, "DNV1",
1664 SPR_NOACCESS, SPR_NOACCESS,
1665 &spr_read_generic, &spr_write_generic,
1666 0x00000000);
1667 /* XXX : not implemented */
1668 spr_register(env, SPR_440_DNV2, "DNV2",
1669 SPR_NOACCESS, SPR_NOACCESS,
1670 &spr_read_generic, &spr_write_generic,
1671 0x00000000);
1672 /* XXX : not implemented */
1673 spr_register(env, SPR_440_DNV3, "DNV3",
1674 SPR_NOACCESS, SPR_NOACCESS,
1675 &spr_read_generic, &spr_write_generic,
1676 0x00000000);
1677 /* XXX : not implemented */
1678 spr_register(env, SPR_440_DTV0, "DTV0",
1679 SPR_NOACCESS, SPR_NOACCESS,
1680 &spr_read_generic, &spr_write_generic,
1681 0x00000000);
1682 /* XXX : not implemented */
1683 spr_register(env, SPR_440_DTV1, "DTV1",
1684 SPR_NOACCESS, SPR_NOACCESS,
1685 &spr_read_generic, &spr_write_generic,
1686 0x00000000);
1687 /* XXX : not implemented */
1688 spr_register(env, SPR_440_DTV2, "DTV2",
1689 SPR_NOACCESS, SPR_NOACCESS,
1690 &spr_read_generic, &spr_write_generic,
1691 0x00000000);
1692 /* XXX : not implemented */
1693 spr_register(env, SPR_440_DTV3, "DTV3",
1694 SPR_NOACCESS, SPR_NOACCESS,
1695 &spr_read_generic, &spr_write_generic,
1696 0x00000000);
1697 /* XXX : not implemented */
1698 spr_register(env, SPR_440_DVLIM, "DVLIM",
1699 SPR_NOACCESS, SPR_NOACCESS,
1700 &spr_read_generic, &spr_write_generic,
1701 0x00000000);
1702 /* XXX : not implemented */
1703 spr_register(env, SPR_440_INV0, "INV0",
1704 SPR_NOACCESS, SPR_NOACCESS,
1705 &spr_read_generic, &spr_write_generic,
1706 0x00000000);
1707 /* XXX : not implemented */
1708 spr_register(env, SPR_440_INV1, "INV1",
1709 SPR_NOACCESS, SPR_NOACCESS,
1710 &spr_read_generic, &spr_write_generic,
1711 0x00000000);
1712 /* XXX : not implemented */
1713 spr_register(env, SPR_440_INV2, "INV2",
1714 SPR_NOACCESS, SPR_NOACCESS,
1715 &spr_read_generic, &spr_write_generic,
1716 0x00000000);
1717 /* XXX : not implemented */
1718 spr_register(env, SPR_440_INV3, "INV3",
1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, &spr_write_generic,
1721 0x00000000);
1722 /* XXX : not implemented */
1723 spr_register(env, SPR_440_ITV0, "ITV0",
1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_generic, &spr_write_generic,
1726 0x00000000);
1727 /* XXX : not implemented */
1728 spr_register(env, SPR_440_ITV1, "ITV1",
1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, &spr_write_generic,
1731 0x00000000);
1732 /* XXX : not implemented */
1733 spr_register(env, SPR_440_ITV2, "ITV2",
1734 SPR_NOACCESS, SPR_NOACCESS,
1735 &spr_read_generic, &spr_write_generic,
1736 0x00000000);
1737 /* XXX : not implemented */
1738 spr_register(env, SPR_440_ITV3, "ITV3",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, &spr_write_generic,
1741 0x00000000);
1742 /* XXX : not implemented */
1743 spr_register(env, SPR_440_IVLIM, "IVLIM",
1744 SPR_NOACCESS, SPR_NOACCESS,
1745 &spr_read_generic, &spr_write_generic,
1746 0x00000000);
1747 /* Cache debug */
1748 /* XXX : not implemented */
1749 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1750 SPR_NOACCESS, SPR_NOACCESS,
1751 &spr_read_generic, SPR_NOACCESS,
1752 0x00000000);
1753 /* XXX : not implemented */
1754 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1755 SPR_NOACCESS, SPR_NOACCESS,
1756 &spr_read_generic, SPR_NOACCESS,
1757 0x00000000);
1758 /* XXX : not implemented */
1759 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1760 SPR_NOACCESS, SPR_NOACCESS,
1761 &spr_read_generic, SPR_NOACCESS,
1762 0x00000000);
1763 /* XXX : not implemented */
1764 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1765 SPR_NOACCESS, SPR_NOACCESS,
1766 &spr_read_generic, SPR_NOACCESS,
1767 0x00000000);
1768 /* XXX : not implemented */
1769 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1770 SPR_NOACCESS, SPR_NOACCESS,
1771 &spr_read_generic, SPR_NOACCESS,
1772 0x00000000);
1773 /* XXX : not implemented */
1774 spr_register(env, SPR_440_DBDR, "DBDR",
1775 SPR_NOACCESS, SPR_NOACCESS,
1776 &spr_read_generic, &spr_write_generic,
1777 0x00000000);
1778 /* Processor control */
1779 spr_register(env, SPR_4xx_CCR0, "CCR0",
1780 SPR_NOACCESS, SPR_NOACCESS,
1781 &spr_read_generic, &spr_write_generic,
1782 0x00000000);
1783 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1784 SPR_NOACCESS, SPR_NOACCESS,
1785 &spr_read_generic, SPR_NOACCESS,
1786 0x00000000);
1787 /* Storage control */
1788 spr_register(env, SPR_440_MMUCR, "MMUCR",
1789 SPR_NOACCESS, SPR_NOACCESS,
1790 &spr_read_generic, &spr_write_generic,
1791 0x00000000);
1792 }
1793
1794 /* SPR shared between PowerPC 40x implementations */
1795 static void gen_spr_40x (CPUPPCState *env)
1796 {
1797 /* Cache */
1798 /* not emulated, as Qemu do not emulate caches */
1799 spr_register(env, SPR_40x_DCCR, "DCCR",
1800 SPR_NOACCESS, SPR_NOACCESS,
1801 &spr_read_generic, &spr_write_generic,
1802 0x00000000);
1803 /* not emulated, as Qemu do not emulate caches */
1804 spr_register(env, SPR_40x_ICCR, "ICCR",
1805 SPR_NOACCESS, SPR_NOACCESS,
1806 &spr_read_generic, &spr_write_generic,
1807 0x00000000);
1808 /* not emulated, as Qemu do not emulate caches */
1809 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1810 SPR_NOACCESS, SPR_NOACCESS,
1811 &spr_read_generic, SPR_NOACCESS,
1812 0x00000000);
1813 /* Exception */
1814 spr_register(env, SPR_40x_DEAR, "DEAR",
1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_generic, &spr_write_generic,
1817 0x00000000);
1818 spr_register(env, SPR_40x_ESR, "ESR",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, &spr_write_generic,
1821 0x00000000);
1822 spr_register(env, SPR_40x_EVPR, "EVPR",
1823 SPR_NOACCESS, SPR_NOACCESS,
1824 &spr_read_generic, &spr_write_excp_prefix,
1825 0x00000000);
1826 spr_register(env, SPR_40x_SRR2, "SRR2",
1827 &spr_read_generic, &spr_write_generic,
1828 &spr_read_generic, &spr_write_generic,
1829 0x00000000);
1830 spr_register(env, SPR_40x_SRR3, "SRR3",
1831 &spr_read_generic, &spr_write_generic,
1832 &spr_read_generic, &spr_write_generic,
1833 0x00000000);
1834 /* Timers */
1835 spr_register(env, SPR_40x_PIT, "PIT",
1836 SPR_NOACCESS, SPR_NOACCESS,
1837 &spr_read_40x_pit, &spr_write_40x_pit,
1838 0x00000000);
1839 spr_register(env, SPR_40x_TCR, "TCR",
1840 SPR_NOACCESS, SPR_NOACCESS,
1841 &spr_read_generic, &spr_write_booke_tcr,
1842 0x00000000);
1843 spr_register(env, SPR_40x_TSR, "TSR",
1844 SPR_NOACCESS, SPR_NOACCESS,
1845 &spr_read_generic, &spr_write_booke_tsr,
1846 0x00000000);
1847 }
1848
1849 /* SPR specific to PowerPC 405 implementation */
1850 static void gen_spr_405 (CPUPPCState *env)
1851 {
1852 /* MMU */
1853 spr_register(env, SPR_40x_PID, "PID",
1854 SPR_NOACCESS, SPR_NOACCESS,
1855 &spr_read_generic, &spr_write_generic,
1856 0x00000000);
1857 spr_register(env, SPR_4xx_CCR0, "CCR0",
1858 SPR_NOACCESS, SPR_NOACCESS,
1859 &spr_read_generic, &spr_write_generic,
1860 0x00700000);
1861 /* Debug interface */
1862 /* XXX : not implemented */
1863 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1864 SPR_NOACCESS, SPR_NOACCESS,
1865 &spr_read_generic, &spr_write_40x_dbcr0,
1866 0x00000000);
1867 /* XXX : not implemented */
1868 spr_register(env, SPR_405_DBCR1, "DBCR1",
1869 SPR_NOACCESS, SPR_NOACCESS,
1870 &spr_read_generic, &spr_write_generic,
1871 0x00000000);
1872 /* XXX : not implemented */
1873 spr_register(env, SPR_40x_DBSR, "DBSR",
1874 SPR_NOACCESS, SPR_NOACCESS,
1875 &spr_read_generic, &spr_write_clear,
1876 /* Last reset was system reset */
1877 0x00000300);
1878 /* XXX : not implemented */
1879 spr_register(env, SPR_40x_DAC1, "DAC1",
1880 SPR_NOACCESS, SPR_NOACCESS,
1881 &spr_read_generic, &spr_write_generic,
1882 0x00000000);
1883 spr_register(env, SPR_40x_DAC2, "DAC2",
1884 SPR_NOACCESS, SPR_NOACCESS,
1885 &spr_read_generic, &spr_write_generic,
1886 0x00000000);
1887 /* XXX : not implemented */
1888 spr_register(env, SPR_405_DVC1, "DVC1",
1889 SPR_NOACCESS, SPR_NOACCESS,
1890 &spr_read_generic, &spr_write_generic,
1891 0x00000000);
1892 /* XXX : not implemented */
1893 spr_register(env, SPR_405_DVC2, "DVC2",
1894 SPR_NOACCESS, SPR_NOACCESS,
1895 &spr_read_generic, &spr_write_generic,
1896 0x00000000);
1897 /* XXX : not implemented */
1898 spr_register(env, SPR_40x_IAC1, "IAC1",
1899 SPR_NOACCESS, SPR_NOACCESS,
1900 &spr_read_generic, &spr_write_generic,
1901 0x00000000);
1902 spr_register(env, SPR_40x_IAC2, "IAC2",
1903 SPR_NOACCESS, SPR_NOACCESS,
1904 &spr_read_generic, &spr_write_generic,
1905 0x00000000);
1906 /* XXX : not implemented */
1907 spr_register(env, SPR_405_IAC3, "IAC3",
1908 SPR_NOACCESS, SPR_NOACCESS,
1909 &spr_read_generic, &spr_write_generic,
1910 0x00000000);
1911 /* XXX : not implemented */
1912 spr_register(env, SPR_405_IAC4, "IAC4",
1913 SPR_NOACCESS, SPR_NOACCESS,
1914 &spr_read_generic, &spr_write_generic,
1915 0x00000000);
1916 /* Storage control */
1917 /* XXX: TODO: not implemented */
1918 spr_register(env, SPR_405_SLER, "SLER",
1919 SPR_NOACCESS, SPR_NOACCESS,
1920 &spr_read_generic, &spr_write_40x_sler,
1921 0x00000000);
1922 spr_register(env, SPR_40x_ZPR, "ZPR",
1923 SPR_NOACCESS, SPR_NOACCESS,
1924 &spr_read_generic, &spr_write_generic,
1925 0x00000000);
1926 /* XXX : not implemented */
1927 spr_register(env, SPR_405_SU0R, "SU0R",
1928 SPR_NOACCESS, SPR_NOACCESS,
1929 &spr_read_generic, &spr_write_generic,
1930 0x00000000);
1931 /* SPRG */
1932 spr_register(env, SPR_USPRG0, "USPRG0",
1933 &spr_read_ureg, SPR_NOACCESS,
1934 &spr_read_ureg, SPR_NOACCESS,
1935 0x00000000);
1936 spr_register(env, SPR_SPRG4, "SPRG4",
1937 SPR_NOACCESS, SPR_NOACCESS,
1938 &spr_read_generic, &spr_write_generic,
1939 0x00000000);
1940 spr_register(env, SPR_SPRG5, "SPRG5",
1941 SPR_NOACCESS, SPR_NOACCESS,
1942 spr_read_generic, &spr_write_generic,
1943 0x00000000);
1944 spr_register(env, SPR_SPRG6, "SPRG6",
1945 SPR_NOACCESS, SPR_NOACCESS,
1946 spr_read_generic, &spr_write_generic,
1947 0x00000000);
1948 spr_register(env, SPR_SPRG7, "SPRG7",
1949 SPR_NOACCESS, SPR_NOACCESS,
1950 spr_read_generic, &spr_write_generic,
1951 0x00000000);
1952 gen_spr_usprgh(env);
1953 }
1954
1955 /* SPR shared between PowerPC 401 & 403 implementations */
1956 static void gen_spr_401_403 (CPUPPCState *env)
1957 {
1958 /* Time base */
1959 spr_register(env, SPR_403_VTBL, "TBL",
1960 &spr_read_tbl, SPR_NOACCESS,
1961 &spr_read_tbl, SPR_NOACCESS,
1962 0x00000000);
1963 spr_register(env, SPR_403_TBL, "TBL",
1964 SPR_NOACCESS, SPR_NOACCESS,
1965 SPR_NOACCESS, &spr_write_tbl,
1966 0x00000000);
1967 spr_register(env, SPR_403_VTBU, "TBU",
1968 &spr_read_tbu, SPR_NOACCESS,
1969 &spr_read_tbu, SPR_NOACCESS,
1970 0x00000000);
1971 spr_register(env, SPR_403_TBU, "TBU",
1972 SPR_NOACCESS, SPR_NOACCESS,
1973 SPR_NOACCESS, &spr_write_tbu,
1974 0x00000000);
1975 /* Debug */
1976 /* not emulated, as Qemu do not emulate caches */
1977 spr_register(env, SPR_403_CDBCR, "CDBCR",
1978 SPR_NOACCESS, SPR_NOACCESS,
1979 &spr_read_generic, &spr_write_generic,
1980 0x00000000);
1981 }
1982
1983 /* SPR specific to PowerPC 401 implementation */
1984 static void gen_spr_401 (CPUPPCState *env)
1985 {
1986 /* Debug interface */
1987 /* XXX : not implemented */
1988 spr_register(env, SPR_40x_DBCR0, "DBCR",
1989 SPR_NOACCESS, SPR_NOACCESS,
1990 &spr_read_generic, &spr_write_40x_dbcr0,
1991 0x00000000);
1992 /* XXX : not implemented */
1993 spr_register(env, SPR_40x_DBSR, "DBSR",
1994 SPR_NOACCESS, SPR_NOACCESS,
1995 &spr_read_generic, &spr_write_clear,
1996 /* Last reset was system reset */
1997 0x00000300);
1998 /* XXX : not implemented */
1999 spr_register(env, SPR_40x_DAC1, "DAC",
2000 SPR_NOACCESS, SPR_NOACCESS,
2001 &spr_read_generic, &spr_write_generic,
2002 0x00000000);
2003 /* XXX : not implemented */
2004 spr_register(env, SPR_40x_IAC1, "IAC",
2005 SPR_NOACCESS, SPR_NOACCESS,
2006 &spr_read_generic, &spr_write_generic,
2007 0x00000000);
2008 /* Storage control */
2009 /* XXX: TODO: not implemented */
2010 spr_register(env, SPR_405_SLER, "SLER",
2011 SPR_NOACCESS, SPR_NOACCESS,
2012 &spr_read_generic, &spr_write_40x_sler,
2013 0x00000000);
2014 /* not emulated, as Qemu never does speculative access */
2015 spr_register(env, SPR_40x_SGR, "SGR",
2016 SPR_NOACCESS, SPR_NOACCESS,
2017 &spr_read_generic, &spr_write_generic,
2018 0xFFFFFFFF);
2019 /* not emulated, as Qemu do not emulate caches */
2020 spr_register(env, SPR_40x_DCWR, "DCWR",
2021 SPR_NOACCESS, SPR_NOACCESS,
2022 &spr_read_generic, &spr_write_generic,
2023 0x00000000);
2024 }
2025
2026 static void gen_spr_401x2 (CPUPPCState *env)
2027 {
2028 gen_spr_401(env);
2029 spr_register(env, SPR_40x_PID, "PID",
2030 SPR_NOACCESS, SPR_NOACCESS,
2031 &spr_read_generic, &spr_write_generic,
2032 0x00000000);
2033 spr_register(env, SPR_40x_ZPR, "ZPR",
2034 SPR_NOACCESS, SPR_NOACCESS,
2035 &spr_read_generic, &spr_write_generic,
2036 0x00000000);
2037 }
2038
2039 /* SPR specific to PowerPC 403 implementation */
2040 static void gen_spr_403 (CPUPPCState *env)
2041 {
2042 /* Debug interface */
2043 /* XXX : not implemented */
2044 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2045 SPR_NOACCESS, SPR_NOACCESS,
2046 &spr_read_generic, &spr_write_40x_dbcr0,
2047 0x00000000);
2048 /* XXX : not implemented */
2049 spr_register(env, SPR_40x_DBSR, "DBSR",
2050 SPR_NOACCESS, SPR_NOACCESS,
2051 &spr_read_generic, &spr_write_clear,
2052 /* Last reset was system reset */
2053 0x00000300);
2054 /* XXX : not implemented */
2055 spr_register(env, SPR_40x_DAC1, "DAC1",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 &spr_read_generic, &spr_write_generic,
2058 0x00000000);
2059 /* XXX : not implemented */
2060 spr_register(env, SPR_40x_DAC2, "DAC2",
2061 SPR_NOACCESS, SPR_NOACCESS,
2062 &spr_read_generic, &spr_write_generic,
2063 0x00000000);
2064 /* XXX : not implemented */
2065 spr_register(env, SPR_40x_IAC1, "IAC1",
2066 SPR_NOACCESS, SPR_NOACCESS,
2067 &spr_read_generic, &spr_write_generic,
2068 0x00000000);
2069 /* XXX : not implemented */
2070 spr_register(env, SPR_40x_IAC2, "IAC2",
2071 SPR_NOACCESS, SPR_NOACCESS,
2072 &spr_read_generic, &spr_write_generic,
2073 0x00000000);
2074 }
2075
2076 static void gen_spr_403_real (CPUPPCState *env)
2077 {
2078 spr_register(env, SPR_403_PBL1, "PBL1",
2079 SPR_NOACCESS, SPR_NOACCESS,
2080 &spr_read_403_pbr, &spr_write_403_pbr,
2081 0x00000000);
2082 spr_register(env, SPR_403_PBU1, "PBU1",
2083 SPR_NOACCESS, SPR_NOACCESS,
2084 &spr_read_403_pbr, &spr_write_403_pbr,
2085 0x00000000);
2086 spr_register(env, SPR_403_PBL2, "PBL2",
2087 SPR_NOACCESS, SPR_NOACCESS,
2088 &spr_read_403_pbr, &spr_write_403_pbr,
2089 0x00000000);
2090 spr_register(env, SPR_403_PBU2, "PBU2",
2091 SPR_NOACCESS, SPR_NOACCESS,
2092 &spr_read_403_pbr, &spr_write_403_pbr,
2093 0x00000000);
2094 }
2095
2096 static void gen_spr_403_mmu (CPUPPCState *env)
2097 {
2098 /* MMU */
2099 spr_register(env, SPR_40x_PID, "PID",
2100 SPR_NOACCESS, SPR_NOACCESS,
2101 &spr_read_generic, &spr_write_generic,
2102 0x00000000);
2103 spr_register(env, SPR_40x_ZPR, "ZPR",
2104 SPR_NOACCESS, SPR_NOACCESS,
2105 &spr_read_generic, &spr_write_generic,
2106 0x00000000);
2107 }
2108
2109 /* SPR specific to PowerPC compression coprocessor extension */
2110 static void gen_spr_compress (CPUPPCState *env)
2111 {
2112 /* XXX : not implemented */
2113 spr_register(env, SPR_401_SKR, "SKR",
2114 SPR_NOACCESS, SPR_NOACCESS,
2115 &spr_read_generic, &spr_write_generic,
2116 0x00000000);
2117 }
2118
2119 #if defined (TARGET_PPC64)
2120 /* SPR specific to PowerPC 620 */
2121 static void gen_spr_620 (CPUPPCState *env)
2122 {
2123 /* Processor identification */
2124 spr_register(env, SPR_PIR, "PIR",
2125 SPR_NOACCESS, SPR_NOACCESS,
2126 &spr_read_generic, &spr_write_pir,
2127 0x00000000);
2128 spr_register(env, SPR_ASR, "ASR",
2129 SPR_NOACCESS, SPR_NOACCESS,
2130 &spr_read_asr, &spr_write_asr,
2131 0x00000000);
2132 /* Breakpoints */
2133 /* XXX : not implemented */
2134 spr_register(env, SPR_IABR, "IABR",
2135 SPR_NOACCESS, SPR_NOACCESS,
2136 &spr_read_generic, &spr_write_generic,
2137 0x00000000);
2138 /* XXX : not implemented */
2139 spr_register(env, SPR_DABR, "DABR",
2140 SPR_NOACCESS, SPR_NOACCESS,
2141 &spr_read_generic, &spr_write_generic,
2142 0x00000000);
2143 /* XXX : not implemented */
2144 spr_register(env, SPR_SIAR, "SIAR",
2145 SPR_NOACCESS, SPR_NOACCESS,
2146 &spr_read_generic, SPR_NOACCESS,
2147 0x00000000);
2148 /* XXX : not implemented */
2149 spr_register(env, SPR_SDA, "SDA",
2150 SPR_NOACCESS, SPR_NOACCESS,
2151 &spr_read_generic, SPR_NOACCESS,
2152 0x00000000);
2153 /* XXX : not implemented */
2154 spr_register(env, SPR_620_PMC1R, "PMC1",
2155 SPR_NOACCESS, SPR_NOACCESS,
2156 &spr_read_generic, SPR_NOACCESS,
2157 0x00000000);
2158 spr_register(env, SPR_620_PMC1W, "PMC1",
2159 SPR_NOACCESS, SPR_NOACCESS,
2160 SPR_NOACCESS, &spr_write_generic,
2161 0x00000000);
2162 /* XXX : not implemented */
2163 spr_register(env, SPR_620_PMC2R, "PMC2",
2164 SPR_NOACCESS, SPR_NOACCESS,
2165 &spr_read_generic, SPR_NOACCESS,
2166 0x00000000);
2167 spr_register(env, SPR_620_PMC2W, "PMC2",
2168 SPR_NOACCESS, SPR_NOACCESS,
2169 SPR_NOACCESS, &spr_write_generic,
2170 0x00000000);
2171 /* XXX : not implemented */
2172 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2173 SPR_NOACCESS, SPR_NOACCESS,
2174 &spr_read_generic, SPR_NOACCESS,
2175 0x00000000);
2176 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2177 SPR_NOACCESS, SPR_NOACCESS,
2178 SPR_NOACCESS, &spr_write_generic,
2179 0x00000000);
2180 /* External access control */
2181 /* XXX : not implemented */
2182 spr_register(env, SPR_EAR, "EAR",
2183 SPR_NOACCESS, SPR_NOACCESS,
2184 &spr_read_generic, &spr_write_generic,
2185 0x00000000);
2186 #if 0 // XXX: check this
2187 /* XXX : not implemented */
2188 spr_register(env, SPR_620_PMR0, "PMR0",
2189 SPR_NOACCESS, SPR_NOACCESS,
2190 &spr_read_generic, &spr_write_generic,
2191 0x00000000);
2192 /* XXX : not implemented */
2193 spr_register(env, SPR_620_PMR1, "PMR1",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 &spr_read_generic, &spr_write_generic,
2196 0x00000000);
2197 /* XXX : not implemented */
2198 spr_register(env, SPR_620_PMR2, "PMR2",
2199 SPR_NOACCESS, SPR_NOACCESS,
2200 &spr_read_generic, &spr_write_generic,
2201 0x00000000);
2202 /* XXX : not implemented */
2203 spr_register(env, SPR_620_PMR3, "PMR3",
2204 SPR_NOACCESS, SPR_NOACCESS,
2205 &spr_read_generic, &spr_write_generic,
2206 0x00000000);
2207 /* XXX : not implemented */
2208 spr_register(env, SPR_620_PMR4, "PMR4",
2209 SPR_NOACCESS, SPR_NOACCESS,
2210 &spr_read_generic, &spr_write_generic,
2211 0x00000000);
2212 /* XXX : not implemented */
2213 spr_register(env, SPR_620_PMR5, "PMR5",
2214 SPR_NOACCESS, SPR_NOACCESS,
2215 &spr_read_generic, &spr_write_generic,
2216 0x00000000);
2217 /* XXX : not implemented */
2218 spr_register(env, SPR_620_PMR6, "PMR6",
2219 SPR_NOACCESS, SPR_NOACCESS,
2220 &spr_read_generic, &spr_write_generic,
2221 0x00000000);
2222 /* XXX : not implemented */
2223 spr_register(env, SPR_620_PMR7, "PMR7",
2224 SPR_NOACCESS, SPR_NOACCESS,
2225 &spr_read_generic, &spr_write_generic,
2226 0x00000000);
2227 /* XXX : not implemented */
2228 spr_register(env, SPR_620_PMR8, "PMR8",
2229 SPR_NOACCESS, SPR_NOACCESS,
2230 &spr_read_generic, &spr_write_generic,
2231 0x00000000);
2232 /* XXX : not implemented */
2233 spr_register(env, SPR_620_PMR9, "PMR9",
2234 SPR_NOACCESS, SPR_NOACCESS,
2235 &spr_read_generic, &spr_write_generic,
2236 0x00000000);
2237 /* XXX : not implemented */
2238 spr_register(env, SPR_620_PMRA, "PMR10",
2239 SPR_NOACCESS, SPR_NOACCESS,
2240 &spr_read_generic, &spr_write_generic,
2241 0x00000000);
2242 /* XXX : not implemented */
2243 spr_register(env, SPR_620_PMRB, "PMR11",
2244 SPR_NOACCESS, SPR_NOACCESS,
2245 &spr_read_generic, &spr_write_generic,
2246 0x00000000);
2247 /* XXX : not implemented */
2248 spr_register(env, SPR_620_PMRC, "PMR12",
2249 SPR_NOACCESS, SPR_NOACCESS,
2250 &spr_read_generic, &spr_write_generic,
2251 0x00000000);
2252 /* XXX : not implemented */
2253 spr_register(env, SPR_620_PMRD, "PMR13",
2254 SPR_NOACCESS, SPR_NOACCESS,
2255 &spr_read_generic, &spr_write_generic,
2256 0x00000000);
2257 /* XXX : not implemented */
2258 spr_register(env, SPR_620_PMRE, "PMR14",
2259 SPR_NOACCESS, SPR_NOACCESS,
2260 &spr_read_generic, &spr_write_generic,
2261 0x00000000);
2262 /* XXX : not implemented */
2263 spr_register(env, SPR_620_PMRF, "PMR15",
2264 SPR_NOACCESS, SPR_NOACCESS,
2265 &spr_read_generic, &spr_write_generic,
2266 0x00000000);
2267 #endif
2268 /* XXX : not implemented */
2269 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2270 SPR_NOACCESS, SPR_NOACCESS,
2271 &spr_read_generic, &spr_write_generic,
2272 0x00000000);
2273 /* XXX : not implemented */
2274 spr_register(env, SPR_620_L2CR, "L2CR",
2275 SPR_NOACCESS, SPR_NOACCESS,
2276 &spr_read_generic, &spr_write_generic,
2277 0x00000000);
2278 /* XXX : not implemented */
2279 spr_register(env, SPR_620_L2SR, "L2SR",
2280 SPR_NOACCESS, SPR_NOACCESS,
2281 &spr_read_generic, &spr_write_generic,
2282 0x00000000);
2283 }
2284 #endif /* defined (TARGET_PPC64) */
2285
2286 static void gen_spr_5xx_8xx (CPUPPCState *env)
2287 {
2288 /* Exception processing */
2289 spr_register(env, SPR_DSISR, "DSISR",
2290 SPR_NOACCESS, SPR_NOACCESS,
2291 &spr_read_generic, &spr_write_generic,
2292 0x00000000);
2293 spr_register(env, SPR_DAR, "DAR",
2294 SPR_NOACCESS, SPR_NOACCESS,
2295 &spr_read_generic, &spr_write_generic,
2296 0x00000000);
2297 /* Timer */
2298 spr_register(env, SPR_DECR, "DECR",
2299 SPR_NOACCESS, SPR_NOACCESS,
2300 &spr_read_decr, &spr_write_decr,
2301 0x00000000);
2302 /* XXX : not implemented */
2303 spr_register(env, SPR_MPC_EIE, "EIE",
2304 SPR_NOACCESS, SPR_NOACCESS,
2305 &spr_read_generic, &spr_write_generic,
2306 0x00000000);
2307 /* XXX : not implemented */
2308 spr_register(env, SPR_MPC_EID, "EID",
2309 SPR_NOACCESS, SPR_NOACCESS,
2310 &spr_read_generic, &spr_write_generic,
2311 0x00000000);
2312 /* XXX : not implemented */
2313 spr_register(env, SPR_MPC_NRI, "NRI",
2314 SPR_NOACCESS, SPR_NOACCESS,
2315 &spr_read_generic, &spr_write_generic,
2316 0x00000000);
2317 /* XXX : not implemented */
2318 spr_register(env, SPR_MPC_CMPA, "CMPA",
2319 SPR_NOACCESS, SPR_NOACCESS,
2320 &spr_read_generic, &spr_write_generic,
2321 0x00000000);
2322 /* XXX : not implemented */
2323 spr_register(env, SPR_MPC_CMPB, "CMPB",
2324 SPR_NOACCESS, SPR_NOACCESS,
2325 &spr_read_generic, &spr_write_generic,
2326 0x00000000);
2327 /* XXX : not implemented */
2328 spr_register(env, SPR_MPC_CMPC, "CMPC",
2329 SPR_NOACCESS, SPR_NOACCESS,
2330 &spr_read_generic, &spr_write_generic,
2331 0x00000000);
2332 /* XXX : not implemented */
2333 spr_register(env, SPR_MPC_CMPD, "CMPD",
2334 SPR_NOACCESS, SPR_NOACCESS,
2335 &spr_read_generic, &spr_write_generic,
2336 0x00000000);
2337 /* XXX : not implemented */
2338 spr_register(env, SPR_MPC_ECR, "ECR",
2339 SPR_NOACCESS, SPR_NOACCESS,
2340 &spr_read_generic, &spr_write_generic,
2341 0x00000000);
2342 /* XXX : not implemented */
2343 spr_register(env, SPR_MPC_DER, "DER",
2344 SPR_NOACCESS, SPR_NOACCESS,
2345 &spr_read_generic, &spr_write_generic,
2346 0x00000000);
2347 /* XXX : not implemented */
2348 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2349 SPR_NOACCESS, SPR_NOACCESS,
2350 &spr_read_generic, &spr_write_generic,
2351 0x00000000);
2352 /* XXX : not implemented */
2353 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2354 SPR_NOACCESS, SPR_NOACCESS,
2355 &spr_read_generic, &spr_write_generic,
2356 0x00000000);
2357 /* XXX : not implemented */
2358 spr_register(env, SPR_MPC_CMPE, "CMPE",
2359 SPR_NOACCESS, SPR_NOACCESS,
2360 &spr_read_generic, &spr_write_generic,
2361 0x00000000);
2362 /* XXX : not implemented */
2363 spr_register(env, SPR_MPC_CMPF, "CMPF",
2364 SPR_NOACCESS, SPR_NOACCESS,
2365 &spr_read_generic, &spr_write_generic,
2366 0x00000000);
2367 /* XXX : not implemented */
2368 spr_register(env, SPR_MPC_CMPG, "CMPG",
2369 SPR_NOACCESS, SPR_NOACCESS,
2370 &spr_read_generic, &spr_write_generic,
2371 0x00000000);
2372 /* XXX : not implemented */
2373 spr_register(env, SPR_MPC_CMPH, "CMPH",
2374 SPR_NOACCESS, SPR_NOACCESS,
2375 &spr_read_generic, &spr_write_generic,
2376 0x00000000);
2377 /* XXX : not implemented */
2378 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2379 SPR_NOACCESS, SPR_NOACCESS,
2380 &spr_read_generic, &spr_write_generic,
2381 0x00000000);
2382 /* XXX : not implemented */
2383 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2384 SPR_NOACCESS, SPR_NOACCESS,
2385 &spr_read_generic, &spr_write_generic,
2386 0x00000000);
2387 /* XXX : not implemented */
2388 spr_register(env, SPR_MPC_BAR, "BAR",
2389 SPR_NOACCESS, SPR_NOACCESS,
2390 &spr_read_generic, &spr_write_generic,
2391 0x00000000);
2392 /* XXX : not implemented */
2393 spr_register(env, SPR_MPC_DPDR, "DPDR",
2394 SPR_NOACCESS, SPR_NOACCESS,
2395 &spr_read_generic, &spr_write_generic,
2396 0x00000000);
2397 /* XXX : not implemented */
2398 spr_register(env, SPR_MPC_IMMR, "IMMR",
2399 SPR_NOACCESS, SPR_NOACCESS,
2400 &spr_read_generic, &spr_write_generic,
2401 0x00000000);
2402 }
2403
2404 static void gen_spr_5xx (CPUPPCState *env)
2405 {
2406 /* XXX : not implemented */
2407 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2408 SPR_NOACCESS, SPR_NOACCESS,
2409 &spr_read_generic, &spr_write_generic,
2410 0x00000000);
2411 /* XXX : not implemented */
2412 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2413 SPR_NOACCESS, SPR_NOACCESS,
2414 &spr_read_generic, &spr_write_generic,
2415 0x00000000);
2416 /* XXX : not implemented */
2417 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2418 SPR_NOACCESS, SPR_NOACCESS,
2419 &spr_read_generic, &spr_write_generic,
2420 0x00000000);
2421 /* XXX : not implemented */
2422 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2423 SPR_NOACCESS, SPR_NOACCESS,
2424 &spr_read_generic, &spr_write_generic,
2425 0x00000000);
2426 /* XXX : not implemented */
2427 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2428 SPR_NOACCESS, SPR_NOACCESS,
2429 &spr_read_generic, &spr_write_generic,
2430 0x00000000);
2431 /* XXX : not implemented */
2432 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2433 SPR_NOACCESS, SPR_NOACCESS,
2434 &spr_read_generic, &spr_write_generic,
2435 0x00000000);
2436 /* XXX : not implemented */
2437 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2438 SPR_NOACCESS, SPR_NOACCESS,
2439 &spr_read_generic, &spr_write_generic,
2440 0x00000000);
2441 /* XXX : not implemented */
2442 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2443 SPR_NOACCESS, SPR_NOACCESS,
2444 &spr_read_generic, &spr_write_generic,
2445 0x00000000);
2446 /* XXX : not implemented */
2447 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2448 SPR_NOACCESS, SPR_NOACCESS,
2449 &spr_read_generic, &spr_write_generic,
2450 0x00000000);
2451 /* XXX : not implemented */
2452 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2453 SPR_NOACCESS, SPR_NOACCESS,
2454 &spr_read_generic, &spr_write_generic,
2455 0x00000000);
2456 /* XXX : not implemented */
2457 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2458 SPR_NOACCESS, SPR_NOACCESS,
2459 &spr_read_generic, &spr_write_generic,
2460 0x00000000);
2461 /* XXX : not implemented */
2462 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2463 SPR_NOACCESS, SPR_NOACCESS,
2464 &spr_read_generic, &spr_write_generic,
2465 0x00000000);
2466 /* XXX : not implemented */
2467 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2468 SPR_NOACCESS, SPR_NOACCESS,
2469 &spr_read_generic, &spr_write_generic,
2470 0x00000000);
2471 /* XXX : not implemented */
2472 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2473 SPR_NOACCESS, SPR_NOACCESS,
2474 &spr_read_generic, &spr_write_generic,
2475 0x00000000);
2476 /* XXX : not implemented */
2477 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2478 SPR_NOACCESS, SPR_NOACCESS,
2479 &spr_read_generic, &spr_write_generic,
2480 0x00000000);
2481 /* XXX : not implemented */
2482 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2483 SPR_NOACCESS, SPR_NOACCESS,
2484 &spr_read_generic, &spr_write_generic,
2485 0x00000000);
2486 /* XXX : not implemented */
2487 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2488 SPR_NOACCESS, SPR_NOACCESS,
2489 &spr_read_generic, &spr_write_generic,
2490 0x00000000);
2491 /* XXX : not implemented */
2492 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2493 SPR_NOACCESS, SPR_NOACCESS,
2494 &spr_read_generic, &spr_write_generic,
2495 0x00000000);
2496 /* XXX : not implemented */
2497 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2498 SPR_NOACCESS, SPR_NOACCESS,
2499 &spr_read_generic, &spr_write_generic,
2500 0x00000000);
2501 /* XXX : not implemented */
2502 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2503 SPR_NOACCESS, SPR_NOACCESS,
2504 &spr_read_generic, &spr_write_generic,
2505 0x00000000);
2506 /* XXX : not implemented */
2507 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2508 SPR_NOACCESS, SPR_NOACCESS,
2509 &spr_read_generic, &spr_write_generic,
2510 0x00000000);
2511 }
2512
2513 static void gen_spr_8xx (CPUPPCState *env)
2514 {
2515 /* XXX : not implemented */
2516 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2517 SPR_NOACCESS, SPR_NOACCESS,
2518 &spr_read_generic, &spr_write_generic,
2519 0x00000000);
2520 /* XXX : not implemented */
2521 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2522 SPR_NOACCESS, SPR_NOACCESS,
2523 &spr_read_generic, &spr_write_generic,
2524 0x00000000);
2525 /* XXX : not implemented */
2526 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2527 SPR_NOACCESS, SPR_NOACCESS,
2528 &spr_read_generic, &spr_write_generic,
2529 0x00000000);
2530 /* XXX : not implemented */
2531 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2532 SPR_NOACCESS, SPR_NOACCESS,
2533 &spr_read_generic, &spr_write_generic,
2534 0x00000000);
2535 /* XXX : not implemented */
2536 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2537 SPR_NOACCESS, SPR_NOACCESS,
2538 &spr_read_generic, &spr_write_generic,
2539 0x00000000);
2540 /* XXX : not implemented */
2541 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2542 SPR_NOACCESS, SPR_NOACCESS,
2543 &spr_read_generic, &spr_write_generic,
2544 0x00000000);
2545 /* XXX : not implemented */
2546 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2547 SPR_NOACCESS, SPR_NOACCESS,
2548 &spr_read_generic, &spr_write_generic,
2549 0x00000000);
2550 /* XXX : not implemented */
2551 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2552 SPR_NOACCESS, SPR_NOACCESS,
2553 &spr_read_generic, &spr_write_generic,
2554 0x00000000);
2555 /* XXX : not implemented */
2556 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2557 SPR_NOACCESS, SPR_NOACCESS,
2558 &spr_read_generic, &spr_write_generic,
2559 0x00000000);
2560 /* XXX : not implemented */
2561 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2562 SPR_NOACCESS, SPR_NOACCESS,
2563 &spr_read_generic, &spr_write_generic,
2564 0x00000000);
2565 /* XXX : not implemented */
2566 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2567 SPR_NOACCESS, SPR_NOACCESS,
2568 &spr_read_generic, &spr_write_generic,
2569 0x00000000);
2570 /* XXX : not implemented */
2571 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2572 SPR_NOACCESS, SPR_NOACCESS,
2573 &spr_read_generic, &spr_write_generic,
2574 0x00000000);
2575 /* XXX : not implemented */
2576 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2577 SPR_NOACCESS, SPR_NOACCESS,
2578 &spr_read_generic, &spr_write_generic,
2579 0x00000000);
2580 /* XXX : not implemented */
2581 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2582 SPR_NOACCESS, SPR_NOACCESS,
2583 &spr_read_generic, &spr_write_generic,
2584 0x00000000);
2585 /* XXX : not implemented */
2586 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2587 SPR_NOACCESS, SPR_NOACCESS,
2588 &spr_read_generic, &spr_write_generic,
2589 0x00000000);
2590 /* XXX : not implemented */
2591 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2592 SPR_NOACCESS, SPR_NOACCESS,
2593 &spr_read_generic, &spr_write_generic,
2594 0x00000000);
2595 /* XXX : not implemented */
2596 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2597 SPR_NOACCESS, SPR_NOACCESS,
2598 &spr_read_generic, &spr_write_generic,
2599 0x00000000);
2600 /* XXX : not implemented */
2601 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2602 SPR_NOACCESS, SPR_NOACCESS,
2603 &spr_read_generic, &spr_write_generic,
2604 0x00000000);
2605 /* XXX : not implemented */
2606 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2607 SPR_NOACCESS, SPR_NOACCESS,
2608 &spr_read_generic, &spr_write_generic,
2609 0x00000000);
2610 /* XXX : not implemented */
2611 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2612 SPR_NOACCESS, SPR_NOACCESS,
2613 &spr_read_generic, &spr_write_generic,
2614 0x00000000);
2615 /* XXX : not implemented */
2616 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2617 SPR_NOACCESS, SPR_NOACCESS,
2618 &spr_read_generic, &spr_write_generic,
2619 0x00000000);
2620 /* XXX : not implemented */
2621 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2622 SPR_NOACCESS, SPR_NOACCESS,
2623 &spr_read_generic, &spr_write_generic,
2624 0x00000000);
2625 /* XXX : not implemented */
2626 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2627 SPR_NOACCESS, SPR_NOACCESS,
2628 &spr_read_generic, &spr_write_generic,
2629 0x00000000);
2630 /* XXX : not implemented */
2631 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2632 SPR_NOACCESS, SPR_NOACCESS,
2633 &spr_read_generic, &spr_write_generic,
2634 0x00000000);
2635 /* XXX : not implemented */
2636 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2637 SPR_NOACCESS, SPR_NOACCESS,
2638 &spr_read_generic, &spr_write_generic,
2639 0x00000000);
2640 }
2641
2642 // XXX: TODO
2643 /*
2644 * AMR => SPR 29 (Power 2.04)
2645 * CTRL => SPR 136 (Power 2.04)
2646 * CTRL => SPR 152 (Power 2.04)
2647 * SCOMC => SPR 276 (64 bits ?)
2648 * SCOMD => SPR 277 (64 bits ?)
2649 * TBU40 => SPR 286 (Power 2.04 hypv)
2650 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2651 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2652 * HDSISR => SPR 306 (Power 2.04 hypv)
2653 * HDAR => SPR 307 (Power 2.04 hypv)
2654 * PURR => SPR 309 (Power 2.04 hypv)
2655 * HDEC => SPR 310 (Power 2.04 hypv)
2656 * HIOR => SPR 311 (hypv)
2657 * RMOR => SPR 312 (970)
2658 * HRMOR => SPR 313 (Power 2.04 hypv)
2659 * HSRR0 => SPR 314 (Power 2.04 hypv)
2660 * HSRR1 => SPR 315 (Power 2.04 hypv)
2661 * LPCR => SPR 316 (970)
2662 * LPIDR => SPR 317 (970)
2663 * EPR => SPR 702 (Power 2.04 emb)
2664 * perf => 768-783 (Power 2.04)
2665 * perf => 784-799 (Power 2.04)
2666 * PPR => SPR 896 (Power 2.04)
2667 * EPLC => SPR 947 (Power 2.04 emb)
2668 * EPSC => SPR 948 (Power 2.04 emb)
2669 * DABRX => 1015 (Power 2.04 hypv)
2670 * FPECR => SPR 1022 (?)
2671 * ... and more (thermal management, performance counters, ...)
2672 */
2673
2674 /*****************************************************************************/
2675 /* Exception vectors models */
2676 static void init_excp_4xx_real (CPUPPCState *env)
2677 {
2678 #if !defined(CONFIG_USER_ONLY)
2679 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2680 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2681 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2682 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2683 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2684 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2685 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2686 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2687 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2688 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2689 env->hreset_excp_prefix = 0x00000000UL;
2690 env->ivor_mask = 0x0000FFF0UL;
2691 env->ivpr_mask = 0xFFFF0000UL;
2692 /* Hardware reset vector */
2693 env->hreset_vector = 0xFFFFFFFCUL;
2694 #endif
2695 }
2696
2697 static void init_excp_4xx_softmmu (CPUPPCState *env)
2698 {
2699 #if !defined(CONFIG_USER_ONLY)
2700 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2701 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2702 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2703 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2704 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2705 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2706 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2707 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2708 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2709 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2710 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2711 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2712 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2713 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2714 env->hreset_excp_prefix = 0x00000000UL;
2715 env->ivor_mask = 0x0000FFF0UL;
2716 env->ivpr_mask = 0xFFFF0000UL;
2717 /* Hardware reset vector */
2718 env->hreset_vector = 0xFFFFFFFCUL;
2719 #endif
2720 }
2721
2722 static void init_excp_MPC5xx (CPUPPCState *env)
2723 {
2724 #if !defined(CONFIG_USER_ONLY)
2725 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2726 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2727 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2728 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2729 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2730 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2731 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2732 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2733 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2734 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2735 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2736 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2737 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2738 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2739 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2740 env->hreset_excp_prefix = 0x00000000UL;
2741 env->ivor_mask = 0x0000FFF0UL;
2742 env->ivpr_mask = 0xFFFF0000UL;
2743 /* Hardware reset vector */
2744 env->hreset_vector = 0xFFFFFFFCUL;
2745 #endif
2746 }
2747
2748 static void init_excp_MPC8xx (CPUPPCState *env)
2749 {
2750 #if !defined(CONFIG_USER_ONLY)
2751 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2752 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2753 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2754 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2755 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2756 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2757 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2758 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2759 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2760 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2761 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2762 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2763 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2764 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2765 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2766 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2767 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2768 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2769 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2770 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2771 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2772 env->hreset_excp_prefix = 0x00000000UL;
2773 env->ivor_mask = 0x0000FFF0UL;
2774 env->ivpr_mask = 0xFFFF0000UL;
2775 /* Hardware reset vector */
2776 env->hreset_vector = 0xFFFFFFFCUL;
2777 #endif
2778 }
2779
2780 static void init_excp_G2 (CPUPPCState *env)
2781 {
2782 #if !defined(CONFIG_USER_ONLY)
2783 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2784 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2785 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2786 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2787 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2788 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2789 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2790 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2791 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2792 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2793 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2794 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2795 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2796 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2797 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2798 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2799 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2800 env->hreset_excp_prefix = 0x00000000UL;
2801 /* Hardware reset vector */
2802 env->hreset_vector = 0xFFFFFFFCUL;
2803 #endif
2804 }
2805
2806 static void init_excp_e200 (CPUPPCState *env)
2807 {
2808 #if !defined(CONFIG_USER_ONLY)
2809 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2810 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2811 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2812 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2813 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2814 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2815 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2816 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2817 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2818 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2819 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2820 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2821 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2822 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2823 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2824 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2825 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2826 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2827 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2828 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2829 env->hreset_excp_prefix = 0x00000000UL;
2830 env->ivor_mask = 0x0000FFF7UL;
2831 env->ivpr_mask = 0xFFFF0000UL;
2832 /* Hardware reset vector */
2833 env->hreset_vector = 0xFFFFFFFCUL;
2834 #endif
2835 }
2836
2837 static void init_excp_BookE (CPUPPCState *env)
2838 {
2839 #if !defined(CONFIG_USER_ONLY)
2840 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2841 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2842 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2843 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2844 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2845 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2846 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2847 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2848 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2849 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2850 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2851 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2852 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2853 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2854 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2855 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2856 env->hreset_excp_prefix = 0x00000000UL;
2857 env->ivor_mask = 0x0000FFE0UL;
2858 env->ivpr_mask = 0xFFFF0000UL;
2859 /* Hardware reset vector */
2860 env->hreset_vector = 0xFFFFFFFCUL;
2861 #endif
2862 }
2863
2864 static void init_excp_601 (CPUPPCState *env)
2865 {
2866 #if !defined(CONFIG_USER_ONLY)
2867 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2868 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2869 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2870 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2871 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2872 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2873 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2874 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2875 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2876 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2877 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2878 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2879 env->hreset_excp_prefix = 0xFFF00000UL;
2880 /* Hardware reset vector */
2881 env->hreset_vector = 0x00000100UL;
2882 #endif
2883 }
2884
2885 static void init_excp_602 (CPUPPCState *env)
2886 {
2887 #if !defined(CONFIG_USER_ONLY)
2888 /* XXX: exception prefix has a special behavior on 602 */
2889 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2890 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2891 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2892 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2893 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2894 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2895 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2896 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2897 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2898 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2899 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2900 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2901 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2902 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2903 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2904 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2905 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2906 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2907 env->hreset_excp_prefix = 0xFFF00000UL;
2908 /* Hardware reset vector */
2909 env->hreset_vector = 0xFFFFFFFCUL;
2910 #endif
2911 }
2912
2913 static void init_excp_603 (CPUPPCState *env)
2914 {
2915 #if !defined(CONFIG_USER_ONLY)
2916 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2917 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2918 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2919 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2920 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2921 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2922 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2923 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2924 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2925 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2926 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2927 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2928 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2929 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2930 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2931 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2932 env->hreset_excp_prefix = 0x00000000UL;
2933 /* Hardware reset vector */
2934 env->hreset_vector = 0xFFFFFFFCUL;
2935 #endif
2936 }
2937
2938 static void init_excp_604 (CPUPPCState *env)
2939 {
2940 #if !defined(CONFIG_USER_ONLY)
2941 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2942 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2943 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2944 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2945 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2946 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2947 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2948 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2949 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2950 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2951 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2952 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2953 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2954 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2955 env->hreset_excp_prefix = 0xFFF00000UL;
2956 /* Hardware reset vector */
2957 env->hreset_vector = 0x00000100UL;
2958 #endif
2959 }
2960
2961 #if defined(TARGET_PPC64)
2962 static void init_excp_620 (CPUPPCState *env)
2963 {
2964 #if !defined(CONFIG_USER_ONLY)
2965 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2966 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2967 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2968 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2969 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2970 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2971 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2972 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2973 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2974 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2975 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2976 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2977 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2978 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2979 env->hreset_excp_prefix = 0xFFF00000UL;
2980 /* Hardware reset vector */
2981 env->hreset_vector = 0x0000000000000100ULL;
2982 #endif
2983 }
2984 #endif /* defined(TARGET_PPC64) */
2985
2986 static void init_excp_7x0 (CPUPPCState *env)
2987 {
2988 #if !defined(CONFIG_USER_ONLY)
2989 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2990 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2991 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2992 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2993 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2994 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2995 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2996 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2997 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2998 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2999 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3000 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3001 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3002 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3003 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3004 env->hreset_excp_prefix = 0x00000000UL;
3005 /* Hardware reset vector */
3006 env->hreset_vector = 0xFFFFFFFCUL;
3007 #endif
3008 }
3009
3010 static void init_excp_750cl (CPUPPCState *env)
3011 {
3012 #if !defined(CONFIG_USER_ONLY)
3013 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3014 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3015 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3016 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3017 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3018 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3019 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3020 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3021 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3022 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3023 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3024 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3025 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3026 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3027 env->hreset_excp_prefix = 0x00000000UL;
3028 /* Hardware reset vector */
3029 env->hreset_vector = 0xFFFFFFFCUL;
3030 #endif
3031 }
3032
3033 static void init_excp_750cx (CPUPPCState *env)
3034 {
3035 #if !defined(CONFIG_USER_ONLY)
3036 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3037 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3038 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3039 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3040 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3041 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3042 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3043 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3044 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3045 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3046 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3047 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3048 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3049 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3050 env->hreset_excp_prefix = 0x00000000UL;
3051 /* Hardware reset vector */
3052 env->hreset_vector = 0xFFFFFFFCUL;
3053 #endif
3054 }
3055
3056 /* XXX: Check if this is correct */
3057 static void init_excp_7x5 (CPUPPCState *env)
3058 {
3059 #if !defined(CONFIG_USER_ONLY)
3060 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3061 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3062 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3063 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3064 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3065 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3066 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3067 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3068 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3069 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3070 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3071 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3072 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3073 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3074 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3075 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3076 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3077 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3078 env->hreset_excp_prefix = 0x00000000UL;
3079 /* Hardware reset vector */
3080 env->hreset_vector = 0xFFFFFFFCUL;
3081 #endif
3082 }
3083
3084 static void init_excp_7400 (CPUPPCState *env)
3085 {
3086 #if !defined(CONFIG_USER_ONLY)
3087 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3088 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3089 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3090 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3091 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3092 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3093 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3094 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3095 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3096 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3097 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3098 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3099 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3100 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3101 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3102 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3103 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3104 env->hreset_excp_prefix = 0x00000000UL;
3105 /* Hardware reset vector */
3106 env->hreset_vector = 0xFFFFFFFCUL;
3107 #endif
3108 }
3109
3110 static void init_excp_7450 (CPUPPCState *env)
3111 {
3112 #if !defined(CONFIG_USER_ONLY)
3113 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3114 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3115 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3116 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3117 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3118 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3119 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3120 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3121 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3122 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3123 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3124 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3125 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3126 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3127 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3128 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3129 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3130 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3131 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3132 env->hreset_excp_prefix = 0x00000000UL;
3133 /* Hardware reset vector */
3134 env->hreset_vector = 0xFFFFFFFCUL;
3135 #endif
3136 }
3137
3138 #if defined (TARGET_PPC64)
3139 static void init_excp_970 (CPUPPCState *env)
3140 {
3141 #if !defined(CONFIG_USER_ONLY)
3142 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3143 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3144 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3145 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3146 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3147 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3148 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3149 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3150 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3151 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3152 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3153 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3154 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3155 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3156 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3157 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3158 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3159 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3160 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3161 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3162 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
3163 /* Hardware reset vector */
3164 env->hreset_vector = 0x0000000000000100ULL;
3165 #endif
3166 }
3167
3168 static void init_excp_POWER7 (CPUPPCState *env)
3169 {
3170 #if !defined(CONFIG_USER_ONLY)
3171 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3172 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3173 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3174 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3175 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3176 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3177 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3178 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3179 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3180 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3181 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3182 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3183 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3184 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3185 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3186 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3187 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3188 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3189 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3190 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3191 env->hreset_excp_prefix = 0;
3192 /* Hardware reset vector */
3193 env->hreset_vector = 0x0000000000000100ULL;
3194 #endif
3195 }
3196 #endif
3197
3198 /*****************************************************************************/
3199 /* Power management enable checks */
3200 static int check_pow_none (CPUPPCState *env)
3201 {
3202 return 0;
3203 }
3204
3205 static int check_pow_nocheck (CPUPPCState *env)
3206 {
3207 return 1;
3208 }
3209
3210 static int check_pow_hid0 (CPUPPCState *env)
3211 {
3212 if (env->spr[SPR_HID0] & 0x00E00000)
3213 return 1;
3214
3215 return 0;
3216 }
3217
3218 static int check_pow_hid0_74xx (CPUPPCState *env)
3219 {
3220 if (env->spr[SPR_HID0] & 0x00600000)
3221 return 1;
3222
3223 return 0;
3224 }
3225
3226 /*****************************************************************************/
3227 /* PowerPC implementations definitions */
3228
3229 /* PowerPC 401 */
3230 #define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3231 PPC_WRTEE | PPC_DCR | \
3232 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3233 PPC_CACHE_DCBZ | \
3234 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3235 PPC_4xx_COMMON | PPC_40x_EXCP)
3236 #define POWERPC_INSNS2_401 (PPC_NONE)
3237 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
3238 #define POWERPC_MMU_401 (POWERPC_MMU_REAL)
3239 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3240 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
3241 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
3242 #define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3243 POWERPC_FLAG_BUS_CLK)
3244 #define check_pow_401 check_pow_nocheck
3245
3246 static void init_proc_401 (CPUPPCState *env)
3247 {
3248 gen_spr_40x(env);
3249 gen_spr_401_403(env);
3250 gen_spr_401(env);
3251 init_excp_4xx_real(env);
3252 env->dcache_line_size = 32;
3253 env->icache_line_size = 32;
3254 /* Allocate hardware IRQ controller */
3255 ppc40x_irq_init(env);
3256
3257 SET_FIT_PERIOD(12, 16, 20, 24);
3258 SET_WDT_PERIOD(16, 20, 24, 28);
3259 }
3260
3261 /* PowerPC 401x2 */
3262 #define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3263 PPC_DCR | PPC_WRTEE | \
3264 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3265 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3266 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3267 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3268 PPC_4xx_COMMON | PPC_40x_EXCP)
3269 #define POWERPC_INSNS2_401x2 (PPC_NONE)
3270 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3271 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3272 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3273 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
3274 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
3275 #define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3276 POWERPC_FLAG_BUS_CLK)
3277 #define check_pow_401x2 check_pow_nocheck
3278
3279 static void init_proc_401x2 (CPUPPCState *env)
3280 {
3281 gen_spr_40x(env);
3282 gen_spr_401_403(env);
3283 gen_spr_401x2(env);
3284 gen_spr_compress(env);
3285 /* Memory management */
3286 #if !defined(CONFIG_USER_ONLY)
3287 env->nb_tlb = 64;
3288 env->nb_ways = 1;
3289 env->id_tlbs = 0;
3290 env->tlb_type = TLB_EMB;
3291 #endif
3292 init_excp_4xx_softmmu(env);
3293 env->dcache_line_size = 32;
3294 env->icache_line_size = 32;
3295 /* Allocate hardware IRQ controller */
3296 ppc40x_irq_init(env);
3297
3298 SET_FIT_PERIOD(12, 16, 20, 24);
3299 SET_WDT_PERIOD(16, 20, 24, 28);
3300 }
3301
3302 /* PowerPC 401x3 */
3303 #define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3304 PPC_DCR | PPC_WRTEE | \
3305 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3306 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3307 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3308 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3309 PPC_4xx_COMMON | PPC_40x_EXCP)
3310 #define POWERPC_INSNS2_401x3 (PPC_NONE)
3311 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3312 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3313 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3314 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
3315 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
3316 #define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3317 POWERPC_FLAG_BUS_CLK)
3318 #define check_pow_401x3 check_pow_nocheck
3319
3320 __attribute__ (( unused ))
3321 static void init_proc_401x3 (CPUPPCState *env)
3322 {
3323 gen_spr_40x(env);
3324 gen_spr_401_403(env);
3325 gen_spr_401(env);
3326 gen_spr_401x2(env);
3327 gen_spr_compress(env);
3328 init_excp_4xx_softmmu(env);
3329 env->dcache_line_size = 32;
3330 env->icache_line_size = 32;
3331 /* Allocate hardware IRQ controller */
3332 ppc40x_irq_init(env);
3333
3334 SET_FIT_PERIOD(12, 16, 20, 24);
3335 SET_WDT_PERIOD(16, 20, 24, 28);
3336 }
3337
3338 /* IOP480 */
3339 #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3340 PPC_DCR | PPC_WRTEE | \
3341 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3342 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3343 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3344 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3345 PPC_4xx_COMMON | PPC_40x_EXCP)
3346 #define POWERPC_INSNS2_IOP480 (PPC_NONE)
3347 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3348 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3349 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3350 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
3351 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
3352 #define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3353 POWERPC_FLAG_BUS_CLK)
3354 #define check_pow_IOP480 check_pow_nocheck
3355
3356 static void init_proc_IOP480 (CPUPPCState *env)
3357 {
3358 gen_spr_40x(env);
3359 gen_spr_401_403(env);
3360 gen_spr_401x2(env);
3361 gen_spr_compress(env);
3362 /* Memory management */
3363 #if !defined(CONFIG_USER_ONLY)
3364 env->nb_tlb = 64;
3365 env->nb_ways = 1;
3366 env->id_tlbs = 0;
3367 env->tlb_type = TLB_EMB;
3368 #endif
3369 init_excp_4xx_softmmu(env);
3370 env->dcache_line_size = 32;
3371 env->icache_line_size = 32;
3372 /* Allocate hardware IRQ controller */
3373 ppc40x_irq_init(env);
3374
3375 SET_FIT_PERIOD(8, 12, 16, 20);
3376 SET_WDT_PERIOD(16, 20, 24, 28);
3377 }
3378
3379 /* PowerPC 403 */
3380 #define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3381 PPC_DCR | PPC_WRTEE | \
3382 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3383 PPC_CACHE_DCBZ | \
3384 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3385 PPC_4xx_COMMON | PPC_40x_EXCP)
3386 #define POWERPC_INSNS2_403 (PPC_NONE)
3387 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
3388 #define POWERPC_MMU_403 (POWERPC_MMU_REAL)
3389 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3390 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
3391 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
3392 #define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3393 POWERPC_FLAG_BUS_CLK)
3394 #define check_pow_403 check_pow_nocheck
3395
3396 static void init_proc_403 (CPUPPCState *env)
3397 {
3398 gen_spr_40x(env);
3399 gen_spr_401_403(env);
3400 gen_spr_403(env);
3401 gen_spr_403_real(env);
3402 init_excp_4xx_real(env);
3403 env->dcache_line_size = 32;
3404 env->icache_line_size = 32;
3405 /* Allocate hardware IRQ controller */
3406 ppc40x_irq_init(env);
3407
3408 SET_FIT_PERIOD(8, 12, 16, 20);
3409 SET_WDT_PERIOD(16, 20, 24, 28);
3410 }
3411
3412 /* PowerPC 403 GCX */
3413 #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3414 PPC_DCR | PPC_WRTEE | \
3415 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3416 PPC_CACHE_DCBZ | \
3417 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3418 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3419 PPC_4xx_COMMON | PPC_40x_EXCP)
3420 #define POWERPC_INSNS2_403GCX (PPC_NONE)
3421 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3422 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3423 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3424 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
3425 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
3426 #define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3427 POWERPC_FLAG_BUS_CLK)
3428 #define check_pow_403GCX check_pow_nocheck
3429
3430 static void init_proc_403GCX (CPUPPCState *env)
3431 {
3432 gen_spr_40x(env);
3433 gen_spr_401_403(env);
3434 gen_spr_403(env);
3435 gen_spr_403_real(env);
3436 gen_spr_403_mmu(env);
3437 /* Bus access control */
3438 /* not emulated, as Qemu never does speculative access */
3439 spr_register(env, SPR_40x_SGR, "SGR",
3440 SPR_NOACCESS, SPR_NOACCESS,
3441 &spr_read_generic, &spr_write_generic,
3442 0xFFFFFFFF);
3443 /* not emulated, as Qemu do not emulate caches */
3444 spr_register(env, SPR_40x_DCWR, "DCWR",
3445 SPR_NOACCESS, SPR_NOACCESS,
3446 &spr_read_generic, &spr_write_generic,
3447 0x00000000);
3448 /* Memory management */
3449 #if !defined(CONFIG_USER_ONLY)
3450 env->nb_tlb = 64;
3451 env->nb_ways = 1;
3452 env->id_tlbs = 0;
3453 env->tlb_type = TLB_EMB;
3454 #endif
3455 init_excp_4xx_softmmu(env);
3456 env->dcache_line_size = 32;
3457 env->icache_line_size = 32;
3458 /* Allocate hardware IRQ controller */
3459 ppc40x_irq_init(env);
3460
3461 SET_FIT_PERIOD(8, 12, 16, 20);
3462 SET_WDT_PERIOD(16, 20, 24, 28);
3463 }
3464
3465 /* PowerPC 405 */
3466 #define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3467 PPC_DCR | PPC_WRTEE | \
3468 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3469 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3470 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3471 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3472 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3473 #define POWERPC_INSNS2_405 (PPC_NONE)
3474 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
3475 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3476 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3477 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3478 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3479 #define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3480 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3481 #define check_pow_405 check_pow_nocheck
3482
3483 static void init_proc_405 (CPUPPCState *env)
3484 {
3485 /* Time base */
3486 gen_tbl(env);
3487 gen_spr_40x(env);
3488 gen_spr_405(env);
3489 /* Bus access control */
3490 /* not emulated, as Qemu never does speculative access */
3491 spr_register(env, SPR_40x_SGR, "SGR",
3492 SPR_NOACCESS, SPR_NOACCESS,
3493 &spr_read_generic, &spr_write_generic,
3494 0xFFFFFFFF);
3495 /* not emulated, as Qemu do not emulate caches */
3496 spr_register(env, SPR_40x_DCWR, "DCWR",
3497 SPR_NOACCESS, SPR_NOACCESS,
3498 &spr_read_generic, &spr_write_generic,
3499 0x00000000);
3500 /* Memory management */
3501 #if !defined(CONFIG_USER_ONLY)
3502 env->nb_tlb = 64;
3503 env->nb_ways = 1;
3504 env->id_tlbs = 0;
3505 env->tlb_type = TLB_EMB;
3506 #endif
3507 init_excp_4xx_softmmu(env);
3508 env->dcache_line_size = 32;
3509 env->icache_line_size = 32;
3510 /* Allocate hardware IRQ controller */
3511 ppc40x_irq_init(env);
3512
3513 SET_FIT_PERIOD(8, 12, 16, 20);
3514 SET_WDT_PERIOD(16, 20, 24, 28);
3515 }
3516
3517 /* PowerPC 440 EP */
3518 #define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3519 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3520 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3521 PPC_FLOAT_STFIWX | \
3522 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3523 PPC_CACHE | PPC_CACHE_ICBI | \
3524 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3525 PPC_MEM_TLBSYNC | PPC_MFTB | \
3526 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3527 PPC_440_SPEC)
3528 #define POWERPC_INSNS2_440EP (PPC_NONE)
3529 #define POWERPC_MSRM_440EP (0x000000000006FF30ULL)
3530 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3531 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3532 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3533 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3534 #define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3535 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3536 #define check_pow_440EP check_pow_nocheck
3537
3538 static void init_proc_440EP (CPUPPCState *env)
3539 {
3540 /* Time base */
3541 gen_tbl(env);
3542 gen_spr_BookE(env, 0x000000000000FFFFULL);
3543 gen_spr_440(env);
3544 gen_spr_usprgh(env);
3545 /* Processor identification */
3546 spr_register(env, SPR_BOOKE_PIR, "PIR",
3547 SPR_NOACCESS, SPR_NOACCESS,
3548 &spr_read_generic, &spr_write_pir,
3549 0x00000000);
3550 /* XXX : not implemented */
3551 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3552 SPR_NOACCESS, SPR_NOACCESS,
3553 &spr_read_generic, &spr_write_generic,
3554 0x00000000);
3555 /* XXX : not implemented */
3556 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3557 SPR_NOACCESS, SPR_NOACCESS,
3558 &spr_read_generic, &spr_write_generic,
3559 0x00000000);
3560 /* XXX : not implemented */
3561 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3562 SPR_NOACCESS, SPR_NOACCESS,
3563 &spr_read_generic, &spr_write_generic,
3564 0x00000000);
3565 /* XXX : not implemented */
3566 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3567 SPR_NOACCESS, SPR_NOACCESS,
3568 &spr_read_generic, &spr_write_generic,
3569 0x00000000);
3570 /* XXX : not implemented */
3571 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3572 SPR_NOACCESS, SPR_NOACCESS,
3573 &spr_read_generic, &spr_write_generic,
3574 0x00000000);
3575 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3576 SPR_NOACCESS, SPR_NOACCESS,
3577 &spr_read_generic, &spr_write_generic,
3578 0x00000000);
3579 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3580 SPR_NOACCESS, SPR_NOACCESS,
3581 &spr_read_generic, &spr_write_generic,
3582 0x00000000);
3583 /* XXX : not implemented */
3584 spr_register(env, SPR_440_CCR1, "CCR1",
3585 SPR_NOACCESS, SPR_NOACCESS,
3586 &spr_read_generic, &spr_write_generic,
3587 0x00000000);
3588 /* Memory management */
3589 #if !defined(CONFIG_USER_ONLY)
3590 env->nb_tlb = 64;
3591 env->nb_ways = 1;
3592 env->id_tlbs = 0;
3593 env->tlb_type = TLB_EMB;
3594 #endif
3595 init_excp_BookE(env);
3596 env->dcache_line_size = 32;
3597 env->icache_line_size = 32;
3598 ppc40x_irq_init(env);
3599
3600 SET_FIT_PERIOD(12, 16, 20, 24);
3601 SET_WDT_PERIOD(20, 24, 28, 32);
3602 }
3603
3604 /* PowerPC 440 GP */
3605 #define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3606 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3607 PPC_CACHE | PPC_CACHE_ICBI | \
3608 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3609 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \
3610 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3611 PPC_440_SPEC)
3612 #define POWERPC_INSNS2_440GP (PPC_NONE)
3613 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3614 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3615 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3616 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3617 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3618 #define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3619 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3620 #define check_pow_440GP check_pow_nocheck
3621
3622 __attribute__ (( unused ))
3623 static void init_proc_440GP (CPUPPCState *env)
3624 {
3625 /* Time base */
3626 gen_tbl(env);
3627 gen_spr_BookE(env, 0x000000000000FFFFULL);
3628 gen_spr_440(env);
3629 gen_spr_usprgh(env);
3630 /* Processor identification */
3631 spr_register(env, SPR_BOOKE_PIR, "PIR",
3632 SPR_NOACCESS, SPR_NOACCESS,
3633 &spr_read_generic, &spr_write_pir,
3634 0x00000000);
3635 /* XXX : not implemented */
3636 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3637 SPR_NOACCESS, SPR_NOACCESS,
3638 &spr_read_generic, &spr_write_generic,
3639 0x00000000);
3640 /* XXX : not implemented */
3641 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3642 SPR_NOACCESS, SPR_NOACCESS,
3643 &spr_read_generic, &spr_write_generic,
3644 0x00000000);
3645 /* XXX : not implemented */
3646 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3647 SPR_NOACCESS, SPR_NOACCESS,
3648 &spr_read_generic, &spr_write_generic,
3649 0x00000000);
3650 /* XXX : not implemented */
3651 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3652 SPR_NOACCESS, SPR_NOACCESS,
3653 &spr_read_generic, &spr_write_generic,
3654 0x00000000);
3655 /* Memory management */
3656 #if !defined(CONFIG_USER_ONLY)
3657 env->nb_tlb = 64;
3658 env->nb_ways = 1;
3659 env->id_tlbs = 0;
3660 env->tlb_type = TLB_EMB;
3661 #endif
3662 init_excp_BookE(env);
3663 env->dcache_line_size = 32;
3664 env->icache_line_size = 32;
3665 /* XXX: TODO: allocate internal IRQ controller */
3666
3667 SET_FIT_PERIOD(12, 16, 20, 24);
3668 SET_WDT_PERIOD(20, 24, 28, 32);
3669 }
3670
3671 /* PowerPC 440x4 */
3672 #define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3673 PPC_DCR | PPC_WRTEE | \
3674 PPC_CACHE | PPC_CACHE_ICBI | \
3675 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3676 PPC_MEM_TLBSYNC | PPC_MFTB | \
3677 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3678 PPC_440_SPEC)
3679 #define POWERPC_INSNS2_440x4 (PPC_NONE)
3680 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3681 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3682 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3683 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3684 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3685 #define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3686 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3687 #define check_pow_440x4 check_pow_nocheck
3688
3689 __attribute__ (( unused ))
3690 static void init_proc_440x4 (CPUPPCState *env)
3691 {
3692 /* Time base */
3693 gen_tbl(env);
3694 gen_spr_BookE(env, 0x000000000000FFFFULL);
3695 gen_spr_440(env);
3696 gen_spr_usprgh(env);
3697 /* Processor identification */
3698 spr_register(env, SPR_BOOKE_PIR, "PIR",
3699 SPR_NOACCESS, SPR_NOACCESS,
3700 &spr_read_generic, &spr_write_pir,
3701 0x00000000);
3702 /* XXX : not implemented */
3703 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3704 SPR_NOACCESS, SPR_NOACCESS,
3705 &spr_read_generic, &spr_write_generic,
3706 0x00000000);
3707 /* XXX : not implemented */
3708 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3709 SPR_NOACCESS, SPR_NOACCESS,
3710 &spr_read_generic, &spr_write_generic,
3711 0x00000000);
3712 /* XXX : not implemented */
3713 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3714 SPR_NOACCESS, SPR_NOACCESS,
3715 &spr_read_generic, &spr_write_generic,
3716 0x00000000);
3717 /* XXX : not implemented */
3718 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3719 SPR_NOACCESS, SPR_NOACCESS,
3720 &spr_read_generic, &spr_write_generic,
3721 0x00000000);
3722 /* Memory management */
3723 #if !defined(CONFIG_USER_ONLY)
3724 env->nb_tlb = 64;
3725 env->nb_ways = 1;
3726 env->id_tlbs = 0;
3727 env->tlb_type = TLB_EMB;
3728 #endif
3729 init_excp_BookE(env);
3730 env->dcache_line_size = 32;
3731 env->icache_line_size = 32;
3732 /* XXX: TODO: allocate internal IRQ controller */
3733
3734 SET_FIT_PERIOD(12, 16, 20, 24);
3735 SET_WDT_PERIOD(20, 24, 28, 32);
3736 }
3737
3738 /* PowerPC 440x5 */
3739 #define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3740 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3741 PPC_CACHE | PPC_CACHE_ICBI | \
3742 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3743 PPC_MEM_TLBSYNC | PPC_MFTB | \
3744 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3745 PPC_440_SPEC)
3746 #define POWERPC_INSNS2_440x5 (PPC_NONE)
3747 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3748 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3749 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3750 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3751 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3752 #define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3753 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3754 #define check_pow_440x5 check_pow_nocheck
3755
3756 static void init_proc_440x5 (CPUPPCState *env)
3757 {
3758 /* Time base */
3759 gen_tbl(env);
3760 gen_spr_BookE(env, 0x000000000000FFFFULL);
3761 gen_spr_440(env);
3762 gen_spr_usprgh(env);
3763 /* Processor identification */
3764 spr_register(env, SPR_BOOKE_PIR, "PIR",
3765 SPR_NOACCESS, SPR_NOACCESS,
3766 &spr_read_generic, &spr_write_pir,
3767 0x00000000);
3768 /* XXX : not implemented */
3769 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3770 SPR_NOACCESS, SPR_NOACCESS,
3771 &spr_read_generic, &spr_write_generic,
3772 0x00000000);
3773 /* XXX : not implemented */
3774 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3775 SPR_NOACCESS, SPR_NOACCESS,
3776 &spr_read_generic, &spr_write_generic,
3777 0x00000000);
3778 /* XXX : not implemented */
3779 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3780 SPR_NOACCESS, SPR_NOACCESS,
3781 &spr_read_generic, &spr_write_generic,
3782 0x00000000);
3783 /* XXX : not implemented */
3784 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3785 SPR_NOACCESS, SPR_NOACCESS,
3786 &spr_read_generic, &spr_write_generic,
3787 0x00000000);
3788 /* XXX : not implemented */
3789 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3790 SPR_NOACCESS, SPR_NOACCESS,
3791 &spr_read_generic, &spr_write_generic,
3792 0x00000000);
3793 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3794 SPR_NOACCESS, SPR_NOACCESS,
3795 &spr_read_generic, &spr_write_generic,
3796 0x00000000);
3797 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3798 SPR_NOACCESS, SPR_NOACCESS,
3799 &spr_read_generic, &spr_write_generic,
3800 0x00000000);
3801 /* XXX : not implemented */
3802 spr_register(env, SPR_440_CCR1, "CCR1",
3803 SPR_NOACCESS, SPR_NOACCESS,
3804 &spr_read_generic, &spr_write_generic,
3805 0x00000000);
3806 /* Memory management */
3807 #if !defined(CONFIG_USER_ONLY)
3808 env->nb_tlb = 64;
3809 env->nb_ways = 1;
3810 env->id_tlbs = 0;
3811 env->tlb_type = TLB_EMB;
3812 #endif
3813 init_excp_BookE(env);
3814 env->dcache_line_size = 32;
3815 env->icache_line_size = 32;
3816 ppc40x_irq_init(env);
3817
3818 SET_FIT_PERIOD(12, 16, 20, 24);
3819 SET_WDT_PERIOD(20, 24, 28, 32);
3820 }
3821
3822 /* PowerPC 460 (guessed) */
3823 #define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
3824 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3825 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | \
3826 PPC_CACHE | PPC_CACHE_ICBI | \
3827 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3828 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3829 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3830 PPC_440_SPEC)
3831 #define POWERPC_INSNS2_460 (PPC_NONE)
3832 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3833 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3834 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3835 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3836 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3837 #define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3838 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3839 #define check_pow_460 check_pow_nocheck
3840
3841 __attribute__ (( unused ))
3842 static void init_proc_460 (CPUPPCState *env)
3843 {
3844 /* Time base */
3845 gen_tbl(env);
3846 gen_spr_BookE(env, 0x000000000000FFFFULL);
3847 gen_spr_440(env);
3848 gen_spr_usprgh(env);
3849 /* Processor identification */
3850 spr_register(env, SPR_BOOKE_PIR, "PIR",
3851 SPR_NOACCESS, SPR_NOACCESS,
3852 &spr_read_generic, &spr_write_pir,
3853 0x00000000);
3854 /* XXX : not implemented */
3855 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3856 SPR_NOACCESS, SPR_NOACCESS,
3857 &spr_read_generic, &spr_write_generic,
3858 0x00000000);
3859 /* XXX : not implemented */
3860 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3861 SPR_NOACCESS, SPR_NOACCESS,
3862 &spr_read_generic, &spr_write_generic,
3863 0x00000000);
3864 /* XXX : not implemented */
3865 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3866 SPR_NOACCESS, SPR_NOACCESS,
3867 &spr_read_generic, &spr_write_generic,
3868 0x00000000);
3869 /* XXX : not implemented */
3870 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3871 SPR_NOACCESS, SPR_NOACCESS,
3872 &spr_read_generic, &spr_write_generic,
3873 0x00000000);
3874 /* XXX : not implemented */
3875 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3876 SPR_NOACCESS, SPR_NOACCESS,
3877 &spr_read_generic, &spr_write_generic,
3878 0x00000000);
3879 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3880 SPR_NOACCESS, SPR_NOACCESS,
3881 &spr_read_generic, &spr_write_generic,
3882 0x00000000);
3883 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3884 SPR_NOACCESS, SPR_NOACCESS,
3885 &spr_read_generic, &spr_write_generic,
3886 0x00000000);
3887 /* XXX : not implemented */
3888 spr_register(env, SPR_440_CCR1, "CCR1",
3889 SPR_NOACCESS, SPR_NOACCESS,
3890 &spr_read_generic, &spr_write_generic,
3891 0x00000000);
3892 /* XXX : not implemented */
3893 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3894 &spr_read_generic, &spr_write_generic,
3895 &spr_read_generic, &spr_write_generic,
3896 0x00000000);
3897 /* Memory management */
3898 #if !defined(CONFIG_USER_ONLY)
3899 env->nb_tlb = 64;
3900 env->nb_ways = 1;
3901 env->id_tlbs = 0;
3902 env->tlb_type = TLB_EMB;
3903 #endif
3904 init_excp_BookE(env);
3905 env->dcache_line_size = 32;
3906 env->icache_line_size = 32;
3907 /* XXX: TODO: allocate internal IRQ controller */
3908
3909 SET_FIT_PERIOD(12, 16, 20, 24);
3910 SET_WDT_PERIOD(20, 24, 28, 32);
3911 }
3912
3913 /* PowerPC 460F (guessed) */
3914 #define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3915 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3916 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3917 PPC_FLOAT_STFIWX | PPC_MFTB | \
3918 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3919 PPC_WRTEE | PPC_MFAPIDI | \
3920 PPC_CACHE | PPC_CACHE_ICBI | \
3921 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3922 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3923 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3924 PPC_440_SPEC)
3925 #define POWERPC_INSNS2_460F (PPC_NONE)
3926 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3927 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3928 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3929 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3930 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3931 #define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3932 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3933 #define check_pow_460F check_pow_nocheck
3934
3935 __attribute__ (( unused ))
3936 static void init_proc_460F (CPUPPCState *env)
3937 {
3938 /* Time base */
3939 gen_tbl(env);
3940 gen_spr_BookE(env, 0x000000000000FFFFULL);
3941 gen_spr_440(env);
3942 gen_spr_usprgh(env);
3943 /* Processor identification */
3944 spr_register(env, SPR_BOOKE_PIR, "PIR",
3945 SPR_NOACCESS, SPR_NOACCESS,
3946 &spr_read_generic, &spr_write_pir,
3947 0x00000000);
3948 /* XXX : not implemented */
3949 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3950 SPR_NOACCESS, SPR_NOACCESS,
3951 &spr_read_generic, &spr_write_generic,
3952 0x00000000);
3953 /* XXX : not implemented */
3954 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3955 SPR_NOACCESS, SPR_NOACCESS,
3956 &spr_read_generic, &spr_write_generic,
3957 0x00000000);
3958 /* XXX : not implemented */
3959 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3960 SPR_NOACCESS, SPR_NOACCESS,
3961 &spr_read_generic, &spr_write_generic,
3962 0x00000000);
3963 /* XXX : not implemented */
3964 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3965 SPR_NOACCESS, SPR_NOACCESS,
3966 &spr_read_generic, &spr_write_generic,
3967 0x00000000);
3968 /* XXX : not implemented */
3969 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3970 SPR_NOACCESS, SPR_NOACCESS,
3971 &spr_read_generic, &spr_write_generic,
3972 0x00000000);
3973 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3974 SPR_NOACCESS, SPR_NOACCESS,
3975 &spr_read_generic, &spr_write_generic,
3976 0x00000000);
3977 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3978 SPR_NOACCESS, SPR_NOACCESS,
3979 &spr_read_generic, &spr_write_generic,
3980 0x00000000);
3981 /* XXX : not implemented */
3982 spr_register(env, SPR_440_CCR1, "CCR1",
3983 SPR_NOACCESS, SPR_NOACCESS,
3984 &spr_read_generic, &spr_write_generic,
3985 0x00000000);
3986 /* XXX : not implemented */
3987 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3988 &spr_read_generic, &spr_write_generic,
3989 &spr_read_generic, &spr_write_generic,
3990 0x00000000);
3991 /* Memory management */
3992 #if !defined(CONFIG_USER_ONLY)
3993 env->nb_tlb = 64;
3994 env->nb_ways = 1;
3995 env->id_tlbs = 0;
3996 env->tlb_type = TLB_EMB;
3997 #endif
3998 init_excp_BookE(env);
3999 env->dcache_line_size = 32;
4000 env->icache_line_size = 32;
4001 /* XXX: TODO: allocate internal IRQ controller */
4002
4003 SET_FIT_PERIOD(12, 16, 20, 24);
4004 SET_WDT_PERIOD(20, 24, 28, 32);
4005 }
4006
4007 /* Freescale 5xx cores (aka RCPU) */
4008 #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
4009 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4010 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
4011 PPC_MFTB)
4012 #define POWERPC_INSNS2_MPC5xx (PPC_NONE)
4013 #define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
4014 #define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
4015 #define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
4016 #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
4017 #define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
4018 #define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4019 POWERPC_FLAG_BUS_CLK)
4020 #define check_pow_MPC5xx check_pow_none
4021
4022 __attribute__ (( unused ))
4023 static void init_proc_MPC5xx (CPUPPCState *env)
4024 {
4025 /* Time base */
4026 gen_tbl(env);
4027 gen_spr_5xx_8xx(env);
4028 gen_spr_5xx(env);
4029 init_excp_MPC5xx(env);
4030 env->dcache_line_size = 32;
4031 env->icache_line_size = 32;
4032 /* XXX: TODO: allocate internal IRQ controller */
4033 }
4034
4035 /* Freescale 8xx cores (aka PowerQUICC) */
4036 #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
4037 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4038 PPC_CACHE_ICBI | PPC_MFTB)
4039 #define POWERPC_INSNS2_MPC8xx (PPC_NONE)
4040 #define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
4041 #define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
4042 #define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
4043 #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
4044 #define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4045 #define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4046 POWERPC_FLAG_BUS_CLK)
4047 #define check_pow_MPC8xx check_pow_none
4048
4049 __attribute__ (( unused ))
4050 static void init_proc_MPC8xx (CPUPPCState *env)
4051 {
4052 /* Time base */
4053 gen_tbl(env);
4054 gen_spr_5xx_8xx(env);
4055 gen_spr_8xx(env);
4056 init_excp_MPC8xx(env);
4057 env->dcache_line_size = 32;
4058 env->icache_line_size = 32;
4059 /* XXX: TODO: allocate internal IRQ controller */
4060 }
4061
4062 /* Freescale 82xx cores (aka PowerQUICC-II) */
4063 /* PowerPC G2 */
4064 #define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4065 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4066 PPC_FLOAT_STFIWX | \
4067 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4068 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4069 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4070 PPC_SEGMENT | PPC_EXTERN)
4071 #define POWERPC_INSNS2_G2 (PPC_NONE)
4072 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
4073 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
4074 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
4075 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
4076 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
4077 #define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4078 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4079 #define check_pow_G2 check_pow_hid0
4080
4081 static void init_proc_G2 (CPUPPCState *env)
4082 {
4083 gen_spr_ne_601(env);
4084 gen_spr_G2_755(env);
4085 gen_spr_G2(env);
4086 /* Time base */
4087 gen_tbl(env);
4088 /* External access control */
4089 /* XXX : not implemented */
4090 spr_register(env, SPR_EAR, "EAR",
4091 SPR_NOACCESS, SPR_NOACCESS,
4092 &spr_read_generic, &spr_write_generic,
4093 0x00000000);
4094 /* Hardware implementation register */
4095 /* XXX : not implemented */
4096 spr_register(env, SPR_HID0, "HID0",
4097 SPR_NOACCESS, SPR_NOACCESS,
4098 &spr_read_generic, &spr_write_generic,
4099 0x00000000);
4100 /* XXX : not implemented */
4101 spr_register(env, SPR_HID1, "HID1",
4102 SPR_NOACCESS, SPR_NOACCESS,
4103 &spr_read_generic, &spr_write_generic,
4104 0x00000000);
4105 /* XXX : not implemented */
4106 spr_register(env, SPR_HID2, "HID2",
4107 SPR_NOACCESS, SPR_NOACCESS,
4108 &spr_read_generic, &spr_write_generic,
4109 0x00000000);
4110 /* Memory management */
4111 gen_low_BATs(env);
4112 gen_high_BATs(env);
4113 gen_6xx_7xx_soft_tlb(env, 64, 2);
4114 init_excp_G2(env);
4115 env->dcache_line_size = 32;
4116 env->icache_line_size = 32;
4117 /* Allocate hardware IRQ controller */
4118 ppc6xx_irq_init(env);
4119 }
4120
4121 /* PowerPC G2LE */
4122 #define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4123 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4124 PPC_FLOAT_STFIWX | \
4125 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4126 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4127 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4128 PPC_SEGMENT | PPC_EXTERN)
4129 #define POWERPC_INSNS2_G2LE (PPC_NONE)
4130 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
4131 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
4132 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
4133 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
4134 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
4135 #define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4136 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4137 #define check_pow_G2LE check_pow_hid0
4138
4139 static void init_proc_G2LE (CPUPPCState *env)
4140 {
4141 gen_spr_ne_601(env);
4142 gen_spr_G2_755(env);
4143 gen_spr_G2(env);
4144 /* Time base */
4145 gen_tbl(env);
4146 /* External access control */
4147 /* XXX : not implemented */
4148 spr_register(env, SPR_EAR, "EAR",
4149 SPR_NOACCESS, SPR_NOACCESS,
4150 &spr_read_generic, &spr_write_generic,
4151 0x00000000);
4152 /* Hardware implementation register */
4153 /* XXX : not implemented */
4154 spr_register(env, SPR_HID0, "HID0",
4155 SPR_NOACCESS, SPR_NOACCESS,
4156 &spr_read_generic, &spr_write_generic,
4157 0x00000000);
4158 /* XXX : not implemented */
4159 spr_register(env, SPR_HID1, "HID1",
4160 SPR_NOACCESS, SPR_NOACCESS,
4161 &spr_read_generic, &spr_write_generic,
4162 0x00000000);
4163 /* XXX : not implemented */
4164 spr_register(env, SPR_HID2, "HID2",
4165 SPR_NOACCESS, SPR_NOACCESS,
4166 &spr_read_generic, &spr_write_generic,
4167 0x00000000);
4168 /* Memory management */
4169 gen_low_BATs(env);
4170 gen_high_BATs(env);
4171 gen_6xx_7xx_soft_tlb(env, 64, 2);
4172 init_excp_G2(env);
4173 env->dcache_line_size = 32;
4174 env->icache_line_size = 32;
4175 /* Allocate hardware IRQ controller */
4176 ppc6xx_irq_init(env);
4177 }
4178
4179 /* e200 core */
4180 /* XXX: unimplemented instructions:
4181 * dcblc
4182 * dcbtlst
4183 * dcbtstls
4184 * icblc
4185 * icbtls
4186 * tlbivax
4187 * all SPE multiply-accumulate instructions
4188 */
4189 #define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
4190 PPC_SPE | PPC_SPE_SINGLE | \
4191 PPC_WRTEE | PPC_RFDI | \
4192 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4193 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4194 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4195 PPC_BOOKE)
4196 #define POWERPC_INSNS2_e200 (PPC_NONE)
4197 #define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
4198 #define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE206)
4199 #define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
4200 #define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
4201 #define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
4202 #define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4203 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4204 POWERPC_FLAG_BUS_CLK)
4205 #define check_pow_e200 check_pow_hid0
4206
4207 __attribute__ (( unused ))
4208 static void init_proc_e200 (CPUPPCState *env)
4209 {
4210 /* Time base */
4211 gen_tbl(env);
4212 gen_spr_BookE(env, 0x000000070000FFFFULL);
4213 /* XXX : not implemented */
4214 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4215 &spr_read_spefscr, &spr_write_spefscr,
4216 &spr_read_spefscr, &spr_write_spefscr,
4217 0x00000000);
4218 /* Memory management */
4219 gen_spr_BookE206(env, 0x0000005D, NULL);
4220 /* XXX : not implemented */
4221 spr_register(env, SPR_HID0, "HID0",
4222 SPR_NOACCESS, SPR_NOACCESS,
4223 &spr_read_generic, &spr_write_generic,
4224 0x00000000);
4225 /* XXX : not implemented */
4226 spr_register(env, SPR_HID1, "HID1",
4227 SPR_NOACCESS, SPR_NOACCESS,
4228 &spr_read_generic, &spr_write_generic,
4229 0x00000000);
4230 /* XXX : not implemented */
4231 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4232 SPR_NOACCESS, SPR_NOACCESS,
4233 &spr_read_generic, &spr_write_generic,
4234 0x00000000);
4235 /* XXX : not implemented */
4236 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4237 SPR_NOACCESS, SPR_NOACCESS,
4238 &spr_read_generic, &spr_write_generic,
4239 0x00000000);
4240 /* XXX : not implemented */
4241 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4242 SPR_NOACCESS, SPR_NOACCESS,
4243 &spr_read_generic, &spr_write_generic,
4244 0x00000000);
4245 /* XXX : not implemented */
4246 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4247 SPR_NOACCESS, SPR_NOACCESS,
4248 &spr_read_generic, &spr_write_generic,
4249 0x00000000);
4250 /* XXX : not implemented */
4251 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4252 SPR_NOACCESS, SPR_NOACCESS,
4253 &spr_read_generic, &spr_write_generic,
4254 0x00000000);
4255 /* XXX : not implemented */
4256 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4257 SPR_NOACCESS, SPR_NOACCESS,
4258 &spr_read_generic, &spr_write_generic,
4259 0x00000000);
4260 /* XXX : not implemented */
4261 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4262 SPR_NOACCESS, SPR_NOACCESS,
4263 &spr_read_generic, &spr_write_generic,
4264 0x00000000);
4265 /* XXX : not implemented */
4266 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4267 SPR_NOACCESS, SPR_NOACCESS,
4268 &spr_read_generic, &spr_write_generic,
4269 0x00000000);
4270 /* XXX : not implemented */
4271 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4272 SPR_NOACCESS, SPR_NOACCESS,
4273 &spr_read_generic, &spr_write_generic,
4274 0x00000000);
4275 /* XXX : not implemented */
4276 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4277 SPR_NOACCESS, SPR_NOACCESS,
4278 &spr_read_generic, &spr_write_generic,
4279 0x00000000);
4280 /* XXX : not implemented */
4281 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4282 SPR_NOACCESS, SPR_NOACCESS,
4283 &spr_read_generic, &spr_write_generic,
4284 0x00000000);
4285 /* XXX : not implemented */
4286 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4287 SPR_NOACCESS, SPR_NOACCESS,
4288 &spr_read_generic, &spr_write_generic,
4289 0x00000000);
4290 /* XXX : not implemented */
4291 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4292 SPR_NOACCESS, SPR_NOACCESS,
4293 &spr_read_generic, &spr_write_generic,
4294 0x00000000); /* TOFIX */
4295 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4296 SPR_NOACCESS, SPR_NOACCESS,
4297 &spr_read_generic, &spr_write_generic,
4298 0x00000000);
4299 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4300 SPR_NOACCESS, SPR_NOACCESS,
4301 &spr_read_generic, &spr_write_generic,
4302 0x00000000);
4303 #if !defined(CONFIG_USER_ONLY)
4304 env->nb_tlb = 64;
4305 env->nb_ways = 1;
4306 env->id_tlbs = 0;
4307 env->tlb_type = TLB_EMB;
4308 #endif
4309 init_excp_e200(env);
4310 env->dcache_line_size = 32;
4311 env->icache_line_size = 32;
4312 /* XXX: TODO: allocate internal IRQ controller */
4313 }
4314
4315 /* e300 core */
4316 #define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4317 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4318 PPC_FLOAT_STFIWX | \
4319 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4320 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4321 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4322 PPC_SEGMENT | PPC_EXTERN)
4323 #define POWERPC_INSNS2_e300 (PPC_NONE)
4324 #define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4325 #define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4326 #define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4327 #define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4328 #define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4329 #define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4330 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4331 #define check_pow_e300 check_pow_hid0
4332
4333 __attribute__ (( unused ))
4334 static void init_proc_e300 (CPUPPCState *env)
4335 {
4336 gen_spr_ne_601(env);
4337 gen_spr_603(env);
4338 /* Time base */
4339 gen_tbl(env);
4340 /* hardware implementation registers */
4341 /* XXX : not implemented */
4342 spr_register(env, SPR_HID0, "HID0",
4343 SPR_NOACCESS, SPR_NOACCESS,
4344 &spr_read_generic, &spr_write_generic,
4345 0x00000000);
4346 /* XXX : not implemented */
4347 spr_register(env, SPR_HID1, "HID1",
4348 SPR_NOACCESS, SPR_NOACCESS,
4349 &spr_read_generic, &spr_write_generic,
4350 0x00000000);
4351 /* XXX : not implemented */
4352 spr_register(env, SPR_HID2, "HID2",
4353 SPR_NOACCESS, SPR_NOACCESS,
4354 &spr_read_generic, &spr_write_generic,
4355 0x00000000);
4356 /* Memory management */
4357 gen_low_BATs(env);
4358 gen_high_BATs(env);
4359 gen_6xx_7xx_soft_tlb(env, 64, 2);
4360 init_excp_603(env);
4361 env->dcache_line_size = 32;
4362 env->icache_line_size = 32;
4363 /* Allocate hardware IRQ controller */
4364 ppc6xx_irq_init(env);
4365 }
4366
4367 /* e500v1 core */
4368 #define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
4369 PPC_SPE | PPC_SPE_SINGLE | \
4370 PPC_WRTEE | PPC_RFDI | \
4371 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4372 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4373 PPC_MEM_TLBSYNC | PPC_TLBIVAX)
4374 #define POWERPC_INSNS2_e500v1 (PPC2_BOOKE206)
4375 #define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
4376 #define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206)
4377 #define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4378 #define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4379 #define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4380 #define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4381 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4382 POWERPC_FLAG_BUS_CLK)
4383 #define check_pow_e500v1 check_pow_hid0
4384 #define init_proc_e500v1 init_proc_e500v1
4385
4386 /* e500v2 core */
4387 #define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
4388 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
4389 PPC_WRTEE | PPC_RFDI | \
4390 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4391 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4392 PPC_MEM_TLBSYNC | PPC_TLBIVAX)
4393 #define POWERPC_INSNS2_e500v2 (PPC2_BOOKE206)
4394 #define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
4395 #define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206)
4396 #define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4397 #define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4398 #define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4399 #define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4400 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4401 POWERPC_FLAG_BUS_CLK)
4402 #define check_pow_e500v2 check_pow_hid0
4403 #define init_proc_e500v2 init_proc_e500v2
4404
4405 /* e500mc core */
4406 #define POWERPC_INSNS_e500mc (PPC_INSNS_BASE | PPC_ISEL | \
4407 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | \
4408 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4409 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4410 PPC_FLOAT | PPC_FLOAT_FRES | \
4411 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
4412 PPC_FLOAT_STFIWX | PPC_WAIT | \
4413 PPC_MEM_TLBSYNC | PPC_TLBIVAX)
4414 #define POWERPC_INSNS2_e500mc (PPC2_BOOKE206)
4415 #define POWERPC_MSRM_e500mc (0x000000001402FB36ULL)
4416 #define POWERPC_MMU_e500mc (POWERPC_MMU_BOOKE206)
4417 #define POWERPC_EXCP_e500mc (POWERPC_EXCP_BOOKE)
4418 #define POWERPC_INPUT_e500mc (PPC_FLAGS_INPUT_BookE)
4419 /* Fixme: figure out the correct flag for e500mc */
4420 #define POWERPC_BFDM_e500mc (bfd_mach_ppc_e500)
4421 #define POWERPC_FLAG_e500mc (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
4422 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4423 #define check_pow_e500mc check_pow_none
4424 #define init_proc_e500mc init_proc_e500mc
4425
4426 enum fsl_e500_version {
4427 fsl_e500v1,
4428 fsl_e500v2,
4429 fsl_e500mc,
4430 };
4431
4432 static void init_proc_e500 (CPUPPCState *env, int version)
4433 {
4434 uint32_t tlbncfg[2];
4435 #if !defined(CONFIG_USER_ONLY)
4436 int i;
4437 #endif
4438
4439 /* Time base */
4440 gen_tbl(env);
4441 /*
4442 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4443 * complain when accessing them.
4444 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4445 */
4446 gen_spr_BookE(env, 0x0000000F0000FFFFULL);
4447 /* Processor identification */
4448 spr_register(env, SPR_BOOKE_PIR, "PIR",
4449 SPR_NOACCESS, SPR_NOACCESS,
4450 &spr_read_generic, &spr_write_pir,
4451 0x00000000);
4452 /* XXX : not implemented */
4453 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4454 &spr_read_spefscr, &spr_write_spefscr,
4455 &spr_read_spefscr, &spr_write_spefscr,
4456 0x00000000);
4457 /* Memory management */
4458 #if !defined(CONFIG_USER_ONLY)
4459 env->nb_pids = 3;
4460 env->nb_ways = 2;
4461 env->id_tlbs = 0;
4462 switch (version) {
4463 case fsl_e500v1:
4464 /* e500v1 */
4465 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4466 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4467 env->dcache_line_size = 32;
4468 env->icache_line_size = 32;
4469 break;
4470 case fsl_e500v2:
4471 /* e500v2 */
4472 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4473 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4474 env->dcache_line_size = 32;
4475 env->icache_line_size = 32;
4476 break;
4477 case fsl_e500mc:
4478 /* e500mc */
4479 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4480 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4481 env->dcache_line_size = 64;
4482 env->icache_line_size = 64;
4483 break;
4484 default:
4485 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4486 }
4487 #endif
4488 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4489 /* XXX : not implemented */
4490 spr_register(env, SPR_HID0, "HID0",
4491 SPR_NOACCESS, SPR_NOACCESS,
4492 &spr_read_generic, &spr_write_generic,
4493 0x00000000);
4494 /* XXX : not implemented */
4495 spr_register(env, SPR_HID1, "HID1",
4496 SPR_NOACCESS, SPR_NOACCESS,
4497 &spr_read_generic, &spr_write_generic,
4498 0x00000000);
4499 /* XXX : not implemented */
4500 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4501 SPR_NOACCESS, SPR_NOACCESS,
4502 &spr_read_generic, &spr_write_generic,
4503 0x00000000);
4504 /* XXX : not implemented */
4505 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4506 SPR_NOACCESS, SPR_NOACCESS,
4507 &spr_read_generic, &spr_write_generic,
4508 0x00000000);
4509 /* XXX : not implemented */
4510 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4511 SPR_NOACCESS, SPR_NOACCESS,
4512 &spr_read_generic, &spr_write_generic,
4513 0x00000000);
4514 /* XXX : not implemented */
4515 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4516 SPR_NOACCESS, SPR_NOACCESS,
4517 &spr_read_generic, &spr_write_generic,
4518 0x00000000);
4519 /* XXX : not implemented */
4520 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4521 SPR_NOACCESS, SPR_NOACCESS,
4522 &spr_read_generic, &spr_write_generic,
4523 0x00000000);
4524 /* XXX : not implemented */
4525 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4526 SPR_NOACCESS, SPR_NOACCESS,
4527 &spr_read_generic, &spr_write_generic,
4528 0x00000000);
4529 /* XXX : not implemented */
4530 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4531 SPR_NOACCESS, SPR_NOACCESS,
4532 &spr_read_generic, &spr_write_generic,
4533 0x00000000);
4534 /* XXX : not implemented */
4535 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4536 SPR_NOACCESS, SPR_NOACCESS,
4537 &spr_read_generic, &spr_write_e500_l1csr0,
4538 0x00000000);
4539 /* XXX : not implemented */
4540 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4541 SPR_NOACCESS, SPR_NOACCESS,
4542 &spr_read_generic, &spr_write_generic,
4543 0x00000000);
4544 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4545 SPR_NOACCESS, SPR_NOACCESS,
4546 &spr_read_generic, &spr_write_generic,
4547 0x00000000);
4548 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4549 SPR_NOACCESS, SPR_NOACCESS,
4550 &spr_read_generic, &spr_write_generic,
4551 0x00000000);
4552 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4553 SPR_NOACCESS, SPR_NOACCESS,
4554 &spr_read_generic, &spr_write_booke206_mmucsr0,
4555 0x00000000);
4556
4557 #if !defined(CONFIG_USER_ONLY)
4558 env->nb_tlb = 0;
4559 env->tlb_type = TLB_MAS;
4560 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4561 env->nb_tlb += booke206_tlb_size(env, i);
4562 }
4563 #endif
4564
4565 init_excp_e200(env);
4566 /* Allocate hardware IRQ controller */
4567 ppce500_irq_init(env);
4568 }
4569
4570 static void init_proc_e500v1(CPUPPCState *env)
4571 {
4572 init_proc_e500(env, fsl_e500v1);
4573 }
4574
4575 static void init_proc_e500v2(CPUPPCState *env)
4576 {
4577 init_proc_e500(env, fsl_e500v2);
4578 }
4579
4580 static void init_proc_e500mc(CPUPPCState *env)
4581 {
4582 init_proc_e500(env, fsl_e500mc);
4583 }
4584
4585 /* Non-embedded PowerPC */
4586
4587 /* POWER : same as 601, without mfmsr, mfsr */
4588 #if defined(TODO)
4589 #define POWERPC_INSNS_POWER (XXX_TODO)
4590 /* POWER RSC (from RAD6000) */
4591 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4592 #endif /* TODO */
4593
4594 /* PowerPC 601 */
4595 #define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4596 PPC_FLOAT | \
4597 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4598 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4599 PPC_SEGMENT | PPC_EXTERN)
4600 #define POWERPC_INSNS2_601 (PPC_NONE)
4601 #define POWERPC_MSRM_601 (0x000000000000FD70ULL)
4602 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4603 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
4604 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4605 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
4606 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4607 #define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4608 #define check_pow_601 check_pow_none
4609
4610 static void init_proc_601 (CPUPPCState *env)
4611 {
4612 gen_spr_ne_601(env);
4613 gen_spr_601(env);
4614 /* Hardware implementation registers */
4615 /* XXX : not implemented */
4616 spr_register(env, SPR_HID0, "HID0",
4617 SPR_NOACCESS, SPR_NOACCESS,
4618 &spr_read_generic, &spr_write_hid0_601,
4619 0x80010080);
4620 /* XXX : not implemented */
4621 spr_register(env, SPR_HID1, "HID1",
4622 SPR_NOACCESS, SPR_NOACCESS,
4623 &spr_read_generic, &spr_write_generic,
4624 0x00000000);
4625 /* XXX : not implemented */
4626 spr_register(env, SPR_601_HID2, "HID2",
4627 SPR_NOACCESS, SPR_NOACCESS,
4628 &spr_read_generic, &spr_write_generic,
4629 0x00000000);
4630 /* XXX : not implemented */
4631 spr_register(env, SPR_601_HID5, "HID5",
4632 SPR_NOACCESS, SPR_NOACCESS,
4633 &spr_read_generic, &spr_write_generic,
4634 0x00000000);
4635 /* Memory management */
4636 init_excp_601(env);
4637 /* XXX: beware that dcache line size is 64
4638 * but dcbz uses 32 bytes "sectors"
4639 * XXX: this breaks clcs instruction !
4640 */
4641 env->dcache_line_size = 32;
4642 env->icache_line_size = 64;
4643 /* Allocate hardware IRQ controller */
4644 ppc6xx_irq_init(env);
4645 }
4646
4647 /* PowerPC 601v */
4648 #define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4649 PPC_FLOAT | \
4650 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4651 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4652 PPC_SEGMENT | PPC_EXTERN)
4653 #define POWERPC_INSNS2_601v (PPC_NONE)
4654 #define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4655 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4656 #define POWERPC_MMU_601v (POWERPC_MMU_601)
4657 #define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4658 #define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4659 #define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4660 #define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4661 #define check_pow_601v check_pow_none
4662
4663 static void init_proc_601v (CPUPPCState *env)
4664 {
4665 init_proc_601(env);
4666 /* XXX : not implemented */
4667 spr_register(env, SPR_601_HID15, "HID15",
4668 SPR_NOACCESS, SPR_NOACCESS,
4669 &spr_read_generic, &spr_write_generic,
4670 0x00000000);
4671 }
4672
4673 /* PowerPC 602 */
4674 #define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4675 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4676 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4677 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4678 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4679 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4680 PPC_SEGMENT | PPC_602_SPEC)
4681 #define POWERPC_INSNS2_602 (PPC_NONE)
4682 #define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4683 /* XXX: 602 MMU is quite specific. Should add a special case */
4684 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4685 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4686 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
4687 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
4688 #define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4689 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4690 #define check_pow_602 check_pow_hid0
4691
4692 static void init_proc_602 (CPUPPCState *env)
4693 {
4694 gen_spr_ne_601(env);
4695 gen_spr_602(env);
4696 /* Time base */
4697 gen_tbl(env);
4698 /* hardware implementation registers */
4699 /* XXX : not implemented */
4700 spr_register(env, SPR_HID0, "HID0",
4701 SPR_NOACCESS, SPR_NOACCESS,
4702 &spr_read_generic, &spr_write_generic,
4703 0x00000000);
4704 /* XXX : not implemented */
4705 spr_register(env, SPR_HID1, "HID1",
4706 SPR_NOACCESS, SPR_NOACCESS,
4707 &spr_read_generic, &spr_write_generic,
4708 0x00000000);
4709 /* Memory management */
4710 gen_low_BATs(env);
4711 gen_6xx_7xx_soft_tlb(env, 64, 2);
4712 init_excp_602(env);
4713 env->dcache_line_size = 32;
4714 env->icache_line_size = 32;
4715 /* Allocate hardware IRQ controller */
4716 ppc6xx_irq_init(env);
4717 }
4718
4719 /* PowerPC 603 */
4720 #define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4721 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4722 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4723 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4724 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4725 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4726 PPC_SEGMENT | PPC_EXTERN)
4727 #define POWERPC_INSNS2_603 (PPC_NONE)
4728 #define POWERPC_MSRM_603 (0x000000000007FF73ULL)
4729 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4730 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4731 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
4732 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
4733 #define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4734 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4735 #define check_pow_603 check_pow_hid0
4736
4737 static void init_proc_603 (CPUPPCState *env)
4738 {
4739 gen_spr_ne_601(env);
4740 gen_spr_603(env);
4741 /* Time base */
4742 gen_tbl(env);
4743 /* hardware implementation registers */
4744 /* XXX : not implemented */
4745 spr_register(env, SPR_HID0, "HID0",
4746 SPR_NOACCESS, SPR_NOACCESS,
4747 &spr_read_generic, &spr_write_generic,
4748 0x00000000);
4749 /* XXX : not implemented */
4750 spr_register(env, SPR_HID1, "HID1",
4751 SPR_NOACCESS, SPR_NOACCESS,
4752 &spr_read_generic, &spr_write_generic,
4753 0x00000000);
4754 /* Memory management */
4755 gen_low_BATs(env);
4756 gen_6xx_7xx_soft_tlb(env, 64, 2);
4757 init_excp_603(env);
4758 env->dcache_line_size = 32;
4759 env->icache_line_size = 32;
4760 /* Allocate hardware IRQ controller */
4761 ppc6xx_irq_init(env);
4762 }
4763
4764 /* PowerPC 603e */
4765 #define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4766 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4767 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4768 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4769 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4770 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4771 PPC_SEGMENT | PPC_EXTERN)
4772 #define POWERPC_INSNS2_603E (PPC_NONE)
4773 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4774 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4775 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4776 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
4777 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
4778 #define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4779 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4780 #define check_pow_603E check_pow_hid0
4781
4782 static void init_proc_603E (CPUPPCState *env)
4783 {
4784 gen_spr_ne_601(env);
4785 gen_spr_603(env);
4786 /* Time base */
4787 gen_tbl(env);
4788 /* hardware implementation registers */
4789 /* XXX : not implemented */
4790 spr_register(env, SPR_HID0, "HID0",
4791 SPR_NOACCESS, SPR_NOACCESS,
4792 &spr_read_generic, &spr_write_generic,
4793 0x00000000);
4794 /* XXX : not implemented */
4795 spr_register(env, SPR_HID1, "HID1",
4796 SPR_NOACCESS, SPR_NOACCESS,
4797 &spr_read_generic, &spr_write_generic,
4798 0x00000000);
4799 /* XXX : not implemented */
4800 spr_register(env, SPR_IABR, "IABR",
4801 SPR_NOACCESS, SPR_NOACCESS,
4802 &spr_read_generic, &spr_write_generic,
4803 0x00000000);
4804 /* Memory management */
4805 gen_low_BATs(env);
4806 gen_6xx_7xx_soft_tlb(env, 64, 2);
4807 init_excp_603(env);
4808 env->dcache_line_size = 32;
4809 env->icache_line_size = 32;
4810 /* Allocate hardware IRQ controller */
4811 ppc6xx_irq_init(env);
4812 }
4813
4814 /* PowerPC 604 */
4815 #define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4816 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4817 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4818 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4819 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4820 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4821 PPC_SEGMENT | PPC_EXTERN)
4822 #define POWERPC_INSNS2_604 (PPC_NONE)
4823 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4824 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
4825 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4826 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
4827 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
4828 #define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4829 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4830 #define check_pow_604 check_pow_nocheck
4831
4832 static void init_proc_604 (CPUPPCState *env)
4833 {
4834 gen_spr_ne_601(env);
4835 gen_spr_604(env);
4836 /* Time base */
4837 gen_tbl(env);
4838 /* Hardware implementation registers */
4839 /* XXX : not implemented */
4840 spr_register(env, SPR_HID0, "HID0",
4841 SPR_NOACCESS, SPR_NOACCESS,
4842 &spr_read_generic, &spr_write_generic,
4843 0x00000000);
4844 /* Memory management */
4845 gen_low_BATs(env);
4846 init_excp_604(env);
4847 env->dcache_line_size = 32;
4848 env->icache_line_size = 32;
4849 /* Allocate hardware IRQ controller */
4850 ppc6xx_irq_init(env);
4851 }
4852
4853 /* PowerPC 604E */
4854 #define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4855 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4856 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4857 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4858 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4859 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4860 PPC_SEGMENT | PPC_EXTERN)
4861 #define POWERPC_INSNS2_604E (PPC_NONE)
4862 #define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4863 #define POWERPC_MMU_604E (POWERPC_MMU_32B)
4864 #define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4865 #define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4866 #define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4867 #define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4868 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4869 #define check_pow_604E check_pow_nocheck
4870
4871 static void init_proc_604E (CPUPPCState *env)
4872 {
4873 gen_spr_ne_601(env);
4874 gen_spr_604(env);
4875 /* XXX : not implemented */
4876 spr_register(env, SPR_MMCR1, "MMCR1",
4877 SPR_NOACCESS, SPR_NOACCESS,
4878 &spr_read_generic, &spr_write_generic,
4879 0x00000000);
4880 /* XXX : not implemented */
4881 spr_register(env, SPR_PMC3, "PMC3",
4882 SPR_NOACCESS, SPR_NOACCESS,
4883 &spr_read_generic, &spr_write_generic,
4884 0x00000000);
4885 /* XXX : not implemented */
4886 spr_register(env, SPR_PMC4, "PMC4",
4887 SPR_NOACCESS, SPR_NOACCESS,
4888 &spr_read_generic, &spr_write_generic,
4889 0x00000000);
4890 /* Time base */
4891 gen_tbl(env);
4892 /* Hardware implementation registers */
4893 /* XXX : not implemented */
4894 spr_register(env, SPR_HID0, "HID0",
4895 SPR_NOACCESS, SPR_NOACCESS,
4896 &spr_read_generic, &spr_write_generic,
4897 0x00000000);
4898 /* XXX : not implemented */
4899 spr_register(env, SPR_HID1, "HID1",
4900 SPR_NOACCESS, SPR_NOACCESS,
4901 &spr_read_generic, &spr_write_generic,
4902 0x00000000);
4903 /* Memory management */
4904 gen_low_BATs(env);
4905 init_excp_604(env);
4906 env->dcache_line_size = 32;
4907 env->icache_line_size = 32;
4908 /* Allocate hardware IRQ controller */
4909 ppc6xx_irq_init(env);
4910 }
4911
4912 /* PowerPC 740 */
4913 #define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4914 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4915 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4916 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4917 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4918 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4919 PPC_SEGMENT | PPC_EXTERN)
4920 #define POWERPC_INSNS2_740 (PPC_NONE)
4921 #define POWERPC_MSRM_740 (0x000000000005FF77ULL)
4922 #define POWERPC_MMU_740 (POWERPC_MMU_32B)
4923 #define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
4924 #define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
4925 #define POWERPC_BFDM_740 (bfd_mach_ppc_750)
4926 #define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4927 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4928 #define check_pow_740 check_pow_hid0
4929
4930 static void init_proc_740 (CPUPPCState *env)
4931 {
4932 gen_spr_ne_601(env);
4933 gen_spr_7xx(env);
4934 /* Time base */
4935 gen_tbl(env);
4936 /* Thermal management */
4937 gen_spr_thrm(env);
4938 /* Hardware implementation registers */
4939 /* XXX : not implemented */
4940 spr_register(env, SPR_HID0, "HID0",
4941 SPR_NOACCESS, SPR_NOACCESS,
4942 &spr_read_generic, &spr_write_generic,
4943 0x00000000);
4944 /* XXX : not implemented */
4945 spr_register(env, SPR_HID1, "HID1",
4946 SPR_NOACCESS, SPR_NOACCESS,
4947 &spr_read_generic, &spr_write_generic,
4948 0x00000000);
4949 /* Memory management */
4950 gen_low_BATs(env);
4951 init_excp_7x0(env);
4952 env->dcache_line_size = 32;
4953 env->icache_line_size = 32;
4954 /* Allocate hardware IRQ controller */
4955 ppc6xx_irq_init(env);
4956 }
4957
4958 /* PowerPC 750 */
4959 #define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4960 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4961 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4962 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4963 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4964 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4965 PPC_SEGMENT | PPC_EXTERN)
4966 #define POWERPC_INSNS2_750 (PPC_NONE)
4967 #define POWERPC_MSRM_750 (0x000000000005FF77ULL)
4968 #define POWERPC_MMU_750 (POWERPC_MMU_32B)
4969 #define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
4970 #define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
4971 #define POWERPC_BFDM_750 (bfd_mach_ppc_750)
4972 #define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4973 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4974 #define check_pow_750 check_pow_hid0
4975
4976 static void init_proc_750 (CPUPPCState *env)
4977 {
4978 gen_spr_ne_601(env);
4979 gen_spr_7xx(env);
4980 /* XXX : not implemented */
4981 spr_register(env, SPR_L2CR, "L2CR",
4982 SPR_NOACCESS, SPR_NOACCESS,
4983 &spr_read_generic, &spr_write_generic,
4984 0x00000000);
4985 /* Time base */
4986 gen_tbl(env);
4987 /* Thermal management */
4988 gen_spr_thrm(env);
4989 /* Hardware implementation registers */
4990 /* XXX : not implemented */
4991 spr_register(env, SPR_HID0, "HID0",
4992 SPR_NOACCESS, SPR_NOACCESS,
4993 &spr_read_generic, &spr_write_generic,
4994 0x00000000);
4995 /* XXX : not implemented */
4996 spr_register(env, SPR_HID1, "HID1",
4997 SPR_NOACCESS, SPR_NOACCESS,
4998 &spr_read_generic, &spr_write_generic,
4999 0x00000000);
5000 /* Memory management */
5001 gen_low_BATs(env);
5002 /* XXX: high BATs are also present but are known to be bugged on
5003 * die version 1.x
5004 */
5005 init_excp_7x0(env);
5006 env->dcache_line_size = 32;
5007 env->icache_line_size = 32;
5008 /* Allocate hardware IRQ controller */
5009 ppc6xx_irq_init(env);
5010 }
5011
5012 /* PowerPC 750 CL */
5013 /* XXX: not implemented:
5014 * cache lock instructions:
5015 * dcbz_l
5016 * floating point paired instructions
5017 * psq_lux
5018 * psq_lx
5019 * psq_stux
5020 * psq_stx
5021 * ps_abs
5022 * ps_add
5023 * ps_cmpo0
5024 * ps_cmpo1
5025 * ps_cmpu0
5026 * ps_cmpu1
5027 * ps_div
5028 * ps_madd
5029 * ps_madds0
5030 * ps_madds1
5031 * ps_merge00
5032 * ps_merge01
5033 * ps_merge10
5034 * ps_merge11
5035 * ps_mr
5036 * ps_msub
5037 * ps_mul
5038 * ps_muls0
5039 * ps_muls1
5040 * ps_nabs
5041 * ps_neg
5042 * ps_nmadd
5043 * ps_nmsub
5044 * ps_res
5045 * ps_rsqrte
5046 * ps_sel
5047 * ps_sub
5048 * ps_sum0
5049 * ps_sum1
5050 */
5051 #define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5052 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5053 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5054 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5055 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5056 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5057 PPC_SEGMENT | PPC_EXTERN)
5058 #define POWERPC_INSNS2_750cl (PPC_NONE)
5059 #define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
5060 #define POWERPC_MMU_750cl (POWERPC_MMU_32B)
5061 #define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
5062 #define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
5063 #define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
5064 #define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5065 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5066 #define check_pow_750cl check_pow_hid0
5067
5068 static void init_proc_750cl (CPUPPCState *env)
5069 {
5070 gen_spr_ne_601(env);
5071 gen_spr_7xx(env);
5072 /* XXX : not implemented */
5073 spr_register(env, SPR_L2CR, "L2CR",
5074 SPR_NOACCESS, SPR_NOACCESS,
5075 &spr_read_generic, &spr_write_generic,
5076 0x00000000);
5077 /* Time base */
5078 gen_tbl(env);
5079 /* Thermal management */
5080 /* Those registers are fake on 750CL */
5081 spr_register(env, SPR_THRM1, "THRM1",
5082 SPR_NOACCESS, SPR_NOACCESS,
5083 &spr_read_generic, &spr_write_generic,
5084 0x00000000);
5085 spr_register(env, SPR_THRM2, "THRM2",
5086 SPR_NOACCESS, SPR_NOACCESS,
5087 &spr_read_generic, &spr_write_generic,
5088 0x00000000);
5089 spr_register(env, SPR_THRM3, "THRM3",
5090 SPR_NOACCESS, SPR_NOACCESS,
5091 &spr_read_generic, &spr_write_generic,
5092 0x00000000);
5093 /* XXX: not implemented */
5094 spr_register(env, SPR_750_TDCL, "TDCL",
5095 SPR_NOACCESS, SPR_NOACCESS,
5096 &spr_read_generic, &spr_write_generic,
5097 0x00000000);
5098 spr_register(env, SPR_750_TDCH, "TDCH",
5099 SPR_NOACCESS, SPR_NOACCESS,
5100 &spr_read_generic, &spr_write_generic,
5101 0x00000000);
5102 /* DMA */
5103 /* XXX : not implemented */
5104 spr_register(env, SPR_750_WPAR, "WPAR",
5105 SPR_NOACCESS, SPR_NOACCESS,
5106 &spr_read_generic, &spr_write_generic,
5107 0x00000000);
5108 spr_register(env, SPR_750_DMAL, "DMAL",
5109 SPR_NOACCESS, SPR_NOACCESS,
5110 &spr_read_generic, &spr_write_generic,
5111 0x00000000);
5112 spr_register(env, SPR_750_DMAU, "DMAU",
5113 SPR_NOACCESS, SPR_NOACCESS,
5114 &spr_read_generic, &spr_write_generic,
5115 0x00000000);
5116 /* Hardware implementation registers */
5117 /* XXX : not implemented */
5118 spr_register(env, SPR_HID0, "HID0",
5119 SPR_NOACCESS, SPR_NOACCESS,
5120 &spr_read_generic, &spr_write_generic,
5121 0x00000000);
5122 /* XXX : not implemented */
5123 spr_register(env, SPR_HID1, "HID1",
5124 SPR_NOACCESS, SPR_NOACCESS,
5125 &spr_read_generic, &spr_write_generic,
5126 0x00000000);
5127 /* XXX : not implemented */
5128 spr_register(env, SPR_750CL_HID2, "HID2",
5129 SPR_NOACCESS, SPR_NOACCESS,
5130 &spr_read_generic, &spr_write_generic,
5131 0x00000000);
5132 /* XXX : not implemented */
5133 spr_register(env, SPR_750CL_HID4, "HID4",
5134 SPR_NOACCESS, SPR_NOACCESS,
5135 &spr_read_generic, &spr_write_generic,
5136 0x00000000);
5137 /* Quantization registers */
5138 /* XXX : not implemented */
5139 spr_register(env, SPR_750_GQR0, "GQR0",
5140 SPR_NOACCESS, SPR_NOACCESS,
5141 &spr_read_generic, &spr_write_generic,
5142 0x00000000);
5143 /* XXX : not implemented */
5144 spr_register(env, SPR_750_GQR1, "GQR1",
5145 SPR_NOACCESS, SPR_NOACCESS,
5146 &spr_read_generic, &spr_write_generic,
5147 0x00000000);
5148 /* XXX : not implemented */
5149 spr_register(env, SPR_750_GQR2, "GQR2",
5150 SPR_NOACCESS, SPR_NOACCESS,
5151 &spr_read_generic, &spr_write_generic,
5152 0x00000000);
5153 /* XXX : not implemented */
5154 spr_register(env, SPR_750_GQR3, "GQR3",
5155 SPR_NOACCESS, SPR_NOACCESS,
5156 &spr_read_generic, &spr_write_generic,
5157 0x00000000);
5158 /* XXX : not implemented */
5159 spr_register(env, SPR_750_GQR4, "GQR4",
5160 SPR_NOACCESS, SPR_NOACCESS,
5161 &spr_read_generic, &spr_write_generic,
5162 0x00000000);
5163 /* XXX : not implemented */
5164 spr_register(env, SPR_750_GQR5, "GQR5",
5165 SPR_NOACCESS, SPR_NOACCESS,
5166 &spr_read_generic, &spr_write_generic,
5167 0x00000000);
5168 /* XXX : not implemented */
5169 spr_register(env, SPR_750_GQR6, "GQR6",
5170 SPR_NOACCESS, SPR_NOACCESS,
5171 &spr_read_generic, &spr_write_generic,
5172 0x00000000);
5173 /* XXX : not implemented */
5174 spr_register(env, SPR_750_GQR7, "GQR7",
5175 SPR_NOACCESS, SPR_NOACCESS,
5176 &spr_read_generic, &spr_write_generic,
5177 0x00000000);
5178 /* Memory management */
5179 gen_low_BATs(env);
5180 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5181 gen_high_BATs(env);
5182 init_excp_750cl(env);
5183 env->dcache_line_size = 32;
5184 env->icache_line_size = 32;
5185 /* Allocate hardware IRQ controller */
5186 ppc6xx_irq_init(env);
5187 }
5188
5189 /* PowerPC 750CX */
5190 #define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5191 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5192 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5193 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5194 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5195 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5196 PPC_SEGMENT | PPC_EXTERN)
5197 #define POWERPC_INSNS2_750cx (PPC_NONE)
5198 #define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
5199 #define POWERPC_MMU_750cx (POWERPC_MMU_32B)
5200 #define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
5201 #define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
5202 #define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
5203 #define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5204 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5205 #define check_pow_750cx check_pow_hid0
5206
5207 static void init_proc_750cx (CPUPPCState *env)
5208 {
5209 gen_spr_ne_601(env);
5210 gen_spr_7xx(env);
5211 /* XXX : not implemented */
5212 spr_register(env, SPR_L2CR, "L2CR",
5213 SPR_NOACCESS, SPR_NOACCESS,
5214 &spr_read_generic, &spr_write_generic,
5215 0x00000000);
5216 /* Time base */
5217 gen_tbl(env);
5218 /* Thermal management */
5219 gen_spr_thrm(env);
5220 /* This register is not implemented but is present for compatibility */
5221 spr_register(env, SPR_SDA, "SDA",
5222 SPR_NOACCESS, SPR_NOACCESS,
5223 &spr_read_generic, &spr_write_generic,
5224 0x00000000);
5225 /* Hardware implementation registers */
5226 /* XXX : not implemented */
5227 spr_register(env, SPR_HID0, "HID0",
5228 SPR_NOACCESS, SPR_NOACCESS,
5229 &spr_read_generic, &spr_write_generic,
5230 0x00000000);
5231 /* XXX : not implemented */
5232 spr_register(env, SPR_HID1, "HID1",
5233 SPR_NOACCESS, SPR_NOACCESS,
5234 &spr_read_generic, &spr_write_generic,
5235 0x00000000);
5236 /* Memory management */
5237 gen_low_BATs(env);
5238 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5239 gen_high_BATs(env);
5240 init_excp_750cx(env);
5241 env->dcache_line_size = 32;
5242 env->icache_line_size = 32;
5243 /* Allocate hardware IRQ controller */
5244 ppc6xx_irq_init(env);
5245 }
5246
5247 /* PowerPC 750FX */
5248 #define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5249 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5250 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5251 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5252 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5253 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5254 PPC_SEGMENT | PPC_EXTERN)
5255 #define POWERPC_INSNS2_750fx (PPC_NONE)
5256 #define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
5257 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
5258 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
5259 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
5260 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
5261 #define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5262 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5263 #define check_pow_750fx check_pow_hid0
5264
5265 static void init_proc_750fx (CPUPPCState *env)
5266 {
5267 gen_spr_ne_601(env);
5268 gen_spr_7xx(env);
5269 /* XXX : not implemented */
5270 spr_register(env, SPR_L2CR, "L2CR",
5271 SPR_NOACCESS, SPR_NOACCESS,
5272 &spr_read_generic, &spr_write_generic,
5273 0x00000000);
5274 /* Time base */
5275 gen_tbl(env);
5276 /* Thermal management */
5277 gen_spr_thrm(env);
5278 /* XXX : not implemented */
5279 spr_register(env, SPR_750_THRM4, "THRM4",
5280 SPR_NOACCESS, SPR_NOACCESS,
5281 &spr_read_generic, &spr_write_generic,
5282 0x00000000);
5283 /* Hardware implementation registers */
5284 /* XXX : not implemented */
5285 spr_register(env, SPR_HID0, "HID0",
5286 SPR_NOACCESS, SPR_NOACCESS,
5287 &spr_read_generic, &spr_write_generic,
5288 0x00000000);
5289 /* XXX : not implemented */
5290 spr_register(env, SPR_HID1, "HID1",
5291 SPR_NOACCESS, SPR_NOACCESS,
5292 &spr_read_generic, &spr_write_generic,
5293 0x00000000);
5294 /* XXX : not implemented */
5295 spr_register(env, SPR_750FX_HID2, "HID2",
5296 SPR_NOACCESS, SPR_NOACCESS,
5297 &spr_read_generic, &spr_write_generic,
5298 0x00000000);
5299 /* Memory management */
5300 gen_low_BATs(env);
5301 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5302 gen_high_BATs(env);
5303 init_excp_7x0(env);
5304 env->dcache_line_size = 32;
5305 env->icache_line_size = 32;
5306 /* Allocate hardware IRQ controller */
5307 ppc6xx_irq_init(env);
5308 }
5309
5310 /* PowerPC 750GX */
5311 #define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5312 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5313 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5314 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5315 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5316 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5317 PPC_SEGMENT | PPC_EXTERN)
5318 #define POWERPC_INSNS2_750gx (PPC_NONE)
5319 #define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5320 #define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5321 #define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5322 #define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5323 #define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5324 #define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5325 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5326 #define check_pow_750gx check_pow_hid0
5327
5328 static void init_proc_750gx (CPUPPCState *env)
5329 {
5330 gen_spr_ne_601(env);
5331 gen_spr_7xx(env);
5332 /* XXX : not implemented (XXX: different from 750fx) */
5333 spr_register(env, SPR_L2CR, "L2CR",
5334 SPR_NOACCESS, SPR_NOACCESS,
5335 &spr_read_generic, &spr_write_generic,
5336 0x00000000);
5337 /* Time base */
5338 gen_tbl(env);
5339 /* Thermal management */
5340 gen_spr_thrm(env);
5341 /* XXX : not implemented */
5342 spr_register(env, SPR_750_THRM4, "THRM4",
5343 SPR_NOACCESS, SPR_NOACCESS,
5344 &spr_read_generic, &spr_write_generic,
5345 0x00000000);
5346 /* Hardware implementation registers */
5347 /* XXX : not implemented (XXX: different from 750fx) */
5348 spr_register(env, SPR_HID0, "HID0",
5349 SPR_NOACCESS, SPR_NOACCESS,
5350 &spr_read_generic, &spr_write_generic,
5351 0x00000000);
5352 /* XXX : not implemented */
5353 spr_register(env, SPR_HID1, "HID1",
5354 SPR_NOACCESS, SPR_NOACCESS,
5355 &spr_read_generic, &spr_write_generic,
5356 0x00000000);
5357 /* XXX : not implemented (XXX: different from 750fx) */
5358 spr_register(env, SPR_750FX_HID2, "HID2",
5359 SPR_NOACCESS, SPR_NOACCESS,
5360 &spr_read_generic, &spr_write_generic,
5361 0x00000000);
5362 /* Memory management */
5363 gen_low_BATs(env);
5364 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5365 gen_high_BATs(env);
5366 init_excp_7x0(env);
5367 env->dcache_line_size = 32;
5368 env->icache_line_size = 32;
5369 /* Allocate hardware IRQ controller */
5370 ppc6xx_irq_init(env);
5371 }
5372
5373 /* PowerPC 745 */
5374 #define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5375 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5376 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5377 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5378 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5379 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5380 PPC_SEGMENT | PPC_EXTERN)
5381 #define POWERPC_INSNS2_745 (PPC_NONE)
5382 #define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5383 #define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5384 #define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5385 #define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5386 #define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5387 #define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5388 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5389 #define check_pow_745 check_pow_hid0
5390
5391 static void init_proc_745 (CPUPPCState *env)
5392 {
5393 gen_spr_ne_601(env);
5394 gen_spr_7xx(env);
5395 gen_spr_G2_755(env);
5396 /* Time base */
5397 gen_tbl(env);
5398 /* Thermal management */
5399 gen_spr_thrm(env);
5400 /* Hardware implementation registers */
5401 /* XXX : not implemented */
5402 spr_register(env, SPR_HID0, "HID0",
5403 SPR_NOACCESS, SPR_NOACCESS,
5404 &spr_read_generic, &spr_write_generic,
5405 0x00000000);
5406 /* XXX : not implemented */
5407 spr_register(env, SPR_HID1, "HID1",
5408 SPR_NOACCESS, SPR_NOACCESS,
5409 &spr_read_generic, &spr_write_generic,
5410 0x00000000);
5411 /* XXX : not implemented */
5412 spr_register(env, SPR_HID2, "HID2",
5413 SPR_NOACCESS, SPR_NOACCESS,
5414 &spr_read_generic, &spr_write_generic,
5415 0x00000000);
5416 /* Memory management */
5417 gen_low_BATs(env);
5418 gen_high_BATs(env);
5419 gen_6xx_7xx_soft_tlb(env, 64, 2);
5420 init_excp_7x5(env);
5421 env->dcache_line_size = 32;
5422 env->icache_line_size = 32;
5423 /* Allocate hardware IRQ controller */
5424 ppc6xx_irq_init(env);
5425 }
5426
5427 /* PowerPC 755 */
5428 #define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5429 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5430 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5431 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5432 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5433 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5434 PPC_SEGMENT | PPC_EXTERN)
5435 #define POWERPC_INSNS2_755 (PPC_NONE)
5436 #define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5437 #define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5438 #define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5439 #define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5440 #define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5441 #define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5442 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5443 #define check_pow_755 check_pow_hid0
5444
5445 static void init_proc_755 (CPUPPCState *env)
5446 {
5447 gen_spr_ne_601(env);
5448 gen_spr_7xx(env);
5449 gen_spr_G2_755(env);
5450 /* Time base */
5451 gen_tbl(env);
5452 /* L2 cache control */
5453 /* XXX : not implemented */
5454 spr_register(env, SPR_L2CR, "L2CR",
5455 SPR_NOACCESS, SPR_NOACCESS,
5456 &spr_read_generic, &spr_write_generic,
5457 0x00000000);
5458 /* XXX : not implemented */
5459 spr_register(env, SPR_L2PMCR, "L2PMCR",
5460 SPR_NOACCESS, SPR_NOACCESS,
5461 &spr_read_generic, &spr_write_generic,
5462 0x00000000);
5463 /* Thermal management */
5464 gen_spr_thrm(env);
5465 /* Hardware implementation registers */
5466 /* XXX : not implemented */
5467 spr_register(env, SPR_HID0, "HID0",
5468 SPR_NOACCESS, SPR_NOACCESS,
5469 &spr_read_generic, &spr_write_generic,
5470 0x00000000);
5471 /* XXX : not implemented */
5472 spr_register(env, SPR_HID1, "HID1",
5473 SPR_NOACCESS, SPR_NOACCESS,
5474 &spr_read_generic, &spr_write_generic,
5475 0x00000000);
5476 /* XXX : not implemented */
5477 spr_register(env, SPR_HID2, "HID2",
5478 SPR_NOACCESS, SPR_NOACCESS,
5479 &spr_read_generic, &spr_write_generic,
5480 0x00000000);
5481 /* Memory management */
5482 gen_low_BATs(env);
5483 gen_high_BATs(env);
5484 gen_6xx_7xx_soft_tlb(env, 64, 2);
5485 init_excp_7x5(env);
5486 env->dcache_line_size = 32;
5487 env->icache_line_size = 32;
5488 /* Allocate hardware IRQ controller */
5489 ppc6xx_irq_init(env);
5490 }
5491
5492 /* PowerPC 7400 (aka G4) */
5493 #define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5494 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5495 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5496 PPC_FLOAT_STFIWX | \
5497 PPC_CACHE | PPC_CACHE_ICBI | \
5498 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5499 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5500 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5501 PPC_MEM_TLBIA | \
5502 PPC_SEGMENT | PPC_EXTERN | \
5503 PPC_ALTIVEC)
5504 #define POWERPC_INSNS2_7400 (PPC_NONE)
5505 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5506 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5507 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5508 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
5509 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
5510 #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5511 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5512 POWERPC_FLAG_BUS_CLK)
5513 #define check_pow_7400 check_pow_hid0
5514
5515 static void init_proc_7400 (CPUPPCState *env)
5516 {
5517 gen_spr_ne_601(env);
5518 gen_spr_7xx(env);
5519 /* Time base */
5520 gen_tbl(env);
5521 /* 74xx specific SPR */
5522 gen_spr_74xx(env);
5523 /* XXX : not implemented */
5524 spr_register(env, SPR_UBAMR, "UBAMR",
5525 &spr_read_ureg, SPR_NOACCESS,
5526 &spr_read_ureg, SPR_NOACCESS,
5527 0x00000000);
5528 /* XXX: this seems not implemented on all revisions. */
5529 /* XXX : not implemented */
5530 spr_register(env, SPR_MSSCR1, "MSSCR1",
5531 SPR_NOACCESS, SPR_NOACCESS,
5532 &spr_read_generic, &spr_write_generic,
5533 0x00000000);
5534 /* Thermal management */
5535 gen_spr_thrm(env);
5536 /* Memory management */
5537 gen_low_BATs(env);
5538 init_excp_7400(env);
5539 env->dcache_line_size = 32;
5540 env->icache_line_size = 32;
5541 /* Allocate hardware IRQ controller */
5542 ppc6xx_irq_init(env);
5543 }
5544
5545 /* PowerPC 7410 (aka G4) */
5546 #define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5547 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5548 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5549 PPC_FLOAT_STFIWX | \
5550 PPC_CACHE | PPC_CACHE_ICBI | \
5551 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5552 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5553 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5554 PPC_MEM_TLBIA | \
5555 PPC_SEGMENT | PPC_EXTERN | \
5556 PPC_ALTIVEC)
5557 #define POWERPC_INSNS2_7410 (PPC_NONE)
5558 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5559 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5560 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5561 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
5562 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
5563 #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5564 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5565 POWERPC_FLAG_BUS_CLK)
5566 #define check_pow_7410 check_pow_hid0
5567
5568 static void init_proc_7410 (CPUPPCState *env)
5569 {
5570 gen_spr_ne_601(env);
5571 gen_spr_7xx(env);
5572 /* Time base */
5573 gen_tbl(env);
5574 /* 74xx specific SPR */
5575 gen_spr_74xx(env);
5576 /* XXX : not implemented */
5577 spr_register(env, SPR_UBAMR, "UBAMR",
5578 &spr_read_ureg, SPR_NOACCESS,
5579 &spr_read_ureg, SPR_NOACCESS,
5580 0x00000000);
5581 /* Thermal management */
5582 gen_spr_thrm(env);
5583 /* L2PMCR */
5584 /* XXX : not implemented */
5585 spr_register(env, SPR_L2PMCR, "L2PMCR",
5586 SPR_NOACCESS, SPR_NOACCESS,
5587 &spr_read_generic, &spr_write_generic,
5588 0x00000000);
5589 /* LDSTDB */
5590 /* XXX : not implemented */
5591 spr_register(env, SPR_LDSTDB, "LDSTDB",
5592 SPR_NOACCESS, SPR_NOACCESS,
5593 &spr_read_generic, &spr_write_generic,
5594 0x00000000);
5595 /* Memory management */
5596 gen_low_BATs(env);
5597 init_excp_7400(env);
5598 env->dcache_line_size = 32;
5599 env->icache_line_size = 32;
5600 /* Allocate hardware IRQ controller */
5601 ppc6xx_irq_init(env);
5602 }
5603
5604 /* PowerPC 7440 (aka G4) */
5605 #define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5606 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5607 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5608 PPC_FLOAT_STFIWX | \
5609 PPC_CACHE | PPC_CACHE_ICBI | \
5610 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5611 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5612 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5613 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5614 PPC_SEGMENT | PPC_EXTERN | \
5615 PPC_ALTIVEC)
5616 #define POWERPC_INSNS2_7440 (PPC_NONE)
5617 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5618 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5619 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5620 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
5621 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
5622 #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5623 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5624 POWERPC_FLAG_BUS_CLK)
5625 #define check_pow_7440 check_pow_hid0_74xx
5626
5627 __attribute__ (( unused ))
5628 static void init_proc_7440 (CPUPPCState *env)
5629 {
5630 gen_spr_ne_601(env);
5631 gen_spr_7xx(env);
5632 /* Time base */
5633 gen_tbl(env);
5634 /* 74xx specific SPR */
5635 gen_spr_74xx(env);
5636 /* XXX : not implemented */
5637 spr_register(env, SPR_UBAMR, "UBAMR",
5638 &spr_read_ureg, SPR_NOACCESS,
5639 &spr_read_ureg, SPR_NOACCESS,
5640 0x00000000);
5641 /* LDSTCR */
5642 /* XXX : not implemented */
5643 spr_register(env, SPR_LDSTCR, "LDSTCR",
5644 SPR_NOACCESS, SPR_NOACCESS,
5645 &spr_read_generic, &spr_write_generic,
5646 0x00000000);
5647 /* ICTRL */
5648 /* XXX : not implemented */
5649 spr_register(env, SPR_ICTRL, "ICTRL",
5650 SPR_NOACCESS, SPR_NOACCESS,
5651 &spr_read_generic, &spr_write_generic,
5652 0x00000000);
5653 /* MSSSR0 */
5654 /* XXX : not implemented */
5655 spr_register(env, SPR_MSSSR0, "MSSSR0",
5656 SPR_NOACCESS, SPR_NOACCESS,
5657 &spr_read_generic, &spr_write_generic,
5658 0x00000000);
5659 /* PMC */
5660 /* XXX : not implemented */
5661 spr_register(env, SPR_PMC5, "PMC5",
5662 SPR_NOACCESS, SPR_NOACCESS,
5663 &spr_read_generic, &spr_write_generic,
5664 0x00000000);
5665 /* XXX : not implemented */
5666 spr_register(env, SPR_UPMC5, "UPMC5",
5667 &spr_read_ureg, SPR_NOACCESS,
5668 &spr_read_ureg, SPR_NOACCESS,
5669 0x00000000);
5670 /* XXX : not implemented */
5671 spr_register(env, SPR_PMC6, "PMC6",
5672 SPR_NOACCESS, SPR_NOACCESS,
5673 &spr_read_generic, &spr_write_generic,
5674 0x00000000);
5675 /* XXX : not implemented */
5676 spr_register(env, SPR_UPMC6, "UPMC6",
5677 &spr_read_ureg, SPR_NOACCESS,
5678 &spr_read_ureg, SPR_NOACCESS,
5679 0x00000000);
5680 /* Memory management */
5681 gen_low_BATs(env);
5682 gen_74xx_soft_tlb(env, 128, 2);
5683 init_excp_7450(env);
5684 env->dcache_line_size = 32;
5685 env->icache_line_size = 32;
5686 /* Allocate hardware IRQ controller */
5687 ppc6xx_irq_init(env);
5688 }
5689
5690 /* PowerPC 7450 (aka G4) */
5691 #define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5692 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5693 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5694 PPC_FLOAT_STFIWX | \
5695 PPC_CACHE | PPC_CACHE_ICBI | \
5696 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5697 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5698 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5699 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5700 PPC_SEGMENT | PPC_EXTERN | \
5701 PPC_ALTIVEC)
5702 #define POWERPC_INSNS2_7450 (PPC_NONE)
5703 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5704 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5705 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5706 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
5707 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
5708 #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5709 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5710 POWERPC_FLAG_BUS_CLK)
5711 #define check_pow_7450 check_pow_hid0_74xx
5712
5713 __attribute__ (( unused ))
5714 static void init_proc_7450 (CPUPPCState *env)
5715 {
5716 gen_spr_ne_601(env);
5717 gen_spr_7xx(env);
5718 /* Time base */
5719 gen_tbl(env);
5720 /* 74xx specific SPR */
5721 gen_spr_74xx(env);
5722 /* Level 3 cache control */
5723 gen_l3_ctrl(env);
5724 /* L3ITCR1 */
5725 /* XXX : not implemented */
5726 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5727 SPR_NOACCESS, SPR_NOACCESS,
5728 &spr_read_generic, &spr_write_generic,
5729 0x00000000);
5730 /* L3ITCR2 */
5731 /* XXX : not implemented */
5732 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5733 SPR_NOACCESS, SPR_NOACCESS,
5734 &spr_read_generic, &spr_write_generic,
5735 0x00000000);
5736 /* L3ITCR3 */
5737 /* XXX : not implemented */
5738 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5739 SPR_NOACCESS, SPR_NOACCESS,
5740 &spr_read_generic, &spr_write_generic,
5741 0x00000000);
5742 /* L3OHCR */
5743 /* XXX : not implemented */
5744 spr_register(env, SPR_L3OHCR, "L3OHCR",
5745 SPR_NOACCESS, SPR_NOACCESS,
5746 &spr_read_generic, &spr_write_generic,
5747 0x00000000);
5748 /* XXX : not implemented */
5749 spr_register(env, SPR_UBAMR, "UBAMR",
5750 &spr_read_ureg, SPR_NOACCESS,
5751 &spr_read_ureg, SPR_NOACCESS,
5752 0x00000000);
5753 /* LDSTCR */
5754 /* XXX : not implemented */
5755 spr_register(env, SPR_LDSTCR, "LDSTCR",
5756 SPR_NOACCESS, SPR_NOACCESS,
5757 &spr_read_generic, &spr_write_generic,
5758 0x00000000);
5759 /* ICTRL */
5760 /* XXX : not implemented */
5761 spr_register(env, SPR_ICTRL, "ICTRL",
5762 SPR_NOACCESS, SPR_NOACCESS,
5763 &spr_read_generic, &spr_write_generic,
5764 0x00000000);
5765 /* MSSSR0 */
5766 /* XXX : not implemented */
5767 spr_register(env, SPR_MSSSR0, "MSSSR0",
5768 SPR_NOACCESS, SPR_NOACCESS,
5769 &spr_read_generic, &spr_write_generic,
5770 0x00000000);
5771 /* PMC */
5772 /* XXX : not implemented */
5773 spr_register(env, SPR_PMC5, "PMC5",
5774 SPR_NOACCESS, SPR_NOACCESS,
5775 &spr_read_generic, &spr_write_generic,
5776 0x00000000);
5777 /* XXX : not implemented */
5778 spr_register(env, SPR_UPMC5, "UPMC5",
5779 &spr_read_ureg, SPR_NOACCESS,
5780 &spr_read_ureg, SPR_NOACCESS,
5781 0x00000000);
5782 /* XXX : not implemented */
5783 spr_register(env, SPR_PMC6, "PMC6",
5784 SPR_NOACCESS, SPR_NOACCESS,
5785 &spr_read_generic, &spr_write_generic,
5786 0x00000000);
5787 /* XXX : not implemented */
5788 spr_register(env, SPR_UPMC6, "UPMC6",
5789 &spr_read_ureg, SPR_NOACCESS,
5790 &spr_read_ureg, SPR_NOACCESS,
5791 0x00000000);
5792 /* Memory management */
5793 gen_low_BATs(env);
5794 gen_74xx_soft_tlb(env, 128, 2);
5795 init_excp_7450(env);
5796 env->dcache_line_size = 32;
5797 env->icache_line_size = 32;
5798 /* Allocate hardware IRQ controller */
5799 ppc6xx_irq_init(env);
5800 }
5801
5802 /* PowerPC 7445 (aka G4) */
5803 #define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5804 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5805 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5806 PPC_FLOAT_STFIWX | \
5807 PPC_CACHE | PPC_CACHE_ICBI | \
5808 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5809 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5810 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5811 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5812 PPC_SEGMENT | PPC_EXTERN | \
5813 PPC_ALTIVEC)
5814 #define POWERPC_INSNS2_7445 (PPC_NONE)
5815 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5816 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5817 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5818 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
5819 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
5820 #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5821 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5822 POWERPC_FLAG_BUS_CLK)
5823 #define check_pow_7445 check_pow_hid0_74xx
5824
5825 __attribute__ (( unused ))
5826 static void init_proc_7445 (CPUPPCState *env)
5827 {
5828 gen_spr_ne_601(env);
5829 gen_spr_7xx(env);
5830 /* Time base */
5831 gen_tbl(env);
5832 /* 74xx specific SPR */
5833 gen_spr_74xx(env);
5834 /* LDSTCR */
5835 /* XXX : not implemented */
5836 spr_register(env, SPR_LDSTCR, "LDSTCR",
5837 SPR_NOACCESS, SPR_NOACCESS,
5838 &spr_read_generic, &spr_write_generic,
5839 0x00000000);
5840 /* ICTRL */
5841 /* XXX : not implemented */
5842 spr_register(env, SPR_ICTRL, "ICTRL",
5843 SPR_NOACCESS, SPR_NOACCESS,
5844 &spr_read_generic, &spr_write_generic,
5845 0x00000000);
5846 /* MSSSR0 */
5847 /* XXX : not implemented */
5848 spr_register(env, SPR_MSSSR0, "MSSSR0",
5849 SPR_NOACCESS, SPR_NOACCESS,
5850 &spr_read_generic, &spr_write_generic,
5851 0x00000000);
5852 /* PMC */
5853 /* XXX : not implemented */
5854 spr_register(env, SPR_PMC5, "PMC5",
5855 SPR_NOACCESS, SPR_NOACCESS,
5856 &spr_read_generic, &spr_write_generic,
5857 0x00000000);
5858 /* XXX : not implemented */
5859 spr_register(env, SPR_UPMC5, "UPMC5",
5860 &spr_read_ureg, SPR_NOACCESS,
5861 &spr_read_ureg, SPR_NOACCESS,
5862 0x00000000);
5863 /* XXX : not implemented */
5864 spr_register(env, SPR_PMC6, "PMC6",
5865 SPR_NOACCESS, SPR_NOACCESS,
5866 &spr_read_generic, &spr_write_generic,
5867 0x00000000);
5868 /* XXX : not implemented */
5869 spr_register(env, SPR_UPMC6, "UPMC6",
5870 &spr_read_ureg, SPR_NOACCESS,
5871 &spr_read_ureg, SPR_NOACCESS,
5872 0x00000000);
5873 /* SPRGs */
5874 spr_register(env, SPR_SPRG4, "SPRG4",
5875 SPR_NOACCESS, SPR_NOACCESS,
5876 &spr_read_generic, &spr_write_generic,
5877 0x00000000);
5878 spr_register(env, SPR_USPRG4, "USPRG4",
5879 &spr_read_ureg, SPR_NOACCESS,
5880 &spr_read_ureg, SPR_NOACCESS,
5881 0x00000000);
5882 spr_register(env, SPR_SPRG5, "SPRG5",
5883 SPR_NOACCESS, SPR_NOACCESS,
5884 &spr_read_generic, &spr_write_generic,
5885 0x00000000);
5886 spr_register(env, SPR_USPRG5, "USPRG5",
5887 &spr_read_ureg, SPR_NOACCESS,
5888 &spr_read_ureg, SPR_NOACCESS,
5889 0x00000000);
5890 spr_register(env, SPR_SPRG6, "SPRG6",
5891 SPR_NOACCESS, SPR_NOACCESS,
5892 &spr_read_generic, &spr_write_generic,
5893 0x00000000);
5894 spr_register(env, SPR_USPRG6, "USPRG6",
5895 &spr_read_ureg, SPR_NOACCESS,
5896 &spr_read_ureg, SPR_NOACCESS,
5897 0x00000000);
5898 spr_register(env, SPR_SPRG7, "SPRG7",
5899 SPR_NOACCESS, SPR_NOACCESS,
5900 &spr_read_generic, &spr_write_generic,
5901 0x00000000);
5902 spr_register(env, SPR_USPRG7, "USPRG7",
5903 &spr_read_ureg, SPR_NOACCESS,
5904 &spr_read_ureg, SPR_NOACCESS,
5905 0x00000000);
5906 /* Memory management */
5907 gen_low_BATs(env);
5908 gen_high_BATs(env);
5909 gen_74xx_soft_tlb(env, 128, 2);
5910 init_excp_7450(env);
5911 env->dcache_line_size = 32;
5912 env->icache_line_size = 32;
5913 /* Allocate hardware IRQ controller */
5914 ppc6xx_irq_init(env);
5915 }
5916
5917 /* PowerPC 7455 (aka G4) */
5918 #define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5919 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5920 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5921 PPC_FLOAT_STFIWX | \
5922 PPC_CACHE | PPC_CACHE_ICBI | \
5923 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5924 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5925 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5926 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5927 PPC_SEGMENT | PPC_EXTERN | \
5928 PPC_ALTIVEC)
5929 #define POWERPC_INSNS2_7455 (PPC_NONE)
5930 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
5931 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
5932 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
5933 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
5934 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
5935 #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5936 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5937 POWERPC_FLAG_BUS_CLK)
5938 #define check_pow_7455 check_pow_hid0_74xx
5939
5940 __attribute__ (( unused ))
5941 static void init_proc_7455 (CPUPPCState *env)
5942 {
5943 gen_spr_ne_601(env);
5944 gen_spr_7xx(env);
5945 /* Time base */
5946 gen_tbl(env);
5947 /* 74xx specific SPR */
5948 gen_spr_74xx(env);
5949 /* Level 3 cache control */
5950 gen_l3_ctrl(env);
5951 /* LDSTCR */
5952 /* XXX : not implemented */
5953 spr_register(env, SPR_LDSTCR, "LDSTCR",
5954 SPR_NOACCESS, SPR_NOACCESS,
5955 &spr_read_generic, &spr_write_generic,
5956 0x00000000);
5957 /* ICTRL */
5958 /* XXX : not implemented */
5959 spr_register(env, SPR_ICTRL, "ICTRL",
5960 SPR_NOACCESS, SPR_NOACCESS,
5961 &spr_read_generic, &spr_write_generic,
5962 0x00000000);
5963 /* MSSSR0 */
5964 /* XXX : not implemented */
5965 spr_register(env, SPR_MSSSR0, "MSSSR0",
5966 SPR_NOACCESS, SPR_NOACCESS,
5967 &spr_read_generic, &spr_write_generic,
5968 0x00000000);
5969 /* PMC */
5970 /* XXX : not implemented */
5971 spr_register(env, SPR_PMC5, "PMC5",
5972 SPR_NOACCESS, SPR_NOACCESS,
5973 &spr_read_generic, &spr_write_generic,
5974 0x00000000);
5975 /* XXX : not implemented */
5976 spr_register(env, SPR_UPMC5, "UPMC5",
5977 &spr_read_ureg, SPR_NOACCESS,
5978 &spr_read_ureg, SPR_NOACCESS,
5979 0x00000000);
5980 /* XXX : not implemented */
5981 spr_register(env, SPR_PMC6, "PMC6",
5982 SPR_NOACCESS, SPR_NOACCESS,
5983 &spr_read_generic, &spr_write_generic,
5984 0x00000000);
5985 /* XXX : not implemented */
5986 spr_register(env, SPR_UPMC6, "UPMC6",
5987 &spr_read_ureg, SPR_NOACCESS,
5988 &spr_read_ureg, SPR_NOACCESS,
5989 0x00000000);
5990 /* SPRGs */
5991 spr_register(env, SPR_SPRG4, "SPRG4",
5992 SPR_NOACCESS, SPR_NOACCESS,
5993 &spr_read_generic, &spr_write_generic,
5994 0x00000000);
5995 spr_register(env, SPR_USPRG4, "USPRG4",
5996 &spr_read_ureg, SPR_NOACCESS,
5997 &spr_read_ureg, SPR_NOACCESS,
5998 0x00000000);
5999 spr_register(env, SPR_SPRG5, "SPRG5",
6000 SPR_NOACCESS, SPR_NOACCESS,
6001 &spr_read_generic, &spr_write_generic,
6002 0x00000000);
6003 spr_register(env, SPR_USPRG5, "USPRG5",
6004 &spr_read_ureg, SPR_NOACCESS,
6005 &spr_read_ureg, SPR_NOACCESS,
6006 0x00000000);
6007 spr_register(env, SPR_SPRG6, "SPRG6",
6008 SPR_NOACCESS, SPR_NOACCESS,
6009 &spr_read_generic, &spr_write_generic,
6010 0x00000000);
6011 spr_register(env, SPR_USPRG6, "USPRG6",
6012 &spr_read_ureg, SPR_NOACCESS,
6013 &spr_read_ureg, SPR_NOACCESS,
6014 0x00000000);
6015 spr_register(env, SPR_SPRG7, "SPRG7",
6016 SPR_NOACCESS, SPR_NOACCESS,
6017 &spr_read_generic, &spr_write_generic,
6018 0x00000000);
6019 spr_register(env, SPR_USPRG7, "USPRG7",
6020 &spr_read_ureg, SPR_NOACCESS,
6021 &spr_read_ureg, SPR_NOACCESS,
6022 0x00000000);
6023 /* Memory management */
6024 gen_low_BATs(env);
6025 gen_high_BATs(env);
6026 gen_74xx_soft_tlb(env, 128, 2);
6027 init_excp_7450(env);
6028 env->dcache_line_size = 32;
6029 env->icache_line_size = 32;
6030 /* Allocate hardware IRQ controller */
6031 ppc6xx_irq_init(env);
6032 }
6033
6034 /* PowerPC 7457 (aka G4) */
6035 #define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6036 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6037 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6038 PPC_FLOAT_STFIWX | \
6039 PPC_CACHE | PPC_CACHE_ICBI | \
6040 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
6041 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6042 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6043 PPC_MEM_TLBIA | PPC_74xx_TLB | \
6044 PPC_SEGMENT | PPC_EXTERN | \
6045 PPC_ALTIVEC)
6046 #define POWERPC_INSNS2_7457 (PPC_NONE)
6047 #define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
6048 #define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
6049 #define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
6050 #define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
6051 #define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
6052 #define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6053 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6054 POWERPC_FLAG_BUS_CLK)
6055 #define check_pow_7457 check_pow_hid0_74xx
6056
6057 __attribute__ (( unused ))
6058 static void init_proc_7457 (CPUPPCState *env)
6059 {
6060 gen_spr_ne_601(env);
6061 gen_spr_7xx(env);
6062 /* Time base */
6063 gen_tbl(env);
6064 /* 74xx specific SPR */
6065 gen_spr_74xx(env);
6066 /* Level 3 cache control */
6067 gen_l3_ctrl(env);
6068 /* L3ITCR1 */
6069 /* XXX : not implemented */
6070 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6071 SPR_NOACCESS, SPR_NOACCESS,
6072 &spr_read_generic, &spr_write_generic,
6073 0x00000000);
6074 /* L3ITCR2 */
6075 /* XXX : not implemented */
6076 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6077 SPR_NOACCESS, SPR_NOACCESS,
6078 &spr_read_generic, &spr_write_generic,
6079 0x00000000);
6080 /* L3ITCR3 */
6081 /* XXX : not implemented */
6082 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6083 SPR_NOACCESS, SPR_NOACCESS,
6084 &spr_read_generic, &spr_write_generic,
6085 0x00000000);
6086 /* L3OHCR */
6087 /* XXX : not implemented */
6088 spr_register(env, SPR_L3OHCR, "L3OHCR",
6089 SPR_NOACCESS, SPR_NOACCESS,
6090 &spr_read_generic, &spr_write_generic,
6091 0x00000000);
6092 /* LDSTCR */
6093 /* XXX : not implemented */
6094 spr_register(env, SPR_LDSTCR, "LDSTCR",
6095 SPR_NOACCESS, SPR_NOACCESS,
6096 &spr_read_generic, &spr_write_generic,
6097 0x00000000);
6098 /* ICTRL */
6099 /* XXX : not implemented */
6100 spr_register(env, SPR_ICTRL, "ICTRL",
6101 SPR_NOACCESS, SPR_NOACCESS,
6102 &spr_read_generic, &spr_write_generic,
6103 0x00000000);
6104 /* MSSSR0 */
6105 /* XXX : not implemented */
6106 spr_register(env, SPR_MSSSR0, "MSSSR0",
6107 SPR_NOACCESS, SPR_NOACCESS,
6108 &spr_read_generic, &spr_write_generic,
6109 0x00000000);
6110 /* PMC */
6111 /* XXX : not implemented */
6112 spr_register(env, SPR_PMC5, "PMC5",
6113 SPR_NOACCESS, SPR_NOACCESS,
6114 &spr_read_generic, &spr_write_generic,
6115 0x00000000);
6116 /* XXX : not implemented */
6117 spr_register(env, SPR_UPMC5, "UPMC5",
6118 &spr_read_ureg, SPR_NOACCESS,
6119 &spr_read_ureg, SPR_NOACCESS,
6120 0x00000000);
6121 /* XXX : not implemented */
6122 spr_register(env, SPR_PMC6, "PMC6",
6123 SPR_NOACCESS, SPR_NOACCESS,
6124 &spr_read_generic, &spr_write_generic,
6125 0x00000000);
6126 /* XXX : not implemented */
6127 spr_register(env, SPR_UPMC6, "UPMC6",
6128 &spr_read_ureg, SPR_NOACCESS,
6129 &spr_read_ureg, SPR_NOACCESS,
6130 0x00000000);
6131 /* SPRGs */
6132 spr_register(env, SPR_SPRG4, "SPRG4",
6133 SPR_NOACCESS, SPR_NOACCESS,
6134 &spr_read_generic, &spr_write_generic,
6135 0x00000000);
6136 spr_register(env, SPR_USPRG4, "USPRG4",
6137 &spr_read_ureg, SPR_NOACCESS,
6138 &spr_read_ureg, SPR_NOACCESS,
6139 0x00000000);
6140 spr_register(env, SPR_SPRG5, "SPRG5",
6141 SPR_NOACCESS, SPR_NOACCESS,
6142 &spr_read_generic, &spr_write_generic,
6143 0x00000000);
6144 spr_register(env, SPR_USPRG5, "USPRG5",
6145 &spr_read_ureg, SPR_NOACCESS,
6146 &spr_read_ureg, SPR_NOACCESS,
6147 0x00000000);
6148 spr_register(env, SPR_SPRG6, "SPRG6",
6149 SPR_NOACCESS, SPR_NOACCESS,
6150 &spr_read_generic, &spr_write_generic,
6151 0x00000000);
6152 spr_register(env, SPR_USPRG6, "USPRG6",
6153 &spr_read_ureg, SPR_NOACCESS,
6154 &spr_read_ureg, SPR_NOACCESS,
6155 0x00000000);
6156 spr_register(env, SPR_SPRG7, "SPRG7",
6157 SPR_NOACCESS, SPR_NOACCESS,
6158 &spr_read_generic, &spr_write_generic,
6159 0x00000000);
6160 spr_register(env, SPR_USPRG7, "USPRG7",
6161 &spr_read_ureg, SPR_NOACCESS,
6162 &spr_read_ureg, SPR_NOACCESS,
6163 0x00000000);
6164 /* Memory management */
6165 gen_low_BATs(env);
6166 gen_high_BATs(env);
6167 gen_74xx_soft_tlb(env, 128, 2);
6168 init_excp_7450(env);
6169 env->dcache_line_size = 32;
6170 env->icache_line_size = 32;
6171 /* Allocate hardware IRQ controller */
6172 ppc6xx_irq_init(env);
6173 }
6174
6175 #if defined (TARGET_PPC64)
6176 /* PowerPC 970 */
6177 #define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6178 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6179 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6180 PPC_FLOAT_STFIWX | \
6181 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6182 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6183 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6184 PPC_64B | PPC_ALTIVEC | \
6185 PPC_SEGMENT_64B | PPC_SLBI)
6186 #define POWERPC_INSNS2_970 (PPC_NONE)
6187 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
6188 #define POWERPC_MMU_970 (POWERPC_MMU_64B)
6189 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
6190 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
6191 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
6192 #define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6193 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6194 POWERPC_FLAG_BUS_CLK)
6195
6196 #if defined(CONFIG_USER_ONLY)
6197 #define POWERPC970_HID5_INIT 0x00000080
6198 #else
6199 #define POWERPC970_HID5_INIT 0x00000000
6200 #endif
6201
6202 static int check_pow_970 (CPUPPCState *env)
6203 {
6204 if (env->spr[SPR_HID0] & 0x00600000)
6205 return 1;
6206
6207 return 0;
6208 }
6209
6210 static void init_proc_970 (CPUPPCState *env)
6211 {
6212 gen_spr_ne_601(env);
6213 gen_spr_7xx(env);
6214 /* Time base */
6215 gen_tbl(env);
6216 /* Hardware implementation registers */
6217 /* XXX : not implemented */
6218 spr_register(env, SPR_HID0, "HID0",
6219 SPR_NOACCESS, SPR_NOACCESS,
6220 &spr_read_generic, &spr_write_clear,
6221 0x60000000);
6222 /* XXX : not implemented */
6223 spr_register(env, SPR_HID1, "HID1",
6224 SPR_NOACCESS, SPR_NOACCESS,
6225 &spr_read_generic, &spr_write_generic,
6226 0x00000000);
6227 /* XXX : not implemented */
6228 spr_register(env, SPR_750FX_HID2, "HID2",
6229 SPR_NOACCESS, SPR_NOACCESS,
6230 &spr_read_generic, &spr_write_generic,
6231 0x00000000);
6232 /* XXX : not implemented */
6233 spr_register(env, SPR_970_HID5, "HID5",
6234 SPR_NOACCESS, SPR_NOACCESS,
6235 &spr_read_generic, &spr_write_generic,
6236 POWERPC970_HID5_INIT);
6237 /* XXX : not implemented */
6238 spr_register(env, SPR_L2CR, "L2CR",
6239 SPR_NOACCESS, SPR_NOACCESS,
6240 &spr_read_generic, &spr_write_generic,
6241 0x00000000);
6242 /* Memory management */
6243 /* XXX: not correct */
6244 gen_low_BATs(env);
6245 /* XXX : not implemented */
6246 spr_register(env, SPR_MMUCFG, "MMUCFG",
6247 SPR_NOACCESS, SPR_NOACCESS,
6248 &spr_read_generic, SPR_NOACCESS,
6249 0x00000000); /* TOFIX */
6250 /* XXX : not implemented */
6251 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6252 SPR_NOACCESS, SPR_NOACCESS,
6253 &spr_read_generic, &spr_write_generic,
6254 0x00000000); /* TOFIX */
6255 spr_register(env, SPR_HIOR, "SPR_HIOR",
6256 SPR_NOACCESS, SPR_NOACCESS,
6257 &spr_read_hior, &spr_write_hior,
6258 0x00000000);
6259 #if !defined(CONFIG_USER_ONLY)
6260 env->slb_nr = 32;
6261 #endif
6262 init_excp_970(env);
6263 env->dcache_line_size = 128;
6264 env->icache_line_size = 128;
6265 /* Allocate hardware IRQ controller */
6266 ppc970_irq_init(env);
6267 /* Can't find information on what this should be on reset. This
6268 * value is the one used by 74xx processors. */
6269 vscr_init(env, 0x00010000);
6270 }
6271
6272 /* PowerPC 970FX (aka G5) */
6273 #define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6274 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6275 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6276 PPC_FLOAT_STFIWX | \
6277 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6278 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6279 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6280 PPC_64B | PPC_ALTIVEC | \
6281 PPC_SEGMENT_64B | PPC_SLBI)
6282 #define POWERPC_INSNS2_970FX (PPC_NONE)
6283 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
6284 #define POWERPC_MMU_970FX (POWERPC_MMU_64B)
6285 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
6286 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
6287 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
6288 #define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6289 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6290 POWERPC_FLAG_BUS_CLK)
6291
6292 static int check_pow_970FX (CPUPPCState *env)
6293 {
6294 if (env->spr[SPR_HID0] & 0x00600000)
6295 return 1;
6296
6297 return 0;
6298 }
6299
6300 static void init_proc_970FX (CPUPPCState *env)
6301 {
6302 gen_spr_ne_601(env);
6303 gen_spr_7xx(env);
6304 /* Time base */
6305 gen_tbl(env);
6306 /* Hardware implementation registers */
6307 /* XXX : not implemented */
6308 spr_register(env, SPR_HID0, "HID0",
6309 SPR_NOACCESS, SPR_NOACCESS,
6310 &spr_read_generic, &spr_write_clear,
6311 0x60000000);
6312 /* XXX : not implemented */
6313 spr_register(env, SPR_HID1, "HID1",
6314 SPR_NOACCESS, SPR_NOACCESS,
6315 &spr_read_generic, &spr_write_generic,
6316 0x00000000);
6317 /* XXX : not implemented */
6318 spr_register(env, SPR_750FX_HID2, "HID2",
6319 SPR_NOACCESS, SPR_NOACCESS,
6320 &spr_read_generic, &spr_write_generic,
6321 0x00000000);
6322 /* XXX : not implemented */
6323 spr_register(env, SPR_970_HID5, "HID5",
6324 SPR_NOACCESS, SPR_NOACCESS,
6325 &spr_read_generic, &spr_write_generic,
6326 POWERPC970_HID5_INIT);
6327 /* XXX : not implemented */
6328 spr_register(env, SPR_L2CR, "L2CR",
6329 SPR_NOACCESS, SPR_NOACCESS,
6330 &spr_read_generic, &spr_write_generic,
6331 0x00000000);
6332 /* Memory management */
6333 /* XXX: not correct */
6334 gen_low_BATs(env);
6335 /* XXX : not implemented */
6336 spr_register(env, SPR_MMUCFG, "MMUCFG",
6337 SPR_NOACCESS, SPR_NOACCESS,
6338 &spr_read_generic, SPR_NOACCESS,
6339 0x00000000); /* TOFIX */
6340 /* XXX : not implemented */
6341 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6342 SPR_NOACCESS, SPR_NOACCESS,
6343 &spr_read_generic, &spr_write_generic,
6344 0x00000000); /* TOFIX */
6345 spr_register(env, SPR_HIOR, "SPR_HIOR",
6346 SPR_NOACCESS, SPR_NOACCESS,
6347 &spr_read_hior, &spr_write_hior,
6348 0x00000000);
6349 spr_register(env, SPR_CTRL, "SPR_CTRL",
6350 SPR_NOACCESS, SPR_NOACCESS,
6351 &spr_read_generic, &spr_write_generic,
6352 0x00000000);
6353 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6354 SPR_NOACCESS, SPR_NOACCESS,
6355 &spr_read_generic, &spr_write_generic,
6356 0x00000000);
6357 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6358 &spr_read_generic, &spr_write_generic,
6359 &spr_read_generic, &spr_write_generic,
6360 0x00000000);
6361 #if !defined(CONFIG_USER_ONLY)
6362 env->slb_nr = 64;
6363 #endif
6364 init_excp_970(env);
6365 env->dcache_line_size = 128;
6366 env->icache_line_size = 128;
6367 /* Allocate hardware IRQ controller */
6368 ppc970_irq_init(env);
6369 /* Can't find information on what this should be on reset. This
6370 * value is the one used by 74xx processors. */
6371 vscr_init(env, 0x00010000);
6372 }
6373
6374 /* PowerPC 970 GX */
6375 #define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6376 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6377 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6378 PPC_FLOAT_STFIWX | \
6379 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6380 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6381 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6382 PPC_64B | PPC_ALTIVEC | \
6383 PPC_SEGMENT_64B | PPC_SLBI)
6384 #define POWERPC_INSNS2_970GX (PPC_NONE)
6385 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
6386 #define POWERPC_MMU_970GX (POWERPC_MMU_64B)
6387 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6388 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
6389 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
6390 #define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6391 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6392 POWERPC_FLAG_BUS_CLK)
6393
6394 static int check_pow_970GX (CPUPPCState *env)
6395 {
6396 if (env->spr[SPR_HID0] & 0x00600000)
6397 return 1;
6398
6399 return 0;
6400 }
6401
6402 static void init_proc_970GX (CPUPPCState *env)
6403 {
6404 gen_spr_ne_601(env);
6405 gen_spr_7xx(env);
6406 /* Time base */
6407 gen_tbl(env);
6408 /* Hardware implementation registers */
6409 /* XXX : not implemented */
6410 spr_register(env, SPR_HID0, "HID0",
6411 SPR_NOACCESS, SPR_NOACCESS,
6412 &spr_read_generic, &spr_write_clear,
6413 0x60000000);
6414 /* XXX : not implemented */
6415 spr_register(env, SPR_HID1, "HID1",
6416 SPR_NOACCESS, SPR_NOACCESS,
6417 &spr_read_generic, &spr_write_generic,
6418 0x00000000);
6419 /* XXX : not implemented */
6420 spr_register(env, SPR_750FX_HID2, "HID2",
6421 SPR_NOACCESS, SPR_NOACCESS,
6422 &spr_read_generic, &spr_write_generic,
6423 0x00000000);
6424 /* XXX : not implemented */
6425 spr_register(env, SPR_970_HID5, "HID5",
6426 SPR_NOACCESS, SPR_NOACCESS,
6427 &spr_read_generic, &spr_write_generic,
6428 POWERPC970_HID5_INIT);
6429 /* XXX : not implemented */
6430 spr_register(env, SPR_L2CR, "L2CR",
6431 SPR_NOACCESS, SPR_NOACCESS,
6432 &spr_read_generic, &spr_write_generic,
6433 0x00000000);
6434 /* Memory management */
6435 /* XXX: not correct */
6436 gen_low_BATs(env);
6437 /* XXX : not implemented */
6438 spr_register(env, SPR_MMUCFG, "MMUCFG",
6439 SPR_NOACCESS, SPR_NOACCESS,
6440 &spr_read_generic, SPR_NOACCESS,
6441 0x00000000); /* TOFIX */
6442 /* XXX : not implemented */
6443 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6444 SPR_NOACCESS, SPR_NOACCESS,
6445 &spr_read_generic, &spr_write_generic,
6446 0x00000000); /* TOFIX */
6447 spr_register(env, SPR_HIOR, "SPR_HIOR",
6448 SPR_NOACCESS, SPR_NOACCESS,
6449 &spr_read_hior, &spr_write_hior,
6450 0x00000000);
6451 #if !defined(CONFIG_USER_ONLY)
6452 env->slb_nr = 32;
6453 #endif
6454 init_excp_970(env);
6455 env->dcache_line_size = 128;
6456 env->icache_line_size = 128;
6457 /* Allocate hardware IRQ controller */
6458 ppc970_irq_init(env);
6459 /* Can't find information on what this should be on reset. This
6460 * value is the one used by 74xx processors. */
6461 vscr_init(env, 0x00010000);
6462 }
6463
6464 /* PowerPC 970 MP */
6465 #define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6466 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6467 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6468 PPC_FLOAT_STFIWX | \
6469 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6470 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6471 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6472 PPC_64B | PPC_ALTIVEC | \
6473 PPC_SEGMENT_64B | PPC_SLBI)
6474 #define POWERPC_INSNS2_970MP (PPC_NONE)
6475 #define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6476 #define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6477 #define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6478 #define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6479 #define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6480 #define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6481 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6482 POWERPC_FLAG_BUS_CLK)
6483
6484 static int check_pow_970MP (CPUPPCState *env)
6485 {
6486 if (env->spr[SPR_HID0] & 0x01C00000)
6487 return 1;
6488
6489 return 0;
6490 }
6491
6492 static void init_proc_970MP (CPUPPCState *env)
6493 {
6494 gen_spr_ne_601(env);
6495 gen_spr_7xx(env);
6496 /* Time base */
6497 gen_tbl(env);
6498 /* Hardware implementation registers */
6499 /* XXX : not implemented */
6500 spr_register(env, SPR_HID0, "HID0",
6501 SPR_NOACCESS, SPR_NOACCESS,
6502 &spr_read_generic, &spr_write_clear,
6503 0x60000000);
6504 /* XXX : not implemented */
6505 spr_register(env, SPR_HID1, "HID1",
6506 SPR_NOACCESS, SPR_NOACCESS,
6507 &spr_read_generic, &spr_write_generic,
6508 0x00000000);
6509 /* XXX : not implemented */
6510 spr_register(env, SPR_750FX_HID2, "HID2",
6511 SPR_NOACCESS, SPR_NOACCESS,
6512 &spr_read_generic, &spr_write_generic,
6513 0x00000000);
6514 /* XXX : not implemented */
6515 spr_register(env, SPR_970_HID5, "HID5",
6516 SPR_NOACCESS, SPR_NOACCESS,
6517 &spr_read_generic, &spr_write_generic,
6518 POWERPC970_HID5_INIT);
6519 /* XXX : not implemented */
6520 spr_register(env, SPR_L2CR, "L2CR",
6521 SPR_NOACCESS, SPR_NOACCESS,
6522 &spr_read_generic, &spr_write_generic,
6523 0x00000000);
6524 /* Memory management */
6525 /* XXX: not correct */
6526 gen_low_BATs(env);
6527 /* XXX : not implemented */
6528 spr_register(env, SPR_MMUCFG, "MMUCFG",
6529 SPR_NOACCESS, SPR_NOACCESS,
6530 &spr_read_generic, SPR_NOACCESS,
6531 0x00000000); /* TOFIX */
6532 /* XXX : not implemented */
6533 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6534 SPR_NOACCESS, SPR_NOACCESS,
6535 &spr_read_generic, &spr_write_generic,
6536 0x00000000); /* TOFIX */
6537 spr_register(env, SPR_HIOR, "SPR_HIOR",
6538 SPR_NOACCESS, SPR_NOACCESS,
6539 &spr_read_hior, &spr_write_hior,
6540 0x00000000);
6541 #if !defined(CONFIG_USER_ONLY)
6542 env->slb_nr = 32;
6543 #endif
6544 init_excp_970(env);
6545 env->dcache_line_size = 128;
6546 env->icache_line_size = 128;
6547 /* Allocate hardware IRQ controller */
6548 ppc970_irq_init(env);
6549 /* Can't find information on what this should be on reset. This
6550 * value is the one used by 74xx processors. */
6551 vscr_init(env, 0x00010000);
6552 }
6553
6554 #if defined(TARGET_PPC64)
6555 /* POWER7 */
6556 #define POWERPC_INSNS_POWER7 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6557 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6558 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6559 PPC_FLOAT_STFIWX | \
6560 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6561 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6562 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6563 PPC_64B | PPC_ALTIVEC | \
6564 PPC_SEGMENT_64B | PPC_SLBI | \
6565 PPC_POPCNTB | PPC_POPCNTWD)
6566 #define POWERPC_INSNS2_POWER7 (PPC2_VSX | PPC2_DFP)
6567 #define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
6568 #define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
6569 #define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
6570 #define POWERPC_INPUT_POWER7 (PPC_FLAGS_INPUT_POWER7)
6571 #define POWERPC_BFDM_POWER7 (bfd_mach_ppc64)
6572 #define POWERPC_FLAG_POWER7 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6573 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6574 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR)
6575 #define check_pow_POWER7 check_pow_nocheck
6576
6577 static void init_proc_POWER7 (CPUPPCState *env)
6578 {
6579 gen_spr_ne_601(env);
6580 gen_spr_7xx(env);
6581 /* Time base */
6582 gen_tbl(env);
6583 #if !defined(CONFIG_USER_ONLY)
6584 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6585 spr_register(env, SPR_PURR, "PURR",
6586 &spr_read_purr, SPR_NOACCESS,
6587 &spr_read_purr, SPR_NOACCESS,
6588 0x00000000);
6589 spr_register(env, SPR_SPURR, "SPURR",
6590 &spr_read_purr, SPR_NOACCESS,
6591 &spr_read_purr, SPR_NOACCESS,
6592 0x00000000);
6593 spr_register(env, SPR_CFAR, "SPR_CFAR",
6594 SPR_NOACCESS, SPR_NOACCESS,
6595 &spr_read_cfar, &spr_write_cfar,
6596 0x00000000);
6597 spr_register(env, SPR_DSCR, "SPR_DSCR",
6598 SPR_NOACCESS, SPR_NOACCESS,
6599 &spr_read_generic, &spr_write_generic,
6600 0x00000000);
6601 #endif /* !CONFIG_USER_ONLY */
6602 /* Memory management */
6603 /* XXX : not implemented */
6604 spr_register(env, SPR_MMUCFG, "MMUCFG",
6605 SPR_NOACCESS, SPR_NOACCESS,
6606 &spr_read_generic, SPR_NOACCESS,
6607 0x00000000); /* TOFIX */
6608 /* XXX : not implemented */
6609 spr_register(env, SPR_CTRL, "SPR_CTRLT",
6610 SPR_NOACCESS, SPR_NOACCESS,
6611 &spr_read_generic, &spr_write_generic,
6612 0x80800000);
6613 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
6614 SPR_NOACCESS, SPR_NOACCESS,
6615 &spr_read_generic, &spr_write_generic,
6616 0x80800000);
6617 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6618 &spr_read_generic, &spr_write_generic,
6619 &spr_read_generic, &spr_write_generic,
6620 0x00000000);
6621 #if !defined(CONFIG_USER_ONLY)
6622 env->slb_nr = 32;
6623 #endif
6624 init_excp_POWER7(env);
6625 env->dcache_line_size = 128;
6626 env->icache_line_size = 128;
6627 /* Allocate hardware IRQ controller */
6628 ppcPOWER7_irq_init(env);
6629 /* Can't find information on what this should be on reset. This
6630 * value is the one used by 74xx processors. */
6631 vscr_init(env, 0x00010000);
6632 }
6633 #endif /* TARGET_PPC64 */
6634
6635 /* PowerPC 620 */
6636 #define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6637 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6638 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6639 PPC_FLOAT_STFIWX | \
6640 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6641 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6642 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6643 PPC_SEGMENT | PPC_EXTERN | \
6644 PPC_64B | PPC_SLBI)
6645 #define POWERPC_INSNS2_620 (PPC_NONE)
6646 #define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6647 //#define POWERPC_MMU_620 (POWERPC_MMU_620)
6648 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
6649 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
6650 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
6651 #define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
6652 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
6653 #define check_pow_620 check_pow_nocheck /* Check this */
6654
6655 __attribute__ (( unused ))
6656 static void init_proc_620 (CPUPPCState *env)
6657 {
6658 gen_spr_ne_601(env);
6659 gen_spr_620(env);
6660 /* Time base */
6661 gen_tbl(env);
6662 /* Hardware implementation registers */
6663 /* XXX : not implemented */
6664 spr_register(env, SPR_HID0, "HID0",
6665 SPR_NOACCESS, SPR_NOACCESS,
6666 &spr_read_generic, &spr_write_generic,
6667 0x00000000);
6668 /* Memory management */
6669 gen_low_BATs(env);
6670 init_excp_620(env);
6671 env->dcache_line_size = 64;
6672 env->icache_line_size = 64;
6673 /* Allocate hardware IRQ controller */
6674 ppc6xx_irq_init(env);
6675 }
6676 #endif /* defined (TARGET_PPC64) */
6677
6678 /* Default 32 bits PowerPC target will be 604 */
6679 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
6680 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
6681 #define POWERPC_INSNS2_PPC32 POWERPC_INSNS2_604
6682 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6683 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
6684 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6685 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
6686 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
6687 #define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
6688 #define check_pow_PPC32 check_pow_604
6689 #define init_proc_PPC32 init_proc_604
6690
6691 /* Default 64 bits PowerPC target will be 970 FX */
6692 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6693 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
6694 #define POWERPC_INSNS2_PPC64 POWERPC_INSNS2_970FX
6695 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6696 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6697 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6698 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
6699 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
6700 #define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
6701 #define check_pow_PPC64 check_pow_970FX
6702 #define init_proc_PPC64 init_proc_970FX
6703
6704 /* Default PowerPC target will be PowerPC 32 */
6705 #if defined (TARGET_PPC64) && 0 // XXX: TODO
6706 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6707 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6708 #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC64
6709 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6710 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6711 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6712 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6713 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
6714 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
6715 #define check_pow_DEFAULT check_pow_PPC64
6716 #define init_proc_DEFAULT init_proc_PPC64
6717 #else
6718 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6719 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6720 #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC32
6721 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6722 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6723 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6724 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6725 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
6726 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
6727 #define check_pow_DEFAULT check_pow_PPC32
6728 #define init_proc_DEFAULT init_proc_PPC32
6729 #endif
6730
6731 /*****************************************************************************/
6732 /* PVR definitions for most known PowerPC */
6733 enum {
6734 /* PowerPC 401 family */
6735 /* Generic PowerPC 401 */
6736 #define CPU_POWERPC_401 CPU_POWERPC_401G2
6737 /* PowerPC 401 cores */
6738 CPU_POWERPC_401A1 = 0x00210000,
6739 CPU_POWERPC_401B2 = 0x00220000,
6740 #if 0
6741 CPU_POWERPC_401B3 = xxx,
6742 #endif
6743 CPU_POWERPC_401C2 = 0x00230000,
6744 CPU_POWERPC_401D2 = 0x00240000,
6745 CPU_POWERPC_401E2 = 0x00250000,
6746 CPU_POWERPC_401F2 = 0x00260000,
6747 CPU_POWERPC_401G2 = 0x00270000,
6748 /* PowerPC 401 microcontrolers */
6749 #if 0
6750 CPU_POWERPC_401GF = xxx,
6751 #endif
6752 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
6753 /* IBM Processor for Network Resources */
6754 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
6755 #if 0
6756 CPU_POWERPC_XIPCHIP = xxx,
6757 #endif
6758 /* PowerPC 403 family */
6759 /* Generic PowerPC 403 */
6760 #define CPU_POWERPC_403 CPU_POWERPC_403GC
6761 /* PowerPC 403 microcontrollers */
6762 CPU_POWERPC_403GA = 0x00200011,
6763 CPU_POWERPC_403GB = 0x00200100,
6764 CPU_POWERPC_403GC = 0x00200200,
6765 CPU_POWERPC_403GCX = 0x00201400,
6766 #if 0
6767 CPU_POWERPC_403GP = xxx,
6768 #endif
6769 /* PowerPC 405 family */
6770 /* Generic PowerPC 405 */
6771 #define CPU_POWERPC_405 CPU_POWERPC_405D4
6772 /* PowerPC 405 cores */
6773 #if 0
6774 CPU_POWERPC_405A3 = xxx,
6775 #endif
6776 #if 0
6777 CPU_POWERPC_405A4 = xxx,
6778 #endif
6779 #if 0
6780 CPU_POWERPC_405B3 = xxx,
6781 #endif
6782 #if 0
6783 CPU_POWERPC_405B4 = xxx,
6784 #endif
6785 #if 0
6786 CPU_POWERPC_405C3 = xxx,
6787 #endif
6788 #if 0
6789 CPU_POWERPC_405C4 = xxx,
6790 #endif
6791 CPU_POWERPC_405D2 = 0x20010000,
6792 #if 0
6793 CPU_POWERPC_405D3 = xxx,
6794 #endif
6795 CPU_POWERPC_405D4 = 0x41810000,
6796 #if 0
6797 CPU_POWERPC_405D5 = xxx,
6798 #endif
6799 #if 0
6800 CPU_POWERPC_405E4 = xxx,
6801 #endif
6802 #if 0
6803 CPU_POWERPC_405F4 = xxx,
6804 #endif
6805 #if 0
6806 CPU_POWERPC_405F5 = xxx,
6807 #endif
6808 #if 0
6809 CPU_POWERPC_405F6 = xxx,
6810 #endif
6811 /* PowerPC 405 microcontrolers */
6812 /* XXX: missing 0x200108a0 */
6813 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6814 CPU_POWERPC_405CRa = 0x40110041,
6815 CPU_POWERPC_405CRb = 0x401100C5,
6816 CPU_POWERPC_405CRc = 0x40110145,
6817 CPU_POWERPC_405EP = 0x51210950,
6818 #if 0
6819 CPU_POWERPC_405EXr = xxx,
6820 #endif
6821 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
6822 #if 0
6823 CPU_POWERPC_405FX = xxx,
6824 #endif
6825 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6826 CPU_POWERPC_405GPa = 0x40110000,
6827 CPU_POWERPC_405GPb = 0x40110040,
6828 CPU_POWERPC_405GPc = 0x40110082,
6829 CPU_POWERPC_405GPd = 0x401100C4,
6830 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6831 CPU_POWERPC_405GPR = 0x50910951,
6832 #if 0
6833 CPU_POWERPC_405H = xxx,
6834 #endif
6835 #if 0
6836 CPU_POWERPC_405L = xxx,
6837 #endif
6838 CPU_POWERPC_405LP = 0x41F10000,
6839 #if 0
6840 CPU_POWERPC_405PM = xxx,
6841 #endif
6842 #if 0
6843 CPU_POWERPC_405PS = xxx,
6844 #endif
6845 #if 0
6846 CPU_POWERPC_405S = xxx,
6847 #endif
6848 /* IBM network processors */
6849 CPU_POWERPC_NPE405H = 0x414100C0,
6850 CPU_POWERPC_NPE405H2 = 0x41410140,
6851 CPU_POWERPC_NPE405L = 0x416100C0,
6852 CPU_POWERPC_NPE4GS3 = 0x40B10000,
6853 #if 0
6854 CPU_POWERPC_NPCxx1 = xxx,
6855 #endif
6856 #if 0
6857 CPU_POWERPC_NPR161 = xxx,
6858 #endif
6859 #if 0
6860 CPU_POWERPC_LC77700 = xxx,
6861 #endif
6862 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6863 #if 0
6864 CPU_POWERPC_STB01000 = xxx,
6865 #endif
6866 #if 0
6867 CPU_POWERPC_STB01010 = xxx,
6868 #endif
6869 #if 0
6870 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
6871 #endif
6872 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
6873 #if 0
6874 CPU_POWERPC_STB043 = xxx,
6875 #endif
6876 #if 0
6877 CPU_POWERPC_STB045 = xxx,
6878 #endif
6879 CPU_POWERPC_STB04 = 0x41810000,
6880 CPU_POWERPC_STB25 = 0x51510950,
6881 #if 0
6882 CPU_POWERPC_STB130 = xxx,
6883 #endif
6884 /* Xilinx cores */
6885 CPU_POWERPC_X2VP4 = 0x20010820,
6886 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
6887 CPU_POWERPC_X2VP20 = 0x20010860,
6888 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
6889 #if 0
6890 CPU_POWERPC_ZL10310 = xxx,
6891 #endif
6892 #if 0
6893 CPU_POWERPC_ZL10311 = xxx,
6894 #endif
6895 #if 0
6896 CPU_POWERPC_ZL10320 = xxx,
6897 #endif
6898 #if 0
6899 CPU_POWERPC_ZL10321 = xxx,
6900 #endif
6901 /* PowerPC 440 family */
6902 /* Generic PowerPC 440 */
6903 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
6904 /* PowerPC 440 cores */
6905 #if 0
6906 CPU_POWERPC_440A4 = xxx,
6907 #endif
6908 CPU_POWERPC_440_XILINX = 0x7ff21910,
6909 #if 0
6910 CPU_POWERPC_440A5 = xxx,
6911 #endif
6912 #if 0
6913 CPU_POWERPC_440B4 = xxx,
6914 #endif
6915 #if 0
6916 CPU_POWERPC_440F5 = xxx,
6917 #endif
6918 #if 0
6919 CPU_POWERPC_440G5 = xxx,
6920 #endif
6921 #if 0
6922 CPU_POWERPC_440H4 = xxx,
6923 #endif
6924 #if 0
6925 CPU_POWERPC_440H6 = xxx,
6926 #endif
6927 /* PowerPC 440 microcontrolers */
6928 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
6929 CPU_POWERPC_440EPa = 0x42221850,
6930 CPU_POWERPC_440EPb = 0x422218D3,
6931 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
6932 CPU_POWERPC_440GPb = 0x40120440,
6933 CPU_POWERPC_440GPc = 0x40120481,
6934 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
6935 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
6936 CPU_POWERPC_440GRX = 0x200008D0,
6937 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
6938 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
6939 CPU_POWERPC_440GXa = 0x51B21850,
6940 CPU_POWERPC_440GXb = 0x51B21851,
6941 CPU_POWERPC_440GXc = 0x51B21892,
6942 CPU_POWERPC_440GXf = 0x51B21894,
6943 #if 0
6944 CPU_POWERPC_440S = xxx,
6945 #endif
6946 CPU_POWERPC_440SP = 0x53221850,
6947 CPU_POWERPC_440SP2 = 0x53221891,
6948 CPU_POWERPC_440SPE = 0x53421890,
6949 /* PowerPC 460 family */
6950 #if 0
6951 /* Generic PowerPC 464 */
6952 #define CPU_POWERPC_464 CPU_POWERPC_464H90
6953 #endif
6954 /* PowerPC 464 microcontrolers */
6955 #if 0
6956 CPU_POWERPC_464H90 = xxx,
6957 #endif
6958 #if 0
6959 CPU_POWERPC_464H90FP = xxx,
6960 #endif
6961 /* Freescale embedded PowerPC cores */
6962 /* PowerPC MPC 5xx cores (aka RCPU) */
6963 CPU_POWERPC_MPC5xx = 0x00020020,
6964 #define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
6965 #define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
6966 #define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
6967 #define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
6968 #define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
6969 #define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
6970 #define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
6971 #define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
6972 #define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
6973 #define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
6974 #define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
6975 #define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
6976 #define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
6977 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
6978 CPU_POWERPC_MPC8xx = 0x00500000,
6979 #define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
6980 #define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
6981 #define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
6982 #define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
6983 #define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
6984 #define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
6985 #define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
6986 #define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
6987 #define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
6988 #define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
6989 #define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
6990 #define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
6991 #define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
6992 #define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
6993 #define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
6994 /* G2 cores (aka PowerQUICC-II) */
6995 CPU_POWERPC_G2 = 0x00810011,
6996 CPU_POWERPC_G2H4 = 0x80811010,
6997 CPU_POWERPC_G2gp = 0x80821010,
6998 CPU_POWERPC_G2ls = 0x90810010,
6999 CPU_POWERPC_MPC603 = 0x00810100,
7000 CPU_POWERPC_G2_HIP3 = 0x00810101,
7001 CPU_POWERPC_G2_HIP4 = 0x80811014,
7002 /* G2_LE core (aka PowerQUICC-II) */
7003 CPU_POWERPC_G2LE = 0x80820010,
7004 CPU_POWERPC_G2LEgp = 0x80822010,
7005 CPU_POWERPC_G2LEls = 0xA0822010,
7006 CPU_POWERPC_G2LEgp1 = 0x80822011,
7007 CPU_POWERPC_G2LEgp3 = 0x80822013,
7008 /* MPC52xx microcontrollers */
7009 /* XXX: MPC 5121 ? */
7010 #define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
7011 #define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
7012 #define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
7013 #define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
7014 #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
7015 #define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
7016 #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
7017 #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
7018 /* MPC82xx microcontrollers */
7019 #define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
7020 #define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
7021 #define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
7022 #define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
7023 #define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
7024 #define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
7025 #define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
7026 #define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
7027 #define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
7028 #define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
7029 #define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
7030 #define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
7031 #define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
7032 #define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
7033 #define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
7034 #define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
7035 #define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
7036 #define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
7037 #define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
7038 #define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
7039 #define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
7040 #define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
7041 #define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
7042 #define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
7043 #define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
7044 #define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
7045 #define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
7046 #define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
7047 #define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
7048 /* e200 family */
7049 /* e200 cores */
7050 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
7051 #if 0
7052 CPU_POWERPC_e200z0 = xxx,
7053 #endif
7054 #if 0
7055 CPU_POWERPC_e200z1 = xxx,
7056 #endif
7057 #if 0 /* ? */
7058 CPU_POWERPC_e200z3 = 0x81120000,
7059 #endif
7060 CPU_POWERPC_e200z5 = 0x81000000,
7061 CPU_POWERPC_e200z6 = 0x81120000,
7062 /* MPC55xx microcontrollers */
7063 #define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
7064 #if 0
7065 #define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
7066 #define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
7067 #define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
7068 #define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
7069 #define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
7070 #define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
7071 #define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
7072 #define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
7073 #define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
7074 #define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
7075 #define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
7076 #define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
7077 #define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
7078 #define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
7079 #endif
7080 #if 0
7081 #define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
7082 #define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
7083 #endif
7084 #define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
7085 #define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
7086 #define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
7087 #define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
7088 #define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
7089 #define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
7090 /* e300 family */
7091 /* e300 cores */
7092 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
7093 CPU_POWERPC_e300c1 = 0x00830010,
7094 CPU_POWERPC_e300c2 = 0x00840010,
7095 CPU_POWERPC_e300c3 = 0x00850010,
7096 CPU_POWERPC_e300c4 = 0x00860010,
7097 /* MPC83xx microcontrollers */
7098 #define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
7099 #define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
7100 #define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
7101 #define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
7102 #define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
7103 #define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
7104 /* e500 family */
7105 /* e500 cores */
7106 #define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
7107 #define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
7108 #define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
7109 CPU_POWERPC_e500v1_v10 = 0x80200010,
7110 CPU_POWERPC_e500v1_v20 = 0x80200020,
7111 CPU_POWERPC_e500v2_v10 = 0x80210010,
7112 CPU_POWERPC_e500v2_v11 = 0x80210011,
7113 CPU_POWERPC_e500v2_v20 = 0x80210020,
7114 CPU_POWERPC_e500v2_v21 = 0x80210021,
7115 CPU_POWERPC_e500v2_v22 = 0x80210022,
7116 CPU_POWERPC_e500v2_v30 = 0x80210030,
7117 CPU_POWERPC_e500mc = 0x80230020,
7118 /* MPC85xx microcontrollers */
7119 #define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
7120 #define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
7121 #define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
7122 #define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
7123 #define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
7124 #define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
7125 #define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
7126 #define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
7127 #define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
7128 #define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
7129 #define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
7130 #define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
7131 #define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
7132 #define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
7133 #define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
7134 #define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
7135 #define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
7136 #define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
7137 #define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
7138 #define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
7139 #define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
7140 #define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
7141 #define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
7142 #define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
7143 #define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
7144 #define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
7145 #define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
7146 #define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
7147 #define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
7148 #define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
7149 #define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
7150 #define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
7151 #define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
7152 #define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
7153 #define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
7154 #define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
7155 #define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
7156 #define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
7157 #define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
7158 #define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
7159 #define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
7160 #define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
7161 #define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
7162 #define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
7163 #define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
7164 #define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
7165 #define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
7166 #define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
7167 #define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
7168 #define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
7169 #define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
7170 #define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
7171 #define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
7172 #define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
7173 #define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
7174 #define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
7175 #define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
7176 #define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
7177 #define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
7178 #define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
7179 #define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
7180 #define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
7181 #define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
7182 #define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
7183 #define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
7184 #define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
7185 #define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
7186 #define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
7187 #define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
7188 #define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
7189 /* e600 family */
7190 /* e600 cores */
7191 CPU_POWERPC_e600 = 0x80040010,
7192 /* MPC86xx microcontrollers */
7193 #define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
7194 #define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
7195 #define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
7196 /* PowerPC 6xx cores */
7197 #define CPU_POWERPC_601 CPU_POWERPC_601_v2
7198 CPU_POWERPC_601_v0 = 0x00010001,
7199 CPU_POWERPC_601_v1 = 0x00010001,
7200 #define CPU_POWERPC_601v CPU_POWERPC_601_v2
7201 CPU_POWERPC_601_v2 = 0x00010002,
7202 CPU_POWERPC_602 = 0x00050100,
7203 CPU_POWERPC_603 = 0x00030100,
7204 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
7205 CPU_POWERPC_603E_v11 = 0x00060101,
7206 CPU_POWERPC_603E_v12 = 0x00060102,
7207 CPU_POWERPC_603E_v13 = 0x00060103,
7208 CPU_POWERPC_603E_v14 = 0x00060104,
7209 CPU_POWERPC_603E_v22 = 0x00060202,
7210 CPU_POWERPC_603E_v3 = 0x00060300,
7211 CPU_POWERPC_603E_v4 = 0x00060400,
7212 CPU_POWERPC_603E_v41 = 0x00060401,
7213 CPU_POWERPC_603E7t = 0x00071201,
7214 CPU_POWERPC_603E7v = 0x00070100,
7215 CPU_POWERPC_603E7v1 = 0x00070101,
7216 CPU_POWERPC_603E7v2 = 0x00070201,
7217 CPU_POWERPC_603E7 = 0x00070200,
7218 CPU_POWERPC_603P = 0x00070000,
7219 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
7220 /* XXX: missing 0x00040303 (604) */
7221 CPU_POWERPC_604 = 0x00040103,
7222 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
7223 /* XXX: missing 0x00091203 */
7224 /* XXX: missing 0x00092110 */
7225 /* XXX: missing 0x00092120 */
7226 CPU_POWERPC_604E_v10 = 0x00090100,
7227 CPU_POWERPC_604E_v22 = 0x00090202,
7228 CPU_POWERPC_604E_v24 = 0x00090204,
7229 /* XXX: missing 0x000a0100 */
7230 /* XXX: missing 0x00093102 */
7231 CPU_POWERPC_604R = 0x000a0101,
7232 #if 0
7233 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
7234 #endif
7235 /* PowerPC 740/750 cores (aka G3) */
7236 /* XXX: missing 0x00084202 */
7237 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
7238 CPU_POWERPC_7x0_v10 = 0x00080100,
7239 CPU_POWERPC_7x0_v20 = 0x00080200,
7240 CPU_POWERPC_7x0_v21 = 0x00080201,
7241 CPU_POWERPC_7x0_v22 = 0x00080202,
7242 CPU_POWERPC_7x0_v30 = 0x00080300,
7243 CPU_POWERPC_7x0_v31 = 0x00080301,
7244 CPU_POWERPC_740E = 0x00080100,
7245 CPU_POWERPC_750E = 0x00080200,
7246 CPU_POWERPC_7x0P = 0x10080000,
7247 /* XXX: missing 0x00087010 (CL ?) */
7248 #define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
7249 CPU_POWERPC_750CL_v10 = 0x00087200,
7250 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
7251 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
7252 CPU_POWERPC_750CX_v10 = 0x00082100,
7253 CPU_POWERPC_750CX_v20 = 0x00082200,
7254 CPU_POWERPC_750CX_v21 = 0x00082201,
7255 CPU_POWERPC_750CX_v22 = 0x00082202,
7256 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
7257 CPU_POWERPC_750CXE_v21 = 0x00082211,
7258 CPU_POWERPC_750CXE_v22 = 0x00082212,
7259 CPU_POWERPC_750CXE_v23 = 0x00082213,
7260 CPU_POWERPC_750CXE_v24 = 0x00082214,
7261 CPU_POWERPC_750CXE_v24b = 0x00083214,
7262 CPU_POWERPC_750CXE_v30 = 0x00082310,
7263 CPU_POWERPC_750CXE_v31 = 0x00082311,
7264 CPU_POWERPC_750CXE_v31b = 0x00083311,
7265 CPU_POWERPC_750CXR = 0x00083410,
7266 CPU_POWERPC_750FL = 0x70000203,
7267 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
7268 CPU_POWERPC_750FX_v10 = 0x70000100,
7269 CPU_POWERPC_750FX_v20 = 0x70000200,
7270 CPU_POWERPC_750FX_v21 = 0x70000201,
7271 CPU_POWERPC_750FX_v22 = 0x70000202,
7272 CPU_POWERPC_750FX_v23 = 0x70000203,
7273 CPU_POWERPC_750GL = 0x70020102,
7274 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
7275 CPU_POWERPC_750GX_v10 = 0x70020100,
7276 CPU_POWERPC_750GX_v11 = 0x70020101,
7277 CPU_POWERPC_750GX_v12 = 0x70020102,
7278 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
7279 CPU_POWERPC_750L_v20 = 0x00088200,
7280 CPU_POWERPC_750L_v21 = 0x00088201,
7281 CPU_POWERPC_750L_v22 = 0x00088202,
7282 CPU_POWERPC_750L_v30 = 0x00088300,
7283 CPU_POWERPC_750L_v32 = 0x00088302,
7284 /* PowerPC 745/755 cores */
7285 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
7286 CPU_POWERPC_7x5_v10 = 0x00083100,
7287 CPU_POWERPC_7x5_v11 = 0x00083101,
7288 CPU_POWERPC_7x5_v20 = 0x00083200,
7289 CPU_POWERPC_7x5_v21 = 0x00083201,
7290 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
7291 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
7292 CPU_POWERPC_7x5_v24 = 0x00083204,
7293 CPU_POWERPC_7x5_v25 = 0x00083205,
7294 CPU_POWERPC_7x5_v26 = 0x00083206,
7295 CPU_POWERPC_7x5_v27 = 0x00083207,
7296 CPU_POWERPC_7x5_v28 = 0x00083208,
7297 #if 0
7298 CPU_POWERPC_7x5P = xxx,
7299 #endif
7300 /* PowerPC 74xx cores (aka G4) */
7301 /* XXX: missing 0x000C1101 */
7302 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
7303 CPU_POWERPC_7400_v10 = 0x000C0100,
7304 CPU_POWERPC_7400_v11 = 0x000C0101,
7305 CPU_POWERPC_7400_v20 = 0x000C0200,
7306 CPU_POWERPC_7400_v21 = 0x000C0201,
7307 CPU_POWERPC_7400_v22 = 0x000C0202,
7308 CPU_POWERPC_7400_v26 = 0x000C0206,
7309 CPU_POWERPC_7400_v27 = 0x000C0207,
7310 CPU_POWERPC_7400_v28 = 0x000C0208,
7311 CPU_POWERPC_7400_v29 = 0x000C0209,
7312 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
7313 CPU_POWERPC_7410_v10 = 0x800C1100,
7314 CPU_POWERPC_7410_v11 = 0x800C1101,
7315 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
7316 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
7317 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
7318 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
7319 CPU_POWERPC_7448_v10 = 0x80040100,
7320 CPU_POWERPC_7448_v11 = 0x80040101,
7321 CPU_POWERPC_7448_v20 = 0x80040200,
7322 CPU_POWERPC_7448_v21 = 0x80040201,
7323 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
7324 CPU_POWERPC_7450_v10 = 0x80000100,
7325 CPU_POWERPC_7450_v11 = 0x80000101,
7326 CPU_POWERPC_7450_v12 = 0x80000102,
7327 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
7328 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
7329 #define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
7330 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
7331 /* XXX: this entry might be a bug in some documentation */
7332 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
7333 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
7334 CPU_POWERPC_74x5_v10 = 0x80010100,
7335 /* XXX: missing 0x80010200 */
7336 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
7337 CPU_POWERPC_74x5_v32 = 0x80010302,
7338 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
7339 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
7340 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
7341 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
7342 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
7343 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
7344 #define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
7345 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
7346 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
7347 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
7348 /* 64 bits PowerPC */
7349 #if defined(TARGET_PPC64)
7350 CPU_POWERPC_620 = 0x00140000,
7351 CPU_POWERPC_630 = 0x00400000,
7352 CPU_POWERPC_631 = 0x00410104,
7353 CPU_POWERPC_POWER4 = 0x00350000,
7354 CPU_POWERPC_POWER4P = 0x00380000,
7355 /* XXX: missing 0x003A0201 */
7356 CPU_POWERPC_POWER5 = 0x003A0203,
7357 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
7358 CPU_POWERPC_POWER5P = 0x003B0000,
7359 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
7360 CPU_POWERPC_POWER6 = 0x003E0000,
7361 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
7362 CPU_POWERPC_POWER6A = 0x0F000002,
7363 #define CPU_POWERPC_POWER7 CPU_POWERPC_POWER7_v20
7364 CPU_POWERPC_POWER7_v20 = 0x003F0200,
7365 CPU_POWERPC_POWER7_v21 = 0x003F0201,
7366 CPU_POWERPC_POWER7_v23 = 0x003F0203,
7367 CPU_POWERPC_970 = 0x00390202,
7368 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
7369 CPU_POWERPC_970FX_v10 = 0x00391100,
7370 CPU_POWERPC_970FX_v20 = 0x003C0200,
7371 CPU_POWERPC_970FX_v21 = 0x003C0201,
7372 CPU_POWERPC_970FX_v30 = 0x003C0300,
7373 CPU_POWERPC_970FX_v31 = 0x003C0301,
7374 CPU_POWERPC_970GX = 0x00450000,
7375 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
7376 CPU_POWERPC_970MP_v10 = 0x00440100,
7377 CPU_POWERPC_970MP_v11 = 0x00440101,
7378 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
7379 CPU_POWERPC_CELL_v10 = 0x00700100,
7380 CPU_POWERPC_CELL_v20 = 0x00700400,
7381 CPU_POWERPC_CELL_v30 = 0x00700500,
7382 CPU_POWERPC_CELL_v31 = 0x00700501,
7383 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
7384 CPU_POWERPC_RS64 = 0x00330000,
7385 CPU_POWERPC_RS64II = 0x00340000,
7386 CPU_POWERPC_RS64III = 0x00360000,
7387 CPU_POWERPC_RS64IV = 0x00370000,
7388 #endif /* defined(TARGET_PPC64) */
7389 /* Original POWER */
7390 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7391 * POWER2 (RIOS2) & RSC2 (P2SC) here
7392 */
7393 #if 0
7394 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
7395 #endif
7396 #if 0
7397 CPU_POWER2 = xxx, /* 0x40000 ? */
7398 #endif
7399 /* PA Semi core */
7400 CPU_POWERPC_PA6T = 0x00900000,
7401 };
7402
7403 /* System version register (used on MPC 8xxx) */
7404 enum {
7405 POWERPC_SVR_NONE = 0x00000000,
7406 #define POWERPC_SVR_52xx POWERPC_SVR_5200
7407 #define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
7408 POWERPC_SVR_5200_v10 = 0x80110010,
7409 POWERPC_SVR_5200_v11 = 0x80110011,
7410 POWERPC_SVR_5200_v12 = 0x80110012,
7411 #define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
7412 POWERPC_SVR_5200B_v20 = 0x80110020,
7413 POWERPC_SVR_5200B_v21 = 0x80110021,
7414 #define POWERPC_SVR_55xx POWERPC_SVR_5567
7415 #if 0
7416 POWERPC_SVR_5533 = xxx,
7417 #endif
7418 #if 0
7419 POWERPC_SVR_5534 = xxx,
7420 #endif
7421 #if 0
7422 POWERPC_SVR_5553 = xxx,
7423 #endif
7424 #if 0
7425 POWERPC_SVR_5554 = xxx,
7426 #endif
7427 #if 0
7428 POWERPC_SVR_5561 = xxx,
7429 #endif
7430 #if 0
7431 POWERPC_SVR_5565 = xxx,
7432 #endif
7433 #if 0
7434 POWERPC_SVR_5566 = xxx,
7435 #endif
7436 #if 0
7437 POWERPC_SVR_5567 = xxx,
7438 #endif
7439 #if 0
7440 POWERPC_SVR_8313 = xxx,
7441 #endif
7442 #if 0
7443 POWERPC_SVR_8313E = xxx,
7444 #endif
7445 #if 0
7446 POWERPC_SVR_8314 = xxx,
7447 #endif
7448 #if 0
7449 POWERPC_SVR_8314E = xxx,
7450 #endif
7451 #if 0
7452 POWERPC_SVR_8315 = xxx,
7453 #endif
7454 #if 0
7455 POWERPC_SVR_8315E = xxx,
7456 #endif
7457 #if 0
7458 POWERPC_SVR_8321 = xxx,
7459 #endif
7460 #if 0
7461 POWERPC_SVR_8321E = xxx,
7462 #endif
7463 #if 0
7464 POWERPC_SVR_8323 = xxx,
7465 #endif
7466 #if 0
7467 POWERPC_SVR_8323E = xxx,
7468 #endif
7469 POWERPC_SVR_8343 = 0x80570010,
7470 POWERPC_SVR_8343A = 0x80570030,
7471 POWERPC_SVR_8343E = 0x80560010,
7472 POWERPC_SVR_8343EA = 0x80560030,
7473 #define POWERPC_SVR_8347 POWERPC_SVR_8347T
7474 POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
7475 POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
7476 #define POWERPC_SVR_8347A POWERPC_SVR_8347AT
7477 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7478 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
7479 #define POWERPC_SVR_8347E POWERPC_SVR_8347ET
7480 POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
7481 POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
7482 #define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
7483 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7484 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7485 POWERPC_SVR_8349 = 0x80510010,
7486 POWERPC_SVR_8349A = 0x80510030,
7487 POWERPC_SVR_8349E = 0x80500010,
7488 POWERPC_SVR_8349EA = 0x80500030,
7489 #if 0
7490 POWERPC_SVR_8358E = xxx,
7491 #endif
7492 #if 0
7493 POWERPC_SVR_8360E = xxx,
7494 #endif
7495 #define POWERPC_SVR_E500 0x40000000
7496 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7497 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7498 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7499 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7500 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7501 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
7502 #define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
7503 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7504 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
7505 #define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
7506 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7507 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
7508 #define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
7509 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7510 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7511 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
7512 #define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
7513 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7514 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
7515 #define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
7516 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7517 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
7518 #define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
7519 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7520 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7521 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7522 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
7523 #define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
7524 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7525 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7526 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7527 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
7528 #define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
7529 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7530 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
7531 #define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
7532 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7533 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
7534 #define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
7535 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7536 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
7537 #define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
7538 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7539 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
7540 #define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
7541 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7542 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
7543 #define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
7544 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7545 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7546 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7547 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
7548 #define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
7549 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7550 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7551 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7552 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
7553 #define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
7554 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7555 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
7556 #define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
7557 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7558 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
7559 #define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
7560 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7561 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7562 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7563 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7564 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7565 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7566 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7567 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7568 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
7569 #if 0
7570 POWERPC_SVR_8610 = xxx,
7571 #endif
7572 POWERPC_SVR_8641 = 0x80900021,
7573 POWERPC_SVR_8641D = 0x80900121,
7574 };
7575
7576 /*****************************************************************************/
7577 /* PowerPC CPU definitions */
7578 #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
7579 { \
7580 .name = _name, \
7581 .pvr = _pvr, \
7582 .svr = _svr, \
7583 .insns_flags = glue(POWERPC_INSNS_,_type), \
7584 .insns_flags2 = glue(POWERPC_INSNS2_,_type), \
7585 .msr_mask = glue(POWERPC_MSRM_,_type), \
7586 .mmu_model = glue(POWERPC_MMU_,_type), \
7587 .excp_model = glue(POWERPC_EXCP_,_type), \
7588 .bus_model = glue(POWERPC_INPUT_,_type), \
7589 .bfd_mach = glue(POWERPC_BFDM_,_type), \
7590 .flags = glue(POWERPC_FLAG_,_type), \
7591 .init_proc = &glue(init_proc_,_type), \
7592 .check_pow = &glue(check_pow_,_type), \
7593 }
7594 #define POWERPC_DEF(_name, _pvr, _type) \
7595 POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
7596
7597 static const ppc_def_t ppc_defs[] = {
7598 /* Embedded PowerPC */
7599 /* PowerPC 401 family */
7600 /* Generic PowerPC 401 */
7601 POWERPC_DEF("401", CPU_POWERPC_401, 401),
7602 /* PowerPC 401 cores */
7603 /* PowerPC 401A1 */
7604 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
7605 /* PowerPC 401B2 */
7606 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
7607 #if defined (TODO)
7608 /* PowerPC 401B3 */
7609 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
7610 #endif
7611 /* PowerPC 401C2 */
7612 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
7613 /* PowerPC 401D2 */
7614 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
7615 /* PowerPC 401E2 */
7616 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
7617 /* PowerPC 401F2 */
7618 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
7619 /* PowerPC 401G2 */
7620 /* XXX: to be checked */
7621 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
7622 /* PowerPC 401 microcontrolers */
7623 #if defined (TODO)
7624 /* PowerPC 401GF */
7625 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
7626 #endif
7627 /* IOP480 (401 microcontroler) */
7628 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
7629 /* IBM Processor for Network Resources */
7630 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
7631 #if defined (TODO)
7632 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
7633 #endif
7634 /* PowerPC 403 family */
7635 /* Generic PowerPC 403 */
7636 POWERPC_DEF("403", CPU_POWERPC_403, 403),
7637 /* PowerPC 403 microcontrolers */
7638 /* PowerPC 403 GA */
7639 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
7640 /* PowerPC 403 GB */
7641 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
7642 /* PowerPC 403 GC */
7643 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
7644 /* PowerPC 403 GCX */
7645 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
7646 #if defined (TODO)
7647 /* PowerPC 403 GP */
7648 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
7649 #endif
7650 /* PowerPC 405 family */
7651 /* Generic PowerPC 405 */
7652 POWERPC_DEF("405", CPU_POWERPC_405, 405),
7653 /* PowerPC 405 cores */
7654 #if defined (TODO)
7655 /* PowerPC 405 A3 */
7656 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
7657 #endif
7658 #if defined (TODO)
7659 /* PowerPC 405 A4 */
7660 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
7661 #endif
7662 #if defined (TODO)
7663 /* PowerPC 405 B3 */
7664 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
7665 #endif
7666 #if defined (TODO)
7667 /* PowerPC 405 B4 */
7668 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
7669 #endif
7670 #if defined (TODO)
7671 /* PowerPC 405 C3 */
7672 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
7673 #endif
7674 #if defined (TODO)
7675 /* PowerPC 405 C4 */
7676 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
7677 #endif
7678 /* PowerPC 405 D2 */
7679 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
7680 #if defined (TODO)
7681 /* PowerPC 405 D3 */
7682 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
7683 #endif
7684 /* PowerPC 405 D4 */
7685 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
7686 #if defined (TODO)
7687 /* PowerPC 405 D5 */
7688 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
7689 #endif
7690 #if defined (TODO)
7691 /* PowerPC 405 E4 */
7692 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
7693 #endif
7694 #if defined (TODO)
7695 /* PowerPC 405 F4 */
7696 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
7697 #endif
7698 #if defined (TODO)
7699 /* PowerPC 405 F5 */
7700 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
7701 #endif
7702 #if defined (TODO)
7703 /* PowerPC 405 F6 */
7704 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
7705 #endif
7706 /* PowerPC 405 microcontrolers */
7707 /* PowerPC 405 CR */
7708 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
7709 /* PowerPC 405 CRa */
7710 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
7711 /* PowerPC 405 CRb */
7712 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
7713 /* PowerPC 405 CRc */
7714 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
7715 /* PowerPC 405 EP */
7716 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
7717 #if defined(TODO)
7718 /* PowerPC 405 EXr */
7719 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
7720 #endif
7721 /* PowerPC 405 EZ */
7722 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
7723 #if defined(TODO)
7724 /* PowerPC 405 FX */
7725 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
7726 #endif
7727 /* PowerPC 405 GP */
7728 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
7729 /* PowerPC 405 GPa */
7730 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
7731 /* PowerPC 405 GPb */
7732 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
7733 /* PowerPC 405 GPc */
7734 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
7735 /* PowerPC 405 GPd */
7736 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
7737 /* PowerPC 405 GPe */
7738 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
7739 /* PowerPC 405 GPR */
7740 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
7741 #if defined(TODO)
7742 /* PowerPC 405 H */
7743 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
7744 #endif
7745 #if defined(TODO)
7746 /* PowerPC 405 L */
7747 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
7748 #endif
7749 /* PowerPC 405 LP */
7750 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
7751 #if defined(TODO)
7752 /* PowerPC 405 PM */
7753 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
7754 #endif
7755 #if defined(TODO)
7756 /* PowerPC 405 PS */
7757 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
7758 #endif
7759 #if defined(TODO)
7760 /* PowerPC 405 S */
7761 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
7762 #endif
7763 /* Npe405 H */
7764 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
7765 /* Npe405 H2 */
7766 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
7767 /* Npe405 L */
7768 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
7769 /* Npe4GS3 */
7770 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
7771 #if defined (TODO)
7772 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
7773 #endif
7774 #if defined (TODO)
7775 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
7776 #endif
7777 #if defined (TODO)
7778 /* PowerPC LC77700 (Sanyo) */
7779 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
7780 #endif
7781 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7782 #if defined (TODO)
7783 /* STB010000 */
7784 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
7785 #endif
7786 #if defined (TODO)
7787 /* STB01010 */
7788 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
7789 #endif
7790 #if defined (TODO)
7791 /* STB0210 */
7792 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
7793 #endif
7794 /* STB03xx */
7795 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
7796 #if defined (TODO)
7797 /* STB043x */
7798 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
7799 #endif
7800 #if defined (TODO)
7801 /* STB045x */
7802 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
7803 #endif
7804 /* STB04xx */
7805 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
7806 /* STB25xx */
7807 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
7808 #if defined (TODO)
7809 /* STB130 */
7810 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
7811 #endif
7812 /* Xilinx PowerPC 405 cores */
7813 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
7814 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
7815 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
7816 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
7817 #if defined (TODO)
7818 /* Zarlink ZL10310 */
7819 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
7820 #endif
7821 #if defined (TODO)
7822 /* Zarlink ZL10311 */
7823 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
7824 #endif
7825 #if defined (TODO)
7826 /* Zarlink ZL10320 */
7827 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
7828 #endif
7829 #if defined (TODO)
7830 /* Zarlink ZL10321 */
7831 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
7832 #endif
7833 /* PowerPC 440 family */
7834 #if defined(TODO_USER_ONLY)
7835 /* Generic PowerPC 440 */
7836 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
7837 #endif
7838 /* PowerPC 440 cores */
7839 #if defined (TODO)
7840 /* PowerPC 440 A4 */
7841 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
7842 #endif
7843 /* PowerPC 440 Xilinx 5 */
7844 POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5),
7845 #if defined (TODO)
7846 /* PowerPC 440 A5 */
7847 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
7848 #endif
7849 #if defined (TODO)
7850 /* PowerPC 440 B4 */
7851 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
7852 #endif
7853 #if defined (TODO)
7854 /* PowerPC 440 G4 */
7855 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
7856 #endif
7857 #if defined (TODO)
7858 /* PowerPC 440 F5 */
7859 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
7860 #endif
7861 #if defined (TODO)
7862 /* PowerPC 440 G5 */
7863 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
7864 #endif
7865 #if defined (TODO)
7866 /* PowerPC 440H4 */
7867 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
7868 #endif
7869 #if defined (TODO)
7870 /* PowerPC 440H6 */
7871 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
7872 #endif
7873 /* PowerPC 440 microcontrolers */
7874 /* PowerPC 440 EP */
7875 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
7876 /* PowerPC 440 EPa */
7877 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
7878 /* PowerPC 440 EPb */
7879 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
7880 /* PowerPC 440 EPX */
7881 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
7882 #if defined(TODO_USER_ONLY)
7883 /* PowerPC 440 GP */
7884 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
7885 #endif
7886 #if defined(TODO_USER_ONLY)
7887 /* PowerPC 440 GPb */
7888 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
7889 #endif
7890 #if defined(TODO_USER_ONLY)
7891 /* PowerPC 440 GPc */
7892 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
7893 #endif
7894 #if defined(TODO_USER_ONLY)
7895 /* PowerPC 440 GR */
7896 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
7897 #endif
7898 #if defined(TODO_USER_ONLY)
7899 /* PowerPC 440 GRa */
7900 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
7901 #endif
7902 #if defined(TODO_USER_ONLY)
7903 /* PowerPC 440 GRX */
7904 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
7905 #endif
7906 #if defined(TODO_USER_ONLY)
7907 /* PowerPC 440 GX */
7908 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
7909 #endif
7910 #if defined(TODO_USER_ONLY)
7911 /* PowerPC 440 GXa */
7912 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
7913 #endif
7914 #if defined(TODO_USER_ONLY)
7915 /* PowerPC 440 GXb */
7916 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
7917 #endif
7918 #if defined(TODO_USER_ONLY)
7919 /* PowerPC 440 GXc */
7920 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
7921 #endif
7922 #if defined(TODO_USER_ONLY)
7923 /* PowerPC 440 GXf */
7924 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
7925 #endif
7926 #if defined(TODO)
7927 /* PowerPC 440 S */
7928 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
7929 #endif
7930 #if defined(TODO_USER_ONLY)
7931 /* PowerPC 440 SP */
7932 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
7933 #endif
7934 #if defined(TODO_USER_ONLY)
7935 /* PowerPC 440 SP2 */
7936 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
7937 #endif
7938 #if defined(TODO_USER_ONLY)
7939 /* PowerPC 440 SPE */
7940 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
7941 #endif
7942 /* PowerPC 460 family */
7943 #if defined (TODO)
7944 /* Generic PowerPC 464 */
7945 POWERPC_DEF("464", CPU_POWERPC_464, 460),
7946 #endif
7947 /* PowerPC 464 microcontrolers */
7948 #if defined (TODO)
7949 /* PowerPC 464H90 */
7950 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
7951 #endif
7952 #if defined (TODO)
7953 /* PowerPC 464H90F */
7954 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
7955 #endif
7956 /* Freescale embedded PowerPC cores */
7957 /* MPC5xx family (aka RCPU) */
7958 #if defined(TODO_USER_ONLY)
7959 /* Generic MPC5xx core */
7960 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
7961 #endif
7962 #if defined(TODO_USER_ONLY)
7963 /* Codename for MPC5xx core */
7964 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
7965 #endif
7966 /* MPC5xx microcontrollers */
7967 #if defined(TODO_USER_ONLY)
7968 /* MGT560 */
7969 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
7970 #endif
7971 #if defined(TODO_USER_ONLY)
7972 /* MPC509 */
7973 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
7974 #endif
7975 #if defined(TODO_USER_ONLY)
7976 /* MPC533 */
7977 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
7978 #endif
7979 #if defined(TODO_USER_ONLY)
7980 /* MPC534 */
7981 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
7982 #endif
7983 #if defined(TODO_USER_ONLY)
7984 /* MPC555 */
7985 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
7986 #endif
7987 #if defined(TODO_USER_ONLY)
7988 /* MPC556 */
7989 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
7990 #endif
7991 #if defined(TODO_USER_ONLY)
7992 /* MPC560 */
7993 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
7994 #endif
7995 #if defined(TODO_USER_ONLY)
7996 /* MPC561 */
7997 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
7998 #endif
7999 #if defined(TODO_USER_ONLY)
8000 /* MPC562 */
8001 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
8002 #endif
8003 #if defined(TODO_USER_ONLY)
8004 /* MPC563 */
8005 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
8006 #endif
8007 #if defined(TODO_USER_ONLY)
8008 /* MPC564 */
8009 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
8010 #endif
8011 #if defined(TODO_USER_ONLY)
8012 /* MPC565 */
8013 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
8014 #endif
8015 #if defined(TODO_USER_ONLY)
8016 /* MPC566 */
8017 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
8018 #endif
8019 /* MPC8xx family (aka PowerQUICC) */
8020 #if defined(TODO_USER_ONLY)
8021 /* Generic MPC8xx core */
8022 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
8023 #endif
8024 #if defined(TODO_USER_ONLY)
8025 /* Codename for MPC8xx core */
8026 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
8027 #endif
8028 /* MPC8xx microcontrollers */
8029 #if defined(TODO_USER_ONLY)
8030 /* MGT823 */
8031 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
8032 #endif
8033 #if defined(TODO_USER_ONLY)
8034 /* MPC821 */
8035 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
8036 #endif
8037 #if defined(TODO_USER_ONLY)
8038 /* MPC823 */
8039 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
8040 #endif
8041 #if defined(TODO_USER_ONLY)
8042 /* MPC850 */
8043 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
8044 #endif
8045 #if defined(TODO_USER_ONLY)
8046 /* MPC852T */
8047 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
8048 #endif
8049 #if defined(TODO_USER_ONLY)
8050 /* MPC855T */
8051 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
8052 #endif
8053 #if defined(TODO_USER_ONLY)
8054 /* MPC857 */
8055 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
8056 #endif
8057 #if defined(TODO_USER_ONLY)
8058 /* MPC859 */
8059 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
8060 #endif
8061 #if defined(TODO_USER_ONLY)
8062 /* MPC860 */
8063 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
8064 #endif
8065 #if defined(TODO_USER_ONLY)
8066 /* MPC862 */
8067 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
8068 #endif
8069 #if defined(TODO_USER_ONLY)
8070 /* MPC866 */
8071 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
8072 #endif
8073 #if defined(TODO_USER_ONLY)
8074 /* MPC870 */
8075 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
8076 #endif
8077 #if defined(TODO_USER_ONLY)
8078 /* MPC875 */
8079 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
8080 #endif
8081 #if defined(TODO_USER_ONLY)
8082 /* MPC880 */
8083 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
8084 #endif
8085 #if defined(TODO_USER_ONLY)
8086 /* MPC885 */
8087 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
8088 #endif
8089 /* MPC82xx family (aka PowerQUICC-II) */
8090 /* Generic MPC52xx core */
8091 POWERPC_DEF_SVR("MPC52xx",
8092 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
8093 /* Generic MPC82xx core */
8094 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
8095 /* Codename for MPC82xx */
8096 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
8097 /* PowerPC G2 core */
8098 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
8099 /* PowerPC G2 H4 core */
8100 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
8101 /* PowerPC G2 GP core */
8102 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
8103 /* PowerPC G2 LS core */
8104 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
8105 /* PowerPC G2 HiP3 core */
8106 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
8107 /* PowerPC G2 HiP4 core */
8108 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
8109 /* PowerPC MPC603 core */
8110 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
8111 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
8112 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
8113 /* PowerPC G2LE GP core */
8114 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
8115 /* PowerPC G2LE LS core */
8116 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
8117 /* PowerPC G2LE GP1 core */
8118 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
8119 /* PowerPC G2LE GP3 core */
8120 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
8121 /* PowerPC MPC603 microcontrollers */
8122 /* MPC8240 */
8123 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
8124 /* PowerPC G2 microcontrollers */
8125 #if defined(TODO)
8126 /* MPC5121 */
8127 POWERPC_DEF_SVR("MPC5121",
8128 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
8129 #endif
8130 /* MPC5200 */
8131 POWERPC_DEF_SVR("MPC5200",
8132 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
8133 /* MPC5200 v1.0 */
8134 POWERPC_DEF_SVR("MPC5200_v10",
8135 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
8136 /* MPC5200 v1.1 */
8137 POWERPC_DEF_SVR("MPC5200_v11",
8138 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
8139 /* MPC5200 v1.2 */
8140 POWERPC_DEF_SVR("MPC5200_v12",
8141 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
8142 /* MPC5200B */
8143 POWERPC_DEF_SVR("MPC5200B",
8144 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
8145 /* MPC5200B v2.0 */
8146 POWERPC_DEF_SVR("MPC5200B_v20",
8147 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
8148 /* MPC5200B v2.1 */
8149 POWERPC_DEF_SVR("MPC5200B_v21",
8150 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
8151 /* MPC8241 */
8152 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
8153 /* MPC8245 */
8154 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
8155 /* MPC8247 */
8156 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
8157 /* MPC8248 */
8158 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
8159 /* MPC8250 */
8160 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
8161 /* MPC8250 HiP3 */
8162 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
8163 /* MPC8250 HiP4 */
8164 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
8165 /* MPC8255 */
8166 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
8167 /* MPC8255 HiP3 */
8168 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
8169 /* MPC8255 HiP4 */
8170 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
8171 /* MPC8260 */
8172 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
8173 /* MPC8260 HiP3 */
8174 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
8175 /* MPC8260 HiP4 */
8176 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
8177 /* MPC8264 */
8178 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
8179 /* MPC8264 HiP3 */
8180 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
8181 /* MPC8264 HiP4 */
8182 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
8183 /* MPC8265 */
8184 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
8185 /* MPC8265 HiP3 */
8186 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
8187 /* MPC8265 HiP4 */
8188 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
8189 /* MPC8266 */
8190 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
8191 /* MPC8266 HiP3 */
8192 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
8193 /* MPC8266 HiP4 */
8194 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
8195 /* MPC8270 */
8196 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
8197 /* MPC8271 */
8198 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
8199 /* MPC8272 */
8200 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
8201 /* MPC8275 */
8202 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
8203 /* MPC8280 */
8204 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
8205 /* e200 family */
8206 /* Generic PowerPC e200 core */
8207 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
8208 /* Generic MPC55xx core */
8209 #if defined (TODO)
8210 POWERPC_DEF_SVR("MPC55xx",
8211 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
8212 #endif
8213 #if defined (TODO)
8214 /* PowerPC e200z0 core */
8215 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
8216 #endif
8217 #if defined (TODO)
8218 /* PowerPC e200z1 core */
8219 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
8220 #endif
8221 #if defined (TODO)
8222 /* PowerPC e200z3 core */
8223 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
8224 #endif
8225 /* PowerPC e200z5 core */
8226 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
8227 /* PowerPC e200z6 core */
8228 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
8229 /* PowerPC e200 microcontrollers */
8230 #if defined (TODO)
8231 /* MPC5514E */
8232 POWERPC_DEF_SVR("MPC5514E",
8233 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
8234 #endif
8235 #if defined (TODO)
8236 /* MPC5514E v0 */
8237 POWERPC_DEF_SVR("MPC5514E_v0",
8238 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
8239 #endif
8240 #if defined (TODO)
8241 /* MPC5514E v1 */
8242 POWERPC_DEF_SVR("MPC5514E_v1",
8243 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
8244 #endif
8245 #if defined (TODO)
8246 /* MPC5514G */
8247 POWERPC_DEF_SVR("MPC5514G",
8248 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
8249 #endif
8250 #if defined (TODO)
8251 /* MPC5514G v0 */
8252 POWERPC_DEF_SVR("MPC5514G_v0",
8253 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
8254 #endif
8255 #if defined (TODO)
8256 /* MPC5514G v1 */
8257 POWERPC_DEF_SVR("MPC5514G_v1",
8258 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
8259 #endif
8260 #if defined (TODO)
8261 /* MPC5515S */
8262 POWERPC_DEF_SVR("MPC5515S",
8263 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
8264 #endif
8265 #if defined (TODO)
8266 /* MPC5516E */
8267 POWERPC_DEF_SVR("MPC5516E",
8268 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
8269 #endif
8270 #if defined (TODO)
8271 /* MPC5516E v0 */
8272 POWERPC_DEF_SVR("MPC5516E_v0",
8273 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
8274 #endif
8275 #if defined (TODO)
8276 /* MPC5516E v1 */
8277 POWERPC_DEF_SVR("MPC5516E_v1",
8278 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
8279 #endif
8280 #if defined (TODO)
8281 /* MPC5516G */
8282 POWERPC_DEF_SVR("MPC5516G",
8283 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
8284 #endif
8285 #if defined (TODO)
8286 /* MPC5516G v0 */
8287 POWERPC_DEF_SVR("MPC5516G_v0",
8288 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
8289 #endif
8290 #if defined (TODO)
8291 /* MPC5516G v1 */
8292 POWERPC_DEF_SVR("MPC5516G_v1",
8293 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
8294 #endif
8295 #if defined (TODO)
8296 /* MPC5516S */
8297 POWERPC_DEF_SVR("MPC5516S",
8298 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
8299 #endif
8300 #if defined (TODO)
8301 /* MPC5533 */
8302 POWERPC_DEF_SVR("MPC5533",
8303 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
8304 #endif
8305 #if defined (TODO)
8306 /* MPC5534 */
8307 POWERPC_DEF_SVR("MPC5534",
8308 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
8309 #endif
8310 #if defined (TODO)
8311 /* MPC5553 */
8312 POWERPC_DEF_SVR("MPC5553",
8313 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
8314 #endif
8315 #if defined (TODO)
8316 /* MPC5554 */
8317 POWERPC_DEF_SVR("MPC5554",
8318 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
8319 #endif
8320 #if defined (TODO)
8321 /* MPC5561 */
8322 POWERPC_DEF_SVR("MPC5561",
8323 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
8324 #endif
8325 #if defined (TODO)
8326 /* MPC5565 */
8327 POWERPC_DEF_SVR("MPC5565",
8328 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
8329 #endif
8330 #if defined (TODO)
8331 /* MPC5566 */
8332 POWERPC_DEF_SVR("MPC5566",
8333 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
8334 #endif
8335 #if defined (TODO)
8336 /* MPC5567 */
8337 POWERPC_DEF_SVR("MPC5567",
8338 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
8339 #endif
8340 /* e300 family */
8341 /* Generic PowerPC e300 core */
8342 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
8343 /* PowerPC e300c1 core */
8344 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
8345 /* PowerPC e300c2 core */
8346 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
8347 /* PowerPC e300c3 core */
8348 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
8349 /* PowerPC e300c4 core */
8350 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
8351 /* PowerPC e300 microcontrollers */
8352 #if defined (TODO)
8353 /* MPC8313 */
8354 POWERPC_DEF_SVR("MPC8313",
8355 CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300),
8356 #endif
8357 #if defined (TODO)
8358 /* MPC8313E */
8359 POWERPC_DEF_SVR("MPC8313E",
8360 CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300),
8361 #endif
8362 #if defined (TODO)
8363 /* MPC8314 */
8364 POWERPC_DEF_SVR("MPC8314",
8365 CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300),
8366 #endif
8367 #if defined (TODO)
8368 /* MPC8314E */
8369 POWERPC_DEF_SVR("MPC8314E",
8370 CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300),
8371 #endif
8372 #if defined (TODO)
8373 /* MPC8315 */
8374 POWERPC_DEF_SVR("MPC8315",
8375 CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300),
8376 #endif
8377 #if defined (TODO)
8378 /* MPC8315E */
8379 POWERPC_DEF_SVR("MPC8315E",
8380 CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300),
8381 #endif
8382 #if defined (TODO)
8383 /* MPC8321 */
8384 POWERPC_DEF_SVR("MPC8321",
8385 CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300),
8386 #endif
8387 #if defined (TODO)
8388 /* MPC8321E */
8389 POWERPC_DEF_SVR("MPC8321E",
8390 CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300),
8391 #endif
8392 #if defined (TODO)
8393 /* MPC8323 */
8394 POWERPC_DEF_SVR("MPC8323",
8395 CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300),
8396 #endif
8397 #if defined (TODO)
8398 /* MPC8323E */
8399 POWERPC_DEF_SVR("MPC8323E",
8400 CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300),
8401 #endif
8402 /* MPC8343 */
8403 POWERPC_DEF_SVR("MPC8343",
8404 CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300),
8405 /* MPC8343A */
8406 POWERPC_DEF_SVR("MPC8343A",
8407 CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300),
8408 /* MPC8343E */
8409 POWERPC_DEF_SVR("MPC8343E",
8410 CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300),
8411 /* MPC8343EA */
8412 POWERPC_DEF_SVR("MPC8343EA",
8413 CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300),
8414 /* MPC8347 */
8415 POWERPC_DEF_SVR("MPC8347",
8416 CPU_POWERPC_MPC834x, POWERPC_SVR_8347, e300),
8417 /* MPC8347T */
8418 POWERPC_DEF_SVR("MPC8347T",
8419 CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300),
8420 /* MPC8347P */
8421 POWERPC_DEF_SVR("MPC8347P",
8422 CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300),
8423 /* MPC8347A */
8424 POWERPC_DEF_SVR("MPC8347A",
8425 CPU_POWERPC_MPC834x, POWERPC_SVR_8347A, e300),
8426 /* MPC8347AT */
8427 POWERPC_DEF_SVR("MPC8347AT",
8428 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300),
8429 /* MPC8347AP */
8430 POWERPC_DEF_SVR("MPC8347AP",
8431 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300),
8432 /* MPC8347E */
8433 POWERPC_DEF_SVR("MPC8347E",
8434 CPU_POWERPC_MPC834x, POWERPC_SVR_8347E, e300),
8435 /* MPC8347ET */
8436 POWERPC_DEF_SVR("MPC8347ET",
8437 CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300),
8438 /* MPC8343EP */
8439 POWERPC_DEF_SVR("MPC8347EP",
8440 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300),
8441 /* MPC8347EA */
8442 POWERPC_DEF_SVR("MPC8347EA",
8443 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EA, e300),
8444 /* MPC8347EAT */
8445 POWERPC_DEF_SVR("MPC8347EAT",
8446 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300),
8447 /* MPC8343EAP */
8448 POWERPC_DEF_SVR("MPC8347EAP",
8449 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300),
8450 /* MPC8349 */
8451 POWERPC_DEF_SVR("MPC8349",
8452 CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300),
8453 /* MPC8349A */
8454 POWERPC_DEF_SVR("MPC8349A",
8455 CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300),
8456 /* MPC8349E */
8457 POWERPC_DEF_SVR("MPC8349E",
8458 CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300),
8459 /* MPC8349EA */
8460 POWERPC_DEF_SVR("MPC8349EA",
8461 CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300),
8462 #if defined (TODO)
8463 /* MPC8358E */
8464 POWERPC_DEF_SVR("MPC8358E",
8465 CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300),
8466 #endif
8467 #if defined (TODO)
8468 /* MPC8360E */
8469 POWERPC_DEF_SVR("MPC8360E",
8470 CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300),
8471 #endif
8472 /* MPC8377 */
8473 POWERPC_DEF_SVR("MPC8377",
8474 CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300),
8475 /* MPC8377E */
8476 POWERPC_DEF_SVR("MPC8377E",
8477 CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300),
8478 /* MPC8378 */
8479 POWERPC_DEF_SVR("MPC8378",
8480 CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300),
8481 /* MPC8378E */
8482 POWERPC_DEF_SVR("MPC8378E",
8483 CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300),
8484 /* MPC8379 */
8485 POWERPC_DEF_SVR("MPC8379",
8486 CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300),
8487 /* MPC8379E */
8488 POWERPC_DEF_SVR("MPC8379E",
8489 CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300),
8490 /* e500 family */
8491 /* PowerPC e500 core */
8492 POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2),
8493 /* PowerPC e500v1 core */
8494 POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1),
8495 /* PowerPC e500 v1.0 core */
8496 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1),
8497 /* PowerPC e500 v2.0 core */
8498 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1),
8499 /* PowerPC e500v2 core */
8500 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2),
8501 /* PowerPC e500v2 v1.0 core */
8502 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2),
8503 /* PowerPC e500v2 v2.0 core */
8504 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2),
8505 /* PowerPC e500v2 v2.1 core */
8506 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2),
8507 /* PowerPC e500v2 v2.2 core */
8508 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2),
8509 /* PowerPC e500v2 v3.0 core */
8510 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
8511 POWERPC_DEF("e500mc", CPU_POWERPC_e500mc, e500mc),
8512 /* PowerPC e500 microcontrollers */
8513 /* MPC8533 */
8514 POWERPC_DEF_SVR("MPC8533",
8515 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2),
8516 /* MPC8533 v1.0 */
8517 POWERPC_DEF_SVR("MPC8533_v10",
8518 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2),
8519 /* MPC8533 v1.1 */
8520 POWERPC_DEF_SVR("MPC8533_v11",
8521 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2),
8522 /* MPC8533E */
8523 POWERPC_DEF_SVR("MPC8533E",
8524 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2),
8525 /* MPC8533E v1.0 */
8526 POWERPC_DEF_SVR("MPC8533E_v10",
8527 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
8528 POWERPC_DEF_SVR("MPC8533E_v11",
8529 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
8530 /* MPC8540 */
8531 POWERPC_DEF_SVR("MPC8540",
8532 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1),
8533 /* MPC8540 v1.0 */
8534 POWERPC_DEF_SVR("MPC8540_v10",
8535 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1),
8536 /* MPC8540 v2.0 */
8537 POWERPC_DEF_SVR("MPC8540_v20",
8538 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1),
8539 /* MPC8540 v2.1 */
8540 POWERPC_DEF_SVR("MPC8540_v21",
8541 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1),
8542 /* MPC8541 */
8543 POWERPC_DEF_SVR("MPC8541",
8544 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1),
8545 /* MPC8541 v1.0 */
8546 POWERPC_DEF_SVR("MPC8541_v10",
8547 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1),
8548 /* MPC8541 v1.1 */
8549 POWERPC_DEF_SVR("MPC8541_v11",
8550 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1),
8551 /* MPC8541E */
8552 POWERPC_DEF_SVR("MPC8541E",
8553 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1),
8554 /* MPC8541E v1.0 */
8555 POWERPC_DEF_SVR("MPC8541E_v10",
8556 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
8557 /* MPC8541E v1.1 */
8558 POWERPC_DEF_SVR("MPC8541E_v11",
8559 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
8560 /* MPC8543 */
8561 POWERPC_DEF_SVR("MPC8543",
8562 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2),
8563 /* MPC8543 v1.0 */
8564 POWERPC_DEF_SVR("MPC8543_v10",
8565 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2),
8566 /* MPC8543 v1.1 */
8567 POWERPC_DEF_SVR("MPC8543_v11",
8568 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2),
8569 /* MPC8543 v2.0 */
8570 POWERPC_DEF_SVR("MPC8543_v20",
8571 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2),
8572 /* MPC8543 v2.1 */
8573 POWERPC_DEF_SVR("MPC8543_v21",
8574 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2),
8575 /* MPC8543E */
8576 POWERPC_DEF_SVR("MPC8543E",
8577 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2),
8578 /* MPC8543E v1.0 */
8579 POWERPC_DEF_SVR("MPC8543E_v10",
8580 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
8581 /* MPC8543E v1.1 */
8582 POWERPC_DEF_SVR("MPC8543E_v11",
8583 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
8584 /* MPC8543E v2.0 */
8585 POWERPC_DEF_SVR("MPC8543E_v20",
8586 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
8587 /* MPC8543E v2.1 */
8588 POWERPC_DEF_SVR("MPC8543E_v21",
8589 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
8590 /* MPC8544 */
8591 POWERPC_DEF_SVR("MPC8544",
8592 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2),
8593 /* MPC8544 v1.0 */
8594 POWERPC_DEF_SVR("MPC8544_v10",
8595 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2),
8596 /* MPC8544 v1.1 */
8597 POWERPC_DEF_SVR("MPC8544_v11",
8598 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2),
8599 /* MPC8544E */
8600 POWERPC_DEF_SVR("MPC8544E",
8601 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2),
8602 /* MPC8544E v1.0 */
8603 POWERPC_DEF_SVR("MPC8544E_v10",
8604 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
8605 /* MPC8544E v1.1 */
8606 POWERPC_DEF_SVR("MPC8544E_v11",
8607 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
8608 /* MPC8545 */
8609 POWERPC_DEF_SVR("MPC8545",
8610 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2),
8611 /* MPC8545 v2.0 */
8612 POWERPC_DEF_SVR("MPC8545_v20",
8613 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2),
8614 /* MPC8545 v2.1 */
8615 POWERPC_DEF_SVR("MPC8545_v21",
8616 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2),
8617 /* MPC8545E */
8618 POWERPC_DEF_SVR("MPC8545E",
8619 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2),
8620 /* MPC8545E v2.0 */
8621 POWERPC_DEF_SVR("MPC8545E_v20",
8622 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
8623 /* MPC8545E v2.1 */
8624 POWERPC_DEF_SVR("MPC8545E_v21",
8625 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
8626 /* MPC8547E */
8627 POWERPC_DEF_SVR("MPC8547E",
8628 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2),
8629 /* MPC8547E v2.0 */
8630 POWERPC_DEF_SVR("MPC8547E_v20",
8631 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
8632 /* MPC8547E v2.1 */
8633 POWERPC_DEF_SVR("MPC8547E_v21",
8634 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
8635 /* MPC8548 */
8636 POWERPC_DEF_SVR("MPC8548",
8637 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2),
8638 /* MPC8548 v1.0 */
8639 POWERPC_DEF_SVR("MPC8548_v10",
8640 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2),
8641 /* MPC8548 v1.1 */
8642 POWERPC_DEF_SVR("MPC8548_v11",
8643 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2),
8644 /* MPC8548 v2.0 */
8645 POWERPC_DEF_SVR("MPC8548_v20",
8646 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2),
8647 /* MPC8548 v2.1 */
8648 POWERPC_DEF_SVR("MPC8548_v21",
8649 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2),
8650 /* MPC8548E */
8651 POWERPC_DEF_SVR("MPC8548E",
8652 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2),
8653 /* MPC8548E v1.0 */
8654 POWERPC_DEF_SVR("MPC8548E_v10",
8655 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
8656 /* MPC8548E v1.1 */
8657 POWERPC_DEF_SVR("MPC8548E_v11",
8658 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
8659 /* MPC8548E v2.0 */
8660 POWERPC_DEF_SVR("MPC8548E_v20",
8661 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
8662 /* MPC8548E v2.1 */
8663 POWERPC_DEF_SVR("MPC8548E_v21",
8664 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
8665 /* MPC8555 */
8666 POWERPC_DEF_SVR("MPC8555",
8667 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2),
8668 /* MPC8555 v1.0 */
8669 POWERPC_DEF_SVR("MPC8555_v10",
8670 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2),
8671 /* MPC8555 v1.1 */
8672 POWERPC_DEF_SVR("MPC8555_v11",
8673 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2),
8674 /* MPC8555E */
8675 POWERPC_DEF_SVR("MPC8555E",
8676 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2),
8677 /* MPC8555E v1.0 */
8678 POWERPC_DEF_SVR("MPC8555E_v10",
8679 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
8680 /* MPC8555E v1.1 */
8681 POWERPC_DEF_SVR("MPC8555E_v11",
8682 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
8683 /* MPC8560 */
8684 POWERPC_DEF_SVR("MPC8560",
8685 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2),
8686 /* MPC8560 v1.0 */
8687 POWERPC_DEF_SVR("MPC8560_v10",
8688 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2),
8689 /* MPC8560 v2.0 */
8690 POWERPC_DEF_SVR("MPC8560_v20",
8691 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2),
8692 /* MPC8560 v2.1 */
8693 POWERPC_DEF_SVR("MPC8560_v21",
8694 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2),
8695 /* MPC8567 */
8696 POWERPC_DEF_SVR("MPC8567",
8697 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2),
8698 /* MPC8567E */
8699 POWERPC_DEF_SVR("MPC8567E",
8700 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2),
8701 /* MPC8568 */
8702 POWERPC_DEF_SVR("MPC8568",
8703 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2),
8704 /* MPC8568E */
8705 POWERPC_DEF_SVR("MPC8568E",
8706 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2),
8707 /* MPC8572 */
8708 POWERPC_DEF_SVR("MPC8572",
8709 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2),
8710 /* MPC8572E */
8711 POWERPC_DEF_SVR("MPC8572E",
8712 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2),
8713 /* e600 family */
8714 /* PowerPC e600 core */
8715 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
8716 /* PowerPC e600 microcontrollers */
8717 #if defined (TODO)
8718 /* MPC8610 */
8719 POWERPC_DEF_SVR("MPC8610",
8720 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
8721 #endif
8722 /* MPC8641 */
8723 POWERPC_DEF_SVR("MPC8641",
8724 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
8725 /* MPC8641D */
8726 POWERPC_DEF_SVR("MPC8641D",
8727 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
8728 /* 32 bits "classic" PowerPC */
8729 /* PowerPC 6xx family */
8730 /* PowerPC 601 */
8731 POWERPC_DEF("601", CPU_POWERPC_601, 601v),
8732 /* PowerPC 601v0 */
8733 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
8734 /* PowerPC 601v1 */
8735 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
8736 /* PowerPC 601v */
8737 POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
8738 /* PowerPC 601v2 */
8739 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
8740 /* PowerPC 602 */
8741 POWERPC_DEF("602", CPU_POWERPC_602, 602),
8742 /* PowerPC 603 */
8743 POWERPC_DEF("603", CPU_POWERPC_603, 603),
8744 /* Code name for PowerPC 603 */
8745 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
8746 /* PowerPC 603e (aka PID6) */
8747 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
8748 /* Code name for PowerPC 603e */
8749 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
8750 /* PowerPC 603e v1.1 */
8751 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
8752 /* PowerPC 603e v1.2 */
8753 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
8754 /* PowerPC 603e v1.3 */
8755 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
8756 /* PowerPC 603e v1.4 */
8757 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
8758 /* PowerPC 603e v2.2 */
8759 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
8760 /* PowerPC 603e v3 */
8761 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
8762 /* PowerPC 603e v4 */
8763 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
8764 /* PowerPC 603e v4.1 */
8765 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
8766 /* PowerPC 603e (aka PID7) */
8767 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
8768 /* PowerPC 603e7t */
8769 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
8770 /* PowerPC 603e7v */
8771 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
8772 /* Code name for PowerPC 603ev */
8773 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
8774 /* PowerPC 603e7v1 */
8775 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
8776 /* PowerPC 603e7v2 */
8777 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
8778 /* PowerPC 603p (aka PID7v) */
8779 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
8780 /* PowerPC 603r (aka PID7t) */
8781 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
8782 /* Code name for PowerPC 603r */
8783 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
8784 /* PowerPC 604 */
8785 POWERPC_DEF("604", CPU_POWERPC_604, 604),
8786 /* PowerPC 604e (aka PID9) */
8787 POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
8788 /* Code name for PowerPC 604e */
8789 POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
8790 /* PowerPC 604e v1.0 */
8791 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
8792 /* PowerPC 604e v2.2 */
8793 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
8794 /* PowerPC 604e v2.4 */
8795 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
8796 /* PowerPC 604r (aka PIDA) */
8797 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
8798 /* Code name for PowerPC 604r */
8799 POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
8800 #if defined(TODO)
8801 /* PowerPC 604ev */
8802 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
8803 #endif
8804 /* PowerPC 7xx family */
8805 /* Generic PowerPC 740 (G3) */
8806 POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
8807 /* Code name for PowerPC 740 */
8808 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
8809 /* Generic PowerPC 750 (G3) */
8810 POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
8811 /* Code name for PowerPC 750 */
8812 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
8813 /* PowerPC 740/750 is also known as G3 */
8814 POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
8815 /* PowerPC 740 v1.0 (G3) */
8816 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
8817 /* PowerPC 750 v1.0 (G3) */
8818 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
8819 /* PowerPC 740 v2.0 (G3) */
8820 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
8821 /* PowerPC 750 v2.0 (G3) */
8822 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
8823 /* PowerPC 740 v2.1 (G3) */
8824 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
8825 /* PowerPC 750 v2.1 (G3) */
8826 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
8827 /* PowerPC 740 v2.2 (G3) */
8828 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
8829 /* PowerPC 750 v2.2 (G3) */
8830 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
8831 /* PowerPC 740 v3.0 (G3) */
8832 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
8833 /* PowerPC 750 v3.0 (G3) */
8834 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
8835 /* PowerPC 740 v3.1 (G3) */
8836 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
8837 /* PowerPC 750 v3.1 (G3) */
8838 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
8839 /* PowerPC 740E (G3) */
8840 POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
8841 /* PowerPC 750E (G3) */
8842 POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
8843 /* PowerPC 740P (G3) */
8844 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
8845 /* PowerPC 750P (G3) */
8846 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
8847 /* Code name for PowerPC 740P/750P (G3) */
8848 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
8849 /* PowerPC 750CL (G3 embedded) */
8850 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
8851 /* PowerPC 750CL v1.0 */
8852 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
8853 /* PowerPC 750CL v2.0 */
8854 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
8855 /* PowerPC 750CX (G3 embedded) */
8856 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
8857 /* PowerPC 750CX v1.0 (G3 embedded) */
8858 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
8859 /* PowerPC 750CX v2.1 (G3 embedded) */
8860 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
8861 /* PowerPC 750CX v2.1 (G3 embedded) */
8862 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
8863 /* PowerPC 750CX v2.2 (G3 embedded) */
8864 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
8865 /* PowerPC 750CXe (G3 embedded) */
8866 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
8867 /* PowerPC 750CXe v2.1 (G3 embedded) */
8868 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
8869 /* PowerPC 750CXe v2.2 (G3 embedded) */
8870 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
8871 /* PowerPC 750CXe v2.3 (G3 embedded) */
8872 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
8873 /* PowerPC 750CXe v2.4 (G3 embedded) */
8874 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
8875 /* PowerPC 750CXe v2.4b (G3 embedded) */
8876 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
8877 /* PowerPC 750CXe v3.0 (G3 embedded) */
8878 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
8879 /* PowerPC 750CXe v3.1 (G3 embedded) */
8880 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
8881 /* PowerPC 750CXe v3.1b (G3 embedded) */
8882 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
8883 /* PowerPC 750CXr (G3 embedded) */
8884 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
8885 /* PowerPC 750FL (G3 embedded) */
8886 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
8887 /* PowerPC 750FX (G3 embedded) */
8888 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
8889 /* PowerPC 750FX v1.0 (G3 embedded) */
8890 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
8891 /* PowerPC 750FX v2.0 (G3 embedded) */
8892 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
8893 /* PowerPC 750FX v2.1 (G3 embedded) */
8894 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
8895 /* PowerPC 750FX v2.2 (G3 embedded) */
8896 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
8897 /* PowerPC 750FX v2.3 (G3 embedded) */
8898 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
8899 /* PowerPC 750GL (G3 embedded) */
8900 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
8901 /* PowerPC 750GX (G3 embedded) */
8902 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
8903 /* PowerPC 750GX v1.0 (G3 embedded) */
8904 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
8905 /* PowerPC 750GX v1.1 (G3 embedded) */
8906 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
8907 /* PowerPC 750GX v1.2 (G3 embedded) */
8908 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
8909 /* PowerPC 750L (G3 embedded) */
8910 POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
8911 /* Code name for PowerPC 750L (G3 embedded) */
8912 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
8913 /* PowerPC 750L v2.0 (G3 embedded) */
8914 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
8915 /* PowerPC 750L v2.1 (G3 embedded) */
8916 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
8917 /* PowerPC 750L v2.2 (G3 embedded) */
8918 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
8919 /* PowerPC 750L v3.0 (G3 embedded) */
8920 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
8921 /* PowerPC 750L v3.2 (G3 embedded) */
8922 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
8923 /* Generic PowerPC 745 */
8924 POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
8925 /* Generic PowerPC 755 */
8926 POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
8927 /* Code name for PowerPC 745/755 */
8928 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
8929 /* PowerPC 745 v1.0 */
8930 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
8931 /* PowerPC 755 v1.0 */
8932 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
8933 /* PowerPC 745 v1.1 */
8934 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
8935 /* PowerPC 755 v1.1 */
8936 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
8937 /* PowerPC 745 v2.0 */
8938 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
8939 /* PowerPC 755 v2.0 */
8940 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
8941 /* PowerPC 745 v2.1 */
8942 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
8943 /* PowerPC 755 v2.1 */
8944 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
8945 /* PowerPC 745 v2.2 */
8946 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
8947 /* PowerPC 755 v2.2 */
8948 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
8949 /* PowerPC 745 v2.3 */
8950 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
8951 /* PowerPC 755 v2.3 */
8952 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
8953 /* PowerPC 745 v2.4 */
8954 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
8955 /* PowerPC 755 v2.4 */
8956 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
8957 /* PowerPC 745 v2.5 */
8958 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
8959 /* PowerPC 755 v2.5 */
8960 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
8961 /* PowerPC 745 v2.6 */
8962 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
8963 /* PowerPC 755 v2.6 */
8964 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
8965 /* PowerPC 745 v2.7 */
8966 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
8967 /* PowerPC 755 v2.7 */
8968 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
8969 /* PowerPC 745 v2.8 */
8970 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
8971 /* PowerPC 755 v2.8 */
8972 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
8973 #if defined (TODO)
8974 /* PowerPC 745P (G3) */
8975 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
8976 /* PowerPC 755P (G3) */
8977 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
8978 #endif
8979 /* PowerPC 74xx family */
8980 /* PowerPC 7400 (G4) */
8981 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
8982 /* Code name for PowerPC 7400 */
8983 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
8984 /* PowerPC 74xx is also well known as G4 */
8985 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
8986 /* PowerPC 7400 v1.0 (G4) */
8987 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
8988 /* PowerPC 7400 v1.1 (G4) */
8989 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
8990 /* PowerPC 7400 v2.0 (G4) */
8991 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
8992 /* PowerPC 7400 v2.1 (G4) */
8993 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
8994 /* PowerPC 7400 v2.2 (G4) */
8995 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
8996 /* PowerPC 7400 v2.6 (G4) */
8997 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
8998 /* PowerPC 7400 v2.7 (G4) */
8999 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
9000 /* PowerPC 7400 v2.8 (G4) */
9001 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
9002 /* PowerPC 7400 v2.9 (G4) */
9003 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
9004 /* PowerPC 7410 (G4) */
9005 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
9006 /* Code name for PowerPC 7410 */
9007 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
9008 /* PowerPC 7410 v1.0 (G4) */
9009 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
9010 /* PowerPC 7410 v1.1 (G4) */
9011 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
9012 /* PowerPC 7410 v1.2 (G4) */
9013 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
9014 /* PowerPC 7410 v1.3 (G4) */
9015 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
9016 /* PowerPC 7410 v1.4 (G4) */
9017 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
9018 /* PowerPC 7448 (G4) */
9019 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
9020 /* PowerPC 7448 v1.0 (G4) */
9021 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
9022 /* PowerPC 7448 v1.1 (G4) */
9023 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
9024 /* PowerPC 7448 v2.0 (G4) */
9025 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
9026 /* PowerPC 7448 v2.1 (G4) */
9027 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
9028 /* PowerPC 7450 (G4) */
9029 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
9030 /* Code name for PowerPC 7450 */
9031 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
9032 /* PowerPC 7450 v1.0 (G4) */
9033 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
9034 /* PowerPC 7450 v1.1 (G4) */
9035 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
9036 /* PowerPC 7450 v1.2 (G4) */
9037 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
9038 /* PowerPC 7450 v2.0 (G4) */
9039 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
9040 /* PowerPC 7450 v2.1 (G4) */
9041 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
9042 /* PowerPC 7441 (G4) */
9043 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
9044 /* PowerPC 7451 (G4) */
9045 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
9046 /* PowerPC 7441 v2.1 (G4) */
9047 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
9048 /* PowerPC 7441 v2.3 (G4) */
9049 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
9050 /* PowerPC 7451 v2.3 (G4) */
9051 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
9052 /* PowerPC 7441 v2.10 (G4) */
9053 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
9054 /* PowerPC 7451 v2.10 (G4) */
9055 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
9056 /* PowerPC 7445 (G4) */
9057 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
9058 /* PowerPC 7455 (G4) */
9059 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
9060 /* Code name for PowerPC 7445/7455 */
9061 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
9062 /* PowerPC 7445 v1.0 (G4) */
9063 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
9064 /* PowerPC 7455 v1.0 (G4) */
9065 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
9066 /* PowerPC 7445 v2.1 (G4) */
9067 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
9068 /* PowerPC 7455 v2.1 (G4) */
9069 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
9070 /* PowerPC 7445 v3.2 (G4) */
9071 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
9072 /* PowerPC 7455 v3.2 (G4) */
9073 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
9074 /* PowerPC 7445 v3.3 (G4) */
9075 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
9076 /* PowerPC 7455 v3.3 (G4) */
9077 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
9078 /* PowerPC 7445 v3.4 (G4) */
9079 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
9080 /* PowerPC 7455 v3.4 (G4) */
9081 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
9082 /* PowerPC 7447 (G4) */
9083 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
9084 /* PowerPC 7457 (G4) */
9085 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
9086 /* Code name for PowerPC 7447/7457 */
9087 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
9088 /* PowerPC 7447 v1.0 (G4) */
9089 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
9090 /* PowerPC 7457 v1.0 (G4) */
9091 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
9092 /* PowerPC 7447 v1.1 (G4) */
9093 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
9094 /* PowerPC 7457 v1.1 (G4) */
9095 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
9096 /* PowerPC 7457 v1.2 (G4) */
9097 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
9098 /* PowerPC 7447A (G4) */
9099 POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
9100 /* PowerPC 7457A (G4) */
9101 POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
9102 /* PowerPC 7447A v1.0 (G4) */
9103 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
9104 /* PowerPC 7457A v1.0 (G4) */
9105 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
9106 /* Code name for PowerPC 7447A/7457A */
9107 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
9108 /* PowerPC 7447A v1.1 (G4) */
9109 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
9110 /* PowerPC 7457A v1.1 (G4) */
9111 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
9112 /* PowerPC 7447A v1.2 (G4) */
9113 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
9114 /* PowerPC 7457A v1.2 (G4) */
9115 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
9116 /* 64 bits PowerPC */
9117 #if defined (TARGET_PPC64)
9118 /* PowerPC 620 */
9119 POWERPC_DEF("620", CPU_POWERPC_620, 620),
9120 /* Code name for PowerPC 620 */
9121 POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
9122 #if defined (TODO)
9123 /* PowerPC 630 (POWER3) */
9124 POWERPC_DEF("630", CPU_POWERPC_630, 630),
9125 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
9126 /* Code names for POWER3 */
9127 POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
9128 POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
9129 #endif
9130 #if defined (TODO)
9131 /* PowerPC 631 (Power 3+) */
9132 POWERPC_DEF("631", CPU_POWERPC_631, 631),
9133 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
9134 #endif
9135 #if defined (TODO)
9136 /* POWER4 */
9137 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
9138 #endif
9139 #if defined (TODO)
9140 /* POWER4p */
9141 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
9142 #endif
9143 #if defined (TODO)
9144 /* POWER5 */
9145 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
9146 /* POWER5GR */
9147 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
9148 #endif
9149 #if defined (TODO)
9150 /* POWER5+ */
9151 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
9152 /* POWER5GS */
9153 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
9154 #endif
9155 #if defined (TODO)
9156 /* POWER6 */
9157 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
9158 /* POWER6 running in POWER5 mode */
9159 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
9160 /* POWER6A */
9161 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
9162 #endif
9163 /* POWER7 */
9164 POWERPC_DEF("POWER7", CPU_POWERPC_POWER7, POWER7),
9165 POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7),
9166 POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21, POWER7),
9167 POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7),
9168 /* PowerPC 970 */
9169 POWERPC_DEF("970", CPU_POWERPC_970, 970),
9170 /* PowerPC 970FX (G5) */
9171 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
9172 /* PowerPC 970FX v1.0 (G5) */
9173 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
9174 /* PowerPC 970FX v2.0 (G5) */
9175 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
9176 /* PowerPC 970FX v2.1 (G5) */
9177 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
9178 /* PowerPC 970FX v3.0 (G5) */
9179 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
9180 /* PowerPC 970FX v3.1 (G5) */
9181 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
9182 /* PowerPC 970GX (G5) */
9183 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
9184 /* PowerPC 970MP */
9185 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
9186 /* PowerPC 970MP v1.0 */
9187 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
9188 /* PowerPC 970MP v1.1 */
9189 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
9190 #if defined (TODO)
9191 /* PowerPC Cell */
9192 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
9193 #endif
9194 #if defined (TODO)
9195 /* PowerPC Cell v1.0 */
9196 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
9197 #endif
9198 #if defined (TODO)
9199 /* PowerPC Cell v2.0 */
9200 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
9201 #endif
9202 #if defined (TODO)
9203 /* PowerPC Cell v3.0 */
9204 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
9205 #endif
9206 #if defined (TODO)
9207 /* PowerPC Cell v3.1 */
9208 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
9209 #endif
9210 #if defined (TODO)
9211 /* PowerPC Cell v3.2 */
9212 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
9213 #endif
9214 #if defined (TODO)
9215 /* RS64 (Apache/A35) */
9216 /* This one seems to support the whole POWER2 instruction set
9217 * and the PowerPC 64 one.
9218 */
9219 /* What about A10 & A30 ? */
9220 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
9221 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
9222 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
9223 #endif
9224 #if defined (TODO)
9225 /* RS64-II (NorthStar/A50) */
9226 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
9227 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
9228 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
9229 #endif
9230 #if defined (TODO)
9231 /* RS64-III (Pulsar) */
9232 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
9233 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
9234 #endif
9235 #if defined (TODO)
9236 /* RS64-IV (IceStar/IStar/SStar) */
9237 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
9238 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
9239 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
9240 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
9241 #endif
9242 #endif /* defined (TARGET_PPC64) */
9243 /* POWER */
9244 #if defined (TODO)
9245 /* Original POWER */
9246 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
9247 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
9248 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
9249 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
9250 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
9251 #endif
9252 #if defined (TODO)
9253 /* POWER2 */
9254 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
9255 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
9256 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
9257 #endif
9258 /* PA semi cores */
9259 #if defined (TODO)
9260 /* PA PA6T */
9261 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
9262 #endif
9263 /* Generic PowerPCs */
9264 #if defined (TARGET_PPC64)
9265 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
9266 #endif
9267 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
9268 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
9269 /* Fallback */
9270 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
9271 };
9272
9273 /*****************************************************************************/
9274 /* Generic CPU instantiation routine */
9275 static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
9276 {
9277 #if !defined(CONFIG_USER_ONLY)
9278 int i;
9279
9280 env->irq_inputs = NULL;
9281 /* Set all exception vectors to an invalid address */
9282 for (i = 0; i < POWERPC_EXCP_NB; i++)
9283 env->excp_vectors[i] = (target_ulong)(-1ULL);
9284 env->hreset_excp_prefix = 0x00000000;
9285 env->ivor_mask = 0x00000000;
9286 env->ivpr_mask = 0x00000000;
9287 /* Default MMU definitions */
9288 env->nb_BATs = 0;
9289 env->nb_tlb = 0;
9290 env->nb_ways = 0;
9291 env->tlb_type = TLB_NONE;
9292 #endif
9293 /* Register SPR common to all PowerPC implementations */
9294 gen_spr_generic(env);
9295 spr_register(env, SPR_PVR, "PVR",
9296 /* Linux permits userspace to read PVR */
9297 #if defined(CONFIG_LINUX_USER)
9298 &spr_read_generic,
9299 #else
9300 SPR_NOACCESS,
9301 #endif
9302 SPR_NOACCESS,
9303 &spr_read_generic, SPR_NOACCESS,
9304 def->pvr);
9305 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
9306 if (def->svr != POWERPC_SVR_NONE) {
9307 if (def->svr & POWERPC_SVR_E500) {
9308 spr_register(env, SPR_E500_SVR, "SVR",
9309 SPR_NOACCESS, SPR_NOACCESS,
9310 &spr_read_generic, SPR_NOACCESS,
9311 def->svr & ~POWERPC_SVR_E500);
9312 } else {
9313 spr_register(env, SPR_SVR, "SVR",
9314 SPR_NOACCESS, SPR_NOACCESS,
9315 &spr_read_generic, SPR_NOACCESS,
9316 def->svr);
9317 }
9318 }
9319 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
9320 (*def->init_proc)(env);
9321 #if !defined(CONFIG_USER_ONLY)
9322 env->excp_prefix = env->hreset_excp_prefix;
9323 #endif
9324 /* MSR bits & flags consistency checks */
9325 if (env->msr_mask & (1 << 25)) {
9326 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9327 case POWERPC_FLAG_SPE:
9328 case POWERPC_FLAG_VRE:
9329 break;
9330 default:
9331 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9332 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9333 exit(1);
9334 }
9335 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9336 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9337 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9338 exit(1);
9339 }
9340 if (env->msr_mask & (1 << 17)) {
9341 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9342 case POWERPC_FLAG_TGPR:
9343 case POWERPC_FLAG_CE:
9344 break;
9345 default:
9346 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9347 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9348 exit(1);
9349 }
9350 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9351 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9352 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9353 exit(1);
9354 }
9355 if (env->msr_mask & (1 << 10)) {
9356 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9357 POWERPC_FLAG_UBLE)) {
9358 case POWERPC_FLAG_SE:
9359 case POWERPC_FLAG_DWE:
9360 case POWERPC_FLAG_UBLE:
9361 break;
9362 default:
9363 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9364 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9365 "POWERPC_FLAG_UBLE\n");
9366 exit(1);
9367 }
9368 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9369 POWERPC_FLAG_UBLE)) {
9370 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9371 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9372 "POWERPC_FLAG_UBLE\n");
9373 exit(1);
9374 }
9375 if (env->msr_mask & (1 << 9)) {
9376 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9377 case POWERPC_FLAG_BE:
9378 case POWERPC_FLAG_DE:
9379 break;
9380 default:
9381 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9382 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9383 exit(1);
9384 }
9385 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9386 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9387 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9388 exit(1);
9389 }
9390 if (env->msr_mask & (1 << 2)) {
9391 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9392 case POWERPC_FLAG_PX:
9393 case POWERPC_FLAG_PMM:
9394 break;
9395 default:
9396 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9397 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9398 exit(1);
9399 }
9400 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9401 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9402 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9403 exit(1);
9404 }
9405 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9406 fprintf(stderr, "PowerPC flags inconsistency\n"
9407 "Should define the time-base and decrementer clock source\n");
9408 exit(1);
9409 }
9410 /* Allocate TLBs buffer when needed */
9411 #if !defined(CONFIG_USER_ONLY)
9412 if (env->nb_tlb != 0) {
9413 int nb_tlb = env->nb_tlb;
9414 if (env->id_tlbs != 0)
9415 nb_tlb *= 2;
9416 switch (env->tlb_type) {
9417 case TLB_6XX:
9418 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
9419 break;
9420 case TLB_EMB:
9421 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
9422 break;
9423 case TLB_MAS:
9424 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
9425 break;
9426 }
9427 /* Pre-compute some useful values */
9428 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9429 }
9430 if (env->irq_inputs == NULL) {
9431 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
9432 " Attempt Qemu to crash very soon !\n");
9433 }
9434 #endif
9435 if (env->check_pow == NULL) {
9436 fprintf(stderr, "WARNING: no power management check handler "
9437 "registered.\n"
9438 " Attempt Qemu to crash very soon !\n");
9439 }
9440 }
9441
9442 #if defined(PPC_DUMP_CPU)
9443 static void dump_ppc_sprs (CPUPPCState *env)
9444 {
9445 ppc_spr_t *spr;
9446 #if !defined(CONFIG_USER_ONLY)
9447 uint32_t sr, sw;
9448 #endif
9449 uint32_t ur, uw;
9450 int i, j, n;
9451
9452 printf("Special purpose registers:\n");
9453 for (i = 0; i < 32; i++) {
9454 for (j = 0; j < 32; j++) {
9455 n = (i << 5) | j;
9456 spr = &env->spr_cb[n];
9457 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9458 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9459 #if !defined(CONFIG_USER_ONLY)
9460 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9461 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9462 if (sw || sr || uw || ur) {
9463 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9464 (i << 5) | j, (i << 5) | j, spr->name,
9465 sw ? 'w' : '-', sr ? 'r' : '-',
9466 uw ? 'w' : '-', ur ? 'r' : '-');
9467 }
9468 #else
9469 if (uw || ur) {
9470 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9471 (i << 5) | j, (i << 5) | j, spr->name,
9472 uw ? 'w' : '-', ur ? 'r' : '-');
9473 }
9474 #endif
9475 }
9476 }
9477 fflush(stdout);
9478 fflush(stderr);
9479 }
9480 #endif
9481
9482 /*****************************************************************************/
9483 #include <stdlib.h>
9484 #include <string.h>
9485
9486 /* Opcode types */
9487 enum {
9488 PPC_DIRECT = 0, /* Opcode routine */
9489 PPC_INDIRECT = 1, /* Indirect opcode table */
9490 };
9491
9492 static inline int is_indirect_opcode (void *handler)
9493 {
9494 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
9495 }
9496
9497 static inline opc_handler_t **ind_table(void *handler)
9498 {
9499 return (opc_handler_t **)((unsigned long)handler & ~3);
9500 }
9501
9502 /* Instruction table creation */
9503 /* Opcodes tables creation */
9504 static void fill_new_table (opc_handler_t **table, int len)
9505 {
9506 int i;
9507
9508 for (i = 0; i < len; i++)
9509 table[i] = &invalid_handler;
9510 }
9511
9512 static int create_new_table (opc_handler_t **table, unsigned char idx)
9513 {
9514 opc_handler_t **tmp;
9515
9516 tmp = malloc(0x20 * sizeof(opc_handler_t));
9517 fill_new_table(tmp, 0x20);
9518 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
9519
9520 return 0;
9521 }
9522
9523 static int insert_in_table (opc_handler_t **table, unsigned char idx,
9524 opc_handler_t *handler)
9525 {
9526 if (table[idx] != &invalid_handler)
9527 return -1;
9528 table[idx] = handler;
9529
9530 return 0;
9531 }
9532
9533 static int register_direct_insn (opc_handler_t **ppc_opcodes,
9534 unsigned char idx, opc_handler_t *handler)
9535 {
9536 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9537 printf("*** ERROR: opcode %02x already assigned in main "
9538 "opcode table\n", idx);
9539 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9540 printf(" Registered handler '%s' - new handler '%s'\n",
9541 ppc_opcodes[idx]->oname, handler->oname);
9542 #endif
9543 return -1;
9544 }
9545
9546 return 0;
9547 }
9548
9549 static int register_ind_in_table (opc_handler_t **table,
9550 unsigned char idx1, unsigned char idx2,
9551 opc_handler_t *handler)
9552 {
9553 if (table[idx1] == &invalid_handler) {
9554 if (create_new_table(table, idx1) < 0) {
9555 printf("*** ERROR: unable to create indirect table "
9556 "idx=%02x\n", idx1);
9557 return -1;
9558 }
9559 } else {
9560 if (!is_indirect_opcode(table[idx1])) {
9561 printf("*** ERROR: idx %02x already assigned to a direct "
9562 "opcode\n", idx1);
9563 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9564 printf(" Registered handler '%s' - new handler '%s'\n",
9565 ind_table(table[idx1])[idx2]->oname, handler->oname);
9566 #endif
9567 return -1;
9568 }
9569 }
9570 if (handler != NULL &&
9571 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9572 printf("*** ERROR: opcode %02x already assigned in "
9573 "opcode table %02x\n", idx2, idx1);
9574 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9575 printf(" Registered handler '%s' - new handler '%s'\n",
9576 ind_table(table[idx1])[idx2]->oname, handler->oname);
9577 #endif
9578 return -1;
9579 }
9580
9581 return 0;
9582 }
9583
9584 static int register_ind_insn (opc_handler_t **ppc_opcodes,
9585 unsigned char idx1, unsigned char idx2,
9586 opc_handler_t *handler)
9587 {
9588 int ret;
9589
9590 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9591
9592 return ret;
9593 }
9594
9595 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
9596 unsigned char idx1, unsigned char idx2,
9597 unsigned char idx3, opc_handler_t *handler)
9598 {
9599 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9600 printf("*** ERROR: unable to join indirect table idx "
9601 "[%02x-%02x]\n", idx1, idx2);
9602 return -1;
9603 }
9604 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9605 handler) < 0) {
9606 printf("*** ERROR: unable to insert opcode "
9607 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9608 return -1;
9609 }
9610
9611 return 0;
9612 }
9613
9614 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
9615 {
9616 if (insn->opc2 != 0xFF) {
9617 if (insn->opc3 != 0xFF) {
9618 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9619 insn->opc3, &insn->handler) < 0)
9620 return -1;
9621 } else {
9622 if (register_ind_insn(ppc_opcodes, insn->opc1,
9623 insn->opc2, &insn->handler) < 0)
9624 return -1;
9625 }
9626 } else {
9627 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9628 return -1;
9629 }
9630
9631 return 0;
9632 }
9633
9634 static int test_opcode_table (opc_handler_t **table, int len)
9635 {
9636 int i, count, tmp;
9637
9638 for (i = 0, count = 0; i < len; i++) {
9639 /* Consistency fixup */
9640 if (table[i] == NULL)
9641 table[i] = &invalid_handler;
9642 if (table[i] != &invalid_handler) {
9643 if (is_indirect_opcode(table[i])) {
9644 tmp = test_opcode_table(ind_table(table[i]), 0x20);
9645 if (tmp == 0) {
9646 free(table[i]);
9647 table[i] = &invalid_handler;
9648 } else {
9649 count++;
9650 }
9651 } else {
9652 count++;
9653 }
9654 }
9655 }
9656
9657 return count;
9658 }
9659
9660 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
9661 {
9662 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9663 printf("*** WARNING: no opcode defined !\n");
9664 }
9665
9666 /*****************************************************************************/
9667 static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
9668 {
9669 opcode_t *opc;
9670
9671 fill_new_table(env->opcodes, 0x40);
9672 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
9673 if (((opc->handler.type & def->insns_flags) != 0) ||
9674 ((opc->handler.type2 & def->insns_flags2) != 0)) {
9675 if (register_insn(env->opcodes, opc) < 0) {
9676 printf("*** ERROR initializing PowerPC instruction "
9677 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9678 opc->opc3);
9679 return -1;
9680 }
9681 }
9682 }
9683 fix_opcode_tables(env->opcodes);
9684 fflush(stdout);
9685 fflush(stderr);
9686
9687 return 0;
9688 }
9689
9690 #if defined(PPC_DUMP_CPU)
9691 static void dump_ppc_insns (CPUPPCState *env)
9692 {
9693 opc_handler_t **table, *handler;
9694 const char *p, *q;
9695 uint8_t opc1, opc2, opc3;
9696
9697 printf("Instructions set:\n");
9698 /* opc1 is 6 bits long */
9699 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9700 table = env->opcodes;
9701 handler = table[opc1];
9702 if (is_indirect_opcode(handler)) {
9703 /* opc2 is 5 bits long */
9704 for (opc2 = 0; opc2 < 0x20; opc2++) {
9705 table = env->opcodes;
9706 handler = env->opcodes[opc1];
9707 table = ind_table(handler);
9708 handler = table[opc2];
9709 if (is_indirect_opcode(handler)) {
9710 table = ind_table(handler);
9711 /* opc3 is 5 bits long */
9712 for (opc3 = 0; opc3 < 0x20; opc3++) {
9713 handler = table[opc3];
9714 if (handler->handler != &gen_invalid) {
9715 /* Special hack to properly dump SPE insns */
9716 p = strchr(handler->oname, '_');
9717 if (p == NULL) {
9718 printf("INSN: %02x %02x %02x (%02d %04d) : "
9719 "%s\n",
9720 opc1, opc2, opc3, opc1,
9721 (opc3 << 5) | opc2,
9722 handler->oname);
9723 } else {
9724 q = "speundef";
9725 if ((p - handler->oname) != strlen(q) ||
9726 memcmp(handler->oname, q, strlen(q)) != 0) {
9727 /* First instruction */
9728 printf("INSN: %02x %02x %02x (%02d %04d) : "
9729 "%.*s\n",
9730 opc1, opc2 << 1, opc3, opc1,
9731 (opc3 << 6) | (opc2 << 1),
9732 (int)(p - handler->oname),
9733 handler->oname);
9734 }
9735 if (strcmp(p + 1, q) != 0) {
9736 /* Second instruction */
9737 printf("INSN: %02x %02x %02x (%02d %04d) : "
9738 "%s\n",
9739 opc1, (opc2 << 1) | 1, opc3, opc1,
9740 (opc3 << 6) | (opc2 << 1) | 1,
9741 p + 1);
9742 }
9743 }
9744 }
9745 }
9746 } else {
9747 if (handler->handler != &gen_invalid) {
9748 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9749 opc1, opc2, opc1, opc2, handler->oname);
9750 }
9751 }
9752 }
9753 } else {
9754 if (handler->handler != &gen_invalid) {
9755 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9756 opc1, opc1, handler->oname);
9757 }
9758 }
9759 }
9760 }
9761 #endif
9762
9763 static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9764 {
9765 if (n < 32) {
9766 stfq_p(mem_buf, env->fpr[n]);
9767 return 8;
9768 }
9769 if (n == 32) {
9770 stl_p(mem_buf, env->fpscr);
9771 return 4;
9772 }
9773 return 0;
9774 }
9775
9776 static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9777 {
9778 if (n < 32) {
9779 env->fpr[n] = ldfq_p(mem_buf);
9780 return 8;
9781 }
9782 if (n == 32) {
9783 /* FPSCR not implemented */
9784 return 4;
9785 }
9786 return 0;
9787 }
9788
9789 static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9790 {
9791 if (n < 32) {
9792 #ifdef HOST_WORDS_BIGENDIAN
9793 stq_p(mem_buf, env->avr[n].u64[0]);
9794 stq_p(mem_buf+8, env->avr[n].u64[1]);
9795 #else
9796 stq_p(mem_buf, env->avr[n].u64[1]);
9797 stq_p(mem_buf+8, env->avr[n].u64[0]);
9798 #endif
9799 return 16;
9800 }
9801 if (n == 32) {
9802 stl_p(mem_buf, env->vscr);
9803 return 4;
9804 }
9805 if (n == 33) {
9806 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9807 return 4;
9808 }
9809 return 0;
9810 }
9811
9812 static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9813 {
9814 if (n < 32) {
9815 #ifdef HOST_WORDS_BIGENDIAN
9816 env->avr[n].u64[0] = ldq_p(mem_buf);
9817 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9818 #else
9819 env->avr[n].u64[1] = ldq_p(mem_buf);
9820 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9821 #endif
9822 return 16;
9823 }
9824 if (n == 32) {
9825 env->vscr = ldl_p(mem_buf);
9826 return 4;
9827 }
9828 if (n == 33) {
9829 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9830 return 4;
9831 }
9832 return 0;
9833 }
9834
9835 static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9836 {
9837 if (n < 32) {
9838 #if defined(TARGET_PPC64)
9839 stl_p(mem_buf, env->gpr[n] >> 32);
9840 #else
9841 stl_p(mem_buf, env->gprh[n]);
9842 #endif
9843 return 4;
9844 }
9845 if (n == 32) {
9846 stq_p(mem_buf, env->spe_acc);
9847 return 8;
9848 }
9849 if (n == 33) {
9850 stl_p(mem_buf, env->spe_fscr);
9851 return 4;
9852 }
9853 return 0;
9854 }
9855
9856 static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9857 {
9858 if (n < 32) {
9859 #if defined(TARGET_PPC64)
9860 target_ulong lo = (uint32_t)env->gpr[n];
9861 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9862 env->gpr[n] = lo | hi;
9863 #else
9864 env->gprh[n] = ldl_p(mem_buf);
9865 #endif
9866 return 4;
9867 }
9868 if (n == 32) {
9869 env->spe_acc = ldq_p(mem_buf);
9870 return 8;
9871 }
9872 if (n == 33) {
9873 env->spe_fscr = ldl_p(mem_buf);
9874 return 4;
9875 }
9876 return 0;
9877 }
9878
9879 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
9880 {
9881 env->msr_mask = def->msr_mask;
9882 env->mmu_model = def->mmu_model;
9883 env->excp_model = def->excp_model;
9884 env->bus_model = def->bus_model;
9885 env->insns_flags = def->insns_flags;
9886 env->insns_flags2 = def->insns_flags2;
9887 if (!kvm_enabled()) {
9888 /* TCG doesn't (yet) emulate some groups of instructions that
9889 * are implemented on some otherwise supported CPUs (e.g. VSX
9890 * and decimal floating point instructions on POWER7). We
9891 * remove unsupported instruction groups from the cpu state's
9892 * instruction masks and hope the guest can cope. For at
9893 * least the pseries machine, the unavailability of these
9894 * instructions can be advertise to the guest via the device
9895 * tree.
9896 *
9897 * FIXME: we should have a similar masking for CPU features
9898 * not accessible under KVM, but so far, there aren't any of
9899 * those. */
9900 env->insns_flags &= PPC_TCG_INSNS;
9901 env->insns_flags2 &= PPC_TCG_INSNS2;
9902 }
9903 env->flags = def->flags;
9904 env->bfd_mach = def->bfd_mach;
9905 env->check_pow = def->check_pow;
9906 if (create_ppc_opcodes(env, def) < 0)
9907 return -1;
9908 init_ppc_proc(env, def);
9909
9910 if (def->insns_flags & PPC_FLOAT) {
9911 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9912 33, "power-fpu.xml", 0);
9913 }
9914 if (def->insns_flags & PPC_ALTIVEC) {
9915 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9916 34, "power-altivec.xml", 0);
9917 }
9918 if (def->insns_flags & PPC_SPE) {
9919 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
9920 34, "power-spe.xml", 0);
9921 }
9922
9923 #if defined(PPC_DUMP_CPU)
9924 {
9925 const char *mmu_model, *excp_model, *bus_model;
9926 switch (env->mmu_model) {
9927 case POWERPC_MMU_32B:
9928 mmu_model = "PowerPC 32";
9929 break;
9930 case POWERPC_MMU_SOFT_6xx:
9931 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9932 break;
9933 case POWERPC_MMU_SOFT_74xx:
9934 mmu_model = "PowerPC 74xx with software driven TLBs";
9935 break;
9936 case POWERPC_MMU_SOFT_4xx:
9937 mmu_model = "PowerPC 4xx with software driven TLBs";
9938 break;
9939 case POWERPC_MMU_SOFT_4xx_Z:
9940 mmu_model = "PowerPC 4xx with software driven TLBs "
9941 "and zones protections";
9942 break;
9943 case POWERPC_MMU_REAL:
9944 mmu_model = "PowerPC real mode only";
9945 break;
9946 case POWERPC_MMU_MPC8xx:
9947 mmu_model = "PowerPC MPC8xx";
9948 break;
9949 case POWERPC_MMU_BOOKE:
9950 mmu_model = "PowerPC BookE";
9951 break;
9952 case POWERPC_MMU_BOOKE206:
9953 mmu_model = "PowerPC BookE 2.06";
9954 break;
9955 case POWERPC_MMU_601:
9956 mmu_model = "PowerPC 601";
9957 break;
9958 #if defined (TARGET_PPC64)
9959 case POWERPC_MMU_64B:
9960 mmu_model = "PowerPC 64";
9961 break;
9962 case POWERPC_MMU_620:
9963 mmu_model = "PowerPC 620";
9964 break;
9965 #endif
9966 default:
9967 mmu_model = "Unknown or invalid";
9968 break;
9969 }
9970 switch (env->excp_model) {
9971 case POWERPC_EXCP_STD:
9972 excp_model = "PowerPC";
9973 break;
9974 case POWERPC_EXCP_40x:
9975 excp_model = "PowerPC 40x";
9976 break;
9977 case POWERPC_EXCP_601:
9978 excp_model = "PowerPC 601";
9979 break;
9980 case POWERPC_EXCP_602:
9981 excp_model = "PowerPC 602";
9982 break;
9983 case POWERPC_EXCP_603:
9984 excp_model = "PowerPC 603";
9985 break;
9986 case POWERPC_EXCP_603E:
9987 excp_model = "PowerPC 603e";
9988 break;
9989 case POWERPC_EXCP_604:
9990 excp_model = "PowerPC 604";
9991 break;
9992 case POWERPC_EXCP_7x0:
9993 excp_model = "PowerPC 740/750";
9994 break;
9995 case POWERPC_EXCP_7x5:
9996 excp_model = "PowerPC 745/755";
9997 break;
9998 case POWERPC_EXCP_74xx:
9999 excp_model = "PowerPC 74xx";
10000 break;
10001 case POWERPC_EXCP_BOOKE:
10002 excp_model = "PowerPC BookE";
10003 break;
10004 #if defined (TARGET_PPC64)
10005 case POWERPC_EXCP_970:
10006 excp_model = "PowerPC 970";
10007 break;
10008 #endif
10009 default:
10010 excp_model = "Unknown or invalid";
10011 break;
10012 }
10013 switch (env->bus_model) {
10014 case PPC_FLAGS_INPUT_6xx:
10015 bus_model = "PowerPC 6xx";
10016 break;
10017 case PPC_FLAGS_INPUT_BookE:
10018 bus_model = "PowerPC BookE";
10019 break;
10020 case PPC_FLAGS_INPUT_405:
10021 bus_model = "PowerPC 405";
10022 break;
10023 case PPC_FLAGS_INPUT_401:
10024 bus_model = "PowerPC 401/403";
10025 break;
10026 case PPC_FLAGS_INPUT_RCPU:
10027 bus_model = "RCPU / MPC8xx";
10028 break;
10029 #if defined (TARGET_PPC64)
10030 case PPC_FLAGS_INPUT_970:
10031 bus_model = "PowerPC 970";
10032 break;
10033 #endif
10034 default:
10035 bus_model = "Unknown or invalid";
10036 break;
10037 }
10038 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
10039 " MMU model : %s\n",
10040 def->name, def->pvr, def->msr_mask, mmu_model);
10041 #if !defined(CONFIG_USER_ONLY)
10042 if (env->tlb != NULL) {
10043 printf(" %d %s TLB in %d ways\n",
10044 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
10045 env->nb_ways);
10046 }
10047 #endif
10048 printf(" Exceptions model : %s\n"
10049 " Bus model : %s\n",
10050 excp_model, bus_model);
10051 printf(" MSR features :\n");
10052 if (env->flags & POWERPC_FLAG_SPE)
10053 printf(" signal processing engine enable"
10054 "\n");
10055 else if (env->flags & POWERPC_FLAG_VRE)
10056 printf(" vector processor enable\n");
10057 if (env->flags & POWERPC_FLAG_TGPR)
10058 printf(" temporary GPRs\n");
10059 else if (env->flags & POWERPC_FLAG_CE)
10060 printf(" critical input enable\n");
10061 if (env->flags & POWERPC_FLAG_SE)
10062 printf(" single-step trace mode\n");
10063 else if (env->flags & POWERPC_FLAG_DWE)
10064 printf(" debug wait enable\n");
10065 else if (env->flags & POWERPC_FLAG_UBLE)
10066 printf(" user BTB lock enable\n");
10067 if (env->flags & POWERPC_FLAG_BE)
10068 printf(" branch-step trace mode\n");
10069 else if (env->flags & POWERPC_FLAG_DE)
10070 printf(" debug interrupt enable\n");
10071 if (env->flags & POWERPC_FLAG_PX)
10072 printf(" inclusive protection\n");
10073 else if (env->flags & POWERPC_FLAG_PMM)
10074 printf(" performance monitor mark\n");
10075 if (env->flags == POWERPC_FLAG_NONE)
10076 printf(" none\n");
10077 printf(" Time-base/decrementer clock source: %s\n",
10078 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
10079 }
10080 dump_ppc_insns(env);
10081 dump_ppc_sprs(env);
10082 fflush(stdout);
10083 #endif
10084
10085 return 0;
10086 }
10087
10088 static bool ppc_cpu_usable(const ppc_def_t *def)
10089 {
10090 #if defined(TARGET_PPCEMB)
10091 /* When using the ppcemb target, we only support 440 style cores */
10092 if (def->mmu_model != POWERPC_MMU_BOOKE) {
10093 return false;
10094 }
10095 #endif
10096
10097 return true;
10098 }
10099
10100 const ppc_def_t *ppc_find_by_pvr(uint32_t pvr)
10101 {
10102 int i;
10103
10104 for (i = 0; i < ARRAY_SIZE(ppc_defs); i++) {
10105 if (!ppc_cpu_usable(&ppc_defs[i])) {
10106 continue;
10107 }
10108
10109 /* If we have an exact match, we're done */
10110 if (pvr == ppc_defs[i].pvr) {
10111 return &ppc_defs[i];
10112 }
10113 }
10114
10115 return NULL;
10116 }
10117
10118 #include <ctype.h>
10119
10120 const ppc_def_t *cpu_ppc_find_by_name (const char *name)
10121 {
10122 const ppc_def_t *ret;
10123 const char *p;
10124 int i, max, len;
10125
10126 if (kvm_enabled() && (strcasecmp(name, "host") == 0)) {
10127 return kvmppc_host_cpu_def();
10128 }
10129
10130 /* Check if the given name is a PVR */
10131 len = strlen(name);
10132 if (len == 10 && name[0] == '0' && name[1] == 'x') {
10133 p = name + 2;
10134 goto check_pvr;
10135 } else if (len == 8) {
10136 p = name;
10137 check_pvr:
10138 for (i = 0; i < 8; i++) {
10139 if (!qemu_isxdigit(*p++))
10140 break;
10141 }
10142 if (i == 8)
10143 return ppc_find_by_pvr(strtoul(name, NULL, 16));
10144 }
10145 ret = NULL;
10146 max = ARRAY_SIZE(ppc_defs);
10147 for (i = 0; i < max; i++) {
10148 if (!ppc_cpu_usable(&ppc_defs[i])) {
10149 continue;
10150 }
10151
10152 if (strcasecmp(name, ppc_defs[i].name) == 0) {
10153 ret = &ppc_defs[i];
10154 break;
10155 }
10156 }
10157
10158 return ret;
10159 }
10160
10161 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
10162 {
10163 int i, max;
10164
10165 max = ARRAY_SIZE(ppc_defs);
10166 for (i = 0; i < max; i++) {
10167 if (!ppc_cpu_usable(&ppc_defs[i])) {
10168 continue;
10169 }
10170
10171 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
10172 ppc_defs[i].name, ppc_defs[i].pvr);
10173 }
10174 }
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