2 * PowerPC CPU initialization for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
28 //#define PPC_DUMP_CPU
29 //#define PPC_DEBUG_SPR
30 //#define PPC_DEBUG_IRQ
33 const unsigned char *name
;
43 void (*init_proc
)(CPUPPCState
*env
);
46 /* For user-mode emulation, we don't emulate any IRQ controller */
47 #if defined(CONFIG_USER_ONLY)
48 #define PPC_IRQ_INIT_FN(name) \
49 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
53 #define PPC_IRQ_INIT_FN(name) \
54 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
63 * do nothing but store/retrieve spr value
65 #ifdef PPC_DUMP_SPR_ACCESSES
66 static void spr_read_generic (void *opaque
, int sprn
)
68 gen_op_load_dump_spr(sprn
);
71 static void spr_write_generic (void *opaque
, int sprn
)
73 gen_op_store_dump_spr(sprn
);
76 static void spr_read_generic (void *opaque
, int sprn
)
78 gen_op_load_spr(sprn
);
81 static void spr_write_generic (void *opaque
, int sprn
)
83 gen_op_store_spr(sprn
);
87 #if !defined(CONFIG_USER_ONLY)
88 static void spr_write_clear (void *opaque
, int sprn
)
90 gen_op_mask_spr(sprn
);
94 /* SPR common to all PowerPC */
96 static void spr_read_xer (void *opaque
, int sprn
)
101 static void spr_write_xer (void *opaque
, int sprn
)
107 static void spr_read_lr (void *opaque
, int sprn
)
112 static void spr_write_lr (void *opaque
, int sprn
)
118 static void spr_read_ctr (void *opaque
, int sprn
)
123 static void spr_write_ctr (void *opaque
, int sprn
)
128 /* User read access to SPR */
134 static void spr_read_ureg (void *opaque
, int sprn
)
136 gen_op_load_spr(sprn
+ 0x10);
139 /* SPR common to all non-embedded PowerPC */
141 #if !defined(CONFIG_USER_ONLY)
142 static void spr_read_decr (void *opaque
, int sprn
)
147 static void spr_write_decr (void *opaque
, int sprn
)
153 /* SPR common to all non-embedded PowerPC, except 601 */
155 static void spr_read_tbl (void *opaque
, int sprn
)
160 static void spr_read_tbu (void *opaque
, int sprn
)
165 #if !defined(CONFIG_USER_ONLY)
166 static void spr_write_tbl (void *opaque
, int sprn
)
171 static void spr_write_tbu (void *opaque
, int sprn
)
177 #if !defined(CONFIG_USER_ONLY)
178 /* IBAT0U...IBAT0U */
179 /* IBAT0L...IBAT7L */
180 static void spr_read_ibat (void *opaque
, int sprn
)
182 gen_op_load_ibat(sprn
& 1, (sprn
- SPR_IBAT0U
) / 2);
185 static void spr_read_ibat_h (void *opaque
, int sprn
)
187 gen_op_load_ibat(sprn
& 1, (sprn
- SPR_IBAT4U
) / 2);
190 static void spr_write_ibatu (void *opaque
, int sprn
)
192 DisasContext
*ctx
= opaque
;
194 gen_op_store_ibatu((sprn
- SPR_IBAT0U
) / 2);
198 static void spr_write_ibatu_h (void *opaque
, int sprn
)
200 DisasContext
*ctx
= opaque
;
202 gen_op_store_ibatu((sprn
- SPR_IBAT4U
) / 2);
206 static void spr_write_ibatl (void *opaque
, int sprn
)
208 DisasContext
*ctx
= opaque
;
210 gen_op_store_ibatl((sprn
- SPR_IBAT0L
) / 2);
214 static void spr_write_ibatl_h (void *opaque
, int sprn
)
216 DisasContext
*ctx
= opaque
;
218 gen_op_store_ibatl((sprn
- SPR_IBAT4L
) / 2);
222 /* DBAT0U...DBAT7U */
223 /* DBAT0L...DBAT7L */
224 static void spr_read_dbat (void *opaque
, int sprn
)
226 gen_op_load_dbat(sprn
& 1, (sprn
- SPR_DBAT0U
) / 2);
229 static void spr_read_dbat_h (void *opaque
, int sprn
)
231 gen_op_load_dbat(sprn
& 1, (sprn
- SPR_DBAT4U
) / 2);
234 static void spr_write_dbatu (void *opaque
, int sprn
)
236 DisasContext
*ctx
= opaque
;
238 gen_op_store_dbatu((sprn
- SPR_DBAT0U
) / 2);
242 static void spr_write_dbatu_h (void *opaque
, int sprn
)
244 DisasContext
*ctx
= opaque
;
246 gen_op_store_dbatu((sprn
- SPR_DBAT4U
) / 2);
250 static void spr_write_dbatl (void *opaque
, int sprn
)
252 DisasContext
*ctx
= opaque
;
254 gen_op_store_dbatl((sprn
- SPR_DBAT0L
) / 2);
258 static void spr_write_dbatl_h (void *opaque
, int sprn
)
260 DisasContext
*ctx
= opaque
;
262 gen_op_store_dbatl((sprn
- SPR_DBAT4L
) / 2);
267 static void spr_read_sdr1 (void *opaque
, int sprn
)
272 static void spr_write_sdr1 (void *opaque
, int sprn
)
274 DisasContext
*ctx
= opaque
;
280 /* 64 bits PowerPC specific SPRs */
282 /* Currently unused */
283 #if 0 && defined(TARGET_PPC64)
284 static void spr_read_asr (void *opaque
, int sprn
)
289 static void spr_write_asr (void *opaque
, int sprn
)
291 DisasContext
*ctx
= opaque
;
299 /* PowerPC 601 specific registers */
301 static void spr_read_601_rtcl (void *opaque
, int sprn
)
303 gen_op_load_601_rtcl();
306 static void spr_read_601_rtcu (void *opaque
, int sprn
)
308 gen_op_load_601_rtcu();
311 #if !defined(CONFIG_USER_ONLY)
312 static void spr_write_601_rtcu (void *opaque
, int sprn
)
314 gen_op_store_601_rtcu();
317 static void spr_write_601_rtcl (void *opaque
, int sprn
)
319 gen_op_store_601_rtcl();
324 #if !defined(CONFIG_USER_ONLY)
325 static void spr_read_601_ubat (void *opaque
, int sprn
)
327 gen_op_load_601_bat(sprn
& 1, (sprn
- SPR_IBAT0U
) / 2);
330 static void spr_write_601_ubatu (void *opaque
, int sprn
)
332 DisasContext
*ctx
= opaque
;
334 gen_op_store_601_batu((sprn
- SPR_IBAT0U
) / 2);
338 static void spr_write_601_ubatl (void *opaque
, int sprn
)
340 DisasContext
*ctx
= opaque
;
342 gen_op_store_601_batl((sprn
- SPR_IBAT0L
) / 2);
347 /* PowerPC 40x specific registers */
348 #if !defined(CONFIG_USER_ONLY)
349 static void spr_read_40x_pit (void *opaque
, int sprn
)
351 gen_op_load_40x_pit();
354 static void spr_write_40x_pit (void *opaque
, int sprn
)
356 gen_op_store_40x_pit();
359 static void spr_write_40x_dbcr0 (void *opaque
, int sprn
)
361 DisasContext
*ctx
= opaque
;
363 gen_op_store_40x_dbcr0();
364 /* We must stop translation as we may have rebooted */
368 static void spr_write_40x_sler (void *opaque
, int sprn
)
370 DisasContext
*ctx
= opaque
;
372 gen_op_store_40x_sler();
373 /* We must stop the translation as we may have changed
374 * some regions endianness
379 static void spr_write_booke_tcr (void *opaque
, int sprn
)
381 gen_op_store_booke_tcr();
384 static void spr_write_booke_tsr (void *opaque
, int sprn
)
386 gen_op_store_booke_tsr();
390 /* PowerPC 403 specific registers */
391 /* PBL1 / PBU1 / PBL2 / PBU2 */
392 #if !defined(CONFIG_USER_ONLY)
393 static void spr_read_403_pbr (void *opaque
, int sprn
)
395 gen_op_load_403_pb(sprn
- SPR_403_PBL1
);
398 static void spr_write_403_pbr (void *opaque
, int sprn
)
400 DisasContext
*ctx
= opaque
;
402 gen_op_store_403_pb(sprn
- SPR_403_PBL1
);
406 static void spr_write_pir (void *opaque
, int sprn
)
412 #if defined(CONFIG_USER_ONLY)
413 #define spr_register(env, num, name, uea_read, uea_write, \
414 oea_read, oea_write, initial_value) \
416 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
418 static inline void _spr_register (CPUPPCState
*env
, int num
,
419 const unsigned char *name
,
420 void (*uea_read
)(void *opaque
, int sprn
),
421 void (*uea_write
)(void *opaque
, int sprn
),
422 target_ulong initial_value
)
424 static inline void spr_register (CPUPPCState
*env
, int num
,
425 const unsigned char *name
,
426 void (*uea_read
)(void *opaque
, int sprn
),
427 void (*uea_write
)(void *opaque
, int sprn
),
428 void (*oea_read
)(void *opaque
, int sprn
),
429 void (*oea_write
)(void *opaque
, int sprn
),
430 target_ulong initial_value
)
435 spr
= &env
->spr_cb
[num
];
436 if (spr
->name
!= NULL
||env
-> spr
[num
] != 0x00000000 ||
437 #if !defined(CONFIG_USER_ONLY)
438 spr
->oea_read
!= NULL
|| spr
->oea_write
!= NULL
||
440 spr
->uea_read
!= NULL
|| spr
->uea_write
!= NULL
) {
441 printf("Error: Trying to register SPR %d (%03x) twice !\n", num
, num
);
444 #if defined(PPC_DEBUG_SPR)
445 printf("*** register spr %d (%03x) %s val " ADDRX
"\n", num
, num
, name
,
449 spr
->uea_read
= uea_read
;
450 spr
->uea_write
= uea_write
;
451 #if !defined(CONFIG_USER_ONLY)
452 spr
->oea_read
= oea_read
;
453 spr
->oea_write
= oea_write
;
455 env
->spr
[num
] = initial_value
;
458 /* Generic PowerPC SPRs */
459 static void gen_spr_generic (CPUPPCState
*env
)
461 /* Integer processing */
462 spr_register(env
, SPR_XER
, "XER",
463 &spr_read_xer
, &spr_write_xer
,
464 &spr_read_xer
, &spr_write_xer
,
467 spr_register(env
, SPR_LR
, "LR",
468 &spr_read_lr
, &spr_write_lr
,
469 &spr_read_lr
, &spr_write_lr
,
471 spr_register(env
, SPR_CTR
, "CTR",
472 &spr_read_ctr
, &spr_write_ctr
,
473 &spr_read_ctr
, &spr_write_ctr
,
475 /* Interrupt processing */
476 spr_register(env
, SPR_SRR0
, "SRR0",
477 SPR_NOACCESS
, SPR_NOACCESS
,
478 &spr_read_generic
, &spr_write_generic
,
480 spr_register(env
, SPR_SRR1
, "SRR1",
481 SPR_NOACCESS
, SPR_NOACCESS
,
482 &spr_read_generic
, &spr_write_generic
,
484 /* Processor control */
485 spr_register(env
, SPR_SPRG0
, "SPRG0",
486 SPR_NOACCESS
, SPR_NOACCESS
,
487 &spr_read_generic
, &spr_write_generic
,
489 spr_register(env
, SPR_SPRG1
, "SPRG1",
490 SPR_NOACCESS
, SPR_NOACCESS
,
491 &spr_read_generic
, &spr_write_generic
,
493 spr_register(env
, SPR_SPRG2
, "SPRG2",
494 SPR_NOACCESS
, SPR_NOACCESS
,
495 &spr_read_generic
, &spr_write_generic
,
497 spr_register(env
, SPR_SPRG3
, "SPRG3",
498 SPR_NOACCESS
, SPR_NOACCESS
,
499 &spr_read_generic
, &spr_write_generic
,
503 /* SPR common to all non-embedded PowerPC, including 601 */
504 static void gen_spr_ne_601 (CPUPPCState
*env
)
506 /* Exception processing */
507 spr_register(env
, SPR_DSISR
, "DSISR",
508 SPR_NOACCESS
, SPR_NOACCESS
,
509 &spr_read_generic
, &spr_write_generic
,
511 spr_register(env
, SPR_DAR
, "DAR",
512 SPR_NOACCESS
, SPR_NOACCESS
,
513 &spr_read_generic
, &spr_write_generic
,
516 spr_register(env
, SPR_DECR
, "DECR",
517 SPR_NOACCESS
, SPR_NOACCESS
,
518 &spr_read_decr
, &spr_write_decr
,
520 /* Memory management */
521 spr_register(env
, SPR_SDR1
, "SDR1",
522 SPR_NOACCESS
, SPR_NOACCESS
,
523 &spr_read_sdr1
, &spr_write_sdr1
,
528 static void gen_low_BATs (CPUPPCState
*env
)
530 spr_register(env
, SPR_IBAT0U
, "IBAT0U",
531 SPR_NOACCESS
, SPR_NOACCESS
,
532 &spr_read_ibat
, &spr_write_ibatu
,
534 spr_register(env
, SPR_IBAT0L
, "IBAT0L",
535 SPR_NOACCESS
, SPR_NOACCESS
,
536 &spr_read_ibat
, &spr_write_ibatl
,
538 spr_register(env
, SPR_IBAT1U
, "IBAT1U",
539 SPR_NOACCESS
, SPR_NOACCESS
,
540 &spr_read_ibat
, &spr_write_ibatu
,
542 spr_register(env
, SPR_IBAT1L
, "IBAT1L",
543 SPR_NOACCESS
, SPR_NOACCESS
,
544 &spr_read_ibat
, &spr_write_ibatl
,
546 spr_register(env
, SPR_IBAT2U
, "IBAT2U",
547 SPR_NOACCESS
, SPR_NOACCESS
,
548 &spr_read_ibat
, &spr_write_ibatu
,
550 spr_register(env
, SPR_IBAT2L
, "IBAT2L",
551 SPR_NOACCESS
, SPR_NOACCESS
,
552 &spr_read_ibat
, &spr_write_ibatl
,
554 spr_register(env
, SPR_IBAT3U
, "IBAT3U",
555 SPR_NOACCESS
, SPR_NOACCESS
,
556 &spr_read_ibat
, &spr_write_ibatu
,
558 spr_register(env
, SPR_IBAT3L
, "IBAT3L",
559 SPR_NOACCESS
, SPR_NOACCESS
,
560 &spr_read_ibat
, &spr_write_ibatl
,
562 spr_register(env
, SPR_DBAT0U
, "DBAT0U",
563 SPR_NOACCESS
, SPR_NOACCESS
,
564 &spr_read_dbat
, &spr_write_dbatu
,
566 spr_register(env
, SPR_DBAT0L
, "DBAT0L",
567 SPR_NOACCESS
, SPR_NOACCESS
,
568 &spr_read_dbat
, &spr_write_dbatl
,
570 spr_register(env
, SPR_DBAT1U
, "DBAT1U",
571 SPR_NOACCESS
, SPR_NOACCESS
,
572 &spr_read_dbat
, &spr_write_dbatu
,
574 spr_register(env
, SPR_DBAT1L
, "DBAT1L",
575 SPR_NOACCESS
, SPR_NOACCESS
,
576 &spr_read_dbat
, &spr_write_dbatl
,
578 spr_register(env
, SPR_DBAT2U
, "DBAT2U",
579 SPR_NOACCESS
, SPR_NOACCESS
,
580 &spr_read_dbat
, &spr_write_dbatu
,
582 spr_register(env
, SPR_DBAT2L
, "DBAT2L",
583 SPR_NOACCESS
, SPR_NOACCESS
,
584 &spr_read_dbat
, &spr_write_dbatl
,
586 spr_register(env
, SPR_DBAT3U
, "DBAT3U",
587 SPR_NOACCESS
, SPR_NOACCESS
,
588 &spr_read_dbat
, &spr_write_dbatu
,
590 spr_register(env
, SPR_DBAT3L
, "DBAT3L",
591 SPR_NOACCESS
, SPR_NOACCESS
,
592 &spr_read_dbat
, &spr_write_dbatl
,
598 static void gen_high_BATs (CPUPPCState
*env
)
600 spr_register(env
, SPR_IBAT4U
, "IBAT4U",
601 SPR_NOACCESS
, SPR_NOACCESS
,
602 &spr_read_ibat_h
, &spr_write_ibatu_h
,
604 spr_register(env
, SPR_IBAT4L
, "IBAT4L",
605 SPR_NOACCESS
, SPR_NOACCESS
,
606 &spr_read_ibat_h
, &spr_write_ibatl_h
,
608 spr_register(env
, SPR_IBAT5U
, "IBAT5U",
609 SPR_NOACCESS
, SPR_NOACCESS
,
610 &spr_read_ibat_h
, &spr_write_ibatu_h
,
612 spr_register(env
, SPR_IBAT5L
, "IBAT5L",
613 SPR_NOACCESS
, SPR_NOACCESS
,
614 &spr_read_ibat_h
, &spr_write_ibatl_h
,
616 spr_register(env
, SPR_IBAT6U
, "IBAT6U",
617 SPR_NOACCESS
, SPR_NOACCESS
,
618 &spr_read_ibat_h
, &spr_write_ibatu_h
,
620 spr_register(env
, SPR_IBAT6L
, "IBAT6L",
621 SPR_NOACCESS
, SPR_NOACCESS
,
622 &spr_read_ibat_h
, &spr_write_ibatl_h
,
624 spr_register(env
, SPR_IBAT7U
, "IBAT7U",
625 SPR_NOACCESS
, SPR_NOACCESS
,
626 &spr_read_ibat_h
, &spr_write_ibatu_h
,
628 spr_register(env
, SPR_IBAT7L
, "IBAT7L",
629 SPR_NOACCESS
, SPR_NOACCESS
,
630 &spr_read_ibat_h
, &spr_write_ibatl_h
,
632 spr_register(env
, SPR_DBAT4U
, "DBAT4U",
633 SPR_NOACCESS
, SPR_NOACCESS
,
634 &spr_read_dbat_h
, &spr_write_dbatu_h
,
636 spr_register(env
, SPR_DBAT4L
, "DBAT4L",
637 SPR_NOACCESS
, SPR_NOACCESS
,
638 &spr_read_dbat_h
, &spr_write_dbatl_h
,
640 spr_register(env
, SPR_DBAT5U
, "DBAT5U",
641 SPR_NOACCESS
, SPR_NOACCESS
,
642 &spr_read_dbat_h
, &spr_write_dbatu_h
,
644 spr_register(env
, SPR_DBAT5L
, "DBAT5L",
645 SPR_NOACCESS
, SPR_NOACCESS
,
646 &spr_read_dbat_h
, &spr_write_dbatl_h
,
648 spr_register(env
, SPR_DBAT6U
, "DBAT6U",
649 SPR_NOACCESS
, SPR_NOACCESS
,
650 &spr_read_dbat_h
, &spr_write_dbatu_h
,
652 spr_register(env
, SPR_DBAT6L
, "DBAT6L",
653 SPR_NOACCESS
, SPR_NOACCESS
,
654 &spr_read_dbat_h
, &spr_write_dbatl_h
,
656 spr_register(env
, SPR_DBAT7U
, "DBAT7U",
657 SPR_NOACCESS
, SPR_NOACCESS
,
658 &spr_read_dbat_h
, &spr_write_dbatu_h
,
660 spr_register(env
, SPR_DBAT7L
, "DBAT7L",
661 SPR_NOACCESS
, SPR_NOACCESS
,
662 &spr_read_dbat_h
, &spr_write_dbatl_h
,
667 /* Generic PowerPC time base */
668 static void gen_tbl (CPUPPCState
*env
)
670 spr_register(env
, SPR_VTBL
, "TBL",
671 &spr_read_tbl
, SPR_NOACCESS
,
672 &spr_read_tbl
, SPR_NOACCESS
,
674 spr_register(env
, SPR_TBL
, "TBL",
675 SPR_NOACCESS
, SPR_NOACCESS
,
676 SPR_NOACCESS
, &spr_write_tbl
,
678 spr_register(env
, SPR_VTBU
, "TBU",
679 &spr_read_tbu
, SPR_NOACCESS
,
680 &spr_read_tbu
, SPR_NOACCESS
,
682 spr_register(env
, SPR_TBU
, "TBU",
683 SPR_NOACCESS
, SPR_NOACCESS
,
684 SPR_NOACCESS
, &spr_write_tbu
,
688 /* Softare table search registers */
689 static void gen_6xx_7xx_soft_tlb (CPUPPCState
*env
, int nb_tlbs
, int nb_ways
)
691 env
->nb_tlb
= nb_tlbs
;
692 env
->nb_ways
= nb_ways
;
694 spr_register(env
, SPR_DMISS
, "DMISS",
695 SPR_NOACCESS
, SPR_NOACCESS
,
696 &spr_read_generic
, SPR_NOACCESS
,
698 spr_register(env
, SPR_DCMP
, "DCMP",
699 SPR_NOACCESS
, SPR_NOACCESS
,
700 &spr_read_generic
, SPR_NOACCESS
,
702 spr_register(env
, SPR_HASH1
, "HASH1",
703 SPR_NOACCESS
, SPR_NOACCESS
,
704 &spr_read_generic
, SPR_NOACCESS
,
706 spr_register(env
, SPR_HASH2
, "HASH2",
707 SPR_NOACCESS
, SPR_NOACCESS
,
708 &spr_read_generic
, SPR_NOACCESS
,
710 spr_register(env
, SPR_IMISS
, "IMISS",
711 SPR_NOACCESS
, SPR_NOACCESS
,
712 &spr_read_generic
, SPR_NOACCESS
,
714 spr_register(env
, SPR_ICMP
, "ICMP",
715 SPR_NOACCESS
, SPR_NOACCESS
,
716 &spr_read_generic
, SPR_NOACCESS
,
718 spr_register(env
, SPR_RPA
, "RPA",
719 SPR_NOACCESS
, SPR_NOACCESS
,
720 &spr_read_generic
, &spr_write_generic
,
724 /* SPR common to MPC755 and G2 */
725 static void gen_spr_G2_755 (CPUPPCState
*env
)
728 spr_register(env
, SPR_SPRG4
, "SPRG4",
729 SPR_NOACCESS
, SPR_NOACCESS
,
730 &spr_read_generic
, &spr_write_generic
,
732 spr_register(env
, SPR_SPRG5
, "SPRG5",
733 SPR_NOACCESS
, SPR_NOACCESS
,
734 &spr_read_generic
, &spr_write_generic
,
736 spr_register(env
, SPR_SPRG6
, "SPRG6",
737 SPR_NOACCESS
, SPR_NOACCESS
,
738 &spr_read_generic
, &spr_write_generic
,
740 spr_register(env
, SPR_SPRG7
, "SPRG7",
741 SPR_NOACCESS
, SPR_NOACCESS
,
742 &spr_read_generic
, &spr_write_generic
,
744 /* External access control */
745 /* XXX : not implemented */
746 spr_register(env
, SPR_EAR
, "EAR",
747 SPR_NOACCESS
, SPR_NOACCESS
,
748 &spr_read_generic
, &spr_write_generic
,
752 /* SPR common to all 7xx PowerPC implementations */
753 static void gen_spr_7xx (CPUPPCState
*env
)
756 /* XXX : not implemented */
757 spr_register(env
, SPR_DABR
, "DABR",
758 SPR_NOACCESS
, SPR_NOACCESS
,
759 &spr_read_generic
, &spr_write_generic
,
761 /* XXX : not implemented */
762 spr_register(env
, SPR_IABR
, "IABR",
763 SPR_NOACCESS
, SPR_NOACCESS
,
764 &spr_read_generic
, &spr_write_generic
,
766 /* Cache management */
767 /* XXX : not implemented */
768 spr_register(env
, SPR_ICTC
, "ICTC",
769 SPR_NOACCESS
, SPR_NOACCESS
,
770 &spr_read_generic
, &spr_write_generic
,
772 /* XXX : not implemented */
773 spr_register(env
, SPR_L2CR
, "L2CR",
774 SPR_NOACCESS
, SPR_NOACCESS
,
775 &spr_read_generic
, &spr_write_generic
,
777 /* Performance monitors */
778 /* XXX : not implemented */
779 spr_register(env
, SPR_MMCR0
, "MMCR0",
780 SPR_NOACCESS
, SPR_NOACCESS
,
781 &spr_read_generic
, &spr_write_generic
,
783 /* XXX : not implemented */
784 spr_register(env
, SPR_MMCR1
, "MMCR1",
785 SPR_NOACCESS
, SPR_NOACCESS
,
786 &spr_read_generic
, &spr_write_generic
,
788 /* XXX : not implemented */
789 spr_register(env
, SPR_PMC1
, "PMC1",
790 SPR_NOACCESS
, SPR_NOACCESS
,
791 &spr_read_generic
, &spr_write_generic
,
793 /* XXX : not implemented */
794 spr_register(env
, SPR_PMC2
, "PMC2",
795 SPR_NOACCESS
, SPR_NOACCESS
,
796 &spr_read_generic
, &spr_write_generic
,
798 /* XXX : not implemented */
799 spr_register(env
, SPR_PMC3
, "PMC3",
800 SPR_NOACCESS
, SPR_NOACCESS
,
801 &spr_read_generic
, &spr_write_generic
,
803 /* XXX : not implemented */
804 spr_register(env
, SPR_PMC4
, "PMC4",
805 SPR_NOACCESS
, SPR_NOACCESS
,
806 &spr_read_generic
, &spr_write_generic
,
808 /* XXX : not implemented */
809 spr_register(env
, SPR_SIAR
, "SIAR",
810 SPR_NOACCESS
, SPR_NOACCESS
,
811 &spr_read_generic
, SPR_NOACCESS
,
813 spr_register(env
, SPR_UMMCR0
, "UMMCR0",
814 &spr_read_ureg
, SPR_NOACCESS
,
815 &spr_read_ureg
, SPR_NOACCESS
,
817 spr_register(env
, SPR_UMMCR1
, "UMMCR1",
818 &spr_read_ureg
, SPR_NOACCESS
,
819 &spr_read_ureg
, SPR_NOACCESS
,
821 spr_register(env
, SPR_UPMC1
, "UPMC1",
822 &spr_read_ureg
, SPR_NOACCESS
,
823 &spr_read_ureg
, SPR_NOACCESS
,
825 spr_register(env
, SPR_UPMC2
, "UPMC2",
826 &spr_read_ureg
, SPR_NOACCESS
,
827 &spr_read_ureg
, SPR_NOACCESS
,
829 spr_register(env
, SPR_UPMC3
, "UPMC3",
830 &spr_read_ureg
, SPR_NOACCESS
,
831 &spr_read_ureg
, SPR_NOACCESS
,
833 spr_register(env
, SPR_UPMC4
, "UPMC4",
834 &spr_read_ureg
, SPR_NOACCESS
,
835 &spr_read_ureg
, SPR_NOACCESS
,
837 spr_register(env
, SPR_USIAR
, "USIAR",
838 &spr_read_ureg
, SPR_NOACCESS
,
839 &spr_read_ureg
, SPR_NOACCESS
,
841 /* External access control */
842 /* XXX : not implemented */
843 spr_register(env
, SPR_EAR
, "EAR",
844 SPR_NOACCESS
, SPR_NOACCESS
,
845 &spr_read_generic
, &spr_write_generic
,
849 static void gen_spr_thrm (CPUPPCState
*env
)
851 /* Thermal management */
852 /* XXX : not implemented */
853 spr_register(env
, SPR_THRM1
, "THRM1",
854 SPR_NOACCESS
, SPR_NOACCESS
,
855 &spr_read_generic
, &spr_write_generic
,
857 /* XXX : not implemented */
858 spr_register(env
, SPR_THRM2
, "THRM2",
859 SPR_NOACCESS
, SPR_NOACCESS
,
860 &spr_read_generic
, &spr_write_generic
,
862 /* XXX : not implemented */
863 spr_register(env
, SPR_THRM3
, "THRM3",
864 SPR_NOACCESS
, SPR_NOACCESS
,
865 &spr_read_generic
, &spr_write_generic
,
869 /* SPR specific to PowerPC 604 implementation */
870 static void gen_spr_604 (CPUPPCState
*env
)
872 /* Processor identification */
873 spr_register(env
, SPR_PIR
, "PIR",
874 SPR_NOACCESS
, SPR_NOACCESS
,
875 &spr_read_generic
, &spr_write_pir
,
878 /* XXX : not implemented */
879 spr_register(env
, SPR_IABR
, "IABR",
880 SPR_NOACCESS
, SPR_NOACCESS
,
881 &spr_read_generic
, &spr_write_generic
,
883 /* XXX : not implemented */
884 spr_register(env
, SPR_DABR
, "DABR",
885 SPR_NOACCESS
, SPR_NOACCESS
,
886 &spr_read_generic
, &spr_write_generic
,
888 /* Performance counters */
889 /* XXX : not implemented */
890 spr_register(env
, SPR_MMCR0
, "MMCR0",
891 SPR_NOACCESS
, SPR_NOACCESS
,
892 &spr_read_generic
, &spr_write_generic
,
894 /* XXX : not implemented */
895 spr_register(env
, SPR_MMCR1
, "MMCR1",
896 SPR_NOACCESS
, SPR_NOACCESS
,
897 &spr_read_generic
, &spr_write_generic
,
899 /* XXX : not implemented */
900 spr_register(env
, SPR_PMC1
, "PMC1",
901 SPR_NOACCESS
, SPR_NOACCESS
,
902 &spr_read_generic
, &spr_write_generic
,
904 /* XXX : not implemented */
905 spr_register(env
, SPR_PMC2
, "PMC2",
906 SPR_NOACCESS
, SPR_NOACCESS
,
907 &spr_read_generic
, &spr_write_generic
,
909 /* XXX : not implemented */
910 spr_register(env
, SPR_PMC3
, "PMC3",
911 SPR_NOACCESS
, SPR_NOACCESS
,
912 &spr_read_generic
, &spr_write_generic
,
914 /* XXX : not implemented */
915 spr_register(env
, SPR_PMC4
, "PMC4",
916 SPR_NOACCESS
, SPR_NOACCESS
,
917 &spr_read_generic
, &spr_write_generic
,
919 /* XXX : not implemented */
920 spr_register(env
, SPR_SIAR
, "SIAR",
921 SPR_NOACCESS
, SPR_NOACCESS
,
922 &spr_read_generic
, SPR_NOACCESS
,
924 /* XXX : not implemented */
925 spr_register(env
, SPR_SDA
, "SDA",
926 SPR_NOACCESS
, SPR_NOACCESS
,
927 &spr_read_generic
, SPR_NOACCESS
,
929 /* External access control */
930 /* XXX : not implemented */
931 spr_register(env
, SPR_EAR
, "EAR",
932 SPR_NOACCESS
, SPR_NOACCESS
,
933 &spr_read_generic
, &spr_write_generic
,
937 /* SPR specific to PowerPC 603 implementation */
938 static void gen_spr_603 (CPUPPCState
*env
)
940 /* External access control */
941 /* XXX : not implemented */
942 spr_register(env
, SPR_EAR
, "EAR",
943 SPR_NOACCESS
, SPR_NOACCESS
,
944 &spr_read_generic
, &spr_write_generic
,
948 /* SPR specific to PowerPC G2 implementation */
949 static void gen_spr_G2 (CPUPPCState
*env
)
951 /* Memory base address */
953 spr_register(env
, SPR_MBAR
, "MBAR",
954 SPR_NOACCESS
, SPR_NOACCESS
,
955 &spr_read_generic
, &spr_write_generic
,
957 /* System version register */
959 spr_register(env
, SPR_SVR
, "SVR",
960 SPR_NOACCESS
, SPR_NOACCESS
,
961 &spr_read_generic
, SPR_NOACCESS
,
963 /* Exception processing */
964 spr_register(env
, SPR_BOOKE_CSRR0
, "CSRR0",
965 SPR_NOACCESS
, SPR_NOACCESS
,
966 &spr_read_generic
, &spr_write_generic
,
968 spr_register(env
, SPR_BOOKE_CSRR1
, "CSRR1",
969 SPR_NOACCESS
, SPR_NOACCESS
,
970 &spr_read_generic
, &spr_write_generic
,
973 /* XXX : not implemented */
974 spr_register(env
, SPR_DABR
, "DABR",
975 SPR_NOACCESS
, SPR_NOACCESS
,
976 &spr_read_generic
, &spr_write_generic
,
978 /* XXX : not implemented */
979 spr_register(env
, SPR_DABR2
, "DABR2",
980 SPR_NOACCESS
, SPR_NOACCESS
,
981 &spr_read_generic
, &spr_write_generic
,
983 /* XXX : not implemented */
984 spr_register(env
, SPR_IABR
, "IABR",
985 SPR_NOACCESS
, SPR_NOACCESS
,
986 &spr_read_generic
, &spr_write_generic
,
988 /* XXX : not implemented */
989 spr_register(env
, SPR_IABR2
, "IABR2",
990 SPR_NOACCESS
, SPR_NOACCESS
,
991 &spr_read_generic
, &spr_write_generic
,
993 /* XXX : not implemented */
994 spr_register(env
, SPR_IBCR
, "IBCR",
995 SPR_NOACCESS
, SPR_NOACCESS
,
996 &spr_read_generic
, &spr_write_generic
,
998 /* XXX : not implemented */
999 spr_register(env
, SPR_DBCR
, "DBCR",
1000 SPR_NOACCESS
, SPR_NOACCESS
,
1001 &spr_read_generic
, &spr_write_generic
,
1005 /* SPR specific to PowerPC 602 implementation */
1006 static void gen_spr_602 (CPUPPCState
*env
)
1009 /* XXX : not implemented */
1010 spr_register(env
, SPR_SER
, "SER",
1011 SPR_NOACCESS
, SPR_NOACCESS
,
1012 &spr_read_generic
, &spr_write_generic
,
1014 /* XXX : not implemented */
1015 spr_register(env
, SPR_SEBR
, "SEBR",
1016 SPR_NOACCESS
, SPR_NOACCESS
,
1017 &spr_read_generic
, &spr_write_generic
,
1019 /* XXX : not implemented */
1020 spr_register(env
, SPR_ESASRR
, "ESASRR",
1021 SPR_NOACCESS
, SPR_NOACCESS
,
1022 &spr_read_generic
, &spr_write_generic
,
1024 /* Floating point status */
1025 /* XXX : not implemented */
1026 spr_register(env
, SPR_SP
, "SP",
1027 SPR_NOACCESS
, SPR_NOACCESS
,
1028 &spr_read_generic
, &spr_write_generic
,
1030 /* XXX : not implemented */
1031 spr_register(env
, SPR_LT
, "LT",
1032 SPR_NOACCESS
, SPR_NOACCESS
,
1033 &spr_read_generic
, &spr_write_generic
,
1035 /* Watchdog timer */
1036 /* XXX : not implemented */
1037 spr_register(env
, SPR_TCR
, "TCR",
1038 SPR_NOACCESS
, SPR_NOACCESS
,
1039 &spr_read_generic
, &spr_write_generic
,
1041 /* Interrupt base */
1042 spr_register(env
, SPR_IBR
, "IBR",
1043 SPR_NOACCESS
, SPR_NOACCESS
,
1044 &spr_read_generic
, &spr_write_generic
,
1046 /* XXX : not implemented */
1047 spr_register(env
, SPR_IABR
, "IABR",
1048 SPR_NOACCESS
, SPR_NOACCESS
,
1049 &spr_read_generic
, &spr_write_generic
,
1053 /* SPR specific to PowerPC 601 implementation */
1054 static void gen_spr_601 (CPUPPCState
*env
)
1056 /* Multiplication/division register */
1058 spr_register(env
, SPR_MQ
, "MQ",
1059 &spr_read_generic
, &spr_write_generic
,
1060 &spr_read_generic
, &spr_write_generic
,
1063 spr_register(env
, SPR_601_RTCU
, "RTCU",
1064 SPR_NOACCESS
, SPR_NOACCESS
,
1065 SPR_NOACCESS
, &spr_write_601_rtcu
,
1067 spr_register(env
, SPR_601_VRTCU
, "RTCU",
1068 &spr_read_601_rtcu
, SPR_NOACCESS
,
1069 &spr_read_601_rtcu
, SPR_NOACCESS
,
1071 spr_register(env
, SPR_601_RTCL
, "RTCL",
1072 SPR_NOACCESS
, SPR_NOACCESS
,
1073 SPR_NOACCESS
, &spr_write_601_rtcl
,
1075 spr_register(env
, SPR_601_VRTCL
, "RTCL",
1076 &spr_read_601_rtcl
, SPR_NOACCESS
,
1077 &spr_read_601_rtcl
, SPR_NOACCESS
,
1081 spr_register(env
, SPR_601_UDECR
, "UDECR",
1082 &spr_read_decr
, SPR_NOACCESS
,
1083 &spr_read_decr
, SPR_NOACCESS
,
1086 /* External access control */
1087 /* XXX : not implemented */
1088 spr_register(env
, SPR_EAR
, "EAR",
1089 SPR_NOACCESS
, SPR_NOACCESS
,
1090 &spr_read_generic
, &spr_write_generic
,
1092 /* Memory management */
1093 spr_register(env
, SPR_IBAT0U
, "IBAT0U",
1094 SPR_NOACCESS
, SPR_NOACCESS
,
1095 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1097 spr_register(env
, SPR_IBAT0L
, "IBAT0L",
1098 SPR_NOACCESS
, SPR_NOACCESS
,
1099 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1101 spr_register(env
, SPR_IBAT1U
, "IBAT1U",
1102 SPR_NOACCESS
, SPR_NOACCESS
,
1103 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1105 spr_register(env
, SPR_IBAT1L
, "IBAT1L",
1106 SPR_NOACCESS
, SPR_NOACCESS
,
1107 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1109 spr_register(env
, SPR_IBAT2U
, "IBAT2U",
1110 SPR_NOACCESS
, SPR_NOACCESS
,
1111 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1113 spr_register(env
, SPR_IBAT2L
, "IBAT2L",
1114 SPR_NOACCESS
, SPR_NOACCESS
,
1115 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1117 spr_register(env
, SPR_IBAT3U
, "IBAT3U",
1118 SPR_NOACCESS
, SPR_NOACCESS
,
1119 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1121 spr_register(env
, SPR_IBAT3L
, "IBAT3L",
1122 SPR_NOACCESS
, SPR_NOACCESS
,
1123 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1128 static void gen_spr_74xx (CPUPPCState
*env
)
1130 /* Processor identification */
1131 spr_register(env
, SPR_PIR
, "PIR",
1132 SPR_NOACCESS
, SPR_NOACCESS
,
1133 &spr_read_generic
, &spr_write_pir
,
1135 /* XXX : not implemented */
1136 spr_register(env
, SPR_MMCR2
, "MMCR2",
1137 SPR_NOACCESS
, SPR_NOACCESS
,
1138 &spr_read_generic
, &spr_write_generic
,
1140 spr_register(env
, SPR_UMMCR2
, "UMMCR2",
1141 &spr_read_ureg
, SPR_NOACCESS
,
1142 &spr_read_ureg
, SPR_NOACCESS
,
1144 /* XXX: not implemented */
1145 spr_register(env
, SPR_BAMR
, "BAMR",
1146 SPR_NOACCESS
, SPR_NOACCESS
,
1147 &spr_read_generic
, &spr_write_generic
,
1149 spr_register(env
, SPR_UBAMR
, "UBAMR",
1150 &spr_read_ureg
, SPR_NOACCESS
,
1151 &spr_read_ureg
, SPR_NOACCESS
,
1153 spr_register(env
, SPR_MSSCR0
, "MSSCR0",
1154 SPR_NOACCESS
, SPR_NOACCESS
,
1155 &spr_read_generic
, &spr_write_generic
,
1157 /* Hardware implementation registers */
1158 /* XXX : not implemented */
1159 spr_register(env
, SPR_HID0
, "HID0",
1160 SPR_NOACCESS
, SPR_NOACCESS
,
1161 &spr_read_generic
, &spr_write_generic
,
1163 /* XXX : not implemented */
1164 spr_register(env
, SPR_HID1
, "HID1",
1165 SPR_NOACCESS
, SPR_NOACCESS
,
1166 &spr_read_generic
, &spr_write_generic
,
1169 spr_register(env
, SPR_VRSAVE
, "VRSAVE",
1170 &spr_read_generic
, &spr_write_generic
,
1171 &spr_read_generic
, &spr_write_generic
,
1176 static void gen_l3_ctrl (CPUPPCState
*env
)
1179 /* XXX : not implemented */
1180 spr_register(env
, SPR_L3CR
, "L3CR",
1181 SPR_NOACCESS
, SPR_NOACCESS
,
1182 &spr_read_generic
, &spr_write_generic
,
1185 spr_register(env
, SPR_L3ITCR0
, "L3ITCR0",
1186 SPR_NOACCESS
, SPR_NOACCESS
,
1187 &spr_read_generic
, &spr_write_generic
,
1190 spr_register(env
, SPR_L3ITCR1
, "L3ITCR1",
1191 SPR_NOACCESS
, SPR_NOACCESS
,
1192 &spr_read_generic
, &spr_write_generic
,
1195 spr_register(env
, SPR_L3ITCR2
, "L3ITCR2",
1196 SPR_NOACCESS
, SPR_NOACCESS
,
1197 &spr_read_generic
, &spr_write_generic
,
1200 spr_register(env
, SPR_L3ITCR3
, "L3ITCR3",
1201 SPR_NOACCESS
, SPR_NOACCESS
,
1202 &spr_read_generic
, &spr_write_generic
,
1205 spr_register(env
, SPR_L3OHCR
, "L3OHCR",
1206 SPR_NOACCESS
, SPR_NOACCESS
,
1207 &spr_read_generic
, &spr_write_generic
,
1210 spr_register(env
, SPR_L3PM
, "L3PM",
1211 SPR_NOACCESS
, SPR_NOACCESS
,
1212 &spr_read_generic
, &spr_write_generic
,
1218 static void gen_74xx_soft_tlb (CPUPPCState
*env
)
1221 spr_register(env
, SPR_PTEHI
, "PTEHI",
1222 SPR_NOACCESS
, SPR_NOACCESS
,
1223 &spr_read_generic
, &spr_write_generic
,
1225 spr_register(env
, SPR_PTELO
, "PTELO",
1226 SPR_NOACCESS
, SPR_NOACCESS
,
1227 &spr_read_generic
, &spr_write_generic
,
1229 spr_register(env
, SPR_TLBMISS
, "TLBMISS",
1230 SPR_NOACCESS
, SPR_NOACCESS
,
1231 &spr_read_generic
, &spr_write_generic
,
1236 /* PowerPC BookE SPR */
1237 static void gen_spr_BookE (CPUPPCState
*env
)
1239 /* Processor identification */
1240 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
1241 SPR_NOACCESS
, SPR_NOACCESS
,
1242 &spr_read_generic
, &spr_write_pir
,
1244 /* Interrupt processing */
1245 spr_register(env
, SPR_BOOKE_CSRR0
, "CSRR0",
1246 SPR_NOACCESS
, SPR_NOACCESS
,
1247 &spr_read_generic
, &spr_write_generic
,
1249 spr_register(env
, SPR_BOOKE_CSRR1
, "CSRR1",
1250 SPR_NOACCESS
, SPR_NOACCESS
,
1251 &spr_read_generic
, &spr_write_generic
,
1254 spr_register(env
, SPR_BOOKE_DSRR0
, "DSRR0",
1255 SPR_NOACCESS
, SPR_NOACCESS
,
1256 &spr_read_generic
, &spr_write_generic
,
1258 spr_register(env
, SPR_BOOKE_DSRR1
, "DSRR1",
1259 SPR_NOACCESS
, SPR_NOACCESS
,
1260 &spr_read_generic
, &spr_write_generic
,
1264 /* XXX : not implemented */
1265 spr_register(env
, SPR_BOOKE_IAC1
, "IAC1",
1266 SPR_NOACCESS
, SPR_NOACCESS
,
1267 &spr_read_generic
, &spr_write_generic
,
1269 /* XXX : not implemented */
1270 spr_register(env
, SPR_BOOKE_IAC2
, "IAC2",
1271 SPR_NOACCESS
, SPR_NOACCESS
,
1272 &spr_read_generic
, &spr_write_generic
,
1274 /* XXX : not implemented */
1275 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
1276 SPR_NOACCESS
, SPR_NOACCESS
,
1277 &spr_read_generic
, &spr_write_generic
,
1279 /* XXX : not implemented */
1280 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
1281 SPR_NOACCESS
, SPR_NOACCESS
,
1282 &spr_read_generic
, &spr_write_generic
,
1284 /* XXX : not implemented */
1285 spr_register(env
, SPR_BOOKE_DAC1
, "DAC1",
1286 SPR_NOACCESS
, SPR_NOACCESS
,
1287 &spr_read_generic
, &spr_write_generic
,
1289 /* XXX : not implemented */
1290 spr_register(env
, SPR_BOOKE_DAC2
, "DAC2",
1291 SPR_NOACCESS
, SPR_NOACCESS
,
1292 &spr_read_generic
, &spr_write_generic
,
1294 /* XXX : not implemented */
1295 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
1296 SPR_NOACCESS
, SPR_NOACCESS
,
1297 &spr_read_generic
, &spr_write_generic
,
1299 /* XXX : not implemented */
1300 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
1301 SPR_NOACCESS
, SPR_NOACCESS
,
1302 &spr_read_generic
, &spr_write_generic
,
1304 /* XXX : not implemented */
1305 spr_register(env
, SPR_BOOKE_DBCR0
, "DBCR0",
1306 SPR_NOACCESS
, SPR_NOACCESS
,
1307 &spr_read_generic
, &spr_write_generic
,
1309 /* XXX : not implemented */
1310 spr_register(env
, SPR_BOOKE_DBCR1
, "DBCR1",
1311 SPR_NOACCESS
, SPR_NOACCESS
,
1312 &spr_read_generic
, &spr_write_generic
,
1314 /* XXX : not implemented */
1315 spr_register(env
, SPR_BOOKE_DBCR2
, "DBCR2",
1316 SPR_NOACCESS
, SPR_NOACCESS
,
1317 &spr_read_generic
, &spr_write_generic
,
1319 /* XXX : not implemented */
1320 spr_register(env
, SPR_BOOKE_DBSR
, "DBSR",
1321 SPR_NOACCESS
, SPR_NOACCESS
,
1322 &spr_read_generic
, &spr_write_clear
,
1324 spr_register(env
, SPR_BOOKE_DEAR
, "DEAR",
1325 SPR_NOACCESS
, SPR_NOACCESS
,
1326 &spr_read_generic
, &spr_write_generic
,
1328 spr_register(env
, SPR_BOOKE_ESR
, "ESR",
1329 SPR_NOACCESS
, SPR_NOACCESS
,
1330 &spr_read_generic
, &spr_write_generic
,
1332 spr_register(env
, SPR_BOOKE_IVPR
, "IVPR",
1333 SPR_NOACCESS
, SPR_NOACCESS
,
1334 &spr_read_generic
, &spr_write_generic
,
1336 /* Exception vectors */
1337 spr_register(env
, SPR_BOOKE_IVOR0
, "IVOR0",
1338 SPR_NOACCESS
, SPR_NOACCESS
,
1339 &spr_read_generic
, &spr_write_generic
,
1341 spr_register(env
, SPR_BOOKE_IVOR1
, "IVOR1",
1342 SPR_NOACCESS
, SPR_NOACCESS
,
1343 &spr_read_generic
, &spr_write_generic
,
1345 spr_register(env
, SPR_BOOKE_IVOR2
, "IVOR2",
1346 SPR_NOACCESS
, SPR_NOACCESS
,
1347 &spr_read_generic
, &spr_write_generic
,
1349 spr_register(env
, SPR_BOOKE_IVOR3
, "IVOR3",
1350 SPR_NOACCESS
, SPR_NOACCESS
,
1351 &spr_read_generic
, &spr_write_generic
,
1353 spr_register(env
, SPR_BOOKE_IVOR4
, "IVOR4",
1354 SPR_NOACCESS
, SPR_NOACCESS
,
1355 &spr_read_generic
, &spr_write_generic
,
1357 spr_register(env
, SPR_BOOKE_IVOR5
, "IVOR5",
1358 SPR_NOACCESS
, SPR_NOACCESS
,
1359 &spr_read_generic
, &spr_write_generic
,
1361 spr_register(env
, SPR_BOOKE_IVOR6
, "IVOR6",
1362 SPR_NOACCESS
, SPR_NOACCESS
,
1363 &spr_read_generic
, &spr_write_generic
,
1365 spr_register(env
, SPR_BOOKE_IVOR7
, "IVOR7",
1366 SPR_NOACCESS
, SPR_NOACCESS
,
1367 &spr_read_generic
, &spr_write_generic
,
1369 spr_register(env
, SPR_BOOKE_IVOR8
, "IVOR8",
1370 SPR_NOACCESS
, SPR_NOACCESS
,
1371 &spr_read_generic
, &spr_write_generic
,
1373 spr_register(env
, SPR_BOOKE_IVOR9
, "IVOR9",
1374 SPR_NOACCESS
, SPR_NOACCESS
,
1375 &spr_read_generic
, &spr_write_generic
,
1377 spr_register(env
, SPR_BOOKE_IVOR10
, "IVOR10",
1378 SPR_NOACCESS
, SPR_NOACCESS
,
1379 &spr_read_generic
, &spr_write_generic
,
1381 spr_register(env
, SPR_BOOKE_IVOR11
, "IVOR11",
1382 SPR_NOACCESS
, SPR_NOACCESS
,
1383 &spr_read_generic
, &spr_write_generic
,
1385 spr_register(env
, SPR_BOOKE_IVOR12
, "IVOR12",
1386 SPR_NOACCESS
, SPR_NOACCESS
,
1387 &spr_read_generic
, &spr_write_generic
,
1389 spr_register(env
, SPR_BOOKE_IVOR13
, "IVOR13",
1390 SPR_NOACCESS
, SPR_NOACCESS
,
1391 &spr_read_generic
, &spr_write_generic
,
1393 spr_register(env
, SPR_BOOKE_IVOR14
, "IVOR14",
1394 SPR_NOACCESS
, SPR_NOACCESS
,
1395 &spr_read_generic
, &spr_write_generic
,
1397 spr_register(env
, SPR_BOOKE_IVOR15
, "IVOR15",
1398 SPR_NOACCESS
, SPR_NOACCESS
,
1399 &spr_read_generic
, &spr_write_generic
,
1402 spr_register(env
, SPR_BOOKE_IVOR32
, "IVOR32",
1403 SPR_NOACCESS
, SPR_NOACCESS
,
1404 &spr_read_generic
, &spr_write_generic
,
1406 spr_register(env
, SPR_BOOKE_IVOR33
, "IVOR33",
1407 SPR_NOACCESS
, SPR_NOACCESS
,
1408 &spr_read_generic
, &spr_write_generic
,
1410 spr_register(env
, SPR_BOOKE_IVOR34
, "IVOR34",
1411 SPR_NOACCESS
, SPR_NOACCESS
,
1412 &spr_read_generic
, &spr_write_generic
,
1414 spr_register(env
, SPR_BOOKE_IVOR35
, "IVOR35",
1415 SPR_NOACCESS
, SPR_NOACCESS
,
1416 &spr_read_generic
, &spr_write_generic
,
1418 spr_register(env
, SPR_BOOKE_IVOR36
, "IVOR36",
1419 SPR_NOACCESS
, SPR_NOACCESS
,
1420 &spr_read_generic
, &spr_write_generic
,
1422 spr_register(env
, SPR_BOOKE_IVOR37
, "IVOR37",
1423 SPR_NOACCESS
, SPR_NOACCESS
,
1424 &spr_read_generic
, &spr_write_generic
,
1427 spr_register(env
, SPR_BOOKE_PID
, "PID",
1428 SPR_NOACCESS
, SPR_NOACCESS
,
1429 &spr_read_generic
, &spr_write_generic
,
1431 spr_register(env
, SPR_BOOKE_TCR
, "TCR",
1432 SPR_NOACCESS
, SPR_NOACCESS
,
1433 &spr_read_generic
, &spr_write_booke_tcr
,
1435 spr_register(env
, SPR_BOOKE_TSR
, "TSR",
1436 SPR_NOACCESS
, SPR_NOACCESS
,
1437 &spr_read_generic
, &spr_write_booke_tsr
,
1440 spr_register(env
, SPR_DECR
, "DECR",
1441 SPR_NOACCESS
, SPR_NOACCESS
,
1442 &spr_read_decr
, &spr_write_decr
,
1444 spr_register(env
, SPR_BOOKE_DECAR
, "DECAR",
1445 SPR_NOACCESS
, SPR_NOACCESS
,
1446 SPR_NOACCESS
, &spr_write_generic
,
1449 spr_register(env
, SPR_USPRG0
, "USPRG0",
1450 &spr_read_generic
, &spr_write_generic
,
1451 &spr_read_generic
, &spr_write_generic
,
1453 spr_register(env
, SPR_SPRG4
, "SPRG4",
1454 SPR_NOACCESS
, SPR_NOACCESS
,
1455 &spr_read_generic
, &spr_write_generic
,
1457 spr_register(env
, SPR_USPRG4
, "USPRG4",
1458 &spr_read_ureg
, SPR_NOACCESS
,
1459 &spr_read_ureg
, SPR_NOACCESS
,
1461 spr_register(env
, SPR_SPRG5
, "SPRG5",
1462 SPR_NOACCESS
, SPR_NOACCESS
,
1463 &spr_read_generic
, &spr_write_generic
,
1465 spr_register(env
, SPR_USPRG5
, "USPRG5",
1466 &spr_read_ureg
, SPR_NOACCESS
,
1467 &spr_read_ureg
, SPR_NOACCESS
,
1469 spr_register(env
, SPR_SPRG6
, "SPRG6",
1470 SPR_NOACCESS
, SPR_NOACCESS
,
1471 &spr_read_generic
, &spr_write_generic
,
1473 spr_register(env
, SPR_USPRG6
, "USPRG6",
1474 &spr_read_ureg
, SPR_NOACCESS
,
1475 &spr_read_ureg
, SPR_NOACCESS
,
1477 spr_register(env
, SPR_SPRG7
, "SPRG7",
1478 SPR_NOACCESS
, SPR_NOACCESS
,
1479 &spr_read_generic
, &spr_write_generic
,
1481 spr_register(env
, SPR_USPRG7
, "USPRG7",
1482 &spr_read_ureg
, SPR_NOACCESS
,
1483 &spr_read_ureg
, SPR_NOACCESS
,
1487 /* FSL storage control registers */
1489 static void gen_spr_BookE_FSL (CPUPPCState
*env
)
1491 /* TLB assist registers */
1492 spr_register(env
, SPR_BOOKE_MAS0
, "MAS0",
1493 SPR_NOACCESS
, SPR_NOACCESS
,
1494 &spr_read_generic
, &spr_write_generic
,
1496 spr_register(env
, SPR_BOOKE_MAS1
, "MAS2",
1497 SPR_NOACCESS
, SPR_NOACCESS
,
1498 &spr_read_generic
, &spr_write_generic
,
1500 spr_register(env
, SPR_BOOKE_MAS2
, "MAS3",
1501 SPR_NOACCESS
, SPR_NOACCESS
,
1502 &spr_read_generic
, &spr_write_generic
,
1504 spr_register(env
, SPR_BOOKE_MAS3
, "MAS4",
1505 SPR_NOACCESS
, SPR_NOACCESS
,
1506 &spr_read_generic
, &spr_write_generic
,
1508 spr_register(env
, SPR_BOOKE_MAS4
, "MAS5",
1509 SPR_NOACCESS
, SPR_NOACCESS
,
1510 &spr_read_generic
, &spr_write_generic
,
1512 spr_register(env
, SPR_BOOKE_MAS6
, "MAS6",
1513 SPR_NOACCESS
, SPR_NOACCESS
,
1514 &spr_read_generic
, &spr_write_generic
,
1516 spr_register(env
, SPR_BOOKE_MAS7
, "MAS7",
1517 SPR_NOACCESS
, SPR_NOACCESS
,
1518 &spr_read_generic
, &spr_write_generic
,
1520 if (env
->nb_pids
> 1) {
1521 spr_register(env
, SPR_BOOKE_PID1
, "PID1",
1522 SPR_NOACCESS
, SPR_NOACCESS
,
1523 &spr_read_generic
, &spr_write_generic
,
1526 if (env
->nb_pids
> 2) {
1527 spr_register(env
, SPR_BOOKE_PID2
, "PID2",
1528 SPR_NOACCESS
, SPR_NOACCESS
,
1529 &spr_read_generic
, &spr_write_generic
,
1532 spr_register(env
, SPR_BOOKE_MMUCFG
, "MMUCFG",
1533 SPR_NOACCESS
, SPR_NOACCESS
,
1534 &spr_read_generic
, SPR_NOACCESS
,
1535 0x00000000); /* TOFIX */
1536 spr_register(env
, SPR_BOOKE_MMUCSR0
, "MMUCSR0",
1537 SPR_NOACCESS
, SPR_NOACCESS
,
1538 &spr_read_generic
, &spr_write_generic
,
1539 0x00000000); /* TOFIX */
1540 switch (env
->nb_ways
) {
1542 spr_register(env
, SPR_BOOKE_TLB3CFG
, "TLB3CFG",
1543 SPR_NOACCESS
, SPR_NOACCESS
,
1544 &spr_read_generic
, SPR_NOACCESS
,
1545 0x00000000); /* TOFIX */
1548 spr_register(env
, SPR_BOOKE_TLB2CFG
, "TLB2CFG",
1549 SPR_NOACCESS
, SPR_NOACCESS
,
1550 &spr_read_generic
, SPR_NOACCESS
,
1551 0x00000000); /* TOFIX */
1554 spr_register(env
, SPR_BOOKE_TLB1CFG
, "TLB1CFG",
1555 SPR_NOACCESS
, SPR_NOACCESS
,
1556 &spr_read_generic
, SPR_NOACCESS
,
1557 0x00000000); /* TOFIX */
1560 spr_register(env
, SPR_BOOKE_TLB0CFG
, "TLB0CFG",
1561 SPR_NOACCESS
, SPR_NOACCESS
,
1562 &spr_read_generic
, SPR_NOACCESS
,
1563 0x00000000); /* TOFIX */
1572 /* SPR specific to PowerPC 440 implementation */
1573 static void gen_spr_440 (CPUPPCState
*env
)
1576 /* XXX : not implemented */
1577 spr_register(env
, SPR_440_DNV0
, "DNV0",
1578 SPR_NOACCESS
, SPR_NOACCESS
,
1579 &spr_read_generic
, &spr_write_generic
,
1581 /* XXX : not implemented */
1582 spr_register(env
, SPR_440_DNV1
, "DNV1",
1583 SPR_NOACCESS
, SPR_NOACCESS
,
1584 &spr_read_generic
, &spr_write_generic
,
1586 /* XXX : not implemented */
1587 spr_register(env
, SPR_440_DNV2
, "DNV2",
1588 SPR_NOACCESS
, SPR_NOACCESS
,
1589 &spr_read_generic
, &spr_write_generic
,
1591 /* XXX : not implemented */
1592 spr_register(env
, SPR_440_DNV3
, "DNV3",
1593 SPR_NOACCESS
, SPR_NOACCESS
,
1594 &spr_read_generic
, &spr_write_generic
,
1596 /* XXX : not implemented */
1597 spr_register(env
, SPR_440_DTV0
, "DTV0",
1598 SPR_NOACCESS
, SPR_NOACCESS
,
1599 &spr_read_generic
, &spr_write_generic
,
1601 /* XXX : not implemented */
1602 spr_register(env
, SPR_440_DTV1
, "DTV1",
1603 SPR_NOACCESS
, SPR_NOACCESS
,
1604 &spr_read_generic
, &spr_write_generic
,
1606 /* XXX : not implemented */
1607 spr_register(env
, SPR_440_DTV2
, "DTV2",
1608 SPR_NOACCESS
, SPR_NOACCESS
,
1609 &spr_read_generic
, &spr_write_generic
,
1611 /* XXX : not implemented */
1612 spr_register(env
, SPR_440_DTV3
, "DTV3",
1613 SPR_NOACCESS
, SPR_NOACCESS
,
1614 &spr_read_generic
, &spr_write_generic
,
1616 /* XXX : not implemented */
1617 spr_register(env
, SPR_440_DVLIM
, "DVLIM",
1618 SPR_NOACCESS
, SPR_NOACCESS
,
1619 &spr_read_generic
, &spr_write_generic
,
1621 /* XXX : not implemented */
1622 spr_register(env
, SPR_440_INV0
, "INV0",
1623 SPR_NOACCESS
, SPR_NOACCESS
,
1624 &spr_read_generic
, &spr_write_generic
,
1626 /* XXX : not implemented */
1627 spr_register(env
, SPR_440_INV1
, "INV1",
1628 SPR_NOACCESS
, SPR_NOACCESS
,
1629 &spr_read_generic
, &spr_write_generic
,
1631 /* XXX : not implemented */
1632 spr_register(env
, SPR_440_INV2
, "INV2",
1633 SPR_NOACCESS
, SPR_NOACCESS
,
1634 &spr_read_generic
, &spr_write_generic
,
1636 /* XXX : not implemented */
1637 spr_register(env
, SPR_440_INV3
, "INV3",
1638 SPR_NOACCESS
, SPR_NOACCESS
,
1639 &spr_read_generic
, &spr_write_generic
,
1641 /* XXX : not implemented */
1642 spr_register(env
, SPR_440_ITV0
, "ITV0",
1643 SPR_NOACCESS
, SPR_NOACCESS
,
1644 &spr_read_generic
, &spr_write_generic
,
1646 /* XXX : not implemented */
1647 spr_register(env
, SPR_440_ITV1
, "ITV1",
1648 SPR_NOACCESS
, SPR_NOACCESS
,
1649 &spr_read_generic
, &spr_write_generic
,
1651 /* XXX : not implemented */
1652 spr_register(env
, SPR_440_ITV2
, "ITV2",
1653 SPR_NOACCESS
, SPR_NOACCESS
,
1654 &spr_read_generic
, &spr_write_generic
,
1656 /* XXX : not implemented */
1657 spr_register(env
, SPR_440_ITV3
, "ITV3",
1658 SPR_NOACCESS
, SPR_NOACCESS
,
1659 &spr_read_generic
, &spr_write_generic
,
1661 /* XXX : not implemented */
1662 spr_register(env
, SPR_440_IVLIM
, "IVLIM",
1663 SPR_NOACCESS
, SPR_NOACCESS
,
1664 &spr_read_generic
, &spr_write_generic
,
1667 /* XXX : not implemented */
1668 spr_register(env
, SPR_BOOKE_DCDBTRH
, "DCDBTRH",
1669 SPR_NOACCESS
, SPR_NOACCESS
,
1670 &spr_read_generic
, SPR_NOACCESS
,
1672 /* XXX : not implemented */
1673 spr_register(env
, SPR_BOOKE_DCDBTRL
, "DCDBTRL",
1674 SPR_NOACCESS
, SPR_NOACCESS
,
1675 &spr_read_generic
, SPR_NOACCESS
,
1677 /* XXX : not implemented */
1678 spr_register(env
, SPR_BOOKE_ICDBDR
, "ICDBDR",
1679 SPR_NOACCESS
, SPR_NOACCESS
,
1680 &spr_read_generic
, SPR_NOACCESS
,
1682 /* XXX : not implemented */
1683 spr_register(env
, SPR_BOOKE_ICDBTRH
, "ICDBTRH",
1684 SPR_NOACCESS
, SPR_NOACCESS
,
1685 &spr_read_generic
, SPR_NOACCESS
,
1687 /* XXX : not implemented */
1688 spr_register(env
, SPR_BOOKE_ICDBTRL
, "ICDBTRL",
1689 SPR_NOACCESS
, SPR_NOACCESS
,
1690 &spr_read_generic
, SPR_NOACCESS
,
1692 /* XXX : not implemented */
1693 spr_register(env
, SPR_440_DBDR
, "DBDR",
1694 SPR_NOACCESS
, SPR_NOACCESS
,
1695 &spr_read_generic
, &spr_write_generic
,
1697 /* Processor control */
1698 spr_register(env
, SPR_4xx_CCR0
, "CCR0",
1699 SPR_NOACCESS
, SPR_NOACCESS
,
1700 &spr_read_generic
, &spr_write_generic
,
1702 spr_register(env
, SPR_440_RSTCFG
, "RSTCFG",
1703 SPR_NOACCESS
, SPR_NOACCESS
,
1704 &spr_read_generic
, SPR_NOACCESS
,
1706 /* Storage control */
1707 spr_register(env
, SPR_440_MMUCR
, "MMUCR",
1708 SPR_NOACCESS
, SPR_NOACCESS
,
1709 &spr_read_generic
, &spr_write_generic
,
1713 /* SPR shared between PowerPC 40x implementations */
1714 static void gen_spr_40x (CPUPPCState
*env
)
1717 /* XXX : not implemented */
1718 spr_register(env
, SPR_40x_DCCR
, "DCCR",
1719 SPR_NOACCESS
, SPR_NOACCESS
,
1720 &spr_read_generic
, &spr_write_generic
,
1722 /* XXX : not implemented */
1723 spr_register(env
, SPR_40x_ICCR
, "ICCR",
1724 SPR_NOACCESS
, SPR_NOACCESS
,
1725 &spr_read_generic
, &spr_write_generic
,
1727 /* XXX : not implemented */
1728 spr_register(env
, SPR_BOOKE_ICDBDR
, "ICDBDR",
1729 SPR_NOACCESS
, SPR_NOACCESS
,
1730 &spr_read_generic
, SPR_NOACCESS
,
1733 spr_register(env
, SPR_40x_DEAR
, "DEAR",
1734 SPR_NOACCESS
, SPR_NOACCESS
,
1735 &spr_read_generic
, &spr_write_generic
,
1737 spr_register(env
, SPR_40x_ESR
, "ESR",
1738 SPR_NOACCESS
, SPR_NOACCESS
,
1739 &spr_read_generic
, &spr_write_generic
,
1741 spr_register(env
, SPR_40x_EVPR
, "EVPR",
1742 SPR_NOACCESS
, SPR_NOACCESS
,
1743 &spr_read_generic
, &spr_write_generic
,
1745 spr_register(env
, SPR_40x_SRR2
, "SRR2",
1746 &spr_read_generic
, &spr_write_generic
,
1747 &spr_read_generic
, &spr_write_generic
,
1749 spr_register(env
, SPR_40x_SRR3
, "SRR3",
1750 &spr_read_generic
, &spr_write_generic
,
1751 &spr_read_generic
, &spr_write_generic
,
1754 spr_register(env
, SPR_40x_PIT
, "PIT",
1755 SPR_NOACCESS
, SPR_NOACCESS
,
1756 &spr_read_40x_pit
, &spr_write_40x_pit
,
1758 spr_register(env
, SPR_40x_TCR
, "TCR",
1759 SPR_NOACCESS
, SPR_NOACCESS
,
1760 &spr_read_generic
, &spr_write_booke_tcr
,
1762 spr_register(env
, SPR_40x_TSR
, "TSR",
1763 SPR_NOACCESS
, SPR_NOACCESS
,
1764 &spr_read_generic
, &spr_write_booke_tsr
,
1768 /* SPR specific to PowerPC 405 implementation */
1769 static void gen_spr_405 (CPUPPCState
*env
)
1772 spr_register(env
, SPR_40x_PID
, "PID",
1773 SPR_NOACCESS
, SPR_NOACCESS
,
1774 &spr_read_generic
, &spr_write_generic
,
1776 spr_register(env
, SPR_4xx_CCR0
, "CCR0",
1777 SPR_NOACCESS
, SPR_NOACCESS
,
1778 &spr_read_generic
, &spr_write_generic
,
1780 /* Debug interface */
1781 /* XXX : not implemented */
1782 spr_register(env
, SPR_40x_DBCR0
, "DBCR0",
1783 SPR_NOACCESS
, SPR_NOACCESS
,
1784 &spr_read_generic
, &spr_write_40x_dbcr0
,
1786 /* XXX : not implemented */
1787 spr_register(env
, SPR_405_DBCR1
, "DBCR1",
1788 SPR_NOACCESS
, SPR_NOACCESS
,
1789 &spr_read_generic
, &spr_write_generic
,
1791 /* XXX : not implemented */
1792 spr_register(env
, SPR_40x_DBSR
, "DBSR",
1793 SPR_NOACCESS
, SPR_NOACCESS
,
1794 &spr_read_generic
, &spr_write_clear
,
1795 /* Last reset was system reset */
1797 /* XXX : not implemented */
1798 spr_register(env
, SPR_40x_DAC1
, "DAC1",
1799 SPR_NOACCESS
, SPR_NOACCESS
,
1800 &spr_read_generic
, &spr_write_generic
,
1802 spr_register(env
, SPR_40x_DAC2
, "DAC2",
1803 SPR_NOACCESS
, SPR_NOACCESS
,
1804 &spr_read_generic
, &spr_write_generic
,
1806 /* XXX : not implemented */
1807 spr_register(env
, SPR_405_DVC1
, "DVC1",
1808 SPR_NOACCESS
, SPR_NOACCESS
,
1809 &spr_read_generic
, &spr_write_generic
,
1811 /* XXX : not implemented */
1812 spr_register(env
, SPR_405_DVC2
, "DVC2",
1813 SPR_NOACCESS
, SPR_NOACCESS
,
1814 &spr_read_generic
, &spr_write_generic
,
1816 /* XXX : not implemented */
1817 spr_register(env
, SPR_40x_IAC1
, "IAC1",
1818 SPR_NOACCESS
, SPR_NOACCESS
,
1819 &spr_read_generic
, &spr_write_generic
,
1821 spr_register(env
, SPR_40x_IAC2
, "IAC2",
1822 SPR_NOACCESS
, SPR_NOACCESS
,
1823 &spr_read_generic
, &spr_write_generic
,
1825 /* XXX : not implemented */
1826 spr_register(env
, SPR_405_IAC3
, "IAC3",
1827 SPR_NOACCESS
, SPR_NOACCESS
,
1828 &spr_read_generic
, &spr_write_generic
,
1830 /* XXX : not implemented */
1831 spr_register(env
, SPR_405_IAC4
, "IAC4",
1832 SPR_NOACCESS
, SPR_NOACCESS
,
1833 &spr_read_generic
, &spr_write_generic
,
1835 /* Storage control */
1836 spr_register(env
, SPR_405_SLER
, "SLER",
1837 SPR_NOACCESS
, SPR_NOACCESS
,
1838 &spr_read_generic
, &spr_write_40x_sler
,
1840 spr_register(env
, SPR_40x_ZPR
, "ZPR",
1841 SPR_NOACCESS
, SPR_NOACCESS
,
1842 &spr_read_generic
, &spr_write_generic
,
1844 /* XXX : not implemented */
1845 spr_register(env
, SPR_405_SU0R
, "SU0R",
1846 SPR_NOACCESS
, SPR_NOACCESS
,
1847 &spr_read_generic
, &spr_write_generic
,
1850 spr_register(env
, SPR_USPRG0
, "USPRG0",
1851 &spr_read_ureg
, SPR_NOACCESS
,
1852 &spr_read_ureg
, SPR_NOACCESS
,
1854 spr_register(env
, SPR_SPRG4
, "SPRG4",
1855 SPR_NOACCESS
, SPR_NOACCESS
,
1856 &spr_read_generic
, &spr_write_generic
,
1858 spr_register(env
, SPR_USPRG4
, "USPRG4",
1859 &spr_read_ureg
, SPR_NOACCESS
,
1860 &spr_read_ureg
, SPR_NOACCESS
,
1862 spr_register(env
, SPR_SPRG5
, "SPRG5",
1863 SPR_NOACCESS
, SPR_NOACCESS
,
1864 spr_read_generic
, &spr_write_generic
,
1866 spr_register(env
, SPR_USPRG5
, "USPRG5",
1867 &spr_read_ureg
, SPR_NOACCESS
,
1868 &spr_read_ureg
, SPR_NOACCESS
,
1870 spr_register(env
, SPR_SPRG6
, "SPRG6",
1871 SPR_NOACCESS
, SPR_NOACCESS
,
1872 spr_read_generic
, &spr_write_generic
,
1874 spr_register(env
, SPR_USPRG6
, "USPRG6",
1875 &spr_read_ureg
, SPR_NOACCESS
,
1876 &spr_read_ureg
, SPR_NOACCESS
,
1878 spr_register(env
, SPR_SPRG7
, "SPRG7",
1879 SPR_NOACCESS
, SPR_NOACCESS
,
1880 spr_read_generic
, &spr_write_generic
,
1882 spr_register(env
, SPR_USPRG7
, "USPRG7",
1883 &spr_read_ureg
, SPR_NOACCESS
,
1884 &spr_read_ureg
, SPR_NOACCESS
,
1888 /* SPR shared between PowerPC 401 & 403 implementations */
1889 static void gen_spr_401_403 (CPUPPCState
*env
)
1892 spr_register(env
, SPR_403_VTBL
, "TBL",
1893 &spr_read_tbl
, SPR_NOACCESS
,
1894 &spr_read_tbl
, SPR_NOACCESS
,
1896 spr_register(env
, SPR_403_TBL
, "TBL",
1897 SPR_NOACCESS
, SPR_NOACCESS
,
1898 SPR_NOACCESS
, &spr_write_tbl
,
1900 spr_register(env
, SPR_403_VTBU
, "TBU",
1901 &spr_read_tbu
, SPR_NOACCESS
,
1902 &spr_read_tbu
, SPR_NOACCESS
,
1904 spr_register(env
, SPR_403_TBU
, "TBU",
1905 SPR_NOACCESS
, SPR_NOACCESS
,
1906 SPR_NOACCESS
, &spr_write_tbu
,
1909 /* XXX: not implemented */
1910 spr_register(env
, SPR_403_CDBCR
, "CDBCR",
1911 SPR_NOACCESS
, SPR_NOACCESS
,
1912 &spr_read_generic
, &spr_write_generic
,
1916 /* SPR specific to PowerPC 401 implementation */
1917 static void gen_spr_401 (CPUPPCState
*env
)
1919 /* Debug interface */
1920 /* XXX : not implemented */
1921 spr_register(env
, SPR_40x_DBCR0
, "DBCR",
1922 SPR_NOACCESS
, SPR_NOACCESS
,
1923 &spr_read_generic
, &spr_write_40x_dbcr0
,
1925 /* XXX : not implemented */
1926 spr_register(env
, SPR_40x_DBSR
, "DBSR",
1927 SPR_NOACCESS
, SPR_NOACCESS
,
1928 &spr_read_generic
, &spr_write_clear
,
1929 /* Last reset was system reset */
1931 /* XXX : not implemented */
1932 spr_register(env
, SPR_40x_DAC1
, "DAC",
1933 SPR_NOACCESS
, SPR_NOACCESS
,
1934 &spr_read_generic
, &spr_write_generic
,
1936 /* XXX : not implemented */
1937 spr_register(env
, SPR_40x_IAC1
, "IAC",
1938 SPR_NOACCESS
, SPR_NOACCESS
,
1939 &spr_read_generic
, &spr_write_generic
,
1941 /* Storage control */
1942 spr_register(env
, SPR_405_SLER
, "SLER",
1943 SPR_NOACCESS
, SPR_NOACCESS
,
1944 &spr_read_generic
, &spr_write_40x_sler
,
1948 static void gen_spr_401x2 (CPUPPCState
*env
)
1951 spr_register(env
, SPR_40x_PID
, "PID",
1952 SPR_NOACCESS
, SPR_NOACCESS
,
1953 &spr_read_generic
, &spr_write_generic
,
1955 spr_register(env
, SPR_40x_ZPR
, "ZPR",
1956 SPR_NOACCESS
, SPR_NOACCESS
,
1957 &spr_read_generic
, &spr_write_generic
,
1961 /* SPR specific to PowerPC 403 implementation */
1962 static void gen_spr_403 (CPUPPCState
*env
)
1964 /* Debug interface */
1965 /* XXX : not implemented */
1966 spr_register(env
, SPR_40x_DBCR0
, "DBCR0",
1967 SPR_NOACCESS
, SPR_NOACCESS
,
1968 &spr_read_generic
, &spr_write_40x_dbcr0
,
1970 /* XXX : not implemented */
1971 spr_register(env
, SPR_40x_DBSR
, "DBSR",
1972 SPR_NOACCESS
, SPR_NOACCESS
,
1973 &spr_read_generic
, &spr_write_clear
,
1974 /* Last reset was system reset */
1976 /* XXX : not implemented */
1977 spr_register(env
, SPR_40x_DAC1
, "DAC1",
1978 SPR_NOACCESS
, SPR_NOACCESS
,
1979 &spr_read_generic
, &spr_write_generic
,
1981 spr_register(env
, SPR_40x_DAC2
, "DAC2",
1982 SPR_NOACCESS
, SPR_NOACCESS
,
1983 &spr_read_generic
, &spr_write_generic
,
1985 /* XXX : not implemented */
1986 spr_register(env
, SPR_40x_IAC1
, "IAC1",
1987 SPR_NOACCESS
, SPR_NOACCESS
,
1988 &spr_read_generic
, &spr_write_generic
,
1990 spr_register(env
, SPR_40x_IAC2
, "IAC2",
1991 SPR_NOACCESS
, SPR_NOACCESS
,
1992 &spr_read_generic
, &spr_write_generic
,
1996 static void gen_spr_403_real (CPUPPCState
*env
)
1998 spr_register(env
, SPR_403_PBL1
, "PBL1",
1999 SPR_NOACCESS
, SPR_NOACCESS
,
2000 &spr_read_403_pbr
, &spr_write_403_pbr
,
2002 spr_register(env
, SPR_403_PBU1
, "PBU1",
2003 SPR_NOACCESS
, SPR_NOACCESS
,
2004 &spr_read_403_pbr
, &spr_write_403_pbr
,
2006 spr_register(env
, SPR_403_PBL2
, "PBL2",
2007 SPR_NOACCESS
, SPR_NOACCESS
,
2008 &spr_read_403_pbr
, &spr_write_403_pbr
,
2010 spr_register(env
, SPR_403_PBU2
, "PBU2",
2011 SPR_NOACCESS
, SPR_NOACCESS
,
2012 &spr_read_403_pbr
, &spr_write_403_pbr
,
2016 static void gen_spr_403_mmu (CPUPPCState
*env
)
2019 spr_register(env
, SPR_40x_PID
, "PID",
2020 SPR_NOACCESS
, SPR_NOACCESS
,
2021 &spr_read_generic
, &spr_write_generic
,
2023 spr_register(env
, SPR_40x_ZPR
, "ZPR",
2024 SPR_NOACCESS
, SPR_NOACCESS
,
2025 &spr_read_generic
, &spr_write_generic
,
2029 /* SPR specific to PowerPC compression coprocessor extension */
2030 static void gen_spr_compress (CPUPPCState
*env
)
2032 spr_register(env
, SPR_401_SKR
, "SKR",
2033 SPR_NOACCESS
, SPR_NOACCESS
,
2034 &spr_read_generic
, &spr_write_generic
,
2038 #if defined (TARGET_PPC64)
2040 /* SPR specific to PowerPC 620 */
2041 static void gen_spr_620 (CPUPPCState
*env
)
2043 spr_register(env
, SPR_620_PMR0
, "PMR0",
2044 SPR_NOACCESS
, SPR_NOACCESS
,
2045 &spr_read_generic
, &spr_write_generic
,
2047 spr_register(env
, SPR_620_PMR1
, "PMR1",
2048 SPR_NOACCESS
, SPR_NOACCESS
,
2049 &spr_read_generic
, &spr_write_generic
,
2051 spr_register(env
, SPR_620_PMR2
, "PMR2",
2052 SPR_NOACCESS
, SPR_NOACCESS
,
2053 &spr_read_generic
, &spr_write_generic
,
2055 spr_register(env
, SPR_620_PMR3
, "PMR3",
2056 SPR_NOACCESS
, SPR_NOACCESS
,
2057 &spr_read_generic
, &spr_write_generic
,
2059 spr_register(env
, SPR_620_PMR4
, "PMR4",
2060 SPR_NOACCESS
, SPR_NOACCESS
,
2061 &spr_read_generic
, &spr_write_generic
,
2063 spr_register(env
, SPR_620_PMR5
, "PMR5",
2064 SPR_NOACCESS
, SPR_NOACCESS
,
2065 &spr_read_generic
, &spr_write_generic
,
2067 spr_register(env
, SPR_620_PMR6
, "PMR6",
2068 SPR_NOACCESS
, SPR_NOACCESS
,
2069 &spr_read_generic
, &spr_write_generic
,
2071 spr_register(env
, SPR_620_PMR7
, "PMR7",
2072 SPR_NOACCESS
, SPR_NOACCESS
,
2073 &spr_read_generic
, &spr_write_generic
,
2075 spr_register(env
, SPR_620_PMR8
, "PMR8",
2076 SPR_NOACCESS
, SPR_NOACCESS
,
2077 &spr_read_generic
, &spr_write_generic
,
2079 spr_register(env
, SPR_620_PMR9
, "PMR9",
2080 SPR_NOACCESS
, SPR_NOACCESS
,
2081 &spr_read_generic
, &spr_write_generic
,
2083 spr_register(env
, SPR_620_PMRA
, "PMR10",
2084 SPR_NOACCESS
, SPR_NOACCESS
,
2085 &spr_read_generic
, &spr_write_generic
,
2087 spr_register(env
, SPR_620_PMRB
, "PMR11",
2088 SPR_NOACCESS
, SPR_NOACCESS
,
2089 &spr_read_generic
, &spr_write_generic
,
2091 spr_register(env
, SPR_620_PMRC
, "PMR12",
2092 SPR_NOACCESS
, SPR_NOACCESS
,
2093 &spr_read_generic
, &spr_write_generic
,
2095 spr_register(env
, SPR_620_PMRD
, "PMR13",
2096 SPR_NOACCESS
, SPR_NOACCESS
,
2097 &spr_read_generic
, &spr_write_generic
,
2099 spr_register(env
, SPR_620_PMRE
, "PMR14",
2100 SPR_NOACCESS
, SPR_NOACCESS
,
2101 &spr_read_generic
, &spr_write_generic
,
2103 spr_register(env
, SPR_620_PMRF
, "PMR15",
2104 SPR_NOACCESS
, SPR_NOACCESS
,
2105 &spr_read_generic
, &spr_write_generic
,
2107 spr_register(env
, SPR_620_HID8
, "HID8",
2108 SPR_NOACCESS
, SPR_NOACCESS
,
2109 &spr_read_generic
, &spr_write_generic
,
2111 spr_register(env
, SPR_620_HID9
, "HID9",
2112 SPR_NOACCESS
, SPR_NOACCESS
,
2113 &spr_read_generic
, &spr_write_generic
,
2117 #endif /* defined (TARGET_PPC64) */
2121 * AMR => SPR 29 (Power 2.04)
2122 * CTRL => SPR 136 (Power 2.04)
2123 * CTRL => SPR 152 (Power 2.04)
2124 * SCOMC => SPR 276 (64 bits ?)
2125 * SCOMD => SPR 277 (64 bits ?)
2126 * ASR => SPR 280 (64 bits)
2127 * TBU40 => SPR 286 (Power 2.04 hypv)
2128 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2129 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2130 * HDSISR => SPR 306 (Power 2.04 hypv)
2131 * HDAR => SPR 307 (Power 2.04 hypv)
2132 * PURR => SPR 309 (Power 2.04 hypv)
2133 * HDEC => SPR 310 (Power 2.04 hypv)
2134 * HIOR => SPR 311 (hypv)
2135 * RMOR => SPR 312 (970)
2136 * HRMOR => SPR 313 (Power 2.04 hypv)
2137 * HSRR0 => SPR 314 (Power 2.04 hypv)
2138 * HSRR1 => SPR 315 (Power 2.04 hypv)
2139 * LPCR => SPR 316 (970)
2140 * LPIDR => SPR 317 (970)
2141 * SPEFSCR => SPR 512 (Power 2.04 emb)
2142 * ATBL => SPR 526 (Power 2.04 emb)
2143 * ATBU => SPR 527 (Power 2.04 emb)
2144 * EPR => SPR 702 (Power 2.04 emb)
2145 * perf => 768-783 (Power 2.04)
2146 * perf => 784-799 (Power 2.04)
2147 * PPR => SPR 896 (Power 2.04)
2148 * EPLC => SPR 947 (Power 2.04 emb)
2149 * EPSC => SPR 948 (Power 2.04 emb)
2150 * DABRX => 1015 (Power 2.04 hypv)
2151 * FPECR => SPR 1022 (?)
2152 * ... and more (thermal management, performance counters, ...)
2155 /*****************************************************************************/
2156 /* Exception vectors models */
2157 static void init_excp_4xx_real (CPUPPCState
*env
)
2159 #if !defined(CONFIG_USER_ONLY)
2160 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000100;
2161 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2162 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2163 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2164 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2165 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2166 env
->excp_vectors
[POWERPC_EXCP_PIT
] = 0x00001000;
2167 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00001010;
2168 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00001020;
2169 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00002000;
2173 static void init_excp_4xx_softmmu (CPUPPCState
*env
)
2175 #if !defined(CONFIG_USER_ONLY)
2176 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000100;
2177 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2178 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2179 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2180 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2181 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2182 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2183 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2184 env
->excp_vectors
[POWERPC_EXCP_PIT
] = 0x00001000;
2185 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00001010;
2186 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00001020;
2187 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00001100;
2188 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00001200;
2189 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00002000;
2193 static void init_excp_BookE (CPUPPCState
*env
)
2195 #if !defined(CONFIG_USER_ONLY)
2196 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000000;
2197 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000000;
2198 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000000;
2199 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000000;
2200 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000000;
2201 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000000;
2202 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000000;
2203 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000000;
2204 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000000;
2205 env
->excp_vectors
[POWERPC_EXCP_APU
] = 0x00000000;
2206 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000000;
2207 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00000000;
2208 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00000000;
2209 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00000000;
2210 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00000000;
2211 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00000000;
2212 env
->excp_prefix
= 0x00000000;
2213 env
->ivor_mask
= 0x0000FFE0;
2214 env
->ivpr_mask
= 0xFFFF0000;
2218 static void init_excp_601 (CPUPPCState
*env
)
2220 #if !defined(CONFIG_USER_ONLY)
2221 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2222 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2223 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2224 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2225 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2226 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2227 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2228 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2229 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2230 env
->excp_vectors
[POWERPC_EXCP_IO
] = 0x00000A00;
2231 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2232 env
->excp_vectors
[POWERPC_EXCP_RUNM
] = 0x00002000;
2233 env
->excp_prefix
= 0xFFF00000;
2237 static void init_excp_602 (CPUPPCState
*env
)
2239 #if !defined(CONFIG_USER_ONLY)
2240 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2241 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2242 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2243 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2244 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2245 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2246 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2247 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2248 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2249 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2250 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2251 env
->excp_vectors
[POWERPC_EXCP_FPA
] = 0x00000E00;
2252 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2253 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2254 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2255 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2256 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2257 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00001500;
2258 env
->excp_vectors
[POWERPC_EXCP_EMUL
] = 0x00001600;
2259 env
->excp_prefix
= 0xFFF00000;
2263 static void init_excp_603 (CPUPPCState
*env
)
2265 #if !defined(CONFIG_USER_ONLY)
2266 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2267 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2268 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2269 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2270 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2271 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2272 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2273 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2274 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2275 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2276 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2277 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2278 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2279 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2280 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2281 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2285 static void init_excp_G2 (CPUPPCState
*env
)
2287 #if !defined(CONFIG_USER_ONLY)
2288 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2289 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2290 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2291 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2292 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2293 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2294 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2295 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2296 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2297 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000A00;
2298 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2299 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2300 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2301 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2302 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2303 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2304 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2308 static void init_excp_604 (CPUPPCState
*env
)
2310 #if !defined(CONFIG_USER_ONLY)
2311 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2312 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2313 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2314 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2315 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2316 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2317 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2318 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2319 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2320 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2321 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2322 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2323 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2324 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2329 static void init_excp_620 (CPUPPCState
*env
)
2331 #if !defined(CONFIG_USER_ONLY)
2332 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2333 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2334 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2335 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2336 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2337 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2338 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2339 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2340 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2341 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2342 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2343 env
->excp_vectors
[POWERPC_EXCP_FPA
] = 0x00000E00;
2344 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2345 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2346 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2349 #endif /* defined (TODO) */
2351 static void init_excp_7x0 (CPUPPCState
*env
)
2353 #if !defined(CONFIG_USER_ONLY)
2354 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2355 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2356 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2357 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2358 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2359 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2360 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2361 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2362 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2363 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2364 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2365 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2366 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2367 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
2371 static void init_excp_750FX (CPUPPCState
*env
)
2373 #if !defined(CONFIG_USER_ONLY)
2374 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2375 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2376 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2377 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2378 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2379 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2380 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2381 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2382 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2383 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2384 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2385 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2386 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2387 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2388 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
2392 static void init_excp_7400 (CPUPPCState
*env
)
2394 #if !defined(CONFIG_USER_ONLY)
2395 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2396 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2397 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2398 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2399 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2400 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2401 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2402 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2403 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2404 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2405 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2406 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2407 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
2408 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2409 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2410 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001600;
2411 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
2416 static void init_excp_7450 (CPUPPCState
*env
)
2418 #if !defined(CONFIG_USER_ONLY)
2419 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2420 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2421 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2422 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2423 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2424 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2425 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2426 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2427 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2428 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2429 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2430 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2431 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
2432 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2433 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2434 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2435 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2436 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2437 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001600;
2440 #endif /* defined (TODO) */
2442 #if defined (TARGET_PPC64)
2443 static void init_excp_970 (CPUPPCState
*env
)
2445 #if !defined(CONFIG_USER_ONLY)
2446 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2447 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2448 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2449 env
->excp_vectors
[POWERPC_EXCP_DSEG
] = 0x00000380;
2450 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2451 env
->excp_vectors
[POWERPC_EXCP_ISEG
] = 0x00000480;
2452 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2453 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2454 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2455 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2456 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2457 #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2458 env
->excp_vectors
[POWERPC_EXCP_HDECR
] = 0x00000980;
2460 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2461 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2462 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2463 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
2464 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2465 env
->excp_vectors
[POWERPC_EXCP_MAINT
] = 0x00001600;
2466 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001700;
2467 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001800;
2472 /*****************************************************************************/
2473 /* PowerPC implementations definitions */
2475 /* PowerPC 40x instruction set */
2476 #define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_EMB_COMMON)
2479 #define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | \
2480 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2481 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2482 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
2483 #define POWERPC_MMU_401 (POWERPC_MMU_REAL_4xx)
2484 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
2485 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
2486 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
2488 static void init_proc_401 (CPUPPCState
*env
)
2491 gen_spr_401_403(env
);
2493 /* Bus access control */
2494 spr_register(env
, SPR_40x_SGR
, "SGR",
2495 SPR_NOACCESS
, SPR_NOACCESS
,
2496 &spr_read_generic
, &spr_write_generic
,
2498 /* XXX : not implemented */
2499 spr_register(env
, SPR_40x_DCWR
, "DCWR",
2500 SPR_NOACCESS
, SPR_NOACCESS
,
2501 &spr_read_generic
, &spr_write_generic
,
2503 init_excp_4xx_real(env
);
2504 /* XXX: TODO: allocate internal IRQ controller */
2508 #define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | \
2509 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2510 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2511 PPC_CACHE_DCBA | PPC_MFTB | \
2512 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2513 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
2514 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
2515 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
2516 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
2517 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
2519 static void init_proc_401x2 (CPUPPCState
*env
)
2522 gen_spr_401_403(env
);
2524 gen_spr_compress(env
);
2525 /* Bus access control */
2526 spr_register(env
, SPR_40x_SGR
, "SGR",
2527 SPR_NOACCESS
, SPR_NOACCESS
,
2528 &spr_read_generic
, &spr_write_generic
,
2530 /* XXX : not implemented */
2531 spr_register(env
, SPR_40x_DCWR
, "DCWR",
2532 SPR_NOACCESS
, SPR_NOACCESS
,
2533 &spr_read_generic
, &spr_write_generic
,
2535 /* Memory management */
2539 init_excp_4xx_softmmu(env
);
2540 /* XXX: TODO: allocate internal IRQ controller */
2545 #define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | \
2546 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2547 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2548 PPC_CACHE_DCBA | PPC_MFTB | \
2549 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2550 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
2551 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
2552 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
2553 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
2554 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
2556 static void init_proc_401x3 (CPUPPCState
*env
)
2558 init_excp_4xx_softmmu(env
);
2563 #define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | \
2564 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2565 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2567 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2568 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
2569 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
2570 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
2571 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
2572 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
2574 static void init_proc_IOP480 (CPUPPCState
*env
)
2577 gen_spr_401_403(env
);
2579 gen_spr_compress(env
);
2580 /* Bus access control */
2581 spr_register(env
, SPR_40x_SGR
, "SGR",
2582 SPR_NOACCESS
, SPR_NOACCESS
,
2583 &spr_read_generic
, &spr_write_generic
,
2585 /* XXX : not implemented */
2586 spr_register(env
, SPR_40x_DCWR
, "DCWR",
2587 SPR_NOACCESS
, SPR_NOACCESS
,
2588 &spr_read_generic
, &spr_write_generic
,
2590 /* Memory management */
2594 init_excp_4xx_softmmu(env
);
2595 /* XXX: TODO: allocate internal IRQ controller */
2599 #define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | \
2600 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2601 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2602 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2603 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
2604 #define POWERPC_MMU_403 (POWERPC_MMU_REAL_4xx)
2605 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
2606 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
2607 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
2609 static void init_proc_403 (CPUPPCState
*env
)
2612 gen_spr_401_403(env
);
2614 gen_spr_403_real(env
);
2615 init_excp_4xx_real(env
);
2616 /* XXX: TODO: allocate internal IRQ controller */
2619 /* PowerPC 403 GCX */
2620 #define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | \
2621 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2622 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2623 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2624 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
2625 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
2626 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
2627 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
2628 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
2630 static void init_proc_403GCX (CPUPPCState
*env
)
2633 gen_spr_401_403(env
);
2635 gen_spr_403_real(env
);
2636 gen_spr_403_mmu(env
);
2637 /* Bus access control */
2638 spr_register(env
, SPR_40x_SGR
, "SGR",
2639 SPR_NOACCESS
, SPR_NOACCESS
,
2640 &spr_read_generic
, &spr_write_generic
,
2642 /* XXX : not implemented */
2643 spr_register(env
, SPR_40x_DCWR
, "DCWR",
2644 SPR_NOACCESS
, SPR_NOACCESS
,
2645 &spr_read_generic
, &spr_write_generic
,
2647 /* Memory management */
2651 init_excp_4xx_softmmu(env
);
2652 /* XXX: TODO: allocate internal IRQ controller */
2656 #define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_MFTB | \
2657 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2658 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2659 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
2661 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
2662 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
2663 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
2664 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
2665 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
2667 static void init_proc_405 (CPUPPCState
*env
)
2673 /* Bus access control */
2674 spr_register(env
, SPR_40x_SGR
, "SGR",
2675 SPR_NOACCESS
, SPR_NOACCESS
,
2676 &spr_read_generic
, &spr_write_generic
,
2678 /* XXX : not implemented */
2679 spr_register(env
, SPR_40x_DCWR
, "DCWR",
2680 SPR_NOACCESS
, SPR_NOACCESS
,
2681 &spr_read_generic
, &spr_write_generic
,
2683 /* Memory management */
2687 init_excp_4xx_softmmu(env
);
2688 /* Allocate hardware IRQ controller */
2689 ppc405_irq_init(env
);
2692 /* PowerPC 440 EP */
2693 #define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | \
2694 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2695 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2696 PPC_440_SPEC | PPC_RFMCI)
2697 #define POWERPC_MSRM_440EP (0x000000000006D630ULL)
2698 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
2699 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
2700 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
2701 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
2703 static void init_proc_440EP (CPUPPCState
*env
)
2709 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
2710 SPR_NOACCESS
, SPR_NOACCESS
,
2711 &spr_read_generic
, &spr_write_generic
,
2713 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
2714 SPR_NOACCESS
, SPR_NOACCESS
,
2715 &spr_read_generic
, &spr_write_generic
,
2717 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
2718 SPR_NOACCESS
, SPR_NOACCESS
,
2719 &spr_read_generic
, &spr_write_generic
,
2721 spr_register(env
, SPR_440_CCR1
, "CCR1",
2722 SPR_NOACCESS
, SPR_NOACCESS
,
2723 &spr_read_generic
, &spr_write_generic
,
2725 /* Memory management */
2729 init_excp_BookE(env
);
2730 /* XXX: TODO: allocate internal IRQ controller */
2733 /* PowerPC 440 GP */
2734 #define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | \
2735 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2736 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2737 PPC_405_MAC | PPC_440_SPEC)
2738 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
2739 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
2740 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
2741 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
2742 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
2744 static void init_proc_440GP (CPUPPCState
*env
)
2750 /* Memory management */
2754 init_excp_BookE(env
);
2755 /* XXX: TODO: allocate internal IRQ controller */
2760 #define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | \
2761 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2762 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2764 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
2765 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
2766 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
2767 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
2768 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
2770 static void init_proc_440x4 (CPUPPCState
*env
)
2776 /* Memory management */
2780 init_excp_BookE(env
);
2781 /* XXX: TODO: allocate internal IRQ controller */
2786 #define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | \
2787 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2788 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2789 PPC_440_SPEC | PPC_RFMCI)
2790 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
2791 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
2792 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
2793 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
2794 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
2796 static void init_proc_440x5 (CPUPPCState
*env
)
2802 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
2803 SPR_NOACCESS
, SPR_NOACCESS
,
2804 &spr_read_generic
, &spr_write_generic
,
2806 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
2807 SPR_NOACCESS
, SPR_NOACCESS
,
2808 &spr_read_generic
, &spr_write_generic
,
2810 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
2811 SPR_NOACCESS
, SPR_NOACCESS
,
2812 &spr_read_generic
, &spr_write_generic
,
2814 spr_register(env
, SPR_440_CCR1
, "CCR1",
2815 SPR_NOACCESS
, SPR_NOACCESS
,
2816 &spr_read_generic
, &spr_write_generic
,
2818 /* Memory management */
2822 init_excp_BookE(env
);
2823 /* XXX: TODO: allocate internal IRQ controller */
2826 /* PowerPC 460 (guessed) */
2828 #define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
2829 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2830 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2831 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
2832 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
2833 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
2834 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
2835 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
2836 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
2838 static void init_proc_460 (CPUPPCState
*env
)
2844 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
2845 SPR_NOACCESS
, SPR_NOACCESS
,
2846 &spr_read_generic
, &spr_write_generic
,
2848 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
2849 SPR_NOACCESS
, SPR_NOACCESS
,
2850 &spr_read_generic
, &spr_write_generic
,
2852 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
2853 SPR_NOACCESS
, SPR_NOACCESS
,
2854 &spr_read_generic
, &spr_write_generic
,
2856 spr_register(env
, SPR_440_CCR1
, "CCR1",
2857 SPR_NOACCESS
, SPR_NOACCESS
,
2858 &spr_read_generic
, &spr_write_generic
,
2860 spr_register(env
, SPR_DCRIPR
, "SPR_DCRIPR",
2861 &spr_read_generic
, &spr_write_generic
,
2862 &spr_read_generic
, &spr_write_generic
,
2864 /* Memory management */
2868 init_excp_BookE(env
);
2869 /* XXX: TODO: allocate internal IRQ controller */
2873 /* PowerPC 460F (guessed) */
2875 #define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
2876 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2877 PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
2878 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
2879 PPC_FLOAT_STFIWX | \
2880 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2881 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
2882 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
2883 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
2884 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
2885 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
2886 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
2888 static void init_proc_460F (CPUPPCState
*env
)
2894 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
2895 SPR_NOACCESS
, SPR_NOACCESS
,
2896 &spr_read_generic
, &spr_write_generic
,
2898 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
2899 SPR_NOACCESS
, SPR_NOACCESS
,
2900 &spr_read_generic
, &spr_write_generic
,
2902 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
2903 SPR_NOACCESS
, SPR_NOACCESS
,
2904 &spr_read_generic
, &spr_write_generic
,
2906 spr_register(env
, SPR_440_CCR1
, "CCR1",
2907 SPR_NOACCESS
, SPR_NOACCESS
,
2908 &spr_read_generic
, &spr_write_generic
,
2910 spr_register(env
, SPR_DCRIPR
, "SPR_DCRIPR",
2911 &spr_read_generic
, &spr_write_generic
,
2912 &spr_read_generic
, &spr_write_generic
,
2914 /* Memory management */
2918 init_excp_BookE(env
);
2919 /* XXX: TODO: allocate internal IRQ controller */
2923 /* Generic BookE PowerPC */
2925 #define POWERPC_INSNS_BookE (POWERPC_INSNS_EMB | \
2926 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
2928 PPC_FLOAT | PPC_FLOAT_FSQRT | \
2929 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
2930 PPC_FLOAT_FSEL | PPC_FLOAT_STFIW | \
2932 #define POWERPC_MSRM_BookE (0x000000000006D630ULL)
2933 #define POWERPC_MMU_BookE (POWERPC_MMU_BOOKE)
2934 #define POWERPC_EXCP_BookE (POWERPC_EXCP_BOOKE)
2935 #define POWERPC_INPUT_BookE (PPC_FLAGS_INPUT_BookE)
2936 #define POWERPC_BFDM_BookE (bfd_mach_ppc_403)
2938 static void init_proc_BookE (CPUPPCState
*env
)
2940 init_excp_BookE(env
);
2954 #define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | \
2955 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
2957 PPC_BOOKE | PPC_E500_VECTOR)
2958 #define POWERPC_MMU_e500 (POWERPC_MMU_SOFT_4xx)
2959 #define POWERPC_EXCP_e500 (POWERPC_EXCP_40x)
2960 #define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
2961 #define POWERPC_BFDM_e500 (bfd_mach_ppc_403)
2963 static void init_proc_e500 (CPUPPCState
*env
)
2968 /* Memory management */
2969 gen_spr_BookE_FSL(env
);
2973 init_excp_BookE(env
);
2974 /* XXX: TODO: allocate internal IRQ controller */
2982 /* Non-embedded PowerPC */
2983 /* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
2984 #define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
2985 PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
2986 /* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */
2987 #define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
2988 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
2989 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
2990 PPC_MEM_TLBSYNC | PPC_MFTB)
2992 /* POWER : same as 601, without mfmsr, mfsr */
2994 #define POWERPC_INSNS_POWER (XXX_TODO)
2995 /* POWER RSC (from RAD6000) */
2996 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
3000 #define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_EXTERN | PPC_POWER_BR)
3001 #define POWERPC_MSRM_601 (0x000000000000FE70ULL)
3002 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
3003 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
3004 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
3005 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
3007 static void init_proc_601 (CPUPPCState
*env
)
3009 gen_spr_ne_601(env
);
3011 /* Hardware implementation registers */
3012 /* XXX : not implemented */
3013 spr_register(env
, SPR_HID0
, "HID0",
3014 SPR_NOACCESS
, SPR_NOACCESS
,
3015 &spr_read_generic
, &spr_write_generic
,
3017 /* XXX : not implemented */
3018 spr_register(env
, SPR_HID1
, "HID1",
3019 SPR_NOACCESS
, SPR_NOACCESS
,
3020 &spr_read_generic
, &spr_write_generic
,
3022 /* XXX : not implemented */
3023 spr_register(env
, SPR_601_HID2
, "HID2",
3024 SPR_NOACCESS
, SPR_NOACCESS
,
3025 &spr_read_generic
, &spr_write_generic
,
3027 /* XXX : not implemented */
3028 spr_register(env
, SPR_601_HID5
, "HID5",
3029 SPR_NOACCESS
, SPR_NOACCESS
,
3030 &spr_read_generic
, &spr_write_generic
,
3032 /* XXX : not implemented */
3033 spr_register(env
, SPR_601_HID15
, "HID15",
3034 SPR_NOACCESS
, SPR_NOACCESS
,
3035 &spr_read_generic
, &spr_write_generic
,
3037 /* Memory management */
3043 /* XXX: TODO: allocate internal IRQ controller */
3047 #define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \
3048 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3049 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3050 PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_602_SPEC)
3051 #define POWERPC_MSRM_602 (0x000000000033FF73ULL)
3052 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
3053 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
3054 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
3055 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
3057 static void init_proc_602 (CPUPPCState
*env
)
3059 gen_spr_ne_601(env
);
3063 /* hardware implementation registers */
3064 /* XXX : not implemented */
3065 spr_register(env
, SPR_HID0
, "HID0",
3066 SPR_NOACCESS
, SPR_NOACCESS
,
3067 &spr_read_generic
, &spr_write_generic
,
3069 /* XXX : not implemented */
3070 spr_register(env
, SPR_HID1
, "HID1",
3071 SPR_NOACCESS
, SPR_NOACCESS
,
3072 &spr_read_generic
, &spr_write_generic
,
3074 /* Memory management */
3076 gen_6xx_7xx_soft_tlb(env
, 64, 2);
3078 /* Allocate hardware IRQ controller */
3079 ppc6xx_irq_init(env
);
3083 #define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3084 #define POWERPC_MSRM_603 (0x000000000001FF73ULL)
3085 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
3086 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
3087 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
3088 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
3090 static void init_proc_603 (CPUPPCState
*env
)
3092 gen_spr_ne_601(env
);
3096 /* hardware implementation registers */
3097 /* XXX : not implemented */
3098 spr_register(env
, SPR_HID0
, "HID0",
3099 SPR_NOACCESS
, SPR_NOACCESS
,
3100 &spr_read_generic
, &spr_write_generic
,
3102 /* XXX : not implemented */
3103 spr_register(env
, SPR_HID1
, "HID1",
3104 SPR_NOACCESS
, SPR_NOACCESS
,
3105 &spr_read_generic
, &spr_write_generic
,
3107 /* Memory management */
3109 gen_6xx_7xx_soft_tlb(env
, 64, 2);
3111 /* Allocate hardware IRQ controller */
3112 ppc6xx_irq_init(env
);
3116 #define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3117 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
3118 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
3119 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
3120 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
3121 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
3123 static void init_proc_603E (CPUPPCState
*env
)
3125 gen_spr_ne_601(env
);
3129 /* hardware implementation registers */
3130 /* XXX : not implemented */
3131 spr_register(env
, SPR_HID0
, "HID0",
3132 SPR_NOACCESS
, SPR_NOACCESS
,
3133 &spr_read_generic
, &spr_write_generic
,
3135 /* XXX : not implemented */
3136 spr_register(env
, SPR_HID1
, "HID1",
3137 SPR_NOACCESS
, SPR_NOACCESS
,
3138 &spr_read_generic
, &spr_write_generic
,
3140 /* XXX : not implemented */
3141 spr_register(env
, SPR_IABR
, "IABR",
3142 SPR_NOACCESS
, SPR_NOACCESS
,
3143 &spr_read_generic
, &spr_write_generic
,
3145 /* Memory management */
3147 gen_6xx_7xx_soft_tlb(env
, 64, 2);
3149 /* Allocate hardware IRQ controller */
3150 ppc6xx_irq_init(env
);
3154 #define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3155 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3156 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3157 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3158 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
3159 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
3161 static void init_proc_G2 (CPUPPCState
*env
)
3163 gen_spr_ne_601(env
);
3164 gen_spr_G2_755(env
);
3168 /* Hardware implementation register */
3169 /* XXX : not implemented */
3170 spr_register(env
, SPR_HID0
, "HID0",
3171 SPR_NOACCESS
, SPR_NOACCESS
,
3172 &spr_read_generic
, &spr_write_generic
,
3174 /* XXX : not implemented */
3175 spr_register(env
, SPR_HID1
, "HID1",
3176 SPR_NOACCESS
, SPR_NOACCESS
,
3177 &spr_read_generic
, &spr_write_generic
,
3179 /* XXX : not implemented */
3180 spr_register(env
, SPR_HID2
, "HID2",
3181 SPR_NOACCESS
, SPR_NOACCESS
,
3182 &spr_read_generic
, &spr_write_generic
,
3184 /* Memory management */
3187 gen_6xx_7xx_soft_tlb(env
, 64, 2);
3189 /* Allocate hardware IRQ controller */
3190 ppc6xx_irq_init(env
);
3194 #define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3195 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3196 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3197 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3198 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
3199 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
3201 static void init_proc_G2LE (CPUPPCState
*env
)
3203 gen_spr_ne_601(env
);
3204 gen_spr_G2_755(env
);
3208 /* Hardware implementation register */
3209 /* XXX : not implemented */
3210 spr_register(env
, SPR_HID0
, "HID0",
3211 SPR_NOACCESS
, SPR_NOACCESS
,
3212 &spr_read_generic
, &spr_write_generic
,
3214 /* XXX : not implemented */
3215 spr_register(env
, SPR_HID1
, "HID1",
3216 SPR_NOACCESS
, SPR_NOACCESS
,
3217 &spr_read_generic
, &spr_write_generic
,
3219 /* XXX : not implemented */
3220 spr_register(env
, SPR_HID2
, "HID2",
3221 SPR_NOACCESS
, SPR_NOACCESS
,
3222 &spr_read_generic
, &spr_write_generic
,
3224 /* Memory management */
3227 gen_6xx_7xx_soft_tlb(env
, 64, 2);
3229 /* Allocate hardware IRQ controller */
3230 ppc6xx_irq_init(env
);
3234 #define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3235 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
3236 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
3237 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
3238 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
3239 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
3241 static void init_proc_604 (CPUPPCState
*env
)
3243 gen_spr_ne_601(env
);
3247 /* Hardware implementation registers */
3248 /* XXX : not implemented */
3249 spr_register(env
, SPR_HID0
, "HID0",
3250 SPR_NOACCESS
, SPR_NOACCESS
,
3251 &spr_read_generic
, &spr_write_generic
,
3253 /* XXX : not implemented */
3254 spr_register(env
, SPR_HID1
, "HID1",
3255 SPR_NOACCESS
, SPR_NOACCESS
,
3256 &spr_read_generic
, &spr_write_generic
,
3258 /* Memory management */
3261 /* Allocate hardware IRQ controller */
3262 ppc6xx_irq_init(env
);
3265 /* PowerPC 740/750 (aka G3) */
3266 #define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3267 #define POWERPC_MSRM_7x0 (0x000000000007FF77ULL)
3268 #define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
3269 //#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
3270 #define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)
3271 #define POWERPC_BFDM_7x0 (bfd_mach_ppc_750)
3273 static void init_proc_7x0 (CPUPPCState
*env
)
3275 gen_spr_ne_601(env
);
3279 /* Thermal management */
3281 /* Hardware implementation registers */
3282 /* XXX : not implemented */
3283 spr_register(env
, SPR_HID0
, "HID0",
3284 SPR_NOACCESS
, SPR_NOACCESS
,
3285 &spr_read_generic
, &spr_write_generic
,
3287 /* XXX : not implemented */
3288 spr_register(env
, SPR_HID1
, "HID1",
3289 SPR_NOACCESS
, SPR_NOACCESS
,
3290 &spr_read_generic
, &spr_write_generic
,
3292 /* Memory management */
3295 /* Allocate hardware IRQ controller */
3296 ppc6xx_irq_init(env
);
3299 /* PowerPC 750FX/GX */
3300 #define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN)
3301 #define POWERPC_MSRM_750fx (0x000000000007FF77ULL)
3302 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
3303 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
3304 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
3305 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
3307 static void init_proc_750fx (CPUPPCState
*env
)
3309 gen_spr_ne_601(env
);
3313 /* Thermal management */
3315 /* Hardware implementation registers */
3316 /* XXX : not implemented */
3317 spr_register(env
, SPR_HID0
, "HID0",
3318 SPR_NOACCESS
, SPR_NOACCESS
,
3319 &spr_read_generic
, &spr_write_generic
,
3321 /* XXX : not implemented */
3322 spr_register(env
, SPR_HID1
, "HID1",
3323 SPR_NOACCESS
, SPR_NOACCESS
,
3324 &spr_read_generic
, &spr_write_generic
,
3326 /* XXX : not implemented */
3327 spr_register(env
, SPR_750_HID2
, "HID2",
3328 SPR_NOACCESS
, SPR_NOACCESS
,
3329 &spr_read_generic
, &spr_write_generic
,
3331 /* Memory management */
3333 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3335 init_excp_750FX(env
);
3336 /* Allocate hardware IRQ controller */
3337 ppc6xx_irq_init(env
);
3340 /* PowerPC 745/755 */
3341 #define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
3342 #define POWERPC_MSRM_7x5 (0x000000000007FF77ULL)
3343 #define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
3344 //#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
3345 #define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)
3346 #define POWERPC_BFDM_7x5 (bfd_mach_ppc_750)
3348 static void init_proc_7x5 (CPUPPCState
*env
)
3350 gen_spr_ne_601(env
);
3351 gen_spr_G2_755(env
);
3354 /* L2 cache control */
3355 /* XXX : not implemented */
3356 spr_register(env
, SPR_ICTC
, "ICTC",
3357 SPR_NOACCESS
, SPR_NOACCESS
,
3358 &spr_read_generic
, &spr_write_generic
,
3360 /* XXX : not implemented */
3361 spr_register(env
, SPR_L2PMCR
, "L2PMCR",
3362 SPR_NOACCESS
, SPR_NOACCESS
,
3363 &spr_read_generic
, &spr_write_generic
,
3365 /* Hardware implementation registers */
3366 /* XXX : not implemented */
3367 spr_register(env
, SPR_HID0
, "HID0",
3368 SPR_NOACCESS
, SPR_NOACCESS
,
3369 &spr_read_generic
, &spr_write_generic
,
3371 /* XXX : not implemented */
3372 spr_register(env
, SPR_HID1
, "HID1",
3373 SPR_NOACCESS
, SPR_NOACCESS
,
3374 &spr_read_generic
, &spr_write_generic
,
3376 /* XXX : not implemented */
3377 spr_register(env
, SPR_HID2
, "HID2",
3378 SPR_NOACCESS
, SPR_NOACCESS
,
3379 &spr_read_generic
, &spr_write_generic
,
3381 /* Memory management */
3384 gen_6xx_7xx_soft_tlb(env
, 64, 2);
3385 /* Allocate hardware IRQ controller */
3386 ppc6xx_irq_init(env
);
3389 /* PowerPC 7400 (aka G4) */
3390 #define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3391 PPC_EXTERN | PPC_MEM_TLBIA | \
3393 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
3394 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
3395 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
3396 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
3397 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
3399 static void init_proc_7400 (CPUPPCState
*env
)
3401 gen_spr_ne_601(env
);
3405 /* 74xx specific SPR */
3407 /* Thermal management */
3409 /* Memory management */
3411 init_excp_7400(env
);
3412 /* Allocate hardware IRQ controller */
3413 ppc6xx_irq_init(env
);
3416 /* PowerPC 7410 (aka G4) */
3417 #define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3418 PPC_EXTERN | PPC_MEM_TLBIA | \
3420 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
3421 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
3422 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
3423 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
3424 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
3426 static void init_proc_7410 (CPUPPCState
*env
)
3428 gen_spr_ne_601(env
);
3432 /* 74xx specific SPR */
3434 /* Thermal management */
3437 /* XXX : not implemented */
3438 spr_register(env
, SPR_L2PMCR
, "L2PMCR",
3439 SPR_NOACCESS
, SPR_NOACCESS
,
3440 &spr_read_generic
, &spr_write_generic
,
3443 /* XXX : not implemented */
3444 spr_register(env
, SPR_LDSTDB
, "LDSTDB",
3445 SPR_NOACCESS
, SPR_NOACCESS
,
3446 &spr_read_generic
, &spr_write_generic
,
3448 /* Memory management */
3450 init_excp_7400(env
);
3451 /* Allocate hardware IRQ controller */
3452 ppc6xx_irq_init(env
);
3455 /* PowerPC 7440 (aka G4) */
3457 #define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3458 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3460 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
3461 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
3462 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
3463 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
3464 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
3466 static void init_proc_7440 (CPUPPCState
*env
)
3468 gen_spr_ne_601(env
);
3472 /* 74xx specific SPR */
3475 /* XXX : not implemented */
3476 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
3477 SPR_NOACCESS
, SPR_NOACCESS
,
3478 &spr_read_generic
, &spr_write_generic
,
3481 /* XXX : not implemented */
3482 spr_register(env
, SPR_ICTRL
, "ICTRL",
3483 SPR_NOACCESS
, SPR_NOACCESS
,
3484 &spr_read_generic
, &spr_write_generic
,
3487 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
3488 SPR_NOACCESS
, SPR_NOACCESS
,
3489 &spr_read_generic
, &spr_write_generic
,
3492 /* XXX : not implemented */
3493 spr_register(env
, SPR_PMC5
, "PMC5",
3494 SPR_NOACCESS
, SPR_NOACCESS
,
3495 &spr_read_generic
, &spr_write_generic
,
3497 spr_register(env
, SPR_UPMC5
, "UPMC5",
3498 &spr_read_ureg
, SPR_NOACCESS
,
3499 &spr_read_ureg
, SPR_NOACCESS
,
3501 spr_register(env
, SPR_PMC6
, "PMC6",
3502 SPR_NOACCESS
, SPR_NOACCESS
,
3503 &spr_read_generic
, &spr_write_generic
,
3505 spr_register(env
, SPR_UPMC6
, "UPMC6",
3506 &spr_read_ureg
, SPR_NOACCESS
,
3507 &spr_read_ureg
, SPR_NOACCESS
,
3509 /* Memory management */
3511 gen_74xx_soft_tlb(env
);
3512 /* Allocate hardware IRQ controller */
3513 ppc6xx_irq_init(env
);
3517 /* PowerPC 7450 (aka G4) */
3519 #define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3520 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3522 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
3523 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
3524 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
3525 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
3526 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
3528 static void init_proc_7450 (CPUPPCState
*env
)
3530 gen_spr_ne_601(env
);
3534 /* 74xx specific SPR */
3536 /* Level 3 cache control */
3539 /* XXX : not implemented */
3540 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
3541 SPR_NOACCESS
, SPR_NOACCESS
,
3542 &spr_read_generic
, &spr_write_generic
,
3545 /* XXX : not implemented */
3546 spr_register(env
, SPR_ICTRL
, "ICTRL",
3547 SPR_NOACCESS
, SPR_NOACCESS
,
3548 &spr_read_generic
, &spr_write_generic
,
3551 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
3552 SPR_NOACCESS
, SPR_NOACCESS
,
3553 &spr_read_generic
, &spr_write_generic
,
3556 /* XXX : not implemented */
3557 spr_register(env
, SPR_PMC5
, "PMC5",
3558 SPR_NOACCESS
, SPR_NOACCESS
,
3559 &spr_read_generic
, &spr_write_generic
,
3561 spr_register(env
, SPR_UPMC5
, "UPMC5",
3562 &spr_read_ureg
, SPR_NOACCESS
,
3563 &spr_read_ureg
, SPR_NOACCESS
,
3565 spr_register(env
, SPR_PMC6
, "PMC6",
3566 SPR_NOACCESS
, SPR_NOACCESS
,
3567 &spr_read_generic
, &spr_write_generic
,
3569 spr_register(env
, SPR_UPMC6
, "UPMC6",
3570 &spr_read_ureg
, SPR_NOACCESS
,
3571 &spr_read_ureg
, SPR_NOACCESS
,
3573 /* Memory management */
3575 gen_74xx_soft_tlb(env
);
3576 init_excp_7450(env
);
3577 /* Allocate hardware IRQ controller */
3578 ppc6xx_irq_init(env
);
3582 /* PowerPC 7445 (aka G4) */
3584 #define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3585 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3587 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
3588 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
3589 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
3590 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
3591 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
3593 static void init_proc_7445 (CPUPPCState
*env
)
3595 gen_spr_ne_601(env
);
3599 /* 74xx specific SPR */
3602 /* XXX : not implemented */
3603 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
3604 SPR_NOACCESS
, SPR_NOACCESS
,
3605 &spr_read_generic
, &spr_write_generic
,
3608 /* XXX : not implemented */
3609 spr_register(env
, SPR_ICTRL
, "ICTRL",
3610 SPR_NOACCESS
, SPR_NOACCESS
,
3611 &spr_read_generic
, &spr_write_generic
,
3614 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
3615 SPR_NOACCESS
, SPR_NOACCESS
,
3616 &spr_read_generic
, &spr_write_generic
,
3619 /* XXX : not implemented */
3620 spr_register(env
, SPR_PMC5
, "PMC5",
3621 SPR_NOACCESS
, SPR_NOACCESS
,
3622 &spr_read_generic
, &spr_write_generic
,
3624 spr_register(env
, SPR_UPMC5
, "UPMC5",
3625 &spr_read_ureg
, SPR_NOACCESS
,
3626 &spr_read_ureg
, SPR_NOACCESS
,
3628 spr_register(env
, SPR_PMC6
, "PMC6",
3629 SPR_NOACCESS
, SPR_NOACCESS
,
3630 &spr_read_generic
, &spr_write_generic
,
3632 spr_register(env
, SPR_UPMC6
, "UPMC6",
3633 &spr_read_ureg
, SPR_NOACCESS
,
3634 &spr_read_ureg
, SPR_NOACCESS
,
3637 spr_register(env
, SPR_SPRG4
, "SPRG4",
3638 SPR_NOACCESS
, SPR_NOACCESS
,
3639 &spr_read_generic
, &spr_write_generic
,
3641 spr_register(env
, SPR_USPRG4
, "USPRG4",
3642 &spr_read_ureg
, SPR_NOACCESS
,
3643 &spr_read_ureg
, SPR_NOACCESS
,
3645 spr_register(env
, SPR_SPRG5
, "SPRG5",
3646 SPR_NOACCESS
, SPR_NOACCESS
,
3647 &spr_read_generic
, &spr_write_generic
,
3649 spr_register(env
, SPR_USPRG5
, "USPRG5",
3650 &spr_read_ureg
, SPR_NOACCESS
,
3651 &spr_read_ureg
, SPR_NOACCESS
,
3653 spr_register(env
, SPR_SPRG6
, "SPRG6",
3654 SPR_NOACCESS
, SPR_NOACCESS
,
3655 &spr_read_generic
, &spr_write_generic
,
3657 spr_register(env
, SPR_USPRG6
, "USPRG6",
3658 &spr_read_ureg
, SPR_NOACCESS
,
3659 &spr_read_ureg
, SPR_NOACCESS
,
3661 spr_register(env
, SPR_SPRG7
, "SPRG7",
3662 SPR_NOACCESS
, SPR_NOACCESS
,
3663 &spr_read_generic
, &spr_write_generic
,
3665 spr_register(env
, SPR_USPRG7
, "USPRG7",
3666 &spr_read_ureg
, SPR_NOACCESS
,
3667 &spr_read_ureg
, SPR_NOACCESS
,
3669 /* Memory management */
3672 gen_74xx_soft_tlb(env
);
3673 init_excp_7450(env
);
3674 /* Allocate hardware IRQ controller */
3675 ppc6xx_irq_init(env
);
3679 /* PowerPC 7455 (aka G4) */
3681 #define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3682 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3684 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
3685 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
3686 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
3687 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
3688 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
3690 static void init_proc_7455 (CPUPPCState
*env
)
3692 gen_spr_ne_601(env
);
3696 /* 74xx specific SPR */
3698 /* Level 3 cache control */
3701 /* XXX : not implemented */
3702 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
3703 SPR_NOACCESS
, SPR_NOACCESS
,
3704 &spr_read_generic
, &spr_write_generic
,
3707 /* XXX : not implemented */
3708 spr_register(env
, SPR_ICTRL
, "ICTRL",
3709 SPR_NOACCESS
, SPR_NOACCESS
,
3710 &spr_read_generic
, &spr_write_generic
,
3713 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
3714 SPR_NOACCESS
, SPR_NOACCESS
,
3715 &spr_read_generic
, &spr_write_generic
,
3718 /* XXX : not implemented */
3719 spr_register(env
, SPR_PMC5
, "PMC5",
3720 SPR_NOACCESS
, SPR_NOACCESS
,
3721 &spr_read_generic
, &spr_write_generic
,
3723 spr_register(env
, SPR_UPMC5
, "UPMC5",
3724 &spr_read_ureg
, SPR_NOACCESS
,
3725 &spr_read_ureg
, SPR_NOACCESS
,
3727 spr_register(env
, SPR_PMC6
, "PMC6",
3728 SPR_NOACCESS
, SPR_NOACCESS
,
3729 &spr_read_generic
, &spr_write_generic
,
3731 spr_register(env
, SPR_UPMC6
, "UPMC6",
3732 &spr_read_ureg
, SPR_NOACCESS
,
3733 &spr_read_ureg
, SPR_NOACCESS
,
3736 spr_register(env
, SPR_SPRG4
, "SPRG4",
3737 SPR_NOACCESS
, SPR_NOACCESS
,
3738 &spr_read_generic
, &spr_write_generic
,
3740 spr_register(env
, SPR_USPRG4
, "USPRG4",
3741 &spr_read_ureg
, SPR_NOACCESS
,
3742 &spr_read_ureg
, SPR_NOACCESS
,
3744 spr_register(env
, SPR_SPRG5
, "SPRG5",
3745 SPR_NOACCESS
, SPR_NOACCESS
,
3746 &spr_read_generic
, &spr_write_generic
,
3748 spr_register(env
, SPR_USPRG5
, "USPRG5",
3749 &spr_read_ureg
, SPR_NOACCESS
,
3750 &spr_read_ureg
, SPR_NOACCESS
,
3752 spr_register(env
, SPR_SPRG6
, "SPRG6",
3753 SPR_NOACCESS
, SPR_NOACCESS
,
3754 &spr_read_generic
, &spr_write_generic
,
3756 spr_register(env
, SPR_USPRG6
, "USPRG6",
3757 &spr_read_ureg
, SPR_NOACCESS
,
3758 &spr_read_ureg
, SPR_NOACCESS
,
3760 spr_register(env
, SPR_SPRG7
, "SPRG7",
3761 SPR_NOACCESS
, SPR_NOACCESS
,
3762 &spr_read_generic
, &spr_write_generic
,
3764 spr_register(env
, SPR_USPRG7
, "USPRG7",
3765 &spr_read_ureg
, SPR_NOACCESS
,
3766 &spr_read_ureg
, SPR_NOACCESS
,
3768 /* Memory management */
3771 gen_74xx_soft_tlb(env
);
3772 init_excp_7450(env
);
3773 /* Allocate hardware IRQ controller */
3774 ppc6xx_irq_init(env
);
3778 #if defined (TARGET_PPC64)
3780 #define POWERPC_INSNS_970 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
3781 PPC_64B | PPC_ALTIVEC | \
3782 PPC_64_BRIDGE | PPC_SLBI)
3783 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
3784 #define POWERPC_MMU_970 (POWERPC_MMU_64BRIDGE)
3785 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
3786 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
3787 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
3789 static void init_proc_970 (CPUPPCState
*env
)
3791 gen_spr_ne_601(env
);
3795 /* Hardware implementation registers */
3796 /* XXX : not implemented */
3797 spr_register(env
, SPR_HID0
, "HID0",
3798 SPR_NOACCESS
, SPR_NOACCESS
,
3799 &spr_read_generic
, &spr_write_generic
,
3801 /* XXX : not implemented */
3802 spr_register(env
, SPR_HID1
, "HID1",
3803 SPR_NOACCESS
, SPR_NOACCESS
,
3804 &spr_read_generic
, &spr_write_generic
,
3806 /* XXX : not implemented */
3807 spr_register(env
, SPR_750_HID2
, "HID2",
3808 SPR_NOACCESS
, SPR_NOACCESS
,
3809 &spr_read_generic
, &spr_write_generic
,
3811 /* Memory management */
3812 /* XXX: not correct */
3818 /* Allocate hardware IRQ controller */
3819 ppc970_irq_init(env
);
3822 /* PowerPC 970FX (aka G5) */
3823 #define POWERPC_INSNS_970FX (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
3824 PPC_64B | PPC_ALTIVEC | \
3825 PPC_64_BRIDGE | PPC_SLBI)
3826 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
3827 #define POWERPC_MMU_970FX (POWERPC_MMU_64BRIDGE)
3828 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
3829 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
3830 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
3832 static void init_proc_970FX (CPUPPCState
*env
)
3834 gen_spr_ne_601(env
);
3838 /* Hardware implementation registers */
3839 /* XXX : not implemented */
3840 spr_register(env
, SPR_HID0
, "HID0",
3841 SPR_NOACCESS
, SPR_NOACCESS
,
3842 &spr_read_generic
, &spr_write_generic
,
3844 /* XXX : not implemented */
3845 spr_register(env
, SPR_HID1
, "HID1",
3846 SPR_NOACCESS
, SPR_NOACCESS
,
3847 &spr_read_generic
, &spr_write_generic
,
3849 /* XXX : not implemented */
3850 spr_register(env
, SPR_750_HID2
, "HID2",
3851 SPR_NOACCESS
, SPR_NOACCESS
,
3852 &spr_read_generic
, &spr_write_generic
,
3854 /* Memory management */
3855 /* XXX: not correct */
3861 /* Allocate hardware IRQ controller */
3862 ppc970_irq_init(env
);
3865 /* PowerPC 970 GX */
3866 #define POWERPC_INSNS_970GX (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
3867 PPC_64B | PPC_ALTIVEC | \
3868 PPC_64_BRIDGE | PPC_SLBI)
3869 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
3870 #define POWERPC_MMU_970GX (POWERPC_MMU_64BRIDGE)
3871 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
3872 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
3873 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
3875 static void init_proc_970GX (CPUPPCState
*env
)
3877 gen_spr_ne_601(env
);
3881 /* Hardware implementation registers */
3882 /* XXX : not implemented */
3883 spr_register(env
, SPR_HID0
, "HID0",
3884 SPR_NOACCESS
, SPR_NOACCESS
,
3885 &spr_read_generic
, &spr_write_generic
,
3887 /* XXX : not implemented */
3888 spr_register(env
, SPR_HID1
, "HID1",
3889 SPR_NOACCESS
, SPR_NOACCESS
,
3890 &spr_read_generic
, &spr_write_generic
,
3892 /* XXX : not implemented */
3893 spr_register(env
, SPR_750_HID2
, "HID2",
3894 SPR_NOACCESS
, SPR_NOACCESS
,
3895 &spr_read_generic
, &spr_write_generic
,
3897 /* Memory management */
3898 /* XXX: not correct */
3904 /* Allocate hardware IRQ controller */
3905 ppc970_irq_init(env
);
3910 #define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
3912 #define POWERPC_MSRM_620 (0x800000000005FF73ULL)
3913 #define POWERPC_MMU_620 (POWERPC_MMU_64B)
3914 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
3915 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_970)
3916 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
3918 static void init_proc_620 (CPUPPCState
*env
)
3920 gen_spr_ne_601(env
);
3924 /* Hardware implementation registers */
3925 /* XXX : not implemented */
3926 spr_register(env
, SPR_HID0
, "HID0",
3927 SPR_NOACCESS
, SPR_NOACCESS
,
3928 &spr_read_generic
, &spr_write_generic
,
3930 /* Memory management */
3934 /* XXX: TODO: initialize internal interrupt controller */
3937 #endif /* defined (TARGET_PPC64) */
3939 /* Default 32 bits PowerPC target will be 604 */
3940 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
3941 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
3942 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
3943 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
3944 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
3945 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
3946 #define init_proc_PPC32 init_proc_604
3947 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
3949 /* Default 64 bits PowerPC target will be 970 FX */
3950 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
3951 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
3952 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
3953 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
3954 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
3955 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
3956 #define init_proc_PPC64 init_proc_970FX
3957 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
3959 /* Default PowerPC target will be PowerPC 32 */
3960 #if defined (TARGET_PPC64) && 0 // XXX: TODO
3961 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
3962 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
3963 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
3964 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
3965 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
3966 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
3967 #define init_proc_DEFAULT init_proc_PPC64
3968 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
3970 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
3971 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
3972 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
3973 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
3974 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
3975 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
3976 #define init_proc_DEFAULT init_proc_PPC32
3977 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
3980 /*****************************************************************************/
3981 /* PVR definitions for most known PowerPC */
3983 /* PowerPC 401 family */
3984 /* Generic PowerPC 401 */
3985 #define CPU_POWERPC_401 CPU_POWERPC_401G2
3986 /* PowerPC 401 cores */
3987 CPU_POWERPC_401A1
= 0x00210000,
3988 CPU_POWERPC_401B2
= 0x00220000,
3990 CPU_POWERPC_401B3
= xxx
,
3992 CPU_POWERPC_401C2
= 0x00230000,
3993 CPU_POWERPC_401D2
= 0x00240000,
3994 CPU_POWERPC_401E2
= 0x00250000,
3995 CPU_POWERPC_401F2
= 0x00260000,
3996 CPU_POWERPC_401G2
= 0x00270000,
3997 /* PowerPC 401 microcontrolers */
3999 CPU_POWERPC_401GF
= xxx
,
4001 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
4002 /* IBM Processor for Network Resources */
4003 CPU_POWERPC_COBRA
= 0x10100000, /* XXX: 405 ? */
4005 CPU_POWERPC_XIPCHIP
= xxx
,
4007 /* PowerPC 403 family */
4008 /* Generic PowerPC 403 */
4009 #define CPU_POWERPC_403 CPU_POWERPC_403GC
4010 /* PowerPC 403 microcontrollers */
4011 CPU_POWERPC_403GA
= 0x00200011,
4012 CPU_POWERPC_403GB
= 0x00200100,
4013 CPU_POWERPC_403GC
= 0x00200200,
4014 CPU_POWERPC_403GCX
= 0x00201400,
4016 CPU_POWERPC_403GP
= xxx
,
4018 /* PowerPC 405 family */
4019 /* Generic PowerPC 405 */
4020 #define CPU_POWERPC_405 CPU_POWERPC_405D4
4021 /* PowerPC 405 cores */
4023 CPU_POWERPC_405A3
= xxx
,
4026 CPU_POWERPC_405A4
= xxx
,
4029 CPU_POWERPC_405B3
= xxx
,
4032 CPU_POWERPC_405B4
= xxx
,
4035 CPU_POWERPC_405C3
= xxx
,
4038 CPU_POWERPC_405C4
= xxx
,
4040 CPU_POWERPC_405D2
= 0x20010000,
4042 CPU_POWERPC_405D3
= xxx
,
4044 CPU_POWERPC_405D4
= 0x41810000,
4046 CPU_POWERPC_405D5
= xxx
,
4049 CPU_POWERPC_405E4
= xxx
,
4052 CPU_POWERPC_405F4
= xxx
,
4055 CPU_POWERPC_405F5
= xxx
,
4058 CPU_POWERPC_405F6
= xxx
,
4060 /* PowerPC 405 microcontrolers */
4061 /* XXX: missing 0x200108a0 */
4062 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
4063 CPU_POWERPC_405CRa
= 0x40110041,
4064 CPU_POWERPC_405CRb
= 0x401100C5,
4065 CPU_POWERPC_405CRc
= 0x40110145,
4066 CPU_POWERPC_405EP
= 0x51210950,
4068 CPU_POWERPC_405EXr
= xxx
,
4070 CPU_POWERPC_405EZ
= 0x41511460, /* 0x51210950 ? */
4072 CPU_POWERPC_405FX
= xxx
,
4074 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
4075 CPU_POWERPC_405GPa
= 0x40110000,
4076 CPU_POWERPC_405GPb
= 0x40110040,
4077 CPU_POWERPC_405GPc
= 0x40110082,
4078 CPU_POWERPC_405GPd
= 0x401100C4,
4079 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
4080 CPU_POWERPC_405GPR
= 0x50910951,
4082 CPU_POWERPC_405H
= xxx
,
4085 CPU_POWERPC_405L
= xxx
,
4087 CPU_POWERPC_405LP
= 0x41F10000,
4089 CPU_POWERPC_405PM
= xxx
,
4092 CPU_POWERPC_405PS
= xxx
,
4095 CPU_POWERPC_405S
= xxx
,
4097 /* IBM network processors */
4098 CPU_POWERPC_NPE405H
= 0x414100C0,
4099 CPU_POWERPC_NPE405H2
= 0x41410140,
4100 CPU_POWERPC_NPE405L
= 0x416100C0,
4101 CPU_POWERPC_NPE4GS3
= 0x40B10000,
4103 CPU_POWERPC_NPCxx1
= xxx
,
4106 CPU_POWERPC_NPR161
= xxx
,
4109 CPU_POWERPC_LC77700
= xxx
,
4111 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
4113 CPU_POWERPC_STB01000
= xxx
,
4116 CPU_POWERPC_STB01010
= xxx
,
4119 CPU_POWERPC_STB0210
= xxx
, /* 401B3 */
4121 CPU_POWERPC_STB03
= 0x40310000, /* 0x40130000 ? */
4123 CPU_POWERPC_STB043
= xxx
,
4126 CPU_POWERPC_STB045
= xxx
,
4128 CPU_POWERPC_STB04
= 0x41810000,
4129 CPU_POWERPC_STB25
= 0x51510950,
4131 CPU_POWERPC_STB130
= xxx
,
4134 CPU_POWERPC_X2VP4
= 0x20010820,
4135 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
4136 CPU_POWERPC_X2VP20
= 0x20010860,
4137 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
4139 CPU_POWERPC_ZL10310
= xxx
,
4142 CPU_POWERPC_ZL10311
= xxx
,
4145 CPU_POWERPC_ZL10320
= xxx
,
4148 CPU_POWERPC_ZL10321
= xxx
,
4150 /* PowerPC 440 family */
4151 /* Generic PowerPC 440 */
4152 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
4153 /* PowerPC 440 cores */
4155 CPU_POWERPC_440A4
= xxx
,
4158 CPU_POWERPC_440A5
= xxx
,
4161 CPU_POWERPC_440B4
= xxx
,
4164 CPU_POWERPC_440F5
= xxx
,
4167 CPU_POWERPC_440G5
= xxx
,
4170 CPU_POWERPC_440H4
= xxx
,
4173 CPU_POWERPC_440H6
= xxx
,
4175 /* PowerPC 440 microcontrolers */
4176 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
4177 CPU_POWERPC_440EPa
= 0x42221850,
4178 CPU_POWERPC_440EPb
= 0x422218D3,
4179 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
4180 CPU_POWERPC_440GPb
= 0x40120440,
4181 CPU_POWERPC_440GPc
= 0x40120481,
4182 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
4183 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
4184 CPU_POWERPC_440GRX
= 0x200008D0,
4185 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
4186 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
4187 CPU_POWERPC_440GXa
= 0x51B21850,
4188 CPU_POWERPC_440GXb
= 0x51B21851,
4189 CPU_POWERPC_440GXc
= 0x51B21892,
4190 CPU_POWERPC_440GXf
= 0x51B21894,
4192 CPU_POWERPC_440S
= xxx
,
4194 CPU_POWERPC_440SP
= 0x53221850,
4195 CPU_POWERPC_440SP2
= 0x53221891,
4196 CPU_POWERPC_440SPE
= 0x53421890,
4197 /* PowerPC 460 family */
4199 /* Generic PowerPC 464 */
4200 #define CPU_POWERPC_464 CPU_POWERPC_464H90
4202 /* PowerPC 464 microcontrolers */
4204 CPU_POWERPC_464H90
= xxx
,
4207 CPU_POWERPC_464H90FP
= xxx
,
4209 /* Freescale embedded PowerPC cores */
4211 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
4213 CPU_POWERPC_e200z0
= xxx
,
4216 CPU_POWERPC_e200z3
= xxx
,
4218 CPU_POWERPC_e200z5
= 0x81000000,
4219 CPU_POWERPC_e200z6
= 0x81120000,
4221 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
4222 CPU_POWERPC_e300c1
= 0x00830000,
4223 CPU_POWERPC_e300c2
= 0x00840000,
4224 CPU_POWERPC_e300c3
= 0x00850000,
4226 #define CPU_POWERPC_e500 CPU_POWERPC_e500_v22
4227 CPU_POWERPC_e500_v11
= 0x80200010,
4228 CPU_POWERPC_e500_v12
= 0x80200020,
4229 CPU_POWERPC_e500_v21
= 0x80210010,
4230 CPU_POWERPC_e500_v22
= 0x80210020,
4232 CPU_POWERPC_e500mc
= xxx
,
4235 CPU_POWERPC_e600
= 0x80040010,
4236 /* PowerPC MPC 5xx cores */
4237 CPU_POWERPC_5xx
= 0x00020020,
4238 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
4239 CPU_POWERPC_8xx
= 0x00500000,
4240 /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
4241 CPU_POWERPC_82xx_HIP3
= 0x00810101,
4242 CPU_POWERPC_82xx_HIP4
= 0x80811014,
4243 CPU_POWERPC_827x
= 0x80822013,
4244 /* PowerPC 6xx cores */
4245 CPU_POWERPC_601
= 0x00010001,
4246 CPU_POWERPC_601a
= 0x00010002,
4247 CPU_POWERPC_602
= 0x00050100,
4248 CPU_POWERPC_603
= 0x00030100,
4249 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
4250 CPU_POWERPC_603E_v11
= 0x00060101,
4251 CPU_POWERPC_603E_v12
= 0x00060102,
4252 CPU_POWERPC_603E_v13
= 0x00060103,
4253 CPU_POWERPC_603E_v14
= 0x00060104,
4254 CPU_POWERPC_603E_v22
= 0x00060202,
4255 CPU_POWERPC_603E_v3
= 0x00060300,
4256 CPU_POWERPC_603E_v4
= 0x00060400,
4257 CPU_POWERPC_603E_v41
= 0x00060401,
4258 CPU_POWERPC_603E7t
= 0x00071201,
4259 CPU_POWERPC_603E7v
= 0x00070100,
4260 CPU_POWERPC_603E7v1
= 0x00070101,
4261 CPU_POWERPC_603E7v2
= 0x00070201,
4262 CPU_POWERPC_603E7
= 0x00070200,
4263 CPU_POWERPC_603P
= 0x00070000,
4264 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
4265 CPU_POWERPC_G2
= 0x00810011,
4266 #if 0 // Linux pretends the MSB is zero...
4267 CPU_POWERPC_G2H4
= 0x80811010,
4268 CPU_POWERPC_G2gp
= 0x80821010,
4269 CPU_POWERPC_G2ls
= 0x90810010,
4270 CPU_POWERPC_G2LE
= 0x80820010,
4271 CPU_POWERPC_G2LEgp
= 0x80822010,
4272 CPU_POWERPC_G2LEls
= 0xA0822010,
4274 CPU_POWERPC_G2H4
= 0x00811010,
4275 CPU_POWERPC_G2gp
= 0x00821010,
4276 CPU_POWERPC_G2ls
= 0x10810010,
4277 CPU_POWERPC_G2LE
= 0x00820010,
4278 CPU_POWERPC_G2LEgp
= 0x00822010,
4279 CPU_POWERPC_G2LEls
= 0x20822010,
4281 CPU_POWERPC_604
= 0x00040103,
4282 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
4283 CPU_POWERPC_604E_v10
= 0x00090100, /* Also 2110 & 2120 */
4284 CPU_POWERPC_604E_v22
= 0x00090202,
4285 CPU_POWERPC_604E_v24
= 0x00090204,
4286 CPU_POWERPC_604R
= 0x000a0101, /* Also 0x00093102 */
4288 CPU_POWERPC_604EV
= xxx
,
4290 /* PowerPC 740/750 cores (aka G3) */
4291 /* XXX: missing 0x00084202 */
4292 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
4293 CPU_POWERPC_7x0_v20
= 0x00080200,
4294 CPU_POWERPC_7x0_v21
= 0x00080201,
4295 CPU_POWERPC_7x0_v22
= 0x00080202,
4296 CPU_POWERPC_7x0_v30
= 0x00080300,
4297 CPU_POWERPC_7x0_v31
= 0x00080301,
4298 CPU_POWERPC_740E
= 0x00080100,
4299 CPU_POWERPC_7x0P
= 0x10080000,
4300 /* XXX: missing 0x00087010 (CL ?) */
4301 CPU_POWERPC_750CL
= 0x00087200,
4302 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
4303 CPU_POWERPC_750CX_v21
= 0x00082201,
4304 CPU_POWERPC_750CX_v22
= 0x00082202,
4305 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
4306 CPU_POWERPC_750CXE_v21
= 0x00082211,
4307 CPU_POWERPC_750CXE_v22
= 0x00082212,
4308 CPU_POWERPC_750CXE_v23
= 0x00082213,
4309 CPU_POWERPC_750CXE_v24
= 0x00082214,
4310 CPU_POWERPC_750CXE_v24b
= 0x00083214,
4311 CPU_POWERPC_750CXE_v31
= 0x00083211,
4312 CPU_POWERPC_750CXE_v31b
= 0x00083311,
4313 CPU_POWERPC_750CXR
= 0x00083410,
4314 CPU_POWERPC_750E
= 0x00080200,
4315 CPU_POWERPC_750FL
= 0x700A0203,
4316 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
4317 CPU_POWERPC_750FX_v10
= 0x70000100,
4318 CPU_POWERPC_750FX_v20
= 0x70000200,
4319 CPU_POWERPC_750FX_v21
= 0x70000201,
4320 CPU_POWERPC_750FX_v22
= 0x70000202,
4321 CPU_POWERPC_750FX_v23
= 0x70000203,
4322 CPU_POWERPC_750GL
= 0x70020102,
4323 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
4324 CPU_POWERPC_750GX_v10
= 0x70020100,
4325 CPU_POWERPC_750GX_v11
= 0x70020101,
4326 CPU_POWERPC_750GX_v12
= 0x70020102,
4327 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
4328 CPU_POWERPC_750L_v22
= 0x00088202,
4329 CPU_POWERPC_750L_v30
= 0x00088300,
4330 CPU_POWERPC_750L_v32
= 0x00088302,
4331 /* PowerPC 745/755 cores */
4332 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
4333 CPU_POWERPC_7x5_v10
= 0x00083100,
4334 CPU_POWERPC_7x5_v11
= 0x00083101,
4335 CPU_POWERPC_7x5_v20
= 0x00083200,
4336 CPU_POWERPC_7x5_v21
= 0x00083201,
4337 CPU_POWERPC_7x5_v22
= 0x00083202, /* aka D */
4338 CPU_POWERPC_7x5_v23
= 0x00083203, /* aka E */
4339 CPU_POWERPC_7x5_v24
= 0x00083204,
4340 CPU_POWERPC_7x5_v25
= 0x00083205,
4341 CPU_POWERPC_7x5_v26
= 0x00083206,
4342 CPU_POWERPC_7x5_v27
= 0x00083207,
4343 CPU_POWERPC_7x5_v28
= 0x00083208,
4345 CPU_POWERPC_7x5P
= xxx
,
4347 /* PowerPC 74xx cores (aka G4) */
4348 /* XXX: missing 0x000C1101 */
4349 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
4350 CPU_POWERPC_7400_v10
= 0x000C0100,
4351 CPU_POWERPC_7400_v11
= 0x000C0101,
4352 CPU_POWERPC_7400_v20
= 0x000C0200,
4353 CPU_POWERPC_7400_v22
= 0x000C0202,
4354 CPU_POWERPC_7400_v26
= 0x000C0206,
4355 CPU_POWERPC_7400_v27
= 0x000C0207,
4356 CPU_POWERPC_7400_v28
= 0x000C0208,
4357 CPU_POWERPC_7400_v29
= 0x000C0209,
4358 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
4359 CPU_POWERPC_7410_v10
= 0x800C1100,
4360 CPU_POWERPC_7410_v11
= 0x800C1101,
4361 CPU_POWERPC_7410_v12
= 0x800C1102, /* aka C */
4362 CPU_POWERPC_7410_v13
= 0x800C1103, /* aka D */
4363 CPU_POWERPC_7410_v14
= 0x800C1104, /* aka E */
4364 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
4365 CPU_POWERPC_7448_v10
= 0x80040100,
4366 CPU_POWERPC_7448_v11
= 0x80040101,
4367 CPU_POWERPC_7448_v20
= 0x80040200,
4368 CPU_POWERPC_7448_v21
= 0x80040201,
4369 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
4370 CPU_POWERPC_7450_v10
= 0x80000100,
4371 CPU_POWERPC_7450_v11
= 0x80000101,
4372 CPU_POWERPC_7450_v12
= 0x80000102,
4373 CPU_POWERPC_7450_v20
= 0x80000200, /* aka D: 2.04 */
4374 CPU_POWERPC_7450_v21
= 0x80000201, /* aka E */
4375 CPU_POWERPC_74x1
= 0x80000203,
4376 CPU_POWERPC_74x1G
= 0x80000210, /* aka G: 2.3 */
4377 /* XXX: missing 0x80010200 */
4378 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
4379 CPU_POWERPC_74x5_v10
= 0x80010100,
4380 CPU_POWERPC_74x5_v21
= 0x80010201, /* aka C: 2.1 */
4381 CPU_POWERPC_74x5_v32
= 0x80010302,
4382 CPU_POWERPC_74x5_v33
= 0x80010303, /* aka F: 3.3 */
4383 CPU_POWERPC_74x5_v34
= 0x80010304, /* aka G: 3.4 */
4384 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
4385 CPU_POWERPC_74x7_v10
= 0x80020100, /* aka A: 1.0 */
4386 CPU_POWERPC_74x7_v11
= 0x80030101, /* aka B: 1.1 */
4387 CPU_POWERPC_74x7_v12
= 0x80020102, /* aka C: 1.2 */
4388 /* 64 bits PowerPC */
4389 CPU_POWERPC_620
= 0x00140000,
4390 CPU_POWERPC_630
= 0x00400000,
4391 CPU_POWERPC_631
= 0x00410104,
4392 CPU_POWERPC_POWER4
= 0x00350000,
4393 CPU_POWERPC_POWER4P
= 0x00380000,
4394 CPU_POWERPC_POWER5
= 0x003A0203,
4395 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
4396 CPU_POWERPC_POWER5P
= 0x003B0000,
4397 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
4398 CPU_POWERPC_POWER6
= 0x003E0000,
4399 CPU_POWERPC_POWER6_5
= 0x0F000001, /* POWER6 running POWER5 mode */
4400 CPU_POWERPC_POWER6A
= 0x0F000002,
4401 CPU_POWERPC_970
= 0x00390202,
4402 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
4403 CPU_POWERPC_970FX_v10
= 0x00391100,
4404 CPU_POWERPC_970FX_v20
= 0x003C0200,
4405 CPU_POWERPC_970FX_v21
= 0x003C0201,
4406 CPU_POWERPC_970FX_v30
= 0x003C0300,
4407 CPU_POWERPC_970FX_v31
= 0x003C0301,
4408 CPU_POWERPC_970GX
= 0x00450000,
4409 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
4410 CPU_POWERPC_970MP_v10
= 0x00440100,
4411 CPU_POWERPC_970MP_v11
= 0x00440101,
4412 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
4413 CPU_POWERPC_CELL_v10
= 0x00700100,
4414 CPU_POWERPC_CELL_v20
= 0x00700400,
4415 CPU_POWERPC_CELL_v30
= 0x00700500,
4416 CPU_POWERPC_CELL_v31
= 0x00700501,
4417 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
4418 CPU_POWERPC_RS64
= 0x00330000,
4419 CPU_POWERPC_RS64II
= 0x00340000,
4420 CPU_POWERPC_RS64III
= 0x00360000,
4421 CPU_POWERPC_RS64IV
= 0x00370000,
4422 /* Original POWER */
4423 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
4424 * POWER2 (RIOS2) & RSC2 (P2SC) here
4427 CPU_POWER
= xxx
, /* 0x20000 ? 0x30000 for RSC ? */
4430 CPU_POWER2
= xxx
, /* 0x40000 ? */
4433 CPU_POWERPC_PA6T
= 0x00900000,
4436 /* System version register (used on MPC 8xxx) */
4438 PPC_SVR_8540
= 0x80300000,
4439 PPC_SVR_8541E
= 0x807A0010,
4440 PPC_SVR_8543v10
= 0x80320010,
4441 PPC_SVR_8543v11
= 0x80320011,
4442 PPC_SVR_8543v20
= 0x80320020,
4443 PPC_SVR_8543Ev10
= 0x803A0010,
4444 PPC_SVR_8543Ev11
= 0x803A0011,
4445 PPC_SVR_8543Ev20
= 0x803A0020,
4446 PPC_SVR_8545
= 0x80310220,
4447 PPC_SVR_8545E
= 0x80390220,
4448 PPC_SVR_8547E
= 0x80390120,
4449 PPC_SCR_8548v10
= 0x80310010,
4450 PPC_SCR_8548v11
= 0x80310011,
4451 PPC_SCR_8548v20
= 0x80310020,
4452 PPC_SVR_8548Ev10
= 0x80390010,
4453 PPC_SVR_8548Ev11
= 0x80390011,
4454 PPC_SVR_8548Ev20
= 0x80390020,
4455 PPC_SVR_8555E
= 0x80790010,
4456 PPC_SVR_8560v10
= 0x80700010,
4457 PPC_SVR_8560v20
= 0x80700020,
4460 /*****************************************************************************/
4461 /* PowerPC CPU definitions */
4462 #define POWERPC_DEF(_name, _pvr, _pvr_mask, _type) \
4466 .pvr_mask = _pvr_mask, \
4467 .insns_flags = glue(POWERPC_INSNS_,_type), \
4468 .msr_mask = glue(POWERPC_MSRM_,_type), \
4469 .mmu_model = glue(POWERPC_MMU_,_type), \
4470 .excp_model = glue(POWERPC_EXCP_,_type), \
4471 .bus_model = glue(POWERPC_INPUT_,_type), \
4472 .bfd_mach = glue(POWERPC_BFDM_,_type), \
4473 .init_proc = &glue(init_proc_,_type), \
4476 static ppc_def_t ppc_defs
[] = {
4477 /* Embedded PowerPC */
4478 /* PowerPC 401 family */
4479 /* Generic PowerPC 401 */
4480 POWERPC_DEF("401", CPU_POWERPC_401
, 0xFFFF0000, 401),
4481 /* PowerPC 401 cores */
4483 POWERPC_DEF("401A1", CPU_POWERPC_401A1
, 0xFFFFFFFF, 401),
4485 POWERPC_DEF("401B2", CPU_POWERPC_401B2
, 0xFFFFFFFF, 401x2
),
4488 POWERPC_DEF("401B3", CPU_POWERPC_401B3
, 0xFFFFFFFF, 401x3
),
4491 POWERPC_DEF("401C2", CPU_POWERPC_401C2
, 0xFFFFFFFF, 401x2
),
4493 POWERPC_DEF("401D2", CPU_POWERPC_401D2
, 0xFFFFFFFF, 401x2
),
4495 POWERPC_DEF("401E2", CPU_POWERPC_401E2
, 0xFFFFFFFF, 401x2
),
4497 POWERPC_DEF("401F2", CPU_POWERPC_401F2
, 0xFFFFFFFF, 401x2
),
4499 /* XXX: to be checked */
4500 POWERPC_DEF("401G2", CPU_POWERPC_401G2
, 0xFFFFFFFF, 401x2
),
4501 /* PowerPC 401 microcontrolers */
4504 POWERPC_DEF("401GF", CPU_POWERPC_401GF
, 0xFFFFFFFF, 401),
4506 /* IOP480 (401 microcontroler) */
4507 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480
, 0xFFFFFFFF, IOP480
),
4508 /* IBM Processor for Network Resources */
4509 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA
, 0xFFFFFFFF, 401),
4511 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP
, 0xFFFFFFFF, 401),
4513 /* PowerPC 403 family */
4514 /* Generic PowerPC 403 */
4515 POWERPC_DEF("403", CPU_POWERPC_403
, 0xFFFF0000, 403),
4516 /* PowerPC 403 microcontrolers */
4517 /* PowerPC 403 GA */
4518 POWERPC_DEF("403GA", CPU_POWERPC_403GA
, 0xFFFFFFFF, 403),
4519 /* PowerPC 403 GB */
4520 POWERPC_DEF("403GB", CPU_POWERPC_403GB
, 0xFFFFFFFF, 403),
4521 /* PowerPC 403 GC */
4522 POWERPC_DEF("403GC", CPU_POWERPC_403GC
, 0xFFFFFFFF, 403),
4523 /* PowerPC 403 GCX */
4524 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX
, 0xFFFFFFFF, 403GCX
),
4526 /* PowerPC 403 GP */
4527 POWERPC_DEF("403GP", CPU_POWERPC_403GP
, 0xFFFFFFFF, 403),
4529 /* PowerPC 405 family */
4530 /* Generic PowerPC 405 */
4531 POWERPC_DEF("405", CPU_POWERPC_405
, 0xFFFF0000, 405),
4532 /* PowerPC 405 cores */
4534 /* PowerPC 405 A3 */
4535 POWERPC_DEF("405A3", CPU_POWERPC_405A3
, 0xFFFFFFFF, 405),
4538 /* PowerPC 405 A4 */
4539 POWERPC_DEF("405A4", CPU_POWERPC_405A4
, 0xFFFFFFFF, 405),
4542 /* PowerPC 405 B3 */
4543 POWERPC_DEF("405B3", CPU_POWERPC_405B3
, 0xFFFFFFFF, 405),
4546 /* PowerPC 405 B4 */
4547 POWERPC_DEF("405B4", CPU_POWERPC_405B4
, 0xFFFFFFFF, 405),
4550 /* PowerPC 405 C3 */
4551 POWERPC_DEF("405C3", CPU_POWERPC_405C3
, 0xFFFFFFFF, 405),
4554 /* PowerPC 405 C4 */
4555 POWERPC_DEF("405C4", CPU_POWERPC_405C4
, 0xFFFFFFFF, 405),
4557 /* PowerPC 405 D2 */
4558 POWERPC_DEF("405D2", CPU_POWERPC_405D2
, 0xFFFFFFFF, 405),
4560 /* PowerPC 405 D3 */
4561 POWERPC_DEF("405D3", CPU_POWERPC_405D3
, 0xFFFFFFFF, 405),
4563 /* PowerPC 405 D4 */
4564 POWERPC_DEF("405D4", CPU_POWERPC_405D4
, 0xFFFFFFFF, 405),
4566 /* PowerPC 405 D5 */
4567 POWERPC_DEF("405D5", CPU_POWERPC_405D5
, 0xFFFFFFFF, 405),
4570 /* PowerPC 405 E4 */
4571 POWERPC_DEF("405E4", CPU_POWERPC_405E4
, 0xFFFFFFFF, 405),
4574 /* PowerPC 405 F4 */
4575 POWERPC_DEF("405F4", CPU_POWERPC_405F4
, 0xFFFFFFFF, 405),
4578 /* PowerPC 405 F5 */
4579 POWERPC_DEF("405F5", CPU_POWERPC_405F5
, 0xFFFFFFFF, 405),
4582 /* PowerPC 405 F6 */
4583 POWERPC_DEF("405F6", CPU_POWERPC_405F6
, 0xFFFFFFFF, 405),
4585 /* PowerPC 405 microcontrolers */
4586 /* PowerPC 405 CR */
4587 POWERPC_DEF("405CR", CPU_POWERPC_405CR
, 0xFFFFFFFF, 405),
4588 /* PowerPC 405 CRa */
4589 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa
, 0xFFFFFFFF, 405),
4590 /* PowerPC 405 CRb */
4591 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb
, 0xFFFFFFFF, 405),
4592 /* PowerPC 405 CRc */
4593 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc
, 0xFFFFFFFF, 405),
4594 /* PowerPC 405 EP */
4595 POWERPC_DEF("405EP", CPU_POWERPC_405EP
, 0xFFFFFFFF, 405),
4597 /* PowerPC 405 EXr */
4598 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr
, 0xFFFFFFFF, 405),
4600 /* PowerPC 405 EZ */
4601 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ
, 0xFFFFFFFF, 405),
4603 /* PowerPC 405 FX */
4604 POWERPC_DEF("405FX", CPU_POWERPC_405FX
, 0xFFFFFFFF, 405),
4606 /* PowerPC 405 GP */
4607 POWERPC_DEF("405GP", CPU_POWERPC_405GP
, 0xFFFFFFFF, 405),
4608 /* PowerPC 405 GPa */
4609 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa
, 0xFFFFFFFF, 405),
4610 /* PowerPC 405 GPb */
4611 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb
, 0xFFFFFFFF, 405),
4612 /* PowerPC 405 GPc */
4613 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc
, 0xFFFFFFFF, 405),
4614 /* PowerPC 405 GPd */
4615 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd
, 0xFFFFFFFF, 405),
4616 /* PowerPC 405 GPe */
4617 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe
, 0xFFFFFFFF, 405),
4618 /* PowerPC 405 GPR */
4619 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR
, 0xFFFFFFFF, 405),
4622 POWERPC_DEF("405H", CPU_POWERPC_405H
, 0xFFFFFFFF, 405),
4626 POWERPC_DEF("405L", CPU_POWERPC_405L
, 0xFFFFFFFF, 405),
4628 /* PowerPC 405 LP */
4629 POWERPC_DEF("405LP", CPU_POWERPC_405LP
, 0xFFFFFFFF, 405),
4631 /* PowerPC 405 PM */
4632 POWERPC_DEF("405PM", CPU_POWERPC_405PM
, 0xFFFFFFFF, 405),
4635 /* PowerPC 405 PS */
4636 POWERPC_DEF("405PS", CPU_POWERPC_405PS
, 0xFFFFFFFF, 405),
4640 POWERPC_DEF("405S", CPU_POWERPC_405S
, 0xFFFFFFFF, 405),
4643 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H
, 0xFFFFFFFF, 405),
4645 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2
, 0xFFFFFFFF, 405),
4647 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L
, 0xFFFFFFFF, 405),
4649 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3
, 0xFFFFFFFF, 405),
4651 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1
, 0xFFFFFFFF, 405),
4654 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161
, 0xFFFFFFFF, 405),
4657 /* PowerPC LC77700 (Sanyo) */
4658 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700
, 0xFFFFFFFF, 405),
4660 /* PowerPC 401/403/405 based set-top-box microcontrolers */
4663 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000
, 0xFFFFFFFF, 401x2
),
4667 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010
, 0xFFFFFFFF, 401x2
),
4671 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210
, 0xFFFFFFFF, 401x3
),
4674 POWERPC_DEF("STB03", CPU_POWERPC_STB03
, 0xFFFFFFFF, 405),
4677 POWERPC_DEF("STB043", CPU_POWERPC_STB043
, 0xFFFFFFFF, 405),
4681 POWERPC_DEF("STB045", CPU_POWERPC_STB045
, 0xFFFFFFFF, 405),
4684 POWERPC_DEF("STB04", CPU_POWERPC_STB04
, 0xFFFF0000, 405),
4686 POWERPC_DEF("STB25", CPU_POWERPC_STB25
, 0xFFFFFFFF, 405),
4689 POWERPC_DEF("STB130", CPU_POWERPC_STB130
, 0xFFFFFFFF, 405),
4691 /* Xilinx PowerPC 405 cores */
4692 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4
, 0xFFFFFFFF, 405),
4693 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7
, 0xFFFFFFFF, 405),
4694 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20
, 0xFFFFFFFF, 405),
4695 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50
, 0xFFFFFFFF, 405),
4697 /* Zarlink ZL10310 */
4698 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310
, 0xFFFFFFFF, 405),
4701 /* Zarlink ZL10311 */
4702 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311
, 0xFFFFFFFF, 405),
4705 /* Zarlink ZL10320 */
4706 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320
, 0xFFFFFFFF, 405),
4709 /* Zarlink ZL10321 */
4710 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321
, 0xFFFFFFFF, 405),
4712 /* PowerPC 440 family */
4713 /* Generic PowerPC 440 */
4714 POWERPC_DEF("440", CPU_POWERPC_440
, 0xFFFFFFFF, 440GP
),
4715 /* PowerPC 440 cores */
4717 /* PowerPC 440 A4 */
4718 POWERPC_DEF("440A4", CPU_POWERPC_440A4
, 0xFFFFFFFF, 440x4
),
4721 /* PowerPC 440 A5 */
4722 POWERPC_DEF("440A5", CPU_POWERPC_440A5
, 0xFFFFFFFF, 440x5
),
4725 /* PowerPC 440 B4 */
4726 POWERPC_DEF("440B4", CPU_POWERPC_440B4
, 0xFFFFFFFF, 440x4
),
4729 /* PowerPC 440 G4 */
4730 POWERPC_DEF("440G4", CPU_POWERPC_440G4
, 0xFFFFFFFF, 440x4
),
4733 /* PowerPC 440 F5 */
4734 POWERPC_DEF("440F5", CPU_POWERPC_440F5
, 0xFFFFFFFF, 440x5
),
4737 /* PowerPC 440 G5 */
4738 POWERPC_DEF("440G5", CPU_POWERPC_440G5
, 0xFFFFFFFF, 440x5
),
4742 POWERPC_DEF("440H4", CPU_POWERPC_440H4
, 0xFFFFFFFF, 440x4
),
4746 POWERPC_DEF("440H6", CPU_POWERPC_440H6
, 0xFFFFFFFF, 440Gx5
),
4748 /* PowerPC 440 microcontrolers */
4749 /* PowerPC 440 EP */
4750 POWERPC_DEF("440EP", CPU_POWERPC_440EP
, 0xFFFFFFFF, 440EP
),
4751 /* PowerPC 440 EPa */
4752 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa
, 0xFFFFFFFF, 440EP
),
4753 /* PowerPC 440 EPb */
4754 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb
, 0xFFFFFFFF, 440EP
),
4755 /* PowerPC 440 EPX */
4756 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX
, 0xFFFFFFFF, 440EP
),
4757 /* PowerPC 440 GP */
4758 POWERPC_DEF("440GP", CPU_POWERPC_440GP
, 0xFFFFFFFF, 440GP
),
4759 /* PowerPC 440 GPb */
4760 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb
, 0xFFFFFFFF, 440GP
),
4761 /* PowerPC 440 GPc */
4762 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc
, 0xFFFFFFFF, 440GP
),
4763 /* PowerPC 440 GR */
4764 POWERPC_DEF("440GR", CPU_POWERPC_440GR
, 0xFFFFFFFF, 440x5
),
4765 /* PowerPC 440 GRa */
4766 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa
, 0xFFFFFFFF, 440x5
),
4767 /* PowerPC 440 GRX */
4768 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX
, 0xFFFFFFFF, 440x5
),
4769 /* PowerPC 440 GX */
4770 POWERPC_DEF("440GX", CPU_POWERPC_440GX
, 0xFFFFFFFF, 440EP
),
4771 /* PowerPC 440 GXa */
4772 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa
, 0xFFFFFFFF, 440EP
),
4773 /* PowerPC 440 GXb */
4774 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb
, 0xFFFFFFFF, 440EP
),
4775 /* PowerPC 440 GXc */
4776 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc
, 0xFFFFFFFF, 440EP
),
4777 /* PowerPC 440 GXf */
4778 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf
, 0xFFFFFFFF, 440EP
),
4781 POWERPC_DEF("440S", CPU_POWERPC_440S
, 0xFFFFFFFF, 440),
4783 /* PowerPC 440 SP */
4784 POWERPC_DEF("440SP", CPU_POWERPC_440SP
, 0xFFFFFFFF, 440EP
),
4785 /* PowerPC 440 SP2 */
4786 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2
, 0xFFFFFFFF, 440EP
),
4787 /* PowerPC 440 SPE */
4788 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE
, 0xFFFFFFFF, 440EP
),
4789 /* PowerPC 460 family */
4791 /* Generic PowerPC 464 */
4792 POWERPC_DEF("464", CPU_POWERPC_464
, 0xFFFFFFFF, 460),
4794 /* PowerPC 464 microcontrolers */
4796 /* PowerPC 464H90 */
4797 POWERPC_DEF("464H90", CPU_POWERPC_464H90
, 0xFFFFFFFF, 460),
4800 /* PowerPC 464H90F */
4801 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F
, 0xFFFFFFFF, 460F
),
4803 /* Freescale embedded PowerPC cores */
4806 /* Generic PowerPC e200 core */
4807 POWERPC_DEF("e200", CPU_POWERPC_e200
, 0xFFFFFFFF, e200
),
4810 /* PowerPC e200z5 core */
4811 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5
, 0xFFFFFFFF, e200
),
4814 /* PowerPC e200z6 core */
4815 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6
, 0xFFFFFFFF, e200
),
4819 /* Generic PowerPC e300 core */
4820 POWERPC_DEF("e300", CPU_POWERPC_e300
, 0xFFFFFFFF, e300
),
4823 /* PowerPC e300c1 core */
4824 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1
, 0xFFFFFFFF, e300
),
4827 /* PowerPC e300c2 core */
4828 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2
, 0xFFFFFFFF, e300
),
4831 /* PowerPC e300c3 core */
4832 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3
, 0xFFFFFFFF, e300
),
4836 /* PowerPC e500 core */
4837 POWERPC_DEF("e500", CPU_POWERPC_e500
, 0xFFFFFFFF, e500
),
4840 /* PowerPC e500 v1.1 core */
4841 POWERPC_DEF("e500v1.1", CPU_POWERPC_e500_v11
, 0xFFFFFFFF, e500
),
4844 /* PowerPC e500 v1.2 core */
4845 POWERPC_DEF("e500v1.2", CPU_POWERPC_e500_v12
, 0xFFFFFFFF, e500
),
4848 /* PowerPC e500 v2.1 core */
4849 POWERPC_DEF("e500v2.1", CPU_POWERPC_e500_v21
, 0xFFFFFFFF, e500
),
4852 /* PowerPC e500 v2.2 core */
4853 POWERPC_DEF("e500v2.2", CPU_POWERPC_e500_v22
, 0xFFFFFFFF, e500
),
4857 /* PowerPC e600 core */
4858 POWERPC_DEF("e600", CPU_POWERPC_e600
, 0xFFFFFFFF, e600
),
4860 /* PowerPC MPC 5xx cores */
4862 /* PowerPC MPC 5xx */
4863 POWERPC_DEF("mpc5xx", CPU_POWERPC_5xx
, 0xFFFFFFFF, 5xx
),
4865 /* PowerPC MPC 8xx cores */
4867 /* PowerPC MPC 8xx */
4868 POWERPC_DEF("mpc8xx", CPU_POWERPC_8xx
, 0xFFFFFFFF, 8xx
),
4870 /* PowerPC MPC 8xxx cores */
4872 /* PowerPC MPC 82xx HIP3 */
4873 POWERPC_DEF("mpc82xxhip3", CPU_POWERPC_82xx_HIP3
, 0xFFFFFFFF, 82xx
),
4876 /* PowerPC MPC 82xx HIP4 */
4877 POWERPC_DEF("mpc82xxhip4", CPU_POWERPC_82xx_HIP4
, 0xFFFFFFFF, 82xx
),
4880 /* PowerPC MPC 827x */
4881 POWERPC_DEF("mpc827x", CPU_POWERPC_827x
, 0xFFFFFFFF, 827x
),
4884 /* 32 bits "classic" PowerPC */
4885 /* PowerPC 6xx family */
4887 POWERPC_DEF("601", CPU_POWERPC_601
, 0xFFFFFFFF, 601),
4889 POWERPC_DEF("601a", CPU_POWERPC_601a
, 0xFFFFFFFF, 601),
4891 POWERPC_DEF("602", CPU_POWERPC_602
, 0xFFFFFFFF, 602),
4893 POWERPC_DEF("603", CPU_POWERPC_603
, 0xFFFFFFFF, 603),
4894 /* Code name for PowerPC 603 */
4895 POWERPC_DEF("Vanilla", CPU_POWERPC_603
, 0xFFFFFFFF, 603),
4897 POWERPC_DEF("603e", CPU_POWERPC_603E
, 0xFFFFFFFF, 603E
),
4898 /* Code name for PowerPC 603e */
4899 POWERPC_DEF("Stretch", CPU_POWERPC_603E
, 0xFFFFFFFF, 603E
),
4900 /* PowerPC 603e v1.1 */
4901 POWERPC_DEF("603e1.1", CPU_POWERPC_603E_v11
, 0xFFFFFFFF, 603E
),
4902 /* PowerPC 603e v1.2 */
4903 POWERPC_DEF("603e1.2", CPU_POWERPC_603E_v12
, 0xFFFFFFFF, 603E
),
4904 /* PowerPC 603e v1.3 */
4905 POWERPC_DEF("603e1.3", CPU_POWERPC_603E_v13
, 0xFFFFFFFF, 603E
),
4906 /* PowerPC 603e v1.4 */
4907 POWERPC_DEF("603e1.4", CPU_POWERPC_603E_v14
, 0xFFFFFFFF, 603E
),
4908 /* PowerPC 603e v2.2 */
4909 POWERPC_DEF("603e2.2", CPU_POWERPC_603E_v22
, 0xFFFFFFFF, 603E
),
4910 /* PowerPC 603e v3 */
4911 POWERPC_DEF("603e3", CPU_POWERPC_603E_v3
, 0xFFFFFFFF, 603E
),
4912 /* PowerPC 603e v4 */
4913 POWERPC_DEF("603e4", CPU_POWERPC_603E_v4
, 0xFFFFFFFF, 603E
),
4914 /* PowerPC 603e v4.1 */
4915 POWERPC_DEF("603e4.1", CPU_POWERPC_603E_v41
, 0xFFFFFFFF, 603E
),
4917 POWERPC_DEF("603e7", CPU_POWERPC_603E7
, 0xFFFFFFFF, 603E
),
4918 /* PowerPC 603e7t */
4919 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t
, 0xFFFFFFFF, 603E
),
4920 /* PowerPC 603e7v */
4921 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v
, 0xFFFFFFFF, 603E
),
4922 /* Code name for PowerPC 603ev */
4923 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v
, 0xFFFFFFFF, 603E
),
4924 /* PowerPC 603e7v1 */
4925 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1
, 0xFFFFFFFF, 603E
),
4926 /* PowerPC 603e7v2 */
4927 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2
, 0xFFFFFFFF, 603E
),
4930 POWERPC_DEF("603p", CPU_POWERPC_603P
, 0xFFFFFFFF, 603),
4932 POWERPC_DEF("603r", CPU_POWERPC_603R
, 0xFFFFFFFF, 603E
),
4933 /* Code name for PowerPC 603r */
4934 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R
, 0xFFFFFFFF, 603E
),
4935 /* PowerPC G2 core */
4936 POWERPC_DEF("G2", CPU_POWERPC_G2
, 0xFFFFFFFF, G2
),
4938 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4
, 0xFFFFFFFF, G2
),
4940 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp
, 0xFFFFFFFF, G2
),
4942 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls
, 0xFFFFFFFF, G2
),
4944 /* Same as G2, with little-endian mode support */
4945 POWERPC_DEF("G2le", CPU_POWERPC_G2LE
, 0xFFFFFFFF, G2LE
),
4946 /* PowerPC G2LE GP */
4947 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp
, 0xFFFFFFFF, G2LE
),
4948 /* PowerPC G2LE LS */
4949 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls
, 0xFFFFFFFF, G2LE
),
4951 POWERPC_DEF("604", CPU_POWERPC_604
, 0xFFFFFFFF, 604),
4953 POWERPC_DEF("604e", CPU_POWERPC_604E
, 0xFFFFFFFF, 604),
4954 /* PowerPC 604e v1.0 */
4955 POWERPC_DEF("604e1.0", CPU_POWERPC_604E_v10
, 0xFFFFFFFF, 604),
4956 /* PowerPC 604e v2.2 */
4957 POWERPC_DEF("604e2.2", CPU_POWERPC_604E_v22
, 0xFFFFFFFF, 604),
4958 /* PowerPC 604e v2.4 */
4959 POWERPC_DEF("604e2.4", CPU_POWERPC_604E_v24
, 0xFFFFFFFF, 604),
4961 POWERPC_DEF("604r", CPU_POWERPC_604R
, 0xFFFFFFFF, 604),
4964 POWERPC_DEF("604ev", CPU_POWERPC_604EV
, 0xFFFFFFFF, 604),
4966 /* PowerPC 7xx family */
4967 /* Generic PowerPC 740 (G3) */
4968 POWERPC_DEF("740", CPU_POWERPC_7x0
, 0xFFFFFFFF, 7x0
),
4969 /* Generic PowerPC 750 (G3) */
4970 POWERPC_DEF("750", CPU_POWERPC_7x0
, 0xFFFFFFFF, 7x0
),
4971 /* Code name for generic PowerPC 740/750 (G3) */
4972 POWERPC_DEF("Arthur", CPU_POWERPC_7x0
, 0xFFFFFFFF, 7x0
),
4973 /* PowerPC 740/750 is also known as G3 */
4974 POWERPC_DEF("G3", CPU_POWERPC_7x0
, 0xFFFFFFFF, 7x0
),
4975 /* PowerPC 740 v2.0 (G3) */
4976 POWERPC_DEF("740v2.0", CPU_POWERPC_7x0_v20
, 0xFFFFFFFF, 7x0
),
4977 /* PowerPC 750 v2.0 (G3) */
4978 POWERPC_DEF("750v2.0", CPU_POWERPC_7x0_v20
, 0xFFFFFFFF, 7x0
),
4979 /* PowerPC 740 v2.1 (G3) */
4980 POWERPC_DEF("740v2.1", CPU_POWERPC_7x0_v21
, 0xFFFFFFFF, 7x0
),
4981 /* PowerPC 750 v2.1 (G3) */
4982 POWERPC_DEF("750v2.1", CPU_POWERPC_7x0_v21
, 0xFFFFFFFF, 7x0
),
4983 /* PowerPC 740 v2.2 (G3) */
4984 POWERPC_DEF("740v2.2", CPU_POWERPC_7x0_v22
, 0xFFFFFFFF, 7x0
),
4985 /* PowerPC 750 v2.2 (G3) */
4986 POWERPC_DEF("750v2.2", CPU_POWERPC_7x0_v22
, 0xFFFFFFFF, 7x0
),
4987 /* PowerPC 740 v3.0 (G3) */
4988 POWERPC_DEF("740v3.0", CPU_POWERPC_7x0_v30
, 0xFFFFFFFF, 7x0
),
4989 /* PowerPC 750 v3.0 (G3) */
4990 POWERPC_DEF("750v3.0", CPU_POWERPC_7x0_v30
, 0xFFFFFFFF, 7x0
),
4991 /* PowerPC 740 v3.1 (G3) */
4992 POWERPC_DEF("740v3.1", CPU_POWERPC_7x0_v31
, 0xFFFFFFFF, 7x0
),
4993 /* PowerPC 750 v3.1 (G3) */
4994 POWERPC_DEF("750v3.1", CPU_POWERPC_7x0_v31
, 0xFFFFFFFF, 7x0
),
4995 /* PowerPC 740E (G3) */
4996 POWERPC_DEF("740e", CPU_POWERPC_740E
, 0xFFFFFFFF, 7x0
),
4997 /* PowerPC 740P (G3) */
4998 POWERPC_DEF("740p", CPU_POWERPC_7x0P
, 0xFFFFFFFF, 7x0
),
4999 /* PowerPC 750P (G3) */
5000 POWERPC_DEF("750p", CPU_POWERPC_7x0P
, 0xFFFFFFFF, 7x0
),
5001 /* Code name for PowerPC 740P/750P (G3) */
5002 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P
, 0xFFFFFFFF, 7x0
),
5003 /* PowerPC 750CL (G3 embedded) */
5004 POWERPC_DEF("750cl", CPU_POWERPC_750CL
, 0xFFFFFFFF, 7x0
),
5005 /* PowerPC 750CX (G3 embedded) */
5006 POWERPC_DEF("750cx", CPU_POWERPC_750CX
, 0xFFFFFFFF, 7x0
),
5007 /* PowerPC 750CX v2.1 (G3 embedded) */
5008 POWERPC_DEF("750cx2.1", CPU_POWERPC_750CX_v21
, 0xFFFFFFFF, 7x0
),
5009 /* PowerPC 750CX v2.2 (G3 embedded) */
5010 POWERPC_DEF("750cx2.2", CPU_POWERPC_750CX_v22
, 0xFFFFFFFF, 7x0
),
5011 /* PowerPC 750CXe (G3 embedded) */
5012 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE
, 0xFFFFFFFF, 7x0
),
5013 /* PowerPC 750CXe v2.1 (G3 embedded) */
5014 POWERPC_DEF("750cxe21", CPU_POWERPC_750CXE_v21
, 0xFFFFFFFF, 7x0
),
5015 /* PowerPC 750CXe v2.2 (G3 embedded) */
5016 POWERPC_DEF("750cxe22", CPU_POWERPC_750CXE_v22
, 0xFFFFFFFF, 7x0
),
5017 /* PowerPC 750CXe v2.3 (G3 embedded) */
5018 POWERPC_DEF("750cxe23", CPU_POWERPC_750CXE_v23
, 0xFFFFFFFF, 7x0
),
5019 /* PowerPC 750CXe v2.4 (G3 embedded) */
5020 POWERPC_DEF("750cxe24", CPU_POWERPC_750CXE_v24
, 0xFFFFFFFF, 7x0
),
5021 /* PowerPC 750CXe v2.4b (G3 embedded) */
5022 POWERPC_DEF("750cxe24b", CPU_POWERPC_750CXE_v24b
, 0xFFFFFFFF, 7x0
),
5023 /* PowerPC 750CXe v3.1 (G3 embedded) */
5024 POWERPC_DEF("750cxe31", CPU_POWERPC_750CXE_v31
, 0xFFFFFFFF, 7x0
),
5025 /* PowerPC 750CXe v3.1b (G3 embedded) */
5026 POWERPC_DEF("750cxe3.1b", CPU_POWERPC_750CXE_v31b
, 0xFFFFFFFF, 7x0
),
5027 /* PowerPC 750CXr (G3 embedded) */
5028 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR
, 0xFFFFFFFF, 7x0
),
5029 /* PowerPC 750E (G3) */
5030 POWERPC_DEF("750e", CPU_POWERPC_750E
, 0xFFFFFFFF, 7x0
),
5031 /* PowerPC 750FL (G3 embedded) */
5032 POWERPC_DEF("750fl", CPU_POWERPC_750FL
, 0xFFFFFFFF, 750fx
),
5033 /* PowerPC 750FX (G3 embedded) */
5034 POWERPC_DEF("750fx", CPU_POWERPC_750FX
, 0xFFFFFFFF, 750fx
),
5035 /* PowerPC 750FX v1.0 (G3 embedded) */
5036 POWERPC_DEF("750fx1.0", CPU_POWERPC_750FX_v10
, 0xFFFFFFFF, 750fx
),
5037 /* PowerPC 750FX v2.0 (G3 embedded) */
5038 POWERPC_DEF("750fx2.0", CPU_POWERPC_750FX_v20
, 0xFFFFFFFF, 750fx
),
5039 /* PowerPC 750FX v2.1 (G3 embedded) */
5040 POWERPC_DEF("750fx2.1", CPU_POWERPC_750FX_v21
, 0xFFFFFFFF, 750fx
),
5041 /* PowerPC 750FX v2.2 (G3 embedded) */
5042 POWERPC_DEF("750fx2.2", CPU_POWERPC_750FX_v22
, 0xFFFFFFFF, 750fx
),
5043 /* PowerPC 750FX v2.3 (G3 embedded) */
5044 POWERPC_DEF("750fx2.3", CPU_POWERPC_750FX_v23
, 0xFFFFFFFF, 750fx
),
5045 /* PowerPC 750GL (G3 embedded) */
5046 POWERPC_DEF("750gl", CPU_POWERPC_750GL
, 0xFFFFFFFF, 750fx
),
5047 /* PowerPC 750GX (G3 embedded) */
5048 POWERPC_DEF("750gx", CPU_POWERPC_750GX
, 0xFFFFFFFF, 750fx
),
5049 /* PowerPC 750GX v1.0 (G3 embedded) */
5050 POWERPC_DEF("750gx1.0", CPU_POWERPC_750GX_v10
, 0xFFFFFFFF, 750fx
),
5051 /* PowerPC 750GX v1.1 (G3 embedded) */
5052 POWERPC_DEF("750gx1.1", CPU_POWERPC_750GX_v11
, 0xFFFFFFFF, 750fx
),
5053 /* PowerPC 750GX v1.2 (G3 embedded) */
5054 POWERPC_DEF("750gx1.2", CPU_POWERPC_750GX_v12
, 0xFFFFFFFF, 750fx
),
5055 /* PowerPC 750L (G3 embedded) */
5056 POWERPC_DEF("750l", CPU_POWERPC_750L
, 0xFFFFFFFF, 7x0
),
5057 /* Code name for PowerPC 750L (G3 embedded) */
5058 POWERPC_DEF("LoneStar", CPU_POWERPC_750L
, 0xFFFFFFFF, 7x0
),
5059 /* PowerPC 750L v2.2 (G3 embedded) */
5060 POWERPC_DEF("750l2.2", CPU_POWERPC_750L_v22
, 0xFFFFFFFF, 7x0
),
5061 /* PowerPC 750L v3.0 (G3 embedded) */
5062 POWERPC_DEF("750l3.0", CPU_POWERPC_750L_v30
, 0xFFFFFFFF, 7x0
),
5063 /* PowerPC 750L v3.2 (G3 embedded) */
5064 POWERPC_DEF("750l3.2", CPU_POWERPC_750L_v32
, 0xFFFFFFFF, 7x0
),
5065 /* Generic PowerPC 745 */
5066 POWERPC_DEF("745", CPU_POWERPC_7x5
, 0xFFFFFFFF, 7x5
),
5067 /* Generic PowerPC 755 */
5068 POWERPC_DEF("755", CPU_POWERPC_7x5
, 0xFFFFFFFF, 7x5
),
5069 /* Code name for PowerPC 745/755 */
5070 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5
, 0xFFFFFFFF, 7x5
),
5071 /* PowerPC 745 v1.0 */
5072 POWERPC_DEF("745v1.0", CPU_POWERPC_7x5_v10
, 0xFFFFFFFF, 7x5
),
5073 /* PowerPC 755 v1.0 */
5074 POWERPC_DEF("755v1.0", CPU_POWERPC_7x5_v10
, 0xFFFFFFFF, 7x5
),
5075 /* PowerPC 745 v1.1 */
5076 POWERPC_DEF("745v1.1", CPU_POWERPC_7x5_v11
, 0xFFFFFFFF, 7x5
),
5077 /* PowerPC 755 v1.1 */
5078 POWERPC_DEF("755v1.1", CPU_POWERPC_7x5_v11
, 0xFFFFFFFF, 7x5
),
5079 /* PowerPC 745 v2.0 */
5080 POWERPC_DEF("745v2.0", CPU_POWERPC_7x5_v20
, 0xFFFFFFFF, 7x5
),
5081 /* PowerPC 755 v2.0 */
5082 POWERPC_DEF("755v2.0", CPU_POWERPC_7x5_v20
, 0xFFFFFFFF, 7x5
),
5083 /* PowerPC 745 v2.1 */
5084 POWERPC_DEF("745v2.1", CPU_POWERPC_7x5_v21
, 0xFFFFFFFF, 7x5
),
5085 /* PowerPC 755 v2.1 */
5086 POWERPC_DEF("755v2.1", CPU_POWERPC_7x5_v21
, 0xFFFFFFFF, 7x5
),
5087 /* PowerPC 745 v2.2 */
5088 POWERPC_DEF("745v2.2", CPU_POWERPC_7x5_v22
, 0xFFFFFFFF, 7x5
),
5089 /* PowerPC 755 v2.2 */
5090 POWERPC_DEF("755v2.2", CPU_POWERPC_7x5_v22
, 0xFFFFFFFF, 7x5
),
5091 /* PowerPC 745 v2.3 */
5092 POWERPC_DEF("745v2.3", CPU_POWERPC_7x5_v23
, 0xFFFFFFFF, 7x5
),
5093 /* PowerPC 755 v2.3 */
5094 POWERPC_DEF("755v2.3", CPU_POWERPC_7x5_v23
, 0xFFFFFFFF, 7x5
),
5095 /* PowerPC 745 v2.4 */
5096 POWERPC_DEF("745v2.4", CPU_POWERPC_7x5_v24
, 0xFFFFFFFF, 7x5
),
5097 /* PowerPC 755 v2.4 */
5098 POWERPC_DEF("755v2.4", CPU_POWERPC_7x5_v24
, 0xFFFFFFFF, 7x5
),
5099 /* PowerPC 745 v2.5 */
5100 POWERPC_DEF("745v2.5", CPU_POWERPC_7x5_v25
, 0xFFFFFFFF, 7x5
),
5101 /* PowerPC 755 v2.5 */
5102 POWERPC_DEF("755v2.5", CPU_POWERPC_7x5_v25
, 0xFFFFFFFF, 7x5
),
5103 /* PowerPC 745 v2.6 */
5104 POWERPC_DEF("745v2.6", CPU_POWERPC_7x5_v26
, 0xFFFFFFFF, 7x5
),
5105 /* PowerPC 755 v2.6 */
5106 POWERPC_DEF("755v2.6", CPU_POWERPC_7x5_v26
, 0xFFFFFFFF, 7x5
),
5107 /* PowerPC 745 v2.7 */
5108 POWERPC_DEF("745v2.7", CPU_POWERPC_7x5_v27
, 0xFFFFFFFF, 7x5
),
5109 /* PowerPC 755 v2.7 */
5110 POWERPC_DEF("755v2.7", CPU_POWERPC_7x5_v27
, 0xFFFFFFFF, 7x5
),
5111 /* PowerPC 745 v2.8 */
5112 POWERPC_DEF("745v2.8", CPU_POWERPC_7x5_v28
, 0xFFFFFFFF, 7x5
),
5113 /* PowerPC 755 v2.8 */
5114 POWERPC_DEF("755v2.8", CPU_POWERPC_7x5_v28
, 0xFFFFFFFF, 7x5
),
5116 /* PowerPC 745P (G3) */
5117 POWERPC_DEF("745p", CPU_POWERPC_7x5P
, 0xFFFFFFFF, 7x5
),
5118 /* PowerPC 755P (G3) */
5119 POWERPC_DEF("755p", CPU_POWERPC_7x5P
, 0xFFFFFFFF, 7x5
),
5121 /* PowerPC 74xx family */
5122 /* PowerPC 7400 (G4) */
5123 POWERPC_DEF("7400", CPU_POWERPC_7400
, 0xFFFFFFFF, 7400),
5124 /* Code name for PowerPC 7400 */
5125 POWERPC_DEF("Max", CPU_POWERPC_7400
, 0xFFFFFFFF, 7400),
5126 /* PowerPC 74xx is also well known as G4 */
5127 POWERPC_DEF("G4", CPU_POWERPC_7400
, 0xFFFFFFFF, 7400),
5128 /* PowerPC 7400 v1.0 (G4) */
5129 POWERPC_DEF("7400v1.0", CPU_POWERPC_7400_v10
, 0xFFFFFFFF, 7400),
5130 /* PowerPC 7400 v1.1 (G4) */
5131 POWERPC_DEF("7400v1.1", CPU_POWERPC_7400_v11
, 0xFFFFFFFF, 7400),
5132 /* PowerPC 7400 v2.0 (G4) */
5133 POWERPC_DEF("7400v2.0", CPU_POWERPC_7400_v20
, 0xFFFFFFFF, 7400),
5134 /* PowerPC 7400 v2.2 (G4) */
5135 POWERPC_DEF("7400v2.2", CPU_POWERPC_7400_v22
, 0xFFFFFFFF, 7400),
5136 /* PowerPC 7400 v2.6 (G4) */
5137 POWERPC_DEF("7400v2.6", CPU_POWERPC_7400_v26
, 0xFFFFFFFF, 7400),
5138 /* PowerPC 7400 v2.7 (G4) */
5139 POWERPC_DEF("7400v2.7", CPU_POWERPC_7400_v27
, 0xFFFFFFFF, 7400),
5140 /* PowerPC 7400 v2.8 (G4) */
5141 POWERPC_DEF("7400v2.8", CPU_POWERPC_7400_v28
, 0xFFFFFFFF, 7400),
5142 /* PowerPC 7400 v2.9 (G4) */
5143 POWERPC_DEF("7400v2.9", CPU_POWERPC_7400_v29
, 0xFFFFFFFF, 7400),
5144 /* PowerPC 7410 (G4) */
5145 POWERPC_DEF("7410", CPU_POWERPC_7410
, 0xFFFFFFFF, 7410),
5146 /* Code name for PowerPC 7410 */
5147 POWERPC_DEF("Nitro", CPU_POWERPC_7410
, 0xFFFFFFFF, 7410),
5148 /* PowerPC 7410 v1.0 (G4) */
5149 POWERPC_DEF("7410v1.0", CPU_POWERPC_7410_v10
, 0xFFFFFFFF, 7410),
5150 /* PowerPC 7410 v1.1 (G4) */
5151 POWERPC_DEF("7410v1.1", CPU_POWERPC_7410_v11
, 0xFFFFFFFF, 7410),
5152 /* PowerPC 7410 v1.2 (G4) */
5153 POWERPC_DEF("7410v1.2", CPU_POWERPC_7410_v12
, 0xFFFFFFFF, 7410),
5154 /* PowerPC 7410 v1.3 (G4) */
5155 POWERPC_DEF("7410v1.3", CPU_POWERPC_7410_v13
, 0xFFFFFFFF, 7410),
5156 /* PowerPC 7410 v1.4 (G4) */
5157 POWERPC_DEF("7410v1.4", CPU_POWERPC_7410_v14
, 0xFFFFFFFF, 7410),
5158 /* PowerPC 7448 (G4) */
5159 POWERPC_DEF("7448", CPU_POWERPC_7448
, 0xFFFFFFFF, 7400),
5160 /* PowerPC 7448 v1.0 (G4) */
5161 POWERPC_DEF("7448v1.0", CPU_POWERPC_7448_v10
, 0xFFFFFFFF, 7400),
5162 /* PowerPC 7448 v1.1 (G4) */
5163 POWERPC_DEF("7448v1.1", CPU_POWERPC_7448_v11
, 0xFFFFFFFF, 7400),
5164 /* PowerPC 7448 v2.0 (G4) */
5165 POWERPC_DEF("7448v2.0", CPU_POWERPC_7448_v20
, 0xFFFFFFFF, 7400),
5166 /* PowerPC 7448 v2.1 (G4) */
5167 POWERPC_DEF("7448v2.1", CPU_POWERPC_7448_v21
, 0xFFFFFFFF, 7400),
5169 /* PowerPC 7450 (G4) */
5170 POWERPC_DEF("7450", CPU_POWERPC_7450
, 0xFFFFFFFF, 7450),
5171 /* Code name for PowerPC 7450 */
5172 POWERPC_DEF("Vger", CPU_POWERPC_7450
, 0xFFFFFFFF, 7450),
5175 /* PowerPC 7450 v1.0 (G4) */
5176 POWERPC_DEF("7450v1.0", CPU_POWERPC_7450_v10
, 0xFFFFFFFF, 7450),
5179 /* PowerPC 7450 v1.1 (G4) */
5180 POWERPC_DEF("7450v1.1", CPU_POWERPC_7450_v11
, 0xFFFFFFFF, 7450),
5183 /* PowerPC 7450 v1.2 (G4) */
5184 POWERPC_DEF("7450v1.2", CPU_POWERPC_7450_v12
, 0xFFFFFFFF, 7450),
5187 /* PowerPC 7450 v2.0 (G4) */
5188 POWERPC_DEF("7450v2.0", CPU_POWERPC_7450_v20
, 0xFFFFFFFF, 7450),
5191 /* PowerPC 7450 v2.1 (G4) */
5192 POWERPC_DEF("7450v2.1", CPU_POWERPC_7450_v21
, 0xFFFFFFFF, 7450),
5195 /* PowerPC 7441 (G4) */
5196 POWERPC_DEF("7441", CPU_POWERPC_74x1
, 0xFFFFFFFF, 7440),
5197 /* PowerPC 7451 (G4) */
5198 POWERPC_DEF("7451", CPU_POWERPC_74x1
, 0xFFFFFFFF, 7450),
5201 /* PowerPC 7441g (G4) */
5202 POWERPC_DEF("7441g", CPU_POWERPC_74x1G
, 0xFFFFFFFF, 7440),
5203 /* PowerPC 7451g (G4) */
5204 POWERPC_DEF("7451g", CPU_POWERPC_74x1G
, 0xFFFFFFFF, 7450),
5207 /* PowerPC 7445 (G4) */
5208 POWERPC_DEF("7445", CPU_POWERPC_74x5
, 0xFFFFFFFF, 7445),
5209 /* PowerPC 7455 (G4) */
5210 POWERPC_DEF("7455", CPU_POWERPC_74x5
, 0xFFFFFFFF, 7455),
5211 /* Code name for PowerPC 7445/7455 */
5212 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5
, 0xFFFFFFFF, 7455),
5215 /* PowerPC 7445 v1.0 (G4) */
5216 POWERPC_DEF("7445v1.0", CPU_POWERPC_74x5_v10
, 0xFFFFFFFF, 7445),
5217 /* PowerPC 7455 v1.0 (G4) */
5218 POWERPC_DEF("7455v1.0", CPU_POWERPC_74x5_v10
, 0xFFFFFFFF, 7455),
5221 /* PowerPC 7445 v2.1 (G4) */
5222 POWERPC_DEF("7445v2.1", CPU_POWERPC_74x5_v21
, 0xFFFFFFFF, 7445),
5223 /* PowerPC 7455 v2.1 (G4) */
5224 POWERPC_DEF("7455v2.1", CPU_POWERPC_74x5_v21
, 0xFFFFFFFF, 7455),
5227 /* PowerPC 7445 v3.2 (G4) */
5228 POWERPC_DEF("7445v3.2", CPU_POWERPC_74x5_v32
, 0xFFFFFFFF, 7445),
5229 /* PowerPC 7455 v3.2 (G4) */
5230 POWERPC_DEF("7455v3.2", CPU_POWERPC_74x5_v32
, 0xFFFFFFFF, 7455),
5233 /* PowerPC 7445 v3.3 (G4) */
5234 POWERPC_DEF("7445v3.3", CPU_POWERPC_74x5_v33
, 0xFFFFFFFF, 7445),
5235 /* PowerPC 7455 v3.3 (G4) */
5236 POWERPC_DEF("7455v3.3", CPU_POWERPC_74x5_v33
, 0xFFFFFFFF, 7455),
5239 /* PowerPC 7445 v3.4 (G4) */
5240 POWERPC_DEF("7445v3.4", CPU_POWERPC_74x5_v34
, 0xFFFFFFFF, 7445),
5241 /* PowerPC 7455 v3.4 (G4) */
5242 POWERPC_DEF("7455v3.4", CPU_POWERPC_74x5_v34
, 0xFFFFFFFF, 7455),
5245 /* PowerPC 7447 (G4) */
5246 POWERPC_DEF("7447", CPU_POWERPC_74x7
, 0xFFFFFFFF, 7445),
5247 /* PowerPC 7457 (G4) */
5248 POWERPC_DEF("7457", CPU_POWERPC_74x7
, 0xFFFFFFFF, 7455),
5249 /* Code name for PowerPC 7447/7457 */
5250 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7
, 0xFFFFFFFF, 7455),
5253 /* PowerPC 7447 v1.0 (G4) */
5254 POWERPC_DEF("7447v1.0", CPU_POWERPC_74x7_v10
, 0xFFFFFFFF, 7445),
5255 /* PowerPC 7457 v1.0 (G4) */
5256 POWERPC_DEF("7457v1.0", CPU_POWERPC_74x7_v10
, 0xFFFFFFFF, 7455),
5257 /* Code name for PowerPC 7447A/7457A */
5258 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10
, 0xFFFFFFFF, 7455),
5261 /* PowerPC 7447 v1.1 (G4) */
5262 POWERPC_DEF("7447v1.1", CPU_POWERPC_74x7_v11
, 0xFFFFFFFF, 7445),
5263 /* PowerPC 7457 v1.1 (G4) */
5264 POWERPC_DEF("7457v1.1", CPU_POWERPC_74x7_v11
, 0xFFFFFFFF, 7455),
5267 /* PowerPC 7447 v1.2 (G4) */
5268 POWERPC_DEF("7447v1.2", CPU_POWERPC_74x7_v12
, 0xFFFFFFFF, 7445),
5269 /* PowerPC 7457 v1.2 (G4) */
5270 POWERPC_DEF("7457v1.2", CPU_POWERPC_74x7_v12
, 0xFFFFFFFF, 7455),
5272 /* 64 bits PowerPC */
5273 #if defined (TARGET_PPC64)
5276 POWERPC_DEF("620", CPU_POWERPC_620
, 0xFFFFFFFF, 620),
5279 /* PowerPC 630 (POWER3) */
5280 POWERPC_DEF("630", CPU_POWERPC_630
, 0xFFFFFFFF, 630),
5281 POWERPC_DEF("POWER3", CPU_POWERPC_630
, 0xFFFFFFFF, 630),
5284 /* PowerPC 631 (Power 3+) */
5285 POWERPC_DEF("631", CPU_POWERPC_631
, 0xFFFFFFFF, 631),
5286 POWERPC_DEF("POWER3+", CPU_POWERPC_631
, 0xFFFFFFFF, 631),
5290 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4
, 0xFFFFFFFF, POWER4
),
5294 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P
, 0xFFFFFFFF, POWER4P
),
5298 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5
, 0xFFFFFFFF, POWER5
),
5300 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR
, 0xFFFFFFFF, POWER5
),
5304 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P
, 0xFFFFFFFF, POWER5P
),
5306 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS
, 0xFFFFFFFF, POWER5P
),
5310 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6
, 0xFFFFFFFF, POWER6
),
5311 /* POWER6 running in POWER5 mode */
5312 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5
, 0xFFFFFFFF, POWER5
),
5314 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A
, 0xFFFFFFFF, POWER6
),
5317 POWERPC_DEF("970", CPU_POWERPC_970
, 0xFFFFFFFF, 970),
5318 /* PowerPC 970FX (G5) */
5319 POWERPC_DEF("970fx", CPU_POWERPC_970FX
, 0xFFFFFFFF, 970FX
),
5320 /* PowerPC 970FX v1.0 (G5) */
5321 POWERPC_DEF("970fx1.0", CPU_POWERPC_970FX_v10
, 0xFFFFFFFF, 970FX
),
5322 /* PowerPC 970FX v2.0 (G5) */
5323 POWERPC_DEF("970fx2.0", CPU_POWERPC_970FX_v20
, 0xFFFFFFFF, 970FX
),
5324 /* PowerPC 970FX v2.1 (G5) */
5325 POWERPC_DEF("970fx2.1", CPU_POWERPC_970FX_v21
, 0xFFFFFFFF, 970FX
),
5326 /* PowerPC 970FX v3.0 (G5) */
5327 POWERPC_DEF("970fx3.0", CPU_POWERPC_970FX_v30
, 0xFFFFFFFF, 970FX
),
5328 /* PowerPC 970FX v3.1 (G5) */
5329 POWERPC_DEF("970fx3.1", CPU_POWERPC_970FX_v31
, 0xFFFFFFFF, 970FX
),
5330 /* PowerPC 970GX (G5) */
5331 POWERPC_DEF("970gx", CPU_POWERPC_970GX
, 0xFFFFFFFF, 970GX
),
5333 POWERPC_DEF("970mp", CPU_POWERPC_970MP
, 0xFFFFFFFF, 970),
5334 /* PowerPC 970MP v1.0 */
5335 POWERPC_DEF("970mp1.0", CPU_POWERPC_970MP_v10
, 0xFFFFFFFF, 970),
5336 /* PowerPC 970MP v1.1 */
5337 POWERPC_DEF("970mp1.1", CPU_POWERPC_970MP_v11
, 0xFFFFFFFF, 970),
5340 POWERPC_DEF("Cell", CPU_POWERPC_CELL
, 0xFFFFFFFF, 970),
5343 /* PowerPC Cell v1.0 */
5344 POWERPC_DEF("Cell1.0", CPU_POWERPC_CELL_v10
, 0xFFFFFFFF, 970),
5347 /* PowerPC Cell v2.0 */
5348 POWERPC_DEF("Cell2.0", CPU_POWERPC_CELL_v20
, 0xFFFFFFFF, 970),
5351 /* PowerPC Cell v3.0 */
5352 POWERPC_DEF("Cell3.0", CPU_POWERPC_CELL_v30
, 0xFFFFFFFF, 970),
5355 /* PowerPC Cell v3.1 */
5356 POWERPC_DEF("Cell3.1", CPU_POWERPC_CELL_v31
, 0xFFFFFFFF, 970),
5359 /* PowerPC Cell v3.2 */
5360 POWERPC_DEF("Cell3.2", CPU_POWERPC_CELL_v32
, 0xFFFFFFFF, 970),
5363 /* RS64 (Apache/A35) */
5364 /* This one seems to support the whole POWER2 instruction set
5365 * and the PowerPC 64 one.
5367 /* What about A10 & A30 ? */
5368 POWERPC_DEF("RS64", CPU_POWERPC_RS64
, 0xFFFFFFFF, RS64
),
5369 POWERPC_DEF("Apache", CPU_POWERPC_RS64
, 0xFFFFFFFF, RS64
),
5370 POWERPC_DEF("A35", CPU_POWERPC_RS64
, 0xFFFFFFFF, RS64
),
5373 /* RS64-II (NorthStar/A50) */
5374 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II
, 0xFFFFFFFF, RS64
),
5375 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II
, 0xFFFFFFFF, RS64
),
5376 POWERPC_DEF("A50", CPU_POWERPC_RS64II
, 0xFFFFFFFF, RS64
),
5379 /* RS64-III (Pulsar) */
5380 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III
, 0xFFFFFFFF, RS64
),
5381 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III
, 0xFFFFFFFF, RS64
),
5384 /* RS64-IV (IceStar/IStar/SStar) */
5385 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV
, 0xFFFFFFFF, RS64
),
5386 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV
, 0xFFFFFFFF, RS64
),
5387 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV
, 0xFFFFFFFF, RS64
),
5388 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV
, 0xFFFFFFFF, RS64
),
5390 #endif /* defined (TARGET_PPC64) */
5393 /* Original POWER */
5394 POWERPC_DEF("POWER", CPU_POWERPC_POWER
, 0xFFFFFFFF, POWER
),
5395 POWERPC_DEF("RIOS", CPU_POWERPC_POWER
, 0xFFFFFFFF, POWER
),
5396 POWERPC_DEF("RSC", CPU_POWERPC_POWER
, 0xFFFFFFFF, POWER
),
5397 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER
, 0xFFFFFFFF, POWER
),
5398 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER
, 0xFFFFFFFF, POWER
),
5402 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2
, 0xFFFFFFFF, POWER
),
5403 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2
, 0xFFFFFFFF, POWER
),
5404 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2
, 0xFFFFFFFF, POWER
),
5409 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T
, 0xFFFFFFFF, PA6T
),
5411 /* Generic PowerPCs */
5412 #if defined (TARGET_PPC64)
5414 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64
, 0xFFFFFFFF, PPC64
),
5417 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32
, 0xFFFFFFFF, PPC32
),
5418 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT
, 0xFFFFFFFF, DEFAULT
),
5420 POWERPC_DEF("default", CPU_POWERPC_DEFAULT
, 0xFFFFFFFF, DEFAULT
),
5423 /*****************************************************************************/
5424 /* Generic CPU instanciation routine */
5425 static void init_ppc_proc (CPUPPCState
*env
, ppc_def_t
*def
)
5427 #if !defined(CONFIG_USER_ONLY)
5430 env
->irq_inputs
= NULL
;
5431 /* Set all exception vectors to an invalid address */
5432 for (i
= 0; i
< POWERPC_EXCP_NB
; i
++)
5433 env
->excp_vectors
[i
] = (target_ulong
)(-1ULL);
5434 env
->excp_prefix
= 0x00000000;
5435 env
->ivor_mask
= 0x00000000;
5436 env
->ivpr_mask
= 0x00000000;
5438 /* Default MMU definitions */
5442 /* Register SPR common to all PowerPC implementations */
5443 gen_spr_generic(env
);
5444 spr_register(env
, SPR_PVR
, "PVR",
5445 SPR_NOACCESS
, SPR_NOACCESS
,
5446 &spr_read_generic
, SPR_NOACCESS
,
5448 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
5449 (*def
->init_proc
)(env
);
5450 /* Allocate TLBs buffer when needed */
5451 if (env
->nb_tlb
!= 0) {
5452 int nb_tlb
= env
->nb_tlb
;
5453 if (env
->id_tlbs
!= 0)
5455 env
->tlb
= qemu_mallocz(nb_tlb
* sizeof(ppc_tlb_t
));
5456 /* Pre-compute some useful values */
5457 env
->tlb_per_way
= env
->nb_tlb
/ env
->nb_ways
;
5459 #if !defined(CONFIG_USER_ONLY)
5460 if (env
->irq_inputs
== NULL
) {
5461 fprintf(stderr
, "WARNING: no internal IRQ controller registered.\n"
5462 " Attempt Qemu to crash very soon !\n");
5467 #if defined(PPC_DUMP_CPU)
5468 static void dump_ppc_sprs (CPUPPCState
*env
)
5471 #if !defined(CONFIG_USER_ONLY)
5477 printf("Special purpose registers:\n");
5478 for (i
= 0; i
< 32; i
++) {
5479 for (j
= 0; j
< 32; j
++) {
5481 spr
= &env
->spr_cb
[n
];
5482 uw
= spr
->uea_write
!= NULL
&& spr
->uea_write
!= SPR_NOACCESS
;
5483 ur
= spr
->uea_read
!= NULL
&& spr
->uea_read
!= SPR_NOACCESS
;
5484 #if !defined(CONFIG_USER_ONLY)
5485 sw
= spr
->oea_write
!= NULL
&& spr
->oea_write
!= SPR_NOACCESS
;
5486 sr
= spr
->oea_read
!= NULL
&& spr
->oea_read
!= SPR_NOACCESS
;
5487 if (sw
|| sr
|| uw
|| ur
) {
5488 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
5489 (i
<< 5) | j
, (i
<< 5) | j
, spr
->name
,
5490 sw
? 'w' : '-', sr
? 'r' : '-',
5491 uw
? 'w' : '-', ur
? 'r' : '-');
5495 printf("SPR: %4d (%03x) %-8s u%c%c\n",
5496 (i
<< 5) | j
, (i
<< 5) | j
, spr
->name
,
5497 uw
? 'w' : '-', ur
? 'r' : '-');
5507 /*****************************************************************************/
5511 int fflush (FILE *stream
);
5515 PPC_DIRECT
= 0, /* Opcode routine */
5516 PPC_INDIRECT
= 1, /* Indirect opcode table */
5519 static inline int is_indirect_opcode (void *handler
)
5521 return ((unsigned long)handler
& 0x03) == PPC_INDIRECT
;
5524 static inline opc_handler_t
**ind_table(void *handler
)
5526 return (opc_handler_t
**)((unsigned long)handler
& ~3);
5529 /* Instruction table creation */
5530 /* Opcodes tables creation */
5531 static void fill_new_table (opc_handler_t
**table
, int len
)
5535 for (i
= 0; i
< len
; i
++)
5536 table
[i
] = &invalid_handler
;
5539 static int create_new_table (opc_handler_t
**table
, unsigned char idx
)
5541 opc_handler_t
**tmp
;
5543 tmp
= malloc(0x20 * sizeof(opc_handler_t
));
5546 fill_new_table(tmp
, 0x20);
5547 table
[idx
] = (opc_handler_t
*)((unsigned long)tmp
| PPC_INDIRECT
);
5552 static int insert_in_table (opc_handler_t
**table
, unsigned char idx
,
5553 opc_handler_t
*handler
)
5555 if (table
[idx
] != &invalid_handler
)
5557 table
[idx
] = handler
;
5562 static int register_direct_insn (opc_handler_t
**ppc_opcodes
,
5563 unsigned char idx
, opc_handler_t
*handler
)
5565 if (insert_in_table(ppc_opcodes
, idx
, handler
) < 0) {
5566 printf("*** ERROR: opcode %02x already assigned in main "
5567 "opcode table\n", idx
);
5574 static int register_ind_in_table (opc_handler_t
**table
,
5575 unsigned char idx1
, unsigned char idx2
,
5576 opc_handler_t
*handler
)
5578 if (table
[idx1
] == &invalid_handler
) {
5579 if (create_new_table(table
, idx1
) < 0) {
5580 printf("*** ERROR: unable to create indirect table "
5581 "idx=%02x\n", idx1
);
5585 if (!is_indirect_opcode(table
[idx1
])) {
5586 printf("*** ERROR: idx %02x already assigned to a direct "
5591 if (handler
!= NULL
&&
5592 insert_in_table(ind_table(table
[idx1
]), idx2
, handler
) < 0) {
5593 printf("*** ERROR: opcode %02x already assigned in "
5594 "opcode table %02x\n", idx2
, idx1
);
5601 static int register_ind_insn (opc_handler_t
**ppc_opcodes
,
5602 unsigned char idx1
, unsigned char idx2
,
5603 opc_handler_t
*handler
)
5607 ret
= register_ind_in_table(ppc_opcodes
, idx1
, idx2
, handler
);
5612 static int register_dblind_insn (opc_handler_t
**ppc_opcodes
,
5613 unsigned char idx1
, unsigned char idx2
,
5614 unsigned char idx3
, opc_handler_t
*handler
)
5616 if (register_ind_in_table(ppc_opcodes
, idx1
, idx2
, NULL
) < 0) {
5617 printf("*** ERROR: unable to join indirect table idx "
5618 "[%02x-%02x]\n", idx1
, idx2
);
5621 if (register_ind_in_table(ind_table(ppc_opcodes
[idx1
]), idx2
, idx3
,
5623 printf("*** ERROR: unable to insert opcode "
5624 "[%02x-%02x-%02x]\n", idx1
, idx2
, idx3
);
5631 static int register_insn (opc_handler_t
**ppc_opcodes
, opcode_t
*insn
)
5633 if (insn
->opc2
!= 0xFF) {
5634 if (insn
->opc3
!= 0xFF) {
5635 if (register_dblind_insn(ppc_opcodes
, insn
->opc1
, insn
->opc2
,
5636 insn
->opc3
, &insn
->handler
) < 0)
5639 if (register_ind_insn(ppc_opcodes
, insn
->opc1
,
5640 insn
->opc2
, &insn
->handler
) < 0)
5644 if (register_direct_insn(ppc_opcodes
, insn
->opc1
, &insn
->handler
) < 0)
5651 static int test_opcode_table (opc_handler_t
**table
, int len
)
5655 for (i
= 0, count
= 0; i
< len
; i
++) {
5656 /* Consistency fixup */
5657 if (table
[i
] == NULL
)
5658 table
[i
] = &invalid_handler
;
5659 if (table
[i
] != &invalid_handler
) {
5660 if (is_indirect_opcode(table
[i
])) {
5661 tmp
= test_opcode_table(ind_table(table
[i
]), 0x20);
5664 table
[i
] = &invalid_handler
;
5677 static void fix_opcode_tables (opc_handler_t
**ppc_opcodes
)
5679 if (test_opcode_table(ppc_opcodes
, 0x40) == 0)
5680 printf("*** WARNING: no opcode defined !\n");
5683 /*****************************************************************************/
5684 static int create_ppc_opcodes (CPUPPCState
*env
, ppc_def_t
*def
)
5686 opcode_t
*opc
, *start
, *end
;
5688 fill_new_table(env
->opcodes
, 0x40);
5689 if (&opc_start
< &opc_end
) {
5696 for (opc
= start
+ 1; opc
!= end
; opc
++) {
5697 if ((opc
->handler
.type
& def
->insns_flags
) != 0) {
5698 if (register_insn(env
->opcodes
, opc
) < 0) {
5699 printf("*** ERROR initializing PowerPC instruction "
5700 "0x%02x 0x%02x 0x%02x\n", opc
->opc1
, opc
->opc2
,
5706 fix_opcode_tables(env
->opcodes
);
5713 #if defined(PPC_DUMP_CPU)
5714 static int dump_ppc_insns (CPUPPCState
*env
)
5716 opc_handler_t
**table
, *handler
;
5717 uint8_t opc1
, opc2
, opc3
;
5719 printf("Instructions set:\n");
5720 /* opc1 is 6 bits long */
5721 for (opc1
= 0x00; opc1
< 0x40; opc1
++) {
5722 table
= env
->opcodes
;
5723 handler
= table
[opc1
];
5724 if (is_indirect_opcode(handler
)) {
5725 /* opc2 is 5 bits long */
5726 for (opc2
= 0; opc2
< 0x20; opc2
++) {
5727 table
= env
->opcodes
;
5728 handler
= env
->opcodes
[opc1
];
5729 table
= ind_table(handler
);
5730 handler
= table
[opc2
];
5731 if (is_indirect_opcode(handler
)) {
5732 table
= ind_table(handler
);
5733 /* opc3 is 5 bits long */
5734 for (opc3
= 0; opc3
< 0x20; opc3
++) {
5735 handler
= table
[opc3
];
5736 if (handler
->handler
!= &gen_invalid
) {
5737 printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
5738 opc1
, opc2
, opc3
, opc1
, (opc3
<< 5) | opc2
,
5743 if (handler
->handler
!= &gen_invalid
) {
5744 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
5745 opc1
, opc2
, opc1
, opc2
, handler
->oname
);
5750 if (handler
->handler
!= &gen_invalid
) {
5751 printf("INSN: %02x -- -- (%02d ----) : %s\n",
5752 opc1
, opc1
, handler
->oname
);
5759 int cpu_ppc_register (CPUPPCState
*env
, ppc_def_t
*def
)
5761 env
->msr_mask
= def
->msr_mask
;
5762 env
->mmu_model
= def
->mmu_model
;
5763 env
->excp_model
= def
->excp_model
;
5764 env
->bus_model
= def
->bus_model
;
5765 env
->bfd_mach
= def
->bfd_mach
;
5766 if (create_ppc_opcodes(env
, def
) < 0)
5768 init_ppc_proc(env
, def
);
5769 #if defined(PPC_DUMP_CPU)
5771 const unsigned char *mmu_model
, *excp_model
, *bus_model
;
5772 switch (env
->mmu_model
) {
5773 case POWERPC_MMU_32B
:
5774 mmu_model
= "PowerPC 32";
5776 case POWERPC_MMU_64B
:
5777 mmu_model
= "PowerPC 64";
5779 case POWERPC_MMU_601
:
5780 mmu_model
= "PowerPC 601";
5782 case POWERPC_MMU_SOFT_6xx
:
5783 mmu_model
= "PowerPC 6xx/7xx with software driven TLBs";
5785 case POWERPC_MMU_SOFT_74xx
:
5786 mmu_model
= "PowerPC 74xx with software driven TLBs";
5788 case POWERPC_MMU_SOFT_4xx
:
5789 mmu_model
= "PowerPC 4xx with software driven TLBs";
5791 case POWERPC_MMU_SOFT_4xx_Z
:
5792 mmu_model
= "PowerPC 4xx with software driven TLBs "
5793 "and zones protections";
5795 case POWERPC_MMU_REAL_4xx
:
5796 mmu_model
= "PowerPC 4xx real mode only";
5798 case POWERPC_MMU_BOOKE
:
5799 mmu_model
= "PowerPC BookE";
5801 case POWERPC_MMU_BOOKE_FSL
:
5802 mmu_model
= "PowerPC BookE FSL";
5804 case POWERPC_MMU_64BRIDGE
:
5805 mmu_model
= "PowerPC 64 bridge";
5808 mmu_model
= "Unknown or invalid";
5811 switch (env
->excp_model
) {
5812 case POWERPC_EXCP_STD
:
5813 excp_model
= "PowerPC";
5815 case POWERPC_EXCP_40x
:
5816 excp_model
= "PowerPC 40x";
5818 case POWERPC_EXCP_601
:
5819 excp_model
= "PowerPC 601";
5821 case POWERPC_EXCP_602
:
5822 excp_model
= "PowerPC 602";
5824 case POWERPC_EXCP_603
:
5825 excp_model
= "PowerPC 603";
5827 case POWERPC_EXCP_603E
:
5828 excp_model
= "PowerPC 603e";
5830 case POWERPC_EXCP_604
:
5831 excp_model
= "PowerPC 604";
5833 case POWERPC_EXCP_7x0
:
5834 excp_model
= "PowerPC 740/750";
5836 case POWERPC_EXCP_7x5
:
5837 excp_model
= "PowerPC 745/755";
5839 case POWERPC_EXCP_74xx
:
5840 excp_model
= "PowerPC 74xx";
5842 case POWERPC_EXCP_970
:
5843 excp_model
= "PowerPC 970";
5845 case POWERPC_EXCP_BOOKE
:
5846 excp_model
= "PowerPC BookE";
5849 excp_model
= "Unknown or invalid";
5852 switch (env
->bus_model
) {
5853 case PPC_FLAGS_INPUT_6xx
:
5854 bus_model
= "PowerPC 6xx";
5856 case PPC_FLAGS_INPUT_BookE
:
5857 bus_model
= "PowerPC BookE";
5859 case PPC_FLAGS_INPUT_405
:
5860 bus_model
= "PowerPC 405";
5862 case PPC_FLAGS_INPUT_970
:
5863 bus_model
= "PowerPC 970";
5865 case PPC_FLAGS_INPUT_401
:
5866 bus_model
= "PowerPC 401/403";
5869 bus_model
= "Unknown or invalid";
5872 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64
"\n"
5873 " MMU model : %s\n",
5874 def
->name
, def
->pvr
, def
->msr_mask
, mmu_model
);
5875 if (env
->tlb
!= NULL
) {
5876 printf(" %d %s TLB in %d ways\n",
5877 env
->nb_tlb
, env
->id_tlbs
? "splitted" : "merged",
5880 printf(" Exceptions model : %s\n"
5881 " Bus model : %s\n",
5882 excp_model
, bus_model
);
5884 dump_ppc_insns(env
);
5892 int ppc_find_by_name (const unsigned char *name
, ppc_def_t
**def
)
5898 for (i
= 0; strcmp(ppc_defs
[i
].name
, "default") != 0; i
++) {
5899 if (strcasecmp(name
, ppc_defs
[i
].name
) == 0) {
5900 *def
= &ppc_defs
[i
];
5909 int ppc_find_by_pvr (uint32_t pvr
, ppc_def_t
**def
)
5915 for (i
= 0; ppc_defs
[i
].name
!= NULL
; i
++) {
5916 if ((pvr
& ppc_defs
[i
].pvr_mask
) ==
5917 (ppc_defs
[i
].pvr
& ppc_defs
[i
].pvr_mask
)) {
5918 *def
= &ppc_defs
[i
];
5927 void ppc_cpu_list (FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...))
5931 for (i
= 0; ; i
++) {
5932 (*cpu_fprintf
)(f
, "PowerPC %-16s PVR %08x\n",
5933 ppc_defs
[i
].name
, ppc_defs
[i
].pvr
);
5934 if (strcmp(ppc_defs
[i
].name
, "default") == 0)