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PPC: BookE: Make ivpr selectable by CPU type
[mirror_qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
26 #include "dis-asm.h"
27 #include "gdbstub.h"
28 #include <kvm.h>
29 #include "kvm_ppc.h"
30
31 //#define PPC_DUMP_CPU
32 //#define PPC_DEBUG_SPR
33 //#define PPC_DUMP_SPR_ACCESSES
34 #if defined(CONFIG_USER_ONLY)
35 #define TODO_USER_ONLY 1
36 #endif
37
38 /* For user-mode emulation, we don't emulate any IRQ controller */
39 #if defined(CONFIG_USER_ONLY)
40 #define PPC_IRQ_INIT_FN(name) \
41 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
42 { \
43 }
44 #else
45 #define PPC_IRQ_INIT_FN(name) \
46 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
47 #endif
48
49 PPC_IRQ_INIT_FN(40x);
50 PPC_IRQ_INIT_FN(6xx);
51 PPC_IRQ_INIT_FN(970);
52 PPC_IRQ_INIT_FN(POWER7);
53 PPC_IRQ_INIT_FN(e500);
54
55 /* Generic callbacks:
56 * do nothing but store/retrieve spr value
57 */
58 static void spr_read_generic (void *opaque, int gprn, int sprn)
59 {
60 gen_load_spr(cpu_gpr[gprn], sprn);
61 #ifdef PPC_DUMP_SPR_ACCESSES
62 {
63 TCGv_i32 t0 = tcg_const_i32(sprn);
64 gen_helper_load_dump_spr(t0);
65 tcg_temp_free_i32(t0);
66 }
67 #endif
68 }
69
70 static void spr_write_generic (void *opaque, int sprn, int gprn)
71 {
72 gen_store_spr(sprn, cpu_gpr[gprn]);
73 #ifdef PPC_DUMP_SPR_ACCESSES
74 {
75 TCGv_i32 t0 = tcg_const_i32(sprn);
76 gen_helper_store_dump_spr(t0);
77 tcg_temp_free_i32(t0);
78 }
79 #endif
80 }
81
82 #if !defined(CONFIG_USER_ONLY)
83 static void spr_write_clear (void *opaque, int sprn, int gprn)
84 {
85 TCGv t0 = tcg_temp_new();
86 TCGv t1 = tcg_temp_new();
87 gen_load_spr(t0, sprn);
88 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
89 tcg_gen_and_tl(t0, t0, t1);
90 gen_store_spr(sprn, t0);
91 tcg_temp_free(t0);
92 tcg_temp_free(t1);
93 }
94 #endif
95
96 /* SPR common to all PowerPC */
97 /* XER */
98 static void spr_read_xer (void *opaque, int gprn, int sprn)
99 {
100 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
101 }
102
103 static void spr_write_xer (void *opaque, int sprn, int gprn)
104 {
105 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
106 }
107
108 /* LR */
109 static void spr_read_lr (void *opaque, int gprn, int sprn)
110 {
111 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
112 }
113
114 static void spr_write_lr (void *opaque, int sprn, int gprn)
115 {
116 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
117 }
118
119 /* CFAR */
120 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
121 static void spr_read_cfar (void *opaque, int gprn, int sprn)
122 {
123 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
124 }
125
126 static void spr_write_cfar (void *opaque, int sprn, int gprn)
127 {
128 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
129 }
130 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
131
132 /* CTR */
133 static void spr_read_ctr (void *opaque, int gprn, int sprn)
134 {
135 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
136 }
137
138 static void spr_write_ctr (void *opaque, int sprn, int gprn)
139 {
140 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
141 }
142
143 /* User read access to SPR */
144 /* USPRx */
145 /* UMMCRx */
146 /* UPMCx */
147 /* USIA */
148 /* UDECR */
149 static void spr_read_ureg (void *opaque, int gprn, int sprn)
150 {
151 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
152 }
153
154 /* SPR common to all non-embedded PowerPC */
155 /* DECR */
156 #if !defined(CONFIG_USER_ONLY)
157 static void spr_read_decr (void *opaque, int gprn, int sprn)
158 {
159 if (use_icount) {
160 gen_io_start();
161 }
162 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
163 if (use_icount) {
164 gen_io_end();
165 gen_stop_exception(opaque);
166 }
167 }
168
169 static void spr_write_decr (void *opaque, int sprn, int gprn)
170 {
171 if (use_icount) {
172 gen_io_start();
173 }
174 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
175 if (use_icount) {
176 gen_io_end();
177 gen_stop_exception(opaque);
178 }
179 }
180 #endif
181
182 /* SPR common to all non-embedded PowerPC, except 601 */
183 /* Time base */
184 static void spr_read_tbl (void *opaque, int gprn, int sprn)
185 {
186 if (use_icount) {
187 gen_io_start();
188 }
189 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
190 if (use_icount) {
191 gen_io_end();
192 gen_stop_exception(opaque);
193 }
194 }
195
196 static void spr_read_tbu (void *opaque, int gprn, int sprn)
197 {
198 if (use_icount) {
199 gen_io_start();
200 }
201 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
202 if (use_icount) {
203 gen_io_end();
204 gen_stop_exception(opaque);
205 }
206 }
207
208 __attribute__ (( unused ))
209 static void spr_read_atbl (void *opaque, int gprn, int sprn)
210 {
211 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
212 }
213
214 __attribute__ (( unused ))
215 static void spr_read_atbu (void *opaque, int gprn, int sprn)
216 {
217 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
218 }
219
220 #if !defined(CONFIG_USER_ONLY)
221 static void spr_write_tbl (void *opaque, int sprn, int gprn)
222 {
223 if (use_icount) {
224 gen_io_start();
225 }
226 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
227 if (use_icount) {
228 gen_io_end();
229 gen_stop_exception(opaque);
230 }
231 }
232
233 static void spr_write_tbu (void *opaque, int sprn, int gprn)
234 {
235 if (use_icount) {
236 gen_io_start();
237 }
238 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
239 if (use_icount) {
240 gen_io_end();
241 gen_stop_exception(opaque);
242 }
243 }
244
245 __attribute__ (( unused ))
246 static void spr_write_atbl (void *opaque, int sprn, int gprn)
247 {
248 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
249 }
250
251 __attribute__ (( unused ))
252 static void spr_write_atbu (void *opaque, int sprn, int gprn)
253 {
254 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
255 }
256
257 #if defined(TARGET_PPC64)
258 __attribute__ (( unused ))
259 static void spr_read_purr (void *opaque, int gprn, int sprn)
260 {
261 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
262 }
263 #endif
264 #endif
265
266 #if !defined(CONFIG_USER_ONLY)
267 /* IBAT0U...IBAT0U */
268 /* IBAT0L...IBAT7L */
269 static void spr_read_ibat (void *opaque, int gprn, int sprn)
270 {
271 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
272 }
273
274 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
275 {
276 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
277 }
278
279 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
280 {
281 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
282 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
283 tcg_temp_free_i32(t0);
284 }
285
286 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
287 {
288 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
289 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
290 tcg_temp_free_i32(t0);
291 }
292
293 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
294 {
295 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
296 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
297 tcg_temp_free_i32(t0);
298 }
299
300 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
301 {
302 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
303 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
304 tcg_temp_free_i32(t0);
305 }
306
307 /* DBAT0U...DBAT7U */
308 /* DBAT0L...DBAT7L */
309 static void spr_read_dbat (void *opaque, int gprn, int sprn)
310 {
311 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
312 }
313
314 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
315 {
316 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
317 }
318
319 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
320 {
321 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
322 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
323 tcg_temp_free_i32(t0);
324 }
325
326 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
327 {
328 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
329 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
330 tcg_temp_free_i32(t0);
331 }
332
333 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
334 {
335 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
336 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
337 tcg_temp_free_i32(t0);
338 }
339
340 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
341 {
342 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
343 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
344 tcg_temp_free_i32(t0);
345 }
346
347 /* SDR1 */
348 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
349 {
350 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
351 }
352
353 /* 64 bits PowerPC specific SPRs */
354 /* ASR */
355 #if defined(TARGET_PPC64)
356 static void spr_read_hior (void *opaque, int gprn, int sprn)
357 {
358 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
359 }
360
361 static void spr_write_hior (void *opaque, int sprn, int gprn)
362 {
363 TCGv t0 = tcg_temp_new();
364 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
365 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
366 tcg_temp_free(t0);
367 }
368
369 static void spr_read_asr (void *opaque, int gprn, int sprn)
370 {
371 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, asr));
372 }
373
374 static void spr_write_asr (void *opaque, int sprn, int gprn)
375 {
376 gen_helper_store_asr(cpu_env, cpu_gpr[gprn]);
377 }
378 #endif
379 #endif
380
381 /* PowerPC 601 specific registers */
382 /* RTC */
383 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
384 {
385 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
386 }
387
388 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
389 {
390 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
391 }
392
393 #if !defined(CONFIG_USER_ONLY)
394 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
395 {
396 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
397 }
398
399 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
400 {
401 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
402 }
403
404 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
405 {
406 DisasContext *ctx = opaque;
407
408 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
409 /* Must stop the translation as endianness may have changed */
410 gen_stop_exception(ctx);
411 }
412 #endif
413
414 /* Unified bats */
415 #if !defined(CONFIG_USER_ONLY)
416 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
417 {
418 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
419 }
420
421 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
422 {
423 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
424 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
425 tcg_temp_free_i32(t0);
426 }
427
428 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
429 {
430 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
431 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
432 tcg_temp_free_i32(t0);
433 }
434 #endif
435
436 /* PowerPC 40x specific registers */
437 #if !defined(CONFIG_USER_ONLY)
438 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
439 {
440 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
441 }
442
443 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
444 {
445 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
446 }
447
448 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
449 {
450 DisasContext *ctx = opaque;
451
452 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
453 /* We must stop translation as we may have rebooted */
454 gen_stop_exception(ctx);
455 }
456
457 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
458 {
459 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
460 }
461
462 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
463 {
464 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
465 }
466
467 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
468 {
469 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
470 }
471 #endif
472
473 /* PowerPC 403 specific registers */
474 /* PBL1 / PBU1 / PBL2 / PBU2 */
475 #if !defined(CONFIG_USER_ONLY)
476 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
477 {
478 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
479 }
480
481 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
482 {
483 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
484 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
485 tcg_temp_free_i32(t0);
486 }
487
488 static void spr_write_pir (void *opaque, int sprn, int gprn)
489 {
490 TCGv t0 = tcg_temp_new();
491 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
492 gen_store_spr(SPR_PIR, t0);
493 tcg_temp_free(t0);
494 }
495 #endif
496
497 /* SPE specific registers */
498 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
499 {
500 TCGv_i32 t0 = tcg_temp_new_i32();
501 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
502 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
503 tcg_temp_free_i32(t0);
504 }
505
506 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
507 {
508 TCGv_i32 t0 = tcg_temp_new_i32();
509 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
510 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
511 tcg_temp_free_i32(t0);
512 }
513
514 #if !defined(CONFIG_USER_ONLY)
515 /* Callback used to write the exception vector base */
516 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
517 {
518 TCGv t0 = tcg_temp_new();
519 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
520 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
521 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
522 gen_store_spr(sprn, t0);
523 tcg_temp_free(t0);
524 }
525
526 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
527 {
528 DisasContext *ctx = opaque;
529 int sprn_offs;
530
531 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
532 sprn_offs = sprn - SPR_BOOKE_IVOR0;
533 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
534 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
535 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
536 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
537 } else {
538 printf("Trying to write an unknown exception vector %d %03x\n",
539 sprn, sprn);
540 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
541 return;
542 }
543
544 TCGv t0 = tcg_temp_new();
545 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
546 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
547 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
548 gen_store_spr(sprn, t0);
549 tcg_temp_free(t0);
550 }
551 #endif
552
553 static inline void vscr_init (CPUPPCState *env, uint32_t val)
554 {
555 env->vscr = val;
556 /* Altivec always uses round-to-nearest */
557 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
558 set_flush_to_zero(vscr_nj, &env->vec_status);
559 }
560
561 #if defined(CONFIG_USER_ONLY)
562 #define spr_register(env, num, name, uea_read, uea_write, \
563 oea_read, oea_write, initial_value) \
564 do { \
565 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
566 } while (0)
567 static inline void _spr_register (CPUPPCState *env, int num,
568 const char *name,
569 void (*uea_read)(void *opaque, int gprn, int sprn),
570 void (*uea_write)(void *opaque, int sprn, int gprn),
571 target_ulong initial_value)
572 #else
573 static inline void spr_register (CPUPPCState *env, int num,
574 const char *name,
575 void (*uea_read)(void *opaque, int gprn, int sprn),
576 void (*uea_write)(void *opaque, int sprn, int gprn),
577 void (*oea_read)(void *opaque, int gprn, int sprn),
578 void (*oea_write)(void *opaque, int sprn, int gprn),
579 target_ulong initial_value)
580 #endif
581 {
582 ppc_spr_t *spr;
583
584 spr = &env->spr_cb[num];
585 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
586 #if !defined(CONFIG_USER_ONLY)
587 spr->oea_read != NULL || spr->oea_write != NULL ||
588 #endif
589 spr->uea_read != NULL || spr->uea_write != NULL) {
590 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
591 exit(1);
592 }
593 #if defined(PPC_DEBUG_SPR)
594 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
595 name, initial_value);
596 #endif
597 spr->name = name;
598 spr->uea_read = uea_read;
599 spr->uea_write = uea_write;
600 #if !defined(CONFIG_USER_ONLY)
601 spr->oea_read = oea_read;
602 spr->oea_write = oea_write;
603 #endif
604 env->spr[num] = initial_value;
605 }
606
607 /* Generic PowerPC SPRs */
608 static void gen_spr_generic (CPUPPCState *env)
609 {
610 /* Integer processing */
611 spr_register(env, SPR_XER, "XER",
612 &spr_read_xer, &spr_write_xer,
613 &spr_read_xer, &spr_write_xer,
614 0x00000000);
615 /* Branch contol */
616 spr_register(env, SPR_LR, "LR",
617 &spr_read_lr, &spr_write_lr,
618 &spr_read_lr, &spr_write_lr,
619 0x00000000);
620 spr_register(env, SPR_CTR, "CTR",
621 &spr_read_ctr, &spr_write_ctr,
622 &spr_read_ctr, &spr_write_ctr,
623 0x00000000);
624 /* Interrupt processing */
625 spr_register(env, SPR_SRR0, "SRR0",
626 SPR_NOACCESS, SPR_NOACCESS,
627 &spr_read_generic, &spr_write_generic,
628 0x00000000);
629 spr_register(env, SPR_SRR1, "SRR1",
630 SPR_NOACCESS, SPR_NOACCESS,
631 &spr_read_generic, &spr_write_generic,
632 0x00000000);
633 /* Processor control */
634 spr_register(env, SPR_SPRG0, "SPRG0",
635 SPR_NOACCESS, SPR_NOACCESS,
636 &spr_read_generic, &spr_write_generic,
637 0x00000000);
638 spr_register(env, SPR_SPRG1, "SPRG1",
639 SPR_NOACCESS, SPR_NOACCESS,
640 &spr_read_generic, &spr_write_generic,
641 0x00000000);
642 spr_register(env, SPR_SPRG2, "SPRG2",
643 SPR_NOACCESS, SPR_NOACCESS,
644 &spr_read_generic, &spr_write_generic,
645 0x00000000);
646 spr_register(env, SPR_SPRG3, "SPRG3",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_generic, &spr_write_generic,
649 0x00000000);
650 }
651
652 /* SPR common to all non-embedded PowerPC, including 601 */
653 static void gen_spr_ne_601 (CPUPPCState *env)
654 {
655 /* Exception processing */
656 spr_register(env, SPR_DSISR, "DSISR",
657 SPR_NOACCESS, SPR_NOACCESS,
658 &spr_read_generic, &spr_write_generic,
659 0x00000000);
660 spr_register(env, SPR_DAR, "DAR",
661 SPR_NOACCESS, SPR_NOACCESS,
662 &spr_read_generic, &spr_write_generic,
663 0x00000000);
664 /* Timer */
665 spr_register(env, SPR_DECR, "DECR",
666 SPR_NOACCESS, SPR_NOACCESS,
667 &spr_read_decr, &spr_write_decr,
668 0x00000000);
669 /* Memory management */
670 spr_register(env, SPR_SDR1, "SDR1",
671 SPR_NOACCESS, SPR_NOACCESS,
672 &spr_read_generic, &spr_write_sdr1,
673 0x00000000);
674 }
675
676 /* BATs 0-3 */
677 static void gen_low_BATs (CPUPPCState *env)
678 {
679 #if !defined(CONFIG_USER_ONLY)
680 spr_register(env, SPR_IBAT0U, "IBAT0U",
681 SPR_NOACCESS, SPR_NOACCESS,
682 &spr_read_ibat, &spr_write_ibatu,
683 0x00000000);
684 spr_register(env, SPR_IBAT0L, "IBAT0L",
685 SPR_NOACCESS, SPR_NOACCESS,
686 &spr_read_ibat, &spr_write_ibatl,
687 0x00000000);
688 spr_register(env, SPR_IBAT1U, "IBAT1U",
689 SPR_NOACCESS, SPR_NOACCESS,
690 &spr_read_ibat, &spr_write_ibatu,
691 0x00000000);
692 spr_register(env, SPR_IBAT1L, "IBAT1L",
693 SPR_NOACCESS, SPR_NOACCESS,
694 &spr_read_ibat, &spr_write_ibatl,
695 0x00000000);
696 spr_register(env, SPR_IBAT2U, "IBAT2U",
697 SPR_NOACCESS, SPR_NOACCESS,
698 &spr_read_ibat, &spr_write_ibatu,
699 0x00000000);
700 spr_register(env, SPR_IBAT2L, "IBAT2L",
701 SPR_NOACCESS, SPR_NOACCESS,
702 &spr_read_ibat, &spr_write_ibatl,
703 0x00000000);
704 spr_register(env, SPR_IBAT3U, "IBAT3U",
705 SPR_NOACCESS, SPR_NOACCESS,
706 &spr_read_ibat, &spr_write_ibatu,
707 0x00000000);
708 spr_register(env, SPR_IBAT3L, "IBAT3L",
709 SPR_NOACCESS, SPR_NOACCESS,
710 &spr_read_ibat, &spr_write_ibatl,
711 0x00000000);
712 spr_register(env, SPR_DBAT0U, "DBAT0U",
713 SPR_NOACCESS, SPR_NOACCESS,
714 &spr_read_dbat, &spr_write_dbatu,
715 0x00000000);
716 spr_register(env, SPR_DBAT0L, "DBAT0L",
717 SPR_NOACCESS, SPR_NOACCESS,
718 &spr_read_dbat, &spr_write_dbatl,
719 0x00000000);
720 spr_register(env, SPR_DBAT1U, "DBAT1U",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_dbat, &spr_write_dbatu,
723 0x00000000);
724 spr_register(env, SPR_DBAT1L, "DBAT1L",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_dbat, &spr_write_dbatl,
727 0x00000000);
728 spr_register(env, SPR_DBAT2U, "DBAT2U",
729 SPR_NOACCESS, SPR_NOACCESS,
730 &spr_read_dbat, &spr_write_dbatu,
731 0x00000000);
732 spr_register(env, SPR_DBAT2L, "DBAT2L",
733 SPR_NOACCESS, SPR_NOACCESS,
734 &spr_read_dbat, &spr_write_dbatl,
735 0x00000000);
736 spr_register(env, SPR_DBAT3U, "DBAT3U",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_dbat, &spr_write_dbatu,
739 0x00000000);
740 spr_register(env, SPR_DBAT3L, "DBAT3L",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_dbat, &spr_write_dbatl,
743 0x00000000);
744 env->nb_BATs += 4;
745 #endif
746 }
747
748 /* BATs 4-7 */
749 static void gen_high_BATs (CPUPPCState *env)
750 {
751 #if !defined(CONFIG_USER_ONLY)
752 spr_register(env, SPR_IBAT4U, "IBAT4U",
753 SPR_NOACCESS, SPR_NOACCESS,
754 &spr_read_ibat_h, &spr_write_ibatu_h,
755 0x00000000);
756 spr_register(env, SPR_IBAT4L, "IBAT4L",
757 SPR_NOACCESS, SPR_NOACCESS,
758 &spr_read_ibat_h, &spr_write_ibatl_h,
759 0x00000000);
760 spr_register(env, SPR_IBAT5U, "IBAT5U",
761 SPR_NOACCESS, SPR_NOACCESS,
762 &spr_read_ibat_h, &spr_write_ibatu_h,
763 0x00000000);
764 spr_register(env, SPR_IBAT5L, "IBAT5L",
765 SPR_NOACCESS, SPR_NOACCESS,
766 &spr_read_ibat_h, &spr_write_ibatl_h,
767 0x00000000);
768 spr_register(env, SPR_IBAT6U, "IBAT6U",
769 SPR_NOACCESS, SPR_NOACCESS,
770 &spr_read_ibat_h, &spr_write_ibatu_h,
771 0x00000000);
772 spr_register(env, SPR_IBAT6L, "IBAT6L",
773 SPR_NOACCESS, SPR_NOACCESS,
774 &spr_read_ibat_h, &spr_write_ibatl_h,
775 0x00000000);
776 spr_register(env, SPR_IBAT7U, "IBAT7U",
777 SPR_NOACCESS, SPR_NOACCESS,
778 &spr_read_ibat_h, &spr_write_ibatu_h,
779 0x00000000);
780 spr_register(env, SPR_IBAT7L, "IBAT7L",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_ibat_h, &spr_write_ibatl_h,
783 0x00000000);
784 spr_register(env, SPR_DBAT4U, "DBAT4U",
785 SPR_NOACCESS, SPR_NOACCESS,
786 &spr_read_dbat_h, &spr_write_dbatu_h,
787 0x00000000);
788 spr_register(env, SPR_DBAT4L, "DBAT4L",
789 SPR_NOACCESS, SPR_NOACCESS,
790 &spr_read_dbat_h, &spr_write_dbatl_h,
791 0x00000000);
792 spr_register(env, SPR_DBAT5U, "DBAT5U",
793 SPR_NOACCESS, SPR_NOACCESS,
794 &spr_read_dbat_h, &spr_write_dbatu_h,
795 0x00000000);
796 spr_register(env, SPR_DBAT5L, "DBAT5L",
797 SPR_NOACCESS, SPR_NOACCESS,
798 &spr_read_dbat_h, &spr_write_dbatl_h,
799 0x00000000);
800 spr_register(env, SPR_DBAT6U, "DBAT6U",
801 SPR_NOACCESS, SPR_NOACCESS,
802 &spr_read_dbat_h, &spr_write_dbatu_h,
803 0x00000000);
804 spr_register(env, SPR_DBAT6L, "DBAT6L",
805 SPR_NOACCESS, SPR_NOACCESS,
806 &spr_read_dbat_h, &spr_write_dbatl_h,
807 0x00000000);
808 spr_register(env, SPR_DBAT7U, "DBAT7U",
809 SPR_NOACCESS, SPR_NOACCESS,
810 &spr_read_dbat_h, &spr_write_dbatu_h,
811 0x00000000);
812 spr_register(env, SPR_DBAT7L, "DBAT7L",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_dbat_h, &spr_write_dbatl_h,
815 0x00000000);
816 env->nb_BATs += 4;
817 #endif
818 }
819
820 /* Generic PowerPC time base */
821 static void gen_tbl (CPUPPCState *env)
822 {
823 spr_register(env, SPR_VTBL, "TBL",
824 &spr_read_tbl, SPR_NOACCESS,
825 &spr_read_tbl, SPR_NOACCESS,
826 0x00000000);
827 spr_register(env, SPR_TBL, "TBL",
828 &spr_read_tbl, SPR_NOACCESS,
829 &spr_read_tbl, &spr_write_tbl,
830 0x00000000);
831 spr_register(env, SPR_VTBU, "TBU",
832 &spr_read_tbu, SPR_NOACCESS,
833 &spr_read_tbu, SPR_NOACCESS,
834 0x00000000);
835 spr_register(env, SPR_TBU, "TBU",
836 &spr_read_tbu, SPR_NOACCESS,
837 &spr_read_tbu, &spr_write_tbu,
838 0x00000000);
839 }
840
841 /* Softare table search registers */
842 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
843 {
844 #if !defined(CONFIG_USER_ONLY)
845 env->nb_tlb = nb_tlbs;
846 env->nb_ways = nb_ways;
847 env->id_tlbs = 1;
848 env->tlb_type = TLB_6XX;
849 spr_register(env, SPR_DMISS, "DMISS",
850 SPR_NOACCESS, SPR_NOACCESS,
851 &spr_read_generic, SPR_NOACCESS,
852 0x00000000);
853 spr_register(env, SPR_DCMP, "DCMP",
854 SPR_NOACCESS, SPR_NOACCESS,
855 &spr_read_generic, SPR_NOACCESS,
856 0x00000000);
857 spr_register(env, SPR_HASH1, "HASH1",
858 SPR_NOACCESS, SPR_NOACCESS,
859 &spr_read_generic, SPR_NOACCESS,
860 0x00000000);
861 spr_register(env, SPR_HASH2, "HASH2",
862 SPR_NOACCESS, SPR_NOACCESS,
863 &spr_read_generic, SPR_NOACCESS,
864 0x00000000);
865 spr_register(env, SPR_IMISS, "IMISS",
866 SPR_NOACCESS, SPR_NOACCESS,
867 &spr_read_generic, SPR_NOACCESS,
868 0x00000000);
869 spr_register(env, SPR_ICMP, "ICMP",
870 SPR_NOACCESS, SPR_NOACCESS,
871 &spr_read_generic, SPR_NOACCESS,
872 0x00000000);
873 spr_register(env, SPR_RPA, "RPA",
874 SPR_NOACCESS, SPR_NOACCESS,
875 &spr_read_generic, &spr_write_generic,
876 0x00000000);
877 #endif
878 }
879
880 /* SPR common to MPC755 and G2 */
881 static void gen_spr_G2_755 (CPUPPCState *env)
882 {
883 /* SGPRs */
884 spr_register(env, SPR_SPRG4, "SPRG4",
885 SPR_NOACCESS, SPR_NOACCESS,
886 &spr_read_generic, &spr_write_generic,
887 0x00000000);
888 spr_register(env, SPR_SPRG5, "SPRG5",
889 SPR_NOACCESS, SPR_NOACCESS,
890 &spr_read_generic, &spr_write_generic,
891 0x00000000);
892 spr_register(env, SPR_SPRG6, "SPRG6",
893 SPR_NOACCESS, SPR_NOACCESS,
894 &spr_read_generic, &spr_write_generic,
895 0x00000000);
896 spr_register(env, SPR_SPRG7, "SPRG7",
897 SPR_NOACCESS, SPR_NOACCESS,
898 &spr_read_generic, &spr_write_generic,
899 0x00000000);
900 }
901
902 /* SPR common to all 7xx PowerPC implementations */
903 static void gen_spr_7xx (CPUPPCState *env)
904 {
905 /* Breakpoints */
906 /* XXX : not implemented */
907 spr_register(env, SPR_DABR, "DABR",
908 SPR_NOACCESS, SPR_NOACCESS,
909 &spr_read_generic, &spr_write_generic,
910 0x00000000);
911 /* XXX : not implemented */
912 spr_register(env, SPR_IABR, "IABR",
913 SPR_NOACCESS, SPR_NOACCESS,
914 &spr_read_generic, &spr_write_generic,
915 0x00000000);
916 /* Cache management */
917 /* XXX : not implemented */
918 spr_register(env, SPR_ICTC, "ICTC",
919 SPR_NOACCESS, SPR_NOACCESS,
920 &spr_read_generic, &spr_write_generic,
921 0x00000000);
922 /* Performance monitors */
923 /* XXX : not implemented */
924 spr_register(env, SPR_MMCR0, "MMCR0",
925 SPR_NOACCESS, SPR_NOACCESS,
926 &spr_read_generic, &spr_write_generic,
927 0x00000000);
928 /* XXX : not implemented */
929 spr_register(env, SPR_MMCR1, "MMCR1",
930 SPR_NOACCESS, SPR_NOACCESS,
931 &spr_read_generic, &spr_write_generic,
932 0x00000000);
933 /* XXX : not implemented */
934 spr_register(env, SPR_PMC1, "PMC1",
935 SPR_NOACCESS, SPR_NOACCESS,
936 &spr_read_generic, &spr_write_generic,
937 0x00000000);
938 /* XXX : not implemented */
939 spr_register(env, SPR_PMC2, "PMC2",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943 /* XXX : not implemented */
944 spr_register(env, SPR_PMC3, "PMC3",
945 SPR_NOACCESS, SPR_NOACCESS,
946 &spr_read_generic, &spr_write_generic,
947 0x00000000);
948 /* XXX : not implemented */
949 spr_register(env, SPR_PMC4, "PMC4",
950 SPR_NOACCESS, SPR_NOACCESS,
951 &spr_read_generic, &spr_write_generic,
952 0x00000000);
953 /* XXX : not implemented */
954 spr_register(env, SPR_SIAR, "SIAR",
955 SPR_NOACCESS, SPR_NOACCESS,
956 &spr_read_generic, SPR_NOACCESS,
957 0x00000000);
958 /* XXX : not implemented */
959 spr_register(env, SPR_UMMCR0, "UMMCR0",
960 &spr_read_ureg, SPR_NOACCESS,
961 &spr_read_ureg, SPR_NOACCESS,
962 0x00000000);
963 /* XXX : not implemented */
964 spr_register(env, SPR_UMMCR1, "UMMCR1",
965 &spr_read_ureg, SPR_NOACCESS,
966 &spr_read_ureg, SPR_NOACCESS,
967 0x00000000);
968 /* XXX : not implemented */
969 spr_register(env, SPR_UPMC1, "UPMC1",
970 &spr_read_ureg, SPR_NOACCESS,
971 &spr_read_ureg, SPR_NOACCESS,
972 0x00000000);
973 /* XXX : not implemented */
974 spr_register(env, SPR_UPMC2, "UPMC2",
975 &spr_read_ureg, SPR_NOACCESS,
976 &spr_read_ureg, SPR_NOACCESS,
977 0x00000000);
978 /* XXX : not implemented */
979 spr_register(env, SPR_UPMC3, "UPMC3",
980 &spr_read_ureg, SPR_NOACCESS,
981 &spr_read_ureg, SPR_NOACCESS,
982 0x00000000);
983 /* XXX : not implemented */
984 spr_register(env, SPR_UPMC4, "UPMC4",
985 &spr_read_ureg, SPR_NOACCESS,
986 &spr_read_ureg, SPR_NOACCESS,
987 0x00000000);
988 /* XXX : not implemented */
989 spr_register(env, SPR_USIAR, "USIAR",
990 &spr_read_ureg, SPR_NOACCESS,
991 &spr_read_ureg, SPR_NOACCESS,
992 0x00000000);
993 /* External access control */
994 /* XXX : not implemented */
995 spr_register(env, SPR_EAR, "EAR",
996 SPR_NOACCESS, SPR_NOACCESS,
997 &spr_read_generic, &spr_write_generic,
998 0x00000000);
999 }
1000
1001 static void gen_spr_thrm (CPUPPCState *env)
1002 {
1003 /* Thermal management */
1004 /* XXX : not implemented */
1005 spr_register(env, SPR_THRM1, "THRM1",
1006 SPR_NOACCESS, SPR_NOACCESS,
1007 &spr_read_generic, &spr_write_generic,
1008 0x00000000);
1009 /* XXX : not implemented */
1010 spr_register(env, SPR_THRM2, "THRM2",
1011 SPR_NOACCESS, SPR_NOACCESS,
1012 &spr_read_generic, &spr_write_generic,
1013 0x00000000);
1014 /* XXX : not implemented */
1015 spr_register(env, SPR_THRM3, "THRM3",
1016 SPR_NOACCESS, SPR_NOACCESS,
1017 &spr_read_generic, &spr_write_generic,
1018 0x00000000);
1019 }
1020
1021 /* SPR specific to PowerPC 604 implementation */
1022 static void gen_spr_604 (CPUPPCState *env)
1023 {
1024 /* Processor identification */
1025 spr_register(env, SPR_PIR, "PIR",
1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, &spr_write_pir,
1028 0x00000000);
1029 /* Breakpoints */
1030 /* XXX : not implemented */
1031 spr_register(env, SPR_IABR, "IABR",
1032 SPR_NOACCESS, SPR_NOACCESS,
1033 &spr_read_generic, &spr_write_generic,
1034 0x00000000);
1035 /* XXX : not implemented */
1036 spr_register(env, SPR_DABR, "DABR",
1037 SPR_NOACCESS, SPR_NOACCESS,
1038 &spr_read_generic, &spr_write_generic,
1039 0x00000000);
1040 /* Performance counters */
1041 /* XXX : not implemented */
1042 spr_register(env, SPR_MMCR0, "MMCR0",
1043 SPR_NOACCESS, SPR_NOACCESS,
1044 &spr_read_generic, &spr_write_generic,
1045 0x00000000);
1046 /* XXX : not implemented */
1047 spr_register(env, SPR_PMC1, "PMC1",
1048 SPR_NOACCESS, SPR_NOACCESS,
1049 &spr_read_generic, &spr_write_generic,
1050 0x00000000);
1051 /* XXX : not implemented */
1052 spr_register(env, SPR_PMC2, "PMC2",
1053 SPR_NOACCESS, SPR_NOACCESS,
1054 &spr_read_generic, &spr_write_generic,
1055 0x00000000);
1056 /* XXX : not implemented */
1057 spr_register(env, SPR_SIAR, "SIAR",
1058 SPR_NOACCESS, SPR_NOACCESS,
1059 &spr_read_generic, SPR_NOACCESS,
1060 0x00000000);
1061 /* XXX : not implemented */
1062 spr_register(env, SPR_SDA, "SDA",
1063 SPR_NOACCESS, SPR_NOACCESS,
1064 &spr_read_generic, SPR_NOACCESS,
1065 0x00000000);
1066 /* External access control */
1067 /* XXX : not implemented */
1068 spr_register(env, SPR_EAR, "EAR",
1069 SPR_NOACCESS, SPR_NOACCESS,
1070 &spr_read_generic, &spr_write_generic,
1071 0x00000000);
1072 }
1073
1074 /* SPR specific to PowerPC 603 implementation */
1075 static void gen_spr_603 (CPUPPCState *env)
1076 {
1077 /* External access control */
1078 /* XXX : not implemented */
1079 spr_register(env, SPR_EAR, "EAR",
1080 SPR_NOACCESS, SPR_NOACCESS,
1081 &spr_read_generic, &spr_write_generic,
1082 0x00000000);
1083 }
1084
1085 /* SPR specific to PowerPC G2 implementation */
1086 static void gen_spr_G2 (CPUPPCState *env)
1087 {
1088 /* Memory base address */
1089 /* MBAR */
1090 /* XXX : not implemented */
1091 spr_register(env, SPR_MBAR, "MBAR",
1092 SPR_NOACCESS, SPR_NOACCESS,
1093 &spr_read_generic, &spr_write_generic,
1094 0x00000000);
1095 /* Exception processing */
1096 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1097 SPR_NOACCESS, SPR_NOACCESS,
1098 &spr_read_generic, &spr_write_generic,
1099 0x00000000);
1100 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1101 SPR_NOACCESS, SPR_NOACCESS,
1102 &spr_read_generic, &spr_write_generic,
1103 0x00000000);
1104 /* Breakpoints */
1105 /* XXX : not implemented */
1106 spr_register(env, SPR_DABR, "DABR",
1107 SPR_NOACCESS, SPR_NOACCESS,
1108 &spr_read_generic, &spr_write_generic,
1109 0x00000000);
1110 /* XXX : not implemented */
1111 spr_register(env, SPR_DABR2, "DABR2",
1112 SPR_NOACCESS, SPR_NOACCESS,
1113 &spr_read_generic, &spr_write_generic,
1114 0x00000000);
1115 /* XXX : not implemented */
1116 spr_register(env, SPR_IABR, "IABR",
1117 SPR_NOACCESS, SPR_NOACCESS,
1118 &spr_read_generic, &spr_write_generic,
1119 0x00000000);
1120 /* XXX : not implemented */
1121 spr_register(env, SPR_IABR2, "IABR2",
1122 SPR_NOACCESS, SPR_NOACCESS,
1123 &spr_read_generic, &spr_write_generic,
1124 0x00000000);
1125 /* XXX : not implemented */
1126 spr_register(env, SPR_IBCR, "IBCR",
1127 SPR_NOACCESS, SPR_NOACCESS,
1128 &spr_read_generic, &spr_write_generic,
1129 0x00000000);
1130 /* XXX : not implemented */
1131 spr_register(env, SPR_DBCR, "DBCR",
1132 SPR_NOACCESS, SPR_NOACCESS,
1133 &spr_read_generic, &spr_write_generic,
1134 0x00000000);
1135 }
1136
1137 /* SPR specific to PowerPC 602 implementation */
1138 static void gen_spr_602 (CPUPPCState *env)
1139 {
1140 /* ESA registers */
1141 /* XXX : not implemented */
1142 spr_register(env, SPR_SER, "SER",
1143 SPR_NOACCESS, SPR_NOACCESS,
1144 &spr_read_generic, &spr_write_generic,
1145 0x00000000);
1146 /* XXX : not implemented */
1147 spr_register(env, SPR_SEBR, "SEBR",
1148 SPR_NOACCESS, SPR_NOACCESS,
1149 &spr_read_generic, &spr_write_generic,
1150 0x00000000);
1151 /* XXX : not implemented */
1152 spr_register(env, SPR_ESASRR, "ESASRR",
1153 SPR_NOACCESS, SPR_NOACCESS,
1154 &spr_read_generic, &spr_write_generic,
1155 0x00000000);
1156 /* Floating point status */
1157 /* XXX : not implemented */
1158 spr_register(env, SPR_SP, "SP",
1159 SPR_NOACCESS, SPR_NOACCESS,
1160 &spr_read_generic, &spr_write_generic,
1161 0x00000000);
1162 /* XXX : not implemented */
1163 spr_register(env, SPR_LT, "LT",
1164 SPR_NOACCESS, SPR_NOACCESS,
1165 &spr_read_generic, &spr_write_generic,
1166 0x00000000);
1167 /* Watchdog timer */
1168 /* XXX : not implemented */
1169 spr_register(env, SPR_TCR, "TCR",
1170 SPR_NOACCESS, SPR_NOACCESS,
1171 &spr_read_generic, &spr_write_generic,
1172 0x00000000);
1173 /* Interrupt base */
1174 spr_register(env, SPR_IBR, "IBR",
1175 SPR_NOACCESS, SPR_NOACCESS,
1176 &spr_read_generic, &spr_write_generic,
1177 0x00000000);
1178 /* XXX : not implemented */
1179 spr_register(env, SPR_IABR, "IABR",
1180 SPR_NOACCESS, SPR_NOACCESS,
1181 &spr_read_generic, &spr_write_generic,
1182 0x00000000);
1183 }
1184
1185 /* SPR specific to PowerPC 601 implementation */
1186 static void gen_spr_601 (CPUPPCState *env)
1187 {
1188 /* Multiplication/division register */
1189 /* MQ */
1190 spr_register(env, SPR_MQ, "MQ",
1191 &spr_read_generic, &spr_write_generic,
1192 &spr_read_generic, &spr_write_generic,
1193 0x00000000);
1194 /* RTC registers */
1195 spr_register(env, SPR_601_RTCU, "RTCU",
1196 SPR_NOACCESS, SPR_NOACCESS,
1197 SPR_NOACCESS, &spr_write_601_rtcu,
1198 0x00000000);
1199 spr_register(env, SPR_601_VRTCU, "RTCU",
1200 &spr_read_601_rtcu, SPR_NOACCESS,
1201 &spr_read_601_rtcu, SPR_NOACCESS,
1202 0x00000000);
1203 spr_register(env, SPR_601_RTCL, "RTCL",
1204 SPR_NOACCESS, SPR_NOACCESS,
1205 SPR_NOACCESS, &spr_write_601_rtcl,
1206 0x00000000);
1207 spr_register(env, SPR_601_VRTCL, "RTCL",
1208 &spr_read_601_rtcl, SPR_NOACCESS,
1209 &spr_read_601_rtcl, SPR_NOACCESS,
1210 0x00000000);
1211 /* Timer */
1212 #if 0 /* ? */
1213 spr_register(env, SPR_601_UDECR, "UDECR",
1214 &spr_read_decr, SPR_NOACCESS,
1215 &spr_read_decr, SPR_NOACCESS,
1216 0x00000000);
1217 #endif
1218 /* External access control */
1219 /* XXX : not implemented */
1220 spr_register(env, SPR_EAR, "EAR",
1221 SPR_NOACCESS, SPR_NOACCESS,
1222 &spr_read_generic, &spr_write_generic,
1223 0x00000000);
1224 /* Memory management */
1225 #if !defined(CONFIG_USER_ONLY)
1226 spr_register(env, SPR_IBAT0U, "IBAT0U",
1227 SPR_NOACCESS, SPR_NOACCESS,
1228 &spr_read_601_ubat, &spr_write_601_ubatu,
1229 0x00000000);
1230 spr_register(env, SPR_IBAT0L, "IBAT0L",
1231 SPR_NOACCESS, SPR_NOACCESS,
1232 &spr_read_601_ubat, &spr_write_601_ubatl,
1233 0x00000000);
1234 spr_register(env, SPR_IBAT1U, "IBAT1U",
1235 SPR_NOACCESS, SPR_NOACCESS,
1236 &spr_read_601_ubat, &spr_write_601_ubatu,
1237 0x00000000);
1238 spr_register(env, SPR_IBAT1L, "IBAT1L",
1239 SPR_NOACCESS, SPR_NOACCESS,
1240 &spr_read_601_ubat, &spr_write_601_ubatl,
1241 0x00000000);
1242 spr_register(env, SPR_IBAT2U, "IBAT2U",
1243 SPR_NOACCESS, SPR_NOACCESS,
1244 &spr_read_601_ubat, &spr_write_601_ubatu,
1245 0x00000000);
1246 spr_register(env, SPR_IBAT2L, "IBAT2L",
1247 SPR_NOACCESS, SPR_NOACCESS,
1248 &spr_read_601_ubat, &spr_write_601_ubatl,
1249 0x00000000);
1250 spr_register(env, SPR_IBAT3U, "IBAT3U",
1251 SPR_NOACCESS, SPR_NOACCESS,
1252 &spr_read_601_ubat, &spr_write_601_ubatu,
1253 0x00000000);
1254 spr_register(env, SPR_IBAT3L, "IBAT3L",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_601_ubat, &spr_write_601_ubatl,
1257 0x00000000);
1258 env->nb_BATs = 4;
1259 #endif
1260 }
1261
1262 static void gen_spr_74xx (CPUPPCState *env)
1263 {
1264 /* Processor identification */
1265 spr_register(env, SPR_PIR, "PIR",
1266 SPR_NOACCESS, SPR_NOACCESS,
1267 &spr_read_generic, &spr_write_pir,
1268 0x00000000);
1269 /* XXX : not implemented */
1270 spr_register(env, SPR_MMCR2, "MMCR2",
1271 SPR_NOACCESS, SPR_NOACCESS,
1272 &spr_read_generic, &spr_write_generic,
1273 0x00000000);
1274 /* XXX : not implemented */
1275 spr_register(env, SPR_UMMCR2, "UMMCR2",
1276 &spr_read_ureg, SPR_NOACCESS,
1277 &spr_read_ureg, SPR_NOACCESS,
1278 0x00000000);
1279 /* XXX: not implemented */
1280 spr_register(env, SPR_BAMR, "BAMR",
1281 SPR_NOACCESS, SPR_NOACCESS,
1282 &spr_read_generic, &spr_write_generic,
1283 0x00000000);
1284 /* XXX : not implemented */
1285 spr_register(env, SPR_MSSCR0, "MSSCR0",
1286 SPR_NOACCESS, SPR_NOACCESS,
1287 &spr_read_generic, &spr_write_generic,
1288 0x00000000);
1289 /* Hardware implementation registers */
1290 /* XXX : not implemented */
1291 spr_register(env, SPR_HID0, "HID0",
1292 SPR_NOACCESS, SPR_NOACCESS,
1293 &spr_read_generic, &spr_write_generic,
1294 0x00000000);
1295 /* XXX : not implemented */
1296 spr_register(env, SPR_HID1, "HID1",
1297 SPR_NOACCESS, SPR_NOACCESS,
1298 &spr_read_generic, &spr_write_generic,
1299 0x00000000);
1300 /* Altivec */
1301 spr_register(env, SPR_VRSAVE, "VRSAVE",
1302 &spr_read_generic, &spr_write_generic,
1303 &spr_read_generic, &spr_write_generic,
1304 0x00000000);
1305 /* XXX : not implemented */
1306 spr_register(env, SPR_L2CR, "L2CR",
1307 SPR_NOACCESS, SPR_NOACCESS,
1308 &spr_read_generic, &spr_write_generic,
1309 0x00000000);
1310 /* Not strictly an SPR */
1311 vscr_init(env, 0x00010000);
1312 }
1313
1314 static void gen_l3_ctrl (CPUPPCState *env)
1315 {
1316 /* L3CR */
1317 /* XXX : not implemented */
1318 spr_register(env, SPR_L3CR, "L3CR",
1319 SPR_NOACCESS, SPR_NOACCESS,
1320 &spr_read_generic, &spr_write_generic,
1321 0x00000000);
1322 /* L3ITCR0 */
1323 /* XXX : not implemented */
1324 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1325 SPR_NOACCESS, SPR_NOACCESS,
1326 &spr_read_generic, &spr_write_generic,
1327 0x00000000);
1328 /* L3PM */
1329 /* XXX : not implemented */
1330 spr_register(env, SPR_L3PM, "L3PM",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_generic,
1333 0x00000000);
1334 }
1335
1336 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1337 {
1338 #if !defined(CONFIG_USER_ONLY)
1339 env->nb_tlb = nb_tlbs;
1340 env->nb_ways = nb_ways;
1341 env->id_tlbs = 1;
1342 env->tlb_type = TLB_6XX;
1343 /* XXX : not implemented */
1344 spr_register(env, SPR_PTEHI, "PTEHI",
1345 SPR_NOACCESS, SPR_NOACCESS,
1346 &spr_read_generic, &spr_write_generic,
1347 0x00000000);
1348 /* XXX : not implemented */
1349 spr_register(env, SPR_PTELO, "PTELO",
1350 SPR_NOACCESS, SPR_NOACCESS,
1351 &spr_read_generic, &spr_write_generic,
1352 0x00000000);
1353 /* XXX : not implemented */
1354 spr_register(env, SPR_TLBMISS, "TLBMISS",
1355 SPR_NOACCESS, SPR_NOACCESS,
1356 &spr_read_generic, &spr_write_generic,
1357 0x00000000);
1358 #endif
1359 }
1360
1361 #if !defined(CONFIG_USER_ONLY)
1362 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1363 {
1364 TCGv t0 = tcg_temp_new();
1365
1366 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1367 gen_store_spr(sprn, t0);
1368 tcg_temp_free(t0);
1369 }
1370
1371 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1372 {
1373 TCGv_i32 t0 = tcg_const_i32(sprn);
1374 gen_helper_booke206_tlbflush(cpu_env, t0);
1375 tcg_temp_free_i32(t0);
1376 }
1377
1378 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1379 {
1380 TCGv_i32 t0 = tcg_const_i32(sprn);
1381 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1382 tcg_temp_free_i32(t0);
1383 }
1384 #endif
1385
1386 static void gen_spr_usprgh (CPUPPCState *env)
1387 {
1388 spr_register(env, SPR_USPRG4, "USPRG4",
1389 &spr_read_ureg, SPR_NOACCESS,
1390 &spr_read_ureg, SPR_NOACCESS,
1391 0x00000000);
1392 spr_register(env, SPR_USPRG5, "USPRG5",
1393 &spr_read_ureg, SPR_NOACCESS,
1394 &spr_read_ureg, SPR_NOACCESS,
1395 0x00000000);
1396 spr_register(env, SPR_USPRG6, "USPRG6",
1397 &spr_read_ureg, SPR_NOACCESS,
1398 &spr_read_ureg, SPR_NOACCESS,
1399 0x00000000);
1400 spr_register(env, SPR_USPRG7, "USPRG7",
1401 &spr_read_ureg, SPR_NOACCESS,
1402 &spr_read_ureg, SPR_NOACCESS,
1403 0x00000000);
1404 }
1405
1406 /* PowerPC BookE SPR */
1407 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1408 {
1409 const char *ivor_names[64] = {
1410 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1411 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1412 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1413 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1414 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1415 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1416 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1417 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1418 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1419 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1420 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1421 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1422 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1423 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1424 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1425 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1426 };
1427 #define SPR_BOOKE_IVORxx (-1)
1428 int ivor_sprn[64] = {
1429 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1430 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1431 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1432 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1433 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1434 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1435 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1436 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1437 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1438 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1439 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1440 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1441 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1442 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1443 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1444 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1445 };
1446 int i;
1447
1448 /* Interrupt processing */
1449 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1450 SPR_NOACCESS, SPR_NOACCESS,
1451 &spr_read_generic, &spr_write_generic,
1452 0x00000000);
1453 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1454 SPR_NOACCESS, SPR_NOACCESS,
1455 &spr_read_generic, &spr_write_generic,
1456 0x00000000);
1457 /* Debug */
1458 /* XXX : not implemented */
1459 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1460 SPR_NOACCESS, SPR_NOACCESS,
1461 &spr_read_generic, &spr_write_generic,
1462 0x00000000);
1463 /* XXX : not implemented */
1464 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1465 SPR_NOACCESS, SPR_NOACCESS,
1466 &spr_read_generic, &spr_write_generic,
1467 0x00000000);
1468 /* XXX : not implemented */
1469 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1470 SPR_NOACCESS, SPR_NOACCESS,
1471 &spr_read_generic, &spr_write_generic,
1472 0x00000000);
1473 /* XXX : not implemented */
1474 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1475 SPR_NOACCESS, SPR_NOACCESS,
1476 &spr_read_generic, &spr_write_generic,
1477 0x00000000);
1478 /* XXX : not implemented */
1479 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1480 SPR_NOACCESS, SPR_NOACCESS,
1481 &spr_read_generic, &spr_write_generic,
1482 0x00000000);
1483 /* XXX : not implemented */
1484 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1485 SPR_NOACCESS, SPR_NOACCESS,
1486 &spr_read_generic, &spr_write_generic,
1487 0x00000000);
1488 /* XXX : not implemented */
1489 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1490 SPR_NOACCESS, SPR_NOACCESS,
1491 &spr_read_generic, &spr_write_generic,
1492 0x00000000);
1493 /* XXX : not implemented */
1494 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1495 SPR_NOACCESS, SPR_NOACCESS,
1496 &spr_read_generic, &spr_write_clear,
1497 0x00000000);
1498 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1499 SPR_NOACCESS, SPR_NOACCESS,
1500 &spr_read_generic, &spr_write_generic,
1501 0x00000000);
1502 spr_register(env, SPR_BOOKE_ESR, "ESR",
1503 SPR_NOACCESS, SPR_NOACCESS,
1504 &spr_read_generic, &spr_write_generic,
1505 0x00000000);
1506 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1507 SPR_NOACCESS, SPR_NOACCESS,
1508 &spr_read_generic, &spr_write_excp_prefix,
1509 0x00000000);
1510 /* Exception vectors */
1511 for (i = 0; i < 64; i++) {
1512 if (ivor_mask & (1ULL << i)) {
1513 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1514 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1515 exit(1);
1516 }
1517 spr_register(env, ivor_sprn[i], ivor_names[i],
1518 SPR_NOACCESS, SPR_NOACCESS,
1519 &spr_read_generic, &spr_write_excp_vector,
1520 0x00000000);
1521 }
1522 }
1523 spr_register(env, SPR_BOOKE_PID, "PID",
1524 SPR_NOACCESS, SPR_NOACCESS,
1525 &spr_read_generic, &spr_write_booke_pid,
1526 0x00000000);
1527 spr_register(env, SPR_BOOKE_TCR, "TCR",
1528 SPR_NOACCESS, SPR_NOACCESS,
1529 &spr_read_generic, &spr_write_booke_tcr,
1530 0x00000000);
1531 spr_register(env, SPR_BOOKE_TSR, "TSR",
1532 SPR_NOACCESS, SPR_NOACCESS,
1533 &spr_read_generic, &spr_write_booke_tsr,
1534 0x00000000);
1535 /* Timer */
1536 spr_register(env, SPR_DECR, "DECR",
1537 SPR_NOACCESS, SPR_NOACCESS,
1538 &spr_read_decr, &spr_write_decr,
1539 0x00000000);
1540 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1541 SPR_NOACCESS, SPR_NOACCESS,
1542 SPR_NOACCESS, &spr_write_generic,
1543 0x00000000);
1544 /* SPRGs */
1545 spr_register(env, SPR_USPRG0, "USPRG0",
1546 &spr_read_generic, &spr_write_generic,
1547 &spr_read_generic, &spr_write_generic,
1548 0x00000000);
1549 spr_register(env, SPR_SPRG4, "SPRG4",
1550 SPR_NOACCESS, SPR_NOACCESS,
1551 &spr_read_generic, &spr_write_generic,
1552 0x00000000);
1553 spr_register(env, SPR_SPRG5, "SPRG5",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
1557 spr_register(env, SPR_SPRG6, "SPRG6",
1558 SPR_NOACCESS, SPR_NOACCESS,
1559 &spr_read_generic, &spr_write_generic,
1560 0x00000000);
1561 spr_register(env, SPR_SPRG7, "SPRG7",
1562 SPR_NOACCESS, SPR_NOACCESS,
1563 &spr_read_generic, &spr_write_generic,
1564 0x00000000);
1565 }
1566
1567 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1568 uint32_t maxsize, uint32_t flags,
1569 uint32_t nentries)
1570 {
1571 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1572 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1573 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1574 flags | nentries;
1575 }
1576
1577 /* BookE 2.06 storage control registers */
1578 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1579 uint32_t *tlbncfg)
1580 {
1581 #if !defined(CONFIG_USER_ONLY)
1582 const char *mas_names[8] = {
1583 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1584 };
1585 int mas_sprn[8] = {
1586 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1587 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1588 };
1589 int i;
1590
1591 /* TLB assist registers */
1592 /* XXX : not implemented */
1593 for (i = 0; i < 8; i++) {
1594 if (mas_mask & (1 << i)) {
1595 spr_register(env, mas_sprn[i], mas_names[i],
1596 SPR_NOACCESS, SPR_NOACCESS,
1597 &spr_read_generic, &spr_write_generic,
1598 0x00000000);
1599 }
1600 }
1601 if (env->nb_pids > 1) {
1602 /* XXX : not implemented */
1603 spr_register(env, SPR_BOOKE_PID1, "PID1",
1604 SPR_NOACCESS, SPR_NOACCESS,
1605 &spr_read_generic, &spr_write_booke_pid,
1606 0x00000000);
1607 }
1608 if (env->nb_pids > 2) {
1609 /* XXX : not implemented */
1610 spr_register(env, SPR_BOOKE_PID2, "PID2",
1611 SPR_NOACCESS, SPR_NOACCESS,
1612 &spr_read_generic, &spr_write_booke_pid,
1613 0x00000000);
1614 }
1615 /* XXX : not implemented */
1616 spr_register(env, SPR_MMUCFG, "MMUCFG",
1617 SPR_NOACCESS, SPR_NOACCESS,
1618 &spr_read_generic, SPR_NOACCESS,
1619 0x00000000); /* TOFIX */
1620 switch (env->nb_ways) {
1621 case 4:
1622 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1623 SPR_NOACCESS, SPR_NOACCESS,
1624 &spr_read_generic, SPR_NOACCESS,
1625 tlbncfg[3]);
1626 /* Fallthru */
1627 case 3:
1628 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1629 SPR_NOACCESS, SPR_NOACCESS,
1630 &spr_read_generic, SPR_NOACCESS,
1631 tlbncfg[2]);
1632 /* Fallthru */
1633 case 2:
1634 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 &spr_read_generic, SPR_NOACCESS,
1637 tlbncfg[1]);
1638 /* Fallthru */
1639 case 1:
1640 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1641 SPR_NOACCESS, SPR_NOACCESS,
1642 &spr_read_generic, SPR_NOACCESS,
1643 tlbncfg[0]);
1644 /* Fallthru */
1645 case 0:
1646 default:
1647 break;
1648 }
1649 #endif
1650
1651 gen_spr_usprgh(env);
1652 }
1653
1654 /* SPR specific to PowerPC 440 implementation */
1655 static void gen_spr_440 (CPUPPCState *env)
1656 {
1657 /* Cache control */
1658 /* XXX : not implemented */
1659 spr_register(env, SPR_440_DNV0, "DNV0",
1660 SPR_NOACCESS, SPR_NOACCESS,
1661 &spr_read_generic, &spr_write_generic,
1662 0x00000000);
1663 /* XXX : not implemented */
1664 spr_register(env, SPR_440_DNV1, "DNV1",
1665 SPR_NOACCESS, SPR_NOACCESS,
1666 &spr_read_generic, &spr_write_generic,
1667 0x00000000);
1668 /* XXX : not implemented */
1669 spr_register(env, SPR_440_DNV2, "DNV2",
1670 SPR_NOACCESS, SPR_NOACCESS,
1671 &spr_read_generic, &spr_write_generic,
1672 0x00000000);
1673 /* XXX : not implemented */
1674 spr_register(env, SPR_440_DNV3, "DNV3",
1675 SPR_NOACCESS, SPR_NOACCESS,
1676 &spr_read_generic, &spr_write_generic,
1677 0x00000000);
1678 /* XXX : not implemented */
1679 spr_register(env, SPR_440_DTV0, "DTV0",
1680 SPR_NOACCESS, SPR_NOACCESS,
1681 &spr_read_generic, &spr_write_generic,
1682 0x00000000);
1683 /* XXX : not implemented */
1684 spr_register(env, SPR_440_DTV1, "DTV1",
1685 SPR_NOACCESS, SPR_NOACCESS,
1686 &spr_read_generic, &spr_write_generic,
1687 0x00000000);
1688 /* XXX : not implemented */
1689 spr_register(env, SPR_440_DTV2, "DTV2",
1690 SPR_NOACCESS, SPR_NOACCESS,
1691 &spr_read_generic, &spr_write_generic,
1692 0x00000000);
1693 /* XXX : not implemented */
1694 spr_register(env, SPR_440_DTV3, "DTV3",
1695 SPR_NOACCESS, SPR_NOACCESS,
1696 &spr_read_generic, &spr_write_generic,
1697 0x00000000);
1698 /* XXX : not implemented */
1699 spr_register(env, SPR_440_DVLIM, "DVLIM",
1700 SPR_NOACCESS, SPR_NOACCESS,
1701 &spr_read_generic, &spr_write_generic,
1702 0x00000000);
1703 /* XXX : not implemented */
1704 spr_register(env, SPR_440_INV0, "INV0",
1705 SPR_NOACCESS, SPR_NOACCESS,
1706 &spr_read_generic, &spr_write_generic,
1707 0x00000000);
1708 /* XXX : not implemented */
1709 spr_register(env, SPR_440_INV1, "INV1",
1710 SPR_NOACCESS, SPR_NOACCESS,
1711 &spr_read_generic, &spr_write_generic,
1712 0x00000000);
1713 /* XXX : not implemented */
1714 spr_register(env, SPR_440_INV2, "INV2",
1715 SPR_NOACCESS, SPR_NOACCESS,
1716 &spr_read_generic, &spr_write_generic,
1717 0x00000000);
1718 /* XXX : not implemented */
1719 spr_register(env, SPR_440_INV3, "INV3",
1720 SPR_NOACCESS, SPR_NOACCESS,
1721 &spr_read_generic, &spr_write_generic,
1722 0x00000000);
1723 /* XXX : not implemented */
1724 spr_register(env, SPR_440_ITV0, "ITV0",
1725 SPR_NOACCESS, SPR_NOACCESS,
1726 &spr_read_generic, &spr_write_generic,
1727 0x00000000);
1728 /* XXX : not implemented */
1729 spr_register(env, SPR_440_ITV1, "ITV1",
1730 SPR_NOACCESS, SPR_NOACCESS,
1731 &spr_read_generic, &spr_write_generic,
1732 0x00000000);
1733 /* XXX : not implemented */
1734 spr_register(env, SPR_440_ITV2, "ITV2",
1735 SPR_NOACCESS, SPR_NOACCESS,
1736 &spr_read_generic, &spr_write_generic,
1737 0x00000000);
1738 /* XXX : not implemented */
1739 spr_register(env, SPR_440_ITV3, "ITV3",
1740 SPR_NOACCESS, SPR_NOACCESS,
1741 &spr_read_generic, &spr_write_generic,
1742 0x00000000);
1743 /* XXX : not implemented */
1744 spr_register(env, SPR_440_IVLIM, "IVLIM",
1745 SPR_NOACCESS, SPR_NOACCESS,
1746 &spr_read_generic, &spr_write_generic,
1747 0x00000000);
1748 /* Cache debug */
1749 /* XXX : not implemented */
1750 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1751 SPR_NOACCESS, SPR_NOACCESS,
1752 &spr_read_generic, SPR_NOACCESS,
1753 0x00000000);
1754 /* XXX : not implemented */
1755 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1756 SPR_NOACCESS, SPR_NOACCESS,
1757 &spr_read_generic, SPR_NOACCESS,
1758 0x00000000);
1759 /* XXX : not implemented */
1760 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1761 SPR_NOACCESS, SPR_NOACCESS,
1762 &spr_read_generic, SPR_NOACCESS,
1763 0x00000000);
1764 /* XXX : not implemented */
1765 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1766 SPR_NOACCESS, SPR_NOACCESS,
1767 &spr_read_generic, SPR_NOACCESS,
1768 0x00000000);
1769 /* XXX : not implemented */
1770 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1771 SPR_NOACCESS, SPR_NOACCESS,
1772 &spr_read_generic, SPR_NOACCESS,
1773 0x00000000);
1774 /* XXX : not implemented */
1775 spr_register(env, SPR_440_DBDR, "DBDR",
1776 SPR_NOACCESS, SPR_NOACCESS,
1777 &spr_read_generic, &spr_write_generic,
1778 0x00000000);
1779 /* Processor control */
1780 spr_register(env, SPR_4xx_CCR0, "CCR0",
1781 SPR_NOACCESS, SPR_NOACCESS,
1782 &spr_read_generic, &spr_write_generic,
1783 0x00000000);
1784 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1785 SPR_NOACCESS, SPR_NOACCESS,
1786 &spr_read_generic, SPR_NOACCESS,
1787 0x00000000);
1788 /* Storage control */
1789 spr_register(env, SPR_440_MMUCR, "MMUCR",
1790 SPR_NOACCESS, SPR_NOACCESS,
1791 &spr_read_generic, &spr_write_generic,
1792 0x00000000);
1793 }
1794
1795 /* SPR shared between PowerPC 40x implementations */
1796 static void gen_spr_40x (CPUPPCState *env)
1797 {
1798 /* Cache */
1799 /* not emulated, as QEMU do not emulate caches */
1800 spr_register(env, SPR_40x_DCCR, "DCCR",
1801 SPR_NOACCESS, SPR_NOACCESS,
1802 &spr_read_generic, &spr_write_generic,
1803 0x00000000);
1804 /* not emulated, as QEMU do not emulate caches */
1805 spr_register(env, SPR_40x_ICCR, "ICCR",
1806 SPR_NOACCESS, SPR_NOACCESS,
1807 &spr_read_generic, &spr_write_generic,
1808 0x00000000);
1809 /* not emulated, as QEMU do not emulate caches */
1810 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1811 SPR_NOACCESS, SPR_NOACCESS,
1812 &spr_read_generic, SPR_NOACCESS,
1813 0x00000000);
1814 /* Exception */
1815 spr_register(env, SPR_40x_DEAR, "DEAR",
1816 SPR_NOACCESS, SPR_NOACCESS,
1817 &spr_read_generic, &spr_write_generic,
1818 0x00000000);
1819 spr_register(env, SPR_40x_ESR, "ESR",
1820 SPR_NOACCESS, SPR_NOACCESS,
1821 &spr_read_generic, &spr_write_generic,
1822 0x00000000);
1823 spr_register(env, SPR_40x_EVPR, "EVPR",
1824 SPR_NOACCESS, SPR_NOACCESS,
1825 &spr_read_generic, &spr_write_excp_prefix,
1826 0x00000000);
1827 spr_register(env, SPR_40x_SRR2, "SRR2",
1828 &spr_read_generic, &spr_write_generic,
1829 &spr_read_generic, &spr_write_generic,
1830 0x00000000);
1831 spr_register(env, SPR_40x_SRR3, "SRR3",
1832 &spr_read_generic, &spr_write_generic,
1833 &spr_read_generic, &spr_write_generic,
1834 0x00000000);
1835 /* Timers */
1836 spr_register(env, SPR_40x_PIT, "PIT",
1837 SPR_NOACCESS, SPR_NOACCESS,
1838 &spr_read_40x_pit, &spr_write_40x_pit,
1839 0x00000000);
1840 spr_register(env, SPR_40x_TCR, "TCR",
1841 SPR_NOACCESS, SPR_NOACCESS,
1842 &spr_read_generic, &spr_write_booke_tcr,
1843 0x00000000);
1844 spr_register(env, SPR_40x_TSR, "TSR",
1845 SPR_NOACCESS, SPR_NOACCESS,
1846 &spr_read_generic, &spr_write_booke_tsr,
1847 0x00000000);
1848 }
1849
1850 /* SPR specific to PowerPC 405 implementation */
1851 static void gen_spr_405 (CPUPPCState *env)
1852 {
1853 /* MMU */
1854 spr_register(env, SPR_40x_PID, "PID",
1855 SPR_NOACCESS, SPR_NOACCESS,
1856 &spr_read_generic, &spr_write_generic,
1857 0x00000000);
1858 spr_register(env, SPR_4xx_CCR0, "CCR0",
1859 SPR_NOACCESS, SPR_NOACCESS,
1860 &spr_read_generic, &spr_write_generic,
1861 0x00700000);
1862 /* Debug interface */
1863 /* XXX : not implemented */
1864 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1865 SPR_NOACCESS, SPR_NOACCESS,
1866 &spr_read_generic, &spr_write_40x_dbcr0,
1867 0x00000000);
1868 /* XXX : not implemented */
1869 spr_register(env, SPR_405_DBCR1, "DBCR1",
1870 SPR_NOACCESS, SPR_NOACCESS,
1871 &spr_read_generic, &spr_write_generic,
1872 0x00000000);
1873 /* XXX : not implemented */
1874 spr_register(env, SPR_40x_DBSR, "DBSR",
1875 SPR_NOACCESS, SPR_NOACCESS,
1876 &spr_read_generic, &spr_write_clear,
1877 /* Last reset was system reset */
1878 0x00000300);
1879 /* XXX : not implemented */
1880 spr_register(env, SPR_40x_DAC1, "DAC1",
1881 SPR_NOACCESS, SPR_NOACCESS,
1882 &spr_read_generic, &spr_write_generic,
1883 0x00000000);
1884 spr_register(env, SPR_40x_DAC2, "DAC2",
1885 SPR_NOACCESS, SPR_NOACCESS,
1886 &spr_read_generic, &spr_write_generic,
1887 0x00000000);
1888 /* XXX : not implemented */
1889 spr_register(env, SPR_405_DVC1, "DVC1",
1890 SPR_NOACCESS, SPR_NOACCESS,
1891 &spr_read_generic, &spr_write_generic,
1892 0x00000000);
1893 /* XXX : not implemented */
1894 spr_register(env, SPR_405_DVC2, "DVC2",
1895 SPR_NOACCESS, SPR_NOACCESS,
1896 &spr_read_generic, &spr_write_generic,
1897 0x00000000);
1898 /* XXX : not implemented */
1899 spr_register(env, SPR_40x_IAC1, "IAC1",
1900 SPR_NOACCESS, SPR_NOACCESS,
1901 &spr_read_generic, &spr_write_generic,
1902 0x00000000);
1903 spr_register(env, SPR_40x_IAC2, "IAC2",
1904 SPR_NOACCESS, SPR_NOACCESS,
1905 &spr_read_generic, &spr_write_generic,
1906 0x00000000);
1907 /* XXX : not implemented */
1908 spr_register(env, SPR_405_IAC3, "IAC3",
1909 SPR_NOACCESS, SPR_NOACCESS,
1910 &spr_read_generic, &spr_write_generic,
1911 0x00000000);
1912 /* XXX : not implemented */
1913 spr_register(env, SPR_405_IAC4, "IAC4",
1914 SPR_NOACCESS, SPR_NOACCESS,
1915 &spr_read_generic, &spr_write_generic,
1916 0x00000000);
1917 /* Storage control */
1918 /* XXX: TODO: not implemented */
1919 spr_register(env, SPR_405_SLER, "SLER",
1920 SPR_NOACCESS, SPR_NOACCESS,
1921 &spr_read_generic, &spr_write_40x_sler,
1922 0x00000000);
1923 spr_register(env, SPR_40x_ZPR, "ZPR",
1924 SPR_NOACCESS, SPR_NOACCESS,
1925 &spr_read_generic, &spr_write_generic,
1926 0x00000000);
1927 /* XXX : not implemented */
1928 spr_register(env, SPR_405_SU0R, "SU0R",
1929 SPR_NOACCESS, SPR_NOACCESS,
1930 &spr_read_generic, &spr_write_generic,
1931 0x00000000);
1932 /* SPRG */
1933 spr_register(env, SPR_USPRG0, "USPRG0",
1934 &spr_read_ureg, SPR_NOACCESS,
1935 &spr_read_ureg, SPR_NOACCESS,
1936 0x00000000);
1937 spr_register(env, SPR_SPRG4, "SPRG4",
1938 SPR_NOACCESS, SPR_NOACCESS,
1939 &spr_read_generic, &spr_write_generic,
1940 0x00000000);
1941 spr_register(env, SPR_SPRG5, "SPRG5",
1942 SPR_NOACCESS, SPR_NOACCESS,
1943 spr_read_generic, &spr_write_generic,
1944 0x00000000);
1945 spr_register(env, SPR_SPRG6, "SPRG6",
1946 SPR_NOACCESS, SPR_NOACCESS,
1947 spr_read_generic, &spr_write_generic,
1948 0x00000000);
1949 spr_register(env, SPR_SPRG7, "SPRG7",
1950 SPR_NOACCESS, SPR_NOACCESS,
1951 spr_read_generic, &spr_write_generic,
1952 0x00000000);
1953 gen_spr_usprgh(env);
1954 }
1955
1956 /* SPR shared between PowerPC 401 & 403 implementations */
1957 static void gen_spr_401_403 (CPUPPCState *env)
1958 {
1959 /* Time base */
1960 spr_register(env, SPR_403_VTBL, "TBL",
1961 &spr_read_tbl, SPR_NOACCESS,
1962 &spr_read_tbl, SPR_NOACCESS,
1963 0x00000000);
1964 spr_register(env, SPR_403_TBL, "TBL",
1965 SPR_NOACCESS, SPR_NOACCESS,
1966 SPR_NOACCESS, &spr_write_tbl,
1967 0x00000000);
1968 spr_register(env, SPR_403_VTBU, "TBU",
1969 &spr_read_tbu, SPR_NOACCESS,
1970 &spr_read_tbu, SPR_NOACCESS,
1971 0x00000000);
1972 spr_register(env, SPR_403_TBU, "TBU",
1973 SPR_NOACCESS, SPR_NOACCESS,
1974 SPR_NOACCESS, &spr_write_tbu,
1975 0x00000000);
1976 /* Debug */
1977 /* not emulated, as QEMU do not emulate caches */
1978 spr_register(env, SPR_403_CDBCR, "CDBCR",
1979 SPR_NOACCESS, SPR_NOACCESS,
1980 &spr_read_generic, &spr_write_generic,
1981 0x00000000);
1982 }
1983
1984 /* SPR specific to PowerPC 401 implementation */
1985 static void gen_spr_401 (CPUPPCState *env)
1986 {
1987 /* Debug interface */
1988 /* XXX : not implemented */
1989 spr_register(env, SPR_40x_DBCR0, "DBCR",
1990 SPR_NOACCESS, SPR_NOACCESS,
1991 &spr_read_generic, &spr_write_40x_dbcr0,
1992 0x00000000);
1993 /* XXX : not implemented */
1994 spr_register(env, SPR_40x_DBSR, "DBSR",
1995 SPR_NOACCESS, SPR_NOACCESS,
1996 &spr_read_generic, &spr_write_clear,
1997 /* Last reset was system reset */
1998 0x00000300);
1999 /* XXX : not implemented */
2000 spr_register(env, SPR_40x_DAC1, "DAC",
2001 SPR_NOACCESS, SPR_NOACCESS,
2002 &spr_read_generic, &spr_write_generic,
2003 0x00000000);
2004 /* XXX : not implemented */
2005 spr_register(env, SPR_40x_IAC1, "IAC",
2006 SPR_NOACCESS, SPR_NOACCESS,
2007 &spr_read_generic, &spr_write_generic,
2008 0x00000000);
2009 /* Storage control */
2010 /* XXX: TODO: not implemented */
2011 spr_register(env, SPR_405_SLER, "SLER",
2012 SPR_NOACCESS, SPR_NOACCESS,
2013 &spr_read_generic, &spr_write_40x_sler,
2014 0x00000000);
2015 /* not emulated, as QEMU never does speculative access */
2016 spr_register(env, SPR_40x_SGR, "SGR",
2017 SPR_NOACCESS, SPR_NOACCESS,
2018 &spr_read_generic, &spr_write_generic,
2019 0xFFFFFFFF);
2020 /* not emulated, as QEMU do not emulate caches */
2021 spr_register(env, SPR_40x_DCWR, "DCWR",
2022 SPR_NOACCESS, SPR_NOACCESS,
2023 &spr_read_generic, &spr_write_generic,
2024 0x00000000);
2025 }
2026
2027 static void gen_spr_401x2 (CPUPPCState *env)
2028 {
2029 gen_spr_401(env);
2030 spr_register(env, SPR_40x_PID, "PID",
2031 SPR_NOACCESS, SPR_NOACCESS,
2032 &spr_read_generic, &spr_write_generic,
2033 0x00000000);
2034 spr_register(env, SPR_40x_ZPR, "ZPR",
2035 SPR_NOACCESS, SPR_NOACCESS,
2036 &spr_read_generic, &spr_write_generic,
2037 0x00000000);
2038 }
2039
2040 /* SPR specific to PowerPC 403 implementation */
2041 static void gen_spr_403 (CPUPPCState *env)
2042 {
2043 /* Debug interface */
2044 /* XXX : not implemented */
2045 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2046 SPR_NOACCESS, SPR_NOACCESS,
2047 &spr_read_generic, &spr_write_40x_dbcr0,
2048 0x00000000);
2049 /* XXX : not implemented */
2050 spr_register(env, SPR_40x_DBSR, "DBSR",
2051 SPR_NOACCESS, SPR_NOACCESS,
2052 &spr_read_generic, &spr_write_clear,
2053 /* Last reset was system reset */
2054 0x00000300);
2055 /* XXX : not implemented */
2056 spr_register(env, SPR_40x_DAC1, "DAC1",
2057 SPR_NOACCESS, SPR_NOACCESS,
2058 &spr_read_generic, &spr_write_generic,
2059 0x00000000);
2060 /* XXX : not implemented */
2061 spr_register(env, SPR_40x_DAC2, "DAC2",
2062 SPR_NOACCESS, SPR_NOACCESS,
2063 &spr_read_generic, &spr_write_generic,
2064 0x00000000);
2065 /* XXX : not implemented */
2066 spr_register(env, SPR_40x_IAC1, "IAC1",
2067 SPR_NOACCESS, SPR_NOACCESS,
2068 &spr_read_generic, &spr_write_generic,
2069 0x00000000);
2070 /* XXX : not implemented */
2071 spr_register(env, SPR_40x_IAC2, "IAC2",
2072 SPR_NOACCESS, SPR_NOACCESS,
2073 &spr_read_generic, &spr_write_generic,
2074 0x00000000);
2075 }
2076
2077 static void gen_spr_403_real (CPUPPCState *env)
2078 {
2079 spr_register(env, SPR_403_PBL1, "PBL1",
2080 SPR_NOACCESS, SPR_NOACCESS,
2081 &spr_read_403_pbr, &spr_write_403_pbr,
2082 0x00000000);
2083 spr_register(env, SPR_403_PBU1, "PBU1",
2084 SPR_NOACCESS, SPR_NOACCESS,
2085 &spr_read_403_pbr, &spr_write_403_pbr,
2086 0x00000000);
2087 spr_register(env, SPR_403_PBL2, "PBL2",
2088 SPR_NOACCESS, SPR_NOACCESS,
2089 &spr_read_403_pbr, &spr_write_403_pbr,
2090 0x00000000);
2091 spr_register(env, SPR_403_PBU2, "PBU2",
2092 SPR_NOACCESS, SPR_NOACCESS,
2093 &spr_read_403_pbr, &spr_write_403_pbr,
2094 0x00000000);
2095 }
2096
2097 static void gen_spr_403_mmu (CPUPPCState *env)
2098 {
2099 /* MMU */
2100 spr_register(env, SPR_40x_PID, "PID",
2101 SPR_NOACCESS, SPR_NOACCESS,
2102 &spr_read_generic, &spr_write_generic,
2103 0x00000000);
2104 spr_register(env, SPR_40x_ZPR, "ZPR",
2105 SPR_NOACCESS, SPR_NOACCESS,
2106 &spr_read_generic, &spr_write_generic,
2107 0x00000000);
2108 }
2109
2110 /* SPR specific to PowerPC compression coprocessor extension */
2111 static void gen_spr_compress (CPUPPCState *env)
2112 {
2113 /* XXX : not implemented */
2114 spr_register(env, SPR_401_SKR, "SKR",
2115 SPR_NOACCESS, SPR_NOACCESS,
2116 &spr_read_generic, &spr_write_generic,
2117 0x00000000);
2118 }
2119
2120 #if defined (TARGET_PPC64)
2121 /* SPR specific to PowerPC 620 */
2122 static void gen_spr_620 (CPUPPCState *env)
2123 {
2124 /* Processor identification */
2125 spr_register(env, SPR_PIR, "PIR",
2126 SPR_NOACCESS, SPR_NOACCESS,
2127 &spr_read_generic, &spr_write_pir,
2128 0x00000000);
2129 spr_register(env, SPR_ASR, "ASR",
2130 SPR_NOACCESS, SPR_NOACCESS,
2131 &spr_read_asr, &spr_write_asr,
2132 0x00000000);
2133 /* Breakpoints */
2134 /* XXX : not implemented */
2135 spr_register(env, SPR_IABR, "IABR",
2136 SPR_NOACCESS, SPR_NOACCESS,
2137 &spr_read_generic, &spr_write_generic,
2138 0x00000000);
2139 /* XXX : not implemented */
2140 spr_register(env, SPR_DABR, "DABR",
2141 SPR_NOACCESS, SPR_NOACCESS,
2142 &spr_read_generic, &spr_write_generic,
2143 0x00000000);
2144 /* XXX : not implemented */
2145 spr_register(env, SPR_SIAR, "SIAR",
2146 SPR_NOACCESS, SPR_NOACCESS,
2147 &spr_read_generic, SPR_NOACCESS,
2148 0x00000000);
2149 /* XXX : not implemented */
2150 spr_register(env, SPR_SDA, "SDA",
2151 SPR_NOACCESS, SPR_NOACCESS,
2152 &spr_read_generic, SPR_NOACCESS,
2153 0x00000000);
2154 /* XXX : not implemented */
2155 spr_register(env, SPR_620_PMC1R, "PMC1",
2156 SPR_NOACCESS, SPR_NOACCESS,
2157 &spr_read_generic, SPR_NOACCESS,
2158 0x00000000);
2159 spr_register(env, SPR_620_PMC1W, "PMC1",
2160 SPR_NOACCESS, SPR_NOACCESS,
2161 SPR_NOACCESS, &spr_write_generic,
2162 0x00000000);
2163 /* XXX : not implemented */
2164 spr_register(env, SPR_620_PMC2R, "PMC2",
2165 SPR_NOACCESS, SPR_NOACCESS,
2166 &spr_read_generic, SPR_NOACCESS,
2167 0x00000000);
2168 spr_register(env, SPR_620_PMC2W, "PMC2",
2169 SPR_NOACCESS, SPR_NOACCESS,
2170 SPR_NOACCESS, &spr_write_generic,
2171 0x00000000);
2172 /* XXX : not implemented */
2173 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2174 SPR_NOACCESS, SPR_NOACCESS,
2175 &spr_read_generic, SPR_NOACCESS,
2176 0x00000000);
2177 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2178 SPR_NOACCESS, SPR_NOACCESS,
2179 SPR_NOACCESS, &spr_write_generic,
2180 0x00000000);
2181 /* External access control */
2182 /* XXX : not implemented */
2183 spr_register(env, SPR_EAR, "EAR",
2184 SPR_NOACCESS, SPR_NOACCESS,
2185 &spr_read_generic, &spr_write_generic,
2186 0x00000000);
2187 #if 0 // XXX: check this
2188 /* XXX : not implemented */
2189 spr_register(env, SPR_620_PMR0, "PMR0",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 &spr_read_generic, &spr_write_generic,
2192 0x00000000);
2193 /* XXX : not implemented */
2194 spr_register(env, SPR_620_PMR1, "PMR1",
2195 SPR_NOACCESS, SPR_NOACCESS,
2196 &spr_read_generic, &spr_write_generic,
2197 0x00000000);
2198 /* XXX : not implemented */
2199 spr_register(env, SPR_620_PMR2, "PMR2",
2200 SPR_NOACCESS, SPR_NOACCESS,
2201 &spr_read_generic, &spr_write_generic,
2202 0x00000000);
2203 /* XXX : not implemented */
2204 spr_register(env, SPR_620_PMR3, "PMR3",
2205 SPR_NOACCESS, SPR_NOACCESS,
2206 &spr_read_generic, &spr_write_generic,
2207 0x00000000);
2208 /* XXX : not implemented */
2209 spr_register(env, SPR_620_PMR4, "PMR4",
2210 SPR_NOACCESS, SPR_NOACCESS,
2211 &spr_read_generic, &spr_write_generic,
2212 0x00000000);
2213 /* XXX : not implemented */
2214 spr_register(env, SPR_620_PMR5, "PMR5",
2215 SPR_NOACCESS, SPR_NOACCESS,
2216 &spr_read_generic, &spr_write_generic,
2217 0x00000000);
2218 /* XXX : not implemented */
2219 spr_register(env, SPR_620_PMR6, "PMR6",
2220 SPR_NOACCESS, SPR_NOACCESS,
2221 &spr_read_generic, &spr_write_generic,
2222 0x00000000);
2223 /* XXX : not implemented */
2224 spr_register(env, SPR_620_PMR7, "PMR7",
2225 SPR_NOACCESS, SPR_NOACCESS,
2226 &spr_read_generic, &spr_write_generic,
2227 0x00000000);
2228 /* XXX : not implemented */
2229 spr_register(env, SPR_620_PMR8, "PMR8",
2230 SPR_NOACCESS, SPR_NOACCESS,
2231 &spr_read_generic, &spr_write_generic,
2232 0x00000000);
2233 /* XXX : not implemented */
2234 spr_register(env, SPR_620_PMR9, "PMR9",
2235 SPR_NOACCESS, SPR_NOACCESS,
2236 &spr_read_generic, &spr_write_generic,
2237 0x00000000);
2238 /* XXX : not implemented */
2239 spr_register(env, SPR_620_PMRA, "PMR10",
2240 SPR_NOACCESS, SPR_NOACCESS,
2241 &spr_read_generic, &spr_write_generic,
2242 0x00000000);
2243 /* XXX : not implemented */
2244 spr_register(env, SPR_620_PMRB, "PMR11",
2245 SPR_NOACCESS, SPR_NOACCESS,
2246 &spr_read_generic, &spr_write_generic,
2247 0x00000000);
2248 /* XXX : not implemented */
2249 spr_register(env, SPR_620_PMRC, "PMR12",
2250 SPR_NOACCESS, SPR_NOACCESS,
2251 &spr_read_generic, &spr_write_generic,
2252 0x00000000);
2253 /* XXX : not implemented */
2254 spr_register(env, SPR_620_PMRD, "PMR13",
2255 SPR_NOACCESS, SPR_NOACCESS,
2256 &spr_read_generic, &spr_write_generic,
2257 0x00000000);
2258 /* XXX : not implemented */
2259 spr_register(env, SPR_620_PMRE, "PMR14",
2260 SPR_NOACCESS, SPR_NOACCESS,
2261 &spr_read_generic, &spr_write_generic,
2262 0x00000000);
2263 /* XXX : not implemented */
2264 spr_register(env, SPR_620_PMRF, "PMR15",
2265 SPR_NOACCESS, SPR_NOACCESS,
2266 &spr_read_generic, &spr_write_generic,
2267 0x00000000);
2268 #endif
2269 /* XXX : not implemented */
2270 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2271 SPR_NOACCESS, SPR_NOACCESS,
2272 &spr_read_generic, &spr_write_generic,
2273 0x00000000);
2274 /* XXX : not implemented */
2275 spr_register(env, SPR_620_L2CR, "L2CR",
2276 SPR_NOACCESS, SPR_NOACCESS,
2277 &spr_read_generic, &spr_write_generic,
2278 0x00000000);
2279 /* XXX : not implemented */
2280 spr_register(env, SPR_620_L2SR, "L2SR",
2281 SPR_NOACCESS, SPR_NOACCESS,
2282 &spr_read_generic, &spr_write_generic,
2283 0x00000000);
2284 }
2285 #endif /* defined (TARGET_PPC64) */
2286
2287 static void gen_spr_5xx_8xx (CPUPPCState *env)
2288 {
2289 /* Exception processing */
2290 spr_register(env, SPR_DSISR, "DSISR",
2291 SPR_NOACCESS, SPR_NOACCESS,
2292 &spr_read_generic, &spr_write_generic,
2293 0x00000000);
2294 spr_register(env, SPR_DAR, "DAR",
2295 SPR_NOACCESS, SPR_NOACCESS,
2296 &spr_read_generic, &spr_write_generic,
2297 0x00000000);
2298 /* Timer */
2299 spr_register(env, SPR_DECR, "DECR",
2300 SPR_NOACCESS, SPR_NOACCESS,
2301 &spr_read_decr, &spr_write_decr,
2302 0x00000000);
2303 /* XXX : not implemented */
2304 spr_register(env, SPR_MPC_EIE, "EIE",
2305 SPR_NOACCESS, SPR_NOACCESS,
2306 &spr_read_generic, &spr_write_generic,
2307 0x00000000);
2308 /* XXX : not implemented */
2309 spr_register(env, SPR_MPC_EID, "EID",
2310 SPR_NOACCESS, SPR_NOACCESS,
2311 &spr_read_generic, &spr_write_generic,
2312 0x00000000);
2313 /* XXX : not implemented */
2314 spr_register(env, SPR_MPC_NRI, "NRI",
2315 SPR_NOACCESS, SPR_NOACCESS,
2316 &spr_read_generic, &spr_write_generic,
2317 0x00000000);
2318 /* XXX : not implemented */
2319 spr_register(env, SPR_MPC_CMPA, "CMPA",
2320 SPR_NOACCESS, SPR_NOACCESS,
2321 &spr_read_generic, &spr_write_generic,
2322 0x00000000);
2323 /* XXX : not implemented */
2324 spr_register(env, SPR_MPC_CMPB, "CMPB",
2325 SPR_NOACCESS, SPR_NOACCESS,
2326 &spr_read_generic, &spr_write_generic,
2327 0x00000000);
2328 /* XXX : not implemented */
2329 spr_register(env, SPR_MPC_CMPC, "CMPC",
2330 SPR_NOACCESS, SPR_NOACCESS,
2331 &spr_read_generic, &spr_write_generic,
2332 0x00000000);
2333 /* XXX : not implemented */
2334 spr_register(env, SPR_MPC_CMPD, "CMPD",
2335 SPR_NOACCESS, SPR_NOACCESS,
2336 &spr_read_generic, &spr_write_generic,
2337 0x00000000);
2338 /* XXX : not implemented */
2339 spr_register(env, SPR_MPC_ECR, "ECR",
2340 SPR_NOACCESS, SPR_NOACCESS,
2341 &spr_read_generic, &spr_write_generic,
2342 0x00000000);
2343 /* XXX : not implemented */
2344 spr_register(env, SPR_MPC_DER, "DER",
2345 SPR_NOACCESS, SPR_NOACCESS,
2346 &spr_read_generic, &spr_write_generic,
2347 0x00000000);
2348 /* XXX : not implemented */
2349 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2350 SPR_NOACCESS, SPR_NOACCESS,
2351 &spr_read_generic, &spr_write_generic,
2352 0x00000000);
2353 /* XXX : not implemented */
2354 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2355 SPR_NOACCESS, SPR_NOACCESS,
2356 &spr_read_generic, &spr_write_generic,
2357 0x00000000);
2358 /* XXX : not implemented */
2359 spr_register(env, SPR_MPC_CMPE, "CMPE",
2360 SPR_NOACCESS, SPR_NOACCESS,
2361 &spr_read_generic, &spr_write_generic,
2362 0x00000000);
2363 /* XXX : not implemented */
2364 spr_register(env, SPR_MPC_CMPF, "CMPF",
2365 SPR_NOACCESS, SPR_NOACCESS,
2366 &spr_read_generic, &spr_write_generic,
2367 0x00000000);
2368 /* XXX : not implemented */
2369 spr_register(env, SPR_MPC_CMPG, "CMPG",
2370 SPR_NOACCESS, SPR_NOACCESS,
2371 &spr_read_generic, &spr_write_generic,
2372 0x00000000);
2373 /* XXX : not implemented */
2374 spr_register(env, SPR_MPC_CMPH, "CMPH",
2375 SPR_NOACCESS, SPR_NOACCESS,
2376 &spr_read_generic, &spr_write_generic,
2377 0x00000000);
2378 /* XXX : not implemented */
2379 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2380 SPR_NOACCESS, SPR_NOACCESS,
2381 &spr_read_generic, &spr_write_generic,
2382 0x00000000);
2383 /* XXX : not implemented */
2384 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2385 SPR_NOACCESS, SPR_NOACCESS,
2386 &spr_read_generic, &spr_write_generic,
2387 0x00000000);
2388 /* XXX : not implemented */
2389 spr_register(env, SPR_MPC_BAR, "BAR",
2390 SPR_NOACCESS, SPR_NOACCESS,
2391 &spr_read_generic, &spr_write_generic,
2392 0x00000000);
2393 /* XXX : not implemented */
2394 spr_register(env, SPR_MPC_DPDR, "DPDR",
2395 SPR_NOACCESS, SPR_NOACCESS,
2396 &spr_read_generic, &spr_write_generic,
2397 0x00000000);
2398 /* XXX : not implemented */
2399 spr_register(env, SPR_MPC_IMMR, "IMMR",
2400 SPR_NOACCESS, SPR_NOACCESS,
2401 &spr_read_generic, &spr_write_generic,
2402 0x00000000);
2403 }
2404
2405 static void gen_spr_5xx (CPUPPCState *env)
2406 {
2407 /* XXX : not implemented */
2408 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2409 SPR_NOACCESS, SPR_NOACCESS,
2410 &spr_read_generic, &spr_write_generic,
2411 0x00000000);
2412 /* XXX : not implemented */
2413 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2414 SPR_NOACCESS, SPR_NOACCESS,
2415 &spr_read_generic, &spr_write_generic,
2416 0x00000000);
2417 /* XXX : not implemented */
2418 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2419 SPR_NOACCESS, SPR_NOACCESS,
2420 &spr_read_generic, &spr_write_generic,
2421 0x00000000);
2422 /* XXX : not implemented */
2423 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2424 SPR_NOACCESS, SPR_NOACCESS,
2425 &spr_read_generic, &spr_write_generic,
2426 0x00000000);
2427 /* XXX : not implemented */
2428 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2429 SPR_NOACCESS, SPR_NOACCESS,
2430 &spr_read_generic, &spr_write_generic,
2431 0x00000000);
2432 /* XXX : not implemented */
2433 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2434 SPR_NOACCESS, SPR_NOACCESS,
2435 &spr_read_generic, &spr_write_generic,
2436 0x00000000);
2437 /* XXX : not implemented */
2438 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2439 SPR_NOACCESS, SPR_NOACCESS,
2440 &spr_read_generic, &spr_write_generic,
2441 0x00000000);
2442 /* XXX : not implemented */
2443 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2444 SPR_NOACCESS, SPR_NOACCESS,
2445 &spr_read_generic, &spr_write_generic,
2446 0x00000000);
2447 /* XXX : not implemented */
2448 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2449 SPR_NOACCESS, SPR_NOACCESS,
2450 &spr_read_generic, &spr_write_generic,
2451 0x00000000);
2452 /* XXX : not implemented */
2453 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2454 SPR_NOACCESS, SPR_NOACCESS,
2455 &spr_read_generic, &spr_write_generic,
2456 0x00000000);
2457 /* XXX : not implemented */
2458 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2459 SPR_NOACCESS, SPR_NOACCESS,
2460 &spr_read_generic, &spr_write_generic,
2461 0x00000000);
2462 /* XXX : not implemented */
2463 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2464 SPR_NOACCESS, SPR_NOACCESS,
2465 &spr_read_generic, &spr_write_generic,
2466 0x00000000);
2467 /* XXX : not implemented */
2468 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2469 SPR_NOACCESS, SPR_NOACCESS,
2470 &spr_read_generic, &spr_write_generic,
2471 0x00000000);
2472 /* XXX : not implemented */
2473 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2474 SPR_NOACCESS, SPR_NOACCESS,
2475 &spr_read_generic, &spr_write_generic,
2476 0x00000000);
2477 /* XXX : not implemented */
2478 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2479 SPR_NOACCESS, SPR_NOACCESS,
2480 &spr_read_generic, &spr_write_generic,
2481 0x00000000);
2482 /* XXX : not implemented */
2483 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2484 SPR_NOACCESS, SPR_NOACCESS,
2485 &spr_read_generic, &spr_write_generic,
2486 0x00000000);
2487 /* XXX : not implemented */
2488 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2489 SPR_NOACCESS, SPR_NOACCESS,
2490 &spr_read_generic, &spr_write_generic,
2491 0x00000000);
2492 /* XXX : not implemented */
2493 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2494 SPR_NOACCESS, SPR_NOACCESS,
2495 &spr_read_generic, &spr_write_generic,
2496 0x00000000);
2497 /* XXX : not implemented */
2498 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2499 SPR_NOACCESS, SPR_NOACCESS,
2500 &spr_read_generic, &spr_write_generic,
2501 0x00000000);
2502 /* XXX : not implemented */
2503 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2504 SPR_NOACCESS, SPR_NOACCESS,
2505 &spr_read_generic, &spr_write_generic,
2506 0x00000000);
2507 /* XXX : not implemented */
2508 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2509 SPR_NOACCESS, SPR_NOACCESS,
2510 &spr_read_generic, &spr_write_generic,
2511 0x00000000);
2512 }
2513
2514 static void gen_spr_8xx (CPUPPCState *env)
2515 {
2516 /* XXX : not implemented */
2517 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2518 SPR_NOACCESS, SPR_NOACCESS,
2519 &spr_read_generic, &spr_write_generic,
2520 0x00000000);
2521 /* XXX : not implemented */
2522 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2523 SPR_NOACCESS, SPR_NOACCESS,
2524 &spr_read_generic, &spr_write_generic,
2525 0x00000000);
2526 /* XXX : not implemented */
2527 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2528 SPR_NOACCESS, SPR_NOACCESS,
2529 &spr_read_generic, &spr_write_generic,
2530 0x00000000);
2531 /* XXX : not implemented */
2532 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2533 SPR_NOACCESS, SPR_NOACCESS,
2534 &spr_read_generic, &spr_write_generic,
2535 0x00000000);
2536 /* XXX : not implemented */
2537 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2538 SPR_NOACCESS, SPR_NOACCESS,
2539 &spr_read_generic, &spr_write_generic,
2540 0x00000000);
2541 /* XXX : not implemented */
2542 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2543 SPR_NOACCESS, SPR_NOACCESS,
2544 &spr_read_generic, &spr_write_generic,
2545 0x00000000);
2546 /* XXX : not implemented */
2547 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2548 SPR_NOACCESS, SPR_NOACCESS,
2549 &spr_read_generic, &spr_write_generic,
2550 0x00000000);
2551 /* XXX : not implemented */
2552 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2553 SPR_NOACCESS, SPR_NOACCESS,
2554 &spr_read_generic, &spr_write_generic,
2555 0x00000000);
2556 /* XXX : not implemented */
2557 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2558 SPR_NOACCESS, SPR_NOACCESS,
2559 &spr_read_generic, &spr_write_generic,
2560 0x00000000);
2561 /* XXX : not implemented */
2562 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2563 SPR_NOACCESS, SPR_NOACCESS,
2564 &spr_read_generic, &spr_write_generic,
2565 0x00000000);
2566 /* XXX : not implemented */
2567 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2568 SPR_NOACCESS, SPR_NOACCESS,
2569 &spr_read_generic, &spr_write_generic,
2570 0x00000000);
2571 /* XXX : not implemented */
2572 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2573 SPR_NOACCESS, SPR_NOACCESS,
2574 &spr_read_generic, &spr_write_generic,
2575 0x00000000);
2576 /* XXX : not implemented */
2577 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2578 SPR_NOACCESS, SPR_NOACCESS,
2579 &spr_read_generic, &spr_write_generic,
2580 0x00000000);
2581 /* XXX : not implemented */
2582 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2583 SPR_NOACCESS, SPR_NOACCESS,
2584 &spr_read_generic, &spr_write_generic,
2585 0x00000000);
2586 /* XXX : not implemented */
2587 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2588 SPR_NOACCESS, SPR_NOACCESS,
2589 &spr_read_generic, &spr_write_generic,
2590 0x00000000);
2591 /* XXX : not implemented */
2592 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2593 SPR_NOACCESS, SPR_NOACCESS,
2594 &spr_read_generic, &spr_write_generic,
2595 0x00000000);
2596 /* XXX : not implemented */
2597 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2598 SPR_NOACCESS, SPR_NOACCESS,
2599 &spr_read_generic, &spr_write_generic,
2600 0x00000000);
2601 /* XXX : not implemented */
2602 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2603 SPR_NOACCESS, SPR_NOACCESS,
2604 &spr_read_generic, &spr_write_generic,
2605 0x00000000);
2606 /* XXX : not implemented */
2607 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2608 SPR_NOACCESS, SPR_NOACCESS,
2609 &spr_read_generic, &spr_write_generic,
2610 0x00000000);
2611 /* XXX : not implemented */
2612 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2613 SPR_NOACCESS, SPR_NOACCESS,
2614 &spr_read_generic, &spr_write_generic,
2615 0x00000000);
2616 /* XXX : not implemented */
2617 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2618 SPR_NOACCESS, SPR_NOACCESS,
2619 &spr_read_generic, &spr_write_generic,
2620 0x00000000);
2621 /* XXX : not implemented */
2622 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2623 SPR_NOACCESS, SPR_NOACCESS,
2624 &spr_read_generic, &spr_write_generic,
2625 0x00000000);
2626 /* XXX : not implemented */
2627 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2628 SPR_NOACCESS, SPR_NOACCESS,
2629 &spr_read_generic, &spr_write_generic,
2630 0x00000000);
2631 /* XXX : not implemented */
2632 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2633 SPR_NOACCESS, SPR_NOACCESS,
2634 &spr_read_generic, &spr_write_generic,
2635 0x00000000);
2636 /* XXX : not implemented */
2637 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2638 SPR_NOACCESS, SPR_NOACCESS,
2639 &spr_read_generic, &spr_write_generic,
2640 0x00000000);
2641 }
2642
2643 // XXX: TODO
2644 /*
2645 * AMR => SPR 29 (Power 2.04)
2646 * CTRL => SPR 136 (Power 2.04)
2647 * CTRL => SPR 152 (Power 2.04)
2648 * SCOMC => SPR 276 (64 bits ?)
2649 * SCOMD => SPR 277 (64 bits ?)
2650 * TBU40 => SPR 286 (Power 2.04 hypv)
2651 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2652 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2653 * HDSISR => SPR 306 (Power 2.04 hypv)
2654 * HDAR => SPR 307 (Power 2.04 hypv)
2655 * PURR => SPR 309 (Power 2.04 hypv)
2656 * HDEC => SPR 310 (Power 2.04 hypv)
2657 * HIOR => SPR 311 (hypv)
2658 * RMOR => SPR 312 (970)
2659 * HRMOR => SPR 313 (Power 2.04 hypv)
2660 * HSRR0 => SPR 314 (Power 2.04 hypv)
2661 * HSRR1 => SPR 315 (Power 2.04 hypv)
2662 * LPCR => SPR 316 (970)
2663 * LPIDR => SPR 317 (970)
2664 * EPR => SPR 702 (Power 2.04 emb)
2665 * perf => 768-783 (Power 2.04)
2666 * perf => 784-799 (Power 2.04)
2667 * PPR => SPR 896 (Power 2.04)
2668 * EPLC => SPR 947 (Power 2.04 emb)
2669 * EPSC => SPR 948 (Power 2.04 emb)
2670 * DABRX => 1015 (Power 2.04 hypv)
2671 * FPECR => SPR 1022 (?)
2672 * ... and more (thermal management, performance counters, ...)
2673 */
2674
2675 /*****************************************************************************/
2676 /* Exception vectors models */
2677 static void init_excp_4xx_real (CPUPPCState *env)
2678 {
2679 #if !defined(CONFIG_USER_ONLY)
2680 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2681 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2682 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2683 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2684 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2685 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2686 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2687 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2688 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2689 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2690 env->hreset_excp_prefix = 0x00000000UL;
2691 env->ivor_mask = 0x0000FFF0UL;
2692 env->ivpr_mask = 0xFFFF0000UL;
2693 /* Hardware reset vector */
2694 env->hreset_vector = 0xFFFFFFFCUL;
2695 #endif
2696 }
2697
2698 static void init_excp_4xx_softmmu (CPUPPCState *env)
2699 {
2700 #if !defined(CONFIG_USER_ONLY)
2701 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2702 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2703 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2704 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2705 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2706 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2707 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2708 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2709 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2710 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2711 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2712 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2713 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2714 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2715 env->hreset_excp_prefix = 0x00000000UL;
2716 env->ivor_mask = 0x0000FFF0UL;
2717 env->ivpr_mask = 0xFFFF0000UL;
2718 /* Hardware reset vector */
2719 env->hreset_vector = 0xFFFFFFFCUL;
2720 #endif
2721 }
2722
2723 static void init_excp_MPC5xx (CPUPPCState *env)
2724 {
2725 #if !defined(CONFIG_USER_ONLY)
2726 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2727 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2728 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2729 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2730 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2731 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2732 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2733 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2734 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2735 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2736 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2737 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2738 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2739 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2740 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2741 env->hreset_excp_prefix = 0x00000000UL;
2742 env->ivor_mask = 0x0000FFF0UL;
2743 env->ivpr_mask = 0xFFFF0000UL;
2744 /* Hardware reset vector */
2745 env->hreset_vector = 0xFFFFFFFCUL;
2746 #endif
2747 }
2748
2749 static void init_excp_MPC8xx (CPUPPCState *env)
2750 {
2751 #if !defined(CONFIG_USER_ONLY)
2752 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2753 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2754 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2755 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2756 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2757 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2758 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2759 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2760 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2761 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2762 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2763 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2764 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2765 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2766 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2767 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2768 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2769 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2770 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2771 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2772 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2773 env->hreset_excp_prefix = 0x00000000UL;
2774 env->ivor_mask = 0x0000FFF0UL;
2775 env->ivpr_mask = 0xFFFF0000UL;
2776 /* Hardware reset vector */
2777 env->hreset_vector = 0xFFFFFFFCUL;
2778 #endif
2779 }
2780
2781 static void init_excp_G2 (CPUPPCState *env)
2782 {
2783 #if !defined(CONFIG_USER_ONLY)
2784 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2785 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2786 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2787 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2788 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2789 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2790 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2791 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2792 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2793 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2794 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2795 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2796 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2797 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2798 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2799 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2800 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2801 env->hreset_excp_prefix = 0x00000000UL;
2802 /* Hardware reset vector */
2803 env->hreset_vector = 0xFFFFFFFCUL;
2804 #endif
2805 }
2806
2807 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2808 {
2809 #if !defined(CONFIG_USER_ONLY)
2810 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2811 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2812 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2813 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2814 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2815 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2816 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2817 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2818 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2819 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2820 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2821 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2822 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2823 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2824 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2825 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2826 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2827 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2828 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2829 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2830 env->hreset_excp_prefix = 0x00000000UL;
2831 env->ivor_mask = 0x0000FFF7UL;
2832 env->ivpr_mask = ivpr_mask;
2833 /* Hardware reset vector */
2834 env->hreset_vector = 0xFFFFFFFCUL;
2835 #endif
2836 }
2837
2838 static void init_excp_BookE (CPUPPCState *env)
2839 {
2840 #if !defined(CONFIG_USER_ONLY)
2841 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2842 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2843 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2844 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2845 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2846 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2847 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2848 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2849 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2850 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2851 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2852 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2853 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2854 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2855 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2856 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2857 env->hreset_excp_prefix = 0x00000000UL;
2858 env->ivor_mask = 0x0000FFE0UL;
2859 env->ivpr_mask = 0xFFFF0000UL;
2860 /* Hardware reset vector */
2861 env->hreset_vector = 0xFFFFFFFCUL;
2862 #endif
2863 }
2864
2865 static void init_excp_601 (CPUPPCState *env)
2866 {
2867 #if !defined(CONFIG_USER_ONLY)
2868 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2869 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2870 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2871 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2872 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2873 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2874 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2875 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2876 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2877 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2878 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2879 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2880 env->hreset_excp_prefix = 0xFFF00000UL;
2881 /* Hardware reset vector */
2882 env->hreset_vector = 0x00000100UL;
2883 #endif
2884 }
2885
2886 static void init_excp_602 (CPUPPCState *env)
2887 {
2888 #if !defined(CONFIG_USER_ONLY)
2889 /* XXX: exception prefix has a special behavior on 602 */
2890 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2891 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2892 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2893 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2894 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2895 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2896 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2897 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2898 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2899 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2900 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2901 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2902 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2903 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2904 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2905 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2906 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2907 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2908 env->hreset_excp_prefix = 0xFFF00000UL;
2909 /* Hardware reset vector */
2910 env->hreset_vector = 0xFFFFFFFCUL;
2911 #endif
2912 }
2913
2914 static void init_excp_603 (CPUPPCState *env)
2915 {
2916 #if !defined(CONFIG_USER_ONLY)
2917 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2918 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2919 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2920 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2921 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2922 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2923 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2924 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2925 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2926 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2927 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2928 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2929 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2930 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2931 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2932 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2933 env->hreset_excp_prefix = 0x00000000UL;
2934 /* Hardware reset vector */
2935 env->hreset_vector = 0xFFFFFFFCUL;
2936 #endif
2937 }
2938
2939 static void init_excp_604 (CPUPPCState *env)
2940 {
2941 #if !defined(CONFIG_USER_ONLY)
2942 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2943 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2944 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2945 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2946 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2947 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2948 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2949 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2950 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2951 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2952 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2953 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2954 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2955 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2956 env->hreset_excp_prefix = 0xFFF00000UL;
2957 /* Hardware reset vector */
2958 env->hreset_vector = 0x00000100UL;
2959 #endif
2960 }
2961
2962 #if defined(TARGET_PPC64)
2963 static void init_excp_620 (CPUPPCState *env)
2964 {
2965 #if !defined(CONFIG_USER_ONLY)
2966 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2967 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2968 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2969 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2970 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2971 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2972 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2973 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2974 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2975 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2976 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2977 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2978 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2979 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2980 env->hreset_excp_prefix = 0xFFF00000UL;
2981 /* Hardware reset vector */
2982 env->hreset_vector = 0x0000000000000100ULL;
2983 #endif
2984 }
2985 #endif /* defined(TARGET_PPC64) */
2986
2987 static void init_excp_7x0 (CPUPPCState *env)
2988 {
2989 #if !defined(CONFIG_USER_ONLY)
2990 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2991 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2992 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2993 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2994 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2995 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2996 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2997 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2998 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2999 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3000 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3001 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3002 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3003 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3004 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3005 env->hreset_excp_prefix = 0x00000000UL;
3006 /* Hardware reset vector */
3007 env->hreset_vector = 0xFFFFFFFCUL;
3008 #endif
3009 }
3010
3011 static void init_excp_750cl (CPUPPCState *env)
3012 {
3013 #if !defined(CONFIG_USER_ONLY)
3014 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3015 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3016 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3017 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3018 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3019 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3020 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3021 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3022 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3023 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3024 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3025 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3026 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3027 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3028 env->hreset_excp_prefix = 0x00000000UL;
3029 /* Hardware reset vector */
3030 env->hreset_vector = 0xFFFFFFFCUL;
3031 #endif
3032 }
3033
3034 static void init_excp_750cx (CPUPPCState *env)
3035 {
3036 #if !defined(CONFIG_USER_ONLY)
3037 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3038 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3039 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3040 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3041 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3042 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3043 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3044 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3045 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3046 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3047 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3048 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3049 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3050 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3051 env->hreset_excp_prefix = 0x00000000UL;
3052 /* Hardware reset vector */
3053 env->hreset_vector = 0xFFFFFFFCUL;
3054 #endif
3055 }
3056
3057 /* XXX: Check if this is correct */
3058 static void init_excp_7x5 (CPUPPCState *env)
3059 {
3060 #if !defined(CONFIG_USER_ONLY)
3061 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3062 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3063 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3064 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3065 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3066 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3067 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3068 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3069 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3070 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3071 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3072 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3073 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3074 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3075 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3076 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3077 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3078 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3079 env->hreset_excp_prefix = 0x00000000UL;
3080 /* Hardware reset vector */
3081 env->hreset_vector = 0xFFFFFFFCUL;
3082 #endif
3083 }
3084
3085 static void init_excp_7400 (CPUPPCState *env)
3086 {
3087 #if !defined(CONFIG_USER_ONLY)
3088 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3089 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3090 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3091 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3092 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3093 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3094 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3095 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3096 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3097 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3098 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3099 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3100 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3101 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3102 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3103 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3104 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3105 env->hreset_excp_prefix = 0x00000000UL;
3106 /* Hardware reset vector */
3107 env->hreset_vector = 0xFFFFFFFCUL;
3108 #endif
3109 }
3110
3111 static void init_excp_7450 (CPUPPCState *env)
3112 {
3113 #if !defined(CONFIG_USER_ONLY)
3114 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3115 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3116 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3117 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3118 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3119 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3120 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3121 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3122 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3123 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3124 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3125 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3126 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3127 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3128 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3129 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3130 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3131 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3132 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3133 env->hreset_excp_prefix = 0x00000000UL;
3134 /* Hardware reset vector */
3135 env->hreset_vector = 0xFFFFFFFCUL;
3136 #endif
3137 }
3138
3139 #if defined (TARGET_PPC64)
3140 static void init_excp_970 (CPUPPCState *env)
3141 {
3142 #if !defined(CONFIG_USER_ONLY)
3143 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3144 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3145 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3146 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3147 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3148 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3149 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3150 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3151 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3152 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3153 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3154 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3155 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3156 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3157 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3158 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3159 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3160 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3161 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3162 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3163 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
3164 /* Hardware reset vector */
3165 env->hreset_vector = 0x0000000000000100ULL;
3166 #endif
3167 }
3168
3169 static void init_excp_POWER7 (CPUPPCState *env)
3170 {
3171 #if !defined(CONFIG_USER_ONLY)
3172 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3173 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3174 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3175 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3176 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3177 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3178 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3179 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3180 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3181 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3182 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3183 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3184 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3185 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3186 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3187 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3188 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3189 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3190 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3191 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3192 env->hreset_excp_prefix = 0;
3193 /* Hardware reset vector */
3194 env->hreset_vector = 0x0000000000000100ULL;
3195 #endif
3196 }
3197 #endif
3198
3199 /*****************************************************************************/
3200 /* Power management enable checks */
3201 static int check_pow_none (CPUPPCState *env)
3202 {
3203 return 0;
3204 }
3205
3206 static int check_pow_nocheck (CPUPPCState *env)
3207 {
3208 return 1;
3209 }
3210
3211 static int check_pow_hid0 (CPUPPCState *env)
3212 {
3213 if (env->spr[SPR_HID0] & 0x00E00000)
3214 return 1;
3215
3216 return 0;
3217 }
3218
3219 static int check_pow_hid0_74xx (CPUPPCState *env)
3220 {
3221 if (env->spr[SPR_HID0] & 0x00600000)
3222 return 1;
3223
3224 return 0;
3225 }
3226
3227 /*****************************************************************************/
3228 /* PowerPC implementations definitions */
3229
3230 /* PowerPC 401 */
3231 #define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3232 PPC_WRTEE | PPC_DCR | \
3233 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3234 PPC_CACHE_DCBZ | \
3235 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3236 PPC_4xx_COMMON | PPC_40x_EXCP)
3237 #define POWERPC_INSNS2_401 (PPC_NONE)
3238 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
3239 #define POWERPC_MMU_401 (POWERPC_MMU_REAL)
3240 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3241 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
3242 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
3243 #define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3244 POWERPC_FLAG_BUS_CLK)
3245 #define check_pow_401 check_pow_nocheck
3246
3247 static void init_proc_401 (CPUPPCState *env)
3248 {
3249 gen_spr_40x(env);
3250 gen_spr_401_403(env);
3251 gen_spr_401(env);
3252 init_excp_4xx_real(env);
3253 env->dcache_line_size = 32;
3254 env->icache_line_size = 32;
3255 /* Allocate hardware IRQ controller */
3256 ppc40x_irq_init(env);
3257
3258 SET_FIT_PERIOD(12, 16, 20, 24);
3259 SET_WDT_PERIOD(16, 20, 24, 28);
3260 }
3261
3262 /* PowerPC 401x2 */
3263 #define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3264 PPC_DCR | PPC_WRTEE | \
3265 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3266 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3267 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3268 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3269 PPC_4xx_COMMON | PPC_40x_EXCP)
3270 #define POWERPC_INSNS2_401x2 (PPC_NONE)
3271 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3272 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3273 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3274 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
3275 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
3276 #define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3277 POWERPC_FLAG_BUS_CLK)
3278 #define check_pow_401x2 check_pow_nocheck
3279
3280 static void init_proc_401x2 (CPUPPCState *env)
3281 {
3282 gen_spr_40x(env);
3283 gen_spr_401_403(env);
3284 gen_spr_401x2(env);
3285 gen_spr_compress(env);
3286 /* Memory management */
3287 #if !defined(CONFIG_USER_ONLY)
3288 env->nb_tlb = 64;
3289 env->nb_ways = 1;
3290 env->id_tlbs = 0;
3291 env->tlb_type = TLB_EMB;
3292 #endif
3293 init_excp_4xx_softmmu(env);
3294 env->dcache_line_size = 32;
3295 env->icache_line_size = 32;
3296 /* Allocate hardware IRQ controller */
3297 ppc40x_irq_init(env);
3298
3299 SET_FIT_PERIOD(12, 16, 20, 24);
3300 SET_WDT_PERIOD(16, 20, 24, 28);
3301 }
3302
3303 /* PowerPC 401x3 */
3304 #define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3305 PPC_DCR | PPC_WRTEE | \
3306 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3307 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3308 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3309 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3310 PPC_4xx_COMMON | PPC_40x_EXCP)
3311 #define POWERPC_INSNS2_401x3 (PPC_NONE)
3312 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3313 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3314 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3315 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
3316 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
3317 #define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3318 POWERPC_FLAG_BUS_CLK)
3319 #define check_pow_401x3 check_pow_nocheck
3320
3321 __attribute__ (( unused ))
3322 static void init_proc_401x3 (CPUPPCState *env)
3323 {
3324 gen_spr_40x(env);
3325 gen_spr_401_403(env);
3326 gen_spr_401(env);
3327 gen_spr_401x2(env);
3328 gen_spr_compress(env);
3329 init_excp_4xx_softmmu(env);
3330 env->dcache_line_size = 32;
3331 env->icache_line_size = 32;
3332 /* Allocate hardware IRQ controller */
3333 ppc40x_irq_init(env);
3334
3335 SET_FIT_PERIOD(12, 16, 20, 24);
3336 SET_WDT_PERIOD(16, 20, 24, 28);
3337 }
3338
3339 /* IOP480 */
3340 #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3341 PPC_DCR | PPC_WRTEE | \
3342 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3343 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3344 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3345 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3346 PPC_4xx_COMMON | PPC_40x_EXCP)
3347 #define POWERPC_INSNS2_IOP480 (PPC_NONE)
3348 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3349 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3350 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3351 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
3352 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
3353 #define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3354 POWERPC_FLAG_BUS_CLK)
3355 #define check_pow_IOP480 check_pow_nocheck
3356
3357 static void init_proc_IOP480 (CPUPPCState *env)
3358 {
3359 gen_spr_40x(env);
3360 gen_spr_401_403(env);
3361 gen_spr_401x2(env);
3362 gen_spr_compress(env);
3363 /* Memory management */
3364 #if !defined(CONFIG_USER_ONLY)
3365 env->nb_tlb = 64;
3366 env->nb_ways = 1;
3367 env->id_tlbs = 0;
3368 env->tlb_type = TLB_EMB;
3369 #endif
3370 init_excp_4xx_softmmu(env);
3371 env->dcache_line_size = 32;
3372 env->icache_line_size = 32;
3373 /* Allocate hardware IRQ controller */
3374 ppc40x_irq_init(env);
3375
3376 SET_FIT_PERIOD(8, 12, 16, 20);
3377 SET_WDT_PERIOD(16, 20, 24, 28);
3378 }
3379
3380 /* PowerPC 403 */
3381 #define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3382 PPC_DCR | PPC_WRTEE | \
3383 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3384 PPC_CACHE_DCBZ | \
3385 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3386 PPC_4xx_COMMON | PPC_40x_EXCP)
3387 #define POWERPC_INSNS2_403 (PPC_NONE)
3388 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
3389 #define POWERPC_MMU_403 (POWERPC_MMU_REAL)
3390 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3391 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
3392 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
3393 #define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3394 POWERPC_FLAG_BUS_CLK)
3395 #define check_pow_403 check_pow_nocheck
3396
3397 static void init_proc_403 (CPUPPCState *env)
3398 {
3399 gen_spr_40x(env);
3400 gen_spr_401_403(env);
3401 gen_spr_403(env);
3402 gen_spr_403_real(env);
3403 init_excp_4xx_real(env);
3404 env->dcache_line_size = 32;
3405 env->icache_line_size = 32;
3406 /* Allocate hardware IRQ controller */
3407 ppc40x_irq_init(env);
3408
3409 SET_FIT_PERIOD(8, 12, 16, 20);
3410 SET_WDT_PERIOD(16, 20, 24, 28);
3411 }
3412
3413 /* PowerPC 403 GCX */
3414 #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3415 PPC_DCR | PPC_WRTEE | \
3416 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3417 PPC_CACHE_DCBZ | \
3418 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3419 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3420 PPC_4xx_COMMON | PPC_40x_EXCP)
3421 #define POWERPC_INSNS2_403GCX (PPC_NONE)
3422 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3423 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3424 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3425 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
3426 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
3427 #define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3428 POWERPC_FLAG_BUS_CLK)
3429 #define check_pow_403GCX check_pow_nocheck
3430
3431 static void init_proc_403GCX (CPUPPCState *env)
3432 {
3433 gen_spr_40x(env);
3434 gen_spr_401_403(env);
3435 gen_spr_403(env);
3436 gen_spr_403_real(env);
3437 gen_spr_403_mmu(env);
3438 /* Bus access control */
3439 /* not emulated, as QEMU never does speculative access */
3440 spr_register(env, SPR_40x_SGR, "SGR",
3441 SPR_NOACCESS, SPR_NOACCESS,
3442 &spr_read_generic, &spr_write_generic,
3443 0xFFFFFFFF);
3444 /* not emulated, as QEMU do not emulate caches */
3445 spr_register(env, SPR_40x_DCWR, "DCWR",
3446 SPR_NOACCESS, SPR_NOACCESS,
3447 &spr_read_generic, &spr_write_generic,
3448 0x00000000);
3449 /* Memory management */
3450 #if !defined(CONFIG_USER_ONLY)
3451 env->nb_tlb = 64;
3452 env->nb_ways = 1;
3453 env->id_tlbs = 0;
3454 env->tlb_type = TLB_EMB;
3455 #endif
3456 init_excp_4xx_softmmu(env);
3457 env->dcache_line_size = 32;
3458 env->icache_line_size = 32;
3459 /* Allocate hardware IRQ controller */
3460 ppc40x_irq_init(env);
3461
3462 SET_FIT_PERIOD(8, 12, 16, 20);
3463 SET_WDT_PERIOD(16, 20, 24, 28);
3464 }
3465
3466 /* PowerPC 405 */
3467 #define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3468 PPC_DCR | PPC_WRTEE | \
3469 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3470 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3471 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3472 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3473 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3474 #define POWERPC_INSNS2_405 (PPC_NONE)
3475 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
3476 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3477 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3478 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3479 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3480 #define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3481 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3482 #define check_pow_405 check_pow_nocheck
3483
3484 static void init_proc_405 (CPUPPCState *env)
3485 {
3486 /* Time base */
3487 gen_tbl(env);
3488 gen_spr_40x(env);
3489 gen_spr_405(env);
3490 /* Bus access control */
3491 /* not emulated, as QEMU never does speculative access */
3492 spr_register(env, SPR_40x_SGR, "SGR",
3493 SPR_NOACCESS, SPR_NOACCESS,
3494 &spr_read_generic, &spr_write_generic,
3495 0xFFFFFFFF);
3496 /* not emulated, as QEMU do not emulate caches */
3497 spr_register(env, SPR_40x_DCWR, "DCWR",
3498 SPR_NOACCESS, SPR_NOACCESS,
3499 &spr_read_generic, &spr_write_generic,
3500 0x00000000);
3501 /* Memory management */
3502 #if !defined(CONFIG_USER_ONLY)
3503 env->nb_tlb = 64;
3504 env->nb_ways = 1;
3505 env->id_tlbs = 0;
3506 env->tlb_type = TLB_EMB;
3507 #endif
3508 init_excp_4xx_softmmu(env);
3509 env->dcache_line_size = 32;
3510 env->icache_line_size = 32;
3511 /* Allocate hardware IRQ controller */
3512 ppc40x_irq_init(env);
3513
3514 SET_FIT_PERIOD(8, 12, 16, 20);
3515 SET_WDT_PERIOD(16, 20, 24, 28);
3516 }
3517
3518 /* PowerPC 440 EP */
3519 #define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3520 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3521 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3522 PPC_FLOAT_STFIWX | \
3523 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3524 PPC_CACHE | PPC_CACHE_ICBI | \
3525 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3526 PPC_MEM_TLBSYNC | PPC_MFTB | \
3527 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3528 PPC_440_SPEC)
3529 #define POWERPC_INSNS2_440EP (PPC_NONE)
3530 #define POWERPC_MSRM_440EP (0x000000000006FF30ULL)
3531 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3532 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3533 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3534 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3535 #define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3536 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3537 #define check_pow_440EP check_pow_nocheck
3538
3539 static void init_proc_440EP (CPUPPCState *env)
3540 {
3541 /* Time base */
3542 gen_tbl(env);
3543 gen_spr_BookE(env, 0x000000000000FFFFULL);
3544 gen_spr_440(env);
3545 gen_spr_usprgh(env);
3546 /* Processor identification */
3547 spr_register(env, SPR_BOOKE_PIR, "PIR",
3548 SPR_NOACCESS, SPR_NOACCESS,
3549 &spr_read_generic, &spr_write_pir,
3550 0x00000000);
3551 /* XXX : not implemented */
3552 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3553 SPR_NOACCESS, SPR_NOACCESS,
3554 &spr_read_generic, &spr_write_generic,
3555 0x00000000);
3556 /* XXX : not implemented */
3557 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3558 SPR_NOACCESS, SPR_NOACCESS,
3559 &spr_read_generic, &spr_write_generic,
3560 0x00000000);
3561 /* XXX : not implemented */
3562 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3563 SPR_NOACCESS, SPR_NOACCESS,
3564 &spr_read_generic, &spr_write_generic,
3565 0x00000000);
3566 /* XXX : not implemented */
3567 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3568 SPR_NOACCESS, SPR_NOACCESS,
3569 &spr_read_generic, &spr_write_generic,
3570 0x00000000);
3571 /* XXX : not implemented */
3572 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3573 SPR_NOACCESS, SPR_NOACCESS,
3574 &spr_read_generic, &spr_write_generic,
3575 0x00000000);
3576 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3577 SPR_NOACCESS, SPR_NOACCESS,
3578 &spr_read_generic, &spr_write_generic,
3579 0x00000000);
3580 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3581 SPR_NOACCESS, SPR_NOACCESS,
3582 &spr_read_generic, &spr_write_generic,
3583 0x00000000);
3584 /* XXX : not implemented */
3585 spr_register(env, SPR_440_CCR1, "CCR1",
3586 SPR_NOACCESS, SPR_NOACCESS,
3587 &spr_read_generic, &spr_write_generic,
3588 0x00000000);
3589 /* Memory management */
3590 #if !defined(CONFIG_USER_ONLY)
3591 env->nb_tlb = 64;
3592 env->nb_ways = 1;
3593 env->id_tlbs = 0;
3594 env->tlb_type = TLB_EMB;
3595 #endif
3596 init_excp_BookE(env);
3597 env->dcache_line_size = 32;
3598 env->icache_line_size = 32;
3599 ppc40x_irq_init(env);
3600
3601 SET_FIT_PERIOD(12, 16, 20, 24);
3602 SET_WDT_PERIOD(20, 24, 28, 32);
3603 }
3604
3605 /* PowerPC 440 GP */
3606 #define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3607 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3608 PPC_CACHE | PPC_CACHE_ICBI | \
3609 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3610 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \
3611 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3612 PPC_440_SPEC)
3613 #define POWERPC_INSNS2_440GP (PPC_NONE)
3614 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3615 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3616 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3617 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3618 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3619 #define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3620 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3621 #define check_pow_440GP check_pow_nocheck
3622
3623 __attribute__ (( unused ))
3624 static void init_proc_440GP (CPUPPCState *env)
3625 {
3626 /* Time base */
3627 gen_tbl(env);
3628 gen_spr_BookE(env, 0x000000000000FFFFULL);
3629 gen_spr_440(env);
3630 gen_spr_usprgh(env);
3631 /* Processor identification */
3632 spr_register(env, SPR_BOOKE_PIR, "PIR",
3633 SPR_NOACCESS, SPR_NOACCESS,
3634 &spr_read_generic, &spr_write_pir,
3635 0x00000000);
3636 /* XXX : not implemented */
3637 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3638 SPR_NOACCESS, SPR_NOACCESS,
3639 &spr_read_generic, &spr_write_generic,
3640 0x00000000);
3641 /* XXX : not implemented */
3642 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3643 SPR_NOACCESS, SPR_NOACCESS,
3644 &spr_read_generic, &spr_write_generic,
3645 0x00000000);
3646 /* XXX : not implemented */
3647 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3648 SPR_NOACCESS, SPR_NOACCESS,
3649 &spr_read_generic, &spr_write_generic,
3650 0x00000000);
3651 /* XXX : not implemented */
3652 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3653 SPR_NOACCESS, SPR_NOACCESS,
3654 &spr_read_generic, &spr_write_generic,
3655 0x00000000);
3656 /* Memory management */
3657 #if !defined(CONFIG_USER_ONLY)
3658 env->nb_tlb = 64;
3659 env->nb_ways = 1;
3660 env->id_tlbs = 0;
3661 env->tlb_type = TLB_EMB;
3662 #endif
3663 init_excp_BookE(env);
3664 env->dcache_line_size = 32;
3665 env->icache_line_size = 32;
3666 /* XXX: TODO: allocate internal IRQ controller */
3667
3668 SET_FIT_PERIOD(12, 16, 20, 24);
3669 SET_WDT_PERIOD(20, 24, 28, 32);
3670 }
3671
3672 /* PowerPC 440x4 */
3673 #define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3674 PPC_DCR | PPC_WRTEE | \
3675 PPC_CACHE | PPC_CACHE_ICBI | \
3676 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3677 PPC_MEM_TLBSYNC | PPC_MFTB | \
3678 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3679 PPC_440_SPEC)
3680 #define POWERPC_INSNS2_440x4 (PPC_NONE)
3681 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3682 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3683 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3684 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3685 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3686 #define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3687 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3688 #define check_pow_440x4 check_pow_nocheck
3689
3690 __attribute__ (( unused ))
3691 static void init_proc_440x4 (CPUPPCState *env)
3692 {
3693 /* Time base */
3694 gen_tbl(env);
3695 gen_spr_BookE(env, 0x000000000000FFFFULL);
3696 gen_spr_440(env);
3697 gen_spr_usprgh(env);
3698 /* Processor identification */
3699 spr_register(env, SPR_BOOKE_PIR, "PIR",
3700 SPR_NOACCESS, SPR_NOACCESS,
3701 &spr_read_generic, &spr_write_pir,
3702 0x00000000);
3703 /* XXX : not implemented */
3704 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3705 SPR_NOACCESS, SPR_NOACCESS,
3706 &spr_read_generic, &spr_write_generic,
3707 0x00000000);
3708 /* XXX : not implemented */
3709 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3710 SPR_NOACCESS, SPR_NOACCESS,
3711 &spr_read_generic, &spr_write_generic,
3712 0x00000000);
3713 /* XXX : not implemented */
3714 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3715 SPR_NOACCESS, SPR_NOACCESS,
3716 &spr_read_generic, &spr_write_generic,
3717 0x00000000);
3718 /* XXX : not implemented */
3719 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3720 SPR_NOACCESS, SPR_NOACCESS,
3721 &spr_read_generic, &spr_write_generic,
3722 0x00000000);
3723 /* Memory management */
3724 #if !defined(CONFIG_USER_ONLY)
3725 env->nb_tlb = 64;
3726 env->nb_ways = 1;
3727 env->id_tlbs = 0;
3728 env->tlb_type = TLB_EMB;
3729 #endif
3730 init_excp_BookE(env);
3731 env->dcache_line_size = 32;
3732 env->icache_line_size = 32;
3733 /* XXX: TODO: allocate internal IRQ controller */
3734
3735 SET_FIT_PERIOD(12, 16, 20, 24);
3736 SET_WDT_PERIOD(20, 24, 28, 32);
3737 }
3738
3739 /* PowerPC 440x5 */
3740 #define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3741 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3742 PPC_CACHE | PPC_CACHE_ICBI | \
3743 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3744 PPC_MEM_TLBSYNC | PPC_MFTB | \
3745 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3746 PPC_440_SPEC)
3747 #define POWERPC_INSNS2_440x5 (PPC_NONE)
3748 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3749 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3750 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3751 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3752 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3753 #define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3754 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3755 #define check_pow_440x5 check_pow_nocheck
3756
3757 static void init_proc_440x5 (CPUPPCState *env)
3758 {
3759 /* Time base */
3760 gen_tbl(env);
3761 gen_spr_BookE(env, 0x000000000000FFFFULL);
3762 gen_spr_440(env);
3763 gen_spr_usprgh(env);
3764 /* Processor identification */
3765 spr_register(env, SPR_BOOKE_PIR, "PIR",
3766 SPR_NOACCESS, SPR_NOACCESS,
3767 &spr_read_generic, &spr_write_pir,
3768 0x00000000);
3769 /* XXX : not implemented */
3770 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3771 SPR_NOACCESS, SPR_NOACCESS,
3772 &spr_read_generic, &spr_write_generic,
3773 0x00000000);
3774 /* XXX : not implemented */
3775 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3776 SPR_NOACCESS, SPR_NOACCESS,
3777 &spr_read_generic, &spr_write_generic,
3778 0x00000000);
3779 /* XXX : not implemented */
3780 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3781 SPR_NOACCESS, SPR_NOACCESS,
3782 &spr_read_generic, &spr_write_generic,
3783 0x00000000);
3784 /* XXX : not implemented */
3785 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3786 SPR_NOACCESS, SPR_NOACCESS,
3787 &spr_read_generic, &spr_write_generic,
3788 0x00000000);
3789 /* XXX : not implemented */
3790 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3791 SPR_NOACCESS, SPR_NOACCESS,
3792 &spr_read_generic, &spr_write_generic,
3793 0x00000000);
3794 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3795 SPR_NOACCESS, SPR_NOACCESS,
3796 &spr_read_generic, &spr_write_generic,
3797 0x00000000);
3798 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3799 SPR_NOACCESS, SPR_NOACCESS,
3800 &spr_read_generic, &spr_write_generic,
3801 0x00000000);
3802 /* XXX : not implemented */
3803 spr_register(env, SPR_440_CCR1, "CCR1",
3804 SPR_NOACCESS, SPR_NOACCESS,
3805 &spr_read_generic, &spr_write_generic,
3806 0x00000000);
3807 /* Memory management */
3808 #if !defined(CONFIG_USER_ONLY)
3809 env->nb_tlb = 64;
3810 env->nb_ways = 1;
3811 env->id_tlbs = 0;
3812 env->tlb_type = TLB_EMB;
3813 #endif
3814 init_excp_BookE(env);
3815 env->dcache_line_size = 32;
3816 env->icache_line_size = 32;
3817 ppc40x_irq_init(env);
3818
3819 SET_FIT_PERIOD(12, 16, 20, 24);
3820 SET_WDT_PERIOD(20, 24, 28, 32);
3821 }
3822
3823 /* PowerPC 460 (guessed) */
3824 #define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
3825 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3826 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | \
3827 PPC_CACHE | PPC_CACHE_ICBI | \
3828 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3829 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3830 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3831 PPC_440_SPEC)
3832 #define POWERPC_INSNS2_460 (PPC_NONE)
3833 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3834 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3835 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3836 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3837 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3838 #define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3839 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3840 #define check_pow_460 check_pow_nocheck
3841
3842 __attribute__ (( unused ))
3843 static void init_proc_460 (CPUPPCState *env)
3844 {
3845 /* Time base */
3846 gen_tbl(env);
3847 gen_spr_BookE(env, 0x000000000000FFFFULL);
3848 gen_spr_440(env);
3849 gen_spr_usprgh(env);
3850 /* Processor identification */
3851 spr_register(env, SPR_BOOKE_PIR, "PIR",
3852 SPR_NOACCESS, SPR_NOACCESS,
3853 &spr_read_generic, &spr_write_pir,
3854 0x00000000);
3855 /* XXX : not implemented */
3856 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3857 SPR_NOACCESS, SPR_NOACCESS,
3858 &spr_read_generic, &spr_write_generic,
3859 0x00000000);
3860 /* XXX : not implemented */
3861 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3862 SPR_NOACCESS, SPR_NOACCESS,
3863 &spr_read_generic, &spr_write_generic,
3864 0x00000000);
3865 /* XXX : not implemented */
3866 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3867 SPR_NOACCESS, SPR_NOACCESS,
3868 &spr_read_generic, &spr_write_generic,
3869 0x00000000);
3870 /* XXX : not implemented */
3871 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3872 SPR_NOACCESS, SPR_NOACCESS,
3873 &spr_read_generic, &spr_write_generic,
3874 0x00000000);
3875 /* XXX : not implemented */
3876 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3877 SPR_NOACCESS, SPR_NOACCESS,
3878 &spr_read_generic, &spr_write_generic,
3879 0x00000000);
3880 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3881 SPR_NOACCESS, SPR_NOACCESS,
3882 &spr_read_generic, &spr_write_generic,
3883 0x00000000);
3884 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3885 SPR_NOACCESS, SPR_NOACCESS,
3886 &spr_read_generic, &spr_write_generic,
3887 0x00000000);
3888 /* XXX : not implemented */
3889 spr_register(env, SPR_440_CCR1, "CCR1",
3890 SPR_NOACCESS, SPR_NOACCESS,
3891 &spr_read_generic, &spr_write_generic,
3892 0x00000000);
3893 /* XXX : not implemented */
3894 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3895 &spr_read_generic, &spr_write_generic,
3896 &spr_read_generic, &spr_write_generic,
3897 0x00000000);
3898 /* Memory management */
3899 #if !defined(CONFIG_USER_ONLY)
3900 env->nb_tlb = 64;
3901 env->nb_ways = 1;
3902 env->id_tlbs = 0;
3903 env->tlb_type = TLB_EMB;
3904 #endif
3905 init_excp_BookE(env);
3906 env->dcache_line_size = 32;
3907 env->icache_line_size = 32;
3908 /* XXX: TODO: allocate internal IRQ controller */
3909
3910 SET_FIT_PERIOD(12, 16, 20, 24);
3911 SET_WDT_PERIOD(20, 24, 28, 32);
3912 }
3913
3914 /* PowerPC 460F (guessed) */
3915 #define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3916 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3917 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3918 PPC_FLOAT_STFIWX | PPC_MFTB | \
3919 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3920 PPC_WRTEE | PPC_MFAPIDI | \
3921 PPC_CACHE | PPC_CACHE_ICBI | \
3922 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3923 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3924 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3925 PPC_440_SPEC)
3926 #define POWERPC_INSNS2_460F (PPC_NONE)
3927 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3928 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3929 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3930 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3931 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3932 #define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3933 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3934 #define check_pow_460F check_pow_nocheck
3935
3936 __attribute__ (( unused ))
3937 static void init_proc_460F (CPUPPCState *env)
3938 {
3939 /* Time base */
3940 gen_tbl(env);
3941 gen_spr_BookE(env, 0x000000000000FFFFULL);
3942 gen_spr_440(env);
3943 gen_spr_usprgh(env);
3944 /* Processor identification */
3945 spr_register(env, SPR_BOOKE_PIR, "PIR",
3946 SPR_NOACCESS, SPR_NOACCESS,
3947 &spr_read_generic, &spr_write_pir,
3948 0x00000000);
3949 /* XXX : not implemented */
3950 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3951 SPR_NOACCESS, SPR_NOACCESS,
3952 &spr_read_generic, &spr_write_generic,
3953 0x00000000);
3954 /* XXX : not implemented */
3955 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3956 SPR_NOACCESS, SPR_NOACCESS,
3957 &spr_read_generic, &spr_write_generic,
3958 0x00000000);
3959 /* XXX : not implemented */
3960 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3961 SPR_NOACCESS, SPR_NOACCESS,
3962 &spr_read_generic, &spr_write_generic,
3963 0x00000000);
3964 /* XXX : not implemented */
3965 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3966 SPR_NOACCESS, SPR_NOACCESS,
3967 &spr_read_generic, &spr_write_generic,
3968 0x00000000);
3969 /* XXX : not implemented */
3970 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3971 SPR_NOACCESS, SPR_NOACCESS,
3972 &spr_read_generic, &spr_write_generic,
3973 0x00000000);
3974 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3975 SPR_NOACCESS, SPR_NOACCESS,
3976 &spr_read_generic, &spr_write_generic,
3977 0x00000000);
3978 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3979 SPR_NOACCESS, SPR_NOACCESS,
3980 &spr_read_generic, &spr_write_generic,
3981 0x00000000);
3982 /* XXX : not implemented */
3983 spr_register(env, SPR_440_CCR1, "CCR1",
3984 SPR_NOACCESS, SPR_NOACCESS,
3985 &spr_read_generic, &spr_write_generic,
3986 0x00000000);
3987 /* XXX : not implemented */
3988 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3989 &spr_read_generic, &spr_write_generic,
3990 &spr_read_generic, &spr_write_generic,
3991 0x00000000);
3992 /* Memory management */
3993 #if !defined(CONFIG_USER_ONLY)
3994 env->nb_tlb = 64;
3995 env->nb_ways = 1;
3996 env->id_tlbs = 0;
3997 env->tlb_type = TLB_EMB;
3998 #endif
3999 init_excp_BookE(env);
4000 env->dcache_line_size = 32;
4001 env->icache_line_size = 32;
4002 /* XXX: TODO: allocate internal IRQ controller */
4003
4004 SET_FIT_PERIOD(12, 16, 20, 24);
4005 SET_WDT_PERIOD(20, 24, 28, 32);
4006 }
4007
4008 /* Freescale 5xx cores (aka RCPU) */
4009 #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
4010 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4011 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
4012 PPC_MFTB)
4013 #define POWERPC_INSNS2_MPC5xx (PPC_NONE)
4014 #define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
4015 #define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
4016 #define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
4017 #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
4018 #define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
4019 #define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4020 POWERPC_FLAG_BUS_CLK)
4021 #define check_pow_MPC5xx check_pow_none
4022
4023 __attribute__ (( unused ))
4024 static void init_proc_MPC5xx (CPUPPCState *env)
4025 {
4026 /* Time base */
4027 gen_tbl(env);
4028 gen_spr_5xx_8xx(env);
4029 gen_spr_5xx(env);
4030 init_excp_MPC5xx(env);
4031 env->dcache_line_size = 32;
4032 env->icache_line_size = 32;
4033 /* XXX: TODO: allocate internal IRQ controller */
4034 }
4035
4036 /* Freescale 8xx cores (aka PowerQUICC) */
4037 #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
4038 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4039 PPC_CACHE_ICBI | PPC_MFTB)
4040 #define POWERPC_INSNS2_MPC8xx (PPC_NONE)
4041 #define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
4042 #define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
4043 #define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
4044 #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
4045 #define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4046 #define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4047 POWERPC_FLAG_BUS_CLK)
4048 #define check_pow_MPC8xx check_pow_none
4049
4050 __attribute__ (( unused ))
4051 static void init_proc_MPC8xx (CPUPPCState *env)
4052 {
4053 /* Time base */
4054 gen_tbl(env);
4055 gen_spr_5xx_8xx(env);
4056 gen_spr_8xx(env);
4057 init_excp_MPC8xx(env);
4058 env->dcache_line_size = 32;
4059 env->icache_line_size = 32;
4060 /* XXX: TODO: allocate internal IRQ controller */
4061 }
4062
4063 /* Freescale 82xx cores (aka PowerQUICC-II) */
4064 /* PowerPC G2 */
4065 #define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4066 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4067 PPC_FLOAT_STFIWX | \
4068 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4069 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4070 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4071 PPC_SEGMENT | PPC_EXTERN)
4072 #define POWERPC_INSNS2_G2 (PPC_NONE)
4073 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
4074 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
4075 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
4076 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
4077 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
4078 #define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4079 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4080 #define check_pow_G2 check_pow_hid0
4081
4082 static void init_proc_G2 (CPUPPCState *env)
4083 {
4084 gen_spr_ne_601(env);
4085 gen_spr_G2_755(env);
4086 gen_spr_G2(env);
4087 /* Time base */
4088 gen_tbl(env);
4089 /* External access control */
4090 /* XXX : not implemented */
4091 spr_register(env, SPR_EAR, "EAR",
4092 SPR_NOACCESS, SPR_NOACCESS,
4093 &spr_read_generic, &spr_write_generic,
4094 0x00000000);
4095 /* Hardware implementation register */
4096 /* XXX : not implemented */
4097 spr_register(env, SPR_HID0, "HID0",
4098 SPR_NOACCESS, SPR_NOACCESS,
4099 &spr_read_generic, &spr_write_generic,
4100 0x00000000);
4101 /* XXX : not implemented */
4102 spr_register(env, SPR_HID1, "HID1",
4103 SPR_NOACCESS, SPR_NOACCESS,
4104 &spr_read_generic, &spr_write_generic,
4105 0x00000000);
4106 /* XXX : not implemented */
4107 spr_register(env, SPR_HID2, "HID2",
4108 SPR_NOACCESS, SPR_NOACCESS,
4109 &spr_read_generic, &spr_write_generic,
4110 0x00000000);
4111 /* Memory management */
4112 gen_low_BATs(env);
4113 gen_high_BATs(env);
4114 gen_6xx_7xx_soft_tlb(env, 64, 2);
4115 init_excp_G2(env);
4116 env->dcache_line_size = 32;
4117 env->icache_line_size = 32;
4118 /* Allocate hardware IRQ controller */
4119 ppc6xx_irq_init(env);
4120 }
4121
4122 /* PowerPC G2LE */
4123 #define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4124 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4125 PPC_FLOAT_STFIWX | \
4126 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4127 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4128 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4129 PPC_SEGMENT | PPC_EXTERN)
4130 #define POWERPC_INSNS2_G2LE (PPC_NONE)
4131 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
4132 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
4133 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
4134 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
4135 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
4136 #define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4137 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4138 #define check_pow_G2LE check_pow_hid0
4139
4140 static void init_proc_G2LE (CPUPPCState *env)
4141 {
4142 gen_spr_ne_601(env);
4143 gen_spr_G2_755(env);
4144 gen_spr_G2(env);
4145 /* Time base */
4146 gen_tbl(env);
4147 /* External access control */
4148 /* XXX : not implemented */
4149 spr_register(env, SPR_EAR, "EAR",
4150 SPR_NOACCESS, SPR_NOACCESS,
4151 &spr_read_generic, &spr_write_generic,
4152 0x00000000);
4153 /* Hardware implementation register */
4154 /* XXX : not implemented */
4155 spr_register(env, SPR_HID0, "HID0",
4156 SPR_NOACCESS, SPR_NOACCESS,
4157 &spr_read_generic, &spr_write_generic,
4158 0x00000000);
4159 /* XXX : not implemented */
4160 spr_register(env, SPR_HID1, "HID1",
4161 SPR_NOACCESS, SPR_NOACCESS,
4162 &spr_read_generic, &spr_write_generic,
4163 0x00000000);
4164 /* XXX : not implemented */
4165 spr_register(env, SPR_HID2, "HID2",
4166 SPR_NOACCESS, SPR_NOACCESS,
4167 &spr_read_generic, &spr_write_generic,
4168 0x00000000);
4169 /* Memory management */
4170 gen_low_BATs(env);
4171 gen_high_BATs(env);
4172 gen_6xx_7xx_soft_tlb(env, 64, 2);
4173 init_excp_G2(env);
4174 env->dcache_line_size = 32;
4175 env->icache_line_size = 32;
4176 /* Allocate hardware IRQ controller */
4177 ppc6xx_irq_init(env);
4178 }
4179
4180 /* e200 core */
4181 /* XXX: unimplemented instructions:
4182 * dcblc
4183 * dcbtlst
4184 * dcbtstls
4185 * icblc
4186 * icbtls
4187 * tlbivax
4188 * all SPE multiply-accumulate instructions
4189 */
4190 #define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
4191 PPC_SPE | PPC_SPE_SINGLE | \
4192 PPC_WRTEE | PPC_RFDI | \
4193 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4194 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4195 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4196 PPC_BOOKE)
4197 #define POWERPC_INSNS2_e200 (PPC_NONE)
4198 #define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
4199 #define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE206)
4200 #define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
4201 #define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
4202 #define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
4203 #define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4204 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4205 POWERPC_FLAG_BUS_CLK)
4206 #define check_pow_e200 check_pow_hid0
4207
4208 __attribute__ (( unused ))
4209 static void init_proc_e200 (CPUPPCState *env)
4210 {
4211 /* Time base */
4212 gen_tbl(env);
4213 gen_spr_BookE(env, 0x000000070000FFFFULL);
4214 /* XXX : not implemented */
4215 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4216 &spr_read_spefscr, &spr_write_spefscr,
4217 &spr_read_spefscr, &spr_write_spefscr,
4218 0x00000000);
4219 /* Memory management */
4220 gen_spr_BookE206(env, 0x0000005D, NULL);
4221 /* XXX : not implemented */
4222 spr_register(env, SPR_HID0, "HID0",
4223 SPR_NOACCESS, SPR_NOACCESS,
4224 &spr_read_generic, &spr_write_generic,
4225 0x00000000);
4226 /* XXX : not implemented */
4227 spr_register(env, SPR_HID1, "HID1",
4228 SPR_NOACCESS, SPR_NOACCESS,
4229 &spr_read_generic, &spr_write_generic,
4230 0x00000000);
4231 /* XXX : not implemented */
4232 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4233 SPR_NOACCESS, SPR_NOACCESS,
4234 &spr_read_generic, &spr_write_generic,
4235 0x00000000);
4236 /* XXX : not implemented */
4237 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4238 SPR_NOACCESS, SPR_NOACCESS,
4239 &spr_read_generic, &spr_write_generic,
4240 0x00000000);
4241 /* XXX : not implemented */
4242 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4243 SPR_NOACCESS, SPR_NOACCESS,
4244 &spr_read_generic, &spr_write_generic,
4245 0x00000000);
4246 /* XXX : not implemented */
4247 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4248 SPR_NOACCESS, SPR_NOACCESS,
4249 &spr_read_generic, &spr_write_generic,
4250 0x00000000);
4251 /* XXX : not implemented */
4252 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4253 SPR_NOACCESS, SPR_NOACCESS,
4254 &spr_read_generic, &spr_write_generic,
4255 0x00000000);
4256 /* XXX : not implemented */
4257 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4258 SPR_NOACCESS, SPR_NOACCESS,
4259 &spr_read_generic, &spr_write_generic,
4260 0x00000000);
4261 /* XXX : not implemented */
4262 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4263 SPR_NOACCESS, SPR_NOACCESS,
4264 &spr_read_generic, &spr_write_generic,
4265 0x00000000);
4266 /* XXX : not implemented */
4267 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4268 SPR_NOACCESS, SPR_NOACCESS,
4269 &spr_read_generic, &spr_write_generic,
4270 0x00000000);
4271 /* XXX : not implemented */
4272 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4273 SPR_NOACCESS, SPR_NOACCESS,
4274 &spr_read_generic, &spr_write_generic,
4275 0x00000000);
4276 /* XXX : not implemented */
4277 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4278 SPR_NOACCESS, SPR_NOACCESS,
4279 &spr_read_generic, &spr_write_generic,
4280 0x00000000);
4281 /* XXX : not implemented */
4282 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4283 SPR_NOACCESS, SPR_NOACCESS,
4284 &spr_read_generic, &spr_write_generic,
4285 0x00000000);
4286 /* XXX : not implemented */
4287 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4288 SPR_NOACCESS, SPR_NOACCESS,
4289 &spr_read_generic, &spr_write_generic,
4290 0x00000000);
4291 /* XXX : not implemented */
4292 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4293 SPR_NOACCESS, SPR_NOACCESS,
4294 &spr_read_generic, &spr_write_generic,
4295 0x00000000); /* TOFIX */
4296 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4297 SPR_NOACCESS, SPR_NOACCESS,
4298 &spr_read_generic, &spr_write_generic,
4299 0x00000000);
4300 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4301 SPR_NOACCESS, SPR_NOACCESS,
4302 &spr_read_generic, &spr_write_generic,
4303 0x00000000);
4304 #if !defined(CONFIG_USER_ONLY)
4305 env->nb_tlb = 64;
4306 env->nb_ways = 1;
4307 env->id_tlbs = 0;
4308 env->tlb_type = TLB_EMB;
4309 #endif
4310 init_excp_e200(env, 0xFFFF0000UL);
4311 env->dcache_line_size = 32;
4312 env->icache_line_size = 32;
4313 /* XXX: TODO: allocate internal IRQ controller */
4314 }
4315
4316 /* e300 core */
4317 #define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4318 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4319 PPC_FLOAT_STFIWX | \
4320 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4321 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4322 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4323 PPC_SEGMENT | PPC_EXTERN)
4324 #define POWERPC_INSNS2_e300 (PPC_NONE)
4325 #define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4326 #define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4327 #define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4328 #define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4329 #define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4330 #define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4331 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4332 #define check_pow_e300 check_pow_hid0
4333
4334 __attribute__ (( unused ))
4335 static void init_proc_e300 (CPUPPCState *env)
4336 {
4337 gen_spr_ne_601(env);
4338 gen_spr_603(env);
4339 /* Time base */
4340 gen_tbl(env);
4341 /* hardware implementation registers */
4342 /* XXX : not implemented */
4343 spr_register(env, SPR_HID0, "HID0",
4344 SPR_NOACCESS, SPR_NOACCESS,
4345 &spr_read_generic, &spr_write_generic,
4346 0x00000000);
4347 /* XXX : not implemented */
4348 spr_register(env, SPR_HID1, "HID1",
4349 SPR_NOACCESS, SPR_NOACCESS,
4350 &spr_read_generic, &spr_write_generic,
4351 0x00000000);
4352 /* XXX : not implemented */
4353 spr_register(env, SPR_HID2, "HID2",
4354 SPR_NOACCESS, SPR_NOACCESS,
4355 &spr_read_generic, &spr_write_generic,
4356 0x00000000);
4357 /* Memory management */
4358 gen_low_BATs(env);
4359 gen_high_BATs(env);
4360 gen_6xx_7xx_soft_tlb(env, 64, 2);
4361 init_excp_603(env);
4362 env->dcache_line_size = 32;
4363 env->icache_line_size = 32;
4364 /* Allocate hardware IRQ controller */
4365 ppc6xx_irq_init(env);
4366 }
4367
4368 /* e500v1 core */
4369 #define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
4370 PPC_SPE | PPC_SPE_SINGLE | \
4371 PPC_WRTEE | PPC_RFDI | \
4372 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4373 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4374 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
4375 #define POWERPC_INSNS2_e500v1 (PPC2_BOOKE206)
4376 #define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
4377 #define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206)
4378 #define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4379 #define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4380 #define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4381 #define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4382 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4383 POWERPC_FLAG_BUS_CLK)
4384 #define check_pow_e500v1 check_pow_hid0
4385 #define init_proc_e500v1 init_proc_e500v1
4386
4387 /* e500v2 core */
4388 #define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
4389 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
4390 PPC_WRTEE | PPC_RFDI | \
4391 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4392 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4393 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
4394 #define POWERPC_INSNS2_e500v2 (PPC2_BOOKE206)
4395 #define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
4396 #define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206)
4397 #define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4398 #define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4399 #define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4400 #define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4401 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4402 POWERPC_FLAG_BUS_CLK)
4403 #define check_pow_e500v2 check_pow_hid0
4404 #define init_proc_e500v2 init_proc_e500v2
4405
4406 /* e500mc core */
4407 #define POWERPC_INSNS_e500mc (PPC_INSNS_BASE | PPC_ISEL | \
4408 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | \
4409 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4410 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4411 PPC_FLOAT | PPC_FLOAT_FRES | \
4412 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
4413 PPC_FLOAT_STFIWX | PPC_WAIT | \
4414 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
4415 #define POWERPC_INSNS2_e500mc (PPC2_BOOKE206 | PPC2_PRCNTL)
4416 #define POWERPC_MSRM_e500mc (0x000000001402FB36ULL)
4417 #define POWERPC_MMU_e500mc (POWERPC_MMU_BOOKE206)
4418 #define POWERPC_EXCP_e500mc (POWERPC_EXCP_BOOKE)
4419 #define POWERPC_INPUT_e500mc (PPC_FLAGS_INPUT_BookE)
4420 /* Fixme: figure out the correct flag for e500mc */
4421 #define POWERPC_BFDM_e500mc (bfd_mach_ppc_e500)
4422 #define POWERPC_FLAG_e500mc (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
4423 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4424 #define check_pow_e500mc check_pow_none
4425 #define init_proc_e500mc init_proc_e500mc
4426
4427 enum fsl_e500_version {
4428 fsl_e500v1,
4429 fsl_e500v2,
4430 fsl_e500mc,
4431 };
4432
4433 static void init_proc_e500 (CPUPPCState *env, int version)
4434 {
4435 uint32_t tlbncfg[2];
4436 uint64_t ivor_mask = 0x0000000F0000FFFFULL;
4437 uint64_t ivpr_mask = 0xFFFF0000ULL;
4438 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4439 | 0x0020; /* 32 kb */
4440 #if !defined(CONFIG_USER_ONLY)
4441 int i;
4442 #endif
4443
4444 /* Time base */
4445 gen_tbl(env);
4446 /*
4447 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4448 * complain when accessing them.
4449 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4450 */
4451 if (version == fsl_e500mc) {
4452 ivor_mask = 0x000003FE0000FFFFULL;
4453 }
4454 gen_spr_BookE(env, ivor_mask);
4455 /* Processor identification */
4456 spr_register(env, SPR_BOOKE_PIR, "PIR",
4457 SPR_NOACCESS, SPR_NOACCESS,
4458 &spr_read_generic, &spr_write_pir,
4459 0x00000000);
4460 /* XXX : not implemented */
4461 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4462 &spr_read_spefscr, &spr_write_spefscr,
4463 &spr_read_spefscr, &spr_write_spefscr,
4464 0x00000000);
4465 #if !defined(CONFIG_USER_ONLY)
4466 /* Memory management */
4467 env->nb_pids = 3;
4468 env->nb_ways = 2;
4469 env->id_tlbs = 0;
4470 switch (version) {
4471 case fsl_e500v1:
4472 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4473 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4474 break;
4475 case fsl_e500v2:
4476 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4477 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4478 break;
4479 case fsl_e500mc:
4480 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4481 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4482 break;
4483 default:
4484 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4485 }
4486 #endif
4487 /* Cache sizes */
4488 switch (version) {
4489 case fsl_e500v1:
4490 case fsl_e500v2:
4491 env->dcache_line_size = 32;
4492 env->icache_line_size = 32;
4493 break;
4494 case fsl_e500mc:
4495 env->dcache_line_size = 64;
4496 env->icache_line_size = 64;
4497 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4498 break;
4499 default:
4500 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4501 }
4502 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4503 /* XXX : not implemented */
4504 spr_register(env, SPR_HID0, "HID0",
4505 SPR_NOACCESS, SPR_NOACCESS,
4506 &spr_read_generic, &spr_write_generic,
4507 0x00000000);
4508 /* XXX : not implemented */
4509 spr_register(env, SPR_HID1, "HID1",
4510 SPR_NOACCESS, SPR_NOACCESS,
4511 &spr_read_generic, &spr_write_generic,
4512 0x00000000);
4513 /* XXX : not implemented */
4514 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4515 SPR_NOACCESS, SPR_NOACCESS,
4516 &spr_read_generic, &spr_write_generic,
4517 0x00000000);
4518 /* XXX : not implemented */
4519 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4520 SPR_NOACCESS, SPR_NOACCESS,
4521 &spr_read_generic, &spr_write_generic,
4522 0x00000000);
4523 /* XXX : not implemented */
4524 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4525 SPR_NOACCESS, SPR_NOACCESS,
4526 &spr_read_generic, &spr_write_generic,
4527 0x00000000);
4528 /* XXX : not implemented */
4529 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4530 SPR_NOACCESS, SPR_NOACCESS,
4531 &spr_read_generic, &spr_write_generic,
4532 0x00000000);
4533 /* XXX : not implemented */
4534 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4535 SPR_NOACCESS, SPR_NOACCESS,
4536 &spr_read_generic, &spr_write_generic,
4537 0x00000000);
4538 /* XXX : not implemented */
4539 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4540 SPR_NOACCESS, SPR_NOACCESS,
4541 &spr_read_generic, &spr_write_generic,
4542 0x00000000);
4543 /* XXX : not implemented */
4544 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4545 SPR_NOACCESS, SPR_NOACCESS,
4546 &spr_read_generic, &spr_write_generic,
4547 l1cfg0);
4548 /* XXX : not implemented */
4549 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4550 SPR_NOACCESS, SPR_NOACCESS,
4551 &spr_read_generic, &spr_write_e500_l1csr0,
4552 0x00000000);
4553 /* XXX : not implemented */
4554 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4555 SPR_NOACCESS, SPR_NOACCESS,
4556 &spr_read_generic, &spr_write_generic,
4557 0x00000000);
4558 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4559 SPR_NOACCESS, SPR_NOACCESS,
4560 &spr_read_generic, &spr_write_generic,
4561 0x00000000);
4562 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4563 SPR_NOACCESS, SPR_NOACCESS,
4564 &spr_read_generic, &spr_write_generic,
4565 0x00000000);
4566 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4567 SPR_NOACCESS, SPR_NOACCESS,
4568 &spr_read_generic, &spr_write_booke206_mmucsr0,
4569 0x00000000);
4570
4571 #if !defined(CONFIG_USER_ONLY)
4572 env->nb_tlb = 0;
4573 env->tlb_type = TLB_MAS;
4574 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4575 env->nb_tlb += booke206_tlb_size(env, i);
4576 }
4577 #endif
4578
4579 init_excp_e200(env, ivpr_mask);
4580 /* Allocate hardware IRQ controller */
4581 ppce500_irq_init(env);
4582 }
4583
4584 static void init_proc_e500v1(CPUPPCState *env)
4585 {
4586 init_proc_e500(env, fsl_e500v1);
4587 }
4588
4589 static void init_proc_e500v2(CPUPPCState *env)
4590 {
4591 init_proc_e500(env, fsl_e500v2);
4592 }
4593
4594 static void init_proc_e500mc(CPUPPCState *env)
4595 {
4596 init_proc_e500(env, fsl_e500mc);
4597 }
4598
4599 /* Non-embedded PowerPC */
4600
4601 /* POWER : same as 601, without mfmsr, mfsr */
4602 #if defined(TODO)
4603 #define POWERPC_INSNS_POWER (XXX_TODO)
4604 /* POWER RSC (from RAD6000) */
4605 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4606 #endif /* TODO */
4607
4608 /* PowerPC 601 */
4609 #define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4610 PPC_FLOAT | \
4611 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4612 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4613 PPC_SEGMENT | PPC_EXTERN)
4614 #define POWERPC_INSNS2_601 (PPC_NONE)
4615 #define POWERPC_MSRM_601 (0x000000000000FD70ULL)
4616 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4617 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
4618 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4619 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
4620 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4621 #define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4622 #define check_pow_601 check_pow_none
4623
4624 static void init_proc_601 (CPUPPCState *env)
4625 {
4626 gen_spr_ne_601(env);
4627 gen_spr_601(env);
4628 /* Hardware implementation registers */
4629 /* XXX : not implemented */
4630 spr_register(env, SPR_HID0, "HID0",
4631 SPR_NOACCESS, SPR_NOACCESS,
4632 &spr_read_generic, &spr_write_hid0_601,
4633 0x80010080);
4634 /* XXX : not implemented */
4635 spr_register(env, SPR_HID1, "HID1",
4636 SPR_NOACCESS, SPR_NOACCESS,
4637 &spr_read_generic, &spr_write_generic,
4638 0x00000000);
4639 /* XXX : not implemented */
4640 spr_register(env, SPR_601_HID2, "HID2",
4641 SPR_NOACCESS, SPR_NOACCESS,
4642 &spr_read_generic, &spr_write_generic,
4643 0x00000000);
4644 /* XXX : not implemented */
4645 spr_register(env, SPR_601_HID5, "HID5",
4646 SPR_NOACCESS, SPR_NOACCESS,
4647 &spr_read_generic, &spr_write_generic,
4648 0x00000000);
4649 /* Memory management */
4650 init_excp_601(env);
4651 /* XXX: beware that dcache line size is 64
4652 * but dcbz uses 32 bytes "sectors"
4653 * XXX: this breaks clcs instruction !
4654 */
4655 env->dcache_line_size = 32;
4656 env->icache_line_size = 64;
4657 /* Allocate hardware IRQ controller */
4658 ppc6xx_irq_init(env);
4659 }
4660
4661 /* PowerPC 601v */
4662 #define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4663 PPC_FLOAT | \
4664 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4665 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4666 PPC_SEGMENT | PPC_EXTERN)
4667 #define POWERPC_INSNS2_601v (PPC_NONE)
4668 #define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4669 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4670 #define POWERPC_MMU_601v (POWERPC_MMU_601)
4671 #define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4672 #define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4673 #define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4674 #define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4675 #define check_pow_601v check_pow_none
4676
4677 static void init_proc_601v (CPUPPCState *env)
4678 {
4679 init_proc_601(env);
4680 /* XXX : not implemented */
4681 spr_register(env, SPR_601_HID15, "HID15",
4682 SPR_NOACCESS, SPR_NOACCESS,
4683 &spr_read_generic, &spr_write_generic,
4684 0x00000000);
4685 }
4686
4687 /* PowerPC 602 */
4688 #define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4689 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4690 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4691 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4692 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4693 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4694 PPC_SEGMENT | PPC_602_SPEC)
4695 #define POWERPC_INSNS2_602 (PPC_NONE)
4696 #define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4697 /* XXX: 602 MMU is quite specific. Should add a special case */
4698 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4699 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4700 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
4701 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
4702 #define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4703 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4704 #define check_pow_602 check_pow_hid0
4705
4706 static void init_proc_602 (CPUPPCState *env)
4707 {
4708 gen_spr_ne_601(env);
4709 gen_spr_602(env);
4710 /* Time base */
4711 gen_tbl(env);
4712 /* hardware implementation registers */
4713 /* XXX : not implemented */
4714 spr_register(env, SPR_HID0, "HID0",
4715 SPR_NOACCESS, SPR_NOACCESS,
4716 &spr_read_generic, &spr_write_generic,
4717 0x00000000);
4718 /* XXX : not implemented */
4719 spr_register(env, SPR_HID1, "HID1",
4720 SPR_NOACCESS, SPR_NOACCESS,
4721 &spr_read_generic, &spr_write_generic,
4722 0x00000000);
4723 /* Memory management */
4724 gen_low_BATs(env);
4725 gen_6xx_7xx_soft_tlb(env, 64, 2);
4726 init_excp_602(env);
4727 env->dcache_line_size = 32;
4728 env->icache_line_size = 32;
4729 /* Allocate hardware IRQ controller */
4730 ppc6xx_irq_init(env);
4731 }
4732
4733 /* PowerPC 603 */
4734 #define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4735 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4736 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4737 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4738 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4739 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4740 PPC_SEGMENT | PPC_EXTERN)
4741 #define POWERPC_INSNS2_603 (PPC_NONE)
4742 #define POWERPC_MSRM_603 (0x000000000007FF73ULL)
4743 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4744 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4745 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
4746 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
4747 #define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4748 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4749 #define check_pow_603 check_pow_hid0
4750
4751 static void init_proc_603 (CPUPPCState *env)
4752 {
4753 gen_spr_ne_601(env);
4754 gen_spr_603(env);
4755 /* Time base */
4756 gen_tbl(env);
4757 /* hardware implementation registers */
4758 /* XXX : not implemented */
4759 spr_register(env, SPR_HID0, "HID0",
4760 SPR_NOACCESS, SPR_NOACCESS,
4761 &spr_read_generic, &spr_write_generic,
4762 0x00000000);
4763 /* XXX : not implemented */
4764 spr_register(env, SPR_HID1, "HID1",
4765 SPR_NOACCESS, SPR_NOACCESS,
4766 &spr_read_generic, &spr_write_generic,
4767 0x00000000);
4768 /* Memory management */
4769 gen_low_BATs(env);
4770 gen_6xx_7xx_soft_tlb(env, 64, 2);
4771 init_excp_603(env);
4772 env->dcache_line_size = 32;
4773 env->icache_line_size = 32;
4774 /* Allocate hardware IRQ controller */
4775 ppc6xx_irq_init(env);
4776 }
4777
4778 /* PowerPC 603e */
4779 #define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4780 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4781 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4782 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4783 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4784 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4785 PPC_SEGMENT | PPC_EXTERN)
4786 #define POWERPC_INSNS2_603E (PPC_NONE)
4787 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4788 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4789 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4790 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
4791 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
4792 #define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4793 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4794 #define check_pow_603E check_pow_hid0
4795
4796 static void init_proc_603E (CPUPPCState *env)
4797 {
4798 gen_spr_ne_601(env);
4799 gen_spr_603(env);
4800 /* Time base */
4801 gen_tbl(env);
4802 /* hardware implementation registers */
4803 /* XXX : not implemented */
4804 spr_register(env, SPR_HID0, "HID0",
4805 SPR_NOACCESS, SPR_NOACCESS,
4806 &spr_read_generic, &spr_write_generic,
4807 0x00000000);
4808 /* XXX : not implemented */
4809 spr_register(env, SPR_HID1, "HID1",
4810 SPR_NOACCESS, SPR_NOACCESS,
4811 &spr_read_generic, &spr_write_generic,
4812 0x00000000);
4813 /* XXX : not implemented */
4814 spr_register(env, SPR_IABR, "IABR",
4815 SPR_NOACCESS, SPR_NOACCESS,
4816 &spr_read_generic, &spr_write_generic,
4817 0x00000000);
4818 /* Memory management */
4819 gen_low_BATs(env);
4820 gen_6xx_7xx_soft_tlb(env, 64, 2);
4821 init_excp_603(env);
4822 env->dcache_line_size = 32;
4823 env->icache_line_size = 32;
4824 /* Allocate hardware IRQ controller */
4825 ppc6xx_irq_init(env);
4826 }
4827
4828 /* PowerPC 604 */
4829 #define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4830 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4831 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4832 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4833 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4834 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4835 PPC_SEGMENT | PPC_EXTERN)
4836 #define POWERPC_INSNS2_604 (PPC_NONE)
4837 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4838 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
4839 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4840 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
4841 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
4842 #define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4843 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4844 #define check_pow_604 check_pow_nocheck
4845
4846 static void init_proc_604 (CPUPPCState *env)
4847 {
4848 gen_spr_ne_601(env);
4849 gen_spr_604(env);
4850 /* Time base */
4851 gen_tbl(env);
4852 /* Hardware implementation registers */
4853 /* XXX : not implemented */
4854 spr_register(env, SPR_HID0, "HID0",
4855 SPR_NOACCESS, SPR_NOACCESS,
4856 &spr_read_generic, &spr_write_generic,
4857 0x00000000);
4858 /* Memory management */
4859 gen_low_BATs(env);
4860 init_excp_604(env);
4861 env->dcache_line_size = 32;
4862 env->icache_line_size = 32;
4863 /* Allocate hardware IRQ controller */
4864 ppc6xx_irq_init(env);
4865 }
4866
4867 /* PowerPC 604E */
4868 #define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4869 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4870 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4871 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4872 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4873 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4874 PPC_SEGMENT | PPC_EXTERN)
4875 #define POWERPC_INSNS2_604E (PPC_NONE)
4876 #define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4877 #define POWERPC_MMU_604E (POWERPC_MMU_32B)
4878 #define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4879 #define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4880 #define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4881 #define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4882 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4883 #define check_pow_604E check_pow_nocheck
4884
4885 static void init_proc_604E (CPUPPCState *env)
4886 {
4887 gen_spr_ne_601(env);
4888 gen_spr_604(env);
4889 /* XXX : not implemented */
4890 spr_register(env, SPR_MMCR1, "MMCR1",
4891 SPR_NOACCESS, SPR_NOACCESS,
4892 &spr_read_generic, &spr_write_generic,
4893 0x00000000);
4894 /* XXX : not implemented */
4895 spr_register(env, SPR_PMC3, "PMC3",
4896 SPR_NOACCESS, SPR_NOACCESS,
4897 &spr_read_generic, &spr_write_generic,
4898 0x00000000);
4899 /* XXX : not implemented */
4900 spr_register(env, SPR_PMC4, "PMC4",
4901 SPR_NOACCESS, SPR_NOACCESS,
4902 &spr_read_generic, &spr_write_generic,
4903 0x00000000);
4904 /* Time base */
4905 gen_tbl(env);
4906 /* Hardware implementation registers */
4907 /* XXX : not implemented */
4908 spr_register(env, SPR_HID0, "HID0",
4909 SPR_NOACCESS, SPR_NOACCESS,
4910 &spr_read_generic, &spr_write_generic,
4911 0x00000000);
4912 /* XXX : not implemented */
4913 spr_register(env, SPR_HID1, "HID1",
4914 SPR_NOACCESS, SPR_NOACCESS,
4915 &spr_read_generic, &spr_write_generic,
4916 0x00000000);
4917 /* Memory management */
4918 gen_low_BATs(env);
4919 init_excp_604(env);
4920 env->dcache_line_size = 32;
4921 env->icache_line_size = 32;
4922 /* Allocate hardware IRQ controller */
4923 ppc6xx_irq_init(env);
4924 }
4925
4926 /* PowerPC 740 */
4927 #define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4928 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4929 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4930 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4931 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4932 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4933 PPC_SEGMENT | PPC_EXTERN)
4934 #define POWERPC_INSNS2_740 (PPC_NONE)
4935 #define POWERPC_MSRM_740 (0x000000000005FF77ULL)
4936 #define POWERPC_MMU_740 (POWERPC_MMU_32B)
4937 #define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
4938 #define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
4939 #define POWERPC_BFDM_740 (bfd_mach_ppc_750)
4940 #define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4941 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4942 #define check_pow_740 check_pow_hid0
4943
4944 static void init_proc_740 (CPUPPCState *env)
4945 {
4946 gen_spr_ne_601(env);
4947 gen_spr_7xx(env);
4948 /* Time base */
4949 gen_tbl(env);
4950 /* Thermal management */
4951 gen_spr_thrm(env);
4952 /* Hardware implementation registers */
4953 /* XXX : not implemented */
4954 spr_register(env, SPR_HID0, "HID0",
4955 SPR_NOACCESS, SPR_NOACCESS,
4956 &spr_read_generic, &spr_write_generic,
4957 0x00000000);
4958 /* XXX : not implemented */
4959 spr_register(env, SPR_HID1, "HID1",
4960 SPR_NOACCESS, SPR_NOACCESS,
4961 &spr_read_generic, &spr_write_generic,
4962 0x00000000);
4963 /* Memory management */
4964 gen_low_BATs(env);
4965 init_excp_7x0(env);
4966 env->dcache_line_size = 32;
4967 env->icache_line_size = 32;
4968 /* Allocate hardware IRQ controller */
4969 ppc6xx_irq_init(env);
4970 }
4971
4972 /* PowerPC 750 */
4973 #define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4974 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4975 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4976 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4977 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4978 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4979 PPC_SEGMENT | PPC_EXTERN)
4980 #define POWERPC_INSNS2_750 (PPC_NONE)
4981 #define POWERPC_MSRM_750 (0x000000000005FF77ULL)
4982 #define POWERPC_MMU_750 (POWERPC_MMU_32B)
4983 #define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
4984 #define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
4985 #define POWERPC_BFDM_750 (bfd_mach_ppc_750)
4986 #define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4987 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4988 #define check_pow_750 check_pow_hid0
4989
4990 static void init_proc_750 (CPUPPCState *env)
4991 {
4992 gen_spr_ne_601(env);
4993 gen_spr_7xx(env);
4994 /* XXX : not implemented */
4995 spr_register(env, SPR_L2CR, "L2CR",
4996 SPR_NOACCESS, SPR_NOACCESS,
4997 &spr_read_generic, &spr_write_generic,
4998 0x00000000);
4999 /* Time base */
5000 gen_tbl(env);
5001 /* Thermal management */
5002 gen_spr_thrm(env);
5003 /* Hardware implementation registers */
5004 /* XXX : not implemented */
5005 spr_register(env, SPR_HID0, "HID0",
5006 SPR_NOACCESS, SPR_NOACCESS,
5007 &spr_read_generic, &spr_write_generic,
5008 0x00000000);
5009 /* XXX : not implemented */
5010 spr_register(env, SPR_HID1, "HID1",
5011 SPR_NOACCESS, SPR_NOACCESS,
5012 &spr_read_generic, &spr_write_generic,
5013 0x00000000);
5014 /* Memory management */
5015 gen_low_BATs(env);
5016 /* XXX: high BATs are also present but are known to be bugged on
5017 * die version 1.x
5018 */
5019 init_excp_7x0(env);
5020 env->dcache_line_size = 32;
5021 env->icache_line_size = 32;
5022 /* Allocate hardware IRQ controller */
5023 ppc6xx_irq_init(env);
5024 }
5025
5026 /* PowerPC 750 CL */
5027 /* XXX: not implemented:
5028 * cache lock instructions:
5029 * dcbz_l
5030 * floating point paired instructions
5031 * psq_lux
5032 * psq_lx
5033 * psq_stux
5034 * psq_stx
5035 * ps_abs
5036 * ps_add
5037 * ps_cmpo0
5038 * ps_cmpo1
5039 * ps_cmpu0
5040 * ps_cmpu1
5041 * ps_div
5042 * ps_madd
5043 * ps_madds0
5044 * ps_madds1
5045 * ps_merge00
5046 * ps_merge01
5047 * ps_merge10
5048 * ps_merge11
5049 * ps_mr
5050 * ps_msub
5051 * ps_mul
5052 * ps_muls0
5053 * ps_muls1
5054 * ps_nabs
5055 * ps_neg
5056 * ps_nmadd
5057 * ps_nmsub
5058 * ps_res
5059 * ps_rsqrte
5060 * ps_sel
5061 * ps_sub
5062 * ps_sum0
5063 * ps_sum1
5064 */
5065 #define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5066 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5067 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5068 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5069 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5070 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5071 PPC_SEGMENT | PPC_EXTERN)
5072 #define POWERPC_INSNS2_750cl (PPC_NONE)
5073 #define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
5074 #define POWERPC_MMU_750cl (POWERPC_MMU_32B)
5075 #define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
5076 #define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
5077 #define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
5078 #define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5079 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5080 #define check_pow_750cl check_pow_hid0
5081
5082 static void init_proc_750cl (CPUPPCState *env)
5083 {
5084 gen_spr_ne_601(env);
5085 gen_spr_7xx(env);
5086 /* XXX : not implemented */
5087 spr_register(env, SPR_L2CR, "L2CR",
5088 SPR_NOACCESS, SPR_NOACCESS,
5089 &spr_read_generic, &spr_write_generic,
5090 0x00000000);
5091 /* Time base */
5092 gen_tbl(env);
5093 /* Thermal management */
5094 /* Those registers are fake on 750CL */
5095 spr_register(env, SPR_THRM1, "THRM1",
5096 SPR_NOACCESS, SPR_NOACCESS,
5097 &spr_read_generic, &spr_write_generic,
5098 0x00000000);
5099 spr_register(env, SPR_THRM2, "THRM2",
5100 SPR_NOACCESS, SPR_NOACCESS,
5101 &spr_read_generic, &spr_write_generic,
5102 0x00000000);
5103 spr_register(env, SPR_THRM3, "THRM3",
5104 SPR_NOACCESS, SPR_NOACCESS,
5105 &spr_read_generic, &spr_write_generic,
5106 0x00000000);
5107 /* XXX: not implemented */
5108 spr_register(env, SPR_750_TDCL, "TDCL",
5109 SPR_NOACCESS, SPR_NOACCESS,
5110 &spr_read_generic, &spr_write_generic,
5111 0x00000000);
5112 spr_register(env, SPR_750_TDCH, "TDCH",
5113 SPR_NOACCESS, SPR_NOACCESS,
5114 &spr_read_generic, &spr_write_generic,
5115 0x00000000);
5116 /* DMA */
5117 /* XXX : not implemented */
5118 spr_register(env, SPR_750_WPAR, "WPAR",
5119 SPR_NOACCESS, SPR_NOACCESS,
5120 &spr_read_generic, &spr_write_generic,
5121 0x00000000);
5122 spr_register(env, SPR_750_DMAL, "DMAL",
5123 SPR_NOACCESS, SPR_NOACCESS,
5124 &spr_read_generic, &spr_write_generic,
5125 0x00000000);
5126 spr_register(env, SPR_750_DMAU, "DMAU",
5127 SPR_NOACCESS, SPR_NOACCESS,
5128 &spr_read_generic, &spr_write_generic,
5129 0x00000000);
5130 /* Hardware implementation registers */
5131 /* XXX : not implemented */
5132 spr_register(env, SPR_HID0, "HID0",
5133 SPR_NOACCESS, SPR_NOACCESS,
5134 &spr_read_generic, &spr_write_generic,
5135 0x00000000);
5136 /* XXX : not implemented */
5137 spr_register(env, SPR_HID1, "HID1",
5138 SPR_NOACCESS, SPR_NOACCESS,
5139 &spr_read_generic, &spr_write_generic,
5140 0x00000000);
5141 /* XXX : not implemented */
5142 spr_register(env, SPR_750CL_HID2, "HID2",
5143 SPR_NOACCESS, SPR_NOACCESS,
5144 &spr_read_generic, &spr_write_generic,
5145 0x00000000);
5146 /* XXX : not implemented */
5147 spr_register(env, SPR_750CL_HID4, "HID4",
5148 SPR_NOACCESS, SPR_NOACCESS,
5149 &spr_read_generic, &spr_write_generic,
5150 0x00000000);
5151 /* Quantization registers */
5152 /* XXX : not implemented */
5153 spr_register(env, SPR_750_GQR0, "GQR0",
5154 SPR_NOACCESS, SPR_NOACCESS,
5155 &spr_read_generic, &spr_write_generic,
5156 0x00000000);
5157 /* XXX : not implemented */
5158 spr_register(env, SPR_750_GQR1, "GQR1",
5159 SPR_NOACCESS, SPR_NOACCESS,
5160 &spr_read_generic, &spr_write_generic,
5161 0x00000000);
5162 /* XXX : not implemented */
5163 spr_register(env, SPR_750_GQR2, "GQR2",
5164 SPR_NOACCESS, SPR_NOACCESS,
5165 &spr_read_generic, &spr_write_generic,
5166 0x00000000);
5167 /* XXX : not implemented */
5168 spr_register(env, SPR_750_GQR3, "GQR3",
5169 SPR_NOACCESS, SPR_NOACCESS,
5170 &spr_read_generic, &spr_write_generic,
5171 0x00000000);
5172 /* XXX : not implemented */
5173 spr_register(env, SPR_750_GQR4, "GQR4",
5174 SPR_NOACCESS, SPR_NOACCESS,
5175 &spr_read_generic, &spr_write_generic,
5176 0x00000000);
5177 /* XXX : not implemented */
5178 spr_register(env, SPR_750_GQR5, "GQR5",
5179 SPR_NOACCESS, SPR_NOACCESS,
5180 &spr_read_generic, &spr_write_generic,
5181 0x00000000);
5182 /* XXX : not implemented */
5183 spr_register(env, SPR_750_GQR6, "GQR6",
5184 SPR_NOACCESS, SPR_NOACCESS,
5185 &spr_read_generic, &spr_write_generic,
5186 0x00000000);
5187 /* XXX : not implemented */
5188 spr_register(env, SPR_750_GQR7, "GQR7",
5189 SPR_NOACCESS, SPR_NOACCESS,
5190 &spr_read_generic, &spr_write_generic,
5191 0x00000000);
5192 /* Memory management */
5193 gen_low_BATs(env);
5194 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5195 gen_high_BATs(env);
5196 init_excp_750cl(env);
5197 env->dcache_line_size = 32;
5198 env->icache_line_size = 32;
5199 /* Allocate hardware IRQ controller */
5200 ppc6xx_irq_init(env);
5201 }
5202
5203 /* PowerPC 750CX */
5204 #define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5205 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5206 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5207 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5208 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5209 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5210 PPC_SEGMENT | PPC_EXTERN)
5211 #define POWERPC_INSNS2_750cx (PPC_NONE)
5212 #define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
5213 #define POWERPC_MMU_750cx (POWERPC_MMU_32B)
5214 #define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
5215 #define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
5216 #define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
5217 #define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5218 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5219 #define check_pow_750cx check_pow_hid0
5220
5221 static void init_proc_750cx (CPUPPCState *env)
5222 {
5223 gen_spr_ne_601(env);
5224 gen_spr_7xx(env);
5225 /* XXX : not implemented */
5226 spr_register(env, SPR_L2CR, "L2CR",
5227 SPR_NOACCESS, SPR_NOACCESS,
5228 &spr_read_generic, &spr_write_generic,
5229 0x00000000);
5230 /* Time base */
5231 gen_tbl(env);
5232 /* Thermal management */
5233 gen_spr_thrm(env);
5234 /* This register is not implemented but is present for compatibility */
5235 spr_register(env, SPR_SDA, "SDA",
5236 SPR_NOACCESS, SPR_NOACCESS,
5237 &spr_read_generic, &spr_write_generic,
5238 0x00000000);
5239 /* Hardware implementation registers */
5240 /* XXX : not implemented */
5241 spr_register(env, SPR_HID0, "HID0",
5242 SPR_NOACCESS, SPR_NOACCESS,
5243 &spr_read_generic, &spr_write_generic,
5244 0x00000000);
5245 /* XXX : not implemented */
5246 spr_register(env, SPR_HID1, "HID1",
5247 SPR_NOACCESS, SPR_NOACCESS,
5248 &spr_read_generic, &spr_write_generic,
5249 0x00000000);
5250 /* Memory management */
5251 gen_low_BATs(env);
5252 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5253 gen_high_BATs(env);
5254 init_excp_750cx(env);
5255 env->dcache_line_size = 32;
5256 env->icache_line_size = 32;
5257 /* Allocate hardware IRQ controller */
5258 ppc6xx_irq_init(env);
5259 }
5260
5261 /* PowerPC 750FX */
5262 #define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5263 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5264 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5265 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5266 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5267 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5268 PPC_SEGMENT | PPC_EXTERN)
5269 #define POWERPC_INSNS2_750fx (PPC_NONE)
5270 #define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
5271 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
5272 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
5273 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
5274 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
5275 #define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5276 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5277 #define check_pow_750fx check_pow_hid0
5278
5279 static void init_proc_750fx (CPUPPCState *env)
5280 {
5281 gen_spr_ne_601(env);
5282 gen_spr_7xx(env);
5283 /* XXX : not implemented */
5284 spr_register(env, SPR_L2CR, "L2CR",
5285 SPR_NOACCESS, SPR_NOACCESS,
5286 &spr_read_generic, &spr_write_generic,
5287 0x00000000);
5288 /* Time base */
5289 gen_tbl(env);
5290 /* Thermal management */
5291 gen_spr_thrm(env);
5292 /* XXX : not implemented */
5293 spr_register(env, SPR_750_THRM4, "THRM4",
5294 SPR_NOACCESS, SPR_NOACCESS,
5295 &spr_read_generic, &spr_write_generic,
5296 0x00000000);
5297 /* Hardware implementation registers */
5298 /* XXX : not implemented */
5299 spr_register(env, SPR_HID0, "HID0",
5300 SPR_NOACCESS, SPR_NOACCESS,
5301 &spr_read_generic, &spr_write_generic,
5302 0x00000000);
5303 /* XXX : not implemented */
5304 spr_register(env, SPR_HID1, "HID1",
5305 SPR_NOACCESS, SPR_NOACCESS,
5306 &spr_read_generic, &spr_write_generic,
5307 0x00000000);
5308 /* XXX : not implemented */
5309 spr_register(env, SPR_750FX_HID2, "HID2",
5310 SPR_NOACCESS, SPR_NOACCESS,
5311 &spr_read_generic, &spr_write_generic,
5312 0x00000000);
5313 /* Memory management */
5314 gen_low_BATs(env);
5315 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5316 gen_high_BATs(env);
5317 init_excp_7x0(env);
5318 env->dcache_line_size = 32;
5319 env->icache_line_size = 32;
5320 /* Allocate hardware IRQ controller */
5321 ppc6xx_irq_init(env);
5322 }
5323
5324 /* PowerPC 750GX */
5325 #define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5326 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5327 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5328 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5329 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5330 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5331 PPC_SEGMENT | PPC_EXTERN)
5332 #define POWERPC_INSNS2_750gx (PPC_NONE)
5333 #define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5334 #define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5335 #define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5336 #define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5337 #define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5338 #define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5339 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5340 #define check_pow_750gx check_pow_hid0
5341
5342 static void init_proc_750gx (CPUPPCState *env)
5343 {
5344 gen_spr_ne_601(env);
5345 gen_spr_7xx(env);
5346 /* XXX : not implemented (XXX: different from 750fx) */
5347 spr_register(env, SPR_L2CR, "L2CR",
5348 SPR_NOACCESS, SPR_NOACCESS,
5349 &spr_read_generic, &spr_write_generic,
5350 0x00000000);
5351 /* Time base */
5352 gen_tbl(env);
5353 /* Thermal management */
5354 gen_spr_thrm(env);
5355 /* XXX : not implemented */
5356 spr_register(env, SPR_750_THRM4, "THRM4",
5357 SPR_NOACCESS, SPR_NOACCESS,
5358 &spr_read_generic, &spr_write_generic,
5359 0x00000000);
5360 /* Hardware implementation registers */
5361 /* XXX : not implemented (XXX: different from 750fx) */
5362 spr_register(env, SPR_HID0, "HID0",
5363 SPR_NOACCESS, SPR_NOACCESS,
5364 &spr_read_generic, &spr_write_generic,
5365 0x00000000);
5366 /* XXX : not implemented */
5367 spr_register(env, SPR_HID1, "HID1",
5368 SPR_NOACCESS, SPR_NOACCESS,
5369 &spr_read_generic, &spr_write_generic,
5370 0x00000000);
5371 /* XXX : not implemented (XXX: different from 750fx) */
5372 spr_register(env, SPR_750FX_HID2, "HID2",
5373 SPR_NOACCESS, SPR_NOACCESS,
5374 &spr_read_generic, &spr_write_generic,
5375 0x00000000);
5376 /* Memory management */
5377 gen_low_BATs(env);
5378 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5379 gen_high_BATs(env);
5380 init_excp_7x0(env);
5381 env->dcache_line_size = 32;
5382 env->icache_line_size = 32;
5383 /* Allocate hardware IRQ controller */
5384 ppc6xx_irq_init(env);
5385 }
5386
5387 /* PowerPC 745 */
5388 #define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5389 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5390 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5391 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5392 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5393 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5394 PPC_SEGMENT | PPC_EXTERN)
5395 #define POWERPC_INSNS2_745 (PPC_NONE)
5396 #define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5397 #define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5398 #define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5399 #define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5400 #define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5401 #define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5402 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5403 #define check_pow_745 check_pow_hid0
5404
5405 static void init_proc_745 (CPUPPCState *env)
5406 {
5407 gen_spr_ne_601(env);
5408 gen_spr_7xx(env);
5409 gen_spr_G2_755(env);
5410 /* Time base */
5411 gen_tbl(env);
5412 /* Thermal management */
5413 gen_spr_thrm(env);
5414 /* Hardware implementation registers */
5415 /* XXX : not implemented */
5416 spr_register(env, SPR_HID0, "HID0",
5417 SPR_NOACCESS, SPR_NOACCESS,
5418 &spr_read_generic, &spr_write_generic,
5419 0x00000000);
5420 /* XXX : not implemented */
5421 spr_register(env, SPR_HID1, "HID1",
5422 SPR_NOACCESS, SPR_NOACCESS,
5423 &spr_read_generic, &spr_write_generic,
5424 0x00000000);
5425 /* XXX : not implemented */
5426 spr_register(env, SPR_HID2, "HID2",
5427 SPR_NOACCESS, SPR_NOACCESS,
5428 &spr_read_generic, &spr_write_generic,
5429 0x00000000);
5430 /* Memory management */
5431 gen_low_BATs(env);
5432 gen_high_BATs(env);
5433 gen_6xx_7xx_soft_tlb(env, 64, 2);
5434 init_excp_7x5(env);
5435 env->dcache_line_size = 32;
5436 env->icache_line_size = 32;
5437 /* Allocate hardware IRQ controller */
5438 ppc6xx_irq_init(env);
5439 }
5440
5441 /* PowerPC 755 */
5442 #define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5443 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5444 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5445 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5446 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5447 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5448 PPC_SEGMENT | PPC_EXTERN)
5449 #define POWERPC_INSNS2_755 (PPC_NONE)
5450 #define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5451 #define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5452 #define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5453 #define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5454 #define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5455 #define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5456 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5457 #define check_pow_755 check_pow_hid0
5458
5459 static void init_proc_755 (CPUPPCState *env)
5460 {
5461 gen_spr_ne_601(env);
5462 gen_spr_7xx(env);
5463 gen_spr_G2_755(env);
5464 /* Time base */
5465 gen_tbl(env);
5466 /* L2 cache control */
5467 /* XXX : not implemented */
5468 spr_register(env, SPR_L2CR, "L2CR",
5469 SPR_NOACCESS, SPR_NOACCESS,
5470 &spr_read_generic, &spr_write_generic,
5471 0x00000000);
5472 /* XXX : not implemented */
5473 spr_register(env, SPR_L2PMCR, "L2PMCR",
5474 SPR_NOACCESS, SPR_NOACCESS,
5475 &spr_read_generic, &spr_write_generic,
5476 0x00000000);
5477 /* Thermal management */
5478 gen_spr_thrm(env);
5479 /* Hardware implementation registers */
5480 /* XXX : not implemented */
5481 spr_register(env, SPR_HID0, "HID0",
5482 SPR_NOACCESS, SPR_NOACCESS,
5483 &spr_read_generic, &spr_write_generic,
5484 0x00000000);
5485 /* XXX : not implemented */
5486 spr_register(env, SPR_HID1, "HID1",
5487 SPR_NOACCESS, SPR_NOACCESS,
5488 &spr_read_generic, &spr_write_generic,
5489 0x00000000);
5490 /* XXX : not implemented */
5491 spr_register(env, SPR_HID2, "HID2",
5492 SPR_NOACCESS, SPR_NOACCESS,
5493 &spr_read_generic, &spr_write_generic,
5494 0x00000000);
5495 /* Memory management */
5496 gen_low_BATs(env);
5497 gen_high_BATs(env);
5498 gen_6xx_7xx_soft_tlb(env, 64, 2);
5499 init_excp_7x5(env);
5500 env->dcache_line_size = 32;
5501 env->icache_line_size = 32;
5502 /* Allocate hardware IRQ controller */
5503 ppc6xx_irq_init(env);
5504 }
5505
5506 /* PowerPC 7400 (aka G4) */
5507 #define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5508 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5509 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5510 PPC_FLOAT_STFIWX | \
5511 PPC_CACHE | PPC_CACHE_ICBI | \
5512 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5513 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5514 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5515 PPC_MEM_TLBIA | \
5516 PPC_SEGMENT | PPC_EXTERN | \
5517 PPC_ALTIVEC)
5518 #define POWERPC_INSNS2_7400 (PPC_NONE)
5519 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5520 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5521 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5522 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
5523 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
5524 #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5525 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5526 POWERPC_FLAG_BUS_CLK)
5527 #define check_pow_7400 check_pow_hid0
5528
5529 static void init_proc_7400 (CPUPPCState *env)
5530 {
5531 gen_spr_ne_601(env);
5532 gen_spr_7xx(env);
5533 /* Time base */
5534 gen_tbl(env);
5535 /* 74xx specific SPR */
5536 gen_spr_74xx(env);
5537 /* XXX : not implemented */
5538 spr_register(env, SPR_UBAMR, "UBAMR",
5539 &spr_read_ureg, SPR_NOACCESS,
5540 &spr_read_ureg, SPR_NOACCESS,
5541 0x00000000);
5542 /* XXX: this seems not implemented on all revisions. */
5543 /* XXX : not implemented */
5544 spr_register(env, SPR_MSSCR1, "MSSCR1",
5545 SPR_NOACCESS, SPR_NOACCESS,
5546 &spr_read_generic, &spr_write_generic,
5547 0x00000000);
5548 /* Thermal management */
5549 gen_spr_thrm(env);
5550 /* Memory management */
5551 gen_low_BATs(env);
5552 init_excp_7400(env);
5553 env->dcache_line_size = 32;
5554 env->icache_line_size = 32;
5555 /* Allocate hardware IRQ controller */
5556 ppc6xx_irq_init(env);
5557 }
5558
5559 /* PowerPC 7410 (aka G4) */
5560 #define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5561 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5562 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5563 PPC_FLOAT_STFIWX | \
5564 PPC_CACHE | PPC_CACHE_ICBI | \
5565 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5566 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5567 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5568 PPC_MEM_TLBIA | \
5569 PPC_SEGMENT | PPC_EXTERN | \
5570 PPC_ALTIVEC)
5571 #define POWERPC_INSNS2_7410 (PPC_NONE)
5572 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5573 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5574 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5575 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
5576 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
5577 #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5578 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5579 POWERPC_FLAG_BUS_CLK)
5580 #define check_pow_7410 check_pow_hid0
5581
5582 static void init_proc_7410 (CPUPPCState *env)
5583 {
5584 gen_spr_ne_601(env);
5585 gen_spr_7xx(env);
5586 /* Time base */
5587 gen_tbl(env);
5588 /* 74xx specific SPR */
5589 gen_spr_74xx(env);
5590 /* XXX : not implemented */
5591 spr_register(env, SPR_UBAMR, "UBAMR",
5592 &spr_read_ureg, SPR_NOACCESS,
5593 &spr_read_ureg, SPR_NOACCESS,
5594 0x00000000);
5595 /* Thermal management */
5596 gen_spr_thrm(env);
5597 /* L2PMCR */
5598 /* XXX : not implemented */
5599 spr_register(env, SPR_L2PMCR, "L2PMCR",
5600 SPR_NOACCESS, SPR_NOACCESS,
5601 &spr_read_generic, &spr_write_generic,
5602 0x00000000);
5603 /* LDSTDB */
5604 /* XXX : not implemented */
5605 spr_register(env, SPR_LDSTDB, "LDSTDB",
5606 SPR_NOACCESS, SPR_NOACCESS,
5607 &spr_read_generic, &spr_write_generic,
5608 0x00000000);
5609 /* Memory management */
5610 gen_low_BATs(env);
5611 init_excp_7400(env);
5612 env->dcache_line_size = 32;
5613 env->icache_line_size = 32;
5614 /* Allocate hardware IRQ controller */
5615 ppc6xx_irq_init(env);
5616 }
5617
5618 /* PowerPC 7440 (aka G4) */
5619 #define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5620 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5621 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5622 PPC_FLOAT_STFIWX | \
5623 PPC_CACHE | PPC_CACHE_ICBI | \
5624 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5625 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5626 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5627 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5628 PPC_SEGMENT | PPC_EXTERN | \
5629 PPC_ALTIVEC)
5630 #define POWERPC_INSNS2_7440 (PPC_NONE)
5631 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5632 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5633 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5634 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
5635 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
5636 #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5637 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5638 POWERPC_FLAG_BUS_CLK)
5639 #define check_pow_7440 check_pow_hid0_74xx
5640
5641 __attribute__ (( unused ))
5642 static void init_proc_7440 (CPUPPCState *env)
5643 {
5644 gen_spr_ne_601(env);
5645 gen_spr_7xx(env);
5646 /* Time base */
5647 gen_tbl(env);
5648 /* 74xx specific SPR */
5649 gen_spr_74xx(env);
5650 /* XXX : not implemented */
5651 spr_register(env, SPR_UBAMR, "UBAMR",
5652 &spr_read_ureg, SPR_NOACCESS,
5653 &spr_read_ureg, SPR_NOACCESS,
5654 0x00000000);
5655 /* LDSTCR */
5656 /* XXX : not implemented */
5657 spr_register(env, SPR_LDSTCR, "LDSTCR",
5658 SPR_NOACCESS, SPR_NOACCESS,
5659 &spr_read_generic, &spr_write_generic,
5660 0x00000000);
5661 /* ICTRL */
5662 /* XXX : not implemented */
5663 spr_register(env, SPR_ICTRL, "ICTRL",
5664 SPR_NOACCESS, SPR_NOACCESS,
5665 &spr_read_generic, &spr_write_generic,
5666 0x00000000);
5667 /* MSSSR0 */
5668 /* XXX : not implemented */
5669 spr_register(env, SPR_MSSSR0, "MSSSR0",
5670 SPR_NOACCESS, SPR_NOACCESS,
5671 &spr_read_generic, &spr_write_generic,
5672 0x00000000);
5673 /* PMC */
5674 /* XXX : not implemented */
5675 spr_register(env, SPR_PMC5, "PMC5",
5676 SPR_NOACCESS, SPR_NOACCESS,
5677 &spr_read_generic, &spr_write_generic,
5678 0x00000000);
5679 /* XXX : not implemented */
5680 spr_register(env, SPR_UPMC5, "UPMC5",
5681 &spr_read_ureg, SPR_NOACCESS,
5682 &spr_read_ureg, SPR_NOACCESS,
5683 0x00000000);
5684 /* XXX : not implemented */
5685 spr_register(env, SPR_PMC6, "PMC6",
5686 SPR_NOACCESS, SPR_NOACCESS,
5687 &spr_read_generic, &spr_write_generic,
5688 0x00000000);
5689 /* XXX : not implemented */
5690 spr_register(env, SPR_UPMC6, "UPMC6",
5691 &spr_read_ureg, SPR_NOACCESS,
5692 &spr_read_ureg, SPR_NOACCESS,
5693 0x00000000);
5694 /* Memory management */
5695 gen_low_BATs(env);
5696 gen_74xx_soft_tlb(env, 128, 2);
5697 init_excp_7450(env);
5698 env->dcache_line_size = 32;
5699 env->icache_line_size = 32;
5700 /* Allocate hardware IRQ controller */
5701 ppc6xx_irq_init(env);
5702 }
5703
5704 /* PowerPC 7450 (aka G4) */
5705 #define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5706 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5707 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5708 PPC_FLOAT_STFIWX | \
5709 PPC_CACHE | PPC_CACHE_ICBI | \
5710 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5711 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5712 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5713 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5714 PPC_SEGMENT | PPC_EXTERN | \
5715 PPC_ALTIVEC)
5716 #define POWERPC_INSNS2_7450 (PPC_NONE)
5717 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5718 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5719 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5720 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
5721 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
5722 #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5723 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5724 POWERPC_FLAG_BUS_CLK)
5725 #define check_pow_7450 check_pow_hid0_74xx
5726
5727 __attribute__ (( unused ))
5728 static void init_proc_7450 (CPUPPCState *env)
5729 {
5730 gen_spr_ne_601(env);
5731 gen_spr_7xx(env);
5732 /* Time base */
5733 gen_tbl(env);
5734 /* 74xx specific SPR */
5735 gen_spr_74xx(env);
5736 /* Level 3 cache control */
5737 gen_l3_ctrl(env);
5738 /* L3ITCR1 */
5739 /* XXX : not implemented */
5740 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5741 SPR_NOACCESS, SPR_NOACCESS,
5742 &spr_read_generic, &spr_write_generic,
5743 0x00000000);
5744 /* L3ITCR2 */
5745 /* XXX : not implemented */
5746 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5747 SPR_NOACCESS, SPR_NOACCESS,
5748 &spr_read_generic, &spr_write_generic,
5749 0x00000000);
5750 /* L3ITCR3 */
5751 /* XXX : not implemented */
5752 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5753 SPR_NOACCESS, SPR_NOACCESS,
5754 &spr_read_generic, &spr_write_generic,
5755 0x00000000);
5756 /* L3OHCR */
5757 /* XXX : not implemented */
5758 spr_register(env, SPR_L3OHCR, "L3OHCR",
5759 SPR_NOACCESS, SPR_NOACCESS,
5760 &spr_read_generic, &spr_write_generic,
5761 0x00000000);
5762 /* XXX : not implemented */
5763 spr_register(env, SPR_UBAMR, "UBAMR",
5764 &spr_read_ureg, SPR_NOACCESS,
5765 &spr_read_ureg, SPR_NOACCESS,
5766 0x00000000);
5767 /* LDSTCR */
5768 /* XXX : not implemented */
5769 spr_register(env, SPR_LDSTCR, "LDSTCR",
5770 SPR_NOACCESS, SPR_NOACCESS,
5771 &spr_read_generic, &spr_write_generic,
5772 0x00000000);
5773 /* ICTRL */
5774 /* XXX : not implemented */
5775 spr_register(env, SPR_ICTRL, "ICTRL",
5776 SPR_NOACCESS, SPR_NOACCESS,
5777 &spr_read_generic, &spr_write_generic,
5778 0x00000000);
5779 /* MSSSR0 */
5780 /* XXX : not implemented */
5781 spr_register(env, SPR_MSSSR0, "MSSSR0",
5782 SPR_NOACCESS, SPR_NOACCESS,
5783 &spr_read_generic, &spr_write_generic,
5784 0x00000000);
5785 /* PMC */
5786 /* XXX : not implemented */
5787 spr_register(env, SPR_PMC5, "PMC5",
5788 SPR_NOACCESS, SPR_NOACCESS,
5789 &spr_read_generic, &spr_write_generic,
5790 0x00000000);
5791 /* XXX : not implemented */
5792 spr_register(env, SPR_UPMC5, "UPMC5",
5793 &spr_read_ureg, SPR_NOACCESS,
5794 &spr_read_ureg, SPR_NOACCESS,
5795 0x00000000);
5796 /* XXX : not implemented */
5797 spr_register(env, SPR_PMC6, "PMC6",
5798 SPR_NOACCESS, SPR_NOACCESS,
5799 &spr_read_generic, &spr_write_generic,
5800 0x00000000);
5801 /* XXX : not implemented */
5802 spr_register(env, SPR_UPMC6, "UPMC6",
5803 &spr_read_ureg, SPR_NOACCESS,
5804 &spr_read_ureg, SPR_NOACCESS,
5805 0x00000000);
5806 /* Memory management */
5807 gen_low_BATs(env);
5808 gen_74xx_soft_tlb(env, 128, 2);
5809 init_excp_7450(env);
5810 env->dcache_line_size = 32;
5811 env->icache_line_size = 32;
5812 /* Allocate hardware IRQ controller */
5813 ppc6xx_irq_init(env);
5814 }
5815
5816 /* PowerPC 7445 (aka G4) */
5817 #define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5818 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5819 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5820 PPC_FLOAT_STFIWX | \
5821 PPC_CACHE | PPC_CACHE_ICBI | \
5822 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5823 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5824 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5825 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5826 PPC_SEGMENT | PPC_EXTERN | \
5827 PPC_ALTIVEC)
5828 #define POWERPC_INSNS2_7445 (PPC_NONE)
5829 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5830 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5831 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5832 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
5833 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
5834 #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5835 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5836 POWERPC_FLAG_BUS_CLK)
5837 #define check_pow_7445 check_pow_hid0_74xx
5838
5839 __attribute__ (( unused ))
5840 static void init_proc_7445 (CPUPPCState *env)
5841 {
5842 gen_spr_ne_601(env);
5843 gen_spr_7xx(env);
5844 /* Time base */
5845 gen_tbl(env);
5846 /* 74xx specific SPR */
5847 gen_spr_74xx(env);
5848 /* LDSTCR */
5849 /* XXX : not implemented */
5850 spr_register(env, SPR_LDSTCR, "LDSTCR",
5851 SPR_NOACCESS, SPR_NOACCESS,
5852 &spr_read_generic, &spr_write_generic,
5853 0x00000000);
5854 /* ICTRL */
5855 /* XXX : not implemented */
5856 spr_register(env, SPR_ICTRL, "ICTRL",
5857 SPR_NOACCESS, SPR_NOACCESS,
5858 &spr_read_generic, &spr_write_generic,
5859 0x00000000);
5860 /* MSSSR0 */
5861 /* XXX : not implemented */
5862 spr_register(env, SPR_MSSSR0, "MSSSR0",
5863 SPR_NOACCESS, SPR_NOACCESS,
5864 &spr_read_generic, &spr_write_generic,
5865 0x00000000);
5866 /* PMC */
5867 /* XXX : not implemented */
5868 spr_register(env, SPR_PMC5, "PMC5",
5869 SPR_NOACCESS, SPR_NOACCESS,
5870 &spr_read_generic, &spr_write_generic,
5871 0x00000000);
5872 /* XXX : not implemented */
5873 spr_register(env, SPR_UPMC5, "UPMC5",
5874 &spr_read_ureg, SPR_NOACCESS,
5875 &spr_read_ureg, SPR_NOACCESS,
5876 0x00000000);
5877 /* XXX : not implemented */
5878 spr_register(env, SPR_PMC6, "PMC6",
5879 SPR_NOACCESS, SPR_NOACCESS,
5880 &spr_read_generic, &spr_write_generic,
5881 0x00000000);
5882 /* XXX : not implemented */
5883 spr_register(env, SPR_UPMC6, "UPMC6",
5884 &spr_read_ureg, SPR_NOACCESS,
5885 &spr_read_ureg, SPR_NOACCESS,
5886 0x00000000);
5887 /* SPRGs */
5888 spr_register(env, SPR_SPRG4, "SPRG4",
5889 SPR_NOACCESS, SPR_NOACCESS,
5890 &spr_read_generic, &spr_write_generic,
5891 0x00000000);
5892 spr_register(env, SPR_USPRG4, "USPRG4",
5893 &spr_read_ureg, SPR_NOACCESS,
5894 &spr_read_ureg, SPR_NOACCESS,
5895 0x00000000);
5896 spr_register(env, SPR_SPRG5, "SPRG5",
5897 SPR_NOACCESS, SPR_NOACCESS,
5898 &spr_read_generic, &spr_write_generic,
5899 0x00000000);
5900 spr_register(env, SPR_USPRG5, "USPRG5",
5901 &spr_read_ureg, SPR_NOACCESS,
5902 &spr_read_ureg, SPR_NOACCESS,
5903 0x00000000);
5904 spr_register(env, SPR_SPRG6, "SPRG6",
5905 SPR_NOACCESS, SPR_NOACCESS,
5906 &spr_read_generic, &spr_write_generic,
5907 0x00000000);
5908 spr_register(env, SPR_USPRG6, "USPRG6",
5909 &spr_read_ureg, SPR_NOACCESS,
5910 &spr_read_ureg, SPR_NOACCESS,
5911 0x00000000);
5912 spr_register(env, SPR_SPRG7, "SPRG7",
5913 SPR_NOACCESS, SPR_NOACCESS,
5914 &spr_read_generic, &spr_write_generic,
5915 0x00000000);
5916 spr_register(env, SPR_USPRG7, "USPRG7",
5917 &spr_read_ureg, SPR_NOACCESS,
5918 &spr_read_ureg, SPR_NOACCESS,
5919 0x00000000);
5920 /* Memory management */
5921 gen_low_BATs(env);
5922 gen_high_BATs(env);
5923 gen_74xx_soft_tlb(env, 128, 2);
5924 init_excp_7450(env);
5925 env->dcache_line_size = 32;
5926 env->icache_line_size = 32;
5927 /* Allocate hardware IRQ controller */
5928 ppc6xx_irq_init(env);
5929 }
5930
5931 /* PowerPC 7455 (aka G4) */
5932 #define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5933 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5934 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5935 PPC_FLOAT_STFIWX | \
5936 PPC_CACHE | PPC_CACHE_ICBI | \
5937 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5938 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5939 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5940 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5941 PPC_SEGMENT | PPC_EXTERN | \
5942 PPC_ALTIVEC)
5943 #define POWERPC_INSNS2_7455 (PPC_NONE)
5944 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
5945 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
5946 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
5947 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
5948 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
5949 #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5950 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5951 POWERPC_FLAG_BUS_CLK)
5952 #define check_pow_7455 check_pow_hid0_74xx
5953
5954 __attribute__ (( unused ))
5955 static void init_proc_7455 (CPUPPCState *env)
5956 {
5957 gen_spr_ne_601(env);
5958 gen_spr_7xx(env);
5959 /* Time base */
5960 gen_tbl(env);
5961 /* 74xx specific SPR */
5962 gen_spr_74xx(env);
5963 /* Level 3 cache control */
5964 gen_l3_ctrl(env);
5965 /* LDSTCR */
5966 /* XXX : not implemented */
5967 spr_register(env, SPR_LDSTCR, "LDSTCR",
5968 SPR_NOACCESS, SPR_NOACCESS,
5969 &spr_read_generic, &spr_write_generic,
5970 0x00000000);
5971 /* ICTRL */
5972 /* XXX : not implemented */
5973 spr_register(env, SPR_ICTRL, "ICTRL",
5974 SPR_NOACCESS, SPR_NOACCESS,
5975 &spr_read_generic, &spr_write_generic,
5976 0x00000000);
5977 /* MSSSR0 */
5978 /* XXX : not implemented */
5979 spr_register(env, SPR_MSSSR0, "MSSSR0",
5980 SPR_NOACCESS, SPR_NOACCESS,
5981 &spr_read_generic, &spr_write_generic,
5982 0x00000000);
5983 /* PMC */
5984 /* XXX : not implemented */
5985 spr_register(env, SPR_PMC5, "PMC5",
5986 SPR_NOACCESS, SPR_NOACCESS,
5987 &spr_read_generic, &spr_write_generic,
5988 0x00000000);
5989 /* XXX : not implemented */
5990 spr_register(env, SPR_UPMC5, "UPMC5",
5991 &spr_read_ureg, SPR_NOACCESS,
5992 &spr_read_ureg, SPR_NOACCESS,
5993 0x00000000);
5994 /* XXX : not implemented */
5995 spr_register(env, SPR_PMC6, "PMC6",
5996 SPR_NOACCESS, SPR_NOACCESS,
5997 &spr_read_generic, &spr_write_generic,
5998 0x00000000);
5999 /* XXX : not implemented */
6000 spr_register(env, SPR_UPMC6, "UPMC6",
6001 &spr_read_ureg, SPR_NOACCESS,
6002 &spr_read_ureg, SPR_NOACCESS,
6003 0x00000000);
6004 /* SPRGs */
6005 spr_register(env, SPR_SPRG4, "SPRG4",
6006 SPR_NOACCESS, SPR_NOACCESS,
6007 &spr_read_generic, &spr_write_generic,
6008 0x00000000);
6009 spr_register(env, SPR_USPRG4, "USPRG4",
6010 &spr_read_ureg, SPR_NOACCESS,
6011 &spr_read_ureg, SPR_NOACCESS,
6012 0x00000000);
6013 spr_register(env, SPR_SPRG5, "SPRG5",
6014 SPR_NOACCESS, SPR_NOACCESS,
6015 &spr_read_generic, &spr_write_generic,
6016 0x00000000);
6017 spr_register(env, SPR_USPRG5, "USPRG5",
6018 &spr_read_ureg, SPR_NOACCESS,
6019 &spr_read_ureg, SPR_NOACCESS,
6020 0x00000000);
6021 spr_register(env, SPR_SPRG6, "SPRG6",
6022 SPR_NOACCESS, SPR_NOACCESS,
6023 &spr_read_generic, &spr_write_generic,
6024 0x00000000);
6025 spr_register(env, SPR_USPRG6, "USPRG6",
6026 &spr_read_ureg, SPR_NOACCESS,
6027 &spr_read_ureg, SPR_NOACCESS,
6028 0x00000000);
6029 spr_register(env, SPR_SPRG7, "SPRG7",
6030 SPR_NOACCESS, SPR_NOACCESS,
6031 &spr_read_generic, &spr_write_generic,
6032 0x00000000);
6033 spr_register(env, SPR_USPRG7, "USPRG7",
6034 &spr_read_ureg, SPR_NOACCESS,
6035 &spr_read_ureg, SPR_NOACCESS,
6036 0x00000000);
6037 /* Memory management */
6038 gen_low_BATs(env);
6039 gen_high_BATs(env);
6040 gen_74xx_soft_tlb(env, 128, 2);
6041 init_excp_7450(env);
6042 env->dcache_line_size = 32;
6043 env->icache_line_size = 32;
6044 /* Allocate hardware IRQ controller */
6045 ppc6xx_irq_init(env);
6046 }
6047
6048 /* PowerPC 7457 (aka G4) */
6049 #define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6050 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6051 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6052 PPC_FLOAT_STFIWX | \
6053 PPC_CACHE | PPC_CACHE_ICBI | \
6054 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
6055 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6056 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6057 PPC_MEM_TLBIA | PPC_74xx_TLB | \
6058 PPC_SEGMENT | PPC_EXTERN | \
6059 PPC_ALTIVEC)
6060 #define POWERPC_INSNS2_7457 (PPC_NONE)
6061 #define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
6062 #define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
6063 #define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
6064 #define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
6065 #define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
6066 #define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6067 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6068 POWERPC_FLAG_BUS_CLK)
6069 #define check_pow_7457 check_pow_hid0_74xx
6070
6071 __attribute__ (( unused ))
6072 static void init_proc_7457 (CPUPPCState *env)
6073 {
6074 gen_spr_ne_601(env);
6075 gen_spr_7xx(env);
6076 /* Time base */
6077 gen_tbl(env);
6078 /* 74xx specific SPR */
6079 gen_spr_74xx(env);
6080 /* Level 3 cache control */
6081 gen_l3_ctrl(env);
6082 /* L3ITCR1 */
6083 /* XXX : not implemented */
6084 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6085 SPR_NOACCESS, SPR_NOACCESS,
6086 &spr_read_generic, &spr_write_generic,
6087 0x00000000);
6088 /* L3ITCR2 */
6089 /* XXX : not implemented */
6090 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6091 SPR_NOACCESS, SPR_NOACCESS,
6092 &spr_read_generic, &spr_write_generic,
6093 0x00000000);
6094 /* L3ITCR3 */
6095 /* XXX : not implemented */
6096 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6097 SPR_NOACCESS, SPR_NOACCESS,
6098 &spr_read_generic, &spr_write_generic,
6099 0x00000000);
6100 /* L3OHCR */
6101 /* XXX : not implemented */
6102 spr_register(env, SPR_L3OHCR, "L3OHCR",
6103 SPR_NOACCESS, SPR_NOACCESS,
6104 &spr_read_generic, &spr_write_generic,
6105 0x00000000);
6106 /* LDSTCR */
6107 /* XXX : not implemented */
6108 spr_register(env, SPR_LDSTCR, "LDSTCR",
6109 SPR_NOACCESS, SPR_NOACCESS,
6110 &spr_read_generic, &spr_write_generic,
6111 0x00000000);
6112 /* ICTRL */
6113 /* XXX : not implemented */
6114 spr_register(env, SPR_ICTRL, "ICTRL",
6115 SPR_NOACCESS, SPR_NOACCESS,
6116 &spr_read_generic, &spr_write_generic,
6117 0x00000000);
6118 /* MSSSR0 */
6119 /* XXX : not implemented */
6120 spr_register(env, SPR_MSSSR0, "MSSSR0",
6121 SPR_NOACCESS, SPR_NOACCESS,
6122 &spr_read_generic, &spr_write_generic,
6123 0x00000000);
6124 /* PMC */
6125 /* XXX : not implemented */
6126 spr_register(env, SPR_PMC5, "PMC5",
6127 SPR_NOACCESS, SPR_NOACCESS,
6128 &spr_read_generic, &spr_write_generic,
6129 0x00000000);
6130 /* XXX : not implemented */
6131 spr_register(env, SPR_UPMC5, "UPMC5",
6132 &spr_read_ureg, SPR_NOACCESS,
6133 &spr_read_ureg, SPR_NOACCESS,
6134 0x00000000);
6135 /* XXX : not implemented */
6136 spr_register(env, SPR_PMC6, "PMC6",
6137 SPR_NOACCESS, SPR_NOACCESS,
6138 &spr_read_generic, &spr_write_generic,
6139 0x00000000);
6140 /* XXX : not implemented */
6141 spr_register(env, SPR_UPMC6, "UPMC6",
6142 &spr_read_ureg, SPR_NOACCESS,
6143 &spr_read_ureg, SPR_NOACCESS,
6144 0x00000000);
6145 /* SPRGs */
6146 spr_register(env, SPR_SPRG4, "SPRG4",
6147 SPR_NOACCESS, SPR_NOACCESS,
6148 &spr_read_generic, &spr_write_generic,
6149 0x00000000);
6150 spr_register(env, SPR_USPRG4, "USPRG4",
6151 &spr_read_ureg, SPR_NOACCESS,
6152 &spr_read_ureg, SPR_NOACCESS,
6153 0x00000000);
6154 spr_register(env, SPR_SPRG5, "SPRG5",
6155 SPR_NOACCESS, SPR_NOACCESS,
6156 &spr_read_generic, &spr_write_generic,
6157 0x00000000);
6158 spr_register(env, SPR_USPRG5, "USPRG5",
6159 &spr_read_ureg, SPR_NOACCESS,
6160 &spr_read_ureg, SPR_NOACCESS,
6161 0x00000000);
6162 spr_register(env, SPR_SPRG6, "SPRG6",
6163 SPR_NOACCESS, SPR_NOACCESS,
6164 &spr_read_generic, &spr_write_generic,
6165 0x00000000);
6166 spr_register(env, SPR_USPRG6, "USPRG6",
6167 &spr_read_ureg, SPR_NOACCESS,
6168 &spr_read_ureg, SPR_NOACCESS,
6169 0x00000000);
6170 spr_register(env, SPR_SPRG7, "SPRG7",
6171 SPR_NOACCESS, SPR_NOACCESS,
6172 &spr_read_generic, &spr_write_generic,
6173 0x00000000);
6174 spr_register(env, SPR_USPRG7, "USPRG7",
6175 &spr_read_ureg, SPR_NOACCESS,
6176 &spr_read_ureg, SPR_NOACCESS,
6177 0x00000000);
6178 /* Memory management */
6179 gen_low_BATs(env);
6180 gen_high_BATs(env);
6181 gen_74xx_soft_tlb(env, 128, 2);
6182 init_excp_7450(env);
6183 env->dcache_line_size = 32;
6184 env->icache_line_size = 32;
6185 /* Allocate hardware IRQ controller */
6186 ppc6xx_irq_init(env);
6187 }
6188
6189 #if defined (TARGET_PPC64)
6190 /* PowerPC 970 */
6191 #define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6192 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6193 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6194 PPC_FLOAT_STFIWX | \
6195 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6196 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6197 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6198 PPC_64B | PPC_ALTIVEC | \
6199 PPC_SEGMENT_64B | PPC_SLBI)
6200 #define POWERPC_INSNS2_970 (PPC_NONE)
6201 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
6202 #define POWERPC_MMU_970 (POWERPC_MMU_64B)
6203 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
6204 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
6205 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
6206 #define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6207 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6208 POWERPC_FLAG_BUS_CLK)
6209
6210 #if defined(CONFIG_USER_ONLY)
6211 #define POWERPC970_HID5_INIT 0x00000080
6212 #else
6213 #define POWERPC970_HID5_INIT 0x00000000
6214 #endif
6215
6216 static int check_pow_970 (CPUPPCState *env)
6217 {
6218 if (env->spr[SPR_HID0] & 0x00600000)
6219 return 1;
6220
6221 return 0;
6222 }
6223
6224 static void init_proc_970 (CPUPPCState *env)
6225 {
6226 gen_spr_ne_601(env);
6227 gen_spr_7xx(env);
6228 /* Time base */
6229 gen_tbl(env);
6230 /* Hardware implementation registers */
6231 /* XXX : not implemented */
6232 spr_register(env, SPR_HID0, "HID0",
6233 SPR_NOACCESS, SPR_NOACCESS,
6234 &spr_read_generic, &spr_write_clear,
6235 0x60000000);
6236 /* XXX : not implemented */
6237 spr_register(env, SPR_HID1, "HID1",
6238 SPR_NOACCESS, SPR_NOACCESS,
6239 &spr_read_generic, &spr_write_generic,
6240 0x00000000);
6241 /* XXX : not implemented */
6242 spr_register(env, SPR_750FX_HID2, "HID2",
6243 SPR_NOACCESS, SPR_NOACCESS,
6244 &spr_read_generic, &spr_write_generic,
6245 0x00000000);
6246 /* XXX : not implemented */
6247 spr_register(env, SPR_970_HID5, "HID5",
6248 SPR_NOACCESS, SPR_NOACCESS,
6249 &spr_read_generic, &spr_write_generic,
6250 POWERPC970_HID5_INIT);
6251 /* XXX : not implemented */
6252 spr_register(env, SPR_L2CR, "L2CR",
6253 SPR_NOACCESS, SPR_NOACCESS,
6254 &spr_read_generic, &spr_write_generic,
6255 0x00000000);
6256 /* Memory management */
6257 /* XXX: not correct */
6258 gen_low_BATs(env);
6259 /* XXX : not implemented */
6260 spr_register(env, SPR_MMUCFG, "MMUCFG",
6261 SPR_NOACCESS, SPR_NOACCESS,
6262 &spr_read_generic, SPR_NOACCESS,
6263 0x00000000); /* TOFIX */
6264 /* XXX : not implemented */
6265 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6266 SPR_NOACCESS, SPR_NOACCESS,
6267 &spr_read_generic, &spr_write_generic,
6268 0x00000000); /* TOFIX */
6269 spr_register(env, SPR_HIOR, "SPR_HIOR",
6270 SPR_NOACCESS, SPR_NOACCESS,
6271 &spr_read_hior, &spr_write_hior,
6272 0x00000000);
6273 #if !defined(CONFIG_USER_ONLY)
6274 env->slb_nr = 32;
6275 #endif
6276 init_excp_970(env);
6277 env->dcache_line_size = 128;
6278 env->icache_line_size = 128;
6279 /* Allocate hardware IRQ controller */
6280 ppc970_irq_init(env);
6281 /* Can't find information on what this should be on reset. This
6282 * value is the one used by 74xx processors. */
6283 vscr_init(env, 0x00010000);
6284 }
6285
6286 /* PowerPC 970FX (aka G5) */
6287 #define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6288 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6289 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6290 PPC_FLOAT_STFIWX | \
6291 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6292 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6293 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6294 PPC_64B | PPC_ALTIVEC | \
6295 PPC_SEGMENT_64B | PPC_SLBI)
6296 #define POWERPC_INSNS2_970FX (PPC_NONE)
6297 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
6298 #define POWERPC_MMU_970FX (POWERPC_MMU_64B)
6299 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
6300 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
6301 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
6302 #define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6303 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6304 POWERPC_FLAG_BUS_CLK)
6305
6306 static int check_pow_970FX (CPUPPCState *env)
6307 {
6308 if (env->spr[SPR_HID0] & 0x00600000)
6309 return 1;
6310
6311 return 0;
6312 }
6313
6314 static void init_proc_970FX (CPUPPCState *env)
6315 {
6316 gen_spr_ne_601(env);
6317 gen_spr_7xx(env);
6318 /* Time base */
6319 gen_tbl(env);
6320 /* Hardware implementation registers */
6321 /* XXX : not implemented */
6322 spr_register(env, SPR_HID0, "HID0",
6323 SPR_NOACCESS, SPR_NOACCESS,
6324 &spr_read_generic, &spr_write_clear,
6325 0x60000000);
6326 /* XXX : not implemented */
6327 spr_register(env, SPR_HID1, "HID1",
6328 SPR_NOACCESS, SPR_NOACCESS,
6329 &spr_read_generic, &spr_write_generic,
6330 0x00000000);
6331 /* XXX : not implemented */
6332 spr_register(env, SPR_750FX_HID2, "HID2",
6333 SPR_NOACCESS, SPR_NOACCESS,
6334 &spr_read_generic, &spr_write_generic,
6335 0x00000000);
6336 /* XXX : not implemented */
6337 spr_register(env, SPR_970_HID5, "HID5",
6338 SPR_NOACCESS, SPR_NOACCESS,
6339 &spr_read_generic, &spr_write_generic,
6340 POWERPC970_HID5_INIT);
6341 /* XXX : not implemented */
6342 spr_register(env, SPR_L2CR, "L2CR",
6343 SPR_NOACCESS, SPR_NOACCESS,
6344 &spr_read_generic, &spr_write_generic,
6345 0x00000000);
6346 /* Memory management */
6347 /* XXX: not correct */
6348 gen_low_BATs(env);
6349 /* XXX : not implemented */
6350 spr_register(env, SPR_MMUCFG, "MMUCFG",
6351 SPR_NOACCESS, SPR_NOACCESS,
6352 &spr_read_generic, SPR_NOACCESS,
6353 0x00000000); /* TOFIX */
6354 /* XXX : not implemented */
6355 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6356 SPR_NOACCESS, SPR_NOACCESS,
6357 &spr_read_generic, &spr_write_generic,
6358 0x00000000); /* TOFIX */
6359 spr_register(env, SPR_HIOR, "SPR_HIOR",
6360 SPR_NOACCESS, SPR_NOACCESS,
6361 &spr_read_hior, &spr_write_hior,
6362 0x00000000);
6363 spr_register(env, SPR_CTRL, "SPR_CTRL",
6364 SPR_NOACCESS, SPR_NOACCESS,
6365 &spr_read_generic, &spr_write_generic,
6366 0x00000000);
6367 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6368 SPR_NOACCESS, SPR_NOACCESS,
6369 &spr_read_generic, &spr_write_generic,
6370 0x00000000);
6371 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6372 &spr_read_generic, &spr_write_generic,
6373 &spr_read_generic, &spr_write_generic,
6374 0x00000000);
6375 #if !defined(CONFIG_USER_ONLY)
6376 env->slb_nr = 64;
6377 #endif
6378 init_excp_970(env);
6379 env->dcache_line_size = 128;
6380 env->icache_line_size = 128;
6381 /* Allocate hardware IRQ controller */
6382 ppc970_irq_init(env);
6383 /* Can't find information on what this should be on reset. This
6384 * value is the one used by 74xx processors. */
6385 vscr_init(env, 0x00010000);
6386 }
6387
6388 /* PowerPC 970 GX */
6389 #define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6390 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6391 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6392 PPC_FLOAT_STFIWX | \
6393 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6394 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6395 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6396 PPC_64B | PPC_ALTIVEC | \
6397 PPC_SEGMENT_64B | PPC_SLBI)
6398 #define POWERPC_INSNS2_970GX (PPC_NONE)
6399 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
6400 #define POWERPC_MMU_970GX (POWERPC_MMU_64B)
6401 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6402 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
6403 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
6404 #define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6405 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6406 POWERPC_FLAG_BUS_CLK)
6407
6408 static int check_pow_970GX (CPUPPCState *env)
6409 {
6410 if (env->spr[SPR_HID0] & 0x00600000)
6411 return 1;
6412
6413 return 0;
6414 }
6415
6416 static void init_proc_970GX (CPUPPCState *env)
6417 {
6418 gen_spr_ne_601(env);
6419 gen_spr_7xx(env);
6420 /* Time base */
6421 gen_tbl(env);
6422 /* Hardware implementation registers */
6423 /* XXX : not implemented */
6424 spr_register(env, SPR_HID0, "HID0",
6425 SPR_NOACCESS, SPR_NOACCESS,
6426 &spr_read_generic, &spr_write_clear,
6427 0x60000000);
6428 /* XXX : not implemented */
6429 spr_register(env, SPR_HID1, "HID1",
6430 SPR_NOACCESS, SPR_NOACCESS,
6431 &spr_read_generic, &spr_write_generic,
6432 0x00000000);
6433 /* XXX : not implemented */
6434 spr_register(env, SPR_750FX_HID2, "HID2",
6435 SPR_NOACCESS, SPR_NOACCESS,
6436 &spr_read_generic, &spr_write_generic,
6437 0x00000000);
6438 /* XXX : not implemented */
6439 spr_register(env, SPR_970_HID5, "HID5",
6440 SPR_NOACCESS, SPR_NOACCESS,
6441 &spr_read_generic, &spr_write_generic,
6442 POWERPC970_HID5_INIT);
6443 /* XXX : not implemented */
6444 spr_register(env, SPR_L2CR, "L2CR",
6445 SPR_NOACCESS, SPR_NOACCESS,
6446 &spr_read_generic, &spr_write_generic,
6447 0x00000000);
6448 /* Memory management */
6449 /* XXX: not correct */
6450 gen_low_BATs(env);
6451 /* XXX : not implemented */
6452 spr_register(env, SPR_MMUCFG, "MMUCFG",
6453 SPR_NOACCESS, SPR_NOACCESS,
6454 &spr_read_generic, SPR_NOACCESS,
6455 0x00000000); /* TOFIX */
6456 /* XXX : not implemented */
6457 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6458 SPR_NOACCESS, SPR_NOACCESS,
6459 &spr_read_generic, &spr_write_generic,
6460 0x00000000); /* TOFIX */
6461 spr_register(env, SPR_HIOR, "SPR_HIOR",
6462 SPR_NOACCESS, SPR_NOACCESS,
6463 &spr_read_hior, &spr_write_hior,
6464 0x00000000);
6465 #if !defined(CONFIG_USER_ONLY)
6466 env->slb_nr = 32;
6467 #endif
6468 init_excp_970(env);
6469 env->dcache_line_size = 128;
6470 env->icache_line_size = 128;
6471 /* Allocate hardware IRQ controller */
6472 ppc970_irq_init(env);
6473 /* Can't find information on what this should be on reset. This
6474 * value is the one used by 74xx processors. */
6475 vscr_init(env, 0x00010000);
6476 }
6477
6478 /* PowerPC 970 MP */
6479 #define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6480 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6481 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6482 PPC_FLOAT_STFIWX | \
6483 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6484 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6485 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6486 PPC_64B | PPC_ALTIVEC | \
6487 PPC_SEGMENT_64B | PPC_SLBI)
6488 #define POWERPC_INSNS2_970MP (PPC_NONE)
6489 #define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6490 #define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6491 #define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6492 #define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6493 #define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6494 #define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6495 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6496 POWERPC_FLAG_BUS_CLK)
6497
6498 static int check_pow_970MP (CPUPPCState *env)
6499 {
6500 if (env->spr[SPR_HID0] & 0x01C00000)
6501 return 1;
6502
6503 return 0;
6504 }
6505
6506 static void init_proc_970MP (CPUPPCState *env)
6507 {
6508 gen_spr_ne_601(env);
6509 gen_spr_7xx(env);
6510 /* Time base */
6511 gen_tbl(env);
6512 /* Hardware implementation registers */
6513 /* XXX : not implemented */
6514 spr_register(env, SPR_HID0, "HID0",
6515 SPR_NOACCESS, SPR_NOACCESS,
6516 &spr_read_generic, &spr_write_clear,
6517 0x60000000);
6518 /* XXX : not implemented */
6519 spr_register(env, SPR_HID1, "HID1",
6520 SPR_NOACCESS, SPR_NOACCESS,
6521 &spr_read_generic, &spr_write_generic,
6522 0x00000000);
6523 /* XXX : not implemented */
6524 spr_register(env, SPR_750FX_HID2, "HID2",
6525 SPR_NOACCESS, SPR_NOACCESS,
6526 &spr_read_generic, &spr_write_generic,
6527 0x00000000);
6528 /* XXX : not implemented */
6529 spr_register(env, SPR_970_HID5, "HID5",
6530 SPR_NOACCESS, SPR_NOACCESS,
6531 &spr_read_generic, &spr_write_generic,
6532 POWERPC970_HID5_INIT);
6533 /* XXX : not implemented */
6534 spr_register(env, SPR_L2CR, "L2CR",
6535 SPR_NOACCESS, SPR_NOACCESS,
6536 &spr_read_generic, &spr_write_generic,
6537 0x00000000);
6538 /* Memory management */
6539 /* XXX: not correct */
6540 gen_low_BATs(env);
6541 /* XXX : not implemented */
6542 spr_register(env, SPR_MMUCFG, "MMUCFG",
6543 SPR_NOACCESS, SPR_NOACCESS,
6544 &spr_read_generic, SPR_NOACCESS,
6545 0x00000000); /* TOFIX */
6546 /* XXX : not implemented */
6547 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6548 SPR_NOACCESS, SPR_NOACCESS,
6549 &spr_read_generic, &spr_write_generic,
6550 0x00000000); /* TOFIX */
6551 spr_register(env, SPR_HIOR, "SPR_HIOR",
6552 SPR_NOACCESS, SPR_NOACCESS,
6553 &spr_read_hior, &spr_write_hior,
6554 0x00000000);
6555 #if !defined(CONFIG_USER_ONLY)
6556 env->slb_nr = 32;
6557 #endif
6558 init_excp_970(env);
6559 env->dcache_line_size = 128;
6560 env->icache_line_size = 128;
6561 /* Allocate hardware IRQ controller */
6562 ppc970_irq_init(env);
6563 /* Can't find information on what this should be on reset. This
6564 * value is the one used by 74xx processors. */
6565 vscr_init(env, 0x00010000);
6566 }
6567
6568 #if defined(TARGET_PPC64)
6569 /* POWER7 */
6570 #define POWERPC_INSNS_POWER7 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6571 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6572 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6573 PPC_FLOAT_STFIWX | \
6574 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6575 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6576 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6577 PPC_64B | PPC_ALTIVEC | \
6578 PPC_SEGMENT_64B | PPC_SLBI | \
6579 PPC_POPCNTB | PPC_POPCNTWD)
6580 #define POWERPC_INSNS2_POWER7 (PPC2_VSX | PPC2_DFP | PPC2_DBRX)
6581 #define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
6582 #define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
6583 #define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
6584 #define POWERPC_INPUT_POWER7 (PPC_FLAGS_INPUT_POWER7)
6585 #define POWERPC_BFDM_POWER7 (bfd_mach_ppc64)
6586 #define POWERPC_FLAG_POWER7 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6587 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6588 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR)
6589 #define check_pow_POWER7 check_pow_nocheck
6590
6591 static void init_proc_POWER7 (CPUPPCState *env)
6592 {
6593 gen_spr_ne_601(env);
6594 gen_spr_7xx(env);
6595 /* Time base */
6596 gen_tbl(env);
6597 /* Processor identification */
6598 spr_register(env, SPR_PIR, "PIR",
6599 SPR_NOACCESS, SPR_NOACCESS,
6600 &spr_read_generic, &spr_write_pir,
6601 0x00000000);
6602 #if !defined(CONFIG_USER_ONLY)
6603 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6604 spr_register(env, SPR_PURR, "PURR",
6605 &spr_read_purr, SPR_NOACCESS,
6606 &spr_read_purr, SPR_NOACCESS,
6607 0x00000000);
6608 spr_register(env, SPR_SPURR, "SPURR",
6609 &spr_read_purr, SPR_NOACCESS,
6610 &spr_read_purr, SPR_NOACCESS,
6611 0x00000000);
6612 spr_register(env, SPR_CFAR, "SPR_CFAR",
6613 SPR_NOACCESS, SPR_NOACCESS,
6614 &spr_read_cfar, &spr_write_cfar,
6615 0x00000000);
6616 spr_register(env, SPR_DSCR, "SPR_DSCR",
6617 SPR_NOACCESS, SPR_NOACCESS,
6618 &spr_read_generic, &spr_write_generic,
6619 0x00000000);
6620 #endif /* !CONFIG_USER_ONLY */
6621 /* Memory management */
6622 /* XXX : not implemented */
6623 spr_register(env, SPR_MMUCFG, "MMUCFG",
6624 SPR_NOACCESS, SPR_NOACCESS,
6625 &spr_read_generic, SPR_NOACCESS,
6626 0x00000000); /* TOFIX */
6627 /* XXX : not implemented */
6628 spr_register(env, SPR_CTRL, "SPR_CTRLT",
6629 SPR_NOACCESS, SPR_NOACCESS,
6630 &spr_read_generic, &spr_write_generic,
6631 0x80800000);
6632 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
6633 SPR_NOACCESS, SPR_NOACCESS,
6634 &spr_read_generic, &spr_write_generic,
6635 0x80800000);
6636 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6637 &spr_read_generic, &spr_write_generic,
6638 &spr_read_generic, &spr_write_generic,
6639 0x00000000);
6640 #if !defined(CONFIG_USER_ONLY)
6641 env->slb_nr = 32;
6642 #endif
6643 init_excp_POWER7(env);
6644 env->dcache_line_size = 128;
6645 env->icache_line_size = 128;
6646 /* Allocate hardware IRQ controller */
6647 ppcPOWER7_irq_init(env);
6648 /* Can't find information on what this should be on reset. This
6649 * value is the one used by 74xx processors. */
6650 vscr_init(env, 0x00010000);
6651 }
6652 #endif /* TARGET_PPC64 */
6653
6654 /* PowerPC 620 */
6655 #define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6656 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6657 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6658 PPC_FLOAT_STFIWX | \
6659 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6660 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6661 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6662 PPC_SEGMENT | PPC_EXTERN | \
6663 PPC_64B | PPC_SLBI)
6664 #define POWERPC_INSNS2_620 (PPC_NONE)
6665 #define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6666 //#define POWERPC_MMU_620 (POWERPC_MMU_620)
6667 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
6668 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
6669 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
6670 #define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
6671 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
6672 #define check_pow_620 check_pow_nocheck /* Check this */
6673
6674 __attribute__ (( unused ))
6675 static void init_proc_620 (CPUPPCState *env)
6676 {
6677 gen_spr_ne_601(env);
6678 gen_spr_620(env);
6679 /* Time base */
6680 gen_tbl(env);
6681 /* Hardware implementation registers */
6682 /* XXX : not implemented */
6683 spr_register(env, SPR_HID0, "HID0",
6684 SPR_NOACCESS, SPR_NOACCESS,
6685 &spr_read_generic, &spr_write_generic,
6686 0x00000000);
6687 /* Memory management */
6688 gen_low_BATs(env);
6689 init_excp_620(env);
6690 env->dcache_line_size = 64;
6691 env->icache_line_size = 64;
6692 /* Allocate hardware IRQ controller */
6693 ppc6xx_irq_init(env);
6694 }
6695 #endif /* defined (TARGET_PPC64) */
6696
6697 /* Default 32 bits PowerPC target will be 604 */
6698 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
6699 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
6700 #define POWERPC_INSNS2_PPC32 POWERPC_INSNS2_604
6701 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6702 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
6703 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6704 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
6705 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
6706 #define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
6707 #define check_pow_PPC32 check_pow_604
6708 #define init_proc_PPC32 init_proc_604
6709
6710 /* Default 64 bits PowerPC target will be 970 FX */
6711 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6712 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
6713 #define POWERPC_INSNS2_PPC64 POWERPC_INSNS2_970FX
6714 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6715 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6716 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6717 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
6718 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
6719 #define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
6720 #define check_pow_PPC64 check_pow_970FX
6721 #define init_proc_PPC64 init_proc_970FX
6722
6723 /* Default PowerPC target will be PowerPC 32 */
6724 #if defined (TARGET_PPC64) && 0 // XXX: TODO
6725 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6726 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6727 #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS2_PPC64
6728 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6729 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6730 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6731 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6732 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
6733 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
6734 #define check_pow_DEFAULT check_pow_PPC64
6735 #define init_proc_DEFAULT init_proc_PPC64
6736 #else
6737 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6738 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6739 #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS2_PPC32
6740 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6741 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6742 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6743 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6744 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
6745 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
6746 #define check_pow_DEFAULT check_pow_PPC32
6747 #define init_proc_DEFAULT init_proc_PPC32
6748 #endif
6749
6750 /*****************************************************************************/
6751 /* PVR definitions for most known PowerPC */
6752 enum {
6753 /* PowerPC 401 family */
6754 /* Generic PowerPC 401 */
6755 #define CPU_POWERPC_401 CPU_POWERPC_401G2
6756 /* PowerPC 401 cores */
6757 CPU_POWERPC_401A1 = 0x00210000,
6758 CPU_POWERPC_401B2 = 0x00220000,
6759 #if 0
6760 CPU_POWERPC_401B3 = xxx,
6761 #endif
6762 CPU_POWERPC_401C2 = 0x00230000,
6763 CPU_POWERPC_401D2 = 0x00240000,
6764 CPU_POWERPC_401E2 = 0x00250000,
6765 CPU_POWERPC_401F2 = 0x00260000,
6766 CPU_POWERPC_401G2 = 0x00270000,
6767 /* PowerPC 401 microcontrolers */
6768 #if 0
6769 CPU_POWERPC_401GF = xxx,
6770 #endif
6771 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
6772 /* IBM Processor for Network Resources */
6773 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
6774 #if 0
6775 CPU_POWERPC_XIPCHIP = xxx,
6776 #endif
6777 /* PowerPC 403 family */
6778 /* Generic PowerPC 403 */
6779 #define CPU_POWERPC_403 CPU_POWERPC_403GC
6780 /* PowerPC 403 microcontrollers */
6781 CPU_POWERPC_403GA = 0x00200011,
6782 CPU_POWERPC_403GB = 0x00200100,
6783 CPU_POWERPC_403GC = 0x00200200,
6784 CPU_POWERPC_403GCX = 0x00201400,
6785 #if 0
6786 CPU_POWERPC_403GP = xxx,
6787 #endif
6788 /* PowerPC 405 family */
6789 /* Generic PowerPC 405 */
6790 #define CPU_POWERPC_405 CPU_POWERPC_405D4
6791 /* PowerPC 405 cores */
6792 #if 0
6793 CPU_POWERPC_405A3 = xxx,
6794 #endif
6795 #if 0
6796 CPU_POWERPC_405A4 = xxx,
6797 #endif
6798 #if 0
6799 CPU_POWERPC_405B3 = xxx,
6800 #endif
6801 #if 0
6802 CPU_POWERPC_405B4 = xxx,
6803 #endif
6804 #if 0
6805 CPU_POWERPC_405C3 = xxx,
6806 #endif
6807 #if 0
6808 CPU_POWERPC_405C4 = xxx,
6809 #endif
6810 CPU_POWERPC_405D2 = 0x20010000,
6811 #if 0
6812 CPU_POWERPC_405D3 = xxx,
6813 #endif
6814 CPU_POWERPC_405D4 = 0x41810000,
6815 #if 0
6816 CPU_POWERPC_405D5 = xxx,
6817 #endif
6818 #if 0
6819 CPU_POWERPC_405E4 = xxx,
6820 #endif
6821 #if 0
6822 CPU_POWERPC_405F4 = xxx,
6823 #endif
6824 #if 0
6825 CPU_POWERPC_405F5 = xxx,
6826 #endif
6827 #if 0
6828 CPU_POWERPC_405F6 = xxx,
6829 #endif
6830 /* PowerPC 405 microcontrolers */
6831 /* XXX: missing 0x200108a0 */
6832 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6833 CPU_POWERPC_405CRa = 0x40110041,
6834 CPU_POWERPC_405CRb = 0x401100C5,
6835 CPU_POWERPC_405CRc = 0x40110145,
6836 CPU_POWERPC_405EP = 0x51210950,
6837 #if 0
6838 CPU_POWERPC_405EXr = xxx,
6839 #endif
6840 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
6841 #if 0
6842 CPU_POWERPC_405FX = xxx,
6843 #endif
6844 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6845 CPU_POWERPC_405GPa = 0x40110000,
6846 CPU_POWERPC_405GPb = 0x40110040,
6847 CPU_POWERPC_405GPc = 0x40110082,
6848 CPU_POWERPC_405GPd = 0x401100C4,
6849 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6850 CPU_POWERPC_405GPR = 0x50910951,
6851 #if 0
6852 CPU_POWERPC_405H = xxx,
6853 #endif
6854 #if 0
6855 CPU_POWERPC_405L = xxx,
6856 #endif
6857 CPU_POWERPC_405LP = 0x41F10000,
6858 #if 0
6859 CPU_POWERPC_405PM = xxx,
6860 #endif
6861 #if 0
6862 CPU_POWERPC_405PS = xxx,
6863 #endif
6864 #if 0
6865 CPU_POWERPC_405S = xxx,
6866 #endif
6867 /* IBM network processors */
6868 CPU_POWERPC_NPE405H = 0x414100C0,
6869 CPU_POWERPC_NPE405H2 = 0x41410140,
6870 CPU_POWERPC_NPE405L = 0x416100C0,
6871 CPU_POWERPC_NPE4GS3 = 0x40B10000,
6872 #if 0
6873 CPU_POWERPC_NPCxx1 = xxx,
6874 #endif
6875 #if 0
6876 CPU_POWERPC_NPR161 = xxx,
6877 #endif
6878 #if 0
6879 CPU_POWERPC_LC77700 = xxx,
6880 #endif
6881 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6882 #if 0
6883 CPU_POWERPC_STB01000 = xxx,
6884 #endif
6885 #if 0
6886 CPU_POWERPC_STB01010 = xxx,
6887 #endif
6888 #if 0
6889 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
6890 #endif
6891 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
6892 #if 0
6893 CPU_POWERPC_STB043 = xxx,
6894 #endif
6895 #if 0
6896 CPU_POWERPC_STB045 = xxx,
6897 #endif
6898 CPU_POWERPC_STB04 = 0x41810000,
6899 CPU_POWERPC_STB25 = 0x51510950,
6900 #if 0
6901 CPU_POWERPC_STB130 = xxx,
6902 #endif
6903 /* Xilinx cores */
6904 CPU_POWERPC_X2VP4 = 0x20010820,
6905 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
6906 CPU_POWERPC_X2VP20 = 0x20010860,
6907 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
6908 #if 0
6909 CPU_POWERPC_ZL10310 = xxx,
6910 #endif
6911 #if 0
6912 CPU_POWERPC_ZL10311 = xxx,
6913 #endif
6914 #if 0
6915 CPU_POWERPC_ZL10320 = xxx,
6916 #endif
6917 #if 0
6918 CPU_POWERPC_ZL10321 = xxx,
6919 #endif
6920 /* PowerPC 440 family */
6921 /* Generic PowerPC 440 */
6922 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
6923 /* PowerPC 440 cores */
6924 #if 0
6925 CPU_POWERPC_440A4 = xxx,
6926 #endif
6927 CPU_POWERPC_440_XILINX = 0x7ff21910,
6928 #if 0
6929 CPU_POWERPC_440A5 = xxx,
6930 #endif
6931 #if 0
6932 CPU_POWERPC_440B4 = xxx,
6933 #endif
6934 #if 0
6935 CPU_POWERPC_440F5 = xxx,
6936 #endif
6937 #if 0
6938 CPU_POWERPC_440G5 = xxx,
6939 #endif
6940 #if 0
6941 CPU_POWERPC_440H4 = xxx,
6942 #endif
6943 #if 0
6944 CPU_POWERPC_440H6 = xxx,
6945 #endif
6946 /* PowerPC 440 microcontrolers */
6947 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
6948 CPU_POWERPC_440EPa = 0x42221850,
6949 CPU_POWERPC_440EPb = 0x422218D3,
6950 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
6951 CPU_POWERPC_440GPb = 0x40120440,
6952 CPU_POWERPC_440GPc = 0x40120481,
6953 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
6954 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
6955 CPU_POWERPC_440GRX = 0x200008D0,
6956 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
6957 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
6958 CPU_POWERPC_440GXa = 0x51B21850,
6959 CPU_POWERPC_440GXb = 0x51B21851,
6960 CPU_POWERPC_440GXc = 0x51B21892,
6961 CPU_POWERPC_440GXf = 0x51B21894,
6962 #if 0
6963 CPU_POWERPC_440S = xxx,
6964 #endif
6965 CPU_POWERPC_440SP = 0x53221850,
6966 CPU_POWERPC_440SP2 = 0x53221891,
6967 CPU_POWERPC_440SPE = 0x53421890,
6968 /* PowerPC 460 family */
6969 #if 0
6970 /* Generic PowerPC 464 */
6971 #define CPU_POWERPC_464 CPU_POWERPC_464H90
6972 #endif
6973 /* PowerPC 464 microcontrolers */
6974 #if 0
6975 CPU_POWERPC_464H90 = xxx,
6976 #endif
6977 #if 0
6978 CPU_POWERPC_464H90FP = xxx,
6979 #endif
6980 /* Freescale embedded PowerPC cores */
6981 /* PowerPC MPC 5xx cores (aka RCPU) */
6982 CPU_POWERPC_MPC5xx = 0x00020020,
6983 #define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
6984 #define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
6985 #define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
6986 #define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
6987 #define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
6988 #define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
6989 #define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
6990 #define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
6991 #define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
6992 #define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
6993 #define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
6994 #define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
6995 #define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
6996 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
6997 CPU_POWERPC_MPC8xx = 0x00500000,
6998 #define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
6999 #define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
7000 #define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
7001 #define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
7002 #define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
7003 #define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
7004 #define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
7005 #define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
7006 #define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
7007 #define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
7008 #define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
7009 #define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
7010 #define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
7011 #define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
7012 #define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
7013 /* G2 cores (aka PowerQUICC-II) */
7014 CPU_POWERPC_G2 = 0x00810011,
7015 CPU_POWERPC_G2H4 = 0x80811010,
7016 CPU_POWERPC_G2gp = 0x80821010,
7017 CPU_POWERPC_G2ls = 0x90810010,
7018 CPU_POWERPC_MPC603 = 0x00810100,
7019 CPU_POWERPC_G2_HIP3 = 0x00810101,
7020 CPU_POWERPC_G2_HIP4 = 0x80811014,
7021 /* G2_LE core (aka PowerQUICC-II) */
7022 CPU_POWERPC_G2LE = 0x80820010,
7023 CPU_POWERPC_G2LEgp = 0x80822010,
7024 CPU_POWERPC_G2LEls = 0xA0822010,
7025 CPU_POWERPC_G2LEgp1 = 0x80822011,
7026 CPU_POWERPC_G2LEgp3 = 0x80822013,
7027 /* MPC52xx microcontrollers */
7028 /* XXX: MPC 5121 ? */
7029 #define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
7030 #define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
7031 #define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
7032 #define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
7033 #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
7034 #define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
7035 #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
7036 #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
7037 /* MPC82xx microcontrollers */
7038 #define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
7039 #define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
7040 #define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
7041 #define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
7042 #define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
7043 #define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
7044 #define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
7045 #define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
7046 #define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
7047 #define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
7048 #define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
7049 #define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
7050 #define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
7051 #define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
7052 #define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
7053 #define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
7054 #define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
7055 #define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
7056 #define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
7057 #define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
7058 #define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
7059 #define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
7060 #define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
7061 #define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
7062 #define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
7063 #define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
7064 #define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
7065 #define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
7066 #define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
7067 /* e200 family */
7068 /* e200 cores */
7069 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
7070 #if 0
7071 CPU_POWERPC_e200z0 = xxx,
7072 #endif
7073 #if 0
7074 CPU_POWERPC_e200z1 = xxx,
7075 #endif
7076 #if 0 /* ? */
7077 CPU_POWERPC_e200z3 = 0x81120000,
7078 #endif
7079 CPU_POWERPC_e200z5 = 0x81000000,
7080 CPU_POWERPC_e200z6 = 0x81120000,
7081 /* MPC55xx microcontrollers */
7082 #define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
7083 #if 0
7084 #define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
7085 #define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
7086 #define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
7087 #define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
7088 #define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
7089 #define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
7090 #define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
7091 #define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
7092 #define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
7093 #define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
7094 #define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
7095 #define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
7096 #define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
7097 #define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
7098 #endif
7099 #if 0
7100 #define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
7101 #define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
7102 #endif
7103 #define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
7104 #define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
7105 #define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
7106 #define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
7107 #define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
7108 #define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
7109 /* e300 family */
7110 /* e300 cores */
7111 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
7112 CPU_POWERPC_e300c1 = 0x00830010,
7113 CPU_POWERPC_e300c2 = 0x00840010,
7114 CPU_POWERPC_e300c3 = 0x00850010,
7115 CPU_POWERPC_e300c4 = 0x00860010,
7116 /* MPC83xx microcontrollers */
7117 #define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
7118 #define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
7119 #define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
7120 #define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
7121 #define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
7122 #define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
7123 /* e500 family */
7124 /* e500 cores */
7125 #define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
7126 #define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
7127 #define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
7128 CPU_POWERPC_e500v1_v10 = 0x80200010,
7129 CPU_POWERPC_e500v1_v20 = 0x80200020,
7130 CPU_POWERPC_e500v2_v10 = 0x80210010,
7131 CPU_POWERPC_e500v2_v11 = 0x80210011,
7132 CPU_POWERPC_e500v2_v20 = 0x80210020,
7133 CPU_POWERPC_e500v2_v21 = 0x80210021,
7134 CPU_POWERPC_e500v2_v22 = 0x80210022,
7135 CPU_POWERPC_e500v2_v30 = 0x80210030,
7136 CPU_POWERPC_e500mc = 0x80230020,
7137 /* MPC85xx microcontrollers */
7138 #define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
7139 #define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
7140 #define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
7141 #define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
7142 #define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
7143 #define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
7144 #define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
7145 #define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
7146 #define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
7147 #define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
7148 #define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
7149 #define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
7150 #define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
7151 #define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
7152 #define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
7153 #define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
7154 #define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
7155 #define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
7156 #define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
7157 #define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
7158 #define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
7159 #define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
7160 #define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
7161 #define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
7162 #define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
7163 #define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
7164 #define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
7165 #define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
7166 #define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
7167 #define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
7168 #define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
7169 #define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
7170 #define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
7171 #define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
7172 #define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
7173 #define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
7174 #define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
7175 #define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
7176 #define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
7177 #define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
7178 #define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
7179 #define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
7180 #define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
7181 #define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
7182 #define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
7183 #define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
7184 #define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
7185 #define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
7186 #define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
7187 #define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
7188 #define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
7189 #define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
7190 #define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
7191 #define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
7192 #define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
7193 #define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
7194 #define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
7195 #define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
7196 #define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
7197 #define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
7198 #define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
7199 #define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
7200 #define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
7201 #define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
7202 #define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
7203 #define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
7204 #define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
7205 #define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
7206 #define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
7207 #define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
7208 /* e600 family */
7209 /* e600 cores */
7210 CPU_POWERPC_e600 = 0x80040010,
7211 /* MPC86xx microcontrollers */
7212 #define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
7213 #define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
7214 #define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
7215 /* PowerPC 6xx cores */
7216 #define CPU_POWERPC_601 CPU_POWERPC_601_v2
7217 CPU_POWERPC_601_v0 = 0x00010001,
7218 CPU_POWERPC_601_v1 = 0x00010001,
7219 #define CPU_POWERPC_601v CPU_POWERPC_601_v2
7220 CPU_POWERPC_601_v2 = 0x00010002,
7221 CPU_POWERPC_602 = 0x00050100,
7222 CPU_POWERPC_603 = 0x00030100,
7223 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
7224 CPU_POWERPC_603E_v11 = 0x00060101,
7225 CPU_POWERPC_603E_v12 = 0x00060102,
7226 CPU_POWERPC_603E_v13 = 0x00060103,
7227 CPU_POWERPC_603E_v14 = 0x00060104,
7228 CPU_POWERPC_603E_v22 = 0x00060202,
7229 CPU_POWERPC_603E_v3 = 0x00060300,
7230 CPU_POWERPC_603E_v4 = 0x00060400,
7231 CPU_POWERPC_603E_v41 = 0x00060401,
7232 CPU_POWERPC_603E7t = 0x00071201,
7233 CPU_POWERPC_603E7v = 0x00070100,
7234 CPU_POWERPC_603E7v1 = 0x00070101,
7235 CPU_POWERPC_603E7v2 = 0x00070201,
7236 CPU_POWERPC_603E7 = 0x00070200,
7237 CPU_POWERPC_603P = 0x00070000,
7238 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
7239 /* XXX: missing 0x00040303 (604) */
7240 CPU_POWERPC_604 = 0x00040103,
7241 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
7242 /* XXX: missing 0x00091203 */
7243 /* XXX: missing 0x00092110 */
7244 /* XXX: missing 0x00092120 */
7245 CPU_POWERPC_604E_v10 = 0x00090100,
7246 CPU_POWERPC_604E_v22 = 0x00090202,
7247 CPU_POWERPC_604E_v24 = 0x00090204,
7248 /* XXX: missing 0x000a0100 */
7249 /* XXX: missing 0x00093102 */
7250 CPU_POWERPC_604R = 0x000a0101,
7251 #if 0
7252 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
7253 #endif
7254 /* PowerPC 740/750 cores (aka G3) */
7255 /* XXX: missing 0x00084202 */
7256 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
7257 CPU_POWERPC_7x0_v10 = 0x00080100,
7258 CPU_POWERPC_7x0_v20 = 0x00080200,
7259 CPU_POWERPC_7x0_v21 = 0x00080201,
7260 CPU_POWERPC_7x0_v22 = 0x00080202,
7261 CPU_POWERPC_7x0_v30 = 0x00080300,
7262 CPU_POWERPC_7x0_v31 = 0x00080301,
7263 CPU_POWERPC_740E = 0x00080100,
7264 CPU_POWERPC_750E = 0x00080200,
7265 CPU_POWERPC_7x0P = 0x10080000,
7266 /* XXX: missing 0x00087010 (CL ?) */
7267 #define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
7268 CPU_POWERPC_750CL_v10 = 0x00087200,
7269 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
7270 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
7271 CPU_POWERPC_750CX_v10 = 0x00082100,
7272 CPU_POWERPC_750CX_v20 = 0x00082200,
7273 CPU_POWERPC_750CX_v21 = 0x00082201,
7274 CPU_POWERPC_750CX_v22 = 0x00082202,
7275 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
7276 CPU_POWERPC_750CXE_v21 = 0x00082211,
7277 CPU_POWERPC_750CXE_v22 = 0x00082212,
7278 CPU_POWERPC_750CXE_v23 = 0x00082213,
7279 CPU_POWERPC_750CXE_v24 = 0x00082214,
7280 CPU_POWERPC_750CXE_v24b = 0x00083214,
7281 CPU_POWERPC_750CXE_v30 = 0x00082310,
7282 CPU_POWERPC_750CXE_v31 = 0x00082311,
7283 CPU_POWERPC_750CXE_v31b = 0x00083311,
7284 CPU_POWERPC_750CXR = 0x00083410,
7285 CPU_POWERPC_750FL = 0x70000203,
7286 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
7287 CPU_POWERPC_750FX_v10 = 0x70000100,
7288 CPU_POWERPC_750FX_v20 = 0x70000200,
7289 CPU_POWERPC_750FX_v21 = 0x70000201,
7290 CPU_POWERPC_750FX_v22 = 0x70000202,
7291 CPU_POWERPC_750FX_v23 = 0x70000203,
7292 CPU_POWERPC_750GL = 0x70020102,
7293 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
7294 CPU_POWERPC_750GX_v10 = 0x70020100,
7295 CPU_POWERPC_750GX_v11 = 0x70020101,
7296 CPU_POWERPC_750GX_v12 = 0x70020102,
7297 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
7298 CPU_POWERPC_750L_v20 = 0x00088200,
7299 CPU_POWERPC_750L_v21 = 0x00088201,
7300 CPU_POWERPC_750L_v22 = 0x00088202,
7301 CPU_POWERPC_750L_v30 = 0x00088300,
7302 CPU_POWERPC_750L_v32 = 0x00088302,
7303 /* PowerPC 745/755 cores */
7304 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
7305 CPU_POWERPC_7x5_v10 = 0x00083100,
7306 CPU_POWERPC_7x5_v11 = 0x00083101,
7307 CPU_POWERPC_7x5_v20 = 0x00083200,
7308 CPU_POWERPC_7x5_v21 = 0x00083201,
7309 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
7310 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
7311 CPU_POWERPC_7x5_v24 = 0x00083204,
7312 CPU_POWERPC_7x5_v25 = 0x00083205,
7313 CPU_POWERPC_7x5_v26 = 0x00083206,
7314 CPU_POWERPC_7x5_v27 = 0x00083207,
7315 CPU_POWERPC_7x5_v28 = 0x00083208,
7316 #if 0
7317 CPU_POWERPC_7x5P = xxx,
7318 #endif
7319 /* PowerPC 74xx cores (aka G4) */
7320 /* XXX: missing 0x000C1101 */
7321 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
7322 CPU_POWERPC_7400_v10 = 0x000C0100,
7323 CPU_POWERPC_7400_v11 = 0x000C0101,
7324 CPU_POWERPC_7400_v20 = 0x000C0200,
7325 CPU_POWERPC_7400_v21 = 0x000C0201,
7326 CPU_POWERPC_7400_v22 = 0x000C0202,
7327 CPU_POWERPC_7400_v26 = 0x000C0206,
7328 CPU_POWERPC_7400_v27 = 0x000C0207,
7329 CPU_POWERPC_7400_v28 = 0x000C0208,
7330 CPU_POWERPC_7400_v29 = 0x000C0209,
7331 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
7332 CPU_POWERPC_7410_v10 = 0x800C1100,
7333 CPU_POWERPC_7410_v11 = 0x800C1101,
7334 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
7335 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
7336 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
7337 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
7338 CPU_POWERPC_7448_v10 = 0x80040100,
7339 CPU_POWERPC_7448_v11 = 0x80040101,
7340 CPU_POWERPC_7448_v20 = 0x80040200,
7341 CPU_POWERPC_7448_v21 = 0x80040201,
7342 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
7343 CPU_POWERPC_7450_v10 = 0x80000100,
7344 CPU_POWERPC_7450_v11 = 0x80000101,
7345 CPU_POWERPC_7450_v12 = 0x80000102,
7346 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
7347 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
7348 #define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
7349 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
7350 /* XXX: this entry might be a bug in some documentation */
7351 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
7352 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
7353 CPU_POWERPC_74x5_v10 = 0x80010100,
7354 /* XXX: missing 0x80010200 */
7355 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
7356 CPU_POWERPC_74x5_v32 = 0x80010302,
7357 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
7358 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
7359 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
7360 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
7361 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
7362 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
7363 #define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
7364 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
7365 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
7366 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
7367 /* 64 bits PowerPC */
7368 #if defined(TARGET_PPC64)
7369 CPU_POWERPC_620 = 0x00140000,
7370 CPU_POWERPC_630 = 0x00400000,
7371 CPU_POWERPC_631 = 0x00410104,
7372 CPU_POWERPC_POWER4 = 0x00350000,
7373 CPU_POWERPC_POWER4P = 0x00380000,
7374 /* XXX: missing 0x003A0201 */
7375 CPU_POWERPC_POWER5 = 0x003A0203,
7376 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
7377 CPU_POWERPC_POWER5P = 0x003B0000,
7378 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
7379 CPU_POWERPC_POWER6 = 0x003E0000,
7380 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
7381 CPU_POWERPC_POWER6A = 0x0F000002,
7382 #define CPU_POWERPC_POWER7 CPU_POWERPC_POWER7_v20
7383 CPU_POWERPC_POWER7_v20 = 0x003F0200,
7384 CPU_POWERPC_POWER7_v21 = 0x003F0201,
7385 CPU_POWERPC_POWER7_v23 = 0x003F0203,
7386 CPU_POWERPC_970 = 0x00390202,
7387 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
7388 CPU_POWERPC_970FX_v10 = 0x00391100,
7389 CPU_POWERPC_970FX_v20 = 0x003C0200,
7390 CPU_POWERPC_970FX_v21 = 0x003C0201,
7391 CPU_POWERPC_970FX_v30 = 0x003C0300,
7392 CPU_POWERPC_970FX_v31 = 0x003C0301,
7393 CPU_POWERPC_970GX = 0x00450000,
7394 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
7395 CPU_POWERPC_970MP_v10 = 0x00440100,
7396 CPU_POWERPC_970MP_v11 = 0x00440101,
7397 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
7398 CPU_POWERPC_CELL_v10 = 0x00700100,
7399 CPU_POWERPC_CELL_v20 = 0x00700400,
7400 CPU_POWERPC_CELL_v30 = 0x00700500,
7401 CPU_POWERPC_CELL_v31 = 0x00700501,
7402 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
7403 CPU_POWERPC_RS64 = 0x00330000,
7404 CPU_POWERPC_RS64II = 0x00340000,
7405 CPU_POWERPC_RS64III = 0x00360000,
7406 CPU_POWERPC_RS64IV = 0x00370000,
7407 #endif /* defined(TARGET_PPC64) */
7408 /* Original POWER */
7409 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7410 * POWER2 (RIOS2) & RSC2 (P2SC) here
7411 */
7412 #if 0
7413 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
7414 #endif
7415 #if 0
7416 CPU_POWER2 = xxx, /* 0x40000 ? */
7417 #endif
7418 /* PA Semi core */
7419 CPU_POWERPC_PA6T = 0x00900000,
7420 };
7421
7422 /* System version register (used on MPC 8xxx) */
7423 enum {
7424 POWERPC_SVR_NONE = 0x00000000,
7425 #define POWERPC_SVR_52xx POWERPC_SVR_5200
7426 #define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
7427 POWERPC_SVR_5200_v10 = 0x80110010,
7428 POWERPC_SVR_5200_v11 = 0x80110011,
7429 POWERPC_SVR_5200_v12 = 0x80110012,
7430 #define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
7431 POWERPC_SVR_5200B_v20 = 0x80110020,
7432 POWERPC_SVR_5200B_v21 = 0x80110021,
7433 #define POWERPC_SVR_55xx POWERPC_SVR_5567
7434 #if 0
7435 POWERPC_SVR_5533 = xxx,
7436 #endif
7437 #if 0
7438 POWERPC_SVR_5534 = xxx,
7439 #endif
7440 #if 0
7441 POWERPC_SVR_5553 = xxx,
7442 #endif
7443 #if 0
7444 POWERPC_SVR_5554 = xxx,
7445 #endif
7446 #if 0
7447 POWERPC_SVR_5561 = xxx,
7448 #endif
7449 #if 0
7450 POWERPC_SVR_5565 = xxx,
7451 #endif
7452 #if 0
7453 POWERPC_SVR_5566 = xxx,
7454 #endif
7455 #if 0
7456 POWERPC_SVR_5567 = xxx,
7457 #endif
7458 #if 0
7459 POWERPC_SVR_8313 = xxx,
7460 #endif
7461 #if 0
7462 POWERPC_SVR_8313E = xxx,
7463 #endif
7464 #if 0
7465 POWERPC_SVR_8314 = xxx,
7466 #endif
7467 #if 0
7468 POWERPC_SVR_8314E = xxx,
7469 #endif
7470 #if 0
7471 POWERPC_SVR_8315 = xxx,
7472 #endif
7473 #if 0
7474 POWERPC_SVR_8315E = xxx,
7475 #endif
7476 #if 0
7477 POWERPC_SVR_8321 = xxx,
7478 #endif
7479 #if 0
7480 POWERPC_SVR_8321E = xxx,
7481 #endif
7482 #if 0
7483 POWERPC_SVR_8323 = xxx,
7484 #endif
7485 #if 0
7486 POWERPC_SVR_8323E = xxx,
7487 #endif
7488 POWERPC_SVR_8343 = 0x80570010,
7489 POWERPC_SVR_8343A = 0x80570030,
7490 POWERPC_SVR_8343E = 0x80560010,
7491 POWERPC_SVR_8343EA = 0x80560030,
7492 #define POWERPC_SVR_8347 POWERPC_SVR_8347T
7493 POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
7494 POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
7495 #define POWERPC_SVR_8347A POWERPC_SVR_8347AT
7496 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7497 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
7498 #define POWERPC_SVR_8347E POWERPC_SVR_8347ET
7499 POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
7500 POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
7501 #define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
7502 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7503 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7504 POWERPC_SVR_8349 = 0x80510010,
7505 POWERPC_SVR_8349A = 0x80510030,
7506 POWERPC_SVR_8349E = 0x80500010,
7507 POWERPC_SVR_8349EA = 0x80500030,
7508 #if 0
7509 POWERPC_SVR_8358E = xxx,
7510 #endif
7511 #if 0
7512 POWERPC_SVR_8360E = xxx,
7513 #endif
7514 #define POWERPC_SVR_E500 0x40000000
7515 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7516 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7517 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7518 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7519 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7520 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
7521 #define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
7522 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7523 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
7524 #define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
7525 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7526 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
7527 #define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
7528 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7529 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7530 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
7531 #define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
7532 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7533 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
7534 #define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
7535 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7536 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
7537 #define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
7538 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7539 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7540 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7541 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
7542 #define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
7543 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7544 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7545 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7546 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
7547 #define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
7548 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7549 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
7550 #define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
7551 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7552 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
7553 #define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
7554 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7555 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
7556 #define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
7557 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7558 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
7559 #define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
7560 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7561 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
7562 #define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
7563 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7564 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7565 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7566 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
7567 #define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
7568 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7569 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7570 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7571 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
7572 #define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
7573 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7574 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
7575 #define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
7576 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7577 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
7578 #define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
7579 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7580 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7581 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7582 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7583 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7584 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7585 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7586 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7587 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
7588 #if 0
7589 POWERPC_SVR_8610 = xxx,
7590 #endif
7591 POWERPC_SVR_8641 = 0x80900021,
7592 POWERPC_SVR_8641D = 0x80900121,
7593 };
7594
7595 /*****************************************************************************/
7596 /* PowerPC CPU definitions */
7597 #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
7598 { \
7599 .name = _name, \
7600 .pvr = _pvr, \
7601 .svr = _svr, \
7602 .insns_flags = glue(POWERPC_INSNS_,_type), \
7603 .insns_flags2 = glue(POWERPC_INSNS2_,_type), \
7604 .msr_mask = glue(POWERPC_MSRM_,_type), \
7605 .mmu_model = glue(POWERPC_MMU_,_type), \
7606 .excp_model = glue(POWERPC_EXCP_,_type), \
7607 .bus_model = glue(POWERPC_INPUT_,_type), \
7608 .bfd_mach = glue(POWERPC_BFDM_,_type), \
7609 .flags = glue(POWERPC_FLAG_,_type), \
7610 .init_proc = &glue(init_proc_,_type), \
7611 .check_pow = &glue(check_pow_,_type), \
7612 }
7613 #define POWERPC_DEF(_name, _pvr, _type) \
7614 POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
7615
7616 static const ppc_def_t ppc_defs[] = {
7617 /* Embedded PowerPC */
7618 /* PowerPC 401 family */
7619 /* Generic PowerPC 401 */
7620 POWERPC_DEF("401", CPU_POWERPC_401, 401),
7621 /* PowerPC 401 cores */
7622 /* PowerPC 401A1 */
7623 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
7624 /* PowerPC 401B2 */
7625 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
7626 #if defined (TODO)
7627 /* PowerPC 401B3 */
7628 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
7629 #endif
7630 /* PowerPC 401C2 */
7631 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
7632 /* PowerPC 401D2 */
7633 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
7634 /* PowerPC 401E2 */
7635 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
7636 /* PowerPC 401F2 */
7637 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
7638 /* PowerPC 401G2 */
7639 /* XXX: to be checked */
7640 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
7641 /* PowerPC 401 microcontrolers */
7642 #if defined (TODO)
7643 /* PowerPC 401GF */
7644 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
7645 #endif
7646 /* IOP480 (401 microcontroler) */
7647 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
7648 /* IBM Processor for Network Resources */
7649 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
7650 #if defined (TODO)
7651 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
7652 #endif
7653 /* PowerPC 403 family */
7654 /* Generic PowerPC 403 */
7655 POWERPC_DEF("403", CPU_POWERPC_403, 403),
7656 /* PowerPC 403 microcontrolers */
7657 /* PowerPC 403 GA */
7658 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
7659 /* PowerPC 403 GB */
7660 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
7661 /* PowerPC 403 GC */
7662 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
7663 /* PowerPC 403 GCX */
7664 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
7665 #if defined (TODO)
7666 /* PowerPC 403 GP */
7667 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
7668 #endif
7669 /* PowerPC 405 family */
7670 /* Generic PowerPC 405 */
7671 POWERPC_DEF("405", CPU_POWERPC_405, 405),
7672 /* PowerPC 405 cores */
7673 #if defined (TODO)
7674 /* PowerPC 405 A3 */
7675 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
7676 #endif
7677 #if defined (TODO)
7678 /* PowerPC 405 A4 */
7679 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
7680 #endif
7681 #if defined (TODO)
7682 /* PowerPC 405 B3 */
7683 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
7684 #endif
7685 #if defined (TODO)
7686 /* PowerPC 405 B4 */
7687 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
7688 #endif
7689 #if defined (TODO)
7690 /* PowerPC 405 C3 */
7691 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
7692 #endif
7693 #if defined (TODO)
7694 /* PowerPC 405 C4 */
7695 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
7696 #endif
7697 /* PowerPC 405 D2 */
7698 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
7699 #if defined (TODO)
7700 /* PowerPC 405 D3 */
7701 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
7702 #endif
7703 /* PowerPC 405 D4 */
7704 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
7705 #if defined (TODO)
7706 /* PowerPC 405 D5 */
7707 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
7708 #endif
7709 #if defined (TODO)
7710 /* PowerPC 405 E4 */
7711 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
7712 #endif
7713 #if defined (TODO)
7714 /* PowerPC 405 F4 */
7715 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
7716 #endif
7717 #if defined (TODO)
7718 /* PowerPC 405 F5 */
7719 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
7720 #endif
7721 #if defined (TODO)
7722 /* PowerPC 405 F6 */
7723 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
7724 #endif
7725 /* PowerPC 405 microcontrolers */
7726 /* PowerPC 405 CR */
7727 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
7728 /* PowerPC 405 CRa */
7729 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
7730 /* PowerPC 405 CRb */
7731 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
7732 /* PowerPC 405 CRc */
7733 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
7734 /* PowerPC 405 EP */
7735 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
7736 #if defined(TODO)
7737 /* PowerPC 405 EXr */
7738 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
7739 #endif
7740 /* PowerPC 405 EZ */
7741 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
7742 #if defined(TODO)
7743 /* PowerPC 405 FX */
7744 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
7745 #endif
7746 /* PowerPC 405 GP */
7747 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
7748 /* PowerPC 405 GPa */
7749 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
7750 /* PowerPC 405 GPb */
7751 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
7752 /* PowerPC 405 GPc */
7753 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
7754 /* PowerPC 405 GPd */
7755 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
7756 /* PowerPC 405 GPe */
7757 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
7758 /* PowerPC 405 GPR */
7759 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
7760 #if defined(TODO)
7761 /* PowerPC 405 H */
7762 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
7763 #endif
7764 #if defined(TODO)
7765 /* PowerPC 405 L */
7766 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
7767 #endif
7768 /* PowerPC 405 LP */
7769 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
7770 #if defined(TODO)
7771 /* PowerPC 405 PM */
7772 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
7773 #endif
7774 #if defined(TODO)
7775 /* PowerPC 405 PS */
7776 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
7777 #endif
7778 #if defined(TODO)
7779 /* PowerPC 405 S */
7780 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
7781 #endif
7782 /* Npe405 H */
7783 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
7784 /* Npe405 H2 */
7785 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
7786 /* Npe405 L */
7787 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
7788 /* Npe4GS3 */
7789 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
7790 #if defined (TODO)
7791 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
7792 #endif
7793 #if defined (TODO)
7794 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
7795 #endif
7796 #if defined (TODO)
7797 /* PowerPC LC77700 (Sanyo) */
7798 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
7799 #endif
7800 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7801 #if defined (TODO)
7802 /* STB010000 */
7803 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
7804 #endif
7805 #if defined (TODO)
7806 /* STB01010 */
7807 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
7808 #endif
7809 #if defined (TODO)
7810 /* STB0210 */
7811 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
7812 #endif
7813 /* STB03xx */
7814 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
7815 #if defined (TODO)
7816 /* STB043x */
7817 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
7818 #endif
7819 #if defined (TODO)
7820 /* STB045x */
7821 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
7822 #endif
7823 /* STB04xx */
7824 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
7825 /* STB25xx */
7826 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
7827 #if defined (TODO)
7828 /* STB130 */
7829 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
7830 #endif
7831 /* Xilinx PowerPC 405 cores */
7832 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
7833 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
7834 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
7835 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
7836 #if defined (TODO)
7837 /* Zarlink ZL10310 */
7838 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
7839 #endif
7840 #if defined (TODO)
7841 /* Zarlink ZL10311 */
7842 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
7843 #endif
7844 #if defined (TODO)
7845 /* Zarlink ZL10320 */
7846 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
7847 #endif
7848 #if defined (TODO)
7849 /* Zarlink ZL10321 */
7850 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
7851 #endif
7852 /* PowerPC 440 family */
7853 #if defined(TODO_USER_ONLY)
7854 /* Generic PowerPC 440 */
7855 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
7856 #endif
7857 /* PowerPC 440 cores */
7858 #if defined (TODO)
7859 /* PowerPC 440 A4 */
7860 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
7861 #endif
7862 /* PowerPC 440 Xilinx 5 */
7863 POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5),
7864 #if defined (TODO)
7865 /* PowerPC 440 A5 */
7866 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
7867 #endif
7868 #if defined (TODO)
7869 /* PowerPC 440 B4 */
7870 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
7871 #endif
7872 #if defined (TODO)
7873 /* PowerPC 440 G4 */
7874 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
7875 #endif
7876 #if defined (TODO)
7877 /* PowerPC 440 F5 */
7878 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
7879 #endif
7880 #if defined (TODO)
7881 /* PowerPC 440 G5 */
7882 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
7883 #endif
7884 #if defined (TODO)
7885 /* PowerPC 440H4 */
7886 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
7887 #endif
7888 #if defined (TODO)
7889 /* PowerPC 440H6 */
7890 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
7891 #endif
7892 /* PowerPC 440 microcontrolers */
7893 /* PowerPC 440 EP */
7894 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
7895 /* PowerPC 440 EPa */
7896 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
7897 /* PowerPC 440 EPb */
7898 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
7899 /* PowerPC 440 EPX */
7900 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
7901 #if defined(TODO_USER_ONLY)
7902 /* PowerPC 440 GP */
7903 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
7904 #endif
7905 #if defined(TODO_USER_ONLY)
7906 /* PowerPC 440 GPb */
7907 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
7908 #endif
7909 #if defined(TODO_USER_ONLY)
7910 /* PowerPC 440 GPc */
7911 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
7912 #endif
7913 #if defined(TODO_USER_ONLY)
7914 /* PowerPC 440 GR */
7915 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
7916 #endif
7917 #if defined(TODO_USER_ONLY)
7918 /* PowerPC 440 GRa */
7919 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
7920 #endif
7921 #if defined(TODO_USER_ONLY)
7922 /* PowerPC 440 GRX */
7923 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
7924 #endif
7925 #if defined(TODO_USER_ONLY)
7926 /* PowerPC 440 GX */
7927 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
7928 #endif
7929 #if defined(TODO_USER_ONLY)
7930 /* PowerPC 440 GXa */
7931 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
7932 #endif
7933 #if defined(TODO_USER_ONLY)
7934 /* PowerPC 440 GXb */
7935 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
7936 #endif
7937 #if defined(TODO_USER_ONLY)
7938 /* PowerPC 440 GXc */
7939 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
7940 #endif
7941 #if defined(TODO_USER_ONLY)
7942 /* PowerPC 440 GXf */
7943 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
7944 #endif
7945 #if defined(TODO)
7946 /* PowerPC 440 S */
7947 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
7948 #endif
7949 #if defined(TODO_USER_ONLY)
7950 /* PowerPC 440 SP */
7951 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
7952 #endif
7953 #if defined(TODO_USER_ONLY)
7954 /* PowerPC 440 SP2 */
7955 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
7956 #endif
7957 #if defined(TODO_USER_ONLY)
7958 /* PowerPC 440 SPE */
7959 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
7960 #endif
7961 /* PowerPC 460 family */
7962 #if defined (TODO)
7963 /* Generic PowerPC 464 */
7964 POWERPC_DEF("464", CPU_POWERPC_464, 460),
7965 #endif
7966 /* PowerPC 464 microcontrolers */
7967 #if defined (TODO)
7968 /* PowerPC 464H90 */
7969 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
7970 #endif
7971 #if defined (TODO)
7972 /* PowerPC 464H90F */
7973 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
7974 #endif
7975 /* Freescale embedded PowerPC cores */
7976 /* MPC5xx family (aka RCPU) */
7977 #if defined(TODO_USER_ONLY)
7978 /* Generic MPC5xx core */
7979 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
7980 #endif
7981 #if defined(TODO_USER_ONLY)
7982 /* Codename for MPC5xx core */
7983 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
7984 #endif
7985 /* MPC5xx microcontrollers */
7986 #if defined(TODO_USER_ONLY)
7987 /* MGT560 */
7988 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
7989 #endif
7990 #if defined(TODO_USER_ONLY)
7991 /* MPC509 */
7992 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
7993 #endif
7994 #if defined(TODO_USER_ONLY)
7995 /* MPC533 */
7996 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
7997 #endif
7998 #if defined(TODO_USER_ONLY)
7999 /* MPC534 */
8000 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
8001 #endif
8002 #if defined(TODO_USER_ONLY)
8003 /* MPC555 */
8004 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
8005 #endif
8006 #if defined(TODO_USER_ONLY)
8007 /* MPC556 */
8008 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
8009 #endif
8010 #if defined(TODO_USER_ONLY)
8011 /* MPC560 */
8012 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
8013 #endif
8014 #if defined(TODO_USER_ONLY)
8015 /* MPC561 */
8016 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
8017 #endif
8018 #if defined(TODO_USER_ONLY)
8019 /* MPC562 */
8020 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
8021 #endif
8022 #if defined(TODO_USER_ONLY)
8023 /* MPC563 */
8024 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
8025 #endif
8026 #if defined(TODO_USER_ONLY)
8027 /* MPC564 */
8028 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
8029 #endif
8030 #if defined(TODO_USER_ONLY)
8031 /* MPC565 */
8032 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
8033 #endif
8034 #if defined(TODO_USER_ONLY)
8035 /* MPC566 */
8036 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
8037 #endif
8038 /* MPC8xx family (aka PowerQUICC) */
8039 #if defined(TODO_USER_ONLY)
8040 /* Generic MPC8xx core */
8041 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
8042 #endif
8043 #if defined(TODO_USER_ONLY)
8044 /* Codename for MPC8xx core */
8045 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
8046 #endif
8047 /* MPC8xx microcontrollers */
8048 #if defined(TODO_USER_ONLY)
8049 /* MGT823 */
8050 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
8051 #endif
8052 #if defined(TODO_USER_ONLY)
8053 /* MPC821 */
8054 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
8055 #endif
8056 #if defined(TODO_USER_ONLY)
8057 /* MPC823 */
8058 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
8059 #endif
8060 #if defined(TODO_USER_ONLY)
8061 /* MPC850 */
8062 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
8063 #endif
8064 #if defined(TODO_USER_ONLY)
8065 /* MPC852T */
8066 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
8067 #endif
8068 #if defined(TODO_USER_ONLY)
8069 /* MPC855T */
8070 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
8071 #endif
8072 #if defined(TODO_USER_ONLY)
8073 /* MPC857 */
8074 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
8075 #endif
8076 #if defined(TODO_USER_ONLY)
8077 /* MPC859 */
8078 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
8079 #endif
8080 #if defined(TODO_USER_ONLY)
8081 /* MPC860 */
8082 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
8083 #endif
8084 #if defined(TODO_USER_ONLY)
8085 /* MPC862 */
8086 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
8087 #endif
8088 #if defined(TODO_USER_ONLY)
8089 /* MPC866 */
8090 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
8091 #endif
8092 #if defined(TODO_USER_ONLY)
8093 /* MPC870 */
8094 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
8095 #endif
8096 #if defined(TODO_USER_ONLY)
8097 /* MPC875 */
8098 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
8099 #endif
8100 #if defined(TODO_USER_ONLY)
8101 /* MPC880 */
8102 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
8103 #endif
8104 #if defined(TODO_USER_ONLY)
8105 /* MPC885 */
8106 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
8107 #endif
8108 /* MPC82xx family (aka PowerQUICC-II) */
8109 /* Generic MPC52xx core */
8110 POWERPC_DEF_SVR("MPC52xx",
8111 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
8112 /* Generic MPC82xx core */
8113 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
8114 /* Codename for MPC82xx */
8115 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
8116 /* PowerPC G2 core */
8117 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
8118 /* PowerPC G2 H4 core */
8119 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
8120 /* PowerPC G2 GP core */
8121 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
8122 /* PowerPC G2 LS core */
8123 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
8124 /* PowerPC G2 HiP3 core */
8125 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
8126 /* PowerPC G2 HiP4 core */
8127 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
8128 /* PowerPC MPC603 core */
8129 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
8130 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
8131 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
8132 /* PowerPC G2LE GP core */
8133 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
8134 /* PowerPC G2LE LS core */
8135 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
8136 /* PowerPC G2LE GP1 core */
8137 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
8138 /* PowerPC G2LE GP3 core */
8139 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
8140 /* PowerPC MPC603 microcontrollers */
8141 /* MPC8240 */
8142 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
8143 /* PowerPC G2 microcontrollers */
8144 #if defined(TODO)
8145 /* MPC5121 */
8146 POWERPC_DEF_SVR("MPC5121",
8147 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
8148 #endif
8149 /* MPC5200 */
8150 POWERPC_DEF_SVR("MPC5200",
8151 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
8152 /* MPC5200 v1.0 */
8153 POWERPC_DEF_SVR("MPC5200_v10",
8154 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
8155 /* MPC5200 v1.1 */
8156 POWERPC_DEF_SVR("MPC5200_v11",
8157 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
8158 /* MPC5200 v1.2 */
8159 POWERPC_DEF_SVR("MPC5200_v12",
8160 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
8161 /* MPC5200B */
8162 POWERPC_DEF_SVR("MPC5200B",
8163 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
8164 /* MPC5200B v2.0 */
8165 POWERPC_DEF_SVR("MPC5200B_v20",
8166 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
8167 /* MPC5200B v2.1 */
8168 POWERPC_DEF_SVR("MPC5200B_v21",
8169 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
8170 /* MPC8241 */
8171 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
8172 /* MPC8245 */
8173 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
8174 /* MPC8247 */
8175 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
8176 /* MPC8248 */
8177 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
8178 /* MPC8250 */
8179 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
8180 /* MPC8250 HiP3 */
8181 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
8182 /* MPC8250 HiP4 */
8183 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
8184 /* MPC8255 */
8185 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
8186 /* MPC8255 HiP3 */
8187 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
8188 /* MPC8255 HiP4 */
8189 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
8190 /* MPC8260 */
8191 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
8192 /* MPC8260 HiP3 */
8193 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
8194 /* MPC8260 HiP4 */
8195 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
8196 /* MPC8264 */
8197 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
8198 /* MPC8264 HiP3 */
8199 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
8200 /* MPC8264 HiP4 */
8201 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
8202 /* MPC8265 */
8203 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
8204 /* MPC8265 HiP3 */
8205 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
8206 /* MPC8265 HiP4 */
8207 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
8208 /* MPC8266 */
8209 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
8210 /* MPC8266 HiP3 */
8211 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
8212 /* MPC8266 HiP4 */
8213 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
8214 /* MPC8270 */
8215 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
8216 /* MPC8271 */
8217 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
8218 /* MPC8272 */
8219 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
8220 /* MPC8275 */
8221 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
8222 /* MPC8280 */
8223 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
8224 /* e200 family */
8225 /* Generic PowerPC e200 core */
8226 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
8227 /* Generic MPC55xx core */
8228 #if defined (TODO)
8229 POWERPC_DEF_SVR("MPC55xx",
8230 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
8231 #endif
8232 #if defined (TODO)
8233 /* PowerPC e200z0 core */
8234 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
8235 #endif
8236 #if defined (TODO)
8237 /* PowerPC e200z1 core */
8238 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
8239 #endif
8240 #if defined (TODO)
8241 /* PowerPC e200z3 core */
8242 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
8243 #endif
8244 /* PowerPC e200z5 core */
8245 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
8246 /* PowerPC e200z6 core */
8247 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
8248 /* PowerPC e200 microcontrollers */
8249 #if defined (TODO)
8250 /* MPC5514E */
8251 POWERPC_DEF_SVR("MPC5514E",
8252 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
8253 #endif
8254 #if defined (TODO)
8255 /* MPC5514E v0 */
8256 POWERPC_DEF_SVR("MPC5514E_v0",
8257 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
8258 #endif
8259 #if defined (TODO)
8260 /* MPC5514E v1 */
8261 POWERPC_DEF_SVR("MPC5514E_v1",
8262 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
8263 #endif
8264 #if defined (TODO)
8265 /* MPC5514G */
8266 POWERPC_DEF_SVR("MPC5514G",
8267 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
8268 #endif
8269 #if defined (TODO)
8270 /* MPC5514G v0 */
8271 POWERPC_DEF_SVR("MPC5514G_v0",
8272 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
8273 #endif
8274 #if defined (TODO)
8275 /* MPC5514G v1 */
8276 POWERPC_DEF_SVR("MPC5514G_v1",
8277 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
8278 #endif
8279 #if defined (TODO)
8280 /* MPC5515S */
8281 POWERPC_DEF_SVR("MPC5515S",
8282 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
8283 #endif
8284 #if defined (TODO)
8285 /* MPC5516E */
8286 POWERPC_DEF_SVR("MPC5516E",
8287 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
8288 #endif
8289 #if defined (TODO)
8290 /* MPC5516E v0 */
8291 POWERPC_DEF_SVR("MPC5516E_v0",
8292 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
8293 #endif
8294 #if defined (TODO)
8295 /* MPC5516E v1 */
8296 POWERPC_DEF_SVR("MPC5516E_v1",
8297 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
8298 #endif
8299 #if defined (TODO)
8300 /* MPC5516G */
8301 POWERPC_DEF_SVR("MPC5516G",
8302 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
8303 #endif
8304 #if defined (TODO)
8305 /* MPC5516G v0 */
8306 POWERPC_DEF_SVR("MPC5516G_v0",
8307 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
8308 #endif
8309 #if defined (TODO)
8310 /* MPC5516G v1 */
8311 POWERPC_DEF_SVR("MPC5516G_v1",
8312 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
8313 #endif
8314 #if defined (TODO)
8315 /* MPC5516S */
8316 POWERPC_DEF_SVR("MPC5516S",
8317 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
8318 #endif
8319 #if defined (TODO)
8320 /* MPC5533 */
8321 POWERPC_DEF_SVR("MPC5533",
8322 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
8323 #endif
8324 #if defined (TODO)
8325 /* MPC5534 */
8326 POWERPC_DEF_SVR("MPC5534",
8327 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
8328 #endif
8329 #if defined (TODO)
8330 /* MPC5553 */
8331 POWERPC_DEF_SVR("MPC5553",
8332 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
8333 #endif
8334 #if defined (TODO)
8335 /* MPC5554 */
8336 POWERPC_DEF_SVR("MPC5554",
8337 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
8338 #endif
8339 #if defined (TODO)
8340 /* MPC5561 */
8341 POWERPC_DEF_SVR("MPC5561",
8342 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
8343 #endif
8344 #if defined (TODO)
8345 /* MPC5565 */
8346 POWERPC_DEF_SVR("MPC5565",
8347 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
8348 #endif
8349 #if defined (TODO)
8350 /* MPC5566 */
8351 POWERPC_DEF_SVR("MPC5566",
8352 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
8353 #endif
8354 #if defined (TODO)
8355 /* MPC5567 */
8356 POWERPC_DEF_SVR("MPC5567",
8357 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
8358 #endif
8359 /* e300 family */
8360 /* Generic PowerPC e300 core */
8361 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
8362 /* PowerPC e300c1 core */
8363 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
8364 /* PowerPC e300c2 core */
8365 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
8366 /* PowerPC e300c3 core */
8367 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
8368 /* PowerPC e300c4 core */
8369 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
8370 /* PowerPC e300 microcontrollers */
8371 #if defined (TODO)
8372 /* MPC8313 */
8373 POWERPC_DEF_SVR("MPC8313",
8374 CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300),
8375 #endif
8376 #if defined (TODO)
8377 /* MPC8313E */
8378 POWERPC_DEF_SVR("MPC8313E",
8379 CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300),
8380 #endif
8381 #if defined (TODO)
8382 /* MPC8314 */
8383 POWERPC_DEF_SVR("MPC8314",
8384 CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300),
8385 #endif
8386 #if defined (TODO)
8387 /* MPC8314E */
8388 POWERPC_DEF_SVR("MPC8314E",
8389 CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300),
8390 #endif
8391 #if defined (TODO)
8392 /* MPC8315 */
8393 POWERPC_DEF_SVR("MPC8315",
8394 CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300),
8395 #endif
8396 #if defined (TODO)
8397 /* MPC8315E */
8398 POWERPC_DEF_SVR("MPC8315E",
8399 CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300),
8400 #endif
8401 #if defined (TODO)
8402 /* MPC8321 */
8403 POWERPC_DEF_SVR("MPC8321",
8404 CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300),
8405 #endif
8406 #if defined (TODO)
8407 /* MPC8321E */
8408 POWERPC_DEF_SVR("MPC8321E",
8409 CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300),
8410 #endif
8411 #if defined (TODO)
8412 /* MPC8323 */
8413 POWERPC_DEF_SVR("MPC8323",
8414 CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300),
8415 #endif
8416 #if defined (TODO)
8417 /* MPC8323E */
8418 POWERPC_DEF_SVR("MPC8323E",
8419 CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300),
8420 #endif
8421 /* MPC8343 */
8422 POWERPC_DEF_SVR("MPC8343",
8423 CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300),
8424 /* MPC8343A */
8425 POWERPC_DEF_SVR("MPC8343A",
8426 CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300),
8427 /* MPC8343E */
8428 POWERPC_DEF_SVR("MPC8343E",
8429 CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300),
8430 /* MPC8343EA */
8431 POWERPC_DEF_SVR("MPC8343EA",
8432 CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300),
8433 /* MPC8347 */
8434 POWERPC_DEF_SVR("MPC8347",
8435 CPU_POWERPC_MPC834x, POWERPC_SVR_8347, e300),
8436 /* MPC8347T */
8437 POWERPC_DEF_SVR("MPC8347T",
8438 CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300),
8439 /* MPC8347P */
8440 POWERPC_DEF_SVR("MPC8347P",
8441 CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300),
8442 /* MPC8347A */
8443 POWERPC_DEF_SVR("MPC8347A",
8444 CPU_POWERPC_MPC834x, POWERPC_SVR_8347A, e300),
8445 /* MPC8347AT */
8446 POWERPC_DEF_SVR("MPC8347AT",
8447 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300),
8448 /* MPC8347AP */
8449 POWERPC_DEF_SVR("MPC8347AP",
8450 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300),
8451 /* MPC8347E */
8452 POWERPC_DEF_SVR("MPC8347E",
8453 CPU_POWERPC_MPC834x, POWERPC_SVR_8347E, e300),
8454 /* MPC8347ET */
8455 POWERPC_DEF_SVR("MPC8347ET",
8456 CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300),
8457 /* MPC8343EP */
8458 POWERPC_DEF_SVR("MPC8347EP",
8459 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300),
8460 /* MPC8347EA */
8461 POWERPC_DEF_SVR("MPC8347EA",
8462 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EA, e300),
8463 /* MPC8347EAT */
8464 POWERPC_DEF_SVR("MPC8347EAT",
8465 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300),
8466 /* MPC8343EAP */
8467 POWERPC_DEF_SVR("MPC8347EAP",
8468 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300),
8469 /* MPC8349 */
8470 POWERPC_DEF_SVR("MPC8349",
8471 CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300),
8472 /* MPC8349A */
8473 POWERPC_DEF_SVR("MPC8349A",
8474 CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300),
8475 /* MPC8349E */
8476 POWERPC_DEF_SVR("MPC8349E",
8477 CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300),
8478 /* MPC8349EA */
8479 POWERPC_DEF_SVR("MPC8349EA",
8480 CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300),
8481 #if defined (TODO)
8482 /* MPC8358E */
8483 POWERPC_DEF_SVR("MPC8358E",
8484 CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300),
8485 #endif
8486 #if defined (TODO)
8487 /* MPC8360E */
8488 POWERPC_DEF_SVR("MPC8360E",
8489 CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300),
8490 #endif
8491 /* MPC8377 */
8492 POWERPC_DEF_SVR("MPC8377",
8493 CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300),
8494 /* MPC8377E */
8495 POWERPC_DEF_SVR("MPC8377E",
8496 CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300),
8497 /* MPC8378 */
8498 POWERPC_DEF_SVR("MPC8378",
8499 CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300),
8500 /* MPC8378E */
8501 POWERPC_DEF_SVR("MPC8378E",
8502 CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300),
8503 /* MPC8379 */
8504 POWERPC_DEF_SVR("MPC8379",
8505 CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300),
8506 /* MPC8379E */
8507 POWERPC_DEF_SVR("MPC8379E",
8508 CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300),
8509 /* e500 family */
8510 /* PowerPC e500 core */
8511 POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2),
8512 /* PowerPC e500v1 core */
8513 POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1),
8514 /* PowerPC e500 v1.0 core */
8515 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1),
8516 /* PowerPC e500 v2.0 core */
8517 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1),
8518 /* PowerPC e500v2 core */
8519 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2),
8520 /* PowerPC e500v2 v1.0 core */
8521 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2),
8522 /* PowerPC e500v2 v2.0 core */
8523 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2),
8524 /* PowerPC e500v2 v2.1 core */
8525 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2),
8526 /* PowerPC e500v2 v2.2 core */
8527 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2),
8528 /* PowerPC e500v2 v3.0 core */
8529 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
8530 POWERPC_DEF("e500mc", CPU_POWERPC_e500mc, e500mc),
8531 /* PowerPC e500 microcontrollers */
8532 /* MPC8533 */
8533 POWERPC_DEF_SVR("MPC8533",
8534 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2),
8535 /* MPC8533 v1.0 */
8536 POWERPC_DEF_SVR("MPC8533_v10",
8537 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2),
8538 /* MPC8533 v1.1 */
8539 POWERPC_DEF_SVR("MPC8533_v11",
8540 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2),
8541 /* MPC8533E */
8542 POWERPC_DEF_SVR("MPC8533E",
8543 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2),
8544 /* MPC8533E v1.0 */
8545 POWERPC_DEF_SVR("MPC8533E_v10",
8546 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
8547 POWERPC_DEF_SVR("MPC8533E_v11",
8548 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
8549 /* MPC8540 */
8550 POWERPC_DEF_SVR("MPC8540",
8551 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1),
8552 /* MPC8540 v1.0 */
8553 POWERPC_DEF_SVR("MPC8540_v10",
8554 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1),
8555 /* MPC8540 v2.0 */
8556 POWERPC_DEF_SVR("MPC8540_v20",
8557 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1),
8558 /* MPC8540 v2.1 */
8559 POWERPC_DEF_SVR("MPC8540_v21",
8560 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1),
8561 /* MPC8541 */
8562 POWERPC_DEF_SVR("MPC8541",
8563 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1),
8564 /* MPC8541 v1.0 */
8565 POWERPC_DEF_SVR("MPC8541_v10",
8566 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1),
8567 /* MPC8541 v1.1 */
8568 POWERPC_DEF_SVR("MPC8541_v11",
8569 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1),
8570 /* MPC8541E */
8571 POWERPC_DEF_SVR("MPC8541E",
8572 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1),
8573 /* MPC8541E v1.0 */
8574 POWERPC_DEF_SVR("MPC8541E_v10",
8575 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
8576 /* MPC8541E v1.1 */
8577 POWERPC_DEF_SVR("MPC8541E_v11",
8578 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
8579 /* MPC8543 */
8580 POWERPC_DEF_SVR("MPC8543",
8581 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2),
8582 /* MPC8543 v1.0 */
8583 POWERPC_DEF_SVR("MPC8543_v10",
8584 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2),
8585 /* MPC8543 v1.1 */
8586 POWERPC_DEF_SVR("MPC8543_v11",
8587 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2),
8588 /* MPC8543 v2.0 */
8589 POWERPC_DEF_SVR("MPC8543_v20",
8590 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2),
8591 /* MPC8543 v2.1 */
8592 POWERPC_DEF_SVR("MPC8543_v21",
8593 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2),
8594 /* MPC8543E */
8595 POWERPC_DEF_SVR("MPC8543E",
8596 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2),
8597 /* MPC8543E v1.0 */
8598 POWERPC_DEF_SVR("MPC8543E_v10",
8599 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
8600 /* MPC8543E v1.1 */
8601 POWERPC_DEF_SVR("MPC8543E_v11",
8602 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
8603 /* MPC8543E v2.0 */
8604 POWERPC_DEF_SVR("MPC8543E_v20",
8605 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
8606 /* MPC8543E v2.1 */
8607 POWERPC_DEF_SVR("MPC8543E_v21",
8608 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
8609 /* MPC8544 */
8610 POWERPC_DEF_SVR("MPC8544",
8611 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2),
8612 /* MPC8544 v1.0 */
8613 POWERPC_DEF_SVR("MPC8544_v10",
8614 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2),
8615 /* MPC8544 v1.1 */
8616 POWERPC_DEF_SVR("MPC8544_v11",
8617 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2),
8618 /* MPC8544E */
8619 POWERPC_DEF_SVR("MPC8544E",
8620 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2),
8621 /* MPC8544E v1.0 */
8622 POWERPC_DEF_SVR("MPC8544E_v10",
8623 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
8624 /* MPC8544E v1.1 */
8625 POWERPC_DEF_SVR("MPC8544E_v11",
8626 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
8627 /* MPC8545 */
8628 POWERPC_DEF_SVR("MPC8545",
8629 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2),
8630 /* MPC8545 v2.0 */
8631 POWERPC_DEF_SVR("MPC8545_v20",
8632 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2),
8633 /* MPC8545 v2.1 */
8634 POWERPC_DEF_SVR("MPC8545_v21",
8635 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2),
8636 /* MPC8545E */
8637 POWERPC_DEF_SVR("MPC8545E",
8638 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2),
8639 /* MPC8545E v2.0 */
8640 POWERPC_DEF_SVR("MPC8545E_v20",
8641 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
8642 /* MPC8545E v2.1 */
8643 POWERPC_DEF_SVR("MPC8545E_v21",
8644 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
8645 /* MPC8547E */
8646 POWERPC_DEF_SVR("MPC8547E",
8647 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2),
8648 /* MPC8547E v2.0 */
8649 POWERPC_DEF_SVR("MPC8547E_v20",
8650 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
8651 /* MPC8547E v2.1 */
8652 POWERPC_DEF_SVR("MPC8547E_v21",
8653 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
8654 /* MPC8548 */
8655 POWERPC_DEF_SVR("MPC8548",
8656 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2),
8657 /* MPC8548 v1.0 */
8658 POWERPC_DEF_SVR("MPC8548_v10",
8659 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2),
8660 /* MPC8548 v1.1 */
8661 POWERPC_DEF_SVR("MPC8548_v11",
8662 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2),
8663 /* MPC8548 v2.0 */
8664 POWERPC_DEF_SVR("MPC8548_v20",
8665 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2),
8666 /* MPC8548 v2.1 */
8667 POWERPC_DEF_SVR("MPC8548_v21",
8668 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2),
8669 /* MPC8548E */
8670 POWERPC_DEF_SVR("MPC8548E",
8671 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2),
8672 /* MPC8548E v1.0 */
8673 POWERPC_DEF_SVR("MPC8548E_v10",
8674 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
8675 /* MPC8548E v1.1 */
8676 POWERPC_DEF_SVR("MPC8548E_v11",
8677 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
8678 /* MPC8548E v2.0 */
8679 POWERPC_DEF_SVR("MPC8548E_v20",
8680 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
8681 /* MPC8548E v2.1 */
8682 POWERPC_DEF_SVR("MPC8548E_v21",
8683 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
8684 /* MPC8555 */
8685 POWERPC_DEF_SVR("MPC8555",
8686 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2),
8687 /* MPC8555 v1.0 */
8688 POWERPC_DEF_SVR("MPC8555_v10",
8689 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2),
8690 /* MPC8555 v1.1 */
8691 POWERPC_DEF_SVR("MPC8555_v11",
8692 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2),
8693 /* MPC8555E */
8694 POWERPC_DEF_SVR("MPC8555E",
8695 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2),
8696 /* MPC8555E v1.0 */
8697 POWERPC_DEF_SVR("MPC8555E_v10",
8698 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
8699 /* MPC8555E v1.1 */
8700 POWERPC_DEF_SVR("MPC8555E_v11",
8701 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
8702 /* MPC8560 */
8703 POWERPC_DEF_SVR("MPC8560",
8704 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2),
8705 /* MPC8560 v1.0 */
8706 POWERPC_DEF_SVR("MPC8560_v10",
8707 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2),
8708 /* MPC8560 v2.0 */
8709 POWERPC_DEF_SVR("MPC8560_v20",
8710 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2),
8711 /* MPC8560 v2.1 */
8712 POWERPC_DEF_SVR("MPC8560_v21",
8713 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2),
8714 /* MPC8567 */
8715 POWERPC_DEF_SVR("MPC8567",
8716 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2),
8717 /* MPC8567E */
8718 POWERPC_DEF_SVR("MPC8567E",
8719 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2),
8720 /* MPC8568 */
8721 POWERPC_DEF_SVR("MPC8568",
8722 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2),
8723 /* MPC8568E */
8724 POWERPC_DEF_SVR("MPC8568E",
8725 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2),
8726 /* MPC8572 */
8727 POWERPC_DEF_SVR("MPC8572",
8728 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2),
8729 /* MPC8572E */
8730 POWERPC_DEF_SVR("MPC8572E",
8731 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2),
8732 /* e600 family */
8733 /* PowerPC e600 core */
8734 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
8735 /* PowerPC e600 microcontrollers */
8736 #if defined (TODO)
8737 /* MPC8610 */
8738 POWERPC_DEF_SVR("MPC8610",
8739 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
8740 #endif
8741 /* MPC8641 */
8742 POWERPC_DEF_SVR("MPC8641",
8743 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
8744 /* MPC8641D */
8745 POWERPC_DEF_SVR("MPC8641D",
8746 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
8747 /* 32 bits "classic" PowerPC */
8748 /* PowerPC 6xx family */
8749 /* PowerPC 601 */
8750 POWERPC_DEF("601", CPU_POWERPC_601, 601v),
8751 /* PowerPC 601v0 */
8752 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
8753 /* PowerPC 601v1 */
8754 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
8755 /* PowerPC 601v */
8756 POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
8757 /* PowerPC 601v2 */
8758 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
8759 /* PowerPC 602 */
8760 POWERPC_DEF("602", CPU_POWERPC_602, 602),
8761 /* PowerPC 603 */
8762 POWERPC_DEF("603", CPU_POWERPC_603, 603),
8763 /* Code name for PowerPC 603 */
8764 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
8765 /* PowerPC 603e (aka PID6) */
8766 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
8767 /* Code name for PowerPC 603e */
8768 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
8769 /* PowerPC 603e v1.1 */
8770 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
8771 /* PowerPC 603e v1.2 */
8772 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
8773 /* PowerPC 603e v1.3 */
8774 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
8775 /* PowerPC 603e v1.4 */
8776 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
8777 /* PowerPC 603e v2.2 */
8778 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
8779 /* PowerPC 603e v3 */
8780 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
8781 /* PowerPC 603e v4 */
8782 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
8783 /* PowerPC 603e v4.1 */
8784 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
8785 /* PowerPC 603e (aka PID7) */
8786 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
8787 /* PowerPC 603e7t */
8788 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
8789 /* PowerPC 603e7v */
8790 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
8791 /* Code name for PowerPC 603ev */
8792 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
8793 /* PowerPC 603e7v1 */
8794 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
8795 /* PowerPC 603e7v2 */
8796 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
8797 /* PowerPC 603p (aka PID7v) */
8798 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
8799 /* PowerPC 603r (aka PID7t) */
8800 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
8801 /* Code name for PowerPC 603r */
8802 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
8803 /* PowerPC 604 */
8804 POWERPC_DEF("604", CPU_POWERPC_604, 604),
8805 /* PowerPC 604e (aka PID9) */
8806 POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
8807 /* Code name for PowerPC 604e */
8808 POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
8809 /* PowerPC 604e v1.0 */
8810 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
8811 /* PowerPC 604e v2.2 */
8812 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
8813 /* PowerPC 604e v2.4 */
8814 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
8815 /* PowerPC 604r (aka PIDA) */
8816 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
8817 /* Code name for PowerPC 604r */
8818 POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
8819 #if defined(TODO)
8820 /* PowerPC 604ev */
8821 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
8822 #endif
8823 /* PowerPC 7xx family */
8824 /* Generic PowerPC 740 (G3) */
8825 POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
8826 /* Code name for PowerPC 740 */
8827 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
8828 /* Generic PowerPC 750 (G3) */
8829 POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
8830 /* Code name for PowerPC 750 */
8831 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
8832 /* PowerPC 740/750 is also known as G3 */
8833 POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
8834 /* PowerPC 740 v1.0 (G3) */
8835 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
8836 /* PowerPC 750 v1.0 (G3) */
8837 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
8838 /* PowerPC 740 v2.0 (G3) */
8839 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
8840 /* PowerPC 750 v2.0 (G3) */
8841 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
8842 /* PowerPC 740 v2.1 (G3) */
8843 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
8844 /* PowerPC 750 v2.1 (G3) */
8845 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
8846 /* PowerPC 740 v2.2 (G3) */
8847 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
8848 /* PowerPC 750 v2.2 (G3) */
8849 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
8850 /* PowerPC 740 v3.0 (G3) */
8851 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
8852 /* PowerPC 750 v3.0 (G3) */
8853 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
8854 /* PowerPC 740 v3.1 (G3) */
8855 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
8856 /* PowerPC 750 v3.1 (G3) */
8857 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
8858 /* PowerPC 740E (G3) */
8859 POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
8860 /* PowerPC 750E (G3) */
8861 POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
8862 /* PowerPC 740P (G3) */
8863 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
8864 /* PowerPC 750P (G3) */
8865 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
8866 /* Code name for PowerPC 740P/750P (G3) */
8867 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
8868 /* PowerPC 750CL (G3 embedded) */
8869 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
8870 /* PowerPC 750CL v1.0 */
8871 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
8872 /* PowerPC 750CL v2.0 */
8873 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
8874 /* PowerPC 750CX (G3 embedded) */
8875 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
8876 /* PowerPC 750CX v1.0 (G3 embedded) */
8877 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
8878 /* PowerPC 750CX v2.1 (G3 embedded) */
8879 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
8880 /* PowerPC 750CX v2.1 (G3 embedded) */
8881 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
8882 /* PowerPC 750CX v2.2 (G3 embedded) */
8883 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
8884 /* PowerPC 750CXe (G3 embedded) */
8885 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
8886 /* PowerPC 750CXe v2.1 (G3 embedded) */
8887 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
8888 /* PowerPC 750CXe v2.2 (G3 embedded) */
8889 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
8890 /* PowerPC 750CXe v2.3 (G3 embedded) */
8891 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
8892 /* PowerPC 750CXe v2.4 (G3 embedded) */
8893 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
8894 /* PowerPC 750CXe v2.4b (G3 embedded) */
8895 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
8896 /* PowerPC 750CXe v3.0 (G3 embedded) */
8897 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
8898 /* PowerPC 750CXe v3.1 (G3 embedded) */
8899 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
8900 /* PowerPC 750CXe v3.1b (G3 embedded) */
8901 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
8902 /* PowerPC 750CXr (G3 embedded) */
8903 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
8904 /* PowerPC 750FL (G3 embedded) */
8905 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
8906 /* PowerPC 750FX (G3 embedded) */
8907 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
8908 /* PowerPC 750FX v1.0 (G3 embedded) */
8909 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
8910 /* PowerPC 750FX v2.0 (G3 embedded) */
8911 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
8912 /* PowerPC 750FX v2.1 (G3 embedded) */
8913 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
8914 /* PowerPC 750FX v2.2 (G3 embedded) */
8915 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
8916 /* PowerPC 750FX v2.3 (G3 embedded) */
8917 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
8918 /* PowerPC 750GL (G3 embedded) */
8919 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
8920 /* PowerPC 750GX (G3 embedded) */
8921 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
8922 /* PowerPC 750GX v1.0 (G3 embedded) */
8923 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
8924 /* PowerPC 750GX v1.1 (G3 embedded) */
8925 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
8926 /* PowerPC 750GX v1.2 (G3 embedded) */
8927 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
8928 /* PowerPC 750L (G3 embedded) */
8929 POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
8930 /* Code name for PowerPC 750L (G3 embedded) */
8931 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
8932 /* PowerPC 750L v2.0 (G3 embedded) */
8933 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
8934 /* PowerPC 750L v2.1 (G3 embedded) */
8935 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
8936 /* PowerPC 750L v2.2 (G3 embedded) */
8937 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
8938 /* PowerPC 750L v3.0 (G3 embedded) */
8939 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
8940 /* PowerPC 750L v3.2 (G3 embedded) */
8941 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
8942 /* Generic PowerPC 745 */
8943 POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
8944 /* Generic PowerPC 755 */
8945 POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
8946 /* Code name for PowerPC 745/755 */
8947 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
8948 /* PowerPC 745 v1.0 */
8949 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
8950 /* PowerPC 755 v1.0 */
8951 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
8952 /* PowerPC 745 v1.1 */
8953 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
8954 /* PowerPC 755 v1.1 */
8955 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
8956 /* PowerPC 745 v2.0 */
8957 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
8958 /* PowerPC 755 v2.0 */
8959 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
8960 /* PowerPC 745 v2.1 */
8961 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
8962 /* PowerPC 755 v2.1 */
8963 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
8964 /* PowerPC 745 v2.2 */
8965 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
8966 /* PowerPC 755 v2.2 */
8967 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
8968 /* PowerPC 745 v2.3 */
8969 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
8970 /* PowerPC 755 v2.3 */
8971 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
8972 /* PowerPC 745 v2.4 */
8973 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
8974 /* PowerPC 755 v2.4 */
8975 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
8976 /* PowerPC 745 v2.5 */
8977 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
8978 /* PowerPC 755 v2.5 */
8979 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
8980 /* PowerPC 745 v2.6 */
8981 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
8982 /* PowerPC 755 v2.6 */
8983 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
8984 /* PowerPC 745 v2.7 */
8985 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
8986 /* PowerPC 755 v2.7 */
8987 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
8988 /* PowerPC 745 v2.8 */
8989 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
8990 /* PowerPC 755 v2.8 */
8991 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
8992 #if defined (TODO)
8993 /* PowerPC 745P (G3) */
8994 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
8995 /* PowerPC 755P (G3) */
8996 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
8997 #endif
8998 /* PowerPC 74xx family */
8999 /* PowerPC 7400 (G4) */
9000 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
9001 /* Code name for PowerPC 7400 */
9002 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
9003 /* PowerPC 74xx is also well known as G4 */
9004 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
9005 /* PowerPC 7400 v1.0 (G4) */
9006 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
9007 /* PowerPC 7400 v1.1 (G4) */
9008 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
9009 /* PowerPC 7400 v2.0 (G4) */
9010 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
9011 /* PowerPC 7400 v2.1 (G4) */
9012 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
9013 /* PowerPC 7400 v2.2 (G4) */
9014 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
9015 /* PowerPC 7400 v2.6 (G4) */
9016 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
9017 /* PowerPC 7400 v2.7 (G4) */
9018 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
9019 /* PowerPC 7400 v2.8 (G4) */
9020 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
9021 /* PowerPC 7400 v2.9 (G4) */
9022 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
9023 /* PowerPC 7410 (G4) */
9024 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
9025 /* Code name for PowerPC 7410 */
9026 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
9027 /* PowerPC 7410 v1.0 (G4) */
9028 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
9029 /* PowerPC 7410 v1.1 (G4) */
9030 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
9031 /* PowerPC 7410 v1.2 (G4) */
9032 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
9033 /* PowerPC 7410 v1.3 (G4) */
9034 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
9035 /* PowerPC 7410 v1.4 (G4) */
9036 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
9037 /* PowerPC 7448 (G4) */
9038 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
9039 /* PowerPC 7448 v1.0 (G4) */
9040 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
9041 /* PowerPC 7448 v1.1 (G4) */
9042 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
9043 /* PowerPC 7448 v2.0 (G4) */
9044 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
9045 /* PowerPC 7448 v2.1 (G4) */
9046 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
9047 /* PowerPC 7450 (G4) */
9048 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
9049 /* Code name for PowerPC 7450 */
9050 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
9051 /* PowerPC 7450 v1.0 (G4) */
9052 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
9053 /* PowerPC 7450 v1.1 (G4) */
9054 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
9055 /* PowerPC 7450 v1.2 (G4) */
9056 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
9057 /* PowerPC 7450 v2.0 (G4) */
9058 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
9059 /* PowerPC 7450 v2.1 (G4) */
9060 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
9061 /* PowerPC 7441 (G4) */
9062 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
9063 /* PowerPC 7451 (G4) */
9064 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
9065 /* PowerPC 7441 v2.1 (G4) */
9066 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
9067 /* PowerPC 7441 v2.3 (G4) */
9068 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
9069 /* PowerPC 7451 v2.3 (G4) */
9070 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
9071 /* PowerPC 7441 v2.10 (G4) */
9072 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
9073 /* PowerPC 7451 v2.10 (G4) */
9074 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
9075 /* PowerPC 7445 (G4) */
9076 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
9077 /* PowerPC 7455 (G4) */
9078 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
9079 /* Code name for PowerPC 7445/7455 */
9080 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
9081 /* PowerPC 7445 v1.0 (G4) */
9082 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
9083 /* PowerPC 7455 v1.0 (G4) */
9084 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
9085 /* PowerPC 7445 v2.1 (G4) */
9086 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
9087 /* PowerPC 7455 v2.1 (G4) */
9088 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
9089 /* PowerPC 7445 v3.2 (G4) */
9090 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
9091 /* PowerPC 7455 v3.2 (G4) */
9092 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
9093 /* PowerPC 7445 v3.3 (G4) */
9094 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
9095 /* PowerPC 7455 v3.3 (G4) */
9096 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
9097 /* PowerPC 7445 v3.4 (G4) */
9098 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
9099 /* PowerPC 7455 v3.4 (G4) */
9100 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
9101 /* PowerPC 7447 (G4) */
9102 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
9103 /* PowerPC 7457 (G4) */
9104 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
9105 /* Code name for PowerPC 7447/7457 */
9106 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
9107 /* PowerPC 7447 v1.0 (G4) */
9108 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
9109 /* PowerPC 7457 v1.0 (G4) */
9110 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
9111 /* PowerPC 7447 v1.1 (G4) */
9112 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
9113 /* PowerPC 7457 v1.1 (G4) */
9114 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
9115 /* PowerPC 7457 v1.2 (G4) */
9116 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
9117 /* PowerPC 7447A (G4) */
9118 POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
9119 /* PowerPC 7457A (G4) */
9120 POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
9121 /* PowerPC 7447A v1.0 (G4) */
9122 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
9123 /* PowerPC 7457A v1.0 (G4) */
9124 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
9125 /* Code name for PowerPC 7447A/7457A */
9126 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
9127 /* PowerPC 7447A v1.1 (G4) */
9128 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
9129 /* PowerPC 7457A v1.1 (G4) */
9130 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
9131 /* PowerPC 7447A v1.2 (G4) */
9132 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
9133 /* PowerPC 7457A v1.2 (G4) */
9134 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
9135 /* 64 bits PowerPC */
9136 #if defined (TARGET_PPC64)
9137 /* PowerPC 620 */
9138 POWERPC_DEF("620", CPU_POWERPC_620, 620),
9139 /* Code name for PowerPC 620 */
9140 POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
9141 #if defined (TODO)
9142 /* PowerPC 630 (POWER3) */
9143 POWERPC_DEF("630", CPU_POWERPC_630, 630),
9144 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
9145 /* Code names for POWER3 */
9146 POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
9147 POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
9148 #endif
9149 #if defined (TODO)
9150 /* PowerPC 631 (Power 3+) */
9151 POWERPC_DEF("631", CPU_POWERPC_631, 631),
9152 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
9153 #endif
9154 #if defined (TODO)
9155 /* POWER4 */
9156 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
9157 #endif
9158 #if defined (TODO)
9159 /* POWER4p */
9160 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
9161 #endif
9162 #if defined (TODO)
9163 /* POWER5 */
9164 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
9165 /* POWER5GR */
9166 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
9167 #endif
9168 #if defined (TODO)
9169 /* POWER5+ */
9170 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
9171 /* POWER5GS */
9172 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
9173 #endif
9174 #if defined (TODO)
9175 /* POWER6 */
9176 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
9177 /* POWER6 running in POWER5 mode */
9178 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
9179 /* POWER6A */
9180 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
9181 #endif
9182 /* POWER7 */
9183 POWERPC_DEF("POWER7", CPU_POWERPC_POWER7, POWER7),
9184 POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7),
9185 POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21, POWER7),
9186 POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7),
9187 /* PowerPC 970 */
9188 POWERPC_DEF("970", CPU_POWERPC_970, 970),
9189 /* PowerPC 970FX (G5) */
9190 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
9191 /* PowerPC 970FX v1.0 (G5) */
9192 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
9193 /* PowerPC 970FX v2.0 (G5) */
9194 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
9195 /* PowerPC 970FX v2.1 (G5) */
9196 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
9197 /* PowerPC 970FX v3.0 (G5) */
9198 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
9199 /* PowerPC 970FX v3.1 (G5) */
9200 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
9201 /* PowerPC 970GX (G5) */
9202 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
9203 /* PowerPC 970MP */
9204 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
9205 /* PowerPC 970MP v1.0 */
9206 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
9207 /* PowerPC 970MP v1.1 */
9208 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
9209 #if defined (TODO)
9210 /* PowerPC Cell */
9211 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
9212 #endif
9213 #if defined (TODO)
9214 /* PowerPC Cell v1.0 */
9215 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
9216 #endif
9217 #if defined (TODO)
9218 /* PowerPC Cell v2.0 */
9219 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
9220 #endif
9221 #if defined (TODO)
9222 /* PowerPC Cell v3.0 */
9223 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
9224 #endif
9225 #if defined (TODO)
9226 /* PowerPC Cell v3.1 */
9227 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
9228 #endif
9229 #if defined (TODO)
9230 /* PowerPC Cell v3.2 */
9231 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
9232 #endif
9233 #if defined (TODO)
9234 /* RS64 (Apache/A35) */
9235 /* This one seems to support the whole POWER2 instruction set
9236 * and the PowerPC 64 one.
9237 */
9238 /* What about A10 & A30 ? */
9239 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
9240 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
9241 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
9242 #endif
9243 #if defined (TODO)
9244 /* RS64-II (NorthStar/A50) */
9245 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
9246 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
9247 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
9248 #endif
9249 #if defined (TODO)
9250 /* RS64-III (Pulsar) */
9251 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
9252 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
9253 #endif
9254 #if defined (TODO)
9255 /* RS64-IV (IceStar/IStar/SStar) */
9256 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
9257 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
9258 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
9259 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
9260 #endif
9261 #endif /* defined (TARGET_PPC64) */
9262 /* POWER */
9263 #if defined (TODO)
9264 /* Original POWER */
9265 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
9266 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
9267 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
9268 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
9269 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
9270 #endif
9271 #if defined (TODO)
9272 /* POWER2 */
9273 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
9274 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
9275 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
9276 #endif
9277 /* PA semi cores */
9278 #if defined (TODO)
9279 /* PA PA6T */
9280 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
9281 #endif
9282 /* Generic PowerPCs */
9283 #if defined (TARGET_PPC64)
9284 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
9285 #endif
9286 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
9287 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
9288 /* Fallback */
9289 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
9290 };
9291
9292 /*****************************************************************************/
9293 /* Generic CPU instantiation routine */
9294 static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
9295 {
9296 #if !defined(CONFIG_USER_ONLY)
9297 int i;
9298
9299 env->irq_inputs = NULL;
9300 /* Set all exception vectors to an invalid address */
9301 for (i = 0; i < POWERPC_EXCP_NB; i++)
9302 env->excp_vectors[i] = (target_ulong)(-1ULL);
9303 env->hreset_excp_prefix = 0x00000000;
9304 env->ivor_mask = 0x00000000;
9305 env->ivpr_mask = 0x00000000;
9306 /* Default MMU definitions */
9307 env->nb_BATs = 0;
9308 env->nb_tlb = 0;
9309 env->nb_ways = 0;
9310 env->tlb_type = TLB_NONE;
9311 #endif
9312 /* Register SPR common to all PowerPC implementations */
9313 gen_spr_generic(env);
9314 spr_register(env, SPR_PVR, "PVR",
9315 /* Linux permits userspace to read PVR */
9316 #if defined(CONFIG_LINUX_USER)
9317 &spr_read_generic,
9318 #else
9319 SPR_NOACCESS,
9320 #endif
9321 SPR_NOACCESS,
9322 &spr_read_generic, SPR_NOACCESS,
9323 def->pvr);
9324 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
9325 if (def->svr != POWERPC_SVR_NONE) {
9326 if (def->svr & POWERPC_SVR_E500) {
9327 spr_register(env, SPR_E500_SVR, "SVR",
9328 SPR_NOACCESS, SPR_NOACCESS,
9329 &spr_read_generic, SPR_NOACCESS,
9330 def->svr & ~POWERPC_SVR_E500);
9331 } else {
9332 spr_register(env, SPR_SVR, "SVR",
9333 SPR_NOACCESS, SPR_NOACCESS,
9334 &spr_read_generic, SPR_NOACCESS,
9335 def->svr);
9336 }
9337 }
9338 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
9339 (*def->init_proc)(env);
9340 #if !defined(CONFIG_USER_ONLY)
9341 env->excp_prefix = env->hreset_excp_prefix;
9342 #endif
9343 /* MSR bits & flags consistency checks */
9344 if (env->msr_mask & (1 << 25)) {
9345 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9346 case POWERPC_FLAG_SPE:
9347 case POWERPC_FLAG_VRE:
9348 break;
9349 default:
9350 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9351 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9352 exit(1);
9353 }
9354 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9355 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9356 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9357 exit(1);
9358 }
9359 if (env->msr_mask & (1 << 17)) {
9360 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9361 case POWERPC_FLAG_TGPR:
9362 case POWERPC_FLAG_CE:
9363 break;
9364 default:
9365 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9366 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9367 exit(1);
9368 }
9369 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9370 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9371 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9372 exit(1);
9373 }
9374 if (env->msr_mask & (1 << 10)) {
9375 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9376 POWERPC_FLAG_UBLE)) {
9377 case POWERPC_FLAG_SE:
9378 case POWERPC_FLAG_DWE:
9379 case POWERPC_FLAG_UBLE:
9380 break;
9381 default:
9382 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9383 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9384 "POWERPC_FLAG_UBLE\n");
9385 exit(1);
9386 }
9387 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9388 POWERPC_FLAG_UBLE)) {
9389 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9390 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9391 "POWERPC_FLAG_UBLE\n");
9392 exit(1);
9393 }
9394 if (env->msr_mask & (1 << 9)) {
9395 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9396 case POWERPC_FLAG_BE:
9397 case POWERPC_FLAG_DE:
9398 break;
9399 default:
9400 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9401 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9402 exit(1);
9403 }
9404 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9405 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9406 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9407 exit(1);
9408 }
9409 if (env->msr_mask & (1 << 2)) {
9410 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9411 case POWERPC_FLAG_PX:
9412 case POWERPC_FLAG_PMM:
9413 break;
9414 default:
9415 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9416 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9417 exit(1);
9418 }
9419 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9420 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9421 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9422 exit(1);
9423 }
9424 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9425 fprintf(stderr, "PowerPC flags inconsistency\n"
9426 "Should define the time-base and decrementer clock source\n");
9427 exit(1);
9428 }
9429 /* Allocate TLBs buffer when needed */
9430 #if !defined(CONFIG_USER_ONLY)
9431 if (env->nb_tlb != 0) {
9432 int nb_tlb = env->nb_tlb;
9433 if (env->id_tlbs != 0)
9434 nb_tlb *= 2;
9435 switch (env->tlb_type) {
9436 case TLB_6XX:
9437 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
9438 break;
9439 case TLB_EMB:
9440 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
9441 break;
9442 case TLB_MAS:
9443 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
9444 break;
9445 }
9446 /* Pre-compute some useful values */
9447 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9448 }
9449 if (env->irq_inputs == NULL) {
9450 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
9451 " Attempt QEMU to crash very soon !\n");
9452 }
9453 #endif
9454 if (env->check_pow == NULL) {
9455 fprintf(stderr, "WARNING: no power management check handler "
9456 "registered.\n"
9457 " Attempt QEMU to crash very soon !\n");
9458 }
9459 }
9460
9461 #if defined(PPC_DUMP_CPU)
9462 static void dump_ppc_sprs (CPUPPCState *env)
9463 {
9464 ppc_spr_t *spr;
9465 #if !defined(CONFIG_USER_ONLY)
9466 uint32_t sr, sw;
9467 #endif
9468 uint32_t ur, uw;
9469 int i, j, n;
9470
9471 printf("Special purpose registers:\n");
9472 for (i = 0; i < 32; i++) {
9473 for (j = 0; j < 32; j++) {
9474 n = (i << 5) | j;
9475 spr = &env->spr_cb[n];
9476 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9477 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9478 #if !defined(CONFIG_USER_ONLY)
9479 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9480 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9481 if (sw || sr || uw || ur) {
9482 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9483 (i << 5) | j, (i << 5) | j, spr->name,
9484 sw ? 'w' : '-', sr ? 'r' : '-',
9485 uw ? 'w' : '-', ur ? 'r' : '-');
9486 }
9487 #else
9488 if (uw || ur) {
9489 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9490 (i << 5) | j, (i << 5) | j, spr->name,
9491 uw ? 'w' : '-', ur ? 'r' : '-');
9492 }
9493 #endif
9494 }
9495 }
9496 fflush(stdout);
9497 fflush(stderr);
9498 }
9499 #endif
9500
9501 /*****************************************************************************/
9502 #include <stdlib.h>
9503 #include <string.h>
9504
9505 /* Opcode types */
9506 enum {
9507 PPC_DIRECT = 0, /* Opcode routine */
9508 PPC_INDIRECT = 1, /* Indirect opcode table */
9509 };
9510
9511 static inline int is_indirect_opcode (void *handler)
9512 {
9513 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
9514 }
9515
9516 static inline opc_handler_t **ind_table(void *handler)
9517 {
9518 return (opc_handler_t **)((uintptr_t)handler & ~3);
9519 }
9520
9521 /* Instruction table creation */
9522 /* Opcodes tables creation */
9523 static void fill_new_table (opc_handler_t **table, int len)
9524 {
9525 int i;
9526
9527 for (i = 0; i < len; i++)
9528 table[i] = &invalid_handler;
9529 }
9530
9531 static int create_new_table (opc_handler_t **table, unsigned char idx)
9532 {
9533 opc_handler_t **tmp;
9534
9535 tmp = malloc(0x20 * sizeof(opc_handler_t));
9536 fill_new_table(tmp, 0x20);
9537 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
9538
9539 return 0;
9540 }
9541
9542 static int insert_in_table (opc_handler_t **table, unsigned char idx,
9543 opc_handler_t *handler)
9544 {
9545 if (table[idx] != &invalid_handler)
9546 return -1;
9547 table[idx] = handler;
9548
9549 return 0;
9550 }
9551
9552 static int register_direct_insn (opc_handler_t **ppc_opcodes,
9553 unsigned char idx, opc_handler_t *handler)
9554 {
9555 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9556 printf("*** ERROR: opcode %02x already assigned in main "
9557 "opcode table\n", idx);
9558 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9559 printf(" Registered handler '%s' - new handler '%s'\n",
9560 ppc_opcodes[idx]->oname, handler->oname);
9561 #endif
9562 return -1;
9563 }
9564
9565 return 0;
9566 }
9567
9568 static int register_ind_in_table (opc_handler_t **table,
9569 unsigned char idx1, unsigned char idx2,
9570 opc_handler_t *handler)
9571 {
9572 if (table[idx1] == &invalid_handler) {
9573 if (create_new_table(table, idx1) < 0) {
9574 printf("*** ERROR: unable to create indirect table "
9575 "idx=%02x\n", idx1);
9576 return -1;
9577 }
9578 } else {
9579 if (!is_indirect_opcode(table[idx1])) {
9580 printf("*** ERROR: idx %02x already assigned to a direct "
9581 "opcode\n", idx1);
9582 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9583 printf(" Registered handler '%s' - new handler '%s'\n",
9584 ind_table(table[idx1])[idx2]->oname, handler->oname);
9585 #endif
9586 return -1;
9587 }
9588 }
9589 if (handler != NULL &&
9590 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9591 printf("*** ERROR: opcode %02x already assigned in "
9592 "opcode table %02x\n", idx2, idx1);
9593 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9594 printf(" Registered handler '%s' - new handler '%s'\n",
9595 ind_table(table[idx1])[idx2]->oname, handler->oname);
9596 #endif
9597 return -1;
9598 }
9599
9600 return 0;
9601 }
9602
9603 static int register_ind_insn (opc_handler_t **ppc_opcodes,
9604 unsigned char idx1, unsigned char idx2,
9605 opc_handler_t *handler)
9606 {
9607 int ret;
9608
9609 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9610
9611 return ret;
9612 }
9613
9614 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
9615 unsigned char idx1, unsigned char idx2,
9616 unsigned char idx3, opc_handler_t *handler)
9617 {
9618 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9619 printf("*** ERROR: unable to join indirect table idx "
9620 "[%02x-%02x]\n", idx1, idx2);
9621 return -1;
9622 }
9623 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9624 handler) < 0) {
9625 printf("*** ERROR: unable to insert opcode "
9626 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9627 return -1;
9628 }
9629
9630 return 0;
9631 }
9632
9633 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
9634 {
9635 if (insn->opc2 != 0xFF) {
9636 if (insn->opc3 != 0xFF) {
9637 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9638 insn->opc3, &insn->handler) < 0)
9639 return -1;
9640 } else {
9641 if (register_ind_insn(ppc_opcodes, insn->opc1,
9642 insn->opc2, &insn->handler) < 0)
9643 return -1;
9644 }
9645 } else {
9646 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9647 return -1;
9648 }
9649
9650 return 0;
9651 }
9652
9653 static int test_opcode_table (opc_handler_t **table, int len)
9654 {
9655 int i, count, tmp;
9656
9657 for (i = 0, count = 0; i < len; i++) {
9658 /* Consistency fixup */
9659 if (table[i] == NULL)
9660 table[i] = &invalid_handler;
9661 if (table[i] != &invalid_handler) {
9662 if (is_indirect_opcode(table[i])) {
9663 tmp = test_opcode_table(ind_table(table[i]), 0x20);
9664 if (tmp == 0) {
9665 free(table[i]);
9666 table[i] = &invalid_handler;
9667 } else {
9668 count++;
9669 }
9670 } else {
9671 count++;
9672 }
9673 }
9674 }
9675
9676 return count;
9677 }
9678
9679 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
9680 {
9681 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9682 printf("*** WARNING: no opcode defined !\n");
9683 }
9684
9685 /*****************************************************************************/
9686 static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
9687 {
9688 opcode_t *opc;
9689
9690 fill_new_table(env->opcodes, 0x40);
9691 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
9692 if (((opc->handler.type & def->insns_flags) != 0) ||
9693 ((opc->handler.type2 & def->insns_flags2) != 0)) {
9694 if (register_insn(env->opcodes, opc) < 0) {
9695 printf("*** ERROR initializing PowerPC instruction "
9696 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9697 opc->opc3);
9698 return -1;
9699 }
9700 }
9701 }
9702 fix_opcode_tables(env->opcodes);
9703 fflush(stdout);
9704 fflush(stderr);
9705
9706 return 0;
9707 }
9708
9709 #if defined(PPC_DUMP_CPU)
9710 static void dump_ppc_insns (CPUPPCState *env)
9711 {
9712 opc_handler_t **table, *handler;
9713 const char *p, *q;
9714 uint8_t opc1, opc2, opc3;
9715
9716 printf("Instructions set:\n");
9717 /* opc1 is 6 bits long */
9718 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9719 table = env->opcodes;
9720 handler = table[opc1];
9721 if (is_indirect_opcode(handler)) {
9722 /* opc2 is 5 bits long */
9723 for (opc2 = 0; opc2 < 0x20; opc2++) {
9724 table = env->opcodes;
9725 handler = env->opcodes[opc1];
9726 table = ind_table(handler);
9727 handler = table[opc2];
9728 if (is_indirect_opcode(handler)) {
9729 table = ind_table(handler);
9730 /* opc3 is 5 bits long */
9731 for (opc3 = 0; opc3 < 0x20; opc3++) {
9732 handler = table[opc3];
9733 if (handler->handler != &gen_invalid) {
9734 /* Special hack to properly dump SPE insns */
9735 p = strchr(handler->oname, '_');
9736 if (p == NULL) {
9737 printf("INSN: %02x %02x %02x (%02d %04d) : "
9738 "%s\n",
9739 opc1, opc2, opc3, opc1,
9740 (opc3 << 5) | opc2,
9741 handler->oname);
9742 } else {
9743 q = "speundef";
9744 if ((p - handler->oname) != strlen(q) ||
9745 memcmp(handler->oname, q, strlen(q)) != 0) {
9746 /* First instruction */
9747 printf("INSN: %02x %02x %02x (%02d %04d) : "
9748 "%.*s\n",
9749 opc1, opc2 << 1, opc3, opc1,
9750 (opc3 << 6) | (opc2 << 1),
9751 (int)(p - handler->oname),
9752 handler->oname);
9753 }
9754 if (strcmp(p + 1, q) != 0) {
9755 /* Second instruction */
9756 printf("INSN: %02x %02x %02x (%02d %04d) : "
9757 "%s\n",
9758 opc1, (opc2 << 1) | 1, opc3, opc1,
9759 (opc3 << 6) | (opc2 << 1) | 1,
9760 p + 1);
9761 }
9762 }
9763 }
9764 }
9765 } else {
9766 if (handler->handler != &gen_invalid) {
9767 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9768 opc1, opc2, opc1, opc2, handler->oname);
9769 }
9770 }
9771 }
9772 } else {
9773 if (handler->handler != &gen_invalid) {
9774 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9775 opc1, opc1, handler->oname);
9776 }
9777 }
9778 }
9779 }
9780 #endif
9781
9782 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9783 {
9784 if (n < 32) {
9785 stfq_p(mem_buf, env->fpr[n]);
9786 return 8;
9787 }
9788 if (n == 32) {
9789 stl_p(mem_buf, env->fpscr);
9790 return 4;
9791 }
9792 return 0;
9793 }
9794
9795 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9796 {
9797 if (n < 32) {
9798 env->fpr[n] = ldfq_p(mem_buf);
9799 return 8;
9800 }
9801 if (n == 32) {
9802 /* FPSCR not implemented */
9803 return 4;
9804 }
9805 return 0;
9806 }
9807
9808 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9809 {
9810 if (n < 32) {
9811 #ifdef HOST_WORDS_BIGENDIAN
9812 stq_p(mem_buf, env->avr[n].u64[0]);
9813 stq_p(mem_buf+8, env->avr[n].u64[1]);
9814 #else
9815 stq_p(mem_buf, env->avr[n].u64[1]);
9816 stq_p(mem_buf+8, env->avr[n].u64[0]);
9817 #endif
9818 return 16;
9819 }
9820 if (n == 32) {
9821 stl_p(mem_buf, env->vscr);
9822 return 4;
9823 }
9824 if (n == 33) {
9825 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9826 return 4;
9827 }
9828 return 0;
9829 }
9830
9831 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9832 {
9833 if (n < 32) {
9834 #ifdef HOST_WORDS_BIGENDIAN
9835 env->avr[n].u64[0] = ldq_p(mem_buf);
9836 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9837 #else
9838 env->avr[n].u64[1] = ldq_p(mem_buf);
9839 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9840 #endif
9841 return 16;
9842 }
9843 if (n == 32) {
9844 env->vscr = ldl_p(mem_buf);
9845 return 4;
9846 }
9847 if (n == 33) {
9848 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9849 return 4;
9850 }
9851 return 0;
9852 }
9853
9854 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9855 {
9856 if (n < 32) {
9857 #if defined(TARGET_PPC64)
9858 stl_p(mem_buf, env->gpr[n] >> 32);
9859 #else
9860 stl_p(mem_buf, env->gprh[n]);
9861 #endif
9862 return 4;
9863 }
9864 if (n == 32) {
9865 stq_p(mem_buf, env->spe_acc);
9866 return 8;
9867 }
9868 if (n == 33) {
9869 stl_p(mem_buf, env->spe_fscr);
9870 return 4;
9871 }
9872 return 0;
9873 }
9874
9875 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9876 {
9877 if (n < 32) {
9878 #if defined(TARGET_PPC64)
9879 target_ulong lo = (uint32_t)env->gpr[n];
9880 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9881 env->gpr[n] = lo | hi;
9882 #else
9883 env->gprh[n] = ldl_p(mem_buf);
9884 #endif
9885 return 4;
9886 }
9887 if (n == 32) {
9888 env->spe_acc = ldq_p(mem_buf);
9889 return 8;
9890 }
9891 if (n == 33) {
9892 env->spe_fscr = ldl_p(mem_buf);
9893 return 4;
9894 }
9895 return 0;
9896 }
9897
9898 static int ppc_fixup_cpu(CPUPPCState *env)
9899 {
9900 /* TCG doesn't (yet) emulate some groups of instructions that
9901 * are implemented on some otherwise supported CPUs (e.g. VSX
9902 * and decimal floating point instructions on POWER7). We
9903 * remove unsupported instruction groups from the cpu state's
9904 * instruction masks and hope the guest can cope. For at
9905 * least the pseries machine, the unavailability of these
9906 * instructions can be advertised to the guest via the device
9907 * tree. */
9908 if ((env->insns_flags & ~PPC_TCG_INSNS)
9909 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
9910 fprintf(stderr, "Warning: Disabling some instructions which are not "
9911 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
9912 env->insns_flags & ~PPC_TCG_INSNS,
9913 env->insns_flags2 & ~PPC_TCG_INSNS2);
9914 }
9915 env->insns_flags &= PPC_TCG_INSNS;
9916 env->insns_flags2 &= PPC_TCG_INSNS2;
9917 return 0;
9918 }
9919
9920 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
9921 {
9922 env->msr_mask = def->msr_mask;
9923 env->mmu_model = def->mmu_model;
9924 env->excp_model = def->excp_model;
9925 env->bus_model = def->bus_model;
9926 env->insns_flags = def->insns_flags;
9927 env->insns_flags2 = def->insns_flags2;
9928 env->flags = def->flags;
9929 env->bfd_mach = def->bfd_mach;
9930 env->check_pow = def->check_pow;
9931
9932 #if defined(TARGET_PPC64)
9933 if (def->sps)
9934 env->sps = *def->sps;
9935 else if (env->mmu_model & POWERPC_MMU_64) {
9936 /* Use default sets of page sizes */
9937 static const struct ppc_segment_page_sizes defsps = {
9938 .sps = {
9939 { .page_shift = 12, /* 4K */
9940 .slb_enc = 0,
9941 .enc = { { .page_shift = 12, .pte_enc = 0 } }
9942 },
9943 { .page_shift = 24, /* 16M */
9944 .slb_enc = 0x100,
9945 .enc = { { .page_shift = 24, .pte_enc = 0 } }
9946 },
9947 },
9948 };
9949 env->sps = defsps;
9950 }
9951 #endif /* defined(TARGET_PPC64) */
9952
9953 if (kvm_enabled()) {
9954 if (kvmppc_fixup_cpu(env) != 0) {
9955 fprintf(stderr, "Unable to virtualize selected CPU with KVM\n");
9956 exit(1);
9957 }
9958 } else {
9959 if (ppc_fixup_cpu(env) != 0) {
9960 fprintf(stderr, "Unable to emulate selected CPU with TCG\n");
9961 exit(1);
9962 }
9963 }
9964
9965 if (create_ppc_opcodes(env, def) < 0)
9966 return -1;
9967 init_ppc_proc(env, def);
9968
9969 if (def->insns_flags & PPC_FLOAT) {
9970 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9971 33, "power-fpu.xml", 0);
9972 }
9973 if (def->insns_flags & PPC_ALTIVEC) {
9974 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9975 34, "power-altivec.xml", 0);
9976 }
9977 if (def->insns_flags & PPC_SPE) {
9978 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
9979 34, "power-spe.xml", 0);
9980 }
9981
9982 #if defined(PPC_DUMP_CPU)
9983 {
9984 const char *mmu_model, *excp_model, *bus_model;
9985 switch (env->mmu_model) {
9986 case POWERPC_MMU_32B:
9987 mmu_model = "PowerPC 32";
9988 break;
9989 case POWERPC_MMU_SOFT_6xx:
9990 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9991 break;
9992 case POWERPC_MMU_SOFT_74xx:
9993 mmu_model = "PowerPC 74xx with software driven TLBs";
9994 break;
9995 case POWERPC_MMU_SOFT_4xx:
9996 mmu_model = "PowerPC 4xx with software driven TLBs";
9997 break;
9998 case POWERPC_MMU_SOFT_4xx_Z:
9999 mmu_model = "PowerPC 4xx with software driven TLBs "
10000 "and zones protections";
10001 break;
10002 case POWERPC_MMU_REAL:
10003 mmu_model = "PowerPC real mode only";
10004 break;
10005 case POWERPC_MMU_MPC8xx:
10006 mmu_model = "PowerPC MPC8xx";
10007 break;
10008 case POWERPC_MMU_BOOKE:
10009 mmu_model = "PowerPC BookE";
10010 break;
10011 case POWERPC_MMU_BOOKE206:
10012 mmu_model = "PowerPC BookE 2.06";
10013 break;
10014 case POWERPC_MMU_601:
10015 mmu_model = "PowerPC 601";
10016 break;
10017 #if defined (TARGET_PPC64)
10018 case POWERPC_MMU_64B:
10019 mmu_model = "PowerPC 64";
10020 break;
10021 case POWERPC_MMU_620:
10022 mmu_model = "PowerPC 620";
10023 break;
10024 #endif
10025 default:
10026 mmu_model = "Unknown or invalid";
10027 break;
10028 }
10029 switch (env->excp_model) {
10030 case POWERPC_EXCP_STD:
10031 excp_model = "PowerPC";
10032 break;
10033 case POWERPC_EXCP_40x:
10034 excp_model = "PowerPC 40x";
10035 break;
10036 case POWERPC_EXCP_601:
10037 excp_model = "PowerPC 601";
10038 break;
10039 case POWERPC_EXCP_602:
10040 excp_model = "PowerPC 602";
10041 break;
10042 case POWERPC_EXCP_603:
10043 excp_model = "PowerPC 603";
10044 break;
10045 case POWERPC_EXCP_603E:
10046 excp_model = "PowerPC 603e";
10047 break;
10048 case POWERPC_EXCP_604:
10049 excp_model = "PowerPC 604";
10050 break;
10051 case POWERPC_EXCP_7x0:
10052 excp_model = "PowerPC 740/750";
10053 break;
10054 case POWERPC_EXCP_7x5:
10055 excp_model = "PowerPC 745/755";
10056 break;
10057 case POWERPC_EXCP_74xx:
10058 excp_model = "PowerPC 74xx";
10059 break;
10060 case POWERPC_EXCP_BOOKE:
10061 excp_model = "PowerPC BookE";
10062 break;
10063 #if defined (TARGET_PPC64)
10064 case POWERPC_EXCP_970:
10065 excp_model = "PowerPC 970";
10066 break;
10067 #endif
10068 default:
10069 excp_model = "Unknown or invalid";
10070 break;
10071 }
10072 switch (env->bus_model) {
10073 case PPC_FLAGS_INPUT_6xx:
10074 bus_model = "PowerPC 6xx";
10075 break;
10076 case PPC_FLAGS_INPUT_BookE:
10077 bus_model = "PowerPC BookE";
10078 break;
10079 case PPC_FLAGS_INPUT_405:
10080 bus_model = "PowerPC 405";
10081 break;
10082 case PPC_FLAGS_INPUT_401:
10083 bus_model = "PowerPC 401/403";
10084 break;
10085 case PPC_FLAGS_INPUT_RCPU:
10086 bus_model = "RCPU / MPC8xx";
10087 break;
10088 #if defined (TARGET_PPC64)
10089 case PPC_FLAGS_INPUT_970:
10090 bus_model = "PowerPC 970";
10091 break;
10092 #endif
10093 default:
10094 bus_model = "Unknown or invalid";
10095 break;
10096 }
10097 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
10098 " MMU model : %s\n",
10099 def->name, def->pvr, def->msr_mask, mmu_model);
10100 #if !defined(CONFIG_USER_ONLY)
10101 if (env->tlb != NULL) {
10102 printf(" %d %s TLB in %d ways\n",
10103 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
10104 env->nb_ways);
10105 }
10106 #endif
10107 printf(" Exceptions model : %s\n"
10108 " Bus model : %s\n",
10109 excp_model, bus_model);
10110 printf(" MSR features :\n");
10111 if (env->flags & POWERPC_FLAG_SPE)
10112 printf(" signal processing engine enable"
10113 "\n");
10114 else if (env->flags & POWERPC_FLAG_VRE)
10115 printf(" vector processor enable\n");
10116 if (env->flags & POWERPC_FLAG_TGPR)
10117 printf(" temporary GPRs\n");
10118 else if (env->flags & POWERPC_FLAG_CE)
10119 printf(" critical input enable\n");
10120 if (env->flags & POWERPC_FLAG_SE)
10121 printf(" single-step trace mode\n");
10122 else if (env->flags & POWERPC_FLAG_DWE)
10123 printf(" debug wait enable\n");
10124 else if (env->flags & POWERPC_FLAG_UBLE)
10125 printf(" user BTB lock enable\n");
10126 if (env->flags & POWERPC_FLAG_BE)
10127 printf(" branch-step trace mode\n");
10128 else if (env->flags & POWERPC_FLAG_DE)
10129 printf(" debug interrupt enable\n");
10130 if (env->flags & POWERPC_FLAG_PX)
10131 printf(" inclusive protection\n");
10132 else if (env->flags & POWERPC_FLAG_PMM)
10133 printf(" performance monitor mark\n");
10134 if (env->flags == POWERPC_FLAG_NONE)
10135 printf(" none\n");
10136 printf(" Time-base/decrementer clock source: %s\n",
10137 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
10138 }
10139 dump_ppc_insns(env);
10140 dump_ppc_sprs(env);
10141 fflush(stdout);
10142 #endif
10143
10144 return 0;
10145 }
10146
10147 static bool ppc_cpu_usable(const ppc_def_t *def)
10148 {
10149 #if defined(TARGET_PPCEMB)
10150 /* When using the ppcemb target, we only support 440 style cores */
10151 if (def->mmu_model != POWERPC_MMU_BOOKE) {
10152 return false;
10153 }
10154 #endif
10155
10156 return true;
10157 }
10158
10159 const ppc_def_t *ppc_find_by_pvr(uint32_t pvr)
10160 {
10161 int i;
10162
10163 for (i = 0; i < ARRAY_SIZE(ppc_defs); i++) {
10164 if (!ppc_cpu_usable(&ppc_defs[i])) {
10165 continue;
10166 }
10167
10168 /* If we have an exact match, we're done */
10169 if (pvr == ppc_defs[i].pvr) {
10170 return &ppc_defs[i];
10171 }
10172 }
10173
10174 return NULL;
10175 }
10176
10177 #include <ctype.h>
10178
10179 const ppc_def_t *cpu_ppc_find_by_name (const char *name)
10180 {
10181 const ppc_def_t *ret;
10182 const char *p;
10183 int i, max, len;
10184
10185 if (kvm_enabled() && (strcasecmp(name, "host") == 0)) {
10186 return kvmppc_host_cpu_def();
10187 }
10188
10189 /* Check if the given name is a PVR */
10190 len = strlen(name);
10191 if (len == 10 && name[0] == '0' && name[1] == 'x') {
10192 p = name + 2;
10193 goto check_pvr;
10194 } else if (len == 8) {
10195 p = name;
10196 check_pvr:
10197 for (i = 0; i < 8; i++) {
10198 if (!qemu_isxdigit(*p++))
10199 break;
10200 }
10201 if (i == 8)
10202 return ppc_find_by_pvr(strtoul(name, NULL, 16));
10203 }
10204 ret = NULL;
10205 max = ARRAY_SIZE(ppc_defs);
10206 for (i = 0; i < max; i++) {
10207 if (!ppc_cpu_usable(&ppc_defs[i])) {
10208 continue;
10209 }
10210
10211 if (strcasecmp(name, ppc_defs[i].name) == 0) {
10212 ret = &ppc_defs[i];
10213 break;
10214 }
10215 }
10216
10217 return ret;
10218 }
10219
10220 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
10221 {
10222 int i, max;
10223
10224 max = ARRAY_SIZE(ppc_defs);
10225 for (i = 0; i < max; i++) {
10226 if (!ppc_cpu_usable(&ppc_defs[i])) {
10227 continue;
10228 }
10229
10230 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
10231 ppc_defs[i].name, ppc_defs[i].pvr);
10232 }
10233 }
10234
10235 /* CPUClass::reset() */
10236 static void ppc_cpu_reset(CPUState *s)
10237 {
10238 PowerPCCPU *cpu = POWERPC_CPU(s);
10239 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10240 CPUPPCState *env = &cpu->env;
10241 target_ulong msr;
10242
10243 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
10244 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
10245 log_cpu_state(env, 0);
10246 }
10247
10248 pcc->parent_reset(s);
10249
10250 msr = (target_ulong)0;
10251 if (0) {
10252 /* XXX: find a suitable condition to enable the hypervisor mode */
10253 msr |= (target_ulong)MSR_HVB;
10254 }
10255 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
10256 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
10257 msr |= (target_ulong)1 << MSR_EP;
10258 #if defined(DO_SINGLE_STEP) && 0
10259 /* Single step trace mode */
10260 msr |= (target_ulong)1 << MSR_SE;
10261 msr |= (target_ulong)1 << MSR_BE;
10262 #endif
10263 #if defined(CONFIG_USER_ONLY)
10264 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
10265 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
10266 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
10267 msr |= (target_ulong)1 << MSR_PR;
10268 #else
10269 env->excp_prefix = env->hreset_excp_prefix;
10270 env->nip = env->hreset_vector | env->excp_prefix;
10271 if (env->mmu_model != POWERPC_MMU_REAL) {
10272 ppc_tlb_invalidate_all(env);
10273 }
10274 #endif
10275 env->msr = msr & env->msr_mask;
10276 #if defined(TARGET_PPC64)
10277 if (env->mmu_model & POWERPC_MMU_64) {
10278 env->msr |= (1ULL << MSR_SF);
10279 }
10280 #endif
10281 hreg_compute_hflags(env);
10282 env->reserve_addr = (target_ulong)-1ULL;
10283 /* Be sure no exception or interrupt is pending */
10284 env->pending_interrupts = 0;
10285 env->exception_index = POWERPC_EXCP_NONE;
10286 env->error_code = 0;
10287 /* Flush all TLBs */
10288 tlb_flush(env, 1);
10289 }
10290
10291 static void ppc_cpu_initfn(Object *obj)
10292 {
10293 PowerPCCPU *cpu = POWERPC_CPU(obj);
10294 CPUPPCState *env = &cpu->env;
10295
10296 cpu_exec_init(env);
10297 }
10298
10299 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
10300 {
10301 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10302 CPUClass *cc = CPU_CLASS(oc);
10303
10304 pcc->parent_reset = cc->reset;
10305 cc->reset = ppc_cpu_reset;
10306 }
10307
10308 static const TypeInfo ppc_cpu_type_info = {
10309 .name = TYPE_POWERPC_CPU,
10310 .parent = TYPE_CPU,
10311 .instance_size = sizeof(PowerPCCPU),
10312 .instance_init = ppc_cpu_initfn,
10313 .abstract = false,
10314 .class_size = sizeof(PowerPCCPUClass),
10315 .class_init = ppc_cpu_class_init,
10316 };
10317
10318 static void ppc_cpu_register_types(void)
10319 {
10320 type_register_static(&ppc_cpu_type_info);
10321 }
10322
10323 type_init(ppc_cpu_register_types)
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