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Duplicated SPR fix for BookE PowerPC by Guglielmo Morandin
[mirror_qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
26 //#define PPC_DUMP_CPU
27 //#define PPC_DEBUG_SPR
28 //#define PPC_DEBUG_IRQ
29
30 struct ppc_def_t {
31 const unsigned char *name;
32 uint32_t pvr;
33 uint32_t pvr_mask;
34 uint64_t insns_flags;
35 uint32_t flags;
36 uint64_t msr_mask;
37 };
38
39 /* For user-mode emulation, we don't emulate any IRQ controller */
40 #if defined(CONFIG_USER_ONLY)
41 #define PPC_IRQ_INIT_FN(name) \
42 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
43 { \
44 }
45 #else
46 #define PPC_IRQ_INIT_FN(name) \
47 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
48 #endif
49 PPC_IRQ_INIT_FN(405);
50 PPC_IRQ_INIT_FN(6xx);
51 PPC_IRQ_INIT_FN(970);
52
53 /* Generic callbacks:
54 * do nothing but store/retrieve spr value
55 */
56 #ifdef PPC_DUMP_SPR_ACCESSES
57 static void spr_read_generic (void *opaque, int sprn)
58 {
59 gen_op_load_dump_spr(sprn);
60 }
61
62 static void spr_write_generic (void *opaque, int sprn)
63 {
64 gen_op_store_dump_spr(sprn);
65 }
66 #else
67 static void spr_read_generic (void *opaque, int sprn)
68 {
69 gen_op_load_spr(sprn);
70 }
71
72 static void spr_write_generic (void *opaque, int sprn)
73 {
74 gen_op_store_spr(sprn);
75 }
76 #endif
77
78 #if !defined(CONFIG_USER_ONLY)
79 static void spr_write_clear (void *opaque, int sprn)
80 {
81 gen_op_mask_spr(sprn);
82 }
83 #endif
84
85 /* SPR common to all PowerPC */
86 /* XER */
87 static void spr_read_xer (void *opaque, int sprn)
88 {
89 gen_op_load_xer();
90 }
91
92 static void spr_write_xer (void *opaque, int sprn)
93 {
94 gen_op_store_xer();
95 }
96
97 /* LR */
98 static void spr_read_lr (void *opaque, int sprn)
99 {
100 gen_op_load_lr();
101 }
102
103 static void spr_write_lr (void *opaque, int sprn)
104 {
105 gen_op_store_lr();
106 }
107
108 /* CTR */
109 static void spr_read_ctr (void *opaque, int sprn)
110 {
111 gen_op_load_ctr();
112 }
113
114 static void spr_write_ctr (void *opaque, int sprn)
115 {
116 gen_op_store_ctr();
117 }
118
119 /* User read access to SPR */
120 /* USPRx */
121 /* UMMCRx */
122 /* UPMCx */
123 /* USIA */
124 /* UDECR */
125 static void spr_read_ureg (void *opaque, int sprn)
126 {
127 gen_op_load_spr(sprn + 0x10);
128 }
129
130 /* SPR common to all non-embedded PowerPC */
131 /* DECR */
132 #if !defined(CONFIG_USER_ONLY)
133 static void spr_read_decr (void *opaque, int sprn)
134 {
135 gen_op_load_decr();
136 }
137
138 static void spr_write_decr (void *opaque, int sprn)
139 {
140 gen_op_store_decr();
141 }
142 #endif
143
144 /* SPR common to all non-embedded PowerPC, except 601 */
145 /* Time base */
146 static void spr_read_tbl (void *opaque, int sprn)
147 {
148 gen_op_load_tbl();
149 }
150
151 static void spr_read_tbu (void *opaque, int sprn)
152 {
153 gen_op_load_tbu();
154 }
155
156 #if !defined(CONFIG_USER_ONLY)
157 static void spr_write_tbl (void *opaque, int sprn)
158 {
159 gen_op_store_tbl();
160 }
161
162 static void spr_write_tbu (void *opaque, int sprn)
163 {
164 gen_op_store_tbu();
165 }
166 #endif
167
168 #if !defined(CONFIG_USER_ONLY)
169 /* IBAT0U...IBAT0U */
170 /* IBAT0L...IBAT7L */
171 static void spr_read_ibat (void *opaque, int sprn)
172 {
173 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
174 }
175
176 static void spr_read_ibat_h (void *opaque, int sprn)
177 {
178 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
179 }
180
181 static void spr_write_ibatu (void *opaque, int sprn)
182 {
183 DisasContext *ctx = opaque;
184
185 gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
186 RET_STOP(ctx);
187 }
188
189 static void spr_write_ibatu_h (void *opaque, int sprn)
190 {
191 DisasContext *ctx = opaque;
192
193 gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
194 RET_STOP(ctx);
195 }
196
197 static void spr_write_ibatl (void *opaque, int sprn)
198 {
199 DisasContext *ctx = opaque;
200
201 gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
202 RET_STOP(ctx);
203 }
204
205 static void spr_write_ibatl_h (void *opaque, int sprn)
206 {
207 DisasContext *ctx = opaque;
208
209 gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
210 RET_STOP(ctx);
211 }
212
213 /* DBAT0U...DBAT7U */
214 /* DBAT0L...DBAT7L */
215 static void spr_read_dbat (void *opaque, int sprn)
216 {
217 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
218 }
219
220 static void spr_read_dbat_h (void *opaque, int sprn)
221 {
222 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
223 }
224
225 static void spr_write_dbatu (void *opaque, int sprn)
226 {
227 DisasContext *ctx = opaque;
228
229 gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
230 RET_STOP(ctx);
231 }
232
233 static void spr_write_dbatu_h (void *opaque, int sprn)
234 {
235 DisasContext *ctx = opaque;
236
237 gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
238 RET_STOP(ctx);
239 }
240
241 static void spr_write_dbatl (void *opaque, int sprn)
242 {
243 DisasContext *ctx = opaque;
244
245 gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
246 RET_STOP(ctx);
247 }
248
249 static void spr_write_dbatl_h (void *opaque, int sprn)
250 {
251 DisasContext *ctx = opaque;
252
253 gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
254 RET_STOP(ctx);
255 }
256
257 /* SDR1 */
258 static void spr_read_sdr1 (void *opaque, int sprn)
259 {
260 gen_op_load_sdr1();
261 }
262
263 static void spr_write_sdr1 (void *opaque, int sprn)
264 {
265 DisasContext *ctx = opaque;
266
267 gen_op_store_sdr1();
268 RET_STOP(ctx);
269 }
270
271 /* 64 bits PowerPC specific SPRs */
272 /* ASR */
273 #if defined(TARGET_PPC64)
274 static void spr_read_asr (void *opaque, int sprn)
275 {
276 gen_op_load_asr();
277 }
278
279 static void spr_write_asr (void *opaque, int sprn)
280 {
281 DisasContext *ctx = opaque;
282
283 gen_op_store_asr();
284 RET_STOP(ctx);
285 }
286 #endif
287 #endif /* !defined(CONFIG_USER_ONLY) */
288
289 /* PowerPC 601 specific registers */
290 /* RTC */
291 static void spr_read_601_rtcl (void *opaque, int sprn)
292 {
293 gen_op_load_601_rtcl();
294 }
295
296 static void spr_read_601_rtcu (void *opaque, int sprn)
297 {
298 gen_op_load_601_rtcu();
299 }
300
301 #if !defined(CONFIG_USER_ONLY)
302 static void spr_write_601_rtcu (void *opaque, int sprn)
303 {
304 gen_op_store_601_rtcu();
305 }
306
307 static void spr_write_601_rtcl (void *opaque, int sprn)
308 {
309 gen_op_store_601_rtcl();
310 }
311 #endif
312
313 /* Unified bats */
314 #if !defined(CONFIG_USER_ONLY)
315 static void spr_read_601_ubat (void *opaque, int sprn)
316 {
317 gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
318 }
319
320 static void spr_write_601_ubatu (void *opaque, int sprn)
321 {
322 DisasContext *ctx = opaque;
323
324 gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
325 RET_STOP(ctx);
326 }
327
328 static void spr_write_601_ubatl (void *opaque, int sprn)
329 {
330 DisasContext *ctx = opaque;
331
332 gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
333 RET_STOP(ctx);
334 }
335 #endif
336
337 /* PowerPC 40x specific registers */
338 #if !defined(CONFIG_USER_ONLY)
339 static void spr_read_40x_pit (void *opaque, int sprn)
340 {
341 gen_op_load_40x_pit();
342 }
343
344 static void spr_write_40x_pit (void *opaque, int sprn)
345 {
346 gen_op_store_40x_pit();
347 }
348
349 static void spr_write_40x_dbcr0 (void *opaque, int sprn)
350 {
351 DisasContext *ctx = opaque;
352
353 gen_op_store_40x_dbcr0();
354 /* We must stop translation as we may have rebooted */
355 RET_STOP(ctx);
356 }
357
358 static void spr_write_booke_tcr (void *opaque, int sprn)
359 {
360 gen_op_store_booke_tcr();
361 }
362
363 static void spr_write_booke_tsr (void *opaque, int sprn)
364 {
365 gen_op_store_booke_tsr();
366 }
367 #endif
368
369 /* PowerPC 403 specific registers */
370 /* PBL1 / PBU1 / PBL2 / PBU2 */
371 #if !defined(CONFIG_USER_ONLY)
372 static void spr_read_403_pbr (void *opaque, int sprn)
373 {
374 gen_op_load_403_pb(sprn - SPR_403_PBL1);
375 }
376
377 static void spr_write_403_pbr (void *opaque, int sprn)
378 {
379 DisasContext *ctx = opaque;
380
381 gen_op_store_403_pb(sprn - SPR_403_PBL1);
382 RET_STOP(ctx);
383 }
384
385 static void spr_write_pir (void *opaque, int sprn)
386 {
387 gen_op_store_pir();
388 }
389 #endif
390
391 #if defined(CONFIG_USER_ONLY)
392 #define spr_register(env, num, name, uea_read, uea_write, \
393 oea_read, oea_write, initial_value) \
394 do { \
395 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
396 } while (0)
397 static inline void _spr_register (CPUPPCState *env, int num,
398 const unsigned char *name,
399 void (*uea_read)(void *opaque, int sprn),
400 void (*uea_write)(void *opaque, int sprn),
401 target_ulong initial_value)
402 #else
403 static inline void spr_register (CPUPPCState *env, int num,
404 const unsigned char *name,
405 void (*uea_read)(void *opaque, int sprn),
406 void (*uea_write)(void *opaque, int sprn),
407 void (*oea_read)(void *opaque, int sprn),
408 void (*oea_write)(void *opaque, int sprn),
409 target_ulong initial_value)
410 #endif
411 {
412 ppc_spr_t *spr;
413
414 spr = &env->spr_cb[num];
415 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
416 #if !defined(CONFIG_USER_ONLY)
417 spr->oea_read != NULL || spr->oea_write != NULL ||
418 #endif
419 spr->uea_read != NULL || spr->uea_write != NULL) {
420 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
421 exit(1);
422 }
423 #if defined(PPC_DEBUG_SPR)
424 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
425 initial_value);
426 #endif
427 spr->name = name;
428 spr->uea_read = uea_read;
429 spr->uea_write = uea_write;
430 #if !defined(CONFIG_USER_ONLY)
431 spr->oea_read = oea_read;
432 spr->oea_write = oea_write;
433 #endif
434 env->spr[num] = initial_value;
435 }
436
437 /* Generic PowerPC SPRs */
438 static void gen_spr_generic (CPUPPCState *env)
439 {
440 /* Integer processing */
441 spr_register(env, SPR_XER, "XER",
442 &spr_read_xer, &spr_write_xer,
443 &spr_read_xer, &spr_write_xer,
444 0x00000000);
445 /* Branch contol */
446 spr_register(env, SPR_LR, "LR",
447 &spr_read_lr, &spr_write_lr,
448 &spr_read_lr, &spr_write_lr,
449 0x00000000);
450 spr_register(env, SPR_CTR, "CTR",
451 &spr_read_ctr, &spr_write_ctr,
452 &spr_read_ctr, &spr_write_ctr,
453 0x00000000);
454 /* Interrupt processing */
455 spr_register(env, SPR_SRR0, "SRR0",
456 SPR_NOACCESS, SPR_NOACCESS,
457 &spr_read_generic, &spr_write_generic,
458 0x00000000);
459 spr_register(env, SPR_SRR1, "SRR1",
460 SPR_NOACCESS, SPR_NOACCESS,
461 &spr_read_generic, &spr_write_generic,
462 0x00000000);
463 /* Processor control */
464 spr_register(env, SPR_SPRG0, "SPRG0",
465 SPR_NOACCESS, SPR_NOACCESS,
466 &spr_read_generic, &spr_write_generic,
467 0x00000000);
468 spr_register(env, SPR_SPRG1, "SPRG1",
469 SPR_NOACCESS, SPR_NOACCESS,
470 &spr_read_generic, &spr_write_generic,
471 0x00000000);
472 spr_register(env, SPR_SPRG2, "SPRG2",
473 SPR_NOACCESS, SPR_NOACCESS,
474 &spr_read_generic, &spr_write_generic,
475 0x00000000);
476 spr_register(env, SPR_SPRG3, "SPRG3",
477 SPR_NOACCESS, SPR_NOACCESS,
478 &spr_read_generic, &spr_write_generic,
479 0x00000000);
480 }
481
482 /* SPR common to all non-embedded PowerPC, including 601 */
483 static void gen_spr_ne_601 (CPUPPCState *env)
484 {
485 /* Exception processing */
486 spr_register(env, SPR_DSISR, "DSISR",
487 SPR_NOACCESS, SPR_NOACCESS,
488 &spr_read_generic, &spr_write_generic,
489 0x00000000);
490 spr_register(env, SPR_DAR, "DAR",
491 SPR_NOACCESS, SPR_NOACCESS,
492 &spr_read_generic, &spr_write_generic,
493 0x00000000);
494 /* Timer */
495 spr_register(env, SPR_DECR, "DECR",
496 SPR_NOACCESS, SPR_NOACCESS,
497 &spr_read_decr, &spr_write_decr,
498 0x00000000);
499 /* Memory management */
500 spr_register(env, SPR_SDR1, "SDR1",
501 SPR_NOACCESS, SPR_NOACCESS,
502 &spr_read_sdr1, &spr_write_sdr1,
503 0x00000000);
504 }
505
506 /* BATs 0-3 */
507 static void gen_low_BATs (CPUPPCState *env)
508 {
509 spr_register(env, SPR_IBAT0U, "IBAT0U",
510 SPR_NOACCESS, SPR_NOACCESS,
511 &spr_read_ibat, &spr_write_ibatu,
512 0x00000000);
513 spr_register(env, SPR_IBAT0L, "IBAT0L",
514 SPR_NOACCESS, SPR_NOACCESS,
515 &spr_read_ibat, &spr_write_ibatl,
516 0x00000000);
517 spr_register(env, SPR_IBAT1U, "IBAT1U",
518 SPR_NOACCESS, SPR_NOACCESS,
519 &spr_read_ibat, &spr_write_ibatu,
520 0x00000000);
521 spr_register(env, SPR_IBAT1L, "IBAT1L",
522 SPR_NOACCESS, SPR_NOACCESS,
523 &spr_read_ibat, &spr_write_ibatl,
524 0x00000000);
525 spr_register(env, SPR_IBAT2U, "IBAT2U",
526 SPR_NOACCESS, SPR_NOACCESS,
527 &spr_read_ibat, &spr_write_ibatu,
528 0x00000000);
529 spr_register(env, SPR_IBAT2L, "IBAT2L",
530 SPR_NOACCESS, SPR_NOACCESS,
531 &spr_read_ibat, &spr_write_ibatl,
532 0x00000000);
533 spr_register(env, SPR_IBAT3U, "IBAT3U",
534 SPR_NOACCESS, SPR_NOACCESS,
535 &spr_read_ibat, &spr_write_ibatu,
536 0x00000000);
537 spr_register(env, SPR_IBAT3L, "IBAT3L",
538 SPR_NOACCESS, SPR_NOACCESS,
539 &spr_read_ibat, &spr_write_ibatl,
540 0x00000000);
541 spr_register(env, SPR_DBAT0U, "DBAT0U",
542 SPR_NOACCESS, SPR_NOACCESS,
543 &spr_read_dbat, &spr_write_dbatu,
544 0x00000000);
545 spr_register(env, SPR_DBAT0L, "DBAT0L",
546 SPR_NOACCESS, SPR_NOACCESS,
547 &spr_read_dbat, &spr_write_dbatl,
548 0x00000000);
549 spr_register(env, SPR_DBAT1U, "DBAT1U",
550 SPR_NOACCESS, SPR_NOACCESS,
551 &spr_read_dbat, &spr_write_dbatu,
552 0x00000000);
553 spr_register(env, SPR_DBAT1L, "DBAT1L",
554 SPR_NOACCESS, SPR_NOACCESS,
555 &spr_read_dbat, &spr_write_dbatl,
556 0x00000000);
557 spr_register(env, SPR_DBAT2U, "DBAT2U",
558 SPR_NOACCESS, SPR_NOACCESS,
559 &spr_read_dbat, &spr_write_dbatu,
560 0x00000000);
561 spr_register(env, SPR_DBAT2L, "DBAT2L",
562 SPR_NOACCESS, SPR_NOACCESS,
563 &spr_read_dbat, &spr_write_dbatl,
564 0x00000000);
565 spr_register(env, SPR_DBAT3U, "DBAT3U",
566 SPR_NOACCESS, SPR_NOACCESS,
567 &spr_read_dbat, &spr_write_dbatu,
568 0x00000000);
569 spr_register(env, SPR_DBAT3L, "DBAT3L",
570 SPR_NOACCESS, SPR_NOACCESS,
571 &spr_read_dbat, &spr_write_dbatl,
572 0x00000000);
573 env->nb_BATs = 4;
574 }
575
576 /* BATs 4-7 */
577 static void gen_high_BATs (CPUPPCState *env)
578 {
579 spr_register(env, SPR_IBAT4U, "IBAT4U",
580 SPR_NOACCESS, SPR_NOACCESS,
581 &spr_read_ibat_h, &spr_write_ibatu_h,
582 0x00000000);
583 spr_register(env, SPR_IBAT4L, "IBAT4L",
584 SPR_NOACCESS, SPR_NOACCESS,
585 &spr_read_ibat_h, &spr_write_ibatl_h,
586 0x00000000);
587 spr_register(env, SPR_IBAT5U, "IBAT5U",
588 SPR_NOACCESS, SPR_NOACCESS,
589 &spr_read_ibat_h, &spr_write_ibatu_h,
590 0x00000000);
591 spr_register(env, SPR_IBAT5L, "IBAT5L",
592 SPR_NOACCESS, SPR_NOACCESS,
593 &spr_read_ibat_h, &spr_write_ibatl_h,
594 0x00000000);
595 spr_register(env, SPR_IBAT6U, "IBAT6U",
596 SPR_NOACCESS, SPR_NOACCESS,
597 &spr_read_ibat_h, &spr_write_ibatu_h,
598 0x00000000);
599 spr_register(env, SPR_IBAT6L, "IBAT6L",
600 SPR_NOACCESS, SPR_NOACCESS,
601 &spr_read_ibat_h, &spr_write_ibatl_h,
602 0x00000000);
603 spr_register(env, SPR_IBAT7U, "IBAT7U",
604 SPR_NOACCESS, SPR_NOACCESS,
605 &spr_read_ibat_h, &spr_write_ibatu_h,
606 0x00000000);
607 spr_register(env, SPR_IBAT7L, "IBAT7L",
608 SPR_NOACCESS, SPR_NOACCESS,
609 &spr_read_ibat_h, &spr_write_ibatl_h,
610 0x00000000);
611 spr_register(env, SPR_DBAT4U, "DBAT4U",
612 SPR_NOACCESS, SPR_NOACCESS,
613 &spr_read_dbat_h, &spr_write_dbatu_h,
614 0x00000000);
615 spr_register(env, SPR_DBAT4L, "DBAT4L",
616 SPR_NOACCESS, SPR_NOACCESS,
617 &spr_read_dbat_h, &spr_write_dbatl_h,
618 0x00000000);
619 spr_register(env, SPR_DBAT5U, "DBAT5U",
620 SPR_NOACCESS, SPR_NOACCESS,
621 &spr_read_dbat_h, &spr_write_dbatu_h,
622 0x00000000);
623 spr_register(env, SPR_DBAT5L, "DBAT5L",
624 SPR_NOACCESS, SPR_NOACCESS,
625 &spr_read_dbat_h, &spr_write_dbatl_h,
626 0x00000000);
627 spr_register(env, SPR_DBAT6U, "DBAT6U",
628 SPR_NOACCESS, SPR_NOACCESS,
629 &spr_read_dbat_h, &spr_write_dbatu_h,
630 0x00000000);
631 spr_register(env, SPR_DBAT6L, "DBAT6L",
632 SPR_NOACCESS, SPR_NOACCESS,
633 &spr_read_dbat_h, &spr_write_dbatl_h,
634 0x00000000);
635 spr_register(env, SPR_DBAT7U, "DBAT7U",
636 SPR_NOACCESS, SPR_NOACCESS,
637 &spr_read_dbat_h, &spr_write_dbatu_h,
638 0x00000000);
639 spr_register(env, SPR_DBAT7L, "DBAT7L",
640 SPR_NOACCESS, SPR_NOACCESS,
641 &spr_read_dbat_h, &spr_write_dbatl_h,
642 0x00000000);
643 env->nb_BATs = 8;
644 }
645
646 /* Generic PowerPC time base */
647 static void gen_tbl (CPUPPCState *env)
648 {
649 spr_register(env, SPR_VTBL, "TBL",
650 &spr_read_tbl, SPR_NOACCESS,
651 &spr_read_tbl, SPR_NOACCESS,
652 0x00000000);
653 spr_register(env, SPR_TBL, "TBL",
654 SPR_NOACCESS, SPR_NOACCESS,
655 SPR_NOACCESS, &spr_write_tbl,
656 0x00000000);
657 spr_register(env, SPR_VTBU, "TBU",
658 &spr_read_tbu, SPR_NOACCESS,
659 &spr_read_tbu, SPR_NOACCESS,
660 0x00000000);
661 spr_register(env, SPR_TBU, "TBU",
662 SPR_NOACCESS, SPR_NOACCESS,
663 SPR_NOACCESS, &spr_write_tbu,
664 0x00000000);
665 }
666
667 /* Softare table search registers */
668 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
669 {
670 env->nb_tlb = nb_tlbs;
671 env->nb_ways = nb_ways;
672 env->id_tlbs = 1;
673 spr_register(env, SPR_DMISS, "DMISS",
674 SPR_NOACCESS, SPR_NOACCESS,
675 &spr_read_generic, SPR_NOACCESS,
676 0x00000000);
677 spr_register(env, SPR_DCMP, "DCMP",
678 SPR_NOACCESS, SPR_NOACCESS,
679 &spr_read_generic, SPR_NOACCESS,
680 0x00000000);
681 spr_register(env, SPR_HASH1, "HASH1",
682 SPR_NOACCESS, SPR_NOACCESS,
683 &spr_read_generic, SPR_NOACCESS,
684 0x00000000);
685 spr_register(env, SPR_HASH2, "HASH2",
686 SPR_NOACCESS, SPR_NOACCESS,
687 &spr_read_generic, SPR_NOACCESS,
688 0x00000000);
689 spr_register(env, SPR_IMISS, "IMISS",
690 SPR_NOACCESS, SPR_NOACCESS,
691 &spr_read_generic, SPR_NOACCESS,
692 0x00000000);
693 spr_register(env, SPR_ICMP, "ICMP",
694 SPR_NOACCESS, SPR_NOACCESS,
695 &spr_read_generic, SPR_NOACCESS,
696 0x00000000);
697 spr_register(env, SPR_RPA, "RPA",
698 SPR_NOACCESS, SPR_NOACCESS,
699 &spr_read_generic, &spr_write_generic,
700 0x00000000);
701 }
702
703 /* SPR common to MPC755 and G2 */
704 static void gen_spr_G2_755 (CPUPPCState *env)
705 {
706 /* SGPRs */
707 spr_register(env, SPR_SPRG4, "SPRG4",
708 SPR_NOACCESS, SPR_NOACCESS,
709 &spr_read_generic, &spr_write_generic,
710 0x00000000);
711 spr_register(env, SPR_SPRG5, "SPRG5",
712 SPR_NOACCESS, SPR_NOACCESS,
713 &spr_read_generic, &spr_write_generic,
714 0x00000000);
715 spr_register(env, SPR_SPRG6, "SPRG6",
716 SPR_NOACCESS, SPR_NOACCESS,
717 &spr_read_generic, &spr_write_generic,
718 0x00000000);
719 spr_register(env, SPR_SPRG7, "SPRG7",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_generic, &spr_write_generic,
722 0x00000000);
723 /* External access control */
724 /* XXX : not implemented */
725 spr_register(env, SPR_EAR, "EAR",
726 SPR_NOACCESS, SPR_NOACCESS,
727 &spr_read_generic, &spr_write_generic,
728 0x00000000);
729 }
730
731 /* SPR common to all 7xx PowerPC implementations */
732 static void gen_spr_7xx (CPUPPCState *env)
733 {
734 /* Breakpoints */
735 /* XXX : not implemented */
736 spr_register(env, SPR_DABR, "DABR",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_generic, &spr_write_generic,
739 0x00000000);
740 /* XXX : not implemented */
741 spr_register(env, SPR_IABR, "IABR",
742 SPR_NOACCESS, SPR_NOACCESS,
743 &spr_read_generic, &spr_write_generic,
744 0x00000000);
745 /* Cache management */
746 /* XXX : not implemented */
747 spr_register(env, SPR_ICTC, "ICTC",
748 SPR_NOACCESS, SPR_NOACCESS,
749 &spr_read_generic, &spr_write_generic,
750 0x00000000);
751 /* XXX : not implemented */
752 spr_register(env, SPR_L2CR, "L2CR",
753 SPR_NOACCESS, SPR_NOACCESS,
754 &spr_read_generic, &spr_write_generic,
755 0x00000000);
756 /* Performance monitors */
757 /* XXX : not implemented */
758 spr_register(env, SPR_MMCR0, "MMCR0",
759 SPR_NOACCESS, SPR_NOACCESS,
760 &spr_read_generic, &spr_write_generic,
761 0x00000000);
762 /* XXX : not implemented */
763 spr_register(env, SPR_MMCR1, "MMCR1",
764 SPR_NOACCESS, SPR_NOACCESS,
765 &spr_read_generic, &spr_write_generic,
766 0x00000000);
767 /* XXX : not implemented */
768 spr_register(env, SPR_PMC1, "PMC1",
769 SPR_NOACCESS, SPR_NOACCESS,
770 &spr_read_generic, &spr_write_generic,
771 0x00000000);
772 /* XXX : not implemented */
773 spr_register(env, SPR_PMC2, "PMC2",
774 SPR_NOACCESS, SPR_NOACCESS,
775 &spr_read_generic, &spr_write_generic,
776 0x00000000);
777 /* XXX : not implemented */
778 spr_register(env, SPR_PMC3, "PMC3",
779 SPR_NOACCESS, SPR_NOACCESS,
780 &spr_read_generic, &spr_write_generic,
781 0x00000000);
782 /* XXX : not implemented */
783 spr_register(env, SPR_PMC4, "PMC4",
784 SPR_NOACCESS, SPR_NOACCESS,
785 &spr_read_generic, &spr_write_generic,
786 0x00000000);
787 /* XXX : not implemented */
788 spr_register(env, SPR_SIA, "SIA",
789 SPR_NOACCESS, SPR_NOACCESS,
790 &spr_read_generic, SPR_NOACCESS,
791 0x00000000);
792 spr_register(env, SPR_UMMCR0, "UMMCR0",
793 &spr_read_ureg, SPR_NOACCESS,
794 &spr_read_ureg, SPR_NOACCESS,
795 0x00000000);
796 spr_register(env, SPR_UMMCR1, "UMMCR1",
797 &spr_read_ureg, SPR_NOACCESS,
798 &spr_read_ureg, SPR_NOACCESS,
799 0x00000000);
800 spr_register(env, SPR_UPMC1, "UPMC1",
801 &spr_read_ureg, SPR_NOACCESS,
802 &spr_read_ureg, SPR_NOACCESS,
803 0x00000000);
804 spr_register(env, SPR_UPMC2, "UPMC2",
805 &spr_read_ureg, SPR_NOACCESS,
806 &spr_read_ureg, SPR_NOACCESS,
807 0x00000000);
808 spr_register(env, SPR_UPMC3, "UPMC3",
809 &spr_read_ureg, SPR_NOACCESS,
810 &spr_read_ureg, SPR_NOACCESS,
811 0x00000000);
812 spr_register(env, SPR_UPMC4, "UPMC4",
813 &spr_read_ureg, SPR_NOACCESS,
814 &spr_read_ureg, SPR_NOACCESS,
815 0x00000000);
816 spr_register(env, SPR_USIA, "USIA",
817 &spr_read_ureg, SPR_NOACCESS,
818 &spr_read_ureg, SPR_NOACCESS,
819 0x00000000);
820 /* Thermal management */
821 /* XXX : not implemented */
822 spr_register(env, SPR_THRM1, "THRM1",
823 SPR_NOACCESS, SPR_NOACCESS,
824 &spr_read_generic, &spr_write_generic,
825 0x00000000);
826 /* XXX : not implemented */
827 spr_register(env, SPR_THRM2, "THRM2",
828 SPR_NOACCESS, SPR_NOACCESS,
829 &spr_read_generic, &spr_write_generic,
830 0x00000000);
831 /* XXX : not implemented */
832 spr_register(env, SPR_THRM3, "THRM3",
833 SPR_NOACCESS, SPR_NOACCESS,
834 &spr_read_generic, &spr_write_generic,
835 0x00000000);
836 /* External access control */
837 /* XXX : not implemented */
838 spr_register(env, SPR_EAR, "EAR",
839 SPR_NOACCESS, SPR_NOACCESS,
840 &spr_read_generic, &spr_write_generic,
841 0x00000000);
842 }
843
844 /* SPR specific to PowerPC 604 implementation */
845 static void gen_spr_604 (CPUPPCState *env)
846 {
847 /* Processor identification */
848 spr_register(env, SPR_PIR, "PIR",
849 SPR_NOACCESS, SPR_NOACCESS,
850 &spr_read_generic, &spr_write_pir,
851 0x00000000);
852 /* Breakpoints */
853 /* XXX : not implemented */
854 spr_register(env, SPR_IABR, "IABR",
855 SPR_NOACCESS, SPR_NOACCESS,
856 &spr_read_generic, &spr_write_generic,
857 0x00000000);
858 /* XXX : not implemented */
859 spr_register(env, SPR_DABR, "DABR",
860 SPR_NOACCESS, SPR_NOACCESS,
861 &spr_read_generic, &spr_write_generic,
862 0x00000000);
863 /* Performance counters */
864 /* XXX : not implemented */
865 spr_register(env, SPR_MMCR0, "MMCR0",
866 SPR_NOACCESS, SPR_NOACCESS,
867 &spr_read_generic, &spr_write_generic,
868 0x00000000);
869 /* XXX : not implemented */
870 spr_register(env, SPR_MMCR1, "MMCR1",
871 SPR_NOACCESS, SPR_NOACCESS,
872 &spr_read_generic, &spr_write_generic,
873 0x00000000);
874 /* XXX : not implemented */
875 spr_register(env, SPR_PMC1, "PMC1",
876 SPR_NOACCESS, SPR_NOACCESS,
877 &spr_read_generic, &spr_write_generic,
878 0x00000000);
879 /* XXX : not implemented */
880 spr_register(env, SPR_PMC2, "PMC2",
881 SPR_NOACCESS, SPR_NOACCESS,
882 &spr_read_generic, &spr_write_generic,
883 0x00000000);
884 /* XXX : not implemented */
885 spr_register(env, SPR_PMC3, "PMC3",
886 SPR_NOACCESS, SPR_NOACCESS,
887 &spr_read_generic, &spr_write_generic,
888 0x00000000);
889 /* XXX : not implemented */
890 spr_register(env, SPR_PMC4, "PMC4",
891 SPR_NOACCESS, SPR_NOACCESS,
892 &spr_read_generic, &spr_write_generic,
893 0x00000000);
894 /* XXX : not implemented */
895 spr_register(env, SPR_SIA, "SIA",
896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_generic, SPR_NOACCESS,
898 0x00000000);
899 /* XXX : not implemented */
900 spr_register(env, SPR_SDA, "SDA",
901 SPR_NOACCESS, SPR_NOACCESS,
902 &spr_read_generic, SPR_NOACCESS,
903 0x00000000);
904 /* External access control */
905 /* XXX : not implemented */
906 spr_register(env, SPR_EAR, "EAR",
907 SPR_NOACCESS, SPR_NOACCESS,
908 &spr_read_generic, &spr_write_generic,
909 0x00000000);
910 }
911
912 /* SPR specific to PowerPC 603 implementation */
913 static void gen_spr_603 (CPUPPCState *env)
914 {
915 /* External access control */
916 /* XXX : not implemented */
917 spr_register(env, SPR_EAR, "EAR",
918 SPR_NOACCESS, SPR_NOACCESS,
919 &spr_read_generic, &spr_write_generic,
920 0x00000000);
921 }
922
923 /* SPR specific to PowerPC G2 implementation */
924 static void gen_spr_G2 (CPUPPCState *env)
925 {
926 /* Memory base address */
927 /* MBAR */
928 spr_register(env, SPR_MBAR, "MBAR",
929 SPR_NOACCESS, SPR_NOACCESS,
930 &spr_read_generic, &spr_write_generic,
931 0x00000000);
932 /* System version register */
933 /* SVR */
934 spr_register(env, SPR_SVR, "SVR",
935 SPR_NOACCESS, SPR_NOACCESS,
936 &spr_read_generic, SPR_NOACCESS,
937 0x00000000);
938 /* Exception processing */
939 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
944 SPR_NOACCESS, SPR_NOACCESS,
945 &spr_read_generic, &spr_write_generic,
946 0x00000000);
947 /* Breakpoints */
948 /* XXX : not implemented */
949 spr_register(env, SPR_DABR, "DABR",
950 SPR_NOACCESS, SPR_NOACCESS,
951 &spr_read_generic, &spr_write_generic,
952 0x00000000);
953 /* XXX : not implemented */
954 spr_register(env, SPR_DABR2, "DABR2",
955 SPR_NOACCESS, SPR_NOACCESS,
956 &spr_read_generic, &spr_write_generic,
957 0x00000000);
958 /* XXX : not implemented */
959 spr_register(env, SPR_IABR, "IABR",
960 SPR_NOACCESS, SPR_NOACCESS,
961 &spr_read_generic, &spr_write_generic,
962 0x00000000);
963 /* XXX : not implemented */
964 spr_register(env, SPR_IABR2, "IABR2",
965 SPR_NOACCESS, SPR_NOACCESS,
966 &spr_read_generic, &spr_write_generic,
967 0x00000000);
968 /* XXX : not implemented */
969 spr_register(env, SPR_IBCR, "IBCR",
970 SPR_NOACCESS, SPR_NOACCESS,
971 &spr_read_generic, &spr_write_generic,
972 0x00000000);
973 /* XXX : not implemented */
974 spr_register(env, SPR_DBCR, "DBCR",
975 SPR_NOACCESS, SPR_NOACCESS,
976 &spr_read_generic, &spr_write_generic,
977 0x00000000);
978 }
979
980 /* SPR specific to PowerPC 602 implementation */
981 static void gen_spr_602 (CPUPPCState *env)
982 {
983 /* ESA registers */
984 /* XXX : not implemented */
985 spr_register(env, SPR_SER, "SER",
986 SPR_NOACCESS, SPR_NOACCESS,
987 &spr_read_generic, &spr_write_generic,
988 0x00000000);
989 /* XXX : not implemented */
990 spr_register(env, SPR_SEBR, "SEBR",
991 SPR_NOACCESS, SPR_NOACCESS,
992 &spr_read_generic, &spr_write_generic,
993 0x00000000);
994 /* XXX : not implemented */
995 spr_register(env, SPR_ESASR, "ESASR",
996 SPR_NOACCESS, SPR_NOACCESS,
997 &spr_read_generic, &spr_write_generic,
998 0x00000000);
999 /* Floating point status */
1000 /* XXX : not implemented */
1001 spr_register(env, SPR_SP, "SP",
1002 SPR_NOACCESS, SPR_NOACCESS,
1003 &spr_read_generic, &spr_write_generic,
1004 0x00000000);
1005 /* XXX : not implemented */
1006 spr_register(env, SPR_LT, "LT",
1007 SPR_NOACCESS, SPR_NOACCESS,
1008 &spr_read_generic, &spr_write_generic,
1009 0x00000000);
1010 /* Watchdog timer */
1011 /* XXX : not implemented */
1012 spr_register(env, SPR_TCR, "TCR",
1013 SPR_NOACCESS, SPR_NOACCESS,
1014 &spr_read_generic, &spr_write_generic,
1015 0x00000000);
1016 /* Interrupt base */
1017 spr_register(env, SPR_IBR, "IBR",
1018 SPR_NOACCESS, SPR_NOACCESS,
1019 &spr_read_generic, &spr_write_generic,
1020 0x00000000);
1021 }
1022
1023 /* SPR specific to PowerPC 601 implementation */
1024 static void gen_spr_601 (CPUPPCState *env)
1025 {
1026 /* Multiplication/division register */
1027 /* MQ */
1028 spr_register(env, SPR_MQ, "MQ",
1029 &spr_read_generic, &spr_write_generic,
1030 &spr_read_generic, &spr_write_generic,
1031 0x00000000);
1032 /* RTC registers */
1033 spr_register(env, SPR_601_RTCU, "RTCU",
1034 SPR_NOACCESS, SPR_NOACCESS,
1035 SPR_NOACCESS, &spr_write_601_rtcu,
1036 0x00000000);
1037 spr_register(env, SPR_601_VRTCU, "RTCU",
1038 &spr_read_601_rtcu, SPR_NOACCESS,
1039 &spr_read_601_rtcu, SPR_NOACCESS,
1040 0x00000000);
1041 spr_register(env, SPR_601_RTCL, "RTCL",
1042 SPR_NOACCESS, SPR_NOACCESS,
1043 SPR_NOACCESS, &spr_write_601_rtcl,
1044 0x00000000);
1045 spr_register(env, SPR_601_VRTCL, "RTCL",
1046 &spr_read_601_rtcl, SPR_NOACCESS,
1047 &spr_read_601_rtcl, SPR_NOACCESS,
1048 0x00000000);
1049 /* Timer */
1050 #if 0 /* ? */
1051 spr_register(env, SPR_601_UDECR, "UDECR",
1052 &spr_read_decr, SPR_NOACCESS,
1053 &spr_read_decr, SPR_NOACCESS,
1054 0x00000000);
1055 #endif
1056 /* External access control */
1057 /* XXX : not implemented */
1058 spr_register(env, SPR_EAR, "EAR",
1059 SPR_NOACCESS, SPR_NOACCESS,
1060 &spr_read_generic, &spr_write_generic,
1061 0x00000000);
1062 /* Memory management */
1063 spr_register(env, SPR_IBAT0U, "IBAT0U",
1064 SPR_NOACCESS, SPR_NOACCESS,
1065 &spr_read_601_ubat, &spr_write_601_ubatu,
1066 0x00000000);
1067 spr_register(env, SPR_IBAT0L, "IBAT0L",
1068 SPR_NOACCESS, SPR_NOACCESS,
1069 &spr_read_601_ubat, &spr_write_601_ubatl,
1070 0x00000000);
1071 spr_register(env, SPR_IBAT1U, "IBAT1U",
1072 SPR_NOACCESS, SPR_NOACCESS,
1073 &spr_read_601_ubat, &spr_write_601_ubatu,
1074 0x00000000);
1075 spr_register(env, SPR_IBAT1L, "IBAT1L",
1076 SPR_NOACCESS, SPR_NOACCESS,
1077 &spr_read_601_ubat, &spr_write_601_ubatl,
1078 0x00000000);
1079 spr_register(env, SPR_IBAT2U, "IBAT2U",
1080 SPR_NOACCESS, SPR_NOACCESS,
1081 &spr_read_601_ubat, &spr_write_601_ubatu,
1082 0x00000000);
1083 spr_register(env, SPR_IBAT2L, "IBAT2L",
1084 SPR_NOACCESS, SPR_NOACCESS,
1085 &spr_read_601_ubat, &spr_write_601_ubatl,
1086 0x00000000);
1087 spr_register(env, SPR_IBAT3U, "IBAT3U",
1088 SPR_NOACCESS, SPR_NOACCESS,
1089 &spr_read_601_ubat, &spr_write_601_ubatu,
1090 0x00000000);
1091 spr_register(env, SPR_IBAT3L, "IBAT3L",
1092 SPR_NOACCESS, SPR_NOACCESS,
1093 &spr_read_601_ubat, &spr_write_601_ubatl,
1094 0x00000000);
1095 }
1096
1097 /* PowerPC BookE SPR */
1098 static void gen_spr_BookE (CPUPPCState *env)
1099 {
1100 /* Processor identification */
1101 spr_register(env, SPR_BOOKE_PIR, "PIR",
1102 SPR_NOACCESS, SPR_NOACCESS,
1103 &spr_read_generic, &spr_write_pir,
1104 0x00000000);
1105 /* Interrupt processing */
1106 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1107 SPR_NOACCESS, SPR_NOACCESS,
1108 &spr_read_generic, &spr_write_generic,
1109 0x00000000);
1110 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1111 SPR_NOACCESS, SPR_NOACCESS,
1112 &spr_read_generic, &spr_write_generic,
1113 0x00000000);
1114 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1115 SPR_NOACCESS, SPR_NOACCESS,
1116 &spr_read_generic, &spr_write_generic,
1117 0x00000000);
1118 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1119 SPR_NOACCESS, SPR_NOACCESS,
1120 &spr_read_generic, &spr_write_generic,
1121 0x00000000);
1122 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
1123 SPR_NOACCESS, SPR_NOACCESS,
1124 &spr_read_generic, &spr_write_generic,
1125 0x00000000);
1126 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
1127 SPR_NOACCESS, SPR_NOACCESS,
1128 &spr_read_generic, &spr_write_generic,
1129 0x00000000);
1130 /* Debug */
1131 /* XXX : not implemented */
1132 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1133 SPR_NOACCESS, SPR_NOACCESS,
1134 &spr_read_generic, &spr_write_generic,
1135 0x00000000);
1136 /* XXX : not implemented */
1137 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1138 SPR_NOACCESS, SPR_NOACCESS,
1139 &spr_read_generic, &spr_write_generic,
1140 0x00000000);
1141 /* XXX : not implemented */
1142 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1143 SPR_NOACCESS, SPR_NOACCESS,
1144 &spr_read_generic, &spr_write_generic,
1145 0x00000000);
1146 /* XXX : not implemented */
1147 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1148 SPR_NOACCESS, SPR_NOACCESS,
1149 &spr_read_generic, &spr_write_generic,
1150 0x00000000);
1151 /* XXX : not implemented */
1152 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1153 SPR_NOACCESS, SPR_NOACCESS,
1154 &spr_read_generic, &spr_write_generic,
1155 0x00000000);
1156 /* XXX : not implemented */
1157 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1158 SPR_NOACCESS, SPR_NOACCESS,
1159 &spr_read_generic, &spr_write_generic,
1160 0x00000000);
1161 /* XXX : not implemented */
1162 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1163 SPR_NOACCESS, SPR_NOACCESS,
1164 &spr_read_generic, &spr_write_generic,
1165 0x00000000);
1166 /* XXX : not implemented */
1167 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1168 SPR_NOACCESS, SPR_NOACCESS,
1169 &spr_read_generic, &spr_write_generic,
1170 0x00000000);
1171 /* XXX : not implemented */
1172 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_generic, &spr_write_generic,
1175 0x00000000);
1176 /* XXX : not implemented */
1177 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1178 SPR_NOACCESS, SPR_NOACCESS,
1179 &spr_read_generic, &spr_write_generic,
1180 0x00000000);
1181 /* XXX : not implemented */
1182 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1183 SPR_NOACCESS, SPR_NOACCESS,
1184 &spr_read_generic, &spr_write_generic,
1185 0x00000000);
1186 /* XXX : not implemented */
1187 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1188 SPR_NOACCESS, SPR_NOACCESS,
1189 &spr_read_generic, &spr_write_clear,
1190 0x00000000);
1191 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
1195 spr_register(env, SPR_BOOKE_ESR, "ESR",
1196 SPR_NOACCESS, SPR_NOACCESS,
1197 &spr_read_generic, &spr_write_generic,
1198 0x00000000);
1199 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1200 SPR_NOACCESS, SPR_NOACCESS,
1201 &spr_read_generic, &spr_write_generic,
1202 0x00000000);
1203 /* Exception vectors */
1204 spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1205 SPR_NOACCESS, SPR_NOACCESS,
1206 &spr_read_generic, &spr_write_generic,
1207 0x00000000);
1208 spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1209 SPR_NOACCESS, SPR_NOACCESS,
1210 &spr_read_generic, &spr_write_generic,
1211 0x00000000);
1212 spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1213 SPR_NOACCESS, SPR_NOACCESS,
1214 &spr_read_generic, &spr_write_generic,
1215 0x00000000);
1216 spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1217 SPR_NOACCESS, SPR_NOACCESS,
1218 &spr_read_generic, &spr_write_generic,
1219 0x00000000);
1220 spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1221 SPR_NOACCESS, SPR_NOACCESS,
1222 &spr_read_generic, &spr_write_generic,
1223 0x00000000);
1224 spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1225 SPR_NOACCESS, SPR_NOACCESS,
1226 &spr_read_generic, &spr_write_generic,
1227 0x00000000);
1228 spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1229 SPR_NOACCESS, SPR_NOACCESS,
1230 &spr_read_generic, &spr_write_generic,
1231 0x00000000);
1232 spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_generic, &spr_write_generic,
1235 0x00000000);
1236 spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1237 SPR_NOACCESS, SPR_NOACCESS,
1238 &spr_read_generic, &spr_write_generic,
1239 0x00000000);
1240 spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1241 SPR_NOACCESS, SPR_NOACCESS,
1242 &spr_read_generic, &spr_write_generic,
1243 0x00000000);
1244 spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1245 SPR_NOACCESS, SPR_NOACCESS,
1246 &spr_read_generic, &spr_write_generic,
1247 0x00000000);
1248 spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1249 SPR_NOACCESS, SPR_NOACCESS,
1250 &spr_read_generic, &spr_write_generic,
1251 0x00000000);
1252 spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1253 SPR_NOACCESS, SPR_NOACCESS,
1254 &spr_read_generic, &spr_write_generic,
1255 0x00000000);
1256 spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1257 SPR_NOACCESS, SPR_NOACCESS,
1258 &spr_read_generic, &spr_write_generic,
1259 0x00000000);
1260 spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1261 SPR_NOACCESS, SPR_NOACCESS,
1262 &spr_read_generic, &spr_write_generic,
1263 0x00000000);
1264 spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_generic,
1267 0x00000000);
1268 spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1269 SPR_NOACCESS, SPR_NOACCESS,
1270 &spr_read_generic, &spr_write_generic,
1271 0x00000000);
1272 spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1273 SPR_NOACCESS, SPR_NOACCESS,
1274 &spr_read_generic, &spr_write_generic,
1275 0x00000000);
1276 spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1277 SPR_NOACCESS, SPR_NOACCESS,
1278 &spr_read_generic, &spr_write_generic,
1279 0x00000000);
1280 spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1281 SPR_NOACCESS, SPR_NOACCESS,
1282 &spr_read_generic, &spr_write_generic,
1283 0x00000000);
1284 spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1285 SPR_NOACCESS, SPR_NOACCESS,
1286 &spr_read_generic, &spr_write_generic,
1287 0x00000000);
1288 spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1289 SPR_NOACCESS, SPR_NOACCESS,
1290 &spr_read_generic, &spr_write_generic,
1291 0x00000000);
1292 spr_register(env, SPR_BOOKE_PID, "PID",
1293 SPR_NOACCESS, SPR_NOACCESS,
1294 &spr_read_generic, &spr_write_generic,
1295 0x00000000);
1296 spr_register(env, SPR_BOOKE_TCR, "TCR",
1297 SPR_NOACCESS, SPR_NOACCESS,
1298 &spr_read_generic, &spr_write_booke_tcr,
1299 0x00000000);
1300 spr_register(env, SPR_BOOKE_TSR, "TSR",
1301 SPR_NOACCESS, SPR_NOACCESS,
1302 &spr_read_generic, &spr_write_booke_tsr,
1303 0x00000000);
1304 /* Timer */
1305 spr_register(env, SPR_DECR, "DECR",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_decr, &spr_write_decr,
1308 0x00000000);
1309 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1310 SPR_NOACCESS, SPR_NOACCESS,
1311 SPR_NOACCESS, &spr_write_generic,
1312 0x00000000);
1313 /* SPRGs */
1314 spr_register(env, SPR_USPRG0, "USPRG0",
1315 &spr_read_generic, &spr_write_generic,
1316 &spr_read_generic, &spr_write_generic,
1317 0x00000000);
1318 spr_register(env, SPR_SPRG4, "SPRG4",
1319 SPR_NOACCESS, SPR_NOACCESS,
1320 &spr_read_generic, &spr_write_generic,
1321 0x00000000);
1322 spr_register(env, SPR_USPRG4, "USPRG4",
1323 &spr_read_ureg, SPR_NOACCESS,
1324 &spr_read_ureg, SPR_NOACCESS,
1325 0x00000000);
1326 spr_register(env, SPR_SPRG5, "SPRG5",
1327 SPR_NOACCESS, SPR_NOACCESS,
1328 &spr_read_generic, &spr_write_generic,
1329 0x00000000);
1330 spr_register(env, SPR_USPRG5, "USPRG5",
1331 &spr_read_ureg, SPR_NOACCESS,
1332 &spr_read_ureg, SPR_NOACCESS,
1333 0x00000000);
1334 spr_register(env, SPR_SPRG6, "SPRG6",
1335 SPR_NOACCESS, SPR_NOACCESS,
1336 &spr_read_generic, &spr_write_generic,
1337 0x00000000);
1338 spr_register(env, SPR_USPRG6, "USPRG6",
1339 &spr_read_ureg, SPR_NOACCESS,
1340 &spr_read_ureg, SPR_NOACCESS,
1341 0x00000000);
1342 spr_register(env, SPR_SPRG7, "SPRG7",
1343 SPR_NOACCESS, SPR_NOACCESS,
1344 &spr_read_generic, &spr_write_generic,
1345 0x00000000);
1346 spr_register(env, SPR_USPRG7, "USPRG7",
1347 &spr_read_ureg, SPR_NOACCESS,
1348 &spr_read_ureg, SPR_NOACCESS,
1349 0x00000000);
1350 }
1351
1352 /* FSL storage control registers */
1353 static void gen_spr_BookE_FSL (CPUPPCState *env)
1354 {
1355 /* TLB assist registers */
1356 spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1357 SPR_NOACCESS, SPR_NOACCESS,
1358 &spr_read_generic, &spr_write_generic,
1359 0x00000000);
1360 spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1361 SPR_NOACCESS, SPR_NOACCESS,
1362 &spr_read_generic, &spr_write_generic,
1363 0x00000000);
1364 spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1365 SPR_NOACCESS, SPR_NOACCESS,
1366 &spr_read_generic, &spr_write_generic,
1367 0x00000000);
1368 spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1369 SPR_NOACCESS, SPR_NOACCESS,
1370 &spr_read_generic, &spr_write_generic,
1371 0x00000000);
1372 spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1373 SPR_NOACCESS, SPR_NOACCESS,
1374 &spr_read_generic, &spr_write_generic,
1375 0x00000000);
1376 spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1377 SPR_NOACCESS, SPR_NOACCESS,
1378 &spr_read_generic, &spr_write_generic,
1379 0x00000000);
1380 spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1381 SPR_NOACCESS, SPR_NOACCESS,
1382 &spr_read_generic, &spr_write_generic,
1383 0x00000000);
1384 if (env->nb_pids > 1) {
1385 spr_register(env, SPR_BOOKE_PID1, "PID1",
1386 SPR_NOACCESS, SPR_NOACCESS,
1387 &spr_read_generic, &spr_write_generic,
1388 0x00000000);
1389 }
1390 if (env->nb_pids > 2) {
1391 spr_register(env, SPR_BOOKE_PID2, "PID2",
1392 SPR_NOACCESS, SPR_NOACCESS,
1393 &spr_read_generic, &spr_write_generic,
1394 0x00000000);
1395 }
1396 spr_register(env, SPR_BOOKE_MMUCFG, "MMUCFG",
1397 SPR_NOACCESS, SPR_NOACCESS,
1398 &spr_read_generic, SPR_NOACCESS,
1399 0x00000000); /* TOFIX */
1400 spr_register(env, SPR_BOOKE_MMUCSR0, "MMUCSR0",
1401 SPR_NOACCESS, SPR_NOACCESS,
1402 &spr_read_generic, &spr_write_generic,
1403 0x00000000); /* TOFIX */
1404 switch (env->nb_ways) {
1405 case 4:
1406 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1407 SPR_NOACCESS, SPR_NOACCESS,
1408 &spr_read_generic, SPR_NOACCESS,
1409 0x00000000); /* TOFIX */
1410 /* Fallthru */
1411 case 3:
1412 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1413 SPR_NOACCESS, SPR_NOACCESS,
1414 &spr_read_generic, SPR_NOACCESS,
1415 0x00000000); /* TOFIX */
1416 /* Fallthru */
1417 case 2:
1418 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1419 SPR_NOACCESS, SPR_NOACCESS,
1420 &spr_read_generic, SPR_NOACCESS,
1421 0x00000000); /* TOFIX */
1422 /* Fallthru */
1423 case 1:
1424 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1425 SPR_NOACCESS, SPR_NOACCESS,
1426 &spr_read_generic, SPR_NOACCESS,
1427 0x00000000); /* TOFIX */
1428 /* Fallthru */
1429 case 0:
1430 default:
1431 break;
1432 }
1433 }
1434
1435 /* SPR specific to PowerPC 440 implementation */
1436 static void gen_spr_440 (CPUPPCState *env)
1437 {
1438 /* Cache control */
1439 /* XXX : not implemented */
1440 spr_register(env, SPR_440_DNV0, "DNV0",
1441 SPR_NOACCESS, SPR_NOACCESS,
1442 &spr_read_generic, &spr_write_generic,
1443 0x00000000);
1444 /* XXX : not implemented */
1445 spr_register(env, SPR_440_DNV1, "DNV1",
1446 SPR_NOACCESS, SPR_NOACCESS,
1447 &spr_read_generic, &spr_write_generic,
1448 0x00000000);
1449 /* XXX : not implemented */
1450 spr_register(env, SPR_440_DNV2, "DNV2",
1451 SPR_NOACCESS, SPR_NOACCESS,
1452 &spr_read_generic, &spr_write_generic,
1453 0x00000000);
1454 /* XXX : not implemented */
1455 spr_register(env, SPR_440_DNV3, "DNV3",
1456 SPR_NOACCESS, SPR_NOACCESS,
1457 &spr_read_generic, &spr_write_generic,
1458 0x00000000);
1459 /* XXX : not implemented */
1460 spr_register(env, SPR_440_DVT0, "DVT0",
1461 SPR_NOACCESS, SPR_NOACCESS,
1462 &spr_read_generic, &spr_write_generic,
1463 0x00000000);
1464 /* XXX : not implemented */
1465 spr_register(env, SPR_440_DVT1, "DVT1",
1466 SPR_NOACCESS, SPR_NOACCESS,
1467 &spr_read_generic, &spr_write_generic,
1468 0x00000000);
1469 /* XXX : not implemented */
1470 spr_register(env, SPR_440_DVT2, "DVT2",
1471 SPR_NOACCESS, SPR_NOACCESS,
1472 &spr_read_generic, &spr_write_generic,
1473 0x00000000);
1474 /* XXX : not implemented */
1475 spr_register(env, SPR_440_DVT3, "DVT3",
1476 SPR_NOACCESS, SPR_NOACCESS,
1477 &spr_read_generic, &spr_write_generic,
1478 0x00000000);
1479 /* XXX : not implemented */
1480 spr_register(env, SPR_440_DVLIM, "DVLIM",
1481 SPR_NOACCESS, SPR_NOACCESS,
1482 &spr_read_generic, &spr_write_generic,
1483 0x00000000);
1484 /* XXX : not implemented */
1485 spr_register(env, SPR_440_INV0, "INV0",
1486 SPR_NOACCESS, SPR_NOACCESS,
1487 &spr_read_generic, &spr_write_generic,
1488 0x00000000);
1489 /* XXX : not implemented */
1490 spr_register(env, SPR_440_INV1, "INV1",
1491 SPR_NOACCESS, SPR_NOACCESS,
1492 &spr_read_generic, &spr_write_generic,
1493 0x00000000);
1494 /* XXX : not implemented */
1495 spr_register(env, SPR_440_INV2, "INV2",
1496 SPR_NOACCESS, SPR_NOACCESS,
1497 &spr_read_generic, &spr_write_generic,
1498 0x00000000);
1499 /* XXX : not implemented */
1500 spr_register(env, SPR_440_INV3, "INV3",
1501 SPR_NOACCESS, SPR_NOACCESS,
1502 &spr_read_generic, &spr_write_generic,
1503 0x00000000);
1504 /* XXX : not implemented */
1505 spr_register(env, SPR_440_IVT0, "IVT0",
1506 SPR_NOACCESS, SPR_NOACCESS,
1507 &spr_read_generic, &spr_write_generic,
1508 0x00000000);
1509 /* XXX : not implemented */
1510 spr_register(env, SPR_440_IVT1, "IVT1",
1511 SPR_NOACCESS, SPR_NOACCESS,
1512 &spr_read_generic, &spr_write_generic,
1513 0x00000000);
1514 /* XXX : not implemented */
1515 spr_register(env, SPR_440_IVT2, "IVT2",
1516 SPR_NOACCESS, SPR_NOACCESS,
1517 &spr_read_generic, &spr_write_generic,
1518 0x00000000);
1519 /* XXX : not implemented */
1520 spr_register(env, SPR_440_IVT3, "IVT3",
1521 SPR_NOACCESS, SPR_NOACCESS,
1522 &spr_read_generic, &spr_write_generic,
1523 0x00000000);
1524 /* XXX : not implemented */
1525 spr_register(env, SPR_440_IVLIM, "IVLIM",
1526 SPR_NOACCESS, SPR_NOACCESS,
1527 &spr_read_generic, &spr_write_generic,
1528 0x00000000);
1529 /* Cache debug */
1530 /* XXX : not implemented */
1531 spr_register(env, SPR_BOOKE_DCBTRH, "DCBTRH",
1532 SPR_NOACCESS, SPR_NOACCESS,
1533 &spr_read_generic, SPR_NOACCESS,
1534 0x00000000);
1535 /* XXX : not implemented */
1536 spr_register(env, SPR_BOOKE_DCBTRL, "DCBTRL",
1537 SPR_NOACCESS, SPR_NOACCESS,
1538 &spr_read_generic, SPR_NOACCESS,
1539 0x00000000);
1540 /* XXX : not implemented */
1541 spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
1542 SPR_NOACCESS, SPR_NOACCESS,
1543 &spr_read_generic, SPR_NOACCESS,
1544 0x00000000);
1545 /* XXX : not implemented */
1546 spr_register(env, SPR_BOOKE_ICBTRH, "ICBTRH",
1547 SPR_NOACCESS, SPR_NOACCESS,
1548 &spr_read_generic, SPR_NOACCESS,
1549 0x00000000);
1550 /* XXX : not implemented */
1551 spr_register(env, SPR_BOOKE_ICBTRL, "ICBTRL",
1552 SPR_NOACCESS, SPR_NOACCESS,
1553 &spr_read_generic, SPR_NOACCESS,
1554 0x00000000);
1555 /* XXX : not implemented */
1556 spr_register(env, SPR_440_DBDR, "DBDR",
1557 SPR_NOACCESS, SPR_NOACCESS,
1558 &spr_read_generic, &spr_write_generic,
1559 0x00000000);
1560 /* Processor control */
1561 spr_register(env, SPR_4xx_CCR0, "CCR0",
1562 SPR_NOACCESS, SPR_NOACCESS,
1563 &spr_read_generic, &spr_write_generic,
1564 0x00000000);
1565 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1566 SPR_NOACCESS, SPR_NOACCESS,
1567 &spr_read_generic, SPR_NOACCESS,
1568 0x00000000);
1569 /* Storage control */
1570 spr_register(env, SPR_440_MMUCR, "MMUCR",
1571 SPR_NOACCESS, SPR_NOACCESS,
1572 &spr_read_generic, &spr_write_generic,
1573 0x00000000);
1574 }
1575
1576 /* SPR shared between PowerPC 40x implementations */
1577 static void gen_spr_40x (CPUPPCState *env)
1578 {
1579 /* Cache */
1580 /* XXX : not implemented */
1581 spr_register(env, SPR_40x_DCCR, "DCCR",
1582 SPR_NOACCESS, SPR_NOACCESS,
1583 &spr_read_generic, &spr_write_generic,
1584 0x00000000);
1585 /* XXX : not implemented */
1586 spr_register(env, SPR_40x_DCWR, "DCWR",
1587 SPR_NOACCESS, SPR_NOACCESS,
1588 &spr_read_generic, &spr_write_generic,
1589 0x00000000);
1590 /* XXX : not implemented */
1591 spr_register(env, SPR_40x_ICCR, "ICCR",
1592 SPR_NOACCESS, SPR_NOACCESS,
1593 &spr_read_generic, &spr_write_generic,
1594 0x00000000);
1595 /* XXX : not implemented */
1596 spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
1597 SPR_NOACCESS, SPR_NOACCESS,
1598 &spr_read_generic, SPR_NOACCESS,
1599 0x00000000);
1600 /* Bus access control */
1601 spr_register(env, SPR_40x_SGR, "SGR",
1602 SPR_NOACCESS, SPR_NOACCESS,
1603 &spr_read_generic, &spr_write_generic,
1604 0xFFFFFFFF);
1605 spr_register(env, SPR_40x_ZPR, "ZPR",
1606 SPR_NOACCESS, SPR_NOACCESS,
1607 &spr_read_generic, &spr_write_generic,
1608 0x00000000);
1609 /* MMU */
1610 spr_register(env, SPR_40x_PID, "PID",
1611 SPR_NOACCESS, SPR_NOACCESS,
1612 &spr_read_generic, &spr_write_generic,
1613 0x00000000);
1614 /* Exception */
1615 spr_register(env, SPR_40x_DEAR, "DEAR",
1616 SPR_NOACCESS, SPR_NOACCESS,
1617 &spr_read_generic, &spr_write_generic,
1618 0x00000000);
1619 spr_register(env, SPR_40x_ESR, "ESR",
1620 SPR_NOACCESS, SPR_NOACCESS,
1621 &spr_read_generic, &spr_write_generic,
1622 0x00000000);
1623 spr_register(env, SPR_40x_EVPR, "EVPR",
1624 SPR_NOACCESS, SPR_NOACCESS,
1625 &spr_read_generic, &spr_write_generic,
1626 0x00000000);
1627 spr_register(env, SPR_40x_SRR2, "SRR2",
1628 &spr_read_generic, &spr_write_generic,
1629 &spr_read_generic, &spr_write_generic,
1630 0x00000000);
1631 spr_register(env, SPR_40x_SRR3, "SRR3",
1632 &spr_read_generic, &spr_write_generic,
1633 &spr_read_generic, &spr_write_generic,
1634 0x00000000);
1635 /* Timers */
1636 spr_register(env, SPR_40x_PIT, "PIT",
1637 SPR_NOACCESS, SPR_NOACCESS,
1638 &spr_read_40x_pit, &spr_write_40x_pit,
1639 0x00000000);
1640 spr_register(env, SPR_40x_TCR, "TCR",
1641 SPR_NOACCESS, SPR_NOACCESS,
1642 &spr_read_generic, &spr_write_booke_tcr,
1643 0x00000000);
1644 spr_register(env, SPR_40x_TSR, "TSR",
1645 SPR_NOACCESS, SPR_NOACCESS,
1646 &spr_read_generic, &spr_write_booke_tsr,
1647 0x00000000);
1648 /* Debug interface */
1649 /* XXX : not implemented */
1650 spr_register(env, SPR_40x_DAC1, "DAC1",
1651 SPR_NOACCESS, SPR_NOACCESS,
1652 &spr_read_generic, &spr_write_generic,
1653 0x00000000);
1654 spr_register(env, SPR_40x_DAC2, "DAC2",
1655 SPR_NOACCESS, SPR_NOACCESS,
1656 &spr_read_generic, &spr_write_generic,
1657 0x00000000);
1658 /* XXX : not implemented */
1659 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1660 SPR_NOACCESS, SPR_NOACCESS,
1661 &spr_read_generic, &spr_write_40x_dbcr0,
1662 0x00000000);
1663 /* XXX : not implemented */
1664 spr_register(env, SPR_40x_DBSR, "DBSR",
1665 SPR_NOACCESS, SPR_NOACCESS,
1666 &spr_read_generic, &spr_write_clear,
1667 /* Last reset was system reset */
1668 0x00000300);
1669 /* XXX : not implemented */
1670 spr_register(env, SPR_40x_IAC1, "IAC1",
1671 SPR_NOACCESS, SPR_NOACCESS,
1672 &spr_read_generic, &spr_write_generic,
1673 0x00000000);
1674 spr_register(env, SPR_40x_IAC2, "IAC2",
1675 SPR_NOACCESS, SPR_NOACCESS,
1676 &spr_read_generic, &spr_write_generic,
1677 0x00000000);
1678 }
1679
1680 /* SPR specific to PowerPC 405 implementation */
1681 static void gen_spr_405 (CPUPPCState *env)
1682 {
1683 spr_register(env, SPR_4xx_CCR0, "CCR0",
1684 SPR_NOACCESS, SPR_NOACCESS,
1685 &spr_read_generic, &spr_write_generic,
1686 0x00700000);
1687 /* Debug */
1688 /* XXX : not implemented */
1689 spr_register(env, SPR_405_DBCR1, "DBCR1",
1690 SPR_NOACCESS, SPR_NOACCESS,
1691 &spr_read_generic, &spr_write_generic,
1692 0x00000000);
1693 /* XXX : not implemented */
1694 spr_register(env, SPR_405_DVC1, "DVC1",
1695 SPR_NOACCESS, SPR_NOACCESS,
1696 &spr_read_generic, &spr_write_generic,
1697 0x00000000);
1698 /* XXX : not implemented */
1699 spr_register(env, SPR_405_DVC2, "DVC2",
1700 SPR_NOACCESS, SPR_NOACCESS,
1701 &spr_read_generic, &spr_write_generic,
1702 0x00000000);
1703 /* XXX : not implemented */
1704 spr_register(env, SPR_405_IAC3, "IAC3",
1705 SPR_NOACCESS, SPR_NOACCESS,
1706 &spr_read_generic, &spr_write_generic,
1707 0x00000000);
1708 /* XXX : not implemented */
1709 spr_register(env, SPR_405_IAC4, "IAC4",
1710 SPR_NOACCESS, SPR_NOACCESS,
1711 &spr_read_generic, &spr_write_generic,
1712 0x00000000);
1713 /* Storage control */
1714 /* XXX : not implemented */
1715 spr_register(env, SPR_405_SLER, "SLER",
1716 SPR_NOACCESS, SPR_NOACCESS,
1717 &spr_read_generic, &spr_write_generic,
1718 0x00000000);
1719 /* XXX : not implemented */
1720 spr_register(env, SPR_405_SU0R, "SU0R",
1721 SPR_NOACCESS, SPR_NOACCESS,
1722 &spr_read_generic, &spr_write_generic,
1723 0x00000000);
1724 /* SPRG */
1725 spr_register(env, SPR_USPRG0, "USPRG0",
1726 &spr_read_ureg, SPR_NOACCESS,
1727 &spr_read_ureg, SPR_NOACCESS,
1728 0x00000000);
1729 spr_register(env, SPR_SPRG4, "SPRG4",
1730 SPR_NOACCESS, SPR_NOACCESS,
1731 &spr_read_generic, &spr_write_generic,
1732 0x00000000);
1733 spr_register(env, SPR_USPRG4, "USPRG4",
1734 &spr_read_ureg, SPR_NOACCESS,
1735 &spr_read_ureg, SPR_NOACCESS,
1736 0x00000000);
1737 spr_register(env, SPR_SPRG5, "SPRG5",
1738 SPR_NOACCESS, SPR_NOACCESS,
1739 spr_read_generic, &spr_write_generic,
1740 0x00000000);
1741 spr_register(env, SPR_USPRG5, "USPRG5",
1742 &spr_read_ureg, SPR_NOACCESS,
1743 &spr_read_ureg, SPR_NOACCESS,
1744 0x00000000);
1745 spr_register(env, SPR_SPRG6, "SPRG6",
1746 SPR_NOACCESS, SPR_NOACCESS,
1747 spr_read_generic, &spr_write_generic,
1748 0x00000000);
1749 spr_register(env, SPR_USPRG6, "USPRG6",
1750 &spr_read_ureg, SPR_NOACCESS,
1751 &spr_read_ureg, SPR_NOACCESS,
1752 0x00000000);
1753 spr_register(env, SPR_SPRG7, "SPRG7",
1754 SPR_NOACCESS, SPR_NOACCESS,
1755 spr_read_generic, &spr_write_generic,
1756 0x00000000);
1757 spr_register(env, SPR_USPRG7, "USPRG7",
1758 &spr_read_ureg, SPR_NOACCESS,
1759 &spr_read_ureg, SPR_NOACCESS,
1760 0x00000000);
1761 }
1762
1763 /* SPR shared between PowerPC 401 & 403 implementations */
1764 static void gen_spr_401_403 (CPUPPCState *env)
1765 {
1766 /* Time base */
1767 spr_register(env, SPR_403_VTBL, "TBL",
1768 &spr_read_tbl, SPR_NOACCESS,
1769 &spr_read_tbl, SPR_NOACCESS,
1770 0x00000000);
1771 spr_register(env, SPR_403_TBL, "TBL",
1772 SPR_NOACCESS, SPR_NOACCESS,
1773 SPR_NOACCESS, &spr_write_tbl,
1774 0x00000000);
1775 spr_register(env, SPR_403_VTBU, "TBU",
1776 &spr_read_tbu, SPR_NOACCESS,
1777 &spr_read_tbu, SPR_NOACCESS,
1778 0x00000000);
1779 spr_register(env, SPR_403_TBU, "TBU",
1780 SPR_NOACCESS, SPR_NOACCESS,
1781 SPR_NOACCESS, &spr_write_tbu,
1782 0x00000000);
1783 /* Debug */
1784 /* XXX: not implemented */
1785 spr_register(env, SPR_403_CDBCR, "CDBCR",
1786 SPR_NOACCESS, SPR_NOACCESS,
1787 &spr_read_generic, &spr_write_generic,
1788 0x00000000);
1789 }
1790
1791 /* SPR specific to PowerPC 403 implementation */
1792 static void gen_spr_403 (CPUPPCState *env)
1793 {
1794 /* MMU */
1795 spr_register(env, SPR_403_PBL1, "PBL1",
1796 SPR_NOACCESS, SPR_NOACCESS,
1797 &spr_read_403_pbr, &spr_write_403_pbr,
1798 0x00000000);
1799 spr_register(env, SPR_403_PBU1, "PBU1",
1800 SPR_NOACCESS, SPR_NOACCESS,
1801 &spr_read_403_pbr, &spr_write_403_pbr,
1802 0x00000000);
1803 spr_register(env, SPR_403_PBL2, "PBL2",
1804 SPR_NOACCESS, SPR_NOACCESS,
1805 &spr_read_403_pbr, &spr_write_403_pbr,
1806 0x00000000);
1807 spr_register(env, SPR_403_PBU2, "PBU2",
1808 SPR_NOACCESS, SPR_NOACCESS,
1809 &spr_read_403_pbr, &spr_write_403_pbr,
1810 0x00000000);
1811 /* Debug */
1812 /* XXX : not implemented */
1813 spr_register(env, SPR_40x_DAC2, "DAC2",
1814 SPR_NOACCESS, SPR_NOACCESS,
1815 &spr_read_generic, &spr_write_generic,
1816 0x00000000);
1817 /* XXX : not implemented */
1818 spr_register(env, SPR_40x_IAC2, "IAC2",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, &spr_write_generic,
1821 0x00000000);
1822 }
1823
1824 /* SPR specific to PowerPC compression coprocessor extension */
1825 #if defined (TODO)
1826 static void gen_spr_compress (CPUPPCState *env)
1827 {
1828 spr_register(env, SPR_401_SKR, "SKR",
1829 SPR_NOACCESS, SPR_NOACCESS,
1830 &spr_read_generic, &spr_write_generic,
1831 0x00000000);
1832 }
1833 #endif
1834
1835 // XXX: TODO (64 bits PowerPC SPRs)
1836 /*
1837 * ASR => SPR 280 (64 bits)
1838 * FPECR => SPR 1022 (?)
1839 * VRSAVE => SPR 256 (Altivec)
1840 * SCOMC => SPR 276 (64 bits ?)
1841 * SCOMD => SPR 277 (64 bits ?)
1842 * HSPRG0 => SPR 304 (hypervisor)
1843 * HSPRG1 => SPR 305 (hypervisor)
1844 * HDEC => SPR 310 (hypervisor)
1845 * HIOR => SPR 311 (hypervisor)
1846 * RMOR => SPR 312 (970)
1847 * HRMOR => SPR 313 (hypervisor)
1848 * HSRR0 => SPR 314 (hypervisor)
1849 * HSRR1 => SPR 315 (hypervisor)
1850 * LPCR => SPR 316 (970)
1851 * LPIDR => SPR 317 (970)
1852 * ... and more (thermal management, performance counters, ...)
1853 */
1854
1855 static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
1856 {
1857 env->reserve = -1;
1858 /* Default MMU definitions */
1859 env->nb_BATs = -1;
1860 env->nb_tlb = 0;
1861 env->nb_ways = 0;
1862 /* XXX: missing:
1863 * 32 bits PowerPC:
1864 * - MPC5xx(x)
1865 * - MPC8xx(x)
1866 * - RCPU (same as MPC5xx ?)
1867 */
1868 spr_register(env, SPR_PVR, "PVR",
1869 SPR_NOACCESS, SPR_NOACCESS,
1870 &spr_read_generic, SPR_NOACCESS,
1871 def->pvr);
1872 printf("%s: PVR %08x mask %08x => %08x\n", __func__,
1873 def->pvr, def->pvr_mask, def->pvr & def->pvr_mask);
1874 switch (def->pvr) {
1875 /* Embedded PowerPC from IBM */
1876 case CPU_PPC_401A1: /* 401 A1 family */
1877 case CPU_PPC_401B2: /* 401 B2 family */
1878 case CPU_PPC_401C2: /* 401 C2 family */
1879 case CPU_PPC_401D2: /* 401 D2 family */
1880 case CPU_PPC_401E2: /* 401 E2 family */
1881 case CPU_PPC_401F2: /* 401 F2 family */
1882 case CPU_PPC_401G2: /* 401 G2 family */
1883 case CPU_PPC_IOP480: /* IOP 480 family */
1884 case CPU_PPC_COBRA: /* IBM Processor for Network Resources */
1885 gen_spr_generic(env);
1886 gen_spr_40x(env);
1887 gen_spr_401_403(env);
1888 #if defined (TODO)
1889 /* XXX: optional ? */
1890 gen_spr_compress(env);
1891 #endif
1892 env->nb_BATs = 0;
1893 env->nb_tlb = 64;
1894 env->nb_ways = 1;
1895 env->id_tlbs = 0;
1896 /* XXX: TODO: allocate internal IRQ controller */
1897 break;
1898
1899 case CPU_PPC_403GA: /* 403 GA family */
1900 case CPU_PPC_403GB: /* 403 GB family */
1901 case CPU_PPC_403GC: /* 403 GC family */
1902 case CPU_PPC_403GCX: /* 403 GCX family */
1903 gen_spr_generic(env);
1904 gen_spr_40x(env);
1905 gen_spr_401_403(env);
1906 gen_spr_403(env);
1907 env->nb_BATs = 0;
1908 env->nb_tlb = 64;
1909 env->nb_ways = 1;
1910 env->id_tlbs = 0;
1911 /* XXX: TODO: allocate internal IRQ controller */
1912 break;
1913
1914 case CPU_PPC_405CR: /* 405 GP/CR family */
1915 case CPU_PPC_405EP: /* 405 EP family */
1916 case CPU_PPC_405GPR: /* 405 GPR family */
1917 case CPU_PPC_405D2: /* 405 D2 family */
1918 case CPU_PPC_405D4: /* 405 D4 family */
1919 gen_spr_generic(env);
1920 /* Time base */
1921 gen_tbl(env);
1922 gen_spr_40x(env);
1923 gen_spr_405(env);
1924 env->nb_BATs = 0;
1925 env->nb_tlb = 64;
1926 env->nb_ways = 1;
1927 env->id_tlbs = 0;
1928 /* Allocate hardware IRQ controller */
1929 ppc405_irq_init(env);
1930 break;
1931
1932 case CPU_PPC_NPE405H: /* NPe405 H family */
1933 case CPU_PPC_NPE405H2:
1934 case CPU_PPC_NPE405L: /* Npe405 L family */
1935 gen_spr_generic(env);
1936 /* Time base */
1937 gen_tbl(env);
1938 gen_spr_40x(env);
1939 gen_spr_405(env);
1940 env->nb_BATs = 0;
1941 env->nb_tlb = 64;
1942 env->nb_ways = 1;
1943 env->id_tlbs = 0;
1944 /* Allocate hardware IRQ controller */
1945 ppc405_irq_init(env);
1946 break;
1947
1948 #if defined (TODO)
1949 case CPU_PPC_STB01000:
1950 #endif
1951 #if defined (TODO)
1952 case CPU_PPC_STB01010:
1953 #endif
1954 #if defined (TODO)
1955 case CPU_PPC_STB0210:
1956 #endif
1957 case CPU_PPC_STB03: /* STB03 family */
1958 #if defined (TODO)
1959 case CPU_PPC_STB043: /* STB043 family */
1960 #endif
1961 #if defined (TODO)
1962 case CPU_PPC_STB045: /* STB045 family */
1963 #endif
1964 case CPU_PPC_STB25: /* STB25 family */
1965 #if defined (TODO)
1966 case CPU_PPC_STB130: /* STB130 family */
1967 #endif
1968 gen_spr_generic(env);
1969 /* Time base */
1970 gen_tbl(env);
1971 gen_spr_40x(env);
1972 gen_spr_405(env);
1973 env->nb_BATs = 0;
1974 env->nb_tlb = 64;
1975 env->nb_ways = 1;
1976 env->id_tlbs = 0;
1977 /* Allocate hardware IRQ controller */
1978 ppc405_irq_init(env);
1979 break;
1980
1981 case CPU_PPC_440EP: /* 440 EP family */
1982 case CPU_PPC_440GP: /* 440 GP family */
1983 case CPU_PPC_440GX: /* 440 GX family */
1984 case CPU_PPC_440GXc: /* 440 GXc family */
1985 case CPU_PPC_440GXf: /* 440 GXf family */
1986 case CPU_PPC_440SP: /* 440 SP family */
1987 case CPU_PPC_440SP2:
1988 case CPU_PPC_440SPE: /* 440 SPE family */
1989 gen_spr_generic(env);
1990 /* Time base */
1991 gen_tbl(env);
1992 gen_spr_BookE(env);
1993 gen_spr_440(env);
1994 env->nb_BATs = 0;
1995 env->nb_tlb = 64;
1996 env->nb_ways = 1;
1997 env->id_tlbs = 0;
1998 /* XXX: TODO: allocate internal IRQ controller */
1999 break;
2000
2001 /* Embedded PowerPC from Freescale */
2002 #if defined (TODO)
2003 case CPU_PPC_5xx:
2004 break;
2005 #endif
2006 #if defined (TODO)
2007 case CPU_PPC_8xx: /* MPC821 / 823 / 850 / 860 */
2008 break;
2009 #endif
2010 #if defined (TODO)
2011 case CPU_PPC_82xx_HIP3: /* MPC8240 / 8260 */
2012 case CPU_PPC_82xx_HIP4: /* MPC8240 / 8260 */
2013 break;
2014 #endif
2015 #if defined (TODO)
2016 case CPU_PPC_827x: /* MPC 827x / 828x */
2017 break;
2018 #endif
2019
2020 /* XXX: Use MPC8540 PVR to implement a test PowerPC BookE target */
2021 case CPU_PPC_e500v110:
2022 case CPU_PPC_e500v120:
2023 case CPU_PPC_e500v210:
2024 case CPU_PPC_e500v220:
2025 gen_spr_generic(env);
2026 /* Time base */
2027 gen_tbl(env);
2028 gen_spr_BookE(env);
2029 gen_spr_BookE_FSL(env);
2030 env->nb_BATs = 0;
2031 env->nb_tlb = 64;
2032 env->nb_ways = 1;
2033 env->id_tlbs = 0;
2034 /* XXX: TODO: allocate internal IRQ controller */
2035 break;
2036
2037 #if defined (TODO)
2038 case CPU_PPC_e600:
2039 break;
2040 #endif
2041
2042 /* 32 bits PowerPC */
2043 case CPU_PPC_601: /* PowerPC 601 */
2044 gen_spr_generic(env);
2045 gen_spr_ne_601(env);
2046 gen_spr_601(env);
2047 /* Hardware implementation registers */
2048 /* XXX : not implemented */
2049 spr_register(env, SPR_HID0, "HID0",
2050 SPR_NOACCESS, SPR_NOACCESS,
2051 &spr_read_generic, &spr_write_generic,
2052 0x00000000);
2053 /* XXX : not implemented */
2054 spr_register(env, SPR_HID1, "HID1",
2055 SPR_NOACCESS, SPR_NOACCESS,
2056 &spr_read_generic, &spr_write_generic,
2057 0x00000000);
2058 /* XXX : not implemented */
2059 spr_register(env, SPR_601_HID2, "HID2",
2060 SPR_NOACCESS, SPR_NOACCESS,
2061 &spr_read_generic, &spr_write_generic,
2062 0x00000000);
2063 /* XXX : not implemented */
2064 spr_register(env, SPR_601_HID5, "HID5",
2065 SPR_NOACCESS, SPR_NOACCESS,
2066 &spr_read_generic, &spr_write_generic,
2067 0x00000000);
2068 /* XXX : not implemented */
2069 #if 0 /* ? */
2070 spr_register(env, SPR_601_HID15, "HID15",
2071 SPR_NOACCESS, SPR_NOACCESS,
2072 &spr_read_generic, &spr_write_generic,
2073 0x00000000);
2074 #endif
2075 env->nb_tlb = 64;
2076 env->nb_ways = 2;
2077 env->id_tlbs = 0;
2078 env->id_tlbs = 0;
2079 /* XXX: TODO: allocate internal IRQ controller */
2080 break;
2081
2082 case CPU_PPC_602: /* PowerPC 602 */
2083 gen_spr_generic(env);
2084 gen_spr_ne_601(env);
2085 /* Memory management */
2086 gen_low_BATs(env);
2087 /* Time base */
2088 gen_tbl(env);
2089 gen_6xx_7xx_soft_tlb(env, 64, 2);
2090 gen_spr_602(env);
2091 /* hardware implementation registers */
2092 /* XXX : not implemented */
2093 spr_register(env, SPR_HID0, "HID0",
2094 SPR_NOACCESS, SPR_NOACCESS,
2095 &spr_read_generic, &spr_write_generic,
2096 0x00000000);
2097 /* XXX : not implemented */
2098 spr_register(env, SPR_HID1, "HID1",
2099 SPR_NOACCESS, SPR_NOACCESS,
2100 &spr_read_generic, &spr_write_generic,
2101 0x00000000);
2102 /* Allocate hardware IRQ controller */
2103 ppc6xx_irq_init(env);
2104 break;
2105
2106 case CPU_PPC_603: /* PowerPC 603 */
2107 case CPU_PPC_603E: /* PowerPC 603e */
2108 case CPU_PPC_603E7v:
2109 case CPU_PPC_603E7v2:
2110 case CPU_PPC_603P: /* PowerPC 603p */
2111 case CPU_PPC_603R: /* PowerPC 603r */
2112 gen_spr_generic(env);
2113 gen_spr_ne_601(env);
2114 /* Memory management */
2115 gen_low_BATs(env);
2116 /* Time base */
2117 gen_tbl(env);
2118 gen_6xx_7xx_soft_tlb(env, 64, 2);
2119 gen_spr_603(env);
2120 /* hardware implementation registers */
2121 /* XXX : not implemented */
2122 spr_register(env, SPR_HID0, "HID0",
2123 SPR_NOACCESS, SPR_NOACCESS,
2124 &spr_read_generic, &spr_write_generic,
2125 0x00000000);
2126 /* XXX : not implemented */
2127 spr_register(env, SPR_HID1, "HID1",
2128 SPR_NOACCESS, SPR_NOACCESS,
2129 &spr_read_generic, &spr_write_generic,
2130 0x00000000);
2131 /* Allocate hardware IRQ controller */
2132 ppc6xx_irq_init(env);
2133 break;
2134
2135 case CPU_PPC_G2: /* PowerPC G2 family */
2136 case CPU_PPC_G2H4:
2137 case CPU_PPC_G2gp:
2138 case CPU_PPC_G2ls:
2139 case CPU_PPC_G2LE: /* PowerPC G2LE family */
2140 case CPU_PPC_G2LEgp:
2141 case CPU_PPC_G2LEls:
2142 gen_spr_generic(env);
2143 gen_spr_ne_601(env);
2144 /* Memory management */
2145 gen_low_BATs(env);
2146 /* Time base */
2147 gen_tbl(env);
2148 /* Memory management */
2149 gen_high_BATs(env);
2150 gen_6xx_7xx_soft_tlb(env, 64, 2);
2151 gen_spr_G2_755(env);
2152 gen_spr_G2(env);
2153 /* Hardware implementation register */
2154 /* XXX : not implemented */
2155 spr_register(env, SPR_HID0, "HID0",
2156 SPR_NOACCESS, SPR_NOACCESS,
2157 &spr_read_generic, &spr_write_generic,
2158 0x00000000);
2159 /* XXX : not implemented */
2160 spr_register(env, SPR_HID1, "HID1",
2161 SPR_NOACCESS, SPR_NOACCESS,
2162 &spr_read_generic, &spr_write_generic,
2163 0x00000000);
2164 /* XXX : not implemented */
2165 spr_register(env, SPR_HID2, "HID2",
2166 SPR_NOACCESS, SPR_NOACCESS,
2167 &spr_read_generic, &spr_write_generic,
2168 0x00000000);
2169 /* Allocate hardware IRQ controller */
2170 ppc6xx_irq_init(env);
2171 break;
2172
2173 case CPU_PPC_604: /* PowerPC 604 */
2174 case CPU_PPC_604E: /* PowerPC 604e */
2175 case CPU_PPC_604R: /* PowerPC 604r */
2176 gen_spr_generic(env);
2177 gen_spr_ne_601(env);
2178 /* Memory management */
2179 gen_low_BATs(env);
2180 /* Time base */
2181 gen_tbl(env);
2182 gen_spr_604(env);
2183 /* Hardware implementation registers */
2184 /* XXX : not implemented */
2185 spr_register(env, SPR_HID0, "HID0",
2186 SPR_NOACCESS, SPR_NOACCESS,
2187 &spr_read_generic, &spr_write_generic,
2188 0x00000000);
2189 /* XXX : not implemented */
2190 spr_register(env, SPR_HID1, "HID1",
2191 SPR_NOACCESS, SPR_NOACCESS,
2192 &spr_read_generic, &spr_write_generic,
2193 0x00000000);
2194 /* Allocate hardware IRQ controller */
2195 ppc6xx_irq_init(env);
2196 break;
2197
2198 case CPU_PPC_74x: /* PowerPC 740 / 750 */
2199 case CPU_PPC_740E:
2200 case CPU_PPC_750E:
2201 case CPU_PPC_74xP: /* PowerPC 740P / 750P */
2202 case CPU_PPC_750CXE21: /* IBM PowerPC 750cxe */
2203 case CPU_PPC_750CXE22:
2204 case CPU_PPC_750CXE23:
2205 case CPU_PPC_750CXE24:
2206 case CPU_PPC_750CXE24b:
2207 case CPU_PPC_750CXE31:
2208 case CPU_PPC_750CXE31b:
2209 case CPU_PPC_750CXR:
2210 gen_spr_generic(env);
2211 gen_spr_ne_601(env);
2212 /* Memory management */
2213 gen_low_BATs(env);
2214 /* Time base */
2215 gen_tbl(env);
2216 gen_spr_7xx(env);
2217 /* Hardware implementation registers */
2218 /* XXX : not implemented */
2219 spr_register(env, SPR_HID0, "HID0",
2220 SPR_NOACCESS, SPR_NOACCESS,
2221 &spr_read_generic, &spr_write_generic,
2222 0x00000000);
2223 /* XXX : not implemented */
2224 spr_register(env, SPR_HID1, "HID1",
2225 SPR_NOACCESS, SPR_NOACCESS,
2226 &spr_read_generic, &spr_write_generic,
2227 0x00000000);
2228 /* Allocate hardware IRQ controller */
2229 ppc6xx_irq_init(env);
2230 break;
2231
2232 case CPU_PPC_750FX10: /* IBM PowerPC 750 FX */
2233 case CPU_PPC_750FX20:
2234 case CPU_PPC_750FX21:
2235 case CPU_PPC_750FX22:
2236 case CPU_PPC_750FX23:
2237 case CPU_PPC_750GX10: /* IBM PowerPC 750 GX */
2238 case CPU_PPC_750GX11:
2239 case CPU_PPC_750GX12:
2240 gen_spr_generic(env);
2241 gen_spr_ne_601(env);
2242 /* Memory management */
2243 gen_low_BATs(env);
2244 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
2245 gen_high_BATs(env);
2246 /* Time base */
2247 gen_tbl(env);
2248 gen_spr_7xx(env);
2249 /* Hardware implementation registers */
2250 /* XXX : not implemented */
2251 spr_register(env, SPR_HID0, "HID0",
2252 SPR_NOACCESS, SPR_NOACCESS,
2253 &spr_read_generic, &spr_write_generic,
2254 0x00000000);
2255 /* XXX : not implemented */
2256 spr_register(env, SPR_HID1, "HID1",
2257 SPR_NOACCESS, SPR_NOACCESS,
2258 &spr_read_generic, &spr_write_generic,
2259 0x00000000);
2260 /* XXX : not implemented */
2261 spr_register(env, SPR_750_HID2, "HID2",
2262 SPR_NOACCESS, SPR_NOACCESS,
2263 &spr_read_generic, &spr_write_generic,
2264 0x00000000);
2265 /* Allocate hardware IRQ controller */
2266 ppc6xx_irq_init(env);
2267 break;
2268
2269 case CPU_PPC_755_10: /* PowerPC 755 */
2270 case CPU_PPC_755_11:
2271 case CPU_PPC_755_20:
2272 case CPU_PPC_755D:
2273 case CPU_PPC_755E:
2274 gen_spr_generic(env);
2275 gen_spr_ne_601(env);
2276 /* Memory management */
2277 gen_low_BATs(env);
2278 /* Time base */
2279 gen_tbl(env);
2280 /* Memory management */
2281 gen_high_BATs(env);
2282 gen_6xx_7xx_soft_tlb(env, 64, 2);
2283 gen_spr_G2_755(env);
2284 /* L2 cache control */
2285 /* XXX : not implemented */
2286 spr_register(env, SPR_ICTC, "ICTC",
2287 SPR_NOACCESS, SPR_NOACCESS,
2288 &spr_read_generic, &spr_write_generic,
2289 0x00000000);
2290 /* XXX : not implemented */
2291 spr_register(env, SPR_L2PM, "L2PM",
2292 SPR_NOACCESS, SPR_NOACCESS,
2293 &spr_read_generic, &spr_write_generic,
2294 0x00000000);
2295 /* Hardware implementation registers */
2296 /* XXX : not implemented */
2297 spr_register(env, SPR_HID0, "HID0",
2298 SPR_NOACCESS, SPR_NOACCESS,
2299 &spr_read_generic, &spr_write_generic,
2300 0x00000000);
2301 /* XXX : not implemented */
2302 spr_register(env, SPR_HID1, "HID1",
2303 SPR_NOACCESS, SPR_NOACCESS,
2304 &spr_read_generic, &spr_write_generic,
2305 0x00000000);
2306 /* XXX : not implemented */
2307 spr_register(env, SPR_HID2, "HID2",
2308 SPR_NOACCESS, SPR_NOACCESS,
2309 &spr_read_generic, &spr_write_generic,
2310 0x00000000);
2311 /* Allocate hardware IRQ controller */
2312 ppc6xx_irq_init(env);
2313 break;
2314
2315 #if defined (TODO)
2316 /* G4 family */
2317 case CPU_PPC_7400: /* PowerPC 7400 */
2318 case CPU_PPC_7410C: /* PowerPC 7410 */
2319 case CPU_PPC_7410D:
2320 case CPU_PPC_7410E:
2321 case CPU_PPC_7441: /* PowerPC 7441 */
2322 case CPU_PPC_7445: /* PowerPC 7445 */
2323 case CPU_PPC_7447: /* PowerPC 7447 */
2324 case CPU_PPC_7447A: /* PowerPC 7447A */
2325 case CPU_PPC_7448: /* PowerPC 7448 */
2326 case CPU_PPC_7450: /* PowerPC 7450 */
2327 case CPU_PPC_7450b:
2328 case CPU_PPC_7451: /* PowerPC 7451 */
2329 case CPU_PPC_7451G:
2330 case CPU_PPC_7455: /* PowerPC 7455 */
2331 case CPU_PPC_7455F:
2332 case CPU_PPC_7455G:
2333 case CPU_PPC_7457: /* PowerPC 7457 */
2334 case CPU_PPC_7457C:
2335 case CPU_PPC_7457A: /* PowerPC 7457A */
2336 break;
2337 #endif
2338
2339 /* 64 bits PowerPC */
2340 #if defined (TARGET_PPC64)
2341 #if defined (TODO)
2342 case CPU_PPC_620: /* PowerPC 620 */
2343 case CPU_PPC_630: /* PowerPC 630 (Power 3) */
2344 case CPU_PPC_631: /* PowerPC 631 (Power 3+) */
2345 case CPU_PPC_POWER4: /* Power 4 */
2346 case CPU_PPC_POWER4P: /* Power 4+ */
2347 case CPU_PPC_POWER5: /* Power 5 */
2348 case CPU_PPC_POWER5P: /* Power 5+ */
2349 #endif
2350 break;
2351
2352 case CPU_PPC_970: /* PowerPC 970 */
2353 case CPU_PPC_970FX10: /* PowerPC 970 FX */
2354 case CPU_PPC_970FX20:
2355 case CPU_PPC_970FX21:
2356 case CPU_PPC_970FX30:
2357 case CPU_PPC_970FX31:
2358 case CPU_PPC_970MP10: /* PowerPC 970 MP */
2359 case CPU_PPC_970MP11:
2360 gen_spr_generic(env);
2361 gen_spr_ne_601(env);
2362 /* XXX: not correct */
2363 gen_low_BATs(env);
2364 /* Time base */
2365 gen_tbl(env);
2366 gen_spr_7xx(env);
2367 /* Hardware implementation registers */
2368 /* XXX : not implemented */
2369 spr_register(env, SPR_HID0, "HID0",
2370 SPR_NOACCESS, SPR_NOACCESS,
2371 &spr_read_generic, &spr_write_generic,
2372 0x00000000);
2373 /* XXX : not implemented */
2374 spr_register(env, SPR_HID1, "HID1",
2375 SPR_NOACCESS, SPR_NOACCESS,
2376 &spr_read_generic, &spr_write_generic,
2377 0x00000000);
2378 /* XXX : not implemented */
2379 spr_register(env, SPR_750_HID2, "HID2",
2380 SPR_NOACCESS, SPR_NOACCESS,
2381 &spr_read_generic, &spr_write_generic,
2382 0x00000000);
2383 /* Allocate hardware IRQ controller */
2384 ppc970_irq_init(env);
2385 break;
2386
2387 #if defined (TODO)
2388 case CPU_PPC_CELL10: /* Cell family */
2389 case CPU_PPC_CELL20:
2390 case CPU_PPC_CELL30:
2391 case CPU_PPC_CELL31:
2392 #endif
2393 break;
2394
2395 #if defined (TODO)
2396 case CPU_PPC_RS64: /* Apache (RS64/A35) */
2397 case CPU_PPC_RS64II: /* NorthStar (RS64-II/A50) */
2398 case CPU_PPC_RS64III: /* Pulsar (RS64-III) */
2399 case CPU_PPC_RS64IV: /* IceStar/IStar/SStar (RS64-IV) */
2400 #endif
2401 break;
2402 #endif /* defined (TARGET_PPC64) */
2403
2404 #if defined (TODO)
2405 /* POWER */
2406 case CPU_POWER: /* POWER */
2407 case CPU_POWER2: /* POWER2 */
2408 break;
2409 #endif
2410
2411 default:
2412 gen_spr_generic(env);
2413 /* XXX: TODO: allocate internal IRQ controller */
2414 break;
2415 }
2416 if (env->nb_BATs == -1)
2417 env->nb_BATs = 4;
2418 /* Allocate TLBs buffer when needed */
2419 if (env->nb_tlb != 0) {
2420 int nb_tlb = env->nb_tlb;
2421 if (env->id_tlbs != 0)
2422 nb_tlb *= 2;
2423 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
2424 /* Pre-compute some useful values */
2425 env->tlb_per_way = env->nb_tlb / env->nb_ways;
2426 }
2427 }
2428
2429 #if defined(PPC_DUMP_CPU)
2430 static void dump_sprs (CPUPPCState *env)
2431 {
2432 ppc_spr_t *spr;
2433 uint32_t pvr = env->spr[SPR_PVR];
2434 uint32_t sr, sw, ur, uw;
2435 int i, j, n;
2436
2437 printf("* SPRs for PVR=%08x\n", pvr);
2438 for (i = 0; i < 32; i++) {
2439 for (j = 0; j < 32; j++) {
2440 n = (i << 5) | j;
2441 spr = &env->spr_cb[n];
2442 #if !defined(CONFIG_USER_ONLY)
2443 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
2444 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
2445 #else
2446 sw = 0;
2447 sr = 0;
2448 #endif
2449 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
2450 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
2451 if (sw || sr || uw || ur) {
2452 printf("%4d (%03x) %8s s%c%c u%c%c\n",
2453 (i << 5) | j, (i << 5) | j, spr->name,
2454 sw ? 'w' : '-', sr ? 'r' : '-',
2455 uw ? 'w' : '-', ur ? 'r' : '-');
2456 }
2457 }
2458 }
2459 fflush(stdout);
2460 fflush(stderr);
2461 }
2462 #endif
2463
2464 /*****************************************************************************/
2465 #include <stdlib.h>
2466 #include <string.h>
2467
2468 int fflush (FILE *stream);
2469
2470 /* Opcode types */
2471 enum {
2472 PPC_DIRECT = 0, /* Opcode routine */
2473 PPC_INDIRECT = 1, /* Indirect opcode table */
2474 };
2475
2476 static inline int is_indirect_opcode (void *handler)
2477 {
2478 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
2479 }
2480
2481 static inline opc_handler_t **ind_table(void *handler)
2482 {
2483 return (opc_handler_t **)((unsigned long)handler & ~3);
2484 }
2485
2486 /* Instruction table creation */
2487 /* Opcodes tables creation */
2488 static void fill_new_table (opc_handler_t **table, int len)
2489 {
2490 int i;
2491
2492 for (i = 0; i < len; i++)
2493 table[i] = &invalid_handler;
2494 }
2495
2496 static int create_new_table (opc_handler_t **table, unsigned char idx)
2497 {
2498 opc_handler_t **tmp;
2499
2500 tmp = malloc(0x20 * sizeof(opc_handler_t));
2501 if (tmp == NULL)
2502 return -1;
2503 fill_new_table(tmp, 0x20);
2504 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
2505
2506 return 0;
2507 }
2508
2509 static int insert_in_table (opc_handler_t **table, unsigned char idx,
2510 opc_handler_t *handler)
2511 {
2512 if (table[idx] != &invalid_handler)
2513 return -1;
2514 table[idx] = handler;
2515
2516 return 0;
2517 }
2518
2519 static int register_direct_insn (opc_handler_t **ppc_opcodes,
2520 unsigned char idx, opc_handler_t *handler)
2521 {
2522 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
2523 printf("*** ERROR: opcode %02x already assigned in main "
2524 "opcode table\n", idx);
2525 return -1;
2526 }
2527
2528 return 0;
2529 }
2530
2531 static int register_ind_in_table (opc_handler_t **table,
2532 unsigned char idx1, unsigned char idx2,
2533 opc_handler_t *handler)
2534 {
2535 if (table[idx1] == &invalid_handler) {
2536 if (create_new_table(table, idx1) < 0) {
2537 printf("*** ERROR: unable to create indirect table "
2538 "idx=%02x\n", idx1);
2539 return -1;
2540 }
2541 } else {
2542 if (!is_indirect_opcode(table[idx1])) {
2543 printf("*** ERROR: idx %02x already assigned to a direct "
2544 "opcode\n", idx1);
2545 return -1;
2546 }
2547 }
2548 if (handler != NULL &&
2549 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
2550 printf("*** ERROR: opcode %02x already assigned in "
2551 "opcode table %02x\n", idx2, idx1);
2552 return -1;
2553 }
2554
2555 return 0;
2556 }
2557
2558 static int register_ind_insn (opc_handler_t **ppc_opcodes,
2559 unsigned char idx1, unsigned char idx2,
2560 opc_handler_t *handler)
2561 {
2562 int ret;
2563
2564 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
2565
2566 return ret;
2567 }
2568
2569 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
2570 unsigned char idx1, unsigned char idx2,
2571 unsigned char idx3, opc_handler_t *handler)
2572 {
2573 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
2574 printf("*** ERROR: unable to join indirect table idx "
2575 "[%02x-%02x]\n", idx1, idx2);
2576 return -1;
2577 }
2578 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
2579 handler) < 0) {
2580 printf("*** ERROR: unable to insert opcode "
2581 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
2582 return -1;
2583 }
2584
2585 return 0;
2586 }
2587
2588 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
2589 {
2590 if (insn->opc2 != 0xFF) {
2591 if (insn->opc3 != 0xFF) {
2592 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
2593 insn->opc3, &insn->handler) < 0)
2594 return -1;
2595 } else {
2596 if (register_ind_insn(ppc_opcodes, insn->opc1,
2597 insn->opc2, &insn->handler) < 0)
2598 return -1;
2599 }
2600 } else {
2601 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
2602 return -1;
2603 }
2604
2605 return 0;
2606 }
2607
2608 static int test_opcode_table (opc_handler_t **table, int len)
2609 {
2610 int i, count, tmp;
2611
2612 for (i = 0, count = 0; i < len; i++) {
2613 /* Consistency fixup */
2614 if (table[i] == NULL)
2615 table[i] = &invalid_handler;
2616 if (table[i] != &invalid_handler) {
2617 if (is_indirect_opcode(table[i])) {
2618 tmp = test_opcode_table(ind_table(table[i]), 0x20);
2619 if (tmp == 0) {
2620 free(table[i]);
2621 table[i] = &invalid_handler;
2622 } else {
2623 count++;
2624 }
2625 } else {
2626 count++;
2627 }
2628 }
2629 }
2630
2631 return count;
2632 }
2633
2634 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
2635 {
2636 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
2637 printf("*** WARNING: no opcode defined !\n");
2638 }
2639
2640 /*****************************************************************************/
2641 static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def)
2642 {
2643 opcode_t *opc, *start, *end;
2644
2645 fill_new_table(env->opcodes, 0x40);
2646 #if defined(PPC_DUMP_CPU)
2647 printf("* PowerPC instructions for PVR %08x: %s flags %016" PRIx64
2648 " %08x\n",
2649 def->pvr, def->name, def->insns_flags, def->flags);
2650 #endif
2651 if (&opc_start < &opc_end) {
2652 start = &opc_start;
2653 end = &opc_end;
2654 } else {
2655 start = &opc_end;
2656 end = &opc_start;
2657 }
2658 for (opc = start + 1; opc != end; opc++) {
2659 if ((opc->handler.type & def->insns_flags) != 0) {
2660 if (register_insn(env->opcodes, opc) < 0) {
2661 printf("*** ERROR initializing PowerPC instruction "
2662 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
2663 opc->opc3);
2664 return -1;
2665 }
2666 #if defined(PPC_DUMP_CPU)
2667 if (opc1 != 0x00) {
2668 if (opc->opc3 == 0xFF) {
2669 if (opc->opc2 == 0xFF) {
2670 printf(" %02x -- -- (%2d ----) : %s\n",
2671 opc->opc1, opc->opc1, opc->oname);
2672 } else {
2673 printf(" %02x %02x -- (%2d %4d) : %s\n",
2674 opc->opc1, opc->opc2, opc->opc1, opc->opc2,
2675 opc->oname);
2676 }
2677 } else {
2678 printf(" %02x %02x %02x (%2d %4d) : %s\n",
2679 opc->opc1, opc->opc2, opc->opc3,
2680 opc->opc1, (opc->opc3 << 5) | opc->opc2,
2681 opc->oname);
2682 }
2683 }
2684 #endif
2685 }
2686 }
2687 fix_opcode_tables(env->opcodes);
2688 fflush(stdout);
2689 fflush(stderr);
2690
2691 return 0;
2692 }
2693
2694 int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
2695 {
2696 env->msr_mask = def->msr_mask;
2697 env->flags = def->flags;
2698 if (create_ppc_opcodes(env, def) < 0)
2699 return -1;
2700 init_ppc_proc(env, def);
2701 #if defined(PPC_DUMP_CPU)
2702 dump_sprs(env);
2703 if (env->tlb != NULL) {
2704 printf("%d %s TLB in %d ways\n", env->nb_tlb,
2705 env->id_tlbs ? "splitted" : "merged", env->nb_ways);
2706 }
2707 #endif
2708
2709 return 0;
2710 }
2711
2712 /*****************************************************************************/
2713 /* PowerPC CPU definitions */
2714 static ppc_def_t ppc_defs[] = {
2715 /* Embedded PowerPC */
2716 #if defined (TODO)
2717 /* PowerPC 401 */
2718 {
2719 .name = "401",
2720 .pvr = CPU_PPC_401,
2721 .pvr_mask = 0xFFFF0000,
2722 .insns_flags = PPC_INSNS_401,
2723 .flags = PPC_FLAGS_401,
2724 .msr_mask = xxx,
2725 },
2726 #endif
2727 #if defined (TODO)
2728 /* IOP480 (401 microcontroler) */
2729 {
2730 .name = "iop480",
2731 .pvr = CPU_PPC_IOP480,
2732 .pvr_mask = 0xFFFF0000,
2733 .insns_flags = PPC_INSNS_401,
2734 .flags = PPC_FLAGS_401,
2735 .msr_mask = xxx,
2736 },
2737 #endif
2738 #if defined (TODO)
2739 /* IBM Processor for Network Resources */
2740 {
2741 .name = "Cobra",
2742 .pvr = CPU_PPC_COBRA,
2743 .pvr_mask = 0xFFFF0000,
2744 .insns_flags = PPC_INSNS_401,
2745 .flags = PPC_FLAGS_401,
2746 .msr_mask = xxx,
2747 },
2748 #endif
2749 #if defined (TODO)
2750 /* Generic PowerPC 403 */
2751 {
2752 .name = "403",
2753 .pvr = CPU_PPC_403,
2754 .pvr_mask = 0xFFFFFF00,
2755 .insns_flags = PPC_INSNS_403,
2756 .flags = PPC_FLAGS_403,
2757 .msr_mask = 0x000000000007D23DULL,
2758 },
2759 #endif
2760 #if defined (TODO)
2761 /* PowerPC 403 GA */
2762 {
2763 .name = "403ga",
2764 .pvr = CPU_PPC_403GA,
2765 .pvr_mask = 0xFFFFFF00,
2766 .insns_flags = PPC_INSNS_403,
2767 .flags = PPC_FLAGS_403,
2768 .msr_mask = 0x000000000007D23DULL,
2769 },
2770 #endif
2771 #if defined (TODO)
2772 /* PowerPC 403 GB */
2773 {
2774 .name = "403gb",
2775 .pvr = CPU_PPC_403GB,
2776 .pvr_mask = 0xFFFFFF00,
2777 .insns_flags = PPC_INSNS_403,
2778 .flags = PPC_FLAGS_403,
2779 .msr_mask = 0x000000000007D23DULL,
2780 },
2781 #endif
2782 #if defined (TODO)
2783 /* PowerPC 403 GC */
2784 {
2785 .name = "403gc",
2786 .pvr = CPU_PPC_403GC,
2787 .pvr_mask = 0xFFFFFF00,
2788 .insns_flags = PPC_INSNS_403,
2789 .flags = PPC_FLAGS_403,
2790 .msr_mask = 0x000000000007D23DULL,
2791 },
2792 #endif
2793 #if defined (TODO)
2794 /* PowerPC 403 GCX */
2795 {
2796 .name = "403gcx",
2797 .pvr = CPU_PPC_403GCX,
2798 .pvr_mask = 0xFFFFFF00,
2799 .insns_flags = PPC_INSNS_403,
2800 .flags = PPC_FLAGS_403,
2801 .msr_mask = 0x000000000007D23DULL,
2802 },
2803 #endif
2804 /* Generic PowerPC 405 */
2805 {
2806 .name = "405",
2807 .pvr = CPU_PPC_405,
2808 .pvr_mask = 0xFFFF0000,
2809 .insns_flags = PPC_INSNS_405,
2810 .flags = PPC_FLAGS_405,
2811 .msr_mask = 0x00000000020EFF30ULL,
2812 },
2813 /* PowerPC 405 CR */
2814 {
2815 .name = "405cr",
2816 .pvr = CPU_PPC_405,
2817 .pvr_mask = 0xFFFFFFFF,
2818 .insns_flags = PPC_INSNS_405,
2819 .flags = PPC_FLAGS_405,
2820 .msr_mask = 0x00000000020EFF30ULL,
2821 },
2822 #if defined (TODO)
2823 /* PowerPC 405 GP */
2824 {
2825 .name = "405gp",
2826 .pvr = CPU_PPC_405,
2827 .pvr_mask = 0xFFFFFFFF,
2828 .insns_flags = PPC_INSNS_405,
2829 .flags = PPC_FLAGS_405,
2830 .msr_mask = 0x00000000020EFF30ULL,
2831 },
2832 #endif
2833 /* PowerPC 405 EP */
2834 {
2835 .name = "405ep",
2836 .pvr = CPU_PPC_405EP,
2837 .pvr_mask = 0xFFFFFFFF,
2838 .insns_flags = PPC_INSNS_405,
2839 .flags = PPC_FLAGS_405,
2840 .msr_mask = 0x00000000020EFF30ULL,
2841 },
2842 #if defined (TODO)
2843 /* PowerPC 405 EZ */
2844 {
2845 .name = "405ez",
2846 .pvr = CPU_PPC_405EZ,
2847 .pvr_mask = 0xFFFFFFFF,
2848 .insns_flags = PPC_INSNS_405,
2849 .flags = PPC_FLAGS_405,
2850 .msr_mask = 0x00000000020EFF30ULL,
2851 },
2852 #endif
2853 #if defined (TODO)
2854 /* PowerPC 405 GPR */
2855 {
2856 .name = "405gpr",
2857 .pvr = CPU_PPC_405GPR,
2858 .pvr_mask = 0xFFFFFFFF,
2859 .insns_flags = PPC_INSNS_405,
2860 .flags = PPC_FLAGS_405,
2861 .msr_mask = 0x00000000020EFF30ULL,
2862 },
2863 #endif
2864 /* PowerPC 405 D2 */
2865 {
2866 .name = "405d2",
2867 .pvr = CPU_PPC_405D2,
2868 .pvr_mask = 0xFFFFFFFF,
2869 .insns_flags = PPC_INSNS_405,
2870 .flags = PPC_FLAGS_405,
2871 .msr_mask = 0x00000000020EFF30ULL,
2872 },
2873 /* PowerPC 405 D4 */
2874 {
2875 .name = "405d4",
2876 .pvr = CPU_PPC_405D4,
2877 .pvr_mask = 0xFFFFFFFF,
2878 .insns_flags = PPC_INSNS_405,
2879 .flags = PPC_FLAGS_405,
2880 .msr_mask = 0x00000000020EFF30ULL,
2881 },
2882 #if defined (TODO)
2883 /* Npe405 H */
2884 {
2885 .name = "Npe405H",
2886 .pvr = CPU_PPC_NPE405H,
2887 .pvr_mask = 0xFFFFFFFF,
2888 .insns_flags = PPC_INSNS_405,
2889 .flags = PPC_FLAGS_405,
2890 .msr_mask = 0x00000000020EFF30ULL,
2891 },
2892 #endif
2893 #if defined (TODO)
2894 /* Npe405 L */
2895 {
2896 .name = "Npe405L",
2897 .pvr = CPU_PPC_NPE405L,
2898 .pvr_mask = 0xFFFFFFFF,
2899 .insns_flags = PPC_INSNS_405,
2900 .flags = PPC_FLAGS_405,
2901 .msr_mask = 0x00000000020EFF30ULL,
2902 },
2903 #endif
2904 #if defined (TODO)
2905 /* STB010000 */
2906 {
2907 .name = "STB01000",
2908 .pvr = CPU_PPC_STB01000,
2909 .pvr_mask = 0xFFFFFFFF,
2910 .insns_flags = PPC_INSNS_405,
2911 .flags = PPC_FLAGS_405,
2912 .msr_mask = 0x00000000020EFF30ULL,
2913 },
2914 #endif
2915 #if defined (TODO)
2916 /* STB01010 */
2917 {
2918 .name = "STB01010",
2919 .pvr = CPU_PPC_STB01010,
2920 .pvr_mask = 0xFFFFFFFF,
2921 .insns_flags = PPC_INSNS_405,
2922 .flags = PPC_FLAGS_405,
2923 .msr_mask = 0x00000000020EFF30ULL,
2924 },
2925 #endif
2926 #if defined (TODO)
2927 /* STB0210 */
2928 {
2929 .name = "STB0210",
2930 .pvr = CPU_PPC_STB0210,
2931 .pvr_mask = 0xFFFFFFFF,
2932 .insns_flags = PPC_INSNS_405,
2933 .flags = PPC_FLAGS_405,
2934 .msr_mask = 0x00000000020EFF30ULL,
2935 },
2936 #endif
2937 #if defined (TODO)
2938 /* STB03xx */
2939 {
2940 .name = "STB03",
2941 .pvr = CPU_PPC_STB03,
2942 .pvr_mask = 0xFFFFFFFF,
2943 .insns_flags = PPC_INSNS_405,
2944 .flags = PPC_FLAGS_405,
2945 .msr_mask = 0x00000000020EFF30ULL,
2946 },
2947 #endif
2948 #if defined (TODO)
2949 /* STB043x */
2950 {
2951 .name = "STB043",
2952 .pvr = CPU_PPC_STB043,
2953 .pvr_mask = 0xFFFFFFFF,
2954 .insns_flags = PPC_INSNS_405,
2955 .flags = PPC_FLAGS_405,
2956 .msr_mask = 0x00000000020EFF30ULL,
2957 },
2958 #endif
2959 #if defined (TODO)
2960 /* STB045x */
2961 {
2962 .name = "STB045",
2963 .pvr = CPU_PPC_STB045,
2964 .pvr_mask = 0xFFFFFFFF,
2965 .insns_flags = PPC_INSNS_405,
2966 .flags = PPC_FLAGS_405,
2967 .msr_mask = 0x00000000020EFF30ULL,
2968 },
2969 #endif
2970 #if defined (TODO)
2971 /* STB25xx */
2972 {
2973 .name = "STB25",
2974 .pvr = CPU_PPC_STB25,
2975 .pvr_mask = 0xFFFFFFFF,
2976 .insns_flags = PPC_INSNS_405,
2977 .flags = PPC_FLAGS_405,
2978 .msr_mask = 0x00000000020EFF30ULL,
2979 },
2980 #endif
2981 #if defined (TODO)
2982 /* STB130 */
2983 {
2984 .name = "STB130",
2985 .pvr = CPU_PPC_STB130,
2986 .pvr_mask = 0xFFFFFFFF,
2987 .insns_flags = PPC_INSNS_405,
2988 .flags = PPC_FLAGS_405,
2989 .msr_mask = 0x00000000020EFF30ULL,
2990 },
2991 #endif
2992 /* Xilinx PowerPC 405 cores */
2993 #if defined (TODO)
2994 {
2995 .name = "x2vp4",
2996 .pvr = CPU_PPC_X2VP4,
2997 .pvr_mask = 0xFFFFFFFF,
2998 .insns_flags = PPC_INSNS_405,
2999 .flags = PPC_FLAGS_405,
3000 .msr_mask = 0x00000000020EFF30ULL,
3001 },
3002 {
3003 .name = "x2vp7",
3004 .pvr = CPU_PPC_X2VP7,
3005 .pvr_mask = 0xFFFFFFFF,
3006 .insns_flags = PPC_INSNS_405,
3007 .flags = PPC_FLAGS_405,
3008 .msr_mask = 0x00000000020EFF30ULL,
3009 },
3010 {
3011 .name = "x2vp20",
3012 .pvr = CPU_PPC_X2VP20,
3013 .pvr_mask = 0xFFFFFFFF,
3014 .insns_flags = PPC_INSNS_405,
3015 .flags = PPC_FLAGS_405,
3016 .msr_mask = 0x00000000020EFF30ULL,
3017 },
3018 {
3019 .name = "x2vp50",
3020 .pvr = CPU_PPC_X2VP50,
3021 .pvr_mask = 0xFFFFFFFF,
3022 .insns_flags = PPC_INSNS_405,
3023 .flags = PPC_FLAGS_405,
3024 .msr_mask = 0x00000000020EFF30ULL,
3025 },
3026 #endif
3027 #if defined (TODO)
3028 /* PowerPC 440 EP */
3029 {
3030 .name = "440ep",
3031 .pvr = CPU_PPC_440EP,
3032 .pvr_mask = 0xFFFF0000,
3033 .insns_flags = PPC_INSNS_440,
3034 .flags = PPC_FLAGS_440,
3035 .msr_mask = 0x000000000006D630ULL,
3036 },
3037 #endif
3038 #if defined (TODO)
3039 /* PowerPC 440 GR */
3040 {
3041 .name = "440gr",
3042 .pvr = CPU_PPC_440GR,
3043 .pvr_mask = 0xFFFF0000,
3044 .insns_flags = PPC_INSNS_440,
3045 .flags = PPC_FLAGS_440,
3046 .msr_mask = 0x000000000006D630ULL,
3047 },
3048 #endif
3049 #if defined (TODO)
3050 /* PowerPC 440 GP */
3051 {
3052 .name = "440gp",
3053 .pvr = CPU_PPC_440GP,
3054 .pvr_mask = 0xFFFFFF00,
3055 .insns_flags = PPC_INSNS_440,
3056 .flags = PPC_FLAGS_440,
3057 .msr_mask = 0x000000000006D630ULL,
3058 },
3059 #endif
3060 #if defined (TODO)
3061 /* PowerPC 440 GX */
3062 {
3063 .name = "440gx",
3064 .pvr = CPU_PPC_440GX,
3065 .pvr_mask = 0xFFFF0000,
3066 .insns_flags = PPC_INSNS_405,
3067 .flags = PPC_FLAGS_440,
3068 .msr_mask = 0x000000000006D630ULL,
3069 },
3070 #endif
3071 #if defined (TODO)
3072 /* PowerPC 440 GXc */
3073 {
3074 .name = "440gxc",
3075 .pvr = CPU_PPC_440GXC,
3076 .pvr_mask = 0xFFFF0000,
3077 .insns_flags = PPC_INSNS_405,
3078 .flags = PPC_FLAGS_440,
3079 .msr_mask = 0x000000000006D630ULL,
3080 },
3081 #endif
3082 #if defined (TODO)
3083 /* PowerPC 440 GXf */
3084 {
3085 .name = "440gxf",
3086 .pvr = CPU_PPC_440GXF,
3087 .pvr_mask = 0xFFFF0000,
3088 .insns_flags = PPC_INSNS_405,
3089 .flags = PPC_FLAGS_440,
3090 .msr_mask = 0x000000000006D630ULL,
3091 },
3092 #endif
3093 #if defined (TODO)
3094 /* PowerPC 440 SP */
3095 {
3096 .name = "440sp",
3097 .pvr = CPU_PPC_440SP,
3098 .pvr_mask = 0xFFFF0000,
3099 .insns_flags = PPC_INSNS_405,
3100 .flags = PPC_FLAGS_440,
3101 .msr_mask = 0x000000000006D630ULL,
3102 },
3103 #endif
3104 #if defined (TODO)
3105 /* PowerPC 440 SP2 */
3106 {
3107 .name = "440sp2",
3108 .pvr = CPU_PPC_440SP2,
3109 .pvr_mask = 0xFFFF0000,
3110 .insns_flags = PPC_INSNS_405,
3111 .flags = PPC_FLAGS_440,
3112 .msr_mask = 0x000000000006D630ULL,
3113 },
3114 #endif
3115 #if defined (TODO)
3116 /* PowerPC 440 SPE */
3117 {
3118 .name = "440spe",
3119 .pvr = CPU_PPC_440SPE,
3120 .pvr_mask = 0xFFFF0000,
3121 .insns_flags = PPC_INSNS_405,
3122 .flags = PPC_FLAGS_440,
3123 .msr_mask = 0x000000000006D630ULL,
3124 },
3125 #endif
3126 /* Fake generic BookE PowerPC */
3127 {
3128 .name = "BookE",
3129 .pvr = CPU_PPC_e500,
3130 .pvr_mask = 0xFFFFFFFF,
3131 .insns_flags = PPC_INSNS_BOOKE,
3132 .flags = PPC_FLAGS_BOOKE,
3133 .msr_mask = 0x000000000006D630ULL,
3134 },
3135 /* PowerPC 460 cores - TODO */
3136 /* PowerPC MPC 5xx cores - TODO */
3137 /* PowerPC MPC 8xx cores - TODO */
3138 /* PowerPC MPC 8xxx cores - TODO */
3139 /* e200 cores - TODO */
3140 /* e500 cores - TODO */
3141 /* e600 cores - TODO */
3142
3143 /* 32 bits "classic" PowerPC */
3144 #if defined (TODO)
3145 /* PowerPC 601 */
3146 {
3147 .name = "601",
3148 .pvr = CPU_PPC_601,
3149 .pvr_mask = 0xFFFF0000,
3150 .insns_flags = PPC_INSNS_601,
3151 .flags = PPC_FLAGS_601,
3152 .msr_mask = 0x000000000000FD70ULL,
3153 },
3154 #endif
3155 #if defined (TODO)
3156 /* PowerPC 602 */
3157 {
3158 .name = "602",
3159 .pvr = CPU_PPC_602,
3160 .pvr_mask = 0xFFFF0000,
3161 .insns_flags = PPC_INSNS_602,
3162 .flags = PPC_FLAGS_602,
3163 .msr_mask = 0x0000000000C7FF73ULL,
3164 },
3165 #endif
3166 /* PowerPC 603 */
3167 {
3168 .name = "603",
3169 .pvr = CPU_PPC_603,
3170 .pvr_mask = 0xFFFFFFFF,
3171 .insns_flags = PPC_INSNS_603,
3172 .flags = PPC_FLAGS_603,
3173 .msr_mask = 0x000000000007FF73ULL,
3174 },
3175 /* PowerPC 603e */
3176 {
3177 .name = "603e",
3178 .pvr = CPU_PPC_603E,
3179 .pvr_mask = 0xFFFFFFFF,
3180 .insns_flags = PPC_INSNS_603,
3181 .flags = PPC_FLAGS_603,
3182 .msr_mask = 0x000000000007FF73ULL,
3183 },
3184 {
3185 .name = "Stretch",
3186 .pvr = CPU_PPC_603E,
3187 .pvr_mask = 0xFFFFFFFF,
3188 .insns_flags = PPC_INSNS_603,
3189 .flags = PPC_FLAGS_603,
3190 .msr_mask = 0x000000000007FF73ULL,
3191 },
3192 /* PowerPC 603p */
3193 {
3194 .name = "603p",
3195 .pvr = CPU_PPC_603P,
3196 .pvr_mask = 0xFFFFFFFF,
3197 .insns_flags = PPC_INSNS_603,
3198 .flags = PPC_FLAGS_603,
3199 .msr_mask = 0x000000000007FF73ULL,
3200 },
3201 /* PowerPC 603e7 */
3202 {
3203 .name = "603e7",
3204 .pvr = CPU_PPC_603E7,
3205 .pvr_mask = 0xFFFFFFFF,
3206 .insns_flags = PPC_INSNS_603,
3207 .flags = PPC_FLAGS_603,
3208 .msr_mask = 0x000000000007FF73ULL,
3209 },
3210 /* PowerPC 603e7v */
3211 {
3212 .name = "603e7v",
3213 .pvr = CPU_PPC_603E7v,
3214 .pvr_mask = 0xFFFFFFFF,
3215 .insns_flags = PPC_INSNS_603,
3216 .flags = PPC_FLAGS_603,
3217 .msr_mask = 0x000000000007FF73ULL,
3218 },
3219 /* PowerPC 603e7v2 */
3220 {
3221 .name = "603e7v2",
3222 .pvr = CPU_PPC_603E7v2,
3223 .pvr_mask = 0xFFFFFFFF,
3224 .insns_flags = PPC_INSNS_603,
3225 .flags = PPC_FLAGS_603,
3226 .msr_mask = 0x000000000007FF73ULL,
3227 },
3228 /* PowerPC 603r */
3229 {
3230 .name = "603r",
3231 .pvr = CPU_PPC_603R,
3232 .pvr_mask = 0xFFFFFFFF,
3233 .insns_flags = PPC_INSNS_603,
3234 .flags = PPC_FLAGS_603,
3235 .msr_mask = 0x000000000007FF73ULL,
3236 },
3237 {
3238 .name = "Goldeneye",
3239 .pvr = CPU_PPC_603R,
3240 .pvr_mask = 0xFFFFFFFF,
3241 .insns_flags = PPC_INSNS_603,
3242 .flags = PPC_FLAGS_603,
3243 .msr_mask = 0x000000000007FF73ULL,
3244 },
3245 #if defined (TODO)
3246 /* XXX: TODO: according to Motorola UM, this is a derivative to 603e */
3247 {
3248 .name = "G2",
3249 .pvr = CPU_PPC_G2,
3250 .pvr_mask = 0xFFFF0000,
3251 .insns_flags = PPC_INSNS_G2,
3252 .flags = PPC_FLAGS_G2,
3253 .msr_mask = 0x000000000006FFF2ULL,
3254 },
3255 {
3256 .name = "G2h4",
3257 .pvr = CPU_PPC_G2H4,
3258 .pvr_mask = 0xFFFF0000,
3259 .insns_flags = PPC_INSNS_G2,
3260 .flags = PPC_FLAGS_G2,
3261 .msr_mask = 0x000000000006FFF2ULL,
3262 },
3263 {
3264 .name = "G2gp",
3265 .pvr = CPU_PPC_G2gp,
3266 .pvr_mask = 0xFFFF0000,
3267 .insns_flags = PPC_INSNS_G2,
3268 .flags = PPC_FLAGS_G2,
3269 .msr_mask = 0x000000000006FFF2ULL,
3270 },
3271 {
3272 .name = "G2ls",
3273 .pvr = CPU_PPC_G2ls,
3274 .pvr_mask = 0xFFFF0000,
3275 .insns_flags = PPC_INSNS_G2,
3276 .flags = PPC_FLAGS_G2,
3277 .msr_mask = 0x000000000006FFF2ULL,
3278 },
3279 { /* Same as G2, with LE mode support */
3280 .name = "G2le",
3281 .pvr = CPU_PPC_G2LE,
3282 .pvr_mask = 0xFFFF0000,
3283 .insns_flags = PPC_INSNS_G2,
3284 .flags = PPC_FLAGS_G2,
3285 .msr_mask = 0x000000000007FFF3ULL,
3286 },
3287 {
3288 .name = "G2legp",
3289 .pvr = CPU_PPC_G2LEgp,
3290 .pvr_mask = 0xFFFF0000,
3291 .insns_flags = PPC_INSNS_G2,
3292 .flags = PPC_FLAGS_G2,
3293 .msr_mask = 0x000000000007FFF3ULL,
3294 },
3295 {
3296 .name = "G2lels",
3297 .pvr = CPU_PPC_G2LEls,
3298 .pvr_mask = 0xFFFF0000,
3299 .insns_flags = PPC_INSNS_G2,
3300 .flags = PPC_FLAGS_G2,
3301 .msr_mask = 0x000000000007FFF3ULL,
3302 },
3303 #endif
3304 /* PowerPC 604 */
3305 {
3306 .name = "604",
3307 .pvr = CPU_PPC_604,
3308 .pvr_mask = 0xFFFFFFFF,
3309 .insns_flags = PPC_INSNS_604,
3310 .flags = PPC_FLAGS_604,
3311 .msr_mask = 0x000000000005FF77ULL,
3312 },
3313 /* PowerPC 604e */
3314 {
3315 .name = "604e",
3316 .pvr = CPU_PPC_604E,
3317 .pvr_mask = 0xFFFFFFFF,
3318 .insns_flags = PPC_INSNS_604,
3319 .flags = PPC_FLAGS_604,
3320 .msr_mask = 0x000000000005FF77ULL,
3321 },
3322 /* PowerPC 604r */
3323 {
3324 .name = "604r",
3325 .pvr = CPU_PPC_604R,
3326 .pvr_mask = 0xFFFFFFFF,
3327 .insns_flags = PPC_INSNS_604,
3328 .flags = PPC_FLAGS_604,
3329 .msr_mask = 0x000000000005FF77ULL,
3330 },
3331 /* generic G3 */
3332 {
3333 .name = "G3",
3334 .pvr = CPU_PPC_74x,
3335 .pvr_mask = 0xFFFFFFFF,
3336 .insns_flags = PPC_INSNS_7x0,
3337 .flags = PPC_FLAGS_7x0,
3338 .msr_mask = 0x000000000007FF77ULL,
3339 },
3340 /* MPC740 (G3) */
3341 {
3342 .name = "740",
3343 .pvr = CPU_PPC_74x,
3344 .pvr_mask = 0xFFFFFFFF,
3345 .insns_flags = PPC_INSNS_7x0,
3346 .flags = PPC_FLAGS_7x0,
3347 .msr_mask = 0x000000000007FF77ULL,
3348 },
3349 {
3350 .name = "Arthur",
3351 .pvr = CPU_PPC_74x,
3352 .pvr_mask = 0xFFFFFFFF,
3353 .insns_flags = PPC_INSNS_7x0,
3354 .flags = PPC_FLAGS_7x0,
3355 .msr_mask = 0x000000000007FF77ULL,
3356 },
3357 #if defined (TODO)
3358 /* MPC745 (G3) */
3359 {
3360 .name = "745",
3361 .pvr = CPU_PPC_74x,
3362 .pvr_mask = 0xFFFFF000,
3363 .insns_flags = PPC_INSNS_7x5,
3364 .flags = PPC_FLAGS_7x5,
3365 .msr_mask = 0x000000000007FF77ULL,
3366 },
3367 {
3368 .name = "Goldfinger",
3369 .pvr = CPU_PPC_74x,
3370 .pvr_mask = 0xFFFFF000,
3371 .insns_flags = PPC_INSNS_7x5,
3372 .flags = PPC_FLAGS_7x5,
3373 .msr_mask = 0x000000000007FF77ULL,
3374 },
3375 #endif
3376 /* MPC750 (G3) */
3377 {
3378 .name = "750",
3379 .pvr = CPU_PPC_74x,
3380 .pvr_mask = 0xFFFFFFFF,
3381 .insns_flags = PPC_INSNS_7x0,
3382 .flags = PPC_FLAGS_7x0,
3383 .msr_mask = 0x000000000007FF77ULL,
3384 },
3385 #if defined (TODO)
3386 /* MPC755 (G3) */
3387 {
3388 .name = "755",
3389 .pvr = CPU_PPC_755,
3390 .pvr_mask = 0xFFFFF000,
3391 .insns_flags = PPC_INSNS_7x5,
3392 .flags = PPC_FLAGS_7x5,
3393 .msr_mask = 0x000000000007FF77ULL,
3394 },
3395 #endif
3396 /* MPC740P (G3) */
3397 {
3398 .name = "740p",
3399 .pvr = CPU_PPC_74xP,
3400 .pvr_mask = 0xFFFFFFFF,
3401 .insns_flags = PPC_INSNS_7x0,
3402 .flags = PPC_FLAGS_7x0,
3403 .msr_mask = 0x000000000007FF77ULL,
3404 },
3405 {
3406 .name = "Conan/Doyle",
3407 .pvr = CPU_PPC_74xP,
3408 .pvr_mask = 0xFFFFFFFF,
3409 .insns_flags = PPC_INSNS_7x0,
3410 .flags = PPC_FLAGS_7x0,
3411 .msr_mask = 0x000000000007FF77ULL,
3412 },
3413 #if defined (TODO)
3414 /* MPC745P (G3) */
3415 {
3416 .name = "745p",
3417 .pvr = CPU_PPC_74xP,
3418 .pvr_mask = 0xFFFFF000,
3419 .insns_flags = PPC_INSNS_7x5,
3420 .flags = PPC_FLAGS_7x5,
3421 .msr_mask = 0x000000000007FF77ULL,
3422 },
3423 #endif
3424 /* MPC750P (G3) */
3425 {
3426 .name = "750p",
3427 .pvr = CPU_PPC_74xP,
3428 .pvr_mask = 0xFFFFFFFF,
3429 .insns_flags = PPC_INSNS_7x0,
3430 .flags = PPC_FLAGS_7x0,
3431 .msr_mask = 0x000000000007FF77ULL,
3432 },
3433 #if defined (TODO)
3434 /* MPC755P (G3) */
3435 {
3436 .name = "755p",
3437 .pvr = CPU_PPC_74xP,
3438 .pvr_mask = 0xFFFFF000,
3439 .insns_flags = PPC_INSNS_7x5,
3440 .flags = PPC_FLAGS_7x5,
3441 .msr_mask = 0x000000000007FF77ULL,
3442 },
3443 #endif
3444 /* IBM 750CXe (G3 embedded) */
3445 {
3446 .name = "750cxe",
3447 .pvr = CPU_PPC_750CXE,
3448 .pvr_mask = 0xFFFFFFFF,
3449 .insns_flags = PPC_INSNS_7x0,
3450 .flags = PPC_FLAGS_7x0,
3451 .msr_mask = 0x000000000007FF77ULL,
3452 },
3453 /* IBM 750FX (G3 embedded) */
3454 {
3455 .name = "750fx",
3456 .pvr = CPU_PPC_750FX,
3457 .pvr_mask = 0xFFFFFFFF,
3458 .insns_flags = PPC_INSNS_7x0,
3459 .flags = PPC_FLAGS_7x0,
3460 .msr_mask = 0x000000000007FF77ULL,
3461 },
3462 /* IBM 750GX (G3 embedded) */
3463 {
3464 .name = "750gx",
3465 .pvr = CPU_PPC_750GX,
3466 .pvr_mask = 0xFFFFFFFF,
3467 .insns_flags = PPC_INSNS_7x0,
3468 .flags = PPC_FLAGS_7x0,
3469 .msr_mask = 0x000000000007FF77ULL,
3470 },
3471 #if defined (TODO)
3472 /* generic G4 */
3473 {
3474 .name = "G4",
3475 .pvr = CPU_PPC_7400,
3476 .pvr_mask = 0xFFFF0000,
3477 .insns_flags = PPC_INSNS_74xx,
3478 .flags = PPC_FLAGS_74xx,
3479 .msr_mask = 0x000000000205FF77ULL,
3480 },
3481 #endif
3482 #if defined (TODO)
3483 /* PowerPC 7400 (G4) */
3484 {
3485 .name = "7400",
3486 .pvr = CPU_PPC_7400,
3487 .pvr_mask = 0xFFFF0000,
3488 .insns_flags = PPC_INSNS_74xx,
3489 .flags = PPC_FLAGS_74xx,
3490 .msr_mask = 0x000000000205FF77ULL,
3491 },
3492 {
3493 .name = "Max",
3494 .pvr = CPU_PPC_7400,
3495 .pvr_mask = 0xFFFF0000,
3496 .insns_flags = PPC_INSNS_74xx,
3497 .flags = PPC_FLAGS_74xx,
3498 .msr_mask = 0x000000000205FF77ULL,
3499 },
3500 #endif
3501 #if defined (TODO)
3502 /* PowerPC 7410 (G4) */
3503 {
3504 .name = "7410",
3505 .pvr = CPU_PPC_7410,
3506 .pvr_mask = 0xFFFF0000,
3507 .insns_flags = PPC_INSNS_74xx,
3508 .flags = PPC_FLAGS_74xx,
3509 .msr_mask = 0x000000000205FF77ULL,
3510 },
3511 {
3512 .name = "Nitro",
3513 .pvr = CPU_PPC_7410,
3514 .pvr_mask = 0xFFFF0000,
3515 .insns_flags = PPC_INSNS_74xx,
3516 .flags = PPC_FLAGS_74xx,
3517 .msr_mask = 0x000000000205FF77ULL,
3518 },
3519 #endif
3520 /* XXX: 7441 */
3521 /* XXX: 7445 */
3522 /* XXX: 7447 */
3523 /* XXX: 7447A */
3524 #if defined (TODO)
3525 /* PowerPC 7450 (G4) */
3526 {
3527 .name = "7450",
3528 .pvr = CPU_PPC_7450,
3529 .pvr_mask = 0xFFFF0000,
3530 .insns_flags = PPC_INSNS_74xx,
3531 .flags = PPC_FLAGS_74xx,
3532 .msr_mask = 0x000000000205FF77ULL,
3533 },
3534 {
3535 .name = "Vger",
3536 .pvr = CPU_PPC_7450,
3537 .pvr_mask = 0xFFFF0000,
3538 .insns_flags = PPC_INSNS_74xx,
3539 .flags = PPC_FLAGS_74xx,
3540 .msr_mask = 0x000000000205FF77ULL,
3541 },
3542 #endif
3543 /* XXX: 7451 */
3544 #if defined (TODO)
3545 /* PowerPC 7455 (G4) */
3546 {
3547 .name = "7455",
3548 .pvr = CPU_PPC_7455,
3549 .pvr_mask = 0xFFFF0000,
3550 .insns_flags = PPC_INSNS_74xx,
3551 .flags = PPC_FLAGS_74xx,
3552 .msr_mask = 0x000000000205FF77ULL,
3553 },
3554 {
3555 .name = "Apollo 6",
3556 .pvr = CPU_PPC_7455,
3557 .pvr_mask = 0xFFFF0000,
3558 .insns_flags = PPC_INSNS_74xx,
3559 .flags = PPC_FLAGS_74xx,
3560 .msr_mask = 0x000000000205FF77ULL,
3561 },
3562 #endif
3563 #if defined (TODO)
3564 /* PowerPC 7457 (G4) */
3565 {
3566 .name = "7457",
3567 .pvr = CPU_PPC_7457,
3568 .pvr_mask = 0xFFFF0000,
3569 .insns_flags = PPC_INSNS_74xx,
3570 .flags = PPC_FLAGS_74xx,
3571 .msr_mask = 0x000000000205FF77ULL,
3572 },
3573 {
3574 .name = "Apollo 7",
3575 .pvr = CPU_PPC_7457,
3576 .pvr_mask = 0xFFFF0000,
3577 .insns_flags = PPC_INSNS_74xx,
3578 .flags = PPC_FLAGS_74xx,
3579 .msr_mask = 0x000000000205FF77ULL,
3580 },
3581 #endif
3582 #if defined (TODO)
3583 /* PowerPC 7457A (G4) */
3584 {
3585 .name = "7457A",
3586 .pvr = CPU_PPC_7457A,
3587 .pvr_mask = 0xFFFF0000,
3588 .insns_flags = PPC_INSNS_74xx,
3589 .flags = PPC_FLAGS_74xx,
3590 .msr_mask = 0x000000000205FF77ULL,
3591 },
3592 {
3593 .name = "Apollo 7 PM",
3594 .pvr = CPU_PPC_7457A,
3595 .pvr_mask = 0xFFFF0000,
3596 .insns_flags = PPC_INSNS_74xx,
3597 .flags = PPC_FLAGS_74xx,
3598 .msr_mask = 0x000000000205FF77ULL,
3599 },
3600 #endif
3601 /* 64 bits PowerPC */
3602 #if defined (TARGET_PPC64)
3603 #if defined (TODO)
3604 /* PowerPC 620 */
3605 {
3606 .name = "620",
3607 .pvr = CPU_PPC_620,
3608 .pvr_mask = 0xFFFF0000,
3609 .insns_flags = PPC_INSNS_620,
3610 .flags = PPC_FLAGS_620,
3611 .msr_mask = 0x800000000005FF73ULL,
3612 },
3613 #endif
3614 #if defined (TODO)
3615 /* PowerPC 630 (POWER3) */
3616 {
3617 .name = "630",
3618 .pvr = CPU_PPC_630,
3619 .pvr_mask = 0xFFFF0000,
3620 .insns_flags = PPC_INSNS_630,
3621 .flags = PPC_FLAGS_630,
3622 .msr_mask = xxx,
3623 }
3624 {
3625 .name = "POWER3",
3626 .pvr = CPU_PPC_630,
3627 .pvr_mask = 0xFFFF0000,
3628 .insns_flags = PPC_INSNS_630,
3629 .flags = PPC_FLAGS_630,
3630 .msr_mask = xxx,
3631 }
3632 #endif
3633 #if defined (TODO)
3634 /* PowerPC 631 (Power 3+)*/
3635 {
3636 .name = "631",
3637 .pvr = CPU_PPC_631,
3638 .pvr_mask = 0xFFFF0000,
3639 .insns_flags = PPC_INSNS_631,
3640 .flags = PPC_FLAGS_631,
3641 .msr_mask = xxx,
3642 },
3643 {
3644 .name = "POWER3+",
3645 .pvr = CPU_PPC_631,
3646 .pvr_mask = 0xFFFF0000,
3647 .insns_flags = PPC_INSNS_631,
3648 .flags = PPC_FLAGS_631,
3649 .msr_mask = xxx,
3650 },
3651 #endif
3652 #if defined (TODO)
3653 /* POWER4 */
3654 {
3655 .name = "POWER4",
3656 .pvr = CPU_PPC_POWER4,
3657 .pvr_mask = 0xFFFF0000,
3658 .insns_flags = PPC_INSNS_POWER4,
3659 .flags = PPC_FLAGS_POWER4,
3660 .msr_mask = xxx,
3661 },
3662 #endif
3663 #if defined (TODO)
3664 /* POWER4p */
3665 {
3666 .name = "POWER4+",
3667 .pvr = CPU_PPC_POWER4P,
3668 .pvr_mask = 0xFFFF0000,
3669 .insns_flags = PPC_INSNS_POWER4,
3670 .flags = PPC_FLAGS_POWER4,
3671 .msr_mask = xxx,
3672 },
3673 #endif
3674 #if defined (TODO)
3675 /* POWER5 */
3676 {
3677 .name = "POWER5",
3678 .pvr = CPU_PPC_POWER5,
3679 .pvr_mask = 0xFFFF0000,
3680 .insns_flags = PPC_INSNS_POWER5,
3681 .flags = PPC_FLAGS_POWER5,
3682 .msr_mask = xxx,
3683 },
3684 #endif
3685 #if defined (TODO)
3686 /* POWER5+ */
3687 {
3688 .name = "POWER5+",
3689 .pvr = CPU_PPC_POWER5P,
3690 .pvr_mask = 0xFFFF0000,
3691 .insns_flags = PPC_INSNS_POWER5,
3692 .flags = PPC_FLAGS_POWER5,
3693 .msr_mask = xxx,
3694 },
3695 #endif
3696 #if defined (TODO)
3697 /* PowerPC 970 */
3698 {
3699 .name = "970",
3700 .pvr = CPU_PPC_970,
3701 .pvr_mask = 0xFFFF0000,
3702 .insns_flags = PPC_INSNS_970,
3703 .flags = PPC_FLAGS_970,
3704 .msr_mask = 0x900000000204FF36ULL,
3705 },
3706 #endif
3707 #if defined (TODO)
3708 /* PowerPC 970FX (G5) */
3709 {
3710 .name = "970fx",
3711 .pvr = CPU_PPC_970FX,
3712 .pvr_mask = 0xFFFF0000,
3713 .insns_flags = PPC_INSNS_970FX,
3714 .flags = PPC_FLAGS_970FX,
3715 .msr_mask = 0x800000000204FF36ULL,
3716 },
3717 #endif
3718 #if defined (TODO)
3719 /* RS64 (Apache/A35) */
3720 /* This one seems to support the whole POWER2 instruction set
3721 * and the PowerPC 64 one.
3722 */
3723 {
3724 .name = "RS64",
3725 .pvr = CPU_PPC_RS64,
3726 .pvr_mask = 0xFFFF0000,
3727 .insns_flags = PPC_INSNS_RS64,
3728 .flags = PPC_FLAGS_RS64,
3729 .msr_mask = xxx,
3730 },
3731 {
3732 .name = "Apache",
3733 .pvr = CPU_PPC_RS64,
3734 .pvr_mask = 0xFFFF0000,
3735 .insns_flags = PPC_INSNS_RS64,
3736 .flags = PPC_FLAGS_RS64,
3737 .msr_mask = xxx,
3738 },
3739 {
3740 .name = "A35",
3741 .pvr = CPU_PPC_RS64,
3742 .pvr_mask = 0xFFFF0000,
3743 .insns_flags = PPC_INSNS_RS64,
3744 .flags = PPC_FLAGS_RS64,
3745 .msr_mask = xxx,
3746 },
3747 #endif
3748 #if defined (TODO)
3749 /* RS64-II (NorthStar/A50) */
3750 {
3751 .name = "RS64-II",
3752 .pvr = CPU_PPC_RS64II,
3753 .pvr_mask = 0xFFFF0000,
3754 .insns_flags = PPC_INSNS_RS64,
3755 .flags = PPC_FLAGS_RS64,
3756 .msr_mask = xxx,
3757 },
3758 {
3759 .name = "NortStar",
3760 .pvr = CPU_PPC_RS64II,
3761 .pvr_mask = 0xFFFF0000,
3762 .insns_flags = PPC_INSNS_RS64,
3763 .flags = PPC_FLAGS_RS64,
3764 .msr_mask = xxx,
3765 },
3766 {
3767 .name = "A50",
3768 .pvr = CPU_PPC_RS64II,
3769 .pvr_mask = 0xFFFF0000,
3770 .insns_flags = PPC_INSNS_RS64,
3771 .flags = PPC_FLAGS_RS64,
3772 .msr_mask = xxx,
3773 },
3774 #endif
3775 #if defined (TODO)
3776 /* RS64-III (Pulsar) */
3777 {
3778 .name = "RS64-III",
3779 .pvr = CPU_PPC_RS64III,
3780 .pvr_mask = 0xFFFF0000,
3781 .insns_flags = PPC_INSNS_RS64,
3782 .flags = PPC_FLAGS_RS64,
3783 .msr_mask = xxx,
3784 },
3785 {
3786 .name = "Pulsar",
3787 .pvr = CPU_PPC_RS64III,
3788 .pvr_mask = 0xFFFF0000,
3789 .insns_flags = PPC_INSNS_RS64,
3790 .flags = PPC_FLAGS_RS64,
3791 .msr_mask = xxx,
3792 },
3793 #endif
3794 #if defined (TODO)
3795 /* RS64-IV (IceStar/IStar/SStar) */
3796 {
3797 .name = "RS64-IV",
3798 .pvr = CPU_PPC_RS64IV,
3799 .pvr_mask = 0xFFFF0000,
3800 .insns_flags = PPC_INSNS_RS64,
3801 .flags = PPC_FLAGS_RS64,
3802 .msr_mask = xxx,
3803 },
3804 {
3805 .name = "IceStar",
3806 .pvr = CPU_PPC_RS64IV,
3807 .pvr_mask = 0xFFFF0000,
3808 .insns_flags = PPC_INSNS_RS64,
3809 .flags = PPC_FLAGS_RS64,
3810 .msr_mask = xxx,
3811 },
3812 {
3813 .name = "IStar",
3814 .pvr = CPU_PPC_RS64IV,
3815 .pvr_mask = 0xFFFF0000,
3816 .insns_flags = PPC_INSNS_RS64,
3817 .flags = PPC_FLAGS_RS64,
3818 .msr_mask = xxx,
3819 },
3820 {
3821 .name = "SStar",
3822 .pvr = CPU_PPC_RS64IV,
3823 .pvr_mask = 0xFFFF0000,
3824 .insns_flags = PPC_INSNS_RS64,
3825 .flags = PPC_FLAGS_RS64,
3826 .msr_mask = xxx,
3827 },
3828 #endif
3829 /* POWER */
3830 #if defined (TODO)
3831 /* Original POWER */
3832 {
3833 .name = "POWER",
3834 .pvr = CPU_POWER,
3835 .pvr_mask = 0xFFFF0000,
3836 .insns_flags = PPC_INSNS_POWER,
3837 .flags = PPC_FLAGS_POWER,
3838 .msr_mask = xxx,
3839 },
3840 #endif
3841 #endif /* defined (TARGET_PPC64) */
3842 #if defined (TODO)
3843 /* POWER2 */
3844 {
3845 .name = "POWER2",
3846 .pvr = CPU_POWER2,
3847 .pvr_mask = 0xFFFF0000,
3848 .insns_flags = PPC_INSNS_POWER,
3849 .flags = PPC_FLAGS_POWER,
3850 .msr_mask = xxx,
3851 },
3852 #endif
3853 /* Generic PowerPCs */
3854 #if defined (TODO)
3855 {
3856 .name = "ppc64",
3857 .pvr = CPU_PPC_970,
3858 .pvr_mask = 0xFFFF0000,
3859 .insns_flags = PPC_INSNS_PPC64,
3860 .flags = PPC_FLAGS_PPC64,
3861 .msr_mask = 0xA00000000204FF36ULL,
3862 },
3863 #endif
3864 {
3865 .name = "ppc32",
3866 .pvr = CPU_PPC_604,
3867 .pvr_mask = 0xFFFFFFFF,
3868 .insns_flags = PPC_INSNS_PPC32,
3869 .flags = PPC_FLAGS_PPC32,
3870 .msr_mask = 0x000000000005FF77ULL,
3871 },
3872 /* Fallback */
3873 {
3874 .name = "ppc",
3875 .pvr = CPU_PPC_604,
3876 .pvr_mask = 0xFFFFFFFF,
3877 .insns_flags = PPC_INSNS_PPC32,
3878 .flags = PPC_FLAGS_PPC32,
3879 .msr_mask = 0x000000000005FF77ULL,
3880 },
3881 };
3882
3883 int ppc_find_by_name (const unsigned char *name, ppc_def_t **def)
3884 {
3885 int i, ret;
3886
3887 ret = -1;
3888 *def = NULL;
3889 for (i = 0; strcmp(ppc_defs[i].name, "ppc") != 0; i++) {
3890 if (strcasecmp(name, ppc_defs[i].name) == 0) {
3891 *def = &ppc_defs[i];
3892 ret = 0;
3893 break;
3894 }
3895 }
3896
3897 return ret;
3898 }
3899
3900 int ppc_find_by_pvr (uint32_t pvr, ppc_def_t **def)
3901 {
3902 int i, ret;
3903
3904 ret = -1;
3905 *def = NULL;
3906 for (i = 0; ppc_defs[i].name != NULL; i++) {
3907 if ((pvr & ppc_defs[i].pvr_mask) ==
3908 (ppc_defs[i].pvr & ppc_defs[i].pvr_mask)) {
3909 *def = &ppc_defs[i];
3910 ret = 0;
3911 break;
3912 }
3913 }
3914
3915 return ret;
3916 }
3917
3918 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3919 {
3920 int i;
3921
3922 for (i = 0; ; i++) {
3923 (*cpu_fprintf)(f, "PowerPC %16s PVR %08x mask %08x\n",
3924 ppc_defs[i].name,
3925 ppc_defs[i].pvr, ppc_defs[i].pvr_mask);
3926 if (strcmp(ppc_defs[i].name, "ppc") == 0)
3927 break;
3928 }
3929 }
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