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Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20150310' into staging
[mirror_qemu.git] / target-s390x / cpu.h
1 /*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 */
22 #ifndef CPU_S390X_H
23 #define CPU_S390X_H
24
25 #include "config.h"
26 #include "qemu-common.h"
27
28 #define TARGET_LONG_BITS 64
29
30 #define ELF_MACHINE EM_S390
31 #define ELF_MACHINE_UNAME "S390X"
32
33 #define CPUArchState struct CPUS390XState
34
35 #include "exec/cpu-defs.h"
36 #define TARGET_PAGE_BITS 12
37
38 #define TARGET_PHYS_ADDR_SPACE_BITS 64
39 #define TARGET_VIRT_ADDR_SPACE_BITS 64
40
41 #include "exec/cpu-all.h"
42
43 #include "fpu/softfloat.h"
44
45 #define NB_MMU_MODES 3
46
47 #define MMU_MODE0_SUFFIX _primary
48 #define MMU_MODE1_SUFFIX _secondary
49 #define MMU_MODE2_SUFFIX _home
50
51 #define MMU_USER_IDX 1
52
53 #define MAX_EXT_QUEUE 16
54 #define MAX_IO_QUEUE 16
55 #define MAX_MCHK_QUEUE 16
56
57 #define PSW_MCHK_MASK 0x0004000000000000
58 #define PSW_IO_MASK 0x0200000000000000
59
60 typedef struct PSW {
61 uint64_t mask;
62 uint64_t addr;
63 } PSW;
64
65 typedef struct ExtQueue {
66 uint32_t code;
67 uint32_t param;
68 uint32_t param64;
69 } ExtQueue;
70
71 typedef struct IOIntQueue {
72 uint16_t id;
73 uint16_t nr;
74 uint32_t parm;
75 uint32_t word;
76 } IOIntQueue;
77
78 typedef struct MchkQueue {
79 uint16_t type;
80 } MchkQueue;
81
82 typedef struct CPUS390XState {
83 uint64_t regs[16]; /* GP registers */
84 CPU_DoubleU fregs[16]; /* FP registers */
85 uint32_t aregs[16]; /* access registers */
86
87 uint32_t fpc; /* floating-point control register */
88 uint32_t cc_op;
89
90 float_status fpu_status; /* passed to softfloat lib */
91
92 /* The low part of a 128-bit return, or remainder of a divide. */
93 uint64_t retxl;
94
95 PSW psw;
96
97 uint64_t cc_src;
98 uint64_t cc_dst;
99 uint64_t cc_vr;
100
101 uint64_t __excp_addr;
102 uint64_t psa;
103
104 uint32_t int_pgm_code;
105 uint32_t int_pgm_ilen;
106
107 uint32_t int_svc_code;
108 uint32_t int_svc_ilen;
109
110 uint64_t cregs[16]; /* control registers */
111
112 ExtQueue ext_queue[MAX_EXT_QUEUE];
113 IOIntQueue io_queue[MAX_IO_QUEUE][8];
114 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
115
116 int pending_int;
117 int ext_index;
118 int io_index[8];
119 int mchk_index;
120
121 uint64_t ckc;
122 uint64_t cputm;
123 uint32_t todpr;
124
125 uint64_t pfault_token;
126 uint64_t pfault_compare;
127 uint64_t pfault_select;
128
129 uint64_t gbea;
130 uint64_t pp;
131
132 CPU_COMMON
133
134 /* reset does memset(0) up to here */
135
136 uint32_t cpu_num;
137 uint32_t machine_type;
138
139 uint8_t *storage_keys;
140
141 uint64_t tod_offset;
142 uint64_t tod_basetime;
143 QEMUTimer *tod_timer;
144
145 QEMUTimer *cpu_timer;
146
147 /*
148 * The cpu state represents the logical state of a cpu. In contrast to other
149 * architectures, there is a difference between a halt and a stop on s390.
150 * If all cpus are either stopped (including check stop) or in the disabled
151 * wait state, the vm can be shut down.
152 */
153 #define CPU_STATE_UNINITIALIZED 0x00
154 #define CPU_STATE_STOPPED 0x01
155 #define CPU_STATE_CHECK_STOP 0x02
156 #define CPU_STATE_OPERATING 0x03
157 #define CPU_STATE_LOAD 0x04
158 uint8_t cpu_state;
159
160 /* currently processed sigp order */
161 uint8_t sigp_order;
162
163 } CPUS390XState;
164
165 #include "cpu-qom.h"
166 #include <sysemu/kvm.h>
167
168 /* distinguish between 24 bit and 31 bit addressing */
169 #define HIGH_ORDER_BIT 0x80000000
170
171 /* Interrupt Codes */
172 /* Program Interrupts */
173 #define PGM_OPERATION 0x0001
174 #define PGM_PRIVILEGED 0x0002
175 #define PGM_EXECUTE 0x0003
176 #define PGM_PROTECTION 0x0004
177 #define PGM_ADDRESSING 0x0005
178 #define PGM_SPECIFICATION 0x0006
179 #define PGM_DATA 0x0007
180 #define PGM_FIXPT_OVERFLOW 0x0008
181 #define PGM_FIXPT_DIVIDE 0x0009
182 #define PGM_DEC_OVERFLOW 0x000a
183 #define PGM_DEC_DIVIDE 0x000b
184 #define PGM_HFP_EXP_OVERFLOW 0x000c
185 #define PGM_HFP_EXP_UNDERFLOW 0x000d
186 #define PGM_HFP_SIGNIFICANCE 0x000e
187 #define PGM_HFP_DIVIDE 0x000f
188 #define PGM_SEGMENT_TRANS 0x0010
189 #define PGM_PAGE_TRANS 0x0011
190 #define PGM_TRANS_SPEC 0x0012
191 #define PGM_SPECIAL_OP 0x0013
192 #define PGM_OPERAND 0x0015
193 #define PGM_TRACE_TABLE 0x0016
194 #define PGM_SPACE_SWITCH 0x001c
195 #define PGM_HFP_SQRT 0x001d
196 #define PGM_PC_TRANS_SPEC 0x001f
197 #define PGM_AFX_TRANS 0x0020
198 #define PGM_ASX_TRANS 0x0021
199 #define PGM_LX_TRANS 0x0022
200 #define PGM_EX_TRANS 0x0023
201 #define PGM_PRIM_AUTH 0x0024
202 #define PGM_SEC_AUTH 0x0025
203 #define PGM_ALET_SPEC 0x0028
204 #define PGM_ALEN_SPEC 0x0029
205 #define PGM_ALE_SEQ 0x002a
206 #define PGM_ASTE_VALID 0x002b
207 #define PGM_ASTE_SEQ 0x002c
208 #define PGM_EXT_AUTH 0x002d
209 #define PGM_STACK_FULL 0x0030
210 #define PGM_STACK_EMPTY 0x0031
211 #define PGM_STACK_SPEC 0x0032
212 #define PGM_STACK_TYPE 0x0033
213 #define PGM_STACK_OP 0x0034
214 #define PGM_ASCE_TYPE 0x0038
215 #define PGM_REG_FIRST_TRANS 0x0039
216 #define PGM_REG_SEC_TRANS 0x003a
217 #define PGM_REG_THIRD_TRANS 0x003b
218 #define PGM_MONITOR 0x0040
219 #define PGM_PER 0x0080
220 #define PGM_CRYPTO 0x0119
221
222 /* External Interrupts */
223 #define EXT_INTERRUPT_KEY 0x0040
224 #define EXT_CLOCK_COMP 0x1004
225 #define EXT_CPU_TIMER 0x1005
226 #define EXT_MALFUNCTION 0x1200
227 #define EXT_EMERGENCY 0x1201
228 #define EXT_EXTERNAL_CALL 0x1202
229 #define EXT_ETR 0x1406
230 #define EXT_SERVICE 0x2401
231 #define EXT_VIRTIO 0x2603
232
233 /* PSW defines */
234 #undef PSW_MASK_PER
235 #undef PSW_MASK_DAT
236 #undef PSW_MASK_IO
237 #undef PSW_MASK_EXT
238 #undef PSW_MASK_KEY
239 #undef PSW_SHIFT_KEY
240 #undef PSW_MASK_MCHECK
241 #undef PSW_MASK_WAIT
242 #undef PSW_MASK_PSTATE
243 #undef PSW_MASK_ASC
244 #undef PSW_MASK_CC
245 #undef PSW_MASK_PM
246 #undef PSW_MASK_64
247 #undef PSW_MASK_32
248 #undef PSW_MASK_ESA_ADDR
249
250 #define PSW_MASK_PER 0x4000000000000000ULL
251 #define PSW_MASK_DAT 0x0400000000000000ULL
252 #define PSW_MASK_IO 0x0200000000000000ULL
253 #define PSW_MASK_EXT 0x0100000000000000ULL
254 #define PSW_MASK_KEY 0x00F0000000000000ULL
255 #define PSW_SHIFT_KEY 56
256 #define PSW_MASK_MCHECK 0x0004000000000000ULL
257 #define PSW_MASK_WAIT 0x0002000000000000ULL
258 #define PSW_MASK_PSTATE 0x0001000000000000ULL
259 #define PSW_MASK_ASC 0x0000C00000000000ULL
260 #define PSW_MASK_CC 0x0000300000000000ULL
261 #define PSW_MASK_PM 0x00000F0000000000ULL
262 #define PSW_MASK_64 0x0000000100000000ULL
263 #define PSW_MASK_32 0x0000000080000000ULL
264 #define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
265
266 #undef PSW_ASC_PRIMARY
267 #undef PSW_ASC_ACCREG
268 #undef PSW_ASC_SECONDARY
269 #undef PSW_ASC_HOME
270
271 #define PSW_ASC_PRIMARY 0x0000000000000000ULL
272 #define PSW_ASC_ACCREG 0x0000400000000000ULL
273 #define PSW_ASC_SECONDARY 0x0000800000000000ULL
274 #define PSW_ASC_HOME 0x0000C00000000000ULL
275
276 /* tb flags */
277
278 #define FLAG_MASK_PER (PSW_MASK_PER >> 32)
279 #define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
280 #define FLAG_MASK_IO (PSW_MASK_IO >> 32)
281 #define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
282 #define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
283 #define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
284 #define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
285 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
286 #define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
287 #define FLAG_MASK_CC (PSW_MASK_CC >> 32)
288 #define FLAG_MASK_PM (PSW_MASK_PM >> 32)
289 #define FLAG_MASK_64 (PSW_MASK_64 >> 32)
290 #define FLAG_MASK_32 0x00001000
291
292 /* Control register 0 bits */
293 #define CR0_LOWPROT 0x0000000010000000ULL
294 #define CR0_EDAT 0x0000000000800000ULL
295
296 static inline int cpu_mmu_index (CPUS390XState *env)
297 {
298 if (env->psw.mask & PSW_MASK_PSTATE) {
299 return 1;
300 }
301
302 return 0;
303 }
304
305 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
306 target_ulong *cs_base, int *flags)
307 {
308 *pc = env->psw.addr;
309 *cs_base = 0;
310 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
311 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
312 }
313
314 /* While the PoO talks about ILC (a number between 1-3) what is actually
315 stored in LowCore is shifted left one bit (an even between 2-6). As
316 this is the actual length of the insn and therefore more useful, that
317 is what we want to pass around and manipulate. To make sure that we
318 have applied this distinction universally, rename the "ILC" to "ILEN". */
319 static inline int get_ilen(uint8_t opc)
320 {
321 switch (opc >> 6) {
322 case 0:
323 return 2;
324 case 1:
325 case 2:
326 return 4;
327 default:
328 return 6;
329 }
330 }
331
332 #ifndef CONFIG_USER_ONLY
333 /* In several cases of runtime exceptions, we havn't recorded the true
334 instruction length. Use these codes when raising exceptions in order
335 to re-compute the length by examining the insn in memory. */
336 #define ILEN_LATER 0x20
337 #define ILEN_LATER_INC 0x21
338 void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
339 #endif
340
341 S390CPU *cpu_s390x_init(const char *cpu_model);
342 void s390x_translate_init(void);
343 int cpu_s390x_exec(CPUS390XState *s);
344
345 /* you can call this signal handler from your SIGBUS and SIGSEGV
346 signal handlers to inform the virtual CPU of exceptions. non zero
347 is returned if the signal was handled by the virtual CPU. */
348 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
349 void *puc);
350 int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
351 int mmu_idx);
352
353 #include "ioinst.h"
354
355
356 #ifndef CONFIG_USER_ONLY
357 void do_restart_interrupt(CPUS390XState *env);
358
359 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
360 {
361 hwaddr addr = 0;
362 uint8_t reg;
363
364 reg = ipb >> 28;
365 if (reg > 0) {
366 addr = env->regs[reg];
367 }
368 addr += (ipb >> 16) & 0xfff;
369
370 return addr;
371 }
372
373 /* Base/displacement are at the same locations. */
374 #define decode_basedisp_rs decode_basedisp_s
375
376 /* helper functions for run_on_cpu() */
377 static inline void s390_do_cpu_reset(void *arg)
378 {
379 CPUState *cs = arg;
380 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
381
382 scc->cpu_reset(cs);
383 }
384 static inline void s390_do_cpu_full_reset(void *arg)
385 {
386 CPUState *cs = arg;
387
388 cpu_reset(cs);
389 }
390
391 void s390x_tod_timer(void *opaque);
392 void s390x_cpu_timer(void *opaque);
393
394 int s390_virtio_hypercall(CPUS390XState *env);
395 void s390_virtio_irq(int config_change, uint64_t token);
396
397 #ifdef CONFIG_KVM
398 void kvm_s390_virtio_irq(int config_change, uint64_t token);
399 void kvm_s390_service_interrupt(uint32_t parm);
400 void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
401 void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
402 int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
403 void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
404 #else
405 static inline void kvm_s390_virtio_irq(int config_change, uint64_t token)
406 {
407 }
408 static inline void kvm_s390_service_interrupt(uint32_t parm)
409 {
410 }
411 static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
412 uint64_t te_code)
413 {
414 }
415 #endif
416 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
417 unsigned int s390_cpu_halt(S390CPU *cpu);
418 void s390_cpu_unhalt(S390CPU *cpu);
419 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
420 static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
421 {
422 return cpu->env.cpu_state;
423 }
424
425 /* service interrupts are floating therefore we must not pass an cpustate */
426 void s390_sclp_extint(uint32_t parm);
427
428 /* from s390-virtio-bus */
429 extern const hwaddr virtio_size;
430
431 #else
432 static inline unsigned int s390_cpu_halt(S390CPU *cpu)
433 {
434 return 0;
435 }
436
437 static inline void s390_cpu_unhalt(S390CPU *cpu)
438 {
439 }
440
441 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
442 {
443 return 0;
444 }
445 #endif
446 void cpu_lock(void);
447 void cpu_unlock(void);
448
449 typedef struct SubchDev SubchDev;
450
451 #ifndef CONFIG_USER_ONLY
452 extern void io_subsystem_reset(void);
453 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
454 uint16_t schid);
455 bool css_subch_visible(SubchDev *sch);
456 void css_conditional_io_interrupt(SubchDev *sch);
457 int css_do_stsch(SubchDev *sch, SCHIB *schib);
458 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
459 int css_do_msch(SubchDev *sch, const SCHIB *schib);
460 int css_do_xsch(SubchDev *sch);
461 int css_do_csch(SubchDev *sch);
462 int css_do_hsch(SubchDev *sch);
463 int css_do_ssch(SubchDev *sch, ORB *orb);
464 int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len);
465 void css_do_tsch_update_subch(SubchDev *sch);
466 int css_do_stcrw(CRW *crw);
467 void css_undo_stcrw(CRW *crw);
468 int css_do_tpi(IOIntCode *int_code, int lowcore);
469 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
470 int rfmt, void *buf);
471 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
472 int css_enable_mcsse(void);
473 int css_enable_mss(void);
474 int css_do_rsch(SubchDev *sch);
475 int css_do_rchp(uint8_t cssid, uint8_t chpid);
476 bool css_present(uint8_t cssid);
477 #endif
478
479 #define cpu_init(model) CPU(cpu_s390x_init(model))
480 #define cpu_exec cpu_s390x_exec
481 #define cpu_gen_code cpu_s390x_gen_code
482 #define cpu_signal_handler cpu_s390x_signal_handler
483
484 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
485 #define cpu_list s390_cpu_list
486
487 #include "exec/exec-all.h"
488
489 #define EXCP_EXT 1 /* external interrupt */
490 #define EXCP_SVC 2 /* supervisor call (syscall) */
491 #define EXCP_PGM 3 /* program interruption */
492 #define EXCP_IO 7 /* I/O interrupt */
493 #define EXCP_MCHK 8 /* machine check */
494
495 #define INTERRUPT_EXT (1 << 0)
496 #define INTERRUPT_TOD (1 << 1)
497 #define INTERRUPT_CPUTIMER (1 << 2)
498 #define INTERRUPT_IO (1 << 3)
499 #define INTERRUPT_MCHK (1 << 4)
500
501 /* Program Status Word. */
502 #define S390_PSWM_REGNUM 0
503 #define S390_PSWA_REGNUM 1
504 /* General Purpose Registers. */
505 #define S390_R0_REGNUM 2
506 #define S390_R1_REGNUM 3
507 #define S390_R2_REGNUM 4
508 #define S390_R3_REGNUM 5
509 #define S390_R4_REGNUM 6
510 #define S390_R5_REGNUM 7
511 #define S390_R6_REGNUM 8
512 #define S390_R7_REGNUM 9
513 #define S390_R8_REGNUM 10
514 #define S390_R9_REGNUM 11
515 #define S390_R10_REGNUM 12
516 #define S390_R11_REGNUM 13
517 #define S390_R12_REGNUM 14
518 #define S390_R13_REGNUM 15
519 #define S390_R14_REGNUM 16
520 #define S390_R15_REGNUM 17
521 /* Total Core Registers. */
522 #define S390_NUM_CORE_REGS 18
523
524 /* CC optimization */
525
526 enum cc_op {
527 CC_OP_CONST0 = 0, /* CC is 0 */
528 CC_OP_CONST1, /* CC is 1 */
529 CC_OP_CONST2, /* CC is 2 */
530 CC_OP_CONST3, /* CC is 3 */
531
532 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
533 CC_OP_STATIC, /* CC value is env->cc_op */
534
535 CC_OP_NZ, /* env->cc_dst != 0 */
536 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
537 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
538 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
539 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
540 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
541 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
542
543 CC_OP_ADD_64, /* overflow on add (64bit) */
544 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
545 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
546 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
547 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
548 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
549 CC_OP_ABS_64, /* sign eval on abs (64bit) */
550 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
551
552 CC_OP_ADD_32, /* overflow on add (32bit) */
553 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
554 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
555 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
556 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
557 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
558 CC_OP_ABS_32, /* sign eval on abs (64bit) */
559 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
560
561 CC_OP_COMP_32, /* complement */
562 CC_OP_COMP_64, /* complement */
563
564 CC_OP_TM_32, /* test under mask (32bit) */
565 CC_OP_TM_64, /* test under mask (64bit) */
566
567 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
568 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
569 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
570
571 CC_OP_ICM, /* insert characters under mask */
572 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
573 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
574 CC_OP_FLOGR, /* find leftmost one */
575 CC_OP_MAX
576 };
577
578 static const char *cc_names[] = {
579 [CC_OP_CONST0] = "CC_OP_CONST0",
580 [CC_OP_CONST1] = "CC_OP_CONST1",
581 [CC_OP_CONST2] = "CC_OP_CONST2",
582 [CC_OP_CONST3] = "CC_OP_CONST3",
583 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
584 [CC_OP_STATIC] = "CC_OP_STATIC",
585 [CC_OP_NZ] = "CC_OP_NZ",
586 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
587 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
588 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
589 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
590 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
591 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
592 [CC_OP_ADD_64] = "CC_OP_ADD_64",
593 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
594 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
595 [CC_OP_SUB_64] = "CC_OP_SUB_64",
596 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
597 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
598 [CC_OP_ABS_64] = "CC_OP_ABS_64",
599 [CC_OP_NABS_64] = "CC_OP_NABS_64",
600 [CC_OP_ADD_32] = "CC_OP_ADD_32",
601 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
602 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
603 [CC_OP_SUB_32] = "CC_OP_SUB_32",
604 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
605 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
606 [CC_OP_ABS_32] = "CC_OP_ABS_32",
607 [CC_OP_NABS_32] = "CC_OP_NABS_32",
608 [CC_OP_COMP_32] = "CC_OP_COMP_32",
609 [CC_OP_COMP_64] = "CC_OP_COMP_64",
610 [CC_OP_TM_32] = "CC_OP_TM_32",
611 [CC_OP_TM_64] = "CC_OP_TM_64",
612 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
613 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
614 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
615 [CC_OP_ICM] = "CC_OP_ICM",
616 [CC_OP_SLA_32] = "CC_OP_SLA_32",
617 [CC_OP_SLA_64] = "CC_OP_SLA_64",
618 [CC_OP_FLOGR] = "CC_OP_FLOGR",
619 };
620
621 static inline const char *cc_name(int cc_op)
622 {
623 return cc_names[cc_op];
624 }
625
626 static inline void setcc(S390CPU *cpu, uint64_t cc)
627 {
628 CPUS390XState *env = &cpu->env;
629
630 env->psw.mask &= ~(3ull << 44);
631 env->psw.mask |= (cc & 3) << 44;
632 }
633
634 typedef struct LowCore
635 {
636 /* prefix area: defined by architecture */
637 uint32_t ccw1[2]; /* 0x000 */
638 uint32_t ccw2[4]; /* 0x008 */
639 uint8_t pad1[0x80-0x18]; /* 0x018 */
640 uint32_t ext_params; /* 0x080 */
641 uint16_t cpu_addr; /* 0x084 */
642 uint16_t ext_int_code; /* 0x086 */
643 uint16_t svc_ilen; /* 0x088 */
644 uint16_t svc_code; /* 0x08a */
645 uint16_t pgm_ilen; /* 0x08c */
646 uint16_t pgm_code; /* 0x08e */
647 uint32_t data_exc_code; /* 0x090 */
648 uint16_t mon_class_num; /* 0x094 */
649 uint16_t per_perc_atmid; /* 0x096 */
650 uint64_t per_address; /* 0x098 */
651 uint8_t exc_access_id; /* 0x0a0 */
652 uint8_t per_access_id; /* 0x0a1 */
653 uint8_t op_access_id; /* 0x0a2 */
654 uint8_t ar_access_id; /* 0x0a3 */
655 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
656 uint64_t trans_exc_code; /* 0x0a8 */
657 uint64_t monitor_code; /* 0x0b0 */
658 uint16_t subchannel_id; /* 0x0b8 */
659 uint16_t subchannel_nr; /* 0x0ba */
660 uint32_t io_int_parm; /* 0x0bc */
661 uint32_t io_int_word; /* 0x0c0 */
662 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
663 uint32_t stfl_fac_list; /* 0x0c8 */
664 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
665 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
666 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
667 uint32_t external_damage_code; /* 0x0f4 */
668 uint64_t failing_storage_address; /* 0x0f8 */
669 uint8_t pad6[0x120-0x100]; /* 0x100 */
670 PSW restart_old_psw; /* 0x120 */
671 PSW external_old_psw; /* 0x130 */
672 PSW svc_old_psw; /* 0x140 */
673 PSW program_old_psw; /* 0x150 */
674 PSW mcck_old_psw; /* 0x160 */
675 PSW io_old_psw; /* 0x170 */
676 uint8_t pad7[0x1a0-0x180]; /* 0x180 */
677 PSW restart_new_psw; /* 0x1a0 */
678 PSW external_new_psw; /* 0x1b0 */
679 PSW svc_new_psw; /* 0x1c0 */
680 PSW program_new_psw; /* 0x1d0 */
681 PSW mcck_new_psw; /* 0x1e0 */
682 PSW io_new_psw; /* 0x1f0 */
683 PSW return_psw; /* 0x200 */
684 uint8_t irb[64]; /* 0x210 */
685 uint64_t sync_enter_timer; /* 0x250 */
686 uint64_t async_enter_timer; /* 0x258 */
687 uint64_t exit_timer; /* 0x260 */
688 uint64_t last_update_timer; /* 0x268 */
689 uint64_t user_timer; /* 0x270 */
690 uint64_t system_timer; /* 0x278 */
691 uint64_t last_update_clock; /* 0x280 */
692 uint64_t steal_clock; /* 0x288 */
693 PSW return_mcck_psw; /* 0x290 */
694 uint8_t pad8[0xc00-0x2a0]; /* 0x2a0 */
695 /* System info area */
696 uint64_t save_area[16]; /* 0xc00 */
697 uint8_t pad9[0xd40-0xc80]; /* 0xc80 */
698 uint64_t kernel_stack; /* 0xd40 */
699 uint64_t thread_info; /* 0xd48 */
700 uint64_t async_stack; /* 0xd50 */
701 uint64_t kernel_asce; /* 0xd58 */
702 uint64_t user_asce; /* 0xd60 */
703 uint64_t panic_stack; /* 0xd68 */
704 uint64_t user_exec_asce; /* 0xd70 */
705 uint8_t pad10[0xdc0-0xd78]; /* 0xd78 */
706
707 /* SMP info area: defined by DJB */
708 uint64_t clock_comparator; /* 0xdc0 */
709 uint64_t ext_call_fast; /* 0xdc8 */
710 uint64_t percpu_offset; /* 0xdd0 */
711 uint64_t current_task; /* 0xdd8 */
712 uint32_t softirq_pending; /* 0xde0 */
713 uint32_t pad_0x0de4; /* 0xde4 */
714 uint64_t int_clock; /* 0xde8 */
715 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
716
717 /* 0xe00 is used as indicator for dump tools */
718 /* whether the kernel died with panic() or not */
719 uint32_t panic_magic; /* 0xe00 */
720
721 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
722
723 /* 64 bit extparam used for pfault, diag 250 etc */
724 uint64_t ext_params2; /* 0x11B8 */
725
726 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
727
728 /* System info area */
729
730 uint64_t floating_pt_save_area[16]; /* 0x1200 */
731 uint64_t gpregs_save_area[16]; /* 0x1280 */
732 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
733 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
734 uint32_t prefixreg_save_area; /* 0x1318 */
735 uint32_t fpt_creg_save_area; /* 0x131c */
736 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
737 uint32_t tod_progreg_save_area; /* 0x1324 */
738 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
739 uint32_t clock_comp_save_area[2]; /* 0x1330 */
740 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
741 uint32_t access_regs_save_area[16]; /* 0x1340 */
742 uint64_t cregs_save_area[16]; /* 0x1380 */
743
744 /* align to the top of the prefix area */
745
746 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
747 } QEMU_PACKED LowCore;
748
749 /* STSI */
750 #define STSI_LEVEL_MASK 0x00000000f0000000ULL
751 #define STSI_LEVEL_CURRENT 0x0000000000000000ULL
752 #define STSI_LEVEL_1 0x0000000010000000ULL
753 #define STSI_LEVEL_2 0x0000000020000000ULL
754 #define STSI_LEVEL_3 0x0000000030000000ULL
755 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
756 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL
757 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
758 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL
759
760 /* Basic Machine Configuration */
761 struct sysib_111 {
762 uint32_t res1[8];
763 uint8_t manuf[16];
764 uint8_t type[4];
765 uint8_t res2[12];
766 uint8_t model[16];
767 uint8_t sequence[16];
768 uint8_t plant[4];
769 uint8_t res3[156];
770 };
771
772 /* Basic Machine CPU */
773 struct sysib_121 {
774 uint32_t res1[80];
775 uint8_t sequence[16];
776 uint8_t plant[4];
777 uint8_t res2[2];
778 uint16_t cpu_addr;
779 uint8_t res3[152];
780 };
781
782 /* Basic Machine CPUs */
783 struct sysib_122 {
784 uint8_t res1[32];
785 uint32_t capability;
786 uint16_t total_cpus;
787 uint16_t active_cpus;
788 uint16_t standby_cpus;
789 uint16_t reserved_cpus;
790 uint16_t adjustments[2026];
791 };
792
793 /* LPAR CPU */
794 struct sysib_221 {
795 uint32_t res1[80];
796 uint8_t sequence[16];
797 uint8_t plant[4];
798 uint16_t cpu_id;
799 uint16_t cpu_addr;
800 uint8_t res3[152];
801 };
802
803 /* LPAR CPUs */
804 struct sysib_222 {
805 uint32_t res1[32];
806 uint16_t lpar_num;
807 uint8_t res2;
808 uint8_t lcpuc;
809 uint16_t total_cpus;
810 uint16_t conf_cpus;
811 uint16_t standby_cpus;
812 uint16_t reserved_cpus;
813 uint8_t name[8];
814 uint32_t caf;
815 uint8_t res3[16];
816 uint16_t dedicated_cpus;
817 uint16_t shared_cpus;
818 uint8_t res4[180];
819 };
820
821 /* VM CPUs */
822 struct sysib_322 {
823 uint8_t res1[31];
824 uint8_t count;
825 struct {
826 uint8_t res2[4];
827 uint16_t total_cpus;
828 uint16_t conf_cpus;
829 uint16_t standby_cpus;
830 uint16_t reserved_cpus;
831 uint8_t name[8];
832 uint32_t caf;
833 uint8_t cpi[16];
834 uint8_t res3[24];
835 } vm[8];
836 uint8_t res4[3552];
837 };
838
839 /* MMU defines */
840 #define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
841 #define _ASCE_SUBSPACE 0x200 /* subspace group control */
842 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
843 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
844 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
845 #define _ASCE_REAL_SPACE 0x20 /* real space control */
846 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
847 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */
848 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */
849 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */
850 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
851 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */
852
853 #define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
854 #define _REGION_ENTRY_RO 0x200 /* region/segment protection bit */
855 #define _REGION_ENTRY_TF 0xc0 /* region/segment table offset */
856 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
857 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
858 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
859 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
860 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
861 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */
862
863 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
864 #define _SEGMENT_ENTRY_FC 0x400 /* format control */
865 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
866 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
867
868 #define _PAGE_RO 0x200 /* HW read-only bit */
869 #define _PAGE_INVALID 0x400 /* HW invalid bit */
870 #define _PAGE_RES0 0x800 /* bit must be zero */
871
872 #define SK_C (0x1 << 1)
873 #define SK_R (0x1 << 2)
874 #define SK_F (0x1 << 3)
875 #define SK_ACC_MASK (0xf << 4)
876
877 /* SIGP order codes */
878 #define SIGP_SENSE 0x01
879 #define SIGP_EXTERNAL_CALL 0x02
880 #define SIGP_EMERGENCY 0x03
881 #define SIGP_START 0x04
882 #define SIGP_STOP 0x05
883 #define SIGP_RESTART 0x06
884 #define SIGP_STOP_STORE_STATUS 0x09
885 #define SIGP_INITIAL_CPU_RESET 0x0b
886 #define SIGP_CPU_RESET 0x0c
887 #define SIGP_SET_PREFIX 0x0d
888 #define SIGP_STORE_STATUS_ADDR 0x0e
889 #define SIGP_SET_ARCH 0x12
890
891 /* SIGP condition codes */
892 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
893 #define SIGP_CC_STATUS_STORED 1
894 #define SIGP_CC_BUSY 2
895 #define SIGP_CC_NOT_OPERATIONAL 3
896
897 /* SIGP status bits */
898 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
899 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL
900 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
901 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
902 #define SIGP_STAT_STOPPED 0x00000040UL
903 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
904 #define SIGP_STAT_CHECK_STOP 0x00000010UL
905 #define SIGP_STAT_INOPERATIVE 0x00000004UL
906 #define SIGP_STAT_INVALID_ORDER 0x00000002UL
907 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
908
909 /* SIGP SET ARCHITECTURE modes */
910 #define SIGP_MODE_ESA_S390 0
911 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
912 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
913
914 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
915 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
916 target_ulong *raddr, int *flags, bool exc);
917 int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
918 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
919 uint64_t vr);
920
921 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, void *hostbuf, int len,
922 bool is_write);
923
924 #define s390_cpu_virt_mem_read(cpu, laddr, dest, len) \
925 s390_cpu_virt_mem_rw(cpu, laddr, dest, len, false)
926 #define s390_cpu_virt_mem_write(cpu, laddr, dest, len) \
927 s390_cpu_virt_mem_rw(cpu, laddr, dest, len, true)
928 #define s390_cpu_virt_mem_check_write(cpu, laddr, len) \
929 s390_cpu_virt_mem_rw(cpu, laddr, NULL, len, true)
930
931 /* The value of the TOD clock for 1.1.1970. */
932 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
933
934 /* Converts ns to s390's clock format */
935 static inline uint64_t time2tod(uint64_t ns) {
936 return (ns << 9) / 125;
937 }
938
939 static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
940 uint64_t param64)
941 {
942 CPUS390XState *env = &cpu->env;
943
944 if (env->ext_index == MAX_EXT_QUEUE - 1) {
945 /* ugh - can't queue anymore. Let's drop. */
946 return;
947 }
948
949 env->ext_index++;
950 assert(env->ext_index < MAX_EXT_QUEUE);
951
952 env->ext_queue[env->ext_index].code = code;
953 env->ext_queue[env->ext_index].param = param;
954 env->ext_queue[env->ext_index].param64 = param64;
955
956 env->pending_int |= INTERRUPT_EXT;
957 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
958 }
959
960 static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
961 uint16_t subchannel_number,
962 uint32_t io_int_parm, uint32_t io_int_word)
963 {
964 CPUS390XState *env = &cpu->env;
965 int isc = IO_INT_WORD_ISC(io_int_word);
966
967 if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
968 /* ugh - can't queue anymore. Let's drop. */
969 return;
970 }
971
972 env->io_index[isc]++;
973 assert(env->io_index[isc] < MAX_IO_QUEUE);
974
975 env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
976 env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
977 env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
978 env->io_queue[env->io_index[isc]][isc].word = io_int_word;
979
980 env->pending_int |= INTERRUPT_IO;
981 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
982 }
983
984 static inline void cpu_inject_crw_mchk(S390CPU *cpu)
985 {
986 CPUS390XState *env = &cpu->env;
987
988 if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
989 /* ugh - can't queue anymore. Let's drop. */
990 return;
991 }
992
993 env->mchk_index++;
994 assert(env->mchk_index < MAX_MCHK_QUEUE);
995
996 env->mchk_queue[env->mchk_index].type = 1;
997
998 env->pending_int |= INTERRUPT_MCHK;
999 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1000 }
1001
1002 /* from s390-virtio-ccw */
1003 #define MEM_SECTION_SIZE 0x10000000UL
1004 #define MAX_AVAIL_SLOTS 32
1005
1006 /* fpu_helper.c */
1007 uint32_t set_cc_nz_f32(float32 v);
1008 uint32_t set_cc_nz_f64(float64 v);
1009 uint32_t set_cc_nz_f128(float128 v);
1010
1011 /* misc_helper.c */
1012 #ifndef CONFIG_USER_ONLY
1013 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1014 #endif
1015 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1016 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1017 uintptr_t retaddr);
1018
1019 #ifdef CONFIG_KVM
1020 void kvm_s390_io_interrupt(uint16_t subchannel_id,
1021 uint16_t subchannel_nr, uint32_t io_int_parm,
1022 uint32_t io_int_word);
1023 void kvm_s390_crw_mchk(void);
1024 void kvm_s390_enable_css_support(S390CPU *cpu);
1025 int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1026 int vq, bool assign);
1027 int kvm_s390_cpu_restart(S390CPU *cpu);
1028 int kvm_s390_get_memslot_count(KVMState *s);
1029 void kvm_s390_clear_cmma_callback(void *opaque);
1030 int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
1031 void kvm_s390_reset_vcpu(S390CPU *cpu);
1032 int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
1033 #else
1034 static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
1035 uint16_t subchannel_nr,
1036 uint32_t io_int_parm,
1037 uint32_t io_int_word)
1038 {
1039 }
1040 static inline void kvm_s390_crw_mchk(void)
1041 {
1042 }
1043 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1044 {
1045 }
1046 static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1047 uint32_t sch, int vq,
1048 bool assign)
1049 {
1050 return -ENOSYS;
1051 }
1052 static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1053 {
1054 return -ENOSYS;
1055 }
1056 static inline void kvm_s390_clear_cmma_callback(void *opaque)
1057 {
1058 }
1059 static inline int kvm_s390_get_memslot_count(KVMState *s)
1060 {
1061 return MAX_AVAIL_SLOTS;
1062 }
1063 static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1064 {
1065 return -ENOSYS;
1066 }
1067 static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1068 {
1069 }
1070 static inline int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit,
1071 uint64_t *hw_limit)
1072 {
1073 return 0;
1074 }
1075 #endif
1076
1077 static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
1078 {
1079 if (kvm_enabled()) {
1080 return kvm_s390_set_mem_limit(kvm_state, new_limit, hw_limit);
1081 }
1082 return 0;
1083 }
1084
1085 static inline void cmma_reset(S390CPU *cpu)
1086 {
1087 if (kvm_enabled()) {
1088 CPUState *cs = CPU(cpu);
1089 kvm_s390_clear_cmma_callback(cs->kvm_state);
1090 }
1091 }
1092
1093 static inline int s390_cpu_restart(S390CPU *cpu)
1094 {
1095 if (kvm_enabled()) {
1096 return kvm_s390_cpu_restart(cpu);
1097 }
1098 return -ENOSYS;
1099 }
1100
1101 static inline int s390_get_memslot_count(KVMState *s)
1102 {
1103 if (kvm_enabled()) {
1104 return kvm_s390_get_memslot_count(s);
1105 } else {
1106 return MAX_AVAIL_SLOTS;
1107 }
1108 }
1109
1110 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1111 uint32_t io_int_parm, uint32_t io_int_word);
1112 void s390_crw_mchk(void);
1113
1114 static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1115 uint32_t sch_id, int vq,
1116 bool assign)
1117 {
1118 if (kvm_enabled()) {
1119 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1120 } else {
1121 return -ENOSYS;
1122 }
1123 }
1124
1125 #endif
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