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[qemu.git] / target-s390x / cpu.h
1 /*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 */
22 #ifndef CPU_S390X_H
23 #define CPU_S390X_H
24
25 #include "config.h"
26 #include "qemu-common.h"
27
28 #define TARGET_LONG_BITS 64
29
30 #define ELF_MACHINE EM_S390
31
32 #define CPUArchState struct CPUS390XState
33
34 #include "exec/cpu-defs.h"
35 #define TARGET_PAGE_BITS 12
36
37 #define TARGET_PHYS_ADDR_SPACE_BITS 64
38 #define TARGET_VIRT_ADDR_SPACE_BITS 64
39
40 #include "exec/cpu-all.h"
41
42 #include "fpu/softfloat.h"
43
44 #define NB_MMU_MODES 3
45
46 #define MMU_MODE0_SUFFIX _primary
47 #define MMU_MODE1_SUFFIX _secondary
48 #define MMU_MODE2_SUFFIX _home
49
50 #define MMU_USER_IDX 1
51
52 #define MAX_EXT_QUEUE 16
53 #define MAX_IO_QUEUE 16
54 #define MAX_MCHK_QUEUE 16
55
56 #define PSW_MCHK_MASK 0x0004000000000000
57 #define PSW_IO_MASK 0x0200000000000000
58
59 typedef struct PSW {
60 uint64_t mask;
61 uint64_t addr;
62 } PSW;
63
64 typedef struct ExtQueue {
65 uint32_t code;
66 uint32_t param;
67 uint32_t param64;
68 } ExtQueue;
69
70 typedef struct IOIntQueue {
71 uint16_t id;
72 uint16_t nr;
73 uint32_t parm;
74 uint32_t word;
75 } IOIntQueue;
76
77 typedef struct MchkQueue {
78 uint16_t type;
79 } MchkQueue;
80
81 /* Defined values for CPUS390XState.runtime_reg_dirty_mask */
82 #define KVM_S390_RUNTIME_DIRTY_NONE 0
83 #define KVM_S390_RUNTIME_DIRTY_PARTIAL 1
84 #define KVM_S390_RUNTIME_DIRTY_FULL 2
85
86 typedef struct CPUS390XState {
87 uint64_t regs[16]; /* GP registers */
88 CPU_DoubleU fregs[16]; /* FP registers */
89 uint32_t aregs[16]; /* access registers */
90
91 uint32_t fpc; /* floating-point control register */
92 uint32_t cc_op;
93
94 float_status fpu_status; /* passed to softfloat lib */
95
96 /* The low part of a 128-bit return, or remainder of a divide. */
97 uint64_t retxl;
98
99 PSW psw;
100
101 uint64_t cc_src;
102 uint64_t cc_dst;
103 uint64_t cc_vr;
104
105 uint64_t __excp_addr;
106 uint64_t psa;
107
108 uint32_t int_pgm_code;
109 uint32_t int_pgm_ilen;
110
111 uint32_t int_svc_code;
112 uint32_t int_svc_ilen;
113
114 uint64_t cregs[16]; /* control registers */
115
116 ExtQueue ext_queue[MAX_EXT_QUEUE];
117 IOIntQueue io_queue[MAX_IO_QUEUE][8];
118 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
119
120 int pending_int;
121 int ext_index;
122 int io_index[8];
123 int mchk_index;
124
125 uint64_t ckc;
126 uint64_t cputm;
127 uint32_t todpr;
128
129 /* on S390 the runtime register set has two dirty states:
130 * a partial dirty state in which only the registers that
131 * are needed all the time are fetched. And a fully dirty
132 * state in which all runtime registers are fetched.
133 */
134 uint32_t runtime_reg_dirty_mask;
135
136 CPU_COMMON
137
138 /* reset does memset(0) up to here */
139
140 int cpu_num;
141 uint8_t *storage_keys;
142
143 uint64_t tod_offset;
144 uint64_t tod_basetime;
145 QEMUTimer *tod_timer;
146
147 QEMUTimer *cpu_timer;
148 } CPUS390XState;
149
150 #include "cpu-qom.h"
151
152 /* distinguish between 24 bit and 31 bit addressing */
153 #define HIGH_ORDER_BIT 0x80000000
154
155 /* Interrupt Codes */
156 /* Program Interrupts */
157 #define PGM_OPERATION 0x0001
158 #define PGM_PRIVILEGED 0x0002
159 #define PGM_EXECUTE 0x0003
160 #define PGM_PROTECTION 0x0004
161 #define PGM_ADDRESSING 0x0005
162 #define PGM_SPECIFICATION 0x0006
163 #define PGM_DATA 0x0007
164 #define PGM_FIXPT_OVERFLOW 0x0008
165 #define PGM_FIXPT_DIVIDE 0x0009
166 #define PGM_DEC_OVERFLOW 0x000a
167 #define PGM_DEC_DIVIDE 0x000b
168 #define PGM_HFP_EXP_OVERFLOW 0x000c
169 #define PGM_HFP_EXP_UNDERFLOW 0x000d
170 #define PGM_HFP_SIGNIFICANCE 0x000e
171 #define PGM_HFP_DIVIDE 0x000f
172 #define PGM_SEGMENT_TRANS 0x0010
173 #define PGM_PAGE_TRANS 0x0011
174 #define PGM_TRANS_SPEC 0x0012
175 #define PGM_SPECIAL_OP 0x0013
176 #define PGM_OPERAND 0x0015
177 #define PGM_TRACE_TABLE 0x0016
178 #define PGM_SPACE_SWITCH 0x001c
179 #define PGM_HFP_SQRT 0x001d
180 #define PGM_PC_TRANS_SPEC 0x001f
181 #define PGM_AFX_TRANS 0x0020
182 #define PGM_ASX_TRANS 0x0021
183 #define PGM_LX_TRANS 0x0022
184 #define PGM_EX_TRANS 0x0023
185 #define PGM_PRIM_AUTH 0x0024
186 #define PGM_SEC_AUTH 0x0025
187 #define PGM_ALET_SPEC 0x0028
188 #define PGM_ALEN_SPEC 0x0029
189 #define PGM_ALE_SEQ 0x002a
190 #define PGM_ASTE_VALID 0x002b
191 #define PGM_ASTE_SEQ 0x002c
192 #define PGM_EXT_AUTH 0x002d
193 #define PGM_STACK_FULL 0x0030
194 #define PGM_STACK_EMPTY 0x0031
195 #define PGM_STACK_SPEC 0x0032
196 #define PGM_STACK_TYPE 0x0033
197 #define PGM_STACK_OP 0x0034
198 #define PGM_ASCE_TYPE 0x0038
199 #define PGM_REG_FIRST_TRANS 0x0039
200 #define PGM_REG_SEC_TRANS 0x003a
201 #define PGM_REG_THIRD_TRANS 0x003b
202 #define PGM_MONITOR 0x0040
203 #define PGM_PER 0x0080
204 #define PGM_CRYPTO 0x0119
205
206 /* External Interrupts */
207 #define EXT_INTERRUPT_KEY 0x0040
208 #define EXT_CLOCK_COMP 0x1004
209 #define EXT_CPU_TIMER 0x1005
210 #define EXT_MALFUNCTION 0x1200
211 #define EXT_EMERGENCY 0x1201
212 #define EXT_EXTERNAL_CALL 0x1202
213 #define EXT_ETR 0x1406
214 #define EXT_SERVICE 0x2401
215 #define EXT_VIRTIO 0x2603
216
217 /* PSW defines */
218 #undef PSW_MASK_PER
219 #undef PSW_MASK_DAT
220 #undef PSW_MASK_IO
221 #undef PSW_MASK_EXT
222 #undef PSW_MASK_KEY
223 #undef PSW_SHIFT_KEY
224 #undef PSW_MASK_MCHECK
225 #undef PSW_MASK_WAIT
226 #undef PSW_MASK_PSTATE
227 #undef PSW_MASK_ASC
228 #undef PSW_MASK_CC
229 #undef PSW_MASK_PM
230 #undef PSW_MASK_64
231
232 #define PSW_MASK_PER 0x4000000000000000ULL
233 #define PSW_MASK_DAT 0x0400000000000000ULL
234 #define PSW_MASK_IO 0x0200000000000000ULL
235 #define PSW_MASK_EXT 0x0100000000000000ULL
236 #define PSW_MASK_KEY 0x00F0000000000000ULL
237 #define PSW_SHIFT_KEY 56
238 #define PSW_MASK_MCHECK 0x0004000000000000ULL
239 #define PSW_MASK_WAIT 0x0002000000000000ULL
240 #define PSW_MASK_PSTATE 0x0001000000000000ULL
241 #define PSW_MASK_ASC 0x0000C00000000000ULL
242 #define PSW_MASK_CC 0x0000300000000000ULL
243 #define PSW_MASK_PM 0x00000F0000000000ULL
244 #define PSW_MASK_64 0x0000000100000000ULL
245 #define PSW_MASK_32 0x0000000080000000ULL
246
247 #undef PSW_ASC_PRIMARY
248 #undef PSW_ASC_ACCREG
249 #undef PSW_ASC_SECONDARY
250 #undef PSW_ASC_HOME
251
252 #define PSW_ASC_PRIMARY 0x0000000000000000ULL
253 #define PSW_ASC_ACCREG 0x0000400000000000ULL
254 #define PSW_ASC_SECONDARY 0x0000800000000000ULL
255 #define PSW_ASC_HOME 0x0000C00000000000ULL
256
257 /* tb flags */
258
259 #define FLAG_MASK_PER (PSW_MASK_PER >> 32)
260 #define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
261 #define FLAG_MASK_IO (PSW_MASK_IO >> 32)
262 #define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
263 #define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
264 #define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
265 #define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
266 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
267 #define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
268 #define FLAG_MASK_CC (PSW_MASK_CC >> 32)
269 #define FLAG_MASK_PM (PSW_MASK_PM >> 32)
270 #define FLAG_MASK_64 (PSW_MASK_64 >> 32)
271 #define FLAG_MASK_32 0x00001000
272
273 static inline int cpu_mmu_index (CPUS390XState *env)
274 {
275 if (env->psw.mask & PSW_MASK_PSTATE) {
276 return 1;
277 }
278
279 return 0;
280 }
281
282 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
283 target_ulong *cs_base, int *flags)
284 {
285 *pc = env->psw.addr;
286 *cs_base = 0;
287 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
288 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
289 }
290
291 /* While the PoO talks about ILC (a number between 1-3) what is actually
292 stored in LowCore is shifted left one bit (an even between 2-6). As
293 this is the actual length of the insn and therefore more useful, that
294 is what we want to pass around and manipulate. To make sure that we
295 have applied this distinction universally, rename the "ILC" to "ILEN". */
296 static inline int get_ilen(uint8_t opc)
297 {
298 switch (opc >> 6) {
299 case 0:
300 return 2;
301 case 1:
302 case 2:
303 return 4;
304 default:
305 return 6;
306 }
307 }
308
309 #ifndef CONFIG_USER_ONLY
310 /* In several cases of runtime exceptions, we havn't recorded the true
311 instruction length. Use these codes when raising exceptions in order
312 to re-compute the length by examining the insn in memory. */
313 #define ILEN_LATER 0x20
314 #define ILEN_LATER_INC 0x21
315 #endif
316
317 S390CPU *cpu_s390x_init(const char *cpu_model);
318 void s390x_translate_init(void);
319 int cpu_s390x_exec(CPUS390XState *s);
320
321 /* you can call this signal handler from your SIGBUS and SIGSEGV
322 signal handlers to inform the virtual CPU of exceptions. non zero
323 is returned if the signal was handled by the virtual CPU. */
324 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
325 void *puc);
326 int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
327 int mmu_idx);
328 #define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault
329
330 #include "ioinst.h"
331
332 #ifndef CONFIG_USER_ONLY
333 void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
334 int is_write);
335 void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
336 int is_write);
337 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
338 {
339 hwaddr addr = 0;
340 uint8_t reg;
341
342 reg = ipb >> 28;
343 if (reg > 0) {
344 addr = env->regs[reg];
345 }
346 addr += (ipb >> 16) & 0xfff;
347
348 return addr;
349 }
350
351 void s390x_tod_timer(void *opaque);
352 void s390x_cpu_timer(void *opaque);
353
354 int s390_virtio_hypercall(CPUS390XState *env);
355
356 #ifdef CONFIG_KVM
357 void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code);
358 void kvm_s390_virtio_irq(S390CPU *cpu, int config_change, uint64_t token);
359 void kvm_s390_interrupt_internal(S390CPU *cpu, int type, uint32_t parm,
360 uint64_t parm64, int vm);
361 #else
362 static inline void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code)
363 {
364 }
365
366 static inline void kvm_s390_virtio_irq(S390CPU *cpu, int config_change,
367 uint64_t token)
368 {
369 }
370
371 static inline void kvm_s390_interrupt_internal(S390CPU *cpu, int type,
372 uint32_t parm, uint64_t parm64,
373 int vm)
374 {
375 }
376 #endif
377 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
378 void s390_add_running_cpu(S390CPU *cpu);
379 unsigned s390_del_running_cpu(S390CPU *cpu);
380
381 /* service interrupts are floating therefore we must not pass an cpustate */
382 void s390_sclp_extint(uint32_t parm);
383
384 /* from s390-virtio-bus */
385 extern const hwaddr virtio_size;
386
387 #else
388 static inline void s390_add_running_cpu(S390CPU *cpu)
389 {
390 }
391
392 static inline unsigned s390_del_running_cpu(S390CPU *cpu)
393 {
394 return 0;
395 }
396 #endif
397 void cpu_lock(void);
398 void cpu_unlock(void);
399
400 typedef struct SubchDev SubchDev;
401
402 #ifndef CONFIG_USER_ONLY
403 extern void io_subsystem_reset(void);
404 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
405 uint16_t schid);
406 bool css_subch_visible(SubchDev *sch);
407 void css_conditional_io_interrupt(SubchDev *sch);
408 int css_do_stsch(SubchDev *sch, SCHIB *schib);
409 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
410 int css_do_msch(SubchDev *sch, SCHIB *schib);
411 int css_do_xsch(SubchDev *sch);
412 int css_do_csch(SubchDev *sch);
413 int css_do_hsch(SubchDev *sch);
414 int css_do_ssch(SubchDev *sch, ORB *orb);
415 int css_do_tsch(SubchDev *sch, IRB *irb);
416 int css_do_stcrw(CRW *crw);
417 int css_do_tpi(IOIntCode *int_code, int lowcore);
418 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
419 int rfmt, void *buf);
420 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
421 int css_enable_mcsse(void);
422 int css_enable_mss(void);
423 int css_do_rsch(SubchDev *sch);
424 int css_do_rchp(uint8_t cssid, uint8_t chpid);
425 bool css_present(uint8_t cssid);
426 #else
427 static inline SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
428 uint16_t schid)
429 {
430 return NULL;
431 }
432 static inline bool css_subch_visible(SubchDev *sch)
433 {
434 return false;
435 }
436 static inline void css_conditional_io_interrupt(SubchDev *sch)
437 {
438 }
439 static inline int css_do_stsch(SubchDev *sch, SCHIB *schib)
440 {
441 return -ENODEV;
442 }
443 static inline bool css_schid_final(uint8_t cssid, uint8_t ssid, uint16_t schid)
444 {
445 return true;
446 }
447 static inline int css_do_msch(SubchDev *sch, SCHIB *schib)
448 {
449 return -ENODEV;
450 }
451 static inline int css_do_xsch(SubchDev *sch)
452 {
453 return -ENODEV;
454 }
455 static inline int css_do_csch(SubchDev *sch)
456 {
457 return -ENODEV;
458 }
459 static inline int css_do_hsch(SubchDev *sch)
460 {
461 return -ENODEV;
462 }
463 static inline int css_do_ssch(SubchDev *sch, ORB *orb)
464 {
465 return -ENODEV;
466 }
467 static inline int css_do_tsch(SubchDev *sch, IRB *irb)
468 {
469 return -ENODEV;
470 }
471 static inline int css_do_stcrw(CRW *crw)
472 {
473 return 1;
474 }
475 static inline int css_do_tpi(IOIntCode *int_code, int lowcore)
476 {
477 return 0;
478 }
479 static inline int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid,
480 int rfmt, uint8_t l_chpid, void *buf)
481 {
482 return 0;
483 }
484 static inline void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
485 {
486 }
487 static inline int css_enable_mss(void)
488 {
489 return -EINVAL;
490 }
491 static inline int css_enable_mcsse(void)
492 {
493 return -EINVAL;
494 }
495 static inline int css_do_rsch(SubchDev *sch)
496 {
497 return -ENODEV;
498 }
499 static inline int css_do_rchp(uint8_t cssid, uint8_t chpid)
500 {
501 return -ENODEV;
502 }
503 static inline bool css_present(uint8_t cssid)
504 {
505 return false;
506 }
507 #endif
508
509 #define cpu_init(model) (&cpu_s390x_init(model)->env)
510 #define cpu_exec cpu_s390x_exec
511 #define cpu_gen_code cpu_s390x_gen_code
512 #define cpu_signal_handler cpu_s390x_signal_handler
513
514 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
515 #define cpu_list s390_cpu_list
516
517 #include "exec/exec-all.h"
518
519 #define EXCP_EXT 1 /* external interrupt */
520 #define EXCP_SVC 2 /* supervisor call (syscall) */
521 #define EXCP_PGM 3 /* program interruption */
522 #define EXCP_IO 7 /* I/O interrupt */
523 #define EXCP_MCHK 8 /* machine check */
524
525 #define INTERRUPT_EXT (1 << 0)
526 #define INTERRUPT_TOD (1 << 1)
527 #define INTERRUPT_CPUTIMER (1 << 2)
528 #define INTERRUPT_IO (1 << 3)
529 #define INTERRUPT_MCHK (1 << 4)
530
531 /* Program Status Word. */
532 #define S390_PSWM_REGNUM 0
533 #define S390_PSWA_REGNUM 1
534 /* General Purpose Registers. */
535 #define S390_R0_REGNUM 2
536 #define S390_R1_REGNUM 3
537 #define S390_R2_REGNUM 4
538 #define S390_R3_REGNUM 5
539 #define S390_R4_REGNUM 6
540 #define S390_R5_REGNUM 7
541 #define S390_R6_REGNUM 8
542 #define S390_R7_REGNUM 9
543 #define S390_R8_REGNUM 10
544 #define S390_R9_REGNUM 11
545 #define S390_R10_REGNUM 12
546 #define S390_R11_REGNUM 13
547 #define S390_R12_REGNUM 14
548 #define S390_R13_REGNUM 15
549 #define S390_R14_REGNUM 16
550 #define S390_R15_REGNUM 17
551 /* Access Registers. */
552 #define S390_A0_REGNUM 18
553 #define S390_A1_REGNUM 19
554 #define S390_A2_REGNUM 20
555 #define S390_A3_REGNUM 21
556 #define S390_A4_REGNUM 22
557 #define S390_A5_REGNUM 23
558 #define S390_A6_REGNUM 24
559 #define S390_A7_REGNUM 25
560 #define S390_A8_REGNUM 26
561 #define S390_A9_REGNUM 27
562 #define S390_A10_REGNUM 28
563 #define S390_A11_REGNUM 29
564 #define S390_A12_REGNUM 30
565 #define S390_A13_REGNUM 31
566 #define S390_A14_REGNUM 32
567 #define S390_A15_REGNUM 33
568 /* Floating Point Control Word. */
569 #define S390_FPC_REGNUM 34
570 /* Floating Point Registers. */
571 #define S390_F0_REGNUM 35
572 #define S390_F1_REGNUM 36
573 #define S390_F2_REGNUM 37
574 #define S390_F3_REGNUM 38
575 #define S390_F4_REGNUM 39
576 #define S390_F5_REGNUM 40
577 #define S390_F6_REGNUM 41
578 #define S390_F7_REGNUM 42
579 #define S390_F8_REGNUM 43
580 #define S390_F9_REGNUM 44
581 #define S390_F10_REGNUM 45
582 #define S390_F11_REGNUM 46
583 #define S390_F12_REGNUM 47
584 #define S390_F13_REGNUM 48
585 #define S390_F14_REGNUM 49
586 #define S390_F15_REGNUM 50
587 /* Total. */
588 #define S390_NUM_REGS 51
589
590 /* CC optimization */
591
592 enum cc_op {
593 CC_OP_CONST0 = 0, /* CC is 0 */
594 CC_OP_CONST1, /* CC is 1 */
595 CC_OP_CONST2, /* CC is 2 */
596 CC_OP_CONST3, /* CC is 3 */
597
598 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
599 CC_OP_STATIC, /* CC value is env->cc_op */
600
601 CC_OP_NZ, /* env->cc_dst != 0 */
602 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
603 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
604 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
605 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
606 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
607 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
608
609 CC_OP_ADD_64, /* overflow on add (64bit) */
610 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
611 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
612 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
613 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
614 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
615 CC_OP_ABS_64, /* sign eval on abs (64bit) */
616 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
617
618 CC_OP_ADD_32, /* overflow on add (32bit) */
619 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
620 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
621 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
622 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
623 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
624 CC_OP_ABS_32, /* sign eval on abs (64bit) */
625 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
626
627 CC_OP_COMP_32, /* complement */
628 CC_OP_COMP_64, /* complement */
629
630 CC_OP_TM_32, /* test under mask (32bit) */
631 CC_OP_TM_64, /* test under mask (64bit) */
632
633 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
634 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
635 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
636
637 CC_OP_ICM, /* insert characters under mask */
638 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
639 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
640 CC_OP_FLOGR, /* find leftmost one */
641 CC_OP_MAX
642 };
643
644 static const char *cc_names[] = {
645 [CC_OP_CONST0] = "CC_OP_CONST0",
646 [CC_OP_CONST1] = "CC_OP_CONST1",
647 [CC_OP_CONST2] = "CC_OP_CONST2",
648 [CC_OP_CONST3] = "CC_OP_CONST3",
649 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
650 [CC_OP_STATIC] = "CC_OP_STATIC",
651 [CC_OP_NZ] = "CC_OP_NZ",
652 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
653 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
654 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
655 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
656 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
657 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
658 [CC_OP_ADD_64] = "CC_OP_ADD_64",
659 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
660 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
661 [CC_OP_SUB_64] = "CC_OP_SUB_64",
662 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
663 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
664 [CC_OP_ABS_64] = "CC_OP_ABS_64",
665 [CC_OP_NABS_64] = "CC_OP_NABS_64",
666 [CC_OP_ADD_32] = "CC_OP_ADD_32",
667 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
668 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
669 [CC_OP_SUB_32] = "CC_OP_SUB_32",
670 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
671 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
672 [CC_OP_ABS_32] = "CC_OP_ABS_32",
673 [CC_OP_NABS_32] = "CC_OP_NABS_32",
674 [CC_OP_COMP_32] = "CC_OP_COMP_32",
675 [CC_OP_COMP_64] = "CC_OP_COMP_64",
676 [CC_OP_TM_32] = "CC_OP_TM_32",
677 [CC_OP_TM_64] = "CC_OP_TM_64",
678 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
679 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
680 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
681 [CC_OP_ICM] = "CC_OP_ICM",
682 [CC_OP_SLA_32] = "CC_OP_SLA_32",
683 [CC_OP_SLA_64] = "CC_OP_SLA_64",
684 [CC_OP_FLOGR] = "CC_OP_FLOGR",
685 };
686
687 static inline const char *cc_name(int cc_op)
688 {
689 return cc_names[cc_op];
690 }
691
692 typedef struct LowCore
693 {
694 /* prefix area: defined by architecture */
695 uint32_t ccw1[2]; /* 0x000 */
696 uint32_t ccw2[4]; /* 0x008 */
697 uint8_t pad1[0x80-0x18]; /* 0x018 */
698 uint32_t ext_params; /* 0x080 */
699 uint16_t cpu_addr; /* 0x084 */
700 uint16_t ext_int_code; /* 0x086 */
701 uint16_t svc_ilen; /* 0x088 */
702 uint16_t svc_code; /* 0x08a */
703 uint16_t pgm_ilen; /* 0x08c */
704 uint16_t pgm_code; /* 0x08e */
705 uint32_t data_exc_code; /* 0x090 */
706 uint16_t mon_class_num; /* 0x094 */
707 uint16_t per_perc_atmid; /* 0x096 */
708 uint64_t per_address; /* 0x098 */
709 uint8_t exc_access_id; /* 0x0a0 */
710 uint8_t per_access_id; /* 0x0a1 */
711 uint8_t op_access_id; /* 0x0a2 */
712 uint8_t ar_access_id; /* 0x0a3 */
713 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
714 uint64_t trans_exc_code; /* 0x0a8 */
715 uint64_t monitor_code; /* 0x0b0 */
716 uint16_t subchannel_id; /* 0x0b8 */
717 uint16_t subchannel_nr; /* 0x0ba */
718 uint32_t io_int_parm; /* 0x0bc */
719 uint32_t io_int_word; /* 0x0c0 */
720 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
721 uint32_t stfl_fac_list; /* 0x0c8 */
722 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
723 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
724 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
725 uint32_t external_damage_code; /* 0x0f4 */
726 uint64_t failing_storage_address; /* 0x0f8 */
727 uint8_t pad6[0x120-0x100]; /* 0x100 */
728 PSW restart_old_psw; /* 0x120 */
729 PSW external_old_psw; /* 0x130 */
730 PSW svc_old_psw; /* 0x140 */
731 PSW program_old_psw; /* 0x150 */
732 PSW mcck_old_psw; /* 0x160 */
733 PSW io_old_psw; /* 0x170 */
734 uint8_t pad7[0x1a0-0x180]; /* 0x180 */
735 PSW restart_psw; /* 0x1a0 */
736 PSW external_new_psw; /* 0x1b0 */
737 PSW svc_new_psw; /* 0x1c0 */
738 PSW program_new_psw; /* 0x1d0 */
739 PSW mcck_new_psw; /* 0x1e0 */
740 PSW io_new_psw; /* 0x1f0 */
741 PSW return_psw; /* 0x200 */
742 uint8_t irb[64]; /* 0x210 */
743 uint64_t sync_enter_timer; /* 0x250 */
744 uint64_t async_enter_timer; /* 0x258 */
745 uint64_t exit_timer; /* 0x260 */
746 uint64_t last_update_timer; /* 0x268 */
747 uint64_t user_timer; /* 0x270 */
748 uint64_t system_timer; /* 0x278 */
749 uint64_t last_update_clock; /* 0x280 */
750 uint64_t steal_clock; /* 0x288 */
751 PSW return_mcck_psw; /* 0x290 */
752 uint8_t pad8[0xc00-0x2a0]; /* 0x2a0 */
753 /* System info area */
754 uint64_t save_area[16]; /* 0xc00 */
755 uint8_t pad9[0xd40-0xc80]; /* 0xc80 */
756 uint64_t kernel_stack; /* 0xd40 */
757 uint64_t thread_info; /* 0xd48 */
758 uint64_t async_stack; /* 0xd50 */
759 uint64_t kernel_asce; /* 0xd58 */
760 uint64_t user_asce; /* 0xd60 */
761 uint64_t panic_stack; /* 0xd68 */
762 uint64_t user_exec_asce; /* 0xd70 */
763 uint8_t pad10[0xdc0-0xd78]; /* 0xd78 */
764
765 /* SMP info area: defined by DJB */
766 uint64_t clock_comparator; /* 0xdc0 */
767 uint64_t ext_call_fast; /* 0xdc8 */
768 uint64_t percpu_offset; /* 0xdd0 */
769 uint64_t current_task; /* 0xdd8 */
770 uint32_t softirq_pending; /* 0xde0 */
771 uint32_t pad_0x0de4; /* 0xde4 */
772 uint64_t int_clock; /* 0xde8 */
773 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
774
775 /* 0xe00 is used as indicator for dump tools */
776 /* whether the kernel died with panic() or not */
777 uint32_t panic_magic; /* 0xe00 */
778
779 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
780
781 /* 64 bit extparam used for pfault, diag 250 etc */
782 uint64_t ext_params2; /* 0x11B8 */
783
784 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
785
786 /* System info area */
787
788 uint64_t floating_pt_save_area[16]; /* 0x1200 */
789 uint64_t gpregs_save_area[16]; /* 0x1280 */
790 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
791 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
792 uint32_t prefixreg_save_area; /* 0x1318 */
793 uint32_t fpt_creg_save_area; /* 0x131c */
794 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
795 uint32_t tod_progreg_save_area; /* 0x1324 */
796 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
797 uint32_t clock_comp_save_area[2]; /* 0x1330 */
798 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
799 uint32_t access_regs_save_area[16]; /* 0x1340 */
800 uint64_t cregs_save_area[16]; /* 0x1380 */
801
802 /* align to the top of the prefix area */
803
804 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
805 } QEMU_PACKED LowCore;
806
807 /* STSI */
808 #define STSI_LEVEL_MASK 0x00000000f0000000ULL
809 #define STSI_LEVEL_CURRENT 0x0000000000000000ULL
810 #define STSI_LEVEL_1 0x0000000010000000ULL
811 #define STSI_LEVEL_2 0x0000000020000000ULL
812 #define STSI_LEVEL_3 0x0000000030000000ULL
813 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
814 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL
815 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
816 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL
817
818 /* Basic Machine Configuration */
819 struct sysib_111 {
820 uint32_t res1[8];
821 uint8_t manuf[16];
822 uint8_t type[4];
823 uint8_t res2[12];
824 uint8_t model[16];
825 uint8_t sequence[16];
826 uint8_t plant[4];
827 uint8_t res3[156];
828 };
829
830 /* Basic Machine CPU */
831 struct sysib_121 {
832 uint32_t res1[80];
833 uint8_t sequence[16];
834 uint8_t plant[4];
835 uint8_t res2[2];
836 uint16_t cpu_addr;
837 uint8_t res3[152];
838 };
839
840 /* Basic Machine CPUs */
841 struct sysib_122 {
842 uint8_t res1[32];
843 uint32_t capability;
844 uint16_t total_cpus;
845 uint16_t active_cpus;
846 uint16_t standby_cpus;
847 uint16_t reserved_cpus;
848 uint16_t adjustments[2026];
849 };
850
851 /* LPAR CPU */
852 struct sysib_221 {
853 uint32_t res1[80];
854 uint8_t sequence[16];
855 uint8_t plant[4];
856 uint16_t cpu_id;
857 uint16_t cpu_addr;
858 uint8_t res3[152];
859 };
860
861 /* LPAR CPUs */
862 struct sysib_222 {
863 uint32_t res1[32];
864 uint16_t lpar_num;
865 uint8_t res2;
866 uint8_t lcpuc;
867 uint16_t total_cpus;
868 uint16_t conf_cpus;
869 uint16_t standby_cpus;
870 uint16_t reserved_cpus;
871 uint8_t name[8];
872 uint32_t caf;
873 uint8_t res3[16];
874 uint16_t dedicated_cpus;
875 uint16_t shared_cpus;
876 uint8_t res4[180];
877 };
878
879 /* VM CPUs */
880 struct sysib_322 {
881 uint8_t res1[31];
882 uint8_t count;
883 struct {
884 uint8_t res2[4];
885 uint16_t total_cpus;
886 uint16_t conf_cpus;
887 uint16_t standby_cpus;
888 uint16_t reserved_cpus;
889 uint8_t name[8];
890 uint32_t caf;
891 uint8_t cpi[16];
892 uint8_t res3[24];
893 } vm[8];
894 uint8_t res4[3552];
895 };
896
897 /* MMU defines */
898 #define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
899 #define _ASCE_SUBSPACE 0x200 /* subspace group control */
900 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
901 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
902 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
903 #define _ASCE_REAL_SPACE 0x20 /* real space control */
904 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
905 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */
906 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */
907 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */
908 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
909 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */
910
911 #define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
912 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
913 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
914 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
915 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
916 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
917 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */
918
919 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
920 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
921 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
922
923 #define _PAGE_RO 0x200 /* HW read-only bit */
924 #define _PAGE_INVALID 0x400 /* HW invalid bit */
925
926 #define SK_C (0x1 << 1)
927 #define SK_R (0x1 << 2)
928 #define SK_F (0x1 << 3)
929 #define SK_ACC_MASK (0xf << 4)
930
931 #define SIGP_SENSE 0x01
932 #define SIGP_EXTERNAL_CALL 0x02
933 #define SIGP_EMERGENCY 0x03
934 #define SIGP_START 0x04
935 #define SIGP_STOP 0x05
936 #define SIGP_RESTART 0x06
937 #define SIGP_STOP_STORE_STATUS 0x09
938 #define SIGP_INITIAL_CPU_RESET 0x0b
939 #define SIGP_CPU_RESET 0x0c
940 #define SIGP_SET_PREFIX 0x0d
941 #define SIGP_STORE_STATUS_ADDR 0x0e
942 #define SIGP_SET_ARCH 0x12
943
944 /* cpu status bits */
945 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
946 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL
947 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
948 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
949 #define SIGP_STAT_STOPPED 0x00000040UL
950 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
951 #define SIGP_STAT_CHECK_STOP 0x00000010UL
952 #define SIGP_STAT_INOPERATIVE 0x00000004UL
953 #define SIGP_STAT_INVALID_ORDER 0x00000002UL
954 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
955
956 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
957 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
958 target_ulong *raddr, int *flags);
959 int sclp_service_call(uint32_t sccb, uint64_t code);
960 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
961 uint64_t vr);
962
963 #define TARGET_HAS_ICE 1
964
965 /* The value of the TOD clock for 1.1.1970. */
966 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
967
968 /* Converts ns to s390's clock format */
969 static inline uint64_t time2tod(uint64_t ns) {
970 return (ns << 9) / 125;
971 }
972
973 static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
974 uint64_t param64)
975 {
976 CPUS390XState *env = &cpu->env;
977
978 if (env->ext_index == MAX_EXT_QUEUE - 1) {
979 /* ugh - can't queue anymore. Let's drop. */
980 return;
981 }
982
983 env->ext_index++;
984 assert(env->ext_index < MAX_EXT_QUEUE);
985
986 env->ext_queue[env->ext_index].code = code;
987 env->ext_queue[env->ext_index].param = param;
988 env->ext_queue[env->ext_index].param64 = param64;
989
990 env->pending_int |= INTERRUPT_EXT;
991 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
992 }
993
994 static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
995 uint16_t subchannel_number,
996 uint32_t io_int_parm, uint32_t io_int_word)
997 {
998 CPUS390XState *env = &cpu->env;
999 int isc = IO_INT_WORD_ISC(io_int_word);
1000
1001 if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1002 /* ugh - can't queue anymore. Let's drop. */
1003 return;
1004 }
1005
1006 env->io_index[isc]++;
1007 assert(env->io_index[isc] < MAX_IO_QUEUE);
1008
1009 env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1010 env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1011 env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1012 env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1013
1014 env->pending_int |= INTERRUPT_IO;
1015 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1016 }
1017
1018 static inline void cpu_inject_crw_mchk(S390CPU *cpu)
1019 {
1020 CPUS390XState *env = &cpu->env;
1021
1022 if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1023 /* ugh - can't queue anymore. Let's drop. */
1024 return;
1025 }
1026
1027 env->mchk_index++;
1028 assert(env->mchk_index < MAX_MCHK_QUEUE);
1029
1030 env->mchk_queue[env->mchk_index].type = 1;
1031
1032 env->pending_int |= INTERRUPT_MCHK;
1033 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1034 }
1035
1036 static inline bool cpu_has_work(CPUState *cpu)
1037 {
1038 S390CPU *s390_cpu = S390_CPU(cpu);
1039 CPUS390XState *env = &s390_cpu->env;
1040
1041 return (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
1042 (env->psw.mask & PSW_MASK_EXT);
1043 }
1044
1045 /* fpu_helper.c */
1046 uint32_t set_cc_nz_f32(float32 v);
1047 uint32_t set_cc_nz_f64(float64 v);
1048 uint32_t set_cc_nz_f128(float128 v);
1049
1050 /* misc_helper.c */
1051 #ifndef CONFIG_USER_ONLY
1052 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1053 #endif
1054 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1055 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1056 uintptr_t retaddr);
1057
1058 #include <sysemu/kvm.h>
1059
1060 #ifdef CONFIG_KVM
1061 void kvm_s390_io_interrupt(S390CPU *cpu, uint16_t subchannel_id,
1062 uint16_t subchannel_nr, uint32_t io_int_parm,
1063 uint32_t io_int_word);
1064 void kvm_s390_crw_mchk(S390CPU *cpu);
1065 void kvm_s390_enable_css_support(S390CPU *cpu);
1066 int kvm_s390_get_registers_partial(CPUState *cpu);
1067 int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1068 int vq, bool assign);
1069 #else
1070 static inline void kvm_s390_io_interrupt(S390CPU *cpu,
1071 uint16_t subchannel_id,
1072 uint16_t subchannel_nr,
1073 uint32_t io_int_parm,
1074 uint32_t io_int_word)
1075 {
1076 }
1077 static inline void kvm_s390_crw_mchk(S390CPU *cpu)
1078 {
1079 }
1080 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1081 {
1082 }
1083 static inline int kvm_s390_get_registers_partial(CPUState *cpu)
1084 {
1085 return -ENOSYS;
1086 }
1087 static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1088 uint32_t sch, int vq,
1089 bool assign)
1090 {
1091 return -ENOSYS;
1092 }
1093 #endif
1094
1095 static inline void s390_io_interrupt(S390CPU *cpu,
1096 uint16_t subchannel_id,
1097 uint16_t subchannel_nr,
1098 uint32_t io_int_parm,
1099 uint32_t io_int_word)
1100 {
1101 if (kvm_enabled()) {
1102 kvm_s390_io_interrupt(cpu, subchannel_id, subchannel_nr, io_int_parm,
1103 io_int_word);
1104 } else {
1105 cpu_inject_io(cpu, subchannel_id, subchannel_nr, io_int_parm,
1106 io_int_word);
1107 }
1108 }
1109
1110 static inline void s390_crw_mchk(S390CPU *cpu)
1111 {
1112 if (kvm_enabled()) {
1113 kvm_s390_crw_mchk(cpu);
1114 } else {
1115 cpu_inject_crw_mchk(cpu);
1116 }
1117 }
1118
1119 static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1120 uint32_t sch_id, int vq,
1121 bool assign)
1122 {
1123 if (kvm_enabled()) {
1124 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1125 } else {
1126 return -ENOSYS;
1127 }
1128 }
1129
1130 #endif
Qemu copy for testing