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s390x/kvm: 2 byte software breakpoint support
[mirror_qemu.git] / target-s390x / cpu.h
1 /*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #ifndef S390X_CPU_H
24 #define S390X_CPU_H
25
26 #include "qemu-common.h"
27 #include "cpu-qom.h"
28
29 #define TARGET_LONG_BITS 64
30
31 #define ELF_MACHINE_UNAME "S390X"
32
33 #define CPUArchState struct CPUS390XState
34
35 #include "exec/cpu-defs.h"
36 #define TARGET_PAGE_BITS 12
37
38 #define TARGET_PHYS_ADDR_SPACE_BITS 64
39 #define TARGET_VIRT_ADDR_SPACE_BITS 64
40
41 #include "exec/cpu-all.h"
42
43 #include "fpu/softfloat.h"
44
45 #define NB_MMU_MODES 3
46 #define TARGET_INSN_START_EXTRA_WORDS 1
47
48 #define MMU_MODE0_SUFFIX _primary
49 #define MMU_MODE1_SUFFIX _secondary
50 #define MMU_MODE2_SUFFIX _home
51
52 #define MMU_USER_IDX 0
53
54 #define MAX_EXT_QUEUE 16
55 #define MAX_IO_QUEUE 16
56 #define MAX_MCHK_QUEUE 16
57
58 #define PSW_MCHK_MASK 0x0004000000000000
59 #define PSW_IO_MASK 0x0200000000000000
60
61 typedef struct PSW {
62 uint64_t mask;
63 uint64_t addr;
64 } PSW;
65
66 typedef struct ExtQueue {
67 uint32_t code;
68 uint32_t param;
69 uint32_t param64;
70 } ExtQueue;
71
72 typedef struct IOIntQueue {
73 uint16_t id;
74 uint16_t nr;
75 uint32_t parm;
76 uint32_t word;
77 } IOIntQueue;
78
79 typedef struct MchkQueue {
80 uint16_t type;
81 } MchkQueue;
82
83 typedef struct CPUS390XState {
84 uint64_t regs[16]; /* GP registers */
85 /*
86 * The floating point registers are part of the vector registers.
87 * vregs[0][0] -> vregs[15][0] are 16 floating point registers
88 */
89 CPU_DoubleU vregs[32][2]; /* vector registers */
90 uint32_t aregs[16]; /* access registers */
91
92 uint32_t fpc; /* floating-point control register */
93 uint32_t cc_op;
94
95 float_status fpu_status; /* passed to softfloat lib */
96
97 /* The low part of a 128-bit return, or remainder of a divide. */
98 uint64_t retxl;
99
100 PSW psw;
101
102 uint64_t cc_src;
103 uint64_t cc_dst;
104 uint64_t cc_vr;
105
106 uint64_t __excp_addr;
107 uint64_t psa;
108
109 uint32_t int_pgm_code;
110 uint32_t int_pgm_ilen;
111
112 uint32_t int_svc_code;
113 uint32_t int_svc_ilen;
114
115 uint64_t per_address;
116 uint16_t per_perc_atmid;
117
118 uint64_t cregs[16]; /* control registers */
119
120 ExtQueue ext_queue[MAX_EXT_QUEUE];
121 IOIntQueue io_queue[MAX_IO_QUEUE][8];
122 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
123
124 int pending_int;
125 int ext_index;
126 int io_index[8];
127 int mchk_index;
128
129 uint64_t ckc;
130 uint64_t cputm;
131 uint32_t todpr;
132
133 uint64_t pfault_token;
134 uint64_t pfault_compare;
135 uint64_t pfault_select;
136
137 uint64_t gbea;
138 uint64_t pp;
139
140 uint8_t riccb[64];
141
142 CPU_COMMON
143
144 /* reset does memset(0) up to here */
145
146 uint32_t cpu_num;
147 uint32_t machine_type;
148
149 uint64_t tod_offset;
150 uint64_t tod_basetime;
151 QEMUTimer *tod_timer;
152
153 QEMUTimer *cpu_timer;
154
155 /*
156 * The cpu state represents the logical state of a cpu. In contrast to other
157 * architectures, there is a difference between a halt and a stop on s390.
158 * If all cpus are either stopped (including check stop) or in the disabled
159 * wait state, the vm can be shut down.
160 */
161 #define CPU_STATE_UNINITIALIZED 0x00
162 #define CPU_STATE_STOPPED 0x01
163 #define CPU_STATE_CHECK_STOP 0x02
164 #define CPU_STATE_OPERATING 0x03
165 #define CPU_STATE_LOAD 0x04
166 uint8_t cpu_state;
167
168 /* currently processed sigp order */
169 uint8_t sigp_order;
170
171 } CPUS390XState;
172
173 static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
174 {
175 return &cs->vregs[nr][0];
176 }
177
178 /**
179 * S390CPU:
180 * @env: #CPUS390XState.
181 *
182 * An S/390 CPU.
183 */
184 struct S390CPU {
185 /*< private >*/
186 CPUState parent_obj;
187 /*< public >*/
188
189 CPUS390XState env;
190 int64_t id;
191 /* needed for live migration */
192 void *irqstate;
193 uint32_t irqstate_saved_size;
194 };
195
196 static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
197 {
198 return container_of(env, S390CPU, env);
199 }
200
201 #define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
202
203 #define ENV_OFFSET offsetof(S390CPU, env)
204
205 #ifndef CONFIG_USER_ONLY
206 extern const struct VMStateDescription vmstate_s390_cpu;
207 #endif
208
209 void s390_cpu_do_interrupt(CPUState *cpu);
210 bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req);
211 void s390_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
212 int flags);
213 int s390_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
214 int cpuid, void *opaque);
215
216 hwaddr s390_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
217 hwaddr s390_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);
218 int s390_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
219 int s390_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
220 void s390_cpu_gdb_init(CPUState *cs);
221 void s390x_cpu_debug_excp_handler(CPUState *cs);
222
223 #include "sysemu/kvm.h"
224
225 /* distinguish between 24 bit and 31 bit addressing */
226 #define HIGH_ORDER_BIT 0x80000000
227
228 /* Interrupt Codes */
229 /* Program Interrupts */
230 #define PGM_OPERATION 0x0001
231 #define PGM_PRIVILEGED 0x0002
232 #define PGM_EXECUTE 0x0003
233 #define PGM_PROTECTION 0x0004
234 #define PGM_ADDRESSING 0x0005
235 #define PGM_SPECIFICATION 0x0006
236 #define PGM_DATA 0x0007
237 #define PGM_FIXPT_OVERFLOW 0x0008
238 #define PGM_FIXPT_DIVIDE 0x0009
239 #define PGM_DEC_OVERFLOW 0x000a
240 #define PGM_DEC_DIVIDE 0x000b
241 #define PGM_HFP_EXP_OVERFLOW 0x000c
242 #define PGM_HFP_EXP_UNDERFLOW 0x000d
243 #define PGM_HFP_SIGNIFICANCE 0x000e
244 #define PGM_HFP_DIVIDE 0x000f
245 #define PGM_SEGMENT_TRANS 0x0010
246 #define PGM_PAGE_TRANS 0x0011
247 #define PGM_TRANS_SPEC 0x0012
248 #define PGM_SPECIAL_OP 0x0013
249 #define PGM_OPERAND 0x0015
250 #define PGM_TRACE_TABLE 0x0016
251 #define PGM_SPACE_SWITCH 0x001c
252 #define PGM_HFP_SQRT 0x001d
253 #define PGM_PC_TRANS_SPEC 0x001f
254 #define PGM_AFX_TRANS 0x0020
255 #define PGM_ASX_TRANS 0x0021
256 #define PGM_LX_TRANS 0x0022
257 #define PGM_EX_TRANS 0x0023
258 #define PGM_PRIM_AUTH 0x0024
259 #define PGM_SEC_AUTH 0x0025
260 #define PGM_ALET_SPEC 0x0028
261 #define PGM_ALEN_SPEC 0x0029
262 #define PGM_ALE_SEQ 0x002a
263 #define PGM_ASTE_VALID 0x002b
264 #define PGM_ASTE_SEQ 0x002c
265 #define PGM_EXT_AUTH 0x002d
266 #define PGM_STACK_FULL 0x0030
267 #define PGM_STACK_EMPTY 0x0031
268 #define PGM_STACK_SPEC 0x0032
269 #define PGM_STACK_TYPE 0x0033
270 #define PGM_STACK_OP 0x0034
271 #define PGM_ASCE_TYPE 0x0038
272 #define PGM_REG_FIRST_TRANS 0x0039
273 #define PGM_REG_SEC_TRANS 0x003a
274 #define PGM_REG_THIRD_TRANS 0x003b
275 #define PGM_MONITOR 0x0040
276 #define PGM_PER 0x0080
277 #define PGM_CRYPTO 0x0119
278
279 /* External Interrupts */
280 #define EXT_INTERRUPT_KEY 0x0040
281 #define EXT_CLOCK_COMP 0x1004
282 #define EXT_CPU_TIMER 0x1005
283 #define EXT_MALFUNCTION 0x1200
284 #define EXT_EMERGENCY 0x1201
285 #define EXT_EXTERNAL_CALL 0x1202
286 #define EXT_ETR 0x1406
287 #define EXT_SERVICE 0x2401
288 #define EXT_VIRTIO 0x2603
289
290 /* PSW defines */
291 #undef PSW_MASK_PER
292 #undef PSW_MASK_DAT
293 #undef PSW_MASK_IO
294 #undef PSW_MASK_EXT
295 #undef PSW_MASK_KEY
296 #undef PSW_SHIFT_KEY
297 #undef PSW_MASK_MCHECK
298 #undef PSW_MASK_WAIT
299 #undef PSW_MASK_PSTATE
300 #undef PSW_MASK_ASC
301 #undef PSW_MASK_CC
302 #undef PSW_MASK_PM
303 #undef PSW_MASK_64
304 #undef PSW_MASK_32
305 #undef PSW_MASK_ESA_ADDR
306
307 #define PSW_MASK_PER 0x4000000000000000ULL
308 #define PSW_MASK_DAT 0x0400000000000000ULL
309 #define PSW_MASK_IO 0x0200000000000000ULL
310 #define PSW_MASK_EXT 0x0100000000000000ULL
311 #define PSW_MASK_KEY 0x00F0000000000000ULL
312 #define PSW_SHIFT_KEY 56
313 #define PSW_MASK_MCHECK 0x0004000000000000ULL
314 #define PSW_MASK_WAIT 0x0002000000000000ULL
315 #define PSW_MASK_PSTATE 0x0001000000000000ULL
316 #define PSW_MASK_ASC 0x0000C00000000000ULL
317 #define PSW_MASK_CC 0x0000300000000000ULL
318 #define PSW_MASK_PM 0x00000F0000000000ULL
319 #define PSW_MASK_64 0x0000000100000000ULL
320 #define PSW_MASK_32 0x0000000080000000ULL
321 #define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
322
323 #undef PSW_ASC_PRIMARY
324 #undef PSW_ASC_ACCREG
325 #undef PSW_ASC_SECONDARY
326 #undef PSW_ASC_HOME
327
328 #define PSW_ASC_PRIMARY 0x0000000000000000ULL
329 #define PSW_ASC_ACCREG 0x0000400000000000ULL
330 #define PSW_ASC_SECONDARY 0x0000800000000000ULL
331 #define PSW_ASC_HOME 0x0000C00000000000ULL
332
333 /* tb flags */
334
335 #define FLAG_MASK_PER (PSW_MASK_PER >> 32)
336 #define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
337 #define FLAG_MASK_IO (PSW_MASK_IO >> 32)
338 #define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
339 #define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
340 #define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
341 #define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
342 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
343 #define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
344 #define FLAG_MASK_CC (PSW_MASK_CC >> 32)
345 #define FLAG_MASK_PM (PSW_MASK_PM >> 32)
346 #define FLAG_MASK_64 (PSW_MASK_64 >> 32)
347 #define FLAG_MASK_32 0x00001000
348
349 /* Control register 0 bits */
350 #define CR0_LOWPROT 0x0000000010000000ULL
351 #define CR0_EDAT 0x0000000000800000ULL
352
353 /* MMU */
354 #define MMU_PRIMARY_IDX 0
355 #define MMU_SECONDARY_IDX 1
356 #define MMU_HOME_IDX 2
357
358 static inline int cpu_mmu_index (CPUS390XState *env, bool ifetch)
359 {
360 switch (env->psw.mask & PSW_MASK_ASC) {
361 case PSW_ASC_PRIMARY:
362 return MMU_PRIMARY_IDX;
363 case PSW_ASC_SECONDARY:
364 return MMU_SECONDARY_IDX;
365 case PSW_ASC_HOME:
366 return MMU_HOME_IDX;
367 case PSW_ASC_ACCREG:
368 /* Fallthrough: access register mode is not yet supported */
369 default:
370 abort();
371 }
372 }
373
374 static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx)
375 {
376 switch (mmu_idx) {
377 case MMU_PRIMARY_IDX:
378 return PSW_ASC_PRIMARY;
379 case MMU_SECONDARY_IDX:
380 return PSW_ASC_SECONDARY;
381 case MMU_HOME_IDX:
382 return PSW_ASC_HOME;
383 default:
384 abort();
385 }
386 }
387
388 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
389 target_ulong *cs_base, uint32_t *flags)
390 {
391 *pc = env->psw.addr;
392 *cs_base = 0;
393 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
394 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
395 }
396
397 #define MAX_ILEN 6
398
399 /* While the PoO talks about ILC (a number between 1-3) what is actually
400 stored in LowCore is shifted left one bit (an even between 2-6). As
401 this is the actual length of the insn and therefore more useful, that
402 is what we want to pass around and manipulate. To make sure that we
403 have applied this distinction universally, rename the "ILC" to "ILEN". */
404 static inline int get_ilen(uint8_t opc)
405 {
406 switch (opc >> 6) {
407 case 0:
408 return 2;
409 case 1:
410 case 2:
411 return 4;
412 default:
413 return 6;
414 }
415 }
416
417 /* PER bits from control register 9 */
418 #define PER_CR9_EVENT_BRANCH 0x80000000
419 #define PER_CR9_EVENT_IFETCH 0x40000000
420 #define PER_CR9_EVENT_STORE 0x20000000
421 #define PER_CR9_EVENT_STORE_REAL 0x08000000
422 #define PER_CR9_EVENT_NULLIFICATION 0x01000000
423 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
424 #define PER_CR9_CONTROL_ALTERATION 0x00200000
425
426 /* PER bits from the PER CODE/ATMID/AI in lowcore */
427 #define PER_CODE_EVENT_BRANCH 0x8000
428 #define PER_CODE_EVENT_IFETCH 0x4000
429 #define PER_CODE_EVENT_STORE 0x2000
430 #define PER_CODE_EVENT_STORE_REAL 0x0800
431 #define PER_CODE_EVENT_NULLIFICATION 0x0100
432
433 /* Compute the ATMID field that is stored in the per_perc_atmid lowcore
434 entry when a PER exception is triggered. */
435 static inline uint8_t get_per_atmid(CPUS390XState *env)
436 {
437 return ((env->psw.mask & PSW_MASK_64) ? (1 << 7) : 0) |
438 ( (1 << 6) ) |
439 ((env->psw.mask & PSW_MASK_32) ? (1 << 5) : 0) |
440 ((env->psw.mask & PSW_MASK_DAT)? (1 << 4) : 0) |
441 ((env->psw.mask & PSW_ASC_SECONDARY)? (1 << 3) : 0) |
442 ((env->psw.mask & PSW_ASC_ACCREG)? (1 << 2) : 0);
443 }
444
445 /* Check if an address is within the PER starting address and the PER
446 ending address. The address range might loop. */
447 static inline bool get_per_in_range(CPUS390XState *env, uint64_t addr)
448 {
449 if (env->cregs[10] <= env->cregs[11]) {
450 return env->cregs[10] <= addr && addr <= env->cregs[11];
451 } else {
452 return env->cregs[10] <= addr || addr <= env->cregs[11];
453 }
454 }
455
456 #ifndef CONFIG_USER_ONLY
457 /* In several cases of runtime exceptions, we havn't recorded the true
458 instruction length. Use these codes when raising exceptions in order
459 to re-compute the length by examining the insn in memory. */
460 #define ILEN_LATER 0x20
461 #define ILEN_LATER_INC 0x21
462 void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
463 #endif
464
465 S390CPU *cpu_s390x_init(const char *cpu_model);
466 S390CPU *s390x_new_cpu(const char *cpu_model, int64_t id, Error **errp);
467 S390CPU *cpu_s390x_create(const char *cpu_model, Error **errp);
468 void s390x_translate_init(void);
469
470 /* you can call this signal handler from your SIGBUS and SIGSEGV
471 signal handlers to inform the virtual CPU of exceptions. non zero
472 is returned if the signal was handled by the virtual CPU. */
473 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
474 void *puc);
475 int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
476 int mmu_idx);
477
478
479 #ifndef CONFIG_USER_ONLY
480 void do_restart_interrupt(CPUS390XState *env);
481
482 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb,
483 uint8_t *ar)
484 {
485 hwaddr addr = 0;
486 uint8_t reg;
487
488 reg = ipb >> 28;
489 if (reg > 0) {
490 addr = env->regs[reg];
491 }
492 addr += (ipb >> 16) & 0xfff;
493 if (ar) {
494 *ar = reg;
495 }
496
497 return addr;
498 }
499
500 /* Base/displacement are at the same locations. */
501 #define decode_basedisp_rs decode_basedisp_s
502
503 /* helper functions for run_on_cpu() */
504 static inline void s390_do_cpu_reset(void *arg)
505 {
506 CPUState *cs = arg;
507 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
508
509 scc->cpu_reset(cs);
510 }
511 static inline void s390_do_cpu_full_reset(void *arg)
512 {
513 CPUState *cs = arg;
514
515 cpu_reset(cs);
516 }
517
518 void s390x_tod_timer(void *opaque);
519 void s390x_cpu_timer(void *opaque);
520
521 int s390_virtio_hypercall(CPUS390XState *env);
522
523 #ifdef CONFIG_KVM
524 void kvm_s390_service_interrupt(uint32_t parm);
525 void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
526 void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
527 int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
528 void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
529 int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, void *hostbuf,
530 int len, bool is_write);
531 int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_clock);
532 int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_clock);
533 #else
534 static inline void kvm_s390_service_interrupt(uint32_t parm)
535 {
536 }
537 static inline int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
538 {
539 return -ENOSYS;
540 }
541 static inline int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
542 {
543 return -ENOSYS;
544 }
545 static inline int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar,
546 void *hostbuf, int len, bool is_write)
547 {
548 return -ENOSYS;
549 }
550 static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
551 uint64_t te_code)
552 {
553 }
554 #endif
555
556 static inline int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
557 {
558 if (kvm_enabled()) {
559 return kvm_s390_get_clock(tod_high, tod_low);
560 }
561 /* Fixme TCG */
562 *tod_high = 0;
563 *tod_low = 0;
564 return 0;
565 }
566
567 static inline int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
568 {
569 if (kvm_enabled()) {
570 return kvm_s390_set_clock(tod_high, tod_low);
571 }
572 /* Fixme TCG */
573 return 0;
574 }
575
576 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
577 unsigned int s390_cpu_halt(S390CPU *cpu);
578 void s390_cpu_unhalt(S390CPU *cpu);
579 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
580 static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
581 {
582 return cpu->env.cpu_state;
583 }
584
585 void gtod_save(QEMUFile *f, void *opaque);
586 int gtod_load(QEMUFile *f, void *opaque, int version_id);
587
588 void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
589 uint64_t param64);
590
591 /* ioinst.c */
592 void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1);
593 void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1);
594 void ioinst_handle_hsch(S390CPU *cpu, uint64_t reg1);
595 void ioinst_handle_msch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
596 void ioinst_handle_ssch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
597 void ioinst_handle_stcrw(S390CPU *cpu, uint32_t ipb);
598 void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
599 int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
600 void ioinst_handle_chsc(S390CPU *cpu, uint32_t ipb);
601 int ioinst_handle_tpi(S390CPU *cpu, uint32_t ipb);
602 void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, uint64_t reg2,
603 uint32_t ipb);
604 void ioinst_handle_rsch(S390CPU *cpu, uint64_t reg1);
605 void ioinst_handle_rchp(S390CPU *cpu, uint64_t reg1);
606 void ioinst_handle_sal(S390CPU *cpu, uint64_t reg1);
607
608 /* service interrupts are floating therefore we must not pass an cpustate */
609 void s390_sclp_extint(uint32_t parm);
610
611 #else
612 static inline unsigned int s390_cpu_halt(S390CPU *cpu)
613 {
614 return 0;
615 }
616
617 static inline void s390_cpu_unhalt(S390CPU *cpu)
618 {
619 }
620
621 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
622 {
623 return 0;
624 }
625 #endif
626 void cpu_lock(void);
627 void cpu_unlock(void);
628
629 extern void subsystem_reset(void);
630
631 #define cpu_init(model) CPU(cpu_s390x_init(model))
632 #define cpu_signal_handler cpu_s390x_signal_handler
633
634 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
635 #define cpu_list s390_cpu_list
636
637 #define EXCP_EXT 1 /* external interrupt */
638 #define EXCP_SVC 2 /* supervisor call (syscall) */
639 #define EXCP_PGM 3 /* program interruption */
640 #define EXCP_IO 7 /* I/O interrupt */
641 #define EXCP_MCHK 8 /* machine check */
642
643 #define INTERRUPT_EXT (1 << 0)
644 #define INTERRUPT_TOD (1 << 1)
645 #define INTERRUPT_CPUTIMER (1 << 2)
646 #define INTERRUPT_IO (1 << 3)
647 #define INTERRUPT_MCHK (1 << 4)
648
649 /* Program Status Word. */
650 #define S390_PSWM_REGNUM 0
651 #define S390_PSWA_REGNUM 1
652 /* General Purpose Registers. */
653 #define S390_R0_REGNUM 2
654 #define S390_R1_REGNUM 3
655 #define S390_R2_REGNUM 4
656 #define S390_R3_REGNUM 5
657 #define S390_R4_REGNUM 6
658 #define S390_R5_REGNUM 7
659 #define S390_R6_REGNUM 8
660 #define S390_R7_REGNUM 9
661 #define S390_R8_REGNUM 10
662 #define S390_R9_REGNUM 11
663 #define S390_R10_REGNUM 12
664 #define S390_R11_REGNUM 13
665 #define S390_R12_REGNUM 14
666 #define S390_R13_REGNUM 15
667 #define S390_R14_REGNUM 16
668 #define S390_R15_REGNUM 17
669 /* Total Core Registers. */
670 #define S390_NUM_CORE_REGS 18
671
672 /* CC optimization */
673
674 enum cc_op {
675 CC_OP_CONST0 = 0, /* CC is 0 */
676 CC_OP_CONST1, /* CC is 1 */
677 CC_OP_CONST2, /* CC is 2 */
678 CC_OP_CONST3, /* CC is 3 */
679
680 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
681 CC_OP_STATIC, /* CC value is env->cc_op */
682
683 CC_OP_NZ, /* env->cc_dst != 0 */
684 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
685 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
686 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
687 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
688 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
689 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
690
691 CC_OP_ADD_64, /* overflow on add (64bit) */
692 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
693 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
694 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
695 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
696 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
697 CC_OP_ABS_64, /* sign eval on abs (64bit) */
698 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
699
700 CC_OP_ADD_32, /* overflow on add (32bit) */
701 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
702 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
703 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
704 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
705 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
706 CC_OP_ABS_32, /* sign eval on abs (64bit) */
707 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
708
709 CC_OP_COMP_32, /* complement */
710 CC_OP_COMP_64, /* complement */
711
712 CC_OP_TM_32, /* test under mask (32bit) */
713 CC_OP_TM_64, /* test under mask (64bit) */
714
715 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
716 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
717 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
718
719 CC_OP_ICM, /* insert characters under mask */
720 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
721 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
722 CC_OP_FLOGR, /* find leftmost one */
723 CC_OP_MAX
724 };
725
726 static const char *cc_names[] = {
727 [CC_OP_CONST0] = "CC_OP_CONST0",
728 [CC_OP_CONST1] = "CC_OP_CONST1",
729 [CC_OP_CONST2] = "CC_OP_CONST2",
730 [CC_OP_CONST3] = "CC_OP_CONST3",
731 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
732 [CC_OP_STATIC] = "CC_OP_STATIC",
733 [CC_OP_NZ] = "CC_OP_NZ",
734 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
735 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
736 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
737 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
738 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
739 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
740 [CC_OP_ADD_64] = "CC_OP_ADD_64",
741 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
742 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
743 [CC_OP_SUB_64] = "CC_OP_SUB_64",
744 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
745 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
746 [CC_OP_ABS_64] = "CC_OP_ABS_64",
747 [CC_OP_NABS_64] = "CC_OP_NABS_64",
748 [CC_OP_ADD_32] = "CC_OP_ADD_32",
749 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
750 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
751 [CC_OP_SUB_32] = "CC_OP_SUB_32",
752 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
753 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
754 [CC_OP_ABS_32] = "CC_OP_ABS_32",
755 [CC_OP_NABS_32] = "CC_OP_NABS_32",
756 [CC_OP_COMP_32] = "CC_OP_COMP_32",
757 [CC_OP_COMP_64] = "CC_OP_COMP_64",
758 [CC_OP_TM_32] = "CC_OP_TM_32",
759 [CC_OP_TM_64] = "CC_OP_TM_64",
760 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
761 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
762 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
763 [CC_OP_ICM] = "CC_OP_ICM",
764 [CC_OP_SLA_32] = "CC_OP_SLA_32",
765 [CC_OP_SLA_64] = "CC_OP_SLA_64",
766 [CC_OP_FLOGR] = "CC_OP_FLOGR",
767 };
768
769 static inline const char *cc_name(int cc_op)
770 {
771 return cc_names[cc_op];
772 }
773
774 static inline void setcc(S390CPU *cpu, uint64_t cc)
775 {
776 CPUS390XState *env = &cpu->env;
777
778 env->psw.mask &= ~(3ull << 44);
779 env->psw.mask |= (cc & 3) << 44;
780 env->cc_op = cc;
781 }
782
783 typedef struct LowCore
784 {
785 /* prefix area: defined by architecture */
786 uint32_t ccw1[2]; /* 0x000 */
787 uint32_t ccw2[4]; /* 0x008 */
788 uint8_t pad1[0x80-0x18]; /* 0x018 */
789 uint32_t ext_params; /* 0x080 */
790 uint16_t cpu_addr; /* 0x084 */
791 uint16_t ext_int_code; /* 0x086 */
792 uint16_t svc_ilen; /* 0x088 */
793 uint16_t svc_code; /* 0x08a */
794 uint16_t pgm_ilen; /* 0x08c */
795 uint16_t pgm_code; /* 0x08e */
796 uint32_t data_exc_code; /* 0x090 */
797 uint16_t mon_class_num; /* 0x094 */
798 uint16_t per_perc_atmid; /* 0x096 */
799 uint64_t per_address; /* 0x098 */
800 uint8_t exc_access_id; /* 0x0a0 */
801 uint8_t per_access_id; /* 0x0a1 */
802 uint8_t op_access_id; /* 0x0a2 */
803 uint8_t ar_access_id; /* 0x0a3 */
804 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
805 uint64_t trans_exc_code; /* 0x0a8 */
806 uint64_t monitor_code; /* 0x0b0 */
807 uint16_t subchannel_id; /* 0x0b8 */
808 uint16_t subchannel_nr; /* 0x0ba */
809 uint32_t io_int_parm; /* 0x0bc */
810 uint32_t io_int_word; /* 0x0c0 */
811 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
812 uint32_t stfl_fac_list; /* 0x0c8 */
813 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
814 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
815 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
816 uint32_t external_damage_code; /* 0x0f4 */
817 uint64_t failing_storage_address; /* 0x0f8 */
818 uint8_t pad6[0x110-0x100]; /* 0x100 */
819 uint64_t per_breaking_event_addr; /* 0x110 */
820 uint8_t pad7[0x120-0x118]; /* 0x118 */
821 PSW restart_old_psw; /* 0x120 */
822 PSW external_old_psw; /* 0x130 */
823 PSW svc_old_psw; /* 0x140 */
824 PSW program_old_psw; /* 0x150 */
825 PSW mcck_old_psw; /* 0x160 */
826 PSW io_old_psw; /* 0x170 */
827 uint8_t pad8[0x1a0-0x180]; /* 0x180 */
828 PSW restart_new_psw; /* 0x1a0 */
829 PSW external_new_psw; /* 0x1b0 */
830 PSW svc_new_psw; /* 0x1c0 */
831 PSW program_new_psw; /* 0x1d0 */
832 PSW mcck_new_psw; /* 0x1e0 */
833 PSW io_new_psw; /* 0x1f0 */
834 PSW return_psw; /* 0x200 */
835 uint8_t irb[64]; /* 0x210 */
836 uint64_t sync_enter_timer; /* 0x250 */
837 uint64_t async_enter_timer; /* 0x258 */
838 uint64_t exit_timer; /* 0x260 */
839 uint64_t last_update_timer; /* 0x268 */
840 uint64_t user_timer; /* 0x270 */
841 uint64_t system_timer; /* 0x278 */
842 uint64_t last_update_clock; /* 0x280 */
843 uint64_t steal_clock; /* 0x288 */
844 PSW return_mcck_psw; /* 0x290 */
845 uint8_t pad9[0xc00-0x2a0]; /* 0x2a0 */
846 /* System info area */
847 uint64_t save_area[16]; /* 0xc00 */
848 uint8_t pad10[0xd40-0xc80]; /* 0xc80 */
849 uint64_t kernel_stack; /* 0xd40 */
850 uint64_t thread_info; /* 0xd48 */
851 uint64_t async_stack; /* 0xd50 */
852 uint64_t kernel_asce; /* 0xd58 */
853 uint64_t user_asce; /* 0xd60 */
854 uint64_t panic_stack; /* 0xd68 */
855 uint64_t user_exec_asce; /* 0xd70 */
856 uint8_t pad11[0xdc0-0xd78]; /* 0xd78 */
857
858 /* SMP info area: defined by DJB */
859 uint64_t clock_comparator; /* 0xdc0 */
860 uint64_t ext_call_fast; /* 0xdc8 */
861 uint64_t percpu_offset; /* 0xdd0 */
862 uint64_t current_task; /* 0xdd8 */
863 uint32_t softirq_pending; /* 0xde0 */
864 uint32_t pad_0x0de4; /* 0xde4 */
865 uint64_t int_clock; /* 0xde8 */
866 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
867
868 /* 0xe00 is used as indicator for dump tools */
869 /* whether the kernel died with panic() or not */
870 uint32_t panic_magic; /* 0xe00 */
871
872 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
873
874 /* 64 bit extparam used for pfault, diag 250 etc */
875 uint64_t ext_params2; /* 0x11B8 */
876
877 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
878
879 /* System info area */
880
881 uint64_t floating_pt_save_area[16]; /* 0x1200 */
882 uint64_t gpregs_save_area[16]; /* 0x1280 */
883 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
884 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
885 uint32_t prefixreg_save_area; /* 0x1318 */
886 uint32_t fpt_creg_save_area; /* 0x131c */
887 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
888 uint32_t tod_progreg_save_area; /* 0x1324 */
889 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
890 uint32_t clock_comp_save_area[2]; /* 0x1330 */
891 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
892 uint32_t access_regs_save_area[16]; /* 0x1340 */
893 uint64_t cregs_save_area[16]; /* 0x1380 */
894
895 /* align to the top of the prefix area */
896
897 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
898 } QEMU_PACKED LowCore;
899
900 /* STSI */
901 #define STSI_LEVEL_MASK 0x00000000f0000000ULL
902 #define STSI_LEVEL_CURRENT 0x0000000000000000ULL
903 #define STSI_LEVEL_1 0x0000000010000000ULL
904 #define STSI_LEVEL_2 0x0000000020000000ULL
905 #define STSI_LEVEL_3 0x0000000030000000ULL
906 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
907 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL
908 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
909 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL
910
911 /* Basic Machine Configuration */
912 struct sysib_111 {
913 uint32_t res1[8];
914 uint8_t manuf[16];
915 uint8_t type[4];
916 uint8_t res2[12];
917 uint8_t model[16];
918 uint8_t sequence[16];
919 uint8_t plant[4];
920 uint8_t res3[156];
921 };
922
923 /* Basic Machine CPU */
924 struct sysib_121 {
925 uint32_t res1[80];
926 uint8_t sequence[16];
927 uint8_t plant[4];
928 uint8_t res2[2];
929 uint16_t cpu_addr;
930 uint8_t res3[152];
931 };
932
933 /* Basic Machine CPUs */
934 struct sysib_122 {
935 uint8_t res1[32];
936 uint32_t capability;
937 uint16_t total_cpus;
938 uint16_t active_cpus;
939 uint16_t standby_cpus;
940 uint16_t reserved_cpus;
941 uint16_t adjustments[2026];
942 };
943
944 /* LPAR CPU */
945 struct sysib_221 {
946 uint32_t res1[80];
947 uint8_t sequence[16];
948 uint8_t plant[4];
949 uint16_t cpu_id;
950 uint16_t cpu_addr;
951 uint8_t res3[152];
952 };
953
954 /* LPAR CPUs */
955 struct sysib_222 {
956 uint32_t res1[32];
957 uint16_t lpar_num;
958 uint8_t res2;
959 uint8_t lcpuc;
960 uint16_t total_cpus;
961 uint16_t conf_cpus;
962 uint16_t standby_cpus;
963 uint16_t reserved_cpus;
964 uint8_t name[8];
965 uint32_t caf;
966 uint8_t res3[16];
967 uint16_t dedicated_cpus;
968 uint16_t shared_cpus;
969 uint8_t res4[180];
970 };
971
972 /* VM CPUs */
973 struct sysib_322 {
974 uint8_t res1[31];
975 uint8_t count;
976 struct {
977 uint8_t res2[4];
978 uint16_t total_cpus;
979 uint16_t conf_cpus;
980 uint16_t standby_cpus;
981 uint16_t reserved_cpus;
982 uint8_t name[8];
983 uint32_t caf;
984 uint8_t cpi[16];
985 uint8_t res5[3];
986 uint8_t ext_name_encoding;
987 uint32_t res3;
988 uint8_t uuid[16];
989 } vm[8];
990 uint8_t res4[1504];
991 uint8_t ext_names[8][256];
992 };
993
994 /* MMU defines */
995 #define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
996 #define _ASCE_SUBSPACE 0x200 /* subspace group control */
997 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
998 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
999 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
1000 #define _ASCE_REAL_SPACE 0x20 /* real space control */
1001 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
1002 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */
1003 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */
1004 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */
1005 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
1006 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */
1007
1008 #define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
1009 #define _REGION_ENTRY_RO 0x200 /* region/segment protection bit */
1010 #define _REGION_ENTRY_TF 0xc0 /* region/segment table offset */
1011 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
1012 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
1013 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
1014 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
1015 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
1016 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */
1017
1018 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
1019 #define _SEGMENT_ENTRY_FC 0x400 /* format control */
1020 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
1021 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
1022
1023 #define _PAGE_RO 0x200 /* HW read-only bit */
1024 #define _PAGE_INVALID 0x400 /* HW invalid bit */
1025 #define _PAGE_RES0 0x800 /* bit must be zero */
1026
1027 #define SK_C (0x1 << 1)
1028 #define SK_R (0x1 << 2)
1029 #define SK_F (0x1 << 3)
1030 #define SK_ACC_MASK (0xf << 4)
1031
1032 /* SIGP order codes */
1033 #define SIGP_SENSE 0x01
1034 #define SIGP_EXTERNAL_CALL 0x02
1035 #define SIGP_EMERGENCY 0x03
1036 #define SIGP_START 0x04
1037 #define SIGP_STOP 0x05
1038 #define SIGP_RESTART 0x06
1039 #define SIGP_STOP_STORE_STATUS 0x09
1040 #define SIGP_INITIAL_CPU_RESET 0x0b
1041 #define SIGP_CPU_RESET 0x0c
1042 #define SIGP_SET_PREFIX 0x0d
1043 #define SIGP_STORE_STATUS_ADDR 0x0e
1044 #define SIGP_SET_ARCH 0x12
1045 #define SIGP_STORE_ADTL_STATUS 0x17
1046
1047 /* SIGP condition codes */
1048 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
1049 #define SIGP_CC_STATUS_STORED 1
1050 #define SIGP_CC_BUSY 2
1051 #define SIGP_CC_NOT_OPERATIONAL 3
1052
1053 /* SIGP status bits */
1054 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
1055 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL
1056 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
1057 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
1058 #define SIGP_STAT_STOPPED 0x00000040UL
1059 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
1060 #define SIGP_STAT_CHECK_STOP 0x00000010UL
1061 #define SIGP_STAT_INOPERATIVE 0x00000004UL
1062 #define SIGP_STAT_INVALID_ORDER 0x00000002UL
1063 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
1064
1065 /* SIGP SET ARCHITECTURE modes */
1066 #define SIGP_MODE_ESA_S390 0
1067 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
1068 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
1069
1070 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
1071 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
1072 target_ulong *raddr, int *flags, bool exc);
1073 int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
1074 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
1075 uint64_t vr);
1076 void s390_cpu_recompute_watchpoints(CPUState *cs);
1077
1078 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
1079 int len, bool is_write);
1080
1081 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
1082 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
1083 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
1084 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
1085 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
1086 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
1087
1088 /* The value of the TOD clock for 1.1.1970. */
1089 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
1090
1091 /* Converts ns to s390's clock format */
1092 static inline uint64_t time2tod(uint64_t ns) {
1093 return (ns << 9) / 125;
1094 }
1095
1096 /* Converts s390's clock format to ns */
1097 static inline uint64_t tod2time(uint64_t t) {
1098 return (t * 125) >> 9;
1099 }
1100
1101 /* from s390-virtio-ccw */
1102 #define MEM_SECTION_SIZE 0x10000000UL
1103 #define MAX_AVAIL_SLOTS 32
1104
1105 /* fpu_helper.c */
1106 uint32_t set_cc_nz_f32(float32 v);
1107 uint32_t set_cc_nz_f64(float64 v);
1108 uint32_t set_cc_nz_f128(float128 v);
1109
1110 /* misc_helper.c */
1111 #ifndef CONFIG_USER_ONLY
1112 int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3);
1113 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1114 #endif
1115 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1116 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1117 uintptr_t retaddr);
1118
1119 #ifdef CONFIG_KVM
1120 void kvm_s390_io_interrupt(uint16_t subchannel_id,
1121 uint16_t subchannel_nr, uint32_t io_int_parm,
1122 uint32_t io_int_word);
1123 void kvm_s390_crw_mchk(void);
1124 void kvm_s390_enable_css_support(S390CPU *cpu);
1125 int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1126 int vq, bool assign);
1127 int kvm_s390_cpu_restart(S390CPU *cpu);
1128 int kvm_s390_get_memslot_count(KVMState *s);
1129 void kvm_s390_cmma_reset(void);
1130 int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
1131 void kvm_s390_reset_vcpu(S390CPU *cpu);
1132 int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
1133 void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu);
1134 int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu);
1135 int kvm_s390_get_ri(void);
1136 void kvm_s390_crypto_reset(void);
1137 #else
1138 static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
1139 uint16_t subchannel_nr,
1140 uint32_t io_int_parm,
1141 uint32_t io_int_word)
1142 {
1143 }
1144 static inline void kvm_s390_crw_mchk(void)
1145 {
1146 }
1147 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1148 {
1149 }
1150 static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1151 uint32_t sch, int vq,
1152 bool assign)
1153 {
1154 return -ENOSYS;
1155 }
1156 static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1157 {
1158 return -ENOSYS;
1159 }
1160 static inline void kvm_s390_cmma_reset(void)
1161 {
1162 }
1163 static inline int kvm_s390_get_memslot_count(KVMState *s)
1164 {
1165 return MAX_AVAIL_SLOTS;
1166 }
1167 static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1168 {
1169 return -ENOSYS;
1170 }
1171 static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1172 {
1173 }
1174 static inline int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit,
1175 uint64_t *hw_limit)
1176 {
1177 return 0;
1178 }
1179 static inline void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu)
1180 {
1181 }
1182 static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
1183 {
1184 return 0;
1185 }
1186 static inline int kvm_s390_get_ri(void)
1187 {
1188 return 0;
1189 }
1190 static inline void kvm_s390_crypto_reset(void)
1191 {
1192 }
1193 #endif
1194
1195 static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
1196 {
1197 if (kvm_enabled()) {
1198 return kvm_s390_set_mem_limit(kvm_state, new_limit, hw_limit);
1199 }
1200 return 0;
1201 }
1202
1203 static inline void s390_cmma_reset(void)
1204 {
1205 if (kvm_enabled()) {
1206 kvm_s390_cmma_reset();
1207 }
1208 }
1209
1210 static inline int s390_cpu_restart(S390CPU *cpu)
1211 {
1212 if (kvm_enabled()) {
1213 return kvm_s390_cpu_restart(cpu);
1214 }
1215 return -ENOSYS;
1216 }
1217
1218 static inline int s390_get_memslot_count(KVMState *s)
1219 {
1220 if (kvm_enabled()) {
1221 return kvm_s390_get_memslot_count(s);
1222 } else {
1223 return MAX_AVAIL_SLOTS;
1224 }
1225 }
1226
1227 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1228 uint32_t io_int_parm, uint32_t io_int_word);
1229 void s390_crw_mchk(void);
1230
1231 static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1232 uint32_t sch_id, int vq,
1233 bool assign)
1234 {
1235 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1236 }
1237
1238 static inline void s390_crypto_reset(void)
1239 {
1240 if (kvm_enabled()) {
1241 kvm_s390_crypto_reset();
1242 }
1243 }
1244
1245 /* machine check interruption code */
1246
1247 /* subclasses */
1248 #define MCIC_SC_SD 0x8000000000000000ULL
1249 #define MCIC_SC_PD 0x4000000000000000ULL
1250 #define MCIC_SC_SR 0x2000000000000000ULL
1251 #define MCIC_SC_CD 0x0800000000000000ULL
1252 #define MCIC_SC_ED 0x0400000000000000ULL
1253 #define MCIC_SC_DG 0x0100000000000000ULL
1254 #define MCIC_SC_W 0x0080000000000000ULL
1255 #define MCIC_SC_CP 0x0040000000000000ULL
1256 #define MCIC_SC_SP 0x0020000000000000ULL
1257 #define MCIC_SC_CK 0x0010000000000000ULL
1258
1259 /* subclass modifiers */
1260 #define MCIC_SCM_B 0x0002000000000000ULL
1261 #define MCIC_SCM_DA 0x0000000020000000ULL
1262 #define MCIC_SCM_AP 0x0000000000080000ULL
1263
1264 /* storage errors */
1265 #define MCIC_SE_SE 0x0000800000000000ULL
1266 #define MCIC_SE_SC 0x0000400000000000ULL
1267 #define MCIC_SE_KE 0x0000200000000000ULL
1268 #define MCIC_SE_DS 0x0000100000000000ULL
1269 #define MCIC_SE_IE 0x0000000080000000ULL
1270
1271 /* validity bits */
1272 #define MCIC_VB_WP 0x0000080000000000ULL
1273 #define MCIC_VB_MS 0x0000040000000000ULL
1274 #define MCIC_VB_PM 0x0000020000000000ULL
1275 #define MCIC_VB_IA 0x0000010000000000ULL
1276 #define MCIC_VB_FA 0x0000008000000000ULL
1277 #define MCIC_VB_VR 0x0000004000000000ULL
1278 #define MCIC_VB_EC 0x0000002000000000ULL
1279 #define MCIC_VB_FP 0x0000001000000000ULL
1280 #define MCIC_VB_GR 0x0000000800000000ULL
1281 #define MCIC_VB_CR 0x0000000400000000ULL
1282 #define MCIC_VB_ST 0x0000000100000000ULL
1283 #define MCIC_VB_AR 0x0000000040000000ULL
1284 #define MCIC_VB_PR 0x0000000000200000ULL
1285 #define MCIC_VB_FC 0x0000000000100000ULL
1286 #define MCIC_VB_CT 0x0000000000020000ULL
1287 #define MCIC_VB_CC 0x0000000000010000ULL
1288
1289 #endif
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