target-s390x/helper.c

   1 /*
   2  *  S/390 helpers
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *  Copyright (c) 2011 Alexander Graf
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "cpu.h"
  22 #include "exec/gdbstub.h"
  23 #include "qemu/timer.h"
  24 #ifndef CONFIG_USER_ONLY
  25 #include "sysemu/sysemu.h"
  26 #endif
  27
  28 //#define DEBUG_S390
  29 //#define DEBUG_S390_PTE
  30 //#define DEBUG_S390_STDOUT
  31
  32 #ifdef DEBUG_S390
  33 #ifdef DEBUG_S390_STDOUT
  34 #define DPRINTF(fmt, ...) \
  35     do { fprintf(stderr, fmt, ## __VA_ARGS__); \
  36          qemu_log(fmt, ##__VA_ARGS__); } while (0)
  37 #else
  38 #define DPRINTF(fmt, ...) \
  39     do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
  40 #endif
  41 #else
  42 #define DPRINTF(fmt, ...) \
  43     do { } while (0)
  44 #endif
  45
  46 #ifdef DEBUG_S390_PTE
  47 #define PTE_DPRINTF DPRINTF
  48 #else
  49 #define PTE_DPRINTF(fmt, ...) \
  50     do { } while (0)
  51 #endif
  52
  53 #ifndef CONFIG_USER_ONLY
  54 void s390x_tod_timer(void *opaque)
  55 {
  56     S390CPU *cpu = opaque;
  57     CPUS390XState *env = &cpu->env;
  58
  59     env->pending_int |= INTERRUPT_TOD;
  60     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
  61 }
  62
  63 void s390x_cpu_timer(void *opaque)
  64 {
  65     S390CPU *cpu = opaque;
  66     CPUS390XState *env = &cpu->env;
  67
  68     env->pending_int |= INTERRUPT_CPUTIMER;
  69     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
  70 }
  71 #endif
  72
  73 S390CPU *cpu_s390x_init(const char *cpu_model)
  74 {
  75     S390CPU *cpu;
  76
  77     cpu = S390_CPU(object_new(TYPE_S390_CPU));
  78
  79     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
  80
  81     return cpu;
  82 }
  83
  84 #if defined(CONFIG_USER_ONLY)
  85
  86 void s390_cpu_do_interrupt(CPUState *cs)
  87 {
  88     S390CPU *cpu = S390_CPU(cs);
  89     CPUS390XState *env = &cpu->env;
  90
  91     env->exception_index = -1;
  92 }
  93
  94 int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong address,
  95                                int rw, int mmu_idx)
  96 {
  97     env->exception_index = EXCP_PGM;
  98     env->int_pgm_code = PGM_ADDRESSING;
  99     /* On real machines this value is dropped into LowMem.  Since this
 100        is userland, simply put this someplace that cpu_loop can find it.  */
 101     env->__excp_addr = address;
 102     return 1;
 103 }
 104
 105 #else /* !CONFIG_USER_ONLY */
 106
 107 /* Ensure to exit the TB after this call! */
 108 static void trigger_pgm_exception(CPUS390XState *env, uint32_t code,
 109                                   uint32_t ilen)
 110 {
 111     env->exception_index = EXCP_PGM;
 112     env->int_pgm_code = code;
 113     env->int_pgm_ilen = ilen;
 114 }
 115
 116 static int trans_bits(CPUS390XState *env, uint64_t mode)
 117 {
 118     int bits = 0;
 119
 120     switch (mode) {
 121     case PSW_ASC_PRIMARY:
 122         bits = 1;
 123         break;
 124     case PSW_ASC_SECONDARY:
 125         bits = 2;
 126         break;
 127     case PSW_ASC_HOME:
 128         bits = 3;
 129         break;
 130     default:
 131         cpu_abort(env, "unknown asc mode\n");
 132         break;
 133     }
 134
 135     return bits;
 136 }
 137
 138 static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
 139                                uint64_t mode)
 140 {
 141     int ilen = ILEN_LATER_INC;
 142     int bits = trans_bits(env, mode) | 4;
 143
 144     DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
 145
 146     stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
 147     trigger_pgm_exception(env, PGM_PROTECTION, ilen);
 148 }
 149
 150 static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
 151                                uint32_t type, uint64_t asc, int rw)
 152 {
 153     int ilen = ILEN_LATER;
 154     int bits = trans_bits(env, asc);
 155
 156     /* Code accesses have an undefined ilc.  */
 157     if (rw == 2) {
 158         ilen = 2;
 159     }
 160
 161     DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
 162
 163     stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
 164     trigger_pgm_exception(env, type, ilen);
 165 }
 166
 167 static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
 168                               uint64_t asc, uint64_t asce, int level,
 169                               target_ulong *raddr, int *flags, int rw)
 170 {
 171     CPUState *cs = ENV_GET_CPU(env);
 172     uint64_t offs = 0;
 173     uint64_t origin;
 174     uint64_t new_asce;
 175
 176     PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, asce);
 177
 178     if (((level != _ASCE_TYPE_SEGMENT) && (asce & _REGION_ENTRY_INV)) ||
 179         ((level == _ASCE_TYPE_SEGMENT) && (asce & _SEGMENT_ENTRY_INV))) {
 180         /* XXX different regions have different faults */
 181         DPRINTF("%s: invalid region\n", __func__);
 182         trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw);
 183         return -1;
 184     }
 185
 186     if ((level <= _ASCE_TYPE_MASK) && ((asce & _ASCE_TYPE_MASK) != level)) {
 187         trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
 188         return -1;
 189     }
 190
 191     if (asce & _ASCE_REAL_SPACE) {
 192         /* direct mapping */
 193
 194         *raddr = vaddr;
 195         return 0;
 196     }
 197
 198     origin = asce & _ASCE_ORIGIN;
 199
 200     switch (level) {
 201     case _ASCE_TYPE_REGION1 + 4:
 202         offs = (vaddr >> 50) & 0x3ff8;
 203         break;
 204     case _ASCE_TYPE_REGION1:
 205         offs = (vaddr >> 39) & 0x3ff8;
 206         break;
 207     case _ASCE_TYPE_REGION2:
 208         offs = (vaddr >> 28) & 0x3ff8;
 209         break;
 210     case _ASCE_TYPE_REGION3:
 211         offs = (vaddr >> 17) & 0x3ff8;
 212         break;
 213     case _ASCE_TYPE_SEGMENT:
 214         offs = (vaddr >> 9) & 0x07f8;
 215         origin = asce & _SEGMENT_ENTRY_ORIGIN;
 216         break;
 217     }
 218
 219     /* XXX region protection flags */
 220     /* *flags &= ~PAGE_WRITE */
 221
 222     new_asce = ldq_phys(cs->as, origin + offs);
 223     PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
 224                 __func__, origin, offs, new_asce);
 225
 226     if (level != _ASCE_TYPE_SEGMENT) {
 227         /* yet another region */
 228         return mmu_translate_asce(env, vaddr, asc, new_asce, level - 4, raddr,
 229                                   flags, rw);
 230     }
 231
 232     /* PTE */
 233     if (new_asce & _PAGE_INVALID) {
 234         DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, new_asce);
 235         trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw);
 236         return -1;
 237     }
 238
 239     if (new_asce & _PAGE_RO) {
 240         *flags &= ~PAGE_WRITE;
 241     }
 242
 243     *raddr = new_asce & _ASCE_ORIGIN;
 244
 245     PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, new_asce);
 246
 247     return 0;
 248 }
 249
 250 static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr,
 251                              uint64_t asc, target_ulong *raddr, int *flags,
 252                              int rw)
 253 {
 254     uint64_t asce = 0;
 255     int level, new_level;
 256     int r;
 257
 258     switch (asc) {
 259     case PSW_ASC_PRIMARY:
 260         PTE_DPRINTF("%s: asc=primary\n", __func__);
 261         asce = env->cregs[1];
 262         break;
 263     case PSW_ASC_SECONDARY:
 264         PTE_DPRINTF("%s: asc=secondary\n", __func__);
 265         asce = env->cregs[7];
 266         break;
 267     case PSW_ASC_HOME:
 268         PTE_DPRINTF("%s: asc=home\n", __func__);
 269         asce = env->cregs[13];
 270         break;
 271     }
 272
 273     switch (asce & _ASCE_TYPE_MASK) {
 274     case _ASCE_TYPE_REGION1:
 275         break;
 276     case _ASCE_TYPE_REGION2:
 277         if (vaddr & 0xffe0000000000000ULL) {
 278             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 279                     " 0xffe0000000000000ULL\n", __func__, vaddr);
 280             trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
 281             return -1;
 282         }
 283         break;
 284     case _ASCE_TYPE_REGION3:
 285         if (vaddr & 0xfffffc0000000000ULL) {
 286             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 287                     " 0xfffffc0000000000ULL\n", __func__, vaddr);
 288             trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
 289             return -1;
 290         }
 291         break;
 292     case _ASCE_TYPE_SEGMENT:
 293         if (vaddr & 0xffffffff80000000ULL) {
 294             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 295                     " 0xffffffff80000000ULL\n", __func__, vaddr);
 296             trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
 297             return -1;
 298         }
 299         break;
 300     }
 301
 302     /* fake level above current */
 303     level = asce & _ASCE_TYPE_MASK;
 304     new_level = level + 4;
 305     asce = (asce & ~_ASCE_TYPE_MASK) | (new_level & _ASCE_TYPE_MASK);
 306
 307     r = mmu_translate_asce(env, vaddr, asc, asce, new_level, raddr, flags, rw);
 308
 309     if ((rw == 1) && !(*flags & PAGE_WRITE)) {
 310         trigger_prot_fault(env, vaddr, asc);
 311         return -1;
 312     }
 313
 314     return r;
 315 }
 316
 317 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
 318                   target_ulong *raddr, int *flags)
 319 {
 320     int r = -1;
 321     uint8_t *sk;
 322
 323     *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 324     vaddr &= TARGET_PAGE_MASK;
 325
 326     if (!(env->psw.mask & PSW_MASK_DAT)) {
 327         *raddr = vaddr;
 328         r = 0;
 329         goto out;
 330     }
 331
 332     switch (asc) {
 333     case PSW_ASC_PRIMARY:
 334     case PSW_ASC_HOME:
 335         r = mmu_translate_asc(env, vaddr, asc, raddr, flags, rw);
 336         break;
 337     case PSW_ASC_SECONDARY:
 338         /*
 339          * Instruction: Primary
 340          * Data: Secondary
 341          */
 342         if (rw == 2) {
 343             r = mmu_translate_asc(env, vaddr, PSW_ASC_PRIMARY, raddr, flags,
 344                                   rw);
 345             *flags &= ~(PAGE_READ | PAGE_WRITE);
 346         } else {
 347             r = mmu_translate_asc(env, vaddr, PSW_ASC_SECONDARY, raddr, flags,
 348                                   rw);
 349             *flags &= ~(PAGE_EXEC);
 350         }
 351         break;
 352     case PSW_ASC_ACCREG:
 353     default:
 354         hw_error("guest switched to unknown asc mode\n");
 355         break;
 356     }
 357
 358  out:
 359     /* Convert real address -> absolute address */
 360     if (*raddr < 0x2000) {
 361         *raddr = *raddr + env->psa;
 362     }
 363
 364     if (*raddr <= ram_size) {
 365         sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE];
 366         if (*flags & PAGE_READ) {
 367             *sk |= SK_R;
 368         }
 369
 370         if (*flags & PAGE_WRITE) {
 371             *sk |= SK_C;
 372         }
 373     }
 374
 375     return r;
 376 }
 377
 378 int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong orig_vaddr,
 379                                int rw, int mmu_idx)
 380 {
 381     uint64_t asc = env->psw.mask & PSW_MASK_ASC;
 382     target_ulong vaddr, raddr;
 383     int prot;
 384
 385     DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d\n",
 386             __func__, orig_vaddr, rw, mmu_idx);
 387
 388     orig_vaddr &= TARGET_PAGE_MASK;
 389     vaddr = orig_vaddr;
 390
 391     /* 31-Bit mode */
 392     if (!(env->psw.mask & PSW_MASK_64)) {
 393         vaddr &= 0x7fffffff;
 394     }
 395
 396     if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot)) {
 397         /* Translation ended in exception */
 398         return 1;
 399     }
 400
 401     /* check out of RAM access */
 402     if (raddr > (ram_size + virtio_size)) {
 403         DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
 404                 (uint64_t)raddr, (uint64_t)ram_size);
 405         trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_LATER);
 406         return 1;
 407     }
 408
 409     DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__,
 410             (uint64_t)vaddr, (uint64_t)raddr, prot);
 411
 412     tlb_set_page(env, orig_vaddr, raddr, prot,
 413                  mmu_idx, TARGET_PAGE_SIZE);
 414
 415     return 0;
 416 }
 417
 418 hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
 419 {
 420     S390CPU *cpu = S390_CPU(cs);
 421     CPUS390XState *env = &cpu->env;
 422     target_ulong raddr;
 423     int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 424     int old_exc = env->exception_index;
 425     uint64_t asc = env->psw.mask & PSW_MASK_ASC;
 426
 427     /* 31-Bit mode */
 428     if (!(env->psw.mask & PSW_MASK_64)) {
 429         vaddr &= 0x7fffffff;
 430     }
 431
 432     mmu_translate(env, vaddr, 2, asc, &raddr, &prot);
 433     env->exception_index = old_exc;
 434
 435     return raddr;
 436 }
 437
 438 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
 439 {
 440     if (mask & PSW_MASK_WAIT) {
 441         S390CPU *cpu = s390_env_get_cpu(env);
 442         CPUState *cs = CPU(cpu);
 443         if (!(mask & (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK))) {
 444             if (s390_del_running_cpu(cpu) == 0) {
 445 #ifndef CONFIG_USER_ONLY
 446                 qemu_system_shutdown_request();
 447 #endif
 448             }
 449         }
 450         cs->halted = 1;
 451         env->exception_index = EXCP_HLT;
 452     }
 453
 454     env->psw.addr = addr;
 455     env->psw.mask = mask;
 456     env->cc_op = (mask >> 44) & 3;
 457 }
 458
 459 static uint64_t get_psw_mask(CPUS390XState *env)
 460 {
 461     uint64_t r;
 462
 463     env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr);
 464
 465     r = env->psw.mask;
 466     r &= ~PSW_MASK_CC;
 467     assert(!(env->cc_op & ~3));
 468     r |= (uint64_t)env->cc_op << 44;
 469
 470     return r;
 471 }
 472
 473 static LowCore *cpu_map_lowcore(CPUS390XState *env)
 474 {
 475     LowCore *lowcore;
 476     hwaddr len = sizeof(LowCore);
 477
 478     lowcore = cpu_physical_memory_map(env->psa, &len, 1);
 479
 480     if (len < sizeof(LowCore)) {
 481         cpu_abort(env, "Could not map lowcore\n");
 482     }
 483
 484     return lowcore;
 485 }
 486
 487 static void cpu_unmap_lowcore(LowCore *lowcore)
 488 {
 489     cpu_physical_memory_unmap(lowcore, sizeof(LowCore), 1, sizeof(LowCore));
 490 }
 491
 492 void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
 493                                    int is_write)
 494 {
 495     hwaddr start = addr;
 496
 497     /* Mind the prefix area. */
 498     if (addr < 8192) {
 499         /* Map the lowcore. */
 500         start += env->psa;
 501         *len = MIN(*len, 8192 - addr);
 502     } else if ((addr >= env->psa) && (addr < env->psa + 8192)) {
 503         /* Map the 0 page. */
 504         start -= env->psa;
 505         *len = MIN(*len, 8192 - start);
 506     }
 507
 508     return cpu_physical_memory_map(start, len, is_write);
 509 }
 510
 511 void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
 512                                     int is_write)
 513 {
 514     cpu_physical_memory_unmap(addr, len, is_write, len);
 515 }
 516
 517 static void do_svc_interrupt(CPUS390XState *env)
 518 {
 519     uint64_t mask, addr;
 520     LowCore *lowcore;
 521
 522     lowcore = cpu_map_lowcore(env);
 523
 524     lowcore->svc_code = cpu_to_be16(env->int_svc_code);
 525     lowcore->svc_ilen = cpu_to_be16(env->int_svc_ilen);
 526     lowcore->svc_old_psw.mask = cpu_to_be64(get_psw_mask(env));
 527     lowcore->svc_old_psw.addr = cpu_to_be64(env->psw.addr + env->int_svc_ilen);
 528     mask = be64_to_cpu(lowcore->svc_new_psw.mask);
 529     addr = be64_to_cpu(lowcore->svc_new_psw.addr);
 530
 531     cpu_unmap_lowcore(lowcore);
 532
 533     load_psw(env, mask, addr);
 534 }
 535
 536 static void do_program_interrupt(CPUS390XState *env)
 537 {
 538     uint64_t mask, addr;
 539     LowCore *lowcore;
 540     int ilen = env->int_pgm_ilen;
 541
 542     switch (ilen) {
 543     case ILEN_LATER:
 544         ilen = get_ilen(cpu_ldub_code(env, env->psw.addr));
 545         break;
 546     case ILEN_LATER_INC:
 547         ilen = get_ilen(cpu_ldub_code(env, env->psw.addr));
 548         env->psw.addr += ilen;
 549         break;
 550     default:
 551         assert(ilen == 2 || ilen == 4 || ilen == 6);
 552     }
 553
 554     qemu_log_mask(CPU_LOG_INT, "%s: code=0x%x ilen=%d\n",
 555                   __func__, env->int_pgm_code, ilen);
 556
 557     lowcore = cpu_map_lowcore(env);
 558
 559     lowcore->pgm_ilen = cpu_to_be16(ilen);
 560     lowcore->pgm_code = cpu_to_be16(env->int_pgm_code);
 561     lowcore->program_old_psw.mask = cpu_to_be64(get_psw_mask(env));
 562     lowcore->program_old_psw.addr = cpu_to_be64(env->psw.addr);
 563     mask = be64_to_cpu(lowcore->program_new_psw.mask);
 564     addr = be64_to_cpu(lowcore->program_new_psw.addr);
 565
 566     cpu_unmap_lowcore(lowcore);
 567
 568     DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __func__,
 569             env->int_pgm_code, ilen, env->psw.mask,
 570             env->psw.addr);
 571
 572     load_psw(env, mask, addr);
 573 }
 574
 575 #define VIRTIO_SUBCODE_64 0x0D00
 576
 577 static void do_ext_interrupt(CPUS390XState *env)
 578 {
 579     uint64_t mask, addr;
 580     LowCore *lowcore;
 581     ExtQueue *q;
 582
 583     if (!(env->psw.mask & PSW_MASK_EXT)) {
 584         cpu_abort(env, "Ext int w/o ext mask\n");
 585     }
 586
 587     if (env->ext_index < 0 || env->ext_index > MAX_EXT_QUEUE) {
 588         cpu_abort(env, "Ext queue overrun: %d\n", env->ext_index);
 589     }
 590
 591     q = &env->ext_queue[env->ext_index];
 592     lowcore = cpu_map_lowcore(env);
 593
 594     lowcore->ext_int_code = cpu_to_be16(q->code);
 595     lowcore->ext_params = cpu_to_be32(q->param);
 596     lowcore->ext_params2 = cpu_to_be64(q->param64);
 597     lowcore->external_old_psw.mask = cpu_to_be64(get_psw_mask(env));
 598     lowcore->external_old_psw.addr = cpu_to_be64(env->psw.addr);
 599     lowcore->cpu_addr = cpu_to_be16(env->cpu_num | VIRTIO_SUBCODE_64);
 600     mask = be64_to_cpu(lowcore->external_new_psw.mask);
 601     addr = be64_to_cpu(lowcore->external_new_psw.addr);
 602
 603     cpu_unmap_lowcore(lowcore);
 604
 605     env->ext_index--;
 606     if (env->ext_index == -1) {
 607         env->pending_int &= ~INTERRUPT_EXT;
 608     }
 609
 610     DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
 611             env->psw.mask, env->psw.addr);
 612
 613     load_psw(env, mask, addr);
 614 }
 615
 616 static void do_io_interrupt(CPUS390XState *env)
 617 {
 618     LowCore *lowcore;
 619     IOIntQueue *q;
 620     uint8_t isc;
 621     int disable = 1;
 622     int found = 0;
 623
 624     if (!(env->psw.mask & PSW_MASK_IO)) {
 625         cpu_abort(env, "I/O int w/o I/O mask\n");
 626     }
 627
 628     for (isc = 0; isc < ARRAY_SIZE(env->io_index); isc++) {
 629         uint64_t isc_bits;
 630
 631         if (env->io_index[isc] < 0) {
 632             continue;
 633         }
 634         if (env->io_index[isc] > MAX_IO_QUEUE) {
 635             cpu_abort(env, "I/O queue overrun for isc %d: %d\n",
 636                       isc, env->io_index[isc]);
 637         }
 638
 639         q = &env->io_queue[env->io_index[isc]][isc];
 640         isc_bits = ISC_TO_ISC_BITS(IO_INT_WORD_ISC(q->word));
 641         if (!(env->cregs[6] & isc_bits)) {
 642             disable = 0;
 643             continue;
 644         }
 645         if (!found) {
 646             uint64_t mask, addr;
 647
 648             found = 1;
 649             lowcore = cpu_map_lowcore(env);
 650
 651             lowcore->subchannel_id = cpu_to_be16(q->id);
 652             lowcore->subchannel_nr = cpu_to_be16(q->nr);
 653             lowcore->io_int_parm = cpu_to_be32(q->parm);
 654             lowcore->io_int_word = cpu_to_be32(q->word);
 655             lowcore->io_old_psw.mask = cpu_to_be64(get_psw_mask(env));
 656             lowcore->io_old_psw.addr = cpu_to_be64(env->psw.addr);
 657             mask = be64_to_cpu(lowcore->io_new_psw.mask);
 658             addr = be64_to_cpu(lowcore->io_new_psw.addr);
 659
 660             cpu_unmap_lowcore(lowcore);
 661
 662             env->io_index[isc]--;
 663
 664             DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
 665                     env->psw.mask, env->psw.addr);
 666             load_psw(env, mask, addr);
 667         }
 668         if (env->io_index[isc] >= 0) {
 669             disable = 0;
 670         }
 671         continue;
 672     }
 673
 674     if (disable) {
 675         env->pending_int &= ~INTERRUPT_IO;
 676     }
 677
 678 }
 679
 680 static void do_mchk_interrupt(CPUS390XState *env)
 681 {
 682     uint64_t mask, addr;
 683     LowCore *lowcore;
 684     MchkQueue *q;
 685     int i;
 686
 687     if (!(env->psw.mask & PSW_MASK_MCHECK)) {
 688         cpu_abort(env, "Machine check w/o mchk mask\n");
 689     }
 690
 691     if (env->mchk_index < 0 || env->mchk_index > MAX_MCHK_QUEUE) {
 692         cpu_abort(env, "Mchk queue overrun: %d\n", env->mchk_index);
 693     }
 694
 695     q = &env->mchk_queue[env->mchk_index];
 696
 697     if (q->type != 1) {
 698         /* Don't know how to handle this... */
 699         cpu_abort(env, "Unknown machine check type %d\n", q->type);
 700     }
 701     if (!(env->cregs[14] & (1 << 28))) {
 702         /* CRW machine checks disabled */
 703         return;
 704     }
 705
 706     lowcore = cpu_map_lowcore(env);
 707
 708     for (i = 0; i < 16; i++) {
 709         lowcore->floating_pt_save_area[i] = cpu_to_be64(env->fregs[i].ll);
 710         lowcore->gpregs_save_area[i] = cpu_to_be64(env->regs[i]);
 711         lowcore->access_regs_save_area[i] = cpu_to_be32(env->aregs[i]);
 712         lowcore->cregs_save_area[i] = cpu_to_be64(env->cregs[i]);
 713     }
 714     lowcore->prefixreg_save_area = cpu_to_be32(env->psa);
 715     lowcore->fpt_creg_save_area = cpu_to_be32(env->fpc);
 716     lowcore->tod_progreg_save_area = cpu_to_be32(env->todpr);
 717     lowcore->cpu_timer_save_area[0] = cpu_to_be32(env->cputm >> 32);
 718     lowcore->cpu_timer_save_area[1] = cpu_to_be32((uint32_t)env->cputm);
 719     lowcore->clock_comp_save_area[0] = cpu_to_be32(env->ckc >> 32);
 720     lowcore->clock_comp_save_area[1] = cpu_to_be32((uint32_t)env->ckc);
 721
 722     lowcore->mcck_interruption_code[0] = cpu_to_be32(0x00400f1d);
 723     lowcore->mcck_interruption_code[1] = cpu_to_be32(0x40330000);
 724     lowcore->mcck_old_psw.mask = cpu_to_be64(get_psw_mask(env));
 725     lowcore->mcck_old_psw.addr = cpu_to_be64(env->psw.addr);
 726     mask = be64_to_cpu(lowcore->mcck_new_psw.mask);
 727     addr = be64_to_cpu(lowcore->mcck_new_psw.addr);
 728
 729     cpu_unmap_lowcore(lowcore);
 730
 731     env->mchk_index--;
 732     if (env->mchk_index == -1) {
 733         env->pending_int &= ~INTERRUPT_MCHK;
 734     }
 735
 736     DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
 737             env->psw.mask, env->psw.addr);
 738
 739     load_psw(env, mask, addr);
 740 }
 741
 742 void s390_cpu_do_interrupt(CPUState *cs)
 743 {
 744     S390CPU *cpu = S390_CPU(cs);
 745     CPUS390XState *env = &cpu->env;
 746
 747     qemu_log_mask(CPU_LOG_INT, "%s: %d at pc=%" PRIx64 "\n",
 748                   __func__, env->exception_index, env->psw.addr);
 749
 750     s390_add_running_cpu(cpu);
 751     /* handle machine checks */
 752     if ((env->psw.mask & PSW_MASK_MCHECK) &&
 753         (env->exception_index == -1)) {
 754         if (env->pending_int & INTERRUPT_MCHK) {
 755             env->exception_index = EXCP_MCHK;
 756         }
 757     }
 758     /* handle external interrupts */
 759     if ((env->psw.mask & PSW_MASK_EXT) &&
 760         env->exception_index == -1) {
 761         if (env->pending_int & INTERRUPT_EXT) {
 762             /* code is already in env */
 763             env->exception_index = EXCP_EXT;
 764         } else if (env->pending_int & INTERRUPT_TOD) {
 765             cpu_inject_ext(cpu, 0x1004, 0, 0);
 766             env->exception_index = EXCP_EXT;
 767             env->pending_int &= ~INTERRUPT_EXT;
 768             env->pending_int &= ~INTERRUPT_TOD;
 769         } else if (env->pending_int & INTERRUPT_CPUTIMER) {
 770             cpu_inject_ext(cpu, 0x1005, 0, 0);
 771             env->exception_index = EXCP_EXT;
 772             env->pending_int &= ~INTERRUPT_EXT;
 773             env->pending_int &= ~INTERRUPT_TOD;
 774         }
 775     }
 776     /* handle I/O interrupts */
 777     if ((env->psw.mask & PSW_MASK_IO) &&
 778         (env->exception_index == -1)) {
 779         if (env->pending_int & INTERRUPT_IO) {
 780             env->exception_index = EXCP_IO;
 781         }
 782     }
 783
 784     switch (env->exception_index) {
 785     case EXCP_PGM:
 786         do_program_interrupt(env);
 787         break;
 788     case EXCP_SVC:
 789         do_svc_interrupt(env);
 790         break;
 791     case EXCP_EXT:
 792         do_ext_interrupt(env);
 793         break;
 794     case EXCP_IO:
 795         do_io_interrupt(env);
 796         break;
 797     case EXCP_MCHK:
 798         do_mchk_interrupt(env);
 799         break;
 800     }
 801     env->exception_index = -1;
 802
 803     if (!env->pending_int) {
 804         cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
 805     }
 806 }
 807
 808 #endif /* CONFIG_USER_ONLY */