target-s390x/mmu_helper.c

   1 /*
   2  * S390x MMU related functions
   3  *
   4  * Copyright (c) 2011 Alexander Graf
   5  * Copyright (c) 2015 Thomas Huth, IBM Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include "cpu.h"
  19
  20 /* #define DEBUG_S390 */
  21 /* #define DEBUG_S390_PTE */
  22 /* #define DEBUG_S390_STDOUT */
  23
  24 #ifdef DEBUG_S390
  25 #ifdef DEBUG_S390_STDOUT
  26 #define DPRINTF(fmt, ...) \
  27     do { fprintf(stderr, fmt, ## __VA_ARGS__); \
  28          qemu_log(fmt, ##__VA_ARGS__); } while (0)
  29 #else
  30 #define DPRINTF(fmt, ...) \
  31     do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
  32 #endif
  33 #else
  34 #define DPRINTF(fmt, ...) \
  35     do { } while (0)
  36 #endif
  37
  38 #ifdef DEBUG_S390_PTE
  39 #define PTE_DPRINTF DPRINTF
  40 #else
  41 #define PTE_DPRINTF(fmt, ...) \
  42     do { } while (0)
  43 #endif
  44
  45 /* Fetch/store bits in the translation exception code: */
  46 #define FS_READ  0x800
  47 #define FS_WRITE 0x400
  48
  49 static void trigger_access_exception(CPUS390XState *env, uint32_t type,
  50                                      uint32_t ilen, uint64_t tec)
  51 {
  52     S390CPU *cpu = s390_env_get_cpu(env);
  53
  54     if (kvm_enabled()) {
  55         kvm_s390_access_exception(cpu, type, tec);
  56     } else {
  57         CPUState *cs = CPU(cpu);
  58         stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec);
  59         trigger_pgm_exception(env, type, ilen);
  60     }
  61 }
  62
  63 static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
  64                                uint64_t asc, int rw, bool exc)
  65 {
  66     uint64_t tec;
  67
  68     tec = vaddr | (rw == 1 ? FS_WRITE : FS_READ) | 4 | asc >> 46;
  69
  70     DPRINTF("%s: trans_exc_code=%016" PRIx64 "\n", __func__, tec);
  71
  72     if (!exc) {
  73         return;
  74     }
  75
  76     trigger_access_exception(env, PGM_PROTECTION, ILEN_LATER_INC, tec);
  77 }
  78
  79 static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
  80                                uint32_t type, uint64_t asc, int rw, bool exc)
  81 {
  82     int ilen = ILEN_LATER;
  83     uint64_t tec;
  84
  85     tec = vaddr | (rw == 1 ? FS_WRITE : FS_READ) | asc >> 46;
  86
  87     DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
  88
  89     if (!exc) {
  90         return;
  91     }
  92
  93     /* Code accesses have an undefined ilc.  */
  94     if (rw == 2) {
  95         ilen = 2;
  96     }
  97
  98     trigger_access_exception(env, type, ilen, tec);
  99 }
 100
 101 /**
 102  * Translate real address to absolute (= physical)
 103  * address by taking care of the prefix mapping.
 104  */
 105 static target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr)
 106 {
 107     if (raddr < 0x2000) {
 108         return raddr + env->psa;    /* Map the lowcore. */
 109     } else if (raddr >= env->psa && raddr < env->psa + 0x2000) {
 110         return raddr - env->psa;    /* Map the 0 page. */
 111     }
 112     return raddr;
 113 }
 114
 115 /* Decode page table entry (normal 4KB page) */
 116 static int mmu_translate_pte(CPUS390XState *env, target_ulong vaddr,
 117                              uint64_t asc, uint64_t pt_entry,
 118                              target_ulong *raddr, int *flags, int rw, bool exc)
 119 {
 120     if (pt_entry & _PAGE_INVALID) {
 121         DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, pt_entry);
 122         trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw, exc);
 123         return -1;
 124     }
 125     if (pt_entry & _PAGE_RES0) {
 126         trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw, exc);
 127         return -1;
 128     }
 129     if (pt_entry & _PAGE_RO) {
 130         *flags &= ~PAGE_WRITE;
 131     }
 132
 133     *raddr = pt_entry & _ASCE_ORIGIN;
 134
 135     PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, pt_entry);
 136
 137     return 0;
 138 }
 139
 140 #define VADDR_PX    0xff000         /* Page index bits */
 141
 142 /* Decode segment table entry */
 143 static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr,
 144                                  uint64_t asc, uint64_t st_entry,
 145                                  target_ulong *raddr, int *flags, int rw,
 146                                  bool exc)
 147 {
 148     CPUState *cs = CPU(s390_env_get_cpu(env));
 149     uint64_t origin, offs, pt_entry;
 150
 151     if (st_entry & _SEGMENT_ENTRY_RO) {
 152         *flags &= ~PAGE_WRITE;
 153     }
 154
 155     if ((st_entry & _SEGMENT_ENTRY_FC) && (env->cregs[0] & CR0_EDAT)) {
 156         /* Decode EDAT1 segment frame absolute address (1MB page) */
 157         *raddr = (st_entry & 0xfffffffffff00000ULL) | (vaddr & 0xfffff);
 158         PTE_DPRINTF("%s: SEG=0x%" PRIx64 "\n", __func__, st_entry);
 159         return 0;
 160     }
 161
 162     /* Look up 4KB page entry */
 163     origin = st_entry & _SEGMENT_ENTRY_ORIGIN;
 164     offs  = (vaddr & VADDR_PX) >> 9;
 165     pt_entry = ldq_phys(cs->as, origin + offs);
 166     PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
 167                 __func__, origin, offs, pt_entry);
 168     return mmu_translate_pte(env, vaddr, asc, pt_entry, raddr, flags, rw, exc);
 169 }
 170
 171 /* Decode region table entries */
 172 static int mmu_translate_region(CPUS390XState *env, target_ulong vaddr,
 173                                 uint64_t asc, uint64_t entry, int level,
 174                                 target_ulong *raddr, int *flags, int rw,
 175                                 bool exc)
 176 {
 177     CPUState *cs = CPU(s390_env_get_cpu(env));
 178     uint64_t origin, offs, new_entry;
 179     const int pchks[4] = {
 180         PGM_SEGMENT_TRANS, PGM_REG_THIRD_TRANS,
 181         PGM_REG_SEC_TRANS, PGM_REG_FIRST_TRANS
 182     };
 183
 184     PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, entry);
 185
 186     origin = entry & _REGION_ENTRY_ORIGIN;
 187     offs = (vaddr >> (17 + 11 * level / 4)) & 0x3ff8;
 188
 189     new_entry = ldq_phys(cs->as, origin + offs);
 190     PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
 191                 __func__, origin, offs, new_entry);
 192
 193     if ((new_entry & _REGION_ENTRY_INV) != 0) {
 194         DPRINTF("%s: invalid region\n", __func__);
 195         trigger_page_fault(env, vaddr, pchks[level / 4], asc, rw, exc);
 196         return -1;
 197     }
 198
 199     if ((new_entry & _REGION_ENTRY_TYPE_MASK) != level) {
 200         trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw, exc);
 201         return -1;
 202     }
 203
 204     if (level == _ASCE_TYPE_SEGMENT) {
 205         return mmu_translate_segment(env, vaddr, asc, new_entry, raddr, flags,
 206                                      rw, exc);
 207     }
 208
 209     /* Check region table offset and length */
 210     offs = (vaddr >> (28 + 11 * (level - 4) / 4)) & 3;
 211     if (offs < ((new_entry & _REGION_ENTRY_TF) >> 6)
 212         || offs > (new_entry & _REGION_ENTRY_LENGTH)) {
 213         DPRINTF("%s: invalid offset or len (%lx)\n", __func__, new_entry);
 214         trigger_page_fault(env, vaddr, pchks[level / 4 - 1], asc, rw, exc);
 215         return -1;
 216     }
 217
 218     if ((env->cregs[0] & CR0_EDAT) && (new_entry & _REGION_ENTRY_RO)) {
 219         *flags &= ~PAGE_WRITE;
 220     }
 221
 222     /* yet another region */
 223     return mmu_translate_region(env, vaddr, asc, new_entry, level - 4,
 224                                 raddr, flags, rw, exc);
 225 }
 226
 227 static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
 228                               uint64_t asc, uint64_t asce, target_ulong *raddr,
 229                               int *flags, int rw, bool exc)
 230 {
 231     int level;
 232     int r;
 233
 234     if (asce & _ASCE_REAL_SPACE) {
 235         /* direct mapping */
 236         *raddr = vaddr;
 237         return 0;
 238     }
 239
 240     level = asce & _ASCE_TYPE_MASK;
 241     switch (level) {
 242     case _ASCE_TYPE_REGION1:
 243         if ((vaddr >> 62) > (asce & _ASCE_TABLE_LENGTH)) {
 244             trigger_page_fault(env, vaddr, PGM_REG_FIRST_TRANS, asc, rw, exc);
 245             return -1;
 246         }
 247         break;
 248     case _ASCE_TYPE_REGION2:
 249         if (vaddr & 0xffe0000000000000ULL) {
 250             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 251                     " 0xffe0000000000000ULL\n", __func__, vaddr);
 252             trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
 253             return -1;
 254         }
 255         if ((vaddr >> 51 & 3) > (asce & _ASCE_TABLE_LENGTH)) {
 256             trigger_page_fault(env, vaddr, PGM_REG_SEC_TRANS, asc, rw, exc);
 257             return -1;
 258         }
 259         break;
 260     case _ASCE_TYPE_REGION3:
 261         if (vaddr & 0xfffffc0000000000ULL) {
 262             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 263                     " 0xfffffc0000000000ULL\n", __func__, vaddr);
 264             trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
 265             return -1;
 266         }
 267         if ((vaddr >> 40 & 3) > (asce & _ASCE_TABLE_LENGTH)) {
 268             trigger_page_fault(env, vaddr, PGM_REG_THIRD_TRANS, asc, rw, exc);
 269             return -1;
 270         }
 271         break;
 272     case _ASCE_TYPE_SEGMENT:
 273         if (vaddr & 0xffffffff80000000ULL) {
 274             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 275                     " 0xffffffff80000000ULL\n", __func__, vaddr);
 276             trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
 277             return -1;
 278         }
 279         if ((vaddr >> 29 & 3) > (asce & _ASCE_TABLE_LENGTH)) {
 280             trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw, exc);
 281             return -1;
 282         }
 283         break;
 284     }
 285
 286     r = mmu_translate_region(env, vaddr, asc, asce, level, raddr, flags, rw,
 287                              exc);
 288     if ((rw == 1) && !(*flags & PAGE_WRITE)) {
 289         trigger_prot_fault(env, vaddr, asc, rw, exc);
 290         return -1;
 291     }
 292
 293     return r;
 294 }
 295
 296 /**
 297  * Translate a virtual (logical) address into a physical (absolute) address.
 298  * @param vaddr  the virtual address
 299  * @param rw     0 = read, 1 = write, 2 = code fetch
 300  * @param asc    address space control (one of the PSW_ASC_* modes)
 301  * @param raddr  the translated address is stored to this pointer
 302  * @param flags  the PAGE_READ/WRITE/EXEC flags are stored to this pointer
 303  * @param exc    true = inject a program check if a fault occured
 304  * @return       0 if the translation was successfull, -1 if a fault occured
 305  */
 306 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
 307                   target_ulong *raddr, int *flags, bool exc)
 308 {
 309     int r = -1;
 310     uint8_t *sk;
 311
 312     *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 313     vaddr &= TARGET_PAGE_MASK;
 314
 315     if (!(env->psw.mask & PSW_MASK_DAT)) {
 316         *raddr = vaddr;
 317         r = 0;
 318         goto out;
 319     }
 320
 321     switch (asc) {
 322     case PSW_ASC_PRIMARY:
 323         PTE_DPRINTF("%s: asc=primary\n", __func__);
 324         r = mmu_translate_asce(env, vaddr, asc, env->cregs[1], raddr, flags,
 325                                rw, exc);
 326         break;
 327     case PSW_ASC_HOME:
 328         PTE_DPRINTF("%s: asc=home\n", __func__);
 329         r = mmu_translate_asce(env, vaddr, asc, env->cregs[13], raddr, flags,
 330                                rw, exc);
 331         break;
 332     case PSW_ASC_SECONDARY:
 333         PTE_DPRINTF("%s: asc=secondary\n", __func__);
 334         /*
 335          * Instruction: Primary
 336          * Data: Secondary
 337          */
 338         if (rw == 2) {
 339             r = mmu_translate_asce(env, vaddr, PSW_ASC_PRIMARY, env->cregs[1],
 340                                    raddr, flags, rw, exc);
 341             *flags &= ~(PAGE_READ | PAGE_WRITE);
 342         } else {
 343             r = mmu_translate_asce(env, vaddr, PSW_ASC_SECONDARY, env->cregs[7],
 344                                    raddr, flags, rw, exc);
 345             *flags &= ~(PAGE_EXEC);
 346         }
 347         break;
 348     case PSW_ASC_ACCREG:
 349     default:
 350         hw_error("guest switched to unknown asc mode\n");
 351         break;
 352     }
 353
 354  out:
 355     /* Convert real address -> absolute address */
 356     *raddr = mmu_real2abs(env, *raddr);
 357
 358     if (*raddr <= ram_size) {
 359         sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE];
 360         if (*flags & PAGE_READ) {
 361             *sk |= SK_R;
 362         }
 363
 364         if (*flags & PAGE_WRITE) {
 365             *sk |= SK_C;
 366         }
 367     }
 368
 369     return r;
 370 }