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target-s390: Implement COMPARE AND TRAP
[mirror_qemu.git] / target-s390x / translate.c
1 /*
2 * S/390 translation
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* #define DEBUG_INLINE_BRANCHES */
22 #define S390X_DEBUG_DISAS
23 /* #define S390X_DEBUG_DISAS_VERBOSE */
24
25 #ifdef S390X_DEBUG_DISAS_VERBOSE
26 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
27 #else
28 # define LOG_DISAS(...) do { } while (0)
29 #endif
30
31 #include "cpu.h"
32 #include "disas/disas.h"
33 #include "tcg-op.h"
34 #include "qemu/log.h"
35 #include "qemu/host-utils.h"
36
37 /* global register indexes */
38 static TCGv_ptr cpu_env;
39
40 #include "exec/gen-icount.h"
41 #include "helper.h"
42 #define GEN_HELPER 1
43 #include "helper.h"
44
45
46 /* Information that (most) every instruction needs to manipulate. */
47 typedef struct DisasContext DisasContext;
48 typedef struct DisasInsn DisasInsn;
49 typedef struct DisasFields DisasFields;
50
51 struct DisasContext {
52 struct TranslationBlock *tb;
53 const DisasInsn *insn;
54 DisasFields *fields;
55 uint64_t pc, next_pc;
56 enum cc_op cc_op;
57 bool singlestep_enabled;
58 };
59
60 /* Information carried about a condition to be evaluated. */
61 typedef struct {
62 TCGCond cond:8;
63 bool is_64;
64 bool g1;
65 bool g2;
66 union {
67 struct { TCGv_i64 a, b; } s64;
68 struct { TCGv_i32 a, b; } s32;
69 } u;
70 } DisasCompare;
71
72 #define DISAS_EXCP 4
73
74 #ifdef DEBUG_INLINE_BRANCHES
75 static uint64_t inline_branch_hit[CC_OP_MAX];
76 static uint64_t inline_branch_miss[CC_OP_MAX];
77 #endif
78
79 static uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
80 {
81 if (!(s->tb->flags & FLAG_MASK_64)) {
82 if (s->tb->flags & FLAG_MASK_32) {
83 return pc | 0x80000000;
84 }
85 }
86 return pc;
87 }
88
89 void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
90 int flags)
91 {
92 int i;
93
94 if (env->cc_op > 3) {
95 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
96 env->psw.mask, env->psw.addr, cc_name(env->cc_op));
97 } else {
98 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
99 env->psw.mask, env->psw.addr, env->cc_op);
100 }
101
102 for (i = 0; i < 16; i++) {
103 cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
104 if ((i % 4) == 3) {
105 cpu_fprintf(f, "\n");
106 } else {
107 cpu_fprintf(f, " ");
108 }
109 }
110
111 for (i = 0; i < 16; i++) {
112 cpu_fprintf(f, "F%02d=%016" PRIx64, i, env->fregs[i].ll);
113 if ((i % 4) == 3) {
114 cpu_fprintf(f, "\n");
115 } else {
116 cpu_fprintf(f, " ");
117 }
118 }
119
120 #ifndef CONFIG_USER_ONLY
121 for (i = 0; i < 16; i++) {
122 cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
123 if ((i % 4) == 3) {
124 cpu_fprintf(f, "\n");
125 } else {
126 cpu_fprintf(f, " ");
127 }
128 }
129 #endif
130
131 #ifdef DEBUG_INLINE_BRANCHES
132 for (i = 0; i < CC_OP_MAX; i++) {
133 cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
134 inline_branch_miss[i], inline_branch_hit[i]);
135 }
136 #endif
137
138 cpu_fprintf(f, "\n");
139 }
140
141 static TCGv_i64 psw_addr;
142 static TCGv_i64 psw_mask;
143
144 static TCGv_i32 cc_op;
145 static TCGv_i64 cc_src;
146 static TCGv_i64 cc_dst;
147 static TCGv_i64 cc_vr;
148
149 static char cpu_reg_names[32][4];
150 static TCGv_i64 regs[16];
151 static TCGv_i64 fregs[16];
152
153 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
154
155 void s390x_translate_init(void)
156 {
157 int i;
158
159 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
160 psw_addr = tcg_global_mem_new_i64(TCG_AREG0,
161 offsetof(CPUS390XState, psw.addr),
162 "psw_addr");
163 psw_mask = tcg_global_mem_new_i64(TCG_AREG0,
164 offsetof(CPUS390XState, psw.mask),
165 "psw_mask");
166
167 cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUS390XState, cc_op),
168 "cc_op");
169 cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_src),
170 "cc_src");
171 cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_dst),
172 "cc_dst");
173 cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_vr),
174 "cc_vr");
175
176 for (i = 0; i < 16; i++) {
177 snprintf(cpu_reg_names[i], sizeof(cpu_reg_names[0]), "r%d", i);
178 regs[i] = tcg_global_mem_new(TCG_AREG0,
179 offsetof(CPUS390XState, regs[i]),
180 cpu_reg_names[i]);
181 }
182
183 for (i = 0; i < 16; i++) {
184 snprintf(cpu_reg_names[i + 16], sizeof(cpu_reg_names[0]), "f%d", i);
185 fregs[i] = tcg_global_mem_new(TCG_AREG0,
186 offsetof(CPUS390XState, fregs[i].d),
187 cpu_reg_names[i + 16]);
188 }
189
190 /* register helpers */
191 #define GEN_HELPER 2
192 #include "helper.h"
193 }
194
195 static TCGv_i64 load_reg(int reg)
196 {
197 TCGv_i64 r = tcg_temp_new_i64();
198 tcg_gen_mov_i64(r, regs[reg]);
199 return r;
200 }
201
202 static TCGv_i64 load_freg32_i64(int reg)
203 {
204 TCGv_i64 r = tcg_temp_new_i64();
205 tcg_gen_shri_i64(r, fregs[reg], 32);
206 return r;
207 }
208
209 static void store_reg(int reg, TCGv_i64 v)
210 {
211 tcg_gen_mov_i64(regs[reg], v);
212 }
213
214 static void store_freg(int reg, TCGv_i64 v)
215 {
216 tcg_gen_mov_i64(fregs[reg], v);
217 }
218
219 static void store_reg32_i64(int reg, TCGv_i64 v)
220 {
221 /* 32 bit register writes keep the upper half */
222 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
223 }
224
225 static void store_reg32h_i64(int reg, TCGv_i64 v)
226 {
227 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 32, 32);
228 }
229
230 static void store_freg32_i64(int reg, TCGv_i64 v)
231 {
232 tcg_gen_deposit_i64(fregs[reg], fregs[reg], v, 32, 32);
233 }
234
235 static void return_low128(TCGv_i64 dest)
236 {
237 tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl));
238 }
239
240 static void update_psw_addr(DisasContext *s)
241 {
242 /* psw.addr */
243 tcg_gen_movi_i64(psw_addr, s->pc);
244 }
245
246 static void update_cc_op(DisasContext *s)
247 {
248 if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) {
249 tcg_gen_movi_i32(cc_op, s->cc_op);
250 }
251 }
252
253 static void potential_page_fault(DisasContext *s)
254 {
255 update_psw_addr(s);
256 update_cc_op(s);
257 }
258
259 static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
260 {
261 return (uint64_t)cpu_lduw_code(env, pc);
262 }
263
264 static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
265 {
266 return (uint64_t)(uint32_t)cpu_ldl_code(env, pc);
267 }
268
269 static inline uint64_t ld_code6(CPUS390XState *env, uint64_t pc)
270 {
271 return (ld_code2(env, pc) << 32) | ld_code4(env, pc + 2);
272 }
273
274 static int get_mem_index(DisasContext *s)
275 {
276 switch (s->tb->flags & FLAG_MASK_ASC) {
277 case PSW_ASC_PRIMARY >> 32:
278 return 0;
279 case PSW_ASC_SECONDARY >> 32:
280 return 1;
281 case PSW_ASC_HOME >> 32:
282 return 2;
283 default:
284 tcg_abort();
285 break;
286 }
287 }
288
289 static void gen_exception(int excp)
290 {
291 TCGv_i32 tmp = tcg_const_i32(excp);
292 gen_helper_exception(cpu_env, tmp);
293 tcg_temp_free_i32(tmp);
294 }
295
296 static void gen_program_exception(DisasContext *s, int code)
297 {
298 TCGv_i32 tmp;
299
300 /* Remember what pgm exeption this was. */
301 tmp = tcg_const_i32(code);
302 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
303 tcg_temp_free_i32(tmp);
304
305 tmp = tcg_const_i32(s->next_pc - s->pc);
306 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen));
307 tcg_temp_free_i32(tmp);
308
309 /* Advance past instruction. */
310 s->pc = s->next_pc;
311 update_psw_addr(s);
312
313 /* Save off cc. */
314 update_cc_op(s);
315
316 /* Trigger exception. */
317 gen_exception(EXCP_PGM);
318 }
319
320 static inline void gen_illegal_opcode(DisasContext *s)
321 {
322 gen_program_exception(s, PGM_SPECIFICATION);
323 }
324
325 static inline void check_privileged(DisasContext *s)
326 {
327 if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
328 gen_program_exception(s, PGM_PRIVILEGED);
329 }
330 }
331
332 static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
333 {
334 TCGv_i64 tmp;
335
336 /* 31-bitify the immediate part; register contents are dealt with below */
337 if (!(s->tb->flags & FLAG_MASK_64)) {
338 d2 &= 0x7fffffffUL;
339 }
340
341 if (x2) {
342 if (d2) {
343 tmp = tcg_const_i64(d2);
344 tcg_gen_add_i64(tmp, tmp, regs[x2]);
345 } else {
346 tmp = load_reg(x2);
347 }
348 if (b2) {
349 tcg_gen_add_i64(tmp, tmp, regs[b2]);
350 }
351 } else if (b2) {
352 if (d2) {
353 tmp = tcg_const_i64(d2);
354 tcg_gen_add_i64(tmp, tmp, regs[b2]);
355 } else {
356 tmp = load_reg(b2);
357 }
358 } else {
359 tmp = tcg_const_i64(d2);
360 }
361
362 /* 31-bit mode mask if there are values loaded from registers */
363 if (!(s->tb->flags & FLAG_MASK_64) && (x2 || b2)) {
364 tcg_gen_andi_i64(tmp, tmp, 0x7fffffffUL);
365 }
366
367 return tmp;
368 }
369
370 static inline void gen_op_movi_cc(DisasContext *s, uint32_t val)
371 {
372 s->cc_op = CC_OP_CONST0 + val;
373 }
374
375 static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst)
376 {
377 tcg_gen_discard_i64(cc_src);
378 tcg_gen_mov_i64(cc_dst, dst);
379 tcg_gen_discard_i64(cc_vr);
380 s->cc_op = op;
381 }
382
383 static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
384 TCGv_i64 dst)
385 {
386 tcg_gen_mov_i64(cc_src, src);
387 tcg_gen_mov_i64(cc_dst, dst);
388 tcg_gen_discard_i64(cc_vr);
389 s->cc_op = op;
390 }
391
392 static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
393 TCGv_i64 dst, TCGv_i64 vr)
394 {
395 tcg_gen_mov_i64(cc_src, src);
396 tcg_gen_mov_i64(cc_dst, dst);
397 tcg_gen_mov_i64(cc_vr, vr);
398 s->cc_op = op;
399 }
400
401 static void set_cc_nz_u64(DisasContext *s, TCGv_i64 val)
402 {
403 gen_op_update1_cc_i64(s, CC_OP_NZ, val);
404 }
405
406 static void gen_set_cc_nz_f32(DisasContext *s, TCGv_i64 val)
407 {
408 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, val);
409 }
410
411 static void gen_set_cc_nz_f64(DisasContext *s, TCGv_i64 val)
412 {
413 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, val);
414 }
415
416 static void gen_set_cc_nz_f128(DisasContext *s, TCGv_i64 vh, TCGv_i64 vl)
417 {
418 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, vh, vl);
419 }
420
421 /* CC value is in env->cc_op */
422 static void set_cc_static(DisasContext *s)
423 {
424 tcg_gen_discard_i64(cc_src);
425 tcg_gen_discard_i64(cc_dst);
426 tcg_gen_discard_i64(cc_vr);
427 s->cc_op = CC_OP_STATIC;
428 }
429
430 /* calculates cc into cc_op */
431 static void gen_op_calc_cc(DisasContext *s)
432 {
433 TCGv_i32 local_cc_op;
434 TCGv_i64 dummy;
435
436 TCGV_UNUSED_I32(local_cc_op);
437 TCGV_UNUSED_I64(dummy);
438 switch (s->cc_op) {
439 default:
440 dummy = tcg_const_i64(0);
441 /* FALLTHRU */
442 case CC_OP_ADD_64:
443 case CC_OP_ADDU_64:
444 case CC_OP_ADDC_64:
445 case CC_OP_SUB_64:
446 case CC_OP_SUBU_64:
447 case CC_OP_SUBB_64:
448 case CC_OP_ADD_32:
449 case CC_OP_ADDU_32:
450 case CC_OP_ADDC_32:
451 case CC_OP_SUB_32:
452 case CC_OP_SUBU_32:
453 case CC_OP_SUBB_32:
454 local_cc_op = tcg_const_i32(s->cc_op);
455 break;
456 case CC_OP_CONST0:
457 case CC_OP_CONST1:
458 case CC_OP_CONST2:
459 case CC_OP_CONST3:
460 case CC_OP_STATIC:
461 case CC_OP_DYNAMIC:
462 break;
463 }
464
465 switch (s->cc_op) {
466 case CC_OP_CONST0:
467 case CC_OP_CONST1:
468 case CC_OP_CONST2:
469 case CC_OP_CONST3:
470 /* s->cc_op is the cc value */
471 tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
472 break;
473 case CC_OP_STATIC:
474 /* env->cc_op already is the cc value */
475 break;
476 case CC_OP_NZ:
477 case CC_OP_ABS_64:
478 case CC_OP_NABS_64:
479 case CC_OP_ABS_32:
480 case CC_OP_NABS_32:
481 case CC_OP_LTGT0_32:
482 case CC_OP_LTGT0_64:
483 case CC_OP_COMP_32:
484 case CC_OP_COMP_64:
485 case CC_OP_NZ_F32:
486 case CC_OP_NZ_F64:
487 case CC_OP_FLOGR:
488 /* 1 argument */
489 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dummy);
490 break;
491 case CC_OP_ICM:
492 case CC_OP_LTGT_32:
493 case CC_OP_LTGT_64:
494 case CC_OP_LTUGTU_32:
495 case CC_OP_LTUGTU_64:
496 case CC_OP_TM_32:
497 case CC_OP_TM_64:
498 case CC_OP_SLA_32:
499 case CC_OP_SLA_64:
500 case CC_OP_NZ_F128:
501 /* 2 arguments */
502 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
503 break;
504 case CC_OP_ADD_64:
505 case CC_OP_ADDU_64:
506 case CC_OP_ADDC_64:
507 case CC_OP_SUB_64:
508 case CC_OP_SUBU_64:
509 case CC_OP_SUBB_64:
510 case CC_OP_ADD_32:
511 case CC_OP_ADDU_32:
512 case CC_OP_ADDC_32:
513 case CC_OP_SUB_32:
514 case CC_OP_SUBU_32:
515 case CC_OP_SUBB_32:
516 /* 3 arguments */
517 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc_vr);
518 break;
519 case CC_OP_DYNAMIC:
520 /* unknown operation - assume 3 arguments and cc_op in env */
521 gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr);
522 break;
523 default:
524 tcg_abort();
525 }
526
527 if (!TCGV_IS_UNUSED_I32(local_cc_op)) {
528 tcg_temp_free_i32(local_cc_op);
529 }
530 if (!TCGV_IS_UNUSED_I64(dummy)) {
531 tcg_temp_free_i64(dummy);
532 }
533
534 /* We now have cc in cc_op as constant */
535 set_cc_static(s);
536 }
537
538 static int use_goto_tb(DisasContext *s, uint64_t dest)
539 {
540 /* NOTE: we handle the case where the TB spans two pages here */
541 return (((dest & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK)
542 || (dest & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK))
543 && !s->singlestep_enabled
544 && !(s->tb->cflags & CF_LAST_IO));
545 }
546
547 static void account_noninline_branch(DisasContext *s, int cc_op)
548 {
549 #ifdef DEBUG_INLINE_BRANCHES
550 inline_branch_miss[cc_op]++;
551 #endif
552 }
553
554 static void account_inline_branch(DisasContext *s, int cc_op)
555 {
556 #ifdef DEBUG_INLINE_BRANCHES
557 inline_branch_hit[cc_op]++;
558 #endif
559 }
560
561 /* Table of mask values to comparison codes, given a comparison as input.
562 For a true comparison CC=3 will never be set, but we treat this
563 conservatively for possible use when CC=3 indicates overflow. */
564 static const TCGCond ltgt_cond[16] = {
565 TCG_COND_NEVER, TCG_COND_NEVER, /* | | | x */
566 TCG_COND_GT, TCG_COND_NEVER, /* | | GT | x */
567 TCG_COND_LT, TCG_COND_NEVER, /* | LT | | x */
568 TCG_COND_NE, TCG_COND_NEVER, /* | LT | GT | x */
569 TCG_COND_EQ, TCG_COND_NEVER, /* EQ | | | x */
570 TCG_COND_GE, TCG_COND_NEVER, /* EQ | | GT | x */
571 TCG_COND_LE, TCG_COND_NEVER, /* EQ | LT | | x */
572 TCG_COND_ALWAYS, TCG_COND_ALWAYS, /* EQ | LT | GT | x */
573 };
574
575 /* Table of mask values to comparison codes, given a logic op as input.
576 For such, only CC=0 and CC=1 should be possible. */
577 static const TCGCond nz_cond[16] = {
578 /* | | x | x */
579 TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER,
580 /* | NE | x | x */
581 TCG_COND_NE, TCG_COND_NE, TCG_COND_NE, TCG_COND_NE,
582 /* EQ | | x | x */
583 TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ,
584 /* EQ | NE | x | x */
585 TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS,
586 };
587
588 /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
589 details required to generate a TCG comparison. */
590 static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
591 {
592 TCGCond cond;
593 enum cc_op old_cc_op = s->cc_op;
594
595 if (mask == 15 || mask == 0) {
596 c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER);
597 c->u.s32.a = cc_op;
598 c->u.s32.b = cc_op;
599 c->g1 = c->g2 = true;
600 c->is_64 = false;
601 return;
602 }
603
604 /* Find the TCG condition for the mask + cc op. */
605 switch (old_cc_op) {
606 case CC_OP_LTGT0_32:
607 case CC_OP_LTGT0_64:
608 case CC_OP_LTGT_32:
609 case CC_OP_LTGT_64:
610 cond = ltgt_cond[mask];
611 if (cond == TCG_COND_NEVER) {
612 goto do_dynamic;
613 }
614 account_inline_branch(s, old_cc_op);
615 break;
616
617 case CC_OP_LTUGTU_32:
618 case CC_OP_LTUGTU_64:
619 cond = tcg_unsigned_cond(ltgt_cond[mask]);
620 if (cond == TCG_COND_NEVER) {
621 goto do_dynamic;
622 }
623 account_inline_branch(s, old_cc_op);
624 break;
625
626 case CC_OP_NZ:
627 cond = nz_cond[mask];
628 if (cond == TCG_COND_NEVER) {
629 goto do_dynamic;
630 }
631 account_inline_branch(s, old_cc_op);
632 break;
633
634 case CC_OP_TM_32:
635 case CC_OP_TM_64:
636 switch (mask) {
637 case 8:
638 cond = TCG_COND_EQ;
639 break;
640 case 4 | 2 | 1:
641 cond = TCG_COND_NE;
642 break;
643 default:
644 goto do_dynamic;
645 }
646 account_inline_branch(s, old_cc_op);
647 break;
648
649 case CC_OP_ICM:
650 switch (mask) {
651 case 8:
652 cond = TCG_COND_EQ;
653 break;
654 case 4 | 2 | 1:
655 case 4 | 2:
656 cond = TCG_COND_NE;
657 break;
658 default:
659 goto do_dynamic;
660 }
661 account_inline_branch(s, old_cc_op);
662 break;
663
664 case CC_OP_FLOGR:
665 switch (mask & 0xa) {
666 case 8: /* src == 0 -> no one bit found */
667 cond = TCG_COND_EQ;
668 break;
669 case 2: /* src != 0 -> one bit found */
670 cond = TCG_COND_NE;
671 break;
672 default:
673 goto do_dynamic;
674 }
675 account_inline_branch(s, old_cc_op);
676 break;
677
678 default:
679 do_dynamic:
680 /* Calculate cc value. */
681 gen_op_calc_cc(s);
682 /* FALLTHRU */
683
684 case CC_OP_STATIC:
685 /* Jump based on CC. We'll load up the real cond below;
686 the assignment here merely avoids a compiler warning. */
687 account_noninline_branch(s, old_cc_op);
688 old_cc_op = CC_OP_STATIC;
689 cond = TCG_COND_NEVER;
690 break;
691 }
692
693 /* Load up the arguments of the comparison. */
694 c->is_64 = true;
695 c->g1 = c->g2 = false;
696 switch (old_cc_op) {
697 case CC_OP_LTGT0_32:
698 c->is_64 = false;
699 c->u.s32.a = tcg_temp_new_i32();
700 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_dst);
701 c->u.s32.b = tcg_const_i32(0);
702 break;
703 case CC_OP_LTGT_32:
704 case CC_OP_LTUGTU_32:
705 c->is_64 = false;
706 c->u.s32.a = tcg_temp_new_i32();
707 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_src);
708 c->u.s32.b = tcg_temp_new_i32();
709 tcg_gen_trunc_i64_i32(c->u.s32.b, cc_dst);
710 break;
711
712 case CC_OP_LTGT0_64:
713 case CC_OP_NZ:
714 case CC_OP_FLOGR:
715 c->u.s64.a = cc_dst;
716 c->u.s64.b = tcg_const_i64(0);
717 c->g1 = true;
718 break;
719 case CC_OP_LTGT_64:
720 case CC_OP_LTUGTU_64:
721 c->u.s64.a = cc_src;
722 c->u.s64.b = cc_dst;
723 c->g1 = c->g2 = true;
724 break;
725
726 case CC_OP_TM_32:
727 case CC_OP_TM_64:
728 case CC_OP_ICM:
729 c->u.s64.a = tcg_temp_new_i64();
730 c->u.s64.b = tcg_const_i64(0);
731 tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst);
732 break;
733
734 case CC_OP_STATIC:
735 c->is_64 = false;
736 c->u.s32.a = cc_op;
737 c->g1 = true;
738 switch (mask) {
739 case 0x8 | 0x4 | 0x2: /* cc != 3 */
740 cond = TCG_COND_NE;
741 c->u.s32.b = tcg_const_i32(3);
742 break;
743 case 0x8 | 0x4 | 0x1: /* cc != 2 */
744 cond = TCG_COND_NE;
745 c->u.s32.b = tcg_const_i32(2);
746 break;
747 case 0x8 | 0x2 | 0x1: /* cc != 1 */
748 cond = TCG_COND_NE;
749 c->u.s32.b = tcg_const_i32(1);
750 break;
751 case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
752 cond = TCG_COND_EQ;
753 c->g1 = false;
754 c->u.s32.a = tcg_temp_new_i32();
755 c->u.s32.b = tcg_const_i32(0);
756 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
757 break;
758 case 0x8 | 0x4: /* cc < 2 */
759 cond = TCG_COND_LTU;
760 c->u.s32.b = tcg_const_i32(2);
761 break;
762 case 0x8: /* cc == 0 */
763 cond = TCG_COND_EQ;
764 c->u.s32.b = tcg_const_i32(0);
765 break;
766 case 0x4 | 0x2 | 0x1: /* cc != 0 */
767 cond = TCG_COND_NE;
768 c->u.s32.b = tcg_const_i32(0);
769 break;
770 case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
771 cond = TCG_COND_NE;
772 c->g1 = false;
773 c->u.s32.a = tcg_temp_new_i32();
774 c->u.s32.b = tcg_const_i32(0);
775 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
776 break;
777 case 0x4: /* cc == 1 */
778 cond = TCG_COND_EQ;
779 c->u.s32.b = tcg_const_i32(1);
780 break;
781 case 0x2 | 0x1: /* cc > 1 */
782 cond = TCG_COND_GTU;
783 c->u.s32.b = tcg_const_i32(1);
784 break;
785 case 0x2: /* cc == 2 */
786 cond = TCG_COND_EQ;
787 c->u.s32.b = tcg_const_i32(2);
788 break;
789 case 0x1: /* cc == 3 */
790 cond = TCG_COND_EQ;
791 c->u.s32.b = tcg_const_i32(3);
792 break;
793 default:
794 /* CC is masked by something else: (8 >> cc) & mask. */
795 cond = TCG_COND_NE;
796 c->g1 = false;
797 c->u.s32.a = tcg_const_i32(8);
798 c->u.s32.b = tcg_const_i32(0);
799 tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op);
800 tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask);
801 break;
802 }
803 break;
804
805 default:
806 abort();
807 }
808 c->cond = cond;
809 }
810
811 static void free_compare(DisasCompare *c)
812 {
813 if (!c->g1) {
814 if (c->is_64) {
815 tcg_temp_free_i64(c->u.s64.a);
816 } else {
817 tcg_temp_free_i32(c->u.s32.a);
818 }
819 }
820 if (!c->g2) {
821 if (c->is_64) {
822 tcg_temp_free_i64(c->u.s64.b);
823 } else {
824 tcg_temp_free_i32(c->u.s32.b);
825 }
826 }
827 }
828
829 /* ====================================================================== */
830 /* Define the insn format enumeration. */
831 #define F0(N) FMT_##N,
832 #define F1(N, X1) F0(N)
833 #define F2(N, X1, X2) F0(N)
834 #define F3(N, X1, X2, X3) F0(N)
835 #define F4(N, X1, X2, X3, X4) F0(N)
836 #define F5(N, X1, X2, X3, X4, X5) F0(N)
837
838 typedef enum {
839 #include "insn-format.def"
840 } DisasFormat;
841
842 #undef F0
843 #undef F1
844 #undef F2
845 #undef F3
846 #undef F4
847 #undef F5
848
849 /* Define a structure to hold the decoded fields. We'll store each inside
850 an array indexed by an enum. In order to conserve memory, we'll arrange
851 for fields that do not exist at the same time to overlap, thus the "C"
852 for compact. For checking purposes there is an "O" for original index
853 as well that will be applied to availability bitmaps. */
854
855 enum DisasFieldIndexO {
856 FLD_O_r1,
857 FLD_O_r2,
858 FLD_O_r3,
859 FLD_O_m1,
860 FLD_O_m3,
861 FLD_O_m4,
862 FLD_O_b1,
863 FLD_O_b2,
864 FLD_O_b4,
865 FLD_O_d1,
866 FLD_O_d2,
867 FLD_O_d4,
868 FLD_O_x2,
869 FLD_O_l1,
870 FLD_O_l2,
871 FLD_O_i1,
872 FLD_O_i2,
873 FLD_O_i3,
874 FLD_O_i4,
875 FLD_O_i5
876 };
877
878 enum DisasFieldIndexC {
879 FLD_C_r1 = 0,
880 FLD_C_m1 = 0,
881 FLD_C_b1 = 0,
882 FLD_C_i1 = 0,
883
884 FLD_C_r2 = 1,
885 FLD_C_b2 = 1,
886 FLD_C_i2 = 1,
887
888 FLD_C_r3 = 2,
889 FLD_C_m3 = 2,
890 FLD_C_i3 = 2,
891
892 FLD_C_m4 = 3,
893 FLD_C_b4 = 3,
894 FLD_C_i4 = 3,
895 FLD_C_l1 = 3,
896
897 FLD_C_i5 = 4,
898 FLD_C_d1 = 4,
899
900 FLD_C_d2 = 5,
901
902 FLD_C_d4 = 6,
903 FLD_C_x2 = 6,
904 FLD_C_l2 = 6,
905
906 NUM_C_FIELD = 7
907 };
908
909 struct DisasFields {
910 unsigned op:8;
911 unsigned op2:8;
912 unsigned presentC:16;
913 unsigned int presentO;
914 int c[NUM_C_FIELD];
915 };
916
917 /* This is the way fields are to be accessed out of DisasFields. */
918 #define have_field(S, F) have_field1((S), FLD_O_##F)
919 #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
920
921 static bool have_field1(const DisasFields *f, enum DisasFieldIndexO c)
922 {
923 return (f->presentO >> c) & 1;
924 }
925
926 static int get_field1(const DisasFields *f, enum DisasFieldIndexO o,
927 enum DisasFieldIndexC c)
928 {
929 assert(have_field1(f, o));
930 return f->c[c];
931 }
932
933 /* Describe the layout of each field in each format. */
934 typedef struct DisasField {
935 unsigned int beg:8;
936 unsigned int size:8;
937 unsigned int type:2;
938 unsigned int indexC:6;
939 enum DisasFieldIndexO indexO:8;
940 } DisasField;
941
942 typedef struct DisasFormatInfo {
943 DisasField op[NUM_C_FIELD];
944 } DisasFormatInfo;
945
946 #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
947 #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
948 #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
949 { BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
950 #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
951 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
952 { 20, 12, 0, FLD_C_d##N, FLD_O_d##N }
953 #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
954 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
955 #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
956 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
957 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
958 #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N }
959 #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N }
960
961 #define F0(N) { { } },
962 #define F1(N, X1) { { X1 } },
963 #define F2(N, X1, X2) { { X1, X2 } },
964 #define F3(N, X1, X2, X3) { { X1, X2, X3 } },
965 #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
966 #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
967
968 static const DisasFormatInfo format_info[] = {
969 #include "insn-format.def"
970 };
971
972 #undef F0
973 #undef F1
974 #undef F2
975 #undef F3
976 #undef F4
977 #undef F5
978 #undef R
979 #undef M
980 #undef BD
981 #undef BXD
982 #undef BDL
983 #undef BXDL
984 #undef I
985 #undef L
986
987 /* Generally, we'll extract operands into this structures, operate upon
988 them, and store them back. See the "in1", "in2", "prep", "wout" sets
989 of routines below for more details. */
990 typedef struct {
991 bool g_out, g_out2, g_in1, g_in2;
992 TCGv_i64 out, out2, in1, in2;
993 TCGv_i64 addr1;
994 } DisasOps;
995
996 /* Return values from translate_one, indicating the state of the TB. */
997 typedef enum {
998 /* Continue the TB. */
999 NO_EXIT,
1000 /* We have emitted one or more goto_tb. No fixup required. */
1001 EXIT_GOTO_TB,
1002 /* We are not using a goto_tb (for whatever reason), but have updated
1003 the PC (for whatever reason), so there's no need to do it again on
1004 exiting the TB. */
1005 EXIT_PC_UPDATED,
1006 /* We are exiting the TB, but have neither emitted a goto_tb, nor
1007 updated the PC for the next instruction to be executed. */
1008 EXIT_PC_STALE,
1009 /* We are ending the TB with a noreturn function call, e.g. longjmp.
1010 No following code will be executed. */
1011 EXIT_NORETURN,
1012 } ExitStatus;
1013
1014 typedef enum DisasFacility {
1015 FAC_Z, /* zarch (default) */
1016 FAC_CASS, /* compare and swap and store */
1017 FAC_CASS2, /* compare and swap and store 2*/
1018 FAC_DFP, /* decimal floating point */
1019 FAC_DFPR, /* decimal floating point rounding */
1020 FAC_DO, /* distinct operands */
1021 FAC_EE, /* execute extensions */
1022 FAC_EI, /* extended immediate */
1023 FAC_FPE, /* floating point extension */
1024 FAC_FPSSH, /* floating point support sign handling */
1025 FAC_FPRGR, /* FPR-GR transfer */
1026 FAC_GIE, /* general instructions extension */
1027 FAC_HFP_MA, /* HFP multiply-and-add/subtract */
1028 FAC_HW, /* high-word */
1029 FAC_IEEEE_SIM, /* IEEE exception sumilation */
1030 FAC_LOC, /* load/store on condition */
1031 FAC_LD, /* long displacement */
1032 FAC_PC, /* population count */
1033 FAC_SCF, /* store clock fast */
1034 FAC_SFLE, /* store facility list extended */
1035 } DisasFacility;
1036
1037 struct DisasInsn {
1038 unsigned opc:16;
1039 DisasFormat fmt:6;
1040 DisasFacility fac:6;
1041
1042 const char *name;
1043
1044 void (*help_in1)(DisasContext *, DisasFields *, DisasOps *);
1045 void (*help_in2)(DisasContext *, DisasFields *, DisasOps *);
1046 void (*help_prep)(DisasContext *, DisasFields *, DisasOps *);
1047 void (*help_wout)(DisasContext *, DisasFields *, DisasOps *);
1048 void (*help_cout)(DisasContext *, DisasOps *);
1049 ExitStatus (*help_op)(DisasContext *, DisasOps *);
1050
1051 uint64_t data;
1052 };
1053
1054 /* ====================================================================== */
1055 /* Miscelaneous helpers, used by several operations. */
1056
1057 static void help_l2_shift(DisasContext *s, DisasFields *f,
1058 DisasOps *o, int mask)
1059 {
1060 int b2 = get_field(f, b2);
1061 int d2 = get_field(f, d2);
1062
1063 if (b2 == 0) {
1064 o->in2 = tcg_const_i64(d2 & mask);
1065 } else {
1066 o->in2 = get_address(s, 0, b2, d2);
1067 tcg_gen_andi_i64(o->in2, o->in2, mask);
1068 }
1069 }
1070
1071 static ExitStatus help_goto_direct(DisasContext *s, uint64_t dest)
1072 {
1073 if (dest == s->next_pc) {
1074 return NO_EXIT;
1075 }
1076 if (use_goto_tb(s, dest)) {
1077 update_cc_op(s);
1078 tcg_gen_goto_tb(0);
1079 tcg_gen_movi_i64(psw_addr, dest);
1080 tcg_gen_exit_tb((tcg_target_long)s->tb);
1081 return EXIT_GOTO_TB;
1082 } else {
1083 tcg_gen_movi_i64(psw_addr, dest);
1084 return EXIT_PC_UPDATED;
1085 }
1086 }
1087
1088 static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
1089 bool is_imm, int imm, TCGv_i64 cdest)
1090 {
1091 ExitStatus ret;
1092 uint64_t dest = s->pc + 2 * imm;
1093 int lab;
1094
1095 /* Take care of the special cases first. */
1096 if (c->cond == TCG_COND_NEVER) {
1097 ret = NO_EXIT;
1098 goto egress;
1099 }
1100 if (is_imm) {
1101 if (dest == s->next_pc) {
1102 /* Branch to next. */
1103 ret = NO_EXIT;
1104 goto egress;
1105 }
1106 if (c->cond == TCG_COND_ALWAYS) {
1107 ret = help_goto_direct(s, dest);
1108 goto egress;
1109 }
1110 } else {
1111 if (TCGV_IS_UNUSED_I64(cdest)) {
1112 /* E.g. bcr %r0 -> no branch. */
1113 ret = NO_EXIT;
1114 goto egress;
1115 }
1116 if (c->cond == TCG_COND_ALWAYS) {
1117 tcg_gen_mov_i64(psw_addr, cdest);
1118 ret = EXIT_PC_UPDATED;
1119 goto egress;
1120 }
1121 }
1122
1123 if (use_goto_tb(s, s->next_pc)) {
1124 if (is_imm && use_goto_tb(s, dest)) {
1125 /* Both exits can use goto_tb. */
1126 update_cc_op(s);
1127
1128 lab = gen_new_label();
1129 if (c->is_64) {
1130 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1131 } else {
1132 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1133 }
1134
1135 /* Branch not taken. */
1136 tcg_gen_goto_tb(0);
1137 tcg_gen_movi_i64(psw_addr, s->next_pc);
1138 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
1139
1140 /* Branch taken. */
1141 gen_set_label(lab);
1142 tcg_gen_goto_tb(1);
1143 tcg_gen_movi_i64(psw_addr, dest);
1144 tcg_gen_exit_tb((tcg_target_long)s->tb + 1);
1145
1146 ret = EXIT_GOTO_TB;
1147 } else {
1148 /* Fallthru can use goto_tb, but taken branch cannot. */
1149 /* Store taken branch destination before the brcond. This
1150 avoids having to allocate a new local temp to hold it.
1151 We'll overwrite this in the not taken case anyway. */
1152 if (!is_imm) {
1153 tcg_gen_mov_i64(psw_addr, cdest);
1154 }
1155
1156 lab = gen_new_label();
1157 if (c->is_64) {
1158 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1159 } else {
1160 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1161 }
1162
1163 /* Branch not taken. */
1164 update_cc_op(s);
1165 tcg_gen_goto_tb(0);
1166 tcg_gen_movi_i64(psw_addr, s->next_pc);
1167 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
1168
1169 gen_set_label(lab);
1170 if (is_imm) {
1171 tcg_gen_movi_i64(psw_addr, dest);
1172 }
1173 ret = EXIT_PC_UPDATED;
1174 }
1175 } else {
1176 /* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
1177 Most commonly we're single-stepping or some other condition that
1178 disables all use of goto_tb. Just update the PC and exit. */
1179
1180 TCGv_i64 next = tcg_const_i64(s->next_pc);
1181 if (is_imm) {
1182 cdest = tcg_const_i64(dest);
1183 }
1184
1185 if (c->is_64) {
1186 tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b,
1187 cdest, next);
1188 } else {
1189 TCGv_i32 t0 = tcg_temp_new_i32();
1190 TCGv_i64 t1 = tcg_temp_new_i64();
1191 TCGv_i64 z = tcg_const_i64(0);
1192 tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b);
1193 tcg_gen_extu_i32_i64(t1, t0);
1194 tcg_temp_free_i32(t0);
1195 tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next);
1196 tcg_temp_free_i64(t1);
1197 tcg_temp_free_i64(z);
1198 }
1199
1200 if (is_imm) {
1201 tcg_temp_free_i64(cdest);
1202 }
1203 tcg_temp_free_i64(next);
1204
1205 ret = EXIT_PC_UPDATED;
1206 }
1207
1208 egress:
1209 free_compare(c);
1210 return ret;
1211 }
1212
1213 /* ====================================================================== */
1214 /* The operations. These perform the bulk of the work for any insn,
1215 usually after the operands have been loaded and output initialized. */
1216
1217 static ExitStatus op_abs(DisasContext *s, DisasOps *o)
1218 {
1219 gen_helper_abs_i64(o->out, o->in2);
1220 return NO_EXIT;
1221 }
1222
1223 static ExitStatus op_absf32(DisasContext *s, DisasOps *o)
1224 {
1225 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffull);
1226 return NO_EXIT;
1227 }
1228
1229 static ExitStatus op_absf64(DisasContext *s, DisasOps *o)
1230 {
1231 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull);
1232 return NO_EXIT;
1233 }
1234
1235 static ExitStatus op_absf128(DisasContext *s, DisasOps *o)
1236 {
1237 tcg_gen_andi_i64(o->out, o->in1, 0x7fffffffffffffffull);
1238 tcg_gen_mov_i64(o->out2, o->in2);
1239 return NO_EXIT;
1240 }
1241
1242 static ExitStatus op_add(DisasContext *s, DisasOps *o)
1243 {
1244 tcg_gen_add_i64(o->out, o->in1, o->in2);
1245 return NO_EXIT;
1246 }
1247
1248 static ExitStatus op_addc(DisasContext *s, DisasOps *o)
1249 {
1250 TCGv_i64 cc;
1251
1252 tcg_gen_add_i64(o->out, o->in1, o->in2);
1253
1254 /* XXX possible optimization point */
1255 gen_op_calc_cc(s);
1256 cc = tcg_temp_new_i64();
1257 tcg_gen_extu_i32_i64(cc, cc_op);
1258 tcg_gen_shri_i64(cc, cc, 1);
1259
1260 tcg_gen_add_i64(o->out, o->out, cc);
1261 tcg_temp_free_i64(cc);
1262 return NO_EXIT;
1263 }
1264
1265 static ExitStatus op_aeb(DisasContext *s, DisasOps *o)
1266 {
1267 gen_helper_aeb(o->out, cpu_env, o->in1, o->in2);
1268 return NO_EXIT;
1269 }
1270
1271 static ExitStatus op_adb(DisasContext *s, DisasOps *o)
1272 {
1273 gen_helper_adb(o->out, cpu_env, o->in1, o->in2);
1274 return NO_EXIT;
1275 }
1276
1277 static ExitStatus op_axb(DisasContext *s, DisasOps *o)
1278 {
1279 gen_helper_axb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
1280 return_low128(o->out2);
1281 return NO_EXIT;
1282 }
1283
1284 static ExitStatus op_and(DisasContext *s, DisasOps *o)
1285 {
1286 tcg_gen_and_i64(o->out, o->in1, o->in2);
1287 return NO_EXIT;
1288 }
1289
1290 static ExitStatus op_andi(DisasContext *s, DisasOps *o)
1291 {
1292 int shift = s->insn->data & 0xff;
1293 int size = s->insn->data >> 8;
1294 uint64_t mask = ((1ull << size) - 1) << shift;
1295
1296 assert(!o->g_in2);
1297 tcg_gen_shli_i64(o->in2, o->in2, shift);
1298 tcg_gen_ori_i64(o->in2, o->in2, ~mask);
1299 tcg_gen_and_i64(o->out, o->in1, o->in2);
1300
1301 /* Produce the CC from only the bits manipulated. */
1302 tcg_gen_andi_i64(cc_dst, o->out, mask);
1303 set_cc_nz_u64(s, cc_dst);
1304 return NO_EXIT;
1305 }
1306
1307 static ExitStatus op_bas(DisasContext *s, DisasOps *o)
1308 {
1309 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1310 if (!TCGV_IS_UNUSED_I64(o->in2)) {
1311 tcg_gen_mov_i64(psw_addr, o->in2);
1312 return EXIT_PC_UPDATED;
1313 } else {
1314 return NO_EXIT;
1315 }
1316 }
1317
1318 static ExitStatus op_basi(DisasContext *s, DisasOps *o)
1319 {
1320 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1321 return help_goto_direct(s, s->pc + 2 * get_field(s->fields, i2));
1322 }
1323
1324 static ExitStatus op_bc(DisasContext *s, DisasOps *o)
1325 {
1326 int m1 = get_field(s->fields, m1);
1327 bool is_imm = have_field(s->fields, i2);
1328 int imm = is_imm ? get_field(s->fields, i2) : 0;
1329 DisasCompare c;
1330
1331 disas_jcc(s, &c, m1);
1332 return help_branch(s, &c, is_imm, imm, o->in2);
1333 }
1334
1335 static ExitStatus op_bct32(DisasContext *s, DisasOps *o)
1336 {
1337 int r1 = get_field(s->fields, r1);
1338 bool is_imm = have_field(s->fields, i2);
1339 int imm = is_imm ? get_field(s->fields, i2) : 0;
1340 DisasCompare c;
1341 TCGv_i64 t;
1342
1343 c.cond = TCG_COND_NE;
1344 c.is_64 = false;
1345 c.g1 = false;
1346 c.g2 = false;
1347
1348 t = tcg_temp_new_i64();
1349 tcg_gen_subi_i64(t, regs[r1], 1);
1350 store_reg32_i64(r1, t);
1351 c.u.s32.a = tcg_temp_new_i32();
1352 c.u.s32.b = tcg_const_i32(0);
1353 tcg_gen_trunc_i64_i32(c.u.s32.a, t);
1354 tcg_temp_free_i64(t);
1355
1356 return help_branch(s, &c, is_imm, imm, o->in2);
1357 }
1358
1359 static ExitStatus op_bct64(DisasContext *s, DisasOps *o)
1360 {
1361 int r1 = get_field(s->fields, r1);
1362 bool is_imm = have_field(s->fields, i2);
1363 int imm = is_imm ? get_field(s->fields, i2) : 0;
1364 DisasCompare c;
1365
1366 c.cond = TCG_COND_NE;
1367 c.is_64 = true;
1368 c.g1 = true;
1369 c.g2 = false;
1370
1371 tcg_gen_subi_i64(regs[r1], regs[r1], 1);
1372 c.u.s64.a = regs[r1];
1373 c.u.s64.b = tcg_const_i64(0);
1374
1375 return help_branch(s, &c, is_imm, imm, o->in2);
1376 }
1377
1378 static ExitStatus op_bx32(DisasContext *s, DisasOps *o)
1379 {
1380 int r1 = get_field(s->fields, r1);
1381 int r3 = get_field(s->fields, r3);
1382 bool is_imm = have_field(s->fields, i2);
1383 int imm = is_imm ? get_field(s->fields, i2) : 0;
1384 DisasCompare c;
1385 TCGv_i64 t;
1386
1387 c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT);
1388 c.is_64 = false;
1389 c.g1 = false;
1390 c.g2 = false;
1391
1392 t = tcg_temp_new_i64();
1393 tcg_gen_add_i64(t, regs[r1], regs[r3]);
1394 c.u.s32.a = tcg_temp_new_i32();
1395 c.u.s32.b = tcg_temp_new_i32();
1396 tcg_gen_trunc_i64_i32(c.u.s32.a, t);
1397 tcg_gen_trunc_i64_i32(c.u.s32.b, regs[r3 | 1]);
1398 store_reg32_i64(r1, t);
1399 tcg_temp_free_i64(t);
1400
1401 return help_branch(s, &c, is_imm, imm, o->in2);
1402 }
1403
1404 static ExitStatus op_bx64(DisasContext *s, DisasOps *o)
1405 {
1406 int r1 = get_field(s->fields, r1);
1407 int r3 = get_field(s->fields, r3);
1408 bool is_imm = have_field(s->fields, i2);
1409 int imm = is_imm ? get_field(s->fields, i2) : 0;
1410 DisasCompare c;
1411
1412 c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT);
1413 c.is_64 = true;
1414
1415 if (r1 == (r3 | 1)) {
1416 c.u.s64.b = load_reg(r3 | 1);
1417 c.g2 = false;
1418 } else {
1419 c.u.s64.b = regs[r3 | 1];
1420 c.g2 = true;
1421 }
1422
1423 tcg_gen_add_i64(regs[r1], regs[r1], regs[r3]);
1424 c.u.s64.a = regs[r1];
1425 c.g1 = true;
1426
1427 return help_branch(s, &c, is_imm, imm, o->in2);
1428 }
1429
1430 static ExitStatus op_cj(DisasContext *s, DisasOps *o)
1431 {
1432 int imm, m3 = get_field(s->fields, m3);
1433 bool is_imm;
1434 DisasCompare c;
1435
1436 /* Bit 3 of the m3 field is reserved and should be zero.
1437 Choose to ignore it wrt the ltgt_cond table above. */
1438 c.cond = ltgt_cond[m3 & 14];
1439 if (s->insn->data) {
1440 c.cond = tcg_unsigned_cond(c.cond);
1441 }
1442 c.is_64 = c.g1 = c.g2 = true;
1443 c.u.s64.a = o->in1;
1444 c.u.s64.b = o->in2;
1445
1446 is_imm = have_field(s->fields, i4);
1447 if (is_imm) {
1448 imm = get_field(s->fields, i4);
1449 } else {
1450 imm = 0;
1451 o->out = get_address(s, 0, get_field(s->fields, b4),
1452 get_field(s->fields, d4));
1453 }
1454
1455 return help_branch(s, &c, is_imm, imm, o->out);
1456 }
1457
1458 static ExitStatus op_ceb(DisasContext *s, DisasOps *o)
1459 {
1460 gen_helper_ceb(cc_op, cpu_env, o->in1, o->in2);
1461 set_cc_static(s);
1462 return NO_EXIT;
1463 }
1464
1465 static ExitStatus op_cdb(DisasContext *s, DisasOps *o)
1466 {
1467 gen_helper_cdb(cc_op, cpu_env, o->in1, o->in2);
1468 set_cc_static(s);
1469 return NO_EXIT;
1470 }
1471
1472 static ExitStatus op_cxb(DisasContext *s, DisasOps *o)
1473 {
1474 gen_helper_cxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2);
1475 set_cc_static(s);
1476 return NO_EXIT;
1477 }
1478
1479 static ExitStatus op_cfeb(DisasContext *s, DisasOps *o)
1480 {
1481 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1482 gen_helper_cfeb(o->out, cpu_env, o->in2, m3);
1483 tcg_temp_free_i32(m3);
1484 gen_set_cc_nz_f32(s, o->in2);
1485 return NO_EXIT;
1486 }
1487
1488 static ExitStatus op_cfdb(DisasContext *s, DisasOps *o)
1489 {
1490 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1491 gen_helper_cfdb(o->out, cpu_env, o->in2, m3);
1492 tcg_temp_free_i32(m3);
1493 gen_set_cc_nz_f64(s, o->in2);
1494 return NO_EXIT;
1495 }
1496
1497 static ExitStatus op_cfxb(DisasContext *s, DisasOps *o)
1498 {
1499 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1500 gen_helper_cfxb(o->out, cpu_env, o->in1, o->in2, m3);
1501 tcg_temp_free_i32(m3);
1502 gen_set_cc_nz_f128(s, o->in1, o->in2);
1503 return NO_EXIT;
1504 }
1505
1506 static ExitStatus op_cgeb(DisasContext *s, DisasOps *o)
1507 {
1508 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1509 gen_helper_cgeb(o->out, cpu_env, o->in2, m3);
1510 tcg_temp_free_i32(m3);
1511 gen_set_cc_nz_f32(s, o->in2);
1512 return NO_EXIT;
1513 }
1514
1515 static ExitStatus op_cgdb(DisasContext *s, DisasOps *o)
1516 {
1517 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1518 gen_helper_cgdb(o->out, cpu_env, o->in2, m3);
1519 tcg_temp_free_i32(m3);
1520 gen_set_cc_nz_f64(s, o->in2);
1521 return NO_EXIT;
1522 }
1523
1524 static ExitStatus op_cgxb(DisasContext *s, DisasOps *o)
1525 {
1526 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1527 gen_helper_cgxb(o->out, cpu_env, o->in1, o->in2, m3);
1528 tcg_temp_free_i32(m3);
1529 gen_set_cc_nz_f128(s, o->in1, o->in2);
1530 return NO_EXIT;
1531 }
1532
1533 static ExitStatus op_cegb(DisasContext *s, DisasOps *o)
1534 {
1535 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1536 gen_helper_cegb(o->out, cpu_env, o->in2, m3);
1537 tcg_temp_free_i32(m3);
1538 return NO_EXIT;
1539 }
1540
1541 static ExitStatus op_cdgb(DisasContext *s, DisasOps *o)
1542 {
1543 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1544 gen_helper_cdgb(o->out, cpu_env, o->in2, m3);
1545 tcg_temp_free_i32(m3);
1546 return NO_EXIT;
1547 }
1548
1549 static ExitStatus op_cxgb(DisasContext *s, DisasOps *o)
1550 {
1551 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1552 gen_helper_cxgb(o->out, cpu_env, o->in2, m3);
1553 tcg_temp_free_i32(m3);
1554 return_low128(o->out2);
1555 return NO_EXIT;
1556 }
1557
1558 static ExitStatus op_cksm(DisasContext *s, DisasOps *o)
1559 {
1560 int r2 = get_field(s->fields, r2);
1561 TCGv_i64 len = tcg_temp_new_i64();
1562
1563 potential_page_fault(s);
1564 gen_helper_cksm(len, cpu_env, o->in1, o->in2, regs[r2 + 1]);
1565 set_cc_static(s);
1566 return_low128(o->out);
1567
1568 tcg_gen_add_i64(regs[r2], regs[r2], len);
1569 tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len);
1570 tcg_temp_free_i64(len);
1571
1572 return NO_EXIT;
1573 }
1574
1575 static ExitStatus op_clc(DisasContext *s, DisasOps *o)
1576 {
1577 int l = get_field(s->fields, l1);
1578 TCGv_i32 vl;
1579
1580 switch (l + 1) {
1581 case 1:
1582 tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s));
1583 tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s));
1584 break;
1585 case 2:
1586 tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s));
1587 tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s));
1588 break;
1589 case 4:
1590 tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s));
1591 tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s));
1592 break;
1593 case 8:
1594 tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s));
1595 tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s));
1596 break;
1597 default:
1598 potential_page_fault(s);
1599 vl = tcg_const_i32(l);
1600 gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
1601 tcg_temp_free_i32(vl);
1602 set_cc_static(s);
1603 return NO_EXIT;
1604 }
1605 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
1606 return NO_EXIT;
1607 }
1608
1609 static ExitStatus op_clcle(DisasContext *s, DisasOps *o)
1610 {
1611 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
1612 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
1613 potential_page_fault(s);
1614 gen_helper_clcle(cc_op, cpu_env, r1, o->in2, r3);
1615 tcg_temp_free_i32(r1);
1616 tcg_temp_free_i32(r3);
1617 set_cc_static(s);
1618 return NO_EXIT;
1619 }
1620
1621 static ExitStatus op_clm(DisasContext *s, DisasOps *o)
1622 {
1623 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1624 TCGv_i32 t1 = tcg_temp_new_i32();
1625 tcg_gen_trunc_i64_i32(t1, o->in1);
1626 potential_page_fault(s);
1627 gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2);
1628 set_cc_static(s);
1629 tcg_temp_free_i32(t1);
1630 tcg_temp_free_i32(m3);
1631 return NO_EXIT;
1632 }
1633
1634 static ExitStatus op_clst(DisasContext *s, DisasOps *o)
1635 {
1636 potential_page_fault(s);
1637 gen_helper_clst(o->in1, cpu_env, regs[0], o->in1, o->in2);
1638 set_cc_static(s);
1639 return_low128(o->in2);
1640 return NO_EXIT;
1641 }
1642
1643 static ExitStatus op_cs(DisasContext *s, DisasOps *o)
1644 {
1645 int r3 = get_field(s->fields, r3);
1646 potential_page_fault(s);
1647 gen_helper_cs(o->out, cpu_env, o->in1, o->in2, regs[r3]);
1648 set_cc_static(s);
1649 return NO_EXIT;
1650 }
1651
1652 static ExitStatus op_csg(DisasContext *s, DisasOps *o)
1653 {
1654 int r3 = get_field(s->fields, r3);
1655 potential_page_fault(s);
1656 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, regs[r3]);
1657 set_cc_static(s);
1658 return NO_EXIT;
1659 }
1660
1661 #ifndef CONFIG_USER_ONLY
1662 static ExitStatus op_csp(DisasContext *s, DisasOps *o)
1663 {
1664 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
1665 check_privileged(s);
1666 gen_helper_csp(cc_op, cpu_env, r1, o->in2);
1667 tcg_temp_free_i32(r1);
1668 set_cc_static(s);
1669 return NO_EXIT;
1670 }
1671 #endif
1672
1673 static ExitStatus op_cds(DisasContext *s, DisasOps *o)
1674 {
1675 int r3 = get_field(s->fields, r3);
1676 TCGv_i64 in3 = tcg_temp_new_i64();
1677 tcg_gen_deposit_i64(in3, regs[r3 + 1], regs[r3], 32, 32);
1678 potential_page_fault(s);
1679 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, in3);
1680 tcg_temp_free_i64(in3);
1681 set_cc_static(s);
1682 return NO_EXIT;
1683 }
1684
1685 static ExitStatus op_cdsg(DisasContext *s, DisasOps *o)
1686 {
1687 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
1688 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
1689 potential_page_fault(s);
1690 /* XXX rewrite in tcg */
1691 gen_helper_cdsg(cc_op, cpu_env, r1, o->in2, r3);
1692 set_cc_static(s);
1693 return NO_EXIT;
1694 }
1695
1696 static ExitStatus op_cvd(DisasContext *s, DisasOps *o)
1697 {
1698 TCGv_i64 t1 = tcg_temp_new_i64();
1699 TCGv_i32 t2 = tcg_temp_new_i32();
1700 tcg_gen_trunc_i64_i32(t2, o->in1);
1701 gen_helper_cvd(t1, t2);
1702 tcg_temp_free_i32(t2);
1703 tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
1704 tcg_temp_free_i64(t1);
1705 return NO_EXIT;
1706 }
1707
1708 static ExitStatus op_ct(DisasContext *s, DisasOps *o)
1709 {
1710 int m3 = get_field(s->fields, m3);
1711 int lab = gen_new_label();
1712 TCGv_i32 t;
1713 TCGCond c;
1714
1715 /* Bit 3 of the m3 field is reserved and should be zero.
1716 Choose to ignore it wrt the ltgt_cond table above. */
1717 c = tcg_invert_cond(ltgt_cond[m3 & 14]);
1718 if (s->insn->data) {
1719 c = tcg_unsigned_cond(c);
1720 }
1721 tcg_gen_brcond_i64(c, o->in1, o->in2, lab);
1722
1723 /* Set DXC to 0xff. */
1724 t = tcg_temp_new_i32();
1725 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUS390XState, fpc));
1726 tcg_gen_ori_i32(t, t, 0xff00);
1727 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, fpc));
1728 tcg_temp_free_i32(t);
1729
1730 /* Trap. */
1731 gen_program_exception(s, PGM_DATA);
1732
1733 gen_set_label(lab);
1734 return NO_EXIT;
1735 }
1736
1737 #ifndef CONFIG_USER_ONLY
1738 static ExitStatus op_diag(DisasContext *s, DisasOps *o)
1739 {
1740 TCGv_i32 tmp;
1741
1742 check_privileged(s);
1743 potential_page_fault(s);
1744
1745 /* We pretend the format is RX_a so that D2 is the field we want. */
1746 tmp = tcg_const_i32(get_field(s->fields, d2) & 0xfff);
1747 gen_helper_diag(regs[2], cpu_env, tmp, regs[2], regs[1]);
1748 tcg_temp_free_i32(tmp);
1749 return NO_EXIT;
1750 }
1751 #endif
1752
1753 static ExitStatus op_divs32(DisasContext *s, DisasOps *o)
1754 {
1755 gen_helper_divs32(o->out2, cpu_env, o->in1, o->in2);
1756 return_low128(o->out);
1757 return NO_EXIT;
1758 }
1759
1760 static ExitStatus op_divu32(DisasContext *s, DisasOps *o)
1761 {
1762 gen_helper_divu32(o->out2, cpu_env, o->in1, o->in2);
1763 return_low128(o->out);
1764 return NO_EXIT;
1765 }
1766
1767 static ExitStatus op_divs64(DisasContext *s, DisasOps *o)
1768 {
1769 gen_helper_divs64(o->out2, cpu_env, o->in1, o->in2);
1770 return_low128(o->out);
1771 return NO_EXIT;
1772 }
1773
1774 static ExitStatus op_divu64(DisasContext *s, DisasOps *o)
1775 {
1776 gen_helper_divu64(o->out2, cpu_env, o->out, o->out2, o->in2);
1777 return_low128(o->out);
1778 return NO_EXIT;
1779 }
1780
1781 static ExitStatus op_deb(DisasContext *s, DisasOps *o)
1782 {
1783 gen_helper_deb(o->out, cpu_env, o->in1, o->in2);
1784 return NO_EXIT;
1785 }
1786
1787 static ExitStatus op_ddb(DisasContext *s, DisasOps *o)
1788 {
1789 gen_helper_ddb(o->out, cpu_env, o->in1, o->in2);
1790 return NO_EXIT;
1791 }
1792
1793 static ExitStatus op_dxb(DisasContext *s, DisasOps *o)
1794 {
1795 gen_helper_dxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
1796 return_low128(o->out2);
1797 return NO_EXIT;
1798 }
1799
1800 static ExitStatus op_ear(DisasContext *s, DisasOps *o)
1801 {
1802 int r2 = get_field(s->fields, r2);
1803 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, aregs[r2]));
1804 return NO_EXIT;
1805 }
1806
1807 static ExitStatus op_efpc(DisasContext *s, DisasOps *o)
1808 {
1809 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, fpc));
1810 return NO_EXIT;
1811 }
1812
1813 static ExitStatus op_ex(DisasContext *s, DisasOps *o)
1814 {
1815 /* ??? Perhaps a better way to implement EXECUTE is to set a bit in
1816 tb->flags, (ab)use the tb->cs_base field as the address of
1817 the template in memory, and grab 8 bits of tb->flags/cflags for
1818 the contents of the register. We would then recognize all this
1819 in gen_intermediate_code_internal, generating code for exactly
1820 one instruction. This new TB then gets executed normally.
1821
1822 On the other hand, this seems to be mostly used for modifying
1823 MVC inside of memcpy, which needs a helper call anyway. So
1824 perhaps this doesn't bear thinking about any further. */
1825
1826 TCGv_i64 tmp;
1827
1828 update_psw_addr(s);
1829 update_cc_op(s);
1830
1831 tmp = tcg_const_i64(s->next_pc);
1832 gen_helper_ex(cc_op, cpu_env, cc_op, o->in1, o->in2, tmp);
1833 tcg_temp_free_i64(tmp);
1834
1835 set_cc_static(s);
1836 return NO_EXIT;
1837 }
1838
1839 static ExitStatus op_flogr(DisasContext *s, DisasOps *o)
1840 {
1841 /* We'll use the original input for cc computation, since we get to
1842 compare that against 0, which ought to be better than comparing
1843 the real output against 64. It also lets cc_dst be a convenient
1844 temporary during our computation. */
1845 gen_op_update1_cc_i64(s, CC_OP_FLOGR, o->in2);
1846
1847 /* R1 = IN ? CLZ(IN) : 64. */
1848 gen_helper_clz(o->out, o->in2);
1849
1850 /* R1+1 = IN & ~(found bit). Note that we may attempt to shift this
1851 value by 64, which is undefined. But since the shift is 64 iff the
1852 input is zero, we still get the correct result after and'ing. */
1853 tcg_gen_movi_i64(o->out2, 0x8000000000000000ull);
1854 tcg_gen_shr_i64(o->out2, o->out2, o->out);
1855 tcg_gen_andc_i64(o->out2, cc_dst, o->out2);
1856 return NO_EXIT;
1857 }
1858
1859 static ExitStatus op_icm(DisasContext *s, DisasOps *o)
1860 {
1861 int m3 = get_field(s->fields, m3);
1862 int pos, len, base = s->insn->data;
1863 TCGv_i64 tmp = tcg_temp_new_i64();
1864 uint64_t ccm;
1865
1866 switch (m3) {
1867 case 0xf:
1868 /* Effectively a 32-bit load. */
1869 tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s));
1870 len = 32;
1871 goto one_insert;
1872
1873 case 0xc:
1874 case 0x6:
1875 case 0x3:
1876 /* Effectively a 16-bit load. */
1877 tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s));
1878 len = 16;
1879 goto one_insert;
1880
1881 case 0x8:
1882 case 0x4:
1883 case 0x2:
1884 case 0x1:
1885 /* Effectively an 8-bit load. */
1886 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
1887 len = 8;
1888 goto one_insert;
1889
1890 one_insert:
1891 pos = base + ctz32(m3) * 8;
1892 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len);
1893 ccm = ((1ull << len) - 1) << pos;
1894 break;
1895
1896 default:
1897 /* This is going to be a sequence of loads and inserts. */
1898 pos = base + 32 - 8;
1899 ccm = 0;
1900 while (m3) {
1901 if (m3 & 0x8) {
1902 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
1903 tcg_gen_addi_i64(o->in2, o->in2, 1);
1904 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
1905 ccm |= 0xff << pos;
1906 }
1907 m3 = (m3 << 1) & 0xf;
1908 pos -= 8;
1909 }
1910 break;
1911 }
1912
1913 tcg_gen_movi_i64(tmp, ccm);
1914 gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out);
1915 tcg_temp_free_i64(tmp);
1916 return NO_EXIT;
1917 }
1918
1919 static ExitStatus op_insi(DisasContext *s, DisasOps *o)
1920 {
1921 int shift = s->insn->data & 0xff;
1922 int size = s->insn->data >> 8;
1923 tcg_gen_deposit_i64(o->out, o->in1, o->in2, shift, size);
1924 return NO_EXIT;
1925 }
1926
1927 static ExitStatus op_ipm(DisasContext *s, DisasOps *o)
1928 {
1929 TCGv_i64 t1;
1930
1931 gen_op_calc_cc(s);
1932 tcg_gen_andi_i64(o->out, o->out, ~0xff000000ull);
1933
1934 t1 = tcg_temp_new_i64();
1935 tcg_gen_shli_i64(t1, psw_mask, 20);
1936 tcg_gen_shri_i64(t1, t1, 36);
1937 tcg_gen_or_i64(o->out, o->out, t1);
1938
1939 tcg_gen_extu_i32_i64(t1, cc_op);
1940 tcg_gen_shli_i64(t1, t1, 28);
1941 tcg_gen_or_i64(o->out, o->out, t1);
1942 tcg_temp_free_i64(t1);
1943 return NO_EXIT;
1944 }
1945
1946 #ifndef CONFIG_USER_ONLY
1947 static ExitStatus op_ipte(DisasContext *s, DisasOps *o)
1948 {
1949 check_privileged(s);
1950 gen_helper_ipte(cpu_env, o->in1, o->in2);
1951 return NO_EXIT;
1952 }
1953
1954 static ExitStatus op_iske(DisasContext *s, DisasOps *o)
1955 {
1956 check_privileged(s);
1957 gen_helper_iske(o->out, cpu_env, o->in2);
1958 return NO_EXIT;
1959 }
1960 #endif
1961
1962 static ExitStatus op_ldeb(DisasContext *s, DisasOps *o)
1963 {
1964 gen_helper_ldeb(o->out, cpu_env, o->in2);
1965 return NO_EXIT;
1966 }
1967
1968 static ExitStatus op_ledb(DisasContext *s, DisasOps *o)
1969 {
1970 gen_helper_ledb(o->out, cpu_env, o->in2);
1971 return NO_EXIT;
1972 }
1973
1974 static ExitStatus op_ldxb(DisasContext *s, DisasOps *o)
1975 {
1976 gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2);
1977 return NO_EXIT;
1978 }
1979
1980 static ExitStatus op_lexb(DisasContext *s, DisasOps *o)
1981 {
1982 gen_helper_lexb(o->out, cpu_env, o->in1, o->in2);
1983 return NO_EXIT;
1984 }
1985
1986 static ExitStatus op_lxdb(DisasContext *s, DisasOps *o)
1987 {
1988 gen_helper_lxdb(o->out, cpu_env, o->in2);
1989 return_low128(o->out2);
1990 return NO_EXIT;
1991 }
1992
1993 static ExitStatus op_lxeb(DisasContext *s, DisasOps *o)
1994 {
1995 gen_helper_lxeb(o->out, cpu_env, o->in2);
1996 return_low128(o->out2);
1997 return NO_EXIT;
1998 }
1999
2000 static ExitStatus op_llgt(DisasContext *s, DisasOps *o)
2001 {
2002 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffff);
2003 return NO_EXIT;
2004 }
2005
2006 static ExitStatus op_ld8s(DisasContext *s, DisasOps *o)
2007 {
2008 tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
2009 return NO_EXIT;
2010 }
2011
2012 static ExitStatus op_ld8u(DisasContext *s, DisasOps *o)
2013 {
2014 tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
2015 return NO_EXIT;
2016 }
2017
2018 static ExitStatus op_ld16s(DisasContext *s, DisasOps *o)
2019 {
2020 tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
2021 return NO_EXIT;
2022 }
2023
2024 static ExitStatus op_ld16u(DisasContext *s, DisasOps *o)
2025 {
2026 tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
2027 return NO_EXIT;
2028 }
2029
2030 static ExitStatus op_ld32s(DisasContext *s, DisasOps *o)
2031 {
2032 tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s));
2033 return NO_EXIT;
2034 }
2035
2036 static ExitStatus op_ld32u(DisasContext *s, DisasOps *o)
2037 {
2038 tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
2039 return NO_EXIT;
2040 }
2041
2042 static ExitStatus op_ld64(DisasContext *s, DisasOps *o)
2043 {
2044 tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
2045 return NO_EXIT;
2046 }
2047
2048 #ifndef CONFIG_USER_ONLY
2049 static ExitStatus op_lctl(DisasContext *s, DisasOps *o)
2050 {
2051 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2052 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2053 check_privileged(s);
2054 potential_page_fault(s);
2055 gen_helper_lctl(cpu_env, r1, o->in2, r3);
2056 tcg_temp_free_i32(r1);
2057 tcg_temp_free_i32(r3);
2058 return NO_EXIT;
2059 }
2060
2061 static ExitStatus op_lctlg(DisasContext *s, DisasOps *o)
2062 {
2063 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2064 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2065 check_privileged(s);
2066 potential_page_fault(s);
2067 gen_helper_lctlg(cpu_env, r1, o->in2, r3);
2068 tcg_temp_free_i32(r1);
2069 tcg_temp_free_i32(r3);
2070 return NO_EXIT;
2071 }
2072 static ExitStatus op_lra(DisasContext *s, DisasOps *o)
2073 {
2074 check_privileged(s);
2075 potential_page_fault(s);
2076 gen_helper_lra(o->out, cpu_env, o->in2);
2077 set_cc_static(s);
2078 return NO_EXIT;
2079 }
2080
2081 static ExitStatus op_lpsw(DisasContext *s, DisasOps *o)
2082 {
2083 TCGv_i64 t1, t2;
2084
2085 check_privileged(s);
2086
2087 t1 = tcg_temp_new_i64();
2088 t2 = tcg_temp_new_i64();
2089 tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
2090 tcg_gen_addi_i64(o->in2, o->in2, 4);
2091 tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s));
2092 /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
2093 tcg_gen_shli_i64(t1, t1, 32);
2094 gen_helper_load_psw(cpu_env, t1, t2);
2095 tcg_temp_free_i64(t1);
2096 tcg_temp_free_i64(t2);
2097 return EXIT_NORETURN;
2098 }
2099
2100 static ExitStatus op_lpswe(DisasContext *s, DisasOps *o)
2101 {
2102 TCGv_i64 t1, t2;
2103
2104 check_privileged(s);
2105
2106 t1 = tcg_temp_new_i64();
2107 t2 = tcg_temp_new_i64();
2108 tcg_gen_qemu_ld64(t1, o->in2, get_mem_index(s));
2109 tcg_gen_addi_i64(o->in2, o->in2, 8);
2110 tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s));
2111 gen_helper_load_psw(cpu_env, t1, t2);
2112 tcg_temp_free_i64(t1);
2113 tcg_temp_free_i64(t2);
2114 return EXIT_NORETURN;
2115 }
2116 #endif
2117
2118 static ExitStatus op_lam(DisasContext *s, DisasOps *o)
2119 {
2120 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2121 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2122 potential_page_fault(s);
2123 gen_helper_lam(cpu_env, r1, o->in2, r3);
2124 tcg_temp_free_i32(r1);
2125 tcg_temp_free_i32(r3);
2126 return NO_EXIT;
2127 }
2128
2129 static ExitStatus op_lm32(DisasContext *s, DisasOps *o)
2130 {
2131 int r1 = get_field(s->fields, r1);
2132 int r3 = get_field(s->fields, r3);
2133 TCGv_i64 t = tcg_temp_new_i64();
2134 TCGv_i64 t4 = tcg_const_i64(4);
2135
2136 while (1) {
2137 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2138 store_reg32_i64(r1, t);
2139 if (r1 == r3) {
2140 break;
2141 }
2142 tcg_gen_add_i64(o->in2, o->in2, t4);
2143 r1 = (r1 + 1) & 15;
2144 }
2145
2146 tcg_temp_free_i64(t);
2147 tcg_temp_free_i64(t4);
2148 return NO_EXIT;
2149 }
2150
2151 static ExitStatus op_lmh(DisasContext *s, DisasOps *o)
2152 {
2153 int r1 = get_field(s->fields, r1);
2154 int r3 = get_field(s->fields, r3);
2155 TCGv_i64 t = tcg_temp_new_i64();
2156 TCGv_i64 t4 = tcg_const_i64(4);
2157
2158 while (1) {
2159 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2160 store_reg32h_i64(r1, t);
2161 if (r1 == r3) {
2162 break;
2163 }
2164 tcg_gen_add_i64(o->in2, o->in2, t4);
2165 r1 = (r1 + 1) & 15;
2166 }
2167
2168 tcg_temp_free_i64(t);
2169 tcg_temp_free_i64(t4);
2170 return NO_EXIT;
2171 }
2172
2173 static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
2174 {
2175 int r1 = get_field(s->fields, r1);
2176 int r3 = get_field(s->fields, r3);
2177 TCGv_i64 t8 = tcg_const_i64(8);
2178
2179 while (1) {
2180 tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
2181 if (r1 == r3) {
2182 break;
2183 }
2184 tcg_gen_add_i64(o->in2, o->in2, t8);
2185 r1 = (r1 + 1) & 15;
2186 }
2187
2188 tcg_temp_free_i64(t8);
2189 return NO_EXIT;
2190 }
2191
2192 static ExitStatus op_mov2(DisasContext *s, DisasOps *o)
2193 {
2194 o->out = o->in2;
2195 o->g_out = o->g_in2;
2196 TCGV_UNUSED_I64(o->in2);
2197 o->g_in2 = false;
2198 return NO_EXIT;
2199 }
2200
2201 static ExitStatus op_movx(DisasContext *s, DisasOps *o)
2202 {
2203 o->out = o->in1;
2204 o->out2 = o->in2;
2205 o->g_out = o->g_in1;
2206 o->g_out2 = o->g_in2;
2207 TCGV_UNUSED_I64(o->in1);
2208 TCGV_UNUSED_I64(o->in2);
2209 o->g_in1 = o->g_in2 = false;
2210 return NO_EXIT;
2211 }
2212
2213 static ExitStatus op_mvc(DisasContext *s, DisasOps *o)
2214 {
2215 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2216 potential_page_fault(s);
2217 gen_helper_mvc(cpu_env, l, o->addr1, o->in2);
2218 tcg_temp_free_i32(l);
2219 return NO_EXIT;
2220 }
2221
2222 static ExitStatus op_mvcl(DisasContext *s, DisasOps *o)
2223 {
2224 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2225 TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
2226 potential_page_fault(s);
2227 gen_helper_mvcl(cc_op, cpu_env, r1, r2);
2228 tcg_temp_free_i32(r1);
2229 tcg_temp_free_i32(r2);
2230 set_cc_static(s);
2231 return NO_EXIT;
2232 }
2233
2234 static ExitStatus op_mvcle(DisasContext *s, DisasOps *o)
2235 {
2236 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2237 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2238 potential_page_fault(s);
2239 gen_helper_mvcle(cc_op, cpu_env, r1, o->in2, r3);
2240 tcg_temp_free_i32(r1);
2241 tcg_temp_free_i32(r3);
2242 set_cc_static(s);
2243 return NO_EXIT;
2244 }
2245
2246 #ifndef CONFIG_USER_ONLY
2247 static ExitStatus op_mvcp(DisasContext *s, DisasOps *o)
2248 {
2249 int r1 = get_field(s->fields, l1);
2250 check_privileged(s);
2251 potential_page_fault(s);
2252 gen_helper_mvcp(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2253 set_cc_static(s);
2254 return NO_EXIT;
2255 }
2256
2257 static ExitStatus op_mvcs(DisasContext *s, DisasOps *o)
2258 {
2259 int r1 = get_field(s->fields, l1);
2260 check_privileged(s);
2261 potential_page_fault(s);
2262 gen_helper_mvcs(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2263 set_cc_static(s);
2264 return NO_EXIT;
2265 }
2266 #endif
2267
2268 static ExitStatus op_mvpg(DisasContext *s, DisasOps *o)
2269 {
2270 potential_page_fault(s);
2271 gen_helper_mvpg(cpu_env, regs[0], o->in1, o->in2);
2272 set_cc_static(s);
2273 return NO_EXIT;
2274 }
2275
2276 static ExitStatus op_mvst(DisasContext *s, DisasOps *o)
2277 {
2278 potential_page_fault(s);
2279 gen_helper_mvst(o->in1, cpu_env, regs[0], o->in1, o->in2);
2280 set_cc_static(s);
2281 return_low128(o->in2);
2282 return NO_EXIT;
2283 }
2284
2285 static ExitStatus op_mul(DisasContext *s, DisasOps *o)
2286 {
2287 tcg_gen_mul_i64(o->out, o->in1, o->in2);
2288 return NO_EXIT;
2289 }
2290
2291 static ExitStatus op_mul128(DisasContext *s, DisasOps *o)
2292 {
2293 gen_helper_mul128(o->out, cpu_env, o->in1, o->in2);
2294 return_low128(o->out2);
2295 return NO_EXIT;
2296 }
2297
2298 static ExitStatus op_meeb(DisasContext *s, DisasOps *o)
2299 {
2300 gen_helper_meeb(o->out, cpu_env, o->in1, o->in2);
2301 return NO_EXIT;
2302 }
2303
2304 static ExitStatus op_mdeb(DisasContext *s, DisasOps *o)
2305 {
2306 gen_helper_mdeb(o->out, cpu_env, o->in1, o->in2);
2307 return NO_EXIT;
2308 }
2309
2310 static ExitStatus op_mdb(DisasContext *s, DisasOps *o)
2311 {
2312 gen_helper_mdb(o->out, cpu_env, o->in1, o->in2);
2313 return NO_EXIT;
2314 }
2315
2316 static ExitStatus op_mxb(DisasContext *s, DisasOps *o)
2317 {
2318 gen_helper_mxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2319 return_low128(o->out2);
2320 return NO_EXIT;
2321 }
2322
2323 static ExitStatus op_mxdb(DisasContext *s, DisasOps *o)
2324 {
2325 gen_helper_mxdb(o->out, cpu_env, o->out, o->out2, o->in2);
2326 return_low128(o->out2);
2327 return NO_EXIT;
2328 }
2329
2330 static ExitStatus op_maeb(DisasContext *s, DisasOps *o)
2331 {
2332 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2333 gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3);
2334 tcg_temp_free_i64(r3);
2335 return NO_EXIT;
2336 }
2337
2338 static ExitStatus op_madb(DisasContext *s, DisasOps *o)
2339 {
2340 int r3 = get_field(s->fields, r3);
2341 gen_helper_madb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2342 return NO_EXIT;
2343 }
2344
2345 static ExitStatus op_mseb(DisasContext *s, DisasOps *o)
2346 {
2347 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2348 gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3);
2349 tcg_temp_free_i64(r3);
2350 return NO_EXIT;
2351 }
2352
2353 static ExitStatus op_msdb(DisasContext *s, DisasOps *o)
2354 {
2355 int r3 = get_field(s->fields, r3);
2356 gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2357 return NO_EXIT;
2358 }
2359
2360 static ExitStatus op_nabs(DisasContext *s, DisasOps *o)
2361 {
2362 gen_helper_nabs_i64(o->out, o->in2);
2363 return NO_EXIT;
2364 }
2365
2366 static ExitStatus op_nabsf32(DisasContext *s, DisasOps *o)
2367 {
2368 tcg_gen_ori_i64(o->out, o->in2, 0x80000000ull);
2369 return NO_EXIT;
2370 }
2371
2372 static ExitStatus op_nabsf64(DisasContext *s, DisasOps *o)
2373 {
2374 tcg_gen_ori_i64(o->out, o->in2, 0x8000000000000000ull);
2375 return NO_EXIT;
2376 }
2377
2378 static ExitStatus op_nabsf128(DisasContext *s, DisasOps *o)
2379 {
2380 tcg_gen_ori_i64(o->out, o->in1, 0x8000000000000000ull);
2381 tcg_gen_mov_i64(o->out2, o->in2);
2382 return NO_EXIT;
2383 }
2384
2385 static ExitStatus op_nc(DisasContext *s, DisasOps *o)
2386 {
2387 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2388 potential_page_fault(s);
2389 gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2);
2390 tcg_temp_free_i32(l);
2391 set_cc_static(s);
2392 return NO_EXIT;
2393 }
2394
2395 static ExitStatus op_neg(DisasContext *s, DisasOps *o)
2396 {
2397 tcg_gen_neg_i64(o->out, o->in2);
2398 return NO_EXIT;
2399 }
2400
2401 static ExitStatus op_negf32(DisasContext *s, DisasOps *o)
2402 {
2403 tcg_gen_xori_i64(o->out, o->in2, 0x80000000ull);
2404 return NO_EXIT;
2405 }
2406
2407 static ExitStatus op_negf64(DisasContext *s, DisasOps *o)
2408 {
2409 tcg_gen_xori_i64(o->out, o->in2, 0x8000000000000000ull);
2410 return NO_EXIT;
2411 }
2412
2413 static ExitStatus op_negf128(DisasContext *s, DisasOps *o)
2414 {
2415 tcg_gen_xori_i64(o->out, o->in1, 0x8000000000000000ull);
2416 tcg_gen_mov_i64(o->out2, o->in2);
2417 return NO_EXIT;
2418 }
2419
2420 static ExitStatus op_oc(DisasContext *s, DisasOps *o)
2421 {
2422 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2423 potential_page_fault(s);
2424 gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2);
2425 tcg_temp_free_i32(l);
2426 set_cc_static(s);
2427 return NO_EXIT;
2428 }
2429
2430 static ExitStatus op_or(DisasContext *s, DisasOps *o)
2431 {
2432 tcg_gen_or_i64(o->out, o->in1, o->in2);
2433 return NO_EXIT;
2434 }
2435
2436 static ExitStatus op_ori(DisasContext *s, DisasOps *o)
2437 {
2438 int shift = s->insn->data & 0xff;
2439 int size = s->insn->data >> 8;
2440 uint64_t mask = ((1ull << size) - 1) << shift;
2441
2442 assert(!o->g_in2);
2443 tcg_gen_shli_i64(o->in2, o->in2, shift);
2444 tcg_gen_or_i64(o->out, o->in1, o->in2);
2445
2446 /* Produce the CC from only the bits manipulated. */
2447 tcg_gen_andi_i64(cc_dst, o->out, mask);
2448 set_cc_nz_u64(s, cc_dst);
2449 return NO_EXIT;
2450 }
2451
2452 #ifndef CONFIG_USER_ONLY
2453 static ExitStatus op_ptlb(DisasContext *s, DisasOps *o)
2454 {
2455 check_privileged(s);
2456 gen_helper_ptlb(cpu_env);
2457 return NO_EXIT;
2458 }
2459 #endif
2460
2461 static ExitStatus op_risbg(DisasContext *s, DisasOps *o)
2462 {
2463 int i3 = get_field(s->fields, i3);
2464 int i4 = get_field(s->fields, i4);
2465 int i5 = get_field(s->fields, i5);
2466 int do_zero = i4 & 0x80;
2467 uint64_t mask, imask, pmask;
2468 int pos, len, rot;
2469
2470 /* Adjust the arguments for the specific insn. */
2471 switch (s->fields->op2) {
2472 case 0x55: /* risbg */
2473 i3 &= 63;
2474 i4 &= 63;
2475 pmask = ~0;
2476 break;
2477 case 0x5d: /* risbhg */
2478 i3 &= 31;
2479 i4 &= 31;
2480 pmask = 0xffffffff00000000ull;
2481 break;
2482 case 0x51: /* risblg */
2483 i3 &= 31;
2484 i4 &= 31;
2485 pmask = 0x00000000ffffffffull;
2486 break;
2487 default:
2488 abort();
2489 }
2490
2491 /* MASK is the set of bits to be inserted from R2.
2492 Take care for I3/I4 wraparound. */
2493 mask = pmask >> i3;
2494 if (i3 <= i4) {
2495 mask ^= pmask >> i4 >> 1;
2496 } else {
2497 mask |= ~(pmask >> i4 >> 1);
2498 }
2499 mask &= pmask;
2500
2501 /* IMASK is the set of bits to be kept from R1. In the case of the high/low
2502 insns, we need to keep the other half of the register. */
2503 imask = ~mask | ~pmask;
2504 if (do_zero) {
2505 if (s->fields->op2 == 0x55) {
2506 imask = 0;
2507 } else {
2508 imask = ~pmask;
2509 }
2510 }
2511
2512 /* In some cases we can implement this with deposit, which can be more
2513 efficient on some hosts. */
2514 if (~mask == imask && i3 <= i4) {
2515 if (s->fields->op2 == 0x5d) {
2516 i3 += 32, i4 += 32;
2517 }
2518 /* Note that we rotate the bits to be inserted to the lsb, not to
2519 the position as described in the PoO. */
2520 len = i4 - i3 + 1;
2521 pos = 63 - i4;
2522 rot = (i5 - pos) & 63;
2523 } else {
2524 pos = len = -1;
2525 rot = i5 & 63;
2526 }
2527
2528 /* Rotate the input as necessary. */
2529 tcg_gen_rotli_i64(o->in2, o->in2, rot);
2530
2531 /* Insert the selected bits into the output. */
2532 if (pos >= 0) {
2533 tcg_gen_deposit_i64(o->out, o->out, o->in2, pos, len);
2534 } else if (imask == 0) {
2535 tcg_gen_andi_i64(o->out, o->in2, mask);
2536 } else {
2537 tcg_gen_andi_i64(o->in2, o->in2, mask);
2538 tcg_gen_andi_i64(o->out, o->out, imask);
2539 tcg_gen_or_i64(o->out, o->out, o->in2);
2540 }
2541 return NO_EXIT;
2542 }
2543
2544 static ExitStatus op_rosbg(DisasContext *s, DisasOps *o)
2545 {
2546 int i3 = get_field(s->fields, i3);
2547 int i4 = get_field(s->fields, i4);
2548 int i5 = get_field(s->fields, i5);
2549 uint64_t mask;
2550
2551 /* If this is a test-only form, arrange to discard the result. */
2552 if (i3 & 0x80) {
2553 o->out = tcg_temp_new_i64();
2554 o->g_out = false;
2555 }
2556
2557 i3 &= 63;
2558 i4 &= 63;
2559 i5 &= 63;
2560
2561 /* MASK is the set of bits to be operated on from R2.
2562 Take care for I3/I4 wraparound. */
2563 mask = ~0ull >> i3;
2564 if (i3 <= i4) {
2565 mask ^= ~0ull >> i4 >> 1;
2566 } else {
2567 mask |= ~(~0ull >> i4 >> 1);
2568 }
2569
2570 /* Rotate the input as necessary. */
2571 tcg_gen_rotli_i64(o->in2, o->in2, i5);
2572
2573 /* Operate. */
2574 switch (s->fields->op2) {
2575 case 0x55: /* AND */
2576 tcg_gen_ori_i64(o->in2, o->in2, ~mask);
2577 tcg_gen_and_i64(o->out, o->out, o->in2);
2578 break;
2579 case 0x56: /* OR */
2580 tcg_gen_andi_i64(o->in2, o->in2, mask);
2581 tcg_gen_or_i64(o->out, o->out, o->in2);
2582 break;
2583 case 0x57: /* XOR */
2584 tcg_gen_andi_i64(o->in2, o->in2, mask);
2585 tcg_gen_xor_i64(o->out, o->out, o->in2);
2586 break;
2587 default:
2588 abort();
2589 }
2590
2591 /* Set the CC. */
2592 tcg_gen_andi_i64(cc_dst, o->out, mask);
2593 set_cc_nz_u64(s, cc_dst);
2594 return NO_EXIT;
2595 }
2596
2597 static ExitStatus op_rev16(DisasContext *s, DisasOps *o)
2598 {
2599 tcg_gen_bswap16_i64(o->out, o->in2);
2600 return NO_EXIT;
2601 }
2602
2603 static ExitStatus op_rev32(DisasContext *s, DisasOps *o)
2604 {
2605 tcg_gen_bswap32_i64(o->out, o->in2);
2606 return NO_EXIT;
2607 }
2608
2609 static ExitStatus op_rev64(DisasContext *s, DisasOps *o)
2610 {
2611 tcg_gen_bswap64_i64(o->out, o->in2);
2612 return NO_EXIT;
2613 }
2614
2615 static ExitStatus op_rll32(DisasContext *s, DisasOps *o)
2616 {
2617 TCGv_i32 t1 = tcg_temp_new_i32();
2618 TCGv_i32 t2 = tcg_temp_new_i32();
2619 TCGv_i32 to = tcg_temp_new_i32();
2620 tcg_gen_trunc_i64_i32(t1, o->in1);
2621 tcg_gen_trunc_i64_i32(t2, o->in2);
2622 tcg_gen_rotl_i32(to, t1, t2);
2623 tcg_gen_extu_i32_i64(o->out, to);
2624 tcg_temp_free_i32(t1);
2625 tcg_temp_free_i32(t2);
2626 tcg_temp_free_i32(to);
2627 return NO_EXIT;
2628 }
2629
2630 static ExitStatus op_rll64(DisasContext *s, DisasOps *o)
2631 {
2632 tcg_gen_rotl_i64(o->out, o->in1, o->in2);
2633 return NO_EXIT;
2634 }
2635
2636 #ifndef CONFIG_USER_ONLY
2637 static ExitStatus op_rrbe(DisasContext *s, DisasOps *o)
2638 {
2639 check_privileged(s);
2640 gen_helper_rrbe(cc_op, cpu_env, o->in2);
2641 set_cc_static(s);
2642 return NO_EXIT;
2643 }
2644
2645 static ExitStatus op_sacf(DisasContext *s, DisasOps *o)
2646 {
2647 check_privileged(s);
2648 gen_helper_sacf(cpu_env, o->in2);
2649 /* Addressing mode has changed, so end the block. */
2650 return EXIT_PC_STALE;
2651 }
2652 #endif
2653
2654 static ExitStatus op_sar(DisasContext *s, DisasOps *o)
2655 {
2656 int r1 = get_field(s->fields, r1);
2657 tcg_gen_st32_i64(o->in2, cpu_env, offsetof(CPUS390XState, aregs[r1]));
2658 return NO_EXIT;
2659 }
2660
2661 static ExitStatus op_seb(DisasContext *s, DisasOps *o)
2662 {
2663 gen_helper_seb(o->out, cpu_env, o->in1, o->in2);
2664 return NO_EXIT;
2665 }
2666
2667 static ExitStatus op_sdb(DisasContext *s, DisasOps *o)
2668 {
2669 gen_helper_sdb(o->out, cpu_env, o->in1, o->in2);
2670 return NO_EXIT;
2671 }
2672
2673 static ExitStatus op_sxb(DisasContext *s, DisasOps *o)
2674 {
2675 gen_helper_sxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2676 return_low128(o->out2);
2677 return NO_EXIT;
2678 }
2679
2680 static ExitStatus op_sqeb(DisasContext *s, DisasOps *o)
2681 {
2682 gen_helper_sqeb(o->out, cpu_env, o->in2);
2683 return NO_EXIT;
2684 }
2685
2686 static ExitStatus op_sqdb(DisasContext *s, DisasOps *o)
2687 {
2688 gen_helper_sqdb(o->out, cpu_env, o->in2);
2689 return NO_EXIT;
2690 }
2691
2692 static ExitStatus op_sqxb(DisasContext *s, DisasOps *o)
2693 {
2694 gen_helper_sqxb(o->out, cpu_env, o->in1, o->in2);
2695 return_low128(o->out2);
2696 return NO_EXIT;
2697 }
2698
2699 #ifndef CONFIG_USER_ONLY
2700 static ExitStatus op_servc(DisasContext *s, DisasOps *o)
2701 {
2702 check_privileged(s);
2703 potential_page_fault(s);
2704 gen_helper_servc(cc_op, cpu_env, o->in2, o->in1);
2705 set_cc_static(s);
2706 return NO_EXIT;
2707 }
2708
2709 static ExitStatus op_sigp(DisasContext *s, DisasOps *o)
2710 {
2711 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2712 check_privileged(s);
2713 potential_page_fault(s);
2714 gen_helper_sigp(cc_op, cpu_env, o->in2, r1, o->in1);
2715 tcg_temp_free_i32(r1);
2716 return NO_EXIT;
2717 }
2718 #endif
2719
2720 static ExitStatus op_sla(DisasContext *s, DisasOps *o)
2721 {
2722 uint64_t sign = 1ull << s->insn->data;
2723 enum cc_op cco = s->insn->data == 31 ? CC_OP_SLA_32 : CC_OP_SLA_64;
2724 gen_op_update2_cc_i64(s, cco, o->in1, o->in2);
2725 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2726 /* The arithmetic left shift is curious in that it does not affect
2727 the sign bit. Copy that over from the source unchanged. */
2728 tcg_gen_andi_i64(o->out, o->out, ~sign);
2729 tcg_gen_andi_i64(o->in1, o->in1, sign);
2730 tcg_gen_or_i64(o->out, o->out, o->in1);
2731 return NO_EXIT;
2732 }
2733
2734 static ExitStatus op_sll(DisasContext *s, DisasOps *o)
2735 {
2736 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2737 return NO_EXIT;
2738 }
2739
2740 static ExitStatus op_sra(DisasContext *s, DisasOps *o)
2741 {
2742 tcg_gen_sar_i64(o->out, o->in1, o->in2);
2743 return NO_EXIT;
2744 }
2745
2746 static ExitStatus op_srl(DisasContext *s, DisasOps *o)
2747 {
2748 tcg_gen_shr_i64(o->out, o->in1, o->in2);
2749 return NO_EXIT;
2750 }
2751
2752 static ExitStatus op_sfpc(DisasContext *s, DisasOps *o)
2753 {
2754 gen_helper_sfpc(cpu_env, o->in2);
2755 return NO_EXIT;
2756 }
2757
2758 #ifndef CONFIG_USER_ONLY
2759 static ExitStatus op_spka(DisasContext *s, DisasOps *o)
2760 {
2761 check_privileged(s);
2762 tcg_gen_shri_i64(o->in2, o->in2, 4);
2763 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, PSW_SHIFT_KEY - 4, 4);
2764 return NO_EXIT;
2765 }
2766
2767 static ExitStatus op_sske(DisasContext *s, DisasOps *o)
2768 {
2769 check_privileged(s);
2770 gen_helper_sske(cpu_env, o->in1, o->in2);
2771 return NO_EXIT;
2772 }
2773
2774 static ExitStatus op_ssm(DisasContext *s, DisasOps *o)
2775 {
2776 check_privileged(s);
2777 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8);
2778 return NO_EXIT;
2779 }
2780
2781 static ExitStatus op_stap(DisasContext *s, DisasOps *o)
2782 {
2783 check_privileged(s);
2784 /* ??? Surely cpu address != cpu number. In any case the previous
2785 version of this stored more than the required half-word, so it
2786 is unlikely this has ever been tested. */
2787 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num));
2788 return NO_EXIT;
2789 }
2790
2791 static ExitStatus op_stck(DisasContext *s, DisasOps *o)
2792 {
2793 gen_helper_stck(o->out, cpu_env);
2794 /* ??? We don't implement clock states. */
2795 gen_op_movi_cc(s, 0);
2796 return NO_EXIT;
2797 }
2798
2799 static ExitStatus op_stcke(DisasContext *s, DisasOps *o)
2800 {
2801 TCGv_i64 c1 = tcg_temp_new_i64();
2802 TCGv_i64 c2 = tcg_temp_new_i64();
2803 gen_helper_stck(c1, cpu_env);
2804 /* Shift the 64-bit value into its place as a zero-extended
2805 104-bit value. Note that "bit positions 64-103 are always
2806 non-zero so that they compare differently to STCK"; we set
2807 the least significant bit to 1. */
2808 tcg_gen_shli_i64(c2, c1, 56);
2809 tcg_gen_shri_i64(c1, c1, 8);
2810 tcg_gen_ori_i64(c2, c2, 0x10000);
2811 tcg_gen_qemu_st64(c1, o->in2, get_mem_index(s));
2812 tcg_gen_addi_i64(o->in2, o->in2, 8);
2813 tcg_gen_qemu_st64(c2, o->in2, get_mem_index(s));
2814 tcg_temp_free_i64(c1);
2815 tcg_temp_free_i64(c2);
2816 /* ??? We don't implement clock states. */
2817 gen_op_movi_cc(s, 0);
2818 return NO_EXIT;
2819 }
2820
2821 static ExitStatus op_sckc(DisasContext *s, DisasOps *o)
2822 {
2823 check_privileged(s);
2824 gen_helper_sckc(cpu_env, o->in2);
2825 return NO_EXIT;
2826 }
2827
2828 static ExitStatus op_stckc(DisasContext *s, DisasOps *o)
2829 {
2830 check_privileged(s);
2831 gen_helper_stckc(o->out, cpu_env);
2832 return NO_EXIT;
2833 }
2834
2835 static ExitStatus op_stctg(DisasContext *s, DisasOps *o)
2836 {
2837 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2838 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2839 check_privileged(s);
2840 potential_page_fault(s);
2841 gen_helper_stctg(cpu_env, r1, o->in2, r3);
2842 tcg_temp_free_i32(r1);
2843 tcg_temp_free_i32(r3);
2844 return NO_EXIT;
2845 }
2846
2847 static ExitStatus op_stctl(DisasContext *s, DisasOps *o)
2848 {
2849 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2850 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2851 check_privileged(s);
2852 potential_page_fault(s);
2853 gen_helper_stctl(cpu_env, r1, o->in2, r3);
2854 tcg_temp_free_i32(r1);
2855 tcg_temp_free_i32(r3);
2856 return NO_EXIT;
2857 }
2858
2859 static ExitStatus op_stidp(DisasContext *s, DisasOps *o)
2860 {
2861 check_privileged(s);
2862 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num));
2863 return NO_EXIT;
2864 }
2865
2866 static ExitStatus op_spt(DisasContext *s, DisasOps *o)
2867 {
2868 check_privileged(s);
2869 gen_helper_spt(cpu_env, o->in2);
2870 return NO_EXIT;
2871 }
2872
2873 static ExitStatus op_stfl(DisasContext *s, DisasOps *o)
2874 {
2875 TCGv_i64 f, a;
2876 /* We really ought to have more complete indication of facilities
2877 that we implement. Address this when STFLE is implemented. */
2878 check_privileged(s);
2879 f = tcg_const_i64(0xc0000000);
2880 a = tcg_const_i64(200);
2881 tcg_gen_qemu_st32(f, a, get_mem_index(s));
2882 tcg_temp_free_i64(f);
2883 tcg_temp_free_i64(a);
2884 return NO_EXIT;
2885 }
2886
2887 static ExitStatus op_stpt(DisasContext *s, DisasOps *o)
2888 {
2889 check_privileged(s);
2890 gen_helper_stpt(o->out, cpu_env);
2891 return NO_EXIT;
2892 }
2893
2894 static ExitStatus op_stsi(DisasContext *s, DisasOps *o)
2895 {
2896 check_privileged(s);
2897 potential_page_fault(s);
2898 gen_helper_stsi(cc_op, cpu_env, o->in2, regs[0], regs[1]);
2899 set_cc_static(s);
2900 return NO_EXIT;
2901 }
2902
2903 static ExitStatus op_spx(DisasContext *s, DisasOps *o)
2904 {
2905 check_privileged(s);
2906 gen_helper_spx(cpu_env, o->in2);
2907 return NO_EXIT;
2908 }
2909
2910 static ExitStatus op_subchannel(DisasContext *s, DisasOps *o)
2911 {
2912 check_privileged(s);
2913 /* Not operational. */
2914 gen_op_movi_cc(s, 3);
2915 return NO_EXIT;
2916 }
2917
2918 static ExitStatus op_stpx(DisasContext *s, DisasOps *o)
2919 {
2920 check_privileged(s);
2921 tcg_gen_ld_i64(o->out, cpu_env, offsetof(CPUS390XState, psa));
2922 tcg_gen_andi_i64(o->out, o->out, 0x7fffe000);
2923 return NO_EXIT;
2924 }
2925
2926 static ExitStatus op_stnosm(DisasContext *s, DisasOps *o)
2927 {
2928 uint64_t i2 = get_field(s->fields, i2);
2929 TCGv_i64 t;
2930
2931 check_privileged(s);
2932
2933 /* It is important to do what the instruction name says: STORE THEN.
2934 If we let the output hook perform the store then if we fault and
2935 restart, we'll have the wrong SYSTEM MASK in place. */
2936 t = tcg_temp_new_i64();
2937 tcg_gen_shri_i64(t, psw_mask, 56);
2938 tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
2939 tcg_temp_free_i64(t);
2940
2941 if (s->fields->op == 0xac) {
2942 tcg_gen_andi_i64(psw_mask, psw_mask,
2943 (i2 << 56) | 0x00ffffffffffffffull);
2944 } else {
2945 tcg_gen_ori_i64(psw_mask, psw_mask, i2 << 56);
2946 }
2947 return NO_EXIT;
2948 }
2949
2950 static ExitStatus op_stura(DisasContext *s, DisasOps *o)
2951 {
2952 check_privileged(s);
2953 potential_page_fault(s);
2954 gen_helper_stura(cpu_env, o->in2, o->in1);
2955 return NO_EXIT;
2956 }
2957 #endif
2958
2959 static ExitStatus op_st8(DisasContext *s, DisasOps *o)
2960 {
2961 tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));
2962 return NO_EXIT;
2963 }
2964
2965 static ExitStatus op_st16(DisasContext *s, DisasOps *o)
2966 {
2967 tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s));
2968 return NO_EXIT;
2969 }
2970
2971 static ExitStatus op_st32(DisasContext *s, DisasOps *o)
2972 {
2973 tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s));
2974 return NO_EXIT;
2975 }
2976
2977 static ExitStatus op_st64(DisasContext *s, DisasOps *o)
2978 {
2979 tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s));
2980 return NO_EXIT;
2981 }
2982
2983 static ExitStatus op_stam(DisasContext *s, DisasOps *o)
2984 {
2985 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2986 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2987 potential_page_fault(s);
2988 gen_helper_stam(cpu_env, r1, o->in2, r3);
2989 tcg_temp_free_i32(r1);
2990 tcg_temp_free_i32(r3);
2991 return NO_EXIT;
2992 }
2993
2994 static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
2995 {
2996 int m3 = get_field(s->fields, m3);
2997 int pos, base = s->insn->data;
2998 TCGv_i64 tmp = tcg_temp_new_i64();
2999
3000 pos = base + ctz32(m3) * 8;
3001 switch (m3) {
3002 case 0xf:
3003 /* Effectively a 32-bit store. */
3004 tcg_gen_shri_i64(tmp, o->in1, pos);
3005 tcg_gen_qemu_st32(tmp, o->in2, get_mem_index(s));
3006 break;
3007
3008 case 0xc:
3009 case 0x6:
3010 case 0x3:
3011 /* Effectively a 16-bit store. */
3012 tcg_gen_shri_i64(tmp, o->in1, pos);
3013 tcg_gen_qemu_st16(tmp, o->in2, get_mem_index(s));
3014 break;
3015
3016 case 0x8:
3017 case 0x4:
3018 case 0x2:
3019 case 0x1:
3020 /* Effectively an 8-bit store. */
3021 tcg_gen_shri_i64(tmp, o->in1, pos);
3022 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3023 break;
3024
3025 default:
3026 /* This is going to be a sequence of shifts and stores. */
3027 pos = base + 32 - 8;
3028 while (m3) {
3029 if (m3 & 0x8) {
3030 tcg_gen_shri_i64(tmp, o->in1, pos);
3031 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3032 tcg_gen_addi_i64(o->in2, o->in2, 1);
3033 }
3034 m3 = (m3 << 1) & 0xf;
3035 pos -= 8;
3036 }
3037 break;
3038 }
3039 tcg_temp_free_i64(tmp);
3040 return NO_EXIT;
3041 }
3042
3043 static ExitStatus op_stm(DisasContext *s, DisasOps *o)
3044 {
3045 int r1 = get_field(s->fields, r1);
3046 int r3 = get_field(s->fields, r3);
3047 int size = s->insn->data;
3048 TCGv_i64 tsize = tcg_const_i64(size);
3049
3050 while (1) {
3051 if (size == 8) {
3052 tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s));
3053 } else {
3054 tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s));
3055 }
3056 if (r1 == r3) {
3057 break;
3058 }
3059 tcg_gen_add_i64(o->in2, o->in2, tsize);
3060 r1 = (r1 + 1) & 15;
3061 }
3062
3063 tcg_temp_free_i64(tsize);
3064 return NO_EXIT;
3065 }
3066
3067 static ExitStatus op_stmh(DisasContext *s, DisasOps *o)
3068 {
3069 int r1 = get_field(s->fields, r1);
3070 int r3 = get_field(s->fields, r3);
3071 TCGv_i64 t = tcg_temp_new_i64();
3072 TCGv_i64 t4 = tcg_const_i64(4);
3073 TCGv_i64 t32 = tcg_const_i64(32);
3074
3075 while (1) {
3076 tcg_gen_shl_i64(t, regs[r1], t32);
3077 tcg_gen_qemu_st32(t, o->in2, get_mem_index(s));
3078 if (r1 == r3) {
3079 break;
3080 }
3081 tcg_gen_add_i64(o->in2, o->in2, t4);
3082 r1 = (r1 + 1) & 15;
3083 }
3084
3085 tcg_temp_free_i64(t);
3086 tcg_temp_free_i64(t4);
3087 tcg_temp_free_i64(t32);
3088 return NO_EXIT;
3089 }
3090
3091 static ExitStatus op_srst(DisasContext *s, DisasOps *o)
3092 {
3093 potential_page_fault(s);
3094 gen_helper_srst(o->in1, cpu_env, regs[0], o->in1, o->in2);
3095 set_cc_static(s);
3096 return_low128(o->in2);
3097 return NO_EXIT;
3098 }
3099
3100 static ExitStatus op_sub(DisasContext *s, DisasOps *o)
3101 {
3102 tcg_gen_sub_i64(o->out, o->in1, o->in2);
3103 return NO_EXIT;
3104 }
3105
3106 static ExitStatus op_subb(DisasContext *s, DisasOps *o)
3107 {
3108 TCGv_i64 cc;
3109
3110 assert(!o->g_in2);
3111 tcg_gen_not_i64(o->in2, o->in2);
3112 tcg_gen_add_i64(o->out, o->in1, o->in2);
3113
3114 /* XXX possible optimization point */
3115 gen_op_calc_cc(s);
3116 cc = tcg_temp_new_i64();
3117 tcg_gen_extu_i32_i64(cc, cc_op);
3118 tcg_gen_shri_i64(cc, cc, 1);
3119 tcg_gen_add_i64(o->out, o->out, cc);
3120 tcg_temp_free_i64(cc);
3121 return NO_EXIT;
3122 }
3123
3124 static ExitStatus op_svc(DisasContext *s, DisasOps *o)
3125 {
3126 TCGv_i32 t;
3127
3128 update_psw_addr(s);
3129 update_cc_op(s);
3130
3131 t = tcg_const_i32(get_field(s->fields, i1) & 0xff);
3132 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code));
3133 tcg_temp_free_i32(t);
3134
3135 t = tcg_const_i32(s->next_pc - s->pc);
3136 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen));
3137 tcg_temp_free_i32(t);
3138
3139 gen_exception(EXCP_SVC);
3140 return EXIT_NORETURN;
3141 }
3142
3143 static ExitStatus op_tceb(DisasContext *s, DisasOps *o)
3144 {
3145 gen_helper_tceb(cc_op, o->in1, o->in2);
3146 set_cc_static(s);
3147 return NO_EXIT;
3148 }
3149
3150 static ExitStatus op_tcdb(DisasContext *s, DisasOps *o)
3151 {
3152 gen_helper_tcdb(cc_op, o->in1, o->in2);
3153 set_cc_static(s);
3154 return NO_EXIT;
3155 }
3156
3157 static ExitStatus op_tcxb(DisasContext *s, DisasOps *o)
3158 {
3159 gen_helper_tcxb(cc_op, o->out, o->out2, o->in2);
3160 set_cc_static(s);
3161 return NO_EXIT;
3162 }
3163
3164 #ifndef CONFIG_USER_ONLY
3165 static ExitStatus op_tprot(DisasContext *s, DisasOps *o)
3166 {
3167 potential_page_fault(s);
3168 gen_helper_tprot(cc_op, o->addr1, o->in2);
3169 set_cc_static(s);
3170 return NO_EXIT;
3171 }
3172 #endif
3173
3174 static ExitStatus op_tr(DisasContext *s, DisasOps *o)
3175 {
3176 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3177 potential_page_fault(s);
3178 gen_helper_tr(cpu_env, l, o->addr1, o->in2);
3179 tcg_temp_free_i32(l);
3180 set_cc_static(s);
3181 return NO_EXIT;
3182 }
3183
3184 static ExitStatus op_unpk(DisasContext *s, DisasOps *o)
3185 {
3186 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3187 potential_page_fault(s);
3188 gen_helper_unpk(cpu_env, l, o->addr1, o->in2);
3189 tcg_temp_free_i32(l);
3190 return NO_EXIT;
3191 }
3192
3193 static ExitStatus op_xc(DisasContext *s, DisasOps *o)
3194 {
3195 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3196 potential_page_fault(s);
3197 gen_helper_xc(cc_op, cpu_env, l, o->addr1, o->in2);
3198 tcg_temp_free_i32(l);
3199 set_cc_static(s);
3200 return NO_EXIT;
3201 }
3202
3203 static ExitStatus op_xor(DisasContext *s, DisasOps *o)
3204 {
3205 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3206 return NO_EXIT;
3207 }
3208
3209 static ExitStatus op_xori(DisasContext *s, DisasOps *o)
3210 {
3211 int shift = s->insn->data & 0xff;
3212 int size = s->insn->data >> 8;
3213 uint64_t mask = ((1ull << size) - 1) << shift;
3214
3215 assert(!o->g_in2);
3216 tcg_gen_shli_i64(o->in2, o->in2, shift);
3217 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3218
3219 /* Produce the CC from only the bits manipulated. */
3220 tcg_gen_andi_i64(cc_dst, o->out, mask);
3221 set_cc_nz_u64(s, cc_dst);
3222 return NO_EXIT;
3223 }
3224
3225 static ExitStatus op_zero(DisasContext *s, DisasOps *o)
3226 {
3227 o->out = tcg_const_i64(0);
3228 return NO_EXIT;
3229 }
3230
3231 static ExitStatus op_zero2(DisasContext *s, DisasOps *o)
3232 {
3233 o->out = tcg_const_i64(0);
3234 o->out2 = o->out;
3235 o->g_out2 = true;
3236 return NO_EXIT;
3237 }
3238
3239 /* ====================================================================== */
3240 /* The "Cc OUTput" generators. Given the generated output (and in some cases
3241 the original inputs), update the various cc data structures in order to
3242 be able to compute the new condition code. */
3243
3244 static void cout_abs32(DisasContext *s, DisasOps *o)
3245 {
3246 gen_op_update1_cc_i64(s, CC_OP_ABS_32, o->out);
3247 }
3248
3249 static void cout_abs64(DisasContext *s, DisasOps *o)
3250 {
3251 gen_op_update1_cc_i64(s, CC_OP_ABS_64, o->out);
3252 }
3253
3254 static void cout_adds32(DisasContext *s, DisasOps *o)
3255 {
3256 gen_op_update3_cc_i64(s, CC_OP_ADD_32, o->in1, o->in2, o->out);
3257 }
3258
3259 static void cout_adds64(DisasContext *s, DisasOps *o)
3260 {
3261 gen_op_update3_cc_i64(s, CC_OP_ADD_64, o->in1, o->in2, o->out);
3262 }
3263
3264 static void cout_addu32(DisasContext *s, DisasOps *o)
3265 {
3266 gen_op_update3_cc_i64(s, CC_OP_ADDU_32, o->in1, o->in2, o->out);
3267 }
3268
3269 static void cout_addu64(DisasContext *s, DisasOps *o)
3270 {
3271 gen_op_update3_cc_i64(s, CC_OP_ADDU_64, o->in1, o->in2, o->out);
3272 }
3273
3274 static void cout_addc32(DisasContext *s, DisasOps *o)
3275 {
3276 gen_op_update3_cc_i64(s, CC_OP_ADDC_32, o->in1, o->in2, o->out);
3277 }
3278
3279 static void cout_addc64(DisasContext *s, DisasOps *o)
3280 {
3281 gen_op_update3_cc_i64(s, CC_OP_ADDC_64, o->in1, o->in2, o->out);
3282 }
3283
3284 static void cout_cmps32(DisasContext *s, DisasOps *o)
3285 {
3286 gen_op_update2_cc_i64(s, CC_OP_LTGT_32, o->in1, o->in2);
3287 }
3288
3289 static void cout_cmps64(DisasContext *s, DisasOps *o)
3290 {
3291 gen_op_update2_cc_i64(s, CC_OP_LTGT_64, o->in1, o->in2);
3292 }
3293
3294 static void cout_cmpu32(DisasContext *s, DisasOps *o)
3295 {
3296 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_32, o->in1, o->in2);
3297 }
3298
3299 static void cout_cmpu64(DisasContext *s, DisasOps *o)
3300 {
3301 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, o->in1, o->in2);
3302 }
3303
3304 static void cout_f32(DisasContext *s, DisasOps *o)
3305 {
3306 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, o->out);
3307 }
3308
3309 static void cout_f64(DisasContext *s, DisasOps *o)
3310 {
3311 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, o->out);
3312 }
3313
3314 static void cout_f128(DisasContext *s, DisasOps *o)
3315 {
3316 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, o->out, o->out2);
3317 }
3318
3319 static void cout_nabs32(DisasContext *s, DisasOps *o)
3320 {
3321 gen_op_update1_cc_i64(s, CC_OP_NABS_32, o->out);
3322 }
3323
3324 static void cout_nabs64(DisasContext *s, DisasOps *o)
3325 {
3326 gen_op_update1_cc_i64(s, CC_OP_NABS_64, o->out);
3327 }
3328
3329 static void cout_neg32(DisasContext *s, DisasOps *o)
3330 {
3331 gen_op_update1_cc_i64(s, CC_OP_COMP_32, o->out);
3332 }
3333
3334 static void cout_neg64(DisasContext *s, DisasOps *o)
3335 {
3336 gen_op_update1_cc_i64(s, CC_OP_COMP_64, o->out);
3337 }
3338
3339 static void cout_nz32(DisasContext *s, DisasOps *o)
3340 {
3341 tcg_gen_ext32u_i64(cc_dst, o->out);
3342 gen_op_update1_cc_i64(s, CC_OP_NZ, cc_dst);
3343 }
3344
3345 static void cout_nz64(DisasContext *s, DisasOps *o)
3346 {
3347 gen_op_update1_cc_i64(s, CC_OP_NZ, o->out);
3348 }
3349
3350 static void cout_s32(DisasContext *s, DisasOps *o)
3351 {
3352 gen_op_update1_cc_i64(s, CC_OP_LTGT0_32, o->out);
3353 }
3354
3355 static void cout_s64(DisasContext *s, DisasOps *o)
3356 {
3357 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, o->out);
3358 }
3359
3360 static void cout_subs32(DisasContext *s, DisasOps *o)
3361 {
3362 gen_op_update3_cc_i64(s, CC_OP_SUB_32, o->in1, o->in2, o->out);
3363 }
3364
3365 static void cout_subs64(DisasContext *s, DisasOps *o)
3366 {
3367 gen_op_update3_cc_i64(s, CC_OP_SUB_64, o->in1, o->in2, o->out);
3368 }
3369
3370 static void cout_subu32(DisasContext *s, DisasOps *o)
3371 {
3372 gen_op_update3_cc_i64(s, CC_OP_SUBU_32, o->in1, o->in2, o->out);
3373 }
3374
3375 static void cout_subu64(DisasContext *s, DisasOps *o)
3376 {
3377 gen_op_update3_cc_i64(s, CC_OP_SUBU_64, o->in1, o->in2, o->out);
3378 }
3379
3380 static void cout_subb32(DisasContext *s, DisasOps *o)
3381 {
3382 gen_op_update3_cc_i64(s, CC_OP_SUBB_32, o->in1, o->in2, o->out);
3383 }
3384
3385 static void cout_subb64(DisasContext *s, DisasOps *o)
3386 {
3387 gen_op_update3_cc_i64(s, CC_OP_SUBB_64, o->in1, o->in2, o->out);
3388 }
3389
3390 static void cout_tm32(DisasContext *s, DisasOps *o)
3391 {
3392 gen_op_update2_cc_i64(s, CC_OP_TM_32, o->in1, o->in2);
3393 }
3394
3395 static void cout_tm64(DisasContext *s, DisasOps *o)
3396 {
3397 gen_op_update2_cc_i64(s, CC_OP_TM_64, o->in1, o->in2);
3398 }
3399
3400 /* ====================================================================== */
3401 /* The "PREPeration" generators. These initialize the DisasOps.OUT fields
3402 with the TCG register to which we will write. Used in combination with
3403 the "wout" generators, in some cases we need a new temporary, and in
3404 some cases we can write to a TCG global. */
3405
3406 static void prep_new(DisasContext *s, DisasFields *f, DisasOps *o)
3407 {
3408 o->out = tcg_temp_new_i64();
3409 }
3410
3411 static void prep_new_P(DisasContext *s, DisasFields *f, DisasOps *o)
3412 {
3413 o->out = tcg_temp_new_i64();
3414 o->out2 = tcg_temp_new_i64();
3415 }
3416
3417 static void prep_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3418 {
3419 o->out = regs[get_field(f, r1)];
3420 o->g_out = true;
3421 }
3422
3423 static void prep_r1_P(DisasContext *s, DisasFields *f, DisasOps *o)
3424 {
3425 /* ??? Specification exception: r1 must be even. */
3426 int r1 = get_field(f, r1);
3427 o->out = regs[r1];
3428 o->out2 = regs[(r1 + 1) & 15];
3429 o->g_out = o->g_out2 = true;
3430 }
3431
3432 static void prep_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3433 {
3434 o->out = fregs[get_field(f, r1)];
3435 o->g_out = true;
3436 }
3437
3438 static void prep_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3439 {
3440 /* ??? Specification exception: r1 must be < 14. */
3441 int r1 = get_field(f, r1);
3442 o->out = fregs[r1];
3443 o->out2 = fregs[(r1 + 2) & 15];
3444 o->g_out = o->g_out2 = true;
3445 }
3446
3447 /* ====================================================================== */
3448 /* The "Write OUTput" generators. These generally perform some non-trivial
3449 copy of data to TCG globals, or to main memory. The trivial cases are
3450 generally handled by having a "prep" generator install the TCG global
3451 as the destination of the operation. */
3452
3453 static void wout_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3454 {
3455 store_reg(get_field(f, r1), o->out);
3456 }
3457
3458 static void wout_r1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3459 {
3460 int r1 = get_field(f, r1);
3461 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8);
3462 }
3463
3464 static void wout_r1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3465 {
3466 int r1 = get_field(f, r1);
3467 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 16);
3468 }
3469
3470 static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3471 {
3472 store_reg32_i64(get_field(f, r1), o->out);
3473 }
3474
3475 static void wout_r1_P32(DisasContext *s, DisasFields *f, DisasOps *o)
3476 {
3477 /* ??? Specification exception: r1 must be even. */
3478 int r1 = get_field(f, r1);
3479 store_reg32_i64(r1, o->out);
3480 store_reg32_i64((r1 + 1) & 15, o->out2);
3481 }
3482
3483 static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3484 {
3485 /* ??? Specification exception: r1 must be even. */
3486 int r1 = get_field(f, r1);
3487 store_reg32_i64((r1 + 1) & 15, o->out);
3488 tcg_gen_shri_i64(o->out, o->out, 32);
3489 store_reg32_i64(r1, o->out);
3490 }
3491
3492 static void wout_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3493 {
3494 store_freg32_i64(get_field(f, r1), o->out);
3495 }
3496
3497 static void wout_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3498 {
3499 store_freg(get_field(f, r1), o->out);
3500 }
3501
3502 static void wout_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3503 {
3504 /* ??? Specification exception: r1 must be < 14. */
3505 int f1 = get_field(s->fields, r1);
3506 store_freg(f1, o->out);
3507 store_freg((f1 + 2) & 15, o->out2);
3508 }
3509
3510 static void wout_cond_r1r2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3511 {
3512 if (get_field(f, r1) != get_field(f, r2)) {
3513 store_reg32_i64(get_field(f, r1), o->out);
3514 }
3515 }
3516
3517 static void wout_cond_e1e2(DisasContext *s, DisasFields *f, DisasOps *o)
3518 {
3519 if (get_field(f, r1) != get_field(f, r2)) {
3520 store_freg32_i64(get_field(f, r1), o->out);
3521 }
3522 }
3523
3524 static void wout_m1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3525 {
3526 tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s));
3527 }
3528
3529 static void wout_m1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3530 {
3531 tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s));
3532 }
3533
3534 static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3535 {
3536 tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
3537 }
3538
3539 static void wout_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3540 {
3541 tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
3542 }
3543
3544 static void wout_m2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3545 {
3546 tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s));
3547 }
3548
3549 /* ====================================================================== */
3550 /* The "INput 1" generators. These load the first operand to an insn. */
3551
3552 static void in1_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3553 {
3554 o->in1 = load_reg(get_field(f, r1));
3555 }
3556
3557 static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3558 {
3559 o->in1 = regs[get_field(f, r1)];
3560 o->g_in1 = true;
3561 }
3562
3563 static void in1_r1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3564 {
3565 o->in1 = tcg_temp_new_i64();
3566 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r1)]);
3567 }
3568
3569 static void in1_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3570 {
3571 o->in1 = tcg_temp_new_i64();
3572 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r1)]);
3573 }
3574
3575 static void in1_r1_sr32(DisasContext *s, DisasFields *f, DisasOps *o)
3576 {
3577 o->in1 = tcg_temp_new_i64();
3578 tcg_gen_shri_i64(o->in1, regs[get_field(f, r1)], 32);
3579 }
3580
3581 static void in1_r1p1(DisasContext *s, DisasFields *f, DisasOps *o)
3582 {
3583 /* ??? Specification exception: r1 must be even. */
3584 int r1 = get_field(f, r1);
3585 o->in1 = load_reg((r1 + 1) & 15);
3586 }
3587
3588 static void in1_r1p1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3589 {
3590 /* ??? Specification exception: r1 must be even. */
3591 int r1 = get_field(f, r1);
3592 o->in1 = tcg_temp_new_i64();
3593 tcg_gen_ext32s_i64(o->in1, regs[(r1 + 1) & 15]);
3594 }
3595
3596 static void in1_r1p1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3597 {
3598 /* ??? Specification exception: r1 must be even. */
3599 int r1 = get_field(f, r1);
3600 o->in1 = tcg_temp_new_i64();
3601 tcg_gen_ext32u_i64(o->in1, regs[(r1 + 1) & 15]);
3602 }
3603
3604 static void in1_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3605 {
3606 /* ??? Specification exception: r1 must be even. */
3607 int r1 = get_field(f, r1);
3608 o->in1 = tcg_temp_new_i64();
3609 tcg_gen_concat32_i64(o->in1, regs[r1 + 1], regs[r1]);
3610 }
3611
3612 static void in1_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3613 {
3614 o->in1 = load_reg(get_field(f, r2));
3615 }
3616
3617 static void in1_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3618 {
3619 o->in1 = load_reg(get_field(f, r3));
3620 }
3621
3622 static void in1_r3_o(DisasContext *s, DisasFields *f, DisasOps *o)
3623 {
3624 o->in1 = regs[get_field(f, r3)];
3625 o->g_in1 = true;
3626 }
3627
3628 static void in1_r3_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3629 {
3630 o->in1 = tcg_temp_new_i64();
3631 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r3)]);
3632 }
3633
3634 static void in1_r3_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3635 {
3636 o->in1 = tcg_temp_new_i64();
3637 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r3)]);
3638 }
3639
3640 static void in1_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3641 {
3642 o->in1 = load_freg32_i64(get_field(f, r1));
3643 }
3644
3645 static void in1_f1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3646 {
3647 o->in1 = fregs[get_field(f, r1)];
3648 o->g_in1 = true;
3649 }
3650
3651 static void in1_x1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3652 {
3653 /* ??? Specification exception: r1 must be < 14. */
3654 int r1 = get_field(f, r1);
3655 o->out = fregs[r1];
3656 o->out2 = fregs[(r1 + 2) & 15];
3657 o->g_out = o->g_out2 = true;
3658 }
3659
3660 static void in1_la1(DisasContext *s, DisasFields *f, DisasOps *o)
3661 {
3662 o->addr1 = get_address(s, 0, get_field(f, b1), get_field(f, d1));
3663 }
3664
3665 static void in1_la2(DisasContext *s, DisasFields *f, DisasOps *o)
3666 {
3667 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3668 o->addr1 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3669 }
3670
3671 static void in1_m1_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3672 {
3673 in1_la1(s, f, o);
3674 o->in1 = tcg_temp_new_i64();
3675 tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s));
3676 }
3677
3678 static void in1_m1_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3679 {
3680 in1_la1(s, f, o);
3681 o->in1 = tcg_temp_new_i64();
3682 tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s));
3683 }
3684
3685 static void in1_m1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3686 {
3687 in1_la1(s, f, o);
3688 o->in1 = tcg_temp_new_i64();
3689 tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s));
3690 }
3691
3692 static void in1_m1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3693 {
3694 in1_la1(s, f, o);
3695 o->in1 = tcg_temp_new_i64();
3696 tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s));
3697 }
3698
3699 static void in1_m1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3700 {
3701 in1_la1(s, f, o);
3702 o->in1 = tcg_temp_new_i64();
3703 tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s));
3704 }
3705
3706 static void in1_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3707 {
3708 in1_la1(s, f, o);
3709 o->in1 = tcg_temp_new_i64();
3710 tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s));
3711 }
3712
3713 /* ====================================================================== */
3714 /* The "INput 2" generators. These load the second operand to an insn. */
3715
3716 static void in2_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3717 {
3718 o->in2 = regs[get_field(f, r1)];
3719 o->g_in2 = true;
3720 }
3721
3722 static void in2_r1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3723 {
3724 o->in2 = tcg_temp_new_i64();
3725 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r1)]);
3726 }
3727
3728 static void in2_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3729 {
3730 o->in2 = tcg_temp_new_i64();
3731 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r1)]);
3732 }
3733
3734 static void in2_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3735 {
3736 o->in2 = load_reg(get_field(f, r2));
3737 }
3738
3739 static void in2_r2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3740 {
3741 o->in2 = regs[get_field(f, r2)];
3742 o->g_in2 = true;
3743 }
3744
3745 static void in2_r2_nz(DisasContext *s, DisasFields *f, DisasOps *o)
3746 {
3747 int r2 = get_field(f, r2);
3748 if (r2 != 0) {
3749 o->in2 = load_reg(r2);
3750 }
3751 }
3752
3753 static void in2_r2_8s(DisasContext *s, DisasFields *f, DisasOps *o)
3754 {
3755 o->in2 = tcg_temp_new_i64();
3756 tcg_gen_ext8s_i64(o->in2, regs[get_field(f, r2)]);
3757 }
3758
3759 static void in2_r2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3760 {
3761 o->in2 = tcg_temp_new_i64();
3762 tcg_gen_ext8u_i64(o->in2, regs[get_field(f, r2)]);
3763 }
3764
3765 static void in2_r2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3766 {
3767 o->in2 = tcg_temp_new_i64();
3768 tcg_gen_ext16s_i64(o->in2, regs[get_field(f, r2)]);
3769 }
3770
3771 static void in2_r2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3772 {
3773 o->in2 = tcg_temp_new_i64();
3774 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r2)]);
3775 }
3776
3777 static void in2_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3778 {
3779 o->in2 = load_reg(get_field(f, r3));
3780 }
3781
3782 static void in2_r2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3783 {
3784 o->in2 = tcg_temp_new_i64();
3785 tcg_gen_ext32s_i64(o->in2, regs[get_field(f, r2)]);
3786 }
3787
3788 static void in2_r2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3789 {
3790 o->in2 = tcg_temp_new_i64();
3791 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r2)]);
3792 }
3793
3794 static void in2_e2(DisasContext *s, DisasFields *f, DisasOps *o)
3795 {
3796 o->in2 = load_freg32_i64(get_field(f, r2));
3797 }
3798
3799 static void in2_f2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3800 {
3801 o->in2 = fregs[get_field(f, r2)];
3802 o->g_in2 = true;
3803 }
3804
3805 static void in2_x2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3806 {
3807 /* ??? Specification exception: r1 must be < 14. */
3808 int r2 = get_field(f, r2);
3809 o->in1 = fregs[r2];
3810 o->in2 = fregs[(r2 + 2) & 15];
3811 o->g_in1 = o->g_in2 = true;
3812 }
3813
3814 static void in2_ra2(DisasContext *s, DisasFields *f, DisasOps *o)
3815 {
3816 o->in2 = get_address(s, 0, get_field(f, r2), 0);
3817 }
3818
3819 static void in2_a2(DisasContext *s, DisasFields *f, DisasOps *o)
3820 {
3821 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3822 o->in2 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3823 }
3824
3825 static void in2_ri2(DisasContext *s, DisasFields *f, DisasOps *o)
3826 {
3827 o->in2 = tcg_const_i64(s->pc + (int64_t)get_field(f, i2) * 2);
3828 }
3829
3830 static void in2_sh32(DisasContext *s, DisasFields *f, DisasOps *o)
3831 {
3832 help_l2_shift(s, f, o, 31);
3833 }
3834
3835 static void in2_sh64(DisasContext *s, DisasFields *f, DisasOps *o)
3836 {
3837 help_l2_shift(s, f, o, 63);
3838 }
3839
3840 static void in2_m2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3841 {
3842 in2_a2(s, f, o);
3843 tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s));
3844 }
3845
3846 static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3847 {
3848 in2_a2(s, f, o);
3849 tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
3850 }
3851
3852 static void in2_m2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3853 {
3854 in2_a2(s, f, o);
3855 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3856 }
3857
3858 static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3859 {
3860 in2_a2(s, f, o);
3861 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3862 }
3863
3864 static void in2_m2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3865 {
3866 in2_a2(s, f, o);
3867 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3868 }
3869
3870 static void in2_m2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3871 {
3872 in2_a2(s, f, o);
3873 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3874 }
3875
3876 static void in2_mri2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3877 {
3878 in2_ri2(s, f, o);
3879 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3880 }
3881
3882 static void in2_mri2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3883 {
3884 in2_ri2(s, f, o);
3885 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3886 }
3887
3888 static void in2_mri2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3889 {
3890 in2_ri2(s, f, o);
3891 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3892 }
3893
3894 static void in2_mri2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3895 {
3896 in2_ri2(s, f, o);
3897 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3898 }
3899
3900 static void in2_i2(DisasContext *s, DisasFields *f, DisasOps *o)
3901 {
3902 o->in2 = tcg_const_i64(get_field(f, i2));
3903 }
3904
3905 static void in2_i2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3906 {
3907 o->in2 = tcg_const_i64((uint8_t)get_field(f, i2));
3908 }
3909
3910 static void in2_i2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3911 {
3912 o->in2 = tcg_const_i64((uint16_t)get_field(f, i2));
3913 }
3914
3915 static void in2_i2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3916 {
3917 o->in2 = tcg_const_i64((uint32_t)get_field(f, i2));
3918 }
3919
3920 static void in2_i2_16u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
3921 {
3922 uint64_t i2 = (uint16_t)get_field(f, i2);
3923 o->in2 = tcg_const_i64(i2 << s->insn->data);
3924 }
3925
3926 static void in2_i2_32u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
3927 {
3928 uint64_t i2 = (uint32_t)get_field(f, i2);
3929 o->in2 = tcg_const_i64(i2 << s->insn->data);
3930 }
3931
3932 /* ====================================================================== */
3933
3934 /* Find opc within the table of insns. This is formulated as a switch
3935 statement so that (1) we get compile-time notice of cut-paste errors
3936 for duplicated opcodes, and (2) the compiler generates the binary
3937 search tree, rather than us having to post-process the table. */
3938
3939 #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \
3940 D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0)
3941
3942 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) insn_ ## NM,
3943
3944 enum DisasInsnEnum {
3945 #include "insn-data.def"
3946 };
3947
3948 #undef D
3949 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) { \
3950 .opc = OPC, \
3951 .fmt = FMT_##FT, \
3952 .fac = FAC_##FC, \
3953 .name = #NM, \
3954 .help_in1 = in1_##I1, \
3955 .help_in2 = in2_##I2, \
3956 .help_prep = prep_##P, \
3957 .help_wout = wout_##W, \
3958 .help_cout = cout_##CC, \
3959 .help_op = op_##OP, \
3960 .data = D \
3961 },
3962
3963 /* Allow 0 to be used for NULL in the table below. */
3964 #define in1_0 NULL
3965 #define in2_0 NULL
3966 #define prep_0 NULL
3967 #define wout_0 NULL
3968 #define cout_0 NULL
3969 #define op_0 NULL
3970
3971 static const DisasInsn insn_info[] = {
3972 #include "insn-data.def"
3973 };
3974
3975 #undef D
3976 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \
3977 case OPC: return &insn_info[insn_ ## NM];
3978
3979 static const DisasInsn *lookup_opc(uint16_t opc)
3980 {
3981 switch (opc) {
3982 #include "insn-data.def"
3983 default:
3984 return NULL;
3985 }
3986 }
3987
3988 #undef D
3989 #undef C
3990
3991 /* Extract a field from the insn. The INSN should be left-aligned in
3992 the uint64_t so that we can more easily utilize the big-bit-endian
3993 definitions we extract from the Principals of Operation. */
3994
3995 static void extract_field(DisasFields *o, const DisasField *f, uint64_t insn)
3996 {
3997 uint32_t r, m;
3998
3999 if (f->size == 0) {
4000 return;
4001 }
4002
4003 /* Zero extract the field from the insn. */
4004 r = (insn << f->beg) >> (64 - f->size);
4005
4006 /* Sign-extend, or un-swap the field as necessary. */
4007 switch (f->type) {
4008 case 0: /* unsigned */
4009 break;
4010 case 1: /* signed */
4011 assert(f->size <= 32);
4012 m = 1u << (f->size - 1);
4013 r = (r ^ m) - m;
4014 break;
4015 case 2: /* dl+dh split, signed 20 bit. */
4016 r = ((int8_t)r << 12) | (r >> 8);
4017 break;
4018 default:
4019 abort();
4020 }
4021
4022 /* Validate that the "compressed" encoding we selected above is valid.
4023 I.e. we havn't make two different original fields overlap. */
4024 assert(((o->presentC >> f->indexC) & 1) == 0);
4025 o->presentC |= 1 << f->indexC;
4026 o->presentO |= 1 << f->indexO;
4027
4028 o->c[f->indexC] = r;
4029 }
4030
4031 /* Lookup the insn at the current PC, extracting the operands into O and
4032 returning the info struct for the insn. Returns NULL for invalid insn. */
4033
4034 static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
4035 DisasFields *f)
4036 {
4037 uint64_t insn, pc = s->pc;
4038 int op, op2, ilen;
4039 const DisasInsn *info;
4040
4041 insn = ld_code2(env, pc);
4042 op = (insn >> 8) & 0xff;
4043 ilen = get_ilen(op);
4044 s->next_pc = s->pc + ilen;
4045
4046 switch (ilen) {
4047 case 2:
4048 insn = insn << 48;
4049 break;
4050 case 4:
4051 insn = ld_code4(env, pc) << 32;
4052 break;
4053 case 6:
4054 insn = (insn << 48) | (ld_code4(env, pc + 2) << 16);
4055 break;
4056 default:
4057 abort();
4058 }
4059
4060 /* We can't actually determine the insn format until we've looked up
4061 the full insn opcode. Which we can't do without locating the
4062 secondary opcode. Assume by default that OP2 is at bit 40; for
4063 those smaller insns that don't actually have a secondary opcode
4064 this will correctly result in OP2 = 0. */
4065 switch (op) {
4066 case 0x01: /* E */
4067 case 0x80: /* S */
4068 case 0x82: /* S */
4069 case 0x93: /* S */
4070 case 0xb2: /* S, RRF, RRE */
4071 case 0xb3: /* RRE, RRD, RRF */
4072 case 0xb9: /* RRE, RRF */
4073 case 0xe5: /* SSE, SIL */
4074 op2 = (insn << 8) >> 56;
4075 break;
4076 case 0xa5: /* RI */
4077 case 0xa7: /* RI */
4078 case 0xc0: /* RIL */
4079 case 0xc2: /* RIL */
4080 case 0xc4: /* RIL */
4081 case 0xc6: /* RIL */
4082 case 0xc8: /* SSF */
4083 case 0xcc: /* RIL */
4084 op2 = (insn << 12) >> 60;
4085 break;
4086 case 0xd0 ... 0xdf: /* SS */
4087 case 0xe1: /* SS */
4088 case 0xe2: /* SS */
4089 case 0xe8: /* SS */
4090 case 0xe9: /* SS */
4091 case 0xea: /* SS */
4092 case 0xee ... 0xf3: /* SS */
4093 case 0xf8 ... 0xfd: /* SS */
4094 op2 = 0;
4095 break;
4096 default:
4097 op2 = (insn << 40) >> 56;
4098 break;
4099 }
4100
4101 memset(f, 0, sizeof(*f));
4102 f->op = op;
4103 f->op2 = op2;
4104
4105 /* Lookup the instruction. */
4106 info = lookup_opc(op << 8 | op2);
4107
4108 /* If we found it, extract the operands. */
4109 if (info != NULL) {
4110 DisasFormat fmt = info->fmt;
4111 int i;
4112
4113 for (i = 0; i < NUM_C_FIELD; ++i) {
4114 extract_field(f, &format_info[fmt].op[i], insn);
4115 }
4116 }
4117 return info;
4118 }
4119
4120 static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
4121 {
4122 const DisasInsn *insn;
4123 ExitStatus ret = NO_EXIT;
4124 DisasFields f;
4125 DisasOps o;
4126
4127 /* Search for the insn in the table. */
4128 insn = extract_insn(env, s, &f);
4129
4130 /* Not found means unimplemented/illegal opcode. */
4131 if (insn == NULL) {
4132 qemu_log_mask(LOG_UNIMP, "unimplemented opcode 0x%02x%02x\n",
4133 f.op, f.op2);
4134 gen_illegal_opcode(s);
4135 return EXIT_NORETURN;
4136 }
4137
4138 /* Set up the strutures we use to communicate with the helpers. */
4139 s->insn = insn;
4140 s->fields = &f;
4141 o.g_out = o.g_out2 = o.g_in1 = o.g_in2 = false;
4142 TCGV_UNUSED_I64(o.out);
4143 TCGV_UNUSED_I64(o.out2);
4144 TCGV_UNUSED_I64(o.in1);
4145 TCGV_UNUSED_I64(o.in2);
4146 TCGV_UNUSED_I64(o.addr1);
4147
4148 /* Implement the instruction. */
4149 if (insn->help_in1) {
4150 insn->help_in1(s, &f, &o);
4151 }
4152 if (insn->help_in2) {
4153 insn->help_in2(s, &f, &o);
4154 }
4155 if (insn->help_prep) {
4156 insn->help_prep(s, &f, &o);
4157 }
4158 if (insn->help_op) {
4159 ret = insn->help_op(s, &o);
4160 }
4161 if (insn->help_wout) {
4162 insn->help_wout(s, &f, &o);
4163 }
4164 if (insn->help_cout) {
4165 insn->help_cout(s, &o);
4166 }
4167
4168 /* Free any temporaries created by the helpers. */
4169 if (!TCGV_IS_UNUSED_I64(o.out) && !o.g_out) {
4170 tcg_temp_free_i64(o.out);
4171 }
4172 if (!TCGV_IS_UNUSED_I64(o.out2) && !o.g_out2) {
4173 tcg_temp_free_i64(o.out2);
4174 }
4175 if (!TCGV_IS_UNUSED_I64(o.in1) && !o.g_in1) {
4176 tcg_temp_free_i64(o.in1);
4177 }
4178 if (!TCGV_IS_UNUSED_I64(o.in2) && !o.g_in2) {
4179 tcg_temp_free_i64(o.in2);
4180 }
4181 if (!TCGV_IS_UNUSED_I64(o.addr1)) {
4182 tcg_temp_free_i64(o.addr1);
4183 }
4184
4185 /* Advance to the next instruction. */
4186 s->pc = s->next_pc;
4187 return ret;
4188 }
4189
4190 static inline void gen_intermediate_code_internal(CPUS390XState *env,
4191 TranslationBlock *tb,
4192 int search_pc)
4193 {
4194 DisasContext dc;
4195 target_ulong pc_start;
4196 uint64_t next_page_start;
4197 uint16_t *gen_opc_end;
4198 int j, lj = -1;
4199 int num_insns, max_insns;
4200 CPUBreakpoint *bp;
4201 ExitStatus status;
4202 bool do_debug;
4203
4204 pc_start = tb->pc;
4205
4206 /* 31-bit mode */
4207 if (!(tb->flags & FLAG_MASK_64)) {
4208 pc_start &= 0x7fffffff;
4209 }
4210
4211 dc.tb = tb;
4212 dc.pc = pc_start;
4213 dc.cc_op = CC_OP_DYNAMIC;
4214 do_debug = dc.singlestep_enabled = env->singlestep_enabled;
4215
4216 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
4217
4218 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4219
4220 num_insns = 0;
4221 max_insns = tb->cflags & CF_COUNT_MASK;
4222 if (max_insns == 0) {
4223 max_insns = CF_COUNT_MASK;
4224 }
4225
4226 gen_icount_start();
4227
4228 do {
4229 if (search_pc) {
4230 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4231 if (lj < j) {
4232 lj++;
4233 while (lj < j) {
4234 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4235 }
4236 }
4237 tcg_ctx.gen_opc_pc[lj] = dc.pc;
4238 gen_opc_cc_op[lj] = dc.cc_op;
4239 tcg_ctx.gen_opc_instr_start[lj] = 1;
4240 tcg_ctx.gen_opc_icount[lj] = num_insns;
4241 }
4242 if (++num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
4243 gen_io_start();
4244 }
4245
4246 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
4247 tcg_gen_debug_insn_start(dc.pc);
4248 }
4249
4250 status = NO_EXIT;
4251 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
4252 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
4253 if (bp->pc == dc.pc) {
4254 status = EXIT_PC_STALE;
4255 do_debug = true;
4256 break;
4257 }
4258 }
4259 }
4260 if (status == NO_EXIT) {
4261 status = translate_one(env, &dc);
4262 }
4263
4264 /* If we reach a page boundary, are single stepping,
4265 or exhaust instruction count, stop generation. */
4266 if (status == NO_EXIT
4267 && (dc.pc >= next_page_start
4268 || tcg_ctx.gen_opc_ptr >= gen_opc_end
4269 || num_insns >= max_insns
4270 || singlestep
4271 || env->singlestep_enabled)) {
4272 status = EXIT_PC_STALE;
4273 }
4274 } while (status == NO_EXIT);
4275
4276 if (tb->cflags & CF_LAST_IO) {
4277 gen_io_end();
4278 }
4279
4280 switch (status) {
4281 case EXIT_GOTO_TB:
4282 case EXIT_NORETURN:
4283 break;
4284 case EXIT_PC_STALE:
4285 update_psw_addr(&dc);
4286 /* FALLTHRU */
4287 case EXIT_PC_UPDATED:
4288 /* Next TB starts off with CC_OP_DYNAMIC, so make sure the
4289 cc op type is in env */
4290 update_cc_op(&dc);
4291 /* Exit the TB, either by raising a debug exception or by return. */
4292 if (do_debug) {
4293 gen_exception(EXCP_DEBUG);
4294 } else {
4295 tcg_gen_exit_tb(0);
4296 }
4297 break;
4298 default:
4299 abort();
4300 }
4301
4302 gen_icount_end(tb, num_insns);
4303 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
4304 if (search_pc) {
4305 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4306 lj++;
4307 while (lj <= j) {
4308 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4309 }
4310 } else {
4311 tb->size = dc.pc - pc_start;
4312 tb->icount = num_insns;
4313 }
4314
4315 #if defined(S390X_DEBUG_DISAS)
4316 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
4317 qemu_log("IN: %s\n", lookup_symbol(pc_start));
4318 log_target_disas(env, pc_start, dc.pc - pc_start, 1);
4319 qemu_log("\n");
4320 }
4321 #endif
4322 }
4323
4324 void gen_intermediate_code (CPUS390XState *env, struct TranslationBlock *tb)
4325 {
4326 gen_intermediate_code_internal(env, tb, 0);
4327 }
4328
4329 void gen_intermediate_code_pc (CPUS390XState *env, struct TranslationBlock *tb)
4330 {
4331 gen_intermediate_code_internal(env, tb, 1);
4332 }
4333
4334 void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, int pc_pos)
4335 {
4336 int cc_op;
4337 env->psw.addr = tcg_ctx.gen_opc_pc[pc_pos];
4338 cc_op = gen_opc_cc_op[pc_pos];
4339 if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {
4340 env->cc_op = cc_op;
4341 }
4342 }
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