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target-s390: Convert CKSM
[mirror_qemu.git] / target-s390x / translate.c
1 /*
2 * S/390 translation
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* #define DEBUG_INLINE_BRANCHES */
22 #define S390X_DEBUG_DISAS
23 /* #define S390X_DEBUG_DISAS_VERBOSE */
24
25 #ifdef S390X_DEBUG_DISAS_VERBOSE
26 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
27 #else
28 # define LOG_DISAS(...) do { } while (0)
29 #endif
30
31 #include "cpu.h"
32 #include "disas/disas.h"
33 #include "tcg-op.h"
34 #include "qemu/log.h"
35 #include "qemu/host-utils.h"
36
37 /* global register indexes */
38 static TCGv_ptr cpu_env;
39
40 #include "exec/gen-icount.h"
41 #include "helper.h"
42 #define GEN_HELPER 1
43 #include "helper.h"
44
45
46 /* Information that (most) every instruction needs to manipulate. */
47 typedef struct DisasContext DisasContext;
48 typedef struct DisasInsn DisasInsn;
49 typedef struct DisasFields DisasFields;
50
51 struct DisasContext {
52 struct TranslationBlock *tb;
53 const DisasInsn *insn;
54 DisasFields *fields;
55 uint64_t pc, next_pc;
56 enum cc_op cc_op;
57 bool singlestep_enabled;
58 int is_jmp;
59 };
60
61 /* Information carried about a condition to be evaluated. */
62 typedef struct {
63 TCGCond cond:8;
64 bool is_64;
65 bool g1;
66 bool g2;
67 union {
68 struct { TCGv_i64 a, b; } s64;
69 struct { TCGv_i32 a, b; } s32;
70 } u;
71 } DisasCompare;
72
73 #define DISAS_EXCP 4
74
75 static void gen_op_calc_cc(DisasContext *s);
76
77 #ifdef DEBUG_INLINE_BRANCHES
78 static uint64_t inline_branch_hit[CC_OP_MAX];
79 static uint64_t inline_branch_miss[CC_OP_MAX];
80 #endif
81
82 static inline void debug_insn(uint64_t insn)
83 {
84 LOG_DISAS("insn: 0x%" PRIx64 "\n", insn);
85 }
86
87 static inline uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
88 {
89 if (!(s->tb->flags & FLAG_MASK_64)) {
90 if (s->tb->flags & FLAG_MASK_32) {
91 return pc | 0x80000000;
92 }
93 }
94 return pc;
95 }
96
97 void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
98 int flags)
99 {
100 int i;
101
102 if (env->cc_op > 3) {
103 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
104 env->psw.mask, env->psw.addr, cc_name(env->cc_op));
105 } else {
106 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
107 env->psw.mask, env->psw.addr, env->cc_op);
108 }
109
110 for (i = 0; i < 16; i++) {
111 cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
112 if ((i % 4) == 3) {
113 cpu_fprintf(f, "\n");
114 } else {
115 cpu_fprintf(f, " ");
116 }
117 }
118
119 for (i = 0; i < 16; i++) {
120 cpu_fprintf(f, "F%02d=%016" PRIx64, i, env->fregs[i].ll);
121 if ((i % 4) == 3) {
122 cpu_fprintf(f, "\n");
123 } else {
124 cpu_fprintf(f, " ");
125 }
126 }
127
128 #ifndef CONFIG_USER_ONLY
129 for (i = 0; i < 16; i++) {
130 cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
131 if ((i % 4) == 3) {
132 cpu_fprintf(f, "\n");
133 } else {
134 cpu_fprintf(f, " ");
135 }
136 }
137 #endif
138
139 #ifdef DEBUG_INLINE_BRANCHES
140 for (i = 0; i < CC_OP_MAX; i++) {
141 cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
142 inline_branch_miss[i], inline_branch_hit[i]);
143 }
144 #endif
145
146 cpu_fprintf(f, "\n");
147 }
148
149 static TCGv_i64 psw_addr;
150 static TCGv_i64 psw_mask;
151
152 static TCGv_i32 cc_op;
153 static TCGv_i64 cc_src;
154 static TCGv_i64 cc_dst;
155 static TCGv_i64 cc_vr;
156
157 static char cpu_reg_names[32][4];
158 static TCGv_i64 regs[16];
159 static TCGv_i64 fregs[16];
160
161 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
162
163 void s390x_translate_init(void)
164 {
165 int i;
166
167 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
168 psw_addr = tcg_global_mem_new_i64(TCG_AREG0,
169 offsetof(CPUS390XState, psw.addr),
170 "psw_addr");
171 psw_mask = tcg_global_mem_new_i64(TCG_AREG0,
172 offsetof(CPUS390XState, psw.mask),
173 "psw_mask");
174
175 cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUS390XState, cc_op),
176 "cc_op");
177 cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_src),
178 "cc_src");
179 cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_dst),
180 "cc_dst");
181 cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_vr),
182 "cc_vr");
183
184 for (i = 0; i < 16; i++) {
185 snprintf(cpu_reg_names[i], sizeof(cpu_reg_names[0]), "r%d", i);
186 regs[i] = tcg_global_mem_new(TCG_AREG0,
187 offsetof(CPUS390XState, regs[i]),
188 cpu_reg_names[i]);
189 }
190
191 for (i = 0; i < 16; i++) {
192 snprintf(cpu_reg_names[i + 16], sizeof(cpu_reg_names[0]), "f%d", i);
193 fregs[i] = tcg_global_mem_new(TCG_AREG0,
194 offsetof(CPUS390XState, fregs[i].d),
195 cpu_reg_names[i + 16]);
196 }
197
198 /* register helpers */
199 #define GEN_HELPER 2
200 #include "helper.h"
201 }
202
203 static inline TCGv_i64 load_reg(int reg)
204 {
205 TCGv_i64 r = tcg_temp_new_i64();
206 tcg_gen_mov_i64(r, regs[reg]);
207 return r;
208 }
209
210 static inline TCGv_i64 load_freg(int reg)
211 {
212 TCGv_i64 r = tcg_temp_new_i64();
213 tcg_gen_mov_i64(r, fregs[reg]);
214 return r;
215 }
216
217 static inline TCGv_i32 load_freg32(int reg)
218 {
219 TCGv_i32 r = tcg_temp_new_i32();
220 #if HOST_LONG_BITS == 32
221 tcg_gen_mov_i32(r, TCGV_HIGH(fregs[reg]));
222 #else
223 tcg_gen_shri_i64(MAKE_TCGV_I64(GET_TCGV_I32(r)), fregs[reg], 32);
224 #endif
225 return r;
226 }
227
228 static inline TCGv_i64 load_freg32_i64(int reg)
229 {
230 TCGv_i64 r = tcg_temp_new_i64();
231 tcg_gen_shri_i64(r, fregs[reg], 32);
232 return r;
233 }
234
235 static inline TCGv_i32 load_reg32(int reg)
236 {
237 TCGv_i32 r = tcg_temp_new_i32();
238 tcg_gen_trunc_i64_i32(r, regs[reg]);
239 return r;
240 }
241
242 static inline TCGv_i64 load_reg32_i64(int reg)
243 {
244 TCGv_i64 r = tcg_temp_new_i64();
245 tcg_gen_ext32s_i64(r, regs[reg]);
246 return r;
247 }
248
249 static inline void store_reg(int reg, TCGv_i64 v)
250 {
251 tcg_gen_mov_i64(regs[reg], v);
252 }
253
254 static inline void store_freg(int reg, TCGv_i64 v)
255 {
256 tcg_gen_mov_i64(fregs[reg], v);
257 }
258
259 static inline void store_reg32(int reg, TCGv_i32 v)
260 {
261 /* 32 bit register writes keep the upper half */
262 #if HOST_LONG_BITS == 32
263 tcg_gen_mov_i32(TCGV_LOW(regs[reg]), v);
264 #else
265 tcg_gen_deposit_i64(regs[reg], regs[reg],
266 MAKE_TCGV_I64(GET_TCGV_I32(v)), 0, 32);
267 #endif
268 }
269
270 static inline void store_reg32_i64(int reg, TCGv_i64 v)
271 {
272 /* 32 bit register writes keep the upper half */
273 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
274 }
275
276 static inline void store_reg32h_i64(int reg, TCGv_i64 v)
277 {
278 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 32, 32);
279 }
280
281 static inline void store_freg32(int reg, TCGv_i32 v)
282 {
283 /* 32 bit register writes keep the lower half */
284 #if HOST_LONG_BITS == 32
285 tcg_gen_mov_i32(TCGV_HIGH(fregs[reg]), v);
286 #else
287 tcg_gen_deposit_i64(fregs[reg], fregs[reg],
288 MAKE_TCGV_I64(GET_TCGV_I32(v)), 32, 32);
289 #endif
290 }
291
292 static inline void store_freg32_i64(int reg, TCGv_i64 v)
293 {
294 tcg_gen_deposit_i64(fregs[reg], fregs[reg], v, 32, 32);
295 }
296
297 static inline void return_low128(TCGv_i64 dest)
298 {
299 tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl));
300 }
301
302 static inline void update_psw_addr(DisasContext *s)
303 {
304 /* psw.addr */
305 tcg_gen_movi_i64(psw_addr, s->pc);
306 }
307
308 static inline void potential_page_fault(DisasContext *s)
309 {
310 #ifndef CONFIG_USER_ONLY
311 update_psw_addr(s);
312 gen_op_calc_cc(s);
313 #endif
314 }
315
316 static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
317 {
318 return (uint64_t)cpu_lduw_code(env, pc);
319 }
320
321 static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
322 {
323 return (uint64_t)(uint32_t)cpu_ldl_code(env, pc);
324 }
325
326 static inline uint64_t ld_code6(CPUS390XState *env, uint64_t pc)
327 {
328 return (ld_code2(env, pc) << 32) | ld_code4(env, pc + 2);
329 }
330
331 static inline int get_mem_index(DisasContext *s)
332 {
333 switch (s->tb->flags & FLAG_MASK_ASC) {
334 case PSW_ASC_PRIMARY >> 32:
335 return 0;
336 case PSW_ASC_SECONDARY >> 32:
337 return 1;
338 case PSW_ASC_HOME >> 32:
339 return 2;
340 default:
341 tcg_abort();
342 break;
343 }
344 }
345
346 static void gen_exception(int excp)
347 {
348 TCGv_i32 tmp = tcg_const_i32(excp);
349 gen_helper_exception(cpu_env, tmp);
350 tcg_temp_free_i32(tmp);
351 }
352
353 static void gen_program_exception(DisasContext *s, int code)
354 {
355 TCGv_i32 tmp;
356
357 /* Remember what pgm exeption this was. */
358 tmp = tcg_const_i32(code);
359 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
360 tcg_temp_free_i32(tmp);
361
362 tmp = tcg_const_i32(s->next_pc - s->pc);
363 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen));
364 tcg_temp_free_i32(tmp);
365
366 /* Advance past instruction. */
367 s->pc = s->next_pc;
368 update_psw_addr(s);
369
370 /* Save off cc. */
371 gen_op_calc_cc(s);
372
373 /* Trigger exception. */
374 gen_exception(EXCP_PGM);
375
376 /* End TB here. */
377 s->is_jmp = DISAS_EXCP;
378 }
379
380 static inline void gen_illegal_opcode(DisasContext *s)
381 {
382 gen_program_exception(s, PGM_SPECIFICATION);
383 }
384
385 static inline void check_privileged(DisasContext *s)
386 {
387 if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
388 gen_program_exception(s, PGM_PRIVILEGED);
389 }
390 }
391
392 static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
393 {
394 TCGv_i64 tmp;
395
396 /* 31-bitify the immediate part; register contents are dealt with below */
397 if (!(s->tb->flags & FLAG_MASK_64)) {
398 d2 &= 0x7fffffffUL;
399 }
400
401 if (x2) {
402 if (d2) {
403 tmp = tcg_const_i64(d2);
404 tcg_gen_add_i64(tmp, tmp, regs[x2]);
405 } else {
406 tmp = load_reg(x2);
407 }
408 if (b2) {
409 tcg_gen_add_i64(tmp, tmp, regs[b2]);
410 }
411 } else if (b2) {
412 if (d2) {
413 tmp = tcg_const_i64(d2);
414 tcg_gen_add_i64(tmp, tmp, regs[b2]);
415 } else {
416 tmp = load_reg(b2);
417 }
418 } else {
419 tmp = tcg_const_i64(d2);
420 }
421
422 /* 31-bit mode mask if there are values loaded from registers */
423 if (!(s->tb->flags & FLAG_MASK_64) && (x2 || b2)) {
424 tcg_gen_andi_i64(tmp, tmp, 0x7fffffffUL);
425 }
426
427 return tmp;
428 }
429
430 static void gen_op_movi_cc(DisasContext *s, uint32_t val)
431 {
432 s->cc_op = CC_OP_CONST0 + val;
433 }
434
435 static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst)
436 {
437 tcg_gen_discard_i64(cc_src);
438 tcg_gen_mov_i64(cc_dst, dst);
439 tcg_gen_discard_i64(cc_vr);
440 s->cc_op = op;
441 }
442
443 static void gen_op_update1_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 dst)
444 {
445 tcg_gen_discard_i64(cc_src);
446 tcg_gen_extu_i32_i64(cc_dst, dst);
447 tcg_gen_discard_i64(cc_vr);
448 s->cc_op = op;
449 }
450
451 static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
452 TCGv_i64 dst)
453 {
454 tcg_gen_mov_i64(cc_src, src);
455 tcg_gen_mov_i64(cc_dst, dst);
456 tcg_gen_discard_i64(cc_vr);
457 s->cc_op = op;
458 }
459
460 static void gen_op_update2_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 src,
461 TCGv_i32 dst)
462 {
463 tcg_gen_extu_i32_i64(cc_src, src);
464 tcg_gen_extu_i32_i64(cc_dst, dst);
465 tcg_gen_discard_i64(cc_vr);
466 s->cc_op = op;
467 }
468
469 static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
470 TCGv_i64 dst, TCGv_i64 vr)
471 {
472 tcg_gen_mov_i64(cc_src, src);
473 tcg_gen_mov_i64(cc_dst, dst);
474 tcg_gen_mov_i64(cc_vr, vr);
475 s->cc_op = op;
476 }
477
478 static inline void set_cc_nz_u32(DisasContext *s, TCGv_i32 val)
479 {
480 gen_op_update1_cc_i32(s, CC_OP_NZ, val);
481 }
482
483 static inline void set_cc_nz_u64(DisasContext *s, TCGv_i64 val)
484 {
485 gen_op_update1_cc_i64(s, CC_OP_NZ, val);
486 }
487
488 static inline void gen_set_cc_nz_f32(DisasContext *s, TCGv_i64 val)
489 {
490 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, val);
491 }
492
493 static inline void gen_set_cc_nz_f64(DisasContext *s, TCGv_i64 val)
494 {
495 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, val);
496 }
497
498 static inline void gen_set_cc_nz_f128(DisasContext *s, TCGv_i64 vh, TCGv_i64 vl)
499 {
500 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, vh, vl);
501 }
502
503 static inline void cmp_32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
504 enum cc_op cond)
505 {
506 gen_op_update2_cc_i32(s, cond, v1, v2);
507 }
508
509 static inline void cmp_64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
510 enum cc_op cond)
511 {
512 gen_op_update2_cc_i64(s, cond, v1, v2);
513 }
514
515 static inline void cmp_s32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
516 {
517 cmp_32(s, v1, v2, CC_OP_LTGT_32);
518 }
519
520 static inline void cmp_u32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
521 {
522 cmp_32(s, v1, v2, CC_OP_LTUGTU_32);
523 }
524
525 static inline void cmp_s32c(DisasContext *s, TCGv_i32 v1, int32_t v2)
526 {
527 /* XXX optimize for the constant? put it in s? */
528 TCGv_i32 tmp = tcg_const_i32(v2);
529 cmp_32(s, v1, tmp, CC_OP_LTGT_32);
530 tcg_temp_free_i32(tmp);
531 }
532
533 static inline void cmp_u32c(DisasContext *s, TCGv_i32 v1, uint32_t v2)
534 {
535 TCGv_i32 tmp = tcg_const_i32(v2);
536 cmp_32(s, v1, tmp, CC_OP_LTUGTU_32);
537 tcg_temp_free_i32(tmp);
538 }
539
540 static inline void cmp_s64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
541 {
542 cmp_64(s, v1, v2, CC_OP_LTGT_64);
543 }
544
545 static inline void cmp_u64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
546 {
547 cmp_64(s, v1, v2, CC_OP_LTUGTU_64);
548 }
549
550 static inline void cmp_s64c(DisasContext *s, TCGv_i64 v1, int64_t v2)
551 {
552 TCGv_i64 tmp = tcg_const_i64(v2);
553 cmp_s64(s, v1, tmp);
554 tcg_temp_free_i64(tmp);
555 }
556
557 static inline void cmp_u64c(DisasContext *s, TCGv_i64 v1, uint64_t v2)
558 {
559 TCGv_i64 tmp = tcg_const_i64(v2);
560 cmp_u64(s, v1, tmp);
561 tcg_temp_free_i64(tmp);
562 }
563
564 static inline void set_cc_s32(DisasContext *s, TCGv_i32 val)
565 {
566 gen_op_update1_cc_i32(s, CC_OP_LTGT0_32, val);
567 }
568
569 static inline void set_cc_s64(DisasContext *s, TCGv_i64 val)
570 {
571 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, val);
572 }
573
574 /* CC value is in env->cc_op */
575 static inline void set_cc_static(DisasContext *s)
576 {
577 tcg_gen_discard_i64(cc_src);
578 tcg_gen_discard_i64(cc_dst);
579 tcg_gen_discard_i64(cc_vr);
580 s->cc_op = CC_OP_STATIC;
581 }
582
583 static inline void gen_op_set_cc_op(DisasContext *s)
584 {
585 if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) {
586 tcg_gen_movi_i32(cc_op, s->cc_op);
587 }
588 }
589
590 static inline void gen_update_cc_op(DisasContext *s)
591 {
592 gen_op_set_cc_op(s);
593 }
594
595 /* calculates cc into cc_op */
596 static void gen_op_calc_cc(DisasContext *s)
597 {
598 TCGv_i32 local_cc_op = tcg_const_i32(s->cc_op);
599 TCGv_i64 dummy = tcg_const_i64(0);
600
601 switch (s->cc_op) {
602 case CC_OP_CONST0:
603 case CC_OP_CONST1:
604 case CC_OP_CONST2:
605 case CC_OP_CONST3:
606 /* s->cc_op is the cc value */
607 tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
608 break;
609 case CC_OP_STATIC:
610 /* env->cc_op already is the cc value */
611 break;
612 case CC_OP_NZ:
613 case CC_OP_ABS_64:
614 case CC_OP_NABS_64:
615 case CC_OP_ABS_32:
616 case CC_OP_NABS_32:
617 case CC_OP_LTGT0_32:
618 case CC_OP_LTGT0_64:
619 case CC_OP_COMP_32:
620 case CC_OP_COMP_64:
621 case CC_OP_NZ_F32:
622 case CC_OP_NZ_F64:
623 case CC_OP_FLOGR:
624 /* 1 argument */
625 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dummy);
626 break;
627 case CC_OP_ICM:
628 case CC_OP_LTGT_32:
629 case CC_OP_LTGT_64:
630 case CC_OP_LTUGTU_32:
631 case CC_OP_LTUGTU_64:
632 case CC_OP_TM_32:
633 case CC_OP_TM_64:
634 case CC_OP_SLA_32:
635 case CC_OP_SLA_64:
636 case CC_OP_NZ_F128:
637 /* 2 arguments */
638 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
639 break;
640 case CC_OP_ADD_64:
641 case CC_OP_ADDU_64:
642 case CC_OP_ADDC_64:
643 case CC_OP_SUB_64:
644 case CC_OP_SUBU_64:
645 case CC_OP_SUBB_64:
646 case CC_OP_ADD_32:
647 case CC_OP_ADDU_32:
648 case CC_OP_ADDC_32:
649 case CC_OP_SUB_32:
650 case CC_OP_SUBU_32:
651 case CC_OP_SUBB_32:
652 /* 3 arguments */
653 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc_vr);
654 break;
655 case CC_OP_DYNAMIC:
656 /* unknown operation - assume 3 arguments and cc_op in env */
657 gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr);
658 break;
659 default:
660 tcg_abort();
661 }
662
663 tcg_temp_free_i32(local_cc_op);
664 tcg_temp_free_i64(dummy);
665
666 /* We now have cc in cc_op as constant */
667 set_cc_static(s);
668 }
669
670 static inline void decode_rr(DisasContext *s, uint64_t insn, int *r1, int *r2)
671 {
672 debug_insn(insn);
673
674 *r1 = (insn >> 4) & 0xf;
675 *r2 = insn & 0xf;
676 }
677
678 static inline TCGv_i64 decode_rx(DisasContext *s, uint64_t insn, int *r1,
679 int *x2, int *b2, int *d2)
680 {
681 debug_insn(insn);
682
683 *r1 = (insn >> 20) & 0xf;
684 *x2 = (insn >> 16) & 0xf;
685 *b2 = (insn >> 12) & 0xf;
686 *d2 = insn & 0xfff;
687
688 return get_address(s, *x2, *b2, *d2);
689 }
690
691 static inline void decode_rs(DisasContext *s, uint64_t insn, int *r1, int *r3,
692 int *b2, int *d2)
693 {
694 debug_insn(insn);
695
696 *r1 = (insn >> 20) & 0xf;
697 /* aka m3 */
698 *r3 = (insn >> 16) & 0xf;
699 *b2 = (insn >> 12) & 0xf;
700 *d2 = insn & 0xfff;
701 }
702
703 static inline TCGv_i64 decode_si(DisasContext *s, uint64_t insn, int *i2,
704 int *b1, int *d1)
705 {
706 debug_insn(insn);
707
708 *i2 = (insn >> 16) & 0xff;
709 *b1 = (insn >> 12) & 0xf;
710 *d1 = insn & 0xfff;
711
712 return get_address(s, 0, *b1, *d1);
713 }
714
715 static int use_goto_tb(DisasContext *s, uint64_t dest)
716 {
717 /* NOTE: we handle the case where the TB spans two pages here */
718 return (((dest & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK)
719 || (dest & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK))
720 && !s->singlestep_enabled
721 && !(s->tb->cflags & CF_LAST_IO));
722 }
723
724 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong pc)
725 {
726 gen_update_cc_op(s);
727
728 if (use_goto_tb(s, pc)) {
729 tcg_gen_goto_tb(tb_num);
730 tcg_gen_movi_i64(psw_addr, pc);
731 tcg_gen_exit_tb((tcg_target_long)s->tb + tb_num);
732 } else {
733 /* jump to another page: currently not optimized */
734 tcg_gen_movi_i64(psw_addr, pc);
735 tcg_gen_exit_tb(0);
736 }
737 }
738
739 static inline void account_noninline_branch(DisasContext *s, int cc_op)
740 {
741 #ifdef DEBUG_INLINE_BRANCHES
742 inline_branch_miss[cc_op]++;
743 #endif
744 }
745
746 static inline void account_inline_branch(DisasContext *s, int cc_op)
747 {
748 #ifdef DEBUG_INLINE_BRANCHES
749 inline_branch_hit[cc_op]++;
750 #endif
751 }
752
753 /* Table of mask values to comparison codes, given a comparison as input.
754 For a true comparison CC=3 will never be set, but we treat this
755 conservatively for possible use when CC=3 indicates overflow. */
756 static const TCGCond ltgt_cond[16] = {
757 TCG_COND_NEVER, TCG_COND_NEVER, /* | | | x */
758 TCG_COND_GT, TCG_COND_NEVER, /* | | GT | x */
759 TCG_COND_LT, TCG_COND_NEVER, /* | LT | | x */
760 TCG_COND_NE, TCG_COND_NEVER, /* | LT | GT | x */
761 TCG_COND_EQ, TCG_COND_NEVER, /* EQ | | | x */
762 TCG_COND_GE, TCG_COND_NEVER, /* EQ | | GT | x */
763 TCG_COND_LE, TCG_COND_NEVER, /* EQ | LT | | x */
764 TCG_COND_ALWAYS, TCG_COND_ALWAYS, /* EQ | LT | GT | x */
765 };
766
767 /* Table of mask values to comparison codes, given a logic op as input.
768 For such, only CC=0 and CC=1 should be possible. */
769 static const TCGCond nz_cond[16] = {
770 /* | | x | x */
771 TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER,
772 /* | NE | x | x */
773 TCG_COND_NE, TCG_COND_NE, TCG_COND_NE, TCG_COND_NE,
774 /* EQ | | x | x */
775 TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ,
776 /* EQ | NE | x | x */
777 TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS,
778 };
779
780 /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
781 details required to generate a TCG comparison. */
782 static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
783 {
784 TCGCond cond;
785 enum cc_op old_cc_op = s->cc_op;
786
787 if (mask == 15 || mask == 0) {
788 c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER);
789 c->u.s32.a = cc_op;
790 c->u.s32.b = cc_op;
791 c->g1 = c->g2 = true;
792 c->is_64 = false;
793 return;
794 }
795
796 /* Find the TCG condition for the mask + cc op. */
797 switch (old_cc_op) {
798 case CC_OP_LTGT0_32:
799 case CC_OP_LTGT0_64:
800 case CC_OP_LTGT_32:
801 case CC_OP_LTGT_64:
802 cond = ltgt_cond[mask];
803 if (cond == TCG_COND_NEVER) {
804 goto do_dynamic;
805 }
806 account_inline_branch(s, old_cc_op);
807 break;
808
809 case CC_OP_LTUGTU_32:
810 case CC_OP_LTUGTU_64:
811 cond = tcg_unsigned_cond(ltgt_cond[mask]);
812 if (cond == TCG_COND_NEVER) {
813 goto do_dynamic;
814 }
815 account_inline_branch(s, old_cc_op);
816 break;
817
818 case CC_OP_NZ:
819 cond = nz_cond[mask];
820 if (cond == TCG_COND_NEVER) {
821 goto do_dynamic;
822 }
823 account_inline_branch(s, old_cc_op);
824 break;
825
826 case CC_OP_TM_32:
827 case CC_OP_TM_64:
828 switch (mask) {
829 case 8:
830 cond = TCG_COND_EQ;
831 break;
832 case 4 | 2 | 1:
833 cond = TCG_COND_NE;
834 break;
835 default:
836 goto do_dynamic;
837 }
838 account_inline_branch(s, old_cc_op);
839 break;
840
841 case CC_OP_ICM:
842 switch (mask) {
843 case 8:
844 cond = TCG_COND_EQ;
845 break;
846 case 4 | 2 | 1:
847 case 4 | 2:
848 cond = TCG_COND_NE;
849 break;
850 default:
851 goto do_dynamic;
852 }
853 account_inline_branch(s, old_cc_op);
854 break;
855
856 case CC_OP_FLOGR:
857 switch (mask & 0xa) {
858 case 8: /* src == 0 -> no one bit found */
859 cond = TCG_COND_EQ;
860 break;
861 case 2: /* src != 0 -> one bit found */
862 cond = TCG_COND_NE;
863 break;
864 default:
865 goto do_dynamic;
866 }
867 account_inline_branch(s, old_cc_op);
868 break;
869
870 default:
871 do_dynamic:
872 /* Calculate cc value. */
873 gen_op_calc_cc(s);
874 /* FALLTHRU */
875
876 case CC_OP_STATIC:
877 /* Jump based on CC. We'll load up the real cond below;
878 the assignment here merely avoids a compiler warning. */
879 account_noninline_branch(s, old_cc_op);
880 old_cc_op = CC_OP_STATIC;
881 cond = TCG_COND_NEVER;
882 break;
883 }
884
885 /* Load up the arguments of the comparison. */
886 c->is_64 = true;
887 c->g1 = c->g2 = false;
888 switch (old_cc_op) {
889 case CC_OP_LTGT0_32:
890 c->is_64 = false;
891 c->u.s32.a = tcg_temp_new_i32();
892 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_dst);
893 c->u.s32.b = tcg_const_i32(0);
894 break;
895 case CC_OP_LTGT_32:
896 case CC_OP_LTUGTU_32:
897 c->is_64 = false;
898 c->u.s32.a = tcg_temp_new_i32();
899 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_src);
900 c->u.s32.b = tcg_temp_new_i32();
901 tcg_gen_trunc_i64_i32(c->u.s32.b, cc_dst);
902 break;
903
904 case CC_OP_LTGT0_64:
905 case CC_OP_NZ:
906 case CC_OP_FLOGR:
907 c->u.s64.a = cc_dst;
908 c->u.s64.b = tcg_const_i64(0);
909 c->g1 = true;
910 break;
911 case CC_OP_LTGT_64:
912 case CC_OP_LTUGTU_64:
913 c->u.s64.a = cc_src;
914 c->u.s64.b = cc_dst;
915 c->g1 = c->g2 = true;
916 break;
917
918 case CC_OP_TM_32:
919 case CC_OP_TM_64:
920 case CC_OP_ICM:
921 c->u.s64.a = tcg_temp_new_i64();
922 c->u.s64.b = tcg_const_i64(0);
923 tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst);
924 break;
925
926 case CC_OP_STATIC:
927 c->is_64 = false;
928 c->u.s32.a = cc_op;
929 c->g1 = true;
930 switch (mask) {
931 case 0x8 | 0x4 | 0x2: /* cc != 3 */
932 cond = TCG_COND_NE;
933 c->u.s32.b = tcg_const_i32(3);
934 break;
935 case 0x8 | 0x4 | 0x1: /* cc != 2 */
936 cond = TCG_COND_NE;
937 c->u.s32.b = tcg_const_i32(2);
938 break;
939 case 0x8 | 0x2 | 0x1: /* cc != 1 */
940 cond = TCG_COND_NE;
941 c->u.s32.b = tcg_const_i32(1);
942 break;
943 case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
944 cond = TCG_COND_EQ;
945 c->g1 = false;
946 c->u.s32.a = tcg_temp_new_i32();
947 c->u.s32.b = tcg_const_i32(0);
948 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
949 break;
950 case 0x8 | 0x4: /* cc < 2 */
951 cond = TCG_COND_LTU;
952 c->u.s32.b = tcg_const_i32(2);
953 break;
954 case 0x8: /* cc == 0 */
955 cond = TCG_COND_EQ;
956 c->u.s32.b = tcg_const_i32(0);
957 break;
958 case 0x4 | 0x2 | 0x1: /* cc != 0 */
959 cond = TCG_COND_NE;
960 c->u.s32.b = tcg_const_i32(0);
961 break;
962 case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
963 cond = TCG_COND_NE;
964 c->g1 = false;
965 c->u.s32.a = tcg_temp_new_i32();
966 c->u.s32.b = tcg_const_i32(0);
967 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
968 break;
969 case 0x4: /* cc == 1 */
970 cond = TCG_COND_EQ;
971 c->u.s32.b = tcg_const_i32(1);
972 break;
973 case 0x2 | 0x1: /* cc > 1 */
974 cond = TCG_COND_GTU;
975 c->u.s32.b = tcg_const_i32(1);
976 break;
977 case 0x2: /* cc == 2 */
978 cond = TCG_COND_EQ;
979 c->u.s32.b = tcg_const_i32(2);
980 break;
981 case 0x1: /* cc == 3 */
982 cond = TCG_COND_EQ;
983 c->u.s32.b = tcg_const_i32(3);
984 break;
985 default:
986 /* CC is masked by something else: (8 >> cc) & mask. */
987 cond = TCG_COND_NE;
988 c->g1 = false;
989 c->u.s32.a = tcg_const_i32(8);
990 c->u.s32.b = tcg_const_i32(0);
991 tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op);
992 tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask);
993 break;
994 }
995 break;
996
997 default:
998 abort();
999 }
1000 c->cond = cond;
1001 }
1002
1003 static void free_compare(DisasCompare *c)
1004 {
1005 if (!c->g1) {
1006 if (c->is_64) {
1007 tcg_temp_free_i64(c->u.s64.a);
1008 } else {
1009 tcg_temp_free_i32(c->u.s32.a);
1010 }
1011 }
1012 if (!c->g2) {
1013 if (c->is_64) {
1014 tcg_temp_free_i64(c->u.s64.b);
1015 } else {
1016 tcg_temp_free_i32(c->u.s32.b);
1017 }
1018 }
1019 }
1020
1021 static void disas_b2(CPUS390XState *env, DisasContext *s, int op,
1022 uint32_t insn)
1023 {
1024 TCGv_i64 tmp, tmp2, tmp3;
1025 TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
1026 int r1, r2;
1027 #ifndef CONFIG_USER_ONLY
1028 int r3, d2, b2;
1029 #endif
1030
1031 r1 = (insn >> 4) & 0xf;
1032 r2 = insn & 0xf;
1033
1034 LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op, r1, r2);
1035
1036 switch (op) {
1037 case 0x4e: /* SAR R1,R2 [RRE] */
1038 tmp32_1 = load_reg32(r2);
1039 tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, aregs[r1]));
1040 tcg_temp_free_i32(tmp32_1);
1041 break;
1042 case 0x4f: /* EAR R1,R2 [RRE] */
1043 tmp32_1 = tcg_temp_new_i32();
1044 tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, aregs[r2]));
1045 store_reg32(r1, tmp32_1);
1046 tcg_temp_free_i32(tmp32_1);
1047 break;
1048 case 0x54: /* MVPG R1,R2 [RRE] */
1049 tmp = load_reg(0);
1050 tmp2 = load_reg(r1);
1051 tmp3 = load_reg(r2);
1052 potential_page_fault(s);
1053 gen_helper_mvpg(cpu_env, tmp, tmp2, tmp3);
1054 tcg_temp_free_i64(tmp);
1055 tcg_temp_free_i64(tmp2);
1056 tcg_temp_free_i64(tmp3);
1057 /* XXX check CCO bit and set CC accordingly */
1058 gen_op_movi_cc(s, 0);
1059 break;
1060 case 0x55: /* MVST R1,R2 [RRE] */
1061 tmp32_1 = load_reg32(0);
1062 tmp32_2 = tcg_const_i32(r1);
1063 tmp32_3 = tcg_const_i32(r2);
1064 potential_page_fault(s);
1065 gen_helper_mvst(cpu_env, tmp32_1, tmp32_2, tmp32_3);
1066 tcg_temp_free_i32(tmp32_1);
1067 tcg_temp_free_i32(tmp32_2);
1068 tcg_temp_free_i32(tmp32_3);
1069 gen_op_movi_cc(s, 1);
1070 break;
1071 case 0x5d: /* CLST R1,R2 [RRE] */
1072 tmp32_1 = load_reg32(0);
1073 tmp32_2 = tcg_const_i32(r1);
1074 tmp32_3 = tcg_const_i32(r2);
1075 potential_page_fault(s);
1076 gen_helper_clst(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1077 set_cc_static(s);
1078 tcg_temp_free_i32(tmp32_1);
1079 tcg_temp_free_i32(tmp32_2);
1080 tcg_temp_free_i32(tmp32_3);
1081 break;
1082 case 0x5e: /* SRST R1,R2 [RRE] */
1083 tmp32_1 = load_reg32(0);
1084 tmp32_2 = tcg_const_i32(r1);
1085 tmp32_3 = tcg_const_i32(r2);
1086 potential_page_fault(s);
1087 gen_helper_srst(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1088 set_cc_static(s);
1089 tcg_temp_free_i32(tmp32_1);
1090 tcg_temp_free_i32(tmp32_2);
1091 tcg_temp_free_i32(tmp32_3);
1092 break;
1093
1094 #ifndef CONFIG_USER_ONLY
1095 case 0x02: /* STIDP D2(B2) [S] */
1096 /* Store CPU ID */
1097 check_privileged(s);
1098 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1099 tmp = get_address(s, 0, b2, d2);
1100 potential_page_fault(s);
1101 gen_helper_stidp(cpu_env, tmp);
1102 tcg_temp_free_i64(tmp);
1103 break;
1104 case 0x04: /* SCK D2(B2) [S] */
1105 /* Set Clock */
1106 check_privileged(s);
1107 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1108 tmp = get_address(s, 0, b2, d2);
1109 potential_page_fault(s);
1110 gen_helper_sck(cc_op, tmp);
1111 set_cc_static(s);
1112 tcg_temp_free_i64(tmp);
1113 break;
1114 case 0x05: /* STCK D2(B2) [S] */
1115 /* Store Clock */
1116 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1117 tmp = get_address(s, 0, b2, d2);
1118 potential_page_fault(s);
1119 gen_helper_stck(cc_op, cpu_env, tmp);
1120 set_cc_static(s);
1121 tcg_temp_free_i64(tmp);
1122 break;
1123 case 0x06: /* SCKC D2(B2) [S] */
1124 /* Set Clock Comparator */
1125 check_privileged(s);
1126 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1127 tmp = get_address(s, 0, b2, d2);
1128 potential_page_fault(s);
1129 gen_helper_sckc(cpu_env, tmp);
1130 tcg_temp_free_i64(tmp);
1131 break;
1132 case 0x07: /* STCKC D2(B2) [S] */
1133 /* Store Clock Comparator */
1134 check_privileged(s);
1135 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1136 tmp = get_address(s, 0, b2, d2);
1137 potential_page_fault(s);
1138 gen_helper_stckc(cpu_env, tmp);
1139 tcg_temp_free_i64(tmp);
1140 break;
1141 case 0x08: /* SPT D2(B2) [S] */
1142 /* Set CPU Timer */
1143 check_privileged(s);
1144 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1145 tmp = get_address(s, 0, b2, d2);
1146 potential_page_fault(s);
1147 gen_helper_spt(cpu_env, tmp);
1148 tcg_temp_free_i64(tmp);
1149 break;
1150 case 0x09: /* STPT D2(B2) [S] */
1151 /* Store CPU Timer */
1152 check_privileged(s);
1153 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1154 tmp = get_address(s, 0, b2, d2);
1155 potential_page_fault(s);
1156 gen_helper_stpt(cpu_env, tmp);
1157 tcg_temp_free_i64(tmp);
1158 break;
1159 case 0x0a: /* SPKA D2(B2) [S] */
1160 /* Set PSW Key from Address */
1161 check_privileged(s);
1162 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1163 tmp = get_address(s, 0, b2, d2);
1164 tmp2 = tcg_temp_new_i64();
1165 tcg_gen_andi_i64(tmp2, psw_mask, ~PSW_MASK_KEY);
1166 tcg_gen_shli_i64(tmp, tmp, PSW_SHIFT_KEY - 4);
1167 tcg_gen_or_i64(psw_mask, tmp2, tmp);
1168 tcg_temp_free_i64(tmp2);
1169 tcg_temp_free_i64(tmp);
1170 break;
1171 case 0x0d: /* PTLB [S] */
1172 /* Purge TLB */
1173 check_privileged(s);
1174 gen_helper_ptlb(cpu_env);
1175 break;
1176 case 0x10: /* SPX D2(B2) [S] */
1177 /* Set Prefix Register */
1178 check_privileged(s);
1179 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1180 tmp = get_address(s, 0, b2, d2);
1181 potential_page_fault(s);
1182 gen_helper_spx(cpu_env, tmp);
1183 tcg_temp_free_i64(tmp);
1184 break;
1185 case 0x11: /* STPX D2(B2) [S] */
1186 /* Store Prefix */
1187 check_privileged(s);
1188 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1189 tmp = get_address(s, 0, b2, d2);
1190 tmp2 = tcg_temp_new_i64();
1191 tcg_gen_ld_i64(tmp2, cpu_env, offsetof(CPUS390XState, psa));
1192 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1193 tcg_temp_free_i64(tmp);
1194 tcg_temp_free_i64(tmp2);
1195 break;
1196 case 0x12: /* STAP D2(B2) [S] */
1197 /* Store CPU Address */
1198 check_privileged(s);
1199 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1200 tmp = get_address(s, 0, b2, d2);
1201 tmp2 = tcg_temp_new_i64();
1202 tmp32_1 = tcg_temp_new_i32();
1203 tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, cpu_num));
1204 tcg_gen_extu_i32_i64(tmp2, tmp32_1);
1205 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1206 tcg_temp_free_i64(tmp);
1207 tcg_temp_free_i64(tmp2);
1208 tcg_temp_free_i32(tmp32_1);
1209 break;
1210 case 0x21: /* IPTE R1,R2 [RRE] */
1211 /* Invalidate PTE */
1212 check_privileged(s);
1213 r1 = (insn >> 4) & 0xf;
1214 r2 = insn & 0xf;
1215 tmp = load_reg(r1);
1216 tmp2 = load_reg(r2);
1217 gen_helper_ipte(cpu_env, tmp, tmp2);
1218 tcg_temp_free_i64(tmp);
1219 tcg_temp_free_i64(tmp2);
1220 break;
1221 case 0x29: /* ISKE R1,R2 [RRE] */
1222 /* Insert Storage Key Extended */
1223 check_privileged(s);
1224 r1 = (insn >> 4) & 0xf;
1225 r2 = insn & 0xf;
1226 tmp = load_reg(r2);
1227 tmp2 = tcg_temp_new_i64();
1228 gen_helper_iske(tmp2, cpu_env, tmp);
1229 store_reg(r1, tmp2);
1230 tcg_temp_free_i64(tmp);
1231 tcg_temp_free_i64(tmp2);
1232 break;
1233 case 0x2a: /* RRBE R1,R2 [RRE] */
1234 /* Set Storage Key Extended */
1235 check_privileged(s);
1236 r1 = (insn >> 4) & 0xf;
1237 r2 = insn & 0xf;
1238 tmp32_1 = load_reg32(r1);
1239 tmp = load_reg(r2);
1240 gen_helper_rrbe(cc_op, cpu_env, tmp32_1, tmp);
1241 set_cc_static(s);
1242 tcg_temp_free_i32(tmp32_1);
1243 tcg_temp_free_i64(tmp);
1244 break;
1245 case 0x2b: /* SSKE R1,R2 [RRE] */
1246 /* Set Storage Key Extended */
1247 check_privileged(s);
1248 r1 = (insn >> 4) & 0xf;
1249 r2 = insn & 0xf;
1250 tmp32_1 = load_reg32(r1);
1251 tmp = load_reg(r2);
1252 gen_helper_sske(cpu_env, tmp32_1, tmp);
1253 tcg_temp_free_i32(tmp32_1);
1254 tcg_temp_free_i64(tmp);
1255 break;
1256 case 0x34: /* STCH ? */
1257 /* Store Subchannel */
1258 check_privileged(s);
1259 gen_op_movi_cc(s, 3);
1260 break;
1261 case 0x46: /* STURA R1,R2 [RRE] */
1262 /* Store Using Real Address */
1263 check_privileged(s);
1264 r1 = (insn >> 4) & 0xf;
1265 r2 = insn & 0xf;
1266 tmp32_1 = load_reg32(r1);
1267 tmp = load_reg(r2);
1268 potential_page_fault(s);
1269 gen_helper_stura(cpu_env, tmp, tmp32_1);
1270 tcg_temp_free_i32(tmp32_1);
1271 tcg_temp_free_i64(tmp);
1272 break;
1273 case 0x50: /* CSP R1,R2 [RRE] */
1274 /* Compare And Swap And Purge */
1275 check_privileged(s);
1276 r1 = (insn >> 4) & 0xf;
1277 r2 = insn & 0xf;
1278 tmp32_1 = tcg_const_i32(r1);
1279 tmp32_2 = tcg_const_i32(r2);
1280 gen_helper_csp(cc_op, cpu_env, tmp32_1, tmp32_2);
1281 set_cc_static(s);
1282 tcg_temp_free_i32(tmp32_1);
1283 tcg_temp_free_i32(tmp32_2);
1284 break;
1285 case 0x5f: /* CHSC ? */
1286 /* Channel Subsystem Call */
1287 check_privileged(s);
1288 gen_op_movi_cc(s, 3);
1289 break;
1290 case 0x78: /* STCKE D2(B2) [S] */
1291 /* Store Clock Extended */
1292 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1293 tmp = get_address(s, 0, b2, d2);
1294 potential_page_fault(s);
1295 gen_helper_stcke(cc_op, cpu_env, tmp);
1296 set_cc_static(s);
1297 tcg_temp_free_i64(tmp);
1298 break;
1299 case 0x79: /* SACF D2(B2) [S] */
1300 /* Set Address Space Control Fast */
1301 check_privileged(s);
1302 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1303 tmp = get_address(s, 0, b2, d2);
1304 potential_page_fault(s);
1305 gen_helper_sacf(cpu_env, tmp);
1306 tcg_temp_free_i64(tmp);
1307 /* addressing mode has changed, so end the block */
1308 s->pc = s->next_pc;
1309 update_psw_addr(s);
1310 s->is_jmp = DISAS_JUMP;
1311 break;
1312 case 0x7d: /* STSI D2,(B2) [S] */
1313 check_privileged(s);
1314 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1315 tmp = get_address(s, 0, b2, d2);
1316 tmp32_1 = load_reg32(0);
1317 tmp32_2 = load_reg32(1);
1318 potential_page_fault(s);
1319 gen_helper_stsi(cc_op, cpu_env, tmp, tmp32_1, tmp32_2);
1320 set_cc_static(s);
1321 tcg_temp_free_i64(tmp);
1322 tcg_temp_free_i32(tmp32_1);
1323 tcg_temp_free_i32(tmp32_2);
1324 break;
1325 case 0xb1: /* STFL D2(B2) [S] */
1326 /* Store Facility List (CPU features) at 200 */
1327 check_privileged(s);
1328 tmp2 = tcg_const_i64(0xc0000000);
1329 tmp = tcg_const_i64(200);
1330 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1331 tcg_temp_free_i64(tmp2);
1332 tcg_temp_free_i64(tmp);
1333 break;
1334 case 0xb2: /* LPSWE D2(B2) [S] */
1335 /* Load PSW Extended */
1336 check_privileged(s);
1337 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1338 tmp = get_address(s, 0, b2, d2);
1339 tmp2 = tcg_temp_new_i64();
1340 tmp3 = tcg_temp_new_i64();
1341 tcg_gen_qemu_ld64(tmp2, tmp, get_mem_index(s));
1342 tcg_gen_addi_i64(tmp, tmp, 8);
1343 tcg_gen_qemu_ld64(tmp3, tmp, get_mem_index(s));
1344 gen_helper_load_psw(cpu_env, tmp2, tmp3);
1345 /* we need to keep cc_op intact */
1346 s->is_jmp = DISAS_JUMP;
1347 tcg_temp_free_i64(tmp);
1348 tcg_temp_free_i64(tmp2);
1349 tcg_temp_free_i64(tmp3);
1350 break;
1351 case 0x20: /* SERVC R1,R2 [RRE] */
1352 /* SCLP Service call (PV hypercall) */
1353 check_privileged(s);
1354 potential_page_fault(s);
1355 tmp32_1 = load_reg32(r2);
1356 tmp = load_reg(r1);
1357 gen_helper_servc(cc_op, cpu_env, tmp32_1, tmp);
1358 set_cc_static(s);
1359 tcg_temp_free_i32(tmp32_1);
1360 tcg_temp_free_i64(tmp);
1361 break;
1362 #endif
1363 default:
1364 LOG_DISAS("illegal b2 operation 0x%x\n", op);
1365 gen_illegal_opcode(s);
1366 break;
1367 }
1368 }
1369
1370 static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
1371 {
1372 unsigned char opc;
1373 uint64_t insn;
1374 int op;
1375
1376 opc = cpu_ldub_code(env, s->pc);
1377 LOG_DISAS("opc 0x%x\n", opc);
1378
1379 switch (opc) {
1380 case 0xb2:
1381 insn = ld_code4(env, s->pc);
1382 op = (insn >> 16) & 0xff;
1383 disas_b2(env, s, op, insn);
1384 break;
1385 default:
1386 qemu_log_mask(LOG_UNIMP, "unimplemented opcode 0x%x\n", opc);
1387 gen_illegal_opcode(s);
1388 break;
1389 }
1390 }
1391
1392 /* ====================================================================== */
1393 /* Define the insn format enumeration. */
1394 #define F0(N) FMT_##N,
1395 #define F1(N, X1) F0(N)
1396 #define F2(N, X1, X2) F0(N)
1397 #define F3(N, X1, X2, X3) F0(N)
1398 #define F4(N, X1, X2, X3, X4) F0(N)
1399 #define F5(N, X1, X2, X3, X4, X5) F0(N)
1400
1401 typedef enum {
1402 #include "insn-format.def"
1403 } DisasFormat;
1404
1405 #undef F0
1406 #undef F1
1407 #undef F2
1408 #undef F3
1409 #undef F4
1410 #undef F5
1411
1412 /* Define a structure to hold the decoded fields. We'll store each inside
1413 an array indexed by an enum. In order to conserve memory, we'll arrange
1414 for fields that do not exist at the same time to overlap, thus the "C"
1415 for compact. For checking purposes there is an "O" for original index
1416 as well that will be applied to availability bitmaps. */
1417
1418 enum DisasFieldIndexO {
1419 FLD_O_r1,
1420 FLD_O_r2,
1421 FLD_O_r3,
1422 FLD_O_m1,
1423 FLD_O_m3,
1424 FLD_O_m4,
1425 FLD_O_b1,
1426 FLD_O_b2,
1427 FLD_O_b4,
1428 FLD_O_d1,
1429 FLD_O_d2,
1430 FLD_O_d4,
1431 FLD_O_x2,
1432 FLD_O_l1,
1433 FLD_O_l2,
1434 FLD_O_i1,
1435 FLD_O_i2,
1436 FLD_O_i3,
1437 FLD_O_i4,
1438 FLD_O_i5
1439 };
1440
1441 enum DisasFieldIndexC {
1442 FLD_C_r1 = 0,
1443 FLD_C_m1 = 0,
1444 FLD_C_b1 = 0,
1445 FLD_C_i1 = 0,
1446
1447 FLD_C_r2 = 1,
1448 FLD_C_b2 = 1,
1449 FLD_C_i2 = 1,
1450
1451 FLD_C_r3 = 2,
1452 FLD_C_m3 = 2,
1453 FLD_C_i3 = 2,
1454
1455 FLD_C_m4 = 3,
1456 FLD_C_b4 = 3,
1457 FLD_C_i4 = 3,
1458 FLD_C_l1 = 3,
1459
1460 FLD_C_i5 = 4,
1461 FLD_C_d1 = 4,
1462
1463 FLD_C_d2 = 5,
1464
1465 FLD_C_d4 = 6,
1466 FLD_C_x2 = 6,
1467 FLD_C_l2 = 6,
1468
1469 NUM_C_FIELD = 7
1470 };
1471
1472 struct DisasFields {
1473 unsigned op:8;
1474 unsigned op2:8;
1475 unsigned presentC:16;
1476 unsigned int presentO;
1477 int c[NUM_C_FIELD];
1478 };
1479
1480 /* This is the way fields are to be accessed out of DisasFields. */
1481 #define have_field(S, F) have_field1((S), FLD_O_##F)
1482 #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
1483
1484 static bool have_field1(const DisasFields *f, enum DisasFieldIndexO c)
1485 {
1486 return (f->presentO >> c) & 1;
1487 }
1488
1489 static int get_field1(const DisasFields *f, enum DisasFieldIndexO o,
1490 enum DisasFieldIndexC c)
1491 {
1492 assert(have_field1(f, o));
1493 return f->c[c];
1494 }
1495
1496 /* Describe the layout of each field in each format. */
1497 typedef struct DisasField {
1498 unsigned int beg:8;
1499 unsigned int size:8;
1500 unsigned int type:2;
1501 unsigned int indexC:6;
1502 enum DisasFieldIndexO indexO:8;
1503 } DisasField;
1504
1505 typedef struct DisasFormatInfo {
1506 DisasField op[NUM_C_FIELD];
1507 } DisasFormatInfo;
1508
1509 #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
1510 #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
1511 #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1512 { BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
1513 #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1514 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1515 { 20, 12, 0, FLD_C_d##N, FLD_O_d##N }
1516 #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1517 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1518 #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1519 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1520 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1521 #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N }
1522 #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N }
1523
1524 #define F0(N) { { } },
1525 #define F1(N, X1) { { X1 } },
1526 #define F2(N, X1, X2) { { X1, X2 } },
1527 #define F3(N, X1, X2, X3) { { X1, X2, X3 } },
1528 #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
1529 #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
1530
1531 static const DisasFormatInfo format_info[] = {
1532 #include "insn-format.def"
1533 };
1534
1535 #undef F0
1536 #undef F1
1537 #undef F2
1538 #undef F3
1539 #undef F4
1540 #undef F5
1541 #undef R
1542 #undef M
1543 #undef BD
1544 #undef BXD
1545 #undef BDL
1546 #undef BXDL
1547 #undef I
1548 #undef L
1549
1550 /* Generally, we'll extract operands into this structures, operate upon
1551 them, and store them back. See the "in1", "in2", "prep", "wout" sets
1552 of routines below for more details. */
1553 typedef struct {
1554 bool g_out, g_out2, g_in1, g_in2;
1555 TCGv_i64 out, out2, in1, in2;
1556 TCGv_i64 addr1;
1557 } DisasOps;
1558
1559 /* Return values from translate_one, indicating the state of the TB. */
1560 typedef enum {
1561 /* Continue the TB. */
1562 NO_EXIT,
1563 /* We have emitted one or more goto_tb. No fixup required. */
1564 EXIT_GOTO_TB,
1565 /* We are not using a goto_tb (for whatever reason), but have updated
1566 the PC (for whatever reason), so there's no need to do it again on
1567 exiting the TB. */
1568 EXIT_PC_UPDATED,
1569 /* We are exiting the TB, but have neither emitted a goto_tb, nor
1570 updated the PC for the next instruction to be executed. */
1571 EXIT_PC_STALE,
1572 /* We are ending the TB with a noreturn function call, e.g. longjmp.
1573 No following code will be executed. */
1574 EXIT_NORETURN,
1575 } ExitStatus;
1576
1577 typedef enum DisasFacility {
1578 FAC_Z, /* zarch (default) */
1579 FAC_CASS, /* compare and swap and store */
1580 FAC_CASS2, /* compare and swap and store 2*/
1581 FAC_DFP, /* decimal floating point */
1582 FAC_DFPR, /* decimal floating point rounding */
1583 FAC_DO, /* distinct operands */
1584 FAC_EE, /* execute extensions */
1585 FAC_EI, /* extended immediate */
1586 FAC_FPE, /* floating point extension */
1587 FAC_FPSSH, /* floating point support sign handling */
1588 FAC_FPRGR, /* FPR-GR transfer */
1589 FAC_GIE, /* general instructions extension */
1590 FAC_HFP_MA, /* HFP multiply-and-add/subtract */
1591 FAC_HW, /* high-word */
1592 FAC_IEEEE_SIM, /* IEEE exception sumilation */
1593 FAC_LOC, /* load/store on condition */
1594 FAC_LD, /* long displacement */
1595 FAC_PC, /* population count */
1596 FAC_SCF, /* store clock fast */
1597 FAC_SFLE, /* store facility list extended */
1598 } DisasFacility;
1599
1600 struct DisasInsn {
1601 unsigned opc:16;
1602 DisasFormat fmt:6;
1603 DisasFacility fac:6;
1604
1605 const char *name;
1606
1607 void (*help_in1)(DisasContext *, DisasFields *, DisasOps *);
1608 void (*help_in2)(DisasContext *, DisasFields *, DisasOps *);
1609 void (*help_prep)(DisasContext *, DisasFields *, DisasOps *);
1610 void (*help_wout)(DisasContext *, DisasFields *, DisasOps *);
1611 void (*help_cout)(DisasContext *, DisasOps *);
1612 ExitStatus (*help_op)(DisasContext *, DisasOps *);
1613
1614 uint64_t data;
1615 };
1616
1617 /* ====================================================================== */
1618 /* Miscelaneous helpers, used by several operations. */
1619
1620 static void help_l2_shift(DisasContext *s, DisasFields *f,
1621 DisasOps *o, int mask)
1622 {
1623 int b2 = get_field(f, b2);
1624 int d2 = get_field(f, d2);
1625
1626 if (b2 == 0) {
1627 o->in2 = tcg_const_i64(d2 & mask);
1628 } else {
1629 o->in2 = get_address(s, 0, b2, d2);
1630 tcg_gen_andi_i64(o->in2, o->in2, mask);
1631 }
1632 }
1633
1634 static ExitStatus help_goto_direct(DisasContext *s, uint64_t dest)
1635 {
1636 if (dest == s->next_pc) {
1637 return NO_EXIT;
1638 }
1639 if (use_goto_tb(s, dest)) {
1640 gen_update_cc_op(s);
1641 tcg_gen_goto_tb(0);
1642 tcg_gen_movi_i64(psw_addr, dest);
1643 tcg_gen_exit_tb((tcg_target_long)s->tb);
1644 return EXIT_GOTO_TB;
1645 } else {
1646 tcg_gen_movi_i64(psw_addr, dest);
1647 return EXIT_PC_UPDATED;
1648 }
1649 }
1650
1651 static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
1652 bool is_imm, int imm, TCGv_i64 cdest)
1653 {
1654 ExitStatus ret;
1655 uint64_t dest = s->pc + 2 * imm;
1656 int lab;
1657
1658 /* Take care of the special cases first. */
1659 if (c->cond == TCG_COND_NEVER) {
1660 ret = NO_EXIT;
1661 goto egress;
1662 }
1663 if (is_imm) {
1664 if (dest == s->next_pc) {
1665 /* Branch to next. */
1666 ret = NO_EXIT;
1667 goto egress;
1668 }
1669 if (c->cond == TCG_COND_ALWAYS) {
1670 ret = help_goto_direct(s, dest);
1671 goto egress;
1672 }
1673 } else {
1674 if (TCGV_IS_UNUSED_I64(cdest)) {
1675 /* E.g. bcr %r0 -> no branch. */
1676 ret = NO_EXIT;
1677 goto egress;
1678 }
1679 if (c->cond == TCG_COND_ALWAYS) {
1680 tcg_gen_mov_i64(psw_addr, cdest);
1681 ret = EXIT_PC_UPDATED;
1682 goto egress;
1683 }
1684 }
1685
1686 if (use_goto_tb(s, s->next_pc)) {
1687 if (is_imm && use_goto_tb(s, dest)) {
1688 /* Both exits can use goto_tb. */
1689 gen_update_cc_op(s);
1690
1691 lab = gen_new_label();
1692 if (c->is_64) {
1693 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1694 } else {
1695 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1696 }
1697
1698 /* Branch not taken. */
1699 tcg_gen_goto_tb(0);
1700 tcg_gen_movi_i64(psw_addr, s->next_pc);
1701 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
1702
1703 /* Branch taken. */
1704 gen_set_label(lab);
1705 tcg_gen_goto_tb(1);
1706 tcg_gen_movi_i64(psw_addr, dest);
1707 tcg_gen_exit_tb((tcg_target_long)s->tb + 1);
1708
1709 ret = EXIT_GOTO_TB;
1710 } else {
1711 /* Fallthru can use goto_tb, but taken branch cannot. */
1712 /* Store taken branch destination before the brcond. This
1713 avoids having to allocate a new local temp to hold it.
1714 We'll overwrite this in the not taken case anyway. */
1715 if (!is_imm) {
1716 tcg_gen_mov_i64(psw_addr, cdest);
1717 }
1718
1719 lab = gen_new_label();
1720 if (c->is_64) {
1721 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1722 } else {
1723 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1724 }
1725
1726 /* Branch not taken. */
1727 gen_update_cc_op(s);
1728 tcg_gen_goto_tb(0);
1729 tcg_gen_movi_i64(psw_addr, s->next_pc);
1730 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
1731
1732 gen_set_label(lab);
1733 if (is_imm) {
1734 tcg_gen_movi_i64(psw_addr, dest);
1735 }
1736 ret = EXIT_PC_UPDATED;
1737 }
1738 } else {
1739 /* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
1740 Most commonly we're single-stepping or some other condition that
1741 disables all use of goto_tb. Just update the PC and exit. */
1742
1743 TCGv_i64 next = tcg_const_i64(s->next_pc);
1744 if (is_imm) {
1745 cdest = tcg_const_i64(dest);
1746 }
1747
1748 if (c->is_64) {
1749 tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b,
1750 cdest, next);
1751 } else {
1752 TCGv_i32 t0 = tcg_temp_new_i32();
1753 TCGv_i64 t1 = tcg_temp_new_i64();
1754 TCGv_i64 z = tcg_const_i64(0);
1755 tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b);
1756 tcg_gen_extu_i32_i64(t1, t0);
1757 tcg_temp_free_i32(t0);
1758 tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next);
1759 tcg_temp_free_i64(t1);
1760 tcg_temp_free_i64(z);
1761 }
1762
1763 if (is_imm) {
1764 tcg_temp_free_i64(cdest);
1765 }
1766 tcg_temp_free_i64(next);
1767
1768 ret = EXIT_PC_UPDATED;
1769 }
1770
1771 egress:
1772 free_compare(c);
1773 return ret;
1774 }
1775
1776 /* ====================================================================== */
1777 /* The operations. These perform the bulk of the work for any insn,
1778 usually after the operands have been loaded and output initialized. */
1779
1780 static ExitStatus op_abs(DisasContext *s, DisasOps *o)
1781 {
1782 gen_helper_abs_i64(o->out, o->in2);
1783 return NO_EXIT;
1784 }
1785
1786 static ExitStatus op_absf32(DisasContext *s, DisasOps *o)
1787 {
1788 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffull);
1789 return NO_EXIT;
1790 }
1791
1792 static ExitStatus op_absf64(DisasContext *s, DisasOps *o)
1793 {
1794 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull);
1795 return NO_EXIT;
1796 }
1797
1798 static ExitStatus op_absf128(DisasContext *s, DisasOps *o)
1799 {
1800 tcg_gen_andi_i64(o->out, o->in1, 0x7fffffffffffffffull);
1801 tcg_gen_mov_i64(o->out2, o->in2);
1802 return NO_EXIT;
1803 }
1804
1805 static ExitStatus op_add(DisasContext *s, DisasOps *o)
1806 {
1807 tcg_gen_add_i64(o->out, o->in1, o->in2);
1808 return NO_EXIT;
1809 }
1810
1811 static ExitStatus op_addc(DisasContext *s, DisasOps *o)
1812 {
1813 TCGv_i64 cc;
1814
1815 tcg_gen_add_i64(o->out, o->in1, o->in2);
1816
1817 /* XXX possible optimization point */
1818 gen_op_calc_cc(s);
1819 cc = tcg_temp_new_i64();
1820 tcg_gen_extu_i32_i64(cc, cc_op);
1821 tcg_gen_shri_i64(cc, cc, 1);
1822
1823 tcg_gen_add_i64(o->out, o->out, cc);
1824 tcg_temp_free_i64(cc);
1825 return NO_EXIT;
1826 }
1827
1828 static ExitStatus op_aeb(DisasContext *s, DisasOps *o)
1829 {
1830 gen_helper_aeb(o->out, cpu_env, o->in1, o->in2);
1831 return NO_EXIT;
1832 }
1833
1834 static ExitStatus op_adb(DisasContext *s, DisasOps *o)
1835 {
1836 gen_helper_adb(o->out, cpu_env, o->in1, o->in2);
1837 return NO_EXIT;
1838 }
1839
1840 static ExitStatus op_axb(DisasContext *s, DisasOps *o)
1841 {
1842 gen_helper_axb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
1843 return_low128(o->out2);
1844 return NO_EXIT;
1845 }
1846
1847 static ExitStatus op_and(DisasContext *s, DisasOps *o)
1848 {
1849 tcg_gen_and_i64(o->out, o->in1, o->in2);
1850 return NO_EXIT;
1851 }
1852
1853 static ExitStatus op_andi(DisasContext *s, DisasOps *o)
1854 {
1855 int shift = s->insn->data & 0xff;
1856 int size = s->insn->data >> 8;
1857 uint64_t mask = ((1ull << size) - 1) << shift;
1858
1859 assert(!o->g_in2);
1860 tcg_gen_shli_i64(o->in2, o->in2, shift);
1861 tcg_gen_ori_i64(o->in2, o->in2, ~mask);
1862 tcg_gen_and_i64(o->out, o->in1, o->in2);
1863
1864 /* Produce the CC from only the bits manipulated. */
1865 tcg_gen_andi_i64(cc_dst, o->out, mask);
1866 set_cc_nz_u64(s, cc_dst);
1867 return NO_EXIT;
1868 }
1869
1870 static ExitStatus op_bas(DisasContext *s, DisasOps *o)
1871 {
1872 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1873 if (!TCGV_IS_UNUSED_I64(o->in2)) {
1874 tcg_gen_mov_i64(psw_addr, o->in2);
1875 return EXIT_PC_UPDATED;
1876 } else {
1877 return NO_EXIT;
1878 }
1879 }
1880
1881 static ExitStatus op_basi(DisasContext *s, DisasOps *o)
1882 {
1883 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1884 return help_goto_direct(s, s->pc + 2 * get_field(s->fields, i2));
1885 }
1886
1887 static ExitStatus op_bc(DisasContext *s, DisasOps *o)
1888 {
1889 int m1 = get_field(s->fields, m1);
1890 bool is_imm = have_field(s->fields, i2);
1891 int imm = is_imm ? get_field(s->fields, i2) : 0;
1892 DisasCompare c;
1893
1894 disas_jcc(s, &c, m1);
1895 return help_branch(s, &c, is_imm, imm, o->in2);
1896 }
1897
1898 static ExitStatus op_bct32(DisasContext *s, DisasOps *o)
1899 {
1900 int r1 = get_field(s->fields, r1);
1901 bool is_imm = have_field(s->fields, i2);
1902 int imm = is_imm ? get_field(s->fields, i2) : 0;
1903 DisasCompare c;
1904 TCGv_i64 t;
1905
1906 c.cond = TCG_COND_NE;
1907 c.is_64 = false;
1908 c.g1 = false;
1909 c.g2 = false;
1910
1911 t = tcg_temp_new_i64();
1912 tcg_gen_subi_i64(t, regs[r1], 1);
1913 store_reg32_i64(r1, t);
1914 c.u.s32.a = tcg_temp_new_i32();
1915 c.u.s32.b = tcg_const_i32(0);
1916 tcg_gen_trunc_i64_i32(c.u.s32.a, t);
1917 tcg_temp_free_i64(t);
1918
1919 return help_branch(s, &c, is_imm, imm, o->in2);
1920 }
1921
1922 static ExitStatus op_bct64(DisasContext *s, DisasOps *o)
1923 {
1924 int r1 = get_field(s->fields, r1);
1925 bool is_imm = have_field(s->fields, i2);
1926 int imm = is_imm ? get_field(s->fields, i2) : 0;
1927 DisasCompare c;
1928
1929 c.cond = TCG_COND_NE;
1930 c.is_64 = true;
1931 c.g1 = true;
1932 c.g2 = false;
1933
1934 tcg_gen_subi_i64(regs[r1], regs[r1], 1);
1935 c.u.s64.a = regs[r1];
1936 c.u.s64.b = tcg_const_i64(0);
1937
1938 return help_branch(s, &c, is_imm, imm, o->in2);
1939 }
1940
1941 static ExitStatus op_ceb(DisasContext *s, DisasOps *o)
1942 {
1943 gen_helper_ceb(cc_op, cpu_env, o->in1, o->in2);
1944 set_cc_static(s);
1945 return NO_EXIT;
1946 }
1947
1948 static ExitStatus op_cdb(DisasContext *s, DisasOps *o)
1949 {
1950 gen_helper_cdb(cc_op, cpu_env, o->in1, o->in2);
1951 set_cc_static(s);
1952 return NO_EXIT;
1953 }
1954
1955 static ExitStatus op_cxb(DisasContext *s, DisasOps *o)
1956 {
1957 gen_helper_cxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2);
1958 set_cc_static(s);
1959 return NO_EXIT;
1960 }
1961
1962 static ExitStatus op_cfeb(DisasContext *s, DisasOps *o)
1963 {
1964 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1965 gen_helper_cfeb(o->out, cpu_env, o->in2, m3);
1966 tcg_temp_free_i32(m3);
1967 gen_set_cc_nz_f32(s, o->in2);
1968 return NO_EXIT;
1969 }
1970
1971 static ExitStatus op_cfdb(DisasContext *s, DisasOps *o)
1972 {
1973 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1974 gen_helper_cfdb(o->out, cpu_env, o->in2, m3);
1975 tcg_temp_free_i32(m3);
1976 gen_set_cc_nz_f64(s, o->in2);
1977 return NO_EXIT;
1978 }
1979
1980 static ExitStatus op_cfxb(DisasContext *s, DisasOps *o)
1981 {
1982 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1983 gen_helper_cfxb(o->out, cpu_env, o->in1, o->in2, m3);
1984 tcg_temp_free_i32(m3);
1985 gen_set_cc_nz_f128(s, o->in1, o->in2);
1986 return NO_EXIT;
1987 }
1988
1989 static ExitStatus op_cgeb(DisasContext *s, DisasOps *o)
1990 {
1991 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1992 gen_helper_cgeb(o->out, cpu_env, o->in2, m3);
1993 tcg_temp_free_i32(m3);
1994 gen_set_cc_nz_f32(s, o->in2);
1995 return NO_EXIT;
1996 }
1997
1998 static ExitStatus op_cgdb(DisasContext *s, DisasOps *o)
1999 {
2000 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
2001 gen_helper_cgdb(o->out, cpu_env, o->in2, m3);
2002 tcg_temp_free_i32(m3);
2003 gen_set_cc_nz_f64(s, o->in2);
2004 return NO_EXIT;
2005 }
2006
2007 static ExitStatus op_cgxb(DisasContext *s, DisasOps *o)
2008 {
2009 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
2010 gen_helper_cgxb(o->out, cpu_env, o->in1, o->in2, m3);
2011 tcg_temp_free_i32(m3);
2012 gen_set_cc_nz_f128(s, o->in1, o->in2);
2013 return NO_EXIT;
2014 }
2015
2016 static ExitStatus op_cegb(DisasContext *s, DisasOps *o)
2017 {
2018 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
2019 gen_helper_cegb(o->out, cpu_env, o->in2, m3);
2020 tcg_temp_free_i32(m3);
2021 return NO_EXIT;
2022 }
2023
2024 static ExitStatus op_cdgb(DisasContext *s, DisasOps *o)
2025 {
2026 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
2027 gen_helper_cdgb(o->out, cpu_env, o->in2, m3);
2028 tcg_temp_free_i32(m3);
2029 return NO_EXIT;
2030 }
2031
2032 static ExitStatus op_cxgb(DisasContext *s, DisasOps *o)
2033 {
2034 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
2035 gen_helper_cxgb(o->out, cpu_env, o->in2, m3);
2036 tcg_temp_free_i32(m3);
2037 return_low128(o->out2);
2038 return NO_EXIT;
2039 }
2040
2041 static ExitStatus op_cksm(DisasContext *s, DisasOps *o)
2042 {
2043 int r2 = get_field(s->fields, r2);
2044 TCGv_i64 len = tcg_temp_new_i64();
2045
2046 potential_page_fault(s);
2047 gen_helper_cksm(len, cpu_env, o->in1, o->in2, regs[r2 + 1]);
2048 set_cc_static(s);
2049 return_low128(o->out);
2050
2051 tcg_gen_add_i64(regs[r2], regs[r2], len);
2052 tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len);
2053 tcg_temp_free_i64(len);
2054
2055 return NO_EXIT;
2056 }
2057
2058 static ExitStatus op_clc(DisasContext *s, DisasOps *o)
2059 {
2060 int l = get_field(s->fields, l1);
2061 TCGv_i32 vl;
2062
2063 switch (l + 1) {
2064 case 1:
2065 tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s));
2066 tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s));
2067 break;
2068 case 2:
2069 tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s));
2070 tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s));
2071 break;
2072 case 4:
2073 tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s));
2074 tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s));
2075 break;
2076 case 8:
2077 tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s));
2078 tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s));
2079 break;
2080 default:
2081 potential_page_fault(s);
2082 vl = tcg_const_i32(l);
2083 gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
2084 tcg_temp_free_i32(vl);
2085 set_cc_static(s);
2086 return NO_EXIT;
2087 }
2088 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
2089 return NO_EXIT;
2090 }
2091
2092 static ExitStatus op_clcle(DisasContext *s, DisasOps *o)
2093 {
2094 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2095 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2096 potential_page_fault(s);
2097 gen_helper_clcle(cc_op, cpu_env, r1, o->in2, r3);
2098 tcg_temp_free_i32(r1);
2099 tcg_temp_free_i32(r3);
2100 set_cc_static(s);
2101 return NO_EXIT;
2102 }
2103
2104 static ExitStatus op_clm(DisasContext *s, DisasOps *o)
2105 {
2106 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
2107 TCGv_i32 t1 = tcg_temp_new_i32();
2108 tcg_gen_trunc_i64_i32(t1, o->in1);
2109 potential_page_fault(s);
2110 gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2);
2111 set_cc_static(s);
2112 tcg_temp_free_i32(t1);
2113 tcg_temp_free_i32(m3);
2114 return NO_EXIT;
2115 }
2116
2117 static ExitStatus op_cs(DisasContext *s, DisasOps *o)
2118 {
2119 int r3 = get_field(s->fields, r3);
2120 potential_page_fault(s);
2121 gen_helper_cs(o->out, cpu_env, o->in1, o->in2, regs[r3]);
2122 set_cc_static(s);
2123 return NO_EXIT;
2124 }
2125
2126 static ExitStatus op_csg(DisasContext *s, DisasOps *o)
2127 {
2128 int r3 = get_field(s->fields, r3);
2129 potential_page_fault(s);
2130 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, regs[r3]);
2131 set_cc_static(s);
2132 return NO_EXIT;
2133 }
2134
2135 static ExitStatus op_cds(DisasContext *s, DisasOps *o)
2136 {
2137 int r3 = get_field(s->fields, r3);
2138 TCGv_i64 in3 = tcg_temp_new_i64();
2139 tcg_gen_deposit_i64(in3, regs[r3 + 1], regs[r3], 32, 32);
2140 potential_page_fault(s);
2141 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, in3);
2142 tcg_temp_free_i64(in3);
2143 set_cc_static(s);
2144 return NO_EXIT;
2145 }
2146
2147 static ExitStatus op_cdsg(DisasContext *s, DisasOps *o)
2148 {
2149 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2150 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2151 potential_page_fault(s);
2152 /* XXX rewrite in tcg */
2153 gen_helper_cdsg(cc_op, cpu_env, r1, o->in2, r3);
2154 set_cc_static(s);
2155 return NO_EXIT;
2156 }
2157
2158 static ExitStatus op_cvd(DisasContext *s, DisasOps *o)
2159 {
2160 TCGv_i64 t1 = tcg_temp_new_i64();
2161 TCGv_i32 t2 = tcg_temp_new_i32();
2162 tcg_gen_trunc_i64_i32(t2, o->in1);
2163 gen_helper_cvd(t1, t2);
2164 tcg_temp_free_i32(t2);
2165 tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
2166 tcg_temp_free_i64(t1);
2167 return NO_EXIT;
2168 }
2169
2170 #ifndef CONFIG_USER_ONLY
2171 static ExitStatus op_diag(DisasContext *s, DisasOps *o)
2172 {
2173 TCGv_i32 tmp;
2174
2175 check_privileged(s);
2176 potential_page_fault(s);
2177
2178 /* We pretend the format is RX_a so that D2 is the field we want. */
2179 tmp = tcg_const_i32(get_field(s->fields, d2) & 0xfff);
2180 gen_helper_diag(regs[2], cpu_env, tmp, regs[2], regs[1]);
2181 tcg_temp_free_i32(tmp);
2182 return NO_EXIT;
2183 }
2184 #endif
2185
2186 static ExitStatus op_divs32(DisasContext *s, DisasOps *o)
2187 {
2188 gen_helper_divs32(o->out2, cpu_env, o->in1, o->in2);
2189 return_low128(o->out);
2190 return NO_EXIT;
2191 }
2192
2193 static ExitStatus op_divu32(DisasContext *s, DisasOps *o)
2194 {
2195 gen_helper_divu32(o->out2, cpu_env, o->in1, o->in2);
2196 return_low128(o->out);
2197 return NO_EXIT;
2198 }
2199
2200 static ExitStatus op_divs64(DisasContext *s, DisasOps *o)
2201 {
2202 gen_helper_divs64(o->out2, cpu_env, o->in1, o->in2);
2203 return_low128(o->out);
2204 return NO_EXIT;
2205 }
2206
2207 static ExitStatus op_divu64(DisasContext *s, DisasOps *o)
2208 {
2209 gen_helper_divu64(o->out2, cpu_env, o->out, o->out2, o->in2);
2210 return_low128(o->out);
2211 return NO_EXIT;
2212 }
2213
2214 static ExitStatus op_deb(DisasContext *s, DisasOps *o)
2215 {
2216 gen_helper_deb(o->out, cpu_env, o->in1, o->in2);
2217 return NO_EXIT;
2218 }
2219
2220 static ExitStatus op_ddb(DisasContext *s, DisasOps *o)
2221 {
2222 gen_helper_ddb(o->out, cpu_env, o->in1, o->in2);
2223 return NO_EXIT;
2224 }
2225
2226 static ExitStatus op_dxb(DisasContext *s, DisasOps *o)
2227 {
2228 gen_helper_dxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2229 return_low128(o->out2);
2230 return NO_EXIT;
2231 }
2232
2233 static ExitStatus op_efpc(DisasContext *s, DisasOps *o)
2234 {
2235 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, fpc));
2236 return NO_EXIT;
2237 }
2238
2239 static ExitStatus op_ex(DisasContext *s, DisasOps *o)
2240 {
2241 /* ??? Perhaps a better way to implement EXECUTE is to set a bit in
2242 tb->flags, (ab)use the tb->cs_base field as the address of
2243 the template in memory, and grab 8 bits of tb->flags/cflags for
2244 the contents of the register. We would then recognize all this
2245 in gen_intermediate_code_internal, generating code for exactly
2246 one instruction. This new TB then gets executed normally.
2247
2248 On the other hand, this seems to be mostly used for modifying
2249 MVC inside of memcpy, which needs a helper call anyway. So
2250 perhaps this doesn't bear thinking about any further. */
2251
2252 TCGv_i64 tmp;
2253
2254 update_psw_addr(s);
2255 gen_op_calc_cc(s);
2256
2257 tmp = tcg_const_i64(s->next_pc);
2258 gen_helper_ex(cc_op, cpu_env, cc_op, o->in1, o->in2, tmp);
2259 tcg_temp_free_i64(tmp);
2260
2261 set_cc_static(s);
2262 return NO_EXIT;
2263 }
2264
2265 static ExitStatus op_flogr(DisasContext *s, DisasOps *o)
2266 {
2267 /* We'll use the original input for cc computation, since we get to
2268 compare that against 0, which ought to be better than comparing
2269 the real output against 64. It also lets cc_dst be a convenient
2270 temporary during our computation. */
2271 gen_op_update1_cc_i64(s, CC_OP_FLOGR, o->in2);
2272
2273 /* R1 = IN ? CLZ(IN) : 64. */
2274 gen_helper_clz(o->out, o->in2);
2275
2276 /* R1+1 = IN & ~(found bit). Note that we may attempt to shift this
2277 value by 64, which is undefined. But since the shift is 64 iff the
2278 input is zero, we still get the correct result after and'ing. */
2279 tcg_gen_movi_i64(o->out2, 0x8000000000000000ull);
2280 tcg_gen_shr_i64(o->out2, o->out2, o->out);
2281 tcg_gen_andc_i64(o->out2, cc_dst, o->out2);
2282 return NO_EXIT;
2283 }
2284
2285 static ExitStatus op_icm(DisasContext *s, DisasOps *o)
2286 {
2287 int m3 = get_field(s->fields, m3);
2288 int pos, len, base = s->insn->data;
2289 TCGv_i64 tmp = tcg_temp_new_i64();
2290 uint64_t ccm;
2291
2292 switch (m3) {
2293 case 0xf:
2294 /* Effectively a 32-bit load. */
2295 tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s));
2296 len = 32;
2297 goto one_insert;
2298
2299 case 0xc:
2300 case 0x6:
2301 case 0x3:
2302 /* Effectively a 16-bit load. */
2303 tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s));
2304 len = 16;
2305 goto one_insert;
2306
2307 case 0x8:
2308 case 0x4:
2309 case 0x2:
2310 case 0x1:
2311 /* Effectively an 8-bit load. */
2312 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2313 len = 8;
2314 goto one_insert;
2315
2316 one_insert:
2317 pos = base + ctz32(m3) * 8;
2318 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len);
2319 ccm = ((1ull << len) - 1) << pos;
2320 break;
2321
2322 default:
2323 /* This is going to be a sequence of loads and inserts. */
2324 pos = base + 32 - 8;
2325 ccm = 0;
2326 while (m3) {
2327 if (m3 & 0x8) {
2328 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2329 tcg_gen_addi_i64(o->in2, o->in2, 1);
2330 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
2331 ccm |= 0xff << pos;
2332 }
2333 m3 = (m3 << 1) & 0xf;
2334 pos -= 8;
2335 }
2336 break;
2337 }
2338
2339 tcg_gen_movi_i64(tmp, ccm);
2340 gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out);
2341 tcg_temp_free_i64(tmp);
2342 return NO_EXIT;
2343 }
2344
2345 static ExitStatus op_insi(DisasContext *s, DisasOps *o)
2346 {
2347 int shift = s->insn->data & 0xff;
2348 int size = s->insn->data >> 8;
2349 tcg_gen_deposit_i64(o->out, o->in1, o->in2, shift, size);
2350 return NO_EXIT;
2351 }
2352
2353 static ExitStatus op_ipm(DisasContext *s, DisasOps *o)
2354 {
2355 TCGv_i64 t1;
2356
2357 gen_op_calc_cc(s);
2358 tcg_gen_andi_i64(o->out, o->out, ~0xff000000ull);
2359
2360 t1 = tcg_temp_new_i64();
2361 tcg_gen_shli_i64(t1, psw_mask, 20);
2362 tcg_gen_shri_i64(t1, t1, 36);
2363 tcg_gen_or_i64(o->out, o->out, t1);
2364
2365 tcg_gen_extu_i32_i64(t1, cc_op);
2366 tcg_gen_shli_i64(t1, t1, 28);
2367 tcg_gen_or_i64(o->out, o->out, t1);
2368 tcg_temp_free_i64(t1);
2369 return NO_EXIT;
2370 }
2371
2372 static ExitStatus op_ldeb(DisasContext *s, DisasOps *o)
2373 {
2374 gen_helper_ldeb(o->out, cpu_env, o->in2);
2375 return NO_EXIT;
2376 }
2377
2378 static ExitStatus op_ledb(DisasContext *s, DisasOps *o)
2379 {
2380 gen_helper_ledb(o->out, cpu_env, o->in2);
2381 return NO_EXIT;
2382 }
2383
2384 static ExitStatus op_ldxb(DisasContext *s, DisasOps *o)
2385 {
2386 gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2);
2387 return NO_EXIT;
2388 }
2389
2390 static ExitStatus op_lexb(DisasContext *s, DisasOps *o)
2391 {
2392 gen_helper_lexb(o->out, cpu_env, o->in1, o->in2);
2393 return NO_EXIT;
2394 }
2395
2396 static ExitStatus op_lxdb(DisasContext *s, DisasOps *o)
2397 {
2398 gen_helper_lxdb(o->out, cpu_env, o->in2);
2399 return_low128(o->out2);
2400 return NO_EXIT;
2401 }
2402
2403 static ExitStatus op_lxeb(DisasContext *s, DisasOps *o)
2404 {
2405 gen_helper_lxeb(o->out, cpu_env, o->in2);
2406 return_low128(o->out2);
2407 return NO_EXIT;
2408 }
2409
2410 static ExitStatus op_llgt(DisasContext *s, DisasOps *o)
2411 {
2412 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffff);
2413 return NO_EXIT;
2414 }
2415
2416 static ExitStatus op_ld8s(DisasContext *s, DisasOps *o)
2417 {
2418 tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
2419 return NO_EXIT;
2420 }
2421
2422 static ExitStatus op_ld8u(DisasContext *s, DisasOps *o)
2423 {
2424 tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
2425 return NO_EXIT;
2426 }
2427
2428 static ExitStatus op_ld16s(DisasContext *s, DisasOps *o)
2429 {
2430 tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
2431 return NO_EXIT;
2432 }
2433
2434 static ExitStatus op_ld16u(DisasContext *s, DisasOps *o)
2435 {
2436 tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
2437 return NO_EXIT;
2438 }
2439
2440 static ExitStatus op_ld32s(DisasContext *s, DisasOps *o)
2441 {
2442 tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s));
2443 return NO_EXIT;
2444 }
2445
2446 static ExitStatus op_ld32u(DisasContext *s, DisasOps *o)
2447 {
2448 tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
2449 return NO_EXIT;
2450 }
2451
2452 static ExitStatus op_ld64(DisasContext *s, DisasOps *o)
2453 {
2454 tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
2455 return NO_EXIT;
2456 }
2457
2458 #ifndef CONFIG_USER_ONLY
2459 static ExitStatus op_lctl(DisasContext *s, DisasOps *o)
2460 {
2461 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2462 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2463 check_privileged(s);
2464 potential_page_fault(s);
2465 gen_helper_lctl(cpu_env, r1, o->in2, r3);
2466 tcg_temp_free_i32(r1);
2467 tcg_temp_free_i32(r3);
2468 return NO_EXIT;
2469 }
2470
2471 static ExitStatus op_lctlg(DisasContext *s, DisasOps *o)
2472 {
2473 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2474 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2475 check_privileged(s);
2476 potential_page_fault(s);
2477 gen_helper_lctlg(cpu_env, r1, o->in2, r3);
2478 tcg_temp_free_i32(r1);
2479 tcg_temp_free_i32(r3);
2480 return NO_EXIT;
2481 }
2482 static ExitStatus op_lra(DisasContext *s, DisasOps *o)
2483 {
2484 check_privileged(s);
2485 potential_page_fault(s);
2486 gen_helper_lra(o->out, cpu_env, o->in2);
2487 set_cc_static(s);
2488 return NO_EXIT;
2489 }
2490
2491 static ExitStatus op_lpsw(DisasContext *s, DisasOps *o)
2492 {
2493 TCGv_i64 t1, t2;
2494
2495 check_privileged(s);
2496
2497 t1 = tcg_temp_new_i64();
2498 t2 = tcg_temp_new_i64();
2499 tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
2500 tcg_gen_addi_i64(o->in2, o->in2, 4);
2501 tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s));
2502 /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
2503 tcg_gen_shli_i64(t1, t1, 32);
2504 gen_helper_load_psw(cpu_env, t1, t2);
2505 tcg_temp_free_i64(t1);
2506 tcg_temp_free_i64(t2);
2507 return EXIT_NORETURN;
2508 }
2509 #endif
2510
2511 static ExitStatus op_lam(DisasContext *s, DisasOps *o)
2512 {
2513 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2514 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2515 potential_page_fault(s);
2516 gen_helper_lam(cpu_env, r1, o->in2, r3);
2517 tcg_temp_free_i32(r1);
2518 tcg_temp_free_i32(r3);
2519 return NO_EXIT;
2520 }
2521
2522 static ExitStatus op_lm32(DisasContext *s, DisasOps *o)
2523 {
2524 int r1 = get_field(s->fields, r1);
2525 int r3 = get_field(s->fields, r3);
2526 TCGv_i64 t = tcg_temp_new_i64();
2527 TCGv_i64 t4 = tcg_const_i64(4);
2528
2529 while (1) {
2530 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2531 store_reg32_i64(r1, t);
2532 if (r1 == r3) {
2533 break;
2534 }
2535 tcg_gen_add_i64(o->in2, o->in2, t4);
2536 r1 = (r1 + 1) & 15;
2537 }
2538
2539 tcg_temp_free_i64(t);
2540 tcg_temp_free_i64(t4);
2541 return NO_EXIT;
2542 }
2543
2544 static ExitStatus op_lmh(DisasContext *s, DisasOps *o)
2545 {
2546 int r1 = get_field(s->fields, r1);
2547 int r3 = get_field(s->fields, r3);
2548 TCGv_i64 t = tcg_temp_new_i64();
2549 TCGv_i64 t4 = tcg_const_i64(4);
2550
2551 while (1) {
2552 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2553 store_reg32h_i64(r1, t);
2554 if (r1 == r3) {
2555 break;
2556 }
2557 tcg_gen_add_i64(o->in2, o->in2, t4);
2558 r1 = (r1 + 1) & 15;
2559 }
2560
2561 tcg_temp_free_i64(t);
2562 tcg_temp_free_i64(t4);
2563 return NO_EXIT;
2564 }
2565
2566 static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
2567 {
2568 int r1 = get_field(s->fields, r1);
2569 int r3 = get_field(s->fields, r3);
2570 TCGv_i64 t8 = tcg_const_i64(8);
2571
2572 while (1) {
2573 tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
2574 if (r1 == r3) {
2575 break;
2576 }
2577 tcg_gen_add_i64(o->in2, o->in2, t8);
2578 r1 = (r1 + 1) & 15;
2579 }
2580
2581 tcg_temp_free_i64(t8);
2582 return NO_EXIT;
2583 }
2584
2585 static ExitStatus op_mov2(DisasContext *s, DisasOps *o)
2586 {
2587 o->out = o->in2;
2588 o->g_out = o->g_in2;
2589 TCGV_UNUSED_I64(o->in2);
2590 o->g_in2 = false;
2591 return NO_EXIT;
2592 }
2593
2594 static ExitStatus op_movx(DisasContext *s, DisasOps *o)
2595 {
2596 o->out = o->in1;
2597 o->out2 = o->in2;
2598 o->g_out = o->g_in1;
2599 o->g_out2 = o->g_in2;
2600 TCGV_UNUSED_I64(o->in1);
2601 TCGV_UNUSED_I64(o->in2);
2602 o->g_in1 = o->g_in2 = false;
2603 return NO_EXIT;
2604 }
2605
2606 static ExitStatus op_mvc(DisasContext *s, DisasOps *o)
2607 {
2608 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2609 potential_page_fault(s);
2610 gen_helper_mvc(cpu_env, l, o->addr1, o->in2);
2611 tcg_temp_free_i32(l);
2612 return NO_EXIT;
2613 }
2614
2615 static ExitStatus op_mvcl(DisasContext *s, DisasOps *o)
2616 {
2617 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2618 TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
2619 potential_page_fault(s);
2620 gen_helper_mvcl(cc_op, cpu_env, r1, r2);
2621 tcg_temp_free_i32(r1);
2622 tcg_temp_free_i32(r2);
2623 set_cc_static(s);
2624 return NO_EXIT;
2625 }
2626
2627 static ExitStatus op_mvcle(DisasContext *s, DisasOps *o)
2628 {
2629 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2630 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2631 potential_page_fault(s);
2632 gen_helper_mvcle(cc_op, cpu_env, r1, o->in2, r3);
2633 tcg_temp_free_i32(r1);
2634 tcg_temp_free_i32(r3);
2635 set_cc_static(s);
2636 return NO_EXIT;
2637 }
2638
2639 #ifndef CONFIG_USER_ONLY
2640 static ExitStatus op_mvcp(DisasContext *s, DisasOps *o)
2641 {
2642 int r1 = get_field(s->fields, l1);
2643 check_privileged(s);
2644 potential_page_fault(s);
2645 gen_helper_mvcp(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2646 set_cc_static(s);
2647 return NO_EXIT;
2648 }
2649
2650 static ExitStatus op_mvcs(DisasContext *s, DisasOps *o)
2651 {
2652 int r1 = get_field(s->fields, l1);
2653 check_privileged(s);
2654 potential_page_fault(s);
2655 gen_helper_mvcs(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2656 set_cc_static(s);
2657 return NO_EXIT;
2658 }
2659 #endif
2660
2661 static ExitStatus op_mul(DisasContext *s, DisasOps *o)
2662 {
2663 tcg_gen_mul_i64(o->out, o->in1, o->in2);
2664 return NO_EXIT;
2665 }
2666
2667 static ExitStatus op_mul128(DisasContext *s, DisasOps *o)
2668 {
2669 gen_helper_mul128(o->out, cpu_env, o->in1, o->in2);
2670 return_low128(o->out2);
2671 return NO_EXIT;
2672 }
2673
2674 static ExitStatus op_meeb(DisasContext *s, DisasOps *o)
2675 {
2676 gen_helper_meeb(o->out, cpu_env, o->in1, o->in2);
2677 return NO_EXIT;
2678 }
2679
2680 static ExitStatus op_mdeb(DisasContext *s, DisasOps *o)
2681 {
2682 gen_helper_mdeb(o->out, cpu_env, o->in1, o->in2);
2683 return NO_EXIT;
2684 }
2685
2686 static ExitStatus op_mdb(DisasContext *s, DisasOps *o)
2687 {
2688 gen_helper_mdb(o->out, cpu_env, o->in1, o->in2);
2689 return NO_EXIT;
2690 }
2691
2692 static ExitStatus op_mxb(DisasContext *s, DisasOps *o)
2693 {
2694 gen_helper_mxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2695 return_low128(o->out2);
2696 return NO_EXIT;
2697 }
2698
2699 static ExitStatus op_mxdb(DisasContext *s, DisasOps *o)
2700 {
2701 gen_helper_mxdb(o->out, cpu_env, o->out, o->out2, o->in2);
2702 return_low128(o->out2);
2703 return NO_EXIT;
2704 }
2705
2706 static ExitStatus op_maeb(DisasContext *s, DisasOps *o)
2707 {
2708 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2709 gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3);
2710 tcg_temp_free_i64(r3);
2711 return NO_EXIT;
2712 }
2713
2714 static ExitStatus op_madb(DisasContext *s, DisasOps *o)
2715 {
2716 int r3 = get_field(s->fields, r3);
2717 gen_helper_madb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2718 return NO_EXIT;
2719 }
2720
2721 static ExitStatus op_mseb(DisasContext *s, DisasOps *o)
2722 {
2723 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2724 gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3);
2725 tcg_temp_free_i64(r3);
2726 return NO_EXIT;
2727 }
2728
2729 static ExitStatus op_msdb(DisasContext *s, DisasOps *o)
2730 {
2731 int r3 = get_field(s->fields, r3);
2732 gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2733 return NO_EXIT;
2734 }
2735
2736 static ExitStatus op_nabs(DisasContext *s, DisasOps *o)
2737 {
2738 gen_helper_nabs_i64(o->out, o->in2);
2739 return NO_EXIT;
2740 }
2741
2742 static ExitStatus op_nabsf32(DisasContext *s, DisasOps *o)
2743 {
2744 tcg_gen_ori_i64(o->out, o->in2, 0x80000000ull);
2745 return NO_EXIT;
2746 }
2747
2748 static ExitStatus op_nabsf64(DisasContext *s, DisasOps *o)
2749 {
2750 tcg_gen_ori_i64(o->out, o->in2, 0x8000000000000000ull);
2751 return NO_EXIT;
2752 }
2753
2754 static ExitStatus op_nabsf128(DisasContext *s, DisasOps *o)
2755 {
2756 tcg_gen_ori_i64(o->out, o->in1, 0x8000000000000000ull);
2757 tcg_gen_mov_i64(o->out2, o->in2);
2758 return NO_EXIT;
2759 }
2760
2761 static ExitStatus op_nc(DisasContext *s, DisasOps *o)
2762 {
2763 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2764 potential_page_fault(s);
2765 gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2);
2766 tcg_temp_free_i32(l);
2767 set_cc_static(s);
2768 return NO_EXIT;
2769 }
2770
2771 static ExitStatus op_neg(DisasContext *s, DisasOps *o)
2772 {
2773 tcg_gen_neg_i64(o->out, o->in2);
2774 return NO_EXIT;
2775 }
2776
2777 static ExitStatus op_negf32(DisasContext *s, DisasOps *o)
2778 {
2779 tcg_gen_xori_i64(o->out, o->in2, 0x80000000ull);
2780 return NO_EXIT;
2781 }
2782
2783 static ExitStatus op_negf64(DisasContext *s, DisasOps *o)
2784 {
2785 tcg_gen_xori_i64(o->out, o->in2, 0x8000000000000000ull);
2786 return NO_EXIT;
2787 }
2788
2789 static ExitStatus op_negf128(DisasContext *s, DisasOps *o)
2790 {
2791 tcg_gen_xori_i64(o->out, o->in1, 0x8000000000000000ull);
2792 tcg_gen_mov_i64(o->out2, o->in2);
2793 return NO_EXIT;
2794 }
2795
2796 static ExitStatus op_oc(DisasContext *s, DisasOps *o)
2797 {
2798 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2799 potential_page_fault(s);
2800 gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2);
2801 tcg_temp_free_i32(l);
2802 set_cc_static(s);
2803 return NO_EXIT;
2804 }
2805
2806 static ExitStatus op_or(DisasContext *s, DisasOps *o)
2807 {
2808 tcg_gen_or_i64(o->out, o->in1, o->in2);
2809 return NO_EXIT;
2810 }
2811
2812 static ExitStatus op_ori(DisasContext *s, DisasOps *o)
2813 {
2814 int shift = s->insn->data & 0xff;
2815 int size = s->insn->data >> 8;
2816 uint64_t mask = ((1ull << size) - 1) << shift;
2817
2818 assert(!o->g_in2);
2819 tcg_gen_shli_i64(o->in2, o->in2, shift);
2820 tcg_gen_or_i64(o->out, o->in1, o->in2);
2821
2822 /* Produce the CC from only the bits manipulated. */
2823 tcg_gen_andi_i64(cc_dst, o->out, mask);
2824 set_cc_nz_u64(s, cc_dst);
2825 return NO_EXIT;
2826 }
2827
2828 static ExitStatus op_rev16(DisasContext *s, DisasOps *o)
2829 {
2830 tcg_gen_bswap16_i64(o->out, o->in2);
2831 return NO_EXIT;
2832 }
2833
2834 static ExitStatus op_rev32(DisasContext *s, DisasOps *o)
2835 {
2836 tcg_gen_bswap32_i64(o->out, o->in2);
2837 return NO_EXIT;
2838 }
2839
2840 static ExitStatus op_rev64(DisasContext *s, DisasOps *o)
2841 {
2842 tcg_gen_bswap64_i64(o->out, o->in2);
2843 return NO_EXIT;
2844 }
2845
2846 static ExitStatus op_rll32(DisasContext *s, DisasOps *o)
2847 {
2848 TCGv_i32 t1 = tcg_temp_new_i32();
2849 TCGv_i32 t2 = tcg_temp_new_i32();
2850 TCGv_i32 to = tcg_temp_new_i32();
2851 tcg_gen_trunc_i64_i32(t1, o->in1);
2852 tcg_gen_trunc_i64_i32(t2, o->in2);
2853 tcg_gen_rotl_i32(to, t1, t2);
2854 tcg_gen_extu_i32_i64(o->out, to);
2855 tcg_temp_free_i32(t1);
2856 tcg_temp_free_i32(t2);
2857 tcg_temp_free_i32(to);
2858 return NO_EXIT;
2859 }
2860
2861 static ExitStatus op_rll64(DisasContext *s, DisasOps *o)
2862 {
2863 tcg_gen_rotl_i64(o->out, o->in1, o->in2);
2864 return NO_EXIT;
2865 }
2866
2867 static ExitStatus op_seb(DisasContext *s, DisasOps *o)
2868 {
2869 gen_helper_seb(o->out, cpu_env, o->in1, o->in2);
2870 return NO_EXIT;
2871 }
2872
2873 static ExitStatus op_sdb(DisasContext *s, DisasOps *o)
2874 {
2875 gen_helper_sdb(o->out, cpu_env, o->in1, o->in2);
2876 return NO_EXIT;
2877 }
2878
2879 static ExitStatus op_sxb(DisasContext *s, DisasOps *o)
2880 {
2881 gen_helper_sxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2882 return_low128(o->out2);
2883 return NO_EXIT;
2884 }
2885
2886 static ExitStatus op_sqeb(DisasContext *s, DisasOps *o)
2887 {
2888 gen_helper_sqeb(o->out, cpu_env, o->in2);
2889 return NO_EXIT;
2890 }
2891
2892 static ExitStatus op_sqdb(DisasContext *s, DisasOps *o)
2893 {
2894 gen_helper_sqdb(o->out, cpu_env, o->in2);
2895 return NO_EXIT;
2896 }
2897
2898 static ExitStatus op_sqxb(DisasContext *s, DisasOps *o)
2899 {
2900 gen_helper_sqxb(o->out, cpu_env, o->in1, o->in2);
2901 return_low128(o->out2);
2902 return NO_EXIT;
2903 }
2904
2905 #ifndef CONFIG_USER_ONLY
2906 static ExitStatus op_sigp(DisasContext *s, DisasOps *o)
2907 {
2908 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2909 check_privileged(s);
2910 potential_page_fault(s);
2911 gen_helper_sigp(cc_op, cpu_env, o->in2, r1, o->in1);
2912 tcg_temp_free_i32(r1);
2913 return NO_EXIT;
2914 }
2915 #endif
2916
2917 static ExitStatus op_sla(DisasContext *s, DisasOps *o)
2918 {
2919 uint64_t sign = 1ull << s->insn->data;
2920 enum cc_op cco = s->insn->data == 31 ? CC_OP_SLA_32 : CC_OP_SLA_64;
2921 gen_op_update2_cc_i64(s, cco, o->in1, o->in2);
2922 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2923 /* The arithmetic left shift is curious in that it does not affect
2924 the sign bit. Copy that over from the source unchanged. */
2925 tcg_gen_andi_i64(o->out, o->out, ~sign);
2926 tcg_gen_andi_i64(o->in1, o->in1, sign);
2927 tcg_gen_or_i64(o->out, o->out, o->in1);
2928 return NO_EXIT;
2929 }
2930
2931 static ExitStatus op_sll(DisasContext *s, DisasOps *o)
2932 {
2933 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2934 return NO_EXIT;
2935 }
2936
2937 static ExitStatus op_sra(DisasContext *s, DisasOps *o)
2938 {
2939 tcg_gen_sar_i64(o->out, o->in1, o->in2);
2940 return NO_EXIT;
2941 }
2942
2943 static ExitStatus op_srl(DisasContext *s, DisasOps *o)
2944 {
2945 tcg_gen_shr_i64(o->out, o->in1, o->in2);
2946 return NO_EXIT;
2947 }
2948
2949 static ExitStatus op_sfpc(DisasContext *s, DisasOps *o)
2950 {
2951 gen_helper_sfpc(cpu_env, o->in2);
2952 return NO_EXIT;
2953 }
2954
2955 #ifndef CONFIG_USER_ONLY
2956 static ExitStatus op_ssm(DisasContext *s, DisasOps *o)
2957 {
2958 check_privileged(s);
2959 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8);
2960 return NO_EXIT;
2961 }
2962
2963 static ExitStatus op_stctg(DisasContext *s, DisasOps *o)
2964 {
2965 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2966 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2967 check_privileged(s);
2968 potential_page_fault(s);
2969 gen_helper_stctg(cpu_env, r1, o->in2, r3);
2970 tcg_temp_free_i32(r1);
2971 tcg_temp_free_i32(r3);
2972 return NO_EXIT;
2973 }
2974
2975 static ExitStatus op_stctl(DisasContext *s, DisasOps *o)
2976 {
2977 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2978 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2979 check_privileged(s);
2980 potential_page_fault(s);
2981 gen_helper_stctl(cpu_env, r1, o->in2, r3);
2982 tcg_temp_free_i32(r1);
2983 tcg_temp_free_i32(r3);
2984 return NO_EXIT;
2985 }
2986
2987 static ExitStatus op_stnosm(DisasContext *s, DisasOps *o)
2988 {
2989 uint64_t i2 = get_field(s->fields, i2);
2990 TCGv_i64 t;
2991
2992 check_privileged(s);
2993
2994 /* It is important to do what the instruction name says: STORE THEN.
2995 If we let the output hook perform the store then if we fault and
2996 restart, we'll have the wrong SYSTEM MASK in place. */
2997 t = tcg_temp_new_i64();
2998 tcg_gen_shri_i64(t, psw_mask, 56);
2999 tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
3000 tcg_temp_free_i64(t);
3001
3002 if (s->fields->op == 0xac) {
3003 tcg_gen_andi_i64(psw_mask, psw_mask,
3004 (i2 << 56) | 0x00ffffffffffffffull);
3005 } else {
3006 tcg_gen_ori_i64(psw_mask, psw_mask, i2 << 56);
3007 }
3008 return NO_EXIT;
3009 }
3010 #endif
3011
3012 static ExitStatus op_st8(DisasContext *s, DisasOps *o)
3013 {
3014 tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));
3015 return NO_EXIT;
3016 }
3017
3018 static ExitStatus op_st16(DisasContext *s, DisasOps *o)
3019 {
3020 tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s));
3021 return NO_EXIT;
3022 }
3023
3024 static ExitStatus op_st32(DisasContext *s, DisasOps *o)
3025 {
3026 tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s));
3027 return NO_EXIT;
3028 }
3029
3030 static ExitStatus op_st64(DisasContext *s, DisasOps *o)
3031 {
3032 tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s));
3033 return NO_EXIT;
3034 }
3035
3036 static ExitStatus op_stam(DisasContext *s, DisasOps *o)
3037 {
3038 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3039 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
3040 potential_page_fault(s);
3041 gen_helper_stam(cpu_env, r1, o->in2, r3);
3042 tcg_temp_free_i32(r1);
3043 tcg_temp_free_i32(r3);
3044 return NO_EXIT;
3045 }
3046
3047 static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
3048 {
3049 int m3 = get_field(s->fields, m3);
3050 int pos, base = s->insn->data;
3051 TCGv_i64 tmp = tcg_temp_new_i64();
3052
3053 pos = base + ctz32(m3) * 8;
3054 switch (m3) {
3055 case 0xf:
3056 /* Effectively a 32-bit store. */
3057 tcg_gen_shri_i64(tmp, o->in1, pos);
3058 tcg_gen_qemu_st32(tmp, o->in2, get_mem_index(s));
3059 break;
3060
3061 case 0xc:
3062 case 0x6:
3063 case 0x3:
3064 /* Effectively a 16-bit store. */
3065 tcg_gen_shri_i64(tmp, o->in1, pos);
3066 tcg_gen_qemu_st16(tmp, o->in2, get_mem_index(s));
3067 break;
3068
3069 case 0x8:
3070 case 0x4:
3071 case 0x2:
3072 case 0x1:
3073 /* Effectively an 8-bit store. */
3074 tcg_gen_shri_i64(tmp, o->in1, pos);
3075 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3076 break;
3077
3078 default:
3079 /* This is going to be a sequence of shifts and stores. */
3080 pos = base + 32 - 8;
3081 while (m3) {
3082 if (m3 & 0x8) {
3083 tcg_gen_shri_i64(tmp, o->in1, pos);
3084 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3085 tcg_gen_addi_i64(o->in2, o->in2, 1);
3086 }
3087 m3 = (m3 << 1) & 0xf;
3088 pos -= 8;
3089 }
3090 break;
3091 }
3092 tcg_temp_free_i64(tmp);
3093 return NO_EXIT;
3094 }
3095
3096 static ExitStatus op_stm(DisasContext *s, DisasOps *o)
3097 {
3098 int r1 = get_field(s->fields, r1);
3099 int r3 = get_field(s->fields, r3);
3100 int size = s->insn->data;
3101 TCGv_i64 tsize = tcg_const_i64(size);
3102
3103 while (1) {
3104 if (size == 8) {
3105 tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s));
3106 } else {
3107 tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s));
3108 }
3109 if (r1 == r3) {
3110 break;
3111 }
3112 tcg_gen_add_i64(o->in2, o->in2, tsize);
3113 r1 = (r1 + 1) & 15;
3114 }
3115
3116 tcg_temp_free_i64(tsize);
3117 return NO_EXIT;
3118 }
3119
3120 static ExitStatus op_stmh(DisasContext *s, DisasOps *o)
3121 {
3122 int r1 = get_field(s->fields, r1);
3123 int r3 = get_field(s->fields, r3);
3124 TCGv_i64 t = tcg_temp_new_i64();
3125 TCGv_i64 t4 = tcg_const_i64(4);
3126 TCGv_i64 t32 = tcg_const_i64(32);
3127
3128 while (1) {
3129 tcg_gen_shl_i64(t, regs[r1], t32);
3130 tcg_gen_qemu_st32(t, o->in2, get_mem_index(s));
3131 if (r1 == r3) {
3132 break;
3133 }
3134 tcg_gen_add_i64(o->in2, o->in2, t4);
3135 r1 = (r1 + 1) & 15;
3136 }
3137
3138 tcg_temp_free_i64(t);
3139 tcg_temp_free_i64(t4);
3140 tcg_temp_free_i64(t32);
3141 return NO_EXIT;
3142 }
3143
3144 static ExitStatus op_sub(DisasContext *s, DisasOps *o)
3145 {
3146 tcg_gen_sub_i64(o->out, o->in1, o->in2);
3147 return NO_EXIT;
3148 }
3149
3150 static ExitStatus op_subb(DisasContext *s, DisasOps *o)
3151 {
3152 TCGv_i64 cc;
3153
3154 assert(!o->g_in2);
3155 tcg_gen_not_i64(o->in2, o->in2);
3156 tcg_gen_add_i64(o->out, o->in1, o->in2);
3157
3158 /* XXX possible optimization point */
3159 gen_op_calc_cc(s);
3160 cc = tcg_temp_new_i64();
3161 tcg_gen_extu_i32_i64(cc, cc_op);
3162 tcg_gen_shri_i64(cc, cc, 1);
3163 tcg_gen_add_i64(o->out, o->out, cc);
3164 tcg_temp_free_i64(cc);
3165 return NO_EXIT;
3166 }
3167
3168 static ExitStatus op_svc(DisasContext *s, DisasOps *o)
3169 {
3170 TCGv_i32 t;
3171
3172 update_psw_addr(s);
3173 gen_op_calc_cc(s);
3174
3175 t = tcg_const_i32(get_field(s->fields, i1) & 0xff);
3176 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code));
3177 tcg_temp_free_i32(t);
3178
3179 t = tcg_const_i32(s->next_pc - s->pc);
3180 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen));
3181 tcg_temp_free_i32(t);
3182
3183 gen_exception(EXCP_SVC);
3184 return EXIT_NORETURN;
3185 }
3186
3187 static ExitStatus op_tceb(DisasContext *s, DisasOps *o)
3188 {
3189 gen_helper_tceb(cc_op, o->in1, o->in2);
3190 set_cc_static(s);
3191 return NO_EXIT;
3192 }
3193
3194 static ExitStatus op_tcdb(DisasContext *s, DisasOps *o)
3195 {
3196 gen_helper_tcdb(cc_op, o->in1, o->in2);
3197 set_cc_static(s);
3198 return NO_EXIT;
3199 }
3200
3201 static ExitStatus op_tcxb(DisasContext *s, DisasOps *o)
3202 {
3203 gen_helper_tcxb(cc_op, o->out, o->out2, o->in2);
3204 set_cc_static(s);
3205 return NO_EXIT;
3206 }
3207
3208 #ifndef CONFIG_USER_ONLY
3209 static ExitStatus op_tprot(DisasContext *s, DisasOps *o)
3210 {
3211 potential_page_fault(s);
3212 gen_helper_tprot(cc_op, o->addr1, o->in2);
3213 set_cc_static(s);
3214 return NO_EXIT;
3215 }
3216 #endif
3217
3218 static ExitStatus op_tr(DisasContext *s, DisasOps *o)
3219 {
3220 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3221 potential_page_fault(s);
3222 gen_helper_tr(cpu_env, l, o->addr1, o->in2);
3223 tcg_temp_free_i32(l);
3224 set_cc_static(s);
3225 return NO_EXIT;
3226 }
3227
3228 static ExitStatus op_unpk(DisasContext *s, DisasOps *o)
3229 {
3230 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3231 potential_page_fault(s);
3232 gen_helper_unpk(cpu_env, l, o->addr1, o->in2);
3233 tcg_temp_free_i32(l);
3234 return NO_EXIT;
3235 }
3236
3237 static ExitStatus op_xc(DisasContext *s, DisasOps *o)
3238 {
3239 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3240 potential_page_fault(s);
3241 gen_helper_xc(cc_op, cpu_env, l, o->addr1, o->in2);
3242 tcg_temp_free_i32(l);
3243 set_cc_static(s);
3244 return NO_EXIT;
3245 }
3246
3247 static ExitStatus op_xor(DisasContext *s, DisasOps *o)
3248 {
3249 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3250 return NO_EXIT;
3251 }
3252
3253 static ExitStatus op_xori(DisasContext *s, DisasOps *o)
3254 {
3255 int shift = s->insn->data & 0xff;
3256 int size = s->insn->data >> 8;
3257 uint64_t mask = ((1ull << size) - 1) << shift;
3258
3259 assert(!o->g_in2);
3260 tcg_gen_shli_i64(o->in2, o->in2, shift);
3261 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3262
3263 /* Produce the CC from only the bits manipulated. */
3264 tcg_gen_andi_i64(cc_dst, o->out, mask);
3265 set_cc_nz_u64(s, cc_dst);
3266 return NO_EXIT;
3267 }
3268
3269 static ExitStatus op_zero(DisasContext *s, DisasOps *o)
3270 {
3271 o->out = tcg_const_i64(0);
3272 return NO_EXIT;
3273 }
3274
3275 static ExitStatus op_zero2(DisasContext *s, DisasOps *o)
3276 {
3277 o->out = tcg_const_i64(0);
3278 o->out2 = o->out;
3279 o->g_out2 = true;
3280 return NO_EXIT;
3281 }
3282
3283 /* ====================================================================== */
3284 /* The "Cc OUTput" generators. Given the generated output (and in some cases
3285 the original inputs), update the various cc data structures in order to
3286 be able to compute the new condition code. */
3287
3288 static void cout_abs32(DisasContext *s, DisasOps *o)
3289 {
3290 gen_op_update1_cc_i64(s, CC_OP_ABS_32, o->out);
3291 }
3292
3293 static void cout_abs64(DisasContext *s, DisasOps *o)
3294 {
3295 gen_op_update1_cc_i64(s, CC_OP_ABS_64, o->out);
3296 }
3297
3298 static void cout_adds32(DisasContext *s, DisasOps *o)
3299 {
3300 gen_op_update3_cc_i64(s, CC_OP_ADD_32, o->in1, o->in2, o->out);
3301 }
3302
3303 static void cout_adds64(DisasContext *s, DisasOps *o)
3304 {
3305 gen_op_update3_cc_i64(s, CC_OP_ADD_64, o->in1, o->in2, o->out);
3306 }
3307
3308 static void cout_addu32(DisasContext *s, DisasOps *o)
3309 {
3310 gen_op_update3_cc_i64(s, CC_OP_ADDU_32, o->in1, o->in2, o->out);
3311 }
3312
3313 static void cout_addu64(DisasContext *s, DisasOps *o)
3314 {
3315 gen_op_update3_cc_i64(s, CC_OP_ADDU_64, o->in1, o->in2, o->out);
3316 }
3317
3318 static void cout_addc32(DisasContext *s, DisasOps *o)
3319 {
3320 gen_op_update3_cc_i64(s, CC_OP_ADDC_32, o->in1, o->in2, o->out);
3321 }
3322
3323 static void cout_addc64(DisasContext *s, DisasOps *o)
3324 {
3325 gen_op_update3_cc_i64(s, CC_OP_ADDC_64, o->in1, o->in2, o->out);
3326 }
3327
3328 static void cout_cmps32(DisasContext *s, DisasOps *o)
3329 {
3330 gen_op_update2_cc_i64(s, CC_OP_LTGT_32, o->in1, o->in2);
3331 }
3332
3333 static void cout_cmps64(DisasContext *s, DisasOps *o)
3334 {
3335 gen_op_update2_cc_i64(s, CC_OP_LTGT_64, o->in1, o->in2);
3336 }
3337
3338 static void cout_cmpu32(DisasContext *s, DisasOps *o)
3339 {
3340 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_32, o->in1, o->in2);
3341 }
3342
3343 static void cout_cmpu64(DisasContext *s, DisasOps *o)
3344 {
3345 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, o->in1, o->in2);
3346 }
3347
3348 static void cout_f32(DisasContext *s, DisasOps *o)
3349 {
3350 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, o->out);
3351 }
3352
3353 static void cout_f64(DisasContext *s, DisasOps *o)
3354 {
3355 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, o->out);
3356 }
3357
3358 static void cout_f128(DisasContext *s, DisasOps *o)
3359 {
3360 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, o->out, o->out2);
3361 }
3362
3363 static void cout_nabs32(DisasContext *s, DisasOps *o)
3364 {
3365 gen_op_update1_cc_i64(s, CC_OP_NABS_32, o->out);
3366 }
3367
3368 static void cout_nabs64(DisasContext *s, DisasOps *o)
3369 {
3370 gen_op_update1_cc_i64(s, CC_OP_NABS_64, o->out);
3371 }
3372
3373 static void cout_neg32(DisasContext *s, DisasOps *o)
3374 {
3375 gen_op_update1_cc_i64(s, CC_OP_COMP_32, o->out);
3376 }
3377
3378 static void cout_neg64(DisasContext *s, DisasOps *o)
3379 {
3380 gen_op_update1_cc_i64(s, CC_OP_COMP_64, o->out);
3381 }
3382
3383 static void cout_nz32(DisasContext *s, DisasOps *o)
3384 {
3385 tcg_gen_ext32u_i64(cc_dst, o->out);
3386 gen_op_update1_cc_i64(s, CC_OP_NZ, cc_dst);
3387 }
3388
3389 static void cout_nz64(DisasContext *s, DisasOps *o)
3390 {
3391 gen_op_update1_cc_i64(s, CC_OP_NZ, o->out);
3392 }
3393
3394 static void cout_s32(DisasContext *s, DisasOps *o)
3395 {
3396 gen_op_update1_cc_i64(s, CC_OP_LTGT0_32, o->out);
3397 }
3398
3399 static void cout_s64(DisasContext *s, DisasOps *o)
3400 {
3401 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, o->out);
3402 }
3403
3404 static void cout_subs32(DisasContext *s, DisasOps *o)
3405 {
3406 gen_op_update3_cc_i64(s, CC_OP_SUB_32, o->in1, o->in2, o->out);
3407 }
3408
3409 static void cout_subs64(DisasContext *s, DisasOps *o)
3410 {
3411 gen_op_update3_cc_i64(s, CC_OP_SUB_64, o->in1, o->in2, o->out);
3412 }
3413
3414 static void cout_subu32(DisasContext *s, DisasOps *o)
3415 {
3416 gen_op_update3_cc_i64(s, CC_OP_SUBU_32, o->in1, o->in2, o->out);
3417 }
3418
3419 static void cout_subu64(DisasContext *s, DisasOps *o)
3420 {
3421 gen_op_update3_cc_i64(s, CC_OP_SUBU_64, o->in1, o->in2, o->out);
3422 }
3423
3424 static void cout_subb32(DisasContext *s, DisasOps *o)
3425 {
3426 gen_op_update3_cc_i64(s, CC_OP_SUBB_32, o->in1, o->in2, o->out);
3427 }
3428
3429 static void cout_subb64(DisasContext *s, DisasOps *o)
3430 {
3431 gen_op_update3_cc_i64(s, CC_OP_SUBB_64, o->in1, o->in2, o->out);
3432 }
3433
3434 static void cout_tm32(DisasContext *s, DisasOps *o)
3435 {
3436 gen_op_update2_cc_i64(s, CC_OP_TM_32, o->in1, o->in2);
3437 }
3438
3439 static void cout_tm64(DisasContext *s, DisasOps *o)
3440 {
3441 gen_op_update2_cc_i64(s, CC_OP_TM_64, o->in1, o->in2);
3442 }
3443
3444 /* ====================================================================== */
3445 /* The "PREPeration" generators. These initialize the DisasOps.OUT fields
3446 with the TCG register to which we will write. Used in combination with
3447 the "wout" generators, in some cases we need a new temporary, and in
3448 some cases we can write to a TCG global. */
3449
3450 static void prep_new(DisasContext *s, DisasFields *f, DisasOps *o)
3451 {
3452 o->out = tcg_temp_new_i64();
3453 }
3454
3455 static void prep_new_P(DisasContext *s, DisasFields *f, DisasOps *o)
3456 {
3457 o->out = tcg_temp_new_i64();
3458 o->out2 = tcg_temp_new_i64();
3459 }
3460
3461 static void prep_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3462 {
3463 o->out = regs[get_field(f, r1)];
3464 o->g_out = true;
3465 }
3466
3467 static void prep_r1_P(DisasContext *s, DisasFields *f, DisasOps *o)
3468 {
3469 /* ??? Specification exception: r1 must be even. */
3470 int r1 = get_field(f, r1);
3471 o->out = regs[r1];
3472 o->out2 = regs[(r1 + 1) & 15];
3473 o->g_out = o->g_out2 = true;
3474 }
3475
3476 static void prep_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3477 {
3478 o->out = fregs[get_field(f, r1)];
3479 o->g_out = true;
3480 }
3481
3482 static void prep_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3483 {
3484 /* ??? Specification exception: r1 must be < 14. */
3485 int r1 = get_field(f, r1);
3486 o->out = fregs[r1];
3487 o->out2 = fregs[(r1 + 2) & 15];
3488 o->g_out = o->g_out2 = true;
3489 }
3490
3491 /* ====================================================================== */
3492 /* The "Write OUTput" generators. These generally perform some non-trivial
3493 copy of data to TCG globals, or to main memory. The trivial cases are
3494 generally handled by having a "prep" generator install the TCG global
3495 as the destination of the operation. */
3496
3497 static void wout_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3498 {
3499 store_reg(get_field(f, r1), o->out);
3500 }
3501
3502 static void wout_r1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3503 {
3504 int r1 = get_field(f, r1);
3505 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8);
3506 }
3507
3508 static void wout_r1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3509 {
3510 int r1 = get_field(f, r1);
3511 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 16);
3512 }
3513
3514 static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3515 {
3516 store_reg32_i64(get_field(f, r1), o->out);
3517 }
3518
3519 static void wout_r1_P32(DisasContext *s, DisasFields *f, DisasOps *o)
3520 {
3521 /* ??? Specification exception: r1 must be even. */
3522 int r1 = get_field(f, r1);
3523 store_reg32_i64(r1, o->out);
3524 store_reg32_i64((r1 + 1) & 15, o->out2);
3525 }
3526
3527 static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3528 {
3529 /* ??? Specification exception: r1 must be even. */
3530 int r1 = get_field(f, r1);
3531 store_reg32_i64((r1 + 1) & 15, o->out);
3532 tcg_gen_shri_i64(o->out, o->out, 32);
3533 store_reg32_i64(r1, o->out);
3534 }
3535
3536 static void wout_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3537 {
3538 store_freg32_i64(get_field(f, r1), o->out);
3539 }
3540
3541 static void wout_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3542 {
3543 store_freg(get_field(f, r1), o->out);
3544 }
3545
3546 static void wout_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3547 {
3548 /* ??? Specification exception: r1 must be < 14. */
3549 int f1 = get_field(s->fields, r1);
3550 store_freg(f1, o->out);
3551 store_freg((f1 + 2) & 15, o->out2);
3552 }
3553
3554 static void wout_cond_r1r2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3555 {
3556 if (get_field(f, r1) != get_field(f, r2)) {
3557 store_reg32_i64(get_field(f, r1), o->out);
3558 }
3559 }
3560
3561 static void wout_cond_e1e2(DisasContext *s, DisasFields *f, DisasOps *o)
3562 {
3563 if (get_field(f, r1) != get_field(f, r2)) {
3564 store_freg32_i64(get_field(f, r1), o->out);
3565 }
3566 }
3567
3568 static void wout_m1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3569 {
3570 tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s));
3571 }
3572
3573 static void wout_m1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3574 {
3575 tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s));
3576 }
3577
3578 static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3579 {
3580 tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
3581 }
3582
3583 static void wout_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3584 {
3585 tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
3586 }
3587
3588 static void wout_m2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3589 {
3590 tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s));
3591 }
3592
3593 /* ====================================================================== */
3594 /* The "INput 1" generators. These load the first operand to an insn. */
3595
3596 static void in1_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3597 {
3598 o->in1 = load_reg(get_field(f, r1));
3599 }
3600
3601 static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3602 {
3603 o->in1 = regs[get_field(f, r1)];
3604 o->g_in1 = true;
3605 }
3606
3607 static void in1_r1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3608 {
3609 o->in1 = tcg_temp_new_i64();
3610 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r1)]);
3611 }
3612
3613 static void in1_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3614 {
3615 o->in1 = tcg_temp_new_i64();
3616 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r1)]);
3617 }
3618
3619 static void in1_r1_sr32(DisasContext *s, DisasFields *f, DisasOps *o)
3620 {
3621 o->in1 = tcg_temp_new_i64();
3622 tcg_gen_shri_i64(o->in1, regs[get_field(f, r1)], 32);
3623 }
3624
3625 static void in1_r1p1(DisasContext *s, DisasFields *f, DisasOps *o)
3626 {
3627 /* ??? Specification exception: r1 must be even. */
3628 int r1 = get_field(f, r1);
3629 o->in1 = load_reg((r1 + 1) & 15);
3630 }
3631
3632 static void in1_r1p1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3633 {
3634 /* ??? Specification exception: r1 must be even. */
3635 int r1 = get_field(f, r1);
3636 o->in1 = tcg_temp_new_i64();
3637 tcg_gen_ext32s_i64(o->in1, regs[(r1 + 1) & 15]);
3638 }
3639
3640 static void in1_r1p1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3641 {
3642 /* ??? Specification exception: r1 must be even. */
3643 int r1 = get_field(f, r1);
3644 o->in1 = tcg_temp_new_i64();
3645 tcg_gen_ext32u_i64(o->in1, regs[(r1 + 1) & 15]);
3646 }
3647
3648 static void in1_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3649 {
3650 /* ??? Specification exception: r1 must be even. */
3651 int r1 = get_field(f, r1);
3652 o->in1 = tcg_temp_new_i64();
3653 tcg_gen_concat32_i64(o->in1, regs[r1 + 1], regs[r1]);
3654 }
3655
3656 static void in1_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3657 {
3658 o->in1 = load_reg(get_field(f, r2));
3659 }
3660
3661 static void in1_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3662 {
3663 o->in1 = load_reg(get_field(f, r3));
3664 }
3665
3666 static void in1_r3_o(DisasContext *s, DisasFields *f, DisasOps *o)
3667 {
3668 o->in1 = regs[get_field(f, r3)];
3669 o->g_in1 = true;
3670 }
3671
3672 static void in1_r3_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3673 {
3674 o->in1 = tcg_temp_new_i64();
3675 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r3)]);
3676 }
3677
3678 static void in1_r3_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3679 {
3680 o->in1 = tcg_temp_new_i64();
3681 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r3)]);
3682 }
3683
3684 static void in1_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3685 {
3686 o->in1 = load_freg32_i64(get_field(f, r1));
3687 }
3688
3689 static void in1_f1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3690 {
3691 o->in1 = fregs[get_field(f, r1)];
3692 o->g_in1 = true;
3693 }
3694
3695 static void in1_x1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3696 {
3697 /* ??? Specification exception: r1 must be < 14. */
3698 int r1 = get_field(f, r1);
3699 o->out = fregs[r1];
3700 o->out2 = fregs[(r1 + 2) & 15];
3701 o->g_out = o->g_out2 = true;
3702 }
3703
3704 static void in1_la1(DisasContext *s, DisasFields *f, DisasOps *o)
3705 {
3706 o->addr1 = get_address(s, 0, get_field(f, b1), get_field(f, d1));
3707 }
3708
3709 static void in1_la2(DisasContext *s, DisasFields *f, DisasOps *o)
3710 {
3711 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3712 o->addr1 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3713 }
3714
3715 static void in1_m1_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3716 {
3717 in1_la1(s, f, o);
3718 o->in1 = tcg_temp_new_i64();
3719 tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s));
3720 }
3721
3722 static void in1_m1_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3723 {
3724 in1_la1(s, f, o);
3725 o->in1 = tcg_temp_new_i64();
3726 tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s));
3727 }
3728
3729 static void in1_m1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3730 {
3731 in1_la1(s, f, o);
3732 o->in1 = tcg_temp_new_i64();
3733 tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s));
3734 }
3735
3736 static void in1_m1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3737 {
3738 in1_la1(s, f, o);
3739 o->in1 = tcg_temp_new_i64();
3740 tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s));
3741 }
3742
3743 static void in1_m1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3744 {
3745 in1_la1(s, f, o);
3746 o->in1 = tcg_temp_new_i64();
3747 tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s));
3748 }
3749
3750 static void in1_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3751 {
3752 in1_la1(s, f, o);
3753 o->in1 = tcg_temp_new_i64();
3754 tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s));
3755 }
3756
3757 /* ====================================================================== */
3758 /* The "INput 2" generators. These load the second operand to an insn. */
3759
3760 static void in2_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3761 {
3762 o->in2 = regs[get_field(f, r1)];
3763 o->g_in2 = true;
3764 }
3765
3766 static void in2_r1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3767 {
3768 o->in2 = tcg_temp_new_i64();
3769 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r1)]);
3770 }
3771
3772 static void in2_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3773 {
3774 o->in2 = tcg_temp_new_i64();
3775 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r1)]);
3776 }
3777
3778 static void in2_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3779 {
3780 o->in2 = load_reg(get_field(f, r2));
3781 }
3782
3783 static void in2_r2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3784 {
3785 o->in2 = regs[get_field(f, r2)];
3786 o->g_in2 = true;
3787 }
3788
3789 static void in2_r2_nz(DisasContext *s, DisasFields *f, DisasOps *o)
3790 {
3791 int r2 = get_field(f, r2);
3792 if (r2 != 0) {
3793 o->in2 = load_reg(r2);
3794 }
3795 }
3796
3797 static void in2_r2_8s(DisasContext *s, DisasFields *f, DisasOps *o)
3798 {
3799 o->in2 = tcg_temp_new_i64();
3800 tcg_gen_ext8s_i64(o->in2, regs[get_field(f, r2)]);
3801 }
3802
3803 static void in2_r2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3804 {
3805 o->in2 = tcg_temp_new_i64();
3806 tcg_gen_ext8u_i64(o->in2, regs[get_field(f, r2)]);
3807 }
3808
3809 static void in2_r2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3810 {
3811 o->in2 = tcg_temp_new_i64();
3812 tcg_gen_ext16s_i64(o->in2, regs[get_field(f, r2)]);
3813 }
3814
3815 static void in2_r2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3816 {
3817 o->in2 = tcg_temp_new_i64();
3818 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r2)]);
3819 }
3820
3821 static void in2_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3822 {
3823 o->in2 = load_reg(get_field(f, r3));
3824 }
3825
3826 static void in2_r2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3827 {
3828 o->in2 = tcg_temp_new_i64();
3829 tcg_gen_ext32s_i64(o->in2, regs[get_field(f, r2)]);
3830 }
3831
3832 static void in2_r2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3833 {
3834 o->in2 = tcg_temp_new_i64();
3835 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r2)]);
3836 }
3837
3838 static void in2_e2(DisasContext *s, DisasFields *f, DisasOps *o)
3839 {
3840 o->in2 = load_freg32_i64(get_field(f, r2));
3841 }
3842
3843 static void in2_f2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3844 {
3845 o->in2 = fregs[get_field(f, r2)];
3846 o->g_in2 = true;
3847 }
3848
3849 static void in2_x2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3850 {
3851 /* ??? Specification exception: r1 must be < 14. */
3852 int r2 = get_field(f, r2);
3853 o->in1 = fregs[r2];
3854 o->in2 = fregs[(r2 + 2) & 15];
3855 o->g_in1 = o->g_in2 = true;
3856 }
3857
3858 static void in2_ra2(DisasContext *s, DisasFields *f, DisasOps *o)
3859 {
3860 o->in2 = get_address(s, 0, get_field(f, r2), 0);
3861 }
3862
3863 static void in2_a2(DisasContext *s, DisasFields *f, DisasOps *o)
3864 {
3865 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3866 o->in2 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3867 }
3868
3869 static void in2_ri2(DisasContext *s, DisasFields *f, DisasOps *o)
3870 {
3871 o->in2 = tcg_const_i64(s->pc + (int64_t)get_field(f, i2) * 2);
3872 }
3873
3874 static void in2_sh32(DisasContext *s, DisasFields *f, DisasOps *o)
3875 {
3876 help_l2_shift(s, f, o, 31);
3877 }
3878
3879 static void in2_sh64(DisasContext *s, DisasFields *f, DisasOps *o)
3880 {
3881 help_l2_shift(s, f, o, 63);
3882 }
3883
3884 static void in2_m2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3885 {
3886 in2_a2(s, f, o);
3887 tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s));
3888 }
3889
3890 static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3891 {
3892 in2_a2(s, f, o);
3893 tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
3894 }
3895
3896 static void in2_m2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3897 {
3898 in2_a2(s, f, o);
3899 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3900 }
3901
3902 static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3903 {
3904 in2_a2(s, f, o);
3905 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3906 }
3907
3908 static void in2_m2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3909 {
3910 in2_a2(s, f, o);
3911 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3912 }
3913
3914 static void in2_m2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3915 {
3916 in2_a2(s, f, o);
3917 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3918 }
3919
3920 static void in2_mri2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3921 {
3922 in2_ri2(s, f, o);
3923 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3924 }
3925
3926 static void in2_mri2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3927 {
3928 in2_ri2(s, f, o);
3929 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3930 }
3931
3932 static void in2_mri2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3933 {
3934 in2_ri2(s, f, o);
3935 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3936 }
3937
3938 static void in2_mri2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3939 {
3940 in2_ri2(s, f, o);
3941 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3942 }
3943
3944 static void in2_i2(DisasContext *s, DisasFields *f, DisasOps *o)
3945 {
3946 o->in2 = tcg_const_i64(get_field(f, i2));
3947 }
3948
3949 static void in2_i2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3950 {
3951 o->in2 = tcg_const_i64((uint8_t)get_field(f, i2));
3952 }
3953
3954 static void in2_i2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3955 {
3956 o->in2 = tcg_const_i64((uint16_t)get_field(f, i2));
3957 }
3958
3959 static void in2_i2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3960 {
3961 o->in2 = tcg_const_i64((uint32_t)get_field(f, i2));
3962 }
3963
3964 static void in2_i2_16u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
3965 {
3966 uint64_t i2 = (uint16_t)get_field(f, i2);
3967 o->in2 = tcg_const_i64(i2 << s->insn->data);
3968 }
3969
3970 static void in2_i2_32u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
3971 {
3972 uint64_t i2 = (uint32_t)get_field(f, i2);
3973 o->in2 = tcg_const_i64(i2 << s->insn->data);
3974 }
3975
3976 /* ====================================================================== */
3977
3978 /* Find opc within the table of insns. This is formulated as a switch
3979 statement so that (1) we get compile-time notice of cut-paste errors
3980 for duplicated opcodes, and (2) the compiler generates the binary
3981 search tree, rather than us having to post-process the table. */
3982
3983 #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \
3984 D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0)
3985
3986 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) insn_ ## NM,
3987
3988 enum DisasInsnEnum {
3989 #include "insn-data.def"
3990 };
3991
3992 #undef D
3993 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) { \
3994 .opc = OPC, \
3995 .fmt = FMT_##FT, \
3996 .fac = FAC_##FC, \
3997 .name = #NM, \
3998 .help_in1 = in1_##I1, \
3999 .help_in2 = in2_##I2, \
4000 .help_prep = prep_##P, \
4001 .help_wout = wout_##W, \
4002 .help_cout = cout_##CC, \
4003 .help_op = op_##OP, \
4004 .data = D \
4005 },
4006
4007 /* Allow 0 to be used for NULL in the table below. */
4008 #define in1_0 NULL
4009 #define in2_0 NULL
4010 #define prep_0 NULL
4011 #define wout_0 NULL
4012 #define cout_0 NULL
4013 #define op_0 NULL
4014
4015 static const DisasInsn insn_info[] = {
4016 #include "insn-data.def"
4017 };
4018
4019 #undef D
4020 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \
4021 case OPC: return &insn_info[insn_ ## NM];
4022
4023 static const DisasInsn *lookup_opc(uint16_t opc)
4024 {
4025 switch (opc) {
4026 #include "insn-data.def"
4027 default:
4028 return NULL;
4029 }
4030 }
4031
4032 #undef D
4033 #undef C
4034
4035 /* Extract a field from the insn. The INSN should be left-aligned in
4036 the uint64_t so that we can more easily utilize the big-bit-endian
4037 definitions we extract from the Principals of Operation. */
4038
4039 static void extract_field(DisasFields *o, const DisasField *f, uint64_t insn)
4040 {
4041 uint32_t r, m;
4042
4043 if (f->size == 0) {
4044 return;
4045 }
4046
4047 /* Zero extract the field from the insn. */
4048 r = (insn << f->beg) >> (64 - f->size);
4049
4050 /* Sign-extend, or un-swap the field as necessary. */
4051 switch (f->type) {
4052 case 0: /* unsigned */
4053 break;
4054 case 1: /* signed */
4055 assert(f->size <= 32);
4056 m = 1u << (f->size - 1);
4057 r = (r ^ m) - m;
4058 break;
4059 case 2: /* dl+dh split, signed 20 bit. */
4060 r = ((int8_t)r << 12) | (r >> 8);
4061 break;
4062 default:
4063 abort();
4064 }
4065
4066 /* Validate that the "compressed" encoding we selected above is valid.
4067 I.e. we havn't make two different original fields overlap. */
4068 assert(((o->presentC >> f->indexC) & 1) == 0);
4069 o->presentC |= 1 << f->indexC;
4070 o->presentO |= 1 << f->indexO;
4071
4072 o->c[f->indexC] = r;
4073 }
4074
4075 /* Lookup the insn at the current PC, extracting the operands into O and
4076 returning the info struct for the insn. Returns NULL for invalid insn. */
4077
4078 static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
4079 DisasFields *f)
4080 {
4081 uint64_t insn, pc = s->pc;
4082 int op, op2, ilen;
4083 const DisasInsn *info;
4084
4085 insn = ld_code2(env, pc);
4086 op = (insn >> 8) & 0xff;
4087 ilen = get_ilen(op);
4088 s->next_pc = s->pc + ilen;
4089
4090 switch (ilen) {
4091 case 2:
4092 insn = insn << 48;
4093 break;
4094 case 4:
4095 insn = ld_code4(env, pc) << 32;
4096 break;
4097 case 6:
4098 insn = (insn << 48) | (ld_code4(env, pc + 2) << 16);
4099 break;
4100 default:
4101 abort();
4102 }
4103
4104 /* We can't actually determine the insn format until we've looked up
4105 the full insn opcode. Which we can't do without locating the
4106 secondary opcode. Assume by default that OP2 is at bit 40; for
4107 those smaller insns that don't actually have a secondary opcode
4108 this will correctly result in OP2 = 0. */
4109 switch (op) {
4110 case 0x01: /* E */
4111 case 0x80: /* S */
4112 case 0x82: /* S */
4113 case 0x93: /* S */
4114 case 0xb2: /* S, RRF, RRE */
4115 case 0xb3: /* RRE, RRD, RRF */
4116 case 0xb9: /* RRE, RRF */
4117 case 0xe5: /* SSE, SIL */
4118 op2 = (insn << 8) >> 56;
4119 break;
4120 case 0xa5: /* RI */
4121 case 0xa7: /* RI */
4122 case 0xc0: /* RIL */
4123 case 0xc2: /* RIL */
4124 case 0xc4: /* RIL */
4125 case 0xc6: /* RIL */
4126 case 0xc8: /* SSF */
4127 case 0xcc: /* RIL */
4128 op2 = (insn << 12) >> 60;
4129 break;
4130 case 0xd0 ... 0xdf: /* SS */
4131 case 0xe1: /* SS */
4132 case 0xe2: /* SS */
4133 case 0xe8: /* SS */
4134 case 0xe9: /* SS */
4135 case 0xea: /* SS */
4136 case 0xee ... 0xf3: /* SS */
4137 case 0xf8 ... 0xfd: /* SS */
4138 op2 = 0;
4139 break;
4140 default:
4141 op2 = (insn << 40) >> 56;
4142 break;
4143 }
4144
4145 memset(f, 0, sizeof(*f));
4146 f->op = op;
4147 f->op2 = op2;
4148
4149 /* Lookup the instruction. */
4150 info = lookup_opc(op << 8 | op2);
4151
4152 /* If we found it, extract the operands. */
4153 if (info != NULL) {
4154 DisasFormat fmt = info->fmt;
4155 int i;
4156
4157 for (i = 0; i < NUM_C_FIELD; ++i) {
4158 extract_field(f, &format_info[fmt].op[i], insn);
4159 }
4160 }
4161 return info;
4162 }
4163
4164 static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
4165 {
4166 const DisasInsn *insn;
4167 ExitStatus ret = NO_EXIT;
4168 DisasFields f;
4169 DisasOps o;
4170
4171 insn = extract_insn(env, s, &f);
4172
4173 /* If not found, try the old interpreter. This includes ILLOPC. */
4174 if (insn == NULL) {
4175 disas_s390_insn(env, s);
4176 switch (s->is_jmp) {
4177 case DISAS_NEXT:
4178 ret = NO_EXIT;
4179 break;
4180 case DISAS_TB_JUMP:
4181 ret = EXIT_GOTO_TB;
4182 break;
4183 case DISAS_JUMP:
4184 ret = EXIT_PC_UPDATED;
4185 break;
4186 case DISAS_EXCP:
4187 ret = EXIT_NORETURN;
4188 break;
4189 default:
4190 abort();
4191 }
4192
4193 s->pc = s->next_pc;
4194 return ret;
4195 }
4196
4197 /* Set up the strutures we use to communicate with the helpers. */
4198 s->insn = insn;
4199 s->fields = &f;
4200 o.g_out = o.g_out2 = o.g_in1 = o.g_in2 = false;
4201 TCGV_UNUSED_I64(o.out);
4202 TCGV_UNUSED_I64(o.out2);
4203 TCGV_UNUSED_I64(o.in1);
4204 TCGV_UNUSED_I64(o.in2);
4205 TCGV_UNUSED_I64(o.addr1);
4206
4207 /* Implement the instruction. */
4208 if (insn->help_in1) {
4209 insn->help_in1(s, &f, &o);
4210 }
4211 if (insn->help_in2) {
4212 insn->help_in2(s, &f, &o);
4213 }
4214 if (insn->help_prep) {
4215 insn->help_prep(s, &f, &o);
4216 }
4217 if (insn->help_op) {
4218 ret = insn->help_op(s, &o);
4219 }
4220 if (insn->help_wout) {
4221 insn->help_wout(s, &f, &o);
4222 }
4223 if (insn->help_cout) {
4224 insn->help_cout(s, &o);
4225 }
4226
4227 /* Free any temporaries created by the helpers. */
4228 if (!TCGV_IS_UNUSED_I64(o.out) && !o.g_out) {
4229 tcg_temp_free_i64(o.out);
4230 }
4231 if (!TCGV_IS_UNUSED_I64(o.out2) && !o.g_out2) {
4232 tcg_temp_free_i64(o.out2);
4233 }
4234 if (!TCGV_IS_UNUSED_I64(o.in1) && !o.g_in1) {
4235 tcg_temp_free_i64(o.in1);
4236 }
4237 if (!TCGV_IS_UNUSED_I64(o.in2) && !o.g_in2) {
4238 tcg_temp_free_i64(o.in2);
4239 }
4240 if (!TCGV_IS_UNUSED_I64(o.addr1)) {
4241 tcg_temp_free_i64(o.addr1);
4242 }
4243
4244 /* Advance to the next instruction. */
4245 s->pc = s->next_pc;
4246 return ret;
4247 }
4248
4249 static inline void gen_intermediate_code_internal(CPUS390XState *env,
4250 TranslationBlock *tb,
4251 int search_pc)
4252 {
4253 DisasContext dc;
4254 target_ulong pc_start;
4255 uint64_t next_page_start;
4256 uint16_t *gen_opc_end;
4257 int j, lj = -1;
4258 int num_insns, max_insns;
4259 CPUBreakpoint *bp;
4260 ExitStatus status;
4261 bool do_debug;
4262
4263 pc_start = tb->pc;
4264
4265 /* 31-bit mode */
4266 if (!(tb->flags & FLAG_MASK_64)) {
4267 pc_start &= 0x7fffffff;
4268 }
4269
4270 dc.tb = tb;
4271 dc.pc = pc_start;
4272 dc.cc_op = CC_OP_DYNAMIC;
4273 do_debug = dc.singlestep_enabled = env->singlestep_enabled;
4274 dc.is_jmp = DISAS_NEXT;
4275
4276 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
4277
4278 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4279
4280 num_insns = 0;
4281 max_insns = tb->cflags & CF_COUNT_MASK;
4282 if (max_insns == 0) {
4283 max_insns = CF_COUNT_MASK;
4284 }
4285
4286 gen_icount_start();
4287
4288 do {
4289 if (search_pc) {
4290 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4291 if (lj < j) {
4292 lj++;
4293 while (lj < j) {
4294 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4295 }
4296 }
4297 tcg_ctx.gen_opc_pc[lj] = dc.pc;
4298 gen_opc_cc_op[lj] = dc.cc_op;
4299 tcg_ctx.gen_opc_instr_start[lj] = 1;
4300 tcg_ctx.gen_opc_icount[lj] = num_insns;
4301 }
4302 if (++num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
4303 gen_io_start();
4304 }
4305
4306 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
4307 tcg_gen_debug_insn_start(dc.pc);
4308 }
4309
4310 status = NO_EXIT;
4311 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
4312 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
4313 if (bp->pc == dc.pc) {
4314 status = EXIT_PC_STALE;
4315 do_debug = true;
4316 break;
4317 }
4318 }
4319 }
4320 if (status == NO_EXIT) {
4321 status = translate_one(env, &dc);
4322 }
4323
4324 /* If we reach a page boundary, are single stepping,
4325 or exhaust instruction count, stop generation. */
4326 if (status == NO_EXIT
4327 && (dc.pc >= next_page_start
4328 || tcg_ctx.gen_opc_ptr >= gen_opc_end
4329 || num_insns >= max_insns
4330 || singlestep
4331 || env->singlestep_enabled)) {
4332 status = EXIT_PC_STALE;
4333 }
4334 } while (status == NO_EXIT);
4335
4336 if (tb->cflags & CF_LAST_IO) {
4337 gen_io_end();
4338 }
4339
4340 switch (status) {
4341 case EXIT_GOTO_TB:
4342 case EXIT_NORETURN:
4343 break;
4344 case EXIT_PC_STALE:
4345 update_psw_addr(&dc);
4346 /* FALLTHRU */
4347 case EXIT_PC_UPDATED:
4348 if (singlestep && dc.cc_op != CC_OP_DYNAMIC) {
4349 gen_op_calc_cc(&dc);
4350 } else {
4351 /* Next TB starts off with CC_OP_DYNAMIC,
4352 so make sure the cc op type is in env */
4353 gen_op_set_cc_op(&dc);
4354 }
4355 if (do_debug) {
4356 gen_exception(EXCP_DEBUG);
4357 } else {
4358 /* Generate the return instruction */
4359 tcg_gen_exit_tb(0);
4360 }
4361 break;
4362 default:
4363 abort();
4364 }
4365
4366 gen_icount_end(tb, num_insns);
4367 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
4368 if (search_pc) {
4369 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4370 lj++;
4371 while (lj <= j) {
4372 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4373 }
4374 } else {
4375 tb->size = dc.pc - pc_start;
4376 tb->icount = num_insns;
4377 }
4378
4379 #if defined(S390X_DEBUG_DISAS)
4380 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
4381 qemu_log("IN: %s\n", lookup_symbol(pc_start));
4382 log_target_disas(env, pc_start, dc.pc - pc_start, 1);
4383 qemu_log("\n");
4384 }
4385 #endif
4386 }
4387
4388 void gen_intermediate_code (CPUS390XState *env, struct TranslationBlock *tb)
4389 {
4390 gen_intermediate_code_internal(env, tb, 0);
4391 }
4392
4393 void gen_intermediate_code_pc (CPUS390XState *env, struct TranslationBlock *tb)
4394 {
4395 gen_intermediate_code_internal(env, tb, 1);
4396 }
4397
4398 void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, int pc_pos)
4399 {
4400 int cc_op;
4401 env->psw.addr = tcg_ctx.gen_opc_pc[pc_pos];
4402 cc_op = gen_opc_cc_op[pc_pos];
4403 if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {
4404 env->cc_op = cc_op;
4405 }
4406 }
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