]> git.proxmox.com Git - mirror_qemu.git/blob - target-s390x/translate.c
projects / mirror_qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
target-s390: Implement STORE ON CONDITION
[mirror_qemu.git] / target-s390x / translate.c
1 /*
2 * S/390 translation
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* #define DEBUG_INLINE_BRANCHES */
22 #define S390X_DEBUG_DISAS
23 /* #define S390X_DEBUG_DISAS_VERBOSE */
24
25 #ifdef S390X_DEBUG_DISAS_VERBOSE
26 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
27 #else
28 # define LOG_DISAS(...) do { } while (0)
29 #endif
30
31 #include "cpu.h"
32 #include "disas/disas.h"
33 #include "tcg-op.h"
34 #include "qemu/log.h"
35 #include "qemu/host-utils.h"
36
37 /* global register indexes */
38 static TCGv_ptr cpu_env;
39
40 #include "exec/gen-icount.h"
41 #include "helper.h"
42 #define GEN_HELPER 1
43 #include "helper.h"
44
45
46 /* Information that (most) every instruction needs to manipulate. */
47 typedef struct DisasContext DisasContext;
48 typedef struct DisasInsn DisasInsn;
49 typedef struct DisasFields DisasFields;
50
51 struct DisasContext {
52 struct TranslationBlock *tb;
53 const DisasInsn *insn;
54 DisasFields *fields;
55 uint64_t pc, next_pc;
56 enum cc_op cc_op;
57 bool singlestep_enabled;
58 };
59
60 /* Information carried about a condition to be evaluated. */
61 typedef struct {
62 TCGCond cond:8;
63 bool is_64;
64 bool g1;
65 bool g2;
66 union {
67 struct { TCGv_i64 a, b; } s64;
68 struct { TCGv_i32 a, b; } s32;
69 } u;
70 } DisasCompare;
71
72 #define DISAS_EXCP 4
73
74 #ifdef DEBUG_INLINE_BRANCHES
75 static uint64_t inline_branch_hit[CC_OP_MAX];
76 static uint64_t inline_branch_miss[CC_OP_MAX];
77 #endif
78
79 static uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
80 {
81 if (!(s->tb->flags & FLAG_MASK_64)) {
82 if (s->tb->flags & FLAG_MASK_32) {
83 return pc | 0x80000000;
84 }
85 }
86 return pc;
87 }
88
89 void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
90 int flags)
91 {
92 int i;
93
94 if (env->cc_op > 3) {
95 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
96 env->psw.mask, env->psw.addr, cc_name(env->cc_op));
97 } else {
98 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
99 env->psw.mask, env->psw.addr, env->cc_op);
100 }
101
102 for (i = 0; i < 16; i++) {
103 cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
104 if ((i % 4) == 3) {
105 cpu_fprintf(f, "\n");
106 } else {
107 cpu_fprintf(f, " ");
108 }
109 }
110
111 for (i = 0; i < 16; i++) {
112 cpu_fprintf(f, "F%02d=%016" PRIx64, i, env->fregs[i].ll);
113 if ((i % 4) == 3) {
114 cpu_fprintf(f, "\n");
115 } else {
116 cpu_fprintf(f, " ");
117 }
118 }
119
120 #ifndef CONFIG_USER_ONLY
121 for (i = 0; i < 16; i++) {
122 cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
123 if ((i % 4) == 3) {
124 cpu_fprintf(f, "\n");
125 } else {
126 cpu_fprintf(f, " ");
127 }
128 }
129 #endif
130
131 #ifdef DEBUG_INLINE_BRANCHES
132 for (i = 0; i < CC_OP_MAX; i++) {
133 cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
134 inline_branch_miss[i], inline_branch_hit[i]);
135 }
136 #endif
137
138 cpu_fprintf(f, "\n");
139 }
140
141 static TCGv_i64 psw_addr;
142 static TCGv_i64 psw_mask;
143
144 static TCGv_i32 cc_op;
145 static TCGv_i64 cc_src;
146 static TCGv_i64 cc_dst;
147 static TCGv_i64 cc_vr;
148
149 static char cpu_reg_names[32][4];
150 static TCGv_i64 regs[16];
151 static TCGv_i64 fregs[16];
152
153 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
154
155 void s390x_translate_init(void)
156 {
157 int i;
158
159 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
160 psw_addr = tcg_global_mem_new_i64(TCG_AREG0,
161 offsetof(CPUS390XState, psw.addr),
162 "psw_addr");
163 psw_mask = tcg_global_mem_new_i64(TCG_AREG0,
164 offsetof(CPUS390XState, psw.mask),
165 "psw_mask");
166
167 cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUS390XState, cc_op),
168 "cc_op");
169 cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_src),
170 "cc_src");
171 cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_dst),
172 "cc_dst");
173 cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_vr),
174 "cc_vr");
175
176 for (i = 0; i < 16; i++) {
177 snprintf(cpu_reg_names[i], sizeof(cpu_reg_names[0]), "r%d", i);
178 regs[i] = tcg_global_mem_new(TCG_AREG0,
179 offsetof(CPUS390XState, regs[i]),
180 cpu_reg_names[i]);
181 }
182
183 for (i = 0; i < 16; i++) {
184 snprintf(cpu_reg_names[i + 16], sizeof(cpu_reg_names[0]), "f%d", i);
185 fregs[i] = tcg_global_mem_new(TCG_AREG0,
186 offsetof(CPUS390XState, fregs[i].d),
187 cpu_reg_names[i + 16]);
188 }
189
190 /* register helpers */
191 #define GEN_HELPER 2
192 #include "helper.h"
193 }
194
195 static TCGv_i64 load_reg(int reg)
196 {
197 TCGv_i64 r = tcg_temp_new_i64();
198 tcg_gen_mov_i64(r, regs[reg]);
199 return r;
200 }
201
202 static TCGv_i64 load_freg32_i64(int reg)
203 {
204 TCGv_i64 r = tcg_temp_new_i64();
205 tcg_gen_shri_i64(r, fregs[reg], 32);
206 return r;
207 }
208
209 static void store_reg(int reg, TCGv_i64 v)
210 {
211 tcg_gen_mov_i64(regs[reg], v);
212 }
213
214 static void store_freg(int reg, TCGv_i64 v)
215 {
216 tcg_gen_mov_i64(fregs[reg], v);
217 }
218
219 static void store_reg32_i64(int reg, TCGv_i64 v)
220 {
221 /* 32 bit register writes keep the upper half */
222 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
223 }
224
225 static void store_reg32h_i64(int reg, TCGv_i64 v)
226 {
227 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 32, 32);
228 }
229
230 static void store_freg32_i64(int reg, TCGv_i64 v)
231 {
232 tcg_gen_deposit_i64(fregs[reg], fregs[reg], v, 32, 32);
233 }
234
235 static void return_low128(TCGv_i64 dest)
236 {
237 tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl));
238 }
239
240 static void update_psw_addr(DisasContext *s)
241 {
242 /* psw.addr */
243 tcg_gen_movi_i64(psw_addr, s->pc);
244 }
245
246 static void update_cc_op(DisasContext *s)
247 {
248 if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) {
249 tcg_gen_movi_i32(cc_op, s->cc_op);
250 }
251 }
252
253 static void potential_page_fault(DisasContext *s)
254 {
255 update_psw_addr(s);
256 update_cc_op(s);
257 }
258
259 static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
260 {
261 return (uint64_t)cpu_lduw_code(env, pc);
262 }
263
264 static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
265 {
266 return (uint64_t)(uint32_t)cpu_ldl_code(env, pc);
267 }
268
269 static inline uint64_t ld_code6(CPUS390XState *env, uint64_t pc)
270 {
271 return (ld_code2(env, pc) << 32) | ld_code4(env, pc + 2);
272 }
273
274 static int get_mem_index(DisasContext *s)
275 {
276 switch (s->tb->flags & FLAG_MASK_ASC) {
277 case PSW_ASC_PRIMARY >> 32:
278 return 0;
279 case PSW_ASC_SECONDARY >> 32:
280 return 1;
281 case PSW_ASC_HOME >> 32:
282 return 2;
283 default:
284 tcg_abort();
285 break;
286 }
287 }
288
289 static void gen_exception(int excp)
290 {
291 TCGv_i32 tmp = tcg_const_i32(excp);
292 gen_helper_exception(cpu_env, tmp);
293 tcg_temp_free_i32(tmp);
294 }
295
296 static void gen_program_exception(DisasContext *s, int code)
297 {
298 TCGv_i32 tmp;
299
300 /* Remember what pgm exeption this was. */
301 tmp = tcg_const_i32(code);
302 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
303 tcg_temp_free_i32(tmp);
304
305 tmp = tcg_const_i32(s->next_pc - s->pc);
306 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen));
307 tcg_temp_free_i32(tmp);
308
309 /* Advance past instruction. */
310 s->pc = s->next_pc;
311 update_psw_addr(s);
312
313 /* Save off cc. */
314 update_cc_op(s);
315
316 /* Trigger exception. */
317 gen_exception(EXCP_PGM);
318 }
319
320 static inline void gen_illegal_opcode(DisasContext *s)
321 {
322 gen_program_exception(s, PGM_SPECIFICATION);
323 }
324
325 static inline void check_privileged(DisasContext *s)
326 {
327 if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
328 gen_program_exception(s, PGM_PRIVILEGED);
329 }
330 }
331
332 static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
333 {
334 TCGv_i64 tmp;
335
336 /* 31-bitify the immediate part; register contents are dealt with below */
337 if (!(s->tb->flags & FLAG_MASK_64)) {
338 d2 &= 0x7fffffffUL;
339 }
340
341 if (x2) {
342 if (d2) {
343 tmp = tcg_const_i64(d2);
344 tcg_gen_add_i64(tmp, tmp, regs[x2]);
345 } else {
346 tmp = load_reg(x2);
347 }
348 if (b2) {
349 tcg_gen_add_i64(tmp, tmp, regs[b2]);
350 }
351 } else if (b2) {
352 if (d2) {
353 tmp = tcg_const_i64(d2);
354 tcg_gen_add_i64(tmp, tmp, regs[b2]);
355 } else {
356 tmp = load_reg(b2);
357 }
358 } else {
359 tmp = tcg_const_i64(d2);
360 }
361
362 /* 31-bit mode mask if there are values loaded from registers */
363 if (!(s->tb->flags & FLAG_MASK_64) && (x2 || b2)) {
364 tcg_gen_andi_i64(tmp, tmp, 0x7fffffffUL);
365 }
366
367 return tmp;
368 }
369
370 static inline void gen_op_movi_cc(DisasContext *s, uint32_t val)
371 {
372 s->cc_op = CC_OP_CONST0 + val;
373 }
374
375 static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst)
376 {
377 tcg_gen_discard_i64(cc_src);
378 tcg_gen_mov_i64(cc_dst, dst);
379 tcg_gen_discard_i64(cc_vr);
380 s->cc_op = op;
381 }
382
383 static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
384 TCGv_i64 dst)
385 {
386 tcg_gen_mov_i64(cc_src, src);
387 tcg_gen_mov_i64(cc_dst, dst);
388 tcg_gen_discard_i64(cc_vr);
389 s->cc_op = op;
390 }
391
392 static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
393 TCGv_i64 dst, TCGv_i64 vr)
394 {
395 tcg_gen_mov_i64(cc_src, src);
396 tcg_gen_mov_i64(cc_dst, dst);
397 tcg_gen_mov_i64(cc_vr, vr);
398 s->cc_op = op;
399 }
400
401 static void set_cc_nz_u64(DisasContext *s, TCGv_i64 val)
402 {
403 gen_op_update1_cc_i64(s, CC_OP_NZ, val);
404 }
405
406 static void gen_set_cc_nz_f32(DisasContext *s, TCGv_i64 val)
407 {
408 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, val);
409 }
410
411 static void gen_set_cc_nz_f64(DisasContext *s, TCGv_i64 val)
412 {
413 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, val);
414 }
415
416 static void gen_set_cc_nz_f128(DisasContext *s, TCGv_i64 vh, TCGv_i64 vl)
417 {
418 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, vh, vl);
419 }
420
421 /* CC value is in env->cc_op */
422 static void set_cc_static(DisasContext *s)
423 {
424 tcg_gen_discard_i64(cc_src);
425 tcg_gen_discard_i64(cc_dst);
426 tcg_gen_discard_i64(cc_vr);
427 s->cc_op = CC_OP_STATIC;
428 }
429
430 /* calculates cc into cc_op */
431 static void gen_op_calc_cc(DisasContext *s)
432 {
433 TCGv_i32 local_cc_op;
434 TCGv_i64 dummy;
435
436 TCGV_UNUSED_I32(local_cc_op);
437 TCGV_UNUSED_I64(dummy);
438 switch (s->cc_op) {
439 default:
440 dummy = tcg_const_i64(0);
441 /* FALLTHRU */
442 case CC_OP_ADD_64:
443 case CC_OP_ADDU_64:
444 case CC_OP_ADDC_64:
445 case CC_OP_SUB_64:
446 case CC_OP_SUBU_64:
447 case CC_OP_SUBB_64:
448 case CC_OP_ADD_32:
449 case CC_OP_ADDU_32:
450 case CC_OP_ADDC_32:
451 case CC_OP_SUB_32:
452 case CC_OP_SUBU_32:
453 case CC_OP_SUBB_32:
454 local_cc_op = tcg_const_i32(s->cc_op);
455 break;
456 case CC_OP_CONST0:
457 case CC_OP_CONST1:
458 case CC_OP_CONST2:
459 case CC_OP_CONST3:
460 case CC_OP_STATIC:
461 case CC_OP_DYNAMIC:
462 break;
463 }
464
465 switch (s->cc_op) {
466 case CC_OP_CONST0:
467 case CC_OP_CONST1:
468 case CC_OP_CONST2:
469 case CC_OP_CONST3:
470 /* s->cc_op is the cc value */
471 tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
472 break;
473 case CC_OP_STATIC:
474 /* env->cc_op already is the cc value */
475 break;
476 case CC_OP_NZ:
477 case CC_OP_ABS_64:
478 case CC_OP_NABS_64:
479 case CC_OP_ABS_32:
480 case CC_OP_NABS_32:
481 case CC_OP_LTGT0_32:
482 case CC_OP_LTGT0_64:
483 case CC_OP_COMP_32:
484 case CC_OP_COMP_64:
485 case CC_OP_NZ_F32:
486 case CC_OP_NZ_F64:
487 case CC_OP_FLOGR:
488 /* 1 argument */
489 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dummy);
490 break;
491 case CC_OP_ICM:
492 case CC_OP_LTGT_32:
493 case CC_OP_LTGT_64:
494 case CC_OP_LTUGTU_32:
495 case CC_OP_LTUGTU_64:
496 case CC_OP_TM_32:
497 case CC_OP_TM_64:
498 case CC_OP_SLA_32:
499 case CC_OP_SLA_64:
500 case CC_OP_NZ_F128:
501 /* 2 arguments */
502 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
503 break;
504 case CC_OP_ADD_64:
505 case CC_OP_ADDU_64:
506 case CC_OP_ADDC_64:
507 case CC_OP_SUB_64:
508 case CC_OP_SUBU_64:
509 case CC_OP_SUBB_64:
510 case CC_OP_ADD_32:
511 case CC_OP_ADDU_32:
512 case CC_OP_ADDC_32:
513 case CC_OP_SUB_32:
514 case CC_OP_SUBU_32:
515 case CC_OP_SUBB_32:
516 /* 3 arguments */
517 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc_vr);
518 break;
519 case CC_OP_DYNAMIC:
520 /* unknown operation - assume 3 arguments and cc_op in env */
521 gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr);
522 break;
523 default:
524 tcg_abort();
525 }
526
527 if (!TCGV_IS_UNUSED_I32(local_cc_op)) {
528 tcg_temp_free_i32(local_cc_op);
529 }
530 if (!TCGV_IS_UNUSED_I64(dummy)) {
531 tcg_temp_free_i64(dummy);
532 }
533
534 /* We now have cc in cc_op as constant */
535 set_cc_static(s);
536 }
537
538 static int use_goto_tb(DisasContext *s, uint64_t dest)
539 {
540 /* NOTE: we handle the case where the TB spans two pages here */
541 return (((dest & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK)
542 || (dest & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK))
543 && !s->singlestep_enabled
544 && !(s->tb->cflags & CF_LAST_IO));
545 }
546
547 static void account_noninline_branch(DisasContext *s, int cc_op)
548 {
549 #ifdef DEBUG_INLINE_BRANCHES
550 inline_branch_miss[cc_op]++;
551 #endif
552 }
553
554 static void account_inline_branch(DisasContext *s, int cc_op)
555 {
556 #ifdef DEBUG_INLINE_BRANCHES
557 inline_branch_hit[cc_op]++;
558 #endif
559 }
560
561 /* Table of mask values to comparison codes, given a comparison as input.
562 For a true comparison CC=3 will never be set, but we treat this
563 conservatively for possible use when CC=3 indicates overflow. */
564 static const TCGCond ltgt_cond[16] = {
565 TCG_COND_NEVER, TCG_COND_NEVER, /* | | | x */
566 TCG_COND_GT, TCG_COND_NEVER, /* | | GT | x */
567 TCG_COND_LT, TCG_COND_NEVER, /* | LT | | x */
568 TCG_COND_NE, TCG_COND_NEVER, /* | LT | GT | x */
569 TCG_COND_EQ, TCG_COND_NEVER, /* EQ | | | x */
570 TCG_COND_GE, TCG_COND_NEVER, /* EQ | | GT | x */
571 TCG_COND_LE, TCG_COND_NEVER, /* EQ | LT | | x */
572 TCG_COND_ALWAYS, TCG_COND_ALWAYS, /* EQ | LT | GT | x */
573 };
574
575 /* Table of mask values to comparison codes, given a logic op as input.
576 For such, only CC=0 and CC=1 should be possible. */
577 static const TCGCond nz_cond[16] = {
578 /* | | x | x */
579 TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER,
580 /* | NE | x | x */
581 TCG_COND_NE, TCG_COND_NE, TCG_COND_NE, TCG_COND_NE,
582 /* EQ | | x | x */
583 TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ,
584 /* EQ | NE | x | x */
585 TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS,
586 };
587
588 /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
589 details required to generate a TCG comparison. */
590 static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
591 {
592 TCGCond cond;
593 enum cc_op old_cc_op = s->cc_op;
594
595 if (mask == 15 || mask == 0) {
596 c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER);
597 c->u.s32.a = cc_op;
598 c->u.s32.b = cc_op;
599 c->g1 = c->g2 = true;
600 c->is_64 = false;
601 return;
602 }
603
604 /* Find the TCG condition for the mask + cc op. */
605 switch (old_cc_op) {
606 case CC_OP_LTGT0_32:
607 case CC_OP_LTGT0_64:
608 case CC_OP_LTGT_32:
609 case CC_OP_LTGT_64:
610 cond = ltgt_cond[mask];
611 if (cond == TCG_COND_NEVER) {
612 goto do_dynamic;
613 }
614 account_inline_branch(s, old_cc_op);
615 break;
616
617 case CC_OP_LTUGTU_32:
618 case CC_OP_LTUGTU_64:
619 cond = tcg_unsigned_cond(ltgt_cond[mask]);
620 if (cond == TCG_COND_NEVER) {
621 goto do_dynamic;
622 }
623 account_inline_branch(s, old_cc_op);
624 break;
625
626 case CC_OP_NZ:
627 cond = nz_cond[mask];
628 if (cond == TCG_COND_NEVER) {
629 goto do_dynamic;
630 }
631 account_inline_branch(s, old_cc_op);
632 break;
633
634 case CC_OP_TM_32:
635 case CC_OP_TM_64:
636 switch (mask) {
637 case 8:
638 cond = TCG_COND_EQ;
639 break;
640 case 4 | 2 | 1:
641 cond = TCG_COND_NE;
642 break;
643 default:
644 goto do_dynamic;
645 }
646 account_inline_branch(s, old_cc_op);
647 break;
648
649 case CC_OP_ICM:
650 switch (mask) {
651 case 8:
652 cond = TCG_COND_EQ;
653 break;
654 case 4 | 2 | 1:
655 case 4 | 2:
656 cond = TCG_COND_NE;
657 break;
658 default:
659 goto do_dynamic;
660 }
661 account_inline_branch(s, old_cc_op);
662 break;
663
664 case CC_OP_FLOGR:
665 switch (mask & 0xa) {
666 case 8: /* src == 0 -> no one bit found */
667 cond = TCG_COND_EQ;
668 break;
669 case 2: /* src != 0 -> one bit found */
670 cond = TCG_COND_NE;
671 break;
672 default:
673 goto do_dynamic;
674 }
675 account_inline_branch(s, old_cc_op);
676 break;
677
678 default:
679 do_dynamic:
680 /* Calculate cc value. */
681 gen_op_calc_cc(s);
682 /* FALLTHRU */
683
684 case CC_OP_STATIC:
685 /* Jump based on CC. We'll load up the real cond below;
686 the assignment here merely avoids a compiler warning. */
687 account_noninline_branch(s, old_cc_op);
688 old_cc_op = CC_OP_STATIC;
689 cond = TCG_COND_NEVER;
690 break;
691 }
692
693 /* Load up the arguments of the comparison. */
694 c->is_64 = true;
695 c->g1 = c->g2 = false;
696 switch (old_cc_op) {
697 case CC_OP_LTGT0_32:
698 c->is_64 = false;
699 c->u.s32.a = tcg_temp_new_i32();
700 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_dst);
701 c->u.s32.b = tcg_const_i32(0);
702 break;
703 case CC_OP_LTGT_32:
704 case CC_OP_LTUGTU_32:
705 c->is_64 = false;
706 c->u.s32.a = tcg_temp_new_i32();
707 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_src);
708 c->u.s32.b = tcg_temp_new_i32();
709 tcg_gen_trunc_i64_i32(c->u.s32.b, cc_dst);
710 break;
711
712 case CC_OP_LTGT0_64:
713 case CC_OP_NZ:
714 case CC_OP_FLOGR:
715 c->u.s64.a = cc_dst;
716 c->u.s64.b = tcg_const_i64(0);
717 c->g1 = true;
718 break;
719 case CC_OP_LTGT_64:
720 case CC_OP_LTUGTU_64:
721 c->u.s64.a = cc_src;
722 c->u.s64.b = cc_dst;
723 c->g1 = c->g2 = true;
724 break;
725
726 case CC_OP_TM_32:
727 case CC_OP_TM_64:
728 case CC_OP_ICM:
729 c->u.s64.a = tcg_temp_new_i64();
730 c->u.s64.b = tcg_const_i64(0);
731 tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst);
732 break;
733
734 case CC_OP_STATIC:
735 c->is_64 = false;
736 c->u.s32.a = cc_op;
737 c->g1 = true;
738 switch (mask) {
739 case 0x8 | 0x4 | 0x2: /* cc != 3 */
740 cond = TCG_COND_NE;
741 c->u.s32.b = tcg_const_i32(3);
742 break;
743 case 0x8 | 0x4 | 0x1: /* cc != 2 */
744 cond = TCG_COND_NE;
745 c->u.s32.b = tcg_const_i32(2);
746 break;
747 case 0x8 | 0x2 | 0x1: /* cc != 1 */
748 cond = TCG_COND_NE;
749 c->u.s32.b = tcg_const_i32(1);
750 break;
751 case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
752 cond = TCG_COND_EQ;
753 c->g1 = false;
754 c->u.s32.a = tcg_temp_new_i32();
755 c->u.s32.b = tcg_const_i32(0);
756 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
757 break;
758 case 0x8 | 0x4: /* cc < 2 */
759 cond = TCG_COND_LTU;
760 c->u.s32.b = tcg_const_i32(2);
761 break;
762 case 0x8: /* cc == 0 */
763 cond = TCG_COND_EQ;
764 c->u.s32.b = tcg_const_i32(0);
765 break;
766 case 0x4 | 0x2 | 0x1: /* cc != 0 */
767 cond = TCG_COND_NE;
768 c->u.s32.b = tcg_const_i32(0);
769 break;
770 case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
771 cond = TCG_COND_NE;
772 c->g1 = false;
773 c->u.s32.a = tcg_temp_new_i32();
774 c->u.s32.b = tcg_const_i32(0);
775 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
776 break;
777 case 0x4: /* cc == 1 */
778 cond = TCG_COND_EQ;
779 c->u.s32.b = tcg_const_i32(1);
780 break;
781 case 0x2 | 0x1: /* cc > 1 */
782 cond = TCG_COND_GTU;
783 c->u.s32.b = tcg_const_i32(1);
784 break;
785 case 0x2: /* cc == 2 */
786 cond = TCG_COND_EQ;
787 c->u.s32.b = tcg_const_i32(2);
788 break;
789 case 0x1: /* cc == 3 */
790 cond = TCG_COND_EQ;
791 c->u.s32.b = tcg_const_i32(3);
792 break;
793 default:
794 /* CC is masked by something else: (8 >> cc) & mask. */
795 cond = TCG_COND_NE;
796 c->g1 = false;
797 c->u.s32.a = tcg_const_i32(8);
798 c->u.s32.b = tcg_const_i32(0);
799 tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op);
800 tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask);
801 break;
802 }
803 break;
804
805 default:
806 abort();
807 }
808 c->cond = cond;
809 }
810
811 static void free_compare(DisasCompare *c)
812 {
813 if (!c->g1) {
814 if (c->is_64) {
815 tcg_temp_free_i64(c->u.s64.a);
816 } else {
817 tcg_temp_free_i32(c->u.s32.a);
818 }
819 }
820 if (!c->g2) {
821 if (c->is_64) {
822 tcg_temp_free_i64(c->u.s64.b);
823 } else {
824 tcg_temp_free_i32(c->u.s32.b);
825 }
826 }
827 }
828
829 /* ====================================================================== */
830 /* Define the insn format enumeration. */
831 #define F0(N) FMT_##N,
832 #define F1(N, X1) F0(N)
833 #define F2(N, X1, X2) F0(N)
834 #define F3(N, X1, X2, X3) F0(N)
835 #define F4(N, X1, X2, X3, X4) F0(N)
836 #define F5(N, X1, X2, X3, X4, X5) F0(N)
837
838 typedef enum {
839 #include "insn-format.def"
840 } DisasFormat;
841
842 #undef F0
843 #undef F1
844 #undef F2
845 #undef F3
846 #undef F4
847 #undef F5
848
849 /* Define a structure to hold the decoded fields. We'll store each inside
850 an array indexed by an enum. In order to conserve memory, we'll arrange
851 for fields that do not exist at the same time to overlap, thus the "C"
852 for compact. For checking purposes there is an "O" for original index
853 as well that will be applied to availability bitmaps. */
854
855 enum DisasFieldIndexO {
856 FLD_O_r1,
857 FLD_O_r2,
858 FLD_O_r3,
859 FLD_O_m1,
860 FLD_O_m3,
861 FLD_O_m4,
862 FLD_O_b1,
863 FLD_O_b2,
864 FLD_O_b4,
865 FLD_O_d1,
866 FLD_O_d2,
867 FLD_O_d4,
868 FLD_O_x2,
869 FLD_O_l1,
870 FLD_O_l2,
871 FLD_O_i1,
872 FLD_O_i2,
873 FLD_O_i3,
874 FLD_O_i4,
875 FLD_O_i5
876 };
877
878 enum DisasFieldIndexC {
879 FLD_C_r1 = 0,
880 FLD_C_m1 = 0,
881 FLD_C_b1 = 0,
882 FLD_C_i1 = 0,
883
884 FLD_C_r2 = 1,
885 FLD_C_b2 = 1,
886 FLD_C_i2 = 1,
887
888 FLD_C_r3 = 2,
889 FLD_C_m3 = 2,
890 FLD_C_i3 = 2,
891
892 FLD_C_m4 = 3,
893 FLD_C_b4 = 3,
894 FLD_C_i4 = 3,
895 FLD_C_l1 = 3,
896
897 FLD_C_i5 = 4,
898 FLD_C_d1 = 4,
899
900 FLD_C_d2 = 5,
901
902 FLD_C_d4 = 6,
903 FLD_C_x2 = 6,
904 FLD_C_l2 = 6,
905
906 NUM_C_FIELD = 7
907 };
908
909 struct DisasFields {
910 unsigned op:8;
911 unsigned op2:8;
912 unsigned presentC:16;
913 unsigned int presentO;
914 int c[NUM_C_FIELD];
915 };
916
917 /* This is the way fields are to be accessed out of DisasFields. */
918 #define have_field(S, F) have_field1((S), FLD_O_##F)
919 #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
920
921 static bool have_field1(const DisasFields *f, enum DisasFieldIndexO c)
922 {
923 return (f->presentO >> c) & 1;
924 }
925
926 static int get_field1(const DisasFields *f, enum DisasFieldIndexO o,
927 enum DisasFieldIndexC c)
928 {
929 assert(have_field1(f, o));
930 return f->c[c];
931 }
932
933 /* Describe the layout of each field in each format. */
934 typedef struct DisasField {
935 unsigned int beg:8;
936 unsigned int size:8;
937 unsigned int type:2;
938 unsigned int indexC:6;
939 enum DisasFieldIndexO indexO:8;
940 } DisasField;
941
942 typedef struct DisasFormatInfo {
943 DisasField op[NUM_C_FIELD];
944 } DisasFormatInfo;
945
946 #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
947 #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
948 #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
949 { BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
950 #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
951 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
952 { 20, 12, 0, FLD_C_d##N, FLD_O_d##N }
953 #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
954 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
955 #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
956 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
957 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
958 #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N }
959 #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N }
960
961 #define F0(N) { { } },
962 #define F1(N, X1) { { X1 } },
963 #define F2(N, X1, X2) { { X1, X2 } },
964 #define F3(N, X1, X2, X3) { { X1, X2, X3 } },
965 #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
966 #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
967
968 static const DisasFormatInfo format_info[] = {
969 #include "insn-format.def"
970 };
971
972 #undef F0
973 #undef F1
974 #undef F2
975 #undef F3
976 #undef F4
977 #undef F5
978 #undef R
979 #undef M
980 #undef BD
981 #undef BXD
982 #undef BDL
983 #undef BXDL
984 #undef I
985 #undef L
986
987 /* Generally, we'll extract operands into this structures, operate upon
988 them, and store them back. See the "in1", "in2", "prep", "wout" sets
989 of routines below for more details. */
990 typedef struct {
991 bool g_out, g_out2, g_in1, g_in2;
992 TCGv_i64 out, out2, in1, in2;
993 TCGv_i64 addr1;
994 } DisasOps;
995
996 /* Return values from translate_one, indicating the state of the TB. */
997 typedef enum {
998 /* Continue the TB. */
999 NO_EXIT,
1000 /* We have emitted one or more goto_tb. No fixup required. */
1001 EXIT_GOTO_TB,
1002 /* We are not using a goto_tb (for whatever reason), but have updated
1003 the PC (for whatever reason), so there's no need to do it again on
1004 exiting the TB. */
1005 EXIT_PC_UPDATED,
1006 /* We are exiting the TB, but have neither emitted a goto_tb, nor
1007 updated the PC for the next instruction to be executed. */
1008 EXIT_PC_STALE,
1009 /* We are ending the TB with a noreturn function call, e.g. longjmp.
1010 No following code will be executed. */
1011 EXIT_NORETURN,
1012 } ExitStatus;
1013
1014 typedef enum DisasFacility {
1015 FAC_Z, /* zarch (default) */
1016 FAC_CASS, /* compare and swap and store */
1017 FAC_CASS2, /* compare and swap and store 2*/
1018 FAC_DFP, /* decimal floating point */
1019 FAC_DFPR, /* decimal floating point rounding */
1020 FAC_DO, /* distinct operands */
1021 FAC_EE, /* execute extensions */
1022 FAC_EI, /* extended immediate */
1023 FAC_FPE, /* floating point extension */
1024 FAC_FPSSH, /* floating point support sign handling */
1025 FAC_FPRGR, /* FPR-GR transfer */
1026 FAC_GIE, /* general instructions extension */
1027 FAC_HFP_MA, /* HFP multiply-and-add/subtract */
1028 FAC_HW, /* high-word */
1029 FAC_IEEEE_SIM, /* IEEE exception sumilation */
1030 FAC_LOC, /* load/store on condition */
1031 FAC_LD, /* long displacement */
1032 FAC_PC, /* population count */
1033 FAC_SCF, /* store clock fast */
1034 FAC_SFLE, /* store facility list extended */
1035 } DisasFacility;
1036
1037 struct DisasInsn {
1038 unsigned opc:16;
1039 DisasFormat fmt:6;
1040 DisasFacility fac:6;
1041
1042 const char *name;
1043
1044 void (*help_in1)(DisasContext *, DisasFields *, DisasOps *);
1045 void (*help_in2)(DisasContext *, DisasFields *, DisasOps *);
1046 void (*help_prep)(DisasContext *, DisasFields *, DisasOps *);
1047 void (*help_wout)(DisasContext *, DisasFields *, DisasOps *);
1048 void (*help_cout)(DisasContext *, DisasOps *);
1049 ExitStatus (*help_op)(DisasContext *, DisasOps *);
1050
1051 uint64_t data;
1052 };
1053
1054 /* ====================================================================== */
1055 /* Miscelaneous helpers, used by several operations. */
1056
1057 static void help_l2_shift(DisasContext *s, DisasFields *f,
1058 DisasOps *o, int mask)
1059 {
1060 int b2 = get_field(f, b2);
1061 int d2 = get_field(f, d2);
1062
1063 if (b2 == 0) {
1064 o->in2 = tcg_const_i64(d2 & mask);
1065 } else {
1066 o->in2 = get_address(s, 0, b2, d2);
1067 tcg_gen_andi_i64(o->in2, o->in2, mask);
1068 }
1069 }
1070
1071 static ExitStatus help_goto_direct(DisasContext *s, uint64_t dest)
1072 {
1073 if (dest == s->next_pc) {
1074 return NO_EXIT;
1075 }
1076 if (use_goto_tb(s, dest)) {
1077 update_cc_op(s);
1078 tcg_gen_goto_tb(0);
1079 tcg_gen_movi_i64(psw_addr, dest);
1080 tcg_gen_exit_tb((tcg_target_long)s->tb);
1081 return EXIT_GOTO_TB;
1082 } else {
1083 tcg_gen_movi_i64(psw_addr, dest);
1084 return EXIT_PC_UPDATED;
1085 }
1086 }
1087
1088 static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
1089 bool is_imm, int imm, TCGv_i64 cdest)
1090 {
1091 ExitStatus ret;
1092 uint64_t dest = s->pc + 2 * imm;
1093 int lab;
1094
1095 /* Take care of the special cases first. */
1096 if (c->cond == TCG_COND_NEVER) {
1097 ret = NO_EXIT;
1098 goto egress;
1099 }
1100 if (is_imm) {
1101 if (dest == s->next_pc) {
1102 /* Branch to next. */
1103 ret = NO_EXIT;
1104 goto egress;
1105 }
1106 if (c->cond == TCG_COND_ALWAYS) {
1107 ret = help_goto_direct(s, dest);
1108 goto egress;
1109 }
1110 } else {
1111 if (TCGV_IS_UNUSED_I64(cdest)) {
1112 /* E.g. bcr %r0 -> no branch. */
1113 ret = NO_EXIT;
1114 goto egress;
1115 }
1116 if (c->cond == TCG_COND_ALWAYS) {
1117 tcg_gen_mov_i64(psw_addr, cdest);
1118 ret = EXIT_PC_UPDATED;
1119 goto egress;
1120 }
1121 }
1122
1123 if (use_goto_tb(s, s->next_pc)) {
1124 if (is_imm && use_goto_tb(s, dest)) {
1125 /* Both exits can use goto_tb. */
1126 update_cc_op(s);
1127
1128 lab = gen_new_label();
1129 if (c->is_64) {
1130 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1131 } else {
1132 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1133 }
1134
1135 /* Branch not taken. */
1136 tcg_gen_goto_tb(0);
1137 tcg_gen_movi_i64(psw_addr, s->next_pc);
1138 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
1139
1140 /* Branch taken. */
1141 gen_set_label(lab);
1142 tcg_gen_goto_tb(1);
1143 tcg_gen_movi_i64(psw_addr, dest);
1144 tcg_gen_exit_tb((tcg_target_long)s->tb + 1);
1145
1146 ret = EXIT_GOTO_TB;
1147 } else {
1148 /* Fallthru can use goto_tb, but taken branch cannot. */
1149 /* Store taken branch destination before the brcond. This
1150 avoids having to allocate a new local temp to hold it.
1151 We'll overwrite this in the not taken case anyway. */
1152 if (!is_imm) {
1153 tcg_gen_mov_i64(psw_addr, cdest);
1154 }
1155
1156 lab = gen_new_label();
1157 if (c->is_64) {
1158 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1159 } else {
1160 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1161 }
1162
1163 /* Branch not taken. */
1164 update_cc_op(s);
1165 tcg_gen_goto_tb(0);
1166 tcg_gen_movi_i64(psw_addr, s->next_pc);
1167 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
1168
1169 gen_set_label(lab);
1170 if (is_imm) {
1171 tcg_gen_movi_i64(psw_addr, dest);
1172 }
1173 ret = EXIT_PC_UPDATED;
1174 }
1175 } else {
1176 /* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
1177 Most commonly we're single-stepping or some other condition that
1178 disables all use of goto_tb. Just update the PC and exit. */
1179
1180 TCGv_i64 next = tcg_const_i64(s->next_pc);
1181 if (is_imm) {
1182 cdest = tcg_const_i64(dest);
1183 }
1184
1185 if (c->is_64) {
1186 tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b,
1187 cdest, next);
1188 } else {
1189 TCGv_i32 t0 = tcg_temp_new_i32();
1190 TCGv_i64 t1 = tcg_temp_new_i64();
1191 TCGv_i64 z = tcg_const_i64(0);
1192 tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b);
1193 tcg_gen_extu_i32_i64(t1, t0);
1194 tcg_temp_free_i32(t0);
1195 tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next);
1196 tcg_temp_free_i64(t1);
1197 tcg_temp_free_i64(z);
1198 }
1199
1200 if (is_imm) {
1201 tcg_temp_free_i64(cdest);
1202 }
1203 tcg_temp_free_i64(next);
1204
1205 ret = EXIT_PC_UPDATED;
1206 }
1207
1208 egress:
1209 free_compare(c);
1210 return ret;
1211 }
1212
1213 /* ====================================================================== */
1214 /* The operations. These perform the bulk of the work for any insn,
1215 usually after the operands have been loaded and output initialized. */
1216
1217 static ExitStatus op_abs(DisasContext *s, DisasOps *o)
1218 {
1219 gen_helper_abs_i64(o->out, o->in2);
1220 return NO_EXIT;
1221 }
1222
1223 static ExitStatus op_absf32(DisasContext *s, DisasOps *o)
1224 {
1225 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffull);
1226 return NO_EXIT;
1227 }
1228
1229 static ExitStatus op_absf64(DisasContext *s, DisasOps *o)
1230 {
1231 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull);
1232 return NO_EXIT;
1233 }
1234
1235 static ExitStatus op_absf128(DisasContext *s, DisasOps *o)
1236 {
1237 tcg_gen_andi_i64(o->out, o->in1, 0x7fffffffffffffffull);
1238 tcg_gen_mov_i64(o->out2, o->in2);
1239 return NO_EXIT;
1240 }
1241
1242 static ExitStatus op_add(DisasContext *s, DisasOps *o)
1243 {
1244 tcg_gen_add_i64(o->out, o->in1, o->in2);
1245 return NO_EXIT;
1246 }
1247
1248 static ExitStatus op_addc(DisasContext *s, DisasOps *o)
1249 {
1250 TCGv_i64 cc;
1251
1252 tcg_gen_add_i64(o->out, o->in1, o->in2);
1253
1254 /* XXX possible optimization point */
1255 gen_op_calc_cc(s);
1256 cc = tcg_temp_new_i64();
1257 tcg_gen_extu_i32_i64(cc, cc_op);
1258 tcg_gen_shri_i64(cc, cc, 1);
1259
1260 tcg_gen_add_i64(o->out, o->out, cc);
1261 tcg_temp_free_i64(cc);
1262 return NO_EXIT;
1263 }
1264
1265 static ExitStatus op_aeb(DisasContext *s, DisasOps *o)
1266 {
1267 gen_helper_aeb(o->out, cpu_env, o->in1, o->in2);
1268 return NO_EXIT;
1269 }
1270
1271 static ExitStatus op_adb(DisasContext *s, DisasOps *o)
1272 {
1273 gen_helper_adb(o->out, cpu_env, o->in1, o->in2);
1274 return NO_EXIT;
1275 }
1276
1277 static ExitStatus op_axb(DisasContext *s, DisasOps *o)
1278 {
1279 gen_helper_axb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
1280 return_low128(o->out2);
1281 return NO_EXIT;
1282 }
1283
1284 static ExitStatus op_and(DisasContext *s, DisasOps *o)
1285 {
1286 tcg_gen_and_i64(o->out, o->in1, o->in2);
1287 return NO_EXIT;
1288 }
1289
1290 static ExitStatus op_andi(DisasContext *s, DisasOps *o)
1291 {
1292 int shift = s->insn->data & 0xff;
1293 int size = s->insn->data >> 8;
1294 uint64_t mask = ((1ull << size) - 1) << shift;
1295
1296 assert(!o->g_in2);
1297 tcg_gen_shli_i64(o->in2, o->in2, shift);
1298 tcg_gen_ori_i64(o->in2, o->in2, ~mask);
1299 tcg_gen_and_i64(o->out, o->in1, o->in2);
1300
1301 /* Produce the CC from only the bits manipulated. */
1302 tcg_gen_andi_i64(cc_dst, o->out, mask);
1303 set_cc_nz_u64(s, cc_dst);
1304 return NO_EXIT;
1305 }
1306
1307 static ExitStatus op_bas(DisasContext *s, DisasOps *o)
1308 {
1309 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1310 if (!TCGV_IS_UNUSED_I64(o->in2)) {
1311 tcg_gen_mov_i64(psw_addr, o->in2);
1312 return EXIT_PC_UPDATED;
1313 } else {
1314 return NO_EXIT;
1315 }
1316 }
1317
1318 static ExitStatus op_basi(DisasContext *s, DisasOps *o)
1319 {
1320 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1321 return help_goto_direct(s, s->pc + 2 * get_field(s->fields, i2));
1322 }
1323
1324 static ExitStatus op_bc(DisasContext *s, DisasOps *o)
1325 {
1326 int m1 = get_field(s->fields, m1);
1327 bool is_imm = have_field(s->fields, i2);
1328 int imm = is_imm ? get_field(s->fields, i2) : 0;
1329 DisasCompare c;
1330
1331 disas_jcc(s, &c, m1);
1332 return help_branch(s, &c, is_imm, imm, o->in2);
1333 }
1334
1335 static ExitStatus op_bct32(DisasContext *s, DisasOps *o)
1336 {
1337 int r1 = get_field(s->fields, r1);
1338 bool is_imm = have_field(s->fields, i2);
1339 int imm = is_imm ? get_field(s->fields, i2) : 0;
1340 DisasCompare c;
1341 TCGv_i64 t;
1342
1343 c.cond = TCG_COND_NE;
1344 c.is_64 = false;
1345 c.g1 = false;
1346 c.g2 = false;
1347
1348 t = tcg_temp_new_i64();
1349 tcg_gen_subi_i64(t, regs[r1], 1);
1350 store_reg32_i64(r1, t);
1351 c.u.s32.a = tcg_temp_new_i32();
1352 c.u.s32.b = tcg_const_i32(0);
1353 tcg_gen_trunc_i64_i32(c.u.s32.a, t);
1354 tcg_temp_free_i64(t);
1355
1356 return help_branch(s, &c, is_imm, imm, o->in2);
1357 }
1358
1359 static ExitStatus op_bct64(DisasContext *s, DisasOps *o)
1360 {
1361 int r1 = get_field(s->fields, r1);
1362 bool is_imm = have_field(s->fields, i2);
1363 int imm = is_imm ? get_field(s->fields, i2) : 0;
1364 DisasCompare c;
1365
1366 c.cond = TCG_COND_NE;
1367 c.is_64 = true;
1368 c.g1 = true;
1369 c.g2 = false;
1370
1371 tcg_gen_subi_i64(regs[r1], regs[r1], 1);
1372 c.u.s64.a = regs[r1];
1373 c.u.s64.b = tcg_const_i64(0);
1374
1375 return help_branch(s, &c, is_imm, imm, o->in2);
1376 }
1377
1378 static ExitStatus op_bx32(DisasContext *s, DisasOps *o)
1379 {
1380 int r1 = get_field(s->fields, r1);
1381 int r3 = get_field(s->fields, r3);
1382 bool is_imm = have_field(s->fields, i2);
1383 int imm = is_imm ? get_field(s->fields, i2) : 0;
1384 DisasCompare c;
1385 TCGv_i64 t;
1386
1387 c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT);
1388 c.is_64 = false;
1389 c.g1 = false;
1390 c.g2 = false;
1391
1392 t = tcg_temp_new_i64();
1393 tcg_gen_add_i64(t, regs[r1], regs[r3]);
1394 c.u.s32.a = tcg_temp_new_i32();
1395 c.u.s32.b = tcg_temp_new_i32();
1396 tcg_gen_trunc_i64_i32(c.u.s32.a, t);
1397 tcg_gen_trunc_i64_i32(c.u.s32.b, regs[r3 | 1]);
1398 store_reg32_i64(r1, t);
1399 tcg_temp_free_i64(t);
1400
1401 return help_branch(s, &c, is_imm, imm, o->in2);
1402 }
1403
1404 static ExitStatus op_bx64(DisasContext *s, DisasOps *o)
1405 {
1406 int r1 = get_field(s->fields, r1);
1407 int r3 = get_field(s->fields, r3);
1408 bool is_imm = have_field(s->fields, i2);
1409 int imm = is_imm ? get_field(s->fields, i2) : 0;
1410 DisasCompare c;
1411
1412 c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT);
1413 c.is_64 = true;
1414
1415 if (r1 == (r3 | 1)) {
1416 c.u.s64.b = load_reg(r3 | 1);
1417 c.g2 = false;
1418 } else {
1419 c.u.s64.b = regs[r3 | 1];
1420 c.g2 = true;
1421 }
1422
1423 tcg_gen_add_i64(regs[r1], regs[r1], regs[r3]);
1424 c.u.s64.a = regs[r1];
1425 c.g1 = true;
1426
1427 return help_branch(s, &c, is_imm, imm, o->in2);
1428 }
1429
1430 static ExitStatus op_cj(DisasContext *s, DisasOps *o)
1431 {
1432 int imm, m3 = get_field(s->fields, m3);
1433 bool is_imm;
1434 DisasCompare c;
1435
1436 /* Bit 3 of the m3 field is reserved and should be zero.
1437 Choose to ignore it wrt the ltgt_cond table above. */
1438 c.cond = ltgt_cond[m3 & 14];
1439 if (s->insn->data) {
1440 c.cond = tcg_unsigned_cond(c.cond);
1441 }
1442 c.is_64 = c.g1 = c.g2 = true;
1443 c.u.s64.a = o->in1;
1444 c.u.s64.b = o->in2;
1445
1446 is_imm = have_field(s->fields, i4);
1447 if (is_imm) {
1448 imm = get_field(s->fields, i4);
1449 } else {
1450 imm = 0;
1451 o->out = get_address(s, 0, get_field(s->fields, b4),
1452 get_field(s->fields, d4));
1453 }
1454
1455 return help_branch(s, &c, is_imm, imm, o->out);
1456 }
1457
1458 static ExitStatus op_ceb(DisasContext *s, DisasOps *o)
1459 {
1460 gen_helper_ceb(cc_op, cpu_env, o->in1, o->in2);
1461 set_cc_static(s);
1462 return NO_EXIT;
1463 }
1464
1465 static ExitStatus op_cdb(DisasContext *s, DisasOps *o)
1466 {
1467 gen_helper_cdb(cc_op, cpu_env, o->in1, o->in2);
1468 set_cc_static(s);
1469 return NO_EXIT;
1470 }
1471
1472 static ExitStatus op_cxb(DisasContext *s, DisasOps *o)
1473 {
1474 gen_helper_cxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2);
1475 set_cc_static(s);
1476 return NO_EXIT;
1477 }
1478
1479 static ExitStatus op_cfeb(DisasContext *s, DisasOps *o)
1480 {
1481 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1482 gen_helper_cfeb(o->out, cpu_env, o->in2, m3);
1483 tcg_temp_free_i32(m3);
1484 gen_set_cc_nz_f32(s, o->in2);
1485 return NO_EXIT;
1486 }
1487
1488 static ExitStatus op_cfdb(DisasContext *s, DisasOps *o)
1489 {
1490 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1491 gen_helper_cfdb(o->out, cpu_env, o->in2, m3);
1492 tcg_temp_free_i32(m3);
1493 gen_set_cc_nz_f64(s, o->in2);
1494 return NO_EXIT;
1495 }
1496
1497 static ExitStatus op_cfxb(DisasContext *s, DisasOps *o)
1498 {
1499 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1500 gen_helper_cfxb(o->out, cpu_env, o->in1, o->in2, m3);
1501 tcg_temp_free_i32(m3);
1502 gen_set_cc_nz_f128(s, o->in1, o->in2);
1503 return NO_EXIT;
1504 }
1505
1506 static ExitStatus op_cgeb(DisasContext *s, DisasOps *o)
1507 {
1508 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1509 gen_helper_cgeb(o->out, cpu_env, o->in2, m3);
1510 tcg_temp_free_i32(m3);
1511 gen_set_cc_nz_f32(s, o->in2);
1512 return NO_EXIT;
1513 }
1514
1515 static ExitStatus op_cgdb(DisasContext *s, DisasOps *o)
1516 {
1517 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1518 gen_helper_cgdb(o->out, cpu_env, o->in2, m3);
1519 tcg_temp_free_i32(m3);
1520 gen_set_cc_nz_f64(s, o->in2);
1521 return NO_EXIT;
1522 }
1523
1524 static ExitStatus op_cgxb(DisasContext *s, DisasOps *o)
1525 {
1526 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1527 gen_helper_cgxb(o->out, cpu_env, o->in1, o->in2, m3);
1528 tcg_temp_free_i32(m3);
1529 gen_set_cc_nz_f128(s, o->in1, o->in2);
1530 return NO_EXIT;
1531 }
1532
1533 static ExitStatus op_cegb(DisasContext *s, DisasOps *o)
1534 {
1535 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1536 gen_helper_cegb(o->out, cpu_env, o->in2, m3);
1537 tcg_temp_free_i32(m3);
1538 return NO_EXIT;
1539 }
1540
1541 static ExitStatus op_cdgb(DisasContext *s, DisasOps *o)
1542 {
1543 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1544 gen_helper_cdgb(o->out, cpu_env, o->in2, m3);
1545 tcg_temp_free_i32(m3);
1546 return NO_EXIT;
1547 }
1548
1549 static ExitStatus op_cxgb(DisasContext *s, DisasOps *o)
1550 {
1551 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1552 gen_helper_cxgb(o->out, cpu_env, o->in2, m3);
1553 tcg_temp_free_i32(m3);
1554 return_low128(o->out2);
1555 return NO_EXIT;
1556 }
1557
1558 static ExitStatus op_cksm(DisasContext *s, DisasOps *o)
1559 {
1560 int r2 = get_field(s->fields, r2);
1561 TCGv_i64 len = tcg_temp_new_i64();
1562
1563 potential_page_fault(s);
1564 gen_helper_cksm(len, cpu_env, o->in1, o->in2, regs[r2 + 1]);
1565 set_cc_static(s);
1566 return_low128(o->out);
1567
1568 tcg_gen_add_i64(regs[r2], regs[r2], len);
1569 tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len);
1570 tcg_temp_free_i64(len);
1571
1572 return NO_EXIT;
1573 }
1574
1575 static ExitStatus op_clc(DisasContext *s, DisasOps *o)
1576 {
1577 int l = get_field(s->fields, l1);
1578 TCGv_i32 vl;
1579
1580 switch (l + 1) {
1581 case 1:
1582 tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s));
1583 tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s));
1584 break;
1585 case 2:
1586 tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s));
1587 tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s));
1588 break;
1589 case 4:
1590 tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s));
1591 tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s));
1592 break;
1593 case 8:
1594 tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s));
1595 tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s));
1596 break;
1597 default:
1598 potential_page_fault(s);
1599 vl = tcg_const_i32(l);
1600 gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
1601 tcg_temp_free_i32(vl);
1602 set_cc_static(s);
1603 return NO_EXIT;
1604 }
1605 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
1606 return NO_EXIT;
1607 }
1608
1609 static ExitStatus op_clcle(DisasContext *s, DisasOps *o)
1610 {
1611 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
1612 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
1613 potential_page_fault(s);
1614 gen_helper_clcle(cc_op, cpu_env, r1, o->in2, r3);
1615 tcg_temp_free_i32(r1);
1616 tcg_temp_free_i32(r3);
1617 set_cc_static(s);
1618 return NO_EXIT;
1619 }
1620
1621 static ExitStatus op_clm(DisasContext *s, DisasOps *o)
1622 {
1623 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1624 TCGv_i32 t1 = tcg_temp_new_i32();
1625 tcg_gen_trunc_i64_i32(t1, o->in1);
1626 potential_page_fault(s);
1627 gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2);
1628 set_cc_static(s);
1629 tcg_temp_free_i32(t1);
1630 tcg_temp_free_i32(m3);
1631 return NO_EXIT;
1632 }
1633
1634 static ExitStatus op_clst(DisasContext *s, DisasOps *o)
1635 {
1636 potential_page_fault(s);
1637 gen_helper_clst(o->in1, cpu_env, regs[0], o->in1, o->in2);
1638 set_cc_static(s);
1639 return_low128(o->in2);
1640 return NO_EXIT;
1641 }
1642
1643 static ExitStatus op_cs(DisasContext *s, DisasOps *o)
1644 {
1645 int r3 = get_field(s->fields, r3);
1646 potential_page_fault(s);
1647 gen_helper_cs(o->out, cpu_env, o->in1, o->in2, regs[r3]);
1648 set_cc_static(s);
1649 return NO_EXIT;
1650 }
1651
1652 static ExitStatus op_csg(DisasContext *s, DisasOps *o)
1653 {
1654 int r3 = get_field(s->fields, r3);
1655 potential_page_fault(s);
1656 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, regs[r3]);
1657 set_cc_static(s);
1658 return NO_EXIT;
1659 }
1660
1661 #ifndef CONFIG_USER_ONLY
1662 static ExitStatus op_csp(DisasContext *s, DisasOps *o)
1663 {
1664 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
1665 check_privileged(s);
1666 gen_helper_csp(cc_op, cpu_env, r1, o->in2);
1667 tcg_temp_free_i32(r1);
1668 set_cc_static(s);
1669 return NO_EXIT;
1670 }
1671 #endif
1672
1673 static ExitStatus op_cds(DisasContext *s, DisasOps *o)
1674 {
1675 int r3 = get_field(s->fields, r3);
1676 TCGv_i64 in3 = tcg_temp_new_i64();
1677 tcg_gen_deposit_i64(in3, regs[r3 + 1], regs[r3], 32, 32);
1678 potential_page_fault(s);
1679 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, in3);
1680 tcg_temp_free_i64(in3);
1681 set_cc_static(s);
1682 return NO_EXIT;
1683 }
1684
1685 static ExitStatus op_cdsg(DisasContext *s, DisasOps *o)
1686 {
1687 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
1688 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
1689 potential_page_fault(s);
1690 /* XXX rewrite in tcg */
1691 gen_helper_cdsg(cc_op, cpu_env, r1, o->in2, r3);
1692 set_cc_static(s);
1693 return NO_EXIT;
1694 }
1695
1696 static ExitStatus op_cvd(DisasContext *s, DisasOps *o)
1697 {
1698 TCGv_i64 t1 = tcg_temp_new_i64();
1699 TCGv_i32 t2 = tcg_temp_new_i32();
1700 tcg_gen_trunc_i64_i32(t2, o->in1);
1701 gen_helper_cvd(t1, t2);
1702 tcg_temp_free_i32(t2);
1703 tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
1704 tcg_temp_free_i64(t1);
1705 return NO_EXIT;
1706 }
1707
1708 static ExitStatus op_ct(DisasContext *s, DisasOps *o)
1709 {
1710 int m3 = get_field(s->fields, m3);
1711 int lab = gen_new_label();
1712 TCGv_i32 t;
1713 TCGCond c;
1714
1715 /* Bit 3 of the m3 field is reserved and should be zero.
1716 Choose to ignore it wrt the ltgt_cond table above. */
1717 c = tcg_invert_cond(ltgt_cond[m3 & 14]);
1718 if (s->insn->data) {
1719 c = tcg_unsigned_cond(c);
1720 }
1721 tcg_gen_brcond_i64(c, o->in1, o->in2, lab);
1722
1723 /* Set DXC to 0xff. */
1724 t = tcg_temp_new_i32();
1725 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUS390XState, fpc));
1726 tcg_gen_ori_i32(t, t, 0xff00);
1727 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, fpc));
1728 tcg_temp_free_i32(t);
1729
1730 /* Trap. */
1731 gen_program_exception(s, PGM_DATA);
1732
1733 gen_set_label(lab);
1734 return NO_EXIT;
1735 }
1736
1737 #ifndef CONFIG_USER_ONLY
1738 static ExitStatus op_diag(DisasContext *s, DisasOps *o)
1739 {
1740 TCGv_i32 tmp;
1741
1742 check_privileged(s);
1743 potential_page_fault(s);
1744
1745 /* We pretend the format is RX_a so that D2 is the field we want. */
1746 tmp = tcg_const_i32(get_field(s->fields, d2) & 0xfff);
1747 gen_helper_diag(regs[2], cpu_env, tmp, regs[2], regs[1]);
1748 tcg_temp_free_i32(tmp);
1749 return NO_EXIT;
1750 }
1751 #endif
1752
1753 static ExitStatus op_divs32(DisasContext *s, DisasOps *o)
1754 {
1755 gen_helper_divs32(o->out2, cpu_env, o->in1, o->in2);
1756 return_low128(o->out);
1757 return NO_EXIT;
1758 }
1759
1760 static ExitStatus op_divu32(DisasContext *s, DisasOps *o)
1761 {
1762 gen_helper_divu32(o->out2, cpu_env, o->in1, o->in2);
1763 return_low128(o->out);
1764 return NO_EXIT;
1765 }
1766
1767 static ExitStatus op_divs64(DisasContext *s, DisasOps *o)
1768 {
1769 gen_helper_divs64(o->out2, cpu_env, o->in1, o->in2);
1770 return_low128(o->out);
1771 return NO_EXIT;
1772 }
1773
1774 static ExitStatus op_divu64(DisasContext *s, DisasOps *o)
1775 {
1776 gen_helper_divu64(o->out2, cpu_env, o->out, o->out2, o->in2);
1777 return_low128(o->out);
1778 return NO_EXIT;
1779 }
1780
1781 static ExitStatus op_deb(DisasContext *s, DisasOps *o)
1782 {
1783 gen_helper_deb(o->out, cpu_env, o->in1, o->in2);
1784 return NO_EXIT;
1785 }
1786
1787 static ExitStatus op_ddb(DisasContext *s, DisasOps *o)
1788 {
1789 gen_helper_ddb(o->out, cpu_env, o->in1, o->in2);
1790 return NO_EXIT;
1791 }
1792
1793 static ExitStatus op_dxb(DisasContext *s, DisasOps *o)
1794 {
1795 gen_helper_dxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
1796 return_low128(o->out2);
1797 return NO_EXIT;
1798 }
1799
1800 static ExitStatus op_ear(DisasContext *s, DisasOps *o)
1801 {
1802 int r2 = get_field(s->fields, r2);
1803 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, aregs[r2]));
1804 return NO_EXIT;
1805 }
1806
1807 static ExitStatus op_efpc(DisasContext *s, DisasOps *o)
1808 {
1809 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, fpc));
1810 return NO_EXIT;
1811 }
1812
1813 static ExitStatus op_ex(DisasContext *s, DisasOps *o)
1814 {
1815 /* ??? Perhaps a better way to implement EXECUTE is to set a bit in
1816 tb->flags, (ab)use the tb->cs_base field as the address of
1817 the template in memory, and grab 8 bits of tb->flags/cflags for
1818 the contents of the register. We would then recognize all this
1819 in gen_intermediate_code_internal, generating code for exactly
1820 one instruction. This new TB then gets executed normally.
1821
1822 On the other hand, this seems to be mostly used for modifying
1823 MVC inside of memcpy, which needs a helper call anyway. So
1824 perhaps this doesn't bear thinking about any further. */
1825
1826 TCGv_i64 tmp;
1827
1828 update_psw_addr(s);
1829 update_cc_op(s);
1830
1831 tmp = tcg_const_i64(s->next_pc);
1832 gen_helper_ex(cc_op, cpu_env, cc_op, o->in1, o->in2, tmp);
1833 tcg_temp_free_i64(tmp);
1834
1835 set_cc_static(s);
1836 return NO_EXIT;
1837 }
1838
1839 static ExitStatus op_flogr(DisasContext *s, DisasOps *o)
1840 {
1841 /* We'll use the original input for cc computation, since we get to
1842 compare that against 0, which ought to be better than comparing
1843 the real output against 64. It also lets cc_dst be a convenient
1844 temporary during our computation. */
1845 gen_op_update1_cc_i64(s, CC_OP_FLOGR, o->in2);
1846
1847 /* R1 = IN ? CLZ(IN) : 64. */
1848 gen_helper_clz(o->out, o->in2);
1849
1850 /* R1+1 = IN & ~(found bit). Note that we may attempt to shift this
1851 value by 64, which is undefined. But since the shift is 64 iff the
1852 input is zero, we still get the correct result after and'ing. */
1853 tcg_gen_movi_i64(o->out2, 0x8000000000000000ull);
1854 tcg_gen_shr_i64(o->out2, o->out2, o->out);
1855 tcg_gen_andc_i64(o->out2, cc_dst, o->out2);
1856 return NO_EXIT;
1857 }
1858
1859 static ExitStatus op_icm(DisasContext *s, DisasOps *o)
1860 {
1861 int m3 = get_field(s->fields, m3);
1862 int pos, len, base = s->insn->data;
1863 TCGv_i64 tmp = tcg_temp_new_i64();
1864 uint64_t ccm;
1865
1866 switch (m3) {
1867 case 0xf:
1868 /* Effectively a 32-bit load. */
1869 tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s));
1870 len = 32;
1871 goto one_insert;
1872
1873 case 0xc:
1874 case 0x6:
1875 case 0x3:
1876 /* Effectively a 16-bit load. */
1877 tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s));
1878 len = 16;
1879 goto one_insert;
1880
1881 case 0x8:
1882 case 0x4:
1883 case 0x2:
1884 case 0x1:
1885 /* Effectively an 8-bit load. */
1886 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
1887 len = 8;
1888 goto one_insert;
1889
1890 one_insert:
1891 pos = base + ctz32(m3) * 8;
1892 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len);
1893 ccm = ((1ull << len) - 1) << pos;
1894 break;
1895
1896 default:
1897 /* This is going to be a sequence of loads and inserts. */
1898 pos = base + 32 - 8;
1899 ccm = 0;
1900 while (m3) {
1901 if (m3 & 0x8) {
1902 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
1903 tcg_gen_addi_i64(o->in2, o->in2, 1);
1904 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
1905 ccm |= 0xff << pos;
1906 }
1907 m3 = (m3 << 1) & 0xf;
1908 pos -= 8;
1909 }
1910 break;
1911 }
1912
1913 tcg_gen_movi_i64(tmp, ccm);
1914 gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out);
1915 tcg_temp_free_i64(tmp);
1916 return NO_EXIT;
1917 }
1918
1919 static ExitStatus op_insi(DisasContext *s, DisasOps *o)
1920 {
1921 int shift = s->insn->data & 0xff;
1922 int size = s->insn->data >> 8;
1923 tcg_gen_deposit_i64(o->out, o->in1, o->in2, shift, size);
1924 return NO_EXIT;
1925 }
1926
1927 static ExitStatus op_ipm(DisasContext *s, DisasOps *o)
1928 {
1929 TCGv_i64 t1;
1930
1931 gen_op_calc_cc(s);
1932 tcg_gen_andi_i64(o->out, o->out, ~0xff000000ull);
1933
1934 t1 = tcg_temp_new_i64();
1935 tcg_gen_shli_i64(t1, psw_mask, 20);
1936 tcg_gen_shri_i64(t1, t1, 36);
1937 tcg_gen_or_i64(o->out, o->out, t1);
1938
1939 tcg_gen_extu_i32_i64(t1, cc_op);
1940 tcg_gen_shli_i64(t1, t1, 28);
1941 tcg_gen_or_i64(o->out, o->out, t1);
1942 tcg_temp_free_i64(t1);
1943 return NO_EXIT;
1944 }
1945
1946 #ifndef CONFIG_USER_ONLY
1947 static ExitStatus op_ipte(DisasContext *s, DisasOps *o)
1948 {
1949 check_privileged(s);
1950 gen_helper_ipte(cpu_env, o->in1, o->in2);
1951 return NO_EXIT;
1952 }
1953
1954 static ExitStatus op_iske(DisasContext *s, DisasOps *o)
1955 {
1956 check_privileged(s);
1957 gen_helper_iske(o->out, cpu_env, o->in2);
1958 return NO_EXIT;
1959 }
1960 #endif
1961
1962 static ExitStatus op_ldeb(DisasContext *s, DisasOps *o)
1963 {
1964 gen_helper_ldeb(o->out, cpu_env, o->in2);
1965 return NO_EXIT;
1966 }
1967
1968 static ExitStatus op_ledb(DisasContext *s, DisasOps *o)
1969 {
1970 gen_helper_ledb(o->out, cpu_env, o->in2);
1971 return NO_EXIT;
1972 }
1973
1974 static ExitStatus op_ldxb(DisasContext *s, DisasOps *o)
1975 {
1976 gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2);
1977 return NO_EXIT;
1978 }
1979
1980 static ExitStatus op_lexb(DisasContext *s, DisasOps *o)
1981 {
1982 gen_helper_lexb(o->out, cpu_env, o->in1, o->in2);
1983 return NO_EXIT;
1984 }
1985
1986 static ExitStatus op_lxdb(DisasContext *s, DisasOps *o)
1987 {
1988 gen_helper_lxdb(o->out, cpu_env, o->in2);
1989 return_low128(o->out2);
1990 return NO_EXIT;
1991 }
1992
1993 static ExitStatus op_lxeb(DisasContext *s, DisasOps *o)
1994 {
1995 gen_helper_lxeb(o->out, cpu_env, o->in2);
1996 return_low128(o->out2);
1997 return NO_EXIT;
1998 }
1999
2000 static ExitStatus op_llgt(DisasContext *s, DisasOps *o)
2001 {
2002 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffff);
2003 return NO_EXIT;
2004 }
2005
2006 static ExitStatus op_ld8s(DisasContext *s, DisasOps *o)
2007 {
2008 tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
2009 return NO_EXIT;
2010 }
2011
2012 static ExitStatus op_ld8u(DisasContext *s, DisasOps *o)
2013 {
2014 tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
2015 return NO_EXIT;
2016 }
2017
2018 static ExitStatus op_ld16s(DisasContext *s, DisasOps *o)
2019 {
2020 tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
2021 return NO_EXIT;
2022 }
2023
2024 static ExitStatus op_ld16u(DisasContext *s, DisasOps *o)
2025 {
2026 tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
2027 return NO_EXIT;
2028 }
2029
2030 static ExitStatus op_ld32s(DisasContext *s, DisasOps *o)
2031 {
2032 tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s));
2033 return NO_EXIT;
2034 }
2035
2036 static ExitStatus op_ld32u(DisasContext *s, DisasOps *o)
2037 {
2038 tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
2039 return NO_EXIT;
2040 }
2041
2042 static ExitStatus op_ld64(DisasContext *s, DisasOps *o)
2043 {
2044 tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
2045 return NO_EXIT;
2046 }
2047
2048 static ExitStatus op_loc(DisasContext *s, DisasOps *o)
2049 {
2050 DisasCompare c;
2051
2052 disas_jcc(s, &c, get_field(s->fields, m3));
2053
2054 if (c.is_64) {
2055 tcg_gen_movcond_i64(c.cond, o->out, c.u.s64.a, c.u.s64.b,
2056 o->in2, o->in1);
2057 free_compare(&c);
2058 } else {
2059 TCGv_i32 t32 = tcg_temp_new_i32();
2060 TCGv_i64 t, z;
2061
2062 tcg_gen_setcond_i32(c.cond, t32, c.u.s32.a, c.u.s32.b);
2063 free_compare(&c);
2064
2065 t = tcg_temp_new_i64();
2066 tcg_gen_extu_i32_i64(t, t32);
2067 tcg_temp_free_i32(t32);
2068
2069 z = tcg_const_i64(0);
2070 tcg_gen_movcond_i64(TCG_COND_NE, o->out, t, z, o->in2, o->in1);
2071 tcg_temp_free_i64(t);
2072 tcg_temp_free_i64(z);
2073 }
2074
2075 return NO_EXIT;
2076 }
2077
2078 #ifndef CONFIG_USER_ONLY
2079 static ExitStatus op_lctl(DisasContext *s, DisasOps *o)
2080 {
2081 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2082 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2083 check_privileged(s);
2084 potential_page_fault(s);
2085 gen_helper_lctl(cpu_env, r1, o->in2, r3);
2086 tcg_temp_free_i32(r1);
2087 tcg_temp_free_i32(r3);
2088 return NO_EXIT;
2089 }
2090
2091 static ExitStatus op_lctlg(DisasContext *s, DisasOps *o)
2092 {
2093 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2094 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2095 check_privileged(s);
2096 potential_page_fault(s);
2097 gen_helper_lctlg(cpu_env, r1, o->in2, r3);
2098 tcg_temp_free_i32(r1);
2099 tcg_temp_free_i32(r3);
2100 return NO_EXIT;
2101 }
2102 static ExitStatus op_lra(DisasContext *s, DisasOps *o)
2103 {
2104 check_privileged(s);
2105 potential_page_fault(s);
2106 gen_helper_lra(o->out, cpu_env, o->in2);
2107 set_cc_static(s);
2108 return NO_EXIT;
2109 }
2110
2111 static ExitStatus op_lpsw(DisasContext *s, DisasOps *o)
2112 {
2113 TCGv_i64 t1, t2;
2114
2115 check_privileged(s);
2116
2117 t1 = tcg_temp_new_i64();
2118 t2 = tcg_temp_new_i64();
2119 tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
2120 tcg_gen_addi_i64(o->in2, o->in2, 4);
2121 tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s));
2122 /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
2123 tcg_gen_shli_i64(t1, t1, 32);
2124 gen_helper_load_psw(cpu_env, t1, t2);
2125 tcg_temp_free_i64(t1);
2126 tcg_temp_free_i64(t2);
2127 return EXIT_NORETURN;
2128 }
2129
2130 static ExitStatus op_lpswe(DisasContext *s, DisasOps *o)
2131 {
2132 TCGv_i64 t1, t2;
2133
2134 check_privileged(s);
2135
2136 t1 = tcg_temp_new_i64();
2137 t2 = tcg_temp_new_i64();
2138 tcg_gen_qemu_ld64(t1, o->in2, get_mem_index(s));
2139 tcg_gen_addi_i64(o->in2, o->in2, 8);
2140 tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s));
2141 gen_helper_load_psw(cpu_env, t1, t2);
2142 tcg_temp_free_i64(t1);
2143 tcg_temp_free_i64(t2);
2144 return EXIT_NORETURN;
2145 }
2146 #endif
2147
2148 static ExitStatus op_lam(DisasContext *s, DisasOps *o)
2149 {
2150 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2151 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2152 potential_page_fault(s);
2153 gen_helper_lam(cpu_env, r1, o->in2, r3);
2154 tcg_temp_free_i32(r1);
2155 tcg_temp_free_i32(r3);
2156 return NO_EXIT;
2157 }
2158
2159 static ExitStatus op_lm32(DisasContext *s, DisasOps *o)
2160 {
2161 int r1 = get_field(s->fields, r1);
2162 int r3 = get_field(s->fields, r3);
2163 TCGv_i64 t = tcg_temp_new_i64();
2164 TCGv_i64 t4 = tcg_const_i64(4);
2165
2166 while (1) {
2167 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2168 store_reg32_i64(r1, t);
2169 if (r1 == r3) {
2170 break;
2171 }
2172 tcg_gen_add_i64(o->in2, o->in2, t4);
2173 r1 = (r1 + 1) & 15;
2174 }
2175
2176 tcg_temp_free_i64(t);
2177 tcg_temp_free_i64(t4);
2178 return NO_EXIT;
2179 }
2180
2181 static ExitStatus op_lmh(DisasContext *s, DisasOps *o)
2182 {
2183 int r1 = get_field(s->fields, r1);
2184 int r3 = get_field(s->fields, r3);
2185 TCGv_i64 t = tcg_temp_new_i64();
2186 TCGv_i64 t4 = tcg_const_i64(4);
2187
2188 while (1) {
2189 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2190 store_reg32h_i64(r1, t);
2191 if (r1 == r3) {
2192 break;
2193 }
2194 tcg_gen_add_i64(o->in2, o->in2, t4);
2195 r1 = (r1 + 1) & 15;
2196 }
2197
2198 tcg_temp_free_i64(t);
2199 tcg_temp_free_i64(t4);
2200 return NO_EXIT;
2201 }
2202
2203 static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
2204 {
2205 int r1 = get_field(s->fields, r1);
2206 int r3 = get_field(s->fields, r3);
2207 TCGv_i64 t8 = tcg_const_i64(8);
2208
2209 while (1) {
2210 tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
2211 if (r1 == r3) {
2212 break;
2213 }
2214 tcg_gen_add_i64(o->in2, o->in2, t8);
2215 r1 = (r1 + 1) & 15;
2216 }
2217
2218 tcg_temp_free_i64(t8);
2219 return NO_EXIT;
2220 }
2221
2222 static ExitStatus op_mov2(DisasContext *s, DisasOps *o)
2223 {
2224 o->out = o->in2;
2225 o->g_out = o->g_in2;
2226 TCGV_UNUSED_I64(o->in2);
2227 o->g_in2 = false;
2228 return NO_EXIT;
2229 }
2230
2231 static ExitStatus op_movx(DisasContext *s, DisasOps *o)
2232 {
2233 o->out = o->in1;
2234 o->out2 = o->in2;
2235 o->g_out = o->g_in1;
2236 o->g_out2 = o->g_in2;
2237 TCGV_UNUSED_I64(o->in1);
2238 TCGV_UNUSED_I64(o->in2);
2239 o->g_in1 = o->g_in2 = false;
2240 return NO_EXIT;
2241 }
2242
2243 static ExitStatus op_mvc(DisasContext *s, DisasOps *o)
2244 {
2245 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2246 potential_page_fault(s);
2247 gen_helper_mvc(cpu_env, l, o->addr1, o->in2);
2248 tcg_temp_free_i32(l);
2249 return NO_EXIT;
2250 }
2251
2252 static ExitStatus op_mvcl(DisasContext *s, DisasOps *o)
2253 {
2254 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2255 TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
2256 potential_page_fault(s);
2257 gen_helper_mvcl(cc_op, cpu_env, r1, r2);
2258 tcg_temp_free_i32(r1);
2259 tcg_temp_free_i32(r2);
2260 set_cc_static(s);
2261 return NO_EXIT;
2262 }
2263
2264 static ExitStatus op_mvcle(DisasContext *s, DisasOps *o)
2265 {
2266 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2267 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2268 potential_page_fault(s);
2269 gen_helper_mvcle(cc_op, cpu_env, r1, o->in2, r3);
2270 tcg_temp_free_i32(r1);
2271 tcg_temp_free_i32(r3);
2272 set_cc_static(s);
2273 return NO_EXIT;
2274 }
2275
2276 #ifndef CONFIG_USER_ONLY
2277 static ExitStatus op_mvcp(DisasContext *s, DisasOps *o)
2278 {
2279 int r1 = get_field(s->fields, l1);
2280 check_privileged(s);
2281 potential_page_fault(s);
2282 gen_helper_mvcp(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2283 set_cc_static(s);
2284 return NO_EXIT;
2285 }
2286
2287 static ExitStatus op_mvcs(DisasContext *s, DisasOps *o)
2288 {
2289 int r1 = get_field(s->fields, l1);
2290 check_privileged(s);
2291 potential_page_fault(s);
2292 gen_helper_mvcs(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2293 set_cc_static(s);
2294 return NO_EXIT;
2295 }
2296 #endif
2297
2298 static ExitStatus op_mvpg(DisasContext *s, DisasOps *o)
2299 {
2300 potential_page_fault(s);
2301 gen_helper_mvpg(cpu_env, regs[0], o->in1, o->in2);
2302 set_cc_static(s);
2303 return NO_EXIT;
2304 }
2305
2306 static ExitStatus op_mvst(DisasContext *s, DisasOps *o)
2307 {
2308 potential_page_fault(s);
2309 gen_helper_mvst(o->in1, cpu_env, regs[0], o->in1, o->in2);
2310 set_cc_static(s);
2311 return_low128(o->in2);
2312 return NO_EXIT;
2313 }
2314
2315 static ExitStatus op_mul(DisasContext *s, DisasOps *o)
2316 {
2317 tcg_gen_mul_i64(o->out, o->in1, o->in2);
2318 return NO_EXIT;
2319 }
2320
2321 static ExitStatus op_mul128(DisasContext *s, DisasOps *o)
2322 {
2323 gen_helper_mul128(o->out, cpu_env, o->in1, o->in2);
2324 return_low128(o->out2);
2325 return NO_EXIT;
2326 }
2327
2328 static ExitStatus op_meeb(DisasContext *s, DisasOps *o)
2329 {
2330 gen_helper_meeb(o->out, cpu_env, o->in1, o->in2);
2331 return NO_EXIT;
2332 }
2333
2334 static ExitStatus op_mdeb(DisasContext *s, DisasOps *o)
2335 {
2336 gen_helper_mdeb(o->out, cpu_env, o->in1, o->in2);
2337 return NO_EXIT;
2338 }
2339
2340 static ExitStatus op_mdb(DisasContext *s, DisasOps *o)
2341 {
2342 gen_helper_mdb(o->out, cpu_env, o->in1, o->in2);
2343 return NO_EXIT;
2344 }
2345
2346 static ExitStatus op_mxb(DisasContext *s, DisasOps *o)
2347 {
2348 gen_helper_mxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2349 return_low128(o->out2);
2350 return NO_EXIT;
2351 }
2352
2353 static ExitStatus op_mxdb(DisasContext *s, DisasOps *o)
2354 {
2355 gen_helper_mxdb(o->out, cpu_env, o->out, o->out2, o->in2);
2356 return_low128(o->out2);
2357 return NO_EXIT;
2358 }
2359
2360 static ExitStatus op_maeb(DisasContext *s, DisasOps *o)
2361 {
2362 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2363 gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3);
2364 tcg_temp_free_i64(r3);
2365 return NO_EXIT;
2366 }
2367
2368 static ExitStatus op_madb(DisasContext *s, DisasOps *o)
2369 {
2370 int r3 = get_field(s->fields, r3);
2371 gen_helper_madb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2372 return NO_EXIT;
2373 }
2374
2375 static ExitStatus op_mseb(DisasContext *s, DisasOps *o)
2376 {
2377 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2378 gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3);
2379 tcg_temp_free_i64(r3);
2380 return NO_EXIT;
2381 }
2382
2383 static ExitStatus op_msdb(DisasContext *s, DisasOps *o)
2384 {
2385 int r3 = get_field(s->fields, r3);
2386 gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2387 return NO_EXIT;
2388 }
2389
2390 static ExitStatus op_nabs(DisasContext *s, DisasOps *o)
2391 {
2392 gen_helper_nabs_i64(o->out, o->in2);
2393 return NO_EXIT;
2394 }
2395
2396 static ExitStatus op_nabsf32(DisasContext *s, DisasOps *o)
2397 {
2398 tcg_gen_ori_i64(o->out, o->in2, 0x80000000ull);
2399 return NO_EXIT;
2400 }
2401
2402 static ExitStatus op_nabsf64(DisasContext *s, DisasOps *o)
2403 {
2404 tcg_gen_ori_i64(o->out, o->in2, 0x8000000000000000ull);
2405 return NO_EXIT;
2406 }
2407
2408 static ExitStatus op_nabsf128(DisasContext *s, DisasOps *o)
2409 {
2410 tcg_gen_ori_i64(o->out, o->in1, 0x8000000000000000ull);
2411 tcg_gen_mov_i64(o->out2, o->in2);
2412 return NO_EXIT;
2413 }
2414
2415 static ExitStatus op_nc(DisasContext *s, DisasOps *o)
2416 {
2417 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2418 potential_page_fault(s);
2419 gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2);
2420 tcg_temp_free_i32(l);
2421 set_cc_static(s);
2422 return NO_EXIT;
2423 }
2424
2425 static ExitStatus op_neg(DisasContext *s, DisasOps *o)
2426 {
2427 tcg_gen_neg_i64(o->out, o->in2);
2428 return NO_EXIT;
2429 }
2430
2431 static ExitStatus op_negf32(DisasContext *s, DisasOps *o)
2432 {
2433 tcg_gen_xori_i64(o->out, o->in2, 0x80000000ull);
2434 return NO_EXIT;
2435 }
2436
2437 static ExitStatus op_negf64(DisasContext *s, DisasOps *o)
2438 {
2439 tcg_gen_xori_i64(o->out, o->in2, 0x8000000000000000ull);
2440 return NO_EXIT;
2441 }
2442
2443 static ExitStatus op_negf128(DisasContext *s, DisasOps *o)
2444 {
2445 tcg_gen_xori_i64(o->out, o->in1, 0x8000000000000000ull);
2446 tcg_gen_mov_i64(o->out2, o->in2);
2447 return NO_EXIT;
2448 }
2449
2450 static ExitStatus op_oc(DisasContext *s, DisasOps *o)
2451 {
2452 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2453 potential_page_fault(s);
2454 gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2);
2455 tcg_temp_free_i32(l);
2456 set_cc_static(s);
2457 return NO_EXIT;
2458 }
2459
2460 static ExitStatus op_or(DisasContext *s, DisasOps *o)
2461 {
2462 tcg_gen_or_i64(o->out, o->in1, o->in2);
2463 return NO_EXIT;
2464 }
2465
2466 static ExitStatus op_ori(DisasContext *s, DisasOps *o)
2467 {
2468 int shift = s->insn->data & 0xff;
2469 int size = s->insn->data >> 8;
2470 uint64_t mask = ((1ull << size) - 1) << shift;
2471
2472 assert(!o->g_in2);
2473 tcg_gen_shli_i64(o->in2, o->in2, shift);
2474 tcg_gen_or_i64(o->out, o->in1, o->in2);
2475
2476 /* Produce the CC from only the bits manipulated. */
2477 tcg_gen_andi_i64(cc_dst, o->out, mask);
2478 set_cc_nz_u64(s, cc_dst);
2479 return NO_EXIT;
2480 }
2481
2482 #ifndef CONFIG_USER_ONLY
2483 static ExitStatus op_ptlb(DisasContext *s, DisasOps *o)
2484 {
2485 check_privileged(s);
2486 gen_helper_ptlb(cpu_env);
2487 return NO_EXIT;
2488 }
2489 #endif
2490
2491 static ExitStatus op_risbg(DisasContext *s, DisasOps *o)
2492 {
2493 int i3 = get_field(s->fields, i3);
2494 int i4 = get_field(s->fields, i4);
2495 int i5 = get_field(s->fields, i5);
2496 int do_zero = i4 & 0x80;
2497 uint64_t mask, imask, pmask;
2498 int pos, len, rot;
2499
2500 /* Adjust the arguments for the specific insn. */
2501 switch (s->fields->op2) {
2502 case 0x55: /* risbg */
2503 i3 &= 63;
2504 i4 &= 63;
2505 pmask = ~0;
2506 break;
2507 case 0x5d: /* risbhg */
2508 i3 &= 31;
2509 i4 &= 31;
2510 pmask = 0xffffffff00000000ull;
2511 break;
2512 case 0x51: /* risblg */
2513 i3 &= 31;
2514 i4 &= 31;
2515 pmask = 0x00000000ffffffffull;
2516 break;
2517 default:
2518 abort();
2519 }
2520
2521 /* MASK is the set of bits to be inserted from R2.
2522 Take care for I3/I4 wraparound. */
2523 mask = pmask >> i3;
2524 if (i3 <= i4) {
2525 mask ^= pmask >> i4 >> 1;
2526 } else {
2527 mask |= ~(pmask >> i4 >> 1);
2528 }
2529 mask &= pmask;
2530
2531 /* IMASK is the set of bits to be kept from R1. In the case of the high/low
2532 insns, we need to keep the other half of the register. */
2533 imask = ~mask | ~pmask;
2534 if (do_zero) {
2535 if (s->fields->op2 == 0x55) {
2536 imask = 0;
2537 } else {
2538 imask = ~pmask;
2539 }
2540 }
2541
2542 /* In some cases we can implement this with deposit, which can be more
2543 efficient on some hosts. */
2544 if (~mask == imask && i3 <= i4) {
2545 if (s->fields->op2 == 0x5d) {
2546 i3 += 32, i4 += 32;
2547 }
2548 /* Note that we rotate the bits to be inserted to the lsb, not to
2549 the position as described in the PoO. */
2550 len = i4 - i3 + 1;
2551 pos = 63 - i4;
2552 rot = (i5 - pos) & 63;
2553 } else {
2554 pos = len = -1;
2555 rot = i5 & 63;
2556 }
2557
2558 /* Rotate the input as necessary. */
2559 tcg_gen_rotli_i64(o->in2, o->in2, rot);
2560
2561 /* Insert the selected bits into the output. */
2562 if (pos >= 0) {
2563 tcg_gen_deposit_i64(o->out, o->out, o->in2, pos, len);
2564 } else if (imask == 0) {
2565 tcg_gen_andi_i64(o->out, o->in2, mask);
2566 } else {
2567 tcg_gen_andi_i64(o->in2, o->in2, mask);
2568 tcg_gen_andi_i64(o->out, o->out, imask);
2569 tcg_gen_or_i64(o->out, o->out, o->in2);
2570 }
2571 return NO_EXIT;
2572 }
2573
2574 static ExitStatus op_rosbg(DisasContext *s, DisasOps *o)
2575 {
2576 int i3 = get_field(s->fields, i3);
2577 int i4 = get_field(s->fields, i4);
2578 int i5 = get_field(s->fields, i5);
2579 uint64_t mask;
2580
2581 /* If this is a test-only form, arrange to discard the result. */
2582 if (i3 & 0x80) {
2583 o->out = tcg_temp_new_i64();
2584 o->g_out = false;
2585 }
2586
2587 i3 &= 63;
2588 i4 &= 63;
2589 i5 &= 63;
2590
2591 /* MASK is the set of bits to be operated on from R2.
2592 Take care for I3/I4 wraparound. */
2593 mask = ~0ull >> i3;
2594 if (i3 <= i4) {
2595 mask ^= ~0ull >> i4 >> 1;
2596 } else {
2597 mask |= ~(~0ull >> i4 >> 1);
2598 }
2599
2600 /* Rotate the input as necessary. */
2601 tcg_gen_rotli_i64(o->in2, o->in2, i5);
2602
2603 /* Operate. */
2604 switch (s->fields->op2) {
2605 case 0x55: /* AND */
2606 tcg_gen_ori_i64(o->in2, o->in2, ~mask);
2607 tcg_gen_and_i64(o->out, o->out, o->in2);
2608 break;
2609 case 0x56: /* OR */
2610 tcg_gen_andi_i64(o->in2, o->in2, mask);
2611 tcg_gen_or_i64(o->out, o->out, o->in2);
2612 break;
2613 case 0x57: /* XOR */
2614 tcg_gen_andi_i64(o->in2, o->in2, mask);
2615 tcg_gen_xor_i64(o->out, o->out, o->in2);
2616 break;
2617 default:
2618 abort();
2619 }
2620
2621 /* Set the CC. */
2622 tcg_gen_andi_i64(cc_dst, o->out, mask);
2623 set_cc_nz_u64(s, cc_dst);
2624 return NO_EXIT;
2625 }
2626
2627 static ExitStatus op_rev16(DisasContext *s, DisasOps *o)
2628 {
2629 tcg_gen_bswap16_i64(o->out, o->in2);
2630 return NO_EXIT;
2631 }
2632
2633 static ExitStatus op_rev32(DisasContext *s, DisasOps *o)
2634 {
2635 tcg_gen_bswap32_i64(o->out, o->in2);
2636 return NO_EXIT;
2637 }
2638
2639 static ExitStatus op_rev64(DisasContext *s, DisasOps *o)
2640 {
2641 tcg_gen_bswap64_i64(o->out, o->in2);
2642 return NO_EXIT;
2643 }
2644
2645 static ExitStatus op_rll32(DisasContext *s, DisasOps *o)
2646 {
2647 TCGv_i32 t1 = tcg_temp_new_i32();
2648 TCGv_i32 t2 = tcg_temp_new_i32();
2649 TCGv_i32 to = tcg_temp_new_i32();
2650 tcg_gen_trunc_i64_i32(t1, o->in1);
2651 tcg_gen_trunc_i64_i32(t2, o->in2);
2652 tcg_gen_rotl_i32(to, t1, t2);
2653 tcg_gen_extu_i32_i64(o->out, to);
2654 tcg_temp_free_i32(t1);
2655 tcg_temp_free_i32(t2);
2656 tcg_temp_free_i32(to);
2657 return NO_EXIT;
2658 }
2659
2660 static ExitStatus op_rll64(DisasContext *s, DisasOps *o)
2661 {
2662 tcg_gen_rotl_i64(o->out, o->in1, o->in2);
2663 return NO_EXIT;
2664 }
2665
2666 #ifndef CONFIG_USER_ONLY
2667 static ExitStatus op_rrbe(DisasContext *s, DisasOps *o)
2668 {
2669 check_privileged(s);
2670 gen_helper_rrbe(cc_op, cpu_env, o->in2);
2671 set_cc_static(s);
2672 return NO_EXIT;
2673 }
2674
2675 static ExitStatus op_sacf(DisasContext *s, DisasOps *o)
2676 {
2677 check_privileged(s);
2678 gen_helper_sacf(cpu_env, o->in2);
2679 /* Addressing mode has changed, so end the block. */
2680 return EXIT_PC_STALE;
2681 }
2682 #endif
2683
2684 static ExitStatus op_sar(DisasContext *s, DisasOps *o)
2685 {
2686 int r1 = get_field(s->fields, r1);
2687 tcg_gen_st32_i64(o->in2, cpu_env, offsetof(CPUS390XState, aregs[r1]));
2688 return NO_EXIT;
2689 }
2690
2691 static ExitStatus op_seb(DisasContext *s, DisasOps *o)
2692 {
2693 gen_helper_seb(o->out, cpu_env, o->in1, o->in2);
2694 return NO_EXIT;
2695 }
2696
2697 static ExitStatus op_sdb(DisasContext *s, DisasOps *o)
2698 {
2699 gen_helper_sdb(o->out, cpu_env, o->in1, o->in2);
2700 return NO_EXIT;
2701 }
2702
2703 static ExitStatus op_sxb(DisasContext *s, DisasOps *o)
2704 {
2705 gen_helper_sxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2706 return_low128(o->out2);
2707 return NO_EXIT;
2708 }
2709
2710 static ExitStatus op_sqeb(DisasContext *s, DisasOps *o)
2711 {
2712 gen_helper_sqeb(o->out, cpu_env, o->in2);
2713 return NO_EXIT;
2714 }
2715
2716 static ExitStatus op_sqdb(DisasContext *s, DisasOps *o)
2717 {
2718 gen_helper_sqdb(o->out, cpu_env, o->in2);
2719 return NO_EXIT;
2720 }
2721
2722 static ExitStatus op_sqxb(DisasContext *s, DisasOps *o)
2723 {
2724 gen_helper_sqxb(o->out, cpu_env, o->in1, o->in2);
2725 return_low128(o->out2);
2726 return NO_EXIT;
2727 }
2728
2729 #ifndef CONFIG_USER_ONLY
2730 static ExitStatus op_servc(DisasContext *s, DisasOps *o)
2731 {
2732 check_privileged(s);
2733 potential_page_fault(s);
2734 gen_helper_servc(cc_op, cpu_env, o->in2, o->in1);
2735 set_cc_static(s);
2736 return NO_EXIT;
2737 }
2738
2739 static ExitStatus op_sigp(DisasContext *s, DisasOps *o)
2740 {
2741 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2742 check_privileged(s);
2743 potential_page_fault(s);
2744 gen_helper_sigp(cc_op, cpu_env, o->in2, r1, o->in1);
2745 tcg_temp_free_i32(r1);
2746 return NO_EXIT;
2747 }
2748 #endif
2749
2750 static ExitStatus op_soc(DisasContext *s, DisasOps *o)
2751 {
2752 DisasCompare c;
2753 TCGv_i64 a;
2754 int lab, r1;
2755
2756 disas_jcc(s, &c, get_field(s->fields, m3));
2757
2758 lab = gen_new_label();
2759 if (c.is_64) {
2760 tcg_gen_brcond_i64(c.cond, c.u.s64.a, c.u.s64.b, lab);
2761 } else {
2762 tcg_gen_brcond_i32(c.cond, c.u.s32.a, c.u.s32.b, lab);
2763 }
2764 free_compare(&c);
2765
2766 r1 = get_field(s->fields, r1);
2767 a = get_address(s, 0, get_field(s->fields, b2), get_field(s->fields, d2));
2768 if (s->insn->data) {
2769 tcg_gen_qemu_st64(regs[r1], a, get_mem_index(s));
2770 } else {
2771 tcg_gen_qemu_st32(regs[r1], a, get_mem_index(s));
2772 }
2773 tcg_temp_free_i64(a);
2774
2775 gen_set_label(lab);
2776 return NO_EXIT;
2777 }
2778
2779 static ExitStatus op_sla(DisasContext *s, DisasOps *o)
2780 {
2781 uint64_t sign = 1ull << s->insn->data;
2782 enum cc_op cco = s->insn->data == 31 ? CC_OP_SLA_32 : CC_OP_SLA_64;
2783 gen_op_update2_cc_i64(s, cco, o->in1, o->in2);
2784 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2785 /* The arithmetic left shift is curious in that it does not affect
2786 the sign bit. Copy that over from the source unchanged. */
2787 tcg_gen_andi_i64(o->out, o->out, ~sign);
2788 tcg_gen_andi_i64(o->in1, o->in1, sign);
2789 tcg_gen_or_i64(o->out, o->out, o->in1);
2790 return NO_EXIT;
2791 }
2792
2793 static ExitStatus op_sll(DisasContext *s, DisasOps *o)
2794 {
2795 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2796 return NO_EXIT;
2797 }
2798
2799 static ExitStatus op_sra(DisasContext *s, DisasOps *o)
2800 {
2801 tcg_gen_sar_i64(o->out, o->in1, o->in2);
2802 return NO_EXIT;
2803 }
2804
2805 static ExitStatus op_srl(DisasContext *s, DisasOps *o)
2806 {
2807 tcg_gen_shr_i64(o->out, o->in1, o->in2);
2808 return NO_EXIT;
2809 }
2810
2811 static ExitStatus op_sfpc(DisasContext *s, DisasOps *o)
2812 {
2813 gen_helper_sfpc(cpu_env, o->in2);
2814 return NO_EXIT;
2815 }
2816
2817 #ifndef CONFIG_USER_ONLY
2818 static ExitStatus op_spka(DisasContext *s, DisasOps *o)
2819 {
2820 check_privileged(s);
2821 tcg_gen_shri_i64(o->in2, o->in2, 4);
2822 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, PSW_SHIFT_KEY - 4, 4);
2823 return NO_EXIT;
2824 }
2825
2826 static ExitStatus op_sske(DisasContext *s, DisasOps *o)
2827 {
2828 check_privileged(s);
2829 gen_helper_sske(cpu_env, o->in1, o->in2);
2830 return NO_EXIT;
2831 }
2832
2833 static ExitStatus op_ssm(DisasContext *s, DisasOps *o)
2834 {
2835 check_privileged(s);
2836 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8);
2837 return NO_EXIT;
2838 }
2839
2840 static ExitStatus op_stap(DisasContext *s, DisasOps *o)
2841 {
2842 check_privileged(s);
2843 /* ??? Surely cpu address != cpu number. In any case the previous
2844 version of this stored more than the required half-word, so it
2845 is unlikely this has ever been tested. */
2846 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num));
2847 return NO_EXIT;
2848 }
2849
2850 static ExitStatus op_stck(DisasContext *s, DisasOps *o)
2851 {
2852 gen_helper_stck(o->out, cpu_env);
2853 /* ??? We don't implement clock states. */
2854 gen_op_movi_cc(s, 0);
2855 return NO_EXIT;
2856 }
2857
2858 static ExitStatus op_stcke(DisasContext *s, DisasOps *o)
2859 {
2860 TCGv_i64 c1 = tcg_temp_new_i64();
2861 TCGv_i64 c2 = tcg_temp_new_i64();
2862 gen_helper_stck(c1, cpu_env);
2863 /* Shift the 64-bit value into its place as a zero-extended
2864 104-bit value. Note that "bit positions 64-103 are always
2865 non-zero so that they compare differently to STCK"; we set
2866 the least significant bit to 1. */
2867 tcg_gen_shli_i64(c2, c1, 56);
2868 tcg_gen_shri_i64(c1, c1, 8);
2869 tcg_gen_ori_i64(c2, c2, 0x10000);
2870 tcg_gen_qemu_st64(c1, o->in2, get_mem_index(s));
2871 tcg_gen_addi_i64(o->in2, o->in2, 8);
2872 tcg_gen_qemu_st64(c2, o->in2, get_mem_index(s));
2873 tcg_temp_free_i64(c1);
2874 tcg_temp_free_i64(c2);
2875 /* ??? We don't implement clock states. */
2876 gen_op_movi_cc(s, 0);
2877 return NO_EXIT;
2878 }
2879
2880 static ExitStatus op_sckc(DisasContext *s, DisasOps *o)
2881 {
2882 check_privileged(s);
2883 gen_helper_sckc(cpu_env, o->in2);
2884 return NO_EXIT;
2885 }
2886
2887 static ExitStatus op_stckc(DisasContext *s, DisasOps *o)
2888 {
2889 check_privileged(s);
2890 gen_helper_stckc(o->out, cpu_env);
2891 return NO_EXIT;
2892 }
2893
2894 static ExitStatus op_stctg(DisasContext *s, DisasOps *o)
2895 {
2896 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2897 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2898 check_privileged(s);
2899 potential_page_fault(s);
2900 gen_helper_stctg(cpu_env, r1, o->in2, r3);
2901 tcg_temp_free_i32(r1);
2902 tcg_temp_free_i32(r3);
2903 return NO_EXIT;
2904 }
2905
2906 static ExitStatus op_stctl(DisasContext *s, DisasOps *o)
2907 {
2908 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2909 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2910 check_privileged(s);
2911 potential_page_fault(s);
2912 gen_helper_stctl(cpu_env, r1, o->in2, r3);
2913 tcg_temp_free_i32(r1);
2914 tcg_temp_free_i32(r3);
2915 return NO_EXIT;
2916 }
2917
2918 static ExitStatus op_stidp(DisasContext *s, DisasOps *o)
2919 {
2920 check_privileged(s);
2921 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num));
2922 return NO_EXIT;
2923 }
2924
2925 static ExitStatus op_spt(DisasContext *s, DisasOps *o)
2926 {
2927 check_privileged(s);
2928 gen_helper_spt(cpu_env, o->in2);
2929 return NO_EXIT;
2930 }
2931
2932 static ExitStatus op_stfl(DisasContext *s, DisasOps *o)
2933 {
2934 TCGv_i64 f, a;
2935 /* We really ought to have more complete indication of facilities
2936 that we implement. Address this when STFLE is implemented. */
2937 check_privileged(s);
2938 f = tcg_const_i64(0xc0000000);
2939 a = tcg_const_i64(200);
2940 tcg_gen_qemu_st32(f, a, get_mem_index(s));
2941 tcg_temp_free_i64(f);
2942 tcg_temp_free_i64(a);
2943 return NO_EXIT;
2944 }
2945
2946 static ExitStatus op_stpt(DisasContext *s, DisasOps *o)
2947 {
2948 check_privileged(s);
2949 gen_helper_stpt(o->out, cpu_env);
2950 return NO_EXIT;
2951 }
2952
2953 static ExitStatus op_stsi(DisasContext *s, DisasOps *o)
2954 {
2955 check_privileged(s);
2956 potential_page_fault(s);
2957 gen_helper_stsi(cc_op, cpu_env, o->in2, regs[0], regs[1]);
2958 set_cc_static(s);
2959 return NO_EXIT;
2960 }
2961
2962 static ExitStatus op_spx(DisasContext *s, DisasOps *o)
2963 {
2964 check_privileged(s);
2965 gen_helper_spx(cpu_env, o->in2);
2966 return NO_EXIT;
2967 }
2968
2969 static ExitStatus op_subchannel(DisasContext *s, DisasOps *o)
2970 {
2971 check_privileged(s);
2972 /* Not operational. */
2973 gen_op_movi_cc(s, 3);
2974 return NO_EXIT;
2975 }
2976
2977 static ExitStatus op_stpx(DisasContext *s, DisasOps *o)
2978 {
2979 check_privileged(s);
2980 tcg_gen_ld_i64(o->out, cpu_env, offsetof(CPUS390XState, psa));
2981 tcg_gen_andi_i64(o->out, o->out, 0x7fffe000);
2982 return NO_EXIT;
2983 }
2984
2985 static ExitStatus op_stnosm(DisasContext *s, DisasOps *o)
2986 {
2987 uint64_t i2 = get_field(s->fields, i2);
2988 TCGv_i64 t;
2989
2990 check_privileged(s);
2991
2992 /* It is important to do what the instruction name says: STORE THEN.
2993 If we let the output hook perform the store then if we fault and
2994 restart, we'll have the wrong SYSTEM MASK in place. */
2995 t = tcg_temp_new_i64();
2996 tcg_gen_shri_i64(t, psw_mask, 56);
2997 tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
2998 tcg_temp_free_i64(t);
2999
3000 if (s->fields->op == 0xac) {
3001 tcg_gen_andi_i64(psw_mask, psw_mask,
3002 (i2 << 56) | 0x00ffffffffffffffull);
3003 } else {
3004 tcg_gen_ori_i64(psw_mask, psw_mask, i2 << 56);
3005 }
3006 return NO_EXIT;
3007 }
3008
3009 static ExitStatus op_stura(DisasContext *s, DisasOps *o)
3010 {
3011 check_privileged(s);
3012 potential_page_fault(s);
3013 gen_helper_stura(cpu_env, o->in2, o->in1);
3014 return NO_EXIT;
3015 }
3016 #endif
3017
3018 static ExitStatus op_st8(DisasContext *s, DisasOps *o)
3019 {
3020 tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));
3021 return NO_EXIT;
3022 }
3023
3024 static ExitStatus op_st16(DisasContext *s, DisasOps *o)
3025 {
3026 tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s));
3027 return NO_EXIT;
3028 }
3029
3030 static ExitStatus op_st32(DisasContext *s, DisasOps *o)
3031 {
3032 tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s));
3033 return NO_EXIT;
3034 }
3035
3036 static ExitStatus op_st64(DisasContext *s, DisasOps *o)
3037 {
3038 tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s));
3039 return NO_EXIT;
3040 }
3041
3042 static ExitStatus op_stam(DisasContext *s, DisasOps *o)
3043 {
3044 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3045 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
3046 potential_page_fault(s);
3047 gen_helper_stam(cpu_env, r1, o->in2, r3);
3048 tcg_temp_free_i32(r1);
3049 tcg_temp_free_i32(r3);
3050 return NO_EXIT;
3051 }
3052
3053 static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
3054 {
3055 int m3 = get_field(s->fields, m3);
3056 int pos, base = s->insn->data;
3057 TCGv_i64 tmp = tcg_temp_new_i64();
3058
3059 pos = base + ctz32(m3) * 8;
3060 switch (m3) {
3061 case 0xf:
3062 /* Effectively a 32-bit store. */
3063 tcg_gen_shri_i64(tmp, o->in1, pos);
3064 tcg_gen_qemu_st32(tmp, o->in2, get_mem_index(s));
3065 break;
3066
3067 case 0xc:
3068 case 0x6:
3069 case 0x3:
3070 /* Effectively a 16-bit store. */
3071 tcg_gen_shri_i64(tmp, o->in1, pos);
3072 tcg_gen_qemu_st16(tmp, o->in2, get_mem_index(s));
3073 break;
3074
3075 case 0x8:
3076 case 0x4:
3077 case 0x2:
3078 case 0x1:
3079 /* Effectively an 8-bit store. */
3080 tcg_gen_shri_i64(tmp, o->in1, pos);
3081 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3082 break;
3083
3084 default:
3085 /* This is going to be a sequence of shifts and stores. */
3086 pos = base + 32 - 8;
3087 while (m3) {
3088 if (m3 & 0x8) {
3089 tcg_gen_shri_i64(tmp, o->in1, pos);
3090 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3091 tcg_gen_addi_i64(o->in2, o->in2, 1);
3092 }
3093 m3 = (m3 << 1) & 0xf;
3094 pos -= 8;
3095 }
3096 break;
3097 }
3098 tcg_temp_free_i64(tmp);
3099 return NO_EXIT;
3100 }
3101
3102 static ExitStatus op_stm(DisasContext *s, DisasOps *o)
3103 {
3104 int r1 = get_field(s->fields, r1);
3105 int r3 = get_field(s->fields, r3);
3106 int size = s->insn->data;
3107 TCGv_i64 tsize = tcg_const_i64(size);
3108
3109 while (1) {
3110 if (size == 8) {
3111 tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s));
3112 } else {
3113 tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s));
3114 }
3115 if (r1 == r3) {
3116 break;
3117 }
3118 tcg_gen_add_i64(o->in2, o->in2, tsize);
3119 r1 = (r1 + 1) & 15;
3120 }
3121
3122 tcg_temp_free_i64(tsize);
3123 return NO_EXIT;
3124 }
3125
3126 static ExitStatus op_stmh(DisasContext *s, DisasOps *o)
3127 {
3128 int r1 = get_field(s->fields, r1);
3129 int r3 = get_field(s->fields, r3);
3130 TCGv_i64 t = tcg_temp_new_i64();
3131 TCGv_i64 t4 = tcg_const_i64(4);
3132 TCGv_i64 t32 = tcg_const_i64(32);
3133
3134 while (1) {
3135 tcg_gen_shl_i64(t, regs[r1], t32);
3136 tcg_gen_qemu_st32(t, o->in2, get_mem_index(s));
3137 if (r1 == r3) {
3138 break;
3139 }
3140 tcg_gen_add_i64(o->in2, o->in2, t4);
3141 r1 = (r1 + 1) & 15;
3142 }
3143
3144 tcg_temp_free_i64(t);
3145 tcg_temp_free_i64(t4);
3146 tcg_temp_free_i64(t32);
3147 return NO_EXIT;
3148 }
3149
3150 static ExitStatus op_srst(DisasContext *s, DisasOps *o)
3151 {
3152 potential_page_fault(s);
3153 gen_helper_srst(o->in1, cpu_env, regs[0], o->in1, o->in2);
3154 set_cc_static(s);
3155 return_low128(o->in2);
3156 return NO_EXIT;
3157 }
3158
3159 static ExitStatus op_sub(DisasContext *s, DisasOps *o)
3160 {
3161 tcg_gen_sub_i64(o->out, o->in1, o->in2);
3162 return NO_EXIT;
3163 }
3164
3165 static ExitStatus op_subb(DisasContext *s, DisasOps *o)
3166 {
3167 TCGv_i64 cc;
3168
3169 assert(!o->g_in2);
3170 tcg_gen_not_i64(o->in2, o->in2);
3171 tcg_gen_add_i64(o->out, o->in1, o->in2);
3172
3173 /* XXX possible optimization point */
3174 gen_op_calc_cc(s);
3175 cc = tcg_temp_new_i64();
3176 tcg_gen_extu_i32_i64(cc, cc_op);
3177 tcg_gen_shri_i64(cc, cc, 1);
3178 tcg_gen_add_i64(o->out, o->out, cc);
3179 tcg_temp_free_i64(cc);
3180 return NO_EXIT;
3181 }
3182
3183 static ExitStatus op_svc(DisasContext *s, DisasOps *o)
3184 {
3185 TCGv_i32 t;
3186
3187 update_psw_addr(s);
3188 update_cc_op(s);
3189
3190 t = tcg_const_i32(get_field(s->fields, i1) & 0xff);
3191 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code));
3192 tcg_temp_free_i32(t);
3193
3194 t = tcg_const_i32(s->next_pc - s->pc);
3195 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen));
3196 tcg_temp_free_i32(t);
3197
3198 gen_exception(EXCP_SVC);
3199 return EXIT_NORETURN;
3200 }
3201
3202 static ExitStatus op_tceb(DisasContext *s, DisasOps *o)
3203 {
3204 gen_helper_tceb(cc_op, o->in1, o->in2);
3205 set_cc_static(s);
3206 return NO_EXIT;
3207 }
3208
3209 static ExitStatus op_tcdb(DisasContext *s, DisasOps *o)
3210 {
3211 gen_helper_tcdb(cc_op, o->in1, o->in2);
3212 set_cc_static(s);
3213 return NO_EXIT;
3214 }
3215
3216 static ExitStatus op_tcxb(DisasContext *s, DisasOps *o)
3217 {
3218 gen_helper_tcxb(cc_op, o->out, o->out2, o->in2);
3219 set_cc_static(s);
3220 return NO_EXIT;
3221 }
3222
3223 #ifndef CONFIG_USER_ONLY
3224 static ExitStatus op_tprot(DisasContext *s, DisasOps *o)
3225 {
3226 potential_page_fault(s);
3227 gen_helper_tprot(cc_op, o->addr1, o->in2);
3228 set_cc_static(s);
3229 return NO_EXIT;
3230 }
3231 #endif
3232
3233 static ExitStatus op_tr(DisasContext *s, DisasOps *o)
3234 {
3235 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3236 potential_page_fault(s);
3237 gen_helper_tr(cpu_env, l, o->addr1, o->in2);
3238 tcg_temp_free_i32(l);
3239 set_cc_static(s);
3240 return NO_EXIT;
3241 }
3242
3243 static ExitStatus op_unpk(DisasContext *s, DisasOps *o)
3244 {
3245 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3246 potential_page_fault(s);
3247 gen_helper_unpk(cpu_env, l, o->addr1, o->in2);
3248 tcg_temp_free_i32(l);
3249 return NO_EXIT;
3250 }
3251
3252 static ExitStatus op_xc(DisasContext *s, DisasOps *o)
3253 {
3254 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3255 potential_page_fault(s);
3256 gen_helper_xc(cc_op, cpu_env, l, o->addr1, o->in2);
3257 tcg_temp_free_i32(l);
3258 set_cc_static(s);
3259 return NO_EXIT;
3260 }
3261
3262 static ExitStatus op_xor(DisasContext *s, DisasOps *o)
3263 {
3264 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3265 return NO_EXIT;
3266 }
3267
3268 static ExitStatus op_xori(DisasContext *s, DisasOps *o)
3269 {
3270 int shift = s->insn->data & 0xff;
3271 int size = s->insn->data >> 8;
3272 uint64_t mask = ((1ull << size) - 1) << shift;
3273
3274 assert(!o->g_in2);
3275 tcg_gen_shli_i64(o->in2, o->in2, shift);
3276 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3277
3278 /* Produce the CC from only the bits manipulated. */
3279 tcg_gen_andi_i64(cc_dst, o->out, mask);
3280 set_cc_nz_u64(s, cc_dst);
3281 return NO_EXIT;
3282 }
3283
3284 static ExitStatus op_zero(DisasContext *s, DisasOps *o)
3285 {
3286 o->out = tcg_const_i64(0);
3287 return NO_EXIT;
3288 }
3289
3290 static ExitStatus op_zero2(DisasContext *s, DisasOps *o)
3291 {
3292 o->out = tcg_const_i64(0);
3293 o->out2 = o->out;
3294 o->g_out2 = true;
3295 return NO_EXIT;
3296 }
3297
3298 /* ====================================================================== */
3299 /* The "Cc OUTput" generators. Given the generated output (and in some cases
3300 the original inputs), update the various cc data structures in order to
3301 be able to compute the new condition code. */
3302
3303 static void cout_abs32(DisasContext *s, DisasOps *o)
3304 {
3305 gen_op_update1_cc_i64(s, CC_OP_ABS_32, o->out);
3306 }
3307
3308 static void cout_abs64(DisasContext *s, DisasOps *o)
3309 {
3310 gen_op_update1_cc_i64(s, CC_OP_ABS_64, o->out);
3311 }
3312
3313 static void cout_adds32(DisasContext *s, DisasOps *o)
3314 {
3315 gen_op_update3_cc_i64(s, CC_OP_ADD_32, o->in1, o->in2, o->out);
3316 }
3317
3318 static void cout_adds64(DisasContext *s, DisasOps *o)
3319 {
3320 gen_op_update3_cc_i64(s, CC_OP_ADD_64, o->in1, o->in2, o->out);
3321 }
3322
3323 static void cout_addu32(DisasContext *s, DisasOps *o)
3324 {
3325 gen_op_update3_cc_i64(s, CC_OP_ADDU_32, o->in1, o->in2, o->out);
3326 }
3327
3328 static void cout_addu64(DisasContext *s, DisasOps *o)
3329 {
3330 gen_op_update3_cc_i64(s, CC_OP_ADDU_64, o->in1, o->in2, o->out);
3331 }
3332
3333 static void cout_addc32(DisasContext *s, DisasOps *o)
3334 {
3335 gen_op_update3_cc_i64(s, CC_OP_ADDC_32, o->in1, o->in2, o->out);
3336 }
3337
3338 static void cout_addc64(DisasContext *s, DisasOps *o)
3339 {
3340 gen_op_update3_cc_i64(s, CC_OP_ADDC_64, o->in1, o->in2, o->out);
3341 }
3342
3343 static void cout_cmps32(DisasContext *s, DisasOps *o)
3344 {
3345 gen_op_update2_cc_i64(s, CC_OP_LTGT_32, o->in1, o->in2);
3346 }
3347
3348 static void cout_cmps64(DisasContext *s, DisasOps *o)
3349 {
3350 gen_op_update2_cc_i64(s, CC_OP_LTGT_64, o->in1, o->in2);
3351 }
3352
3353 static void cout_cmpu32(DisasContext *s, DisasOps *o)
3354 {
3355 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_32, o->in1, o->in2);
3356 }
3357
3358 static void cout_cmpu64(DisasContext *s, DisasOps *o)
3359 {
3360 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, o->in1, o->in2);
3361 }
3362
3363 static void cout_f32(DisasContext *s, DisasOps *o)
3364 {
3365 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, o->out);
3366 }
3367
3368 static void cout_f64(DisasContext *s, DisasOps *o)
3369 {
3370 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, o->out);
3371 }
3372
3373 static void cout_f128(DisasContext *s, DisasOps *o)
3374 {
3375 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, o->out, o->out2);
3376 }
3377
3378 static void cout_nabs32(DisasContext *s, DisasOps *o)
3379 {
3380 gen_op_update1_cc_i64(s, CC_OP_NABS_32, o->out);
3381 }
3382
3383 static void cout_nabs64(DisasContext *s, DisasOps *o)
3384 {
3385 gen_op_update1_cc_i64(s, CC_OP_NABS_64, o->out);
3386 }
3387
3388 static void cout_neg32(DisasContext *s, DisasOps *o)
3389 {
3390 gen_op_update1_cc_i64(s, CC_OP_COMP_32, o->out);
3391 }
3392
3393 static void cout_neg64(DisasContext *s, DisasOps *o)
3394 {
3395 gen_op_update1_cc_i64(s, CC_OP_COMP_64, o->out);
3396 }
3397
3398 static void cout_nz32(DisasContext *s, DisasOps *o)
3399 {
3400 tcg_gen_ext32u_i64(cc_dst, o->out);
3401 gen_op_update1_cc_i64(s, CC_OP_NZ, cc_dst);
3402 }
3403
3404 static void cout_nz64(DisasContext *s, DisasOps *o)
3405 {
3406 gen_op_update1_cc_i64(s, CC_OP_NZ, o->out);
3407 }
3408
3409 static void cout_s32(DisasContext *s, DisasOps *o)
3410 {
3411 gen_op_update1_cc_i64(s, CC_OP_LTGT0_32, o->out);
3412 }
3413
3414 static void cout_s64(DisasContext *s, DisasOps *o)
3415 {
3416 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, o->out);
3417 }
3418
3419 static void cout_subs32(DisasContext *s, DisasOps *o)
3420 {
3421 gen_op_update3_cc_i64(s, CC_OP_SUB_32, o->in1, o->in2, o->out);
3422 }
3423
3424 static void cout_subs64(DisasContext *s, DisasOps *o)
3425 {
3426 gen_op_update3_cc_i64(s, CC_OP_SUB_64, o->in1, o->in2, o->out);
3427 }
3428
3429 static void cout_subu32(DisasContext *s, DisasOps *o)
3430 {
3431 gen_op_update3_cc_i64(s, CC_OP_SUBU_32, o->in1, o->in2, o->out);
3432 }
3433
3434 static void cout_subu64(DisasContext *s, DisasOps *o)
3435 {
3436 gen_op_update3_cc_i64(s, CC_OP_SUBU_64, o->in1, o->in2, o->out);
3437 }
3438
3439 static void cout_subb32(DisasContext *s, DisasOps *o)
3440 {
3441 gen_op_update3_cc_i64(s, CC_OP_SUBB_32, o->in1, o->in2, o->out);
3442 }
3443
3444 static void cout_subb64(DisasContext *s, DisasOps *o)
3445 {
3446 gen_op_update3_cc_i64(s, CC_OP_SUBB_64, o->in1, o->in2, o->out);
3447 }
3448
3449 static void cout_tm32(DisasContext *s, DisasOps *o)
3450 {
3451 gen_op_update2_cc_i64(s, CC_OP_TM_32, o->in1, o->in2);
3452 }
3453
3454 static void cout_tm64(DisasContext *s, DisasOps *o)
3455 {
3456 gen_op_update2_cc_i64(s, CC_OP_TM_64, o->in1, o->in2);
3457 }
3458
3459 /* ====================================================================== */
3460 /* The "PREPeration" generators. These initialize the DisasOps.OUT fields
3461 with the TCG register to which we will write. Used in combination with
3462 the "wout" generators, in some cases we need a new temporary, and in
3463 some cases we can write to a TCG global. */
3464
3465 static void prep_new(DisasContext *s, DisasFields *f, DisasOps *o)
3466 {
3467 o->out = tcg_temp_new_i64();
3468 }
3469
3470 static void prep_new_P(DisasContext *s, DisasFields *f, DisasOps *o)
3471 {
3472 o->out = tcg_temp_new_i64();
3473 o->out2 = tcg_temp_new_i64();
3474 }
3475
3476 static void prep_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3477 {
3478 o->out = regs[get_field(f, r1)];
3479 o->g_out = true;
3480 }
3481
3482 static void prep_r1_P(DisasContext *s, DisasFields *f, DisasOps *o)
3483 {
3484 /* ??? Specification exception: r1 must be even. */
3485 int r1 = get_field(f, r1);
3486 o->out = regs[r1];
3487 o->out2 = regs[(r1 + 1) & 15];
3488 o->g_out = o->g_out2 = true;
3489 }
3490
3491 static void prep_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3492 {
3493 o->out = fregs[get_field(f, r1)];
3494 o->g_out = true;
3495 }
3496
3497 static void prep_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3498 {
3499 /* ??? Specification exception: r1 must be < 14. */
3500 int r1 = get_field(f, r1);
3501 o->out = fregs[r1];
3502 o->out2 = fregs[(r1 + 2) & 15];
3503 o->g_out = o->g_out2 = true;
3504 }
3505
3506 /* ====================================================================== */
3507 /* The "Write OUTput" generators. These generally perform some non-trivial
3508 copy of data to TCG globals, or to main memory. The trivial cases are
3509 generally handled by having a "prep" generator install the TCG global
3510 as the destination of the operation. */
3511
3512 static void wout_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3513 {
3514 store_reg(get_field(f, r1), o->out);
3515 }
3516
3517 static void wout_r1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3518 {
3519 int r1 = get_field(f, r1);
3520 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8);
3521 }
3522
3523 static void wout_r1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3524 {
3525 int r1 = get_field(f, r1);
3526 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 16);
3527 }
3528
3529 static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3530 {
3531 store_reg32_i64(get_field(f, r1), o->out);
3532 }
3533
3534 static void wout_r1_P32(DisasContext *s, DisasFields *f, DisasOps *o)
3535 {
3536 /* ??? Specification exception: r1 must be even. */
3537 int r1 = get_field(f, r1);
3538 store_reg32_i64(r1, o->out);
3539 store_reg32_i64((r1 + 1) & 15, o->out2);
3540 }
3541
3542 static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3543 {
3544 /* ??? Specification exception: r1 must be even. */
3545 int r1 = get_field(f, r1);
3546 store_reg32_i64((r1 + 1) & 15, o->out);
3547 tcg_gen_shri_i64(o->out, o->out, 32);
3548 store_reg32_i64(r1, o->out);
3549 }
3550
3551 static void wout_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3552 {
3553 store_freg32_i64(get_field(f, r1), o->out);
3554 }
3555
3556 static void wout_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3557 {
3558 store_freg(get_field(f, r1), o->out);
3559 }
3560
3561 static void wout_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3562 {
3563 /* ??? Specification exception: r1 must be < 14. */
3564 int f1 = get_field(s->fields, r1);
3565 store_freg(f1, o->out);
3566 store_freg((f1 + 2) & 15, o->out2);
3567 }
3568
3569 static void wout_cond_r1r2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3570 {
3571 if (get_field(f, r1) != get_field(f, r2)) {
3572 store_reg32_i64(get_field(f, r1), o->out);
3573 }
3574 }
3575
3576 static void wout_cond_e1e2(DisasContext *s, DisasFields *f, DisasOps *o)
3577 {
3578 if (get_field(f, r1) != get_field(f, r2)) {
3579 store_freg32_i64(get_field(f, r1), o->out);
3580 }
3581 }
3582
3583 static void wout_m1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3584 {
3585 tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s));
3586 }
3587
3588 static void wout_m1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3589 {
3590 tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s));
3591 }
3592
3593 static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3594 {
3595 tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
3596 }
3597
3598 static void wout_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3599 {
3600 tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
3601 }
3602
3603 static void wout_m2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3604 {
3605 tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s));
3606 }
3607
3608 /* ====================================================================== */
3609 /* The "INput 1" generators. These load the first operand to an insn. */
3610
3611 static void in1_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3612 {
3613 o->in1 = load_reg(get_field(f, r1));
3614 }
3615
3616 static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3617 {
3618 o->in1 = regs[get_field(f, r1)];
3619 o->g_in1 = true;
3620 }
3621
3622 static void in1_r1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3623 {
3624 o->in1 = tcg_temp_new_i64();
3625 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r1)]);
3626 }
3627
3628 static void in1_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3629 {
3630 o->in1 = tcg_temp_new_i64();
3631 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r1)]);
3632 }
3633
3634 static void in1_r1_sr32(DisasContext *s, DisasFields *f, DisasOps *o)
3635 {
3636 o->in1 = tcg_temp_new_i64();
3637 tcg_gen_shri_i64(o->in1, regs[get_field(f, r1)], 32);
3638 }
3639
3640 static void in1_r1p1(DisasContext *s, DisasFields *f, DisasOps *o)
3641 {
3642 /* ??? Specification exception: r1 must be even. */
3643 int r1 = get_field(f, r1);
3644 o->in1 = load_reg((r1 + 1) & 15);
3645 }
3646
3647 static void in1_r1p1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3648 {
3649 /* ??? Specification exception: r1 must be even. */
3650 int r1 = get_field(f, r1);
3651 o->in1 = tcg_temp_new_i64();
3652 tcg_gen_ext32s_i64(o->in1, regs[(r1 + 1) & 15]);
3653 }
3654
3655 static void in1_r1p1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3656 {
3657 /* ??? Specification exception: r1 must be even. */
3658 int r1 = get_field(f, r1);
3659 o->in1 = tcg_temp_new_i64();
3660 tcg_gen_ext32u_i64(o->in1, regs[(r1 + 1) & 15]);
3661 }
3662
3663 static void in1_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3664 {
3665 /* ??? Specification exception: r1 must be even. */
3666 int r1 = get_field(f, r1);
3667 o->in1 = tcg_temp_new_i64();
3668 tcg_gen_concat32_i64(o->in1, regs[r1 + 1], regs[r1]);
3669 }
3670
3671 static void in1_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3672 {
3673 o->in1 = load_reg(get_field(f, r2));
3674 }
3675
3676 static void in1_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3677 {
3678 o->in1 = load_reg(get_field(f, r3));
3679 }
3680
3681 static void in1_r3_o(DisasContext *s, DisasFields *f, DisasOps *o)
3682 {
3683 o->in1 = regs[get_field(f, r3)];
3684 o->g_in1 = true;
3685 }
3686
3687 static void in1_r3_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3688 {
3689 o->in1 = tcg_temp_new_i64();
3690 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r3)]);
3691 }
3692
3693 static void in1_r3_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3694 {
3695 o->in1 = tcg_temp_new_i64();
3696 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r3)]);
3697 }
3698
3699 static void in1_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3700 {
3701 o->in1 = load_freg32_i64(get_field(f, r1));
3702 }
3703
3704 static void in1_f1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3705 {
3706 o->in1 = fregs[get_field(f, r1)];
3707 o->g_in1 = true;
3708 }
3709
3710 static void in1_x1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3711 {
3712 /* ??? Specification exception: r1 must be < 14. */
3713 int r1 = get_field(f, r1);
3714 o->out = fregs[r1];
3715 o->out2 = fregs[(r1 + 2) & 15];
3716 o->g_out = o->g_out2 = true;
3717 }
3718
3719 static void in1_la1(DisasContext *s, DisasFields *f, DisasOps *o)
3720 {
3721 o->addr1 = get_address(s, 0, get_field(f, b1), get_field(f, d1));
3722 }
3723
3724 static void in1_la2(DisasContext *s, DisasFields *f, DisasOps *o)
3725 {
3726 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3727 o->addr1 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3728 }
3729
3730 static void in1_m1_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3731 {
3732 in1_la1(s, f, o);
3733 o->in1 = tcg_temp_new_i64();
3734 tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s));
3735 }
3736
3737 static void in1_m1_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3738 {
3739 in1_la1(s, f, o);
3740 o->in1 = tcg_temp_new_i64();
3741 tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s));
3742 }
3743
3744 static void in1_m1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3745 {
3746 in1_la1(s, f, o);
3747 o->in1 = tcg_temp_new_i64();
3748 tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s));
3749 }
3750
3751 static void in1_m1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3752 {
3753 in1_la1(s, f, o);
3754 o->in1 = tcg_temp_new_i64();
3755 tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s));
3756 }
3757
3758 static void in1_m1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3759 {
3760 in1_la1(s, f, o);
3761 o->in1 = tcg_temp_new_i64();
3762 tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s));
3763 }
3764
3765 static void in1_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3766 {
3767 in1_la1(s, f, o);
3768 o->in1 = tcg_temp_new_i64();
3769 tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s));
3770 }
3771
3772 /* ====================================================================== */
3773 /* The "INput 2" generators. These load the second operand to an insn. */
3774
3775 static void in2_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3776 {
3777 o->in2 = regs[get_field(f, r1)];
3778 o->g_in2 = true;
3779 }
3780
3781 static void in2_r1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3782 {
3783 o->in2 = tcg_temp_new_i64();
3784 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r1)]);
3785 }
3786
3787 static void in2_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3788 {
3789 o->in2 = tcg_temp_new_i64();
3790 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r1)]);
3791 }
3792
3793 static void in2_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3794 {
3795 o->in2 = load_reg(get_field(f, r2));
3796 }
3797
3798 static void in2_r2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3799 {
3800 o->in2 = regs[get_field(f, r2)];
3801 o->g_in2 = true;
3802 }
3803
3804 static void in2_r2_nz(DisasContext *s, DisasFields *f, DisasOps *o)
3805 {
3806 int r2 = get_field(f, r2);
3807 if (r2 != 0) {
3808 o->in2 = load_reg(r2);
3809 }
3810 }
3811
3812 static void in2_r2_8s(DisasContext *s, DisasFields *f, DisasOps *o)
3813 {
3814 o->in2 = tcg_temp_new_i64();
3815 tcg_gen_ext8s_i64(o->in2, regs[get_field(f, r2)]);
3816 }
3817
3818 static void in2_r2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3819 {
3820 o->in2 = tcg_temp_new_i64();
3821 tcg_gen_ext8u_i64(o->in2, regs[get_field(f, r2)]);
3822 }
3823
3824 static void in2_r2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3825 {
3826 o->in2 = tcg_temp_new_i64();
3827 tcg_gen_ext16s_i64(o->in2, regs[get_field(f, r2)]);
3828 }
3829
3830 static void in2_r2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3831 {
3832 o->in2 = tcg_temp_new_i64();
3833 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r2)]);
3834 }
3835
3836 static void in2_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3837 {
3838 o->in2 = load_reg(get_field(f, r3));
3839 }
3840
3841 static void in2_r2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3842 {
3843 o->in2 = tcg_temp_new_i64();
3844 tcg_gen_ext32s_i64(o->in2, regs[get_field(f, r2)]);
3845 }
3846
3847 static void in2_r2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3848 {
3849 o->in2 = tcg_temp_new_i64();
3850 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r2)]);
3851 }
3852
3853 static void in2_e2(DisasContext *s, DisasFields *f, DisasOps *o)
3854 {
3855 o->in2 = load_freg32_i64(get_field(f, r2));
3856 }
3857
3858 static void in2_f2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3859 {
3860 o->in2 = fregs[get_field(f, r2)];
3861 o->g_in2 = true;
3862 }
3863
3864 static void in2_x2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3865 {
3866 /* ??? Specification exception: r1 must be < 14. */
3867 int r2 = get_field(f, r2);
3868 o->in1 = fregs[r2];
3869 o->in2 = fregs[(r2 + 2) & 15];
3870 o->g_in1 = o->g_in2 = true;
3871 }
3872
3873 static void in2_ra2(DisasContext *s, DisasFields *f, DisasOps *o)
3874 {
3875 o->in2 = get_address(s, 0, get_field(f, r2), 0);
3876 }
3877
3878 static void in2_a2(DisasContext *s, DisasFields *f, DisasOps *o)
3879 {
3880 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3881 o->in2 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3882 }
3883
3884 static void in2_ri2(DisasContext *s, DisasFields *f, DisasOps *o)
3885 {
3886 o->in2 = tcg_const_i64(s->pc + (int64_t)get_field(f, i2) * 2);
3887 }
3888
3889 static void in2_sh32(DisasContext *s, DisasFields *f, DisasOps *o)
3890 {
3891 help_l2_shift(s, f, o, 31);
3892 }
3893
3894 static void in2_sh64(DisasContext *s, DisasFields *f, DisasOps *o)
3895 {
3896 help_l2_shift(s, f, o, 63);
3897 }
3898
3899 static void in2_m2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3900 {
3901 in2_a2(s, f, o);
3902 tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s));
3903 }
3904
3905 static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3906 {
3907 in2_a2(s, f, o);
3908 tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
3909 }
3910
3911 static void in2_m2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3912 {
3913 in2_a2(s, f, o);
3914 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3915 }
3916
3917 static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3918 {
3919 in2_a2(s, f, o);
3920 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3921 }
3922
3923 static void in2_m2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3924 {
3925 in2_a2(s, f, o);
3926 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3927 }
3928
3929 static void in2_m2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3930 {
3931 in2_a2(s, f, o);
3932 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3933 }
3934
3935 static void in2_mri2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3936 {
3937 in2_ri2(s, f, o);
3938 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3939 }
3940
3941 static void in2_mri2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3942 {
3943 in2_ri2(s, f, o);
3944 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3945 }
3946
3947 static void in2_mri2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3948 {
3949 in2_ri2(s, f, o);
3950 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3951 }
3952
3953 static void in2_mri2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3954 {
3955 in2_ri2(s, f, o);
3956 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3957 }
3958
3959 static void in2_i2(DisasContext *s, DisasFields *f, DisasOps *o)
3960 {
3961 o->in2 = tcg_const_i64(get_field(f, i2));
3962 }
3963
3964 static void in2_i2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3965 {
3966 o->in2 = tcg_const_i64((uint8_t)get_field(f, i2));
3967 }
3968
3969 static void in2_i2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3970 {
3971 o->in2 = tcg_const_i64((uint16_t)get_field(f, i2));
3972 }
3973
3974 static void in2_i2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3975 {
3976 o->in2 = tcg_const_i64((uint32_t)get_field(f, i2));
3977 }
3978
3979 static void in2_i2_16u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
3980 {
3981 uint64_t i2 = (uint16_t)get_field(f, i2);
3982 o->in2 = tcg_const_i64(i2 << s->insn->data);
3983 }
3984
3985 static void in2_i2_32u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
3986 {
3987 uint64_t i2 = (uint32_t)get_field(f, i2);
3988 o->in2 = tcg_const_i64(i2 << s->insn->data);
3989 }
3990
3991 /* ====================================================================== */
3992
3993 /* Find opc within the table of insns. This is formulated as a switch
3994 statement so that (1) we get compile-time notice of cut-paste errors
3995 for duplicated opcodes, and (2) the compiler generates the binary
3996 search tree, rather than us having to post-process the table. */
3997
3998 #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \
3999 D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0)
4000
4001 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) insn_ ## NM,
4002
4003 enum DisasInsnEnum {
4004 #include "insn-data.def"
4005 };
4006
4007 #undef D
4008 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) { \
4009 .opc = OPC, \
4010 .fmt = FMT_##FT, \
4011 .fac = FAC_##FC, \
4012 .name = #NM, \
4013 .help_in1 = in1_##I1, \
4014 .help_in2 = in2_##I2, \
4015 .help_prep = prep_##P, \
4016 .help_wout = wout_##W, \
4017 .help_cout = cout_##CC, \
4018 .help_op = op_##OP, \
4019 .data = D \
4020 },
4021
4022 /* Allow 0 to be used for NULL in the table below. */
4023 #define in1_0 NULL
4024 #define in2_0 NULL
4025 #define prep_0 NULL
4026 #define wout_0 NULL
4027 #define cout_0 NULL
4028 #define op_0 NULL
4029
4030 static const DisasInsn insn_info[] = {
4031 #include "insn-data.def"
4032 };
4033
4034 #undef D
4035 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \
4036 case OPC: return &insn_info[insn_ ## NM];
4037
4038 static const DisasInsn *lookup_opc(uint16_t opc)
4039 {
4040 switch (opc) {
4041 #include "insn-data.def"
4042 default:
4043 return NULL;
4044 }
4045 }
4046
4047 #undef D
4048 #undef C
4049
4050 /* Extract a field from the insn. The INSN should be left-aligned in
4051 the uint64_t so that we can more easily utilize the big-bit-endian
4052 definitions we extract from the Principals of Operation. */
4053
4054 static void extract_field(DisasFields *o, const DisasField *f, uint64_t insn)
4055 {
4056 uint32_t r, m;
4057
4058 if (f->size == 0) {
4059 return;
4060 }
4061
4062 /* Zero extract the field from the insn. */
4063 r = (insn << f->beg) >> (64 - f->size);
4064
4065 /* Sign-extend, or un-swap the field as necessary. */
4066 switch (f->type) {
4067 case 0: /* unsigned */
4068 break;
4069 case 1: /* signed */
4070 assert(f->size <= 32);
4071 m = 1u << (f->size - 1);
4072 r = (r ^ m) - m;
4073 break;
4074 case 2: /* dl+dh split, signed 20 bit. */
4075 r = ((int8_t)r << 12) | (r >> 8);
4076 break;
4077 default:
4078 abort();
4079 }
4080
4081 /* Validate that the "compressed" encoding we selected above is valid.
4082 I.e. we havn't make two different original fields overlap. */
4083 assert(((o->presentC >> f->indexC) & 1) == 0);
4084 o->presentC |= 1 << f->indexC;
4085 o->presentO |= 1 << f->indexO;
4086
4087 o->c[f->indexC] = r;
4088 }
4089
4090 /* Lookup the insn at the current PC, extracting the operands into O and
4091 returning the info struct for the insn. Returns NULL for invalid insn. */
4092
4093 static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
4094 DisasFields *f)
4095 {
4096 uint64_t insn, pc = s->pc;
4097 int op, op2, ilen;
4098 const DisasInsn *info;
4099
4100 insn = ld_code2(env, pc);
4101 op = (insn >> 8) & 0xff;
4102 ilen = get_ilen(op);
4103 s->next_pc = s->pc + ilen;
4104
4105 switch (ilen) {
4106 case 2:
4107 insn = insn << 48;
4108 break;
4109 case 4:
4110 insn = ld_code4(env, pc) << 32;
4111 break;
4112 case 6:
4113 insn = (insn << 48) | (ld_code4(env, pc + 2) << 16);
4114 break;
4115 default:
4116 abort();
4117 }
4118
4119 /* We can't actually determine the insn format until we've looked up
4120 the full insn opcode. Which we can't do without locating the
4121 secondary opcode. Assume by default that OP2 is at bit 40; for
4122 those smaller insns that don't actually have a secondary opcode
4123 this will correctly result in OP2 = 0. */
4124 switch (op) {
4125 case 0x01: /* E */
4126 case 0x80: /* S */
4127 case 0x82: /* S */
4128 case 0x93: /* S */
4129 case 0xb2: /* S, RRF, RRE */
4130 case 0xb3: /* RRE, RRD, RRF */
4131 case 0xb9: /* RRE, RRF */
4132 case 0xe5: /* SSE, SIL */
4133 op2 = (insn << 8) >> 56;
4134 break;
4135 case 0xa5: /* RI */
4136 case 0xa7: /* RI */
4137 case 0xc0: /* RIL */
4138 case 0xc2: /* RIL */
4139 case 0xc4: /* RIL */
4140 case 0xc6: /* RIL */
4141 case 0xc8: /* SSF */
4142 case 0xcc: /* RIL */
4143 op2 = (insn << 12) >> 60;
4144 break;
4145 case 0xd0 ... 0xdf: /* SS */
4146 case 0xe1: /* SS */
4147 case 0xe2: /* SS */
4148 case 0xe8: /* SS */
4149 case 0xe9: /* SS */
4150 case 0xea: /* SS */
4151 case 0xee ... 0xf3: /* SS */
4152 case 0xf8 ... 0xfd: /* SS */
4153 op2 = 0;
4154 break;
4155 default:
4156 op2 = (insn << 40) >> 56;
4157 break;
4158 }
4159
4160 memset(f, 0, sizeof(*f));
4161 f->op = op;
4162 f->op2 = op2;
4163
4164 /* Lookup the instruction. */
4165 info = lookup_opc(op << 8 | op2);
4166
4167 /* If we found it, extract the operands. */
4168 if (info != NULL) {
4169 DisasFormat fmt = info->fmt;
4170 int i;
4171
4172 for (i = 0; i < NUM_C_FIELD; ++i) {
4173 extract_field(f, &format_info[fmt].op[i], insn);
4174 }
4175 }
4176 return info;
4177 }
4178
4179 static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
4180 {
4181 const DisasInsn *insn;
4182 ExitStatus ret = NO_EXIT;
4183 DisasFields f;
4184 DisasOps o;
4185
4186 /* Search for the insn in the table. */
4187 insn = extract_insn(env, s, &f);
4188
4189 /* Not found means unimplemented/illegal opcode. */
4190 if (insn == NULL) {
4191 qemu_log_mask(LOG_UNIMP, "unimplemented opcode 0x%02x%02x\n",
4192 f.op, f.op2);
4193 gen_illegal_opcode(s);
4194 return EXIT_NORETURN;
4195 }
4196
4197 /* Set up the strutures we use to communicate with the helpers. */
4198 s->insn = insn;
4199 s->fields = &f;
4200 o.g_out = o.g_out2 = o.g_in1 = o.g_in2 = false;
4201 TCGV_UNUSED_I64(o.out);
4202 TCGV_UNUSED_I64(o.out2);
4203 TCGV_UNUSED_I64(o.in1);
4204 TCGV_UNUSED_I64(o.in2);
4205 TCGV_UNUSED_I64(o.addr1);
4206
4207 /* Implement the instruction. */
4208 if (insn->help_in1) {
4209 insn->help_in1(s, &f, &o);
4210 }
4211 if (insn->help_in2) {
4212 insn->help_in2(s, &f, &o);
4213 }
4214 if (insn->help_prep) {
4215 insn->help_prep(s, &f, &o);
4216 }
4217 if (insn->help_op) {
4218 ret = insn->help_op(s, &o);
4219 }
4220 if (insn->help_wout) {
4221 insn->help_wout(s, &f, &o);
4222 }
4223 if (insn->help_cout) {
4224 insn->help_cout(s, &o);
4225 }
4226
4227 /* Free any temporaries created by the helpers. */
4228 if (!TCGV_IS_UNUSED_I64(o.out) && !o.g_out) {
4229 tcg_temp_free_i64(o.out);
4230 }
4231 if (!TCGV_IS_UNUSED_I64(o.out2) && !o.g_out2) {
4232 tcg_temp_free_i64(o.out2);
4233 }
4234 if (!TCGV_IS_UNUSED_I64(o.in1) && !o.g_in1) {
4235 tcg_temp_free_i64(o.in1);
4236 }
4237 if (!TCGV_IS_UNUSED_I64(o.in2) && !o.g_in2) {
4238 tcg_temp_free_i64(o.in2);
4239 }
4240 if (!TCGV_IS_UNUSED_I64(o.addr1)) {
4241 tcg_temp_free_i64(o.addr1);
4242 }
4243
4244 /* Advance to the next instruction. */
4245 s->pc = s->next_pc;
4246 return ret;
4247 }
4248
4249 static inline void gen_intermediate_code_internal(CPUS390XState *env,
4250 TranslationBlock *tb,
4251 int search_pc)
4252 {
4253 DisasContext dc;
4254 target_ulong pc_start;
4255 uint64_t next_page_start;
4256 uint16_t *gen_opc_end;
4257 int j, lj = -1;
4258 int num_insns, max_insns;
4259 CPUBreakpoint *bp;
4260 ExitStatus status;
4261 bool do_debug;
4262
4263 pc_start = tb->pc;
4264
4265 /* 31-bit mode */
4266 if (!(tb->flags & FLAG_MASK_64)) {
4267 pc_start &= 0x7fffffff;
4268 }
4269
4270 dc.tb = tb;
4271 dc.pc = pc_start;
4272 dc.cc_op = CC_OP_DYNAMIC;
4273 do_debug = dc.singlestep_enabled = env->singlestep_enabled;
4274
4275 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
4276
4277 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4278
4279 num_insns = 0;
4280 max_insns = tb->cflags & CF_COUNT_MASK;
4281 if (max_insns == 0) {
4282 max_insns = CF_COUNT_MASK;
4283 }
4284
4285 gen_icount_start();
4286
4287 do {
4288 if (search_pc) {
4289 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4290 if (lj < j) {
4291 lj++;
4292 while (lj < j) {
4293 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4294 }
4295 }
4296 tcg_ctx.gen_opc_pc[lj] = dc.pc;
4297 gen_opc_cc_op[lj] = dc.cc_op;
4298 tcg_ctx.gen_opc_instr_start[lj] = 1;
4299 tcg_ctx.gen_opc_icount[lj] = num_insns;
4300 }
4301 if (++num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
4302 gen_io_start();
4303 }
4304
4305 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
4306 tcg_gen_debug_insn_start(dc.pc);
4307 }
4308
4309 status = NO_EXIT;
4310 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
4311 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
4312 if (bp->pc == dc.pc) {
4313 status = EXIT_PC_STALE;
4314 do_debug = true;
4315 break;
4316 }
4317 }
4318 }
4319 if (status == NO_EXIT) {
4320 status = translate_one(env, &dc);
4321 }
4322
4323 /* If we reach a page boundary, are single stepping,
4324 or exhaust instruction count, stop generation. */
4325 if (status == NO_EXIT
4326 && (dc.pc >= next_page_start
4327 || tcg_ctx.gen_opc_ptr >= gen_opc_end
4328 || num_insns >= max_insns
4329 || singlestep
4330 || env->singlestep_enabled)) {
4331 status = EXIT_PC_STALE;
4332 }
4333 } while (status == NO_EXIT);
4334
4335 if (tb->cflags & CF_LAST_IO) {
4336 gen_io_end();
4337 }
4338
4339 switch (status) {
4340 case EXIT_GOTO_TB:
4341 case EXIT_NORETURN:
4342 break;
4343 case EXIT_PC_STALE:
4344 update_psw_addr(&dc);
4345 /* FALLTHRU */
4346 case EXIT_PC_UPDATED:
4347 /* Next TB starts off with CC_OP_DYNAMIC, so make sure the
4348 cc op type is in env */
4349 update_cc_op(&dc);
4350 /* Exit the TB, either by raising a debug exception or by return. */
4351 if (do_debug) {
4352 gen_exception(EXCP_DEBUG);
4353 } else {
4354 tcg_gen_exit_tb(0);
4355 }
4356 break;
4357 default:
4358 abort();
4359 }
4360
4361 gen_icount_end(tb, num_insns);
4362 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
4363 if (search_pc) {
4364 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4365 lj++;
4366 while (lj <= j) {
4367 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4368 }
4369 } else {
4370 tb->size = dc.pc - pc_start;
4371 tb->icount = num_insns;
4372 }
4373
4374 #if defined(S390X_DEBUG_DISAS)
4375 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
4376 qemu_log("IN: %s\n", lookup_symbol(pc_start));
4377 log_target_disas(env, pc_start, dc.pc - pc_start, 1);
4378 qemu_log("\n");
4379 }
4380 #endif
4381 }
4382
4383 void gen_intermediate_code (CPUS390XState *env, struct TranslationBlock *tb)
4384 {
4385 gen_intermediate_code_internal(env, tb, 0);
4386 }
4387
4388 void gen_intermediate_code_pc (CPUS390XState *env, struct TranslationBlock *tb)
4389 {
4390 gen_intermediate_code_internal(env, tb, 1);
4391 }
4392
4393 void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, int pc_pos)
4394 {
4395 int cc_op;
4396 env->psw.addr = tcg_ctx.gen_opc_pc[pc_pos];
4397 cc_op = gen_opc_cc_op[pc_pos];
4398 if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {
4399 env->cc_op = cc_op;
4400 }
4401 }
QEMU mirror