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[mirror_qemu.git] / target-s390x / translate.c
1 /*
2 * S/390 translation
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* #define DEBUG_INLINE_BRANCHES */
22 #define S390X_DEBUG_DISAS
23 /* #define S390X_DEBUG_DISAS_VERBOSE */
24
25 #ifdef S390X_DEBUG_DISAS_VERBOSE
26 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
27 #else
28 # define LOG_DISAS(...) do { } while (0)
29 #endif
30
31 #include "cpu.h"
32 #include "disas/disas.h"
33 #include "tcg-op.h"
34 #include "qemu/log.h"
35 #include "qemu/host-utils.h"
36
37 /* global register indexes */
38 static TCGv_ptr cpu_env;
39
40 #include "exec/gen-icount.h"
41 #include "helper.h"
42 #define GEN_HELPER 1
43 #include "helper.h"
44
45
46 /* Information that (most) every instruction needs to manipulate. */
47 typedef struct DisasContext DisasContext;
48 typedef struct DisasInsn DisasInsn;
49 typedef struct DisasFields DisasFields;
50
51 struct DisasContext {
52 struct TranslationBlock *tb;
53 const DisasInsn *insn;
54 DisasFields *fields;
55 uint64_t pc, next_pc;
56 enum cc_op cc_op;
57 bool singlestep_enabled;
58 int is_jmp;
59 };
60
61 /* Information carried about a condition to be evaluated. */
62 typedef struct {
63 TCGCond cond:8;
64 bool is_64;
65 bool g1;
66 bool g2;
67 union {
68 struct { TCGv_i64 a, b; } s64;
69 struct { TCGv_i32 a, b; } s32;
70 } u;
71 } DisasCompare;
72
73 #define DISAS_EXCP 4
74
75 static void gen_op_calc_cc(DisasContext *s);
76
77 #ifdef DEBUG_INLINE_BRANCHES
78 static uint64_t inline_branch_hit[CC_OP_MAX];
79 static uint64_t inline_branch_miss[CC_OP_MAX];
80 #endif
81
82 static inline void debug_insn(uint64_t insn)
83 {
84 LOG_DISAS("insn: 0x%" PRIx64 "\n", insn);
85 }
86
87 static inline uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
88 {
89 if (!(s->tb->flags & FLAG_MASK_64)) {
90 if (s->tb->flags & FLAG_MASK_32) {
91 return pc | 0x80000000;
92 }
93 }
94 return pc;
95 }
96
97 void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
98 int flags)
99 {
100 int i;
101
102 if (env->cc_op > 3) {
103 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
104 env->psw.mask, env->psw.addr, cc_name(env->cc_op));
105 } else {
106 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
107 env->psw.mask, env->psw.addr, env->cc_op);
108 }
109
110 for (i = 0; i < 16; i++) {
111 cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
112 if ((i % 4) == 3) {
113 cpu_fprintf(f, "\n");
114 } else {
115 cpu_fprintf(f, " ");
116 }
117 }
118
119 for (i = 0; i < 16; i++) {
120 cpu_fprintf(f, "F%02d=%016" PRIx64, i, env->fregs[i].ll);
121 if ((i % 4) == 3) {
122 cpu_fprintf(f, "\n");
123 } else {
124 cpu_fprintf(f, " ");
125 }
126 }
127
128 #ifndef CONFIG_USER_ONLY
129 for (i = 0; i < 16; i++) {
130 cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
131 if ((i % 4) == 3) {
132 cpu_fprintf(f, "\n");
133 } else {
134 cpu_fprintf(f, " ");
135 }
136 }
137 #endif
138
139 #ifdef DEBUG_INLINE_BRANCHES
140 for (i = 0; i < CC_OP_MAX; i++) {
141 cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
142 inline_branch_miss[i], inline_branch_hit[i]);
143 }
144 #endif
145
146 cpu_fprintf(f, "\n");
147 }
148
149 static TCGv_i64 psw_addr;
150 static TCGv_i64 psw_mask;
151
152 static TCGv_i32 cc_op;
153 static TCGv_i64 cc_src;
154 static TCGv_i64 cc_dst;
155 static TCGv_i64 cc_vr;
156
157 static char cpu_reg_names[32][4];
158 static TCGv_i64 regs[16];
159 static TCGv_i64 fregs[16];
160
161 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
162
163 void s390x_translate_init(void)
164 {
165 int i;
166
167 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
168 psw_addr = tcg_global_mem_new_i64(TCG_AREG0,
169 offsetof(CPUS390XState, psw.addr),
170 "psw_addr");
171 psw_mask = tcg_global_mem_new_i64(TCG_AREG0,
172 offsetof(CPUS390XState, psw.mask),
173 "psw_mask");
174
175 cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUS390XState, cc_op),
176 "cc_op");
177 cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_src),
178 "cc_src");
179 cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_dst),
180 "cc_dst");
181 cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_vr),
182 "cc_vr");
183
184 for (i = 0; i < 16; i++) {
185 snprintf(cpu_reg_names[i], sizeof(cpu_reg_names[0]), "r%d", i);
186 regs[i] = tcg_global_mem_new(TCG_AREG0,
187 offsetof(CPUS390XState, regs[i]),
188 cpu_reg_names[i]);
189 }
190
191 for (i = 0; i < 16; i++) {
192 snprintf(cpu_reg_names[i + 16], sizeof(cpu_reg_names[0]), "f%d", i);
193 fregs[i] = tcg_global_mem_new(TCG_AREG0,
194 offsetof(CPUS390XState, fregs[i].d),
195 cpu_reg_names[i + 16]);
196 }
197
198 /* register helpers */
199 #define GEN_HELPER 2
200 #include "helper.h"
201 }
202
203 static inline TCGv_i64 load_reg(int reg)
204 {
205 TCGv_i64 r = tcg_temp_new_i64();
206 tcg_gen_mov_i64(r, regs[reg]);
207 return r;
208 }
209
210 static inline TCGv_i64 load_freg(int reg)
211 {
212 TCGv_i64 r = tcg_temp_new_i64();
213 tcg_gen_mov_i64(r, fregs[reg]);
214 return r;
215 }
216
217 static inline TCGv_i32 load_freg32(int reg)
218 {
219 TCGv_i32 r = tcg_temp_new_i32();
220 #if HOST_LONG_BITS == 32
221 tcg_gen_mov_i32(r, TCGV_HIGH(fregs[reg]));
222 #else
223 tcg_gen_shri_i64(MAKE_TCGV_I64(GET_TCGV_I32(r)), fregs[reg], 32);
224 #endif
225 return r;
226 }
227
228 static inline TCGv_i64 load_freg32_i64(int reg)
229 {
230 TCGv_i64 r = tcg_temp_new_i64();
231 tcg_gen_shri_i64(r, fregs[reg], 32);
232 return r;
233 }
234
235 static inline TCGv_i32 load_reg32(int reg)
236 {
237 TCGv_i32 r = tcg_temp_new_i32();
238 tcg_gen_trunc_i64_i32(r, regs[reg]);
239 return r;
240 }
241
242 static inline TCGv_i64 load_reg32_i64(int reg)
243 {
244 TCGv_i64 r = tcg_temp_new_i64();
245 tcg_gen_ext32s_i64(r, regs[reg]);
246 return r;
247 }
248
249 static inline void store_reg(int reg, TCGv_i64 v)
250 {
251 tcg_gen_mov_i64(regs[reg], v);
252 }
253
254 static inline void store_freg(int reg, TCGv_i64 v)
255 {
256 tcg_gen_mov_i64(fregs[reg], v);
257 }
258
259 static inline void store_reg32(int reg, TCGv_i32 v)
260 {
261 /* 32 bit register writes keep the upper half */
262 #if HOST_LONG_BITS == 32
263 tcg_gen_mov_i32(TCGV_LOW(regs[reg]), v);
264 #else
265 tcg_gen_deposit_i64(regs[reg], regs[reg],
266 MAKE_TCGV_I64(GET_TCGV_I32(v)), 0, 32);
267 #endif
268 }
269
270 static inline void store_reg32_i64(int reg, TCGv_i64 v)
271 {
272 /* 32 bit register writes keep the upper half */
273 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
274 }
275
276 static inline void store_reg32h_i64(int reg, TCGv_i64 v)
277 {
278 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 32, 32);
279 }
280
281 static inline void store_freg32(int reg, TCGv_i32 v)
282 {
283 /* 32 bit register writes keep the lower half */
284 #if HOST_LONG_BITS == 32
285 tcg_gen_mov_i32(TCGV_HIGH(fregs[reg]), v);
286 #else
287 tcg_gen_deposit_i64(fregs[reg], fregs[reg],
288 MAKE_TCGV_I64(GET_TCGV_I32(v)), 32, 32);
289 #endif
290 }
291
292 static inline void store_freg32_i64(int reg, TCGv_i64 v)
293 {
294 tcg_gen_deposit_i64(fregs[reg], fregs[reg], v, 32, 32);
295 }
296
297 static inline void return_low128(TCGv_i64 dest)
298 {
299 tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl));
300 }
301
302 static inline void update_psw_addr(DisasContext *s)
303 {
304 /* psw.addr */
305 tcg_gen_movi_i64(psw_addr, s->pc);
306 }
307
308 static inline void potential_page_fault(DisasContext *s)
309 {
310 #ifndef CONFIG_USER_ONLY
311 update_psw_addr(s);
312 gen_op_calc_cc(s);
313 #endif
314 }
315
316 static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
317 {
318 return (uint64_t)cpu_lduw_code(env, pc);
319 }
320
321 static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
322 {
323 return (uint64_t)(uint32_t)cpu_ldl_code(env, pc);
324 }
325
326 static inline uint64_t ld_code6(CPUS390XState *env, uint64_t pc)
327 {
328 return (ld_code2(env, pc) << 32) | ld_code4(env, pc + 2);
329 }
330
331 static inline int get_mem_index(DisasContext *s)
332 {
333 switch (s->tb->flags & FLAG_MASK_ASC) {
334 case PSW_ASC_PRIMARY >> 32:
335 return 0;
336 case PSW_ASC_SECONDARY >> 32:
337 return 1;
338 case PSW_ASC_HOME >> 32:
339 return 2;
340 default:
341 tcg_abort();
342 break;
343 }
344 }
345
346 static void gen_exception(int excp)
347 {
348 TCGv_i32 tmp = tcg_const_i32(excp);
349 gen_helper_exception(cpu_env, tmp);
350 tcg_temp_free_i32(tmp);
351 }
352
353 static void gen_program_exception(DisasContext *s, int code)
354 {
355 TCGv_i32 tmp;
356
357 /* Remember what pgm exeption this was. */
358 tmp = tcg_const_i32(code);
359 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
360 tcg_temp_free_i32(tmp);
361
362 tmp = tcg_const_i32(s->next_pc - s->pc);
363 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen));
364 tcg_temp_free_i32(tmp);
365
366 /* Advance past instruction. */
367 s->pc = s->next_pc;
368 update_psw_addr(s);
369
370 /* Save off cc. */
371 gen_op_calc_cc(s);
372
373 /* Trigger exception. */
374 gen_exception(EXCP_PGM);
375
376 /* End TB here. */
377 s->is_jmp = DISAS_EXCP;
378 }
379
380 static inline void gen_illegal_opcode(DisasContext *s)
381 {
382 gen_program_exception(s, PGM_SPECIFICATION);
383 }
384
385 static inline void check_privileged(DisasContext *s)
386 {
387 if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
388 gen_program_exception(s, PGM_PRIVILEGED);
389 }
390 }
391
392 static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
393 {
394 TCGv_i64 tmp;
395
396 /* 31-bitify the immediate part; register contents are dealt with below */
397 if (!(s->tb->flags & FLAG_MASK_64)) {
398 d2 &= 0x7fffffffUL;
399 }
400
401 if (x2) {
402 if (d2) {
403 tmp = tcg_const_i64(d2);
404 tcg_gen_add_i64(tmp, tmp, regs[x2]);
405 } else {
406 tmp = load_reg(x2);
407 }
408 if (b2) {
409 tcg_gen_add_i64(tmp, tmp, regs[b2]);
410 }
411 } else if (b2) {
412 if (d2) {
413 tmp = tcg_const_i64(d2);
414 tcg_gen_add_i64(tmp, tmp, regs[b2]);
415 } else {
416 tmp = load_reg(b2);
417 }
418 } else {
419 tmp = tcg_const_i64(d2);
420 }
421
422 /* 31-bit mode mask if there are values loaded from registers */
423 if (!(s->tb->flags & FLAG_MASK_64) && (x2 || b2)) {
424 tcg_gen_andi_i64(tmp, tmp, 0x7fffffffUL);
425 }
426
427 return tmp;
428 }
429
430 static inline void gen_op_movi_cc(DisasContext *s, uint32_t val)
431 {
432 s->cc_op = CC_OP_CONST0 + val;
433 }
434
435 static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst)
436 {
437 tcg_gen_discard_i64(cc_src);
438 tcg_gen_mov_i64(cc_dst, dst);
439 tcg_gen_discard_i64(cc_vr);
440 s->cc_op = op;
441 }
442
443 static void gen_op_update1_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 dst)
444 {
445 tcg_gen_discard_i64(cc_src);
446 tcg_gen_extu_i32_i64(cc_dst, dst);
447 tcg_gen_discard_i64(cc_vr);
448 s->cc_op = op;
449 }
450
451 static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
452 TCGv_i64 dst)
453 {
454 tcg_gen_mov_i64(cc_src, src);
455 tcg_gen_mov_i64(cc_dst, dst);
456 tcg_gen_discard_i64(cc_vr);
457 s->cc_op = op;
458 }
459
460 static void gen_op_update2_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 src,
461 TCGv_i32 dst)
462 {
463 tcg_gen_extu_i32_i64(cc_src, src);
464 tcg_gen_extu_i32_i64(cc_dst, dst);
465 tcg_gen_discard_i64(cc_vr);
466 s->cc_op = op;
467 }
468
469 static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
470 TCGv_i64 dst, TCGv_i64 vr)
471 {
472 tcg_gen_mov_i64(cc_src, src);
473 tcg_gen_mov_i64(cc_dst, dst);
474 tcg_gen_mov_i64(cc_vr, vr);
475 s->cc_op = op;
476 }
477
478 static inline void set_cc_nz_u32(DisasContext *s, TCGv_i32 val)
479 {
480 gen_op_update1_cc_i32(s, CC_OP_NZ, val);
481 }
482
483 static inline void set_cc_nz_u64(DisasContext *s, TCGv_i64 val)
484 {
485 gen_op_update1_cc_i64(s, CC_OP_NZ, val);
486 }
487
488 static inline void gen_set_cc_nz_f32(DisasContext *s, TCGv_i64 val)
489 {
490 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, val);
491 }
492
493 static inline void gen_set_cc_nz_f64(DisasContext *s, TCGv_i64 val)
494 {
495 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, val);
496 }
497
498 static inline void gen_set_cc_nz_f128(DisasContext *s, TCGv_i64 vh, TCGv_i64 vl)
499 {
500 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, vh, vl);
501 }
502
503 static inline void cmp_32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
504 enum cc_op cond)
505 {
506 gen_op_update2_cc_i32(s, cond, v1, v2);
507 }
508
509 static inline void cmp_64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
510 enum cc_op cond)
511 {
512 gen_op_update2_cc_i64(s, cond, v1, v2);
513 }
514
515 static inline void cmp_s32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
516 {
517 cmp_32(s, v1, v2, CC_OP_LTGT_32);
518 }
519
520 static inline void cmp_u32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
521 {
522 cmp_32(s, v1, v2, CC_OP_LTUGTU_32);
523 }
524
525 static inline void cmp_s32c(DisasContext *s, TCGv_i32 v1, int32_t v2)
526 {
527 /* XXX optimize for the constant? put it in s? */
528 TCGv_i32 tmp = tcg_const_i32(v2);
529 cmp_32(s, v1, tmp, CC_OP_LTGT_32);
530 tcg_temp_free_i32(tmp);
531 }
532
533 static inline void cmp_u32c(DisasContext *s, TCGv_i32 v1, uint32_t v2)
534 {
535 TCGv_i32 tmp = tcg_const_i32(v2);
536 cmp_32(s, v1, tmp, CC_OP_LTUGTU_32);
537 tcg_temp_free_i32(tmp);
538 }
539
540 static inline void cmp_s64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
541 {
542 cmp_64(s, v1, v2, CC_OP_LTGT_64);
543 }
544
545 static inline void cmp_u64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
546 {
547 cmp_64(s, v1, v2, CC_OP_LTUGTU_64);
548 }
549
550 static inline void cmp_s64c(DisasContext *s, TCGv_i64 v1, int64_t v2)
551 {
552 TCGv_i64 tmp = tcg_const_i64(v2);
553 cmp_s64(s, v1, tmp);
554 tcg_temp_free_i64(tmp);
555 }
556
557 static inline void cmp_u64c(DisasContext *s, TCGv_i64 v1, uint64_t v2)
558 {
559 TCGv_i64 tmp = tcg_const_i64(v2);
560 cmp_u64(s, v1, tmp);
561 tcg_temp_free_i64(tmp);
562 }
563
564 static inline void set_cc_s32(DisasContext *s, TCGv_i32 val)
565 {
566 gen_op_update1_cc_i32(s, CC_OP_LTGT0_32, val);
567 }
568
569 static inline void set_cc_s64(DisasContext *s, TCGv_i64 val)
570 {
571 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, val);
572 }
573
574 /* CC value is in env->cc_op */
575 static inline void set_cc_static(DisasContext *s)
576 {
577 tcg_gen_discard_i64(cc_src);
578 tcg_gen_discard_i64(cc_dst);
579 tcg_gen_discard_i64(cc_vr);
580 s->cc_op = CC_OP_STATIC;
581 }
582
583 static inline void gen_op_set_cc_op(DisasContext *s)
584 {
585 if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) {
586 tcg_gen_movi_i32(cc_op, s->cc_op);
587 }
588 }
589
590 static inline void gen_update_cc_op(DisasContext *s)
591 {
592 gen_op_set_cc_op(s);
593 }
594
595 /* calculates cc into cc_op */
596 static void gen_op_calc_cc(DisasContext *s)
597 {
598 TCGv_i32 local_cc_op = tcg_const_i32(s->cc_op);
599 TCGv_i64 dummy = tcg_const_i64(0);
600
601 switch (s->cc_op) {
602 case CC_OP_CONST0:
603 case CC_OP_CONST1:
604 case CC_OP_CONST2:
605 case CC_OP_CONST3:
606 /* s->cc_op is the cc value */
607 tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
608 break;
609 case CC_OP_STATIC:
610 /* env->cc_op already is the cc value */
611 break;
612 case CC_OP_NZ:
613 case CC_OP_ABS_64:
614 case CC_OP_NABS_64:
615 case CC_OP_ABS_32:
616 case CC_OP_NABS_32:
617 case CC_OP_LTGT0_32:
618 case CC_OP_LTGT0_64:
619 case CC_OP_COMP_32:
620 case CC_OP_COMP_64:
621 case CC_OP_NZ_F32:
622 case CC_OP_NZ_F64:
623 case CC_OP_FLOGR:
624 /* 1 argument */
625 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dummy);
626 break;
627 case CC_OP_ICM:
628 case CC_OP_LTGT_32:
629 case CC_OP_LTGT_64:
630 case CC_OP_LTUGTU_32:
631 case CC_OP_LTUGTU_64:
632 case CC_OP_TM_32:
633 case CC_OP_TM_64:
634 case CC_OP_SLA_32:
635 case CC_OP_SLA_64:
636 case CC_OP_NZ_F128:
637 /* 2 arguments */
638 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
639 break;
640 case CC_OP_ADD_64:
641 case CC_OP_ADDU_64:
642 case CC_OP_ADDC_64:
643 case CC_OP_SUB_64:
644 case CC_OP_SUBU_64:
645 case CC_OP_SUBB_64:
646 case CC_OP_ADD_32:
647 case CC_OP_ADDU_32:
648 case CC_OP_ADDC_32:
649 case CC_OP_SUB_32:
650 case CC_OP_SUBU_32:
651 case CC_OP_SUBB_32:
652 /* 3 arguments */
653 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc_vr);
654 break;
655 case CC_OP_DYNAMIC:
656 /* unknown operation - assume 3 arguments and cc_op in env */
657 gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr);
658 break;
659 default:
660 tcg_abort();
661 }
662
663 tcg_temp_free_i32(local_cc_op);
664 tcg_temp_free_i64(dummy);
665
666 /* We now have cc in cc_op as constant */
667 set_cc_static(s);
668 }
669
670 static inline void decode_rr(DisasContext *s, uint64_t insn, int *r1, int *r2)
671 {
672 debug_insn(insn);
673
674 *r1 = (insn >> 4) & 0xf;
675 *r2 = insn & 0xf;
676 }
677
678 static inline TCGv_i64 decode_rx(DisasContext *s, uint64_t insn, int *r1,
679 int *x2, int *b2, int *d2)
680 {
681 debug_insn(insn);
682
683 *r1 = (insn >> 20) & 0xf;
684 *x2 = (insn >> 16) & 0xf;
685 *b2 = (insn >> 12) & 0xf;
686 *d2 = insn & 0xfff;
687
688 return get_address(s, *x2, *b2, *d2);
689 }
690
691 static inline void decode_rs(DisasContext *s, uint64_t insn, int *r1, int *r3,
692 int *b2, int *d2)
693 {
694 debug_insn(insn);
695
696 *r1 = (insn >> 20) & 0xf;
697 /* aka m3 */
698 *r3 = (insn >> 16) & 0xf;
699 *b2 = (insn >> 12) & 0xf;
700 *d2 = insn & 0xfff;
701 }
702
703 static inline TCGv_i64 decode_si(DisasContext *s, uint64_t insn, int *i2,
704 int *b1, int *d1)
705 {
706 debug_insn(insn);
707
708 *i2 = (insn >> 16) & 0xff;
709 *b1 = (insn >> 12) & 0xf;
710 *d1 = insn & 0xfff;
711
712 return get_address(s, 0, *b1, *d1);
713 }
714
715 static int use_goto_tb(DisasContext *s, uint64_t dest)
716 {
717 /* NOTE: we handle the case where the TB spans two pages here */
718 return (((dest & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK)
719 || (dest & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK))
720 && !s->singlestep_enabled
721 && !(s->tb->cflags & CF_LAST_IO));
722 }
723
724 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong pc)
725 {
726 gen_update_cc_op(s);
727
728 if (use_goto_tb(s, pc)) {
729 tcg_gen_goto_tb(tb_num);
730 tcg_gen_movi_i64(psw_addr, pc);
731 tcg_gen_exit_tb((tcg_target_long)s->tb + tb_num);
732 } else {
733 /* jump to another page: currently not optimized */
734 tcg_gen_movi_i64(psw_addr, pc);
735 tcg_gen_exit_tb(0);
736 }
737 }
738
739 static inline void account_noninline_branch(DisasContext *s, int cc_op)
740 {
741 #ifdef DEBUG_INLINE_BRANCHES
742 inline_branch_miss[cc_op]++;
743 #endif
744 }
745
746 static inline void account_inline_branch(DisasContext *s, int cc_op)
747 {
748 #ifdef DEBUG_INLINE_BRANCHES
749 inline_branch_hit[cc_op]++;
750 #endif
751 }
752
753 /* Table of mask values to comparison codes, given a comparison as input.
754 For a true comparison CC=3 will never be set, but we treat this
755 conservatively for possible use when CC=3 indicates overflow. */
756 static const TCGCond ltgt_cond[16] = {
757 TCG_COND_NEVER, TCG_COND_NEVER, /* | | | x */
758 TCG_COND_GT, TCG_COND_NEVER, /* | | GT | x */
759 TCG_COND_LT, TCG_COND_NEVER, /* | LT | | x */
760 TCG_COND_NE, TCG_COND_NEVER, /* | LT | GT | x */
761 TCG_COND_EQ, TCG_COND_NEVER, /* EQ | | | x */
762 TCG_COND_GE, TCG_COND_NEVER, /* EQ | | GT | x */
763 TCG_COND_LE, TCG_COND_NEVER, /* EQ | LT | | x */
764 TCG_COND_ALWAYS, TCG_COND_ALWAYS, /* EQ | LT | GT | x */
765 };
766
767 /* Table of mask values to comparison codes, given a logic op as input.
768 For such, only CC=0 and CC=1 should be possible. */
769 static const TCGCond nz_cond[16] = {
770 /* | | x | x */
771 TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER,
772 /* | NE | x | x */
773 TCG_COND_NE, TCG_COND_NE, TCG_COND_NE, TCG_COND_NE,
774 /* EQ | | x | x */
775 TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ,
776 /* EQ | NE | x | x */
777 TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS,
778 };
779
780 /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
781 details required to generate a TCG comparison. */
782 static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
783 {
784 TCGCond cond;
785 enum cc_op old_cc_op = s->cc_op;
786
787 if (mask == 15 || mask == 0) {
788 c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER);
789 c->u.s32.a = cc_op;
790 c->u.s32.b = cc_op;
791 c->g1 = c->g2 = true;
792 c->is_64 = false;
793 return;
794 }
795
796 /* Find the TCG condition for the mask + cc op. */
797 switch (old_cc_op) {
798 case CC_OP_LTGT0_32:
799 case CC_OP_LTGT0_64:
800 case CC_OP_LTGT_32:
801 case CC_OP_LTGT_64:
802 cond = ltgt_cond[mask];
803 if (cond == TCG_COND_NEVER) {
804 goto do_dynamic;
805 }
806 account_inline_branch(s, old_cc_op);
807 break;
808
809 case CC_OP_LTUGTU_32:
810 case CC_OP_LTUGTU_64:
811 cond = tcg_unsigned_cond(ltgt_cond[mask]);
812 if (cond == TCG_COND_NEVER) {
813 goto do_dynamic;
814 }
815 account_inline_branch(s, old_cc_op);
816 break;
817
818 case CC_OP_NZ:
819 cond = nz_cond[mask];
820 if (cond == TCG_COND_NEVER) {
821 goto do_dynamic;
822 }
823 account_inline_branch(s, old_cc_op);
824 break;
825
826 case CC_OP_TM_32:
827 case CC_OP_TM_64:
828 switch (mask) {
829 case 8:
830 cond = TCG_COND_EQ;
831 break;
832 case 4 | 2 | 1:
833 cond = TCG_COND_NE;
834 break;
835 default:
836 goto do_dynamic;
837 }
838 account_inline_branch(s, old_cc_op);
839 break;
840
841 case CC_OP_ICM:
842 switch (mask) {
843 case 8:
844 cond = TCG_COND_EQ;
845 break;
846 case 4 | 2 | 1:
847 case 4 | 2:
848 cond = TCG_COND_NE;
849 break;
850 default:
851 goto do_dynamic;
852 }
853 account_inline_branch(s, old_cc_op);
854 break;
855
856 case CC_OP_FLOGR:
857 switch (mask & 0xa) {
858 case 8: /* src == 0 -> no one bit found */
859 cond = TCG_COND_EQ;
860 break;
861 case 2: /* src != 0 -> one bit found */
862 cond = TCG_COND_NE;
863 break;
864 default:
865 goto do_dynamic;
866 }
867 account_inline_branch(s, old_cc_op);
868 break;
869
870 default:
871 do_dynamic:
872 /* Calculate cc value. */
873 gen_op_calc_cc(s);
874 /* FALLTHRU */
875
876 case CC_OP_STATIC:
877 /* Jump based on CC. We'll load up the real cond below;
878 the assignment here merely avoids a compiler warning. */
879 account_noninline_branch(s, old_cc_op);
880 old_cc_op = CC_OP_STATIC;
881 cond = TCG_COND_NEVER;
882 break;
883 }
884
885 /* Load up the arguments of the comparison. */
886 c->is_64 = true;
887 c->g1 = c->g2 = false;
888 switch (old_cc_op) {
889 case CC_OP_LTGT0_32:
890 c->is_64 = false;
891 c->u.s32.a = tcg_temp_new_i32();
892 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_dst);
893 c->u.s32.b = tcg_const_i32(0);
894 break;
895 case CC_OP_LTGT_32:
896 case CC_OP_LTUGTU_32:
897 c->is_64 = false;
898 c->u.s32.a = tcg_temp_new_i32();
899 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_src);
900 c->u.s32.b = tcg_temp_new_i32();
901 tcg_gen_trunc_i64_i32(c->u.s32.b, cc_dst);
902 break;
903
904 case CC_OP_LTGT0_64:
905 case CC_OP_NZ:
906 case CC_OP_FLOGR:
907 c->u.s64.a = cc_dst;
908 c->u.s64.b = tcg_const_i64(0);
909 c->g1 = true;
910 break;
911 case CC_OP_LTGT_64:
912 case CC_OP_LTUGTU_64:
913 c->u.s64.a = cc_src;
914 c->u.s64.b = cc_dst;
915 c->g1 = c->g2 = true;
916 break;
917
918 case CC_OP_TM_32:
919 case CC_OP_TM_64:
920 case CC_OP_ICM:
921 c->u.s64.a = tcg_temp_new_i64();
922 c->u.s64.b = tcg_const_i64(0);
923 tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst);
924 break;
925
926 case CC_OP_STATIC:
927 c->is_64 = false;
928 c->u.s32.a = cc_op;
929 c->g1 = true;
930 switch (mask) {
931 case 0x8 | 0x4 | 0x2: /* cc != 3 */
932 cond = TCG_COND_NE;
933 c->u.s32.b = tcg_const_i32(3);
934 break;
935 case 0x8 | 0x4 | 0x1: /* cc != 2 */
936 cond = TCG_COND_NE;
937 c->u.s32.b = tcg_const_i32(2);
938 break;
939 case 0x8 | 0x2 | 0x1: /* cc != 1 */
940 cond = TCG_COND_NE;
941 c->u.s32.b = tcg_const_i32(1);
942 break;
943 case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
944 cond = TCG_COND_EQ;
945 c->g1 = false;
946 c->u.s32.a = tcg_temp_new_i32();
947 c->u.s32.b = tcg_const_i32(0);
948 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
949 break;
950 case 0x8 | 0x4: /* cc < 2 */
951 cond = TCG_COND_LTU;
952 c->u.s32.b = tcg_const_i32(2);
953 break;
954 case 0x8: /* cc == 0 */
955 cond = TCG_COND_EQ;
956 c->u.s32.b = tcg_const_i32(0);
957 break;
958 case 0x4 | 0x2 | 0x1: /* cc != 0 */
959 cond = TCG_COND_NE;
960 c->u.s32.b = tcg_const_i32(0);
961 break;
962 case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
963 cond = TCG_COND_NE;
964 c->g1 = false;
965 c->u.s32.a = tcg_temp_new_i32();
966 c->u.s32.b = tcg_const_i32(0);
967 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
968 break;
969 case 0x4: /* cc == 1 */
970 cond = TCG_COND_EQ;
971 c->u.s32.b = tcg_const_i32(1);
972 break;
973 case 0x2 | 0x1: /* cc > 1 */
974 cond = TCG_COND_GTU;
975 c->u.s32.b = tcg_const_i32(1);
976 break;
977 case 0x2: /* cc == 2 */
978 cond = TCG_COND_EQ;
979 c->u.s32.b = tcg_const_i32(2);
980 break;
981 case 0x1: /* cc == 3 */
982 cond = TCG_COND_EQ;
983 c->u.s32.b = tcg_const_i32(3);
984 break;
985 default:
986 /* CC is masked by something else: (8 >> cc) & mask. */
987 cond = TCG_COND_NE;
988 c->g1 = false;
989 c->u.s32.a = tcg_const_i32(8);
990 c->u.s32.b = tcg_const_i32(0);
991 tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op);
992 tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask);
993 break;
994 }
995 break;
996
997 default:
998 abort();
999 }
1000 c->cond = cond;
1001 }
1002
1003 static void free_compare(DisasCompare *c)
1004 {
1005 if (!c->g1) {
1006 if (c->is_64) {
1007 tcg_temp_free_i64(c->u.s64.a);
1008 } else {
1009 tcg_temp_free_i32(c->u.s32.a);
1010 }
1011 }
1012 if (!c->g2) {
1013 if (c->is_64) {
1014 tcg_temp_free_i64(c->u.s64.b);
1015 } else {
1016 tcg_temp_free_i32(c->u.s32.b);
1017 }
1018 }
1019 }
1020
1021 static void disas_b2(CPUS390XState *env, DisasContext *s, int op,
1022 uint32_t insn)
1023 {
1024 #ifndef CONFIG_USER_ONLY
1025 TCGv_i64 tmp, tmp2, tmp3;
1026 TCGv_i32 tmp32_1;
1027 int r1, r2;
1028 int r3, d2, b2;
1029
1030 r1 = (insn >> 4) & 0xf;
1031 r2 = insn & 0xf;
1032
1033 LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op, r1, r2);
1034
1035 switch (op) {
1036 case 0xb1: /* STFL D2(B2) [S] */
1037 /* Store Facility List (CPU features) at 200 */
1038 check_privileged(s);
1039 tmp2 = tcg_const_i64(0xc0000000);
1040 tmp = tcg_const_i64(200);
1041 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1042 tcg_temp_free_i64(tmp2);
1043 tcg_temp_free_i64(tmp);
1044 break;
1045 case 0xb2: /* LPSWE D2(B2) [S] */
1046 /* Load PSW Extended */
1047 check_privileged(s);
1048 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1049 tmp = get_address(s, 0, b2, d2);
1050 tmp2 = tcg_temp_new_i64();
1051 tmp3 = tcg_temp_new_i64();
1052 tcg_gen_qemu_ld64(tmp2, tmp, get_mem_index(s));
1053 tcg_gen_addi_i64(tmp, tmp, 8);
1054 tcg_gen_qemu_ld64(tmp3, tmp, get_mem_index(s));
1055 gen_helper_load_psw(cpu_env, tmp2, tmp3);
1056 /* we need to keep cc_op intact */
1057 s->is_jmp = DISAS_JUMP;
1058 tcg_temp_free_i64(tmp);
1059 tcg_temp_free_i64(tmp2);
1060 tcg_temp_free_i64(tmp3);
1061 break;
1062 case 0x20: /* SERVC R1,R2 [RRE] */
1063 /* SCLP Service call (PV hypercall) */
1064 check_privileged(s);
1065 potential_page_fault(s);
1066 tmp32_1 = load_reg32(r2);
1067 tmp = load_reg(r1);
1068 gen_helper_servc(cc_op, cpu_env, tmp32_1, tmp);
1069 set_cc_static(s);
1070 tcg_temp_free_i32(tmp32_1);
1071 tcg_temp_free_i64(tmp);
1072 break;
1073 default:
1074 #endif
1075 LOG_DISAS("illegal b2 operation 0x%x\n", op);
1076 gen_illegal_opcode(s);
1077 #ifndef CONFIG_USER_ONLY
1078 break;
1079 }
1080 #endif
1081 }
1082
1083 static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
1084 {
1085 unsigned char opc;
1086 uint64_t insn;
1087 int op;
1088
1089 opc = cpu_ldub_code(env, s->pc);
1090 LOG_DISAS("opc 0x%x\n", opc);
1091
1092 switch (opc) {
1093 case 0xb2:
1094 insn = ld_code4(env, s->pc);
1095 op = (insn >> 16) & 0xff;
1096 disas_b2(env, s, op, insn);
1097 break;
1098 default:
1099 qemu_log_mask(LOG_UNIMP, "unimplemented opcode 0x%x\n", opc);
1100 gen_illegal_opcode(s);
1101 break;
1102 }
1103 }
1104
1105 /* ====================================================================== */
1106 /* Define the insn format enumeration. */
1107 #define F0(N) FMT_##N,
1108 #define F1(N, X1) F0(N)
1109 #define F2(N, X1, X2) F0(N)
1110 #define F3(N, X1, X2, X3) F0(N)
1111 #define F4(N, X1, X2, X3, X4) F0(N)
1112 #define F5(N, X1, X2, X3, X4, X5) F0(N)
1113
1114 typedef enum {
1115 #include "insn-format.def"
1116 } DisasFormat;
1117
1118 #undef F0
1119 #undef F1
1120 #undef F2
1121 #undef F3
1122 #undef F4
1123 #undef F5
1124
1125 /* Define a structure to hold the decoded fields. We'll store each inside
1126 an array indexed by an enum. In order to conserve memory, we'll arrange
1127 for fields that do not exist at the same time to overlap, thus the "C"
1128 for compact. For checking purposes there is an "O" for original index
1129 as well that will be applied to availability bitmaps. */
1130
1131 enum DisasFieldIndexO {
1132 FLD_O_r1,
1133 FLD_O_r2,
1134 FLD_O_r3,
1135 FLD_O_m1,
1136 FLD_O_m3,
1137 FLD_O_m4,
1138 FLD_O_b1,
1139 FLD_O_b2,
1140 FLD_O_b4,
1141 FLD_O_d1,
1142 FLD_O_d2,
1143 FLD_O_d4,
1144 FLD_O_x2,
1145 FLD_O_l1,
1146 FLD_O_l2,
1147 FLD_O_i1,
1148 FLD_O_i2,
1149 FLD_O_i3,
1150 FLD_O_i4,
1151 FLD_O_i5
1152 };
1153
1154 enum DisasFieldIndexC {
1155 FLD_C_r1 = 0,
1156 FLD_C_m1 = 0,
1157 FLD_C_b1 = 0,
1158 FLD_C_i1 = 0,
1159
1160 FLD_C_r2 = 1,
1161 FLD_C_b2 = 1,
1162 FLD_C_i2 = 1,
1163
1164 FLD_C_r3 = 2,
1165 FLD_C_m3 = 2,
1166 FLD_C_i3 = 2,
1167
1168 FLD_C_m4 = 3,
1169 FLD_C_b4 = 3,
1170 FLD_C_i4 = 3,
1171 FLD_C_l1 = 3,
1172
1173 FLD_C_i5 = 4,
1174 FLD_C_d1 = 4,
1175
1176 FLD_C_d2 = 5,
1177
1178 FLD_C_d4 = 6,
1179 FLD_C_x2 = 6,
1180 FLD_C_l2 = 6,
1181
1182 NUM_C_FIELD = 7
1183 };
1184
1185 struct DisasFields {
1186 unsigned op:8;
1187 unsigned op2:8;
1188 unsigned presentC:16;
1189 unsigned int presentO;
1190 int c[NUM_C_FIELD];
1191 };
1192
1193 /* This is the way fields are to be accessed out of DisasFields. */
1194 #define have_field(S, F) have_field1((S), FLD_O_##F)
1195 #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
1196
1197 static bool have_field1(const DisasFields *f, enum DisasFieldIndexO c)
1198 {
1199 return (f->presentO >> c) & 1;
1200 }
1201
1202 static int get_field1(const DisasFields *f, enum DisasFieldIndexO o,
1203 enum DisasFieldIndexC c)
1204 {
1205 assert(have_field1(f, o));
1206 return f->c[c];
1207 }
1208
1209 /* Describe the layout of each field in each format. */
1210 typedef struct DisasField {
1211 unsigned int beg:8;
1212 unsigned int size:8;
1213 unsigned int type:2;
1214 unsigned int indexC:6;
1215 enum DisasFieldIndexO indexO:8;
1216 } DisasField;
1217
1218 typedef struct DisasFormatInfo {
1219 DisasField op[NUM_C_FIELD];
1220 } DisasFormatInfo;
1221
1222 #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
1223 #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
1224 #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1225 { BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
1226 #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1227 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1228 { 20, 12, 0, FLD_C_d##N, FLD_O_d##N }
1229 #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1230 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1231 #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1232 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1233 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1234 #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N }
1235 #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N }
1236
1237 #define F0(N) { { } },
1238 #define F1(N, X1) { { X1 } },
1239 #define F2(N, X1, X2) { { X1, X2 } },
1240 #define F3(N, X1, X2, X3) { { X1, X2, X3 } },
1241 #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
1242 #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
1243
1244 static const DisasFormatInfo format_info[] = {
1245 #include "insn-format.def"
1246 };
1247
1248 #undef F0
1249 #undef F1
1250 #undef F2
1251 #undef F3
1252 #undef F4
1253 #undef F5
1254 #undef R
1255 #undef M
1256 #undef BD
1257 #undef BXD
1258 #undef BDL
1259 #undef BXDL
1260 #undef I
1261 #undef L
1262
1263 /* Generally, we'll extract operands into this structures, operate upon
1264 them, and store them back. See the "in1", "in2", "prep", "wout" sets
1265 of routines below for more details. */
1266 typedef struct {
1267 bool g_out, g_out2, g_in1, g_in2;
1268 TCGv_i64 out, out2, in1, in2;
1269 TCGv_i64 addr1;
1270 } DisasOps;
1271
1272 /* Return values from translate_one, indicating the state of the TB. */
1273 typedef enum {
1274 /* Continue the TB. */
1275 NO_EXIT,
1276 /* We have emitted one or more goto_tb. No fixup required. */
1277 EXIT_GOTO_TB,
1278 /* We are not using a goto_tb (for whatever reason), but have updated
1279 the PC (for whatever reason), so there's no need to do it again on
1280 exiting the TB. */
1281 EXIT_PC_UPDATED,
1282 /* We are exiting the TB, but have neither emitted a goto_tb, nor
1283 updated the PC for the next instruction to be executed. */
1284 EXIT_PC_STALE,
1285 /* We are ending the TB with a noreturn function call, e.g. longjmp.
1286 No following code will be executed. */
1287 EXIT_NORETURN,
1288 } ExitStatus;
1289
1290 typedef enum DisasFacility {
1291 FAC_Z, /* zarch (default) */
1292 FAC_CASS, /* compare and swap and store */
1293 FAC_CASS2, /* compare and swap and store 2*/
1294 FAC_DFP, /* decimal floating point */
1295 FAC_DFPR, /* decimal floating point rounding */
1296 FAC_DO, /* distinct operands */
1297 FAC_EE, /* execute extensions */
1298 FAC_EI, /* extended immediate */
1299 FAC_FPE, /* floating point extension */
1300 FAC_FPSSH, /* floating point support sign handling */
1301 FAC_FPRGR, /* FPR-GR transfer */
1302 FAC_GIE, /* general instructions extension */
1303 FAC_HFP_MA, /* HFP multiply-and-add/subtract */
1304 FAC_HW, /* high-word */
1305 FAC_IEEEE_SIM, /* IEEE exception sumilation */
1306 FAC_LOC, /* load/store on condition */
1307 FAC_LD, /* long displacement */
1308 FAC_PC, /* population count */
1309 FAC_SCF, /* store clock fast */
1310 FAC_SFLE, /* store facility list extended */
1311 } DisasFacility;
1312
1313 struct DisasInsn {
1314 unsigned opc:16;
1315 DisasFormat fmt:6;
1316 DisasFacility fac:6;
1317
1318 const char *name;
1319
1320 void (*help_in1)(DisasContext *, DisasFields *, DisasOps *);
1321 void (*help_in2)(DisasContext *, DisasFields *, DisasOps *);
1322 void (*help_prep)(DisasContext *, DisasFields *, DisasOps *);
1323 void (*help_wout)(DisasContext *, DisasFields *, DisasOps *);
1324 void (*help_cout)(DisasContext *, DisasOps *);
1325 ExitStatus (*help_op)(DisasContext *, DisasOps *);
1326
1327 uint64_t data;
1328 };
1329
1330 /* ====================================================================== */
1331 /* Miscelaneous helpers, used by several operations. */
1332
1333 static void help_l2_shift(DisasContext *s, DisasFields *f,
1334 DisasOps *o, int mask)
1335 {
1336 int b2 = get_field(f, b2);
1337 int d2 = get_field(f, d2);
1338
1339 if (b2 == 0) {
1340 o->in2 = tcg_const_i64(d2 & mask);
1341 } else {
1342 o->in2 = get_address(s, 0, b2, d2);
1343 tcg_gen_andi_i64(o->in2, o->in2, mask);
1344 }
1345 }
1346
1347 static ExitStatus help_goto_direct(DisasContext *s, uint64_t dest)
1348 {
1349 if (dest == s->next_pc) {
1350 return NO_EXIT;
1351 }
1352 if (use_goto_tb(s, dest)) {
1353 gen_update_cc_op(s);
1354 tcg_gen_goto_tb(0);
1355 tcg_gen_movi_i64(psw_addr, dest);
1356 tcg_gen_exit_tb((tcg_target_long)s->tb);
1357 return EXIT_GOTO_TB;
1358 } else {
1359 tcg_gen_movi_i64(psw_addr, dest);
1360 return EXIT_PC_UPDATED;
1361 }
1362 }
1363
1364 static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
1365 bool is_imm, int imm, TCGv_i64 cdest)
1366 {
1367 ExitStatus ret;
1368 uint64_t dest = s->pc + 2 * imm;
1369 int lab;
1370
1371 /* Take care of the special cases first. */
1372 if (c->cond == TCG_COND_NEVER) {
1373 ret = NO_EXIT;
1374 goto egress;
1375 }
1376 if (is_imm) {
1377 if (dest == s->next_pc) {
1378 /* Branch to next. */
1379 ret = NO_EXIT;
1380 goto egress;
1381 }
1382 if (c->cond == TCG_COND_ALWAYS) {
1383 ret = help_goto_direct(s, dest);
1384 goto egress;
1385 }
1386 } else {
1387 if (TCGV_IS_UNUSED_I64(cdest)) {
1388 /* E.g. bcr %r0 -> no branch. */
1389 ret = NO_EXIT;
1390 goto egress;
1391 }
1392 if (c->cond == TCG_COND_ALWAYS) {
1393 tcg_gen_mov_i64(psw_addr, cdest);
1394 ret = EXIT_PC_UPDATED;
1395 goto egress;
1396 }
1397 }
1398
1399 if (use_goto_tb(s, s->next_pc)) {
1400 if (is_imm && use_goto_tb(s, dest)) {
1401 /* Both exits can use goto_tb. */
1402 gen_update_cc_op(s);
1403
1404 lab = gen_new_label();
1405 if (c->is_64) {
1406 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1407 } else {
1408 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1409 }
1410
1411 /* Branch not taken. */
1412 tcg_gen_goto_tb(0);
1413 tcg_gen_movi_i64(psw_addr, s->next_pc);
1414 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
1415
1416 /* Branch taken. */
1417 gen_set_label(lab);
1418 tcg_gen_goto_tb(1);
1419 tcg_gen_movi_i64(psw_addr, dest);
1420 tcg_gen_exit_tb((tcg_target_long)s->tb + 1);
1421
1422 ret = EXIT_GOTO_TB;
1423 } else {
1424 /* Fallthru can use goto_tb, but taken branch cannot. */
1425 /* Store taken branch destination before the brcond. This
1426 avoids having to allocate a new local temp to hold it.
1427 We'll overwrite this in the not taken case anyway. */
1428 if (!is_imm) {
1429 tcg_gen_mov_i64(psw_addr, cdest);
1430 }
1431
1432 lab = gen_new_label();
1433 if (c->is_64) {
1434 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1435 } else {
1436 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1437 }
1438
1439 /* Branch not taken. */
1440 gen_update_cc_op(s);
1441 tcg_gen_goto_tb(0);
1442 tcg_gen_movi_i64(psw_addr, s->next_pc);
1443 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
1444
1445 gen_set_label(lab);
1446 if (is_imm) {
1447 tcg_gen_movi_i64(psw_addr, dest);
1448 }
1449 ret = EXIT_PC_UPDATED;
1450 }
1451 } else {
1452 /* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
1453 Most commonly we're single-stepping or some other condition that
1454 disables all use of goto_tb. Just update the PC and exit. */
1455
1456 TCGv_i64 next = tcg_const_i64(s->next_pc);
1457 if (is_imm) {
1458 cdest = tcg_const_i64(dest);
1459 }
1460
1461 if (c->is_64) {
1462 tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b,
1463 cdest, next);
1464 } else {
1465 TCGv_i32 t0 = tcg_temp_new_i32();
1466 TCGv_i64 t1 = tcg_temp_new_i64();
1467 TCGv_i64 z = tcg_const_i64(0);
1468 tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b);
1469 tcg_gen_extu_i32_i64(t1, t0);
1470 tcg_temp_free_i32(t0);
1471 tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next);
1472 tcg_temp_free_i64(t1);
1473 tcg_temp_free_i64(z);
1474 }
1475
1476 if (is_imm) {
1477 tcg_temp_free_i64(cdest);
1478 }
1479 tcg_temp_free_i64(next);
1480
1481 ret = EXIT_PC_UPDATED;
1482 }
1483
1484 egress:
1485 free_compare(c);
1486 return ret;
1487 }
1488
1489 /* ====================================================================== */
1490 /* The operations. These perform the bulk of the work for any insn,
1491 usually after the operands have been loaded and output initialized. */
1492
1493 static ExitStatus op_abs(DisasContext *s, DisasOps *o)
1494 {
1495 gen_helper_abs_i64(o->out, o->in2);
1496 return NO_EXIT;
1497 }
1498
1499 static ExitStatus op_absf32(DisasContext *s, DisasOps *o)
1500 {
1501 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffull);
1502 return NO_EXIT;
1503 }
1504
1505 static ExitStatus op_absf64(DisasContext *s, DisasOps *o)
1506 {
1507 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull);
1508 return NO_EXIT;
1509 }
1510
1511 static ExitStatus op_absf128(DisasContext *s, DisasOps *o)
1512 {
1513 tcg_gen_andi_i64(o->out, o->in1, 0x7fffffffffffffffull);
1514 tcg_gen_mov_i64(o->out2, o->in2);
1515 return NO_EXIT;
1516 }
1517
1518 static ExitStatus op_add(DisasContext *s, DisasOps *o)
1519 {
1520 tcg_gen_add_i64(o->out, o->in1, o->in2);
1521 return NO_EXIT;
1522 }
1523
1524 static ExitStatus op_addc(DisasContext *s, DisasOps *o)
1525 {
1526 TCGv_i64 cc;
1527
1528 tcg_gen_add_i64(o->out, o->in1, o->in2);
1529
1530 /* XXX possible optimization point */
1531 gen_op_calc_cc(s);
1532 cc = tcg_temp_new_i64();
1533 tcg_gen_extu_i32_i64(cc, cc_op);
1534 tcg_gen_shri_i64(cc, cc, 1);
1535
1536 tcg_gen_add_i64(o->out, o->out, cc);
1537 tcg_temp_free_i64(cc);
1538 return NO_EXIT;
1539 }
1540
1541 static ExitStatus op_aeb(DisasContext *s, DisasOps *o)
1542 {
1543 gen_helper_aeb(o->out, cpu_env, o->in1, o->in2);
1544 return NO_EXIT;
1545 }
1546
1547 static ExitStatus op_adb(DisasContext *s, DisasOps *o)
1548 {
1549 gen_helper_adb(o->out, cpu_env, o->in1, o->in2);
1550 return NO_EXIT;
1551 }
1552
1553 static ExitStatus op_axb(DisasContext *s, DisasOps *o)
1554 {
1555 gen_helper_axb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
1556 return_low128(o->out2);
1557 return NO_EXIT;
1558 }
1559
1560 static ExitStatus op_and(DisasContext *s, DisasOps *o)
1561 {
1562 tcg_gen_and_i64(o->out, o->in1, o->in2);
1563 return NO_EXIT;
1564 }
1565
1566 static ExitStatus op_andi(DisasContext *s, DisasOps *o)
1567 {
1568 int shift = s->insn->data & 0xff;
1569 int size = s->insn->data >> 8;
1570 uint64_t mask = ((1ull << size) - 1) << shift;
1571
1572 assert(!o->g_in2);
1573 tcg_gen_shli_i64(o->in2, o->in2, shift);
1574 tcg_gen_ori_i64(o->in2, o->in2, ~mask);
1575 tcg_gen_and_i64(o->out, o->in1, o->in2);
1576
1577 /* Produce the CC from only the bits manipulated. */
1578 tcg_gen_andi_i64(cc_dst, o->out, mask);
1579 set_cc_nz_u64(s, cc_dst);
1580 return NO_EXIT;
1581 }
1582
1583 static ExitStatus op_bas(DisasContext *s, DisasOps *o)
1584 {
1585 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1586 if (!TCGV_IS_UNUSED_I64(o->in2)) {
1587 tcg_gen_mov_i64(psw_addr, o->in2);
1588 return EXIT_PC_UPDATED;
1589 } else {
1590 return NO_EXIT;
1591 }
1592 }
1593
1594 static ExitStatus op_basi(DisasContext *s, DisasOps *o)
1595 {
1596 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1597 return help_goto_direct(s, s->pc + 2 * get_field(s->fields, i2));
1598 }
1599
1600 static ExitStatus op_bc(DisasContext *s, DisasOps *o)
1601 {
1602 int m1 = get_field(s->fields, m1);
1603 bool is_imm = have_field(s->fields, i2);
1604 int imm = is_imm ? get_field(s->fields, i2) : 0;
1605 DisasCompare c;
1606
1607 disas_jcc(s, &c, m1);
1608 return help_branch(s, &c, is_imm, imm, o->in2);
1609 }
1610
1611 static ExitStatus op_bct32(DisasContext *s, DisasOps *o)
1612 {
1613 int r1 = get_field(s->fields, r1);
1614 bool is_imm = have_field(s->fields, i2);
1615 int imm = is_imm ? get_field(s->fields, i2) : 0;
1616 DisasCompare c;
1617 TCGv_i64 t;
1618
1619 c.cond = TCG_COND_NE;
1620 c.is_64 = false;
1621 c.g1 = false;
1622 c.g2 = false;
1623
1624 t = tcg_temp_new_i64();
1625 tcg_gen_subi_i64(t, regs[r1], 1);
1626 store_reg32_i64(r1, t);
1627 c.u.s32.a = tcg_temp_new_i32();
1628 c.u.s32.b = tcg_const_i32(0);
1629 tcg_gen_trunc_i64_i32(c.u.s32.a, t);
1630 tcg_temp_free_i64(t);
1631
1632 return help_branch(s, &c, is_imm, imm, o->in2);
1633 }
1634
1635 static ExitStatus op_bct64(DisasContext *s, DisasOps *o)
1636 {
1637 int r1 = get_field(s->fields, r1);
1638 bool is_imm = have_field(s->fields, i2);
1639 int imm = is_imm ? get_field(s->fields, i2) : 0;
1640 DisasCompare c;
1641
1642 c.cond = TCG_COND_NE;
1643 c.is_64 = true;
1644 c.g1 = true;
1645 c.g2 = false;
1646
1647 tcg_gen_subi_i64(regs[r1], regs[r1], 1);
1648 c.u.s64.a = regs[r1];
1649 c.u.s64.b = tcg_const_i64(0);
1650
1651 return help_branch(s, &c, is_imm, imm, o->in2);
1652 }
1653
1654 static ExitStatus op_ceb(DisasContext *s, DisasOps *o)
1655 {
1656 gen_helper_ceb(cc_op, cpu_env, o->in1, o->in2);
1657 set_cc_static(s);
1658 return NO_EXIT;
1659 }
1660
1661 static ExitStatus op_cdb(DisasContext *s, DisasOps *o)
1662 {
1663 gen_helper_cdb(cc_op, cpu_env, o->in1, o->in2);
1664 set_cc_static(s);
1665 return NO_EXIT;
1666 }
1667
1668 static ExitStatus op_cxb(DisasContext *s, DisasOps *o)
1669 {
1670 gen_helper_cxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2);
1671 set_cc_static(s);
1672 return NO_EXIT;
1673 }
1674
1675 static ExitStatus op_cfeb(DisasContext *s, DisasOps *o)
1676 {
1677 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1678 gen_helper_cfeb(o->out, cpu_env, o->in2, m3);
1679 tcg_temp_free_i32(m3);
1680 gen_set_cc_nz_f32(s, o->in2);
1681 return NO_EXIT;
1682 }
1683
1684 static ExitStatus op_cfdb(DisasContext *s, DisasOps *o)
1685 {
1686 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1687 gen_helper_cfdb(o->out, cpu_env, o->in2, m3);
1688 tcg_temp_free_i32(m3);
1689 gen_set_cc_nz_f64(s, o->in2);
1690 return NO_EXIT;
1691 }
1692
1693 static ExitStatus op_cfxb(DisasContext *s, DisasOps *o)
1694 {
1695 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1696 gen_helper_cfxb(o->out, cpu_env, o->in1, o->in2, m3);
1697 tcg_temp_free_i32(m3);
1698 gen_set_cc_nz_f128(s, o->in1, o->in2);
1699 return NO_EXIT;
1700 }
1701
1702 static ExitStatus op_cgeb(DisasContext *s, DisasOps *o)
1703 {
1704 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1705 gen_helper_cgeb(o->out, cpu_env, o->in2, m3);
1706 tcg_temp_free_i32(m3);
1707 gen_set_cc_nz_f32(s, o->in2);
1708 return NO_EXIT;
1709 }
1710
1711 static ExitStatus op_cgdb(DisasContext *s, DisasOps *o)
1712 {
1713 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1714 gen_helper_cgdb(o->out, cpu_env, o->in2, m3);
1715 tcg_temp_free_i32(m3);
1716 gen_set_cc_nz_f64(s, o->in2);
1717 return NO_EXIT;
1718 }
1719
1720 static ExitStatus op_cgxb(DisasContext *s, DisasOps *o)
1721 {
1722 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1723 gen_helper_cgxb(o->out, cpu_env, o->in1, o->in2, m3);
1724 tcg_temp_free_i32(m3);
1725 gen_set_cc_nz_f128(s, o->in1, o->in2);
1726 return NO_EXIT;
1727 }
1728
1729 static ExitStatus op_cegb(DisasContext *s, DisasOps *o)
1730 {
1731 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1732 gen_helper_cegb(o->out, cpu_env, o->in2, m3);
1733 tcg_temp_free_i32(m3);
1734 return NO_EXIT;
1735 }
1736
1737 static ExitStatus op_cdgb(DisasContext *s, DisasOps *o)
1738 {
1739 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1740 gen_helper_cdgb(o->out, cpu_env, o->in2, m3);
1741 tcg_temp_free_i32(m3);
1742 return NO_EXIT;
1743 }
1744
1745 static ExitStatus op_cxgb(DisasContext *s, DisasOps *o)
1746 {
1747 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1748 gen_helper_cxgb(o->out, cpu_env, o->in2, m3);
1749 tcg_temp_free_i32(m3);
1750 return_low128(o->out2);
1751 return NO_EXIT;
1752 }
1753
1754 static ExitStatus op_cksm(DisasContext *s, DisasOps *o)
1755 {
1756 int r2 = get_field(s->fields, r2);
1757 TCGv_i64 len = tcg_temp_new_i64();
1758
1759 potential_page_fault(s);
1760 gen_helper_cksm(len, cpu_env, o->in1, o->in2, regs[r2 + 1]);
1761 set_cc_static(s);
1762 return_low128(o->out);
1763
1764 tcg_gen_add_i64(regs[r2], regs[r2], len);
1765 tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len);
1766 tcg_temp_free_i64(len);
1767
1768 return NO_EXIT;
1769 }
1770
1771 static ExitStatus op_clc(DisasContext *s, DisasOps *o)
1772 {
1773 int l = get_field(s->fields, l1);
1774 TCGv_i32 vl;
1775
1776 switch (l + 1) {
1777 case 1:
1778 tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s));
1779 tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s));
1780 break;
1781 case 2:
1782 tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s));
1783 tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s));
1784 break;
1785 case 4:
1786 tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s));
1787 tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s));
1788 break;
1789 case 8:
1790 tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s));
1791 tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s));
1792 break;
1793 default:
1794 potential_page_fault(s);
1795 vl = tcg_const_i32(l);
1796 gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
1797 tcg_temp_free_i32(vl);
1798 set_cc_static(s);
1799 return NO_EXIT;
1800 }
1801 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
1802 return NO_EXIT;
1803 }
1804
1805 static ExitStatus op_clcle(DisasContext *s, DisasOps *o)
1806 {
1807 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
1808 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
1809 potential_page_fault(s);
1810 gen_helper_clcle(cc_op, cpu_env, r1, o->in2, r3);
1811 tcg_temp_free_i32(r1);
1812 tcg_temp_free_i32(r3);
1813 set_cc_static(s);
1814 return NO_EXIT;
1815 }
1816
1817 static ExitStatus op_clm(DisasContext *s, DisasOps *o)
1818 {
1819 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1820 TCGv_i32 t1 = tcg_temp_new_i32();
1821 tcg_gen_trunc_i64_i32(t1, o->in1);
1822 potential_page_fault(s);
1823 gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2);
1824 set_cc_static(s);
1825 tcg_temp_free_i32(t1);
1826 tcg_temp_free_i32(m3);
1827 return NO_EXIT;
1828 }
1829
1830 static ExitStatus op_clst(DisasContext *s, DisasOps *o)
1831 {
1832 potential_page_fault(s);
1833 gen_helper_clst(o->in1, cpu_env, regs[0], o->in1, o->in2);
1834 set_cc_static(s);
1835 return_low128(o->in2);
1836 return NO_EXIT;
1837 }
1838
1839 static ExitStatus op_cs(DisasContext *s, DisasOps *o)
1840 {
1841 int r3 = get_field(s->fields, r3);
1842 potential_page_fault(s);
1843 gen_helper_cs(o->out, cpu_env, o->in1, o->in2, regs[r3]);
1844 set_cc_static(s);
1845 return NO_EXIT;
1846 }
1847
1848 static ExitStatus op_csg(DisasContext *s, DisasOps *o)
1849 {
1850 int r3 = get_field(s->fields, r3);
1851 potential_page_fault(s);
1852 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, regs[r3]);
1853 set_cc_static(s);
1854 return NO_EXIT;
1855 }
1856
1857 #ifndef CONFIG_USER_ONLY
1858 static ExitStatus op_csp(DisasContext *s, DisasOps *o)
1859 {
1860 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
1861 check_privileged(s);
1862 gen_helper_csp(cc_op, cpu_env, r1, o->in2);
1863 tcg_temp_free_i32(r1);
1864 set_cc_static(s);
1865 return NO_EXIT;
1866 }
1867 #endif
1868
1869 static ExitStatus op_cds(DisasContext *s, DisasOps *o)
1870 {
1871 int r3 = get_field(s->fields, r3);
1872 TCGv_i64 in3 = tcg_temp_new_i64();
1873 tcg_gen_deposit_i64(in3, regs[r3 + 1], regs[r3], 32, 32);
1874 potential_page_fault(s);
1875 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, in3);
1876 tcg_temp_free_i64(in3);
1877 set_cc_static(s);
1878 return NO_EXIT;
1879 }
1880
1881 static ExitStatus op_cdsg(DisasContext *s, DisasOps *o)
1882 {
1883 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
1884 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
1885 potential_page_fault(s);
1886 /* XXX rewrite in tcg */
1887 gen_helper_cdsg(cc_op, cpu_env, r1, o->in2, r3);
1888 set_cc_static(s);
1889 return NO_EXIT;
1890 }
1891
1892 static ExitStatus op_cvd(DisasContext *s, DisasOps *o)
1893 {
1894 TCGv_i64 t1 = tcg_temp_new_i64();
1895 TCGv_i32 t2 = tcg_temp_new_i32();
1896 tcg_gen_trunc_i64_i32(t2, o->in1);
1897 gen_helper_cvd(t1, t2);
1898 tcg_temp_free_i32(t2);
1899 tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
1900 tcg_temp_free_i64(t1);
1901 return NO_EXIT;
1902 }
1903
1904 #ifndef CONFIG_USER_ONLY
1905 static ExitStatus op_diag(DisasContext *s, DisasOps *o)
1906 {
1907 TCGv_i32 tmp;
1908
1909 check_privileged(s);
1910 potential_page_fault(s);
1911
1912 /* We pretend the format is RX_a so that D2 is the field we want. */
1913 tmp = tcg_const_i32(get_field(s->fields, d2) & 0xfff);
1914 gen_helper_diag(regs[2], cpu_env, tmp, regs[2], regs[1]);
1915 tcg_temp_free_i32(tmp);
1916 return NO_EXIT;
1917 }
1918 #endif
1919
1920 static ExitStatus op_divs32(DisasContext *s, DisasOps *o)
1921 {
1922 gen_helper_divs32(o->out2, cpu_env, o->in1, o->in2);
1923 return_low128(o->out);
1924 return NO_EXIT;
1925 }
1926
1927 static ExitStatus op_divu32(DisasContext *s, DisasOps *o)
1928 {
1929 gen_helper_divu32(o->out2, cpu_env, o->in1, o->in2);
1930 return_low128(o->out);
1931 return NO_EXIT;
1932 }
1933
1934 static ExitStatus op_divs64(DisasContext *s, DisasOps *o)
1935 {
1936 gen_helper_divs64(o->out2, cpu_env, o->in1, o->in2);
1937 return_low128(o->out);
1938 return NO_EXIT;
1939 }
1940
1941 static ExitStatus op_divu64(DisasContext *s, DisasOps *o)
1942 {
1943 gen_helper_divu64(o->out2, cpu_env, o->out, o->out2, o->in2);
1944 return_low128(o->out);
1945 return NO_EXIT;
1946 }
1947
1948 static ExitStatus op_deb(DisasContext *s, DisasOps *o)
1949 {
1950 gen_helper_deb(o->out, cpu_env, o->in1, o->in2);
1951 return NO_EXIT;
1952 }
1953
1954 static ExitStatus op_ddb(DisasContext *s, DisasOps *o)
1955 {
1956 gen_helper_ddb(o->out, cpu_env, o->in1, o->in2);
1957 return NO_EXIT;
1958 }
1959
1960 static ExitStatus op_dxb(DisasContext *s, DisasOps *o)
1961 {
1962 gen_helper_dxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
1963 return_low128(o->out2);
1964 return NO_EXIT;
1965 }
1966
1967 static ExitStatus op_ear(DisasContext *s, DisasOps *o)
1968 {
1969 int r2 = get_field(s->fields, r2);
1970 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, aregs[r2]));
1971 return NO_EXIT;
1972 }
1973
1974 static ExitStatus op_efpc(DisasContext *s, DisasOps *o)
1975 {
1976 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, fpc));
1977 return NO_EXIT;
1978 }
1979
1980 static ExitStatus op_ex(DisasContext *s, DisasOps *o)
1981 {
1982 /* ??? Perhaps a better way to implement EXECUTE is to set a bit in
1983 tb->flags, (ab)use the tb->cs_base field as the address of
1984 the template in memory, and grab 8 bits of tb->flags/cflags for
1985 the contents of the register. We would then recognize all this
1986 in gen_intermediate_code_internal, generating code for exactly
1987 one instruction. This new TB then gets executed normally.
1988
1989 On the other hand, this seems to be mostly used for modifying
1990 MVC inside of memcpy, which needs a helper call anyway. So
1991 perhaps this doesn't bear thinking about any further. */
1992
1993 TCGv_i64 tmp;
1994
1995 update_psw_addr(s);
1996 gen_op_calc_cc(s);
1997
1998 tmp = tcg_const_i64(s->next_pc);
1999 gen_helper_ex(cc_op, cpu_env, cc_op, o->in1, o->in2, tmp);
2000 tcg_temp_free_i64(tmp);
2001
2002 set_cc_static(s);
2003 return NO_EXIT;
2004 }
2005
2006 static ExitStatus op_flogr(DisasContext *s, DisasOps *o)
2007 {
2008 /* We'll use the original input for cc computation, since we get to
2009 compare that against 0, which ought to be better than comparing
2010 the real output against 64. It also lets cc_dst be a convenient
2011 temporary during our computation. */
2012 gen_op_update1_cc_i64(s, CC_OP_FLOGR, o->in2);
2013
2014 /* R1 = IN ? CLZ(IN) : 64. */
2015 gen_helper_clz(o->out, o->in2);
2016
2017 /* R1+1 = IN & ~(found bit). Note that we may attempt to shift this
2018 value by 64, which is undefined. But since the shift is 64 iff the
2019 input is zero, we still get the correct result after and'ing. */
2020 tcg_gen_movi_i64(o->out2, 0x8000000000000000ull);
2021 tcg_gen_shr_i64(o->out2, o->out2, o->out);
2022 tcg_gen_andc_i64(o->out2, cc_dst, o->out2);
2023 return NO_EXIT;
2024 }
2025
2026 static ExitStatus op_icm(DisasContext *s, DisasOps *o)
2027 {
2028 int m3 = get_field(s->fields, m3);
2029 int pos, len, base = s->insn->data;
2030 TCGv_i64 tmp = tcg_temp_new_i64();
2031 uint64_t ccm;
2032
2033 switch (m3) {
2034 case 0xf:
2035 /* Effectively a 32-bit load. */
2036 tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s));
2037 len = 32;
2038 goto one_insert;
2039
2040 case 0xc:
2041 case 0x6:
2042 case 0x3:
2043 /* Effectively a 16-bit load. */
2044 tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s));
2045 len = 16;
2046 goto one_insert;
2047
2048 case 0x8:
2049 case 0x4:
2050 case 0x2:
2051 case 0x1:
2052 /* Effectively an 8-bit load. */
2053 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2054 len = 8;
2055 goto one_insert;
2056
2057 one_insert:
2058 pos = base + ctz32(m3) * 8;
2059 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len);
2060 ccm = ((1ull << len) - 1) << pos;
2061 break;
2062
2063 default:
2064 /* This is going to be a sequence of loads and inserts. */
2065 pos = base + 32 - 8;
2066 ccm = 0;
2067 while (m3) {
2068 if (m3 & 0x8) {
2069 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2070 tcg_gen_addi_i64(o->in2, o->in2, 1);
2071 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
2072 ccm |= 0xff << pos;
2073 }
2074 m3 = (m3 << 1) & 0xf;
2075 pos -= 8;
2076 }
2077 break;
2078 }
2079
2080 tcg_gen_movi_i64(tmp, ccm);
2081 gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out);
2082 tcg_temp_free_i64(tmp);
2083 return NO_EXIT;
2084 }
2085
2086 static ExitStatus op_insi(DisasContext *s, DisasOps *o)
2087 {
2088 int shift = s->insn->data & 0xff;
2089 int size = s->insn->data >> 8;
2090 tcg_gen_deposit_i64(o->out, o->in1, o->in2, shift, size);
2091 return NO_EXIT;
2092 }
2093
2094 static ExitStatus op_ipm(DisasContext *s, DisasOps *o)
2095 {
2096 TCGv_i64 t1;
2097
2098 gen_op_calc_cc(s);
2099 tcg_gen_andi_i64(o->out, o->out, ~0xff000000ull);
2100
2101 t1 = tcg_temp_new_i64();
2102 tcg_gen_shli_i64(t1, psw_mask, 20);
2103 tcg_gen_shri_i64(t1, t1, 36);
2104 tcg_gen_or_i64(o->out, o->out, t1);
2105
2106 tcg_gen_extu_i32_i64(t1, cc_op);
2107 tcg_gen_shli_i64(t1, t1, 28);
2108 tcg_gen_or_i64(o->out, o->out, t1);
2109 tcg_temp_free_i64(t1);
2110 return NO_EXIT;
2111 }
2112
2113 #ifndef CONFIG_USER_ONLY
2114 static ExitStatus op_ipte(DisasContext *s, DisasOps *o)
2115 {
2116 check_privileged(s);
2117 gen_helper_ipte(cpu_env, o->in1, o->in2);
2118 return NO_EXIT;
2119 }
2120
2121 static ExitStatus op_iske(DisasContext *s, DisasOps *o)
2122 {
2123 check_privileged(s);
2124 gen_helper_iske(o->out, cpu_env, o->in2);
2125 return NO_EXIT;
2126 }
2127 #endif
2128
2129 static ExitStatus op_ldeb(DisasContext *s, DisasOps *o)
2130 {
2131 gen_helper_ldeb(o->out, cpu_env, o->in2);
2132 return NO_EXIT;
2133 }
2134
2135 static ExitStatus op_ledb(DisasContext *s, DisasOps *o)
2136 {
2137 gen_helper_ledb(o->out, cpu_env, o->in2);
2138 return NO_EXIT;
2139 }
2140
2141 static ExitStatus op_ldxb(DisasContext *s, DisasOps *o)
2142 {
2143 gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2);
2144 return NO_EXIT;
2145 }
2146
2147 static ExitStatus op_lexb(DisasContext *s, DisasOps *o)
2148 {
2149 gen_helper_lexb(o->out, cpu_env, o->in1, o->in2);
2150 return NO_EXIT;
2151 }
2152
2153 static ExitStatus op_lxdb(DisasContext *s, DisasOps *o)
2154 {
2155 gen_helper_lxdb(o->out, cpu_env, o->in2);
2156 return_low128(o->out2);
2157 return NO_EXIT;
2158 }
2159
2160 static ExitStatus op_lxeb(DisasContext *s, DisasOps *o)
2161 {
2162 gen_helper_lxeb(o->out, cpu_env, o->in2);
2163 return_low128(o->out2);
2164 return NO_EXIT;
2165 }
2166
2167 static ExitStatus op_llgt(DisasContext *s, DisasOps *o)
2168 {
2169 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffff);
2170 return NO_EXIT;
2171 }
2172
2173 static ExitStatus op_ld8s(DisasContext *s, DisasOps *o)
2174 {
2175 tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
2176 return NO_EXIT;
2177 }
2178
2179 static ExitStatus op_ld8u(DisasContext *s, DisasOps *o)
2180 {
2181 tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
2182 return NO_EXIT;
2183 }
2184
2185 static ExitStatus op_ld16s(DisasContext *s, DisasOps *o)
2186 {
2187 tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
2188 return NO_EXIT;
2189 }
2190
2191 static ExitStatus op_ld16u(DisasContext *s, DisasOps *o)
2192 {
2193 tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
2194 return NO_EXIT;
2195 }
2196
2197 static ExitStatus op_ld32s(DisasContext *s, DisasOps *o)
2198 {
2199 tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s));
2200 return NO_EXIT;
2201 }
2202
2203 static ExitStatus op_ld32u(DisasContext *s, DisasOps *o)
2204 {
2205 tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
2206 return NO_EXIT;
2207 }
2208
2209 static ExitStatus op_ld64(DisasContext *s, DisasOps *o)
2210 {
2211 tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
2212 return NO_EXIT;
2213 }
2214
2215 #ifndef CONFIG_USER_ONLY
2216 static ExitStatus op_lctl(DisasContext *s, DisasOps *o)
2217 {
2218 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2219 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2220 check_privileged(s);
2221 potential_page_fault(s);
2222 gen_helper_lctl(cpu_env, r1, o->in2, r3);
2223 tcg_temp_free_i32(r1);
2224 tcg_temp_free_i32(r3);
2225 return NO_EXIT;
2226 }
2227
2228 static ExitStatus op_lctlg(DisasContext *s, DisasOps *o)
2229 {
2230 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2231 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2232 check_privileged(s);
2233 potential_page_fault(s);
2234 gen_helper_lctlg(cpu_env, r1, o->in2, r3);
2235 tcg_temp_free_i32(r1);
2236 tcg_temp_free_i32(r3);
2237 return NO_EXIT;
2238 }
2239 static ExitStatus op_lra(DisasContext *s, DisasOps *o)
2240 {
2241 check_privileged(s);
2242 potential_page_fault(s);
2243 gen_helper_lra(o->out, cpu_env, o->in2);
2244 set_cc_static(s);
2245 return NO_EXIT;
2246 }
2247
2248 static ExitStatus op_lpsw(DisasContext *s, DisasOps *o)
2249 {
2250 TCGv_i64 t1, t2;
2251
2252 check_privileged(s);
2253
2254 t1 = tcg_temp_new_i64();
2255 t2 = tcg_temp_new_i64();
2256 tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
2257 tcg_gen_addi_i64(o->in2, o->in2, 4);
2258 tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s));
2259 /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
2260 tcg_gen_shli_i64(t1, t1, 32);
2261 gen_helper_load_psw(cpu_env, t1, t2);
2262 tcg_temp_free_i64(t1);
2263 tcg_temp_free_i64(t2);
2264 return EXIT_NORETURN;
2265 }
2266 #endif
2267
2268 static ExitStatus op_lam(DisasContext *s, DisasOps *o)
2269 {
2270 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2271 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2272 potential_page_fault(s);
2273 gen_helper_lam(cpu_env, r1, o->in2, r3);
2274 tcg_temp_free_i32(r1);
2275 tcg_temp_free_i32(r3);
2276 return NO_EXIT;
2277 }
2278
2279 static ExitStatus op_lm32(DisasContext *s, DisasOps *o)
2280 {
2281 int r1 = get_field(s->fields, r1);
2282 int r3 = get_field(s->fields, r3);
2283 TCGv_i64 t = tcg_temp_new_i64();
2284 TCGv_i64 t4 = tcg_const_i64(4);
2285
2286 while (1) {
2287 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2288 store_reg32_i64(r1, t);
2289 if (r1 == r3) {
2290 break;
2291 }
2292 tcg_gen_add_i64(o->in2, o->in2, t4);
2293 r1 = (r1 + 1) & 15;
2294 }
2295
2296 tcg_temp_free_i64(t);
2297 tcg_temp_free_i64(t4);
2298 return NO_EXIT;
2299 }
2300
2301 static ExitStatus op_lmh(DisasContext *s, DisasOps *o)
2302 {
2303 int r1 = get_field(s->fields, r1);
2304 int r3 = get_field(s->fields, r3);
2305 TCGv_i64 t = tcg_temp_new_i64();
2306 TCGv_i64 t4 = tcg_const_i64(4);
2307
2308 while (1) {
2309 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2310 store_reg32h_i64(r1, t);
2311 if (r1 == r3) {
2312 break;
2313 }
2314 tcg_gen_add_i64(o->in2, o->in2, t4);
2315 r1 = (r1 + 1) & 15;
2316 }
2317
2318 tcg_temp_free_i64(t);
2319 tcg_temp_free_i64(t4);
2320 return NO_EXIT;
2321 }
2322
2323 static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
2324 {
2325 int r1 = get_field(s->fields, r1);
2326 int r3 = get_field(s->fields, r3);
2327 TCGv_i64 t8 = tcg_const_i64(8);
2328
2329 while (1) {
2330 tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
2331 if (r1 == r3) {
2332 break;
2333 }
2334 tcg_gen_add_i64(o->in2, o->in2, t8);
2335 r1 = (r1 + 1) & 15;
2336 }
2337
2338 tcg_temp_free_i64(t8);
2339 return NO_EXIT;
2340 }
2341
2342 static ExitStatus op_mov2(DisasContext *s, DisasOps *o)
2343 {
2344 o->out = o->in2;
2345 o->g_out = o->g_in2;
2346 TCGV_UNUSED_I64(o->in2);
2347 o->g_in2 = false;
2348 return NO_EXIT;
2349 }
2350
2351 static ExitStatus op_movx(DisasContext *s, DisasOps *o)
2352 {
2353 o->out = o->in1;
2354 o->out2 = o->in2;
2355 o->g_out = o->g_in1;
2356 o->g_out2 = o->g_in2;
2357 TCGV_UNUSED_I64(o->in1);
2358 TCGV_UNUSED_I64(o->in2);
2359 o->g_in1 = o->g_in2 = false;
2360 return NO_EXIT;
2361 }
2362
2363 static ExitStatus op_mvc(DisasContext *s, DisasOps *o)
2364 {
2365 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2366 potential_page_fault(s);
2367 gen_helper_mvc(cpu_env, l, o->addr1, o->in2);
2368 tcg_temp_free_i32(l);
2369 return NO_EXIT;
2370 }
2371
2372 static ExitStatus op_mvcl(DisasContext *s, DisasOps *o)
2373 {
2374 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2375 TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
2376 potential_page_fault(s);
2377 gen_helper_mvcl(cc_op, cpu_env, r1, r2);
2378 tcg_temp_free_i32(r1);
2379 tcg_temp_free_i32(r2);
2380 set_cc_static(s);
2381 return NO_EXIT;
2382 }
2383
2384 static ExitStatus op_mvcle(DisasContext *s, DisasOps *o)
2385 {
2386 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2387 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2388 potential_page_fault(s);
2389 gen_helper_mvcle(cc_op, cpu_env, r1, o->in2, r3);
2390 tcg_temp_free_i32(r1);
2391 tcg_temp_free_i32(r3);
2392 set_cc_static(s);
2393 return NO_EXIT;
2394 }
2395
2396 #ifndef CONFIG_USER_ONLY
2397 static ExitStatus op_mvcp(DisasContext *s, DisasOps *o)
2398 {
2399 int r1 = get_field(s->fields, l1);
2400 check_privileged(s);
2401 potential_page_fault(s);
2402 gen_helper_mvcp(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2403 set_cc_static(s);
2404 return NO_EXIT;
2405 }
2406
2407 static ExitStatus op_mvcs(DisasContext *s, DisasOps *o)
2408 {
2409 int r1 = get_field(s->fields, l1);
2410 check_privileged(s);
2411 potential_page_fault(s);
2412 gen_helper_mvcs(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2413 set_cc_static(s);
2414 return NO_EXIT;
2415 }
2416 #endif
2417
2418 static ExitStatus op_mvpg(DisasContext *s, DisasOps *o)
2419 {
2420 potential_page_fault(s);
2421 gen_helper_mvpg(cpu_env, regs[0], o->in1, o->in2);
2422 set_cc_static(s);
2423 return NO_EXIT;
2424 }
2425
2426 static ExitStatus op_mvst(DisasContext *s, DisasOps *o)
2427 {
2428 potential_page_fault(s);
2429 gen_helper_mvst(o->in1, cpu_env, regs[0], o->in1, o->in2);
2430 set_cc_static(s);
2431 return_low128(o->in2);
2432 return NO_EXIT;
2433 }
2434
2435 static ExitStatus op_mul(DisasContext *s, DisasOps *o)
2436 {
2437 tcg_gen_mul_i64(o->out, o->in1, o->in2);
2438 return NO_EXIT;
2439 }
2440
2441 static ExitStatus op_mul128(DisasContext *s, DisasOps *o)
2442 {
2443 gen_helper_mul128(o->out, cpu_env, o->in1, o->in2);
2444 return_low128(o->out2);
2445 return NO_EXIT;
2446 }
2447
2448 static ExitStatus op_meeb(DisasContext *s, DisasOps *o)
2449 {
2450 gen_helper_meeb(o->out, cpu_env, o->in1, o->in2);
2451 return NO_EXIT;
2452 }
2453
2454 static ExitStatus op_mdeb(DisasContext *s, DisasOps *o)
2455 {
2456 gen_helper_mdeb(o->out, cpu_env, o->in1, o->in2);
2457 return NO_EXIT;
2458 }
2459
2460 static ExitStatus op_mdb(DisasContext *s, DisasOps *o)
2461 {
2462 gen_helper_mdb(o->out, cpu_env, o->in1, o->in2);
2463 return NO_EXIT;
2464 }
2465
2466 static ExitStatus op_mxb(DisasContext *s, DisasOps *o)
2467 {
2468 gen_helper_mxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2469 return_low128(o->out2);
2470 return NO_EXIT;
2471 }
2472
2473 static ExitStatus op_mxdb(DisasContext *s, DisasOps *o)
2474 {
2475 gen_helper_mxdb(o->out, cpu_env, o->out, o->out2, o->in2);
2476 return_low128(o->out2);
2477 return NO_EXIT;
2478 }
2479
2480 static ExitStatus op_maeb(DisasContext *s, DisasOps *o)
2481 {
2482 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2483 gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3);
2484 tcg_temp_free_i64(r3);
2485 return NO_EXIT;
2486 }
2487
2488 static ExitStatus op_madb(DisasContext *s, DisasOps *o)
2489 {
2490 int r3 = get_field(s->fields, r3);
2491 gen_helper_madb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2492 return NO_EXIT;
2493 }
2494
2495 static ExitStatus op_mseb(DisasContext *s, DisasOps *o)
2496 {
2497 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2498 gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3);
2499 tcg_temp_free_i64(r3);
2500 return NO_EXIT;
2501 }
2502
2503 static ExitStatus op_msdb(DisasContext *s, DisasOps *o)
2504 {
2505 int r3 = get_field(s->fields, r3);
2506 gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2507 return NO_EXIT;
2508 }
2509
2510 static ExitStatus op_nabs(DisasContext *s, DisasOps *o)
2511 {
2512 gen_helper_nabs_i64(o->out, o->in2);
2513 return NO_EXIT;
2514 }
2515
2516 static ExitStatus op_nabsf32(DisasContext *s, DisasOps *o)
2517 {
2518 tcg_gen_ori_i64(o->out, o->in2, 0x80000000ull);
2519 return NO_EXIT;
2520 }
2521
2522 static ExitStatus op_nabsf64(DisasContext *s, DisasOps *o)
2523 {
2524 tcg_gen_ori_i64(o->out, o->in2, 0x8000000000000000ull);
2525 return NO_EXIT;
2526 }
2527
2528 static ExitStatus op_nabsf128(DisasContext *s, DisasOps *o)
2529 {
2530 tcg_gen_ori_i64(o->out, o->in1, 0x8000000000000000ull);
2531 tcg_gen_mov_i64(o->out2, o->in2);
2532 return NO_EXIT;
2533 }
2534
2535 static ExitStatus op_nc(DisasContext *s, DisasOps *o)
2536 {
2537 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2538 potential_page_fault(s);
2539 gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2);
2540 tcg_temp_free_i32(l);
2541 set_cc_static(s);
2542 return NO_EXIT;
2543 }
2544
2545 static ExitStatus op_neg(DisasContext *s, DisasOps *o)
2546 {
2547 tcg_gen_neg_i64(o->out, o->in2);
2548 return NO_EXIT;
2549 }
2550
2551 static ExitStatus op_negf32(DisasContext *s, DisasOps *o)
2552 {
2553 tcg_gen_xori_i64(o->out, o->in2, 0x80000000ull);
2554 return NO_EXIT;
2555 }
2556
2557 static ExitStatus op_negf64(DisasContext *s, DisasOps *o)
2558 {
2559 tcg_gen_xori_i64(o->out, o->in2, 0x8000000000000000ull);
2560 return NO_EXIT;
2561 }
2562
2563 static ExitStatus op_negf128(DisasContext *s, DisasOps *o)
2564 {
2565 tcg_gen_xori_i64(o->out, o->in1, 0x8000000000000000ull);
2566 tcg_gen_mov_i64(o->out2, o->in2);
2567 return NO_EXIT;
2568 }
2569
2570 static ExitStatus op_oc(DisasContext *s, DisasOps *o)
2571 {
2572 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2573 potential_page_fault(s);
2574 gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2);
2575 tcg_temp_free_i32(l);
2576 set_cc_static(s);
2577 return NO_EXIT;
2578 }
2579
2580 static ExitStatus op_or(DisasContext *s, DisasOps *o)
2581 {
2582 tcg_gen_or_i64(o->out, o->in1, o->in2);
2583 return NO_EXIT;
2584 }
2585
2586 static ExitStatus op_ori(DisasContext *s, DisasOps *o)
2587 {
2588 int shift = s->insn->data & 0xff;
2589 int size = s->insn->data >> 8;
2590 uint64_t mask = ((1ull << size) - 1) << shift;
2591
2592 assert(!o->g_in2);
2593 tcg_gen_shli_i64(o->in2, o->in2, shift);
2594 tcg_gen_or_i64(o->out, o->in1, o->in2);
2595
2596 /* Produce the CC from only the bits manipulated. */
2597 tcg_gen_andi_i64(cc_dst, o->out, mask);
2598 set_cc_nz_u64(s, cc_dst);
2599 return NO_EXIT;
2600 }
2601
2602 #ifndef CONFIG_USER_ONLY
2603 static ExitStatus op_ptlb(DisasContext *s, DisasOps *o)
2604 {
2605 check_privileged(s);
2606 gen_helper_ptlb(cpu_env);
2607 return NO_EXIT;
2608 }
2609 #endif
2610
2611 static ExitStatus op_rev16(DisasContext *s, DisasOps *o)
2612 {
2613 tcg_gen_bswap16_i64(o->out, o->in2);
2614 return NO_EXIT;
2615 }
2616
2617 static ExitStatus op_rev32(DisasContext *s, DisasOps *o)
2618 {
2619 tcg_gen_bswap32_i64(o->out, o->in2);
2620 return NO_EXIT;
2621 }
2622
2623 static ExitStatus op_rev64(DisasContext *s, DisasOps *o)
2624 {
2625 tcg_gen_bswap64_i64(o->out, o->in2);
2626 return NO_EXIT;
2627 }
2628
2629 static ExitStatus op_rll32(DisasContext *s, DisasOps *o)
2630 {
2631 TCGv_i32 t1 = tcg_temp_new_i32();
2632 TCGv_i32 t2 = tcg_temp_new_i32();
2633 TCGv_i32 to = tcg_temp_new_i32();
2634 tcg_gen_trunc_i64_i32(t1, o->in1);
2635 tcg_gen_trunc_i64_i32(t2, o->in2);
2636 tcg_gen_rotl_i32(to, t1, t2);
2637 tcg_gen_extu_i32_i64(o->out, to);
2638 tcg_temp_free_i32(t1);
2639 tcg_temp_free_i32(t2);
2640 tcg_temp_free_i32(to);
2641 return NO_EXIT;
2642 }
2643
2644 static ExitStatus op_rll64(DisasContext *s, DisasOps *o)
2645 {
2646 tcg_gen_rotl_i64(o->out, o->in1, o->in2);
2647 return NO_EXIT;
2648 }
2649
2650 #ifndef CONFIG_USER_ONLY
2651 static ExitStatus op_rrbe(DisasContext *s, DisasOps *o)
2652 {
2653 check_privileged(s);
2654 gen_helper_rrbe(cc_op, cpu_env, o->in2);
2655 set_cc_static(s);
2656 return NO_EXIT;
2657 }
2658
2659 static ExitStatus op_sacf(DisasContext *s, DisasOps *o)
2660 {
2661 check_privileged(s);
2662 gen_helper_sacf(cpu_env, o->in2);
2663 /* Addressing mode has changed, so end the block. */
2664 return EXIT_PC_STALE;
2665 }
2666 #endif
2667
2668 static ExitStatus op_sar(DisasContext *s, DisasOps *o)
2669 {
2670 int r1 = get_field(s->fields, r1);
2671 tcg_gen_st32_i64(o->in2, cpu_env, offsetof(CPUS390XState, aregs[r1]));
2672 return NO_EXIT;
2673 }
2674
2675 static ExitStatus op_seb(DisasContext *s, DisasOps *o)
2676 {
2677 gen_helper_seb(o->out, cpu_env, o->in1, o->in2);
2678 return NO_EXIT;
2679 }
2680
2681 static ExitStatus op_sdb(DisasContext *s, DisasOps *o)
2682 {
2683 gen_helper_sdb(o->out, cpu_env, o->in1, o->in2);
2684 return NO_EXIT;
2685 }
2686
2687 static ExitStatus op_sxb(DisasContext *s, DisasOps *o)
2688 {
2689 gen_helper_sxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2690 return_low128(o->out2);
2691 return NO_EXIT;
2692 }
2693
2694 static ExitStatus op_sqeb(DisasContext *s, DisasOps *o)
2695 {
2696 gen_helper_sqeb(o->out, cpu_env, o->in2);
2697 return NO_EXIT;
2698 }
2699
2700 static ExitStatus op_sqdb(DisasContext *s, DisasOps *o)
2701 {
2702 gen_helper_sqdb(o->out, cpu_env, o->in2);
2703 return NO_EXIT;
2704 }
2705
2706 static ExitStatus op_sqxb(DisasContext *s, DisasOps *o)
2707 {
2708 gen_helper_sqxb(o->out, cpu_env, o->in1, o->in2);
2709 return_low128(o->out2);
2710 return NO_EXIT;
2711 }
2712
2713 #ifndef CONFIG_USER_ONLY
2714 static ExitStatus op_sigp(DisasContext *s, DisasOps *o)
2715 {
2716 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2717 check_privileged(s);
2718 potential_page_fault(s);
2719 gen_helper_sigp(cc_op, cpu_env, o->in2, r1, o->in1);
2720 tcg_temp_free_i32(r1);
2721 return NO_EXIT;
2722 }
2723 #endif
2724
2725 static ExitStatus op_sla(DisasContext *s, DisasOps *o)
2726 {
2727 uint64_t sign = 1ull << s->insn->data;
2728 enum cc_op cco = s->insn->data == 31 ? CC_OP_SLA_32 : CC_OP_SLA_64;
2729 gen_op_update2_cc_i64(s, cco, o->in1, o->in2);
2730 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2731 /* The arithmetic left shift is curious in that it does not affect
2732 the sign bit. Copy that over from the source unchanged. */
2733 tcg_gen_andi_i64(o->out, o->out, ~sign);
2734 tcg_gen_andi_i64(o->in1, o->in1, sign);
2735 tcg_gen_or_i64(o->out, o->out, o->in1);
2736 return NO_EXIT;
2737 }
2738
2739 static ExitStatus op_sll(DisasContext *s, DisasOps *o)
2740 {
2741 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2742 return NO_EXIT;
2743 }
2744
2745 static ExitStatus op_sra(DisasContext *s, DisasOps *o)
2746 {
2747 tcg_gen_sar_i64(o->out, o->in1, o->in2);
2748 return NO_EXIT;
2749 }
2750
2751 static ExitStatus op_srl(DisasContext *s, DisasOps *o)
2752 {
2753 tcg_gen_shr_i64(o->out, o->in1, o->in2);
2754 return NO_EXIT;
2755 }
2756
2757 static ExitStatus op_sfpc(DisasContext *s, DisasOps *o)
2758 {
2759 gen_helper_sfpc(cpu_env, o->in2);
2760 return NO_EXIT;
2761 }
2762
2763 #ifndef CONFIG_USER_ONLY
2764 static ExitStatus op_spka(DisasContext *s, DisasOps *o)
2765 {
2766 check_privileged(s);
2767 tcg_gen_shri_i64(o->in2, o->in2, 4);
2768 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, PSW_SHIFT_KEY - 4, 4);
2769 return NO_EXIT;
2770 }
2771
2772 static ExitStatus op_sske(DisasContext *s, DisasOps *o)
2773 {
2774 check_privileged(s);
2775 gen_helper_sske(cpu_env, o->in1, o->in2);
2776 return NO_EXIT;
2777 }
2778
2779 static ExitStatus op_ssm(DisasContext *s, DisasOps *o)
2780 {
2781 check_privileged(s);
2782 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8);
2783 return NO_EXIT;
2784 }
2785
2786 static ExitStatus op_stap(DisasContext *s, DisasOps *o)
2787 {
2788 check_privileged(s);
2789 /* ??? Surely cpu address != cpu number. In any case the previous
2790 version of this stored more than the required half-word, so it
2791 is unlikely this has ever been tested. */
2792 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num));
2793 return NO_EXIT;
2794 }
2795
2796 static ExitStatus op_stck(DisasContext *s, DisasOps *o)
2797 {
2798 gen_helper_stck(o->out, cpu_env);
2799 /* ??? We don't implement clock states. */
2800 gen_op_movi_cc(s, 0);
2801 return NO_EXIT;
2802 }
2803
2804 static ExitStatus op_stcke(DisasContext *s, DisasOps *o)
2805 {
2806 TCGv_i64 c1 = tcg_temp_new_i64();
2807 TCGv_i64 c2 = tcg_temp_new_i64();
2808 gen_helper_stck(c1, cpu_env);
2809 /* Shift the 64-bit value into its place as a zero-extended
2810 104-bit value. Note that "bit positions 64-103 are always
2811 non-zero so that they compare differently to STCK"; we set
2812 the least significant bit to 1. */
2813 tcg_gen_shli_i64(c2, c1, 56);
2814 tcg_gen_shri_i64(c1, c1, 8);
2815 tcg_gen_ori_i64(c2, c2, 0x10000);
2816 tcg_gen_qemu_st64(c1, o->in2, get_mem_index(s));
2817 tcg_gen_addi_i64(o->in2, o->in2, 8);
2818 tcg_gen_qemu_st64(c2, o->in2, get_mem_index(s));
2819 tcg_temp_free_i64(c1);
2820 tcg_temp_free_i64(c2);
2821 /* ??? We don't implement clock states. */
2822 gen_op_movi_cc(s, 0);
2823 return NO_EXIT;
2824 }
2825
2826 static ExitStatus op_sckc(DisasContext *s, DisasOps *o)
2827 {
2828 check_privileged(s);
2829 gen_helper_sckc(cpu_env, o->in2);
2830 return NO_EXIT;
2831 }
2832
2833 static ExitStatus op_stckc(DisasContext *s, DisasOps *o)
2834 {
2835 check_privileged(s);
2836 gen_helper_stckc(o->out, cpu_env);
2837 return NO_EXIT;
2838 }
2839
2840 static ExitStatus op_stctg(DisasContext *s, DisasOps *o)
2841 {
2842 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2843 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2844 check_privileged(s);
2845 potential_page_fault(s);
2846 gen_helper_stctg(cpu_env, r1, o->in2, r3);
2847 tcg_temp_free_i32(r1);
2848 tcg_temp_free_i32(r3);
2849 return NO_EXIT;
2850 }
2851
2852 static ExitStatus op_stctl(DisasContext *s, DisasOps *o)
2853 {
2854 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2855 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2856 check_privileged(s);
2857 potential_page_fault(s);
2858 gen_helper_stctl(cpu_env, r1, o->in2, r3);
2859 tcg_temp_free_i32(r1);
2860 tcg_temp_free_i32(r3);
2861 return NO_EXIT;
2862 }
2863
2864 static ExitStatus op_stidp(DisasContext *s, DisasOps *o)
2865 {
2866 check_privileged(s);
2867 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num));
2868 return NO_EXIT;
2869 }
2870
2871 static ExitStatus op_spt(DisasContext *s, DisasOps *o)
2872 {
2873 check_privileged(s);
2874 gen_helper_spt(cpu_env, o->in2);
2875 return NO_EXIT;
2876 }
2877
2878 static ExitStatus op_stpt(DisasContext *s, DisasOps *o)
2879 {
2880 check_privileged(s);
2881 gen_helper_stpt(o->out, cpu_env);
2882 return NO_EXIT;
2883 }
2884
2885 static ExitStatus op_stsi(DisasContext *s, DisasOps *o)
2886 {
2887 check_privileged(s);
2888 potential_page_fault(s);
2889 gen_helper_stsi(cc_op, cpu_env, o->in2, regs[0], regs[1]);
2890 set_cc_static(s);
2891 return NO_EXIT;
2892 }
2893
2894 static ExitStatus op_spx(DisasContext *s, DisasOps *o)
2895 {
2896 check_privileged(s);
2897 gen_helper_spx(cpu_env, o->in2);
2898 return NO_EXIT;
2899 }
2900
2901 static ExitStatus op_subchannel(DisasContext *s, DisasOps *o)
2902 {
2903 check_privileged(s);
2904 /* Not operational. */
2905 gen_op_movi_cc(s, 3);
2906 return NO_EXIT;
2907 }
2908
2909 static ExitStatus op_stpx(DisasContext *s, DisasOps *o)
2910 {
2911 check_privileged(s);
2912 tcg_gen_ld_i64(o->out, cpu_env, offsetof(CPUS390XState, psa));
2913 tcg_gen_andi_i64(o->out, o->out, 0x7fffe000);
2914 return NO_EXIT;
2915 }
2916
2917 static ExitStatus op_stnosm(DisasContext *s, DisasOps *o)
2918 {
2919 uint64_t i2 = get_field(s->fields, i2);
2920 TCGv_i64 t;
2921
2922 check_privileged(s);
2923
2924 /* It is important to do what the instruction name says: STORE THEN.
2925 If we let the output hook perform the store then if we fault and
2926 restart, we'll have the wrong SYSTEM MASK in place. */
2927 t = tcg_temp_new_i64();
2928 tcg_gen_shri_i64(t, psw_mask, 56);
2929 tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
2930 tcg_temp_free_i64(t);
2931
2932 if (s->fields->op == 0xac) {
2933 tcg_gen_andi_i64(psw_mask, psw_mask,
2934 (i2 << 56) | 0x00ffffffffffffffull);
2935 } else {
2936 tcg_gen_ori_i64(psw_mask, psw_mask, i2 << 56);
2937 }
2938 return NO_EXIT;
2939 }
2940
2941 static ExitStatus op_stura(DisasContext *s, DisasOps *o)
2942 {
2943 check_privileged(s);
2944 potential_page_fault(s);
2945 gen_helper_stura(cpu_env, o->in2, o->in1);
2946 return NO_EXIT;
2947 }
2948 #endif
2949
2950 static ExitStatus op_st8(DisasContext *s, DisasOps *o)
2951 {
2952 tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));
2953 return NO_EXIT;
2954 }
2955
2956 static ExitStatus op_st16(DisasContext *s, DisasOps *o)
2957 {
2958 tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s));
2959 return NO_EXIT;
2960 }
2961
2962 static ExitStatus op_st32(DisasContext *s, DisasOps *o)
2963 {
2964 tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s));
2965 return NO_EXIT;
2966 }
2967
2968 static ExitStatus op_st64(DisasContext *s, DisasOps *o)
2969 {
2970 tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s));
2971 return NO_EXIT;
2972 }
2973
2974 static ExitStatus op_stam(DisasContext *s, DisasOps *o)
2975 {
2976 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2977 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2978 potential_page_fault(s);
2979 gen_helper_stam(cpu_env, r1, o->in2, r3);
2980 tcg_temp_free_i32(r1);
2981 tcg_temp_free_i32(r3);
2982 return NO_EXIT;
2983 }
2984
2985 static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
2986 {
2987 int m3 = get_field(s->fields, m3);
2988 int pos, base = s->insn->data;
2989 TCGv_i64 tmp = tcg_temp_new_i64();
2990
2991 pos = base + ctz32(m3) * 8;
2992 switch (m3) {
2993 case 0xf:
2994 /* Effectively a 32-bit store. */
2995 tcg_gen_shri_i64(tmp, o->in1, pos);
2996 tcg_gen_qemu_st32(tmp, o->in2, get_mem_index(s));
2997 break;
2998
2999 case 0xc:
3000 case 0x6:
3001 case 0x3:
3002 /* Effectively a 16-bit store. */
3003 tcg_gen_shri_i64(tmp, o->in1, pos);
3004 tcg_gen_qemu_st16(tmp, o->in2, get_mem_index(s));
3005 break;
3006
3007 case 0x8:
3008 case 0x4:
3009 case 0x2:
3010 case 0x1:
3011 /* Effectively an 8-bit store. */
3012 tcg_gen_shri_i64(tmp, o->in1, pos);
3013 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3014 break;
3015
3016 default:
3017 /* This is going to be a sequence of shifts and stores. */
3018 pos = base + 32 - 8;
3019 while (m3) {
3020 if (m3 & 0x8) {
3021 tcg_gen_shri_i64(tmp, o->in1, pos);
3022 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3023 tcg_gen_addi_i64(o->in2, o->in2, 1);
3024 }
3025 m3 = (m3 << 1) & 0xf;
3026 pos -= 8;
3027 }
3028 break;
3029 }
3030 tcg_temp_free_i64(tmp);
3031 return NO_EXIT;
3032 }
3033
3034 static ExitStatus op_stm(DisasContext *s, DisasOps *o)
3035 {
3036 int r1 = get_field(s->fields, r1);
3037 int r3 = get_field(s->fields, r3);
3038 int size = s->insn->data;
3039 TCGv_i64 tsize = tcg_const_i64(size);
3040
3041 while (1) {
3042 if (size == 8) {
3043 tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s));
3044 } else {
3045 tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s));
3046 }
3047 if (r1 == r3) {
3048 break;
3049 }
3050 tcg_gen_add_i64(o->in2, o->in2, tsize);
3051 r1 = (r1 + 1) & 15;
3052 }
3053
3054 tcg_temp_free_i64(tsize);
3055 return NO_EXIT;
3056 }
3057
3058 static ExitStatus op_stmh(DisasContext *s, DisasOps *o)
3059 {
3060 int r1 = get_field(s->fields, r1);
3061 int r3 = get_field(s->fields, r3);
3062 TCGv_i64 t = tcg_temp_new_i64();
3063 TCGv_i64 t4 = tcg_const_i64(4);
3064 TCGv_i64 t32 = tcg_const_i64(32);
3065
3066 while (1) {
3067 tcg_gen_shl_i64(t, regs[r1], t32);
3068 tcg_gen_qemu_st32(t, o->in2, get_mem_index(s));
3069 if (r1 == r3) {
3070 break;
3071 }
3072 tcg_gen_add_i64(o->in2, o->in2, t4);
3073 r1 = (r1 + 1) & 15;
3074 }
3075
3076 tcg_temp_free_i64(t);
3077 tcg_temp_free_i64(t4);
3078 tcg_temp_free_i64(t32);
3079 return NO_EXIT;
3080 }
3081
3082 static ExitStatus op_srst(DisasContext *s, DisasOps *o)
3083 {
3084 potential_page_fault(s);
3085 gen_helper_srst(o->in1, cpu_env, regs[0], o->in1, o->in2);
3086 set_cc_static(s);
3087 return_low128(o->in2);
3088 return NO_EXIT;
3089 }
3090
3091 static ExitStatus op_sub(DisasContext *s, DisasOps *o)
3092 {
3093 tcg_gen_sub_i64(o->out, o->in1, o->in2);
3094 return NO_EXIT;
3095 }
3096
3097 static ExitStatus op_subb(DisasContext *s, DisasOps *o)
3098 {
3099 TCGv_i64 cc;
3100
3101 assert(!o->g_in2);
3102 tcg_gen_not_i64(o->in2, o->in2);
3103 tcg_gen_add_i64(o->out, o->in1, o->in2);
3104
3105 /* XXX possible optimization point */
3106 gen_op_calc_cc(s);
3107 cc = tcg_temp_new_i64();
3108 tcg_gen_extu_i32_i64(cc, cc_op);
3109 tcg_gen_shri_i64(cc, cc, 1);
3110 tcg_gen_add_i64(o->out, o->out, cc);
3111 tcg_temp_free_i64(cc);
3112 return NO_EXIT;
3113 }
3114
3115 static ExitStatus op_svc(DisasContext *s, DisasOps *o)
3116 {
3117 TCGv_i32 t;
3118
3119 update_psw_addr(s);
3120 gen_op_calc_cc(s);
3121
3122 t = tcg_const_i32(get_field(s->fields, i1) & 0xff);
3123 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code));
3124 tcg_temp_free_i32(t);
3125
3126 t = tcg_const_i32(s->next_pc - s->pc);
3127 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen));
3128 tcg_temp_free_i32(t);
3129
3130 gen_exception(EXCP_SVC);
3131 return EXIT_NORETURN;
3132 }
3133
3134 static ExitStatus op_tceb(DisasContext *s, DisasOps *o)
3135 {
3136 gen_helper_tceb(cc_op, o->in1, o->in2);
3137 set_cc_static(s);
3138 return NO_EXIT;
3139 }
3140
3141 static ExitStatus op_tcdb(DisasContext *s, DisasOps *o)
3142 {
3143 gen_helper_tcdb(cc_op, o->in1, o->in2);
3144 set_cc_static(s);
3145 return NO_EXIT;
3146 }
3147
3148 static ExitStatus op_tcxb(DisasContext *s, DisasOps *o)
3149 {
3150 gen_helper_tcxb(cc_op, o->out, o->out2, o->in2);
3151 set_cc_static(s);
3152 return NO_EXIT;
3153 }
3154
3155 #ifndef CONFIG_USER_ONLY
3156 static ExitStatus op_tprot(DisasContext *s, DisasOps *o)
3157 {
3158 potential_page_fault(s);
3159 gen_helper_tprot(cc_op, o->addr1, o->in2);
3160 set_cc_static(s);
3161 return NO_EXIT;
3162 }
3163 #endif
3164
3165 static ExitStatus op_tr(DisasContext *s, DisasOps *o)
3166 {
3167 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3168 potential_page_fault(s);
3169 gen_helper_tr(cpu_env, l, o->addr1, o->in2);
3170 tcg_temp_free_i32(l);
3171 set_cc_static(s);
3172 return NO_EXIT;
3173 }
3174
3175 static ExitStatus op_unpk(DisasContext *s, DisasOps *o)
3176 {
3177 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3178 potential_page_fault(s);
3179 gen_helper_unpk(cpu_env, l, o->addr1, o->in2);
3180 tcg_temp_free_i32(l);
3181 return NO_EXIT;
3182 }
3183
3184 static ExitStatus op_xc(DisasContext *s, DisasOps *o)
3185 {
3186 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3187 potential_page_fault(s);
3188 gen_helper_xc(cc_op, cpu_env, l, o->addr1, o->in2);
3189 tcg_temp_free_i32(l);
3190 set_cc_static(s);
3191 return NO_EXIT;
3192 }
3193
3194 static ExitStatus op_xor(DisasContext *s, DisasOps *o)
3195 {
3196 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3197 return NO_EXIT;
3198 }
3199
3200 static ExitStatus op_xori(DisasContext *s, DisasOps *o)
3201 {
3202 int shift = s->insn->data & 0xff;
3203 int size = s->insn->data >> 8;
3204 uint64_t mask = ((1ull << size) - 1) << shift;
3205
3206 assert(!o->g_in2);
3207 tcg_gen_shli_i64(o->in2, o->in2, shift);
3208 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3209
3210 /* Produce the CC from only the bits manipulated. */
3211 tcg_gen_andi_i64(cc_dst, o->out, mask);
3212 set_cc_nz_u64(s, cc_dst);
3213 return NO_EXIT;
3214 }
3215
3216 static ExitStatus op_zero(DisasContext *s, DisasOps *o)
3217 {
3218 o->out = tcg_const_i64(0);
3219 return NO_EXIT;
3220 }
3221
3222 static ExitStatus op_zero2(DisasContext *s, DisasOps *o)
3223 {
3224 o->out = tcg_const_i64(0);
3225 o->out2 = o->out;
3226 o->g_out2 = true;
3227 return NO_EXIT;
3228 }
3229
3230 /* ====================================================================== */
3231 /* The "Cc OUTput" generators. Given the generated output (and in some cases
3232 the original inputs), update the various cc data structures in order to
3233 be able to compute the new condition code. */
3234
3235 static void cout_abs32(DisasContext *s, DisasOps *o)
3236 {
3237 gen_op_update1_cc_i64(s, CC_OP_ABS_32, o->out);
3238 }
3239
3240 static void cout_abs64(DisasContext *s, DisasOps *o)
3241 {
3242 gen_op_update1_cc_i64(s, CC_OP_ABS_64, o->out);
3243 }
3244
3245 static void cout_adds32(DisasContext *s, DisasOps *o)
3246 {
3247 gen_op_update3_cc_i64(s, CC_OP_ADD_32, o->in1, o->in2, o->out);
3248 }
3249
3250 static void cout_adds64(DisasContext *s, DisasOps *o)
3251 {
3252 gen_op_update3_cc_i64(s, CC_OP_ADD_64, o->in1, o->in2, o->out);
3253 }
3254
3255 static void cout_addu32(DisasContext *s, DisasOps *o)
3256 {
3257 gen_op_update3_cc_i64(s, CC_OP_ADDU_32, o->in1, o->in2, o->out);
3258 }
3259
3260 static void cout_addu64(DisasContext *s, DisasOps *o)
3261 {
3262 gen_op_update3_cc_i64(s, CC_OP_ADDU_64, o->in1, o->in2, o->out);
3263 }
3264
3265 static void cout_addc32(DisasContext *s, DisasOps *o)
3266 {
3267 gen_op_update3_cc_i64(s, CC_OP_ADDC_32, o->in1, o->in2, o->out);
3268 }
3269
3270 static void cout_addc64(DisasContext *s, DisasOps *o)
3271 {
3272 gen_op_update3_cc_i64(s, CC_OP_ADDC_64, o->in1, o->in2, o->out);
3273 }
3274
3275 static void cout_cmps32(DisasContext *s, DisasOps *o)
3276 {
3277 gen_op_update2_cc_i64(s, CC_OP_LTGT_32, o->in1, o->in2);
3278 }
3279
3280 static void cout_cmps64(DisasContext *s, DisasOps *o)
3281 {
3282 gen_op_update2_cc_i64(s, CC_OP_LTGT_64, o->in1, o->in2);
3283 }
3284
3285 static void cout_cmpu32(DisasContext *s, DisasOps *o)
3286 {
3287 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_32, o->in1, o->in2);
3288 }
3289
3290 static void cout_cmpu64(DisasContext *s, DisasOps *o)
3291 {
3292 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, o->in1, o->in2);
3293 }
3294
3295 static void cout_f32(DisasContext *s, DisasOps *o)
3296 {
3297 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, o->out);
3298 }
3299
3300 static void cout_f64(DisasContext *s, DisasOps *o)
3301 {
3302 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, o->out);
3303 }
3304
3305 static void cout_f128(DisasContext *s, DisasOps *o)
3306 {
3307 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, o->out, o->out2);
3308 }
3309
3310 static void cout_nabs32(DisasContext *s, DisasOps *o)
3311 {
3312 gen_op_update1_cc_i64(s, CC_OP_NABS_32, o->out);
3313 }
3314
3315 static void cout_nabs64(DisasContext *s, DisasOps *o)
3316 {
3317 gen_op_update1_cc_i64(s, CC_OP_NABS_64, o->out);
3318 }
3319
3320 static void cout_neg32(DisasContext *s, DisasOps *o)
3321 {
3322 gen_op_update1_cc_i64(s, CC_OP_COMP_32, o->out);
3323 }
3324
3325 static void cout_neg64(DisasContext *s, DisasOps *o)
3326 {
3327 gen_op_update1_cc_i64(s, CC_OP_COMP_64, o->out);
3328 }
3329
3330 static void cout_nz32(DisasContext *s, DisasOps *o)
3331 {
3332 tcg_gen_ext32u_i64(cc_dst, o->out);
3333 gen_op_update1_cc_i64(s, CC_OP_NZ, cc_dst);
3334 }
3335
3336 static void cout_nz64(DisasContext *s, DisasOps *o)
3337 {
3338 gen_op_update1_cc_i64(s, CC_OP_NZ, o->out);
3339 }
3340
3341 static void cout_s32(DisasContext *s, DisasOps *o)
3342 {
3343 gen_op_update1_cc_i64(s, CC_OP_LTGT0_32, o->out);
3344 }
3345
3346 static void cout_s64(DisasContext *s, DisasOps *o)
3347 {
3348 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, o->out);
3349 }
3350
3351 static void cout_subs32(DisasContext *s, DisasOps *o)
3352 {
3353 gen_op_update3_cc_i64(s, CC_OP_SUB_32, o->in1, o->in2, o->out);
3354 }
3355
3356 static void cout_subs64(DisasContext *s, DisasOps *o)
3357 {
3358 gen_op_update3_cc_i64(s, CC_OP_SUB_64, o->in1, o->in2, o->out);
3359 }
3360
3361 static void cout_subu32(DisasContext *s, DisasOps *o)
3362 {
3363 gen_op_update3_cc_i64(s, CC_OP_SUBU_32, o->in1, o->in2, o->out);
3364 }
3365
3366 static void cout_subu64(DisasContext *s, DisasOps *o)
3367 {
3368 gen_op_update3_cc_i64(s, CC_OP_SUBU_64, o->in1, o->in2, o->out);
3369 }
3370
3371 static void cout_subb32(DisasContext *s, DisasOps *o)
3372 {
3373 gen_op_update3_cc_i64(s, CC_OP_SUBB_32, o->in1, o->in2, o->out);
3374 }
3375
3376 static void cout_subb64(DisasContext *s, DisasOps *o)
3377 {
3378 gen_op_update3_cc_i64(s, CC_OP_SUBB_64, o->in1, o->in2, o->out);
3379 }
3380
3381 static void cout_tm32(DisasContext *s, DisasOps *o)
3382 {
3383 gen_op_update2_cc_i64(s, CC_OP_TM_32, o->in1, o->in2);
3384 }
3385
3386 static void cout_tm64(DisasContext *s, DisasOps *o)
3387 {
3388 gen_op_update2_cc_i64(s, CC_OP_TM_64, o->in1, o->in2);
3389 }
3390
3391 /* ====================================================================== */
3392 /* The "PREPeration" generators. These initialize the DisasOps.OUT fields
3393 with the TCG register to which we will write. Used in combination with
3394 the "wout" generators, in some cases we need a new temporary, and in
3395 some cases we can write to a TCG global. */
3396
3397 static void prep_new(DisasContext *s, DisasFields *f, DisasOps *o)
3398 {
3399 o->out = tcg_temp_new_i64();
3400 }
3401
3402 static void prep_new_P(DisasContext *s, DisasFields *f, DisasOps *o)
3403 {
3404 o->out = tcg_temp_new_i64();
3405 o->out2 = tcg_temp_new_i64();
3406 }
3407
3408 static void prep_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3409 {
3410 o->out = regs[get_field(f, r1)];
3411 o->g_out = true;
3412 }
3413
3414 static void prep_r1_P(DisasContext *s, DisasFields *f, DisasOps *o)
3415 {
3416 /* ??? Specification exception: r1 must be even. */
3417 int r1 = get_field(f, r1);
3418 o->out = regs[r1];
3419 o->out2 = regs[(r1 + 1) & 15];
3420 o->g_out = o->g_out2 = true;
3421 }
3422
3423 static void prep_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3424 {
3425 o->out = fregs[get_field(f, r1)];
3426 o->g_out = true;
3427 }
3428
3429 static void prep_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3430 {
3431 /* ??? Specification exception: r1 must be < 14. */
3432 int r1 = get_field(f, r1);
3433 o->out = fregs[r1];
3434 o->out2 = fregs[(r1 + 2) & 15];
3435 o->g_out = o->g_out2 = true;
3436 }
3437
3438 /* ====================================================================== */
3439 /* The "Write OUTput" generators. These generally perform some non-trivial
3440 copy of data to TCG globals, or to main memory. The trivial cases are
3441 generally handled by having a "prep" generator install the TCG global
3442 as the destination of the operation. */
3443
3444 static void wout_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3445 {
3446 store_reg(get_field(f, r1), o->out);
3447 }
3448
3449 static void wout_r1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3450 {
3451 int r1 = get_field(f, r1);
3452 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8);
3453 }
3454
3455 static void wout_r1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3456 {
3457 int r1 = get_field(f, r1);
3458 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 16);
3459 }
3460
3461 static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3462 {
3463 store_reg32_i64(get_field(f, r1), o->out);
3464 }
3465
3466 static void wout_r1_P32(DisasContext *s, DisasFields *f, DisasOps *o)
3467 {
3468 /* ??? Specification exception: r1 must be even. */
3469 int r1 = get_field(f, r1);
3470 store_reg32_i64(r1, o->out);
3471 store_reg32_i64((r1 + 1) & 15, o->out2);
3472 }
3473
3474 static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3475 {
3476 /* ??? Specification exception: r1 must be even. */
3477 int r1 = get_field(f, r1);
3478 store_reg32_i64((r1 + 1) & 15, o->out);
3479 tcg_gen_shri_i64(o->out, o->out, 32);
3480 store_reg32_i64(r1, o->out);
3481 }
3482
3483 static void wout_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3484 {
3485 store_freg32_i64(get_field(f, r1), o->out);
3486 }
3487
3488 static void wout_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3489 {
3490 store_freg(get_field(f, r1), o->out);
3491 }
3492
3493 static void wout_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3494 {
3495 /* ??? Specification exception: r1 must be < 14. */
3496 int f1 = get_field(s->fields, r1);
3497 store_freg(f1, o->out);
3498 store_freg((f1 + 2) & 15, o->out2);
3499 }
3500
3501 static void wout_cond_r1r2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3502 {
3503 if (get_field(f, r1) != get_field(f, r2)) {
3504 store_reg32_i64(get_field(f, r1), o->out);
3505 }
3506 }
3507
3508 static void wout_cond_e1e2(DisasContext *s, DisasFields *f, DisasOps *o)
3509 {
3510 if (get_field(f, r1) != get_field(f, r2)) {
3511 store_freg32_i64(get_field(f, r1), o->out);
3512 }
3513 }
3514
3515 static void wout_m1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3516 {
3517 tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s));
3518 }
3519
3520 static void wout_m1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3521 {
3522 tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s));
3523 }
3524
3525 static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3526 {
3527 tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
3528 }
3529
3530 static void wout_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3531 {
3532 tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
3533 }
3534
3535 static void wout_m2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3536 {
3537 tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s));
3538 }
3539
3540 /* ====================================================================== */
3541 /* The "INput 1" generators. These load the first operand to an insn. */
3542
3543 static void in1_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3544 {
3545 o->in1 = load_reg(get_field(f, r1));
3546 }
3547
3548 static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3549 {
3550 o->in1 = regs[get_field(f, r1)];
3551 o->g_in1 = true;
3552 }
3553
3554 static void in1_r1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3555 {
3556 o->in1 = tcg_temp_new_i64();
3557 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r1)]);
3558 }
3559
3560 static void in1_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3561 {
3562 o->in1 = tcg_temp_new_i64();
3563 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r1)]);
3564 }
3565
3566 static void in1_r1_sr32(DisasContext *s, DisasFields *f, DisasOps *o)
3567 {
3568 o->in1 = tcg_temp_new_i64();
3569 tcg_gen_shri_i64(o->in1, regs[get_field(f, r1)], 32);
3570 }
3571
3572 static void in1_r1p1(DisasContext *s, DisasFields *f, DisasOps *o)
3573 {
3574 /* ??? Specification exception: r1 must be even. */
3575 int r1 = get_field(f, r1);
3576 o->in1 = load_reg((r1 + 1) & 15);
3577 }
3578
3579 static void in1_r1p1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3580 {
3581 /* ??? Specification exception: r1 must be even. */
3582 int r1 = get_field(f, r1);
3583 o->in1 = tcg_temp_new_i64();
3584 tcg_gen_ext32s_i64(o->in1, regs[(r1 + 1) & 15]);
3585 }
3586
3587 static void in1_r1p1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3588 {
3589 /* ??? Specification exception: r1 must be even. */
3590 int r1 = get_field(f, r1);
3591 o->in1 = tcg_temp_new_i64();
3592 tcg_gen_ext32u_i64(o->in1, regs[(r1 + 1) & 15]);
3593 }
3594
3595 static void in1_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3596 {
3597 /* ??? Specification exception: r1 must be even. */
3598 int r1 = get_field(f, r1);
3599 o->in1 = tcg_temp_new_i64();
3600 tcg_gen_concat32_i64(o->in1, regs[r1 + 1], regs[r1]);
3601 }
3602
3603 static void in1_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3604 {
3605 o->in1 = load_reg(get_field(f, r2));
3606 }
3607
3608 static void in1_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3609 {
3610 o->in1 = load_reg(get_field(f, r3));
3611 }
3612
3613 static void in1_r3_o(DisasContext *s, DisasFields *f, DisasOps *o)
3614 {
3615 o->in1 = regs[get_field(f, r3)];
3616 o->g_in1 = true;
3617 }
3618
3619 static void in1_r3_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3620 {
3621 o->in1 = tcg_temp_new_i64();
3622 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r3)]);
3623 }
3624
3625 static void in1_r3_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3626 {
3627 o->in1 = tcg_temp_new_i64();
3628 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r3)]);
3629 }
3630
3631 static void in1_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3632 {
3633 o->in1 = load_freg32_i64(get_field(f, r1));
3634 }
3635
3636 static void in1_f1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3637 {
3638 o->in1 = fregs[get_field(f, r1)];
3639 o->g_in1 = true;
3640 }
3641
3642 static void in1_x1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3643 {
3644 /* ??? Specification exception: r1 must be < 14. */
3645 int r1 = get_field(f, r1);
3646 o->out = fregs[r1];
3647 o->out2 = fregs[(r1 + 2) & 15];
3648 o->g_out = o->g_out2 = true;
3649 }
3650
3651 static void in1_la1(DisasContext *s, DisasFields *f, DisasOps *o)
3652 {
3653 o->addr1 = get_address(s, 0, get_field(f, b1), get_field(f, d1));
3654 }
3655
3656 static void in1_la2(DisasContext *s, DisasFields *f, DisasOps *o)
3657 {
3658 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3659 o->addr1 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3660 }
3661
3662 static void in1_m1_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3663 {
3664 in1_la1(s, f, o);
3665 o->in1 = tcg_temp_new_i64();
3666 tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s));
3667 }
3668
3669 static void in1_m1_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3670 {
3671 in1_la1(s, f, o);
3672 o->in1 = tcg_temp_new_i64();
3673 tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s));
3674 }
3675
3676 static void in1_m1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3677 {
3678 in1_la1(s, f, o);
3679 o->in1 = tcg_temp_new_i64();
3680 tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s));
3681 }
3682
3683 static void in1_m1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3684 {
3685 in1_la1(s, f, o);
3686 o->in1 = tcg_temp_new_i64();
3687 tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s));
3688 }
3689
3690 static void in1_m1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3691 {
3692 in1_la1(s, f, o);
3693 o->in1 = tcg_temp_new_i64();
3694 tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s));
3695 }
3696
3697 static void in1_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3698 {
3699 in1_la1(s, f, o);
3700 o->in1 = tcg_temp_new_i64();
3701 tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s));
3702 }
3703
3704 /* ====================================================================== */
3705 /* The "INput 2" generators. These load the second operand to an insn. */
3706
3707 static void in2_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3708 {
3709 o->in2 = regs[get_field(f, r1)];
3710 o->g_in2 = true;
3711 }
3712
3713 static void in2_r1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3714 {
3715 o->in2 = tcg_temp_new_i64();
3716 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r1)]);
3717 }
3718
3719 static void in2_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3720 {
3721 o->in2 = tcg_temp_new_i64();
3722 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r1)]);
3723 }
3724
3725 static void in2_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3726 {
3727 o->in2 = load_reg(get_field(f, r2));
3728 }
3729
3730 static void in2_r2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3731 {
3732 o->in2 = regs[get_field(f, r2)];
3733 o->g_in2 = true;
3734 }
3735
3736 static void in2_r2_nz(DisasContext *s, DisasFields *f, DisasOps *o)
3737 {
3738 int r2 = get_field(f, r2);
3739 if (r2 != 0) {
3740 o->in2 = load_reg(r2);
3741 }
3742 }
3743
3744 static void in2_r2_8s(DisasContext *s, DisasFields *f, DisasOps *o)
3745 {
3746 o->in2 = tcg_temp_new_i64();
3747 tcg_gen_ext8s_i64(o->in2, regs[get_field(f, r2)]);
3748 }
3749
3750 static void in2_r2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3751 {
3752 o->in2 = tcg_temp_new_i64();
3753 tcg_gen_ext8u_i64(o->in2, regs[get_field(f, r2)]);
3754 }
3755
3756 static void in2_r2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3757 {
3758 o->in2 = tcg_temp_new_i64();
3759 tcg_gen_ext16s_i64(o->in2, regs[get_field(f, r2)]);
3760 }
3761
3762 static void in2_r2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3763 {
3764 o->in2 = tcg_temp_new_i64();
3765 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r2)]);
3766 }
3767
3768 static void in2_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3769 {
3770 o->in2 = load_reg(get_field(f, r3));
3771 }
3772
3773 static void in2_r2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3774 {
3775 o->in2 = tcg_temp_new_i64();
3776 tcg_gen_ext32s_i64(o->in2, regs[get_field(f, r2)]);
3777 }
3778
3779 static void in2_r2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3780 {
3781 o->in2 = tcg_temp_new_i64();
3782 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r2)]);
3783 }
3784
3785 static void in2_e2(DisasContext *s, DisasFields *f, DisasOps *o)
3786 {
3787 o->in2 = load_freg32_i64(get_field(f, r2));
3788 }
3789
3790 static void in2_f2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3791 {
3792 o->in2 = fregs[get_field(f, r2)];
3793 o->g_in2 = true;
3794 }
3795
3796 static void in2_x2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3797 {
3798 /* ??? Specification exception: r1 must be < 14. */
3799 int r2 = get_field(f, r2);
3800 o->in1 = fregs[r2];
3801 o->in2 = fregs[(r2 + 2) & 15];
3802 o->g_in1 = o->g_in2 = true;
3803 }
3804
3805 static void in2_ra2(DisasContext *s, DisasFields *f, DisasOps *o)
3806 {
3807 o->in2 = get_address(s, 0, get_field(f, r2), 0);
3808 }
3809
3810 static void in2_a2(DisasContext *s, DisasFields *f, DisasOps *o)
3811 {
3812 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3813 o->in2 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3814 }
3815
3816 static void in2_ri2(DisasContext *s, DisasFields *f, DisasOps *o)
3817 {
3818 o->in2 = tcg_const_i64(s->pc + (int64_t)get_field(f, i2) * 2);
3819 }
3820
3821 static void in2_sh32(DisasContext *s, DisasFields *f, DisasOps *o)
3822 {
3823 help_l2_shift(s, f, o, 31);
3824 }
3825
3826 static void in2_sh64(DisasContext *s, DisasFields *f, DisasOps *o)
3827 {
3828 help_l2_shift(s, f, o, 63);
3829 }
3830
3831 static void in2_m2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3832 {
3833 in2_a2(s, f, o);
3834 tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s));
3835 }
3836
3837 static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3838 {
3839 in2_a2(s, f, o);
3840 tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
3841 }
3842
3843 static void in2_m2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3844 {
3845 in2_a2(s, f, o);
3846 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3847 }
3848
3849 static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3850 {
3851 in2_a2(s, f, o);
3852 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3853 }
3854
3855 static void in2_m2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3856 {
3857 in2_a2(s, f, o);
3858 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3859 }
3860
3861 static void in2_m2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3862 {
3863 in2_a2(s, f, o);
3864 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3865 }
3866
3867 static void in2_mri2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3868 {
3869 in2_ri2(s, f, o);
3870 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3871 }
3872
3873 static void in2_mri2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3874 {
3875 in2_ri2(s, f, o);
3876 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3877 }
3878
3879 static void in2_mri2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3880 {
3881 in2_ri2(s, f, o);
3882 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3883 }
3884
3885 static void in2_mri2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3886 {
3887 in2_ri2(s, f, o);
3888 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3889 }
3890
3891 static void in2_i2(DisasContext *s, DisasFields *f, DisasOps *o)
3892 {
3893 o->in2 = tcg_const_i64(get_field(f, i2));
3894 }
3895
3896 static void in2_i2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3897 {
3898 o->in2 = tcg_const_i64((uint8_t)get_field(f, i2));
3899 }
3900
3901 static void in2_i2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3902 {
3903 o->in2 = tcg_const_i64((uint16_t)get_field(f, i2));
3904 }
3905
3906 static void in2_i2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3907 {
3908 o->in2 = tcg_const_i64((uint32_t)get_field(f, i2));
3909 }
3910
3911 static void in2_i2_16u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
3912 {
3913 uint64_t i2 = (uint16_t)get_field(f, i2);
3914 o->in2 = tcg_const_i64(i2 << s->insn->data);
3915 }
3916
3917 static void in2_i2_32u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
3918 {
3919 uint64_t i2 = (uint32_t)get_field(f, i2);
3920 o->in2 = tcg_const_i64(i2 << s->insn->data);
3921 }
3922
3923 /* ====================================================================== */
3924
3925 /* Find opc within the table of insns. This is formulated as a switch
3926 statement so that (1) we get compile-time notice of cut-paste errors
3927 for duplicated opcodes, and (2) the compiler generates the binary
3928 search tree, rather than us having to post-process the table. */
3929
3930 #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \
3931 D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0)
3932
3933 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) insn_ ## NM,
3934
3935 enum DisasInsnEnum {
3936 #include "insn-data.def"
3937 };
3938
3939 #undef D
3940 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) { \
3941 .opc = OPC, \
3942 .fmt = FMT_##FT, \
3943 .fac = FAC_##FC, \
3944 .name = #NM, \
3945 .help_in1 = in1_##I1, \
3946 .help_in2 = in2_##I2, \
3947 .help_prep = prep_##P, \
3948 .help_wout = wout_##W, \
3949 .help_cout = cout_##CC, \
3950 .help_op = op_##OP, \
3951 .data = D \
3952 },
3953
3954 /* Allow 0 to be used for NULL in the table below. */
3955 #define in1_0 NULL
3956 #define in2_0 NULL
3957 #define prep_0 NULL
3958 #define wout_0 NULL
3959 #define cout_0 NULL
3960 #define op_0 NULL
3961
3962 static const DisasInsn insn_info[] = {
3963 #include "insn-data.def"
3964 };
3965
3966 #undef D
3967 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \
3968 case OPC: return &insn_info[insn_ ## NM];
3969
3970 static const DisasInsn *lookup_opc(uint16_t opc)
3971 {
3972 switch (opc) {
3973 #include "insn-data.def"
3974 default:
3975 return NULL;
3976 }
3977 }
3978
3979 #undef D
3980 #undef C
3981
3982 /* Extract a field from the insn. The INSN should be left-aligned in
3983 the uint64_t so that we can more easily utilize the big-bit-endian
3984 definitions we extract from the Principals of Operation. */
3985
3986 static void extract_field(DisasFields *o, const DisasField *f, uint64_t insn)
3987 {
3988 uint32_t r, m;
3989
3990 if (f->size == 0) {
3991 return;
3992 }
3993
3994 /* Zero extract the field from the insn. */
3995 r = (insn << f->beg) >> (64 - f->size);
3996
3997 /* Sign-extend, or un-swap the field as necessary. */
3998 switch (f->type) {
3999 case 0: /* unsigned */
4000 break;
4001 case 1: /* signed */
4002 assert(f->size <= 32);
4003 m = 1u << (f->size - 1);
4004 r = (r ^ m) - m;
4005 break;
4006 case 2: /* dl+dh split, signed 20 bit. */
4007 r = ((int8_t)r << 12) | (r >> 8);
4008 break;
4009 default:
4010 abort();
4011 }
4012
4013 /* Validate that the "compressed" encoding we selected above is valid.
4014 I.e. we havn't make two different original fields overlap. */
4015 assert(((o->presentC >> f->indexC) & 1) == 0);
4016 o->presentC |= 1 << f->indexC;
4017 o->presentO |= 1 << f->indexO;
4018
4019 o->c[f->indexC] = r;
4020 }
4021
4022 /* Lookup the insn at the current PC, extracting the operands into O and
4023 returning the info struct for the insn. Returns NULL for invalid insn. */
4024
4025 static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
4026 DisasFields *f)
4027 {
4028 uint64_t insn, pc = s->pc;
4029 int op, op2, ilen;
4030 const DisasInsn *info;
4031
4032 insn = ld_code2(env, pc);
4033 op = (insn >> 8) & 0xff;
4034 ilen = get_ilen(op);
4035 s->next_pc = s->pc + ilen;
4036
4037 switch (ilen) {
4038 case 2:
4039 insn = insn << 48;
4040 break;
4041 case 4:
4042 insn = ld_code4(env, pc) << 32;
4043 break;
4044 case 6:
4045 insn = (insn << 48) | (ld_code4(env, pc + 2) << 16);
4046 break;
4047 default:
4048 abort();
4049 }
4050
4051 /* We can't actually determine the insn format until we've looked up
4052 the full insn opcode. Which we can't do without locating the
4053 secondary opcode. Assume by default that OP2 is at bit 40; for
4054 those smaller insns that don't actually have a secondary opcode
4055 this will correctly result in OP2 = 0. */
4056 switch (op) {
4057 case 0x01: /* E */
4058 case 0x80: /* S */
4059 case 0x82: /* S */
4060 case 0x93: /* S */
4061 case 0xb2: /* S, RRF, RRE */
4062 case 0xb3: /* RRE, RRD, RRF */
4063 case 0xb9: /* RRE, RRF */
4064 case 0xe5: /* SSE, SIL */
4065 op2 = (insn << 8) >> 56;
4066 break;
4067 case 0xa5: /* RI */
4068 case 0xa7: /* RI */
4069 case 0xc0: /* RIL */
4070 case 0xc2: /* RIL */
4071 case 0xc4: /* RIL */
4072 case 0xc6: /* RIL */
4073 case 0xc8: /* SSF */
4074 case 0xcc: /* RIL */
4075 op2 = (insn << 12) >> 60;
4076 break;
4077 case 0xd0 ... 0xdf: /* SS */
4078 case 0xe1: /* SS */
4079 case 0xe2: /* SS */
4080 case 0xe8: /* SS */
4081 case 0xe9: /* SS */
4082 case 0xea: /* SS */
4083 case 0xee ... 0xf3: /* SS */
4084 case 0xf8 ... 0xfd: /* SS */
4085 op2 = 0;
4086 break;
4087 default:
4088 op2 = (insn << 40) >> 56;
4089 break;
4090 }
4091
4092 memset(f, 0, sizeof(*f));
4093 f->op = op;
4094 f->op2 = op2;
4095
4096 /* Lookup the instruction. */
4097 info = lookup_opc(op << 8 | op2);
4098
4099 /* If we found it, extract the operands. */
4100 if (info != NULL) {
4101 DisasFormat fmt = info->fmt;
4102 int i;
4103
4104 for (i = 0; i < NUM_C_FIELD; ++i) {
4105 extract_field(f, &format_info[fmt].op[i], insn);
4106 }
4107 }
4108 return info;
4109 }
4110
4111 static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
4112 {
4113 const DisasInsn *insn;
4114 ExitStatus ret = NO_EXIT;
4115 DisasFields f;
4116 DisasOps o;
4117
4118 insn = extract_insn(env, s, &f);
4119
4120 /* If not found, try the old interpreter. This includes ILLOPC. */
4121 if (insn == NULL) {
4122 disas_s390_insn(env, s);
4123 switch (s->is_jmp) {
4124 case DISAS_NEXT:
4125 ret = NO_EXIT;
4126 break;
4127 case DISAS_TB_JUMP:
4128 ret = EXIT_GOTO_TB;
4129 break;
4130 case DISAS_JUMP:
4131 ret = EXIT_PC_UPDATED;
4132 break;
4133 case DISAS_EXCP:
4134 ret = EXIT_NORETURN;
4135 break;
4136 default:
4137 abort();
4138 }
4139
4140 s->pc = s->next_pc;
4141 return ret;
4142 }
4143
4144 /* Set up the strutures we use to communicate with the helpers. */
4145 s->insn = insn;
4146 s->fields = &f;
4147 o.g_out = o.g_out2 = o.g_in1 = o.g_in2 = false;
4148 TCGV_UNUSED_I64(o.out);
4149 TCGV_UNUSED_I64(o.out2);
4150 TCGV_UNUSED_I64(o.in1);
4151 TCGV_UNUSED_I64(o.in2);
4152 TCGV_UNUSED_I64(o.addr1);
4153
4154 /* Implement the instruction. */
4155 if (insn->help_in1) {
4156 insn->help_in1(s, &f, &o);
4157 }
4158 if (insn->help_in2) {
4159 insn->help_in2(s, &f, &o);
4160 }
4161 if (insn->help_prep) {
4162 insn->help_prep(s, &f, &o);
4163 }
4164 if (insn->help_op) {
4165 ret = insn->help_op(s, &o);
4166 }
4167 if (insn->help_wout) {
4168 insn->help_wout(s, &f, &o);
4169 }
4170 if (insn->help_cout) {
4171 insn->help_cout(s, &o);
4172 }
4173
4174 /* Free any temporaries created by the helpers. */
4175 if (!TCGV_IS_UNUSED_I64(o.out) && !o.g_out) {
4176 tcg_temp_free_i64(o.out);
4177 }
4178 if (!TCGV_IS_UNUSED_I64(o.out2) && !o.g_out2) {
4179 tcg_temp_free_i64(o.out2);
4180 }
4181 if (!TCGV_IS_UNUSED_I64(o.in1) && !o.g_in1) {
4182 tcg_temp_free_i64(o.in1);
4183 }
4184 if (!TCGV_IS_UNUSED_I64(o.in2) && !o.g_in2) {
4185 tcg_temp_free_i64(o.in2);
4186 }
4187 if (!TCGV_IS_UNUSED_I64(o.addr1)) {
4188 tcg_temp_free_i64(o.addr1);
4189 }
4190
4191 /* Advance to the next instruction. */
4192 s->pc = s->next_pc;
4193 return ret;
4194 }
4195
4196 static inline void gen_intermediate_code_internal(CPUS390XState *env,
4197 TranslationBlock *tb,
4198 int search_pc)
4199 {
4200 DisasContext dc;
4201 target_ulong pc_start;
4202 uint64_t next_page_start;
4203 uint16_t *gen_opc_end;
4204 int j, lj = -1;
4205 int num_insns, max_insns;
4206 CPUBreakpoint *bp;
4207 ExitStatus status;
4208 bool do_debug;
4209
4210 pc_start = tb->pc;
4211
4212 /* 31-bit mode */
4213 if (!(tb->flags & FLAG_MASK_64)) {
4214 pc_start &= 0x7fffffff;
4215 }
4216
4217 dc.tb = tb;
4218 dc.pc = pc_start;
4219 dc.cc_op = CC_OP_DYNAMIC;
4220 do_debug = dc.singlestep_enabled = env->singlestep_enabled;
4221 dc.is_jmp = DISAS_NEXT;
4222
4223 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
4224
4225 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4226
4227 num_insns = 0;
4228 max_insns = tb->cflags & CF_COUNT_MASK;
4229 if (max_insns == 0) {
4230 max_insns = CF_COUNT_MASK;
4231 }
4232
4233 gen_icount_start();
4234
4235 do {
4236 if (search_pc) {
4237 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4238 if (lj < j) {
4239 lj++;
4240 while (lj < j) {
4241 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4242 }
4243 }
4244 tcg_ctx.gen_opc_pc[lj] = dc.pc;
4245 gen_opc_cc_op[lj] = dc.cc_op;
4246 tcg_ctx.gen_opc_instr_start[lj] = 1;
4247 tcg_ctx.gen_opc_icount[lj] = num_insns;
4248 }
4249 if (++num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
4250 gen_io_start();
4251 }
4252
4253 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
4254 tcg_gen_debug_insn_start(dc.pc);
4255 }
4256
4257 status = NO_EXIT;
4258 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
4259 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
4260 if (bp->pc == dc.pc) {
4261 status = EXIT_PC_STALE;
4262 do_debug = true;
4263 break;
4264 }
4265 }
4266 }
4267 if (status == NO_EXIT) {
4268 status = translate_one(env, &dc);
4269 }
4270
4271 /* If we reach a page boundary, are single stepping,
4272 or exhaust instruction count, stop generation. */
4273 if (status == NO_EXIT
4274 && (dc.pc >= next_page_start
4275 || tcg_ctx.gen_opc_ptr >= gen_opc_end
4276 || num_insns >= max_insns
4277 || singlestep
4278 || env->singlestep_enabled)) {
4279 status = EXIT_PC_STALE;
4280 }
4281 } while (status == NO_EXIT);
4282
4283 if (tb->cflags & CF_LAST_IO) {
4284 gen_io_end();
4285 }
4286
4287 switch (status) {
4288 case EXIT_GOTO_TB:
4289 case EXIT_NORETURN:
4290 break;
4291 case EXIT_PC_STALE:
4292 update_psw_addr(&dc);
4293 /* FALLTHRU */
4294 case EXIT_PC_UPDATED:
4295 if (singlestep && dc.cc_op != CC_OP_DYNAMIC) {
4296 gen_op_calc_cc(&dc);
4297 } else {
4298 /* Next TB starts off with CC_OP_DYNAMIC,
4299 so make sure the cc op type is in env */
4300 gen_op_set_cc_op(&dc);
4301 }
4302 if (do_debug) {
4303 gen_exception(EXCP_DEBUG);
4304 } else {
4305 /* Generate the return instruction */
4306 tcg_gen_exit_tb(0);
4307 }
4308 break;
4309 default:
4310 abort();
4311 }
4312
4313 gen_icount_end(tb, num_insns);
4314 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
4315 if (search_pc) {
4316 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4317 lj++;
4318 while (lj <= j) {
4319 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4320 }
4321 } else {
4322 tb->size = dc.pc - pc_start;
4323 tb->icount = num_insns;
4324 }
4325
4326 #if defined(S390X_DEBUG_DISAS)
4327 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
4328 qemu_log("IN: %s\n", lookup_symbol(pc_start));
4329 log_target_disas(env, pc_start, dc.pc - pc_start, 1);
4330 qemu_log("\n");
4331 }
4332 #endif
4333 }
4334
4335 void gen_intermediate_code (CPUS390XState *env, struct TranslationBlock *tb)
4336 {
4337 gen_intermediate_code_internal(env, tb, 0);
4338 }
4339
4340 void gen_intermediate_code_pc (CPUS390XState *env, struct TranslationBlock *tb)
4341 {
4342 gen_intermediate_code_internal(env, tb, 1);
4343 }
4344
4345 void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, int pc_pos)
4346 {
4347 int cc_op;
4348 env->psw.addr = tcg_ctx.gen_opc_pc[pc_pos];
4349 cc_op = gen_opc_cc_op[pc_pos];
4350 if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {
4351 env->cc_op = cc_op;
4352 }
4353 }
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