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target-s390: Convert LRA
[mirror_qemu.git] / target-s390x / translate.c
1 /*
2 * S/390 translation
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* #define DEBUG_INLINE_BRANCHES */
22 #define S390X_DEBUG_DISAS
23 /* #define S390X_DEBUG_DISAS_VERBOSE */
24
25 #ifdef S390X_DEBUG_DISAS_VERBOSE
26 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
27 #else
28 # define LOG_DISAS(...) do { } while (0)
29 #endif
30
31 #include "cpu.h"
32 #include "disas/disas.h"
33 #include "tcg-op.h"
34 #include "qemu/log.h"
35 #include "qemu/host-utils.h"
36
37 /* global register indexes */
38 static TCGv_ptr cpu_env;
39
40 #include "exec/gen-icount.h"
41 #include "helper.h"
42 #define GEN_HELPER 1
43 #include "helper.h"
44
45
46 /* Information that (most) every instruction needs to manipulate. */
47 typedef struct DisasContext DisasContext;
48 typedef struct DisasInsn DisasInsn;
49 typedef struct DisasFields DisasFields;
50
51 struct DisasContext {
52 struct TranslationBlock *tb;
53 const DisasInsn *insn;
54 DisasFields *fields;
55 uint64_t pc, next_pc;
56 enum cc_op cc_op;
57 bool singlestep_enabled;
58 int is_jmp;
59 };
60
61 /* Information carried about a condition to be evaluated. */
62 typedef struct {
63 TCGCond cond:8;
64 bool is_64;
65 bool g1;
66 bool g2;
67 union {
68 struct { TCGv_i64 a, b; } s64;
69 struct { TCGv_i32 a, b; } s32;
70 } u;
71 } DisasCompare;
72
73 #define DISAS_EXCP 4
74
75 static void gen_op_calc_cc(DisasContext *s);
76
77 #ifdef DEBUG_INLINE_BRANCHES
78 static uint64_t inline_branch_hit[CC_OP_MAX];
79 static uint64_t inline_branch_miss[CC_OP_MAX];
80 #endif
81
82 static inline void debug_insn(uint64_t insn)
83 {
84 LOG_DISAS("insn: 0x%" PRIx64 "\n", insn);
85 }
86
87 static inline uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
88 {
89 if (!(s->tb->flags & FLAG_MASK_64)) {
90 if (s->tb->flags & FLAG_MASK_32) {
91 return pc | 0x80000000;
92 }
93 }
94 return pc;
95 }
96
97 void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
98 int flags)
99 {
100 int i;
101
102 if (env->cc_op > 3) {
103 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
104 env->psw.mask, env->psw.addr, cc_name(env->cc_op));
105 } else {
106 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
107 env->psw.mask, env->psw.addr, env->cc_op);
108 }
109
110 for (i = 0; i < 16; i++) {
111 cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
112 if ((i % 4) == 3) {
113 cpu_fprintf(f, "\n");
114 } else {
115 cpu_fprintf(f, " ");
116 }
117 }
118
119 for (i = 0; i < 16; i++) {
120 cpu_fprintf(f, "F%02d=%016" PRIx64, i, env->fregs[i].ll);
121 if ((i % 4) == 3) {
122 cpu_fprintf(f, "\n");
123 } else {
124 cpu_fprintf(f, " ");
125 }
126 }
127
128 #ifndef CONFIG_USER_ONLY
129 for (i = 0; i < 16; i++) {
130 cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
131 if ((i % 4) == 3) {
132 cpu_fprintf(f, "\n");
133 } else {
134 cpu_fprintf(f, " ");
135 }
136 }
137 #endif
138
139 #ifdef DEBUG_INLINE_BRANCHES
140 for (i = 0; i < CC_OP_MAX; i++) {
141 cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
142 inline_branch_miss[i], inline_branch_hit[i]);
143 }
144 #endif
145
146 cpu_fprintf(f, "\n");
147 }
148
149 static TCGv_i64 psw_addr;
150 static TCGv_i64 psw_mask;
151
152 static TCGv_i32 cc_op;
153 static TCGv_i64 cc_src;
154 static TCGv_i64 cc_dst;
155 static TCGv_i64 cc_vr;
156
157 static char cpu_reg_names[32][4];
158 static TCGv_i64 regs[16];
159 static TCGv_i64 fregs[16];
160
161 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
162
163 void s390x_translate_init(void)
164 {
165 int i;
166
167 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
168 psw_addr = tcg_global_mem_new_i64(TCG_AREG0,
169 offsetof(CPUS390XState, psw.addr),
170 "psw_addr");
171 psw_mask = tcg_global_mem_new_i64(TCG_AREG0,
172 offsetof(CPUS390XState, psw.mask),
173 "psw_mask");
174
175 cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUS390XState, cc_op),
176 "cc_op");
177 cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_src),
178 "cc_src");
179 cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_dst),
180 "cc_dst");
181 cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_vr),
182 "cc_vr");
183
184 for (i = 0; i < 16; i++) {
185 snprintf(cpu_reg_names[i], sizeof(cpu_reg_names[0]), "r%d", i);
186 regs[i] = tcg_global_mem_new(TCG_AREG0,
187 offsetof(CPUS390XState, regs[i]),
188 cpu_reg_names[i]);
189 }
190
191 for (i = 0; i < 16; i++) {
192 snprintf(cpu_reg_names[i + 16], sizeof(cpu_reg_names[0]), "f%d", i);
193 fregs[i] = tcg_global_mem_new(TCG_AREG0,
194 offsetof(CPUS390XState, fregs[i].d),
195 cpu_reg_names[i + 16]);
196 }
197
198 /* register helpers */
199 #define GEN_HELPER 2
200 #include "helper.h"
201 }
202
203 static inline TCGv_i64 load_reg(int reg)
204 {
205 TCGv_i64 r = tcg_temp_new_i64();
206 tcg_gen_mov_i64(r, regs[reg]);
207 return r;
208 }
209
210 static inline TCGv_i64 load_freg(int reg)
211 {
212 TCGv_i64 r = tcg_temp_new_i64();
213 tcg_gen_mov_i64(r, fregs[reg]);
214 return r;
215 }
216
217 static inline TCGv_i32 load_freg32(int reg)
218 {
219 TCGv_i32 r = tcg_temp_new_i32();
220 #if HOST_LONG_BITS == 32
221 tcg_gen_mov_i32(r, TCGV_HIGH(fregs[reg]));
222 #else
223 tcg_gen_shri_i64(MAKE_TCGV_I64(GET_TCGV_I32(r)), fregs[reg], 32);
224 #endif
225 return r;
226 }
227
228 static inline TCGv_i64 load_freg32_i64(int reg)
229 {
230 TCGv_i64 r = tcg_temp_new_i64();
231 tcg_gen_shri_i64(r, fregs[reg], 32);
232 return r;
233 }
234
235 static inline TCGv_i32 load_reg32(int reg)
236 {
237 TCGv_i32 r = tcg_temp_new_i32();
238 tcg_gen_trunc_i64_i32(r, regs[reg]);
239 return r;
240 }
241
242 static inline TCGv_i64 load_reg32_i64(int reg)
243 {
244 TCGv_i64 r = tcg_temp_new_i64();
245 tcg_gen_ext32s_i64(r, regs[reg]);
246 return r;
247 }
248
249 static inline void store_reg(int reg, TCGv_i64 v)
250 {
251 tcg_gen_mov_i64(regs[reg], v);
252 }
253
254 static inline void store_freg(int reg, TCGv_i64 v)
255 {
256 tcg_gen_mov_i64(fregs[reg], v);
257 }
258
259 static inline void store_reg32(int reg, TCGv_i32 v)
260 {
261 /* 32 bit register writes keep the upper half */
262 #if HOST_LONG_BITS == 32
263 tcg_gen_mov_i32(TCGV_LOW(regs[reg]), v);
264 #else
265 tcg_gen_deposit_i64(regs[reg], regs[reg],
266 MAKE_TCGV_I64(GET_TCGV_I32(v)), 0, 32);
267 #endif
268 }
269
270 static inline void store_reg32_i64(int reg, TCGv_i64 v)
271 {
272 /* 32 bit register writes keep the upper half */
273 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
274 }
275
276 static inline void store_reg32h_i64(int reg, TCGv_i64 v)
277 {
278 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 32, 32);
279 }
280
281 static inline void store_reg16(int reg, TCGv_i32 v)
282 {
283 /* 16 bit register writes keep the upper bytes */
284 #if HOST_LONG_BITS == 32
285 tcg_gen_deposit_i32(TCGV_LOW(regs[reg]), TCGV_LOW(regs[reg]), v, 0, 16);
286 #else
287 tcg_gen_deposit_i64(regs[reg], regs[reg],
288 MAKE_TCGV_I64(GET_TCGV_I32(v)), 0, 16);
289 #endif
290 }
291
292 static inline void store_freg32(int reg, TCGv_i32 v)
293 {
294 /* 32 bit register writes keep the lower half */
295 #if HOST_LONG_BITS == 32
296 tcg_gen_mov_i32(TCGV_HIGH(fregs[reg]), v);
297 #else
298 tcg_gen_deposit_i64(fregs[reg], fregs[reg],
299 MAKE_TCGV_I64(GET_TCGV_I32(v)), 32, 32);
300 #endif
301 }
302
303 static inline void store_freg32_i64(int reg, TCGv_i64 v)
304 {
305 tcg_gen_deposit_i64(fregs[reg], fregs[reg], v, 32, 32);
306 }
307
308 static inline void return_low128(TCGv_i64 dest)
309 {
310 tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl));
311 }
312
313 static inline void update_psw_addr(DisasContext *s)
314 {
315 /* psw.addr */
316 tcg_gen_movi_i64(psw_addr, s->pc);
317 }
318
319 static inline void potential_page_fault(DisasContext *s)
320 {
321 #ifndef CONFIG_USER_ONLY
322 update_psw_addr(s);
323 gen_op_calc_cc(s);
324 #endif
325 }
326
327 static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
328 {
329 return (uint64_t)cpu_lduw_code(env, pc);
330 }
331
332 static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
333 {
334 return (uint64_t)(uint32_t)cpu_ldl_code(env, pc);
335 }
336
337 static inline uint64_t ld_code6(CPUS390XState *env, uint64_t pc)
338 {
339 return (ld_code2(env, pc) << 32) | ld_code4(env, pc + 2);
340 }
341
342 static inline int get_mem_index(DisasContext *s)
343 {
344 switch (s->tb->flags & FLAG_MASK_ASC) {
345 case PSW_ASC_PRIMARY >> 32:
346 return 0;
347 case PSW_ASC_SECONDARY >> 32:
348 return 1;
349 case PSW_ASC_HOME >> 32:
350 return 2;
351 default:
352 tcg_abort();
353 break;
354 }
355 }
356
357 static void gen_exception(int excp)
358 {
359 TCGv_i32 tmp = tcg_const_i32(excp);
360 gen_helper_exception(cpu_env, tmp);
361 tcg_temp_free_i32(tmp);
362 }
363
364 static void gen_program_exception(DisasContext *s, int code)
365 {
366 TCGv_i32 tmp;
367
368 /* Remember what pgm exeption this was. */
369 tmp = tcg_const_i32(code);
370 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
371 tcg_temp_free_i32(tmp);
372
373 tmp = tcg_const_i32(s->next_pc - s->pc);
374 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen));
375 tcg_temp_free_i32(tmp);
376
377 /* Advance past instruction. */
378 s->pc = s->next_pc;
379 update_psw_addr(s);
380
381 /* Save off cc. */
382 gen_op_calc_cc(s);
383
384 /* Trigger exception. */
385 gen_exception(EXCP_PGM);
386
387 /* End TB here. */
388 s->is_jmp = DISAS_EXCP;
389 }
390
391 static inline void gen_illegal_opcode(DisasContext *s)
392 {
393 gen_program_exception(s, PGM_SPECIFICATION);
394 }
395
396 static inline void check_privileged(DisasContext *s)
397 {
398 if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
399 gen_program_exception(s, PGM_PRIVILEGED);
400 }
401 }
402
403 static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
404 {
405 TCGv_i64 tmp;
406
407 /* 31-bitify the immediate part; register contents are dealt with below */
408 if (!(s->tb->flags & FLAG_MASK_64)) {
409 d2 &= 0x7fffffffUL;
410 }
411
412 if (x2) {
413 if (d2) {
414 tmp = tcg_const_i64(d2);
415 tcg_gen_add_i64(tmp, tmp, regs[x2]);
416 } else {
417 tmp = load_reg(x2);
418 }
419 if (b2) {
420 tcg_gen_add_i64(tmp, tmp, regs[b2]);
421 }
422 } else if (b2) {
423 if (d2) {
424 tmp = tcg_const_i64(d2);
425 tcg_gen_add_i64(tmp, tmp, regs[b2]);
426 } else {
427 tmp = load_reg(b2);
428 }
429 } else {
430 tmp = tcg_const_i64(d2);
431 }
432
433 /* 31-bit mode mask if there are values loaded from registers */
434 if (!(s->tb->flags & FLAG_MASK_64) && (x2 || b2)) {
435 tcg_gen_andi_i64(tmp, tmp, 0x7fffffffUL);
436 }
437
438 return tmp;
439 }
440
441 static void gen_op_movi_cc(DisasContext *s, uint32_t val)
442 {
443 s->cc_op = CC_OP_CONST0 + val;
444 }
445
446 static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst)
447 {
448 tcg_gen_discard_i64(cc_src);
449 tcg_gen_mov_i64(cc_dst, dst);
450 tcg_gen_discard_i64(cc_vr);
451 s->cc_op = op;
452 }
453
454 static void gen_op_update1_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 dst)
455 {
456 tcg_gen_discard_i64(cc_src);
457 tcg_gen_extu_i32_i64(cc_dst, dst);
458 tcg_gen_discard_i64(cc_vr);
459 s->cc_op = op;
460 }
461
462 static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
463 TCGv_i64 dst)
464 {
465 tcg_gen_mov_i64(cc_src, src);
466 tcg_gen_mov_i64(cc_dst, dst);
467 tcg_gen_discard_i64(cc_vr);
468 s->cc_op = op;
469 }
470
471 static void gen_op_update2_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 src,
472 TCGv_i32 dst)
473 {
474 tcg_gen_extu_i32_i64(cc_src, src);
475 tcg_gen_extu_i32_i64(cc_dst, dst);
476 tcg_gen_discard_i64(cc_vr);
477 s->cc_op = op;
478 }
479
480 static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
481 TCGv_i64 dst, TCGv_i64 vr)
482 {
483 tcg_gen_mov_i64(cc_src, src);
484 tcg_gen_mov_i64(cc_dst, dst);
485 tcg_gen_mov_i64(cc_vr, vr);
486 s->cc_op = op;
487 }
488
489 static inline void set_cc_nz_u32(DisasContext *s, TCGv_i32 val)
490 {
491 gen_op_update1_cc_i32(s, CC_OP_NZ, val);
492 }
493
494 static inline void set_cc_nz_u64(DisasContext *s, TCGv_i64 val)
495 {
496 gen_op_update1_cc_i64(s, CC_OP_NZ, val);
497 }
498
499 static inline void cmp_32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
500 enum cc_op cond)
501 {
502 gen_op_update2_cc_i32(s, cond, v1, v2);
503 }
504
505 static inline void cmp_64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
506 enum cc_op cond)
507 {
508 gen_op_update2_cc_i64(s, cond, v1, v2);
509 }
510
511 static inline void cmp_s32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
512 {
513 cmp_32(s, v1, v2, CC_OP_LTGT_32);
514 }
515
516 static inline void cmp_u32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
517 {
518 cmp_32(s, v1, v2, CC_OP_LTUGTU_32);
519 }
520
521 static inline void cmp_s32c(DisasContext *s, TCGv_i32 v1, int32_t v2)
522 {
523 /* XXX optimize for the constant? put it in s? */
524 TCGv_i32 tmp = tcg_const_i32(v2);
525 cmp_32(s, v1, tmp, CC_OP_LTGT_32);
526 tcg_temp_free_i32(tmp);
527 }
528
529 static inline void cmp_u32c(DisasContext *s, TCGv_i32 v1, uint32_t v2)
530 {
531 TCGv_i32 tmp = tcg_const_i32(v2);
532 cmp_32(s, v1, tmp, CC_OP_LTUGTU_32);
533 tcg_temp_free_i32(tmp);
534 }
535
536 static inline void cmp_s64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
537 {
538 cmp_64(s, v1, v2, CC_OP_LTGT_64);
539 }
540
541 static inline void cmp_u64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
542 {
543 cmp_64(s, v1, v2, CC_OP_LTUGTU_64);
544 }
545
546 static inline void cmp_s64c(DisasContext *s, TCGv_i64 v1, int64_t v2)
547 {
548 TCGv_i64 tmp = tcg_const_i64(v2);
549 cmp_s64(s, v1, tmp);
550 tcg_temp_free_i64(tmp);
551 }
552
553 static inline void cmp_u64c(DisasContext *s, TCGv_i64 v1, uint64_t v2)
554 {
555 TCGv_i64 tmp = tcg_const_i64(v2);
556 cmp_u64(s, v1, tmp);
557 tcg_temp_free_i64(tmp);
558 }
559
560 static inline void set_cc_s32(DisasContext *s, TCGv_i32 val)
561 {
562 gen_op_update1_cc_i32(s, CC_OP_LTGT0_32, val);
563 }
564
565 static inline void set_cc_s64(DisasContext *s, TCGv_i64 val)
566 {
567 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, val);
568 }
569
570 static void set_cc_cmp_f32_i64(DisasContext *s, TCGv_i32 v1, TCGv_i64 v2)
571 {
572 tcg_gen_extu_i32_i64(cc_src, v1);
573 tcg_gen_mov_i64(cc_dst, v2);
574 tcg_gen_discard_i64(cc_vr);
575 s->cc_op = CC_OP_LTGT_F32;
576 }
577
578 static void gen_set_cc_nz_f32(DisasContext *s, TCGv_i32 v1)
579 {
580 gen_op_update1_cc_i32(s, CC_OP_NZ_F32, v1);
581 }
582
583 /* CC value is in env->cc_op */
584 static inline void set_cc_static(DisasContext *s)
585 {
586 tcg_gen_discard_i64(cc_src);
587 tcg_gen_discard_i64(cc_dst);
588 tcg_gen_discard_i64(cc_vr);
589 s->cc_op = CC_OP_STATIC;
590 }
591
592 static inline void gen_op_set_cc_op(DisasContext *s)
593 {
594 if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) {
595 tcg_gen_movi_i32(cc_op, s->cc_op);
596 }
597 }
598
599 static inline void gen_update_cc_op(DisasContext *s)
600 {
601 gen_op_set_cc_op(s);
602 }
603
604 /* calculates cc into cc_op */
605 static void gen_op_calc_cc(DisasContext *s)
606 {
607 TCGv_i32 local_cc_op = tcg_const_i32(s->cc_op);
608 TCGv_i64 dummy = tcg_const_i64(0);
609
610 switch (s->cc_op) {
611 case CC_OP_CONST0:
612 case CC_OP_CONST1:
613 case CC_OP_CONST2:
614 case CC_OP_CONST3:
615 /* s->cc_op is the cc value */
616 tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
617 break;
618 case CC_OP_STATIC:
619 /* env->cc_op already is the cc value */
620 break;
621 case CC_OP_NZ:
622 case CC_OP_ABS_64:
623 case CC_OP_NABS_64:
624 case CC_OP_ABS_32:
625 case CC_OP_NABS_32:
626 case CC_OP_LTGT0_32:
627 case CC_OP_LTGT0_64:
628 case CC_OP_COMP_32:
629 case CC_OP_COMP_64:
630 case CC_OP_NZ_F32:
631 case CC_OP_NZ_F64:
632 /* 1 argument */
633 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dummy);
634 break;
635 case CC_OP_ICM:
636 case CC_OP_LTGT_32:
637 case CC_OP_LTGT_64:
638 case CC_OP_LTUGTU_32:
639 case CC_OP_LTUGTU_64:
640 case CC_OP_TM_32:
641 case CC_OP_TM_64:
642 case CC_OP_LTGT_F32:
643 case CC_OP_LTGT_F64:
644 case CC_OP_SLA_32:
645 case CC_OP_SLA_64:
646 /* 2 arguments */
647 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
648 break;
649 case CC_OP_ADD_64:
650 case CC_OP_ADDU_64:
651 case CC_OP_ADDC_64:
652 case CC_OP_SUB_64:
653 case CC_OP_SUBU_64:
654 case CC_OP_SUBB_64:
655 case CC_OP_ADD_32:
656 case CC_OP_ADDU_32:
657 case CC_OP_ADDC_32:
658 case CC_OP_SUB_32:
659 case CC_OP_SUBU_32:
660 case CC_OP_SUBB_32:
661 /* 3 arguments */
662 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc_vr);
663 break;
664 case CC_OP_DYNAMIC:
665 /* unknown operation - assume 3 arguments and cc_op in env */
666 gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr);
667 break;
668 default:
669 tcg_abort();
670 }
671
672 tcg_temp_free_i32(local_cc_op);
673 tcg_temp_free_i64(dummy);
674
675 /* We now have cc in cc_op as constant */
676 set_cc_static(s);
677 }
678
679 static inline void decode_rr(DisasContext *s, uint64_t insn, int *r1, int *r2)
680 {
681 debug_insn(insn);
682
683 *r1 = (insn >> 4) & 0xf;
684 *r2 = insn & 0xf;
685 }
686
687 static inline TCGv_i64 decode_rx(DisasContext *s, uint64_t insn, int *r1,
688 int *x2, int *b2, int *d2)
689 {
690 debug_insn(insn);
691
692 *r1 = (insn >> 20) & 0xf;
693 *x2 = (insn >> 16) & 0xf;
694 *b2 = (insn >> 12) & 0xf;
695 *d2 = insn & 0xfff;
696
697 return get_address(s, *x2, *b2, *d2);
698 }
699
700 static inline void decode_rs(DisasContext *s, uint64_t insn, int *r1, int *r3,
701 int *b2, int *d2)
702 {
703 debug_insn(insn);
704
705 *r1 = (insn >> 20) & 0xf;
706 /* aka m3 */
707 *r3 = (insn >> 16) & 0xf;
708 *b2 = (insn >> 12) & 0xf;
709 *d2 = insn & 0xfff;
710 }
711
712 static inline TCGv_i64 decode_si(DisasContext *s, uint64_t insn, int *i2,
713 int *b1, int *d1)
714 {
715 debug_insn(insn);
716
717 *i2 = (insn >> 16) & 0xff;
718 *b1 = (insn >> 12) & 0xf;
719 *d1 = insn & 0xfff;
720
721 return get_address(s, 0, *b1, *d1);
722 }
723
724 static int use_goto_tb(DisasContext *s, uint64_t dest)
725 {
726 /* NOTE: we handle the case where the TB spans two pages here */
727 return (((dest & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK)
728 || (dest & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK))
729 && !s->singlestep_enabled
730 && !(s->tb->cflags & CF_LAST_IO));
731 }
732
733 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong pc)
734 {
735 gen_update_cc_op(s);
736
737 if (use_goto_tb(s, pc)) {
738 tcg_gen_goto_tb(tb_num);
739 tcg_gen_movi_i64(psw_addr, pc);
740 tcg_gen_exit_tb((tcg_target_long)s->tb + tb_num);
741 } else {
742 /* jump to another page: currently not optimized */
743 tcg_gen_movi_i64(psw_addr, pc);
744 tcg_gen_exit_tb(0);
745 }
746 }
747
748 static inline void account_noninline_branch(DisasContext *s, int cc_op)
749 {
750 #ifdef DEBUG_INLINE_BRANCHES
751 inline_branch_miss[cc_op]++;
752 #endif
753 }
754
755 static inline void account_inline_branch(DisasContext *s, int cc_op)
756 {
757 #ifdef DEBUG_INLINE_BRANCHES
758 inline_branch_hit[cc_op]++;
759 #endif
760 }
761
762 /* Table of mask values to comparison codes, given a comparison as input.
763 For a true comparison CC=3 will never be set, but we treat this
764 conservatively for possible use when CC=3 indicates overflow. */
765 static const TCGCond ltgt_cond[16] = {
766 TCG_COND_NEVER, TCG_COND_NEVER, /* | | | x */
767 TCG_COND_GT, TCG_COND_NEVER, /* | | GT | x */
768 TCG_COND_LT, TCG_COND_NEVER, /* | LT | | x */
769 TCG_COND_NE, TCG_COND_NEVER, /* | LT | GT | x */
770 TCG_COND_EQ, TCG_COND_NEVER, /* EQ | | | x */
771 TCG_COND_GE, TCG_COND_NEVER, /* EQ | | GT | x */
772 TCG_COND_LE, TCG_COND_NEVER, /* EQ | LT | | x */
773 TCG_COND_ALWAYS, TCG_COND_ALWAYS, /* EQ | LT | GT | x */
774 };
775
776 /* Table of mask values to comparison codes, given a logic op as input.
777 For such, only CC=0 and CC=1 should be possible. */
778 static const TCGCond nz_cond[16] = {
779 /* | | x | x */
780 TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER,
781 /* | NE | x | x */
782 TCG_COND_NE, TCG_COND_NE, TCG_COND_NE, TCG_COND_NE,
783 /* EQ | | x | x */
784 TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ,
785 /* EQ | NE | x | x */
786 TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS,
787 };
788
789 /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
790 details required to generate a TCG comparison. */
791 static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
792 {
793 TCGCond cond;
794 enum cc_op old_cc_op = s->cc_op;
795
796 if (mask == 15 || mask == 0) {
797 c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER);
798 c->u.s32.a = cc_op;
799 c->u.s32.b = cc_op;
800 c->g1 = c->g2 = true;
801 c->is_64 = false;
802 return;
803 }
804
805 /* Find the TCG condition for the mask + cc op. */
806 switch (old_cc_op) {
807 case CC_OP_LTGT0_32:
808 case CC_OP_LTGT0_64:
809 case CC_OP_LTGT_32:
810 case CC_OP_LTGT_64:
811 cond = ltgt_cond[mask];
812 if (cond == TCG_COND_NEVER) {
813 goto do_dynamic;
814 }
815 account_inline_branch(s, old_cc_op);
816 break;
817
818 case CC_OP_LTUGTU_32:
819 case CC_OP_LTUGTU_64:
820 cond = tcg_unsigned_cond(ltgt_cond[mask]);
821 if (cond == TCG_COND_NEVER) {
822 goto do_dynamic;
823 }
824 account_inline_branch(s, old_cc_op);
825 break;
826
827 case CC_OP_NZ:
828 cond = nz_cond[mask];
829 if (cond == TCG_COND_NEVER) {
830 goto do_dynamic;
831 }
832 account_inline_branch(s, old_cc_op);
833 break;
834
835 case CC_OP_TM_32:
836 case CC_OP_TM_64:
837 switch (mask) {
838 case 8:
839 cond = TCG_COND_EQ;
840 break;
841 case 4 | 2 | 1:
842 cond = TCG_COND_NE;
843 break;
844 default:
845 goto do_dynamic;
846 }
847 account_inline_branch(s, old_cc_op);
848 break;
849
850 case CC_OP_ICM:
851 switch (mask) {
852 case 8:
853 cond = TCG_COND_EQ;
854 break;
855 case 4 | 2 | 1:
856 case 4 | 2:
857 cond = TCG_COND_NE;
858 break;
859 default:
860 goto do_dynamic;
861 }
862 account_inline_branch(s, old_cc_op);
863 break;
864
865 default:
866 do_dynamic:
867 /* Calculate cc value. */
868 gen_op_calc_cc(s);
869 /* FALLTHRU */
870
871 case CC_OP_STATIC:
872 /* Jump based on CC. We'll load up the real cond below;
873 the assignment here merely avoids a compiler warning. */
874 account_noninline_branch(s, old_cc_op);
875 old_cc_op = CC_OP_STATIC;
876 cond = TCG_COND_NEVER;
877 break;
878 }
879
880 /* Load up the arguments of the comparison. */
881 c->is_64 = true;
882 c->g1 = c->g2 = false;
883 switch (old_cc_op) {
884 case CC_OP_LTGT0_32:
885 c->is_64 = false;
886 c->u.s32.a = tcg_temp_new_i32();
887 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_dst);
888 c->u.s32.b = tcg_const_i32(0);
889 break;
890 case CC_OP_LTGT_32:
891 case CC_OP_LTUGTU_32:
892 c->is_64 = false;
893 c->u.s32.a = tcg_temp_new_i32();
894 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_src);
895 c->u.s32.b = tcg_temp_new_i32();
896 tcg_gen_trunc_i64_i32(c->u.s32.b, cc_dst);
897 break;
898
899 case CC_OP_LTGT0_64:
900 case CC_OP_NZ:
901 c->u.s64.a = cc_dst;
902 c->u.s64.b = tcg_const_i64(0);
903 c->g1 = true;
904 break;
905 case CC_OP_LTGT_64:
906 case CC_OP_LTUGTU_64:
907 c->u.s64.a = cc_src;
908 c->u.s64.b = cc_dst;
909 c->g1 = c->g2 = true;
910 break;
911
912 case CC_OP_TM_32:
913 case CC_OP_TM_64:
914 case CC_OP_ICM:
915 c->u.s64.a = tcg_temp_new_i64();
916 c->u.s64.b = tcg_const_i64(0);
917 tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst);
918 break;
919
920 case CC_OP_STATIC:
921 c->is_64 = false;
922 c->u.s32.a = cc_op;
923 c->g1 = true;
924 switch (mask) {
925 case 0x8 | 0x4 | 0x2: /* cc != 3 */
926 cond = TCG_COND_NE;
927 c->u.s32.b = tcg_const_i32(3);
928 break;
929 case 0x8 | 0x4 | 0x1: /* cc != 2 */
930 cond = TCG_COND_NE;
931 c->u.s32.b = tcg_const_i32(2);
932 break;
933 case 0x8 | 0x2 | 0x1: /* cc != 1 */
934 cond = TCG_COND_NE;
935 c->u.s32.b = tcg_const_i32(1);
936 break;
937 case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
938 cond = TCG_COND_EQ;
939 c->g1 = false;
940 c->u.s32.a = tcg_temp_new_i32();
941 c->u.s32.b = tcg_const_i32(0);
942 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
943 break;
944 case 0x8 | 0x4: /* cc < 2 */
945 cond = TCG_COND_LTU;
946 c->u.s32.b = tcg_const_i32(2);
947 break;
948 case 0x8: /* cc == 0 */
949 cond = TCG_COND_EQ;
950 c->u.s32.b = tcg_const_i32(0);
951 break;
952 case 0x4 | 0x2 | 0x1: /* cc != 0 */
953 cond = TCG_COND_NE;
954 c->u.s32.b = tcg_const_i32(0);
955 break;
956 case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
957 cond = TCG_COND_NE;
958 c->g1 = false;
959 c->u.s32.a = tcg_temp_new_i32();
960 c->u.s32.b = tcg_const_i32(0);
961 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
962 break;
963 case 0x4: /* cc == 1 */
964 cond = TCG_COND_EQ;
965 c->u.s32.b = tcg_const_i32(1);
966 break;
967 case 0x2 | 0x1: /* cc > 1 */
968 cond = TCG_COND_GTU;
969 c->u.s32.b = tcg_const_i32(1);
970 break;
971 case 0x2: /* cc == 2 */
972 cond = TCG_COND_EQ;
973 c->u.s32.b = tcg_const_i32(2);
974 break;
975 case 0x1: /* cc == 3 */
976 cond = TCG_COND_EQ;
977 c->u.s32.b = tcg_const_i32(3);
978 break;
979 default:
980 /* CC is masked by something else: (8 >> cc) & mask. */
981 cond = TCG_COND_NE;
982 c->g1 = false;
983 c->u.s32.a = tcg_const_i32(8);
984 c->u.s32.b = tcg_const_i32(0);
985 tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op);
986 tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask);
987 break;
988 }
989 break;
990
991 default:
992 abort();
993 }
994 c->cond = cond;
995 }
996
997 static void free_compare(DisasCompare *c)
998 {
999 if (!c->g1) {
1000 if (c->is_64) {
1001 tcg_temp_free_i64(c->u.s64.a);
1002 } else {
1003 tcg_temp_free_i32(c->u.s32.a);
1004 }
1005 }
1006 if (!c->g2) {
1007 if (c->is_64) {
1008 tcg_temp_free_i64(c->u.s64.b);
1009 } else {
1010 tcg_temp_free_i32(c->u.s32.b);
1011 }
1012 }
1013 }
1014
1015 static void disas_e3(CPUS390XState *env, DisasContext* s, int op, int r1,
1016 int x2, int b2, int d2)
1017 {
1018 TCGv_i64 addr, tmp2;
1019 TCGv_i32 tmp32_1;
1020
1021 LOG_DISAS("disas_e3: op 0x%x r1 %d x2 %d b2 %d d2 %d\n",
1022 op, r1, x2, b2, d2);
1023 addr = get_address(s, x2, b2, d2);
1024 switch (op) {
1025 case 0xf: /* LRVG R1,D2(X2,B2) [RXE] */
1026 tmp2 = tcg_temp_new_i64();
1027 tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1028 tcg_gen_bswap64_i64(tmp2, tmp2);
1029 store_reg(r1, tmp2);
1030 tcg_temp_free_i64(tmp2);
1031 break;
1032 case 0x17: /* LLGT R1,D2(X2,B2) [RXY] */
1033 tmp2 = tcg_temp_new_i64();
1034 tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1035 tcg_gen_andi_i64(tmp2, tmp2, 0x7fffffffULL);
1036 store_reg(r1, tmp2);
1037 tcg_temp_free_i64(tmp2);
1038 break;
1039 case 0x1e: /* LRV R1,D2(X2,B2) [RXY] */
1040 tmp2 = tcg_temp_new_i64();
1041 tmp32_1 = tcg_temp_new_i32();
1042 tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1043 tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
1044 tcg_temp_free_i64(tmp2);
1045 tcg_gen_bswap32_i32(tmp32_1, tmp32_1);
1046 store_reg32(r1, tmp32_1);
1047 tcg_temp_free_i32(tmp32_1);
1048 break;
1049 case 0x1f: /* LRVH R1,D2(X2,B2) [RXY] */
1050 tmp2 = tcg_temp_new_i64();
1051 tmp32_1 = tcg_temp_new_i32();
1052 tcg_gen_qemu_ld16u(tmp2, addr, get_mem_index(s));
1053 tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
1054 tcg_temp_free_i64(tmp2);
1055 tcg_gen_bswap16_i32(tmp32_1, tmp32_1);
1056 store_reg16(r1, tmp32_1);
1057 tcg_temp_free_i32(tmp32_1);
1058 break;
1059 case 0x3e: /* STRV R1,D2(X2,B2) [RXY] */
1060 tmp32_1 = load_reg32(r1);
1061 tmp2 = tcg_temp_new_i64();
1062 tcg_gen_bswap32_i32(tmp32_1, tmp32_1);
1063 tcg_gen_extu_i32_i64(tmp2, tmp32_1);
1064 tcg_temp_free_i32(tmp32_1);
1065 tcg_gen_qemu_st32(tmp2, addr, get_mem_index(s));
1066 tcg_temp_free_i64(tmp2);
1067 break;
1068 default:
1069 LOG_DISAS("illegal e3 operation 0x%x\n", op);
1070 gen_illegal_opcode(s);
1071 break;
1072 }
1073 tcg_temp_free_i64(addr);
1074 }
1075
1076 #ifndef CONFIG_USER_ONLY
1077 static void disas_e5(CPUS390XState *env, DisasContext* s, uint64_t insn)
1078 {
1079 TCGv_i64 tmp, tmp2;
1080 int op = (insn >> 32) & 0xff;
1081
1082 tmp = get_address(s, 0, (insn >> 28) & 0xf, (insn >> 16) & 0xfff);
1083 tmp2 = get_address(s, 0, (insn >> 12) & 0xf, insn & 0xfff);
1084
1085 LOG_DISAS("disas_e5: insn %" PRIx64 "\n", insn);
1086 switch (op) {
1087 case 0x01: /* TPROT D1(B1),D2(B2) [SSE] */
1088 /* Test Protection */
1089 potential_page_fault(s);
1090 gen_helper_tprot(cc_op, tmp, tmp2);
1091 set_cc_static(s);
1092 break;
1093 default:
1094 LOG_DISAS("illegal e5 operation 0x%x\n", op);
1095 gen_illegal_opcode(s);
1096 break;
1097 }
1098
1099 tcg_temp_free_i64(tmp);
1100 tcg_temp_free_i64(tmp2);
1101 }
1102 #endif
1103
1104 static void disas_eb(CPUS390XState *env, DisasContext *s, int op, int r1,
1105 int r3, int b2, int d2)
1106 {
1107 TCGv_i64 tmp;
1108 TCGv_i32 tmp32_1, tmp32_2;
1109
1110 LOG_DISAS("disas_eb: op 0x%x r1 %d r3 %d b2 %d d2 0x%x\n",
1111 op, r1, r3, b2, d2);
1112 switch (op) {
1113 case 0x2c: /* STCMH R1,M3,D2(B2) [RSY] */
1114 tmp = get_address(s, 0, b2, d2);
1115 tmp32_1 = tcg_const_i32(r1);
1116 tmp32_2 = tcg_const_i32(r3);
1117 potential_page_fault(s);
1118 gen_helper_stcmh(cpu_env, tmp32_1, tmp, tmp32_2);
1119 tcg_temp_free_i64(tmp);
1120 tcg_temp_free_i32(tmp32_1);
1121 tcg_temp_free_i32(tmp32_2);
1122 break;
1123 #ifndef CONFIG_USER_ONLY
1124 case 0x2f: /* LCTLG R1,R3,D2(B2) [RSE] */
1125 /* Load Control */
1126 check_privileged(s);
1127 tmp = get_address(s, 0, b2, d2);
1128 tmp32_1 = tcg_const_i32(r1);
1129 tmp32_2 = tcg_const_i32(r3);
1130 potential_page_fault(s);
1131 gen_helper_lctlg(cpu_env, tmp32_1, tmp, tmp32_2);
1132 tcg_temp_free_i64(tmp);
1133 tcg_temp_free_i32(tmp32_1);
1134 tcg_temp_free_i32(tmp32_2);
1135 break;
1136 case 0x25: /* STCTG R1,R3,D2(B2) [RSE] */
1137 /* Store Control */
1138 check_privileged(s);
1139 tmp = get_address(s, 0, b2, d2);
1140 tmp32_1 = tcg_const_i32(r1);
1141 tmp32_2 = tcg_const_i32(r3);
1142 potential_page_fault(s);
1143 gen_helper_stctg(cpu_env, tmp32_1, tmp, tmp32_2);
1144 tcg_temp_free_i64(tmp);
1145 tcg_temp_free_i32(tmp32_1);
1146 tcg_temp_free_i32(tmp32_2);
1147 break;
1148 #endif
1149 case 0x30: /* CSG R1,R3,D2(B2) [RSY] */
1150 tmp = get_address(s, 0, b2, d2);
1151 tmp32_1 = tcg_const_i32(r1);
1152 tmp32_2 = tcg_const_i32(r3);
1153 potential_page_fault(s);
1154 /* XXX rewrite in tcg */
1155 gen_helper_csg(cc_op, cpu_env, tmp32_1, tmp, tmp32_2);
1156 set_cc_static(s);
1157 tcg_temp_free_i64(tmp);
1158 tcg_temp_free_i32(tmp32_1);
1159 tcg_temp_free_i32(tmp32_2);
1160 break;
1161 case 0x3e: /* CDSG R1,R3,D2(B2) [RSY] */
1162 tmp = get_address(s, 0, b2, d2);
1163 tmp32_1 = tcg_const_i32(r1);
1164 tmp32_2 = tcg_const_i32(r3);
1165 potential_page_fault(s);
1166 /* XXX rewrite in tcg */
1167 gen_helper_cdsg(cc_op, cpu_env, tmp32_1, tmp, tmp32_2);
1168 set_cc_static(s);
1169 tcg_temp_free_i64(tmp);
1170 tcg_temp_free_i32(tmp32_1);
1171 tcg_temp_free_i32(tmp32_2);
1172 break;
1173 default:
1174 LOG_DISAS("illegal eb operation 0x%x\n", op);
1175 gen_illegal_opcode(s);
1176 break;
1177 }
1178 }
1179
1180 static void disas_ed(CPUS390XState *env, DisasContext *s, int op, int r1,
1181 int x2, int b2, int d2, int r1b)
1182 {
1183 TCGv_i32 tmp_r1, tmp32;
1184 TCGv_i64 addr, tmp;
1185 addr = get_address(s, x2, b2, d2);
1186 tmp_r1 = tcg_const_i32(r1);
1187 switch (op) {
1188 case 0x4: /* LDEB R1,D2(X2,B2) [RXE] */
1189 potential_page_fault(s);
1190 gen_helper_ldeb(cpu_env, tmp_r1, addr);
1191 break;
1192 case 0x5: /* LXDB R1,D2(X2,B2) [RXE] */
1193 potential_page_fault(s);
1194 gen_helper_lxdb(cpu_env, tmp_r1, addr);
1195 break;
1196 case 0x9: /* CEB R1,D2(X2,B2) [RXE] */
1197 tmp = tcg_temp_new_i64();
1198 tmp32 = load_freg32(r1);
1199 tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
1200 set_cc_cmp_f32_i64(s, tmp32, tmp);
1201 tcg_temp_free_i64(tmp);
1202 tcg_temp_free_i32(tmp32);
1203 break;
1204 case 0xa: /* AEB R1,D2(X2,B2) [RXE] */
1205 tmp = tcg_temp_new_i64();
1206 tmp32 = tcg_temp_new_i32();
1207 tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
1208 tcg_gen_trunc_i64_i32(tmp32, tmp);
1209 gen_helper_aeb(cpu_env, tmp_r1, tmp32);
1210 tcg_temp_free_i64(tmp);
1211 tcg_temp_free_i32(tmp32);
1212
1213 tmp32 = load_freg32(r1);
1214 gen_set_cc_nz_f32(s, tmp32);
1215 tcg_temp_free_i32(tmp32);
1216 break;
1217 case 0xb: /* SEB R1,D2(X2,B2) [RXE] */
1218 tmp = tcg_temp_new_i64();
1219 tmp32 = tcg_temp_new_i32();
1220 tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
1221 tcg_gen_trunc_i64_i32(tmp32, tmp);
1222 gen_helper_seb(cpu_env, tmp_r1, tmp32);
1223 tcg_temp_free_i64(tmp);
1224 tcg_temp_free_i32(tmp32);
1225
1226 tmp32 = load_freg32(r1);
1227 gen_set_cc_nz_f32(s, tmp32);
1228 tcg_temp_free_i32(tmp32);
1229 break;
1230 case 0xd: /* DEB R1,D2(X2,B2) [RXE] */
1231 tmp = tcg_temp_new_i64();
1232 tmp32 = tcg_temp_new_i32();
1233 tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
1234 tcg_gen_trunc_i64_i32(tmp32, tmp);
1235 gen_helper_deb(cpu_env, tmp_r1, tmp32);
1236 tcg_temp_free_i64(tmp);
1237 tcg_temp_free_i32(tmp32);
1238 break;
1239 case 0x10: /* TCEB R1,D2(X2,B2) [RXE] */
1240 potential_page_fault(s);
1241 gen_helper_tceb(cc_op, cpu_env, tmp_r1, addr);
1242 set_cc_static(s);
1243 break;
1244 case 0x11: /* TCDB R1,D2(X2,B2) [RXE] */
1245 potential_page_fault(s);
1246 gen_helper_tcdb(cc_op, cpu_env, tmp_r1, addr);
1247 set_cc_static(s);
1248 break;
1249 case 0x12: /* TCXB R1,D2(X2,B2) [RXE] */
1250 potential_page_fault(s);
1251 gen_helper_tcxb(cc_op, cpu_env, tmp_r1, addr);
1252 set_cc_static(s);
1253 break;
1254 case 0x17: /* MEEB R1,D2(X2,B2) [RXE] */
1255 tmp = tcg_temp_new_i64();
1256 tmp32 = tcg_temp_new_i32();
1257 tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
1258 tcg_gen_trunc_i64_i32(tmp32, tmp);
1259 gen_helper_meeb(cpu_env, tmp_r1, tmp32);
1260 tcg_temp_free_i64(tmp);
1261 tcg_temp_free_i32(tmp32);
1262 break;
1263 case 0x19: /* CDB R1,D2(X2,B2) [RXE] */
1264 potential_page_fault(s);
1265 gen_helper_cdb(cc_op, cpu_env, tmp_r1, addr);
1266 set_cc_static(s);
1267 break;
1268 case 0x1a: /* ADB R1,D2(X2,B2) [RXE] */
1269 potential_page_fault(s);
1270 gen_helper_adb(cc_op, cpu_env, tmp_r1, addr);
1271 set_cc_static(s);
1272 break;
1273 case 0x1b: /* SDB R1,D2(X2,B2) [RXE] */
1274 potential_page_fault(s);
1275 gen_helper_sdb(cc_op, cpu_env, tmp_r1, addr);
1276 set_cc_static(s);
1277 break;
1278 case 0x1c: /* MDB R1,D2(X2,B2) [RXE] */
1279 potential_page_fault(s);
1280 gen_helper_mdb(cpu_env, tmp_r1, addr);
1281 break;
1282 case 0x1d: /* DDB R1,D2(X2,B2) [RXE] */
1283 potential_page_fault(s);
1284 gen_helper_ddb(cpu_env, tmp_r1, addr);
1285 break;
1286 case 0x1e: /* MADB R1,R3,D2(X2,B2) [RXF] */
1287 /* for RXF insns, r1 is R3 and r1b is R1 */
1288 tmp32 = tcg_const_i32(r1b);
1289 potential_page_fault(s);
1290 gen_helper_madb(cpu_env, tmp32, addr, tmp_r1);
1291 tcg_temp_free_i32(tmp32);
1292 break;
1293 default:
1294 LOG_DISAS("illegal ed operation 0x%x\n", op);
1295 gen_illegal_opcode(s);
1296 return;
1297 }
1298 tcg_temp_free_i32(tmp_r1);
1299 tcg_temp_free_i64(addr);
1300 }
1301
1302 static void disas_b2(CPUS390XState *env, DisasContext *s, int op,
1303 uint32_t insn)
1304 {
1305 TCGv_i64 tmp, tmp2, tmp3;
1306 TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
1307 int r1, r2;
1308 #ifndef CONFIG_USER_ONLY
1309 int r3, d2, b2;
1310 #endif
1311
1312 r1 = (insn >> 4) & 0xf;
1313 r2 = insn & 0xf;
1314
1315 LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op, r1, r2);
1316
1317 switch (op) {
1318 case 0x22: /* IPM R1 [RRE] */
1319 tmp32_1 = tcg_const_i32(r1);
1320 gen_op_calc_cc(s);
1321 gen_helper_ipm(cpu_env, cc_op, tmp32_1);
1322 tcg_temp_free_i32(tmp32_1);
1323 break;
1324 case 0x41: /* CKSM R1,R2 [RRE] */
1325 tmp32_1 = tcg_const_i32(r1);
1326 tmp32_2 = tcg_const_i32(r2);
1327 potential_page_fault(s);
1328 gen_helper_cksm(cpu_env, tmp32_1, tmp32_2);
1329 tcg_temp_free_i32(tmp32_1);
1330 tcg_temp_free_i32(tmp32_2);
1331 gen_op_movi_cc(s, 0);
1332 break;
1333 case 0x4e: /* SAR R1,R2 [RRE] */
1334 tmp32_1 = load_reg32(r2);
1335 tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, aregs[r1]));
1336 tcg_temp_free_i32(tmp32_1);
1337 break;
1338 case 0x4f: /* EAR R1,R2 [RRE] */
1339 tmp32_1 = tcg_temp_new_i32();
1340 tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, aregs[r2]));
1341 store_reg32(r1, tmp32_1);
1342 tcg_temp_free_i32(tmp32_1);
1343 break;
1344 case 0x54: /* MVPG R1,R2 [RRE] */
1345 tmp = load_reg(0);
1346 tmp2 = load_reg(r1);
1347 tmp3 = load_reg(r2);
1348 potential_page_fault(s);
1349 gen_helper_mvpg(cpu_env, tmp, tmp2, tmp3);
1350 tcg_temp_free_i64(tmp);
1351 tcg_temp_free_i64(tmp2);
1352 tcg_temp_free_i64(tmp3);
1353 /* XXX check CCO bit and set CC accordingly */
1354 gen_op_movi_cc(s, 0);
1355 break;
1356 case 0x55: /* MVST R1,R2 [RRE] */
1357 tmp32_1 = load_reg32(0);
1358 tmp32_2 = tcg_const_i32(r1);
1359 tmp32_3 = tcg_const_i32(r2);
1360 potential_page_fault(s);
1361 gen_helper_mvst(cpu_env, tmp32_1, tmp32_2, tmp32_3);
1362 tcg_temp_free_i32(tmp32_1);
1363 tcg_temp_free_i32(tmp32_2);
1364 tcg_temp_free_i32(tmp32_3);
1365 gen_op_movi_cc(s, 1);
1366 break;
1367 case 0x5d: /* CLST R1,R2 [RRE] */
1368 tmp32_1 = load_reg32(0);
1369 tmp32_2 = tcg_const_i32(r1);
1370 tmp32_3 = tcg_const_i32(r2);
1371 potential_page_fault(s);
1372 gen_helper_clst(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1373 set_cc_static(s);
1374 tcg_temp_free_i32(tmp32_1);
1375 tcg_temp_free_i32(tmp32_2);
1376 tcg_temp_free_i32(tmp32_3);
1377 break;
1378 case 0x5e: /* SRST R1,R2 [RRE] */
1379 tmp32_1 = load_reg32(0);
1380 tmp32_2 = tcg_const_i32(r1);
1381 tmp32_3 = tcg_const_i32(r2);
1382 potential_page_fault(s);
1383 gen_helper_srst(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1384 set_cc_static(s);
1385 tcg_temp_free_i32(tmp32_1);
1386 tcg_temp_free_i32(tmp32_2);
1387 tcg_temp_free_i32(tmp32_3);
1388 break;
1389
1390 #ifndef CONFIG_USER_ONLY
1391 case 0x02: /* STIDP D2(B2) [S] */
1392 /* Store CPU ID */
1393 check_privileged(s);
1394 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1395 tmp = get_address(s, 0, b2, d2);
1396 potential_page_fault(s);
1397 gen_helper_stidp(cpu_env, tmp);
1398 tcg_temp_free_i64(tmp);
1399 break;
1400 case 0x04: /* SCK D2(B2) [S] */
1401 /* Set Clock */
1402 check_privileged(s);
1403 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1404 tmp = get_address(s, 0, b2, d2);
1405 potential_page_fault(s);
1406 gen_helper_sck(cc_op, tmp);
1407 set_cc_static(s);
1408 tcg_temp_free_i64(tmp);
1409 break;
1410 case 0x05: /* STCK D2(B2) [S] */
1411 /* Store Clock */
1412 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1413 tmp = get_address(s, 0, b2, d2);
1414 potential_page_fault(s);
1415 gen_helper_stck(cc_op, cpu_env, tmp);
1416 set_cc_static(s);
1417 tcg_temp_free_i64(tmp);
1418 break;
1419 case 0x06: /* SCKC D2(B2) [S] */
1420 /* Set Clock Comparator */
1421 check_privileged(s);
1422 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1423 tmp = get_address(s, 0, b2, d2);
1424 potential_page_fault(s);
1425 gen_helper_sckc(cpu_env, tmp);
1426 tcg_temp_free_i64(tmp);
1427 break;
1428 case 0x07: /* STCKC D2(B2) [S] */
1429 /* Store Clock Comparator */
1430 check_privileged(s);
1431 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1432 tmp = get_address(s, 0, b2, d2);
1433 potential_page_fault(s);
1434 gen_helper_stckc(cpu_env, tmp);
1435 tcg_temp_free_i64(tmp);
1436 break;
1437 case 0x08: /* SPT D2(B2) [S] */
1438 /* Set CPU Timer */
1439 check_privileged(s);
1440 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1441 tmp = get_address(s, 0, b2, d2);
1442 potential_page_fault(s);
1443 gen_helper_spt(cpu_env, tmp);
1444 tcg_temp_free_i64(tmp);
1445 break;
1446 case 0x09: /* STPT D2(B2) [S] */
1447 /* Store CPU Timer */
1448 check_privileged(s);
1449 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1450 tmp = get_address(s, 0, b2, d2);
1451 potential_page_fault(s);
1452 gen_helper_stpt(cpu_env, tmp);
1453 tcg_temp_free_i64(tmp);
1454 break;
1455 case 0x0a: /* SPKA D2(B2) [S] */
1456 /* Set PSW Key from Address */
1457 check_privileged(s);
1458 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1459 tmp = get_address(s, 0, b2, d2);
1460 tmp2 = tcg_temp_new_i64();
1461 tcg_gen_andi_i64(tmp2, psw_mask, ~PSW_MASK_KEY);
1462 tcg_gen_shli_i64(tmp, tmp, PSW_SHIFT_KEY - 4);
1463 tcg_gen_or_i64(psw_mask, tmp2, tmp);
1464 tcg_temp_free_i64(tmp2);
1465 tcg_temp_free_i64(tmp);
1466 break;
1467 case 0x0d: /* PTLB [S] */
1468 /* Purge TLB */
1469 check_privileged(s);
1470 gen_helper_ptlb(cpu_env);
1471 break;
1472 case 0x10: /* SPX D2(B2) [S] */
1473 /* Set Prefix Register */
1474 check_privileged(s);
1475 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1476 tmp = get_address(s, 0, b2, d2);
1477 potential_page_fault(s);
1478 gen_helper_spx(cpu_env, tmp);
1479 tcg_temp_free_i64(tmp);
1480 break;
1481 case 0x11: /* STPX D2(B2) [S] */
1482 /* Store Prefix */
1483 check_privileged(s);
1484 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1485 tmp = get_address(s, 0, b2, d2);
1486 tmp2 = tcg_temp_new_i64();
1487 tcg_gen_ld_i64(tmp2, cpu_env, offsetof(CPUS390XState, psa));
1488 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1489 tcg_temp_free_i64(tmp);
1490 tcg_temp_free_i64(tmp2);
1491 break;
1492 case 0x12: /* STAP D2(B2) [S] */
1493 /* Store CPU Address */
1494 check_privileged(s);
1495 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1496 tmp = get_address(s, 0, b2, d2);
1497 tmp2 = tcg_temp_new_i64();
1498 tmp32_1 = tcg_temp_new_i32();
1499 tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, cpu_num));
1500 tcg_gen_extu_i32_i64(tmp2, tmp32_1);
1501 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1502 tcg_temp_free_i64(tmp);
1503 tcg_temp_free_i64(tmp2);
1504 tcg_temp_free_i32(tmp32_1);
1505 break;
1506 case 0x21: /* IPTE R1,R2 [RRE] */
1507 /* Invalidate PTE */
1508 check_privileged(s);
1509 r1 = (insn >> 4) & 0xf;
1510 r2 = insn & 0xf;
1511 tmp = load_reg(r1);
1512 tmp2 = load_reg(r2);
1513 gen_helper_ipte(cpu_env, tmp, tmp2);
1514 tcg_temp_free_i64(tmp);
1515 tcg_temp_free_i64(tmp2);
1516 break;
1517 case 0x29: /* ISKE R1,R2 [RRE] */
1518 /* Insert Storage Key Extended */
1519 check_privileged(s);
1520 r1 = (insn >> 4) & 0xf;
1521 r2 = insn & 0xf;
1522 tmp = load_reg(r2);
1523 tmp2 = tcg_temp_new_i64();
1524 gen_helper_iske(tmp2, cpu_env, tmp);
1525 store_reg(r1, tmp2);
1526 tcg_temp_free_i64(tmp);
1527 tcg_temp_free_i64(tmp2);
1528 break;
1529 case 0x2a: /* RRBE R1,R2 [RRE] */
1530 /* Set Storage Key Extended */
1531 check_privileged(s);
1532 r1 = (insn >> 4) & 0xf;
1533 r2 = insn & 0xf;
1534 tmp32_1 = load_reg32(r1);
1535 tmp = load_reg(r2);
1536 gen_helper_rrbe(cc_op, cpu_env, tmp32_1, tmp);
1537 set_cc_static(s);
1538 tcg_temp_free_i32(tmp32_1);
1539 tcg_temp_free_i64(tmp);
1540 break;
1541 case 0x2b: /* SSKE R1,R2 [RRE] */
1542 /* Set Storage Key Extended */
1543 check_privileged(s);
1544 r1 = (insn >> 4) & 0xf;
1545 r2 = insn & 0xf;
1546 tmp32_1 = load_reg32(r1);
1547 tmp = load_reg(r2);
1548 gen_helper_sske(cpu_env, tmp32_1, tmp);
1549 tcg_temp_free_i32(tmp32_1);
1550 tcg_temp_free_i64(tmp);
1551 break;
1552 case 0x34: /* STCH ? */
1553 /* Store Subchannel */
1554 check_privileged(s);
1555 gen_op_movi_cc(s, 3);
1556 break;
1557 case 0x46: /* STURA R1,R2 [RRE] */
1558 /* Store Using Real Address */
1559 check_privileged(s);
1560 r1 = (insn >> 4) & 0xf;
1561 r2 = insn & 0xf;
1562 tmp32_1 = load_reg32(r1);
1563 tmp = load_reg(r2);
1564 potential_page_fault(s);
1565 gen_helper_stura(cpu_env, tmp, tmp32_1);
1566 tcg_temp_free_i32(tmp32_1);
1567 tcg_temp_free_i64(tmp);
1568 break;
1569 case 0x50: /* CSP R1,R2 [RRE] */
1570 /* Compare And Swap And Purge */
1571 check_privileged(s);
1572 r1 = (insn >> 4) & 0xf;
1573 r2 = insn & 0xf;
1574 tmp32_1 = tcg_const_i32(r1);
1575 tmp32_2 = tcg_const_i32(r2);
1576 gen_helper_csp(cc_op, cpu_env, tmp32_1, tmp32_2);
1577 set_cc_static(s);
1578 tcg_temp_free_i32(tmp32_1);
1579 tcg_temp_free_i32(tmp32_2);
1580 break;
1581 case 0x5f: /* CHSC ? */
1582 /* Channel Subsystem Call */
1583 check_privileged(s);
1584 gen_op_movi_cc(s, 3);
1585 break;
1586 case 0x78: /* STCKE D2(B2) [S] */
1587 /* Store Clock Extended */
1588 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1589 tmp = get_address(s, 0, b2, d2);
1590 potential_page_fault(s);
1591 gen_helper_stcke(cc_op, cpu_env, tmp);
1592 set_cc_static(s);
1593 tcg_temp_free_i64(tmp);
1594 break;
1595 case 0x79: /* SACF D2(B2) [S] */
1596 /* Set Address Space Control Fast */
1597 check_privileged(s);
1598 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1599 tmp = get_address(s, 0, b2, d2);
1600 potential_page_fault(s);
1601 gen_helper_sacf(cpu_env, tmp);
1602 tcg_temp_free_i64(tmp);
1603 /* addressing mode has changed, so end the block */
1604 s->pc = s->next_pc;
1605 update_psw_addr(s);
1606 s->is_jmp = DISAS_JUMP;
1607 break;
1608 case 0x7d: /* STSI D2,(B2) [S] */
1609 check_privileged(s);
1610 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1611 tmp = get_address(s, 0, b2, d2);
1612 tmp32_1 = load_reg32(0);
1613 tmp32_2 = load_reg32(1);
1614 potential_page_fault(s);
1615 gen_helper_stsi(cc_op, cpu_env, tmp, tmp32_1, tmp32_2);
1616 set_cc_static(s);
1617 tcg_temp_free_i64(tmp);
1618 tcg_temp_free_i32(tmp32_1);
1619 tcg_temp_free_i32(tmp32_2);
1620 break;
1621 case 0x9d: /* LFPC D2(B2) [S] */
1622 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1623 tmp = get_address(s, 0, b2, d2);
1624 tmp2 = tcg_temp_new_i64();
1625 tmp32_1 = tcg_temp_new_i32();
1626 tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
1627 tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
1628 tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc));
1629 tcg_temp_free_i64(tmp);
1630 tcg_temp_free_i64(tmp2);
1631 tcg_temp_free_i32(tmp32_1);
1632 break;
1633 case 0xb1: /* STFL D2(B2) [S] */
1634 /* Store Facility List (CPU features) at 200 */
1635 check_privileged(s);
1636 tmp2 = tcg_const_i64(0xc0000000);
1637 tmp = tcg_const_i64(200);
1638 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1639 tcg_temp_free_i64(tmp2);
1640 tcg_temp_free_i64(tmp);
1641 break;
1642 case 0xb2: /* LPSWE D2(B2) [S] */
1643 /* Load PSW Extended */
1644 check_privileged(s);
1645 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1646 tmp = get_address(s, 0, b2, d2);
1647 tmp2 = tcg_temp_new_i64();
1648 tmp3 = tcg_temp_new_i64();
1649 tcg_gen_qemu_ld64(tmp2, tmp, get_mem_index(s));
1650 tcg_gen_addi_i64(tmp, tmp, 8);
1651 tcg_gen_qemu_ld64(tmp3, tmp, get_mem_index(s));
1652 gen_helper_load_psw(cpu_env, tmp2, tmp3);
1653 /* we need to keep cc_op intact */
1654 s->is_jmp = DISAS_JUMP;
1655 tcg_temp_free_i64(tmp);
1656 tcg_temp_free_i64(tmp2);
1657 tcg_temp_free_i64(tmp3);
1658 break;
1659 case 0x20: /* SERVC R1,R2 [RRE] */
1660 /* SCLP Service call (PV hypercall) */
1661 check_privileged(s);
1662 potential_page_fault(s);
1663 tmp32_1 = load_reg32(r2);
1664 tmp = load_reg(r1);
1665 gen_helper_servc(cc_op, cpu_env, tmp32_1, tmp);
1666 set_cc_static(s);
1667 tcg_temp_free_i32(tmp32_1);
1668 tcg_temp_free_i64(tmp);
1669 break;
1670 #endif
1671 default:
1672 LOG_DISAS("illegal b2 operation 0x%x\n", op);
1673 gen_illegal_opcode(s);
1674 break;
1675 }
1676 }
1677
1678 static void disas_b3(CPUS390XState *env, DisasContext *s, int op, int m3,
1679 int r1, int r2)
1680 {
1681 TCGv_i64 tmp;
1682 TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
1683 LOG_DISAS("disas_b3: op 0x%x m3 0x%x r1 %d r2 %d\n", op, m3, r1, r2);
1684 #define FP_HELPER(i) \
1685 tmp32_1 = tcg_const_i32(r1); \
1686 tmp32_2 = tcg_const_i32(r2); \
1687 gen_helper_ ## i(cpu_env, tmp32_1, tmp32_2); \
1688 tcg_temp_free_i32(tmp32_1); \
1689 tcg_temp_free_i32(tmp32_2);
1690
1691 #define FP_HELPER_CC(i) \
1692 tmp32_1 = tcg_const_i32(r1); \
1693 tmp32_2 = tcg_const_i32(r2); \
1694 gen_helper_ ## i(cc_op, cpu_env, tmp32_1, tmp32_2); \
1695 set_cc_static(s); \
1696 tcg_temp_free_i32(tmp32_1); \
1697 tcg_temp_free_i32(tmp32_2);
1698
1699 switch (op) {
1700 case 0x0: /* LPEBR R1,R2 [RRE] */
1701 FP_HELPER_CC(lpebr);
1702 break;
1703 case 0x2: /* LTEBR R1,R2 [RRE] */
1704 FP_HELPER_CC(ltebr);
1705 break;
1706 case 0x3: /* LCEBR R1,R2 [RRE] */
1707 FP_HELPER_CC(lcebr);
1708 break;
1709 case 0x4: /* LDEBR R1,R2 [RRE] */
1710 FP_HELPER(ldebr);
1711 break;
1712 case 0x5: /* LXDBR R1,R2 [RRE] */
1713 FP_HELPER(lxdbr);
1714 break;
1715 case 0x9: /* CEBR R1,R2 [RRE] */
1716 FP_HELPER_CC(cebr);
1717 break;
1718 case 0xa: /* AEBR R1,R2 [RRE] */
1719 FP_HELPER_CC(aebr);
1720 break;
1721 case 0xb: /* SEBR R1,R2 [RRE] */
1722 FP_HELPER_CC(sebr);
1723 break;
1724 case 0xd: /* DEBR R1,R2 [RRE] */
1725 FP_HELPER(debr);
1726 break;
1727 case 0x10: /* LPDBR R1,R2 [RRE] */
1728 FP_HELPER_CC(lpdbr);
1729 break;
1730 case 0x12: /* LTDBR R1,R2 [RRE] */
1731 FP_HELPER_CC(ltdbr);
1732 break;
1733 case 0x13: /* LCDBR R1,R2 [RRE] */
1734 FP_HELPER_CC(lcdbr);
1735 break;
1736 case 0x15: /* SQBDR R1,R2 [RRE] */
1737 FP_HELPER(sqdbr);
1738 break;
1739 case 0x17: /* MEEBR R1,R2 [RRE] */
1740 FP_HELPER(meebr);
1741 break;
1742 case 0x19: /* CDBR R1,R2 [RRE] */
1743 FP_HELPER_CC(cdbr);
1744 break;
1745 case 0x1a: /* ADBR R1,R2 [RRE] */
1746 FP_HELPER_CC(adbr);
1747 break;
1748 case 0x1b: /* SDBR R1,R2 [RRE] */
1749 FP_HELPER_CC(sdbr);
1750 break;
1751 case 0x1c: /* MDBR R1,R2 [RRE] */
1752 FP_HELPER(mdbr);
1753 break;
1754 case 0x1d: /* DDBR R1,R2 [RRE] */
1755 FP_HELPER(ddbr);
1756 break;
1757 case 0xe: /* MAEBR R1,R3,R2 [RRF] */
1758 case 0x1e: /* MADBR R1,R3,R2 [RRF] */
1759 case 0x1f: /* MSDBR R1,R3,R2 [RRF] */
1760 /* for RRF insns, m3 is R1, r1 is R3, and r2 is R2 */
1761 tmp32_1 = tcg_const_i32(m3);
1762 tmp32_2 = tcg_const_i32(r2);
1763 tmp32_3 = tcg_const_i32(r1);
1764 switch (op) {
1765 case 0xe:
1766 gen_helper_maebr(cpu_env, tmp32_1, tmp32_3, tmp32_2);
1767 break;
1768 case 0x1e:
1769 gen_helper_madbr(cpu_env, tmp32_1, tmp32_3, tmp32_2);
1770 break;
1771 case 0x1f:
1772 gen_helper_msdbr(cpu_env, tmp32_1, tmp32_3, tmp32_2);
1773 break;
1774 default:
1775 tcg_abort();
1776 }
1777 tcg_temp_free_i32(tmp32_1);
1778 tcg_temp_free_i32(tmp32_2);
1779 tcg_temp_free_i32(tmp32_3);
1780 break;
1781 case 0x40: /* LPXBR R1,R2 [RRE] */
1782 FP_HELPER_CC(lpxbr);
1783 break;
1784 case 0x42: /* LTXBR R1,R2 [RRE] */
1785 FP_HELPER_CC(ltxbr);
1786 break;
1787 case 0x43: /* LCXBR R1,R2 [RRE] */
1788 FP_HELPER_CC(lcxbr);
1789 break;
1790 case 0x44: /* LEDBR R1,R2 [RRE] */
1791 FP_HELPER(ledbr);
1792 break;
1793 case 0x45: /* LDXBR R1,R2 [RRE] */
1794 FP_HELPER(ldxbr);
1795 break;
1796 case 0x46: /* LEXBR R1,R2 [RRE] */
1797 FP_HELPER(lexbr);
1798 break;
1799 case 0x49: /* CXBR R1,R2 [RRE] */
1800 FP_HELPER_CC(cxbr);
1801 break;
1802 case 0x4a: /* AXBR R1,R2 [RRE] */
1803 FP_HELPER_CC(axbr);
1804 break;
1805 case 0x4b: /* SXBR R1,R2 [RRE] */
1806 FP_HELPER_CC(sxbr);
1807 break;
1808 case 0x4c: /* MXBR R1,R2 [RRE] */
1809 FP_HELPER(mxbr);
1810 break;
1811 case 0x4d: /* DXBR R1,R2 [RRE] */
1812 FP_HELPER(dxbr);
1813 break;
1814 case 0x65: /* LXR R1,R2 [RRE] */
1815 tmp = load_freg(r2);
1816 store_freg(r1, tmp);
1817 tcg_temp_free_i64(tmp);
1818 tmp = load_freg(r2 + 2);
1819 store_freg(r1 + 2, tmp);
1820 tcg_temp_free_i64(tmp);
1821 break;
1822 case 0x74: /* LZER R1 [RRE] */
1823 tmp32_1 = tcg_const_i32(r1);
1824 gen_helper_lzer(cpu_env, tmp32_1);
1825 tcg_temp_free_i32(tmp32_1);
1826 break;
1827 case 0x75: /* LZDR R1 [RRE] */
1828 tmp32_1 = tcg_const_i32(r1);
1829 gen_helper_lzdr(cpu_env, tmp32_1);
1830 tcg_temp_free_i32(tmp32_1);
1831 break;
1832 case 0x76: /* LZXR R1 [RRE] */
1833 tmp32_1 = tcg_const_i32(r1);
1834 gen_helper_lzxr(cpu_env, tmp32_1);
1835 tcg_temp_free_i32(tmp32_1);
1836 break;
1837 case 0x84: /* SFPC R1 [RRE] */
1838 tmp32_1 = load_reg32(r1);
1839 tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc));
1840 tcg_temp_free_i32(tmp32_1);
1841 break;
1842 case 0x8c: /* EFPC R1 [RRE] */
1843 tmp32_1 = tcg_temp_new_i32();
1844 tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc));
1845 store_reg32(r1, tmp32_1);
1846 tcg_temp_free_i32(tmp32_1);
1847 break;
1848 case 0x94: /* CEFBR R1,R2 [RRE] */
1849 case 0x95: /* CDFBR R1,R2 [RRE] */
1850 case 0x96: /* CXFBR R1,R2 [RRE] */
1851 tmp32_1 = tcg_const_i32(r1);
1852 tmp32_2 = load_reg32(r2);
1853 switch (op) {
1854 case 0x94:
1855 gen_helper_cefbr(cpu_env, tmp32_1, tmp32_2);
1856 break;
1857 case 0x95:
1858 gen_helper_cdfbr(cpu_env, tmp32_1, tmp32_2);
1859 break;
1860 case 0x96:
1861 gen_helper_cxfbr(cpu_env, tmp32_1, tmp32_2);
1862 break;
1863 default:
1864 tcg_abort();
1865 }
1866 tcg_temp_free_i32(tmp32_1);
1867 tcg_temp_free_i32(tmp32_2);
1868 break;
1869 case 0x98: /* CFEBR R1,R2 [RRE] */
1870 case 0x99: /* CFDBR R1,R2 [RRE] */
1871 case 0x9a: /* CFXBR R1,R2 [RRE] */
1872 tmp32_1 = tcg_const_i32(r1);
1873 tmp32_2 = tcg_const_i32(r2);
1874 tmp32_3 = tcg_const_i32(m3);
1875 switch (op) {
1876 case 0x98:
1877 gen_helper_cfebr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1878 break;
1879 case 0x99:
1880 gen_helper_cfdbr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1881 break;
1882 case 0x9a:
1883 gen_helper_cfxbr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1884 break;
1885 default:
1886 tcg_abort();
1887 }
1888 set_cc_static(s);
1889 tcg_temp_free_i32(tmp32_1);
1890 tcg_temp_free_i32(tmp32_2);
1891 tcg_temp_free_i32(tmp32_3);
1892 break;
1893 case 0xa4: /* CEGBR R1,R2 [RRE] */
1894 case 0xa5: /* CDGBR R1,R2 [RRE] */
1895 tmp32_1 = tcg_const_i32(r1);
1896 tmp = load_reg(r2);
1897 switch (op) {
1898 case 0xa4:
1899 gen_helper_cegbr(cpu_env, tmp32_1, tmp);
1900 break;
1901 case 0xa5:
1902 gen_helper_cdgbr(cpu_env, tmp32_1, tmp);
1903 break;
1904 default:
1905 tcg_abort();
1906 }
1907 tcg_temp_free_i32(tmp32_1);
1908 tcg_temp_free_i64(tmp);
1909 break;
1910 case 0xa6: /* CXGBR R1,R2 [RRE] */
1911 tmp32_1 = tcg_const_i32(r1);
1912 tmp = load_reg(r2);
1913 gen_helper_cxgbr(cpu_env, tmp32_1, tmp);
1914 tcg_temp_free_i32(tmp32_1);
1915 tcg_temp_free_i64(tmp);
1916 break;
1917 case 0xa8: /* CGEBR R1,R2 [RRE] */
1918 tmp32_1 = tcg_const_i32(r1);
1919 tmp32_2 = tcg_const_i32(r2);
1920 tmp32_3 = tcg_const_i32(m3);
1921 gen_helper_cgebr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1922 set_cc_static(s);
1923 tcg_temp_free_i32(tmp32_1);
1924 tcg_temp_free_i32(tmp32_2);
1925 tcg_temp_free_i32(tmp32_3);
1926 break;
1927 case 0xa9: /* CGDBR R1,R2 [RRE] */
1928 tmp32_1 = tcg_const_i32(r1);
1929 tmp32_2 = tcg_const_i32(r2);
1930 tmp32_3 = tcg_const_i32(m3);
1931 gen_helper_cgdbr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1932 set_cc_static(s);
1933 tcg_temp_free_i32(tmp32_1);
1934 tcg_temp_free_i32(tmp32_2);
1935 tcg_temp_free_i32(tmp32_3);
1936 break;
1937 case 0xaa: /* CGXBR R1,R2 [RRE] */
1938 tmp32_1 = tcg_const_i32(r1);
1939 tmp32_2 = tcg_const_i32(r2);
1940 tmp32_3 = tcg_const_i32(m3);
1941 gen_helper_cgxbr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1942 set_cc_static(s);
1943 tcg_temp_free_i32(tmp32_1);
1944 tcg_temp_free_i32(tmp32_2);
1945 tcg_temp_free_i32(tmp32_3);
1946 break;
1947 default:
1948 LOG_DISAS("illegal b3 operation 0x%x\n", op);
1949 gen_illegal_opcode(s);
1950 break;
1951 }
1952
1953 #undef FP_HELPER_CC
1954 #undef FP_HELPER
1955 }
1956
1957 static void disas_b9(CPUS390XState *env, DisasContext *s, int op, int r1,
1958 int r2)
1959 {
1960 TCGv_i64 tmp;
1961 TCGv_i32 tmp32_1;
1962
1963 LOG_DISAS("disas_b9: op 0x%x r1 %d r2 %d\n", op, r1, r2);
1964 switch (op) {
1965 case 0x17: /* LLGTR R1,R2 [RRE] */
1966 tmp32_1 = load_reg32(r2);
1967 tmp = tcg_temp_new_i64();
1968 tcg_gen_andi_i32(tmp32_1, tmp32_1, 0x7fffffffUL);
1969 tcg_gen_extu_i32_i64(tmp, tmp32_1);
1970 store_reg(r1, tmp);
1971 tcg_temp_free_i32(tmp32_1);
1972 tcg_temp_free_i64(tmp);
1973 break;
1974 case 0x0f: /* LRVGR R1,R2 [RRE] */
1975 tcg_gen_bswap64_i64(regs[r1], regs[r2]);
1976 break;
1977 case 0x1f: /* LRVR R1,R2 [RRE] */
1978 tmp32_1 = load_reg32(r2);
1979 tcg_gen_bswap32_i32(tmp32_1, tmp32_1);
1980 store_reg32(r1, tmp32_1);
1981 tcg_temp_free_i32(tmp32_1);
1982 break;
1983 case 0x83: /* FLOGR R1,R2 [RRE] */
1984 tmp = load_reg(r2);
1985 tmp32_1 = tcg_const_i32(r1);
1986 gen_helper_flogr(cc_op, cpu_env, tmp32_1, tmp);
1987 set_cc_static(s);
1988 tcg_temp_free_i64(tmp);
1989 tcg_temp_free_i32(tmp32_1);
1990 break;
1991 default:
1992 LOG_DISAS("illegal b9 operation 0x%x\n", op);
1993 gen_illegal_opcode(s);
1994 break;
1995 }
1996 }
1997
1998 static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
1999 {
2000 TCGv_i64 tmp, tmp2;
2001 TCGv_i32 tmp32_1, tmp32_2;
2002 unsigned char opc;
2003 uint64_t insn;
2004 int op, r1, r2, r3, d2, x2, b2, r1b;
2005
2006 opc = cpu_ldub_code(env, s->pc);
2007 LOG_DISAS("opc 0x%x\n", opc);
2008
2009 switch (opc) {
2010 #ifndef CONFIG_USER_ONLY
2011 case 0xae: /* SIGP R1,R3,D2(B2) [RS] */
2012 check_privileged(s);
2013 insn = ld_code4(env, s->pc);
2014 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2015 tmp = get_address(s, 0, b2, d2);
2016 tmp2 = load_reg(r3);
2017 tmp32_1 = tcg_const_i32(r1);
2018 potential_page_fault(s);
2019 gen_helper_sigp(cc_op, cpu_env, tmp, tmp32_1, tmp2);
2020 set_cc_static(s);
2021 tcg_temp_free_i64(tmp);
2022 tcg_temp_free_i64(tmp2);
2023 tcg_temp_free_i32(tmp32_1);
2024 break;
2025 #endif
2026 case 0xb2:
2027 insn = ld_code4(env, s->pc);
2028 op = (insn >> 16) & 0xff;
2029 switch (op) {
2030 case 0x9c: /* STFPC D2(B2) [S] */
2031 d2 = insn & 0xfff;
2032 b2 = (insn >> 12) & 0xf;
2033 tmp32_1 = tcg_temp_new_i32();
2034 tmp = tcg_temp_new_i64();
2035 tmp2 = get_address(s, 0, b2, d2);
2036 tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc));
2037 tcg_gen_extu_i32_i64(tmp, tmp32_1);
2038 tcg_gen_qemu_st32(tmp, tmp2, get_mem_index(s));
2039 tcg_temp_free_i32(tmp32_1);
2040 tcg_temp_free_i64(tmp);
2041 tcg_temp_free_i64(tmp2);
2042 break;
2043 default:
2044 disas_b2(env, s, op, insn);
2045 break;
2046 }
2047 break;
2048 case 0xb3:
2049 insn = ld_code4(env, s->pc);
2050 op = (insn >> 16) & 0xff;
2051 r3 = (insn >> 12) & 0xf; /* aka m3 */
2052 r1 = (insn >> 4) & 0xf;
2053 r2 = insn & 0xf;
2054 disas_b3(env, s, op, r3, r1, r2);
2055 break;
2056 #ifndef CONFIG_USER_ONLY
2057 case 0xb6: /* STCTL R1,R3,D2(B2) [RS] */
2058 /* Store Control */
2059 check_privileged(s);
2060 insn = ld_code4(env, s->pc);
2061 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2062 tmp = get_address(s, 0, b2, d2);
2063 tmp32_1 = tcg_const_i32(r1);
2064 tmp32_2 = tcg_const_i32(r3);
2065 potential_page_fault(s);
2066 gen_helper_stctl(cpu_env, tmp32_1, tmp, tmp32_2);
2067 tcg_temp_free_i64(tmp);
2068 tcg_temp_free_i32(tmp32_1);
2069 tcg_temp_free_i32(tmp32_2);
2070 break;
2071 case 0xb7: /* LCTL R1,R3,D2(B2) [RS] */
2072 /* Load Control */
2073 check_privileged(s);
2074 insn = ld_code4(env, s->pc);
2075 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2076 tmp = get_address(s, 0, b2, d2);
2077 tmp32_1 = tcg_const_i32(r1);
2078 tmp32_2 = tcg_const_i32(r3);
2079 potential_page_fault(s);
2080 gen_helper_lctl(cpu_env, tmp32_1, tmp, tmp32_2);
2081 tcg_temp_free_i64(tmp);
2082 tcg_temp_free_i32(tmp32_1);
2083 tcg_temp_free_i32(tmp32_2);
2084 break;
2085 #endif
2086 case 0xb9:
2087 insn = ld_code4(env, s->pc);
2088 r1 = (insn >> 4) & 0xf;
2089 r2 = insn & 0xf;
2090 op = (insn >> 16) & 0xff;
2091 disas_b9(env, s, op, r1, r2);
2092 break;
2093 case 0xba: /* CS R1,R3,D2(B2) [RS] */
2094 insn = ld_code4(env, s->pc);
2095 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2096 tmp = get_address(s, 0, b2, d2);
2097 tmp32_1 = tcg_const_i32(r1);
2098 tmp32_2 = tcg_const_i32(r3);
2099 potential_page_fault(s);
2100 gen_helper_cs(cc_op, cpu_env, tmp32_1, tmp, tmp32_2);
2101 set_cc_static(s);
2102 tcg_temp_free_i64(tmp);
2103 tcg_temp_free_i32(tmp32_1);
2104 tcg_temp_free_i32(tmp32_2);
2105 break;
2106 case 0xbd: /* CLM R1,M3,D2(B2) [RS] */
2107 insn = ld_code4(env, s->pc);
2108 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2109 tmp = get_address(s, 0, b2, d2);
2110 tmp32_1 = load_reg32(r1);
2111 tmp32_2 = tcg_const_i32(r3);
2112 potential_page_fault(s);
2113 gen_helper_clm(cc_op, cpu_env, tmp32_1, tmp32_2, tmp);
2114 set_cc_static(s);
2115 tcg_temp_free_i64(tmp);
2116 tcg_temp_free_i32(tmp32_1);
2117 tcg_temp_free_i32(tmp32_2);
2118 break;
2119 case 0xbe: /* STCM R1,M3,D2(B2) [RS] */
2120 insn = ld_code4(env, s->pc);
2121 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2122 tmp = get_address(s, 0, b2, d2);
2123 tmp32_1 = load_reg32(r1);
2124 tmp32_2 = tcg_const_i32(r3);
2125 potential_page_fault(s);
2126 gen_helper_stcm(cpu_env, tmp32_1, tmp32_2, tmp);
2127 tcg_temp_free_i64(tmp);
2128 tcg_temp_free_i32(tmp32_1);
2129 tcg_temp_free_i32(tmp32_2);
2130 break;
2131 case 0xe3:
2132 insn = ld_code6(env, s->pc);
2133 debug_insn(insn);
2134 op = insn & 0xff;
2135 r1 = (insn >> 36) & 0xf;
2136 x2 = (insn >> 32) & 0xf;
2137 b2 = (insn >> 28) & 0xf;
2138 d2 = ((int)((((insn >> 16) & 0xfff)
2139 | ((insn << 4) & 0xff000)) << 12)) >> 12;
2140 disas_e3(env, s, op, r1, x2, b2, d2 );
2141 break;
2142 #ifndef CONFIG_USER_ONLY
2143 case 0xe5:
2144 /* Test Protection */
2145 check_privileged(s);
2146 insn = ld_code6(env, s->pc);
2147 debug_insn(insn);
2148 disas_e5(env, s, insn);
2149 break;
2150 #endif
2151 case 0xeb:
2152 insn = ld_code6(env, s->pc);
2153 debug_insn(insn);
2154 op = insn & 0xff;
2155 r1 = (insn >> 36) & 0xf;
2156 r3 = (insn >> 32) & 0xf;
2157 b2 = (insn >> 28) & 0xf;
2158 d2 = ((int)((((insn >> 16) & 0xfff)
2159 | ((insn << 4) & 0xff000)) << 12)) >> 12;
2160 disas_eb(env, s, op, r1, r3, b2, d2);
2161 break;
2162 case 0xed:
2163 insn = ld_code6(env, s->pc);
2164 debug_insn(insn);
2165 op = insn & 0xff;
2166 r1 = (insn >> 36) & 0xf;
2167 x2 = (insn >> 32) & 0xf;
2168 b2 = (insn >> 28) & 0xf;
2169 d2 = (short)((insn >> 16) & 0xfff);
2170 r1b = (insn >> 12) & 0xf;
2171 disas_ed(env, s, op, r1, x2, b2, d2, r1b);
2172 break;
2173 default:
2174 qemu_log_mask(LOG_UNIMP, "unimplemented opcode 0x%x\n", opc);
2175 gen_illegal_opcode(s);
2176 break;
2177 }
2178 }
2179
2180 /* ====================================================================== */
2181 /* Define the insn format enumeration. */
2182 #define F0(N) FMT_##N,
2183 #define F1(N, X1) F0(N)
2184 #define F2(N, X1, X2) F0(N)
2185 #define F3(N, X1, X2, X3) F0(N)
2186 #define F4(N, X1, X2, X3, X4) F0(N)
2187 #define F5(N, X1, X2, X3, X4, X5) F0(N)
2188
2189 typedef enum {
2190 #include "insn-format.def"
2191 } DisasFormat;
2192
2193 #undef F0
2194 #undef F1
2195 #undef F2
2196 #undef F3
2197 #undef F4
2198 #undef F5
2199
2200 /* Define a structure to hold the decoded fields. We'll store each inside
2201 an array indexed by an enum. In order to conserve memory, we'll arrange
2202 for fields that do not exist at the same time to overlap, thus the "C"
2203 for compact. For checking purposes there is an "O" for original index
2204 as well that will be applied to availability bitmaps. */
2205
2206 enum DisasFieldIndexO {
2207 FLD_O_r1,
2208 FLD_O_r2,
2209 FLD_O_r3,
2210 FLD_O_m1,
2211 FLD_O_m3,
2212 FLD_O_m4,
2213 FLD_O_b1,
2214 FLD_O_b2,
2215 FLD_O_b4,
2216 FLD_O_d1,
2217 FLD_O_d2,
2218 FLD_O_d4,
2219 FLD_O_x2,
2220 FLD_O_l1,
2221 FLD_O_l2,
2222 FLD_O_i1,
2223 FLD_O_i2,
2224 FLD_O_i3,
2225 FLD_O_i4,
2226 FLD_O_i5
2227 };
2228
2229 enum DisasFieldIndexC {
2230 FLD_C_r1 = 0,
2231 FLD_C_m1 = 0,
2232 FLD_C_b1 = 0,
2233 FLD_C_i1 = 0,
2234
2235 FLD_C_r2 = 1,
2236 FLD_C_b2 = 1,
2237 FLD_C_i2 = 1,
2238
2239 FLD_C_r3 = 2,
2240 FLD_C_m3 = 2,
2241 FLD_C_i3 = 2,
2242
2243 FLD_C_m4 = 3,
2244 FLD_C_b4 = 3,
2245 FLD_C_i4 = 3,
2246 FLD_C_l1 = 3,
2247
2248 FLD_C_i5 = 4,
2249 FLD_C_d1 = 4,
2250
2251 FLD_C_d2 = 5,
2252
2253 FLD_C_d4 = 6,
2254 FLD_C_x2 = 6,
2255 FLD_C_l2 = 6,
2256
2257 NUM_C_FIELD = 7
2258 };
2259
2260 struct DisasFields {
2261 unsigned op:8;
2262 unsigned op2:8;
2263 unsigned presentC:16;
2264 unsigned int presentO;
2265 int c[NUM_C_FIELD];
2266 };
2267
2268 /* This is the way fields are to be accessed out of DisasFields. */
2269 #define have_field(S, F) have_field1((S), FLD_O_##F)
2270 #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
2271
2272 static bool have_field1(const DisasFields *f, enum DisasFieldIndexO c)
2273 {
2274 return (f->presentO >> c) & 1;
2275 }
2276
2277 static int get_field1(const DisasFields *f, enum DisasFieldIndexO o,
2278 enum DisasFieldIndexC c)
2279 {
2280 assert(have_field1(f, o));
2281 return f->c[c];
2282 }
2283
2284 /* Describe the layout of each field in each format. */
2285 typedef struct DisasField {
2286 unsigned int beg:8;
2287 unsigned int size:8;
2288 unsigned int type:2;
2289 unsigned int indexC:6;
2290 enum DisasFieldIndexO indexO:8;
2291 } DisasField;
2292
2293 typedef struct DisasFormatInfo {
2294 DisasField op[NUM_C_FIELD];
2295 } DisasFormatInfo;
2296
2297 #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
2298 #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
2299 #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
2300 { BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
2301 #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
2302 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
2303 { 20, 12, 0, FLD_C_d##N, FLD_O_d##N }
2304 #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
2305 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
2306 #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
2307 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
2308 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
2309 #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N }
2310 #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N }
2311
2312 #define F0(N) { { } },
2313 #define F1(N, X1) { { X1 } },
2314 #define F2(N, X1, X2) { { X1, X2 } },
2315 #define F3(N, X1, X2, X3) { { X1, X2, X3 } },
2316 #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
2317 #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
2318
2319 static const DisasFormatInfo format_info[] = {
2320 #include "insn-format.def"
2321 };
2322
2323 #undef F0
2324 #undef F1
2325 #undef F2
2326 #undef F3
2327 #undef F4
2328 #undef F5
2329 #undef R
2330 #undef M
2331 #undef BD
2332 #undef BXD
2333 #undef BDL
2334 #undef BXDL
2335 #undef I
2336 #undef L
2337
2338 /* Generally, we'll extract operands into this structures, operate upon
2339 them, and store them back. See the "in1", "in2", "prep", "wout" sets
2340 of routines below for more details. */
2341 typedef struct {
2342 bool g_out, g_out2, g_in1, g_in2;
2343 TCGv_i64 out, out2, in1, in2;
2344 TCGv_i64 addr1;
2345 } DisasOps;
2346
2347 /* Return values from translate_one, indicating the state of the TB. */
2348 typedef enum {
2349 /* Continue the TB. */
2350 NO_EXIT,
2351 /* We have emitted one or more goto_tb. No fixup required. */
2352 EXIT_GOTO_TB,
2353 /* We are not using a goto_tb (for whatever reason), but have updated
2354 the PC (for whatever reason), so there's no need to do it again on
2355 exiting the TB. */
2356 EXIT_PC_UPDATED,
2357 /* We are exiting the TB, but have neither emitted a goto_tb, nor
2358 updated the PC for the next instruction to be executed. */
2359 EXIT_PC_STALE,
2360 /* We are ending the TB with a noreturn function call, e.g. longjmp.
2361 No following code will be executed. */
2362 EXIT_NORETURN,
2363 } ExitStatus;
2364
2365 typedef enum DisasFacility {
2366 FAC_Z, /* zarch (default) */
2367 FAC_CASS, /* compare and swap and store */
2368 FAC_CASS2, /* compare and swap and store 2*/
2369 FAC_DFP, /* decimal floating point */
2370 FAC_DFPR, /* decimal floating point rounding */
2371 FAC_DO, /* distinct operands */
2372 FAC_EE, /* execute extensions */
2373 FAC_EI, /* extended immediate */
2374 FAC_FPE, /* floating point extension */
2375 FAC_FPSSH, /* floating point support sign handling */
2376 FAC_FPRGR, /* FPR-GR transfer */
2377 FAC_GIE, /* general instructions extension */
2378 FAC_HFP_MA, /* HFP multiply-and-add/subtract */
2379 FAC_HW, /* high-word */
2380 FAC_IEEEE_SIM, /* IEEE exception sumilation */
2381 FAC_LOC, /* load/store on condition */
2382 FAC_LD, /* long displacement */
2383 FAC_PC, /* population count */
2384 FAC_SCF, /* store clock fast */
2385 FAC_SFLE, /* store facility list extended */
2386 } DisasFacility;
2387
2388 struct DisasInsn {
2389 unsigned opc:16;
2390 DisasFormat fmt:6;
2391 DisasFacility fac:6;
2392
2393 const char *name;
2394
2395 void (*help_in1)(DisasContext *, DisasFields *, DisasOps *);
2396 void (*help_in2)(DisasContext *, DisasFields *, DisasOps *);
2397 void (*help_prep)(DisasContext *, DisasFields *, DisasOps *);
2398 void (*help_wout)(DisasContext *, DisasFields *, DisasOps *);
2399 void (*help_cout)(DisasContext *, DisasOps *);
2400 ExitStatus (*help_op)(DisasContext *, DisasOps *);
2401
2402 uint64_t data;
2403 };
2404
2405 /* ====================================================================== */
2406 /* Miscelaneous helpers, used by several operations. */
2407
2408 static void help_l2_shift(DisasContext *s, DisasFields *f,
2409 DisasOps *o, int mask)
2410 {
2411 int b2 = get_field(f, b2);
2412 int d2 = get_field(f, d2);
2413
2414 if (b2 == 0) {
2415 o->in2 = tcg_const_i64(d2 & mask);
2416 } else {
2417 o->in2 = get_address(s, 0, b2, d2);
2418 tcg_gen_andi_i64(o->in2, o->in2, mask);
2419 }
2420 }
2421
2422 static ExitStatus help_goto_direct(DisasContext *s, uint64_t dest)
2423 {
2424 if (dest == s->next_pc) {
2425 return NO_EXIT;
2426 }
2427 if (use_goto_tb(s, dest)) {
2428 gen_update_cc_op(s);
2429 tcg_gen_goto_tb(0);
2430 tcg_gen_movi_i64(psw_addr, dest);
2431 tcg_gen_exit_tb((tcg_target_long)s->tb);
2432 return EXIT_GOTO_TB;
2433 } else {
2434 tcg_gen_movi_i64(psw_addr, dest);
2435 return EXIT_PC_UPDATED;
2436 }
2437 }
2438
2439 static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
2440 bool is_imm, int imm, TCGv_i64 cdest)
2441 {
2442 ExitStatus ret;
2443 uint64_t dest = s->pc + 2 * imm;
2444 int lab;
2445
2446 /* Take care of the special cases first. */
2447 if (c->cond == TCG_COND_NEVER) {
2448 ret = NO_EXIT;
2449 goto egress;
2450 }
2451 if (is_imm) {
2452 if (dest == s->next_pc) {
2453 /* Branch to next. */
2454 ret = NO_EXIT;
2455 goto egress;
2456 }
2457 if (c->cond == TCG_COND_ALWAYS) {
2458 ret = help_goto_direct(s, dest);
2459 goto egress;
2460 }
2461 } else {
2462 if (TCGV_IS_UNUSED_I64(cdest)) {
2463 /* E.g. bcr %r0 -> no branch. */
2464 ret = NO_EXIT;
2465 goto egress;
2466 }
2467 if (c->cond == TCG_COND_ALWAYS) {
2468 tcg_gen_mov_i64(psw_addr, cdest);
2469 ret = EXIT_PC_UPDATED;
2470 goto egress;
2471 }
2472 }
2473
2474 if (use_goto_tb(s, s->next_pc)) {
2475 if (is_imm && use_goto_tb(s, dest)) {
2476 /* Both exits can use goto_tb. */
2477 gen_update_cc_op(s);
2478
2479 lab = gen_new_label();
2480 if (c->is_64) {
2481 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
2482 } else {
2483 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
2484 }
2485
2486 /* Branch not taken. */
2487 tcg_gen_goto_tb(0);
2488 tcg_gen_movi_i64(psw_addr, s->next_pc);
2489 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
2490
2491 /* Branch taken. */
2492 gen_set_label(lab);
2493 tcg_gen_goto_tb(1);
2494 tcg_gen_movi_i64(psw_addr, dest);
2495 tcg_gen_exit_tb((tcg_target_long)s->tb + 1);
2496
2497 ret = EXIT_GOTO_TB;
2498 } else {
2499 /* Fallthru can use goto_tb, but taken branch cannot. */
2500 /* Store taken branch destination before the brcond. This
2501 avoids having to allocate a new local temp to hold it.
2502 We'll overwrite this in the not taken case anyway. */
2503 if (!is_imm) {
2504 tcg_gen_mov_i64(psw_addr, cdest);
2505 }
2506
2507 lab = gen_new_label();
2508 if (c->is_64) {
2509 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
2510 } else {
2511 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
2512 }
2513
2514 /* Branch not taken. */
2515 gen_update_cc_op(s);
2516 tcg_gen_goto_tb(0);
2517 tcg_gen_movi_i64(psw_addr, s->next_pc);
2518 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
2519
2520 gen_set_label(lab);
2521 if (is_imm) {
2522 tcg_gen_movi_i64(psw_addr, dest);
2523 }
2524 ret = EXIT_PC_UPDATED;
2525 }
2526 } else {
2527 /* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
2528 Most commonly we're single-stepping or some other condition that
2529 disables all use of goto_tb. Just update the PC and exit. */
2530
2531 TCGv_i64 next = tcg_const_i64(s->next_pc);
2532 if (is_imm) {
2533 cdest = tcg_const_i64(dest);
2534 }
2535
2536 if (c->is_64) {
2537 tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b,
2538 cdest, next);
2539 } else {
2540 TCGv_i32 t0 = tcg_temp_new_i32();
2541 TCGv_i64 t1 = tcg_temp_new_i64();
2542 TCGv_i64 z = tcg_const_i64(0);
2543 tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b);
2544 tcg_gen_extu_i32_i64(t1, t0);
2545 tcg_temp_free_i32(t0);
2546 tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next);
2547 tcg_temp_free_i64(t1);
2548 tcg_temp_free_i64(z);
2549 }
2550
2551 if (is_imm) {
2552 tcg_temp_free_i64(cdest);
2553 }
2554 tcg_temp_free_i64(next);
2555
2556 ret = EXIT_PC_UPDATED;
2557 }
2558
2559 egress:
2560 free_compare(c);
2561 return ret;
2562 }
2563
2564 /* ====================================================================== */
2565 /* The operations. These perform the bulk of the work for any insn,
2566 usually after the operands have been loaded and output initialized. */
2567
2568 static ExitStatus op_abs(DisasContext *s, DisasOps *o)
2569 {
2570 gen_helper_abs_i64(o->out, o->in2);
2571 return NO_EXIT;
2572 }
2573
2574 static ExitStatus op_add(DisasContext *s, DisasOps *o)
2575 {
2576 tcg_gen_add_i64(o->out, o->in1, o->in2);
2577 return NO_EXIT;
2578 }
2579
2580 static ExitStatus op_addc(DisasContext *s, DisasOps *o)
2581 {
2582 TCGv_i64 cc;
2583
2584 tcg_gen_add_i64(o->out, o->in1, o->in2);
2585
2586 /* XXX possible optimization point */
2587 gen_op_calc_cc(s);
2588 cc = tcg_temp_new_i64();
2589 tcg_gen_extu_i32_i64(cc, cc_op);
2590 tcg_gen_shri_i64(cc, cc, 1);
2591
2592 tcg_gen_add_i64(o->out, o->out, cc);
2593 tcg_temp_free_i64(cc);
2594 return NO_EXIT;
2595 }
2596
2597 static ExitStatus op_and(DisasContext *s, DisasOps *o)
2598 {
2599 tcg_gen_and_i64(o->out, o->in1, o->in2);
2600 return NO_EXIT;
2601 }
2602
2603 static ExitStatus op_andi(DisasContext *s, DisasOps *o)
2604 {
2605 int shift = s->insn->data & 0xff;
2606 int size = s->insn->data >> 8;
2607 uint64_t mask = ((1ull << size) - 1) << shift;
2608
2609 assert(!o->g_in2);
2610 tcg_gen_shli_i64(o->in2, o->in2, shift);
2611 tcg_gen_ori_i64(o->in2, o->in2, ~mask);
2612 tcg_gen_and_i64(o->out, o->in1, o->in2);
2613
2614 /* Produce the CC from only the bits manipulated. */
2615 tcg_gen_andi_i64(cc_dst, o->out, mask);
2616 set_cc_nz_u64(s, cc_dst);
2617 return NO_EXIT;
2618 }
2619
2620 static ExitStatus op_bas(DisasContext *s, DisasOps *o)
2621 {
2622 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
2623 if (!TCGV_IS_UNUSED_I64(o->in2)) {
2624 tcg_gen_mov_i64(psw_addr, o->in2);
2625 return EXIT_PC_UPDATED;
2626 } else {
2627 return NO_EXIT;
2628 }
2629 }
2630
2631 static ExitStatus op_basi(DisasContext *s, DisasOps *o)
2632 {
2633 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
2634 return help_goto_direct(s, s->pc + 2 * get_field(s->fields, i2));
2635 }
2636
2637 static ExitStatus op_bc(DisasContext *s, DisasOps *o)
2638 {
2639 int m1 = get_field(s->fields, m1);
2640 bool is_imm = have_field(s->fields, i2);
2641 int imm = is_imm ? get_field(s->fields, i2) : 0;
2642 DisasCompare c;
2643
2644 disas_jcc(s, &c, m1);
2645 return help_branch(s, &c, is_imm, imm, o->in2);
2646 }
2647
2648 static ExitStatus op_bct32(DisasContext *s, DisasOps *o)
2649 {
2650 int r1 = get_field(s->fields, r1);
2651 bool is_imm = have_field(s->fields, i2);
2652 int imm = is_imm ? get_field(s->fields, i2) : 0;
2653 DisasCompare c;
2654 TCGv_i64 t;
2655
2656 c.cond = TCG_COND_NE;
2657 c.is_64 = false;
2658 c.g1 = false;
2659 c.g2 = false;
2660
2661 t = tcg_temp_new_i64();
2662 tcg_gen_subi_i64(t, regs[r1], 1);
2663 store_reg32_i64(r1, t);
2664 c.u.s32.a = tcg_temp_new_i32();
2665 c.u.s32.b = tcg_const_i32(0);
2666 tcg_gen_trunc_i64_i32(c.u.s32.a, t);
2667 tcg_temp_free_i64(t);
2668
2669 return help_branch(s, &c, is_imm, imm, o->in2);
2670 }
2671
2672 static ExitStatus op_bct64(DisasContext *s, DisasOps *o)
2673 {
2674 int r1 = get_field(s->fields, r1);
2675 bool is_imm = have_field(s->fields, i2);
2676 int imm = is_imm ? get_field(s->fields, i2) : 0;
2677 DisasCompare c;
2678
2679 c.cond = TCG_COND_NE;
2680 c.is_64 = true;
2681 c.g1 = true;
2682 c.g2 = false;
2683
2684 tcg_gen_subi_i64(regs[r1], regs[r1], 1);
2685 c.u.s64.a = regs[r1];
2686 c.u.s64.b = tcg_const_i64(0);
2687
2688 return help_branch(s, &c, is_imm, imm, o->in2);
2689 }
2690
2691 static ExitStatus op_clc(DisasContext *s, DisasOps *o)
2692 {
2693 int l = get_field(s->fields, l1);
2694 TCGv_i32 vl;
2695
2696 switch (l + 1) {
2697 case 1:
2698 tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s));
2699 tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s));
2700 break;
2701 case 2:
2702 tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s));
2703 tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s));
2704 break;
2705 case 4:
2706 tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s));
2707 tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s));
2708 break;
2709 case 8:
2710 tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s));
2711 tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s));
2712 break;
2713 default:
2714 potential_page_fault(s);
2715 vl = tcg_const_i32(l);
2716 gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
2717 tcg_temp_free_i32(vl);
2718 set_cc_static(s);
2719 return NO_EXIT;
2720 }
2721 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
2722 return NO_EXIT;
2723 }
2724
2725 static ExitStatus op_clcle(DisasContext *s, DisasOps *o)
2726 {
2727 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2728 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2729 potential_page_fault(s);
2730 gen_helper_clcle(cc_op, cpu_env, r1, o->in2, r3);
2731 tcg_temp_free_i32(r1);
2732 tcg_temp_free_i32(r3);
2733 set_cc_static(s);
2734 return NO_EXIT;
2735 }
2736
2737 static ExitStatus op_cvd(DisasContext *s, DisasOps *o)
2738 {
2739 TCGv_i64 t1 = tcg_temp_new_i64();
2740 TCGv_i32 t2 = tcg_temp_new_i32();
2741 tcg_gen_trunc_i64_i32(t2, o->in1);
2742 gen_helper_cvd(t1, t2);
2743 tcg_temp_free_i32(t2);
2744 tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
2745 tcg_temp_free_i64(t1);
2746 return NO_EXIT;
2747 }
2748
2749 #ifndef CONFIG_USER_ONLY
2750 static ExitStatus op_diag(DisasContext *s, DisasOps *o)
2751 {
2752 TCGv_i32 tmp;
2753
2754 check_privileged(s);
2755 potential_page_fault(s);
2756
2757 /* We pretend the format is RX_a so that D2 is the field we want. */
2758 tmp = tcg_const_i32(get_field(s->fields, d2) & 0xfff);
2759 gen_helper_diag(regs[2], cpu_env, tmp, regs[2], regs[1]);
2760 tcg_temp_free_i32(tmp);
2761 return NO_EXIT;
2762 }
2763 #endif
2764
2765 static ExitStatus op_divs32(DisasContext *s, DisasOps *o)
2766 {
2767 gen_helper_divs32(o->out2, cpu_env, o->in1, o->in2);
2768 return_low128(o->out);
2769 return NO_EXIT;
2770 }
2771
2772 static ExitStatus op_divu32(DisasContext *s, DisasOps *o)
2773 {
2774 gen_helper_divu32(o->out2, cpu_env, o->in1, o->in2);
2775 return_low128(o->out);
2776 return NO_EXIT;
2777 }
2778
2779 static ExitStatus op_divs64(DisasContext *s, DisasOps *o)
2780 {
2781 gen_helper_divs64(o->out2, cpu_env, o->in1, o->in2);
2782 return_low128(o->out);
2783 return NO_EXIT;
2784 }
2785
2786 static ExitStatus op_divu64(DisasContext *s, DisasOps *o)
2787 {
2788 gen_helper_divu64(o->out2, cpu_env, o->out, o->out2, o->in2);
2789 return_low128(o->out);
2790 return NO_EXIT;
2791 }
2792
2793 static ExitStatus op_ex(DisasContext *s, DisasOps *o)
2794 {
2795 /* ??? Perhaps a better way to implement EXECUTE is to set a bit in
2796 tb->flags, (ab)use the tb->cs_base field as the address of
2797 the template in memory, and grab 8 bits of tb->flags/cflags for
2798 the contents of the register. We would then recognize all this
2799 in gen_intermediate_code_internal, generating code for exactly
2800 one instruction. This new TB then gets executed normally.
2801
2802 On the other hand, this seems to be mostly used for modifying
2803 MVC inside of memcpy, which needs a helper call anyway. So
2804 perhaps this doesn't bear thinking about any further. */
2805
2806 TCGv_i64 tmp;
2807
2808 update_psw_addr(s);
2809 gen_op_calc_cc(s);
2810
2811 tmp = tcg_const_i64(s->next_pc);
2812 gen_helper_ex(cc_op, cpu_env, cc_op, o->in1, o->in2, tmp);
2813 tcg_temp_free_i64(tmp);
2814
2815 set_cc_static(s);
2816 return NO_EXIT;
2817 }
2818
2819 static ExitStatus op_icm(DisasContext *s, DisasOps *o)
2820 {
2821 int m3 = get_field(s->fields, m3);
2822 int pos, len, base = s->insn->data;
2823 TCGv_i64 tmp = tcg_temp_new_i64();
2824 uint64_t ccm;
2825
2826 switch (m3) {
2827 case 0xf:
2828 /* Effectively a 32-bit load. */
2829 tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s));
2830 len = 32;
2831 goto one_insert;
2832
2833 case 0xc:
2834 case 0x6:
2835 case 0x3:
2836 /* Effectively a 16-bit load. */
2837 tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s));
2838 len = 16;
2839 goto one_insert;
2840
2841 case 0x8:
2842 case 0x4:
2843 case 0x2:
2844 case 0x1:
2845 /* Effectively an 8-bit load. */
2846 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2847 len = 8;
2848 goto one_insert;
2849
2850 one_insert:
2851 pos = base + ctz32(m3) * 8;
2852 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len);
2853 ccm = ((1ull << len) - 1) << pos;
2854 break;
2855
2856 default:
2857 /* This is going to be a sequence of loads and inserts. */
2858 pos = base + 32 - 8;
2859 ccm = 0;
2860 while (m3) {
2861 if (m3 & 0x8) {
2862 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2863 tcg_gen_addi_i64(o->in2, o->in2, 1);
2864 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
2865 ccm |= 0xff << pos;
2866 }
2867 m3 = (m3 << 1) & 0xf;
2868 pos -= 8;
2869 }
2870 break;
2871 }
2872
2873 tcg_gen_movi_i64(tmp, ccm);
2874 gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out);
2875 tcg_temp_free_i64(tmp);
2876 return NO_EXIT;
2877 }
2878
2879 static ExitStatus op_insi(DisasContext *s, DisasOps *o)
2880 {
2881 int shift = s->insn->data & 0xff;
2882 int size = s->insn->data >> 8;
2883 tcg_gen_deposit_i64(o->out, o->in1, o->in2, shift, size);
2884 return NO_EXIT;
2885 }
2886
2887 static ExitStatus op_ld8s(DisasContext *s, DisasOps *o)
2888 {
2889 tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
2890 return NO_EXIT;
2891 }
2892
2893 static ExitStatus op_ld8u(DisasContext *s, DisasOps *o)
2894 {
2895 tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
2896 return NO_EXIT;
2897 }
2898
2899 static ExitStatus op_ld16s(DisasContext *s, DisasOps *o)
2900 {
2901 tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
2902 return NO_EXIT;
2903 }
2904
2905 static ExitStatus op_ld16u(DisasContext *s, DisasOps *o)
2906 {
2907 tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
2908 return NO_EXIT;
2909 }
2910
2911 static ExitStatus op_ld32s(DisasContext *s, DisasOps *o)
2912 {
2913 tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s));
2914 return NO_EXIT;
2915 }
2916
2917 static ExitStatus op_ld32u(DisasContext *s, DisasOps *o)
2918 {
2919 tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
2920 return NO_EXIT;
2921 }
2922
2923 static ExitStatus op_ld64(DisasContext *s, DisasOps *o)
2924 {
2925 tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
2926 return NO_EXIT;
2927 }
2928
2929 #ifndef CONFIG_USER_ONLY
2930 static ExitStatus op_lra(DisasContext *s, DisasOps *o)
2931 {
2932 check_privileged(s);
2933 potential_page_fault(s);
2934 gen_helper_lra(o->out, cpu_env, o->in2);
2935 set_cc_static(s);
2936 return NO_EXIT;
2937 }
2938
2939 static ExitStatus op_lpsw(DisasContext *s, DisasOps *o)
2940 {
2941 TCGv_i64 t1, t2;
2942
2943 check_privileged(s);
2944
2945 t1 = tcg_temp_new_i64();
2946 t2 = tcg_temp_new_i64();
2947 tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
2948 tcg_gen_addi_i64(o->in2, o->in2, 4);
2949 tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s));
2950 /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
2951 tcg_gen_shli_i64(t1, t1, 32);
2952 gen_helper_load_psw(cpu_env, t1, t2);
2953 tcg_temp_free_i64(t1);
2954 tcg_temp_free_i64(t2);
2955 return EXIT_NORETURN;
2956 }
2957 #endif
2958
2959 static ExitStatus op_lam(DisasContext *s, DisasOps *o)
2960 {
2961 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2962 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2963 potential_page_fault(s);
2964 gen_helper_lam(cpu_env, r1, o->in2, r3);
2965 tcg_temp_free_i32(r1);
2966 tcg_temp_free_i32(r3);
2967 return NO_EXIT;
2968 }
2969
2970 static ExitStatus op_lm32(DisasContext *s, DisasOps *o)
2971 {
2972 int r1 = get_field(s->fields, r1);
2973 int r3 = get_field(s->fields, r3);
2974 TCGv_i64 t = tcg_temp_new_i64();
2975 TCGv_i64 t4 = tcg_const_i64(4);
2976
2977 while (1) {
2978 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2979 store_reg32_i64(r1, t);
2980 if (r1 == r3) {
2981 break;
2982 }
2983 tcg_gen_add_i64(o->in2, o->in2, t4);
2984 r1 = (r1 + 1) & 15;
2985 }
2986
2987 tcg_temp_free_i64(t);
2988 tcg_temp_free_i64(t4);
2989 return NO_EXIT;
2990 }
2991
2992 static ExitStatus op_lmh(DisasContext *s, DisasOps *o)
2993 {
2994 int r1 = get_field(s->fields, r1);
2995 int r3 = get_field(s->fields, r3);
2996 TCGv_i64 t = tcg_temp_new_i64();
2997 TCGv_i64 t4 = tcg_const_i64(4);
2998
2999 while (1) {
3000 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
3001 store_reg32h_i64(r1, t);
3002 if (r1 == r3) {
3003 break;
3004 }
3005 tcg_gen_add_i64(o->in2, o->in2, t4);
3006 r1 = (r1 + 1) & 15;
3007 }
3008
3009 tcg_temp_free_i64(t);
3010 tcg_temp_free_i64(t4);
3011 return NO_EXIT;
3012 }
3013
3014 static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
3015 {
3016 int r1 = get_field(s->fields, r1);
3017 int r3 = get_field(s->fields, r3);
3018 TCGv_i64 t8 = tcg_const_i64(8);
3019
3020 while (1) {
3021 tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
3022 if (r1 == r3) {
3023 break;
3024 }
3025 tcg_gen_add_i64(o->in2, o->in2, t8);
3026 r1 = (r1 + 1) & 15;
3027 }
3028
3029 tcg_temp_free_i64(t8);
3030 return NO_EXIT;
3031 }
3032
3033 static ExitStatus op_mov2(DisasContext *s, DisasOps *o)
3034 {
3035 o->out = o->in2;
3036 o->g_out = o->g_in2;
3037 TCGV_UNUSED_I64(o->in2);
3038 o->g_in2 = false;
3039 return NO_EXIT;
3040 }
3041
3042 static ExitStatus op_movx(DisasContext *s, DisasOps *o)
3043 {
3044 o->out = o->in1;
3045 o->out2 = o->in2;
3046 o->g_out = o->g_in1;
3047 o->g_out2 = o->g_in2;
3048 TCGV_UNUSED_I64(o->in1);
3049 TCGV_UNUSED_I64(o->in2);
3050 o->g_in1 = o->g_in2 = false;
3051 return NO_EXIT;
3052 }
3053
3054 static ExitStatus op_mvc(DisasContext *s, DisasOps *o)
3055 {
3056 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3057 potential_page_fault(s);
3058 gen_helper_mvc(cpu_env, l, o->addr1, o->in2);
3059 tcg_temp_free_i32(l);
3060 return NO_EXIT;
3061 }
3062
3063 static ExitStatus op_mvcl(DisasContext *s, DisasOps *o)
3064 {
3065 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3066 TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
3067 potential_page_fault(s);
3068 gen_helper_mvcl(cc_op, cpu_env, r1, r2);
3069 tcg_temp_free_i32(r1);
3070 tcg_temp_free_i32(r2);
3071 set_cc_static(s);
3072 return NO_EXIT;
3073 }
3074
3075 static ExitStatus op_mvcle(DisasContext *s, DisasOps *o)
3076 {
3077 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3078 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
3079 potential_page_fault(s);
3080 gen_helper_mvcle(cc_op, cpu_env, r1, o->in2, r3);
3081 tcg_temp_free_i32(r1);
3082 tcg_temp_free_i32(r3);
3083 set_cc_static(s);
3084 return NO_EXIT;
3085 }
3086
3087 #ifndef CONFIG_USER_ONLY
3088 static ExitStatus op_mvcp(DisasContext *s, DisasOps *o)
3089 {
3090 int r1 = get_field(s->fields, l1);
3091 check_privileged(s);
3092 potential_page_fault(s);
3093 gen_helper_mvcp(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
3094 set_cc_static(s);
3095 return NO_EXIT;
3096 }
3097
3098 static ExitStatus op_mvcs(DisasContext *s, DisasOps *o)
3099 {
3100 int r1 = get_field(s->fields, l1);
3101 check_privileged(s);
3102 potential_page_fault(s);
3103 gen_helper_mvcs(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
3104 set_cc_static(s);
3105 return NO_EXIT;
3106 }
3107 #endif
3108
3109 static ExitStatus op_mul(DisasContext *s, DisasOps *o)
3110 {
3111 tcg_gen_mul_i64(o->out, o->in1, o->in2);
3112 return NO_EXIT;
3113 }
3114
3115 static ExitStatus op_mul128(DisasContext *s, DisasOps *o)
3116 {
3117 gen_helper_mul128(o->out, cpu_env, o->in1, o->in2);
3118 return_low128(o->out2);
3119 return NO_EXIT;
3120 }
3121
3122 static ExitStatus op_nabs(DisasContext *s, DisasOps *o)
3123 {
3124 gen_helper_nabs_i64(o->out, o->in2);
3125 return NO_EXIT;
3126 }
3127
3128 static ExitStatus op_nc(DisasContext *s, DisasOps *o)
3129 {
3130 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3131 potential_page_fault(s);
3132 gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2);
3133 tcg_temp_free_i32(l);
3134 set_cc_static(s);
3135 return NO_EXIT;
3136 }
3137
3138 static ExitStatus op_neg(DisasContext *s, DisasOps *o)
3139 {
3140 tcg_gen_neg_i64(o->out, o->in2);
3141 return NO_EXIT;
3142 }
3143
3144 static ExitStatus op_oc(DisasContext *s, DisasOps *o)
3145 {
3146 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3147 potential_page_fault(s);
3148 gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2);
3149 tcg_temp_free_i32(l);
3150 set_cc_static(s);
3151 return NO_EXIT;
3152 }
3153
3154 static ExitStatus op_or(DisasContext *s, DisasOps *o)
3155 {
3156 tcg_gen_or_i64(o->out, o->in1, o->in2);
3157 return NO_EXIT;
3158 }
3159
3160 static ExitStatus op_ori(DisasContext *s, DisasOps *o)
3161 {
3162 int shift = s->insn->data & 0xff;
3163 int size = s->insn->data >> 8;
3164 uint64_t mask = ((1ull << size) - 1) << shift;
3165
3166 assert(!o->g_in2);
3167 tcg_gen_shli_i64(o->in2, o->in2, shift);
3168 tcg_gen_or_i64(o->out, o->in1, o->in2);
3169
3170 /* Produce the CC from only the bits manipulated. */
3171 tcg_gen_andi_i64(cc_dst, o->out, mask);
3172 set_cc_nz_u64(s, cc_dst);
3173 return NO_EXIT;
3174 }
3175
3176 static ExitStatus op_rll32(DisasContext *s, DisasOps *o)
3177 {
3178 TCGv_i32 t1 = tcg_temp_new_i32();
3179 TCGv_i32 t2 = tcg_temp_new_i32();
3180 TCGv_i32 to = tcg_temp_new_i32();
3181 tcg_gen_trunc_i64_i32(t1, o->in1);
3182 tcg_gen_trunc_i64_i32(t2, o->in2);
3183 tcg_gen_rotl_i32(to, t1, t2);
3184 tcg_gen_extu_i32_i64(o->out, to);
3185 tcg_temp_free_i32(t1);
3186 tcg_temp_free_i32(t2);
3187 tcg_temp_free_i32(to);
3188 return NO_EXIT;
3189 }
3190
3191 static ExitStatus op_rll64(DisasContext *s, DisasOps *o)
3192 {
3193 tcg_gen_rotl_i64(o->out, o->in1, o->in2);
3194 return NO_EXIT;
3195 }
3196
3197 static ExitStatus op_sla(DisasContext *s, DisasOps *o)
3198 {
3199 uint64_t sign = 1ull << s->insn->data;
3200 enum cc_op cco = s->insn->data == 31 ? CC_OP_SLA_32 : CC_OP_SLA_64;
3201 gen_op_update2_cc_i64(s, cco, o->in1, o->in2);
3202 tcg_gen_shl_i64(o->out, o->in1, o->in2);
3203 /* The arithmetic left shift is curious in that it does not affect
3204 the sign bit. Copy that over from the source unchanged. */
3205 tcg_gen_andi_i64(o->out, o->out, ~sign);
3206 tcg_gen_andi_i64(o->in1, o->in1, sign);
3207 tcg_gen_or_i64(o->out, o->out, o->in1);
3208 return NO_EXIT;
3209 }
3210
3211 static ExitStatus op_sll(DisasContext *s, DisasOps *o)
3212 {
3213 tcg_gen_shl_i64(o->out, o->in1, o->in2);
3214 return NO_EXIT;
3215 }
3216
3217 static ExitStatus op_sra(DisasContext *s, DisasOps *o)
3218 {
3219 tcg_gen_sar_i64(o->out, o->in1, o->in2);
3220 return NO_EXIT;
3221 }
3222
3223 static ExitStatus op_srl(DisasContext *s, DisasOps *o)
3224 {
3225 tcg_gen_shr_i64(o->out, o->in1, o->in2);
3226 return NO_EXIT;
3227 }
3228
3229 #ifndef CONFIG_USER_ONLY
3230 static ExitStatus op_ssm(DisasContext *s, DisasOps *o)
3231 {
3232 check_privileged(s);
3233 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8);
3234 return NO_EXIT;
3235 }
3236
3237 static ExitStatus op_stnosm(DisasContext *s, DisasOps *o)
3238 {
3239 uint64_t i2 = get_field(s->fields, i2);
3240 TCGv_i64 t;
3241
3242 check_privileged(s);
3243
3244 /* It is important to do what the instruction name says: STORE THEN.
3245 If we let the output hook perform the store then if we fault and
3246 restart, we'll have the wrong SYSTEM MASK in place. */
3247 t = tcg_temp_new_i64();
3248 tcg_gen_shri_i64(t, psw_mask, 56);
3249 tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
3250 tcg_temp_free_i64(t);
3251
3252 if (s->fields->op == 0xac) {
3253 tcg_gen_andi_i64(psw_mask, psw_mask,
3254 (i2 << 56) | 0x00ffffffffffffffull);
3255 } else {
3256 tcg_gen_ori_i64(psw_mask, psw_mask, i2 << 56);
3257 }
3258 return NO_EXIT;
3259 }
3260 #endif
3261
3262 static ExitStatus op_st8(DisasContext *s, DisasOps *o)
3263 {
3264 tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));
3265 return NO_EXIT;
3266 }
3267
3268 static ExitStatus op_st16(DisasContext *s, DisasOps *o)
3269 {
3270 tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s));
3271 return NO_EXIT;
3272 }
3273
3274 static ExitStatus op_st32(DisasContext *s, DisasOps *o)
3275 {
3276 tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s));
3277 return NO_EXIT;
3278 }
3279
3280 static ExitStatus op_st64(DisasContext *s, DisasOps *o)
3281 {
3282 tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s));
3283 return NO_EXIT;
3284 }
3285
3286 static ExitStatus op_stam(DisasContext *s, DisasOps *o)
3287 {
3288 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3289 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
3290 potential_page_fault(s);
3291 gen_helper_stam(cpu_env, r1, o->in2, r3);
3292 tcg_temp_free_i32(r1);
3293 tcg_temp_free_i32(r3);
3294 return NO_EXIT;
3295 }
3296
3297 static ExitStatus op_stm(DisasContext *s, DisasOps *o)
3298 {
3299 int r1 = get_field(s->fields, r1);
3300 int r3 = get_field(s->fields, r3);
3301 int size = s->insn->data;
3302 TCGv_i64 tsize = tcg_const_i64(size);
3303
3304 while (1) {
3305 if (size == 8) {
3306 tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s));
3307 } else {
3308 tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s));
3309 }
3310 if (r1 == r3) {
3311 break;
3312 }
3313 tcg_gen_add_i64(o->in2, o->in2, tsize);
3314 r1 = (r1 + 1) & 15;
3315 }
3316
3317 tcg_temp_free_i64(tsize);
3318 return NO_EXIT;
3319 }
3320
3321 static ExitStatus op_stmh(DisasContext *s, DisasOps *o)
3322 {
3323 int r1 = get_field(s->fields, r1);
3324 int r3 = get_field(s->fields, r3);
3325 TCGv_i64 t = tcg_temp_new_i64();
3326 TCGv_i64 t4 = tcg_const_i64(4);
3327 TCGv_i64 t32 = tcg_const_i64(32);
3328
3329 while (1) {
3330 tcg_gen_shl_i64(t, regs[r1], t32);
3331 tcg_gen_qemu_st32(t, o->in2, get_mem_index(s));
3332 if (r1 == r3) {
3333 break;
3334 }
3335 tcg_gen_add_i64(o->in2, o->in2, t4);
3336 r1 = (r1 + 1) & 15;
3337 }
3338
3339 tcg_temp_free_i64(t);
3340 tcg_temp_free_i64(t4);
3341 tcg_temp_free_i64(t32);
3342 return NO_EXIT;
3343 }
3344
3345 static ExitStatus op_sub(DisasContext *s, DisasOps *o)
3346 {
3347 tcg_gen_sub_i64(o->out, o->in1, o->in2);
3348 return NO_EXIT;
3349 }
3350
3351 static ExitStatus op_subb(DisasContext *s, DisasOps *o)
3352 {
3353 TCGv_i64 cc;
3354
3355 assert(!o->g_in2);
3356 tcg_gen_not_i64(o->in2, o->in2);
3357 tcg_gen_add_i64(o->out, o->in1, o->in2);
3358
3359 /* XXX possible optimization point */
3360 gen_op_calc_cc(s);
3361 cc = tcg_temp_new_i64();
3362 tcg_gen_extu_i32_i64(cc, cc_op);
3363 tcg_gen_shri_i64(cc, cc, 1);
3364 tcg_gen_add_i64(o->out, o->out, cc);
3365 tcg_temp_free_i64(cc);
3366 return NO_EXIT;
3367 }
3368
3369 static ExitStatus op_svc(DisasContext *s, DisasOps *o)
3370 {
3371 TCGv_i32 t;
3372
3373 update_psw_addr(s);
3374 gen_op_calc_cc(s);
3375
3376 t = tcg_const_i32(get_field(s->fields, i1) & 0xff);
3377 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code));
3378 tcg_temp_free_i32(t);
3379
3380 t = tcg_const_i32(s->next_pc - s->pc);
3381 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen));
3382 tcg_temp_free_i32(t);
3383
3384 gen_exception(EXCP_SVC);
3385 return EXIT_NORETURN;
3386 }
3387
3388 static ExitStatus op_tr(DisasContext *s, DisasOps *o)
3389 {
3390 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3391 potential_page_fault(s);
3392 gen_helper_tr(cpu_env, l, o->addr1, o->in2);
3393 tcg_temp_free_i32(l);
3394 set_cc_static(s);
3395 return NO_EXIT;
3396 }
3397
3398 static ExitStatus op_unpk(DisasContext *s, DisasOps *o)
3399 {
3400 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3401 potential_page_fault(s);
3402 gen_helper_unpk(cpu_env, l, o->addr1, o->in2);
3403 tcg_temp_free_i32(l);
3404 return NO_EXIT;
3405 }
3406
3407 static ExitStatus op_xc(DisasContext *s, DisasOps *o)
3408 {
3409 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3410 potential_page_fault(s);
3411 gen_helper_xc(cc_op, cpu_env, l, o->addr1, o->in2);
3412 tcg_temp_free_i32(l);
3413 set_cc_static(s);
3414 return NO_EXIT;
3415 }
3416
3417 static ExitStatus op_xor(DisasContext *s, DisasOps *o)
3418 {
3419 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3420 return NO_EXIT;
3421 }
3422
3423 static ExitStatus op_xori(DisasContext *s, DisasOps *o)
3424 {
3425 int shift = s->insn->data & 0xff;
3426 int size = s->insn->data >> 8;
3427 uint64_t mask = ((1ull << size) - 1) << shift;
3428
3429 assert(!o->g_in2);
3430 tcg_gen_shli_i64(o->in2, o->in2, shift);
3431 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3432
3433 /* Produce the CC from only the bits manipulated. */
3434 tcg_gen_andi_i64(cc_dst, o->out, mask);
3435 set_cc_nz_u64(s, cc_dst);
3436 return NO_EXIT;
3437 }
3438
3439 /* ====================================================================== */
3440 /* The "Cc OUTput" generators. Given the generated output (and in some cases
3441 the original inputs), update the various cc data structures in order to
3442 be able to compute the new condition code. */
3443
3444 static void cout_abs32(DisasContext *s, DisasOps *o)
3445 {
3446 gen_op_update1_cc_i64(s, CC_OP_ABS_32, o->out);
3447 }
3448
3449 static void cout_abs64(DisasContext *s, DisasOps *o)
3450 {
3451 gen_op_update1_cc_i64(s, CC_OP_ABS_64, o->out);
3452 }
3453
3454 static void cout_adds32(DisasContext *s, DisasOps *o)
3455 {
3456 gen_op_update3_cc_i64(s, CC_OP_ADD_32, o->in1, o->in2, o->out);
3457 }
3458
3459 static void cout_adds64(DisasContext *s, DisasOps *o)
3460 {
3461 gen_op_update3_cc_i64(s, CC_OP_ADD_64, o->in1, o->in2, o->out);
3462 }
3463
3464 static void cout_addu32(DisasContext *s, DisasOps *o)
3465 {
3466 gen_op_update3_cc_i64(s, CC_OP_ADDU_32, o->in1, o->in2, o->out);
3467 }
3468
3469 static void cout_addu64(DisasContext *s, DisasOps *o)
3470 {
3471 gen_op_update3_cc_i64(s, CC_OP_ADDU_64, o->in1, o->in2, o->out);
3472 }
3473
3474 static void cout_addc32(DisasContext *s, DisasOps *o)
3475 {
3476 gen_op_update3_cc_i64(s, CC_OP_ADDC_32, o->in1, o->in2, o->out);
3477 }
3478
3479 static void cout_addc64(DisasContext *s, DisasOps *o)
3480 {
3481 gen_op_update3_cc_i64(s, CC_OP_ADDC_64, o->in1, o->in2, o->out);
3482 }
3483
3484 static void cout_cmps32(DisasContext *s, DisasOps *o)
3485 {
3486 gen_op_update2_cc_i64(s, CC_OP_LTGT_32, o->in1, o->in2);
3487 }
3488
3489 static void cout_cmps64(DisasContext *s, DisasOps *o)
3490 {
3491 gen_op_update2_cc_i64(s, CC_OP_LTGT_64, o->in1, o->in2);
3492 }
3493
3494 static void cout_cmpu32(DisasContext *s, DisasOps *o)
3495 {
3496 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_32, o->in1, o->in2);
3497 }
3498
3499 static void cout_cmpu64(DisasContext *s, DisasOps *o)
3500 {
3501 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, o->in1, o->in2);
3502 }
3503
3504 static void cout_nabs32(DisasContext *s, DisasOps *o)
3505 {
3506 gen_op_update1_cc_i64(s, CC_OP_NABS_32, o->out);
3507 }
3508
3509 static void cout_nabs64(DisasContext *s, DisasOps *o)
3510 {
3511 gen_op_update1_cc_i64(s, CC_OP_NABS_64, o->out);
3512 }
3513
3514 static void cout_neg32(DisasContext *s, DisasOps *o)
3515 {
3516 gen_op_update1_cc_i64(s, CC_OP_COMP_32, o->out);
3517 }
3518
3519 static void cout_neg64(DisasContext *s, DisasOps *o)
3520 {
3521 gen_op_update1_cc_i64(s, CC_OP_COMP_64, o->out);
3522 }
3523
3524 static void cout_nz32(DisasContext *s, DisasOps *o)
3525 {
3526 tcg_gen_ext32u_i64(cc_dst, o->out);
3527 gen_op_update1_cc_i64(s, CC_OP_NZ, cc_dst);
3528 }
3529
3530 static void cout_nz64(DisasContext *s, DisasOps *o)
3531 {
3532 gen_op_update1_cc_i64(s, CC_OP_NZ, o->out);
3533 }
3534
3535 static void cout_s32(DisasContext *s, DisasOps *o)
3536 {
3537 gen_op_update1_cc_i64(s, CC_OP_LTGT0_32, o->out);
3538 }
3539
3540 static void cout_s64(DisasContext *s, DisasOps *o)
3541 {
3542 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, o->out);
3543 }
3544
3545 static void cout_subs32(DisasContext *s, DisasOps *o)
3546 {
3547 gen_op_update3_cc_i64(s, CC_OP_SUB_32, o->in1, o->in2, o->out);
3548 }
3549
3550 static void cout_subs64(DisasContext *s, DisasOps *o)
3551 {
3552 gen_op_update3_cc_i64(s, CC_OP_SUB_64, o->in1, o->in2, o->out);
3553 }
3554
3555 static void cout_subu32(DisasContext *s, DisasOps *o)
3556 {
3557 gen_op_update3_cc_i64(s, CC_OP_SUBU_32, o->in1, o->in2, o->out);
3558 }
3559
3560 static void cout_subu64(DisasContext *s, DisasOps *o)
3561 {
3562 gen_op_update3_cc_i64(s, CC_OP_SUBU_64, o->in1, o->in2, o->out);
3563 }
3564
3565 static void cout_subb32(DisasContext *s, DisasOps *o)
3566 {
3567 gen_op_update3_cc_i64(s, CC_OP_SUBB_32, o->in1, o->in2, o->out);
3568 }
3569
3570 static void cout_subb64(DisasContext *s, DisasOps *o)
3571 {
3572 gen_op_update3_cc_i64(s, CC_OP_SUBB_64, o->in1, o->in2, o->out);
3573 }
3574
3575 static void cout_tm32(DisasContext *s, DisasOps *o)
3576 {
3577 gen_op_update2_cc_i64(s, CC_OP_TM_32, o->in1, o->in2);
3578 }
3579
3580 static void cout_tm64(DisasContext *s, DisasOps *o)
3581 {
3582 gen_op_update2_cc_i64(s, CC_OP_TM_64, o->in1, o->in2);
3583 }
3584
3585 /* ====================================================================== */
3586 /* The "PREPeration" generators. These initialize the DisasOps.OUT fields
3587 with the TCG register to which we will write. Used in combination with
3588 the "wout" generators, in some cases we need a new temporary, and in
3589 some cases we can write to a TCG global. */
3590
3591 static void prep_new(DisasContext *s, DisasFields *f, DisasOps *o)
3592 {
3593 o->out = tcg_temp_new_i64();
3594 }
3595
3596 static void prep_new_P(DisasContext *s, DisasFields *f, DisasOps *o)
3597 {
3598 o->out = tcg_temp_new_i64();
3599 o->out2 = tcg_temp_new_i64();
3600 }
3601
3602 static void prep_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3603 {
3604 o->out = regs[get_field(f, r1)];
3605 o->g_out = true;
3606 }
3607
3608 static void prep_r1_P(DisasContext *s, DisasFields *f, DisasOps *o)
3609 {
3610 /* ??? Specification exception: r1 must be even. */
3611 int r1 = get_field(f, r1);
3612 o->out = regs[r1];
3613 o->out2 = regs[(r1 + 1) & 15];
3614 o->g_out = o->g_out2 = true;
3615 }
3616
3617 /* ====================================================================== */
3618 /* The "Write OUTput" generators. These generally perform some non-trivial
3619 copy of data to TCG globals, or to main memory. The trivial cases are
3620 generally handled by having a "prep" generator install the TCG global
3621 as the destination of the operation. */
3622
3623 static void wout_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3624 {
3625 store_reg(get_field(f, r1), o->out);
3626 }
3627
3628 static void wout_r1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3629 {
3630 int r1 = get_field(f, r1);
3631 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8);
3632 }
3633
3634 static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3635 {
3636 store_reg32_i64(get_field(f, r1), o->out);
3637 }
3638
3639 static void wout_r1_P32(DisasContext *s, DisasFields *f, DisasOps *o)
3640 {
3641 /* ??? Specification exception: r1 must be even. */
3642 int r1 = get_field(f, r1);
3643 store_reg32_i64(r1, o->out);
3644 store_reg32_i64((r1 + 1) & 15, o->out2);
3645 }
3646
3647 static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3648 {
3649 /* ??? Specification exception: r1 must be even. */
3650 int r1 = get_field(f, r1);
3651 store_reg32_i64((r1 + 1) & 15, o->out);
3652 tcg_gen_shri_i64(o->out, o->out, 32);
3653 store_reg32_i64(r1, o->out);
3654 }
3655
3656 static void wout_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3657 {
3658 store_freg32_i64(get_field(f, r1), o->out);
3659 }
3660
3661 static void wout_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3662 {
3663 store_freg(get_field(f, r1), o->out);
3664 }
3665
3666 static void wout_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3667 {
3668 int f1 = get_field(s->fields, r1);
3669 store_freg(f1, o->out);
3670 store_freg((f1 + 2) & 15, o->out2);
3671 }
3672
3673 static void wout_cond_r1r2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3674 {
3675 if (get_field(f, r1) != get_field(f, r2)) {
3676 store_reg32_i64(get_field(f, r1), o->out);
3677 }
3678 }
3679
3680 static void wout_cond_e1e2(DisasContext *s, DisasFields *f, DisasOps *o)
3681 {
3682 if (get_field(f, r1) != get_field(f, r2)) {
3683 store_freg32_i64(get_field(f, r1), o->out);
3684 }
3685 }
3686
3687 static void wout_m1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3688 {
3689 tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s));
3690 }
3691
3692 static void wout_m1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3693 {
3694 tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s));
3695 }
3696
3697 static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3698 {
3699 tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
3700 }
3701
3702 static void wout_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3703 {
3704 tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
3705 }
3706
3707 /* ====================================================================== */
3708 /* The "INput 1" generators. These load the first operand to an insn. */
3709
3710 static void in1_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3711 {
3712 o->in1 = load_reg(get_field(f, r1));
3713 }
3714
3715 static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3716 {
3717 o->in1 = regs[get_field(f, r1)];
3718 o->g_in1 = true;
3719 }
3720
3721 static void in1_r1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3722 {
3723 o->in1 = tcg_temp_new_i64();
3724 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r1)]);
3725 }
3726
3727 static void in1_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3728 {
3729 o->in1 = tcg_temp_new_i64();
3730 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r1)]);
3731 }
3732
3733 static void in1_r1p1(DisasContext *s, DisasFields *f, DisasOps *o)
3734 {
3735 /* ??? Specification exception: r1 must be even. */
3736 int r1 = get_field(f, r1);
3737 o->in1 = load_reg((r1 + 1) & 15);
3738 }
3739
3740 static void in1_r1p1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3741 {
3742 /* ??? Specification exception: r1 must be even. */
3743 int r1 = get_field(f, r1);
3744 o->in1 = tcg_temp_new_i64();
3745 tcg_gen_ext32s_i64(o->in1, regs[(r1 + 1) & 15]);
3746 }
3747
3748 static void in1_r1p1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3749 {
3750 /* ??? Specification exception: r1 must be even. */
3751 int r1 = get_field(f, r1);
3752 o->in1 = tcg_temp_new_i64();
3753 tcg_gen_ext32u_i64(o->in1, regs[(r1 + 1) & 15]);
3754 }
3755
3756 static void in1_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3757 {
3758 /* ??? Specification exception: r1 must be even. */
3759 int r1 = get_field(f, r1);
3760 o->in1 = tcg_temp_new_i64();
3761 tcg_gen_concat32_i64(o->in1, regs[r1 + 1], regs[r1]);
3762 }
3763
3764 static void in1_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3765 {
3766 o->in1 = load_reg(get_field(f, r2));
3767 }
3768
3769 static void in1_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3770 {
3771 o->in1 = load_reg(get_field(f, r3));
3772 }
3773
3774 static void in1_r3_o(DisasContext *s, DisasFields *f, DisasOps *o)
3775 {
3776 o->in1 = regs[get_field(f, r3)];
3777 o->g_in1 = true;
3778 }
3779
3780 static void in1_r3_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3781 {
3782 o->in1 = tcg_temp_new_i64();
3783 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r3)]);
3784 }
3785
3786 static void in1_r3_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3787 {
3788 o->in1 = tcg_temp_new_i64();
3789 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r3)]);
3790 }
3791
3792 static void in1_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3793 {
3794 o->in1 = load_freg32_i64(get_field(f, r1));
3795 }
3796
3797 static void in1_f1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3798 {
3799 o->in1 = fregs[get_field(f, r1)];
3800 o->g_in1 = true;
3801 }
3802
3803 static void in1_la1(DisasContext *s, DisasFields *f, DisasOps *o)
3804 {
3805 o->addr1 = get_address(s, 0, get_field(f, b1), get_field(f, d1));
3806 }
3807
3808 static void in1_m1_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3809 {
3810 in1_la1(s, f, o);
3811 o->in1 = tcg_temp_new_i64();
3812 tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s));
3813 }
3814
3815 static void in1_m1_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3816 {
3817 in1_la1(s, f, o);
3818 o->in1 = tcg_temp_new_i64();
3819 tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s));
3820 }
3821
3822 static void in1_m1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3823 {
3824 in1_la1(s, f, o);
3825 o->in1 = tcg_temp_new_i64();
3826 tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s));
3827 }
3828
3829 static void in1_m1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3830 {
3831 in1_la1(s, f, o);
3832 o->in1 = tcg_temp_new_i64();
3833 tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s));
3834 }
3835
3836 static void in1_m1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3837 {
3838 in1_la1(s, f, o);
3839 o->in1 = tcg_temp_new_i64();
3840 tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s));
3841 }
3842
3843 static void in1_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3844 {
3845 in1_la1(s, f, o);
3846 o->in1 = tcg_temp_new_i64();
3847 tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s));
3848 }
3849
3850 /* ====================================================================== */
3851 /* The "INput 2" generators. These load the second operand to an insn. */
3852
3853 static void in2_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3854 {
3855 o->in2 = load_reg(get_field(f, r2));
3856 }
3857
3858 static void in2_r2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3859 {
3860 o->in2 = regs[get_field(f, r2)];
3861 o->g_in2 = true;
3862 }
3863
3864 static void in2_r2_nz(DisasContext *s, DisasFields *f, DisasOps *o)
3865 {
3866 int r2 = get_field(f, r2);
3867 if (r2 != 0) {
3868 o->in2 = load_reg(r2);
3869 }
3870 }
3871
3872 static void in2_r2_8s(DisasContext *s, DisasFields *f, DisasOps *o)
3873 {
3874 o->in2 = tcg_temp_new_i64();
3875 tcg_gen_ext8s_i64(o->in2, regs[get_field(f, r2)]);
3876 }
3877
3878 static void in2_r2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3879 {
3880 o->in2 = tcg_temp_new_i64();
3881 tcg_gen_ext8u_i64(o->in2, regs[get_field(f, r2)]);
3882 }
3883
3884 static void in2_r2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3885 {
3886 o->in2 = tcg_temp_new_i64();
3887 tcg_gen_ext16s_i64(o->in2, regs[get_field(f, r2)]);
3888 }
3889
3890 static void in2_r2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3891 {
3892 o->in2 = tcg_temp_new_i64();
3893 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r2)]);
3894 }
3895
3896 static void in2_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3897 {
3898 o->in2 = load_reg(get_field(f, r3));
3899 }
3900
3901 static void in2_r2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3902 {
3903 o->in2 = tcg_temp_new_i64();
3904 tcg_gen_ext32s_i64(o->in2, regs[get_field(f, r2)]);
3905 }
3906
3907 static void in2_r2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3908 {
3909 o->in2 = tcg_temp_new_i64();
3910 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r2)]);
3911 }
3912
3913 static void in2_e2(DisasContext *s, DisasFields *f, DisasOps *o)
3914 {
3915 o->in2 = load_freg32_i64(get_field(f, r2));
3916 }
3917
3918 static void in2_f2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3919 {
3920 o->in2 = fregs[get_field(f, r2)];
3921 o->g_in2 = true;
3922 }
3923
3924 static void in2_x2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3925 {
3926 int f2 = get_field(f, r2);
3927 o->in1 = fregs[f2];
3928 o->in2 = fregs[(f2 + 2) & 15];
3929 o->g_in1 = o->g_in2 = true;
3930 }
3931
3932 static void in2_a2(DisasContext *s, DisasFields *f, DisasOps *o)
3933 {
3934 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3935 o->in2 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3936 }
3937
3938 static void in2_ri2(DisasContext *s, DisasFields *f, DisasOps *o)
3939 {
3940 o->in2 = tcg_const_i64(s->pc + (int64_t)get_field(f, i2) * 2);
3941 }
3942
3943 static void in2_sh32(DisasContext *s, DisasFields *f, DisasOps *o)
3944 {
3945 help_l2_shift(s, f, o, 31);
3946 }
3947
3948 static void in2_sh64(DisasContext *s, DisasFields *f, DisasOps *o)
3949 {
3950 help_l2_shift(s, f, o, 63);
3951 }
3952
3953 static void in2_m2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3954 {
3955 in2_a2(s, f, o);
3956 tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s));
3957 }
3958
3959 static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3960 {
3961 in2_a2(s, f, o);
3962 tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
3963 }
3964
3965 static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3966 {
3967 in2_a2(s, f, o);
3968 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3969 }
3970
3971 static void in2_m2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3972 {
3973 in2_a2(s, f, o);
3974 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3975 }
3976
3977 static void in2_m2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3978 {
3979 in2_a2(s, f, o);
3980 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3981 }
3982
3983 static void in2_mri2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3984 {
3985 in2_ri2(s, f, o);
3986 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3987 }
3988
3989 static void in2_mri2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3990 {
3991 in2_ri2(s, f, o);
3992 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3993 }
3994
3995 static void in2_mri2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3996 {
3997 in2_ri2(s, f, o);
3998 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3999 }
4000
4001 static void in2_mri2_64(DisasContext *s, DisasFields *f, DisasOps *o)
4002 {
4003 in2_ri2(s, f, o);
4004 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
4005 }
4006
4007 static void in2_i2(DisasContext *s, DisasFields *f, DisasOps *o)
4008 {
4009 o->in2 = tcg_const_i64(get_field(f, i2));
4010 }
4011
4012 static void in2_i2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
4013 {
4014 o->in2 = tcg_const_i64((uint8_t)get_field(f, i2));
4015 }
4016
4017 static void in2_i2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
4018 {
4019 o->in2 = tcg_const_i64((uint16_t)get_field(f, i2));
4020 }
4021
4022 static void in2_i2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4023 {
4024 o->in2 = tcg_const_i64((uint32_t)get_field(f, i2));
4025 }
4026
4027 static void in2_i2_16u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
4028 {
4029 uint64_t i2 = (uint16_t)get_field(f, i2);
4030 o->in2 = tcg_const_i64(i2 << s->insn->data);
4031 }
4032
4033 static void in2_i2_32u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
4034 {
4035 uint64_t i2 = (uint32_t)get_field(f, i2);
4036 o->in2 = tcg_const_i64(i2 << s->insn->data);
4037 }
4038
4039 /* ====================================================================== */
4040
4041 /* Find opc within the table of insns. This is formulated as a switch
4042 statement so that (1) we get compile-time notice of cut-paste errors
4043 for duplicated opcodes, and (2) the compiler generates the binary
4044 search tree, rather than us having to post-process the table. */
4045
4046 #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \
4047 D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0)
4048
4049 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) insn_ ## NM,
4050
4051 enum DisasInsnEnum {
4052 #include "insn-data.def"
4053 };
4054
4055 #undef D
4056 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) { \
4057 .opc = OPC, \
4058 .fmt = FMT_##FT, \
4059 .fac = FAC_##FC, \
4060 .name = #NM, \
4061 .help_in1 = in1_##I1, \
4062 .help_in2 = in2_##I2, \
4063 .help_prep = prep_##P, \
4064 .help_wout = wout_##W, \
4065 .help_cout = cout_##CC, \
4066 .help_op = op_##OP, \
4067 .data = D \
4068 },
4069
4070 /* Allow 0 to be used for NULL in the table below. */
4071 #define in1_0 NULL
4072 #define in2_0 NULL
4073 #define prep_0 NULL
4074 #define wout_0 NULL
4075 #define cout_0 NULL
4076 #define op_0 NULL
4077
4078 static const DisasInsn insn_info[] = {
4079 #include "insn-data.def"
4080 };
4081
4082 #undef D
4083 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \
4084 case OPC: return &insn_info[insn_ ## NM];
4085
4086 static const DisasInsn *lookup_opc(uint16_t opc)
4087 {
4088 switch (opc) {
4089 #include "insn-data.def"
4090 default:
4091 return NULL;
4092 }
4093 }
4094
4095 #undef D
4096 #undef C
4097
4098 /* Extract a field from the insn. The INSN should be left-aligned in
4099 the uint64_t so that we can more easily utilize the big-bit-endian
4100 definitions we extract from the Principals of Operation. */
4101
4102 static void extract_field(DisasFields *o, const DisasField *f, uint64_t insn)
4103 {
4104 uint32_t r, m;
4105
4106 if (f->size == 0) {
4107 return;
4108 }
4109
4110 /* Zero extract the field from the insn. */
4111 r = (insn << f->beg) >> (64 - f->size);
4112
4113 /* Sign-extend, or un-swap the field as necessary. */
4114 switch (f->type) {
4115 case 0: /* unsigned */
4116 break;
4117 case 1: /* signed */
4118 assert(f->size <= 32);
4119 m = 1u << (f->size - 1);
4120 r = (r ^ m) - m;
4121 break;
4122 case 2: /* dl+dh split, signed 20 bit. */
4123 r = ((int8_t)r << 12) | (r >> 8);
4124 break;
4125 default:
4126 abort();
4127 }
4128
4129 /* Validate that the "compressed" encoding we selected above is valid.
4130 I.e. we havn't make two different original fields overlap. */
4131 assert(((o->presentC >> f->indexC) & 1) == 0);
4132 o->presentC |= 1 << f->indexC;
4133 o->presentO |= 1 << f->indexO;
4134
4135 o->c[f->indexC] = r;
4136 }
4137
4138 /* Lookup the insn at the current PC, extracting the operands into O and
4139 returning the info struct for the insn. Returns NULL for invalid insn. */
4140
4141 static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
4142 DisasFields *f)
4143 {
4144 uint64_t insn, pc = s->pc;
4145 int op, op2, ilen;
4146 const DisasInsn *info;
4147
4148 insn = ld_code2(env, pc);
4149 op = (insn >> 8) & 0xff;
4150 ilen = get_ilen(op);
4151 s->next_pc = s->pc + ilen;
4152
4153 switch (ilen) {
4154 case 2:
4155 insn = insn << 48;
4156 break;
4157 case 4:
4158 insn = ld_code4(env, pc) << 32;
4159 break;
4160 case 6:
4161 insn = (insn << 48) | (ld_code4(env, pc + 2) << 16);
4162 break;
4163 default:
4164 abort();
4165 }
4166
4167 /* We can't actually determine the insn format until we've looked up
4168 the full insn opcode. Which we can't do without locating the
4169 secondary opcode. Assume by default that OP2 is at bit 40; for
4170 those smaller insns that don't actually have a secondary opcode
4171 this will correctly result in OP2 = 0. */
4172 switch (op) {
4173 case 0x01: /* E */
4174 case 0x80: /* S */
4175 case 0x82: /* S */
4176 case 0x93: /* S */
4177 case 0xb2: /* S, RRF, RRE */
4178 case 0xb3: /* RRE, RRD, RRF */
4179 case 0xb9: /* RRE, RRF */
4180 case 0xe5: /* SSE, SIL */
4181 op2 = (insn << 8) >> 56;
4182 break;
4183 case 0xa5: /* RI */
4184 case 0xa7: /* RI */
4185 case 0xc0: /* RIL */
4186 case 0xc2: /* RIL */
4187 case 0xc4: /* RIL */
4188 case 0xc6: /* RIL */
4189 case 0xc8: /* SSF */
4190 case 0xcc: /* RIL */
4191 op2 = (insn << 12) >> 60;
4192 break;
4193 case 0xd0 ... 0xdf: /* SS */
4194 case 0xe1: /* SS */
4195 case 0xe2: /* SS */
4196 case 0xe8: /* SS */
4197 case 0xe9: /* SS */
4198 case 0xea: /* SS */
4199 case 0xee ... 0xf3: /* SS */
4200 case 0xf8 ... 0xfd: /* SS */
4201 op2 = 0;
4202 break;
4203 default:
4204 op2 = (insn << 40) >> 56;
4205 break;
4206 }
4207
4208 memset(f, 0, sizeof(*f));
4209 f->op = op;
4210 f->op2 = op2;
4211
4212 /* Lookup the instruction. */
4213 info = lookup_opc(op << 8 | op2);
4214
4215 /* If we found it, extract the operands. */
4216 if (info != NULL) {
4217 DisasFormat fmt = info->fmt;
4218 int i;
4219
4220 for (i = 0; i < NUM_C_FIELD; ++i) {
4221 extract_field(f, &format_info[fmt].op[i], insn);
4222 }
4223 }
4224 return info;
4225 }
4226
4227 static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
4228 {
4229 const DisasInsn *insn;
4230 ExitStatus ret = NO_EXIT;
4231 DisasFields f;
4232 DisasOps o;
4233
4234 insn = extract_insn(env, s, &f);
4235
4236 /* If not found, try the old interpreter. This includes ILLOPC. */
4237 if (insn == NULL) {
4238 disas_s390_insn(env, s);
4239 switch (s->is_jmp) {
4240 case DISAS_NEXT:
4241 ret = NO_EXIT;
4242 break;
4243 case DISAS_TB_JUMP:
4244 ret = EXIT_GOTO_TB;
4245 break;
4246 case DISAS_JUMP:
4247 ret = EXIT_PC_UPDATED;
4248 break;
4249 case DISAS_EXCP:
4250 ret = EXIT_NORETURN;
4251 break;
4252 default:
4253 abort();
4254 }
4255
4256 s->pc = s->next_pc;
4257 return ret;
4258 }
4259
4260 /* Set up the strutures we use to communicate with the helpers. */
4261 s->insn = insn;
4262 s->fields = &f;
4263 o.g_out = o.g_out2 = o.g_in1 = o.g_in2 = false;
4264 TCGV_UNUSED_I64(o.out);
4265 TCGV_UNUSED_I64(o.out2);
4266 TCGV_UNUSED_I64(o.in1);
4267 TCGV_UNUSED_I64(o.in2);
4268 TCGV_UNUSED_I64(o.addr1);
4269
4270 /* Implement the instruction. */
4271 if (insn->help_in1) {
4272 insn->help_in1(s, &f, &o);
4273 }
4274 if (insn->help_in2) {
4275 insn->help_in2(s, &f, &o);
4276 }
4277 if (insn->help_prep) {
4278 insn->help_prep(s, &f, &o);
4279 }
4280 if (insn->help_op) {
4281 ret = insn->help_op(s, &o);
4282 }
4283 if (insn->help_wout) {
4284 insn->help_wout(s, &f, &o);
4285 }
4286 if (insn->help_cout) {
4287 insn->help_cout(s, &o);
4288 }
4289
4290 /* Free any temporaries created by the helpers. */
4291 if (!TCGV_IS_UNUSED_I64(o.out) && !o.g_out) {
4292 tcg_temp_free_i64(o.out);
4293 }
4294 if (!TCGV_IS_UNUSED_I64(o.out2) && !o.g_out2) {
4295 tcg_temp_free_i64(o.out2);
4296 }
4297 if (!TCGV_IS_UNUSED_I64(o.in1) && !o.g_in1) {
4298 tcg_temp_free_i64(o.in1);
4299 }
4300 if (!TCGV_IS_UNUSED_I64(o.in2) && !o.g_in2) {
4301 tcg_temp_free_i64(o.in2);
4302 }
4303 if (!TCGV_IS_UNUSED_I64(o.addr1)) {
4304 tcg_temp_free_i64(o.addr1);
4305 }
4306
4307 /* Advance to the next instruction. */
4308 s->pc = s->next_pc;
4309 return ret;
4310 }
4311
4312 static inline void gen_intermediate_code_internal(CPUS390XState *env,
4313 TranslationBlock *tb,
4314 int search_pc)
4315 {
4316 DisasContext dc;
4317 target_ulong pc_start;
4318 uint64_t next_page_start;
4319 uint16_t *gen_opc_end;
4320 int j, lj = -1;
4321 int num_insns, max_insns;
4322 CPUBreakpoint *bp;
4323 ExitStatus status;
4324 bool do_debug;
4325
4326 pc_start = tb->pc;
4327
4328 /* 31-bit mode */
4329 if (!(tb->flags & FLAG_MASK_64)) {
4330 pc_start &= 0x7fffffff;
4331 }
4332
4333 dc.tb = tb;
4334 dc.pc = pc_start;
4335 dc.cc_op = CC_OP_DYNAMIC;
4336 do_debug = dc.singlestep_enabled = env->singlestep_enabled;
4337 dc.is_jmp = DISAS_NEXT;
4338
4339 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
4340
4341 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4342
4343 num_insns = 0;
4344 max_insns = tb->cflags & CF_COUNT_MASK;
4345 if (max_insns == 0) {
4346 max_insns = CF_COUNT_MASK;
4347 }
4348
4349 gen_icount_start();
4350
4351 do {
4352 if (search_pc) {
4353 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4354 if (lj < j) {
4355 lj++;
4356 while (lj < j) {
4357 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4358 }
4359 }
4360 tcg_ctx.gen_opc_pc[lj] = dc.pc;
4361 gen_opc_cc_op[lj] = dc.cc_op;
4362 tcg_ctx.gen_opc_instr_start[lj] = 1;
4363 tcg_ctx.gen_opc_icount[lj] = num_insns;
4364 }
4365 if (++num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
4366 gen_io_start();
4367 }
4368
4369 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
4370 tcg_gen_debug_insn_start(dc.pc);
4371 }
4372
4373 status = NO_EXIT;
4374 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
4375 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
4376 if (bp->pc == dc.pc) {
4377 status = EXIT_PC_STALE;
4378 do_debug = true;
4379 break;
4380 }
4381 }
4382 }
4383 if (status == NO_EXIT) {
4384 status = translate_one(env, &dc);
4385 }
4386
4387 /* If we reach a page boundary, are single stepping,
4388 or exhaust instruction count, stop generation. */
4389 if (status == NO_EXIT
4390 && (dc.pc >= next_page_start
4391 || tcg_ctx.gen_opc_ptr >= gen_opc_end
4392 || num_insns >= max_insns
4393 || singlestep
4394 || env->singlestep_enabled)) {
4395 status = EXIT_PC_STALE;
4396 }
4397 } while (status == NO_EXIT);
4398
4399 if (tb->cflags & CF_LAST_IO) {
4400 gen_io_end();
4401 }
4402
4403 switch (status) {
4404 case EXIT_GOTO_TB:
4405 case EXIT_NORETURN:
4406 break;
4407 case EXIT_PC_STALE:
4408 update_psw_addr(&dc);
4409 /* FALLTHRU */
4410 case EXIT_PC_UPDATED:
4411 if (singlestep && dc.cc_op != CC_OP_DYNAMIC) {
4412 gen_op_calc_cc(&dc);
4413 } else {
4414 /* Next TB starts off with CC_OP_DYNAMIC,
4415 so make sure the cc op type is in env */
4416 gen_op_set_cc_op(&dc);
4417 }
4418 if (do_debug) {
4419 gen_exception(EXCP_DEBUG);
4420 } else {
4421 /* Generate the return instruction */
4422 tcg_gen_exit_tb(0);
4423 }
4424 break;
4425 default:
4426 abort();
4427 }
4428
4429 gen_icount_end(tb, num_insns);
4430 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
4431 if (search_pc) {
4432 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4433 lj++;
4434 while (lj <= j) {
4435 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4436 }
4437 } else {
4438 tb->size = dc.pc - pc_start;
4439 tb->icount = num_insns;
4440 }
4441
4442 #if defined(S390X_DEBUG_DISAS)
4443 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
4444 qemu_log("IN: %s\n", lookup_symbol(pc_start));
4445 log_target_disas(env, pc_start, dc.pc - pc_start, 1);
4446 qemu_log("\n");
4447 }
4448 #endif
4449 }
4450
4451 void gen_intermediate_code (CPUS390XState *env, struct TranslationBlock *tb)
4452 {
4453 gen_intermediate_code_internal(env, tb, 0);
4454 }
4455
4456 void gen_intermediate_code_pc (CPUS390XState *env, struct TranslationBlock *tb)
4457 {
4458 gen_intermediate_code_internal(env, tb, 1);
4459 }
4460
4461 void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, int pc_pos)
4462 {
4463 int cc_op;
4464 env->psw.addr = tcg_ctx.gen_opc_pc[pc_pos];
4465 cc_op = gen_opc_cc_op[pc_pos];
4466 if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {
4467 env->cc_op = cc_op;
4468 }
4469 }
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