target-sh4/cpu.h

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef _CPU_SH4_H
  21 #define _CPU_SH4_H
  22
  23 #include "config.h"
  24
  25 #define TARGET_LONG_BITS 32
  26 #define TARGET_HAS_ICE 1
  27
  28 #define ELF_MACHINE     EM_SH
  29
  30 #include "cpu-defs.h"
  31
  32 #include "softfloat.h"
  33
  34 #define TARGET_PAGE_BITS 12     /* 4k XXXXX */
  35
  36 #define SR_MD (1 << 30)
  37 #define SR_RB (1 << 29)
  38 #define SR_BL (1 << 28)
  39 #define SR_FD (1 << 15)
  40 #define SR_M  (1 << 9)
  41 #define SR_Q  (1 << 8)
  42 #define SR_S  (1 << 1)
  43 #define SR_T  (1 << 0)
  44
  45 #define FPSCR_FR (1 << 21)
  46 #define FPSCR_SZ (1 << 20)
  47 #define FPSCR_PR (1 << 19)
  48 #define FPSCR_DN (1 << 18)
  49 #define DELAY_SLOT             (1 << 0)
  50 #define DELAY_SLOT_CONDITIONAL (1 << 1)
  51 #define DELAY_SLOT_TRUE        (1 << 2)
  52 #define DELAY_SLOT_CLEARME     (1 << 3)
  53 /* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump
  54  * after the delay slot should be taken or not. It is calculated from SR_T.
  55  *
  56  * It is unclear if it is permitted to modify the SR_T flag in a delay slot.
  57  * The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification.
  58  */
  59
  60 /* XXXXX The structure could be made more compact */
  61 typedef struct tlb_t {
  62     uint8_t asid;               /* address space identifier */
  63     uint32_t vpn;               /* virtual page number */
  64     uint8_t v;                  /* validity */
  65     uint32_t ppn;               /* physical page number */
  66     uint8_t sz;                 /* page size */
  67     uint32_t size;              /* cached page size in bytes */
  68     uint8_t sh;                 /* share status */
  69     uint8_t c;                  /* cacheability */
  70     uint8_t pr;                 /* protection key */
  71     uint8_t d;                  /* dirty */
  72     uint8_t wt;                 /* write through */
  73     uint8_t sa;                 /* space attribute (PCMCIA) */
  74     uint8_t tc;                 /* timing control */
  75 } tlb_t;
  76
  77 #define UTLB_SIZE 64
  78 #define ITLB_SIZE 4
  79
  80 #define NB_MMU_MODES 2
  81
  82 typedef struct CPUSH4State {
  83     uint32_t flags;             /* general execution flags */
  84     uint32_t gregs[24];         /* general registers */
  85     float32 fregs[32];          /* floating point registers */
  86     uint32_t sr;                /* status register */
  87     uint32_t ssr;               /* saved status register */
  88     uint32_t spc;               /* saved program counter */
  89     uint32_t gbr;               /* global base register */
  90     uint32_t vbr;               /* vector base register */
  91     uint32_t sgr;               /* saved global register 15 */
  92     uint32_t dbr;               /* debug base register */
  93     uint32_t pc;                /* program counter */
  94     uint32_t delayed_pc;        /* target of delayed jump */
  95     uint32_t mach;              /* multiply and accumulate high */
  96     uint32_t macl;              /* multiply and accumulate low */
  97     uint32_t pr;                /* procedure register */
  98     uint32_t fpscr;             /* floating point status/control register */
  99     uint32_t fpul;              /* floating point communication register */
 100
 101     /* float point status register */
 102     float_status fp_status;
 103
 104     /* Those belong to the specific unit (SH7750) but are handled here */
 105     uint32_t mmucr;             /* MMU control register */
 106     uint32_t pteh;              /* page table entry high register */
 107     uint32_t ptel;              /* page table entry low register */
 108     uint32_t ptea;              /* page table entry assistance register */
 109     uint32_t ttb;               /* tranlation table base register */
 110     uint32_t tea;               /* TLB exception address register */
 111     uint32_t tra;               /* TRAPA exception register */
 112     uint32_t expevt;            /* exception event register */
 113     uint32_t intevt;            /* interrupt event register */
 114
 115      CPU_COMMON tlb_t utlb[UTLB_SIZE];  /* unified translation table */
 116     tlb_t itlb[ITLB_SIZE];      /* instruction translation table */
 117     void *intc_handle;
 118     int intr_at_halt;           /* SR_BL ignored during sleep */
 119 } CPUSH4State;
 120
 121 CPUSH4State *cpu_sh4_init(const char *cpu_model);
 122 int cpu_sh4_exec(CPUSH4State * s);
 123 int cpu_sh4_signal_handler(int host_signum, void *pinfo,
 124                            void *puc);
 125 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
 126                                     uint32_t mem_value);
 127
 128 #include "softfloat.h"
 129
 130 #define CPUState CPUSH4State
 131 #define cpu_init cpu_sh4_init
 132 #define cpu_exec cpu_sh4_exec
 133 #define cpu_gen_code cpu_sh4_gen_code
 134 #define cpu_signal_handler cpu_sh4_signal_handler
 135
 136 /* MMU modes definitions */
 137 #define MMU_MODE0_SUFFIX _kernel
 138 #define MMU_MODE1_SUFFIX _user
 139 #define MMU_USER_IDX 1
 140 static inline int cpu_mmu_index (CPUState *env)
 141 {
 142     return (env->sr & SR_MD) == 0 ? 1 : 0;
 143 }
 144
 145 #if defined(CONFIG_USER_ONLY)
 146 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 147 {
 148     if (newsp)
 149         env->gregs[15] = newsp;
 150     env->gregs[0] = 0;
 151 }
 152 #endif
 153
 154 #define CPU_PC_FROM_TB(env, tb) do { \
 155     env->pc = tb->pc; \
 156     env->flags = tb->flags; \
 157     } while (0)
 158
 159 #include "cpu-all.h"
 160
 161 /* Memory access type */
 162 enum {
 163     /* Privilege */
 164     ACCESS_PRIV = 0x01,
 165     /* Direction */
 166     ACCESS_WRITE = 0x02,
 167     /* Type of instruction */
 168     ACCESS_CODE = 0x10,
 169     ACCESS_INT = 0x20
 170 };
 171
 172 /* MMU control register */
 173 #define MMUCR    0x1F000010
 174 #define MMUCR_AT (1<<0)
 175 #define MMUCR_SV (1<<8)
 176 #define MMUCR_URC_BITS (6)
 177 #define MMUCR_URC_OFFSET (10)
 178 #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
 179 #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
 180 static inline int cpu_mmucr_urc (uint32_t mmucr)
 181 {
 182     return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
 183 }
 184
 185 /* PTEH : Page Translation Entry High register */
 186 #define PTEH_ASID_BITS (8)
 187 #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
 188 #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
 189 #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
 190 #define PTEH_VPN_BITS (22)
 191 #define PTEH_VPN_OFFSET (10)
 192 #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
 193 #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
 194 static inline int cpu_pteh_vpn (uint32_t pteh)
 195 {
 196     return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
 197 }
 198
 199 /* PTEL : Page Translation Entry Low register */
 200 #define PTEL_V        (1 << 8)
 201 #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
 202 #define PTEL_C        (1 << 3)
 203 #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
 204 #define PTEL_D        (1 << 2)
 205 #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
 206 #define PTEL_SH       (1 << 1)
 207 #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
 208 #define PTEL_WT       (1 << 0)
 209 #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
 210
 211 #define PTEL_SZ_HIGH_OFFSET  (7)
 212 #define PTEL_SZ_HIGH  (1 << PTEL_SZ_HIGH_OFFSET)
 213 #define PTEL_SZ_LOW_OFFSET   (4)
 214 #define PTEL_SZ_LOW   (1 << PTEL_SZ_LOW_OFFSET)
 215 static inline int cpu_ptel_sz (uint32_t ptel)
 216 {
 217     int sz;
 218     sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
 219     sz <<= 1;
 220     sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
 221     return sz;
 222 }
 223
 224 #define PTEL_PPN_BITS (19)
 225 #define PTEL_PPN_OFFSET (10)
 226 #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
 227 #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
 228 static inline int cpu_ptel_ppn (uint32_t ptel)
 229 {
 230     return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
 231 }
 232
 233 #define PTEL_PR_BITS   (2)
 234 #define PTEL_PR_OFFSET (5)
 235 #define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
 236 #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
 237 static inline int cpu_ptel_pr (uint32_t ptel)
 238 {
 239     return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
 240 }
 241
 242 /* PTEA : Page Translation Entry Assistance register */
 243 #define PTEA_SA_BITS (3)
 244 #define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
 245 #define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
 246 #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
 247 #define PTEA_TC        (1 << 3)
 248 #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
 249
 250 #endif                          /* _CPU_SH4_H */