]> git.proxmox.com Git - mirror_qemu.git/blob - target-sh4/op.c
Fix missing status ro mask initialization, thanks Stefan Weil.
[mirror_qemu.git] / target-sh4 / op.c
1 /*
2 * SH4 emulation
3 *
4 * Copyright (c) 2005 Samuel Tardieu
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "exec.h"
21
22 static inline void set_flag(uint32_t flag)
23 {
24 env->flags |= flag;
25 }
26
27 static inline void clr_flag(uint32_t flag)
28 {
29 env->flags &= ~flag;
30 }
31
32 static inline void set_t(void)
33 {
34 env->sr |= SR_T;
35 }
36
37 static inline void clr_t(void)
38 {
39 env->sr &= ~SR_T;
40 }
41
42 static inline void cond_t(int cond)
43 {
44 if (cond)
45 set_t();
46 else
47 clr_t();
48 }
49
50 void OPPROTO op_movl_imm_T0(void)
51 {
52 T0 = (uint32_t) PARAM1;
53 RETURN();
54 }
55
56 void OPPROTO op_movl_imm_T1(void)
57 {
58 T0 = (uint32_t) PARAM1;
59 RETURN();
60 }
61
62 void OPPROTO op_movl_imm_T2(void)
63 {
64 T0 = (uint32_t) PARAM1;
65 RETURN();
66 }
67
68 void OPPROTO op_cmp_eq_imm_T0(void)
69 {
70 cond_t((int32_t) T0 == (int32_t) PARAM1);
71 RETURN();
72 }
73
74 void OPPROTO op_cmd_eq_T0_T1(void)
75 {
76 cond_t(T0 == T1);
77 RETURN();
78 }
79
80 void OPPROTO op_cmd_hs_T0_T1(void)
81 {
82 cond_t((uint32_t) T0 <= (uint32_t) T1);
83 RETURN();
84 }
85
86 void OPPROTO op_cmd_ge_T0_T1(void)
87 {
88 cond_t((int32_t) T0 <= (int32_t) T1);
89 RETURN();
90 }
91
92 void OPPROTO op_cmd_hi_T0_T1(void)
93 {
94 cond_t((uint32_t) T0 < (uint32_t) T1);
95 RETURN();
96 }
97
98 void OPPROTO op_cmd_gt_T0_T1(void)
99 {
100 cond_t((int32_t) T0 < (int32_t) T1);
101 RETURN();
102 }
103
104 void OPPROTO op_not_T0(void)
105 {
106 T0 = ~T0;
107 RETURN();
108 }
109
110 void OPPROTO op_bf_s(void)
111 {
112 env->delayed_pc = PARAM1;
113 set_flag(DELAY_SLOT_CONDITIONAL | ((~env->sr) & SR_T));
114 RETURN();
115 }
116
117 void OPPROTO op_bt_s(void)
118 {
119 env->delayed_pc = PARAM1;
120 set_flag(DELAY_SLOT_CONDITIONAL | (env->sr & SR_T));
121 RETURN();
122 }
123
124 void OPPROTO op_bra(void)
125 {
126 env->delayed_pc = PARAM1;
127 set_flag(DELAY_SLOT);
128 RETURN();
129 }
130
131 void OPPROTO op_braf_T0(void)
132 {
133 env->delayed_pc = PARAM1 + T0;
134 set_flag(DELAY_SLOT);
135 RETURN();
136 }
137
138 void OPPROTO op_bsr(void)
139 {
140 env->pr = PARAM1;
141 env->delayed_pc = PARAM2;
142 set_flag(DELAY_SLOT);
143 RETURN();
144 }
145
146 void OPPROTO op_bsrf_T0(void)
147 {
148 env->pr = PARAM1;
149 env->delayed_pc = PARAM1 + T0;
150 set_flag(DELAY_SLOT);
151 RETURN();
152 }
153
154 void OPPROTO op_jsr_T0(void)
155 {
156 env->pr = PARAM1;
157 env->delayed_pc = T0;
158 set_flag(DELAY_SLOT);
159 RETURN();
160 }
161
162 void OPPROTO op_rts(void)
163 {
164 env->delayed_pc = env->pr;
165 set_flag(DELAY_SLOT);
166 RETURN();
167 }
168
169 void OPPROTO op_clr_delay_slot(void)
170 {
171 clr_flag(DELAY_SLOT);
172 RETURN();
173 }
174
175 void OPPROTO op_clr_delay_slot_conditional(void)
176 {
177 clr_flag(DELAY_SLOT_CONDITIONAL);
178 RETURN();
179 }
180
181 void OPPROTO op_exit_tb(void)
182 {
183 EXIT_TB();
184 RETURN();
185 }
186
187 void OPPROTO op_addl_imm_T0(void)
188 {
189 T0 += PARAM1;
190 RETURN();
191 }
192
193 void OPPROTO op_addl_imm_T1(void)
194 {
195 T1 += PARAM1;
196 RETURN();
197 }
198
199 void OPPROTO op_clrmac(void)
200 {
201 env->mach = env->macl = 0;
202 RETURN();
203 }
204
205 void OPPROTO op_clrs(void)
206 {
207 env->sr &= ~SR_S;
208 RETURN();
209 }
210
211 void OPPROTO op_clrt(void)
212 {
213 env->sr &= ~SR_T;
214 RETURN();
215 }
216
217 void OPPROTO op_sets(void)
218 {
219 env->sr |= SR_S;
220 RETURN();
221 }
222
223 void OPPROTO op_sett(void)
224 {
225 env->sr |= SR_T;
226 RETURN();
227 }
228
229 void OPPROTO op_frchg(void)
230 {
231 env->fpscr ^= FPSCR_FR;
232 RETURN();
233 }
234
235 void OPPROTO op_fschg(void)
236 {
237 env->fpscr ^= FPSCR_SZ;
238 RETURN();
239 }
240
241 void OPPROTO op_rte(void)
242 {
243 env->sr = env->ssr;
244 env->delayed_pc = env->spc;
245 set_flag(DELAY_SLOT);
246 RETURN();
247 }
248
249 void OPPROTO op_swapb_T0(void)
250 {
251 T0 = (T0 & 0xffff0000) | ((T0 & 0xff) << 8) | ((T0 >> 8) & 0xff);
252 RETURN();
253 }
254
255 void OPPROTO op_swapw_T0(void)
256 {
257 T0 = ((T0 & 0xffff) << 16) | ((T0 >> 16) & 0xffff);
258 RETURN();
259 }
260
261 void OPPROTO op_xtrct_T0_T1(void)
262 {
263 T1 = ((T0 & 0xffff) << 16) | ((T1 >> 16) & 0xffff);
264 RETURN();
265 }
266
267 void OPPROTO op_addc_T0_T1(void)
268 {
269 helper_addc_T0_T1();
270 RETURN();
271 }
272
273 void OPPROTO op_addv_T0_T1(void)
274 {
275 helper_addv_T0_T1();
276 RETURN();
277 }
278
279 void OPPROTO op_cmp_eq_T0_T1(void)
280 {
281 cond_t(T1 == T0);
282 RETURN();
283 }
284
285 void OPPROTO op_cmp_ge_T0_T1(void)
286 {
287 cond_t((int32_t) T1 >= (int32_t) T0);
288 RETURN();
289 }
290
291 void OPPROTO op_cmp_gt_T0_T1(void)
292 {
293 cond_t((int32_t) T1 > (int32_t) T0);
294 RETURN();
295 }
296
297 void OPPROTO op_cmp_hi_T0_T1(void)
298 {
299 cond_t((uint32_t) T1 > (uint32_t) T0);
300 RETURN();
301 }
302
303 void OPPROTO op_cmp_hs_T0_T1(void)
304 {
305 cond_t((uint32_t) T1 >= (uint32_t) T0);
306 RETURN();
307 }
308
309 void OPPROTO op_cmp_str_T0_T1(void)
310 {
311 cond_t((T0 & 0x000000ff) == (T1 & 0x000000ff) ||
312 (T0 & 0x0000ff00) == (T1 & 0x0000ff00) ||
313 (T0 & 0x00ff0000) == (T1 & 0x00ff0000) ||
314 (T0 & 0xff000000) == (T1 & 0xff000000));
315 RETURN();
316 }
317
318 void OPPROTO op_tst_T0_T1(void)
319 {
320 cond_t((T1 & T0) == 0);
321 RETURN();
322 }
323
324 void OPPROTO op_div0s_T0_T1(void)
325 {
326 if (T1 & 0x80000000)
327 env->sr |= SR_Q;
328 else
329 env->sr &= ~SR_Q;
330 if (T0 & 0x80000000)
331 env->sr |= SR_M;
332 else
333 env->sr &= ~SR_M;
334 cond_t((T1 ^ T0) & 0x80000000);
335 RETURN();
336 }
337
338 void OPPROTO op_div0u(void)
339 {
340 env->sr &= ~(SR_M | SR_Q | SR_T);
341 RETURN();
342 }
343
344 void OPPROTO op_div1_T0_T1(void)
345 {
346 helper_div1_T0_T1();
347 RETURN();
348 }
349
350 void OPPROTO op_dmulsl_T0_T1(void)
351 {
352 helper_dmulsl_T0_T1();
353 RETURN();
354 }
355
356 void OPPROTO op_dmulul_T0_T1(void)
357 {
358 helper_dmulul_T0_T1();
359 RETURN();
360 }
361
362 void OPPROTO op_macl_T0_T1(void)
363 {
364 helper_macl_T0_T1();
365 RETURN();
366 }
367
368 void OPPROTO op_macw_T0_T1(void)
369 {
370 helper_macw_T0_T1();
371 RETURN();
372 }
373
374 void OPPROTO op_mull_T0_T1(void)
375 {
376 env->macl = (T0 * T1) & 0xffffffff;
377 RETURN();
378 }
379
380 void OPPROTO op_mulsw_T0_T1(void)
381 {
382 env->macl = (int32_t) T0 *(int32_t) T1;
383 RETURN();
384 }
385
386 void OPPROTO op_muluw_T0_T1(void)
387 {
388 env->macl = (uint32_t) T0 *(uint32_t) T1;
389 RETURN();
390 }
391
392 void OPPROTO op_neg_T0(void)
393 {
394 T0 = -T0;
395 RETURN();
396 }
397
398 void OPPROTO op_negc_T0(void)
399 {
400 helper_negc_T0();
401 RETURN();
402 }
403
404 void OPPROTO op_shad_T0_T1(void)
405 {
406 if ((T0 & 0x80000000) == 0)
407 T1 <<= (T0 & 0x1f);
408 else if ((T0 & 0x1f) == 0)
409 T1 = 0;
410 else
411 T1 = ((int32_t) T1) >> ((~T0 & 0x1f) + 1);
412 RETURN();
413 }
414
415 void OPPROTO op_shld_T0_T1(void)
416 {
417 if ((T0 & 0x80000000) == 0)
418 T1 <<= (T0 & 0x1f);
419 else if ((T0 & 0x1f) == 0)
420 T1 = 0;
421 else
422 T1 = ((uint32_t) T1) >> ((~T0 & 0x1f) + 1);
423 RETURN();
424 }
425
426 void OPPROTO op_subc_T0_T1(void)
427 {
428 helper_subc_T0_T1();
429 RETURN();
430 }
431
432 void OPPROTO op_subv_T0_T1(void)
433 {
434 helper_subv_T0_T1();
435 RETURN();
436 }
437
438 void OPPROTO op_trapa(void)
439 {
440 env->tra = PARAM1 * 2;
441 env->exception_index = 0x160;
442 do_raise_exception();
443 RETURN();
444 }
445
446 void OPPROTO op_cmp_pl_T0(void)
447 {
448 cond_t((int32_t) T0 > 0);
449 RETURN();
450 }
451
452 void OPPROTO op_cmp_pz_T0(void)
453 {
454 cond_t((int32_t) T0 >= 0);
455 RETURN();
456 }
457
458 void OPPROTO op_jmp_T0(void)
459 {
460 env->delayed_pc = T0;
461 set_flag(DELAY_SLOT);
462 RETURN();
463 }
464
465 void OPPROTO op_movl_rN_rN(void)
466 {
467 env->gregs[PARAM2] = env->gregs[PARAM1];
468 RETURN();
469 }
470
471 void OPPROTO op_ldcl_rMplus_rN_bank(void)
472 {
473 env->gregs[PARAM2] = env->gregs[PARAM1];
474 env->gregs[PARAM1] += 4;
475 RETURN();
476 }
477
478 void OPPROTO op_ldc_T0_sr(void)
479 {
480 env->sr = T0 & 0x700083f3;
481 RETURN();
482 }
483
484 void OPPROTO op_stc_sr_T0(void)
485 {
486 T0 = env->sr;
487 RETURN();
488 }
489
490 #define LDSTOPS(target,load,store) \
491 void OPPROTO op_##load##_T0_##target (void) \
492 { env ->target = T0; RETURN(); \
493 } \
494 void OPPROTO op_##store##_##target##_T0 (void) \
495 { T0 = env->target; RETURN(); \
496 } \
497
498 LDSTOPS(gbr, ldc, stc)
499 LDSTOPS(vbr, ldc, stc)
500 LDSTOPS(ssr, ldc, stc)
501 LDSTOPS(spc, ldc, stc)
502 LDSTOPS(sgr, ldc, stc)
503 LDSTOPS(dbr, ldc, stc)
504 LDSTOPS(mach, lds, sts)
505 LDSTOPS(macl, lds, sts)
506 LDSTOPS(pr, lds, sts)
507 LDSTOPS(fpul, lds, sts)
508
509 void OPPROTO op_lds_T0_fpscr(void)
510 {
511 env->fpscr = T0 & 0x003fffff;
512 RETURN();
513 }
514
515 void OPPROTO op_sts_fpscr_T0(void)
516 {
517 T0 = env->fpscr & 0x003fffff;
518 RETURN();
519 }
520
521 void OPPROTO op_movt_rN(void)
522 {
523 env->gregs[PARAM1] = env->sr & SR_T;
524 RETURN();
525 }
526
527 void OPPROTO op_rotcl_Rn(void)
528 {
529 helper_rotcl(&env->gregs[PARAM1]);
530 RETURN();
531 }
532
533 void OPPROTO op_rotcr_Rn(void)
534 {
535 helper_rotcr(&env->gregs[PARAM1]);
536 RETURN();
537 }
538
539 void OPPROTO op_rotl_Rn(void)
540 {
541 cond_t(env->gregs[PARAM1] & 0x80000000);
542 env->gregs[PARAM1] = (env->gregs[PARAM1] << 1) | (env->sr & SR_T);
543 RETURN();
544 }
545
546 void OPPROTO op_rotr_Rn(void)
547 {
548 cond_t(env->gregs[PARAM1] & 1);
549 env->gregs[PARAM1] = (env->gregs[PARAM1] >> 1) |
550 ((env->sr & SR_T) ? 0x80000000 : 0);
551 RETURN();
552 }
553
554 void OPPROTO op_shal_Rn(void)
555 {
556 cond_t(env->gregs[PARAM1] & 0x80000000);
557 env->gregs[PARAM1] <<= 1;
558 RETURN();
559 }
560
561 void OPPROTO op_shar_Rn(void)
562 {
563 cond_t(env->gregs[PARAM1] & 1);
564 *(int32_t *) & env->gregs[PARAM1] >>= 1;
565 RETURN();
566 }
567
568 void OPPROTO op_shlr_Rn(void)
569 {
570 cond_t(env->gregs[PARAM1] & 1);
571 *(uint32_t *) & env->gregs[PARAM1] >>= 1;
572 RETURN();
573 }
574
575 void OPPROTO op_shll2_Rn(void)
576 {
577 env->gregs[PARAM1] <<= 2;
578 RETURN();
579 }
580
581 void OPPROTO op_shll8_Rn(void)
582 {
583 env->gregs[PARAM1] <<= 8;
584 RETURN();
585 }
586
587 void OPPROTO op_shll16_Rn(void)
588 {
589 env->gregs[PARAM1] <<= 16;
590 RETURN();
591 }
592
593 void OPPROTO op_shlr2_Rn(void)
594 {
595 *(uint32_t *) & env->gregs[PARAM1] >>= 2;
596 RETURN();
597 }
598
599 void OPPROTO op_shlr8_Rn(void)
600 {
601 *(uint32_t *) & env->gregs[PARAM1] >>= 8;
602 RETURN();
603 }
604
605 void OPPROTO op_shlr16_Rn(void)
606 {
607 *(uint32_t *) & env->gregs[PARAM1] >>= 16;
608 RETURN();
609 }
610
611 void OPPROTO op_tasb_rN(void)
612 {
613 cond_t(*(int8_t *) env->gregs[PARAM1] == 0);
614 *(int8_t *) env->gregs[PARAM1] |= 0x80;
615 RETURN();
616 }
617
618 void OPPROTO op_movl_T0_rN(void)
619 {
620 env->gregs[PARAM1] = T0;
621 RETURN();
622 }
623
624 void OPPROTO op_movl_T1_rN(void)
625 {
626 env->gregs[PARAM1] = T1;
627 RETURN();
628 }
629
630 void OPPROTO op_movb_rN_T0(void)
631 {
632 T0 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
633 RETURN();
634 }
635
636 void OPPROTO op_movub_rN_T0(void)
637 {
638 T0 = env->gregs[PARAM1] & 0xff;
639 RETURN();
640 }
641
642 void OPPROTO op_movw_rN_T0(void)
643 {
644 T0 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
645 RETURN();
646 }
647
648 void OPPROTO op_movuw_rN_T0(void)
649 {
650 T0 = env->gregs[PARAM1] & 0xffff;
651 RETURN();
652 }
653
654 void OPPROTO op_movl_rN_T0(void)
655 {
656 T0 = env->gregs[PARAM1];
657 RETURN();
658 }
659
660 void OPPROTO op_movb_rN_T1(void)
661 {
662 T1 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
663 RETURN();
664 }
665
666 void OPPROTO op_movub_rN_T1(void)
667 {
668 T1 = env->gregs[PARAM1] & 0xff;
669 RETURN();
670 }
671
672 void OPPROTO op_movw_rN_T1(void)
673 {
674 T1 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
675 RETURN();
676 }
677
678 void OPPROTO op_movuw_rN_T1(void)
679 {
680 T1 = env->gregs[PARAM1] & 0xffff;
681 RETURN();
682 }
683
684 void OPPROTO op_movl_rN_T1(void)
685 {
686 T1 = env->gregs[PARAM1];
687 RETURN();
688 }
689
690 void OPPROTO op_movl_imm_rN(void)
691 {
692 env->gregs[PARAM2] = PARAM1;
693 RETURN();
694 }
695
696 void OPPROTO op_fmov_frN_FT0(void)
697 {
698 FT0 = *(float32 *)&env->fregs[PARAM1];
699 RETURN();
700 }
701
702 void OPPROTO op_fmov_drN_DT0(void)
703 {
704 DT0 = *(float64 *)&env->fregs[PARAM1];
705 RETURN();
706 }
707
708 void OPPROTO op_fmov_FT0_frN(void)
709 {
710 *(float32 *)&env->fregs[PARAM1] = FT0;
711 RETURN();
712 }
713
714 void OPPROTO op_fmov_DT0_drN(void)
715 {
716 *(float64 *)&env->fregs[PARAM1] = DT0;
717 RETURN();
718 }
719
720 void OPPROTO op_dec1_rN(void)
721 {
722 env->gregs[PARAM1] -= 1;
723 RETURN();
724 }
725
726 void OPPROTO op_dec2_rN(void)
727 {
728 env->gregs[PARAM1] -= 2;
729 RETURN();
730 }
731
732 void OPPROTO op_dec4_rN(void)
733 {
734 env->gregs[PARAM1] -= 4;
735 RETURN();
736 }
737
738 void OPPROTO op_dec8_rN(void)
739 {
740 env->gregs[PARAM1] -= 8;
741 RETURN();
742 }
743
744 void OPPROTO op_inc1_rN(void)
745 {
746 env->gregs[PARAM1] += 1;
747 RETURN();
748 }
749
750 void OPPROTO op_inc2_rN(void)
751 {
752 env->gregs[PARAM1] += 2;
753 RETURN();
754 }
755
756 void OPPROTO op_inc4_rN(void)
757 {
758 env->gregs[PARAM1] += 4;
759 RETURN();
760 }
761
762 void OPPROTO op_inc8_rN(void)
763 {
764 env->gregs[PARAM1] += 8;
765 RETURN();
766 }
767
768 void OPPROTO op_add_T0_rN(void)
769 {
770 env->gregs[PARAM1] += T0;
771 RETURN();
772 }
773
774 void OPPROTO op_sub_T0_rN(void)
775 {
776 env->gregs[PARAM1] -= T0;
777 RETURN();
778 }
779
780 void OPPROTO op_and_T0_rN(void)
781 {
782 env->gregs[PARAM1] &= T0;
783 RETURN();
784 }
785
786 void OPPROTO op_or_T0_rN(void)
787 {
788 env->gregs[PARAM1] |= T0;
789 RETURN();
790 }
791
792 void OPPROTO op_xor_T0_rN(void)
793 {
794 env->gregs[PARAM1] ^= T0;
795 RETURN();
796 }
797
798 void OPPROTO op_add_rN_T0(void)
799 {
800 T0 += env->gregs[PARAM1];
801 RETURN();
802 }
803
804 void OPPROTO op_add_rN_T1(void)
805 {
806 T1 += env->gregs[PARAM1];
807 RETURN();
808 }
809
810 void OPPROTO op_add_imm_rN(void)
811 {
812 env->gregs[PARAM2] += PARAM1;
813 RETURN();
814 }
815
816 void OPPROTO op_and_imm_rN(void)
817 {
818 env->gregs[PARAM2] &= PARAM1;
819 RETURN();
820 }
821
822 void OPPROTO op_or_imm_rN(void)
823 {
824 env->gregs[PARAM2] |= PARAM1;
825 RETURN();
826 }
827
828 void OPPROTO op_xor_imm_rN(void)
829 {
830 env->gregs[PARAM2] ^= PARAM1;
831 RETURN();
832 }
833
834 void OPPROTO op_dt_rN(void)
835 {
836 cond_t((--env->gregs[PARAM1]) == 0);
837 RETURN();
838 }
839
840 void OPPROTO op_tst_imm_rN(void)
841 {
842 cond_t((env->gregs[PARAM2] & PARAM1) == 0);
843 RETURN();
844 }
845
846 void OPPROTO op_movl_T0_T1(void)
847 {
848 T1 = T0;
849 RETURN();
850 }
851
852 void OPPROTO op_movl_fpul_FT0(void)
853 {
854 FT0 = *(float32 *)&env->fpul;
855 RETURN();
856 }
857
858 void OPPROTO op_movl_FT0_fpul(void)
859 {
860 *(float32 *)&env->fpul = FT0;
861 RETURN();
862 }
863
864 void OPPROTO op_goto_tb0(void)
865 {
866 GOTO_TB(op_goto_tb0, PARAM1, 0);
867 RETURN();
868 }
869
870 void OPPROTO op_goto_tb1(void)
871 {
872 GOTO_TB(op_goto_tb1, PARAM1, 1);
873 RETURN();
874 }
875
876 void OPPROTO op_movl_imm_PC(void)
877 {
878 env->pc = PARAM1;
879 RETURN();
880 }
881
882 void OPPROTO op_jT(void)
883 {
884 if (env->sr & SR_T)
885 GOTO_LABEL_PARAM(1);
886 RETURN();
887 }
888
889 void OPPROTO op_jdelayed(void)
890 {
891 uint32_t flags;
892 flags = env->flags;
893 env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
894 if (flags & DELAY_SLOT)
895 GOTO_LABEL_PARAM(1);
896 RETURN();
897 }
898
899 void OPPROTO op_movl_delayed_pc_PC(void)
900 {
901 env->pc = env->delayed_pc;
902 RETURN();
903 }
904
905 void OPPROTO op_addl_GBR_T0(void)
906 {
907 T0 += env->gbr;
908 RETURN();
909 }
910
911 void OPPROTO op_and_imm_T0(void)
912 {
913 T0 &= PARAM1;
914 RETURN();
915 }
916
917 void OPPROTO op_or_imm_T0(void)
918 {
919 T0 |= PARAM1;
920 RETURN();
921 }
922
923 void OPPROTO op_xor_imm_T0(void)
924 {
925 T0 ^= PARAM1;
926 RETURN();
927 }
928
929 void OPPROTO op_tst_imm_T0(void)
930 {
931 cond_t((T0 & PARAM1) == 0);
932 RETURN();
933 }
934
935 void OPPROTO op_raise_illegal_instruction(void)
936 {
937 env->exception_index = 0x180;
938 do_raise_exception();
939 RETURN();
940 }
941
942 void OPPROTO op_raise_slot_illegal_instruction(void)
943 {
944 env->exception_index = 0x1a0;
945 do_raise_exception();
946 RETURN();
947 }
948
949 void OPPROTO op_debug(void)
950 {
951 env->exception_index = EXCP_DEBUG;
952 cpu_loop_exit();
953 }
954
955 /* Load and store */
956 #define MEMSUFFIX _raw
957 #include "op_mem.c"
958 #undef MEMSUFFIX
959 #if !defined(CONFIG_USER_ONLY)
960 #define MEMSUFFIX _user
961 #include "op_mem.c"
962 #undef MEMSUFFIX
963
964 #define MEMSUFFIX _kernel
965 #include "op_mem.c"
966 #undef MEMSUFFIX
967 #endif