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target-sh4: simplify comparisons after a 'and' op
[mirror_qemu.git] / target-sh4 / translate.c
1 /*
2 * SH4 translation
3 *
4 * Copyright (c) 2005 Samuel Tardieu
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24
25 #define DEBUG_DISAS
26 #define SH4_DEBUG_DISAS
27 //#define SH4_SINGLE_STEP
28
29 #include "cpu.h"
30 #include "exec-all.h"
31 #include "disas.h"
32 #include "tcg-op.h"
33 #include "qemu-common.h"
34
35 #include "helper.h"
36 #define GEN_HELPER 1
37 #include "helper.h"
38
39 typedef struct DisasContext {
40 struct TranslationBlock *tb;
41 target_ulong pc;
42 uint32_t sr;
43 uint32_t fpscr;
44 uint16_t opcode;
45 uint32_t flags;
46 int bstate;
47 int memidx;
48 uint32_t delayed_pc;
49 int singlestep_enabled;
50 uint32_t features;
51 int has_movcal;
52 } DisasContext;
53
54 #if defined(CONFIG_USER_ONLY)
55 #define IS_USER(ctx) 1
56 #else
57 #define IS_USER(ctx) (!(ctx->sr & SR_MD))
58 #endif
59
60 enum {
61 BS_NONE = 0, /* We go out of the TB without reaching a branch or an
62 * exception condition
63 */
64 BS_STOP = 1, /* We want to stop translation for any reason */
65 BS_BRANCH = 2, /* We reached a branch condition */
66 BS_EXCP = 3, /* We reached an exception condition */
67 };
68
69 /* global register indexes */
70 static TCGv_ptr cpu_env;
71 static TCGv cpu_gregs[24];
72 static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr;
73 static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
74 static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_ldst;
75 static TCGv cpu_fregs[32];
76
77 /* internal register indexes */
78 static TCGv cpu_flags, cpu_delayed_pc;
79
80 static uint32_t gen_opc_hflags[OPC_BUF_SIZE];
81
82 #include "gen-icount.h"
83
84 static void sh4_translate_init(void)
85 {
86 int i;
87 static int done_init = 0;
88 static const char * const gregnames[24] = {
89 "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0",
90 "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0",
91 "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
92 "R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1",
93 "R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1"
94 };
95 static const char * const fregnames[32] = {
96 "FPR0_BANK0", "FPR1_BANK0", "FPR2_BANK0", "FPR3_BANK0",
97 "FPR4_BANK0", "FPR5_BANK0", "FPR6_BANK0", "FPR7_BANK0",
98 "FPR8_BANK0", "FPR9_BANK0", "FPR10_BANK0", "FPR11_BANK0",
99 "FPR12_BANK0", "FPR13_BANK0", "FPR14_BANK0", "FPR15_BANK0",
100 "FPR0_BANK1", "FPR1_BANK1", "FPR2_BANK1", "FPR3_BANK1",
101 "FPR4_BANK1", "FPR5_BANK1", "FPR6_BANK1", "FPR7_BANK1",
102 "FPR8_BANK1", "FPR9_BANK1", "FPR10_BANK1", "FPR11_BANK1",
103 "FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1",
104 };
105
106 if (done_init)
107 return;
108
109 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
110
111 for (i = 0; i < 24; i++)
112 cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
113 offsetof(CPUState, gregs[i]),
114 gregnames[i]);
115
116 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
117 offsetof(CPUState, pc), "PC");
118 cpu_sr = tcg_global_mem_new_i32(TCG_AREG0,
119 offsetof(CPUState, sr), "SR");
120 cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0,
121 offsetof(CPUState, ssr), "SSR");
122 cpu_spc = tcg_global_mem_new_i32(TCG_AREG0,
123 offsetof(CPUState, spc), "SPC");
124 cpu_gbr = tcg_global_mem_new_i32(TCG_AREG0,
125 offsetof(CPUState, gbr), "GBR");
126 cpu_vbr = tcg_global_mem_new_i32(TCG_AREG0,
127 offsetof(CPUState, vbr), "VBR");
128 cpu_sgr = tcg_global_mem_new_i32(TCG_AREG0,
129 offsetof(CPUState, sgr), "SGR");
130 cpu_dbr = tcg_global_mem_new_i32(TCG_AREG0,
131 offsetof(CPUState, dbr), "DBR");
132 cpu_mach = tcg_global_mem_new_i32(TCG_AREG0,
133 offsetof(CPUState, mach), "MACH");
134 cpu_macl = tcg_global_mem_new_i32(TCG_AREG0,
135 offsetof(CPUState, macl), "MACL");
136 cpu_pr = tcg_global_mem_new_i32(TCG_AREG0,
137 offsetof(CPUState, pr), "PR");
138 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
139 offsetof(CPUState, fpscr), "FPSCR");
140 cpu_fpul = tcg_global_mem_new_i32(TCG_AREG0,
141 offsetof(CPUState, fpul), "FPUL");
142
143 cpu_flags = tcg_global_mem_new_i32(TCG_AREG0,
144 offsetof(CPUState, flags), "_flags_");
145 cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0,
146 offsetof(CPUState, delayed_pc),
147 "_delayed_pc_");
148 cpu_ldst = tcg_global_mem_new_i32(TCG_AREG0,
149 offsetof(CPUState, ldst), "_ldst_");
150
151 for (i = 0; i < 32; i++)
152 cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
153 offsetof(CPUState, fregs[i]),
154 fregnames[i]);
155
156 /* register helpers */
157 #define GEN_HELPER 2
158 #include "helper.h"
159
160 done_init = 1;
161 }
162
163 void cpu_dump_state(CPUState * env, FILE * f,
164 int (*cpu_fprintf) (FILE * f, const char *fmt, ...),
165 int flags)
166 {
167 int i;
168 cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n",
169 env->pc, env->sr, env->pr, env->fpscr);
170 cpu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n",
171 env->spc, env->ssr, env->gbr, env->vbr);
172 cpu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n",
173 env->sgr, env->dbr, env->delayed_pc, env->fpul);
174 for (i = 0; i < 24; i += 4) {
175 cpu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n",
176 i, env->gregs[i], i + 1, env->gregs[i + 1],
177 i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]);
178 }
179 if (env->flags & DELAY_SLOT) {
180 cpu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n",
181 env->delayed_pc);
182 } else if (env->flags & DELAY_SLOT_CONDITIONAL) {
183 cpu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n",
184 env->delayed_pc);
185 }
186 }
187
188 void cpu_reset(CPUSH4State * env)
189 {
190 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
191 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
192 log_cpu_state(env, 0);
193 }
194
195 memset(env, 0, offsetof(CPUSH4State, breakpoints));
196 tlb_flush(env, 1);
197
198 env->pc = 0xA0000000;
199 #if defined(CONFIG_USER_ONLY)
200 env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
201 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
202 #else
203 env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0;
204 env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
205 set_float_rounding_mode(float_round_to_zero, &env->fp_status);
206 set_flush_to_zero(1, &env->fp_status);
207 #endif
208 set_default_nan_mode(1, &env->fp_status);
209 }
210
211 typedef struct {
212 const char *name;
213 int id;
214 uint32_t pvr;
215 uint32_t prr;
216 uint32_t cvr;
217 uint32_t features;
218 } sh4_def_t;
219
220 static sh4_def_t sh4_defs[] = {
221 {
222 .name = "SH7750R",
223 .id = SH_CPU_SH7750R,
224 .pvr = 0x00050000,
225 .prr = 0x00000100,
226 .cvr = 0x00110000,
227 .features = SH_FEATURE_BCR3_AND_BCR4,
228 }, {
229 .name = "SH7751R",
230 .id = SH_CPU_SH7751R,
231 .pvr = 0x04050005,
232 .prr = 0x00000113,
233 .cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */
234 .features = SH_FEATURE_BCR3_AND_BCR4,
235 }, {
236 .name = "SH7785",
237 .id = SH_CPU_SH7785,
238 .pvr = 0x10300700,
239 .prr = 0x00000200,
240 .cvr = 0x71440211,
241 .features = SH_FEATURE_SH4A,
242 },
243 };
244
245 static const sh4_def_t *cpu_sh4_find_by_name(const char *name)
246 {
247 int i;
248
249 if (strcasecmp(name, "any") == 0)
250 return &sh4_defs[0];
251
252 for (i = 0; i < ARRAY_SIZE(sh4_defs); i++)
253 if (strcasecmp(name, sh4_defs[i].name) == 0)
254 return &sh4_defs[i];
255
256 return NULL;
257 }
258
259 void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
260 {
261 int i;
262
263 for (i = 0; i < ARRAY_SIZE(sh4_defs); i++)
264 (*cpu_fprintf)(f, "%s\n", sh4_defs[i].name);
265 }
266
267 static void cpu_register(CPUSH4State *env, const sh4_def_t *def)
268 {
269 env->pvr = def->pvr;
270 env->prr = def->prr;
271 env->cvr = def->cvr;
272 env->id = def->id;
273 }
274
275 CPUSH4State *cpu_sh4_init(const char *cpu_model)
276 {
277 CPUSH4State *env;
278 const sh4_def_t *def;
279
280 def = cpu_sh4_find_by_name(cpu_model);
281 if (!def)
282 return NULL;
283 env = qemu_mallocz(sizeof(CPUSH4State));
284 env->features = def->features;
285 cpu_exec_init(env);
286 env->movcal_backup_tail = &(env->movcal_backup);
287 sh4_translate_init();
288 env->cpu_model_str = cpu_model;
289 cpu_reset(env);
290 cpu_register(env, def);
291 qemu_init_vcpu(env);
292 return env;
293 }
294
295 static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest)
296 {
297 TranslationBlock *tb;
298 tb = ctx->tb;
299
300 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
301 !ctx->singlestep_enabled) {
302 /* Use a direct jump if in same page and singlestep not enabled */
303 tcg_gen_goto_tb(n);
304 tcg_gen_movi_i32(cpu_pc, dest);
305 tcg_gen_exit_tb((long) tb + n);
306 } else {
307 tcg_gen_movi_i32(cpu_pc, dest);
308 if (ctx->singlestep_enabled)
309 gen_helper_debug();
310 tcg_gen_exit_tb(0);
311 }
312 }
313
314 static void gen_jump(DisasContext * ctx)
315 {
316 if (ctx->delayed_pc == (uint32_t) - 1) {
317 /* Target is not statically known, it comes necessarily from a
318 delayed jump as immediate jump are conditinal jumps */
319 tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc);
320 if (ctx->singlestep_enabled)
321 gen_helper_debug();
322 tcg_gen_exit_tb(0);
323 } else {
324 gen_goto_tb(ctx, 0, ctx->delayed_pc);
325 }
326 }
327
328 static inline void gen_branch_slot(uint32_t delayed_pc, int t)
329 {
330 TCGv sr;
331 int label = gen_new_label();
332 tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc);
333 sr = tcg_temp_new();
334 tcg_gen_andi_i32(sr, cpu_sr, SR_T);
335 tcg_gen_brcondi_i32(t ? TCG_COND_EQ:TCG_COND_NE, sr, 0, label);
336 tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE);
337 gen_set_label(label);
338 }
339
340 /* Immediate conditional jump (bt or bf) */
341 static void gen_conditional_jump(DisasContext * ctx,
342 target_ulong ift, target_ulong ifnott)
343 {
344 int l1;
345 TCGv sr;
346
347 l1 = gen_new_label();
348 sr = tcg_temp_new();
349 tcg_gen_andi_i32(sr, cpu_sr, SR_T);
350 tcg_gen_brcondi_i32(TCG_COND_NE, sr, 0, l1);
351 gen_goto_tb(ctx, 0, ifnott);
352 gen_set_label(l1);
353 gen_goto_tb(ctx, 1, ift);
354 }
355
356 /* Delayed conditional jump (bt or bf) */
357 static void gen_delayed_conditional_jump(DisasContext * ctx)
358 {
359 int l1;
360 TCGv ds;
361
362 l1 = gen_new_label();
363 ds = tcg_temp_new();
364 tcg_gen_andi_i32(ds, cpu_flags, DELAY_SLOT_TRUE);
365 tcg_gen_brcondi_i32(TCG_COND_NE, ds, 0, l1);
366 gen_goto_tb(ctx, 1, ctx->pc + 2);
367 gen_set_label(l1);
368 tcg_gen_andi_i32(cpu_flags, cpu_flags, ~DELAY_SLOT_TRUE);
369 gen_jump(ctx);
370 }
371
372 static inline void gen_set_t(void)
373 {
374 tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
375 }
376
377 static inline void gen_clr_t(void)
378 {
379 tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
380 }
381
382 static inline void gen_cmp(int cond, TCGv t0, TCGv t1)
383 {
384 int label1 = gen_new_label();
385 int label2 = gen_new_label();
386 tcg_gen_brcond_i32(cond, t1, t0, label1);
387 gen_clr_t();
388 tcg_gen_br(label2);
389 gen_set_label(label1);
390 gen_set_t();
391 gen_set_label(label2);
392 }
393
394 static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm)
395 {
396 int label1 = gen_new_label();
397 int label2 = gen_new_label();
398 tcg_gen_brcondi_i32(cond, t0, imm, label1);
399 gen_clr_t();
400 tcg_gen_br(label2);
401 gen_set_label(label1);
402 gen_set_t();
403 gen_set_label(label2);
404 }
405
406 static inline void gen_store_flags(uint32_t flags)
407 {
408 tcg_gen_andi_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE);
409 tcg_gen_ori_i32(cpu_flags, cpu_flags, flags);
410 }
411
412 static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1)
413 {
414 TCGv tmp = tcg_temp_new();
415
416 p0 &= 0x1f;
417 p1 &= 0x1f;
418
419 tcg_gen_andi_i32(tmp, t1, (1 << p1));
420 tcg_gen_andi_i32(t0, t0, ~(1 << p0));
421 if (p0 < p1)
422 tcg_gen_shri_i32(tmp, tmp, p1 - p0);
423 else if (p0 > p1)
424 tcg_gen_shli_i32(tmp, tmp, p0 - p1);
425 tcg_gen_or_i32(t0, t0, tmp);
426
427 tcg_temp_free(tmp);
428 }
429
430 static inline void gen_load_fpr64(TCGv_i64 t, int reg)
431 {
432 tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]);
433 }
434
435 static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
436 {
437 TCGv_i32 tmp = tcg_temp_new_i32();
438 tcg_gen_trunc_i64_i32(tmp, t);
439 tcg_gen_mov_i32(cpu_fregs[reg + 1], tmp);
440 tcg_gen_shri_i64(t, t, 32);
441 tcg_gen_trunc_i64_i32(tmp, t);
442 tcg_gen_mov_i32(cpu_fregs[reg], tmp);
443 tcg_temp_free_i32(tmp);
444 }
445
446 #define B3_0 (ctx->opcode & 0xf)
447 #define B6_4 ((ctx->opcode >> 4) & 0x7)
448 #define B7_4 ((ctx->opcode >> 4) & 0xf)
449 #define B7_0 (ctx->opcode & 0xff)
450 #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff))
451 #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \
452 (ctx->opcode & 0xfff))
453 #define B11_8 ((ctx->opcode >> 8) & 0xf)
454 #define B15_12 ((ctx->opcode >> 12) & 0xf)
455
456 #define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \
457 (cpu_gregs[x + 16]) : (cpu_gregs[x]))
458
459 #define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \
460 ? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
461
462 #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x))
463 #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
464 #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
465 #define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */
466
467 #define CHECK_NOT_DELAY_SLOT \
468 if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
469 { \
470 gen_helper_raise_slot_illegal_instruction(); \
471 ctx->bstate = BS_EXCP; \
472 return; \
473 }
474
475 #define CHECK_PRIVILEGED \
476 if (IS_USER(ctx)) { \
477 if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
478 gen_helper_raise_slot_illegal_instruction(); \
479 } else { \
480 gen_helper_raise_illegal_instruction(); \
481 } \
482 ctx->bstate = BS_EXCP; \
483 return; \
484 }
485
486 #define CHECK_FPU_ENABLED \
487 if (ctx->flags & SR_FD) { \
488 if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
489 gen_helper_raise_slot_fpu_disable(); \
490 } else { \
491 gen_helper_raise_fpu_disable(); \
492 } \
493 ctx->bstate = BS_EXCP; \
494 return; \
495 }
496
497 static void _decode_opc(DisasContext * ctx)
498 {
499 /* This code tries to make movcal emulation sufficiently
500 accurate for Linux purposes. This instruction writes
501 memory, and prior to that, always allocates a cache line.
502 It is used in two contexts:
503 - in memcpy, where data is copied in blocks, the first write
504 of to a block uses movca.l for performance.
505 - in arch/sh/mm/cache-sh4.c, movcal.l + ocbi combination is used
506 to flush the cache. Here, the data written by movcal.l is never
507 written to memory, and the data written is just bogus.
508
509 To simulate this, we simulate movcal.l, we store the value to memory,
510 but we also remember the previous content. If we see ocbi, we check
511 if movcal.l for that address was done previously. If so, the write should
512 not have hit the memory, so we restore the previous content.
513 When we see an instruction that is neither movca.l
514 nor ocbi, the previous content is discarded.
515
516 To optimize, we only try to flush stores when we're at the start of
517 TB, or if we already saw movca.l in this TB and did not flush stores
518 yet. */
519 if (ctx->has_movcal)
520 {
521 int opcode = ctx->opcode & 0xf0ff;
522 if (opcode != 0x0093 /* ocbi */
523 && opcode != 0x00c3 /* movca.l */)
524 {
525 gen_helper_discard_movcal_backup ();
526 ctx->has_movcal = 0;
527 }
528 }
529
530 #if 0
531 fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);
532 #endif
533
534 switch (ctx->opcode) {
535 case 0x0019: /* div0u */
536 tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T));
537 return;
538 case 0x000b: /* rts */
539 CHECK_NOT_DELAY_SLOT
540 tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr);
541 ctx->flags |= DELAY_SLOT;
542 ctx->delayed_pc = (uint32_t) - 1;
543 return;
544 case 0x0028: /* clrmac */
545 tcg_gen_movi_i32(cpu_mach, 0);
546 tcg_gen_movi_i32(cpu_macl, 0);
547 return;
548 case 0x0048: /* clrs */
549 tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S);
550 return;
551 case 0x0008: /* clrt */
552 gen_clr_t();
553 return;
554 case 0x0038: /* ldtlb */
555 CHECK_PRIVILEGED
556 gen_helper_ldtlb();
557 return;
558 case 0x002b: /* rte */
559 CHECK_PRIVILEGED
560 CHECK_NOT_DELAY_SLOT
561 tcg_gen_mov_i32(cpu_sr, cpu_ssr);
562 tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc);
563 ctx->flags |= DELAY_SLOT;
564 ctx->delayed_pc = (uint32_t) - 1;
565 return;
566 case 0x0058: /* sets */
567 tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S);
568 return;
569 case 0x0018: /* sett */
570 gen_set_t();
571 return;
572 case 0xfbfd: /* frchg */
573 tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR);
574 ctx->bstate = BS_STOP;
575 return;
576 case 0xf3fd: /* fschg */
577 tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ);
578 ctx->bstate = BS_STOP;
579 return;
580 case 0x0009: /* nop */
581 return;
582 case 0x001b: /* sleep */
583 CHECK_PRIVILEGED
584 gen_helper_sleep(tcg_const_i32(ctx->pc + 2));
585 return;
586 }
587
588 switch (ctx->opcode & 0xf000) {
589 case 0x1000: /* mov.l Rm,@(disp,Rn) */
590 {
591 TCGv addr = tcg_temp_new();
592 tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
593 tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
594 tcg_temp_free(addr);
595 }
596 return;
597 case 0x5000: /* mov.l @(disp,Rm),Rn */
598 {
599 TCGv addr = tcg_temp_new();
600 tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4);
601 tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
602 tcg_temp_free(addr);
603 }
604 return;
605 case 0xe000: /* mov #imm,Rn */
606 tcg_gen_movi_i32(REG(B11_8), B7_0s);
607 return;
608 case 0x9000: /* mov.w @(disp,PC),Rn */
609 {
610 TCGv addr = tcg_const_i32(ctx->pc + 4 + B7_0 * 2);
611 tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx);
612 tcg_temp_free(addr);
613 }
614 return;
615 case 0xd000: /* mov.l @(disp,PC),Rn */
616 {
617 TCGv addr = tcg_const_i32((ctx->pc + 4 + B7_0 * 4) & ~3);
618 tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
619 tcg_temp_free(addr);
620 }
621 return;
622 case 0x7000: /* add #imm,Rn */
623 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), B7_0s);
624 return;
625 case 0xa000: /* bra disp */
626 CHECK_NOT_DELAY_SLOT
627 ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;
628 tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);
629 ctx->flags |= DELAY_SLOT;
630 return;
631 case 0xb000: /* bsr disp */
632 CHECK_NOT_DELAY_SLOT
633 tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
634 ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;
635 tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);
636 ctx->flags |= DELAY_SLOT;
637 return;
638 }
639
640 switch (ctx->opcode & 0xf00f) {
641 case 0x6003: /* mov Rm,Rn */
642 tcg_gen_mov_i32(REG(B11_8), REG(B7_4));
643 return;
644 case 0x2000: /* mov.b Rm,@Rn */
645 tcg_gen_qemu_st8(REG(B7_4), REG(B11_8), ctx->memidx);
646 return;
647 case 0x2001: /* mov.w Rm,@Rn */
648 tcg_gen_qemu_st16(REG(B7_4), REG(B11_8), ctx->memidx);
649 return;
650 case 0x2002: /* mov.l Rm,@Rn */
651 tcg_gen_qemu_st32(REG(B7_4), REG(B11_8), ctx->memidx);
652 return;
653 case 0x6000: /* mov.b @Rm,Rn */
654 tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx);
655 return;
656 case 0x6001: /* mov.w @Rm,Rn */
657 tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx);
658 return;
659 case 0x6002: /* mov.l @Rm,Rn */
660 tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx);
661 return;
662 case 0x2004: /* mov.b Rm,@-Rn */
663 {
664 TCGv addr = tcg_temp_new();
665 tcg_gen_subi_i32(addr, REG(B11_8), 1);
666 tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); /* might cause re-execution */
667 tcg_gen_mov_i32(REG(B11_8), addr); /* modify register status */
668 tcg_temp_free(addr);
669 }
670 return;
671 case 0x2005: /* mov.w Rm,@-Rn */
672 {
673 TCGv addr = tcg_temp_new();
674 tcg_gen_subi_i32(addr, REG(B11_8), 2);
675 tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);
676 tcg_gen_mov_i32(REG(B11_8), addr);
677 tcg_temp_free(addr);
678 }
679 return;
680 case 0x2006: /* mov.l Rm,@-Rn */
681 {
682 TCGv addr = tcg_temp_new();
683 tcg_gen_subi_i32(addr, REG(B11_8), 4);
684 tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
685 tcg_gen_mov_i32(REG(B11_8), addr);
686 }
687 return;
688 case 0x6004: /* mov.b @Rm+,Rn */
689 tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx);
690 if ( B11_8 != B7_4 )
691 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1);
692 return;
693 case 0x6005: /* mov.w @Rm+,Rn */
694 tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx);
695 if ( B11_8 != B7_4 )
696 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
697 return;
698 case 0x6006: /* mov.l @Rm+,Rn */
699 tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx);
700 if ( B11_8 != B7_4 )
701 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
702 return;
703 case 0x0004: /* mov.b Rm,@(R0,Rn) */
704 {
705 TCGv addr = tcg_temp_new();
706 tcg_gen_add_i32(addr, REG(B11_8), REG(0));
707 tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx);
708 tcg_temp_free(addr);
709 }
710 return;
711 case 0x0005: /* mov.w Rm,@(R0,Rn) */
712 {
713 TCGv addr = tcg_temp_new();
714 tcg_gen_add_i32(addr, REG(B11_8), REG(0));
715 tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);
716 tcg_temp_free(addr);
717 }
718 return;
719 case 0x0006: /* mov.l Rm,@(R0,Rn) */
720 {
721 TCGv addr = tcg_temp_new();
722 tcg_gen_add_i32(addr, REG(B11_8), REG(0));
723 tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
724 tcg_temp_free(addr);
725 }
726 return;
727 case 0x000c: /* mov.b @(R0,Rm),Rn */
728 {
729 TCGv addr = tcg_temp_new();
730 tcg_gen_add_i32(addr, REG(B7_4), REG(0));
731 tcg_gen_qemu_ld8s(REG(B11_8), addr, ctx->memidx);
732 tcg_temp_free(addr);
733 }
734 return;
735 case 0x000d: /* mov.w @(R0,Rm),Rn */
736 {
737 TCGv addr = tcg_temp_new();
738 tcg_gen_add_i32(addr, REG(B7_4), REG(0));
739 tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx);
740 tcg_temp_free(addr);
741 }
742 return;
743 case 0x000e: /* mov.l @(R0,Rm),Rn */
744 {
745 TCGv addr = tcg_temp_new();
746 tcg_gen_add_i32(addr, REG(B7_4), REG(0));
747 tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
748 tcg_temp_free(addr);
749 }
750 return;
751 case 0x6008: /* swap.b Rm,Rn */
752 {
753 TCGv high, low;
754 high = tcg_temp_new();
755 tcg_gen_andi_i32(high, REG(B7_4), 0xffff0000);
756 low = tcg_temp_new();
757 tcg_gen_ext16u_i32(low, REG(B7_4));
758 tcg_gen_bswap16_i32(low, low);
759 tcg_gen_or_i32(REG(B11_8), high, low);
760 tcg_temp_free(low);
761 tcg_temp_free(high);
762 }
763 return;
764 case 0x6009: /* swap.w Rm,Rn */
765 {
766 TCGv high, low;
767 high = tcg_temp_new();
768 tcg_gen_shli_i32(high, REG(B7_4), 16);
769 low = tcg_temp_new();
770 tcg_gen_shri_i32(low, REG(B7_4), 16);
771 tcg_gen_ext16u_i32(low, low);
772 tcg_gen_or_i32(REG(B11_8), high, low);
773 tcg_temp_free(low);
774 tcg_temp_free(high);
775 }
776 return;
777 case 0x200d: /* xtrct Rm,Rn */
778 {
779 TCGv high, low;
780 high = tcg_temp_new();
781 tcg_gen_shli_i32(high, REG(B7_4), 16);
782 low = tcg_temp_new();
783 tcg_gen_shri_i32(low, REG(B11_8), 16);
784 tcg_gen_ext16u_i32(low, low);
785 tcg_gen_or_i32(REG(B11_8), high, low);
786 tcg_temp_free(low);
787 tcg_temp_free(high);
788 }
789 return;
790 case 0x300c: /* add Rm,Rn */
791 tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4));
792 return;
793 case 0x300e: /* addc Rm,Rn */
794 gen_helper_addc(REG(B11_8), REG(B7_4), REG(B11_8));
795 return;
796 case 0x300f: /* addv Rm,Rn */
797 gen_helper_addv(REG(B11_8), REG(B7_4), REG(B11_8));
798 return;
799 case 0x2009: /* and Rm,Rn */
800 tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4));
801 return;
802 case 0x3000: /* cmp/eq Rm,Rn */
803 gen_cmp(TCG_COND_EQ, REG(B7_4), REG(B11_8));
804 return;
805 case 0x3003: /* cmp/ge Rm,Rn */
806 gen_cmp(TCG_COND_GE, REG(B7_4), REG(B11_8));
807 return;
808 case 0x3007: /* cmp/gt Rm,Rn */
809 gen_cmp(TCG_COND_GT, REG(B7_4), REG(B11_8));
810 return;
811 case 0x3006: /* cmp/hi Rm,Rn */
812 gen_cmp(TCG_COND_GTU, REG(B7_4), REG(B11_8));
813 return;
814 case 0x3002: /* cmp/hs Rm,Rn */
815 gen_cmp(TCG_COND_GEU, REG(B7_4), REG(B11_8));
816 return;
817 case 0x200c: /* cmp/str Rm,Rn */
818 {
819 int label1 = gen_new_label();
820 int label2 = gen_new_label();
821 TCGv cmp1 = tcg_temp_local_new();
822 TCGv cmp2 = tcg_temp_local_new();
823 tcg_gen_xor_i32(cmp1, REG(B7_4), REG(B11_8));
824 tcg_gen_andi_i32(cmp2, cmp1, 0xff000000);
825 tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
826 tcg_gen_andi_i32(cmp2, cmp1, 0x00ff0000);
827 tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
828 tcg_gen_andi_i32(cmp2, cmp1, 0x0000ff00);
829 tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
830 tcg_gen_andi_i32(cmp2, cmp1, 0x000000ff);
831 tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
832 tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
833 tcg_gen_br(label2);
834 gen_set_label(label1);
835 tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
836 gen_set_label(label2);
837 tcg_temp_free(cmp2);
838 tcg_temp_free(cmp1);
839 }
840 return;
841 case 0x2007: /* div0s Rm,Rn */
842 {
843 gen_copy_bit_i32(cpu_sr, 8, REG(B11_8), 31); /* SR_Q */
844 gen_copy_bit_i32(cpu_sr, 9, REG(B7_4), 31); /* SR_M */
845 TCGv val = tcg_temp_new();
846 tcg_gen_xor_i32(val, REG(B7_4), REG(B11_8));
847 gen_copy_bit_i32(cpu_sr, 0, val, 31); /* SR_T */
848 tcg_temp_free(val);
849 }
850 return;
851 case 0x3004: /* div1 Rm,Rn */
852 gen_helper_div1(REG(B11_8), REG(B7_4), REG(B11_8));
853 return;
854 case 0x300d: /* dmuls.l Rm,Rn */
855 {
856 TCGv_i64 tmp1 = tcg_temp_new_i64();
857 TCGv_i64 tmp2 = tcg_temp_new_i64();
858
859 tcg_gen_ext_i32_i64(tmp1, REG(B7_4));
860 tcg_gen_ext_i32_i64(tmp2, REG(B11_8));
861 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
862 tcg_gen_trunc_i64_i32(cpu_macl, tmp1);
863 tcg_gen_shri_i64(tmp1, tmp1, 32);
864 tcg_gen_trunc_i64_i32(cpu_mach, tmp1);
865
866 tcg_temp_free_i64(tmp2);
867 tcg_temp_free_i64(tmp1);
868 }
869 return;
870 case 0x3005: /* dmulu.l Rm,Rn */
871 {
872 TCGv_i64 tmp1 = tcg_temp_new_i64();
873 TCGv_i64 tmp2 = tcg_temp_new_i64();
874
875 tcg_gen_extu_i32_i64(tmp1, REG(B7_4));
876 tcg_gen_extu_i32_i64(tmp2, REG(B11_8));
877 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
878 tcg_gen_trunc_i64_i32(cpu_macl, tmp1);
879 tcg_gen_shri_i64(tmp1, tmp1, 32);
880 tcg_gen_trunc_i64_i32(cpu_mach, tmp1);
881
882 tcg_temp_free_i64(tmp2);
883 tcg_temp_free_i64(tmp1);
884 }
885 return;
886 case 0x600e: /* exts.b Rm,Rn */
887 tcg_gen_ext8s_i32(REG(B11_8), REG(B7_4));
888 return;
889 case 0x600f: /* exts.w Rm,Rn */
890 tcg_gen_ext16s_i32(REG(B11_8), REG(B7_4));
891 return;
892 case 0x600c: /* extu.b Rm,Rn */
893 tcg_gen_ext8u_i32(REG(B11_8), REG(B7_4));
894 return;
895 case 0x600d: /* extu.w Rm,Rn */
896 tcg_gen_ext16u_i32(REG(B11_8), REG(B7_4));
897 return;
898 case 0x000f: /* mac.l @Rm+,@Rn+ */
899 {
900 TCGv arg0, arg1;
901 arg0 = tcg_temp_new();
902 tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
903 arg1 = tcg_temp_new();
904 tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
905 gen_helper_macl(arg0, arg1);
906 tcg_temp_free(arg1);
907 tcg_temp_free(arg0);
908 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
909 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
910 }
911 return;
912 case 0x400f: /* mac.w @Rm+,@Rn+ */
913 {
914 TCGv arg0, arg1;
915 arg0 = tcg_temp_new();
916 tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
917 arg1 = tcg_temp_new();
918 tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
919 gen_helper_macw(arg0, arg1);
920 tcg_temp_free(arg1);
921 tcg_temp_free(arg0);
922 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2);
923 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
924 }
925 return;
926 case 0x0007: /* mul.l Rm,Rn */
927 tcg_gen_mul_i32(cpu_macl, REG(B7_4), REG(B11_8));
928 return;
929 case 0x200f: /* muls.w Rm,Rn */
930 {
931 TCGv arg0, arg1;
932 arg0 = tcg_temp_new();
933 tcg_gen_ext16s_i32(arg0, REG(B7_4));
934 arg1 = tcg_temp_new();
935 tcg_gen_ext16s_i32(arg1, REG(B11_8));
936 tcg_gen_mul_i32(cpu_macl, arg0, arg1);
937 tcg_temp_free(arg1);
938 tcg_temp_free(arg0);
939 }
940 return;
941 case 0x200e: /* mulu.w Rm,Rn */
942 {
943 TCGv arg0, arg1;
944 arg0 = tcg_temp_new();
945 tcg_gen_ext16u_i32(arg0, REG(B7_4));
946 arg1 = tcg_temp_new();
947 tcg_gen_ext16u_i32(arg1, REG(B11_8));
948 tcg_gen_mul_i32(cpu_macl, arg0, arg1);
949 tcg_temp_free(arg1);
950 tcg_temp_free(arg0);
951 }
952 return;
953 case 0x600b: /* neg Rm,Rn */
954 tcg_gen_neg_i32(REG(B11_8), REG(B7_4));
955 return;
956 case 0x600a: /* negc Rm,Rn */
957 gen_helper_negc(REG(B11_8), REG(B7_4));
958 return;
959 case 0x6007: /* not Rm,Rn */
960 tcg_gen_not_i32(REG(B11_8), REG(B7_4));
961 return;
962 case 0x200b: /* or Rm,Rn */
963 tcg_gen_or_i32(REG(B11_8), REG(B11_8), REG(B7_4));
964 return;
965 case 0x400c: /* shad Rm,Rn */
966 {
967 int label1 = gen_new_label();
968 int label2 = gen_new_label();
969 int label3 = gen_new_label();
970 int label4 = gen_new_label();
971 TCGv shift;
972 tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
973 /* Rm positive, shift to the left */
974 shift = tcg_temp_new();
975 tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
976 tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);
977 tcg_temp_free(shift);
978 tcg_gen_br(label4);
979 /* Rm negative, shift to the right */
980 gen_set_label(label1);
981 shift = tcg_temp_new();
982 tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
983 tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
984 tcg_gen_not_i32(shift, REG(B7_4));
985 tcg_gen_andi_i32(shift, shift, 0x1f);
986 tcg_gen_addi_i32(shift, shift, 1);
987 tcg_gen_sar_i32(REG(B11_8), REG(B11_8), shift);
988 tcg_temp_free(shift);
989 tcg_gen_br(label4);
990 /* Rm = -32 */
991 gen_set_label(label2);
992 tcg_gen_brcondi_i32(TCG_COND_LT, REG(B11_8), 0, label3);
993 tcg_gen_movi_i32(REG(B11_8), 0);
994 tcg_gen_br(label4);
995 gen_set_label(label3);
996 tcg_gen_movi_i32(REG(B11_8), 0xffffffff);
997 gen_set_label(label4);
998 }
999 return;
1000 case 0x400d: /* shld Rm,Rn */
1001 {
1002 int label1 = gen_new_label();
1003 int label2 = gen_new_label();
1004 int label3 = gen_new_label();
1005 TCGv shift;
1006 tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
1007 /* Rm positive, shift to the left */
1008 shift = tcg_temp_new();
1009 tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
1010 tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);
1011 tcg_temp_free(shift);
1012 tcg_gen_br(label3);
1013 /* Rm negative, shift to the right */
1014 gen_set_label(label1);
1015 shift = tcg_temp_new();
1016 tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
1017 tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
1018 tcg_gen_not_i32(shift, REG(B7_4));
1019 tcg_gen_andi_i32(shift, shift, 0x1f);
1020 tcg_gen_addi_i32(shift, shift, 1);
1021 tcg_gen_shr_i32(REG(B11_8), REG(B11_8), shift);
1022 tcg_temp_free(shift);
1023 tcg_gen_br(label3);
1024 /* Rm = -32 */
1025 gen_set_label(label2);
1026 tcg_gen_movi_i32(REG(B11_8), 0);
1027 gen_set_label(label3);
1028 }
1029 return;
1030 case 0x3008: /* sub Rm,Rn */
1031 tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4));
1032 return;
1033 case 0x300a: /* subc Rm,Rn */
1034 gen_helper_subc(REG(B11_8), REG(B7_4), REG(B11_8));
1035 return;
1036 case 0x300b: /* subv Rm,Rn */
1037 gen_helper_subv(REG(B11_8), REG(B7_4), REG(B11_8));
1038 return;
1039 case 0x2008: /* tst Rm,Rn */
1040 {
1041 TCGv val = tcg_temp_new();
1042 tcg_gen_and_i32(val, REG(B7_4), REG(B11_8));
1043 gen_cmp_imm(TCG_COND_EQ, val, 0);
1044 tcg_temp_free(val);
1045 }
1046 return;
1047 case 0x200a: /* xor Rm,Rn */
1048 tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4));
1049 return;
1050 case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
1051 CHECK_FPU_ENABLED
1052 if (ctx->fpscr & FPSCR_SZ) {
1053 TCGv_i64 fp = tcg_temp_new_i64();
1054 gen_load_fpr64(fp, XREG(B7_4));
1055 gen_store_fpr64(fp, XREG(B11_8));
1056 tcg_temp_free_i64(fp);
1057 } else {
1058 tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1059 }
1060 return;
1061 case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
1062 CHECK_FPU_ENABLED
1063 if (ctx->fpscr & FPSCR_SZ) {
1064 TCGv addr_hi = tcg_temp_new();
1065 int fr = XREG(B7_4);
1066 tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
1067 tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
1068 tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
1069 tcg_temp_free(addr_hi);
1070 } else {
1071 tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
1072 }
1073 return;
1074 case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
1075 CHECK_FPU_ENABLED
1076 if (ctx->fpscr & FPSCR_SZ) {
1077 TCGv addr_hi = tcg_temp_new();
1078 int fr = XREG(B11_8);
1079 tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
1080 tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
1081 tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
1082 tcg_temp_free(addr_hi);
1083 } else {
1084 tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
1085 }
1086 return;
1087 case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
1088 CHECK_FPU_ENABLED
1089 if (ctx->fpscr & FPSCR_SZ) {
1090 TCGv addr_hi = tcg_temp_new();
1091 int fr = XREG(B11_8);
1092 tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
1093 tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
1094 tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
1095 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8);
1096 tcg_temp_free(addr_hi);
1097 } else {
1098 tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
1099 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
1100 }
1101 return;
1102 case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
1103 CHECK_FPU_ENABLED
1104 if (ctx->fpscr & FPSCR_SZ) {
1105 TCGv addr = tcg_temp_new_i32();
1106 int fr = XREG(B7_4);
1107 tcg_gen_subi_i32(addr, REG(B11_8), 4);
1108 tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
1109 tcg_gen_subi_i32(addr, addr, 4);
1110 tcg_gen_qemu_st32(cpu_fregs[fr ], addr, ctx->memidx);
1111 tcg_gen_mov_i32(REG(B11_8), addr);
1112 tcg_temp_free(addr);
1113 } else {
1114 TCGv addr;
1115 addr = tcg_temp_new_i32();
1116 tcg_gen_subi_i32(addr, REG(B11_8), 4);
1117 tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
1118 tcg_gen_mov_i32(REG(B11_8), addr);
1119 tcg_temp_free(addr);
1120 }
1121 return;
1122 case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
1123 CHECK_FPU_ENABLED
1124 {
1125 TCGv addr = tcg_temp_new_i32();
1126 tcg_gen_add_i32(addr, REG(B7_4), REG(0));
1127 if (ctx->fpscr & FPSCR_SZ) {
1128 int fr = XREG(B11_8);
1129 tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
1130 tcg_gen_addi_i32(addr, addr, 4);
1131 tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
1132 } else {
1133 tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx);
1134 }
1135 tcg_temp_free(addr);
1136 }
1137 return;
1138 case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
1139 CHECK_FPU_ENABLED
1140 {
1141 TCGv addr = tcg_temp_new();
1142 tcg_gen_add_i32(addr, REG(B11_8), REG(0));
1143 if (ctx->fpscr & FPSCR_SZ) {
1144 int fr = XREG(B7_4);
1145 tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
1146 tcg_gen_addi_i32(addr, addr, 4);
1147 tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
1148 } else {
1149 tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
1150 }
1151 tcg_temp_free(addr);
1152 }
1153 return;
1154 case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1155 case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1156 case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1157 case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1158 case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1159 case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1160 {
1161 CHECK_FPU_ENABLED
1162 if (ctx->fpscr & FPSCR_PR) {
1163 TCGv_i64 fp0, fp1;
1164
1165 if (ctx->opcode & 0x0110)
1166 break; /* illegal instruction */
1167 fp0 = tcg_temp_new_i64();
1168 fp1 = tcg_temp_new_i64();
1169 gen_load_fpr64(fp0, DREG(B11_8));
1170 gen_load_fpr64(fp1, DREG(B7_4));
1171 switch (ctx->opcode & 0xf00f) {
1172 case 0xf000: /* fadd Rm,Rn */
1173 gen_helper_fadd_DT(fp0, fp0, fp1);
1174 break;
1175 case 0xf001: /* fsub Rm,Rn */
1176 gen_helper_fsub_DT(fp0, fp0, fp1);
1177 break;
1178 case 0xf002: /* fmul Rm,Rn */
1179 gen_helper_fmul_DT(fp0, fp0, fp1);
1180 break;
1181 case 0xf003: /* fdiv Rm,Rn */
1182 gen_helper_fdiv_DT(fp0, fp0, fp1);
1183 break;
1184 case 0xf004: /* fcmp/eq Rm,Rn */
1185 gen_helper_fcmp_eq_DT(fp0, fp1);
1186 return;
1187 case 0xf005: /* fcmp/gt Rm,Rn */
1188 gen_helper_fcmp_gt_DT(fp0, fp1);
1189 return;
1190 }
1191 gen_store_fpr64(fp0, DREG(B11_8));
1192 tcg_temp_free_i64(fp0);
1193 tcg_temp_free_i64(fp1);
1194 } else {
1195 switch (ctx->opcode & 0xf00f) {
1196 case 0xf000: /* fadd Rm,Rn */
1197 gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1198 break;
1199 case 0xf001: /* fsub Rm,Rn */
1200 gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1201 break;
1202 case 0xf002: /* fmul Rm,Rn */
1203 gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1204 break;
1205 case 0xf003: /* fdiv Rm,Rn */
1206 gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1207 break;
1208 case 0xf004: /* fcmp/eq Rm,Rn */
1209 gen_helper_fcmp_eq_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1210 return;
1211 case 0xf005: /* fcmp/gt Rm,Rn */
1212 gen_helper_fcmp_gt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1213 return;
1214 }
1215 }
1216 }
1217 return;
1218 case 0xf00e: /* fmac FR0,RM,Rn */
1219 {
1220 CHECK_FPU_ENABLED
1221 if (ctx->fpscr & FPSCR_PR) {
1222 break; /* illegal instruction */
1223 } else {
1224 gen_helper_fmac_FT(cpu_fregs[FREG(B11_8)],
1225 cpu_fregs[FREG(0)], cpu_fregs[FREG(B7_4)], cpu_fregs[FREG(B11_8)]);
1226 return;
1227 }
1228 }
1229 }
1230
1231 switch (ctx->opcode & 0xff00) {
1232 case 0xc900: /* and #imm,R0 */
1233 tcg_gen_andi_i32(REG(0), REG(0), B7_0);
1234 return;
1235 case 0xcd00: /* and.b #imm,@(R0,GBR) */
1236 {
1237 TCGv addr, val;
1238 addr = tcg_temp_new();
1239 tcg_gen_add_i32(addr, REG(0), cpu_gbr);
1240 val = tcg_temp_new();
1241 tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1242 tcg_gen_andi_i32(val, val, B7_0);
1243 tcg_gen_qemu_st8(val, addr, ctx->memidx);
1244 tcg_temp_free(val);
1245 tcg_temp_free(addr);
1246 }
1247 return;
1248 case 0x8b00: /* bf label */
1249 CHECK_NOT_DELAY_SLOT
1250 gen_conditional_jump(ctx, ctx->pc + 2,
1251 ctx->pc + 4 + B7_0s * 2);
1252 ctx->bstate = BS_BRANCH;
1253 return;
1254 case 0x8f00: /* bf/s label */
1255 CHECK_NOT_DELAY_SLOT
1256 gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 0);
1257 ctx->flags |= DELAY_SLOT_CONDITIONAL;
1258 return;
1259 case 0x8900: /* bt label */
1260 CHECK_NOT_DELAY_SLOT
1261 gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2,
1262 ctx->pc + 2);
1263 ctx->bstate = BS_BRANCH;
1264 return;
1265 case 0x8d00: /* bt/s label */
1266 CHECK_NOT_DELAY_SLOT
1267 gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 1);
1268 ctx->flags |= DELAY_SLOT_CONDITIONAL;
1269 return;
1270 case 0x8800: /* cmp/eq #imm,R0 */
1271 gen_cmp_imm(TCG_COND_EQ, REG(0), B7_0s);
1272 return;
1273 case 0xc400: /* mov.b @(disp,GBR),R0 */
1274 {
1275 TCGv addr = tcg_temp_new();
1276 tcg_gen_addi_i32(addr, cpu_gbr, B7_0);
1277 tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
1278 tcg_temp_free(addr);
1279 }
1280 return;
1281 case 0xc500: /* mov.w @(disp,GBR),R0 */
1282 {
1283 TCGv addr = tcg_temp_new();
1284 tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
1285 tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
1286 tcg_temp_free(addr);
1287 }
1288 return;
1289 case 0xc600: /* mov.l @(disp,GBR),R0 */
1290 {
1291 TCGv addr = tcg_temp_new();
1292 tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
1293 tcg_gen_qemu_ld32s(REG(0), addr, ctx->memidx);
1294 tcg_temp_free(addr);
1295 }
1296 return;
1297 case 0xc000: /* mov.b R0,@(disp,GBR) */
1298 {
1299 TCGv addr = tcg_temp_new();
1300 tcg_gen_addi_i32(addr, cpu_gbr, B7_0);
1301 tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
1302 tcg_temp_free(addr);
1303 }
1304 return;
1305 case 0xc100: /* mov.w R0,@(disp,GBR) */
1306 {
1307 TCGv addr = tcg_temp_new();
1308 tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
1309 tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
1310 tcg_temp_free(addr);
1311 }
1312 return;
1313 case 0xc200: /* mov.l R0,@(disp,GBR) */
1314 {
1315 TCGv addr = tcg_temp_new();
1316 tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
1317 tcg_gen_qemu_st32(REG(0), addr, ctx->memidx);
1318 tcg_temp_free(addr);
1319 }
1320 return;
1321 case 0x8000: /* mov.b R0,@(disp,Rn) */
1322 {
1323 TCGv addr = tcg_temp_new();
1324 tcg_gen_addi_i32(addr, REG(B7_4), B3_0);
1325 tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
1326 tcg_temp_free(addr);
1327 }
1328 return;
1329 case 0x8100: /* mov.w R0,@(disp,Rn) */
1330 {
1331 TCGv addr = tcg_temp_new();
1332 tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
1333 tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
1334 tcg_temp_free(addr);
1335 }
1336 return;
1337 case 0x8400: /* mov.b @(disp,Rn),R0 */
1338 {
1339 TCGv addr = tcg_temp_new();
1340 tcg_gen_addi_i32(addr, REG(B7_4), B3_0);
1341 tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
1342 tcg_temp_free(addr);
1343 }
1344 return;
1345 case 0x8500: /* mov.w @(disp,Rn),R0 */
1346 {
1347 TCGv addr = tcg_temp_new();
1348 tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
1349 tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
1350 tcg_temp_free(addr);
1351 }
1352 return;
1353 case 0xc700: /* mova @(disp,PC),R0 */
1354 tcg_gen_movi_i32(REG(0), ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3);
1355 return;
1356 case 0xcb00: /* or #imm,R0 */
1357 tcg_gen_ori_i32(REG(0), REG(0), B7_0);
1358 return;
1359 case 0xcf00: /* or.b #imm,@(R0,GBR) */
1360 {
1361 TCGv addr, val;
1362 addr = tcg_temp_new();
1363 tcg_gen_add_i32(addr, REG(0), cpu_gbr);
1364 val = tcg_temp_new();
1365 tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1366 tcg_gen_ori_i32(val, val, B7_0);
1367 tcg_gen_qemu_st8(val, addr, ctx->memidx);
1368 tcg_temp_free(val);
1369 tcg_temp_free(addr);
1370 }
1371 return;
1372 case 0xc300: /* trapa #imm */
1373 {
1374 TCGv imm;
1375 CHECK_NOT_DELAY_SLOT
1376 imm = tcg_const_i32(B7_0);
1377 gen_helper_trapa(imm);
1378 tcg_temp_free(imm);
1379 ctx->bstate = BS_BRANCH;
1380 }
1381 return;
1382 case 0xc800: /* tst #imm,R0 */
1383 {
1384 TCGv val = tcg_temp_new();
1385 tcg_gen_andi_i32(val, REG(0), B7_0);
1386 gen_cmp_imm(TCG_COND_EQ, val, 0);
1387 tcg_temp_free(val);
1388 }
1389 return;
1390 case 0xcc00: /* tst.b #imm,@(R0,GBR) */
1391 {
1392 TCGv val = tcg_temp_new();
1393 tcg_gen_add_i32(val, REG(0), cpu_gbr);
1394 tcg_gen_qemu_ld8u(val, val, ctx->memidx);
1395 tcg_gen_andi_i32(val, val, B7_0);
1396 gen_cmp_imm(TCG_COND_EQ, val, 0);
1397 tcg_temp_free(val);
1398 }
1399 return;
1400 case 0xca00: /* xor #imm,R0 */
1401 tcg_gen_xori_i32(REG(0), REG(0), B7_0);
1402 return;
1403 case 0xce00: /* xor.b #imm,@(R0,GBR) */
1404 {
1405 TCGv addr, val;
1406 addr = tcg_temp_new();
1407 tcg_gen_add_i32(addr, REG(0), cpu_gbr);
1408 val = tcg_temp_new();
1409 tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1410 tcg_gen_xori_i32(val, val, B7_0);
1411 tcg_gen_qemu_st8(val, addr, ctx->memidx);
1412 tcg_temp_free(val);
1413 tcg_temp_free(addr);
1414 }
1415 return;
1416 }
1417
1418 switch (ctx->opcode & 0xf08f) {
1419 case 0x408e: /* ldc Rm,Rn_BANK */
1420 CHECK_PRIVILEGED
1421 tcg_gen_mov_i32(ALTREG(B6_4), REG(B11_8));
1422 return;
1423 case 0x4087: /* ldc.l @Rm+,Rn_BANK */
1424 CHECK_PRIVILEGED
1425 tcg_gen_qemu_ld32s(ALTREG(B6_4), REG(B11_8), ctx->memidx);
1426 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1427 return;
1428 case 0x0082: /* stc Rm_BANK,Rn */
1429 CHECK_PRIVILEGED
1430 tcg_gen_mov_i32(REG(B11_8), ALTREG(B6_4));
1431 return;
1432 case 0x4083: /* stc.l Rm_BANK,@-Rn */
1433 CHECK_PRIVILEGED
1434 {
1435 TCGv addr = tcg_temp_new();
1436 tcg_gen_subi_i32(addr, REG(B11_8), 4);
1437 tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx);
1438 tcg_gen_mov_i32(REG(B11_8), addr);
1439 tcg_temp_free(addr);
1440 }
1441 return;
1442 }
1443
1444 switch (ctx->opcode & 0xf0ff) {
1445 case 0x0023: /* braf Rn */
1446 CHECK_NOT_DELAY_SLOT
1447 tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->pc + 4);
1448 ctx->flags |= DELAY_SLOT;
1449 ctx->delayed_pc = (uint32_t) - 1;
1450 return;
1451 case 0x0003: /* bsrf Rn */
1452 CHECK_NOT_DELAY_SLOT
1453 tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
1454 tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr);
1455 ctx->flags |= DELAY_SLOT;
1456 ctx->delayed_pc = (uint32_t) - 1;
1457 return;
1458 case 0x4015: /* cmp/pl Rn */
1459 gen_cmp_imm(TCG_COND_GT, REG(B11_8), 0);
1460 return;
1461 case 0x4011: /* cmp/pz Rn */
1462 gen_cmp_imm(TCG_COND_GE, REG(B11_8), 0);
1463 return;
1464 case 0x4010: /* dt Rn */
1465 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1);
1466 gen_cmp_imm(TCG_COND_EQ, REG(B11_8), 0);
1467 return;
1468 case 0x402b: /* jmp @Rn */
1469 CHECK_NOT_DELAY_SLOT
1470 tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
1471 ctx->flags |= DELAY_SLOT;
1472 ctx->delayed_pc = (uint32_t) - 1;
1473 return;
1474 case 0x400b: /* jsr @Rn */
1475 CHECK_NOT_DELAY_SLOT
1476 tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
1477 tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
1478 ctx->flags |= DELAY_SLOT;
1479 ctx->delayed_pc = (uint32_t) - 1;
1480 return;
1481 case 0x400e: /* ldc Rm,SR */
1482 CHECK_PRIVILEGED
1483 tcg_gen_andi_i32(cpu_sr, REG(B11_8), 0x700083f3);
1484 ctx->bstate = BS_STOP;
1485 return;
1486 case 0x4007: /* ldc.l @Rm+,SR */
1487 CHECK_PRIVILEGED
1488 {
1489 TCGv val = tcg_temp_new();
1490 tcg_gen_qemu_ld32s(val, REG(B11_8), ctx->memidx);
1491 tcg_gen_andi_i32(cpu_sr, val, 0x700083f3);
1492 tcg_temp_free(val);
1493 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1494 ctx->bstate = BS_STOP;
1495 }
1496 return;
1497 case 0x0002: /* stc SR,Rn */
1498 CHECK_PRIVILEGED
1499 tcg_gen_mov_i32(REG(B11_8), cpu_sr);
1500 return;
1501 case 0x4003: /* stc SR,@-Rn */
1502 CHECK_PRIVILEGED
1503 {
1504 TCGv addr = tcg_temp_new();
1505 tcg_gen_subi_i32(addr, REG(B11_8), 4);
1506 tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx);
1507 tcg_gen_mov_i32(REG(B11_8), addr);
1508 tcg_temp_free(addr);
1509 }
1510 return;
1511 #define LD(reg,ldnum,ldpnum,prechk) \
1512 case ldnum: \
1513 prechk \
1514 tcg_gen_mov_i32 (cpu_##reg, REG(B11_8)); \
1515 return; \
1516 case ldpnum: \
1517 prechk \
1518 tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx); \
1519 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); \
1520 return;
1521 #define ST(reg,stnum,stpnum,prechk) \
1522 case stnum: \
1523 prechk \
1524 tcg_gen_mov_i32 (REG(B11_8), cpu_##reg); \
1525 return; \
1526 case stpnum: \
1527 prechk \
1528 { \
1529 TCGv addr = tcg_temp_new(); \
1530 tcg_gen_subi_i32(addr, REG(B11_8), 4); \
1531 tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx); \
1532 tcg_gen_mov_i32(REG(B11_8), addr); \
1533 tcg_temp_free(addr); \
1534 } \
1535 return;
1536 #define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \
1537 LD(reg,ldnum,ldpnum,prechk) \
1538 ST(reg,stnum,stpnum,prechk)
1539 LDST(gbr, 0x401e, 0x4017, 0x0012, 0x4013, {})
1540 LDST(vbr, 0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED)
1541 LDST(ssr, 0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED)
1542 LDST(spc, 0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED)
1543 ST(sgr, 0x003a, 0x4032, CHECK_PRIVILEGED)
1544 LD(sgr, 0x403a, 0x4036, CHECK_PRIVILEGED if (!(ctx->features & SH_FEATURE_SH4A)) break;)
1545 LDST(dbr, 0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED)
1546 LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {})
1547 LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {})
1548 LDST(pr, 0x402a, 0x4026, 0x002a, 0x4022, {})
1549 LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {CHECK_FPU_ENABLED})
1550 case 0x406a: /* lds Rm,FPSCR */
1551 CHECK_FPU_ENABLED
1552 gen_helper_ld_fpscr(REG(B11_8));
1553 ctx->bstate = BS_STOP;
1554 return;
1555 case 0x4066: /* lds.l @Rm+,FPSCR */
1556 CHECK_FPU_ENABLED
1557 {
1558 TCGv addr = tcg_temp_new();
1559 tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx);
1560 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1561 gen_helper_ld_fpscr(addr);
1562 tcg_temp_free(addr);
1563 ctx->bstate = BS_STOP;
1564 }
1565 return;
1566 case 0x006a: /* sts FPSCR,Rn */
1567 CHECK_FPU_ENABLED
1568 tcg_gen_andi_i32(REG(B11_8), cpu_fpscr, 0x003fffff);
1569 return;
1570 case 0x4062: /* sts FPSCR,@-Rn */
1571 CHECK_FPU_ENABLED
1572 {
1573 TCGv addr, val;
1574 val = tcg_temp_new();
1575 tcg_gen_andi_i32(val, cpu_fpscr, 0x003fffff);
1576 addr = tcg_temp_new();
1577 tcg_gen_subi_i32(addr, REG(B11_8), 4);
1578 tcg_gen_qemu_st32(val, addr, ctx->memidx);
1579 tcg_gen_mov_i32(REG(B11_8), addr);
1580 tcg_temp_free(addr);
1581 tcg_temp_free(val);
1582 }
1583 return;
1584 case 0x00c3: /* movca.l R0,@Rm */
1585 {
1586 TCGv val = tcg_temp_new();
1587 tcg_gen_qemu_ld32u(val, REG(B11_8), ctx->memidx);
1588 gen_helper_movcal (REG(B11_8), val);
1589 tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
1590 }
1591 ctx->has_movcal = 1;
1592 return;
1593 case 0x40a9:
1594 /* MOVUA.L @Rm,R0 (Rm) -> R0
1595 Load non-boundary-aligned data */
1596 tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);
1597 return;
1598 case 0x40e9:
1599 /* MOVUA.L @Rm+,R0 (Rm) -> R0, Rm + 4 -> Rm
1600 Load non-boundary-aligned data */
1601 tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);
1602 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1603 return;
1604 case 0x0029: /* movt Rn */
1605 tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T);
1606 return;
1607 case 0x0073:
1608 /* MOVCO.L
1609 LDST -> T
1610 If (T == 1) R0 -> (Rn)
1611 0 -> LDST
1612 */
1613 if (ctx->features & SH_FEATURE_SH4A) {
1614 int label = gen_new_label();
1615 gen_clr_t();
1616 tcg_gen_or_i32(cpu_sr, cpu_sr, cpu_ldst);
1617 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label);
1618 tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
1619 gen_set_label(label);
1620 tcg_gen_movi_i32(cpu_ldst, 0);
1621 return;
1622 } else
1623 break;
1624 case 0x0063:
1625 /* MOVLI.L @Rm,R0
1626 1 -> LDST
1627 (Rm) -> R0
1628 When interrupt/exception
1629 occurred 0 -> LDST
1630 */
1631 if (ctx->features & SH_FEATURE_SH4A) {
1632 tcg_gen_movi_i32(cpu_ldst, 0);
1633 tcg_gen_qemu_ld32s(REG(0), REG(B11_8), ctx->memidx);
1634 tcg_gen_movi_i32(cpu_ldst, 1);
1635 return;
1636 } else
1637 break;
1638 case 0x0093: /* ocbi @Rn */
1639 {
1640 gen_helper_ocbi (REG(B11_8));
1641 }
1642 return;
1643 case 0x00a3: /* ocbp @Rn */
1644 {
1645 TCGv dummy = tcg_temp_new();
1646 tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
1647 tcg_temp_free(dummy);
1648 }
1649 return;
1650 case 0x00b3: /* ocbwb @Rn */
1651 {
1652 TCGv dummy = tcg_temp_new();
1653 tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
1654 tcg_temp_free(dummy);
1655 }
1656 return;
1657 case 0x0083: /* pref @Rn */
1658 return;
1659 case 0x00d3: /* prefi @Rn */
1660 if (ctx->features & SH_FEATURE_SH4A)
1661 return;
1662 else
1663 break;
1664 case 0x00e3: /* icbi @Rn */
1665 if (ctx->features & SH_FEATURE_SH4A)
1666 return;
1667 else
1668 break;
1669 case 0x00ab: /* synco */
1670 if (ctx->features & SH_FEATURE_SH4A)
1671 return;
1672 else
1673 break;
1674 case 0x4024: /* rotcl Rn */
1675 {
1676 TCGv tmp = tcg_temp_new();
1677 tcg_gen_mov_i32(tmp, cpu_sr);
1678 gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
1679 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
1680 gen_copy_bit_i32(REG(B11_8), 0, tmp, 0);
1681 tcg_temp_free(tmp);
1682 }
1683 return;
1684 case 0x4025: /* rotcr Rn */
1685 {
1686 TCGv tmp = tcg_temp_new();
1687 tcg_gen_mov_i32(tmp, cpu_sr);
1688 gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1689 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
1690 gen_copy_bit_i32(REG(B11_8), 31, tmp, 0);
1691 tcg_temp_free(tmp);
1692 }
1693 return;
1694 case 0x4004: /* rotl Rn */
1695 gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
1696 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
1697 gen_copy_bit_i32(REG(B11_8), 0, cpu_sr, 0);
1698 return;
1699 case 0x4005: /* rotr Rn */
1700 gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1701 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
1702 gen_copy_bit_i32(REG(B11_8), 31, cpu_sr, 0);
1703 return;
1704 case 0x4000: /* shll Rn */
1705 case 0x4020: /* shal Rn */
1706 gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
1707 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
1708 return;
1709 case 0x4021: /* shar Rn */
1710 gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1711 tcg_gen_sari_i32(REG(B11_8), REG(B11_8), 1);
1712 return;
1713 case 0x4001: /* shlr Rn */
1714 gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1715 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
1716 return;
1717 case 0x4008: /* shll2 Rn */
1718 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 2);
1719 return;
1720 case 0x4018: /* shll8 Rn */
1721 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 8);
1722 return;
1723 case 0x4028: /* shll16 Rn */
1724 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 16);
1725 return;
1726 case 0x4009: /* shlr2 Rn */
1727 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 2);
1728 return;
1729 case 0x4019: /* shlr8 Rn */
1730 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 8);
1731 return;
1732 case 0x4029: /* shlr16 Rn */
1733 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16);
1734 return;
1735 case 0x401b: /* tas.b @Rn */
1736 {
1737 TCGv addr, val;
1738 addr = tcg_temp_local_new();
1739 tcg_gen_mov_i32(addr, REG(B11_8));
1740 val = tcg_temp_local_new();
1741 tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1742 gen_cmp_imm(TCG_COND_EQ, val, 0);
1743 tcg_gen_ori_i32(val, val, 0x80);
1744 tcg_gen_qemu_st8(val, addr, ctx->memidx);
1745 tcg_temp_free(val);
1746 tcg_temp_free(addr);
1747 }
1748 return;
1749 case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
1750 CHECK_FPU_ENABLED
1751 tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fpul);
1752 return;
1753 case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */
1754 CHECK_FPU_ENABLED
1755 tcg_gen_mov_i32(cpu_fpul, cpu_fregs[FREG(B11_8)]);
1756 return;
1757 case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
1758 CHECK_FPU_ENABLED
1759 if (ctx->fpscr & FPSCR_PR) {
1760 TCGv_i64 fp;
1761 if (ctx->opcode & 0x0100)
1762 break; /* illegal instruction */
1763 fp = tcg_temp_new_i64();
1764 gen_helper_float_DT(fp, cpu_fpul);
1765 gen_store_fpr64(fp, DREG(B11_8));
1766 tcg_temp_free_i64(fp);
1767 }
1768 else {
1769 gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_fpul);
1770 }
1771 return;
1772 case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1773 CHECK_FPU_ENABLED
1774 if (ctx->fpscr & FPSCR_PR) {
1775 TCGv_i64 fp;
1776 if (ctx->opcode & 0x0100)
1777 break; /* illegal instruction */
1778 fp = tcg_temp_new_i64();
1779 gen_load_fpr64(fp, DREG(B11_8));
1780 gen_helper_ftrc_DT(cpu_fpul, fp);
1781 tcg_temp_free_i64(fp);
1782 }
1783 else {
1784 gen_helper_ftrc_FT(cpu_fpul, cpu_fregs[FREG(B11_8)]);
1785 }
1786 return;
1787 case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
1788 CHECK_FPU_ENABLED
1789 {
1790 gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
1791 }
1792 return;
1793 case 0xf05d: /* fabs FRn/DRn */
1794 CHECK_FPU_ENABLED
1795 if (ctx->fpscr & FPSCR_PR) {
1796 if (ctx->opcode & 0x0100)
1797 break; /* illegal instruction */
1798 TCGv_i64 fp = tcg_temp_new_i64();
1799 gen_load_fpr64(fp, DREG(B11_8));
1800 gen_helper_fabs_DT(fp, fp);
1801 gen_store_fpr64(fp, DREG(B11_8));
1802 tcg_temp_free_i64(fp);
1803 } else {
1804 gen_helper_fabs_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
1805 }
1806 return;
1807 case 0xf06d: /* fsqrt FRn */
1808 CHECK_FPU_ENABLED
1809 if (ctx->fpscr & FPSCR_PR) {
1810 if (ctx->opcode & 0x0100)
1811 break; /* illegal instruction */
1812 TCGv_i64 fp = tcg_temp_new_i64();
1813 gen_load_fpr64(fp, DREG(B11_8));
1814 gen_helper_fsqrt_DT(fp, fp);
1815 gen_store_fpr64(fp, DREG(B11_8));
1816 tcg_temp_free_i64(fp);
1817 } else {
1818 gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
1819 }
1820 return;
1821 case 0xf07d: /* fsrra FRn */
1822 CHECK_FPU_ENABLED
1823 break;
1824 case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
1825 CHECK_FPU_ENABLED
1826 if (!(ctx->fpscr & FPSCR_PR)) {
1827 tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0);
1828 }
1829 return;
1830 case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
1831 CHECK_FPU_ENABLED
1832 if (!(ctx->fpscr & FPSCR_PR)) {
1833 tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000);
1834 }
1835 return;
1836 case 0xf0ad: /* fcnvsd FPUL,DRn */
1837 CHECK_FPU_ENABLED
1838 {
1839 TCGv_i64 fp = tcg_temp_new_i64();
1840 gen_helper_fcnvsd_FT_DT(fp, cpu_fpul);
1841 gen_store_fpr64(fp, DREG(B11_8));
1842 tcg_temp_free_i64(fp);
1843 }
1844 return;
1845 case 0xf0bd: /* fcnvds DRn,FPUL */
1846 CHECK_FPU_ENABLED
1847 {
1848 TCGv_i64 fp = tcg_temp_new_i64();
1849 gen_load_fpr64(fp, DREG(B11_8));
1850 gen_helper_fcnvds_DT_FT(cpu_fpul, fp);
1851 tcg_temp_free_i64(fp);
1852 }
1853 return;
1854 case 0xf0ed: /* fipr FVm,FVn */
1855 CHECK_FPU_ENABLED
1856 if ((ctx->fpscr & FPSCR_PR) == 0) {
1857 TCGv m, n;
1858 m = tcg_const_i32((ctx->opcode >> 16) & 3);
1859 n = tcg_const_i32((ctx->opcode >> 18) & 3);
1860 gen_helper_fipr(m, n);
1861 tcg_temp_free(m);
1862 tcg_temp_free(n);
1863 return;
1864 }
1865 break;
1866 case 0xf0fd: /* ftrv XMTRX,FVn */
1867 CHECK_FPU_ENABLED
1868 if ((ctx->opcode & 0x0300) == 0x0100 &&
1869 (ctx->fpscr & FPSCR_PR) == 0) {
1870 TCGv n;
1871 n = tcg_const_i32((ctx->opcode >> 18) & 3);
1872 gen_helper_ftrv(n);
1873 tcg_temp_free(n);
1874 return;
1875 }
1876 break;
1877 }
1878 #if 0
1879 fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
1880 ctx->opcode, ctx->pc);
1881 fflush(stderr);
1882 #endif
1883 if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
1884 gen_helper_raise_slot_illegal_instruction();
1885 } else {
1886 gen_helper_raise_illegal_instruction();
1887 }
1888 ctx->bstate = BS_EXCP;
1889 }
1890
1891 static void decode_opc(DisasContext * ctx)
1892 {
1893 uint32_t old_flags = ctx->flags;
1894
1895 _decode_opc(ctx);
1896
1897 if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
1898 if (ctx->flags & DELAY_SLOT_CLEARME) {
1899 gen_store_flags(0);
1900 } else {
1901 /* go out of the delay slot */
1902 uint32_t new_flags = ctx->flags;
1903 new_flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
1904 gen_store_flags(new_flags);
1905 }
1906 ctx->flags = 0;
1907 ctx->bstate = BS_BRANCH;
1908 if (old_flags & DELAY_SLOT_CONDITIONAL) {
1909 gen_delayed_conditional_jump(ctx);
1910 } else if (old_flags & DELAY_SLOT) {
1911 gen_jump(ctx);
1912 }
1913
1914 }
1915
1916 /* go into a delay slot */
1917 if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL))
1918 gen_store_flags(ctx->flags);
1919 }
1920
1921 static inline void
1922 gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
1923 int search_pc)
1924 {
1925 DisasContext ctx;
1926 target_ulong pc_start;
1927 static uint16_t *gen_opc_end;
1928 CPUBreakpoint *bp;
1929 int i, ii;
1930 int num_insns;
1931 int max_insns;
1932
1933 pc_start = tb->pc;
1934 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1935 ctx.pc = pc_start;
1936 ctx.flags = (uint32_t)tb->flags;
1937 ctx.bstate = BS_NONE;
1938 ctx.sr = env->sr;
1939 ctx.fpscr = env->fpscr;
1940 ctx.memidx = (env->sr & SR_MD) == 0 ? 1 : 0;
1941 /* We don't know if the delayed pc came from a dynamic or static branch,
1942 so assume it is a dynamic branch. */
1943 ctx.delayed_pc = -1; /* use delayed pc from env pointer */
1944 ctx.tb = tb;
1945 ctx.singlestep_enabled = env->singlestep_enabled;
1946 ctx.features = env->features;
1947 ctx.has_movcal = (tb->flags & TB_FLAG_PENDING_MOVCA);
1948
1949 ii = -1;
1950 num_insns = 0;
1951 max_insns = tb->cflags & CF_COUNT_MASK;
1952 if (max_insns == 0)
1953 max_insns = CF_COUNT_MASK;
1954 gen_icount_start();
1955 while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
1956 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1957 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1958 if (ctx.pc == bp->pc) {
1959 /* We have hit a breakpoint - make sure PC is up-to-date */
1960 tcg_gen_movi_i32(cpu_pc, ctx.pc);
1961 gen_helper_debug();
1962 ctx.bstate = BS_EXCP;
1963 break;
1964 }
1965 }
1966 }
1967 if (search_pc) {
1968 i = gen_opc_ptr - gen_opc_buf;
1969 if (ii < i) {
1970 ii++;
1971 while (ii < i)
1972 gen_opc_instr_start[ii++] = 0;
1973 }
1974 gen_opc_pc[ii] = ctx.pc;
1975 gen_opc_hflags[ii] = ctx.flags;
1976 gen_opc_instr_start[ii] = 1;
1977 gen_opc_icount[ii] = num_insns;
1978 }
1979 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1980 gen_io_start();
1981 #if 0
1982 fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc);
1983 fflush(stderr);
1984 #endif
1985 ctx.opcode = lduw_code(ctx.pc);
1986 decode_opc(&ctx);
1987 num_insns++;
1988 ctx.pc += 2;
1989 if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
1990 break;
1991 if (env->singlestep_enabled)
1992 break;
1993 if (num_insns >= max_insns)
1994 break;
1995 if (singlestep)
1996 break;
1997 }
1998 if (tb->cflags & CF_LAST_IO)
1999 gen_io_end();
2000 if (env->singlestep_enabled) {
2001 tcg_gen_movi_i32(cpu_pc, ctx.pc);
2002 gen_helper_debug();
2003 } else {
2004 switch (ctx.bstate) {
2005 case BS_STOP:
2006 /* gen_op_interrupt_restart(); */
2007 /* fall through */
2008 case BS_NONE:
2009 if (ctx.flags) {
2010 gen_store_flags(ctx.flags | DELAY_SLOT_CLEARME);
2011 }
2012 gen_goto_tb(&ctx, 0, ctx.pc);
2013 break;
2014 case BS_EXCP:
2015 /* gen_op_interrupt_restart(); */
2016 tcg_gen_exit_tb(0);
2017 break;
2018 case BS_BRANCH:
2019 default:
2020 break;
2021 }
2022 }
2023
2024 gen_icount_end(tb, num_insns);
2025 *gen_opc_ptr = INDEX_op_end;
2026 if (search_pc) {
2027 i = gen_opc_ptr - gen_opc_buf;
2028 ii++;
2029 while (ii <= i)
2030 gen_opc_instr_start[ii++] = 0;
2031 } else {
2032 tb->size = ctx.pc - pc_start;
2033 tb->icount = num_insns;
2034 }
2035
2036 #ifdef DEBUG_DISAS
2037 #ifdef SH4_DEBUG_DISAS
2038 qemu_log_mask(CPU_LOG_TB_IN_ASM, "\n");
2039 #endif
2040 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
2041 qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */
2042 log_target_disas(pc_start, ctx.pc - pc_start, 0);
2043 qemu_log("\n");
2044 }
2045 #endif
2046 }
2047
2048 void gen_intermediate_code(CPUState * env, struct TranslationBlock *tb)
2049 {
2050 gen_intermediate_code_internal(env, tb, 0);
2051 }
2052
2053 void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb)
2054 {
2055 gen_intermediate_code_internal(env, tb, 1);
2056 }
2057
2058 void gen_pc_load(CPUState *env, TranslationBlock *tb,
2059 unsigned long searched_pc, int pc_pos, void *puc)
2060 {
2061 env->pc = gen_opc_pc[pc_pos];
2062 env->flags = gen_opc_hflags[pc_pos];
2063 }
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