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git.proxmox.com Git - mirror_qemu.git/blob - target-sparc/cpu.h
6 #if !defined(TARGET_SPARC64)
7 #define TARGET_LONG_BITS 32
8 #define TARGET_FPREGS 32
10 #define TARGET_LONG_BITS 64
11 #define TARGET_FPREGS 64
13 #define TARGET_FPREG_T float
17 #include "softfloat.h"
19 #define TARGET_HAS_ICE 1
21 /*#define EXCP_INTERRUPT 0x100*/
23 /* trap definitions */
24 #ifndef TARGET_SPARC64
25 #define TT_TFAULT 0x01
26 #define TT_ILL_INSN 0x02
27 #define TT_PRIV_INSN 0x03
28 #define TT_NFPU_INSN 0x04
29 #define TT_WIN_OVF 0x05
30 #define TT_WIN_UNF 0x06
31 #define TT_FP_EXCP 0x08
32 #define TT_DFAULT 0x09
33 #define TT_EXTINT 0x10
34 #define TT_DIV_ZERO 0x2a
37 #define TT_TFAULT 0x08
38 #define TT_ILL_INSN 0x10
39 #define TT_PRIV_INSN 0x11
40 #define TT_NFPU_INSN 0x20
41 #define TT_FP_EXCP 0x21
42 #define TT_CLRWIN 0x24
43 #define TT_DIV_ZERO 0x28
44 #define TT_DFAULT 0x30
45 #define TT_EXTINT 0x40
48 #define TT_WOTHER 0x10
52 #define PSR_NEG (1<<23)
53 #define PSR_ZERO (1<<22)
54 #define PSR_OVF (1<<21)
55 #define PSR_CARRY (1<<20)
56 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
57 #define PSR_EF (1<<12)
64 /* Trap base register */
65 #define TBR_BASE_MASK 0xfffff000
67 #if defined(TARGET_SPARC64)
70 #define PS_PRIV (1<<2)
75 #define FSR_RD1 (1<<31)
76 #define FSR_RD0 (1<<30)
77 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
78 #define FSR_RD_NEAREST 0
79 #define FSR_RD_ZERO FSR_RD0
80 #define FSR_RD_POS FSR_RD1
81 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
83 #define FSR_NVM (1<<27)
84 #define FSR_OFM (1<<26)
85 #define FSR_UFM (1<<25)
86 #define FSR_DZM (1<<24)
87 #define FSR_NXM (1<<23)
88 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
90 #define FSR_NVA (1<<9)
91 #define FSR_OFA (1<<8)
92 #define FSR_UFA (1<<7)
93 #define FSR_DZA (1<<6)
94 #define FSR_NXA (1<<5)
95 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
97 #define FSR_NVC (1<<4)
98 #define FSR_OFC (1<<3)
99 #define FSR_UFC (1<<2)
100 #define FSR_DZC (1<<1)
101 #define FSR_NXC (1<<0)
102 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
104 #define FSR_FTT2 (1<<16)
105 #define FSR_FTT1 (1<<15)
106 #define FSR_FTT0 (1<<14)
107 #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
108 #define FSR_FTT_IEEE_EXCP (1 << 14)
109 #define FSR_FTT_UNIMPFPOP (3 << 14)
110 #define FSR_FTT_INVAL_FPR (6 << 14)
112 #define FSR_FCC1 (1<<11)
113 #define FSR_FCC0 (1<<10)
117 #define MMU_NF (1<<1)
119 #define PTE_ENTRYTYPE_MASK 3
120 #define PTE_ACCESS_MASK 0x1c
121 #define PTE_ACCESS_SHIFT 2
122 #define PTE_PPN_SHIFT 7
123 #define PTE_ADDR_MASK 0xffffff00
125 #define PG_ACCESSED_BIT 5
126 #define PG_MODIFIED_BIT 6
127 #define PG_CACHE_BIT 7
129 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
130 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
131 #define PG_CACHE_MASK (1 << PG_CACHE_BIT)
133 /* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
136 typedef struct CPUSPARCState
{
137 target_ulong gregs
[8]; /* general registers */
138 target_ulong
*regwptr
; /* pointer to current register window */
139 TARGET_FPREG_T fpr
[TARGET_FPREGS
]; /* floating point registers */
140 target_ulong pc
; /* program counter */
141 target_ulong npc
; /* next program counter */
142 target_ulong y
; /* multiply/divide register */
143 uint32_t psr
; /* processor state register */
144 target_ulong fsr
; /* FPU state register */
145 uint32_t cwp
; /* index of current register window (extracted
147 uint32_t wim
; /* window invalid mask */
148 target_ulong tbr
; /* trap base register */
149 int psrs
; /* supervisor mode (extracted from PSR) */
150 int psrps
; /* previous supervisor mode */
151 int psret
; /* enable traps */
152 uint32_t psrpil
; /* interrupt level */
153 int psref
; /* enable fpu */
158 int interrupt_request
;
159 struct TranslationBlock
*current_tb
;
161 /* NOTE: we allow 8 more registers to handle wrapping */
162 target_ulong regbase
[NWINDOWS
* 16 + 8];
164 /* in order to avoid passing too many arguments to the memory
165 write helpers, we store some rarely used information in the CPU
167 unsigned long mem_write_pc
; /* host pc at which the memory was
169 unsigned long mem_write_vaddr
; /* target virtual addr at which the
170 memory was written */
171 /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
172 CPUTLBEntry tlb_read
[2][CPU_TLB_SIZE
];
173 CPUTLBEntry tlb_write
[2][CPU_TLB_SIZE
];
175 #if defined(TARGET_SPARC64)
179 uint64_t immuregs
[16];
180 uint64_t dmmuregs
[16];
181 uint64_t itlb_tag
[64];
182 uint64_t itlb_tte
[64];
183 uint64_t dtlb_tag
[64];
184 uint64_t dtlb_tte
[64];
186 uint32_t mmuregs
[16];
188 /* temporary float registers */
191 float_status fp_status
;
192 #if defined(TARGET_SPARC64)
196 uint64_t tnpc
[MAXTL
];
197 uint64_t tstate
[MAXTL
];
199 uint32_t xcc
; /* Extended integer condition codes */
203 uint32_t cansave
, canrestore
, otherwin
, wstate
, cleanwin
;
204 target_ulong agregs
[8]; /* alternate general registers */
205 target_ulong igregs
[8]; /* interrupt general registers */
206 target_ulong mgregs
[8]; /* mmu general registers */
210 #if !defined(TARGET_SPARC64) && !defined(reg_T2)
214 /* ice debug support */
215 target_ulong breakpoints
[MAX_BREAKPOINTS
];
217 int singlestep_enabled
; /* XXX: should use CPU single step mode instead */
220 #if defined(TARGET_SPARC64)
221 #define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
222 #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
223 env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \
225 #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
226 #define PUT_FSR64(env, val) do { uint64_t _tmp = val; \
227 env->fsr = _tmp & 0x3fcfc1c3ffULL; \
229 // Manuf 0x17, version 0x11, mask 0 (UltraSparc-II)
230 #define GET_VER(env) ((0x17ULL << 48) | (0x11ULL << 32) | \
231 (0 << 24) | (MAXTL << 8) | (NWINDOWS - 1))
233 #define GET_FSR32(env) (env->fsr)
234 #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
235 env->fsr = _tmp & 0xcfc1ffff; \
239 CPUSPARCState
*cpu_sparc_init(void);
240 int cpu_sparc_exec(CPUSPARCState
*s
);
241 int cpu_sparc_close(CPUSPARCState
*s
);
242 void cpu_get_fp64(uint64_t *pmant
, uint16_t *pexp
, double f
);
243 double cpu_put_fp64(uint64_t mant
, uint16_t exp
);
245 /* Fake impl 0, version 4 */
246 #define GET_PSR(env) ((0 << 28) | (4 << 24) | (env->psr & PSR_ICC) | \
247 (env->psref? PSR_EF : 0) | \
248 (env->psrpil << 8) | \
249 (env->psrs? PSR_S : 0) | \
250 (env->psrps? PSR_PS : 0) | \
251 (env->psret? PSR_ET : 0) | env->cwp)
253 #ifndef NO_CPU_IO_DEFS
254 void cpu_set_cwp(CPUSPARCState
*env1
, int new_cwp
);
257 #define PUT_PSR(env, val) do { int _tmp = val; \
258 env->psr = _tmp & PSR_ICC; \
259 env->psref = (_tmp & PSR_EF)? 1 : 0; \
260 env->psrpil = (_tmp & PSR_PIL) >> 8; \
261 env->psrs = (_tmp & PSR_S)? 1 : 0; \
262 env->psrps = (_tmp & PSR_PS)? 1 : 0; \
263 env->psret = (_tmp & PSR_ET)? 1 : 0; \
264 cpu_set_cwp(env, _tmp & PSR_CWP & (NWINDOWS - 1)); \
267 #ifdef TARGET_SPARC64
268 #define GET_CCR(env) ((env->xcc << 4) | (env->psr & PSR_ICC))
269 #define PUT_CCR(env, val) do { int _tmp = val; \
270 env->xcc = _tmp >> 4; \
271 env->psr = (_tmp & 0xf) << 20; \
276 int cpu_sparc_signal_handler(int hostsignum
, struct siginfo
*info
, void *puc
);
278 #define TARGET_PAGE_BITS 12 /* 4k */