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git.proxmox.com Git - qemu.git/blob - target-sparc/fop_helper.c
f6348c2e3b44a568e39c68be2cfb0a8784ba128d
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #define QT0 (env->qt0)
24 #define QT1 (env->qt1)
26 #define F_HELPER(name, p) void helper_f##name##p(CPUState *env)
28 #define F_BINOP(name) \
29 float32 helper_f ## name ## s (CPUState * env, float32 src1,\
32 return float32_ ## name (src1, src2, &env->fp_status); \
34 float64 helper_f ## name ## d (CPUState * env, float64 src1,\
37 return float64_ ## name (src1, src2, &env->fp_status); \
41 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
50 float64
helper_fsmuld(CPUState
*env
, float32 src1
, float32 src2
)
52 return float64_mul(float32_to_float64(src1
, &env
->fp_status
),
53 float32_to_float64(src2
, &env
->fp_status
),
57 void helper_fdmulq(CPUState
*env
, float64 src1
, float64 src2
)
59 QT0
= float128_mul(float64_to_float128(src1
, &env
->fp_status
),
60 float64_to_float128(src2
, &env
->fp_status
),
64 float32
helper_fnegs(float32 src
)
66 return float32_chs(src
);
70 float64
helper_fnegd(float64 src
)
72 return float64_chs(src
);
77 QT0
= float128_chs(QT1
);
81 /* Integer to float conversion. */
82 float32
helper_fitos(CPUState
*env
, int32_t src
)
84 return int32_to_float32(src
, &env
->fp_status
);
87 float64
helper_fitod(CPUState
*env
, int32_t src
)
89 return int32_to_float64(src
, &env
->fp_status
);
92 void helper_fitoq(CPUState
*env
, int32_t src
)
94 QT0
= int32_to_float128(src
, &env
->fp_status
);
98 float32
helper_fxtos(CPUState
*env
, int64_t src
)
100 return int64_to_float32(src
, &env
->fp_status
);
103 float64
helper_fxtod(CPUState
*env
, int64_t src
)
105 return int64_to_float64(src
, &env
->fp_status
);
108 void helper_fxtoq(CPUState
*env
, int64_t src
)
110 QT0
= int64_to_float128(src
, &env
->fp_status
);
115 /* floating point conversion */
116 float32
helper_fdtos(CPUState
*env
, float64 src
)
118 return float64_to_float32(src
, &env
->fp_status
);
121 float64
helper_fstod(CPUState
*env
, float32 src
)
123 return float32_to_float64(src
, &env
->fp_status
);
126 float32
helper_fqtos(CPUState
*env
)
128 return float128_to_float32(QT1
, &env
->fp_status
);
131 void helper_fstoq(CPUState
*env
, float32 src
)
133 QT0
= float32_to_float128(src
, &env
->fp_status
);
136 float64
helper_fqtod(CPUState
*env
)
138 return float128_to_float64(QT1
, &env
->fp_status
);
141 void helper_fdtoq(CPUState
*env
, float64 src
)
143 QT0
= float64_to_float128(src
, &env
->fp_status
);
146 /* Float to integer conversion. */
147 int32_t helper_fstoi(CPUState
*env
, float32 src
)
149 return float32_to_int32_round_to_zero(src
, &env
->fp_status
);
152 int32_t helper_fdtoi(CPUState
*env
, float64 src
)
154 return float64_to_int32_round_to_zero(src
, &env
->fp_status
);
157 int32_t helper_fqtoi(CPUState
*env
)
159 return float128_to_int32_round_to_zero(QT1
, &env
->fp_status
);
162 #ifdef TARGET_SPARC64
163 int64_t helper_fstox(CPUState
*env
, float32 src
)
165 return float32_to_int64_round_to_zero(src
, &env
->fp_status
);
168 int64_t helper_fdtox(CPUState
*env
, float64 src
)
170 return float64_to_int64_round_to_zero(src
, &env
->fp_status
);
173 int64_t helper_fqtox(CPUState
*env
)
175 return float128_to_int64_round_to_zero(QT1
, &env
->fp_status
);
179 float32
helper_fabss(float32 src
)
181 return float32_abs(src
);
184 #ifdef TARGET_SPARC64
185 float64
helper_fabsd(CPUState
*env
, float64 src
)
187 return float64_abs(src
);
190 void helper_fabsq(CPUState
*env
)
192 QT0
= float128_abs(QT1
);
196 float32
helper_fsqrts(CPUState
*env
, float32 src
)
198 return float32_sqrt(src
, &env
->fp_status
);
201 float64
helper_fsqrtd(CPUState
*env
, float64 src
)
203 return float64_sqrt(src
, &env
->fp_status
);
206 void helper_fsqrtq(CPUState
*env
)
208 QT0
= float128_sqrt(QT1
, &env
->fp_status
);
211 #define GEN_FCMP(name, size, reg1, reg2, FS, E) \
212 void glue(helper_, name) (CPUState *env) \
214 env->fsr &= FSR_FTT_NMASK; \
215 if (E && (glue(size, _is_any_nan)(reg1) || \
216 glue(size, _is_any_nan)(reg2)) && \
217 (env->fsr & FSR_NVM)) { \
218 env->fsr |= FSR_NVC; \
219 env->fsr |= FSR_FTT_IEEE_EXCP; \
220 helper_raise_exception(env, TT_FP_EXCP); \
222 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
223 case float_relation_unordered: \
224 if ((env->fsr & FSR_NVM)) { \
225 env->fsr |= FSR_NVC; \
226 env->fsr |= FSR_FTT_IEEE_EXCP; \
227 helper_raise_exception(env, TT_FP_EXCP); \
229 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
230 env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
231 env->fsr |= FSR_NVA; \
234 case float_relation_less: \
235 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
236 env->fsr |= FSR_FCC0 << FS; \
238 case float_relation_greater: \
239 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
240 env->fsr |= FSR_FCC1 << FS; \
243 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
247 #define GEN_FCMP_T(name, size, FS, E) \
248 void glue(helper_, name)(CPUState *env, size src1, size src2) \
250 env->fsr &= FSR_FTT_NMASK; \
251 if (E && (glue(size, _is_any_nan)(src1) || \
252 glue(size, _is_any_nan)(src2)) && \
253 (env->fsr & FSR_NVM)) { \
254 env->fsr |= FSR_NVC; \
255 env->fsr |= FSR_FTT_IEEE_EXCP; \
256 helper_raise_exception(env, TT_FP_EXCP); \
258 switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
259 case float_relation_unordered: \
260 if ((env->fsr & FSR_NVM)) { \
261 env->fsr |= FSR_NVC; \
262 env->fsr |= FSR_FTT_IEEE_EXCP; \
263 helper_raise_exception(env, TT_FP_EXCP); \
265 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
266 env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
267 env->fsr |= FSR_NVA; \
270 case float_relation_less: \
271 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
272 env->fsr |= FSR_FCC0 << FS; \
274 case float_relation_greater: \
275 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
276 env->fsr |= FSR_FCC1 << FS; \
279 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
284 GEN_FCMP_T(fcmps
, float32
, 0, 0);
285 GEN_FCMP_T(fcmpd
, float64
, 0, 0);
287 GEN_FCMP_T(fcmpes
, float32
, 0, 1);
288 GEN_FCMP_T(fcmped
, float64
, 0, 1);
290 GEN_FCMP(fcmpq
, float128
, QT0
, QT1
, 0, 0);
291 GEN_FCMP(fcmpeq
, float128
, QT0
, QT1
, 0, 1);
293 #ifdef TARGET_SPARC64
294 GEN_FCMP_T(fcmps_fcc1
, float32
, 22, 0);
295 GEN_FCMP_T(fcmpd_fcc1
, float64
, 22, 0);
296 GEN_FCMP(fcmpq_fcc1
, float128
, QT0
, QT1
, 22, 0);
298 GEN_FCMP_T(fcmps_fcc2
, float32
, 24, 0);
299 GEN_FCMP_T(fcmpd_fcc2
, float64
, 24, 0);
300 GEN_FCMP(fcmpq_fcc2
, float128
, QT0
, QT1
, 24, 0);
302 GEN_FCMP_T(fcmps_fcc3
, float32
, 26, 0);
303 GEN_FCMP_T(fcmpd_fcc3
, float64
, 26, 0);
304 GEN_FCMP(fcmpq_fcc3
, float128
, QT0
, QT1
, 26, 0);
306 GEN_FCMP_T(fcmpes_fcc1
, float32
, 22, 1);
307 GEN_FCMP_T(fcmped_fcc1
, float64
, 22, 1);
308 GEN_FCMP(fcmpeq_fcc1
, float128
, QT0
, QT1
, 22, 1);
310 GEN_FCMP_T(fcmpes_fcc2
, float32
, 24, 1);
311 GEN_FCMP_T(fcmped_fcc2
, float64
, 24, 1);
312 GEN_FCMP(fcmpeq_fcc2
, float128
, QT0
, QT1
, 24, 1);
314 GEN_FCMP_T(fcmpes_fcc3
, float32
, 26, 1);
315 GEN_FCMP_T(fcmped_fcc3
, float64
, 26, 1);
316 GEN_FCMP(fcmpeq_fcc3
, float128
, QT0
, QT1
, 26, 1);
321 void helper_check_ieee_exceptions(CPUState
*env
)
325 status
= get_float_exception_flags(&env
->fp_status
);
327 /* Copy IEEE 754 flags into FSR */
328 if (status
& float_flag_invalid
) {
331 if (status
& float_flag_overflow
) {
334 if (status
& float_flag_underflow
) {
337 if (status
& float_flag_divbyzero
) {
340 if (status
& float_flag_inexact
) {
344 if ((env
->fsr
& FSR_CEXC_MASK
) & ((env
->fsr
& FSR_TEM_MASK
) >> 23)) {
345 /* Unmasked exception, generate a trap */
346 env
->fsr
|= FSR_FTT_IEEE_EXCP
;
347 helper_raise_exception(env
, TT_FP_EXCP
);
349 /* Accumulate exceptions */
350 env
->fsr
|= (env
->fsr
& FSR_CEXC_MASK
) << 5;
355 void helper_clear_float_exceptions(CPUState
*env
)
357 set_float_exception_flags(0, &env
->fp_status
);
360 static inline void set_fsr(CPUState
*env
)
364 switch (env
->fsr
& FSR_RD_MASK
) {
366 rnd_mode
= float_round_nearest_even
;
370 rnd_mode
= float_round_to_zero
;
373 rnd_mode
= float_round_up
;
376 rnd_mode
= float_round_down
;
379 set_float_rounding_mode(rnd_mode
, &env
->fp_status
);
382 void helper_ldfsr(CPUState
*env
, uint32_t new_fsr
)
384 env
->fsr
= (new_fsr
& FSR_LDFSR_MASK
) | (env
->fsr
& FSR_LDFSR_OLDMASK
);
388 #ifdef TARGET_SPARC64
389 void helper_ldxfsr(CPUState
*env
, uint64_t new_fsr
)
391 env
->fsr
= (new_fsr
& FSR_LDXFSR_MASK
) | (env
->fsr
& FSR_LDXFSR_OLDMASK
);