]>
git.proxmox.com Git - mirror_qemu.git/blob - target-sparc/fop_helper.c
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #define DT0 (env->dt0)
24 #define DT1 (env->dt1)
25 #define QT0 (env->qt0)
26 #define QT1 (env->qt1)
28 #define F_HELPER(name, p) void helper_f##name##p(CPUState *env)
30 #define F_BINOP(name) \
31 float32 helper_f ## name ## s (CPUState * env, float32 src1,\
34 return float32_ ## name (src1, src2, &env->fp_status); \
38 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
42 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
51 void helper_fsmuld(CPUState
*env
, float32 src1
, float32 src2
)
53 DT0
= float64_mul(float32_to_float64(src1
, &env
->fp_status
),
54 float32_to_float64(src2
, &env
->fp_status
),
58 void helper_fdmulq(CPUState
*env
)
60 QT0
= float128_mul(float64_to_float128(DT0
, &env
->fp_status
),
61 float64_to_float128(DT1
, &env
->fp_status
),
65 float32
helper_fnegs(float32 src
)
67 return float32_chs(src
);
73 DT0
= float64_chs(DT1
);
78 QT0
= float128_chs(QT1
);
82 /* Integer to float conversion. */
83 float32
helper_fitos(CPUState
*env
, int32_t src
)
85 return int32_to_float32(src
, &env
->fp_status
);
88 void helper_fitod(CPUState
*env
, int32_t src
)
90 DT0
= int32_to_float64(src
, &env
->fp_status
);
93 void helper_fitoq(CPUState
*env
, int32_t src
)
95 QT0
= int32_to_float128(src
, &env
->fp_status
);
99 float32
helper_fxtos(CPUState
*env
)
101 return int64_to_float32(*((int64_t *)&DT1
), &env
->fp_status
);
106 DT0
= int64_to_float64(*((int64_t *)&DT1
), &env
->fp_status
);
111 QT0
= int64_to_float128(*((int64_t *)&DT1
), &env
->fp_status
);
116 /* floating point conversion */
117 float32
helper_fdtos(CPUState
*env
)
119 return float64_to_float32(DT1
, &env
->fp_status
);
122 void helper_fstod(CPUState
*env
, float32 src
)
124 DT0
= float32_to_float64(src
, &env
->fp_status
);
127 float32
helper_fqtos(CPUState
*env
)
129 return float128_to_float32(QT1
, &env
->fp_status
);
132 void helper_fstoq(CPUState
*env
, float32 src
)
134 QT0
= float32_to_float128(src
, &env
->fp_status
);
137 void helper_fqtod(CPUState
*env
)
139 DT0
= float128_to_float64(QT1
, &env
->fp_status
);
142 void helper_fdtoq(CPUState
*env
)
144 QT0
= float64_to_float128(DT1
, &env
->fp_status
);
147 /* Float to integer conversion. */
148 int32_t helper_fstoi(CPUState
*env
, float32 src
)
150 return float32_to_int32_round_to_zero(src
, &env
->fp_status
);
153 int32_t helper_fdtoi(CPUState
*env
)
155 return float64_to_int32_round_to_zero(DT1
, &env
->fp_status
);
158 int32_t helper_fqtoi(CPUState
*env
)
160 return float128_to_int32_round_to_zero(QT1
, &env
->fp_status
);
163 #ifdef TARGET_SPARC64
164 void helper_fstox(CPUState
*env
, float32 src
)
166 *((int64_t *)&DT0
) = float32_to_int64_round_to_zero(src
, &env
->fp_status
);
169 void helper_fdtox(CPUState
*env
)
171 *((int64_t *)&DT0
) = float64_to_int64_round_to_zero(DT1
, &env
->fp_status
);
174 void helper_fqtox(CPUState
*env
)
176 *((int64_t *)&DT0
) = float128_to_int64_round_to_zero(QT1
, &env
->fp_status
);
180 float32
helper_fabss(float32 src
)
182 return float32_abs(src
);
185 #ifdef TARGET_SPARC64
186 void helper_fabsd(CPUState
*env
)
188 DT0
= float64_abs(DT1
);
191 void helper_fabsq(CPUState
*env
)
193 QT0
= float128_abs(QT1
);
197 float32
helper_fsqrts(CPUState
*env
, float32 src
)
199 return float32_sqrt(src
, &env
->fp_status
);
202 void helper_fsqrtd(CPUState
*env
)
204 DT0
= float64_sqrt(DT1
, &env
->fp_status
);
207 void helper_fsqrtq(CPUState
*env
)
209 QT0
= float128_sqrt(QT1
, &env
->fp_status
);
212 #define GEN_FCMP(name, size, reg1, reg2, FS, E) \
213 void glue(helper_, name) (CPUState *env) \
215 env->fsr &= FSR_FTT_NMASK; \
216 if (E && (glue(size, _is_any_nan)(reg1) || \
217 glue(size, _is_any_nan)(reg2)) && \
218 (env->fsr & FSR_NVM)) { \
219 env->fsr |= FSR_NVC; \
220 env->fsr |= FSR_FTT_IEEE_EXCP; \
221 helper_raise_exception(env, TT_FP_EXCP); \
223 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
224 case float_relation_unordered: \
225 if ((env->fsr & FSR_NVM)) { \
226 env->fsr |= FSR_NVC; \
227 env->fsr |= FSR_FTT_IEEE_EXCP; \
228 helper_raise_exception(env, TT_FP_EXCP); \
230 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
231 env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
232 env->fsr |= FSR_NVA; \
235 case float_relation_less: \
236 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
237 env->fsr |= FSR_FCC0 << FS; \
239 case float_relation_greater: \
240 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
241 env->fsr |= FSR_FCC1 << FS; \
244 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
248 #define GEN_FCMPS(name, size, FS, E) \
249 void glue(helper_, name)(CPUState *env, float32 src1, float32 src2) \
251 env->fsr &= FSR_FTT_NMASK; \
252 if (E && (glue(size, _is_any_nan)(src1) || \
253 glue(size, _is_any_nan)(src2)) && \
254 (env->fsr & FSR_NVM)) { \
255 env->fsr |= FSR_NVC; \
256 env->fsr |= FSR_FTT_IEEE_EXCP; \
257 helper_raise_exception(env, TT_FP_EXCP); \
259 switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
260 case float_relation_unordered: \
261 if ((env->fsr & FSR_NVM)) { \
262 env->fsr |= FSR_NVC; \
263 env->fsr |= FSR_FTT_IEEE_EXCP; \
264 helper_raise_exception(env, TT_FP_EXCP); \
266 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
267 env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
268 env->fsr |= FSR_NVA; \
271 case float_relation_less: \
272 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
273 env->fsr |= FSR_FCC0 << FS; \
275 case float_relation_greater: \
276 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
277 env->fsr |= FSR_FCC1 << FS; \
280 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
285 GEN_FCMPS(fcmps
, float32
, 0, 0);
286 GEN_FCMP(fcmpd
, float64
, DT0
, DT1
, 0, 0);
288 GEN_FCMPS(fcmpes
, float32
, 0, 1);
289 GEN_FCMP(fcmped
, float64
, DT0
, DT1
, 0, 1);
291 GEN_FCMP(fcmpq
, float128
, QT0
, QT1
, 0, 0);
292 GEN_FCMP(fcmpeq
, float128
, QT0
, QT1
, 0, 1);
294 #ifdef TARGET_SPARC64
295 GEN_FCMPS(fcmps_fcc1
, float32
, 22, 0);
296 GEN_FCMP(fcmpd_fcc1
, float64
, DT0
, DT1
, 22, 0);
297 GEN_FCMP(fcmpq_fcc1
, float128
, QT0
, QT1
, 22, 0);
299 GEN_FCMPS(fcmps_fcc2
, float32
, 24, 0);
300 GEN_FCMP(fcmpd_fcc2
, float64
, DT0
, DT1
, 24, 0);
301 GEN_FCMP(fcmpq_fcc2
, float128
, QT0
, QT1
, 24, 0);
303 GEN_FCMPS(fcmps_fcc3
, float32
, 26, 0);
304 GEN_FCMP(fcmpd_fcc3
, float64
, DT0
, DT1
, 26, 0);
305 GEN_FCMP(fcmpq_fcc3
, float128
, QT0
, QT1
, 26, 0);
307 GEN_FCMPS(fcmpes_fcc1
, float32
, 22, 1);
308 GEN_FCMP(fcmped_fcc1
, float64
, DT0
, DT1
, 22, 1);
309 GEN_FCMP(fcmpeq_fcc1
, float128
, QT0
, QT1
, 22, 1);
311 GEN_FCMPS(fcmpes_fcc2
, float32
, 24, 1);
312 GEN_FCMP(fcmped_fcc2
, float64
, DT0
, DT1
, 24, 1);
313 GEN_FCMP(fcmpeq_fcc2
, float128
, QT0
, QT1
, 24, 1);
315 GEN_FCMPS(fcmpes_fcc3
, float32
, 26, 1);
316 GEN_FCMP(fcmped_fcc3
, float64
, DT0
, DT1
, 26, 1);
317 GEN_FCMP(fcmpeq_fcc3
, float128
, QT0
, QT1
, 26, 1);
321 void helper_check_ieee_exceptions(CPUState
*env
)
325 status
= get_float_exception_flags(&env
->fp_status
);
327 /* Copy IEEE 754 flags into FSR */
328 if (status
& float_flag_invalid
) {
331 if (status
& float_flag_overflow
) {
334 if (status
& float_flag_underflow
) {
337 if (status
& float_flag_divbyzero
) {
340 if (status
& float_flag_inexact
) {
344 if ((env
->fsr
& FSR_CEXC_MASK
) & ((env
->fsr
& FSR_TEM_MASK
) >> 23)) {
345 /* Unmasked exception, generate a trap */
346 env
->fsr
|= FSR_FTT_IEEE_EXCP
;
347 helper_raise_exception(env
, TT_FP_EXCP
);
349 /* Accumulate exceptions */
350 env
->fsr
|= (env
->fsr
& FSR_CEXC_MASK
) << 5;
355 void helper_clear_float_exceptions(CPUState
*env
)
357 set_float_exception_flags(0, &env
->fp_status
);
360 static inline void set_fsr(CPUState
*env
)
364 switch (env
->fsr
& FSR_RD_MASK
) {
366 rnd_mode
= float_round_nearest_even
;
370 rnd_mode
= float_round_to_zero
;
373 rnd_mode
= float_round_up
;
376 rnd_mode
= float_round_down
;
379 set_float_rounding_mode(rnd_mode
, &env
->fp_status
);
382 void helper_ldfsr(CPUState
*env
, uint32_t new_fsr
)
384 env
->fsr
= (new_fsr
& FSR_LDFSR_MASK
) | (env
->fsr
& FSR_LDFSR_OLDMASK
);
388 #ifdef TARGET_SPARC64
389 void helper_ldxfsr(CPUState
*env
, uint64_t new_fsr
)
391 env
->fsr
= (new_fsr
& FSR_LDXFSR_MASK
) | (env
->fsr
& FSR_LDXFSR_OLDMASK
);