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1 /*
2 * sparc helpers
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24 #include <signal.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28 #include "qemu-common.h"
29
30 //#define DEBUG_MMU
31 //#define DEBUG_FEATURES
32
33 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
34
35 /* Sparc MMU emulation */
36
37 /* thread support */
38
39 static spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
40
41 void cpu_lock(void)
42 {
43 spin_lock(&global_cpu_lock);
44 }
45
46 void cpu_unlock(void)
47 {
48 spin_unlock(&global_cpu_lock);
49 }
50
51 #if defined(CONFIG_USER_ONLY)
52
53 int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw,
54 int mmu_idx, int is_softmmu)
55 {
56 if (rw & 2)
57 env1->exception_index = TT_TFAULT;
58 else
59 env1->exception_index = TT_DFAULT;
60 return 1;
61 }
62
63 #else
64
65 #ifndef TARGET_SPARC64
66 /*
67 * Sparc V8 Reference MMU (SRMMU)
68 */
69 static const int access_table[8][8] = {
70 { 0, 0, 0, 0, 8, 0, 12, 12 },
71 { 0, 0, 0, 0, 8, 0, 0, 0 },
72 { 8, 8, 0, 0, 0, 8, 12, 12 },
73 { 8, 8, 0, 0, 0, 8, 0, 0 },
74 { 8, 0, 8, 0, 8, 8, 12, 12 },
75 { 8, 0, 8, 0, 8, 0, 8, 0 },
76 { 8, 8, 8, 0, 8, 8, 12, 12 },
77 { 8, 8, 8, 0, 8, 8, 8, 0 }
78 };
79
80 static const int perm_table[2][8] = {
81 {
82 PAGE_READ,
83 PAGE_READ | PAGE_WRITE,
84 PAGE_READ | PAGE_EXEC,
85 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
86 PAGE_EXEC,
87 PAGE_READ | PAGE_WRITE,
88 PAGE_READ | PAGE_EXEC,
89 PAGE_READ | PAGE_WRITE | PAGE_EXEC
90 },
91 {
92 PAGE_READ,
93 PAGE_READ | PAGE_WRITE,
94 PAGE_READ | PAGE_EXEC,
95 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
96 PAGE_EXEC,
97 PAGE_READ,
98 0,
99 0,
100 }
101 };
102
103 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
104 int *prot, int *access_index,
105 target_ulong address, int rw, int mmu_idx)
106 {
107 int access_perms = 0;
108 target_phys_addr_t pde_ptr;
109 uint32_t pde;
110 int error_code = 0, is_dirty, is_user;
111 unsigned long page_offset;
112
113 is_user = mmu_idx == MMU_USER_IDX;
114
115 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
116 // Boot mode: instruction fetches are taken from PROM
117 if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) {
118 *physical = env->prom_addr | (address & 0x7ffffULL);
119 *prot = PAGE_READ | PAGE_EXEC;
120 return 0;
121 }
122 *physical = address;
123 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
124 return 0;
125 }
126
127 *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
128 *physical = 0xffffffffffff0000ULL;
129
130 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
131 /* Context base + context number */
132 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
133 pde = ldl_phys(pde_ptr);
134
135 /* Ctx pde */
136 switch (pde & PTE_ENTRYTYPE_MASK) {
137 default:
138 case 0: /* Invalid */
139 return 1 << 2;
140 case 2: /* L0 PTE, maybe should not happen? */
141 case 3: /* Reserved */
142 return 4 << 2;
143 case 1: /* L0 PDE */
144 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
145 pde = ldl_phys(pde_ptr);
146
147 switch (pde & PTE_ENTRYTYPE_MASK) {
148 default:
149 case 0: /* Invalid */
150 return (1 << 8) | (1 << 2);
151 case 3: /* Reserved */
152 return (1 << 8) | (4 << 2);
153 case 1: /* L1 PDE */
154 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
155 pde = ldl_phys(pde_ptr);
156
157 switch (pde & PTE_ENTRYTYPE_MASK) {
158 default:
159 case 0: /* Invalid */
160 return (2 << 8) | (1 << 2);
161 case 3: /* Reserved */
162 return (2 << 8) | (4 << 2);
163 case 1: /* L2 PDE */
164 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
165 pde = ldl_phys(pde_ptr);
166
167 switch (pde & PTE_ENTRYTYPE_MASK) {
168 default:
169 case 0: /* Invalid */
170 return (3 << 8) | (1 << 2);
171 case 1: /* PDE, should not happen */
172 case 3: /* Reserved */
173 return (3 << 8) | (4 << 2);
174 case 2: /* L3 PTE */
175 page_offset = (address & TARGET_PAGE_MASK) &
176 (TARGET_PAGE_SIZE - 1);
177 }
178 break;
179 case 2: /* L2 PTE */
180 page_offset = address & 0x3ffff;
181 }
182 break;
183 case 2: /* L1 PTE */
184 page_offset = address & 0xffffff;
185 }
186 }
187
188 /* check access */
189 access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
190 error_code = access_table[*access_index][access_perms];
191 if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
192 return error_code;
193
194 /* update page modified and dirty bits */
195 is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
196 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
197 pde |= PG_ACCESSED_MASK;
198 if (is_dirty)
199 pde |= PG_MODIFIED_MASK;
200 stl_phys_notdirty(pde_ptr, pde);
201 }
202
203 /* the page can be put in the TLB */
204 *prot = perm_table[is_user][access_perms];
205 if (!(pde & PG_MODIFIED_MASK)) {
206 /* only set write access if already dirty... otherwise wait
207 for dirty access */
208 *prot &= ~PAGE_WRITE;
209 }
210
211 /* Even if large ptes, we map only one 4KB page in the cache to
212 avoid filling it too fast */
213 *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
214 return error_code;
215 }
216
217 /* Perform address translation */
218 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
219 int mmu_idx, int is_softmmu)
220 {
221 target_phys_addr_t paddr;
222 target_ulong vaddr;
223 int error_code = 0, prot, ret = 0, access_index;
224
225 error_code = get_physical_address(env, &paddr, &prot, &access_index,
226 address, rw, mmu_idx);
227 if (error_code == 0) {
228 vaddr = address & TARGET_PAGE_MASK;
229 paddr &= TARGET_PAGE_MASK;
230 #ifdef DEBUG_MMU
231 printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
232 TARGET_FMT_lx "\n", address, paddr, vaddr);
233 #endif
234 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
235 return ret;
236 }
237
238 if (env->mmuregs[3]) /* Fault status register */
239 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
240 env->mmuregs[3] |= (access_index << 5) | error_code | 2;
241 env->mmuregs[4] = address; /* Fault address register */
242
243 if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) {
244 // No fault mode: if a mapping is available, just override
245 // permissions. If no mapping is available, redirect accesses to
246 // neverland. Fake/overridden mappings will be flushed when
247 // switching to normal mode.
248 vaddr = address & TARGET_PAGE_MASK;
249 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
250 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
251 return ret;
252 } else {
253 if (rw & 2)
254 env->exception_index = TT_TFAULT;
255 else
256 env->exception_index = TT_DFAULT;
257 return 1;
258 }
259 }
260
261 target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
262 {
263 target_phys_addr_t pde_ptr;
264 uint32_t pde;
265
266 /* Context base + context number */
267 pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
268 (env->mmuregs[2] << 2);
269 pde = ldl_phys(pde_ptr);
270
271 switch (pde & PTE_ENTRYTYPE_MASK) {
272 default:
273 case 0: /* Invalid */
274 case 2: /* PTE, maybe should not happen? */
275 case 3: /* Reserved */
276 return 0;
277 case 1: /* L1 PDE */
278 if (mmulev == 3)
279 return pde;
280 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
281 pde = ldl_phys(pde_ptr);
282
283 switch (pde & PTE_ENTRYTYPE_MASK) {
284 default:
285 case 0: /* Invalid */
286 case 3: /* Reserved */
287 return 0;
288 case 2: /* L1 PTE */
289 return pde;
290 case 1: /* L2 PDE */
291 if (mmulev == 2)
292 return pde;
293 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
294 pde = ldl_phys(pde_ptr);
295
296 switch (pde & PTE_ENTRYTYPE_MASK) {
297 default:
298 case 0: /* Invalid */
299 case 3: /* Reserved */
300 return 0;
301 case 2: /* L2 PTE */
302 return pde;
303 case 1: /* L3 PDE */
304 if (mmulev == 1)
305 return pde;
306 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
307 pde = ldl_phys(pde_ptr);
308
309 switch (pde & PTE_ENTRYTYPE_MASK) {
310 default:
311 case 0: /* Invalid */
312 case 1: /* PDE, should not happen */
313 case 3: /* Reserved */
314 return 0;
315 case 2: /* L3 PTE */
316 return pde;
317 }
318 }
319 }
320 }
321 return 0;
322 }
323
324 #ifdef DEBUG_MMU
325 void dump_mmu(CPUState *env)
326 {
327 target_ulong va, va1, va2;
328 unsigned int n, m, o;
329 target_phys_addr_t pde_ptr, pa;
330 uint32_t pde;
331
332 printf("MMU dump:\n");
333 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
334 pde = ldl_phys(pde_ptr);
335 printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
336 (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
337 for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
338 pde = mmu_probe(env, va, 2);
339 if (pde) {
340 pa = cpu_get_phys_page_debug(env, va);
341 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
342 " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
343 for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
344 pde = mmu_probe(env, va1, 1);
345 if (pde) {
346 pa = cpu_get_phys_page_debug(env, va1);
347 printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
348 " PDE: " TARGET_FMT_lx "\n", va1, pa, pde);
349 for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
350 pde = mmu_probe(env, va2, 0);
351 if (pde) {
352 pa = cpu_get_phys_page_debug(env, va2);
353 printf(" VA: " TARGET_FMT_lx ", PA: "
354 TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n",
355 va2, pa, pde);
356 }
357 }
358 }
359 }
360 }
361 }
362 printf("MMU dump ends\n");
363 }
364 #endif /* DEBUG_MMU */
365
366 #else /* !TARGET_SPARC64 */
367
368 // 41 bit physical address space
369 static inline target_phys_addr_t ultrasparc_truncate_physical(uint64_t x)
370 {
371 return x & 0x1ffffffffffULL;
372 }
373
374 /*
375 * UltraSparc IIi I/DMMUs
376 */
377
378 static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
379 {
380 return (x & mask) == (y & mask);
381 }
382
383 // Returns true if TTE tag is valid and matches virtual address value in context
384 // requires virtual address mask value calculated from TTE entry size
385 static inline int ultrasparc_tag_match(SparcTLBEntry *tlb,
386 uint64_t address, uint64_t context,
387 target_phys_addr_t *physical,
388 int is_nucleus)
389 {
390 uint64_t mask;
391
392 switch ((tlb->tte >> 61) & 3) {
393 default:
394 case 0x0: // 8k
395 mask = 0xffffffffffffe000ULL;
396 break;
397 case 0x1: // 64k
398 mask = 0xffffffffffff0000ULL;
399 break;
400 case 0x2: // 512k
401 mask = 0xfffffffffff80000ULL;
402 break;
403 case 0x3: // 4M
404 mask = 0xffffffffffc00000ULL;
405 break;
406 }
407
408 // valid, context match, virtual address match?
409 if (TTE_IS_VALID(tlb->tte) &&
410 ((is_nucleus && compare_masked(0, tlb->tag, 0x1fff))
411 || TTE_IS_GLOBAL(tlb->tte) || compare_masked(context, tlb->tag, 0x1fff))
412 && compare_masked(address, tlb->tag, mask))
413 {
414 // decode physical address
415 *physical = ((tlb->tte & mask) | (address & ~mask)) & 0x1ffffffe000ULL;
416 return 1;
417 }
418
419 return 0;
420 }
421
422 static int get_physical_address_data(CPUState *env,
423 target_phys_addr_t *physical, int *prot,
424 target_ulong address, int rw, int is_user)
425 {
426 unsigned int i;
427 uint64_t context;
428 int is_nucleus;
429
430 if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
431 *physical = ultrasparc_truncate_physical(address);
432 *prot = PAGE_READ | PAGE_WRITE;
433 return 0;
434 }
435
436 context = env->dmmu.mmu_primary_context & 0x1fff;
437 is_nucleus = env->tl > 0;
438
439 for (i = 0; i < 64; i++) {
440 // ctx match, vaddr match, valid?
441 if (ultrasparc_tag_match(&env->dtlb[i],
442 address, context, physical,
443 is_nucleus)) {
444 // access ok?
445 if (((env->dtlb[i].tte & 0x4) && is_user) ||
446 (!(env->dtlb[i].tte & 0x2) && (rw == 1))) {
447 uint8_t fault_type = 0;
448
449 if ((env->dtlb[i].tte & 0x4) && is_user) {
450 fault_type |= 1; /* privilege violation */
451 }
452
453 if (env->dmmu.sfsr & 1) /* Fault status register */
454 env->dmmu.sfsr = 2; /* overflow (not read before
455 another fault) */
456
457 env->dmmu.sfsr |= (is_user << 3) | ((rw == 1) << 2) | 1;
458
459 env->dmmu.sfsr |= (fault_type << 7);
460
461 env->dmmu.sfar = address; /* Fault address register */
462 env->exception_index = TT_DFAULT;
463 #ifdef DEBUG_MMU
464 printf("DFAULT at 0x%" PRIx64 "\n", address);
465 #endif
466 return 1;
467 }
468 *prot = PAGE_READ;
469 if (env->dtlb[i].tte & 0x2)
470 *prot |= PAGE_WRITE;
471 TTE_SET_USED(env->dtlb[i].tte);
472 return 0;
473 }
474 }
475 #ifdef DEBUG_MMU
476 printf("DMISS at 0x%" PRIx64 "\n", address);
477 #endif
478 env->dmmu.tag_access = (address & ~0x1fffULL) | context;
479 env->exception_index = TT_DMISS;
480 return 1;
481 }
482
483 static int get_physical_address_code(CPUState *env,
484 target_phys_addr_t *physical, int *prot,
485 target_ulong address, int is_user)
486 {
487 unsigned int i;
488 uint64_t context;
489 int is_nucleus;
490
491 if ((env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0) {
492 /* IMMU disabled */
493 *physical = ultrasparc_truncate_physical(address);
494 *prot = PAGE_EXEC;
495 return 0;
496 }
497
498 context = env->dmmu.mmu_primary_context & 0x1fff;
499 is_nucleus = env->tl > 0;
500
501 for (i = 0; i < 64; i++) {
502 // ctx match, vaddr match, valid?
503 if (ultrasparc_tag_match(&env->itlb[i],
504 address, context, physical,
505 is_nucleus)) {
506 // access ok?
507 if ((env->itlb[i].tte & 0x4) && is_user) {
508 if (env->immu.sfsr) /* Fault status register */
509 env->immu.sfsr = 2; /* overflow (not read before
510 another fault) */
511 env->immu.sfsr |= (is_user << 3) | 1;
512 env->exception_index = TT_TFAULT;
513 #ifdef DEBUG_MMU
514 printf("TFAULT at 0x%" PRIx64 "\n", address);
515 #endif
516 return 1;
517 }
518 *prot = PAGE_EXEC;
519 TTE_SET_USED(env->itlb[i].tte);
520 return 0;
521 }
522 }
523 #ifdef DEBUG_MMU
524 printf("TMISS at 0x%" PRIx64 "\n", address);
525 #endif
526 /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */
527 env->immu.tag_access = (address & ~0x1fffULL) | context;
528 env->exception_index = TT_TMISS;
529 return 1;
530 }
531
532 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
533 int *prot, int *access_index,
534 target_ulong address, int rw, int mmu_idx)
535 {
536 int is_user = mmu_idx == MMU_USER_IDX;
537
538 if (rw == 2)
539 return get_physical_address_code(env, physical, prot, address,
540 is_user);
541 else
542 return get_physical_address_data(env, physical, prot, address, rw,
543 is_user);
544 }
545
546 /* Perform address translation */
547 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
548 int mmu_idx, int is_softmmu)
549 {
550 target_ulong virt_addr, vaddr;
551 target_phys_addr_t paddr;
552 int error_code = 0, prot, ret = 0, access_index;
553
554 error_code = get_physical_address(env, &paddr, &prot, &access_index,
555 address, rw, mmu_idx);
556 if (error_code == 0) {
557 virt_addr = address & TARGET_PAGE_MASK;
558 vaddr = virt_addr + ((address & TARGET_PAGE_MASK) &
559 (TARGET_PAGE_SIZE - 1));
560 #ifdef DEBUG_MMU
561 printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64
562 "\n", address, paddr, vaddr);
563 #endif
564 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
565 return ret;
566 }
567 // XXX
568 return 1;
569 }
570
571 #ifdef DEBUG_MMU
572 void dump_mmu(CPUState *env)
573 {
574 unsigned int i;
575 const char *mask;
576
577 printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n",
578 env->dmmu.mmu_primary_context, env->dmmu.mmu_secondary_context);
579 if ((env->lsu & DMMU_E) == 0) {
580 printf("DMMU disabled\n");
581 } else {
582 printf("DMMU dump:\n");
583 for (i = 0; i < 64; i++) {
584 switch ((env->dtlb[i].tte >> 61) & 3) {
585 default:
586 case 0x0:
587 mask = " 8k";
588 break;
589 case 0x1:
590 mask = " 64k";
591 break;
592 case 0x2:
593 mask = "512k";
594 break;
595 case 0x3:
596 mask = " 4M";
597 break;
598 }
599 if ((env->dtlb[i].tte & 0x8000000000000000ULL) != 0) {
600 printf("[%02u] VA: %" PRIx64 ", PA: %" PRIx64
601 ", %s, %s, %s, %s, ctx %" PRId64 " %s\n",
602 i,
603 env->dtlb[i].tag & (uint64_t)~0x1fffULL,
604 env->dtlb[i].tte & (uint64_t)0x1ffffffe000ULL,
605 mask,
606 env->dtlb[i].tte & 0x4? "priv": "user",
607 env->dtlb[i].tte & 0x2? "RW": "RO",
608 env->dtlb[i].tte & 0x40? "locked": "unlocked",
609 env->dtlb[i].tag & (uint64_t)0x1fffULL,
610 TTE_IS_GLOBAL(env->dtlb[i].tag)? "global" : "local");
611 }
612 }
613 }
614 if ((env->lsu & IMMU_E) == 0) {
615 printf("IMMU disabled\n");
616 } else {
617 printf("IMMU dump:\n");
618 for (i = 0; i < 64; i++) {
619 switch ((env->itlb[i].tte >> 61) & 3) {
620 default:
621 case 0x0:
622 mask = " 8k";
623 break;
624 case 0x1:
625 mask = " 64k";
626 break;
627 case 0x2:
628 mask = "512k";
629 break;
630 case 0x3:
631 mask = " 4M";
632 break;
633 }
634 if ((env->itlb[i].tte & 0x8000000000000000ULL) != 0) {
635 printf("[%02u] VA: %" PRIx64 ", PA: %" PRIx64
636 ", %s, %s, %s, ctx %" PRId64 " %s\n",
637 i,
638 env->itlb[i].tag & (uint64_t)~0x1fffULL,
639 env->itlb[i].tte & (uint64_t)0x1ffffffe000ULL,
640 mask,
641 env->itlb[i].tte & 0x4? "priv": "user",
642 env->itlb[i].tte & 0x40? "locked": "unlocked",
643 env->itlb[i].tag & (uint64_t)0x1fffULL,
644 TTE_IS_GLOBAL(env->itlb[i].tag)? "global" : "local");
645 }
646 }
647 }
648 }
649 #endif /* DEBUG_MMU */
650
651 #endif /* TARGET_SPARC64 */
652 #endif /* !CONFIG_USER_ONLY */
653
654
655 #if !defined(CONFIG_USER_ONLY)
656 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
657 {
658 target_phys_addr_t phys_addr;
659 int prot, access_index;
660
661 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,
662 MMU_KERNEL_IDX) != 0)
663 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
664 0, MMU_KERNEL_IDX) != 0)
665 return -1;
666 if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
667 return -1;
668 return phys_addr;
669 }
670 #endif
671
672 void cpu_reset(CPUSPARCState *env)
673 {
674 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
675 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
676 log_cpu_state(env, 0);
677 }
678
679 tlb_flush(env, 1);
680 env->cwp = 0;
681 #ifndef TARGET_SPARC64
682 env->wim = 1;
683 #endif
684 env->regwptr = env->regbase + (env->cwp * 16);
685 CC_OP = CC_OP_FLAGS;
686 #if defined(CONFIG_USER_ONLY)
687 #ifdef TARGET_SPARC64
688 env->cleanwin = env->nwindows - 2;
689 env->cansave = env->nwindows - 2;
690 env->pstate = PS_RMO | PS_PEF | PS_IE;
691 env->asi = 0x82; // Primary no-fault
692 #endif
693 #else
694 #if !defined(TARGET_SPARC64)
695 env->psret = 0;
696 #endif
697 env->psrs = 1;
698 env->psrps = 1;
699 #ifdef TARGET_SPARC64
700 env->pstate = PS_PRIV|PS_RED|PS_PEF|PS_AG;
701 env->hpstate = HS_PRIV;
702 env->tl = env->maxtl;
703 cpu_tsptr(env)->tt = TT_POWER_ON_RESET;
704 env->lsu = 0;
705 #else
706 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
707 env->mmuregs[0] |= env->def->mmu_bm;
708 #endif
709 env->pc = 0;
710 env->npc = env->pc + 4;
711 #endif
712 }
713
714 static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
715 {
716 sparc_def_t def1, *def = &def1;
717
718 if (cpu_sparc_find_by_name(def, cpu_model) < 0)
719 return -1;
720
721 env->def = qemu_mallocz(sizeof(*def));
722 memcpy(env->def, def, sizeof(*def));
723 #if defined(CONFIG_USER_ONLY)
724 if ((env->def->features & CPU_FEATURE_FLOAT))
725 env->def->features |= CPU_FEATURE_FLOAT128;
726 #endif
727 env->cpu_model_str = cpu_model;
728 env->version = def->iu_version;
729 env->fsr = def->fpu_version;
730 env->nwindows = def->nwindows;
731 #if !defined(TARGET_SPARC64)
732 env->mmuregs[0] |= def->mmu_version;
733 cpu_sparc_set_id(env, 0);
734 env->mxccregs[7] |= def->mxcc_version;
735 #else
736 env->mmu_version = def->mmu_version;
737 env->maxtl = def->maxtl;
738 env->version |= def->maxtl << 8;
739 env->version |= def->nwindows - 1;
740 #endif
741 return 0;
742 }
743
744 static void cpu_sparc_close(CPUSPARCState *env)
745 {
746 free(env->def);
747 free(env);
748 }
749
750 CPUSPARCState *cpu_sparc_init(const char *cpu_model)
751 {
752 CPUSPARCState *env;
753
754 env = qemu_mallocz(sizeof(CPUSPARCState));
755 cpu_exec_init(env);
756
757 gen_intermediate_code_init(env);
758
759 if (cpu_sparc_register(env, cpu_model) < 0) {
760 cpu_sparc_close(env);
761 return NULL;
762 }
763 qemu_init_vcpu(env);
764
765 return env;
766 }
767
768 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
769 {
770 #if !defined(TARGET_SPARC64)
771 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
772 #endif
773 }
774
775 static const sparc_def_t sparc_defs[] = {
776 #ifdef TARGET_SPARC64
777 {
778 .name = "Fujitsu Sparc64",
779 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
780 .fpu_version = 0x00000000,
781 .mmu_version = mmu_us_12,
782 .nwindows = 4,
783 .maxtl = 4,
784 .features = CPU_DEFAULT_FEATURES,
785 },
786 {
787 .name = "Fujitsu Sparc64 III",
788 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
789 .fpu_version = 0x00000000,
790 .mmu_version = mmu_us_12,
791 .nwindows = 5,
792 .maxtl = 4,
793 .features = CPU_DEFAULT_FEATURES,
794 },
795 {
796 .name = "Fujitsu Sparc64 IV",
797 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
798 .fpu_version = 0x00000000,
799 .mmu_version = mmu_us_12,
800 .nwindows = 8,
801 .maxtl = 5,
802 .features = CPU_DEFAULT_FEATURES,
803 },
804 {
805 .name = "Fujitsu Sparc64 V",
806 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
807 .fpu_version = 0x00000000,
808 .mmu_version = mmu_us_12,
809 .nwindows = 8,
810 .maxtl = 5,
811 .features = CPU_DEFAULT_FEATURES,
812 },
813 {
814 .name = "TI UltraSparc I",
815 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
816 .fpu_version = 0x00000000,
817 .mmu_version = mmu_us_12,
818 .nwindows = 8,
819 .maxtl = 5,
820 .features = CPU_DEFAULT_FEATURES,
821 },
822 {
823 .name = "TI UltraSparc II",
824 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
825 .fpu_version = 0x00000000,
826 .mmu_version = mmu_us_12,
827 .nwindows = 8,
828 .maxtl = 5,
829 .features = CPU_DEFAULT_FEATURES,
830 },
831 {
832 .name = "TI UltraSparc IIi",
833 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
834 .fpu_version = 0x00000000,
835 .mmu_version = mmu_us_12,
836 .nwindows = 8,
837 .maxtl = 5,
838 .features = CPU_DEFAULT_FEATURES,
839 },
840 {
841 .name = "TI UltraSparc IIe",
842 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
843 .fpu_version = 0x00000000,
844 .mmu_version = mmu_us_12,
845 .nwindows = 8,
846 .maxtl = 5,
847 .features = CPU_DEFAULT_FEATURES,
848 },
849 {
850 .name = "Sun UltraSparc III",
851 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
852 .fpu_version = 0x00000000,
853 .mmu_version = mmu_us_12,
854 .nwindows = 8,
855 .maxtl = 5,
856 .features = CPU_DEFAULT_FEATURES,
857 },
858 {
859 .name = "Sun UltraSparc III Cu",
860 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
861 .fpu_version = 0x00000000,
862 .mmu_version = mmu_us_3,
863 .nwindows = 8,
864 .maxtl = 5,
865 .features = CPU_DEFAULT_FEATURES,
866 },
867 {
868 .name = "Sun UltraSparc IIIi",
869 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
870 .fpu_version = 0x00000000,
871 .mmu_version = mmu_us_12,
872 .nwindows = 8,
873 .maxtl = 5,
874 .features = CPU_DEFAULT_FEATURES,
875 },
876 {
877 .name = "Sun UltraSparc IV",
878 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
879 .fpu_version = 0x00000000,
880 .mmu_version = mmu_us_4,
881 .nwindows = 8,
882 .maxtl = 5,
883 .features = CPU_DEFAULT_FEATURES,
884 },
885 {
886 .name = "Sun UltraSparc IV+",
887 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
888 .fpu_version = 0x00000000,
889 .mmu_version = mmu_us_12,
890 .nwindows = 8,
891 .maxtl = 5,
892 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
893 },
894 {
895 .name = "Sun UltraSparc IIIi+",
896 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
897 .fpu_version = 0x00000000,
898 .mmu_version = mmu_us_3,
899 .nwindows = 8,
900 .maxtl = 5,
901 .features = CPU_DEFAULT_FEATURES,
902 },
903 {
904 .name = "Sun UltraSparc T1",
905 // defined in sparc_ifu_fdp.v and ctu.h
906 .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
907 .fpu_version = 0x00000000,
908 .mmu_version = mmu_sun4v,
909 .nwindows = 8,
910 .maxtl = 6,
911 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
912 | CPU_FEATURE_GL,
913 },
914 {
915 .name = "Sun UltraSparc T2",
916 // defined in tlu_asi_ctl.v and n2_revid_cust.v
917 .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
918 .fpu_version = 0x00000000,
919 .mmu_version = mmu_sun4v,
920 .nwindows = 8,
921 .maxtl = 6,
922 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
923 | CPU_FEATURE_GL,
924 },
925 {
926 .name = "NEC UltraSparc I",
927 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
928 .fpu_version = 0x00000000,
929 .mmu_version = mmu_us_12,
930 .nwindows = 8,
931 .maxtl = 5,
932 .features = CPU_DEFAULT_FEATURES,
933 },
934 #else
935 {
936 .name = "Fujitsu MB86900",
937 .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
938 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
939 .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
940 .mmu_bm = 0x00004000,
941 .mmu_ctpr_mask = 0x007ffff0,
942 .mmu_cxr_mask = 0x0000003f,
943 .mmu_sfsr_mask = 0xffffffff,
944 .mmu_trcr_mask = 0xffffffff,
945 .nwindows = 7,
946 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD,
947 },
948 {
949 .name = "Fujitsu MB86904",
950 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
951 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
952 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
953 .mmu_bm = 0x00004000,
954 .mmu_ctpr_mask = 0x00ffffc0,
955 .mmu_cxr_mask = 0x000000ff,
956 .mmu_sfsr_mask = 0x00016fff,
957 .mmu_trcr_mask = 0x00ffffff,
958 .nwindows = 8,
959 .features = CPU_DEFAULT_FEATURES,
960 },
961 {
962 .name = "Fujitsu MB86907",
963 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
964 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
965 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
966 .mmu_bm = 0x00004000,
967 .mmu_ctpr_mask = 0xffffffc0,
968 .mmu_cxr_mask = 0x000000ff,
969 .mmu_sfsr_mask = 0x00016fff,
970 .mmu_trcr_mask = 0xffffffff,
971 .nwindows = 8,
972 .features = CPU_DEFAULT_FEATURES,
973 },
974 {
975 .name = "LSI L64811",
976 .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
977 .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
978 .mmu_version = 0x10 << 24,
979 .mmu_bm = 0x00004000,
980 .mmu_ctpr_mask = 0x007ffff0,
981 .mmu_cxr_mask = 0x0000003f,
982 .mmu_sfsr_mask = 0xffffffff,
983 .mmu_trcr_mask = 0xffffffff,
984 .nwindows = 8,
985 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
986 CPU_FEATURE_FSMULD,
987 },
988 {
989 .name = "Cypress CY7C601",
990 .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
991 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
992 .mmu_version = 0x10 << 24,
993 .mmu_bm = 0x00004000,
994 .mmu_ctpr_mask = 0x007ffff0,
995 .mmu_cxr_mask = 0x0000003f,
996 .mmu_sfsr_mask = 0xffffffff,
997 .mmu_trcr_mask = 0xffffffff,
998 .nwindows = 8,
999 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1000 CPU_FEATURE_FSMULD,
1001 },
1002 {
1003 .name = "Cypress CY7C611",
1004 .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
1005 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
1006 .mmu_version = 0x10 << 24,
1007 .mmu_bm = 0x00004000,
1008 .mmu_ctpr_mask = 0x007ffff0,
1009 .mmu_cxr_mask = 0x0000003f,
1010 .mmu_sfsr_mask = 0xffffffff,
1011 .mmu_trcr_mask = 0xffffffff,
1012 .nwindows = 8,
1013 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1014 CPU_FEATURE_FSMULD,
1015 },
1016 {
1017 .name = "TI MicroSparc I",
1018 .iu_version = 0x41000000,
1019 .fpu_version = 4 << 17,
1020 .mmu_version = 0x41000000,
1021 .mmu_bm = 0x00004000,
1022 .mmu_ctpr_mask = 0x007ffff0,
1023 .mmu_cxr_mask = 0x0000003f,
1024 .mmu_sfsr_mask = 0x00016fff,
1025 .mmu_trcr_mask = 0x0000003f,
1026 .nwindows = 7,
1027 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
1028 CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
1029 CPU_FEATURE_FMUL,
1030 },
1031 {
1032 .name = "TI MicroSparc II",
1033 .iu_version = 0x42000000,
1034 .fpu_version = 4 << 17,
1035 .mmu_version = 0x02000000,
1036 .mmu_bm = 0x00004000,
1037 .mmu_ctpr_mask = 0x00ffffc0,
1038 .mmu_cxr_mask = 0x000000ff,
1039 .mmu_sfsr_mask = 0x00016fff,
1040 .mmu_trcr_mask = 0x00ffffff,
1041 .nwindows = 8,
1042 .features = CPU_DEFAULT_FEATURES,
1043 },
1044 {
1045 .name = "TI MicroSparc IIep",
1046 .iu_version = 0x42000000,
1047 .fpu_version = 4 << 17,
1048 .mmu_version = 0x04000000,
1049 .mmu_bm = 0x00004000,
1050 .mmu_ctpr_mask = 0x00ffffc0,
1051 .mmu_cxr_mask = 0x000000ff,
1052 .mmu_sfsr_mask = 0x00016bff,
1053 .mmu_trcr_mask = 0x00ffffff,
1054 .nwindows = 8,
1055 .features = CPU_DEFAULT_FEATURES,
1056 },
1057 {
1058 .name = "TI SuperSparc 40", // STP1020NPGA
1059 .iu_version = 0x41000000, // SuperSPARC 2.x
1060 .fpu_version = 0 << 17,
1061 .mmu_version = 0x00000800, // SuperSPARC 2.x, no MXCC
1062 .mmu_bm = 0x00002000,
1063 .mmu_ctpr_mask = 0xffffffc0,
1064 .mmu_cxr_mask = 0x0000ffff,
1065 .mmu_sfsr_mask = 0xffffffff,
1066 .mmu_trcr_mask = 0xffffffff,
1067 .nwindows = 8,
1068 .features = CPU_DEFAULT_FEATURES,
1069 },
1070 {
1071 .name = "TI SuperSparc 50", // STP1020PGA
1072 .iu_version = 0x40000000, // SuperSPARC 3.x
1073 .fpu_version = 0 << 17,
1074 .mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC
1075 .mmu_bm = 0x00002000,
1076 .mmu_ctpr_mask = 0xffffffc0,
1077 .mmu_cxr_mask = 0x0000ffff,
1078 .mmu_sfsr_mask = 0xffffffff,
1079 .mmu_trcr_mask = 0xffffffff,
1080 .nwindows = 8,
1081 .features = CPU_DEFAULT_FEATURES,
1082 },
1083 {
1084 .name = "TI SuperSparc 51",
1085 .iu_version = 0x40000000, // SuperSPARC 3.x
1086 .fpu_version = 0 << 17,
1087 .mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC
1088 .mmu_bm = 0x00002000,
1089 .mmu_ctpr_mask = 0xffffffc0,
1090 .mmu_cxr_mask = 0x0000ffff,
1091 .mmu_sfsr_mask = 0xffffffff,
1092 .mmu_trcr_mask = 0xffffffff,
1093 .mxcc_version = 0x00000104,
1094 .nwindows = 8,
1095 .features = CPU_DEFAULT_FEATURES,
1096 },
1097 {
1098 .name = "TI SuperSparc 60", // STP1020APGA
1099 .iu_version = 0x40000000, // SuperSPARC 3.x
1100 .fpu_version = 0 << 17,
1101 .mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC
1102 .mmu_bm = 0x00002000,
1103 .mmu_ctpr_mask = 0xffffffc0,
1104 .mmu_cxr_mask = 0x0000ffff,
1105 .mmu_sfsr_mask = 0xffffffff,
1106 .mmu_trcr_mask = 0xffffffff,
1107 .nwindows = 8,
1108 .features = CPU_DEFAULT_FEATURES,
1109 },
1110 {
1111 .name = "TI SuperSparc 61",
1112 .iu_version = 0x44000000, // SuperSPARC 3.x
1113 .fpu_version = 0 << 17,
1114 .mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC
1115 .mmu_bm = 0x00002000,
1116 .mmu_ctpr_mask = 0xffffffc0,
1117 .mmu_cxr_mask = 0x0000ffff,
1118 .mmu_sfsr_mask = 0xffffffff,
1119 .mmu_trcr_mask = 0xffffffff,
1120 .mxcc_version = 0x00000104,
1121 .nwindows = 8,
1122 .features = CPU_DEFAULT_FEATURES,
1123 },
1124 {
1125 .name = "TI SuperSparc II",
1126 .iu_version = 0x40000000, // SuperSPARC II 1.x
1127 .fpu_version = 0 << 17,
1128 .mmu_version = 0x08000000, // SuperSPARC II 1.x, MXCC
1129 .mmu_bm = 0x00002000,
1130 .mmu_ctpr_mask = 0xffffffc0,
1131 .mmu_cxr_mask = 0x0000ffff,
1132 .mmu_sfsr_mask = 0xffffffff,
1133 .mmu_trcr_mask = 0xffffffff,
1134 .mxcc_version = 0x00000104,
1135 .nwindows = 8,
1136 .features = CPU_DEFAULT_FEATURES,
1137 },
1138 {
1139 .name = "Ross RT625",
1140 .iu_version = 0x1e000000,
1141 .fpu_version = 1 << 17,
1142 .mmu_version = 0x1e000000,
1143 .mmu_bm = 0x00004000,
1144 .mmu_ctpr_mask = 0x007ffff0,
1145 .mmu_cxr_mask = 0x0000003f,
1146 .mmu_sfsr_mask = 0xffffffff,
1147 .mmu_trcr_mask = 0xffffffff,
1148 .nwindows = 8,
1149 .features = CPU_DEFAULT_FEATURES,
1150 },
1151 {
1152 .name = "Ross RT620",
1153 .iu_version = 0x1f000000,
1154 .fpu_version = 1 << 17,
1155 .mmu_version = 0x1f000000,
1156 .mmu_bm = 0x00004000,
1157 .mmu_ctpr_mask = 0x007ffff0,
1158 .mmu_cxr_mask = 0x0000003f,
1159 .mmu_sfsr_mask = 0xffffffff,
1160 .mmu_trcr_mask = 0xffffffff,
1161 .nwindows = 8,
1162 .features = CPU_DEFAULT_FEATURES,
1163 },
1164 {
1165 .name = "BIT B5010",
1166 .iu_version = 0x20000000,
1167 .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
1168 .mmu_version = 0x20000000,
1169 .mmu_bm = 0x00004000,
1170 .mmu_ctpr_mask = 0x007ffff0,
1171 .mmu_cxr_mask = 0x0000003f,
1172 .mmu_sfsr_mask = 0xffffffff,
1173 .mmu_trcr_mask = 0xffffffff,
1174 .nwindows = 8,
1175 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1176 CPU_FEATURE_FSMULD,
1177 },
1178 {
1179 .name = "Matsushita MN10501",
1180 .iu_version = 0x50000000,
1181 .fpu_version = 0 << 17,
1182 .mmu_version = 0x50000000,
1183 .mmu_bm = 0x00004000,
1184 .mmu_ctpr_mask = 0x007ffff0,
1185 .mmu_cxr_mask = 0x0000003f,
1186 .mmu_sfsr_mask = 0xffffffff,
1187 .mmu_trcr_mask = 0xffffffff,
1188 .nwindows = 8,
1189 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT |
1190 CPU_FEATURE_FSMULD,
1191 },
1192 {
1193 .name = "Weitek W8601",
1194 .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
1195 .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
1196 .mmu_version = 0x10 << 24,
1197 .mmu_bm = 0x00004000,
1198 .mmu_ctpr_mask = 0x007ffff0,
1199 .mmu_cxr_mask = 0x0000003f,
1200 .mmu_sfsr_mask = 0xffffffff,
1201 .mmu_trcr_mask = 0xffffffff,
1202 .nwindows = 8,
1203 .features = CPU_DEFAULT_FEATURES,
1204 },
1205 {
1206 .name = "LEON2",
1207 .iu_version = 0xf2000000,
1208 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1209 .mmu_version = 0xf2000000,
1210 .mmu_bm = 0x00004000,
1211 .mmu_ctpr_mask = 0x007ffff0,
1212 .mmu_cxr_mask = 0x0000003f,
1213 .mmu_sfsr_mask = 0xffffffff,
1214 .mmu_trcr_mask = 0xffffffff,
1215 .nwindows = 8,
1216 .features = CPU_DEFAULT_FEATURES,
1217 },
1218 {
1219 .name = "LEON3",
1220 .iu_version = 0xf3000000,
1221 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1222 .mmu_version = 0xf3000000,
1223 .mmu_bm = 0x00004000,
1224 .mmu_ctpr_mask = 0x007ffff0,
1225 .mmu_cxr_mask = 0x0000003f,
1226 .mmu_sfsr_mask = 0xffffffff,
1227 .mmu_trcr_mask = 0xffffffff,
1228 .nwindows = 8,
1229 .features = CPU_DEFAULT_FEATURES,
1230 },
1231 #endif
1232 };
1233
1234 static const char * const feature_name[] = {
1235 "float",
1236 "float128",
1237 "swap",
1238 "mul",
1239 "div",
1240 "flush",
1241 "fsqrt",
1242 "fmul",
1243 "vis1",
1244 "vis2",
1245 "fsmuld",
1246 "hypv",
1247 "cmt",
1248 "gl",
1249 };
1250
1251 static void print_features(FILE *f,
1252 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1253 uint32_t features, const char *prefix)
1254 {
1255 unsigned int i;
1256
1257 for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1258 if (feature_name[i] && (features & (1 << i))) {
1259 if (prefix)
1260 (*cpu_fprintf)(f, "%s", prefix);
1261 (*cpu_fprintf)(f, "%s ", feature_name[i]);
1262 }
1263 }
1264
1265 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
1266 {
1267 unsigned int i;
1268
1269 for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1270 if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
1271 *features |= 1 << i;
1272 return;
1273 }
1274 fprintf(stderr, "CPU feature %s not found\n", flagname);
1275 }
1276
1277 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model)
1278 {
1279 unsigned int i;
1280 const sparc_def_t *def = NULL;
1281 char *s = strdup(cpu_model);
1282 char *featurestr, *name = strtok(s, ",");
1283 uint32_t plus_features = 0;
1284 uint32_t minus_features = 0;
1285 long long iu_version;
1286 uint32_t fpu_version, mmu_version, nwindows;
1287
1288 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
1289 if (strcasecmp(name, sparc_defs[i].name) == 0) {
1290 def = &sparc_defs[i];
1291 }
1292 }
1293 if (!def)
1294 goto error;
1295 memcpy(cpu_def, def, sizeof(*def));
1296
1297 featurestr = strtok(NULL, ",");
1298 while (featurestr) {
1299 char *val;
1300
1301 if (featurestr[0] == '+') {
1302 add_flagname_to_bitmaps(featurestr + 1, &plus_features);
1303 } else if (featurestr[0] == '-') {
1304 add_flagname_to_bitmaps(featurestr + 1, &minus_features);
1305 } else if ((val = strchr(featurestr, '='))) {
1306 *val = 0; val++;
1307 if (!strcmp(featurestr, "iu_version")) {
1308 char *err;
1309
1310 iu_version = strtoll(val, &err, 0);
1311 if (!*val || *err) {
1312 fprintf(stderr, "bad numerical value %s\n", val);
1313 goto error;
1314 }
1315 cpu_def->iu_version = iu_version;
1316 #ifdef DEBUG_FEATURES
1317 fprintf(stderr, "iu_version %llx\n", iu_version);
1318 #endif
1319 } else if (!strcmp(featurestr, "fpu_version")) {
1320 char *err;
1321
1322 fpu_version = strtol(val, &err, 0);
1323 if (!*val || *err) {
1324 fprintf(stderr, "bad numerical value %s\n", val);
1325 goto error;
1326 }
1327 cpu_def->fpu_version = fpu_version;
1328 #ifdef DEBUG_FEATURES
1329 fprintf(stderr, "fpu_version %x\n", fpu_version);
1330 #endif
1331 } else if (!strcmp(featurestr, "mmu_version")) {
1332 char *err;
1333
1334 mmu_version = strtol(val, &err, 0);
1335 if (!*val || *err) {
1336 fprintf(stderr, "bad numerical value %s\n", val);
1337 goto error;
1338 }
1339 cpu_def->mmu_version = mmu_version;
1340 #ifdef DEBUG_FEATURES
1341 fprintf(stderr, "mmu_version %x\n", mmu_version);
1342 #endif
1343 } else if (!strcmp(featurestr, "nwindows")) {
1344 char *err;
1345
1346 nwindows = strtol(val, &err, 0);
1347 if (!*val || *err || nwindows > MAX_NWINDOWS ||
1348 nwindows < MIN_NWINDOWS) {
1349 fprintf(stderr, "bad numerical value %s\n", val);
1350 goto error;
1351 }
1352 cpu_def->nwindows = nwindows;
1353 #ifdef DEBUG_FEATURES
1354 fprintf(stderr, "nwindows %d\n", nwindows);
1355 #endif
1356 } else {
1357 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1358 goto error;
1359 }
1360 } else {
1361 fprintf(stderr, "feature string `%s' not in format "
1362 "(+feature|-feature|feature=xyz)\n", featurestr);
1363 goto error;
1364 }
1365 featurestr = strtok(NULL, ",");
1366 }
1367 cpu_def->features |= plus_features;
1368 cpu_def->features &= ~minus_features;
1369 #ifdef DEBUG_FEATURES
1370 print_features(stderr, fprintf, cpu_def->features, NULL);
1371 #endif
1372 free(s);
1373 return 0;
1374
1375 error:
1376 free(s);
1377 return -1;
1378 }
1379
1380 void sparc_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
1381 {
1382 unsigned int i;
1383
1384 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
1385 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x NWINS %d ",
1386 sparc_defs[i].name,
1387 sparc_defs[i].iu_version,
1388 sparc_defs[i].fpu_version,
1389 sparc_defs[i].mmu_version,
1390 sparc_defs[i].nwindows);
1391 print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES &
1392 ~sparc_defs[i].features, "-");
1393 print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES &
1394 sparc_defs[i].features, "+");
1395 (*cpu_fprintf)(f, "\n");
1396 }
1397 (*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): ");
1398 print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL);
1399 (*cpu_fprintf)(f, "\n");
1400 (*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): ");
1401 print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL);
1402 (*cpu_fprintf)(f, "\n");
1403 (*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version "
1404 "fpu_version mmu_version nwindows\n");
1405 }
1406
1407 static void cpu_print_cc(FILE *f,
1408 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1409 uint32_t cc)
1410 {
1411 cpu_fprintf(f, "%c%c%c%c", cc & PSR_NEG? 'N' : '-',
1412 cc & PSR_ZERO? 'Z' : '-', cc & PSR_OVF? 'V' : '-',
1413 cc & PSR_CARRY? 'C' : '-');
1414 }
1415
1416 #ifdef TARGET_SPARC64
1417 #define REGS_PER_LINE 4
1418 #else
1419 #define REGS_PER_LINE 8
1420 #endif
1421
1422 void cpu_dump_state(CPUState *env, FILE *f,
1423 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1424 int flags)
1425 {
1426 int i, x;
1427
1428 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
1429 env->npc);
1430 cpu_fprintf(f, "General Registers:\n");
1431
1432 for (i = 0; i < 8; i++) {
1433 if (i % REGS_PER_LINE == 0) {
1434 cpu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1);
1435 }
1436 cpu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]);
1437 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
1438 cpu_fprintf(f, "\n");
1439 }
1440 }
1441 cpu_fprintf(f, "\nCurrent Register Window:\n");
1442 for (x = 0; x < 3; x++) {
1443 for (i = 0; i < 8; i++) {
1444 if (i % REGS_PER_LINE == 0) {
1445 cpu_fprintf(f, "%%%c%d-%d: ",
1446 x == 0 ? 'o' : (x == 1 ? 'l' : 'i'),
1447 i, i + REGS_PER_LINE - 1);
1448 }
1449 cpu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]);
1450 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
1451 cpu_fprintf(f, "\n");
1452 }
1453 }
1454 }
1455 cpu_fprintf(f, "\nFloating Point Registers:\n");
1456 for (i = 0; i < TARGET_FPREGS; i++) {
1457 if ((i & 3) == 0)
1458 cpu_fprintf(f, "%%f%02d:", i);
1459 cpu_fprintf(f, " %016f", *(float *)&env->fpr[i]);
1460 if ((i & 3) == 3)
1461 cpu_fprintf(f, "\n");
1462 }
1463 #ifdef TARGET_SPARC64
1464 cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
1465 GET_CCR(env));
1466 cpu_print_cc(f, cpu_fprintf, GET_CCR(env) << PSR_CARRY_SHIFT);
1467 cpu_fprintf(f, " xcc: ");
1468 cpu_print_cc(f, cpu_fprintf, GET_CCR(env) << (PSR_CARRY_SHIFT - 4));
1469 cpu_fprintf(f, ") asi: %02x tl: %d pil: %x\n", env->asi, env->tl,
1470 env->psrpil);
1471 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d "
1472 "cleanwin: %d cwp: %d\n",
1473 env->cansave, env->canrestore, env->otherwin, env->wstate,
1474 env->cleanwin, env->nwindows - 1 - env->cwp);
1475 cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: "
1476 TARGET_FMT_lx "\n", env->fsr, env->y, env->fprs);
1477 #else
1478 cpu_fprintf(f, "psr: %08x (icc: ", GET_PSR(env));
1479 cpu_print_cc(f, cpu_fprintf, GET_PSR(env));
1480 cpu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs? 'S' : '-',
1481 env->psrps? 'P' : '-', env->psret? 'E' : '-',
1482 env->wim);
1483 cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n",
1484 env->fsr, env->y);
1485 #endif
1486 }
Qemu copy for testing