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1 /*
2 * sparc helpers
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24
25 #include "cpu.h"
26 #include "qemu-common.h"
27
28 //#define DEBUG_MMU
29 //#define DEBUG_FEATURES
30
31 #ifdef DEBUG_MMU
32 #define DPRINTF_MMU(fmt, ...) \
33 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
34 #else
35 #define DPRINTF_MMU(fmt, ...) do {} while (0)
36 #endif
37
38 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
39
40 /* Sparc MMU emulation */
41
42 #if defined(CONFIG_USER_ONLY)
43
44 int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw,
45 int mmu_idx, int is_softmmu)
46 {
47 if (rw & 2)
48 env1->exception_index = TT_TFAULT;
49 else
50 env1->exception_index = TT_DFAULT;
51 return 1;
52 }
53
54 #else
55
56 #ifndef TARGET_SPARC64
57 /*
58 * Sparc V8 Reference MMU (SRMMU)
59 */
60 static const int access_table[8][8] = {
61 { 0, 0, 0, 0, 8, 0, 12, 12 },
62 { 0, 0, 0, 0, 8, 0, 0, 0 },
63 { 8, 8, 0, 0, 0, 8, 12, 12 },
64 { 8, 8, 0, 0, 0, 8, 0, 0 },
65 { 8, 0, 8, 0, 8, 8, 12, 12 },
66 { 8, 0, 8, 0, 8, 0, 8, 0 },
67 { 8, 8, 8, 0, 8, 8, 12, 12 },
68 { 8, 8, 8, 0, 8, 8, 8, 0 }
69 };
70
71 static const int perm_table[2][8] = {
72 {
73 PAGE_READ,
74 PAGE_READ | PAGE_WRITE,
75 PAGE_READ | PAGE_EXEC,
76 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
77 PAGE_EXEC,
78 PAGE_READ | PAGE_WRITE,
79 PAGE_READ | PAGE_EXEC,
80 PAGE_READ | PAGE_WRITE | PAGE_EXEC
81 },
82 {
83 PAGE_READ,
84 PAGE_READ | PAGE_WRITE,
85 PAGE_READ | PAGE_EXEC,
86 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
87 PAGE_EXEC,
88 PAGE_READ,
89 0,
90 0,
91 }
92 };
93
94 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
95 int *prot, int *access_index,
96 target_ulong address, int rw, int mmu_idx,
97 target_ulong *page_size)
98 {
99 int access_perms = 0;
100 target_phys_addr_t pde_ptr;
101 uint32_t pde;
102 int error_code = 0, is_dirty, is_user;
103 unsigned long page_offset;
104
105 is_user = mmu_idx == MMU_USER_IDX;
106
107 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
108 *page_size = TARGET_PAGE_SIZE;
109 // Boot mode: instruction fetches are taken from PROM
110 if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) {
111 *physical = env->prom_addr | (address & 0x7ffffULL);
112 *prot = PAGE_READ | PAGE_EXEC;
113 return 0;
114 }
115 *physical = address;
116 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
117 return 0;
118 }
119
120 *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
121 *physical = 0xffffffffffff0000ULL;
122
123 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
124 /* Context base + context number */
125 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
126 pde = ldl_phys(pde_ptr);
127
128 /* Ctx pde */
129 switch (pde & PTE_ENTRYTYPE_MASK) {
130 default:
131 case 0: /* Invalid */
132 return 1 << 2;
133 case 2: /* L0 PTE, maybe should not happen? */
134 case 3: /* Reserved */
135 return 4 << 2;
136 case 1: /* L0 PDE */
137 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
138 pde = ldl_phys(pde_ptr);
139
140 switch (pde & PTE_ENTRYTYPE_MASK) {
141 default:
142 case 0: /* Invalid */
143 return (1 << 8) | (1 << 2);
144 case 3: /* Reserved */
145 return (1 << 8) | (4 << 2);
146 case 1: /* L1 PDE */
147 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
148 pde = ldl_phys(pde_ptr);
149
150 switch (pde & PTE_ENTRYTYPE_MASK) {
151 default:
152 case 0: /* Invalid */
153 return (2 << 8) | (1 << 2);
154 case 3: /* Reserved */
155 return (2 << 8) | (4 << 2);
156 case 1: /* L2 PDE */
157 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
158 pde = ldl_phys(pde_ptr);
159
160 switch (pde & PTE_ENTRYTYPE_MASK) {
161 default:
162 case 0: /* Invalid */
163 return (3 << 8) | (1 << 2);
164 case 1: /* PDE, should not happen */
165 case 3: /* Reserved */
166 return (3 << 8) | (4 << 2);
167 case 2: /* L3 PTE */
168 page_offset = (address & TARGET_PAGE_MASK) &
169 (TARGET_PAGE_SIZE - 1);
170 }
171 *page_size = TARGET_PAGE_SIZE;
172 break;
173 case 2: /* L2 PTE */
174 page_offset = address & 0x3ffff;
175 *page_size = 0x40000;
176 }
177 break;
178 case 2: /* L1 PTE */
179 page_offset = address & 0xffffff;
180 *page_size = 0x1000000;
181 }
182 }
183
184 /* check access */
185 access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
186 error_code = access_table[*access_index][access_perms];
187 if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
188 return error_code;
189
190 /* update page modified and dirty bits */
191 is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
192 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
193 pde |= PG_ACCESSED_MASK;
194 if (is_dirty)
195 pde |= PG_MODIFIED_MASK;
196 stl_phys_notdirty(pde_ptr, pde);
197 }
198
199 /* the page can be put in the TLB */
200 *prot = perm_table[is_user][access_perms];
201 if (!(pde & PG_MODIFIED_MASK)) {
202 /* only set write access if already dirty... otherwise wait
203 for dirty access */
204 *prot &= ~PAGE_WRITE;
205 }
206
207 /* Even if large ptes, we map only one 4KB page in the cache to
208 avoid filling it too fast */
209 *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
210 return error_code;
211 }
212
213 /* Perform address translation */
214 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
215 int mmu_idx, int is_softmmu)
216 {
217 target_phys_addr_t paddr;
218 target_ulong vaddr;
219 target_ulong page_size;
220 int error_code = 0, prot, access_index;
221
222 error_code = get_physical_address(env, &paddr, &prot, &access_index,
223 address, rw, mmu_idx, &page_size);
224 if (error_code == 0) {
225 vaddr = address & TARGET_PAGE_MASK;
226 paddr &= TARGET_PAGE_MASK;
227 #ifdef DEBUG_MMU
228 printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
229 TARGET_FMT_lx "\n", address, paddr, vaddr);
230 #endif
231 tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
232 return 0;
233 }
234
235 if (env->mmuregs[3]) /* Fault status register */
236 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
237 env->mmuregs[3] |= (access_index << 5) | error_code | 2;
238 env->mmuregs[4] = address; /* Fault address register */
239
240 if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) {
241 // No fault mode: if a mapping is available, just override
242 // permissions. If no mapping is available, redirect accesses to
243 // neverland. Fake/overridden mappings will be flushed when
244 // switching to normal mode.
245 vaddr = address & TARGET_PAGE_MASK;
246 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
247 tlb_set_page(env, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);
248 return 0;
249 } else {
250 if (rw & 2)
251 env->exception_index = TT_TFAULT;
252 else
253 env->exception_index = TT_DFAULT;
254 return 1;
255 }
256 }
257
258 target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
259 {
260 target_phys_addr_t pde_ptr;
261 uint32_t pde;
262
263 /* Context base + context number */
264 pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
265 (env->mmuregs[2] << 2);
266 pde = ldl_phys(pde_ptr);
267
268 switch (pde & PTE_ENTRYTYPE_MASK) {
269 default:
270 case 0: /* Invalid */
271 case 2: /* PTE, maybe should not happen? */
272 case 3: /* Reserved */
273 return 0;
274 case 1: /* L1 PDE */
275 if (mmulev == 3)
276 return pde;
277 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
278 pde = ldl_phys(pde_ptr);
279
280 switch (pde & PTE_ENTRYTYPE_MASK) {
281 default:
282 case 0: /* Invalid */
283 case 3: /* Reserved */
284 return 0;
285 case 2: /* L1 PTE */
286 return pde;
287 case 1: /* L2 PDE */
288 if (mmulev == 2)
289 return pde;
290 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
291 pde = ldl_phys(pde_ptr);
292
293 switch (pde & PTE_ENTRYTYPE_MASK) {
294 default:
295 case 0: /* Invalid */
296 case 3: /* Reserved */
297 return 0;
298 case 2: /* L2 PTE */
299 return pde;
300 case 1: /* L3 PDE */
301 if (mmulev == 1)
302 return pde;
303 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
304 pde = ldl_phys(pde_ptr);
305
306 switch (pde & PTE_ENTRYTYPE_MASK) {
307 default:
308 case 0: /* Invalid */
309 case 1: /* PDE, should not happen */
310 case 3: /* Reserved */
311 return 0;
312 case 2: /* L3 PTE */
313 return pde;
314 }
315 }
316 }
317 }
318 return 0;
319 }
320
321 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
322 {
323 target_ulong va, va1, va2;
324 unsigned int n, m, o;
325 target_phys_addr_t pde_ptr, pa;
326 uint32_t pde;
327
328 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
329 pde = ldl_phys(pde_ptr);
330 (*cpu_fprintf)(f, "Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
331 (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
332 for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
333 pde = mmu_probe(env, va, 2);
334 if (pde) {
335 pa = cpu_get_phys_page_debug(env, va);
336 (*cpu_fprintf)(f, "VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
337 " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
338 for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
339 pde = mmu_probe(env, va1, 1);
340 if (pde) {
341 pa = cpu_get_phys_page_debug(env, va1);
342 (*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: "
343 TARGET_FMT_plx " PDE: " TARGET_FMT_lx "\n",
344 va1, pa, pde);
345 for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
346 pde = mmu_probe(env, va2, 0);
347 if (pde) {
348 pa = cpu_get_phys_page_debug(env, va2);
349 (*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: "
350 TARGET_FMT_plx " PTE: "
351 TARGET_FMT_lx "\n",
352 va2, pa, pde);
353 }
354 }
355 }
356 }
357 }
358 }
359 }
360
361 #else /* !TARGET_SPARC64 */
362
363 // 41 bit physical address space
364 static inline target_phys_addr_t ultrasparc_truncate_physical(uint64_t x)
365 {
366 return x & 0x1ffffffffffULL;
367 }
368
369 /*
370 * UltraSparc IIi I/DMMUs
371 */
372
373 // Returns true if TTE tag is valid and matches virtual address value in context
374 // requires virtual address mask value calculated from TTE entry size
375 static inline int ultrasparc_tag_match(SparcTLBEntry *tlb,
376 uint64_t address, uint64_t context,
377 target_phys_addr_t *physical)
378 {
379 uint64_t mask;
380
381 switch (TTE_PGSIZE(tlb->tte)) {
382 default:
383 case 0x0: // 8k
384 mask = 0xffffffffffffe000ULL;
385 break;
386 case 0x1: // 64k
387 mask = 0xffffffffffff0000ULL;
388 break;
389 case 0x2: // 512k
390 mask = 0xfffffffffff80000ULL;
391 break;
392 case 0x3: // 4M
393 mask = 0xffffffffffc00000ULL;
394 break;
395 }
396
397 // valid, context match, virtual address match?
398 if (TTE_IS_VALID(tlb->tte) &&
399 (TTE_IS_GLOBAL(tlb->tte) || tlb_compare_context(tlb, context))
400 && compare_masked(address, tlb->tag, mask))
401 {
402 // decode physical address
403 *physical = ((tlb->tte & mask) | (address & ~mask)) & 0x1ffffffe000ULL;
404 return 1;
405 }
406
407 return 0;
408 }
409
410 static int get_physical_address_data(CPUState *env,
411 target_phys_addr_t *physical, int *prot,
412 target_ulong address, int rw, int mmu_idx)
413 {
414 unsigned int i;
415 uint64_t context;
416 uint64_t sfsr = 0;
417
418 int is_user = (mmu_idx == MMU_USER_IDX ||
419 mmu_idx == MMU_USER_SECONDARY_IDX);
420
421 if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
422 *physical = ultrasparc_truncate_physical(address);
423 *prot = PAGE_READ | PAGE_WRITE;
424 return 0;
425 }
426
427 switch(mmu_idx) {
428 case MMU_USER_IDX:
429 case MMU_KERNEL_IDX:
430 context = env->dmmu.mmu_primary_context & 0x1fff;
431 sfsr |= SFSR_CT_PRIMARY;
432 break;
433 case MMU_USER_SECONDARY_IDX:
434 case MMU_KERNEL_SECONDARY_IDX:
435 context = env->dmmu.mmu_secondary_context & 0x1fff;
436 sfsr |= SFSR_CT_SECONDARY;
437 break;
438 case MMU_NUCLEUS_IDX:
439 sfsr |= SFSR_CT_NUCLEUS;
440 /* FALLTHRU */
441 default:
442 context = 0;
443 break;
444 }
445
446 if (rw == 1) {
447 sfsr |= SFSR_WRITE_BIT;
448 }
449
450 for (i = 0; i < 64; i++) {
451 // ctx match, vaddr match, valid?
452 if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) {
453
454 // access ok?
455 if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) {
456 sfsr |= SFSR_FT_PRIV_BIT; /* privilege violation */
457 env->exception_index = TT_DFAULT;
458
459 DPRINTF_MMU("DFAULT at %" PRIx64 " context %" PRIx64
460 " mmu_idx=%d tl=%d\n",
461 address, context, mmu_idx, env->tl);
462 } else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) {
463 env->exception_index = TT_DPROT;
464
465 DPRINTF_MMU("DPROT at %" PRIx64 " context %" PRIx64
466 " mmu_idx=%d tl=%d\n",
467 address, context, mmu_idx, env->tl);
468 } else {
469 *prot = PAGE_READ;
470 if (TTE_IS_W_OK(env->dtlb[i].tte)) {
471 *prot |= PAGE_WRITE;
472 }
473
474 TTE_SET_USED(env->dtlb[i].tte);
475
476 return 0;
477 }
478
479 if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */
480 sfsr |= SFSR_OW_BIT; /* overflow (not read before
481 another fault) */
482 }
483
484 if (env->pstate & PS_PRIV) {
485 sfsr |= SFSR_PR_BIT;
486 }
487
488 /* FIXME: ASI field in SFSR must be set */
489 env->dmmu.sfsr = sfsr | SFSR_VALID_BIT;
490
491 env->dmmu.sfar = address; /* Fault address register */
492
493 env->dmmu.tag_access = (address & ~0x1fffULL) | context;
494
495 return 1;
496 }
497 }
498
499 DPRINTF_MMU("DMISS at %" PRIx64 " context %" PRIx64 "\n",
500 address, context);
501
502 /*
503 * On MMU misses:
504 * - UltraSPARC IIi: SFSR and SFAR unmodified
505 * - JPS1: SFAR updated and some fields of SFSR updated
506 */
507 env->dmmu.tag_access = (address & ~0x1fffULL) | context;
508 env->exception_index = TT_DMISS;
509 return 1;
510 }
511
512 static int get_physical_address_code(CPUState *env,
513 target_phys_addr_t *physical, int *prot,
514 target_ulong address, int mmu_idx)
515 {
516 unsigned int i;
517 uint64_t context;
518
519 int is_user = (mmu_idx == MMU_USER_IDX ||
520 mmu_idx == MMU_USER_SECONDARY_IDX);
521
522 if ((env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0) {
523 /* IMMU disabled */
524 *physical = ultrasparc_truncate_physical(address);
525 *prot = PAGE_EXEC;
526 return 0;
527 }
528
529 if (env->tl == 0) {
530 /* PRIMARY context */
531 context = env->dmmu.mmu_primary_context & 0x1fff;
532 } else {
533 /* NUCLEUS context */
534 context = 0;
535 }
536
537 for (i = 0; i < 64; i++) {
538 // ctx match, vaddr match, valid?
539 if (ultrasparc_tag_match(&env->itlb[i],
540 address, context, physical)) {
541 // access ok?
542 if (TTE_IS_PRIV(env->itlb[i].tte) && is_user) {
543 /* Fault status register */
544 if (env->immu.sfsr & SFSR_VALID_BIT) {
545 env->immu.sfsr = SFSR_OW_BIT; /* overflow (not read before
546 another fault) */
547 } else {
548 env->immu.sfsr = 0;
549 }
550 if (env->pstate & PS_PRIV) {
551 env->immu.sfsr |= SFSR_PR_BIT;
552 }
553 if (env->tl > 0) {
554 env->immu.sfsr |= SFSR_CT_NUCLEUS;
555 }
556
557 /* FIXME: ASI field in SFSR must be set */
558 env->immu.sfsr |= SFSR_FT_PRIV_BIT | SFSR_VALID_BIT;
559 env->exception_index = TT_TFAULT;
560
561 env->immu.tag_access = (address & ~0x1fffULL) | context;
562
563 DPRINTF_MMU("TFAULT at %" PRIx64 " context %" PRIx64 "\n",
564 address, context);
565
566 return 1;
567 }
568 *prot = PAGE_EXEC;
569 TTE_SET_USED(env->itlb[i].tte);
570 return 0;
571 }
572 }
573
574 DPRINTF_MMU("TMISS at %" PRIx64 " context %" PRIx64 "\n",
575 address, context);
576
577 /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */
578 env->immu.tag_access = (address & ~0x1fffULL) | context;
579 env->exception_index = TT_TMISS;
580 return 1;
581 }
582
583 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
584 int *prot, int *access_index,
585 target_ulong address, int rw, int mmu_idx,
586 target_ulong *page_size)
587 {
588 /* ??? We treat everything as a small page, then explicitly flush
589 everything when an entry is evicted. */
590 *page_size = TARGET_PAGE_SIZE;
591
592 #if defined (DEBUG_MMU)
593 /* safety net to catch wrong softmmu index use from dynamic code */
594 if (env->tl > 0 && mmu_idx != MMU_NUCLEUS_IDX) {
595 DPRINTF_MMU("get_physical_address %s tl=%d mmu_idx=%d"
596 " primary context=%" PRIx64
597 " secondary context=%" PRIx64
598 " address=%" PRIx64
599 "\n",
600 (rw == 2 ? "CODE" : "DATA"),
601 env->tl, mmu_idx,
602 env->dmmu.mmu_primary_context,
603 env->dmmu.mmu_secondary_context,
604 address);
605 }
606 #endif
607
608 if (rw == 2)
609 return get_physical_address_code(env, physical, prot, address,
610 mmu_idx);
611 else
612 return get_physical_address_data(env, physical, prot, address, rw,
613 mmu_idx);
614 }
615
616 /* Perform address translation */
617 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
618 int mmu_idx, int is_softmmu)
619 {
620 target_ulong virt_addr, vaddr;
621 target_phys_addr_t paddr;
622 target_ulong page_size;
623 int error_code = 0, prot, access_index;
624
625 error_code = get_physical_address(env, &paddr, &prot, &access_index,
626 address, rw, mmu_idx, &page_size);
627 if (error_code == 0) {
628 virt_addr = address & TARGET_PAGE_MASK;
629 vaddr = virt_addr + ((address & TARGET_PAGE_MASK) &
630 (TARGET_PAGE_SIZE - 1));
631
632 DPRINTF_MMU("Translate at %" PRIx64 " -> %" PRIx64 ","
633 " vaddr %" PRIx64
634 " mmu_idx=%d"
635 " tl=%d"
636 " primary context=%" PRIx64
637 " secondary context=%" PRIx64
638 "\n",
639 address, paddr, vaddr, mmu_idx, env->tl,
640 env->dmmu.mmu_primary_context,
641 env->dmmu.mmu_secondary_context);
642
643 tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
644 return 0;
645 }
646 // XXX
647 return 1;
648 }
649
650 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
651 {
652 unsigned int i;
653 const char *mask;
654
655 (*cpu_fprintf)(f, "MMU contexts: Primary: %" PRId64 ", Secondary: %"
656 PRId64 "\n",
657 env->dmmu.mmu_primary_context,
658 env->dmmu.mmu_secondary_context);
659 if ((env->lsu & DMMU_E) == 0) {
660 (*cpu_fprintf)(f, "DMMU disabled\n");
661 } else {
662 (*cpu_fprintf)(f, "DMMU dump\n");
663 for (i = 0; i < 64; i++) {
664 switch (TTE_PGSIZE(env->dtlb[i].tte)) {
665 default:
666 case 0x0:
667 mask = " 8k";
668 break;
669 case 0x1:
670 mask = " 64k";
671 break;
672 case 0x2:
673 mask = "512k";
674 break;
675 case 0x3:
676 mask = " 4M";
677 break;
678 }
679 if (TTE_IS_VALID(env->dtlb[i].tte)) {
680 (*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %" PRIx64
681 ", %s, %s, %s, %s, ctx %" PRId64 " %s\n",
682 i,
683 env->dtlb[i].tag & (uint64_t)~0x1fffULL,
684 TTE_PA(env->dtlb[i].tte),
685 mask,
686 TTE_IS_PRIV(env->dtlb[i].tte) ? "priv" : "user",
687 TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO",
688 TTE_IS_LOCKED(env->dtlb[i].tte) ?
689 "locked" : "unlocked",
690 env->dtlb[i].tag & (uint64_t)0x1fffULL,
691 TTE_IS_GLOBAL(env->dtlb[i].tte)?
692 "global" : "local");
693 }
694 }
695 }
696 if ((env->lsu & IMMU_E) == 0) {
697 (*cpu_fprintf)(f, "IMMU disabled\n");
698 } else {
699 (*cpu_fprintf)(f, "IMMU dump\n");
700 for (i = 0; i < 64; i++) {
701 switch (TTE_PGSIZE(env->itlb[i].tte)) {
702 default:
703 case 0x0:
704 mask = " 8k";
705 break;
706 case 0x1:
707 mask = " 64k";
708 break;
709 case 0x2:
710 mask = "512k";
711 break;
712 case 0x3:
713 mask = " 4M";
714 break;
715 }
716 if (TTE_IS_VALID(env->itlb[i].tte)) {
717 (*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %" PRIx64
718 ", %s, %s, %s, ctx %" PRId64 " %s\n",
719 i,
720 env->itlb[i].tag & (uint64_t)~0x1fffULL,
721 TTE_PA(env->itlb[i].tte),
722 mask,
723 TTE_IS_PRIV(env->itlb[i].tte) ? "priv" : "user",
724 TTE_IS_LOCKED(env->itlb[i].tte) ?
725 "locked" : "unlocked",
726 env->itlb[i].tag & (uint64_t)0x1fffULL,
727 TTE_IS_GLOBAL(env->itlb[i].tte)?
728 "global" : "local");
729 }
730 }
731 }
732 }
733
734 #endif /* TARGET_SPARC64 */
735 #endif /* !CONFIG_USER_ONLY */
736
737
738 #if !defined(CONFIG_USER_ONLY)
739 static int cpu_sparc_get_phys_page(CPUState *env, target_phys_addr_t *phys,
740 target_ulong addr, int rw, int mmu_idx)
741 {
742 target_ulong page_size;
743 int prot, access_index;
744
745 return get_physical_address(env, phys, &prot, &access_index, addr, rw,
746 mmu_idx, &page_size);
747 }
748
749 #if defined(TARGET_SPARC64)
750 target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
751 int mmu_idx)
752 {
753 target_phys_addr_t phys_addr;
754
755 if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != 0) {
756 return -1;
757 }
758 return phys_addr;
759 }
760 #endif
761
762 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
763 {
764 target_phys_addr_t phys_addr;
765 int mmu_idx = cpu_mmu_index(env);
766
767 if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 2, mmu_idx) != 0) {
768 if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != 0) {
769 return -1;
770 }
771 }
772 if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED) {
773 return -1;
774 }
775 return phys_addr;
776 }
777 #endif
778
779 #ifdef TARGET_SPARC64
780 #ifdef DEBUG_PCALL
781 static const char * const excp_names[0x80] = {
782 [TT_TFAULT] = "Instruction Access Fault",
783 [TT_TMISS] = "Instruction Access MMU Miss",
784 [TT_CODE_ACCESS] = "Instruction Access Error",
785 [TT_ILL_INSN] = "Illegal Instruction",
786 [TT_PRIV_INSN] = "Privileged Instruction",
787 [TT_NFPU_INSN] = "FPU Disabled",
788 [TT_FP_EXCP] = "FPU Exception",
789 [TT_TOVF] = "Tag Overflow",
790 [TT_CLRWIN] = "Clean Windows",
791 [TT_DIV_ZERO] = "Division By Zero",
792 [TT_DFAULT] = "Data Access Fault",
793 [TT_DMISS] = "Data Access MMU Miss",
794 [TT_DATA_ACCESS] = "Data Access Error",
795 [TT_DPROT] = "Data Protection Error",
796 [TT_UNALIGNED] = "Unaligned Memory Access",
797 [TT_PRIV_ACT] = "Privileged Action",
798 [TT_EXTINT | 0x1] = "External Interrupt 1",
799 [TT_EXTINT | 0x2] = "External Interrupt 2",
800 [TT_EXTINT | 0x3] = "External Interrupt 3",
801 [TT_EXTINT | 0x4] = "External Interrupt 4",
802 [TT_EXTINT | 0x5] = "External Interrupt 5",
803 [TT_EXTINT | 0x6] = "External Interrupt 6",
804 [TT_EXTINT | 0x7] = "External Interrupt 7",
805 [TT_EXTINT | 0x8] = "External Interrupt 8",
806 [TT_EXTINT | 0x9] = "External Interrupt 9",
807 [TT_EXTINT | 0xa] = "External Interrupt 10",
808 [TT_EXTINT | 0xb] = "External Interrupt 11",
809 [TT_EXTINT | 0xc] = "External Interrupt 12",
810 [TT_EXTINT | 0xd] = "External Interrupt 13",
811 [TT_EXTINT | 0xe] = "External Interrupt 14",
812 [TT_EXTINT | 0xf] = "External Interrupt 15",
813 };
814 #endif
815
816 void do_interrupt(CPUState *env)
817 {
818 int intno = env->exception_index;
819 trap_state *tsptr;
820
821 #ifdef DEBUG_PCALL
822 if (qemu_loglevel_mask(CPU_LOG_INT)) {
823 static int count;
824 const char *name;
825
826 if (intno < 0 || intno >= 0x180) {
827 name = "Unknown";
828 } else if (intno >= 0x100) {
829 name = "Trap Instruction";
830 } else if (intno >= 0xc0) {
831 name = "Window Fill";
832 } else if (intno >= 0x80) {
833 name = "Window Spill";
834 } else {
835 name = excp_names[intno];
836 if (!name) {
837 name = "Unknown";
838 }
839 }
840
841 qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
842 " SP=%016" PRIx64 "\n",
843 count, name, intno,
844 env->pc,
845 env->npc, env->regwptr[6]);
846 log_cpu_state(env, 0);
847 #if 0
848 {
849 int i;
850 uint8_t *ptr;
851
852 qemu_log(" code=");
853 ptr = (uint8_t *)env->pc;
854 for (i = 0; i < 16; i++) {
855 qemu_log(" %02x", ldub(ptr + i));
856 }
857 qemu_log("\n");
858 }
859 #endif
860 count++;
861 }
862 #endif
863 #if !defined(CONFIG_USER_ONLY)
864 if (env->tl >= env->maxtl) {
865 cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
866 " Error state", env->exception_index, env->tl, env->maxtl);
867 return;
868 }
869 #endif
870 if (env->tl < env->maxtl - 1) {
871 env->tl++;
872 } else {
873 env->pstate |= PS_RED;
874 if (env->tl < env->maxtl) {
875 env->tl++;
876 }
877 }
878 tsptr = cpu_tsptr(env);
879
880 tsptr->tstate = (cpu_get_ccr(env) << 32) |
881 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
882 cpu_get_cwp64(env);
883 tsptr->tpc = env->pc;
884 tsptr->tnpc = env->npc;
885 tsptr->tt = intno;
886
887 switch (intno) {
888 case TT_IVEC:
889 cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_IG);
890 break;
891 case TT_TFAULT:
892 case TT_DFAULT:
893 case TT_TMISS ... TT_TMISS + 3:
894 case TT_DMISS ... TT_DMISS + 3:
895 case TT_DPROT ... TT_DPROT + 3:
896 cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_MG);
897 break;
898 default:
899 cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_AG);
900 break;
901 }
902
903 if (intno == TT_CLRWIN) {
904 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
905 } else if ((intno & 0x1c0) == TT_SPILL) {
906 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
907 } else if ((intno & 0x1c0) == TT_FILL) {
908 cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
909 }
910 env->tbr &= ~0x7fffULL;
911 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
912 env->pc = env->tbr;
913 env->npc = env->pc + 4;
914 env->exception_index = -1;
915 }
916 #else
917 #ifdef DEBUG_PCALL
918 static const char * const excp_names[0x80] = {
919 [TT_TFAULT] = "Instruction Access Fault",
920 [TT_ILL_INSN] = "Illegal Instruction",
921 [TT_PRIV_INSN] = "Privileged Instruction",
922 [TT_NFPU_INSN] = "FPU Disabled",
923 [TT_WIN_OVF] = "Window Overflow",
924 [TT_WIN_UNF] = "Window Underflow",
925 [TT_UNALIGNED] = "Unaligned Memory Access",
926 [TT_FP_EXCP] = "FPU Exception",
927 [TT_DFAULT] = "Data Access Fault",
928 [TT_TOVF] = "Tag Overflow",
929 [TT_EXTINT | 0x1] = "External Interrupt 1",
930 [TT_EXTINT | 0x2] = "External Interrupt 2",
931 [TT_EXTINT | 0x3] = "External Interrupt 3",
932 [TT_EXTINT | 0x4] = "External Interrupt 4",
933 [TT_EXTINT | 0x5] = "External Interrupt 5",
934 [TT_EXTINT | 0x6] = "External Interrupt 6",
935 [TT_EXTINT | 0x7] = "External Interrupt 7",
936 [TT_EXTINT | 0x8] = "External Interrupt 8",
937 [TT_EXTINT | 0x9] = "External Interrupt 9",
938 [TT_EXTINT | 0xa] = "External Interrupt 10",
939 [TT_EXTINT | 0xb] = "External Interrupt 11",
940 [TT_EXTINT | 0xc] = "External Interrupt 12",
941 [TT_EXTINT | 0xd] = "External Interrupt 13",
942 [TT_EXTINT | 0xe] = "External Interrupt 14",
943 [TT_EXTINT | 0xf] = "External Interrupt 15",
944 [TT_TOVF] = "Tag Overflow",
945 [TT_CODE_ACCESS] = "Instruction Access Error",
946 [TT_DATA_ACCESS] = "Data Access Error",
947 [TT_DIV_ZERO] = "Division By Zero",
948 [TT_NCP_INSN] = "Coprocessor Disabled",
949 };
950 #endif
951
952 void do_interrupt(CPUState *env)
953 {
954 int cwp, intno = env->exception_index;
955
956 #ifdef DEBUG_PCALL
957 if (qemu_loglevel_mask(CPU_LOG_INT)) {
958 static int count;
959 const char *name;
960
961 if (intno < 0 || intno >= 0x100) {
962 name = "Unknown";
963 } else if (intno >= 0x80) {
964 name = "Trap Instruction";
965 } else {
966 name = excp_names[intno];
967 if (!name) {
968 name = "Unknown";
969 }
970 }
971
972 qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
973 count, name, intno,
974 env->pc,
975 env->npc, env->regwptr[6]);
976 log_cpu_state(env, 0);
977 #if 0
978 {
979 int i;
980 uint8_t *ptr;
981
982 qemu_log(" code=");
983 ptr = (uint8_t *)env->pc;
984 for (i = 0; i < 16; i++) {
985 qemu_log(" %02x", ldub(ptr + i));
986 }
987 qemu_log("\n");
988 }
989 #endif
990 count++;
991 }
992 #endif
993 #if !defined(CONFIG_USER_ONLY)
994 if (env->psret == 0) {
995 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
996 env->exception_index);
997 return;
998 }
999 #endif
1000 env->psret = 0;
1001 cwp = cpu_cwp_dec(env, env->cwp - 1);
1002 cpu_set_cwp(env, cwp);
1003 env->regwptr[9] = env->pc;
1004 env->regwptr[10] = env->npc;
1005 env->psrps = env->psrs;
1006 env->psrs = 1;
1007 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
1008 env->pc = env->tbr;
1009 env->npc = env->pc + 4;
1010 env->exception_index = -1;
1011
1012 #if !defined(CONFIG_USER_ONLY)
1013 /* IRQ acknowledgment */
1014 if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) {
1015 env->qemu_irq_ack(env->irq_manager, intno);
1016 }
1017 #endif
1018 }
1019 #endif
1020
1021 void cpu_reset(CPUSPARCState *env)
1022 {
1023 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1024 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1025 log_cpu_state(env, 0);
1026 }
1027
1028 tlb_flush(env, 1);
1029 env->cwp = 0;
1030 #ifndef TARGET_SPARC64
1031 env->wim = 1;
1032 #endif
1033 env->regwptr = env->regbase + (env->cwp * 16);
1034 CC_OP = CC_OP_FLAGS;
1035 #if defined(CONFIG_USER_ONLY)
1036 #ifdef TARGET_SPARC64
1037 env->cleanwin = env->nwindows - 2;
1038 env->cansave = env->nwindows - 2;
1039 env->pstate = PS_RMO | PS_PEF | PS_IE;
1040 env->asi = 0x82; // Primary no-fault
1041 #endif
1042 #else
1043 #if !defined(TARGET_SPARC64)
1044 env->psret = 0;
1045 env->psrs = 1;
1046 env->psrps = 1;
1047 #endif
1048 #ifdef TARGET_SPARC64
1049 env->pstate = PS_PRIV|PS_RED|PS_PEF|PS_AG;
1050 env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;
1051 env->tl = env->maxtl;
1052 cpu_tsptr(env)->tt = TT_POWER_ON_RESET;
1053 env->lsu = 0;
1054 #else
1055 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
1056 env->mmuregs[0] |= env->def->mmu_bm;
1057 #endif
1058 env->pc = 0;
1059 env->npc = env->pc + 4;
1060 #endif
1061 env->cache_control = 0;
1062 }
1063
1064 static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
1065 {
1066 sparc_def_t def1, *def = &def1;
1067
1068 if (cpu_sparc_find_by_name(def, cpu_model) < 0)
1069 return -1;
1070
1071 env->def = qemu_mallocz(sizeof(*def));
1072 memcpy(env->def, def, sizeof(*def));
1073 #if defined(CONFIG_USER_ONLY)
1074 if ((env->def->features & CPU_FEATURE_FLOAT))
1075 env->def->features |= CPU_FEATURE_FLOAT128;
1076 #endif
1077 env->cpu_model_str = cpu_model;
1078 env->version = def->iu_version;
1079 env->fsr = def->fpu_version;
1080 env->nwindows = def->nwindows;
1081 #if !defined(TARGET_SPARC64)
1082 env->mmuregs[0] |= def->mmu_version;
1083 cpu_sparc_set_id(env, 0);
1084 env->mxccregs[7] |= def->mxcc_version;
1085 #else
1086 env->mmu_version = def->mmu_version;
1087 env->maxtl = def->maxtl;
1088 env->version |= def->maxtl << 8;
1089 env->version |= def->nwindows - 1;
1090 #endif
1091 return 0;
1092 }
1093
1094 static void cpu_sparc_close(CPUSPARCState *env)
1095 {
1096 free(env->def);
1097 free(env);
1098 }
1099
1100 CPUSPARCState *cpu_sparc_init(const char *cpu_model)
1101 {
1102 CPUSPARCState *env;
1103
1104 env = qemu_mallocz(sizeof(CPUSPARCState));
1105 cpu_exec_init(env);
1106
1107 gen_intermediate_code_init(env);
1108
1109 if (cpu_sparc_register(env, cpu_model) < 0) {
1110 cpu_sparc_close(env);
1111 return NULL;
1112 }
1113 qemu_init_vcpu(env);
1114
1115 return env;
1116 }
1117
1118 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
1119 {
1120 #if !defined(TARGET_SPARC64)
1121 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
1122 #endif
1123 }
1124
1125 static const sparc_def_t sparc_defs[] = {
1126 #ifdef TARGET_SPARC64
1127 {
1128 .name = "Fujitsu Sparc64",
1129 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
1130 .fpu_version = 0x00000000,
1131 .mmu_version = mmu_us_12,
1132 .nwindows = 4,
1133 .maxtl = 4,
1134 .features = CPU_DEFAULT_FEATURES,
1135 },
1136 {
1137 .name = "Fujitsu Sparc64 III",
1138 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
1139 .fpu_version = 0x00000000,
1140 .mmu_version = mmu_us_12,
1141 .nwindows = 5,
1142 .maxtl = 4,
1143 .features = CPU_DEFAULT_FEATURES,
1144 },
1145 {
1146 .name = "Fujitsu Sparc64 IV",
1147 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
1148 .fpu_version = 0x00000000,
1149 .mmu_version = mmu_us_12,
1150 .nwindows = 8,
1151 .maxtl = 5,
1152 .features = CPU_DEFAULT_FEATURES,
1153 },
1154 {
1155 .name = "Fujitsu Sparc64 V",
1156 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
1157 .fpu_version = 0x00000000,
1158 .mmu_version = mmu_us_12,
1159 .nwindows = 8,
1160 .maxtl = 5,
1161 .features = CPU_DEFAULT_FEATURES,
1162 },
1163 {
1164 .name = "TI UltraSparc I",
1165 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
1166 .fpu_version = 0x00000000,
1167 .mmu_version = mmu_us_12,
1168 .nwindows = 8,
1169 .maxtl = 5,
1170 .features = CPU_DEFAULT_FEATURES,
1171 },
1172 {
1173 .name = "TI UltraSparc II",
1174 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
1175 .fpu_version = 0x00000000,
1176 .mmu_version = mmu_us_12,
1177 .nwindows = 8,
1178 .maxtl = 5,
1179 .features = CPU_DEFAULT_FEATURES,
1180 },
1181 {
1182 .name = "TI UltraSparc IIi",
1183 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
1184 .fpu_version = 0x00000000,
1185 .mmu_version = mmu_us_12,
1186 .nwindows = 8,
1187 .maxtl = 5,
1188 .features = CPU_DEFAULT_FEATURES,
1189 },
1190 {
1191 .name = "TI UltraSparc IIe",
1192 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
1193 .fpu_version = 0x00000000,
1194 .mmu_version = mmu_us_12,
1195 .nwindows = 8,
1196 .maxtl = 5,
1197 .features = CPU_DEFAULT_FEATURES,
1198 },
1199 {
1200 .name = "Sun UltraSparc III",
1201 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
1202 .fpu_version = 0x00000000,
1203 .mmu_version = mmu_us_12,
1204 .nwindows = 8,
1205 .maxtl = 5,
1206 .features = CPU_DEFAULT_FEATURES,
1207 },
1208 {
1209 .name = "Sun UltraSparc III Cu",
1210 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
1211 .fpu_version = 0x00000000,
1212 .mmu_version = mmu_us_3,
1213 .nwindows = 8,
1214 .maxtl = 5,
1215 .features = CPU_DEFAULT_FEATURES,
1216 },
1217 {
1218 .name = "Sun UltraSparc IIIi",
1219 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
1220 .fpu_version = 0x00000000,
1221 .mmu_version = mmu_us_12,
1222 .nwindows = 8,
1223 .maxtl = 5,
1224 .features = CPU_DEFAULT_FEATURES,
1225 },
1226 {
1227 .name = "Sun UltraSparc IV",
1228 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
1229 .fpu_version = 0x00000000,
1230 .mmu_version = mmu_us_4,
1231 .nwindows = 8,
1232 .maxtl = 5,
1233 .features = CPU_DEFAULT_FEATURES,
1234 },
1235 {
1236 .name = "Sun UltraSparc IV+",
1237 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
1238 .fpu_version = 0x00000000,
1239 .mmu_version = mmu_us_12,
1240 .nwindows = 8,
1241 .maxtl = 5,
1242 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
1243 },
1244 {
1245 .name = "Sun UltraSparc IIIi+",
1246 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
1247 .fpu_version = 0x00000000,
1248 .mmu_version = mmu_us_3,
1249 .nwindows = 8,
1250 .maxtl = 5,
1251 .features = CPU_DEFAULT_FEATURES,
1252 },
1253 {
1254 .name = "Sun UltraSparc T1",
1255 // defined in sparc_ifu_fdp.v and ctu.h
1256 .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
1257 .fpu_version = 0x00000000,
1258 .mmu_version = mmu_sun4v,
1259 .nwindows = 8,
1260 .maxtl = 6,
1261 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
1262 | CPU_FEATURE_GL,
1263 },
1264 {
1265 .name = "Sun UltraSparc T2",
1266 // defined in tlu_asi_ctl.v and n2_revid_cust.v
1267 .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
1268 .fpu_version = 0x00000000,
1269 .mmu_version = mmu_sun4v,
1270 .nwindows = 8,
1271 .maxtl = 6,
1272 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
1273 | CPU_FEATURE_GL,
1274 },
1275 {
1276 .name = "NEC UltraSparc I",
1277 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
1278 .fpu_version = 0x00000000,
1279 .mmu_version = mmu_us_12,
1280 .nwindows = 8,
1281 .maxtl = 5,
1282 .features = CPU_DEFAULT_FEATURES,
1283 },
1284 #else
1285 {
1286 .name = "Fujitsu MB86900",
1287 .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
1288 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1289 .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
1290 .mmu_bm = 0x00004000,
1291 .mmu_ctpr_mask = 0x007ffff0,
1292 .mmu_cxr_mask = 0x0000003f,
1293 .mmu_sfsr_mask = 0xffffffff,
1294 .mmu_trcr_mask = 0xffffffff,
1295 .nwindows = 7,
1296 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD,
1297 },
1298 {
1299 .name = "Fujitsu MB86904",
1300 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
1301 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1302 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
1303 .mmu_bm = 0x00004000,
1304 .mmu_ctpr_mask = 0x00ffffc0,
1305 .mmu_cxr_mask = 0x000000ff,
1306 .mmu_sfsr_mask = 0x00016fff,
1307 .mmu_trcr_mask = 0x00ffffff,
1308 .nwindows = 8,
1309 .features = CPU_DEFAULT_FEATURES,
1310 },
1311 {
1312 .name = "Fujitsu MB86907",
1313 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
1314 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1315 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
1316 .mmu_bm = 0x00004000,
1317 .mmu_ctpr_mask = 0xffffffc0,
1318 .mmu_cxr_mask = 0x000000ff,
1319 .mmu_sfsr_mask = 0x00016fff,
1320 .mmu_trcr_mask = 0xffffffff,
1321 .nwindows = 8,
1322 .features = CPU_DEFAULT_FEATURES,
1323 },
1324 {
1325 .name = "LSI L64811",
1326 .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
1327 .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
1328 .mmu_version = 0x10 << 24,
1329 .mmu_bm = 0x00004000,
1330 .mmu_ctpr_mask = 0x007ffff0,
1331 .mmu_cxr_mask = 0x0000003f,
1332 .mmu_sfsr_mask = 0xffffffff,
1333 .mmu_trcr_mask = 0xffffffff,
1334 .nwindows = 8,
1335 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1336 CPU_FEATURE_FSMULD,
1337 },
1338 {
1339 .name = "Cypress CY7C601",
1340 .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
1341 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
1342 .mmu_version = 0x10 << 24,
1343 .mmu_bm = 0x00004000,
1344 .mmu_ctpr_mask = 0x007ffff0,
1345 .mmu_cxr_mask = 0x0000003f,
1346 .mmu_sfsr_mask = 0xffffffff,
1347 .mmu_trcr_mask = 0xffffffff,
1348 .nwindows = 8,
1349 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1350 CPU_FEATURE_FSMULD,
1351 },
1352 {
1353 .name = "Cypress CY7C611",
1354 .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
1355 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
1356 .mmu_version = 0x10 << 24,
1357 .mmu_bm = 0x00004000,
1358 .mmu_ctpr_mask = 0x007ffff0,
1359 .mmu_cxr_mask = 0x0000003f,
1360 .mmu_sfsr_mask = 0xffffffff,
1361 .mmu_trcr_mask = 0xffffffff,
1362 .nwindows = 8,
1363 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1364 CPU_FEATURE_FSMULD,
1365 },
1366 {
1367 .name = "TI MicroSparc I",
1368 .iu_version = 0x41000000,
1369 .fpu_version = 4 << 17,
1370 .mmu_version = 0x41000000,
1371 .mmu_bm = 0x00004000,
1372 .mmu_ctpr_mask = 0x007ffff0,
1373 .mmu_cxr_mask = 0x0000003f,
1374 .mmu_sfsr_mask = 0x00016fff,
1375 .mmu_trcr_mask = 0x0000003f,
1376 .nwindows = 7,
1377 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
1378 CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
1379 CPU_FEATURE_FMUL,
1380 },
1381 {
1382 .name = "TI MicroSparc II",
1383 .iu_version = 0x42000000,
1384 .fpu_version = 4 << 17,
1385 .mmu_version = 0x02000000,
1386 .mmu_bm = 0x00004000,
1387 .mmu_ctpr_mask = 0x00ffffc0,
1388 .mmu_cxr_mask = 0x000000ff,
1389 .mmu_sfsr_mask = 0x00016fff,
1390 .mmu_trcr_mask = 0x00ffffff,
1391 .nwindows = 8,
1392 .features = CPU_DEFAULT_FEATURES,
1393 },
1394 {
1395 .name = "TI MicroSparc IIep",
1396 .iu_version = 0x42000000,
1397 .fpu_version = 4 << 17,
1398 .mmu_version = 0x04000000,
1399 .mmu_bm = 0x00004000,
1400 .mmu_ctpr_mask = 0x00ffffc0,
1401 .mmu_cxr_mask = 0x000000ff,
1402 .mmu_sfsr_mask = 0x00016bff,
1403 .mmu_trcr_mask = 0x00ffffff,
1404 .nwindows = 8,
1405 .features = CPU_DEFAULT_FEATURES,
1406 },
1407 {
1408 .name = "TI SuperSparc 40", // STP1020NPGA
1409 .iu_version = 0x41000000, // SuperSPARC 2.x
1410 .fpu_version = 0 << 17,
1411 .mmu_version = 0x00000800, // SuperSPARC 2.x, no MXCC
1412 .mmu_bm = 0x00002000,
1413 .mmu_ctpr_mask = 0xffffffc0,
1414 .mmu_cxr_mask = 0x0000ffff,
1415 .mmu_sfsr_mask = 0xffffffff,
1416 .mmu_trcr_mask = 0xffffffff,
1417 .nwindows = 8,
1418 .features = CPU_DEFAULT_FEATURES,
1419 },
1420 {
1421 .name = "TI SuperSparc 50", // STP1020PGA
1422 .iu_version = 0x40000000, // SuperSPARC 3.x
1423 .fpu_version = 0 << 17,
1424 .mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC
1425 .mmu_bm = 0x00002000,
1426 .mmu_ctpr_mask = 0xffffffc0,
1427 .mmu_cxr_mask = 0x0000ffff,
1428 .mmu_sfsr_mask = 0xffffffff,
1429 .mmu_trcr_mask = 0xffffffff,
1430 .nwindows = 8,
1431 .features = CPU_DEFAULT_FEATURES,
1432 },
1433 {
1434 .name = "TI SuperSparc 51",
1435 .iu_version = 0x40000000, // SuperSPARC 3.x
1436 .fpu_version = 0 << 17,
1437 .mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC
1438 .mmu_bm = 0x00002000,
1439 .mmu_ctpr_mask = 0xffffffc0,
1440 .mmu_cxr_mask = 0x0000ffff,
1441 .mmu_sfsr_mask = 0xffffffff,
1442 .mmu_trcr_mask = 0xffffffff,
1443 .mxcc_version = 0x00000104,
1444 .nwindows = 8,
1445 .features = CPU_DEFAULT_FEATURES,
1446 },
1447 {
1448 .name = "TI SuperSparc 60", // STP1020APGA
1449 .iu_version = 0x40000000, // SuperSPARC 3.x
1450 .fpu_version = 0 << 17,
1451 .mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC
1452 .mmu_bm = 0x00002000,
1453 .mmu_ctpr_mask = 0xffffffc0,
1454 .mmu_cxr_mask = 0x0000ffff,
1455 .mmu_sfsr_mask = 0xffffffff,
1456 .mmu_trcr_mask = 0xffffffff,
1457 .nwindows = 8,
1458 .features = CPU_DEFAULT_FEATURES,
1459 },
1460 {
1461 .name = "TI SuperSparc 61",
1462 .iu_version = 0x44000000, // SuperSPARC 3.x
1463 .fpu_version = 0 << 17,
1464 .mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC
1465 .mmu_bm = 0x00002000,
1466 .mmu_ctpr_mask = 0xffffffc0,
1467 .mmu_cxr_mask = 0x0000ffff,
1468 .mmu_sfsr_mask = 0xffffffff,
1469 .mmu_trcr_mask = 0xffffffff,
1470 .mxcc_version = 0x00000104,
1471 .nwindows = 8,
1472 .features = CPU_DEFAULT_FEATURES,
1473 },
1474 {
1475 .name = "TI SuperSparc II",
1476 .iu_version = 0x40000000, // SuperSPARC II 1.x
1477 .fpu_version = 0 << 17,
1478 .mmu_version = 0x08000000, // SuperSPARC II 1.x, MXCC
1479 .mmu_bm = 0x00002000,
1480 .mmu_ctpr_mask = 0xffffffc0,
1481 .mmu_cxr_mask = 0x0000ffff,
1482 .mmu_sfsr_mask = 0xffffffff,
1483 .mmu_trcr_mask = 0xffffffff,
1484 .mxcc_version = 0x00000104,
1485 .nwindows = 8,
1486 .features = CPU_DEFAULT_FEATURES,
1487 },
1488 {
1489 .name = "Ross RT625",
1490 .iu_version = 0x1e000000,
1491 .fpu_version = 1 << 17,
1492 .mmu_version = 0x1e000000,
1493 .mmu_bm = 0x00004000,
1494 .mmu_ctpr_mask = 0x007ffff0,
1495 .mmu_cxr_mask = 0x0000003f,
1496 .mmu_sfsr_mask = 0xffffffff,
1497 .mmu_trcr_mask = 0xffffffff,
1498 .nwindows = 8,
1499 .features = CPU_DEFAULT_FEATURES,
1500 },
1501 {
1502 .name = "Ross RT620",
1503 .iu_version = 0x1f000000,
1504 .fpu_version = 1 << 17,
1505 .mmu_version = 0x1f000000,
1506 .mmu_bm = 0x00004000,
1507 .mmu_ctpr_mask = 0x007ffff0,
1508 .mmu_cxr_mask = 0x0000003f,
1509 .mmu_sfsr_mask = 0xffffffff,
1510 .mmu_trcr_mask = 0xffffffff,
1511 .nwindows = 8,
1512 .features = CPU_DEFAULT_FEATURES,
1513 },
1514 {
1515 .name = "BIT B5010",
1516 .iu_version = 0x20000000,
1517 .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
1518 .mmu_version = 0x20000000,
1519 .mmu_bm = 0x00004000,
1520 .mmu_ctpr_mask = 0x007ffff0,
1521 .mmu_cxr_mask = 0x0000003f,
1522 .mmu_sfsr_mask = 0xffffffff,
1523 .mmu_trcr_mask = 0xffffffff,
1524 .nwindows = 8,
1525 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1526 CPU_FEATURE_FSMULD,
1527 },
1528 {
1529 .name = "Matsushita MN10501",
1530 .iu_version = 0x50000000,
1531 .fpu_version = 0 << 17,
1532 .mmu_version = 0x50000000,
1533 .mmu_bm = 0x00004000,
1534 .mmu_ctpr_mask = 0x007ffff0,
1535 .mmu_cxr_mask = 0x0000003f,
1536 .mmu_sfsr_mask = 0xffffffff,
1537 .mmu_trcr_mask = 0xffffffff,
1538 .nwindows = 8,
1539 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT |
1540 CPU_FEATURE_FSMULD,
1541 },
1542 {
1543 .name = "Weitek W8601",
1544 .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
1545 .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
1546 .mmu_version = 0x10 << 24,
1547 .mmu_bm = 0x00004000,
1548 .mmu_ctpr_mask = 0x007ffff0,
1549 .mmu_cxr_mask = 0x0000003f,
1550 .mmu_sfsr_mask = 0xffffffff,
1551 .mmu_trcr_mask = 0xffffffff,
1552 .nwindows = 8,
1553 .features = CPU_DEFAULT_FEATURES,
1554 },
1555 {
1556 .name = "LEON2",
1557 .iu_version = 0xf2000000,
1558 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1559 .mmu_version = 0xf2000000,
1560 .mmu_bm = 0x00004000,
1561 .mmu_ctpr_mask = 0x007ffff0,
1562 .mmu_cxr_mask = 0x0000003f,
1563 .mmu_sfsr_mask = 0xffffffff,
1564 .mmu_trcr_mask = 0xffffffff,
1565 .nwindows = 8,
1566 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
1567 },
1568 {
1569 .name = "LEON3",
1570 .iu_version = 0xf3000000,
1571 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1572 .mmu_version = 0xf3000000,
1573 .mmu_bm = 0x00000000,
1574 .mmu_ctpr_mask = 0x007ffff0,
1575 .mmu_cxr_mask = 0x0000003f,
1576 .mmu_sfsr_mask = 0xffffffff,
1577 .mmu_trcr_mask = 0xffffffff,
1578 .nwindows = 8,
1579 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
1580 CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL,
1581 },
1582 #endif
1583 };
1584
1585 static const char * const feature_name[] = {
1586 "float",
1587 "float128",
1588 "swap",
1589 "mul",
1590 "div",
1591 "flush",
1592 "fsqrt",
1593 "fmul",
1594 "vis1",
1595 "vis2",
1596 "fsmuld",
1597 "hypv",
1598 "cmt",
1599 "gl",
1600 };
1601
1602 static void print_features(FILE *f, fprintf_function cpu_fprintf,
1603 uint32_t features, const char *prefix)
1604 {
1605 unsigned int i;
1606
1607 for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1608 if (feature_name[i] && (features & (1 << i))) {
1609 if (prefix)
1610 (*cpu_fprintf)(f, "%s", prefix);
1611 (*cpu_fprintf)(f, "%s ", feature_name[i]);
1612 }
1613 }
1614
1615 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
1616 {
1617 unsigned int i;
1618
1619 for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1620 if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
1621 *features |= 1 << i;
1622 return;
1623 }
1624 fprintf(stderr, "CPU feature %s not found\n", flagname);
1625 }
1626
1627 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model)
1628 {
1629 unsigned int i;
1630 const sparc_def_t *def = NULL;
1631 char *s = strdup(cpu_model);
1632 char *featurestr, *name = strtok(s, ",");
1633 uint32_t plus_features = 0;
1634 uint32_t minus_features = 0;
1635 uint64_t iu_version;
1636 uint32_t fpu_version, mmu_version, nwindows;
1637
1638 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
1639 if (strcasecmp(name, sparc_defs[i].name) == 0) {
1640 def = &sparc_defs[i];
1641 }
1642 }
1643 if (!def)
1644 goto error;
1645 memcpy(cpu_def, def, sizeof(*def));
1646
1647 featurestr = strtok(NULL, ",");
1648 while (featurestr) {
1649 char *val;
1650
1651 if (featurestr[0] == '+') {
1652 add_flagname_to_bitmaps(featurestr + 1, &plus_features);
1653 } else if (featurestr[0] == '-') {
1654 add_flagname_to_bitmaps(featurestr + 1, &minus_features);
1655 } else if ((val = strchr(featurestr, '='))) {
1656 *val = 0; val++;
1657 if (!strcmp(featurestr, "iu_version")) {
1658 char *err;
1659
1660 iu_version = strtoll(val, &err, 0);
1661 if (!*val || *err) {
1662 fprintf(stderr, "bad numerical value %s\n", val);
1663 goto error;
1664 }
1665 cpu_def->iu_version = iu_version;
1666 #ifdef DEBUG_FEATURES
1667 fprintf(stderr, "iu_version %" PRIx64 "\n", iu_version);
1668 #endif
1669 } else if (!strcmp(featurestr, "fpu_version")) {
1670 char *err;
1671
1672 fpu_version = strtol(val, &err, 0);
1673 if (!*val || *err) {
1674 fprintf(stderr, "bad numerical value %s\n", val);
1675 goto error;
1676 }
1677 cpu_def->fpu_version = fpu_version;
1678 #ifdef DEBUG_FEATURES
1679 fprintf(stderr, "fpu_version %x\n", fpu_version);
1680 #endif
1681 } else if (!strcmp(featurestr, "mmu_version")) {
1682 char *err;
1683
1684 mmu_version = strtol(val, &err, 0);
1685 if (!*val || *err) {
1686 fprintf(stderr, "bad numerical value %s\n", val);
1687 goto error;
1688 }
1689 cpu_def->mmu_version = mmu_version;
1690 #ifdef DEBUG_FEATURES
1691 fprintf(stderr, "mmu_version %x\n", mmu_version);
1692 #endif
1693 } else if (!strcmp(featurestr, "nwindows")) {
1694 char *err;
1695
1696 nwindows = strtol(val, &err, 0);
1697 if (!*val || *err || nwindows > MAX_NWINDOWS ||
1698 nwindows < MIN_NWINDOWS) {
1699 fprintf(stderr, "bad numerical value %s\n", val);
1700 goto error;
1701 }
1702 cpu_def->nwindows = nwindows;
1703 #ifdef DEBUG_FEATURES
1704 fprintf(stderr, "nwindows %d\n", nwindows);
1705 #endif
1706 } else {
1707 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1708 goto error;
1709 }
1710 } else {
1711 fprintf(stderr, "feature string `%s' not in format "
1712 "(+feature|-feature|feature=xyz)\n", featurestr);
1713 goto error;
1714 }
1715 featurestr = strtok(NULL, ",");
1716 }
1717 cpu_def->features |= plus_features;
1718 cpu_def->features &= ~minus_features;
1719 #ifdef DEBUG_FEATURES
1720 print_features(stderr, fprintf, cpu_def->features, NULL);
1721 #endif
1722 free(s);
1723 return 0;
1724
1725 error:
1726 free(s);
1727 return -1;
1728 }
1729
1730 void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1731 {
1732 unsigned int i;
1733
1734 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
1735 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x NWINS %d ",
1736 sparc_defs[i].name,
1737 sparc_defs[i].iu_version,
1738 sparc_defs[i].fpu_version,
1739 sparc_defs[i].mmu_version,
1740 sparc_defs[i].nwindows);
1741 print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES &
1742 ~sparc_defs[i].features, "-");
1743 print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES &
1744 sparc_defs[i].features, "+");
1745 (*cpu_fprintf)(f, "\n");
1746 }
1747 (*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): ");
1748 print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL);
1749 (*cpu_fprintf)(f, "\n");
1750 (*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): ");
1751 print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL);
1752 (*cpu_fprintf)(f, "\n");
1753 (*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version "
1754 "fpu_version mmu_version nwindows\n");
1755 }
1756
1757 static void cpu_print_cc(FILE *f, fprintf_function cpu_fprintf,
1758 uint32_t cc)
1759 {
1760 cpu_fprintf(f, "%c%c%c%c", cc & PSR_NEG? 'N' : '-',
1761 cc & PSR_ZERO? 'Z' : '-', cc & PSR_OVF? 'V' : '-',
1762 cc & PSR_CARRY? 'C' : '-');
1763 }
1764
1765 #ifdef TARGET_SPARC64
1766 #define REGS_PER_LINE 4
1767 #else
1768 #define REGS_PER_LINE 8
1769 #endif
1770
1771 void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
1772 int flags)
1773 {
1774 int i, x;
1775
1776 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
1777 env->npc);
1778 cpu_fprintf(f, "General Registers:\n");
1779
1780 for (i = 0; i < 8; i++) {
1781 if (i % REGS_PER_LINE == 0) {
1782 cpu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1);
1783 }
1784 cpu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]);
1785 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
1786 cpu_fprintf(f, "\n");
1787 }
1788 }
1789 cpu_fprintf(f, "\nCurrent Register Window:\n");
1790 for (x = 0; x < 3; x++) {
1791 for (i = 0; i < 8; i++) {
1792 if (i % REGS_PER_LINE == 0) {
1793 cpu_fprintf(f, "%%%c%d-%d: ",
1794 x == 0 ? 'o' : (x == 1 ? 'l' : 'i'),
1795 i, i + REGS_PER_LINE - 1);
1796 }
1797 cpu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]);
1798 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
1799 cpu_fprintf(f, "\n");
1800 }
1801 }
1802 }
1803 cpu_fprintf(f, "\nFloating Point Registers:\n");
1804 for (i = 0; i < TARGET_FPREGS; i++) {
1805 if ((i & 3) == 0)
1806 cpu_fprintf(f, "%%f%02d:", i);
1807 cpu_fprintf(f, " %016f", *(float *)&env->fpr[i]);
1808 if ((i & 3) == 3)
1809 cpu_fprintf(f, "\n");
1810 }
1811 #ifdef TARGET_SPARC64
1812 cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
1813 (unsigned)cpu_get_ccr(env));
1814 cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << PSR_CARRY_SHIFT);
1815 cpu_fprintf(f, " xcc: ");
1816 cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4));
1817 cpu_fprintf(f, ") asi: %02x tl: %d pil: %x\n", env->asi, env->tl,
1818 env->psrpil);
1819 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d "
1820 "cleanwin: %d cwp: %d\n",
1821 env->cansave, env->canrestore, env->otherwin, env->wstate,
1822 env->cleanwin, env->nwindows - 1 - env->cwp);
1823 cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: "
1824 TARGET_FMT_lx "\n", env->fsr, env->y, env->fprs);
1825 #else
1826 cpu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env));
1827 cpu_print_cc(f, cpu_fprintf, cpu_get_psr(env));
1828 cpu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs? 'S' : '-',
1829 env->psrps? 'P' : '-', env->psret? 'E' : '-',
1830 env->wim);
1831 cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n",
1832 env->fsr, env->y);
1833 #endif
1834 }
Qemu copy for testing