]>
git.proxmox.com Git - mirror_qemu.git/blob - target-sparc/ldst_helper.c
2 * Helpers for loads and stores
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "dyngen-exec.h"
24 #if !defined(CONFIG_USER_ONLY)
25 #include "softmmu_exec.h"
30 //#define DEBUG_UNALIGNED
31 //#define DEBUG_UNASSIGNED
33 //#define DEBUG_CACHE_CONTROL
36 #define DPRINTF_MMU(fmt, ...) \
37 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
39 #define DPRINTF_MMU(fmt, ...) do {} while (0)
43 #define DPRINTF_MXCC(fmt, ...) \
44 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
46 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
50 #define DPRINTF_ASI(fmt, ...) \
51 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
54 #ifdef DEBUG_CACHE_CONTROL
55 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
56 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
58 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
63 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
65 #define AM_CHECK(env1) (1)
69 #define QT0 (env->qt0)
70 #define QT1 (env->qt1)
72 #if !defined(CONFIG_USER_ONLY)
73 static void do_unassigned_access(target_phys_addr_t addr
, int is_write
,
74 int is_exec
, int is_asi
, int size
);
77 static void do_unassigned_access(target_ulong addr
, int is_write
, int is_exec
,
78 int is_asi
, int size
);
82 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
83 /* Calculates TSB pointer value for fault page size 8k or 64k */
84 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register
,
85 uint64_t tag_access_register
,
88 uint64_t tsb_base
= tsb_register
& ~0x1fffULL
;
89 int tsb_split
= (tsb_register
& 0x1000ULL
) ? 1 : 0;
90 int tsb_size
= tsb_register
& 0xf;
92 /* discard lower 13 bits which hold tag access context */
93 uint64_t tag_access_va
= tag_access_register
& ~0x1fffULL
;
95 /* now reorder bits */
96 uint64_t tsb_base_mask
= ~0x1fffULL
;
97 uint64_t va
= tag_access_va
;
99 /* move va bits to correct position */
100 if (page_size
== 8*1024) {
102 } else if (page_size
== 64*1024) {
107 tsb_base_mask
<<= tsb_size
;
110 /* calculate tsb_base mask and adjust va if split is in use */
112 if (page_size
== 8*1024) {
113 va
&= ~(1ULL << (13 + tsb_size
));
114 } else if (page_size
== 64*1024) {
115 va
|= (1ULL << (13 + tsb_size
));
120 return ((tsb_base
& tsb_base_mask
) | (va
& ~tsb_base_mask
)) & ~0xfULL
;
123 /* Calculates tag target register value by reordering bits
124 in tag access register */
125 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register
)
127 return ((tag_access_register
& 0x1fff) << 48) | (tag_access_register
>> 22);
130 static void replace_tlb_entry(SparcTLBEntry
*tlb
,
131 uint64_t tlb_tag
, uint64_t tlb_tte
,
134 target_ulong mask
, size
, va
, offset
;
136 /* flush page range if translation is valid */
137 if (TTE_IS_VALID(tlb
->tte
)) {
139 mask
= 0xffffffffffffe000ULL
;
140 mask
<<= 3 * ((tlb
->tte
>> 61) & 3);
143 va
= tlb
->tag
& mask
;
145 for (offset
= 0; offset
< size
; offset
+= TARGET_PAGE_SIZE
) {
146 tlb_flush_page(env1
, va
+ offset
);
154 static void demap_tlb(SparcTLBEntry
*tlb
, target_ulong demap_addr
,
155 const char *strmmu
, CPUSPARCState
*env1
)
161 int is_demap_context
= (demap_addr
>> 6) & 1;
164 switch ((demap_addr
>> 4) & 3) {
165 case 0: /* primary */
166 context
= env1
->dmmu
.mmu_primary_context
;
168 case 1: /* secondary */
169 context
= env1
->dmmu
.mmu_secondary_context
;
171 case 2: /* nucleus */
174 case 3: /* reserved */
179 for (i
= 0; i
< 64; i
++) {
180 if (TTE_IS_VALID(tlb
[i
].tte
)) {
182 if (is_demap_context
) {
183 /* will remove non-global entries matching context value */
184 if (TTE_IS_GLOBAL(tlb
[i
].tte
) ||
185 !tlb_compare_context(&tlb
[i
], context
)) {
190 will remove any entry matching VA */
191 mask
= 0xffffffffffffe000ULL
;
192 mask
<<= 3 * ((tlb
[i
].tte
>> 61) & 3);
194 if (!compare_masked(demap_addr
, tlb
[i
].tag
, mask
)) {
198 /* entry should be global or matching context value */
199 if (!TTE_IS_GLOBAL(tlb
[i
].tte
) &&
200 !tlb_compare_context(&tlb
[i
], context
)) {
205 replace_tlb_entry(&tlb
[i
], 0, 0, env1
);
207 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu
, i
);
208 dump_mmu(stdout
, fprintf
, env1
);
214 static void replace_tlb_1bit_lru(SparcTLBEntry
*tlb
,
215 uint64_t tlb_tag
, uint64_t tlb_tte
,
216 const char *strmmu
, CPUSPARCState
*env1
)
218 unsigned int i
, replace_used
;
220 /* Try replacing invalid entry */
221 for (i
= 0; i
< 64; i
++) {
222 if (!TTE_IS_VALID(tlb
[i
].tte
)) {
223 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
225 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu
, i
);
226 dump_mmu(stdout
, fprintf
, env1
);
232 /* All entries are valid, try replacing unlocked entry */
234 for (replace_used
= 0; replace_used
< 2; ++replace_used
) {
236 /* Used entries are not replaced on first pass */
238 for (i
= 0; i
< 64; i
++) {
239 if (!TTE_IS_LOCKED(tlb
[i
].tte
) && !TTE_IS_USED(tlb
[i
].tte
)) {
241 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
243 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
244 strmmu
, (replace_used
? "used" : "unused"), i
);
245 dump_mmu(stdout
, fprintf
, env1
);
251 /* Now reset used bit and search for unused entries again */
253 for (i
= 0; i
< 64; i
++) {
254 TTE_SET_UNUSED(tlb
[i
].tte
);
259 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu
);
266 static inline target_ulong
address_mask(CPUSPARCState
*env1
, target_ulong addr
)
268 #ifdef TARGET_SPARC64
269 if (AM_CHECK(env1
)) {
270 addr
&= 0xffffffffULL
;
276 /* returns true if access using this ASI is to have address translated by MMU
277 otherwise access is to raw physical address */
278 static inline int is_translating_asi(int asi
)
280 #ifdef TARGET_SPARC64
281 /* Ultrasparc IIi translating asi
282 - note this list is defined by cpu implementation
298 /* TODO: check sparc32 bits */
303 static inline target_ulong
asi_address_mask(CPUSPARCState
*env1
,
304 int asi
, target_ulong addr
)
306 if (is_translating_asi(asi
)) {
307 return address_mask(env
, addr
);
313 void helper_check_align(target_ulong addr
, uint32_t align
)
316 #ifdef DEBUG_UNALIGNED
317 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
318 "\n", addr
, env
->pc
);
320 helper_raise_exception(env
, TT_UNALIGNED
);
324 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
326 static void dump_mxcc(CPUSPARCState
*env
)
328 printf("mxccdata: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
330 env
->mxccdata
[0], env
->mxccdata
[1],
331 env
->mxccdata
[2], env
->mxccdata
[3]);
332 printf("mxccregs: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
334 " %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
336 env
->mxccregs
[0], env
->mxccregs
[1],
337 env
->mxccregs
[2], env
->mxccregs
[3],
338 env
->mxccregs
[4], env
->mxccregs
[5],
339 env
->mxccregs
[6], env
->mxccregs
[7]);
343 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
344 && defined(DEBUG_ASI)
345 static void dump_asi(const char *txt
, target_ulong addr
, int asi
, int size
,
350 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %02" PRIx64
"\n", txt
,
351 addr
, asi
, r1
& 0xff);
354 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %04" PRIx64
"\n", txt
,
355 addr
, asi
, r1
& 0xffff);
358 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %08" PRIx64
"\n", txt
,
359 addr
, asi
, r1
& 0xffffffff);
362 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %016" PRIx64
"\n", txt
,
369 #ifndef TARGET_SPARC64
370 #ifndef CONFIG_USER_ONLY
373 /* Leon3 cache control */
375 static void leon3_cache_control_st(target_ulong addr
, uint64_t val
, int size
)
377 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64
", size:%d\n",
381 DPRINTF_CACHE_CONTROL("32bits only\n");
386 case 0x00: /* Cache control */
388 /* These values must always be read as zeros */
389 val
&= ~CACHE_CTRL_FD
;
390 val
&= ~CACHE_CTRL_FI
;
391 val
&= ~CACHE_CTRL_IB
;
392 val
&= ~CACHE_CTRL_IP
;
393 val
&= ~CACHE_CTRL_DP
;
395 env
->cache_control
= val
;
397 case 0x04: /* Instruction cache configuration */
398 case 0x08: /* Data cache configuration */
402 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr
);
407 static uint64_t leon3_cache_control_ld(target_ulong addr
, int size
)
412 DPRINTF_CACHE_CONTROL("32bits only\n");
417 case 0x00: /* Cache control */
418 ret
= env
->cache_control
;
421 /* Configuration registers are read and only always keep those
424 case 0x04: /* Instruction cache configuration */
427 case 0x08: /* Data cache configuration */
431 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr
);
434 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64
", size:%d\n",
439 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
442 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
443 uint32_t last_addr
= addr
;
446 helper_check_align(addr
, size
- 1);
448 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
450 case 0x00: /* Leon3 Cache Control */
451 case 0x08: /* Leon3 Instruction Cache config */
452 case 0x0C: /* Leon3 Date Cache config */
453 if (env
->def
->features
& CPU_FEATURE_CACHE_CTRL
) {
454 ret
= leon3_cache_control_ld(addr
, size
);
457 case 0x01c00a00: /* MXCC control register */
459 ret
= env
->mxccregs
[3];
461 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
465 case 0x01c00a04: /* MXCC control register */
467 ret
= env
->mxccregs
[3];
469 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
473 case 0x01c00c00: /* Module reset register */
475 ret
= env
->mxccregs
[5];
476 /* should we do something here? */
478 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
482 case 0x01c00f00: /* MBus port address register */
484 ret
= env
->mxccregs
[7];
486 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
491 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
495 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
496 "addr = %08x -> ret = %" PRIx64
","
497 "addr = %08x\n", asi
, size
, sign
, last_addr
, ret
, addr
);
502 case 3: /* MMU probe */
506 mmulev
= (addr
>> 8) & 15;
510 ret
= mmu_probe(env
, addr
, mmulev
);
512 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64
"\n",
516 case 4: /* read MMU regs */
518 int reg
= (addr
>> 8) & 0x1f;
520 ret
= env
->mmuregs
[reg
];
521 if (reg
== 3) { /* Fault status cleared on read */
523 } else if (reg
== 0x13) { /* Fault status read */
524 ret
= env
->mmuregs
[3];
525 } else if (reg
== 0x14) { /* Fault address read */
526 ret
= env
->mmuregs
[4];
528 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64
"\n", reg
, ret
);
531 case 5: /* Turbosparc ITLB Diagnostic */
532 case 6: /* Turbosparc DTLB Diagnostic */
533 case 7: /* Turbosparc IOTLB Diagnostic */
535 case 9: /* Supervisor code access */
538 ret
= ldub_code(addr
);
541 ret
= lduw_code(addr
);
545 ret
= ldl_code(addr
);
548 ret
= ldq_code(addr
);
552 case 0xa: /* User data access */
555 ret
= ldub_user(addr
);
558 ret
= lduw_user(addr
);
562 ret
= ldl_user(addr
);
565 ret
= ldq_user(addr
);
569 case 0xb: /* Supervisor data access */
572 ret
= ldub_kernel(addr
);
575 ret
= lduw_kernel(addr
);
579 ret
= ldl_kernel(addr
);
582 ret
= ldq_kernel(addr
);
586 case 0xc: /* I-cache tag */
587 case 0xd: /* I-cache data */
588 case 0xe: /* D-cache tag */
589 case 0xf: /* D-cache data */
591 case 0x20: /* MMU passthrough */
594 ret
= ldub_phys(addr
);
597 ret
= lduw_phys(addr
);
601 ret
= ldl_phys(addr
);
604 ret
= ldq_phys(addr
);
608 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
611 ret
= ldub_phys((target_phys_addr_t
)addr
612 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
615 ret
= lduw_phys((target_phys_addr_t
)addr
616 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
620 ret
= ldl_phys((target_phys_addr_t
)addr
621 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
624 ret
= ldq_phys((target_phys_addr_t
)addr
625 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
629 case 0x30: /* Turbosparc secondary cache diagnostic */
630 case 0x31: /* Turbosparc RAM snoop */
631 case 0x32: /* Turbosparc page table descriptor diagnostic */
632 case 0x39: /* data cache diagnostic register */
635 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
637 int reg
= (addr
>> 8) & 3;
640 case 0: /* Breakpoint Value (Addr) */
641 ret
= env
->mmubpregs
[reg
];
643 case 1: /* Breakpoint Mask */
644 ret
= env
->mmubpregs
[reg
];
646 case 2: /* Breakpoint Control */
647 ret
= env
->mmubpregs
[reg
];
649 case 3: /* Breakpoint Status */
650 ret
= env
->mmubpregs
[reg
];
651 env
->mmubpregs
[reg
] = 0ULL;
654 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64
"\n", reg
,
658 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
659 ret
= env
->mmubpctrv
;
661 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
662 ret
= env
->mmubpctrc
;
664 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
665 ret
= env
->mmubpctrs
;
667 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
668 ret
= env
->mmubpaction
;
670 case 8: /* User code access, XXX */
672 do_unassigned_access(addr
, 0, 0, asi
, size
);
692 dump_asi("read ", last_addr
, asi
, size
, ret
);
697 void helper_st_asi(target_ulong addr
, uint64_t val
, int asi
, int size
)
699 helper_check_align(addr
, size
- 1);
701 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
703 case 0x00: /* Leon3 Cache Control */
704 case 0x08: /* Leon3 Instruction Cache config */
705 case 0x0C: /* Leon3 Date Cache config */
706 if (env
->def
->features
& CPU_FEATURE_CACHE_CTRL
) {
707 leon3_cache_control_st(addr
, val
, size
);
711 case 0x01c00000: /* MXCC stream data register 0 */
713 env
->mxccdata
[0] = val
;
715 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
719 case 0x01c00008: /* MXCC stream data register 1 */
721 env
->mxccdata
[1] = val
;
723 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
727 case 0x01c00010: /* MXCC stream data register 2 */
729 env
->mxccdata
[2] = val
;
731 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
735 case 0x01c00018: /* MXCC stream data register 3 */
737 env
->mxccdata
[3] = val
;
739 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
743 case 0x01c00100: /* MXCC stream source */
745 env
->mxccregs
[0] = val
;
747 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
750 env
->mxccdata
[0] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
752 env
->mxccdata
[1] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
754 env
->mxccdata
[2] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
756 env
->mxccdata
[3] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
759 case 0x01c00200: /* MXCC stream destination */
761 env
->mxccregs
[1] = val
;
763 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
766 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 0,
768 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 8,
770 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 16,
772 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 24,
775 case 0x01c00a00: /* MXCC control register */
777 env
->mxccregs
[3] = val
;
779 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
783 case 0x01c00a04: /* MXCC control register */
785 env
->mxccregs
[3] = (env
->mxccregs
[3] & 0xffffffff00000000ULL
)
788 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
792 case 0x01c00e00: /* MXCC error register */
793 /* writing a 1 bit clears the error */
795 env
->mxccregs
[6] &= ~val
;
797 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
801 case 0x01c00f00: /* MBus port address register */
803 env
->mxccregs
[7] = val
;
805 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
810 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
814 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64
"\n",
815 asi
, size
, addr
, val
);
820 case 3: /* MMU flush */
824 mmulev
= (addr
>> 8) & 15;
825 DPRINTF_MMU("mmu flush level %d\n", mmulev
);
827 case 0: /* flush page */
828 tlb_flush_page(env
, addr
& 0xfffff000);
830 case 1: /* flush segment (256k) */
831 case 2: /* flush region (16M) */
832 case 3: /* flush context (4G) */
833 case 4: /* flush entire */
840 dump_mmu(stdout
, fprintf
, env
);
844 case 4: /* write MMU regs */
846 int reg
= (addr
>> 8) & 0x1f;
849 oldreg
= env
->mmuregs
[reg
];
851 case 0: /* Control Register */
852 env
->mmuregs
[reg
] = (env
->mmuregs
[reg
] & 0xff000000) |
854 /* Mappings generated during no-fault mode or MMU
855 disabled mode are invalid in normal mode */
856 if ((oldreg
& (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)) !=
857 (env
->mmuregs
[reg
] & (MMU_E
| MMU_NF
| env
->def
->mmu_bm
))) {
861 case 1: /* Context Table Pointer Register */
862 env
->mmuregs
[reg
] = val
& env
->def
->mmu_ctpr_mask
;
864 case 2: /* Context Register */
865 env
->mmuregs
[reg
] = val
& env
->def
->mmu_cxr_mask
;
866 if (oldreg
!= env
->mmuregs
[reg
]) {
867 /* we flush when the MMU context changes because
868 QEMU has no MMU context support */
872 case 3: /* Synchronous Fault Status Register with Clear */
873 case 4: /* Synchronous Fault Address Register */
875 case 0x10: /* TLB Replacement Control Register */
876 env
->mmuregs
[reg
] = val
& env
->def
->mmu_trcr_mask
;
878 case 0x13: /* Synchronous Fault Status Register with Read
880 env
->mmuregs
[3] = val
& env
->def
->mmu_sfsr_mask
;
882 case 0x14: /* Synchronous Fault Address Register */
883 env
->mmuregs
[4] = val
;
886 env
->mmuregs
[reg
] = val
;
889 if (oldreg
!= env
->mmuregs
[reg
]) {
890 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
891 reg
, oldreg
, env
->mmuregs
[reg
]);
894 dump_mmu(stdout
, fprintf
, env
);
898 case 5: /* Turbosparc ITLB Diagnostic */
899 case 6: /* Turbosparc DTLB Diagnostic */
900 case 7: /* Turbosparc IOTLB Diagnostic */
902 case 0xa: /* User data access */
919 case 0xb: /* Supervisor data access */
922 stb_kernel(addr
, val
);
925 stw_kernel(addr
, val
);
929 stl_kernel(addr
, val
);
932 stq_kernel(addr
, val
);
936 case 0xc: /* I-cache tag */
937 case 0xd: /* I-cache data */
938 case 0xe: /* D-cache tag */
939 case 0xf: /* D-cache data */
940 case 0x10: /* I/D-cache flush page */
941 case 0x11: /* I/D-cache flush segment */
942 case 0x12: /* I/D-cache flush region */
943 case 0x13: /* I/D-cache flush context */
944 case 0x14: /* I/D-cache flush user */
946 case 0x17: /* Block copy, sta access */
952 uint32_t src
= val
& ~3, dst
= addr
& ~3, temp
;
954 for (i
= 0; i
< 32; i
+= 4, src
+= 4, dst
+= 4) {
955 temp
= ldl_kernel(src
);
956 stl_kernel(dst
, temp
);
960 case 0x1f: /* Block fill, stda access */
963 fill 32 bytes with val */
965 uint32_t dst
= addr
& 7;
967 for (i
= 0; i
< 32; i
+= 8, dst
+= 8) {
968 stq_kernel(dst
, val
);
972 case 0x20: /* MMU passthrough */
991 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
995 stb_phys((target_phys_addr_t
)addr
996 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
999 stw_phys((target_phys_addr_t
)addr
1000 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1004 stl_phys((target_phys_addr_t
)addr
1005 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1008 stq_phys((target_phys_addr_t
)addr
1009 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1014 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1015 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1016 Turbosparc snoop RAM */
1017 case 0x32: /* store buffer control or Turbosparc page table
1018 descriptor diagnostic */
1019 case 0x36: /* I-cache flash clear */
1020 case 0x37: /* D-cache flash clear */
1022 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1024 int reg
= (addr
>> 8) & 3;
1027 case 0: /* Breakpoint Value (Addr) */
1028 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1030 case 1: /* Breakpoint Mask */
1031 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1033 case 2: /* Breakpoint Control */
1034 env
->mmubpregs
[reg
] = (val
& 0x7fULL
);
1036 case 3: /* Breakpoint Status */
1037 env
->mmubpregs
[reg
] = (val
& 0xfULL
);
1040 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg
,
1044 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1045 env
->mmubpctrv
= val
& 0xffffffff;
1047 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1048 env
->mmubpctrc
= val
& 0x3;
1050 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1051 env
->mmubpctrs
= val
& 0x3;
1053 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1054 env
->mmubpaction
= val
& 0x1fff;
1056 case 8: /* User code access, XXX */
1057 case 9: /* Supervisor code access, XXX */
1059 do_unassigned_access(addr
, 1, 0, asi
, size
);
1063 dump_asi("write", addr
, asi
, size
, val
);
1067 #endif /* CONFIG_USER_ONLY */
1068 #else /* TARGET_SPARC64 */
1070 #ifdef CONFIG_USER_ONLY
1071 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
1074 #if defined(DEBUG_ASI)
1075 target_ulong last_addr
= addr
;
1079 helper_raise_exception(env
, TT_PRIV_ACT
);
1082 helper_check_align(addr
, size
- 1);
1083 addr
= asi_address_mask(env
, asi
, addr
);
1086 case 0x82: /* Primary no-fault */
1087 case 0x8a: /* Primary no-fault LE */
1088 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
1090 dump_asi("read ", last_addr
, asi
, size
, ret
);
1095 case 0x80: /* Primary */
1096 case 0x88: /* Primary LE */
1100 ret
= ldub_raw(addr
);
1103 ret
= lduw_raw(addr
);
1106 ret
= ldl_raw(addr
);
1110 ret
= ldq_raw(addr
);
1115 case 0x83: /* Secondary no-fault */
1116 case 0x8b: /* Secondary no-fault LE */
1117 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
1119 dump_asi("read ", last_addr
, asi
, size
, ret
);
1124 case 0x81: /* Secondary */
1125 case 0x89: /* Secondary LE */
1132 /* Convert from little endian */
1134 case 0x88: /* Primary LE */
1135 case 0x89: /* Secondary LE */
1136 case 0x8a: /* Primary no-fault LE */
1137 case 0x8b: /* Secondary no-fault LE */
1155 /* Convert to signed number */
1162 ret
= (int16_t) ret
;
1165 ret
= (int32_t) ret
;
1172 dump_asi("read ", last_addr
, asi
, size
, ret
);
1177 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
1180 dump_asi("write", addr
, asi
, size
, val
);
1183 helper_raise_exception(env
, TT_PRIV_ACT
);
1186 helper_check_align(addr
, size
- 1);
1187 addr
= asi_address_mask(env
, asi
, addr
);
1189 /* Convert to little endian */
1191 case 0x88: /* Primary LE */
1192 case 0x89: /* Secondary LE */
1211 case 0x80: /* Primary */
1212 case 0x88: /* Primary LE */
1231 case 0x81: /* Secondary */
1232 case 0x89: /* Secondary LE */
1236 case 0x82: /* Primary no-fault, RO */
1237 case 0x83: /* Secondary no-fault, RO */
1238 case 0x8a: /* Primary no-fault LE, RO */
1239 case 0x8b: /* Secondary no-fault LE, RO */
1241 do_unassigned_access(addr
, 1, 0, 1, size
);
1246 #else /* CONFIG_USER_ONLY */
1248 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
1251 #if defined(DEBUG_ASI)
1252 target_ulong last_addr
= addr
;
1257 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
1258 || (cpu_has_hypervisor(env
)
1259 && asi
>= 0x30 && asi
< 0x80
1260 && !(env
->hpstate
& HS_PRIV
))) {
1261 helper_raise_exception(env
, TT_PRIV_ACT
);
1264 helper_check_align(addr
, size
- 1);
1265 addr
= asi_address_mask(env
, asi
, addr
);
1267 /* process nonfaulting loads first */
1268 if ((asi
& 0xf6) == 0x82) {
1271 /* secondary space access has lowest asi bit equal to 1 */
1272 if (env
->pstate
& PS_PRIV
) {
1273 mmu_idx
= (asi
& 1) ? MMU_KERNEL_SECONDARY_IDX
: MMU_KERNEL_IDX
;
1275 mmu_idx
= (asi
& 1) ? MMU_USER_SECONDARY_IDX
: MMU_USER_IDX
;
1278 if (cpu_get_phys_page_nofault(env
, addr
, mmu_idx
) == -1ULL) {
1280 dump_asi("read ", last_addr
, asi
, size
, ret
);
1282 /* env->exception_index is set in get_physical_address_data(). */
1283 helper_raise_exception(env
, env
->exception_index
);
1286 /* convert nonfaulting load ASIs to normal load ASIs */
1291 case 0x10: /* As if user primary */
1292 case 0x11: /* As if user secondary */
1293 case 0x18: /* As if user primary LE */
1294 case 0x19: /* As if user secondary LE */
1295 case 0x80: /* Primary */
1296 case 0x81: /* Secondary */
1297 case 0x88: /* Primary LE */
1298 case 0x89: /* Secondary LE */
1299 case 0xe2: /* UA2007 Primary block init */
1300 case 0xe3: /* UA2007 Secondary block init */
1301 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
1302 if (cpu_hypervisor_mode(env
)) {
1305 ret
= ldub_hypv(addr
);
1308 ret
= lduw_hypv(addr
);
1311 ret
= ldl_hypv(addr
);
1315 ret
= ldq_hypv(addr
);
1319 /* secondary space access has lowest asi bit equal to 1 */
1323 ret
= ldub_kernel_secondary(addr
);
1326 ret
= lduw_kernel_secondary(addr
);
1329 ret
= ldl_kernel_secondary(addr
);
1333 ret
= ldq_kernel_secondary(addr
);
1339 ret
= ldub_kernel(addr
);
1342 ret
= lduw_kernel(addr
);
1345 ret
= ldl_kernel(addr
);
1349 ret
= ldq_kernel(addr
);
1355 /* secondary space access has lowest asi bit equal to 1 */
1359 ret
= ldub_user_secondary(addr
);
1362 ret
= lduw_user_secondary(addr
);
1365 ret
= ldl_user_secondary(addr
);
1369 ret
= ldq_user_secondary(addr
);
1375 ret
= ldub_user(addr
);
1378 ret
= lduw_user(addr
);
1381 ret
= ldl_user(addr
);
1385 ret
= ldq_user(addr
);
1391 case 0x14: /* Bypass */
1392 case 0x15: /* Bypass, non-cacheable */
1393 case 0x1c: /* Bypass LE */
1394 case 0x1d: /* Bypass, non-cacheable LE */
1398 ret
= ldub_phys(addr
);
1401 ret
= lduw_phys(addr
);
1404 ret
= ldl_phys(addr
);
1408 ret
= ldq_phys(addr
);
1413 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1414 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1415 Only ldda allowed */
1416 helper_raise_exception(env
, TT_ILL_INSN
);
1418 case 0x04: /* Nucleus */
1419 case 0x0c: /* Nucleus Little Endian (LE) */
1423 ret
= ldub_nucleus(addr
);
1426 ret
= lduw_nucleus(addr
);
1429 ret
= ldl_nucleus(addr
);
1433 ret
= ldq_nucleus(addr
);
1438 case 0x4a: /* UPA config */
1441 case 0x45: /* LSU */
1444 case 0x50: /* I-MMU regs */
1446 int reg
= (addr
>> 3) & 0xf;
1449 /* I-TSB Tag Target register */
1450 ret
= ultrasparc_tag_target(env
->immu
.tag_access
);
1452 ret
= env
->immuregs
[reg
];
1457 case 0x51: /* I-MMU 8k TSB pointer */
1459 /* env->immuregs[5] holds I-MMU TSB register value
1460 env->immuregs[6] holds I-MMU Tag Access register value */
1461 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
1465 case 0x52: /* I-MMU 64k TSB pointer */
1467 /* env->immuregs[5] holds I-MMU TSB register value
1468 env->immuregs[6] holds I-MMU Tag Access register value */
1469 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
1473 case 0x55: /* I-MMU data access */
1475 int reg
= (addr
>> 3) & 0x3f;
1477 ret
= env
->itlb
[reg
].tte
;
1480 case 0x56: /* I-MMU tag read */
1482 int reg
= (addr
>> 3) & 0x3f;
1484 ret
= env
->itlb
[reg
].tag
;
1487 case 0x58: /* D-MMU regs */
1489 int reg
= (addr
>> 3) & 0xf;
1492 /* D-TSB Tag Target register */
1493 ret
= ultrasparc_tag_target(env
->dmmu
.tag_access
);
1495 ret
= env
->dmmuregs
[reg
];
1499 case 0x59: /* D-MMU 8k TSB pointer */
1501 /* env->dmmuregs[5] holds D-MMU TSB register value
1502 env->dmmuregs[6] holds D-MMU Tag Access register value */
1503 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
1507 case 0x5a: /* D-MMU 64k TSB pointer */
1509 /* env->dmmuregs[5] holds D-MMU TSB register value
1510 env->dmmuregs[6] holds D-MMU Tag Access register value */
1511 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
1515 case 0x5d: /* D-MMU data access */
1517 int reg
= (addr
>> 3) & 0x3f;
1519 ret
= env
->dtlb
[reg
].tte
;
1522 case 0x5e: /* D-MMU tag read */
1524 int reg
= (addr
>> 3) & 0x3f;
1526 ret
= env
->dtlb
[reg
].tag
;
1529 case 0x48: /* Interrupt dispatch, RO */
1531 case 0x49: /* Interrupt data receive */
1532 ret
= env
->ivec_status
;
1534 case 0x7f: /* Incoming interrupt vector, RO */
1536 int reg
= (addr
>> 4) & 0x3;
1538 ret
= env
->ivec_data
[reg
];
1542 case 0x46: /* D-cache data */
1543 case 0x47: /* D-cache tag access */
1544 case 0x4b: /* E-cache error enable */
1545 case 0x4c: /* E-cache asynchronous fault status */
1546 case 0x4d: /* E-cache asynchronous fault address */
1547 case 0x4e: /* E-cache tag data */
1548 case 0x66: /* I-cache instruction access */
1549 case 0x67: /* I-cache tag access */
1550 case 0x6e: /* I-cache predecode */
1551 case 0x6f: /* I-cache LRU etc. */
1552 case 0x76: /* E-cache tag */
1553 case 0x7e: /* E-cache tag */
1555 case 0x5b: /* D-MMU data pointer */
1556 case 0x54: /* I-MMU data in, WO */
1557 case 0x57: /* I-MMU demap, WO */
1558 case 0x5c: /* D-MMU data in, WO */
1559 case 0x5f: /* D-MMU demap, WO */
1560 case 0x77: /* Interrupt vector, WO */
1562 do_unassigned_access(addr
, 0, 0, 1, size
);
1567 /* Convert from little endian */
1569 case 0x0c: /* Nucleus Little Endian (LE) */
1570 case 0x18: /* As if user primary LE */
1571 case 0x19: /* As if user secondary LE */
1572 case 0x1c: /* Bypass LE */
1573 case 0x1d: /* Bypass, non-cacheable LE */
1574 case 0x88: /* Primary LE */
1575 case 0x89: /* Secondary LE */
1593 /* Convert to signed number */
1600 ret
= (int16_t) ret
;
1603 ret
= (int32_t) ret
;
1610 dump_asi("read ", last_addr
, asi
, size
, ret
);
1615 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
1618 dump_asi("write", addr
, asi
, size
, val
);
1623 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
1624 || (cpu_has_hypervisor(env
)
1625 && asi
>= 0x30 && asi
< 0x80
1626 && !(env
->hpstate
& HS_PRIV
))) {
1627 helper_raise_exception(env
, TT_PRIV_ACT
);
1630 helper_check_align(addr
, size
- 1);
1631 addr
= asi_address_mask(env
, asi
, addr
);
1633 /* Convert to little endian */
1635 case 0x0c: /* Nucleus Little Endian (LE) */
1636 case 0x18: /* As if user primary LE */
1637 case 0x19: /* As if user secondary LE */
1638 case 0x1c: /* Bypass LE */
1639 case 0x1d: /* Bypass, non-cacheable LE */
1640 case 0x88: /* Primary LE */
1641 case 0x89: /* Secondary LE */
1660 case 0x10: /* As if user primary */
1661 case 0x11: /* As if user secondary */
1662 case 0x18: /* As if user primary LE */
1663 case 0x19: /* As if user secondary LE */
1664 case 0x80: /* Primary */
1665 case 0x81: /* Secondary */
1666 case 0x88: /* Primary LE */
1667 case 0x89: /* Secondary LE */
1668 case 0xe2: /* UA2007 Primary block init */
1669 case 0xe3: /* UA2007 Secondary block init */
1670 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
1671 if (cpu_hypervisor_mode(env
)) {
1674 stb_hypv(addr
, val
);
1677 stw_hypv(addr
, val
);
1680 stl_hypv(addr
, val
);
1684 stq_hypv(addr
, val
);
1688 /* secondary space access has lowest asi bit equal to 1 */
1692 stb_kernel_secondary(addr
, val
);
1695 stw_kernel_secondary(addr
, val
);
1698 stl_kernel_secondary(addr
, val
);
1702 stq_kernel_secondary(addr
, val
);
1708 stb_kernel(addr
, val
);
1711 stw_kernel(addr
, val
);
1714 stl_kernel(addr
, val
);
1718 stq_kernel(addr
, val
);
1724 /* secondary space access has lowest asi bit equal to 1 */
1728 stb_user_secondary(addr
, val
);
1731 stw_user_secondary(addr
, val
);
1734 stl_user_secondary(addr
, val
);
1738 stq_user_secondary(addr
, val
);
1744 stb_user(addr
, val
);
1747 stw_user(addr
, val
);
1750 stl_user(addr
, val
);
1754 stq_user(addr
, val
);
1760 case 0x14: /* Bypass */
1761 case 0x15: /* Bypass, non-cacheable */
1762 case 0x1c: /* Bypass LE */
1763 case 0x1d: /* Bypass, non-cacheable LE */
1767 stb_phys(addr
, val
);
1770 stw_phys(addr
, val
);
1773 stl_phys(addr
, val
);
1777 stq_phys(addr
, val
);
1782 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1783 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1784 Only ldda allowed */
1785 helper_raise_exception(env
, TT_ILL_INSN
);
1787 case 0x04: /* Nucleus */
1788 case 0x0c: /* Nucleus Little Endian (LE) */
1792 stb_nucleus(addr
, val
);
1795 stw_nucleus(addr
, val
);
1798 stl_nucleus(addr
, val
);
1802 stq_nucleus(addr
, val
);
1808 case 0x4a: /* UPA config */
1811 case 0x45: /* LSU */
1816 env
->lsu
= val
& (DMMU_E
| IMMU_E
);
1817 /* Mappings generated during D/I MMU disabled mode are
1818 invalid in normal mode */
1819 if (oldreg
!= env
->lsu
) {
1820 DPRINTF_MMU("LSU change: 0x%" PRIx64
" -> 0x%" PRIx64
"\n",
1823 dump_mmu(stdout
, fprintf
, env1
);
1829 case 0x50: /* I-MMU regs */
1831 int reg
= (addr
>> 3) & 0xf;
1834 oldreg
= env
->immuregs
[reg
];
1838 case 1: /* Not in I-MMU */
1842 if ((val
& 1) == 0) {
1843 val
= 0; /* Clear SFSR */
1845 env
->immu
.sfsr
= val
;
1849 case 5: /* TSB access */
1850 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64
" -> 0x%016"
1851 PRIx64
"\n", env
->immu
.tsb
, val
);
1852 env
->immu
.tsb
= val
;
1854 case 6: /* Tag access */
1855 env
->immu
.tag_access
= val
;
1864 if (oldreg
!= env
->immuregs
[reg
]) {
1865 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
1866 PRIx64
"\n", reg
, oldreg
, env
->immuregs
[reg
]);
1869 dump_mmu(stdout
, fprintf
, env
);
1873 case 0x54: /* I-MMU data in */
1874 replace_tlb_1bit_lru(env
->itlb
, env
->immu
.tag_access
, val
, "immu", env
);
1876 case 0x55: /* I-MMU data access */
1878 /* TODO: auto demap */
1880 unsigned int i
= (addr
>> 3) & 0x3f;
1882 replace_tlb_entry(&env
->itlb
[i
], env
->immu
.tag_access
, val
, env
);
1885 DPRINTF_MMU("immu data access replaced entry [%i]\n", i
);
1886 dump_mmu(stdout
, fprintf
, env
);
1890 case 0x57: /* I-MMU demap */
1891 demap_tlb(env
->itlb
, addr
, "immu", env
);
1893 case 0x58: /* D-MMU regs */
1895 int reg
= (addr
>> 3) & 0xf;
1898 oldreg
= env
->dmmuregs
[reg
];
1904 if ((val
& 1) == 0) {
1905 val
= 0; /* Clear SFSR, Fault address */
1908 env
->dmmu
.sfsr
= val
;
1910 case 1: /* Primary context */
1911 env
->dmmu
.mmu_primary_context
= val
;
1912 /* can be optimized to only flush MMU_USER_IDX
1913 and MMU_KERNEL_IDX entries */
1916 case 2: /* Secondary context */
1917 env
->dmmu
.mmu_secondary_context
= val
;
1918 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1919 and MMU_KERNEL_SECONDARY_IDX entries */
1922 case 5: /* TSB access */
1923 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64
" -> 0x%016"
1924 PRIx64
"\n", env
->dmmu
.tsb
, val
);
1925 env
->dmmu
.tsb
= val
;
1927 case 6: /* Tag access */
1928 env
->dmmu
.tag_access
= val
;
1930 case 7: /* Virtual Watchpoint */
1931 case 8: /* Physical Watchpoint */
1933 env
->dmmuregs
[reg
] = val
;
1937 if (oldreg
!= env
->dmmuregs
[reg
]) {
1938 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
1939 PRIx64
"\n", reg
, oldreg
, env
->dmmuregs
[reg
]);
1942 dump_mmu(stdout
, fprintf
, env
);
1946 case 0x5c: /* D-MMU data in */
1947 replace_tlb_1bit_lru(env
->dtlb
, env
->dmmu
.tag_access
, val
, "dmmu", env
);
1949 case 0x5d: /* D-MMU data access */
1951 unsigned int i
= (addr
>> 3) & 0x3f;
1953 replace_tlb_entry(&env
->dtlb
[i
], env
->dmmu
.tag_access
, val
, env
);
1956 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i
);
1957 dump_mmu(stdout
, fprintf
, env
);
1961 case 0x5f: /* D-MMU demap */
1962 demap_tlb(env
->dtlb
, addr
, "dmmu", env
);
1964 case 0x49: /* Interrupt data receive */
1965 env
->ivec_status
= val
& 0x20;
1967 case 0x46: /* D-cache data */
1968 case 0x47: /* D-cache tag access */
1969 case 0x4b: /* E-cache error enable */
1970 case 0x4c: /* E-cache asynchronous fault status */
1971 case 0x4d: /* E-cache asynchronous fault address */
1972 case 0x4e: /* E-cache tag data */
1973 case 0x66: /* I-cache instruction access */
1974 case 0x67: /* I-cache tag access */
1975 case 0x6e: /* I-cache predecode */
1976 case 0x6f: /* I-cache LRU etc. */
1977 case 0x76: /* E-cache tag */
1978 case 0x7e: /* E-cache tag */
1980 case 0x51: /* I-MMU 8k TSB pointer, RO */
1981 case 0x52: /* I-MMU 64k TSB pointer, RO */
1982 case 0x56: /* I-MMU tag read, RO */
1983 case 0x59: /* D-MMU 8k TSB pointer, RO */
1984 case 0x5a: /* D-MMU 64k TSB pointer, RO */
1985 case 0x5b: /* D-MMU data pointer, RO */
1986 case 0x5e: /* D-MMU tag read, RO */
1987 case 0x48: /* Interrupt dispatch, RO */
1988 case 0x7f: /* Incoming interrupt vector, RO */
1989 case 0x82: /* Primary no-fault, RO */
1990 case 0x83: /* Secondary no-fault, RO */
1991 case 0x8a: /* Primary no-fault LE, RO */
1992 case 0x8b: /* Secondary no-fault LE, RO */
1994 do_unassigned_access(addr
, 1, 0, 1, size
);
1998 #endif /* CONFIG_USER_ONLY */
2000 void helper_ldda_asi(target_ulong addr
, int asi
, int rd
)
2002 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2003 || (cpu_has_hypervisor(env
)
2004 && asi
>= 0x30 && asi
< 0x80
2005 && !(env
->hpstate
& HS_PRIV
))) {
2006 helper_raise_exception(env
, TT_PRIV_ACT
);
2009 addr
= asi_address_mask(env
, asi
, addr
);
2012 #if !defined(CONFIG_USER_ONLY)
2013 case 0x24: /* Nucleus quad LDD 128 bit atomic */
2014 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE */
2015 helper_check_align(addr
, 0xf);
2017 env
->gregs
[1] = ldq_nucleus(addr
+ 8);
2019 bswap64s(&env
->gregs
[1]);
2021 } else if (rd
< 8) {
2022 env
->gregs
[rd
] = ldq_nucleus(addr
);
2023 env
->gregs
[rd
+ 1] = ldq_nucleus(addr
+ 8);
2025 bswap64s(&env
->gregs
[rd
]);
2026 bswap64s(&env
->gregs
[rd
+ 1]);
2029 env
->regwptr
[rd
] = ldq_nucleus(addr
);
2030 env
->regwptr
[rd
+ 1] = ldq_nucleus(addr
+ 8);
2032 bswap64s(&env
->regwptr
[rd
]);
2033 bswap64s(&env
->regwptr
[rd
+ 1]);
2039 helper_check_align(addr
, 0x3);
2041 env
->gregs
[1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
2042 } else if (rd
< 8) {
2043 env
->gregs
[rd
] = helper_ld_asi(addr
, asi
, 4, 0);
2044 env
->gregs
[rd
+ 1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
2046 env
->regwptr
[rd
] = helper_ld_asi(addr
, asi
, 4, 0);
2047 env
->regwptr
[rd
+ 1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
2053 void helper_ldf_asi(target_ulong addr
, int asi
, int size
, int rd
)
2058 helper_check_align(addr
, 3);
2059 addr
= asi_address_mask(env
, asi
, addr
);
2062 case 0xf0: /* UA2007/JPS1 Block load primary */
2063 case 0xf1: /* UA2007/JPS1 Block load secondary */
2064 case 0xf8: /* UA2007/JPS1 Block load primary LE */
2065 case 0xf9: /* UA2007/JPS1 Block load secondary LE */
2067 helper_raise_exception(env
, TT_ILL_INSN
);
2070 helper_check_align(addr
, 0x3f);
2071 for (i
= 0; i
< 8; i
++, rd
+= 2, addr
+= 8) {
2072 env
->fpr
[rd
/2].ll
= helper_ld_asi(addr
, asi
& 0x8f, 8, 0);
2076 case 0x16: /* UA2007 Block load primary, user privilege */
2077 case 0x17: /* UA2007 Block load secondary, user privilege */
2078 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2079 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2080 case 0x70: /* JPS1 Block load primary, user privilege */
2081 case 0x71: /* JPS1 Block load secondary, user privilege */
2082 case 0x78: /* JPS1 Block load primary LE, user privilege */
2083 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2085 helper_raise_exception(env
, TT_ILL_INSN
);
2088 helper_check_align(addr
, 0x3f);
2089 for (i
= 0; i
< 8; i
++, rd
+= 2, addr
+= 4) {
2090 env
->fpr
[rd
/2].ll
= helper_ld_asi(addr
, asi
& 0x19, 8, 0);
2101 val
= helper_ld_asi(addr
, asi
, size
, 0);
2103 env
->fpr
[rd
/2].l
.lower
= val
;
2105 env
->fpr
[rd
/2].l
.upper
= val
;
2109 env
->fpr
[rd
/2].ll
= helper_ld_asi(addr
, asi
, size
, 0);
2112 env
->fpr
[rd
/2].ll
= helper_ld_asi(addr
, asi
, 8, 0);
2113 env
->fpr
[rd
/2 + 1].ll
= helper_ld_asi(addr
+ 8, asi
, 8, 0);
2118 void helper_stf_asi(target_ulong addr
, int asi
, int size
, int rd
)
2123 helper_check_align(addr
, 3);
2124 addr
= asi_address_mask(env
, asi
, addr
);
2127 case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */
2128 case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */
2129 case 0xf0: /* UA2007/JPS1 Block store primary */
2130 case 0xf1: /* UA2007/JPS1 Block store secondary */
2131 case 0xf8: /* UA2007/JPS1 Block store primary LE */
2132 case 0xf9: /* UA2007/JPS1 Block store secondary LE */
2134 helper_raise_exception(env
, TT_ILL_INSN
);
2137 helper_check_align(addr
, 0x3f);
2138 for (i
= 0; i
< 8; i
++, rd
+= 2, addr
+= 8) {
2139 helper_st_asi(addr
, env
->fpr
[rd
/2].ll
, asi
& 0x8f, 8);
2143 case 0x16: /* UA2007 Block load primary, user privilege */
2144 case 0x17: /* UA2007 Block load secondary, user privilege */
2145 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2146 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2147 case 0x70: /* JPS1 Block store primary, user privilege */
2148 case 0x71: /* JPS1 Block store secondary, user privilege */
2149 case 0x78: /* JPS1 Block load primary LE, user privilege */
2150 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2152 helper_raise_exception(env
, TT_ILL_INSN
);
2155 helper_check_align(addr
, 0x3f);
2156 for (i
= 0; i
< 8; i
++, rd
+= 2, addr
+= 8) {
2157 helper_st_asi(addr
, env
->fpr
[rd
/2].ll
, asi
& 0x19, 8);
2169 val
= env
->fpr
[rd
/2].l
.lower
;
2171 val
= env
->fpr
[rd
/2].l
.upper
;
2173 helper_st_asi(addr
, val
, asi
, size
);
2176 helper_st_asi(addr
, env
->fpr
[rd
/2].ll
, asi
, size
);
2179 helper_st_asi(addr
, env
->fpr
[rd
/2].ll
, asi
, 8);
2180 helper_st_asi(addr
+ 8, env
->fpr
[rd
/2 + 1].ll
, asi
, 8);
2185 target_ulong
helper_cas_asi(target_ulong addr
, target_ulong val1
,
2186 target_ulong val2
, uint32_t asi
)
2190 val2
&= 0xffffffffUL
;
2191 ret
= helper_ld_asi(addr
, asi
, 4, 0);
2192 ret
&= 0xffffffffUL
;
2194 helper_st_asi(addr
, val1
& 0xffffffffUL
, asi
, 4);
2199 target_ulong
helper_casx_asi(target_ulong addr
, target_ulong val1
,
2200 target_ulong val2
, uint32_t asi
)
2204 ret
= helper_ld_asi(addr
, asi
, 8, 0);
2206 helper_st_asi(addr
, val1
, asi
, 8);
2210 #endif /* TARGET_SPARC64 */
2212 void helper_ldqf(target_ulong addr
, int mem_idx
)
2214 /* XXX add 128 bit load */
2217 helper_check_align(addr
, 7);
2218 #if !defined(CONFIG_USER_ONLY)
2221 u
.ll
.upper
= ldq_user(addr
);
2222 u
.ll
.lower
= ldq_user(addr
+ 8);
2225 case MMU_KERNEL_IDX
:
2226 u
.ll
.upper
= ldq_kernel(addr
);
2227 u
.ll
.lower
= ldq_kernel(addr
+ 8);
2230 #ifdef TARGET_SPARC64
2232 u
.ll
.upper
= ldq_hypv(addr
);
2233 u
.ll
.lower
= ldq_hypv(addr
+ 8);
2238 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx
);
2242 u
.ll
.upper
= ldq_raw(address_mask(env
, addr
));
2243 u
.ll
.lower
= ldq_raw(address_mask(env
, addr
+ 8));
2248 void helper_stqf(target_ulong addr
, int mem_idx
)
2250 /* XXX add 128 bit store */
2253 helper_check_align(addr
, 7);
2254 #if !defined(CONFIG_USER_ONLY)
2258 stq_user(addr
, u
.ll
.upper
);
2259 stq_user(addr
+ 8, u
.ll
.lower
);
2261 case MMU_KERNEL_IDX
:
2263 stq_kernel(addr
, u
.ll
.upper
);
2264 stq_kernel(addr
+ 8, u
.ll
.lower
);
2266 #ifdef TARGET_SPARC64
2269 stq_hypv(addr
, u
.ll
.upper
);
2270 stq_hypv(addr
+ 8, u
.ll
.lower
);
2274 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx
);
2279 stq_raw(address_mask(env
, addr
), u
.ll
.upper
);
2280 stq_raw(address_mask(env
, addr
+ 8), u
.ll
.lower
);
2284 #ifndef TARGET_SPARC64
2285 #if !defined(CONFIG_USER_ONLY)
2286 static void do_unassigned_access(target_phys_addr_t addr
, int is_write
,
2287 int is_exec
, int is_asi
, int size
)
2291 #ifdef DEBUG_UNASSIGNED
2293 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2294 " asi 0x%02x from " TARGET_FMT_lx
"\n",
2295 is_exec
? "exec" : is_write
? "write" : "read", size
,
2296 size
== 1 ? "" : "s", addr
, is_asi
, env
->pc
);
2298 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2299 " from " TARGET_FMT_lx
"\n",
2300 is_exec
? "exec" : is_write
? "write" : "read", size
,
2301 size
== 1 ? "" : "s", addr
, env
->pc
);
2304 /* Don't overwrite translation and access faults */
2305 fault_type
= (env
->mmuregs
[3] & 0x1c) >> 2;
2306 if ((fault_type
> 4) || (fault_type
== 0)) {
2307 env
->mmuregs
[3] = 0; /* Fault status register */
2309 env
->mmuregs
[3] |= 1 << 16;
2312 env
->mmuregs
[3] |= 1 << 5;
2315 env
->mmuregs
[3] |= 1 << 6;
2318 env
->mmuregs
[3] |= 1 << 7;
2320 env
->mmuregs
[3] |= (5 << 2) | 2;
2321 /* SuperSPARC will never place instruction fault addresses in the FAR */
2323 env
->mmuregs
[4] = addr
; /* Fault address register */
2326 /* overflow (same type fault was not read before another fault) */
2327 if (fault_type
== ((env
->mmuregs
[3] & 0x1c)) >> 2) {
2328 env
->mmuregs
[3] |= 1;
2331 if ((env
->mmuregs
[0] & MMU_E
) && !(env
->mmuregs
[0] & MMU_NF
)) {
2333 helper_raise_exception(env
, TT_CODE_ACCESS
);
2335 helper_raise_exception(env
, TT_DATA_ACCESS
);
2339 /* flush neverland mappings created during no-fault mode,
2340 so the sequential MMU faults report proper fault types */
2341 if (env
->mmuregs
[0] & MMU_NF
) {
2347 #if defined(CONFIG_USER_ONLY)
2348 static void do_unassigned_access(target_ulong addr
, int is_write
, int is_exec
,
2349 int is_asi
, int size
)
2351 static void do_unassigned_access(target_phys_addr_t addr
, int is_write
,
2352 int is_exec
, int is_asi
, int size
)
2355 #ifdef DEBUG_UNASSIGNED
2356 printf("Unassigned mem access to " TARGET_FMT_plx
" from " TARGET_FMT_lx
2357 "\n", addr
, env
->pc
);
2361 helper_raise_exception(env
, TT_CODE_ACCESS
);
2363 helper_raise_exception(env
, TT_DATA_ACCESS
);
2368 #if !defined(CONFIG_USER_ONLY)
2369 void cpu_unassigned_access(CPUSPARCState
*env1
, target_phys_addr_t addr
,
2370 int is_write
, int is_exec
, int is_asi
, int size
)
2372 CPUSPARCState
*saved_env
;
2376 do_unassigned_access(addr
, is_write
, is_exec
, is_asi
, size
);