]>
git.proxmox.com Git - mirror_qemu.git/blob - target-sparc/ldst_helper.c
2 * Helpers for loads and stores
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
25 //#define DEBUG_UNALIGNED
26 //#define DEBUG_UNASSIGNED
28 //#define DEBUG_CACHE_CONTROL
31 #define DPRINTF_MMU(fmt, ...) \
32 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
34 #define DPRINTF_MMU(fmt, ...) do {} while (0)
38 #define DPRINTF_MXCC(fmt, ...) \
39 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
41 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
45 #define DPRINTF_ASI(fmt, ...) \
46 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
49 #ifdef DEBUG_CACHE_CONTROL
50 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
51 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
53 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
58 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
60 #define AM_CHECK(env1) (1)
64 #define QT0 (env->qt0)
65 #define QT1 (env->qt1)
67 #if !defined(CONFIG_USER_ONLY)
68 static void QEMU_NORETURN
do_unaligned_access(CPUSPARCState
*env
,
69 target_ulong addr
, int is_write
,
70 int is_user
, uintptr_t retaddr
);
71 #include "exec/softmmu_exec.h"
72 #define MMUSUFFIX _mmu
76 #include "exec/softmmu_template.h"
79 #include "exec/softmmu_template.h"
82 #include "exec/softmmu_template.h"
85 #include "exec/softmmu_template.h"
88 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
89 /* Calculates TSB pointer value for fault page size 8k or 64k */
90 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register
,
91 uint64_t tag_access_register
,
94 uint64_t tsb_base
= tsb_register
& ~0x1fffULL
;
95 int tsb_split
= (tsb_register
& 0x1000ULL
) ? 1 : 0;
96 int tsb_size
= tsb_register
& 0xf;
98 /* discard lower 13 bits which hold tag access context */
99 uint64_t tag_access_va
= tag_access_register
& ~0x1fffULL
;
101 /* now reorder bits */
102 uint64_t tsb_base_mask
= ~0x1fffULL
;
103 uint64_t va
= tag_access_va
;
105 /* move va bits to correct position */
106 if (page_size
== 8*1024) {
108 } else if (page_size
== 64*1024) {
113 tsb_base_mask
<<= tsb_size
;
116 /* calculate tsb_base mask and adjust va if split is in use */
118 if (page_size
== 8*1024) {
119 va
&= ~(1ULL << (13 + tsb_size
));
120 } else if (page_size
== 64*1024) {
121 va
|= (1ULL << (13 + tsb_size
));
126 return ((tsb_base
& tsb_base_mask
) | (va
& ~tsb_base_mask
)) & ~0xfULL
;
129 /* Calculates tag target register value by reordering bits
130 in tag access register */
131 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register
)
133 return ((tag_access_register
& 0x1fff) << 48) | (tag_access_register
>> 22);
136 static void replace_tlb_entry(SparcTLBEntry
*tlb
,
137 uint64_t tlb_tag
, uint64_t tlb_tte
,
140 target_ulong mask
, size
, va
, offset
;
142 /* flush page range if translation is valid */
143 if (TTE_IS_VALID(tlb
->tte
)) {
145 mask
= 0xffffffffffffe000ULL
;
146 mask
<<= 3 * ((tlb
->tte
>> 61) & 3);
149 va
= tlb
->tag
& mask
;
151 for (offset
= 0; offset
< size
; offset
+= TARGET_PAGE_SIZE
) {
152 tlb_flush_page(env1
, va
+ offset
);
160 static void demap_tlb(SparcTLBEntry
*tlb
, target_ulong demap_addr
,
161 const char *strmmu
, CPUSPARCState
*env1
)
167 int is_demap_context
= (demap_addr
>> 6) & 1;
170 switch ((demap_addr
>> 4) & 3) {
171 case 0: /* primary */
172 context
= env1
->dmmu
.mmu_primary_context
;
174 case 1: /* secondary */
175 context
= env1
->dmmu
.mmu_secondary_context
;
177 case 2: /* nucleus */
180 case 3: /* reserved */
185 for (i
= 0; i
< 64; i
++) {
186 if (TTE_IS_VALID(tlb
[i
].tte
)) {
188 if (is_demap_context
) {
189 /* will remove non-global entries matching context value */
190 if (TTE_IS_GLOBAL(tlb
[i
].tte
) ||
191 !tlb_compare_context(&tlb
[i
], context
)) {
196 will remove any entry matching VA */
197 mask
= 0xffffffffffffe000ULL
;
198 mask
<<= 3 * ((tlb
[i
].tte
>> 61) & 3);
200 if (!compare_masked(demap_addr
, tlb
[i
].tag
, mask
)) {
204 /* entry should be global or matching context value */
205 if (!TTE_IS_GLOBAL(tlb
[i
].tte
) &&
206 !tlb_compare_context(&tlb
[i
], context
)) {
211 replace_tlb_entry(&tlb
[i
], 0, 0, env1
);
213 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu
, i
);
214 dump_mmu(stdout
, fprintf
, env1
);
220 static void replace_tlb_1bit_lru(SparcTLBEntry
*tlb
,
221 uint64_t tlb_tag
, uint64_t tlb_tte
,
222 const char *strmmu
, CPUSPARCState
*env1
)
224 unsigned int i
, replace_used
;
226 /* Try replacing invalid entry */
227 for (i
= 0; i
< 64; i
++) {
228 if (!TTE_IS_VALID(tlb
[i
].tte
)) {
229 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
231 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu
, i
);
232 dump_mmu(stdout
, fprintf
, env1
);
238 /* All entries are valid, try replacing unlocked entry */
240 for (replace_used
= 0; replace_used
< 2; ++replace_used
) {
242 /* Used entries are not replaced on first pass */
244 for (i
= 0; i
< 64; i
++) {
245 if (!TTE_IS_LOCKED(tlb
[i
].tte
) && !TTE_IS_USED(tlb
[i
].tte
)) {
247 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
249 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
250 strmmu
, (replace_used
? "used" : "unused"), i
);
251 dump_mmu(stdout
, fprintf
, env1
);
257 /* Now reset used bit and search for unused entries again */
259 for (i
= 0; i
< 64; i
++) {
260 TTE_SET_UNUSED(tlb
[i
].tte
);
265 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu
);
272 static inline target_ulong
address_mask(CPUSPARCState
*env1
, target_ulong addr
)
274 #ifdef TARGET_SPARC64
275 if (AM_CHECK(env1
)) {
276 addr
&= 0xffffffffULL
;
282 /* returns true if access using this ASI is to have address translated by MMU
283 otherwise access is to raw physical address */
284 static inline int is_translating_asi(int asi
)
286 #ifdef TARGET_SPARC64
287 /* Ultrasparc IIi translating asi
288 - note this list is defined by cpu implementation
304 /* TODO: check sparc32 bits */
309 static inline target_ulong
asi_address_mask(CPUSPARCState
*env
,
310 int asi
, target_ulong addr
)
312 if (is_translating_asi(asi
)) {
313 return address_mask(env
, addr
);
319 void helper_check_align(CPUSPARCState
*env
, target_ulong addr
, uint32_t align
)
322 #ifdef DEBUG_UNALIGNED
323 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
324 "\n", addr
, env
->pc
);
326 helper_raise_exception(env
, TT_UNALIGNED
);
330 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
332 static void dump_mxcc(CPUSPARCState
*env
)
334 printf("mxccdata: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
336 env
->mxccdata
[0], env
->mxccdata
[1],
337 env
->mxccdata
[2], env
->mxccdata
[3]);
338 printf("mxccregs: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
340 " %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
342 env
->mxccregs
[0], env
->mxccregs
[1],
343 env
->mxccregs
[2], env
->mxccregs
[3],
344 env
->mxccregs
[4], env
->mxccregs
[5],
345 env
->mxccregs
[6], env
->mxccregs
[7]);
349 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
350 && defined(DEBUG_ASI)
351 static void dump_asi(const char *txt
, target_ulong addr
, int asi
, int size
,
356 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %02" PRIx64
"\n", txt
,
357 addr
, asi
, r1
& 0xff);
360 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %04" PRIx64
"\n", txt
,
361 addr
, asi
, r1
& 0xffff);
364 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %08" PRIx64
"\n", txt
,
365 addr
, asi
, r1
& 0xffffffff);
368 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %016" PRIx64
"\n", txt
,
375 #ifndef TARGET_SPARC64
376 #ifndef CONFIG_USER_ONLY
379 /* Leon3 cache control */
381 static void leon3_cache_control_st(CPUSPARCState
*env
, target_ulong addr
,
382 uint64_t val
, int size
)
384 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64
", size:%d\n",
388 DPRINTF_CACHE_CONTROL("32bits only\n");
393 case 0x00: /* Cache control */
395 /* These values must always be read as zeros */
396 val
&= ~CACHE_CTRL_FD
;
397 val
&= ~CACHE_CTRL_FI
;
398 val
&= ~CACHE_CTRL_IB
;
399 val
&= ~CACHE_CTRL_IP
;
400 val
&= ~CACHE_CTRL_DP
;
402 env
->cache_control
= val
;
404 case 0x04: /* Instruction cache configuration */
405 case 0x08: /* Data cache configuration */
409 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr
);
414 static uint64_t leon3_cache_control_ld(CPUSPARCState
*env
, target_ulong addr
,
420 DPRINTF_CACHE_CONTROL("32bits only\n");
425 case 0x00: /* Cache control */
426 ret
= env
->cache_control
;
429 /* Configuration registers are read and only always keep those
432 case 0x04: /* Instruction cache configuration */
435 case 0x08: /* Data cache configuration */
439 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr
);
442 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64
", size:%d\n",
447 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int size
,
450 CPUState
*cs
= ENV_GET_CPU(env
);
452 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
453 uint32_t last_addr
= addr
;
456 helper_check_align(env
, addr
, size
- 1);
458 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
460 case 0x00: /* Leon3 Cache Control */
461 case 0x08: /* Leon3 Instruction Cache config */
462 case 0x0C: /* Leon3 Date Cache config */
463 if (env
->def
->features
& CPU_FEATURE_CACHE_CTRL
) {
464 ret
= leon3_cache_control_ld(env
, addr
, size
);
467 case 0x01c00a00: /* MXCC control register */
469 ret
= env
->mxccregs
[3];
471 qemu_log_mask(LOG_UNIMP
,
472 "%08x: unimplemented access size: %d\n", addr
,
476 case 0x01c00a04: /* MXCC control register */
478 ret
= env
->mxccregs
[3];
480 qemu_log_mask(LOG_UNIMP
,
481 "%08x: unimplemented access size: %d\n", addr
,
485 case 0x01c00c00: /* Module reset register */
487 ret
= env
->mxccregs
[5];
488 /* should we do something here? */
490 qemu_log_mask(LOG_UNIMP
,
491 "%08x: unimplemented access size: %d\n", addr
,
495 case 0x01c00f00: /* MBus port address register */
497 ret
= env
->mxccregs
[7];
499 qemu_log_mask(LOG_UNIMP
,
500 "%08x: unimplemented access size: %d\n", addr
,
505 qemu_log_mask(LOG_UNIMP
,
506 "%08x: unimplemented address, size: %d\n", addr
,
510 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
511 "addr = %08x -> ret = %" PRIx64
","
512 "addr = %08x\n", asi
, size
, sign
, last_addr
, ret
, addr
);
517 case 3: /* MMU probe */
518 case 0x18: /* LEON3 MMU probe */
522 mmulev
= (addr
>> 8) & 15;
526 ret
= mmu_probe(env
, addr
, mmulev
);
528 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64
"\n",
532 case 4: /* read MMU regs */
533 case 0x19: /* LEON3 read MMU regs */
535 int reg
= (addr
>> 8) & 0x1f;
537 ret
= env
->mmuregs
[reg
];
538 if (reg
== 3) { /* Fault status cleared on read */
540 } else if (reg
== 0x13) { /* Fault status read */
541 ret
= env
->mmuregs
[3];
542 } else if (reg
== 0x14) { /* Fault address read */
543 ret
= env
->mmuregs
[4];
545 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64
"\n", reg
, ret
);
548 case 5: /* Turbosparc ITLB Diagnostic */
549 case 6: /* Turbosparc DTLB Diagnostic */
550 case 7: /* Turbosparc IOTLB Diagnostic */
552 case 9: /* Supervisor code access */
555 ret
= cpu_ldub_code(env
, addr
);
558 ret
= cpu_lduw_code(env
, addr
);
562 ret
= cpu_ldl_code(env
, addr
);
565 ret
= cpu_ldq_code(env
, addr
);
569 case 0xa: /* User data access */
572 ret
= cpu_ldub_user(env
, addr
);
575 ret
= cpu_lduw_user(env
, addr
);
579 ret
= cpu_ldl_user(env
, addr
);
582 ret
= cpu_ldq_user(env
, addr
);
586 case 0xb: /* Supervisor data access */
590 ret
= cpu_ldub_kernel(env
, addr
);
593 ret
= cpu_lduw_kernel(env
, addr
);
597 ret
= cpu_ldl_kernel(env
, addr
);
600 ret
= cpu_ldq_kernel(env
, addr
);
604 case 0xc: /* I-cache tag */
605 case 0xd: /* I-cache data */
606 case 0xe: /* D-cache tag */
607 case 0xf: /* D-cache data */
609 case 0x20: /* MMU passthrough */
610 case 0x1c: /* LEON MMU passthrough */
613 ret
= ldub_phys(cs
->as
, addr
);
616 ret
= lduw_phys(cs
->as
, addr
);
620 ret
= ldl_phys(cs
->as
, addr
);
623 ret
= ldq_phys(cs
->as
, addr
);
627 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
630 ret
= ldub_phys(cs
->as
, (hwaddr
)addr
631 | ((hwaddr
)(asi
& 0xf) << 32));
634 ret
= lduw_phys(cs
->as
, (hwaddr
)addr
635 | ((hwaddr
)(asi
& 0xf) << 32));
639 ret
= ldl_phys(cs
->as
, (hwaddr
)addr
640 | ((hwaddr
)(asi
& 0xf) << 32));
643 ret
= ldq_phys(cs
->as
, (hwaddr
)addr
644 | ((hwaddr
)(asi
& 0xf) << 32));
648 case 0x30: /* Turbosparc secondary cache diagnostic */
649 case 0x31: /* Turbosparc RAM snoop */
650 case 0x32: /* Turbosparc page table descriptor diagnostic */
651 case 0x39: /* data cache diagnostic register */
654 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
656 int reg
= (addr
>> 8) & 3;
659 case 0: /* Breakpoint Value (Addr) */
660 ret
= env
->mmubpregs
[reg
];
662 case 1: /* Breakpoint Mask */
663 ret
= env
->mmubpregs
[reg
];
665 case 2: /* Breakpoint Control */
666 ret
= env
->mmubpregs
[reg
];
668 case 3: /* Breakpoint Status */
669 ret
= env
->mmubpregs
[reg
];
670 env
->mmubpregs
[reg
] = 0ULL;
673 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64
"\n", reg
,
677 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
678 ret
= env
->mmubpctrv
;
680 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
681 ret
= env
->mmubpctrc
;
683 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
684 ret
= env
->mmubpctrs
;
686 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
687 ret
= env
->mmubpaction
;
689 case 8: /* User code access, XXX */
691 cpu_unassigned_access(CPU(sparc_env_get_cpu(env
)),
692 addr
, false, false, asi
, size
);
712 dump_asi("read ", last_addr
, asi
, size
, ret
);
717 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, uint64_t val
, int asi
,
720 CPUState
*cs
= ENV_GET_CPU(env
);
721 helper_check_align(env
, addr
, size
- 1);
723 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
725 case 0x00: /* Leon3 Cache Control */
726 case 0x08: /* Leon3 Instruction Cache config */
727 case 0x0C: /* Leon3 Date Cache config */
728 if (env
->def
->features
& CPU_FEATURE_CACHE_CTRL
) {
729 leon3_cache_control_st(env
, addr
, val
, size
);
733 case 0x01c00000: /* MXCC stream data register 0 */
735 env
->mxccdata
[0] = val
;
737 qemu_log_mask(LOG_UNIMP
,
738 "%08x: unimplemented access size: %d\n", addr
,
742 case 0x01c00008: /* MXCC stream data register 1 */
744 env
->mxccdata
[1] = val
;
746 qemu_log_mask(LOG_UNIMP
,
747 "%08x: unimplemented access size: %d\n", addr
,
751 case 0x01c00010: /* MXCC stream data register 2 */
753 env
->mxccdata
[2] = val
;
755 qemu_log_mask(LOG_UNIMP
,
756 "%08x: unimplemented access size: %d\n", addr
,
760 case 0x01c00018: /* MXCC stream data register 3 */
762 env
->mxccdata
[3] = val
;
764 qemu_log_mask(LOG_UNIMP
,
765 "%08x: unimplemented access size: %d\n", addr
,
769 case 0x01c00100: /* MXCC stream source */
771 env
->mxccregs
[0] = val
;
773 qemu_log_mask(LOG_UNIMP
,
774 "%08x: unimplemented access size: %d\n", addr
,
777 env
->mxccdata
[0] = ldq_phys(cs
->as
,
778 (env
->mxccregs
[0] & 0xffffffffULL
) +
780 env
->mxccdata
[1] = ldq_phys(cs
->as
,
781 (env
->mxccregs
[0] & 0xffffffffULL
) +
783 env
->mxccdata
[2] = ldq_phys(cs
->as
,
784 (env
->mxccregs
[0] & 0xffffffffULL
) +
786 env
->mxccdata
[3] = ldq_phys(cs
->as
,
787 (env
->mxccregs
[0] & 0xffffffffULL
) +
790 case 0x01c00200: /* MXCC stream destination */
792 env
->mxccregs
[1] = val
;
794 qemu_log_mask(LOG_UNIMP
,
795 "%08x: unimplemented access size: %d\n", addr
,
798 stq_phys(cs
->as
, (env
->mxccregs
[1] & 0xffffffffULL
) + 0,
800 stq_phys(cs
->as
, (env
->mxccregs
[1] & 0xffffffffULL
) + 8,
802 stq_phys(cs
->as
, (env
->mxccregs
[1] & 0xffffffffULL
) + 16,
804 stq_phys(cs
->as
, (env
->mxccregs
[1] & 0xffffffffULL
) + 24,
807 case 0x01c00a00: /* MXCC control register */
809 env
->mxccregs
[3] = val
;
811 qemu_log_mask(LOG_UNIMP
,
812 "%08x: unimplemented access size: %d\n", addr
,
816 case 0x01c00a04: /* MXCC control register */
818 env
->mxccregs
[3] = (env
->mxccregs
[3] & 0xffffffff00000000ULL
)
821 qemu_log_mask(LOG_UNIMP
,
822 "%08x: unimplemented access size: %d\n", addr
,
826 case 0x01c00e00: /* MXCC error register */
827 /* writing a 1 bit clears the error */
829 env
->mxccregs
[6] &= ~val
;
831 qemu_log_mask(LOG_UNIMP
,
832 "%08x: unimplemented access size: %d\n", addr
,
836 case 0x01c00f00: /* MBus port address register */
838 env
->mxccregs
[7] = val
;
840 qemu_log_mask(LOG_UNIMP
,
841 "%08x: unimplemented access size: %d\n", addr
,
846 qemu_log_mask(LOG_UNIMP
,
847 "%08x: unimplemented address, size: %d\n", addr
,
851 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64
"\n",
852 asi
, size
, addr
, val
);
857 case 3: /* MMU flush */
858 case 0x18: /* LEON3 MMU flush */
862 mmulev
= (addr
>> 8) & 15;
863 DPRINTF_MMU("mmu flush level %d\n", mmulev
);
865 case 0: /* flush page */
866 tlb_flush_page(env
, addr
& 0xfffff000);
868 case 1: /* flush segment (256k) */
869 case 2: /* flush region (16M) */
870 case 3: /* flush context (4G) */
871 case 4: /* flush entire */
878 dump_mmu(stdout
, fprintf
, env
);
882 case 4: /* write MMU regs */
883 case 0x19: /* LEON3 write MMU regs */
885 int reg
= (addr
>> 8) & 0x1f;
888 oldreg
= env
->mmuregs
[reg
];
890 case 0: /* Control Register */
891 env
->mmuregs
[reg
] = (env
->mmuregs
[reg
] & 0xff000000) |
893 /* Mappings generated during no-fault mode or MMU
894 disabled mode are invalid in normal mode */
895 if ((oldreg
& (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)) !=
896 (env
->mmuregs
[reg
] & (MMU_E
| MMU_NF
| env
->def
->mmu_bm
))) {
900 case 1: /* Context Table Pointer Register */
901 env
->mmuregs
[reg
] = val
& env
->def
->mmu_ctpr_mask
;
903 case 2: /* Context Register */
904 env
->mmuregs
[reg
] = val
& env
->def
->mmu_cxr_mask
;
905 if (oldreg
!= env
->mmuregs
[reg
]) {
906 /* we flush when the MMU context changes because
907 QEMU has no MMU context support */
911 case 3: /* Synchronous Fault Status Register with Clear */
912 case 4: /* Synchronous Fault Address Register */
914 case 0x10: /* TLB Replacement Control Register */
915 env
->mmuregs
[reg
] = val
& env
->def
->mmu_trcr_mask
;
917 case 0x13: /* Synchronous Fault Status Register with Read
919 env
->mmuregs
[3] = val
& env
->def
->mmu_sfsr_mask
;
921 case 0x14: /* Synchronous Fault Address Register */
922 env
->mmuregs
[4] = val
;
925 env
->mmuregs
[reg
] = val
;
928 if (oldreg
!= env
->mmuregs
[reg
]) {
929 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
930 reg
, oldreg
, env
->mmuregs
[reg
]);
933 dump_mmu(stdout
, fprintf
, env
);
937 case 5: /* Turbosparc ITLB Diagnostic */
938 case 6: /* Turbosparc DTLB Diagnostic */
939 case 7: /* Turbosparc IOTLB Diagnostic */
941 case 0xa: /* User data access */
944 cpu_stb_user(env
, addr
, val
);
947 cpu_stw_user(env
, addr
, val
);
951 cpu_stl_user(env
, addr
, val
);
954 cpu_stq_user(env
, addr
, val
);
958 case 0xb: /* Supervisor data access */
962 cpu_stb_kernel(env
, addr
, val
);
965 cpu_stw_kernel(env
, addr
, val
);
969 cpu_stl_kernel(env
, addr
, val
);
972 cpu_stq_kernel(env
, addr
, val
);
976 case 0xc: /* I-cache tag */
977 case 0xd: /* I-cache data */
978 case 0xe: /* D-cache tag */
979 case 0xf: /* D-cache data */
980 case 0x10: /* I/D-cache flush page */
981 case 0x11: /* I/D-cache flush segment */
982 case 0x12: /* I/D-cache flush region */
983 case 0x13: /* I/D-cache flush context */
984 case 0x14: /* I/D-cache flush user */
986 case 0x17: /* Block copy, sta access */
992 uint32_t src
= val
& ~3, dst
= addr
& ~3, temp
;
994 for (i
= 0; i
< 32; i
+= 4, src
+= 4, dst
+= 4) {
995 temp
= cpu_ldl_kernel(env
, src
);
996 cpu_stl_kernel(env
, dst
, temp
);
1000 case 0x1f: /* Block fill, stda access */
1003 fill 32 bytes with val */
1005 uint32_t dst
= addr
& 7;
1007 for (i
= 0; i
< 32; i
+= 8, dst
+= 8) {
1008 cpu_stq_kernel(env
, dst
, val
);
1012 case 0x20: /* MMU passthrough */
1013 case 0x1c: /* LEON MMU passthrough */
1017 stb_phys(cs
->as
, addr
, val
);
1020 stw_phys(cs
->as
, addr
, val
);
1024 stl_phys(cs
->as
, addr
, val
);
1027 stq_phys(cs
->as
, addr
, val
);
1032 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1036 stb_phys(cs
->as
, (hwaddr
)addr
1037 | ((hwaddr
)(asi
& 0xf) << 32), val
);
1040 stw_phys(cs
->as
, (hwaddr
)addr
1041 | ((hwaddr
)(asi
& 0xf) << 32), val
);
1045 stl_phys(cs
->as
, (hwaddr
)addr
1046 | ((hwaddr
)(asi
& 0xf) << 32), val
);
1049 stq_phys(cs
->as
, (hwaddr
)addr
1050 | ((hwaddr
)(asi
& 0xf) << 32), val
);
1055 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1056 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1057 Turbosparc snoop RAM */
1058 case 0x32: /* store buffer control or Turbosparc page table
1059 descriptor diagnostic */
1060 case 0x36: /* I-cache flash clear */
1061 case 0x37: /* D-cache flash clear */
1063 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1065 int reg
= (addr
>> 8) & 3;
1068 case 0: /* Breakpoint Value (Addr) */
1069 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1071 case 1: /* Breakpoint Mask */
1072 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1074 case 2: /* Breakpoint Control */
1075 env
->mmubpregs
[reg
] = (val
& 0x7fULL
);
1077 case 3: /* Breakpoint Status */
1078 env
->mmubpregs
[reg
] = (val
& 0xfULL
);
1081 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg
,
1085 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1086 env
->mmubpctrv
= val
& 0xffffffff;
1088 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1089 env
->mmubpctrc
= val
& 0x3;
1091 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1092 env
->mmubpctrs
= val
& 0x3;
1094 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1095 env
->mmubpaction
= val
& 0x1fff;
1097 case 8: /* User code access, XXX */
1098 case 9: /* Supervisor code access, XXX */
1100 cpu_unassigned_access(CPU(sparc_env_get_cpu(env
)),
1101 addr
, true, false, asi
, size
);
1105 dump_asi("write", addr
, asi
, size
, val
);
1109 #endif /* CONFIG_USER_ONLY */
1110 #else /* TARGET_SPARC64 */
1112 #ifdef CONFIG_USER_ONLY
1113 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int size
,
1117 #if defined(DEBUG_ASI)
1118 target_ulong last_addr
= addr
;
1122 helper_raise_exception(env
, TT_PRIV_ACT
);
1125 helper_check_align(env
, addr
, size
- 1);
1126 addr
= asi_address_mask(env
, asi
, addr
);
1129 case 0x82: /* Primary no-fault */
1130 case 0x8a: /* Primary no-fault LE */
1131 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
1133 dump_asi("read ", last_addr
, asi
, size
, ret
);
1138 case 0x80: /* Primary */
1139 case 0x88: /* Primary LE */
1143 ret
= ldub_raw(addr
);
1146 ret
= lduw_raw(addr
);
1149 ret
= ldl_raw(addr
);
1153 ret
= ldq_raw(addr
);
1158 case 0x83: /* Secondary no-fault */
1159 case 0x8b: /* Secondary no-fault LE */
1160 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
1162 dump_asi("read ", last_addr
, asi
, size
, ret
);
1167 case 0x81: /* Secondary */
1168 case 0x89: /* Secondary LE */
1175 /* Convert from little endian */
1177 case 0x88: /* Primary LE */
1178 case 0x89: /* Secondary LE */
1179 case 0x8a: /* Primary no-fault LE */
1180 case 0x8b: /* Secondary no-fault LE */
1198 /* Convert to signed number */
1205 ret
= (int16_t) ret
;
1208 ret
= (int32_t) ret
;
1215 dump_asi("read ", last_addr
, asi
, size
, ret
);
1220 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, target_ulong val
,
1224 dump_asi("write", addr
, asi
, size
, val
);
1227 helper_raise_exception(env
, TT_PRIV_ACT
);
1230 helper_check_align(env
, addr
, size
- 1);
1231 addr
= asi_address_mask(env
, asi
, addr
);
1233 /* Convert to little endian */
1235 case 0x88: /* Primary LE */
1236 case 0x89: /* Secondary LE */
1255 case 0x80: /* Primary */
1256 case 0x88: /* Primary LE */
1275 case 0x81: /* Secondary */
1276 case 0x89: /* Secondary LE */
1280 case 0x82: /* Primary no-fault, RO */
1281 case 0x83: /* Secondary no-fault, RO */
1282 case 0x8a: /* Primary no-fault LE, RO */
1283 case 0x8b: /* Secondary no-fault LE, RO */
1285 helper_raise_exception(env
, TT_DATA_ACCESS
);
1290 #else /* CONFIG_USER_ONLY */
1292 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int size
,
1295 CPUState
*cs
= ENV_GET_CPU(env
);
1297 #if defined(DEBUG_ASI)
1298 target_ulong last_addr
= addr
;
1303 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
1304 || (cpu_has_hypervisor(env
)
1305 && asi
>= 0x30 && asi
< 0x80
1306 && !(env
->hpstate
& HS_PRIV
))) {
1307 helper_raise_exception(env
, TT_PRIV_ACT
);
1310 helper_check_align(env
, addr
, size
- 1);
1311 addr
= asi_address_mask(env
, asi
, addr
);
1313 /* process nonfaulting loads first */
1314 if ((asi
& 0xf6) == 0x82) {
1317 /* secondary space access has lowest asi bit equal to 1 */
1318 if (env
->pstate
& PS_PRIV
) {
1319 mmu_idx
= (asi
& 1) ? MMU_KERNEL_SECONDARY_IDX
: MMU_KERNEL_IDX
;
1321 mmu_idx
= (asi
& 1) ? MMU_USER_SECONDARY_IDX
: MMU_USER_IDX
;
1324 if (cpu_get_phys_page_nofault(env
, addr
, mmu_idx
) == -1ULL) {
1326 dump_asi("read ", last_addr
, asi
, size
, ret
);
1328 /* env->exception_index is set in get_physical_address_data(). */
1329 helper_raise_exception(env
, env
->exception_index
);
1332 /* convert nonfaulting load ASIs to normal load ASIs */
1337 case 0x10: /* As if user primary */
1338 case 0x11: /* As if user secondary */
1339 case 0x18: /* As if user primary LE */
1340 case 0x19: /* As if user secondary LE */
1341 case 0x80: /* Primary */
1342 case 0x81: /* Secondary */
1343 case 0x88: /* Primary LE */
1344 case 0x89: /* Secondary LE */
1345 case 0xe2: /* UA2007 Primary block init */
1346 case 0xe3: /* UA2007 Secondary block init */
1347 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
1348 if (cpu_hypervisor_mode(env
)) {
1351 ret
= cpu_ldub_hypv(env
, addr
);
1354 ret
= cpu_lduw_hypv(env
, addr
);
1357 ret
= cpu_ldl_hypv(env
, addr
);
1361 ret
= cpu_ldq_hypv(env
, addr
);
1365 /* secondary space access has lowest asi bit equal to 1 */
1369 ret
= cpu_ldub_kernel_secondary(env
, addr
);
1372 ret
= cpu_lduw_kernel_secondary(env
, addr
);
1375 ret
= cpu_ldl_kernel_secondary(env
, addr
);
1379 ret
= cpu_ldq_kernel_secondary(env
, addr
);
1385 ret
= cpu_ldub_kernel(env
, addr
);
1388 ret
= cpu_lduw_kernel(env
, addr
);
1391 ret
= cpu_ldl_kernel(env
, addr
);
1395 ret
= cpu_ldq_kernel(env
, addr
);
1401 /* secondary space access has lowest asi bit equal to 1 */
1405 ret
= cpu_ldub_user_secondary(env
, addr
);
1408 ret
= cpu_lduw_user_secondary(env
, addr
);
1411 ret
= cpu_ldl_user_secondary(env
, addr
);
1415 ret
= cpu_ldq_user_secondary(env
, addr
);
1421 ret
= cpu_ldub_user(env
, addr
);
1424 ret
= cpu_lduw_user(env
, addr
);
1427 ret
= cpu_ldl_user(env
, addr
);
1431 ret
= cpu_ldq_user(env
, addr
);
1437 case 0x14: /* Bypass */
1438 case 0x15: /* Bypass, non-cacheable */
1439 case 0x1c: /* Bypass LE */
1440 case 0x1d: /* Bypass, non-cacheable LE */
1444 ret
= ldub_phys(cs
->as
, addr
);
1447 ret
= lduw_phys(cs
->as
, addr
);
1450 ret
= ldl_phys(cs
->as
, addr
);
1454 ret
= ldq_phys(cs
->as
, addr
);
1459 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1460 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1461 Only ldda allowed */
1462 helper_raise_exception(env
, TT_ILL_INSN
);
1464 case 0x04: /* Nucleus */
1465 case 0x0c: /* Nucleus Little Endian (LE) */
1469 ret
= cpu_ldub_nucleus(env
, addr
);
1472 ret
= cpu_lduw_nucleus(env
, addr
);
1475 ret
= cpu_ldl_nucleus(env
, addr
);
1479 ret
= cpu_ldq_nucleus(env
, addr
);
1484 case 0x4a: /* UPA config */
1487 case 0x45: /* LSU */
1490 case 0x50: /* I-MMU regs */
1492 int reg
= (addr
>> 3) & 0xf;
1495 /* I-TSB Tag Target register */
1496 ret
= ultrasparc_tag_target(env
->immu
.tag_access
);
1498 ret
= env
->immuregs
[reg
];
1503 case 0x51: /* I-MMU 8k TSB pointer */
1505 /* env->immuregs[5] holds I-MMU TSB register value
1506 env->immuregs[6] holds I-MMU Tag Access register value */
1507 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
1511 case 0x52: /* I-MMU 64k TSB pointer */
1513 /* env->immuregs[5] holds I-MMU TSB register value
1514 env->immuregs[6] holds I-MMU Tag Access register value */
1515 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
1519 case 0x55: /* I-MMU data access */
1521 int reg
= (addr
>> 3) & 0x3f;
1523 ret
= env
->itlb
[reg
].tte
;
1526 case 0x56: /* I-MMU tag read */
1528 int reg
= (addr
>> 3) & 0x3f;
1530 ret
= env
->itlb
[reg
].tag
;
1533 case 0x58: /* D-MMU regs */
1535 int reg
= (addr
>> 3) & 0xf;
1538 /* D-TSB Tag Target register */
1539 ret
= ultrasparc_tag_target(env
->dmmu
.tag_access
);
1541 ret
= env
->dmmuregs
[reg
];
1545 case 0x59: /* D-MMU 8k TSB pointer */
1547 /* env->dmmuregs[5] holds D-MMU TSB register value
1548 env->dmmuregs[6] holds D-MMU Tag Access register value */
1549 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
1553 case 0x5a: /* D-MMU 64k TSB pointer */
1555 /* env->dmmuregs[5] holds D-MMU TSB register value
1556 env->dmmuregs[6] holds D-MMU Tag Access register value */
1557 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
1561 case 0x5d: /* D-MMU data access */
1563 int reg
= (addr
>> 3) & 0x3f;
1565 ret
= env
->dtlb
[reg
].tte
;
1568 case 0x5e: /* D-MMU tag read */
1570 int reg
= (addr
>> 3) & 0x3f;
1572 ret
= env
->dtlb
[reg
].tag
;
1575 case 0x48: /* Interrupt dispatch, RO */
1577 case 0x49: /* Interrupt data receive */
1578 ret
= env
->ivec_status
;
1580 case 0x7f: /* Incoming interrupt vector, RO */
1582 int reg
= (addr
>> 4) & 0x3;
1584 ret
= env
->ivec_data
[reg
];
1588 case 0x46: /* D-cache data */
1589 case 0x47: /* D-cache tag access */
1590 case 0x4b: /* E-cache error enable */
1591 case 0x4c: /* E-cache asynchronous fault status */
1592 case 0x4d: /* E-cache asynchronous fault address */
1593 case 0x4e: /* E-cache tag data */
1594 case 0x66: /* I-cache instruction access */
1595 case 0x67: /* I-cache tag access */
1596 case 0x6e: /* I-cache predecode */
1597 case 0x6f: /* I-cache LRU etc. */
1598 case 0x76: /* E-cache tag */
1599 case 0x7e: /* E-cache tag */
1601 case 0x5b: /* D-MMU data pointer */
1602 case 0x54: /* I-MMU data in, WO */
1603 case 0x57: /* I-MMU demap, WO */
1604 case 0x5c: /* D-MMU data in, WO */
1605 case 0x5f: /* D-MMU demap, WO */
1606 case 0x77: /* Interrupt vector, WO */
1608 cpu_unassigned_access(CPU(sparc_env_get_cpu(env
)),
1609 addr
, false, false, 1, size
);
1614 /* Convert from little endian */
1616 case 0x0c: /* Nucleus Little Endian (LE) */
1617 case 0x18: /* As if user primary LE */
1618 case 0x19: /* As if user secondary LE */
1619 case 0x1c: /* Bypass LE */
1620 case 0x1d: /* Bypass, non-cacheable LE */
1621 case 0x88: /* Primary LE */
1622 case 0x89: /* Secondary LE */
1640 /* Convert to signed number */
1647 ret
= (int16_t) ret
;
1650 ret
= (int32_t) ret
;
1657 dump_asi("read ", last_addr
, asi
, size
, ret
);
1662 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, target_ulong val
,
1665 CPUState
*cs
= ENV_GET_CPU(env
);
1667 dump_asi("write", addr
, asi
, size
, val
);
1672 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
1673 || (cpu_has_hypervisor(env
)
1674 && asi
>= 0x30 && asi
< 0x80
1675 && !(env
->hpstate
& HS_PRIV
))) {
1676 helper_raise_exception(env
, TT_PRIV_ACT
);
1679 helper_check_align(env
, addr
, size
- 1);
1680 addr
= asi_address_mask(env
, asi
, addr
);
1682 /* Convert to little endian */
1684 case 0x0c: /* Nucleus Little Endian (LE) */
1685 case 0x18: /* As if user primary LE */
1686 case 0x19: /* As if user secondary LE */
1687 case 0x1c: /* Bypass LE */
1688 case 0x1d: /* Bypass, non-cacheable LE */
1689 case 0x88: /* Primary LE */
1690 case 0x89: /* Secondary LE */
1709 case 0x10: /* As if user primary */
1710 case 0x11: /* As if user secondary */
1711 case 0x18: /* As if user primary LE */
1712 case 0x19: /* As if user secondary LE */
1713 case 0x80: /* Primary */
1714 case 0x81: /* Secondary */
1715 case 0x88: /* Primary LE */
1716 case 0x89: /* Secondary LE */
1717 case 0xe2: /* UA2007 Primary block init */
1718 case 0xe3: /* UA2007 Secondary block init */
1719 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
1720 if (cpu_hypervisor_mode(env
)) {
1723 cpu_stb_hypv(env
, addr
, val
);
1726 cpu_stw_hypv(env
, addr
, val
);
1729 cpu_stl_hypv(env
, addr
, val
);
1733 cpu_stq_hypv(env
, addr
, val
);
1737 /* secondary space access has lowest asi bit equal to 1 */
1741 cpu_stb_kernel_secondary(env
, addr
, val
);
1744 cpu_stw_kernel_secondary(env
, addr
, val
);
1747 cpu_stl_kernel_secondary(env
, addr
, val
);
1751 cpu_stq_kernel_secondary(env
, addr
, val
);
1757 cpu_stb_kernel(env
, addr
, val
);
1760 cpu_stw_kernel(env
, addr
, val
);
1763 cpu_stl_kernel(env
, addr
, val
);
1767 cpu_stq_kernel(env
, addr
, val
);
1773 /* secondary space access has lowest asi bit equal to 1 */
1777 cpu_stb_user_secondary(env
, addr
, val
);
1780 cpu_stw_user_secondary(env
, addr
, val
);
1783 cpu_stl_user_secondary(env
, addr
, val
);
1787 cpu_stq_user_secondary(env
, addr
, val
);
1793 cpu_stb_user(env
, addr
, val
);
1796 cpu_stw_user(env
, addr
, val
);
1799 cpu_stl_user(env
, addr
, val
);
1803 cpu_stq_user(env
, addr
, val
);
1809 case 0x14: /* Bypass */
1810 case 0x15: /* Bypass, non-cacheable */
1811 case 0x1c: /* Bypass LE */
1812 case 0x1d: /* Bypass, non-cacheable LE */
1816 stb_phys(cs
->as
, addr
, val
);
1819 stw_phys(cs
->as
, addr
, val
);
1822 stl_phys(cs
->as
, addr
, val
);
1826 stq_phys(cs
->as
, addr
, val
);
1831 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1832 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1833 Only ldda allowed */
1834 helper_raise_exception(env
, TT_ILL_INSN
);
1836 case 0x04: /* Nucleus */
1837 case 0x0c: /* Nucleus Little Endian (LE) */
1841 cpu_stb_nucleus(env
, addr
, val
);
1844 cpu_stw_nucleus(env
, addr
, val
);
1847 cpu_stl_nucleus(env
, addr
, val
);
1851 cpu_stq_nucleus(env
, addr
, val
);
1857 case 0x4a: /* UPA config */
1860 case 0x45: /* LSU */
1865 env
->lsu
= val
& (DMMU_E
| IMMU_E
);
1866 /* Mappings generated during D/I MMU disabled mode are
1867 invalid in normal mode */
1868 if (oldreg
!= env
->lsu
) {
1869 DPRINTF_MMU("LSU change: 0x%" PRIx64
" -> 0x%" PRIx64
"\n",
1872 dump_mmu(stdout
, fprintf
, env
);
1878 case 0x50: /* I-MMU regs */
1880 int reg
= (addr
>> 3) & 0xf;
1883 oldreg
= env
->immuregs
[reg
];
1887 case 1: /* Not in I-MMU */
1891 if ((val
& 1) == 0) {
1892 val
= 0; /* Clear SFSR */
1894 env
->immu
.sfsr
= val
;
1898 case 5: /* TSB access */
1899 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64
" -> 0x%016"
1900 PRIx64
"\n", env
->immu
.tsb
, val
);
1901 env
->immu
.tsb
= val
;
1903 case 6: /* Tag access */
1904 env
->immu
.tag_access
= val
;
1913 if (oldreg
!= env
->immuregs
[reg
]) {
1914 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
1915 PRIx64
"\n", reg
, oldreg
, env
->immuregs
[reg
]);
1918 dump_mmu(stdout
, fprintf
, env
);
1922 case 0x54: /* I-MMU data in */
1923 replace_tlb_1bit_lru(env
->itlb
, env
->immu
.tag_access
, val
, "immu", env
);
1925 case 0x55: /* I-MMU data access */
1927 /* TODO: auto demap */
1929 unsigned int i
= (addr
>> 3) & 0x3f;
1931 replace_tlb_entry(&env
->itlb
[i
], env
->immu
.tag_access
, val
, env
);
1934 DPRINTF_MMU("immu data access replaced entry [%i]\n", i
);
1935 dump_mmu(stdout
, fprintf
, env
);
1939 case 0x57: /* I-MMU demap */
1940 demap_tlb(env
->itlb
, addr
, "immu", env
);
1942 case 0x58: /* D-MMU regs */
1944 int reg
= (addr
>> 3) & 0xf;
1947 oldreg
= env
->dmmuregs
[reg
];
1953 if ((val
& 1) == 0) {
1954 val
= 0; /* Clear SFSR, Fault address */
1957 env
->dmmu
.sfsr
= val
;
1959 case 1: /* Primary context */
1960 env
->dmmu
.mmu_primary_context
= val
;
1961 /* can be optimized to only flush MMU_USER_IDX
1962 and MMU_KERNEL_IDX entries */
1965 case 2: /* Secondary context */
1966 env
->dmmu
.mmu_secondary_context
= val
;
1967 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1968 and MMU_KERNEL_SECONDARY_IDX entries */
1971 case 5: /* TSB access */
1972 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64
" -> 0x%016"
1973 PRIx64
"\n", env
->dmmu
.tsb
, val
);
1974 env
->dmmu
.tsb
= val
;
1976 case 6: /* Tag access */
1977 env
->dmmu
.tag_access
= val
;
1979 case 7: /* Virtual Watchpoint */
1980 case 8: /* Physical Watchpoint */
1982 env
->dmmuregs
[reg
] = val
;
1986 if (oldreg
!= env
->dmmuregs
[reg
]) {
1987 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
1988 PRIx64
"\n", reg
, oldreg
, env
->dmmuregs
[reg
]);
1991 dump_mmu(stdout
, fprintf
, env
);
1995 case 0x5c: /* D-MMU data in */
1996 replace_tlb_1bit_lru(env
->dtlb
, env
->dmmu
.tag_access
, val
, "dmmu", env
);
1998 case 0x5d: /* D-MMU data access */
2000 unsigned int i
= (addr
>> 3) & 0x3f;
2002 replace_tlb_entry(&env
->dtlb
[i
], env
->dmmu
.tag_access
, val
, env
);
2005 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i
);
2006 dump_mmu(stdout
, fprintf
, env
);
2010 case 0x5f: /* D-MMU demap */
2011 demap_tlb(env
->dtlb
, addr
, "dmmu", env
);
2013 case 0x49: /* Interrupt data receive */
2014 env
->ivec_status
= val
& 0x20;
2016 case 0x46: /* D-cache data */
2017 case 0x47: /* D-cache tag access */
2018 case 0x4b: /* E-cache error enable */
2019 case 0x4c: /* E-cache asynchronous fault status */
2020 case 0x4d: /* E-cache asynchronous fault address */
2021 case 0x4e: /* E-cache tag data */
2022 case 0x66: /* I-cache instruction access */
2023 case 0x67: /* I-cache tag access */
2024 case 0x6e: /* I-cache predecode */
2025 case 0x6f: /* I-cache LRU etc. */
2026 case 0x76: /* E-cache tag */
2027 case 0x7e: /* E-cache tag */
2029 case 0x51: /* I-MMU 8k TSB pointer, RO */
2030 case 0x52: /* I-MMU 64k TSB pointer, RO */
2031 case 0x56: /* I-MMU tag read, RO */
2032 case 0x59: /* D-MMU 8k TSB pointer, RO */
2033 case 0x5a: /* D-MMU 64k TSB pointer, RO */
2034 case 0x5b: /* D-MMU data pointer, RO */
2035 case 0x5e: /* D-MMU tag read, RO */
2036 case 0x48: /* Interrupt dispatch, RO */
2037 case 0x7f: /* Incoming interrupt vector, RO */
2038 case 0x82: /* Primary no-fault, RO */
2039 case 0x83: /* Secondary no-fault, RO */
2040 case 0x8a: /* Primary no-fault LE, RO */
2041 case 0x8b: /* Secondary no-fault LE, RO */
2043 cpu_unassigned_access(CPU(sparc_env_get_cpu(env
)),
2044 addr
, true, false, 1, size
);
2048 #endif /* CONFIG_USER_ONLY */
2050 void helper_ldda_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int rd
)
2052 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2053 || (cpu_has_hypervisor(env
)
2054 && asi
>= 0x30 && asi
< 0x80
2055 && !(env
->hpstate
& HS_PRIV
))) {
2056 helper_raise_exception(env
, TT_PRIV_ACT
);
2059 addr
= asi_address_mask(env
, asi
, addr
);
2062 #if !defined(CONFIG_USER_ONLY)
2063 case 0x24: /* Nucleus quad LDD 128 bit atomic */
2064 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE */
2065 helper_check_align(env
, addr
, 0xf);
2067 env
->gregs
[1] = cpu_ldq_nucleus(env
, addr
+ 8);
2069 bswap64s(&env
->gregs
[1]);
2071 } else if (rd
< 8) {
2072 env
->gregs
[rd
] = cpu_ldq_nucleus(env
, addr
);
2073 env
->gregs
[rd
+ 1] = cpu_ldq_nucleus(env
, addr
+ 8);
2075 bswap64s(&env
->gregs
[rd
]);
2076 bswap64s(&env
->gregs
[rd
+ 1]);
2079 env
->regwptr
[rd
] = cpu_ldq_nucleus(env
, addr
);
2080 env
->regwptr
[rd
+ 1] = cpu_ldq_nucleus(env
, addr
+ 8);
2082 bswap64s(&env
->regwptr
[rd
]);
2083 bswap64s(&env
->regwptr
[rd
+ 1]);
2089 helper_check_align(env
, addr
, 0x3);
2091 env
->gregs
[1] = helper_ld_asi(env
, addr
+ 4, asi
, 4, 0);
2092 } else if (rd
< 8) {
2093 env
->gregs
[rd
] = helper_ld_asi(env
, addr
, asi
, 4, 0);
2094 env
->gregs
[rd
+ 1] = helper_ld_asi(env
, addr
+ 4, asi
, 4, 0);
2096 env
->regwptr
[rd
] = helper_ld_asi(env
, addr
, asi
, 4, 0);
2097 env
->regwptr
[rd
+ 1] = helper_ld_asi(env
, addr
+ 4, asi
, 4, 0);
2103 void helper_ldf_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int size
,
2109 helper_check_align(env
, addr
, 3);
2110 addr
= asi_address_mask(env
, asi
, addr
);
2113 case 0xf0: /* UA2007/JPS1 Block load primary */
2114 case 0xf1: /* UA2007/JPS1 Block load secondary */
2115 case 0xf8: /* UA2007/JPS1 Block load primary LE */
2116 case 0xf9: /* UA2007/JPS1 Block load secondary LE */
2118 helper_raise_exception(env
, TT_ILL_INSN
);
2121 helper_check_align(env
, addr
, 0x3f);
2122 for (i
= 0; i
< 8; i
++, rd
+= 2, addr
+= 8) {
2123 env
->fpr
[rd
/ 2].ll
= helper_ld_asi(env
, addr
, asi
& 0x8f, 8, 0);
2127 case 0x16: /* UA2007 Block load primary, user privilege */
2128 case 0x17: /* UA2007 Block load secondary, user privilege */
2129 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2130 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2131 case 0x70: /* JPS1 Block load primary, user privilege */
2132 case 0x71: /* JPS1 Block load secondary, user privilege */
2133 case 0x78: /* JPS1 Block load primary LE, user privilege */
2134 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2136 helper_raise_exception(env
, TT_ILL_INSN
);
2139 helper_check_align(env
, addr
, 0x3f);
2140 for (i
= 0; i
< 8; i
++, rd
+= 2, addr
+= 8) {
2141 env
->fpr
[rd
/ 2].ll
= helper_ld_asi(env
, addr
, asi
& 0x19, 8, 0);
2152 val
= helper_ld_asi(env
, addr
, asi
, size
, 0);
2154 env
->fpr
[rd
/ 2].l
.lower
= val
;
2156 env
->fpr
[rd
/ 2].l
.upper
= val
;
2160 env
->fpr
[rd
/ 2].ll
= helper_ld_asi(env
, addr
, asi
, size
, 0);
2163 env
->fpr
[rd
/ 2].ll
= helper_ld_asi(env
, addr
, asi
, 8, 0);
2164 env
->fpr
[rd
/ 2 + 1].ll
= helper_ld_asi(env
, addr
+ 8, asi
, 8, 0);
2169 void helper_stf_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int size
,
2175 helper_check_align(env
, addr
, 3);
2176 addr
= asi_address_mask(env
, asi
, addr
);
2179 case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */
2180 case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */
2181 case 0xf0: /* UA2007/JPS1 Block store primary */
2182 case 0xf1: /* UA2007/JPS1 Block store secondary */
2183 case 0xf8: /* UA2007/JPS1 Block store primary LE */
2184 case 0xf9: /* UA2007/JPS1 Block store secondary LE */
2186 helper_raise_exception(env
, TT_ILL_INSN
);
2189 helper_check_align(env
, addr
, 0x3f);
2190 for (i
= 0; i
< 8; i
++, rd
+= 2, addr
+= 8) {
2191 helper_st_asi(env
, addr
, env
->fpr
[rd
/ 2].ll
, asi
& 0x8f, 8);
2195 case 0x16: /* UA2007 Block load primary, user privilege */
2196 case 0x17: /* UA2007 Block load secondary, user privilege */
2197 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2198 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2199 case 0x70: /* JPS1 Block store primary, user privilege */
2200 case 0x71: /* JPS1 Block store secondary, user privilege */
2201 case 0x78: /* JPS1 Block load primary LE, user privilege */
2202 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2204 helper_raise_exception(env
, TT_ILL_INSN
);
2207 helper_check_align(env
, addr
, 0x3f);
2208 for (i
= 0; i
< 8; i
++, rd
+= 2, addr
+= 8) {
2209 helper_st_asi(env
, addr
, env
->fpr
[rd
/ 2].ll
, asi
& 0x19, 8);
2221 val
= env
->fpr
[rd
/ 2].l
.lower
;
2223 val
= env
->fpr
[rd
/ 2].l
.upper
;
2225 helper_st_asi(env
, addr
, val
, asi
, size
);
2228 helper_st_asi(env
, addr
, env
->fpr
[rd
/ 2].ll
, asi
, size
);
2231 helper_st_asi(env
, addr
, env
->fpr
[rd
/ 2].ll
, asi
, 8);
2232 helper_st_asi(env
, addr
+ 8, env
->fpr
[rd
/ 2 + 1].ll
, asi
, 8);
2237 target_ulong
helper_casx_asi(CPUSPARCState
*env
, target_ulong addr
,
2238 target_ulong val1
, target_ulong val2
,
2243 ret
= helper_ld_asi(env
, addr
, asi
, 8, 0);
2245 helper_st_asi(env
, addr
, val1
, asi
, 8);
2249 #endif /* TARGET_SPARC64 */
2251 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2252 target_ulong
helper_cas_asi(CPUSPARCState
*env
, target_ulong addr
,
2253 target_ulong val1
, target_ulong val2
, uint32_t asi
)
2257 val2
&= 0xffffffffUL
;
2258 ret
= helper_ld_asi(env
, addr
, asi
, 4, 0);
2259 ret
&= 0xffffffffUL
;
2261 helper_st_asi(env
, addr
, val1
& 0xffffffffUL
, asi
, 4);
2265 #endif /* !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) */
2267 void helper_ldqf(CPUSPARCState
*env
, target_ulong addr
, int mem_idx
)
2269 /* XXX add 128 bit load */
2272 helper_check_align(env
, addr
, 7);
2273 #if !defined(CONFIG_USER_ONLY)
2276 u
.ll
.upper
= cpu_ldq_user(env
, addr
);
2277 u
.ll
.lower
= cpu_ldq_user(env
, addr
+ 8);
2280 case MMU_KERNEL_IDX
:
2281 u
.ll
.upper
= cpu_ldq_kernel(env
, addr
);
2282 u
.ll
.lower
= cpu_ldq_kernel(env
, addr
+ 8);
2285 #ifdef TARGET_SPARC64
2287 u
.ll
.upper
= cpu_ldq_hypv(env
, addr
);
2288 u
.ll
.lower
= cpu_ldq_hypv(env
, addr
+ 8);
2293 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx
);
2297 u
.ll
.upper
= ldq_raw(address_mask(env
, addr
));
2298 u
.ll
.lower
= ldq_raw(address_mask(env
, addr
+ 8));
2303 void helper_stqf(CPUSPARCState
*env
, target_ulong addr
, int mem_idx
)
2305 /* XXX add 128 bit store */
2308 helper_check_align(env
, addr
, 7);
2309 #if !defined(CONFIG_USER_ONLY)
2313 cpu_stq_user(env
, addr
, u
.ll
.upper
);
2314 cpu_stq_user(env
, addr
+ 8, u
.ll
.lower
);
2316 case MMU_KERNEL_IDX
:
2318 cpu_stq_kernel(env
, addr
, u
.ll
.upper
);
2319 cpu_stq_kernel(env
, addr
+ 8, u
.ll
.lower
);
2321 #ifdef TARGET_SPARC64
2324 cpu_stq_hypv(env
, addr
, u
.ll
.upper
);
2325 cpu_stq_hypv(env
, addr
+ 8, u
.ll
.lower
);
2329 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx
);
2334 stq_raw(address_mask(env
, addr
), u
.ll
.upper
);
2335 stq_raw(address_mask(env
, addr
+ 8), u
.ll
.lower
);
2339 #if !defined(CONFIG_USER_ONLY)
2340 #ifndef TARGET_SPARC64
2341 void sparc_cpu_unassigned_access(CPUState
*cs
, hwaddr addr
,
2342 bool is_write
, bool is_exec
, int is_asi
,
2345 SPARCCPU
*cpu
= SPARC_CPU(cs
);
2346 CPUSPARCState
*env
= &cpu
->env
;
2349 #ifdef DEBUG_UNASSIGNED
2351 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2352 " asi 0x%02x from " TARGET_FMT_lx
"\n",
2353 is_exec
? "exec" : is_write
? "write" : "read", size
,
2354 size
== 1 ? "" : "s", addr
, is_asi
, env
->pc
);
2356 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2357 " from " TARGET_FMT_lx
"\n",
2358 is_exec
? "exec" : is_write
? "write" : "read", size
,
2359 size
== 1 ? "" : "s", addr
, env
->pc
);
2362 /* Don't overwrite translation and access faults */
2363 fault_type
= (env
->mmuregs
[3] & 0x1c) >> 2;
2364 if ((fault_type
> 4) || (fault_type
== 0)) {
2365 env
->mmuregs
[3] = 0; /* Fault status register */
2367 env
->mmuregs
[3] |= 1 << 16;
2370 env
->mmuregs
[3] |= 1 << 5;
2373 env
->mmuregs
[3] |= 1 << 6;
2376 env
->mmuregs
[3] |= 1 << 7;
2378 env
->mmuregs
[3] |= (5 << 2) | 2;
2379 /* SuperSPARC will never place instruction fault addresses in the FAR */
2381 env
->mmuregs
[4] = addr
; /* Fault address register */
2384 /* overflow (same type fault was not read before another fault) */
2385 if (fault_type
== ((env
->mmuregs
[3] & 0x1c)) >> 2) {
2386 env
->mmuregs
[3] |= 1;
2389 if ((env
->mmuregs
[0] & MMU_E
) && !(env
->mmuregs
[0] & MMU_NF
)) {
2391 helper_raise_exception(env
, TT_CODE_ACCESS
);
2393 helper_raise_exception(env
, TT_DATA_ACCESS
);
2397 /* flush neverland mappings created during no-fault mode,
2398 so the sequential MMU faults report proper fault types */
2399 if (env
->mmuregs
[0] & MMU_NF
) {
2404 void sparc_cpu_unassigned_access(CPUState
*cs
, hwaddr addr
,
2405 bool is_write
, bool is_exec
, int is_asi
,
2408 SPARCCPU
*cpu
= SPARC_CPU(cs
);
2409 CPUSPARCState
*env
= &cpu
->env
;
2411 #ifdef DEBUG_UNASSIGNED
2412 printf("Unassigned mem access to " TARGET_FMT_plx
" from " TARGET_FMT_lx
2413 "\n", addr
, env
->pc
);
2417 helper_raise_exception(env
, TT_CODE_ACCESS
);
2419 helper_raise_exception(env
, TT_DATA_ACCESS
);
2425 #if !defined(CONFIG_USER_ONLY)
2426 static void QEMU_NORETURN
do_unaligned_access(CPUSPARCState
*env
,
2427 target_ulong addr
, int is_write
,
2428 int is_user
, uintptr_t retaddr
)
2430 #ifdef DEBUG_UNALIGNED
2431 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
2432 "\n", addr
, env
->pc
);
2435 cpu_restore_state(env
, retaddr
);
2437 helper_raise_exception(env
, TT_UNALIGNED
);
2440 /* try to fill the TLB and return an exception if error. If retaddr is
2441 NULL, it means that the function was called in C code (i.e. not
2442 from generated code or from helper.c) */
2443 /* XXX: fix it to restore all registers */
2444 void tlb_fill(CPUSPARCState
*env
, target_ulong addr
, int is_write
, int mmu_idx
,
2449 ret
= cpu_sparc_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
);
2452 cpu_restore_state(env
, retaddr
);