]>
git.proxmox.com Git - mirror_qemu.git/blob - target-sparc/ldst_helper.c
2 * Helpers for loads and stores
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
25 //#define DEBUG_UNALIGNED
26 //#define DEBUG_UNASSIGNED
28 //#define DEBUG_CACHE_CONTROL
31 #define DPRINTF_MMU(fmt, ...) \
32 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
34 #define DPRINTF_MMU(fmt, ...) do {} while (0)
38 #define DPRINTF_MXCC(fmt, ...) \
39 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
41 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
45 #define DPRINTF_ASI(fmt, ...) \
46 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
49 #ifdef DEBUG_CACHE_CONTROL
50 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
51 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
53 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
58 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
60 #define AM_CHECK(env1) (1)
64 #define QT0 (env->qt0)
65 #define QT1 (env->qt1)
67 #if !defined(CONFIG_USER_ONLY)
68 static void QEMU_NORETURN
do_unaligned_access(CPUSPARCState
*env
,
69 target_ulong addr
, int is_write
,
70 int is_user
, uintptr_t retaddr
);
71 #include "exec/softmmu_exec.h"
72 #define MMUSUFFIX _mmu
76 #include "exec/softmmu_template.h"
79 #include "exec/softmmu_template.h"
82 #include "exec/softmmu_template.h"
85 #include "exec/softmmu_template.h"
88 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
89 /* Calculates TSB pointer value for fault page size 8k or 64k */
90 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register
,
91 uint64_t tag_access_register
,
94 uint64_t tsb_base
= tsb_register
& ~0x1fffULL
;
95 int tsb_split
= (tsb_register
& 0x1000ULL
) ? 1 : 0;
96 int tsb_size
= tsb_register
& 0xf;
98 /* discard lower 13 bits which hold tag access context */
99 uint64_t tag_access_va
= tag_access_register
& ~0x1fffULL
;
101 /* now reorder bits */
102 uint64_t tsb_base_mask
= ~0x1fffULL
;
103 uint64_t va
= tag_access_va
;
105 /* move va bits to correct position */
106 if (page_size
== 8*1024) {
108 } else if (page_size
== 64*1024) {
113 tsb_base_mask
<<= tsb_size
;
116 /* calculate tsb_base mask and adjust va if split is in use */
118 if (page_size
== 8*1024) {
119 va
&= ~(1ULL << (13 + tsb_size
));
120 } else if (page_size
== 64*1024) {
121 va
|= (1ULL << (13 + tsb_size
));
126 return ((tsb_base
& tsb_base_mask
) | (va
& ~tsb_base_mask
)) & ~0xfULL
;
129 /* Calculates tag target register value by reordering bits
130 in tag access register */
131 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register
)
133 return ((tag_access_register
& 0x1fff) << 48) | (tag_access_register
>> 22);
136 static void replace_tlb_entry(SparcTLBEntry
*tlb
,
137 uint64_t tlb_tag
, uint64_t tlb_tte
,
140 target_ulong mask
, size
, va
, offset
;
142 /* flush page range if translation is valid */
143 if (TTE_IS_VALID(tlb
->tte
)) {
145 mask
= 0xffffffffffffe000ULL
;
146 mask
<<= 3 * ((tlb
->tte
>> 61) & 3);
149 va
= tlb
->tag
& mask
;
151 for (offset
= 0; offset
< size
; offset
+= TARGET_PAGE_SIZE
) {
152 tlb_flush_page(env1
, va
+ offset
);
160 static void demap_tlb(SparcTLBEntry
*tlb
, target_ulong demap_addr
,
161 const char *strmmu
, CPUSPARCState
*env1
)
167 int is_demap_context
= (demap_addr
>> 6) & 1;
170 switch ((demap_addr
>> 4) & 3) {
171 case 0: /* primary */
172 context
= env1
->dmmu
.mmu_primary_context
;
174 case 1: /* secondary */
175 context
= env1
->dmmu
.mmu_secondary_context
;
177 case 2: /* nucleus */
180 case 3: /* reserved */
185 for (i
= 0; i
< 64; i
++) {
186 if (TTE_IS_VALID(tlb
[i
].tte
)) {
188 if (is_demap_context
) {
189 /* will remove non-global entries matching context value */
190 if (TTE_IS_GLOBAL(tlb
[i
].tte
) ||
191 !tlb_compare_context(&tlb
[i
], context
)) {
196 will remove any entry matching VA */
197 mask
= 0xffffffffffffe000ULL
;
198 mask
<<= 3 * ((tlb
[i
].tte
>> 61) & 3);
200 if (!compare_masked(demap_addr
, tlb
[i
].tag
, mask
)) {
204 /* entry should be global or matching context value */
205 if (!TTE_IS_GLOBAL(tlb
[i
].tte
) &&
206 !tlb_compare_context(&tlb
[i
], context
)) {
211 replace_tlb_entry(&tlb
[i
], 0, 0, env1
);
213 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu
, i
);
214 dump_mmu(stdout
, fprintf
, env1
);
220 static void replace_tlb_1bit_lru(SparcTLBEntry
*tlb
,
221 uint64_t tlb_tag
, uint64_t tlb_tte
,
222 const char *strmmu
, CPUSPARCState
*env1
)
224 unsigned int i
, replace_used
;
226 /* Try replacing invalid entry */
227 for (i
= 0; i
< 64; i
++) {
228 if (!TTE_IS_VALID(tlb
[i
].tte
)) {
229 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
231 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu
, i
);
232 dump_mmu(stdout
, fprintf
, env1
);
238 /* All entries are valid, try replacing unlocked entry */
240 for (replace_used
= 0; replace_used
< 2; ++replace_used
) {
242 /* Used entries are not replaced on first pass */
244 for (i
= 0; i
< 64; i
++) {
245 if (!TTE_IS_LOCKED(tlb
[i
].tte
) && !TTE_IS_USED(tlb
[i
].tte
)) {
247 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
249 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
250 strmmu
, (replace_used
? "used" : "unused"), i
);
251 dump_mmu(stdout
, fprintf
, env1
);
257 /* Now reset used bit and search for unused entries again */
259 for (i
= 0; i
< 64; i
++) {
260 TTE_SET_UNUSED(tlb
[i
].tte
);
265 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu
);
272 static inline target_ulong
address_mask(CPUSPARCState
*env1
, target_ulong addr
)
274 #ifdef TARGET_SPARC64
275 if (AM_CHECK(env1
)) {
276 addr
&= 0xffffffffULL
;
282 /* returns true if access using this ASI is to have address translated by MMU
283 otherwise access is to raw physical address */
284 static inline int is_translating_asi(int asi
)
286 #ifdef TARGET_SPARC64
287 /* Ultrasparc IIi translating asi
288 - note this list is defined by cpu implementation
304 /* TODO: check sparc32 bits */
309 static inline target_ulong
asi_address_mask(CPUSPARCState
*env
,
310 int asi
, target_ulong addr
)
312 if (is_translating_asi(asi
)) {
313 return address_mask(env
, addr
);
319 void helper_check_align(CPUSPARCState
*env
, target_ulong addr
, uint32_t align
)
322 #ifdef DEBUG_UNALIGNED
323 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
324 "\n", addr
, env
->pc
);
326 helper_raise_exception(env
, TT_UNALIGNED
);
330 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
332 static void dump_mxcc(CPUSPARCState
*env
)
334 printf("mxccdata: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
336 env
->mxccdata
[0], env
->mxccdata
[1],
337 env
->mxccdata
[2], env
->mxccdata
[3]);
338 printf("mxccregs: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
340 " %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
342 env
->mxccregs
[0], env
->mxccregs
[1],
343 env
->mxccregs
[2], env
->mxccregs
[3],
344 env
->mxccregs
[4], env
->mxccregs
[5],
345 env
->mxccregs
[6], env
->mxccregs
[7]);
349 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
350 && defined(DEBUG_ASI)
351 static void dump_asi(const char *txt
, target_ulong addr
, int asi
, int size
,
356 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %02" PRIx64
"\n", txt
,
357 addr
, asi
, r1
& 0xff);
360 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %04" PRIx64
"\n", txt
,
361 addr
, asi
, r1
& 0xffff);
364 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %08" PRIx64
"\n", txt
,
365 addr
, asi
, r1
& 0xffffffff);
368 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %016" PRIx64
"\n", txt
,
375 #ifndef TARGET_SPARC64
376 #ifndef CONFIG_USER_ONLY
379 /* Leon3 cache control */
381 static void leon3_cache_control_st(CPUSPARCState
*env
, target_ulong addr
,
382 uint64_t val
, int size
)
384 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64
", size:%d\n",
388 DPRINTF_CACHE_CONTROL("32bits only\n");
393 case 0x00: /* Cache control */
395 /* These values must always be read as zeros */
396 val
&= ~CACHE_CTRL_FD
;
397 val
&= ~CACHE_CTRL_FI
;
398 val
&= ~CACHE_CTRL_IB
;
399 val
&= ~CACHE_CTRL_IP
;
400 val
&= ~CACHE_CTRL_DP
;
402 env
->cache_control
= val
;
404 case 0x04: /* Instruction cache configuration */
405 case 0x08: /* Data cache configuration */
409 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr
);
414 static uint64_t leon3_cache_control_ld(CPUSPARCState
*env
, target_ulong addr
,
420 DPRINTF_CACHE_CONTROL("32bits only\n");
425 case 0x00: /* Cache control */
426 ret
= env
->cache_control
;
429 /* Configuration registers are read and only always keep those
432 case 0x04: /* Instruction cache configuration */
435 case 0x08: /* Data cache configuration */
439 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr
);
442 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64
", size:%d\n",
447 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int size
,
450 CPUState
*cs
= ENV_GET_CPU(env
);
452 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
453 uint32_t last_addr
= addr
;
456 helper_check_align(env
, addr
, size
- 1);
458 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
460 case 0x00: /* Leon3 Cache Control */
461 case 0x08: /* Leon3 Instruction Cache config */
462 case 0x0C: /* Leon3 Date Cache config */
463 if (env
->def
->features
& CPU_FEATURE_CACHE_CTRL
) {
464 ret
= leon3_cache_control_ld(env
, addr
, size
);
467 case 0x01c00a00: /* MXCC control register */
469 ret
= env
->mxccregs
[3];
471 qemu_log_mask(LOG_UNIMP
,
472 "%08x: unimplemented access size: %d\n", addr
,
476 case 0x01c00a04: /* MXCC control register */
478 ret
= env
->mxccregs
[3];
480 qemu_log_mask(LOG_UNIMP
,
481 "%08x: unimplemented access size: %d\n", addr
,
485 case 0x01c00c00: /* Module reset register */
487 ret
= env
->mxccregs
[5];
488 /* should we do something here? */
490 qemu_log_mask(LOG_UNIMP
,
491 "%08x: unimplemented access size: %d\n", addr
,
495 case 0x01c00f00: /* MBus port address register */
497 ret
= env
->mxccregs
[7];
499 qemu_log_mask(LOG_UNIMP
,
500 "%08x: unimplemented access size: %d\n", addr
,
505 qemu_log_mask(LOG_UNIMP
,
506 "%08x: unimplemented address, size: %d\n", addr
,
510 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
511 "addr = %08x -> ret = %" PRIx64
","
512 "addr = %08x\n", asi
, size
, sign
, last_addr
, ret
, addr
);
517 case 3: /* MMU probe */
518 case 0x18: /* LEON3 MMU probe */
522 mmulev
= (addr
>> 8) & 15;
526 ret
= mmu_probe(env
, addr
, mmulev
);
528 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64
"\n",
532 case 4: /* read MMU regs */
533 case 0x19: /* LEON3 read MMU regs */
535 int reg
= (addr
>> 8) & 0x1f;
537 ret
= env
->mmuregs
[reg
];
538 if (reg
== 3) { /* Fault status cleared on read */
540 } else if (reg
== 0x13) { /* Fault status read */
541 ret
= env
->mmuregs
[3];
542 } else if (reg
== 0x14) { /* Fault address read */
543 ret
= env
->mmuregs
[4];
545 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64
"\n", reg
, ret
);
548 case 5: /* Turbosparc ITLB Diagnostic */
549 case 6: /* Turbosparc DTLB Diagnostic */
550 case 7: /* Turbosparc IOTLB Diagnostic */
552 case 9: /* Supervisor code access */
555 ret
= cpu_ldub_code(env
, addr
);
558 ret
= cpu_lduw_code(env
, addr
);
562 ret
= cpu_ldl_code(env
, addr
);
565 ret
= cpu_ldq_code(env
, addr
);
569 case 0xa: /* User data access */
572 ret
= cpu_ldub_user(env
, addr
);
575 ret
= cpu_lduw_user(env
, addr
);
579 ret
= cpu_ldl_user(env
, addr
);
582 ret
= cpu_ldq_user(env
, addr
);
586 case 0xb: /* Supervisor data access */
589 ret
= cpu_ldub_kernel(env
, addr
);
592 ret
= cpu_lduw_kernel(env
, addr
);
596 ret
= cpu_ldl_kernel(env
, addr
);
599 ret
= cpu_ldq_kernel(env
, addr
);
603 case 0xc: /* I-cache tag */
604 case 0xd: /* I-cache data */
605 case 0xe: /* D-cache tag */
606 case 0xf: /* D-cache data */
608 case 0x20: /* MMU passthrough */
609 case 0x1c: /* LEON MMU passthrough */
612 ret
= ldub_phys(cs
->as
, addr
);
615 ret
= lduw_phys(cs
->as
, addr
);
619 ret
= ldl_phys(cs
->as
, addr
);
622 ret
= ldq_phys(cs
->as
, addr
);
626 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
629 ret
= ldub_phys(cs
->as
, (hwaddr
)addr
630 | ((hwaddr
)(asi
& 0xf) << 32));
633 ret
= lduw_phys(cs
->as
, (hwaddr
)addr
634 | ((hwaddr
)(asi
& 0xf) << 32));
638 ret
= ldl_phys(cs
->as
, (hwaddr
)addr
639 | ((hwaddr
)(asi
& 0xf) << 32));
642 ret
= ldq_phys(cs
->as
, (hwaddr
)addr
643 | ((hwaddr
)(asi
& 0xf) << 32));
647 case 0x30: /* Turbosparc secondary cache diagnostic */
648 case 0x31: /* Turbosparc RAM snoop */
649 case 0x32: /* Turbosparc page table descriptor diagnostic */
650 case 0x39: /* data cache diagnostic register */
653 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
655 int reg
= (addr
>> 8) & 3;
658 case 0: /* Breakpoint Value (Addr) */
659 ret
= env
->mmubpregs
[reg
];
661 case 1: /* Breakpoint Mask */
662 ret
= env
->mmubpregs
[reg
];
664 case 2: /* Breakpoint Control */
665 ret
= env
->mmubpregs
[reg
];
667 case 3: /* Breakpoint Status */
668 ret
= env
->mmubpregs
[reg
];
669 env
->mmubpregs
[reg
] = 0ULL;
672 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64
"\n", reg
,
676 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
677 ret
= env
->mmubpctrv
;
679 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
680 ret
= env
->mmubpctrc
;
682 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
683 ret
= env
->mmubpctrs
;
685 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
686 ret
= env
->mmubpaction
;
688 case 8: /* User code access, XXX */
690 cpu_unassigned_access(CPU(sparc_env_get_cpu(env
)),
691 addr
, false, false, asi
, size
);
711 dump_asi("read ", last_addr
, asi
, size
, ret
);
716 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, uint64_t val
, int asi
,
719 CPUState
*cs
= ENV_GET_CPU(env
);
720 helper_check_align(env
, addr
, size
- 1);
722 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
724 case 0x00: /* Leon3 Cache Control */
725 case 0x08: /* Leon3 Instruction Cache config */
726 case 0x0C: /* Leon3 Date Cache config */
727 if (env
->def
->features
& CPU_FEATURE_CACHE_CTRL
) {
728 leon3_cache_control_st(env
, addr
, val
, size
);
732 case 0x01c00000: /* MXCC stream data register 0 */
734 env
->mxccdata
[0] = val
;
736 qemu_log_mask(LOG_UNIMP
,
737 "%08x: unimplemented access size: %d\n", addr
,
741 case 0x01c00008: /* MXCC stream data register 1 */
743 env
->mxccdata
[1] = val
;
745 qemu_log_mask(LOG_UNIMP
,
746 "%08x: unimplemented access size: %d\n", addr
,
750 case 0x01c00010: /* MXCC stream data register 2 */
752 env
->mxccdata
[2] = val
;
754 qemu_log_mask(LOG_UNIMP
,
755 "%08x: unimplemented access size: %d\n", addr
,
759 case 0x01c00018: /* MXCC stream data register 3 */
761 env
->mxccdata
[3] = val
;
763 qemu_log_mask(LOG_UNIMP
,
764 "%08x: unimplemented access size: %d\n", addr
,
768 case 0x01c00100: /* MXCC stream source */
770 env
->mxccregs
[0] = val
;
772 qemu_log_mask(LOG_UNIMP
,
773 "%08x: unimplemented access size: %d\n", addr
,
776 env
->mxccdata
[0] = ldq_phys(cs
->as
,
777 (env
->mxccregs
[0] & 0xffffffffULL
) +
779 env
->mxccdata
[1] = ldq_phys(cs
->as
,
780 (env
->mxccregs
[0] & 0xffffffffULL
) +
782 env
->mxccdata
[2] = ldq_phys(cs
->as
,
783 (env
->mxccregs
[0] & 0xffffffffULL
) +
785 env
->mxccdata
[3] = ldq_phys(cs
->as
,
786 (env
->mxccregs
[0] & 0xffffffffULL
) +
789 case 0x01c00200: /* MXCC stream destination */
791 env
->mxccregs
[1] = val
;
793 qemu_log_mask(LOG_UNIMP
,
794 "%08x: unimplemented access size: %d\n", addr
,
797 stq_phys(cs
->as
, (env
->mxccregs
[1] & 0xffffffffULL
) + 0,
799 stq_phys(cs
->as
, (env
->mxccregs
[1] & 0xffffffffULL
) + 8,
801 stq_phys(cs
->as
, (env
->mxccregs
[1] & 0xffffffffULL
) + 16,
803 stq_phys(cs
->as
, (env
->mxccregs
[1] & 0xffffffffULL
) + 24,
806 case 0x01c00a00: /* MXCC control register */
808 env
->mxccregs
[3] = val
;
810 qemu_log_mask(LOG_UNIMP
,
811 "%08x: unimplemented access size: %d\n", addr
,
815 case 0x01c00a04: /* MXCC control register */
817 env
->mxccregs
[3] = (env
->mxccregs
[3] & 0xffffffff00000000ULL
)
820 qemu_log_mask(LOG_UNIMP
,
821 "%08x: unimplemented access size: %d\n", addr
,
825 case 0x01c00e00: /* MXCC error register */
826 /* writing a 1 bit clears the error */
828 env
->mxccregs
[6] &= ~val
;
830 qemu_log_mask(LOG_UNIMP
,
831 "%08x: unimplemented access size: %d\n", addr
,
835 case 0x01c00f00: /* MBus port address register */
837 env
->mxccregs
[7] = val
;
839 qemu_log_mask(LOG_UNIMP
,
840 "%08x: unimplemented access size: %d\n", addr
,
845 qemu_log_mask(LOG_UNIMP
,
846 "%08x: unimplemented address, size: %d\n", addr
,
850 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64
"\n",
851 asi
, size
, addr
, val
);
856 case 3: /* MMU flush */
857 case 0x18: /* LEON3 MMU flush */
861 mmulev
= (addr
>> 8) & 15;
862 DPRINTF_MMU("mmu flush level %d\n", mmulev
);
864 case 0: /* flush page */
865 tlb_flush_page(env
, addr
& 0xfffff000);
867 case 1: /* flush segment (256k) */
868 case 2: /* flush region (16M) */
869 case 3: /* flush context (4G) */
870 case 4: /* flush entire */
877 dump_mmu(stdout
, fprintf
, env
);
881 case 4: /* write MMU regs */
882 case 0x19: /* LEON3 write MMU regs */
884 int reg
= (addr
>> 8) & 0x1f;
887 oldreg
= env
->mmuregs
[reg
];
889 case 0: /* Control Register */
890 env
->mmuregs
[reg
] = (env
->mmuregs
[reg
] & 0xff000000) |
892 /* Mappings generated during no-fault mode or MMU
893 disabled mode are invalid in normal mode */
894 if ((oldreg
& (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)) !=
895 (env
->mmuregs
[reg
] & (MMU_E
| MMU_NF
| env
->def
->mmu_bm
))) {
899 case 1: /* Context Table Pointer Register */
900 env
->mmuregs
[reg
] = val
& env
->def
->mmu_ctpr_mask
;
902 case 2: /* Context Register */
903 env
->mmuregs
[reg
] = val
& env
->def
->mmu_cxr_mask
;
904 if (oldreg
!= env
->mmuregs
[reg
]) {
905 /* we flush when the MMU context changes because
906 QEMU has no MMU context support */
910 case 3: /* Synchronous Fault Status Register with Clear */
911 case 4: /* Synchronous Fault Address Register */
913 case 0x10: /* TLB Replacement Control Register */
914 env
->mmuregs
[reg
] = val
& env
->def
->mmu_trcr_mask
;
916 case 0x13: /* Synchronous Fault Status Register with Read
918 env
->mmuregs
[3] = val
& env
->def
->mmu_sfsr_mask
;
920 case 0x14: /* Synchronous Fault Address Register */
921 env
->mmuregs
[4] = val
;
924 env
->mmuregs
[reg
] = val
;
927 if (oldreg
!= env
->mmuregs
[reg
]) {
928 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
929 reg
, oldreg
, env
->mmuregs
[reg
]);
932 dump_mmu(stdout
, fprintf
, env
);
936 case 5: /* Turbosparc ITLB Diagnostic */
937 case 6: /* Turbosparc DTLB Diagnostic */
938 case 7: /* Turbosparc IOTLB Diagnostic */
940 case 0xa: /* User data access */
943 cpu_stb_user(env
, addr
, val
);
946 cpu_stw_user(env
, addr
, val
);
950 cpu_stl_user(env
, addr
, val
);
953 cpu_stq_user(env
, addr
, val
);
957 case 0xb: /* Supervisor data access */
960 cpu_stb_kernel(env
, addr
, val
);
963 cpu_stw_kernel(env
, addr
, val
);
967 cpu_stl_kernel(env
, addr
, val
);
970 cpu_stq_kernel(env
, addr
, val
);
974 case 0xc: /* I-cache tag */
975 case 0xd: /* I-cache data */
976 case 0xe: /* D-cache tag */
977 case 0xf: /* D-cache data */
978 case 0x10: /* I/D-cache flush page */
979 case 0x11: /* I/D-cache flush segment */
980 case 0x12: /* I/D-cache flush region */
981 case 0x13: /* I/D-cache flush context */
982 case 0x14: /* I/D-cache flush user */
984 case 0x17: /* Block copy, sta access */
990 uint32_t src
= val
& ~3, dst
= addr
& ~3, temp
;
992 for (i
= 0; i
< 32; i
+= 4, src
+= 4, dst
+= 4) {
993 temp
= cpu_ldl_kernel(env
, src
);
994 cpu_stl_kernel(env
, dst
, temp
);
998 case 0x1f: /* Block fill, stda access */
1001 fill 32 bytes with val */
1003 uint32_t dst
= addr
& 7;
1005 for (i
= 0; i
< 32; i
+= 8, dst
+= 8) {
1006 cpu_stq_kernel(env
, dst
, val
);
1010 case 0x20: /* MMU passthrough */
1011 case 0x1c: /* LEON MMU passthrough */
1015 stb_phys(cs
->as
, addr
, val
);
1018 stw_phys(cs
->as
, addr
, val
);
1022 stl_phys(cs
->as
, addr
, val
);
1025 stq_phys(cs
->as
, addr
, val
);
1030 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1034 stb_phys(cs
->as
, (hwaddr
)addr
1035 | ((hwaddr
)(asi
& 0xf) << 32), val
);
1038 stw_phys(cs
->as
, (hwaddr
)addr
1039 | ((hwaddr
)(asi
& 0xf) << 32), val
);
1043 stl_phys(cs
->as
, (hwaddr
)addr
1044 | ((hwaddr
)(asi
& 0xf) << 32), val
);
1047 stq_phys(cs
->as
, (hwaddr
)addr
1048 | ((hwaddr
)(asi
& 0xf) << 32), val
);
1053 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1054 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1055 Turbosparc snoop RAM */
1056 case 0x32: /* store buffer control or Turbosparc page table
1057 descriptor diagnostic */
1058 case 0x36: /* I-cache flash clear */
1059 case 0x37: /* D-cache flash clear */
1061 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1063 int reg
= (addr
>> 8) & 3;
1066 case 0: /* Breakpoint Value (Addr) */
1067 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1069 case 1: /* Breakpoint Mask */
1070 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1072 case 2: /* Breakpoint Control */
1073 env
->mmubpregs
[reg
] = (val
& 0x7fULL
);
1075 case 3: /* Breakpoint Status */
1076 env
->mmubpregs
[reg
] = (val
& 0xfULL
);
1079 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg
,
1083 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1084 env
->mmubpctrv
= val
& 0xffffffff;
1086 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1087 env
->mmubpctrc
= val
& 0x3;
1089 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1090 env
->mmubpctrs
= val
& 0x3;
1092 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1093 env
->mmubpaction
= val
& 0x1fff;
1095 case 8: /* User code access, XXX */
1096 case 9: /* Supervisor code access, XXX */
1098 cpu_unassigned_access(CPU(sparc_env_get_cpu(env
)),
1099 addr
, true, false, asi
, size
);
1103 dump_asi("write", addr
, asi
, size
, val
);
1107 #endif /* CONFIG_USER_ONLY */
1108 #else /* TARGET_SPARC64 */
1110 #ifdef CONFIG_USER_ONLY
1111 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int size
,
1115 #if defined(DEBUG_ASI)
1116 target_ulong last_addr
= addr
;
1120 helper_raise_exception(env
, TT_PRIV_ACT
);
1123 helper_check_align(env
, addr
, size
- 1);
1124 addr
= asi_address_mask(env
, asi
, addr
);
1127 case 0x82: /* Primary no-fault */
1128 case 0x8a: /* Primary no-fault LE */
1129 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
1131 dump_asi("read ", last_addr
, asi
, size
, ret
);
1136 case 0x80: /* Primary */
1137 case 0x88: /* Primary LE */
1141 ret
= ldub_raw(addr
);
1144 ret
= lduw_raw(addr
);
1147 ret
= ldl_raw(addr
);
1151 ret
= ldq_raw(addr
);
1156 case 0x83: /* Secondary no-fault */
1157 case 0x8b: /* Secondary no-fault LE */
1158 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
1160 dump_asi("read ", last_addr
, asi
, size
, ret
);
1165 case 0x81: /* Secondary */
1166 case 0x89: /* Secondary LE */
1173 /* Convert from little endian */
1175 case 0x88: /* Primary LE */
1176 case 0x89: /* Secondary LE */
1177 case 0x8a: /* Primary no-fault LE */
1178 case 0x8b: /* Secondary no-fault LE */
1196 /* Convert to signed number */
1203 ret
= (int16_t) ret
;
1206 ret
= (int32_t) ret
;
1213 dump_asi("read ", last_addr
, asi
, size
, ret
);
1218 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, target_ulong val
,
1222 dump_asi("write", addr
, asi
, size
, val
);
1225 helper_raise_exception(env
, TT_PRIV_ACT
);
1228 helper_check_align(env
, addr
, size
- 1);
1229 addr
= asi_address_mask(env
, asi
, addr
);
1231 /* Convert to little endian */
1233 case 0x88: /* Primary LE */
1234 case 0x89: /* Secondary LE */
1253 case 0x80: /* Primary */
1254 case 0x88: /* Primary LE */
1273 case 0x81: /* Secondary */
1274 case 0x89: /* Secondary LE */
1278 case 0x82: /* Primary no-fault, RO */
1279 case 0x83: /* Secondary no-fault, RO */
1280 case 0x8a: /* Primary no-fault LE, RO */
1281 case 0x8b: /* Secondary no-fault LE, RO */
1283 helper_raise_exception(env
, TT_DATA_ACCESS
);
1288 #else /* CONFIG_USER_ONLY */
1290 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int size
,
1293 CPUState
*cs
= ENV_GET_CPU(env
);
1295 #if defined(DEBUG_ASI)
1296 target_ulong last_addr
= addr
;
1301 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
1302 || (cpu_has_hypervisor(env
)
1303 && asi
>= 0x30 && asi
< 0x80
1304 && !(env
->hpstate
& HS_PRIV
))) {
1305 helper_raise_exception(env
, TT_PRIV_ACT
);
1308 helper_check_align(env
, addr
, size
- 1);
1309 addr
= asi_address_mask(env
, asi
, addr
);
1311 /* process nonfaulting loads first */
1312 if ((asi
& 0xf6) == 0x82) {
1315 /* secondary space access has lowest asi bit equal to 1 */
1316 if (env
->pstate
& PS_PRIV
) {
1317 mmu_idx
= (asi
& 1) ? MMU_KERNEL_SECONDARY_IDX
: MMU_KERNEL_IDX
;
1319 mmu_idx
= (asi
& 1) ? MMU_USER_SECONDARY_IDX
: MMU_USER_IDX
;
1322 if (cpu_get_phys_page_nofault(env
, addr
, mmu_idx
) == -1ULL) {
1324 dump_asi("read ", last_addr
, asi
, size
, ret
);
1326 /* env->exception_index is set in get_physical_address_data(). */
1327 helper_raise_exception(env
, env
->exception_index
);
1330 /* convert nonfaulting load ASIs to normal load ASIs */
1335 case 0x10: /* As if user primary */
1336 case 0x11: /* As if user secondary */
1337 case 0x18: /* As if user primary LE */
1338 case 0x19: /* As if user secondary LE */
1339 case 0x80: /* Primary */
1340 case 0x81: /* Secondary */
1341 case 0x88: /* Primary LE */
1342 case 0x89: /* Secondary LE */
1343 case 0xe2: /* UA2007 Primary block init */
1344 case 0xe3: /* UA2007 Secondary block init */
1345 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
1346 if (cpu_hypervisor_mode(env
)) {
1349 ret
= cpu_ldub_hypv(env
, addr
);
1352 ret
= cpu_lduw_hypv(env
, addr
);
1355 ret
= cpu_ldl_hypv(env
, addr
);
1359 ret
= cpu_ldq_hypv(env
, addr
);
1363 /* secondary space access has lowest asi bit equal to 1 */
1367 ret
= cpu_ldub_kernel_secondary(env
, addr
);
1370 ret
= cpu_lduw_kernel_secondary(env
, addr
);
1373 ret
= cpu_ldl_kernel_secondary(env
, addr
);
1377 ret
= cpu_ldq_kernel_secondary(env
, addr
);
1383 ret
= cpu_ldub_kernel(env
, addr
);
1386 ret
= cpu_lduw_kernel(env
, addr
);
1389 ret
= cpu_ldl_kernel(env
, addr
);
1393 ret
= cpu_ldq_kernel(env
, addr
);
1399 /* secondary space access has lowest asi bit equal to 1 */
1403 ret
= cpu_ldub_user_secondary(env
, addr
);
1406 ret
= cpu_lduw_user_secondary(env
, addr
);
1409 ret
= cpu_ldl_user_secondary(env
, addr
);
1413 ret
= cpu_ldq_user_secondary(env
, addr
);
1419 ret
= cpu_ldub_user(env
, addr
);
1422 ret
= cpu_lduw_user(env
, addr
);
1425 ret
= cpu_ldl_user(env
, addr
);
1429 ret
= cpu_ldq_user(env
, addr
);
1435 case 0x14: /* Bypass */
1436 case 0x15: /* Bypass, non-cacheable */
1437 case 0x1c: /* Bypass LE */
1438 case 0x1d: /* Bypass, non-cacheable LE */
1442 ret
= ldub_phys(cs
->as
, addr
);
1445 ret
= lduw_phys(cs
->as
, addr
);
1448 ret
= ldl_phys(cs
->as
, addr
);
1452 ret
= ldq_phys(cs
->as
, addr
);
1457 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1458 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1459 Only ldda allowed */
1460 helper_raise_exception(env
, TT_ILL_INSN
);
1462 case 0x04: /* Nucleus */
1463 case 0x0c: /* Nucleus Little Endian (LE) */
1467 ret
= cpu_ldub_nucleus(env
, addr
);
1470 ret
= cpu_lduw_nucleus(env
, addr
);
1473 ret
= cpu_ldl_nucleus(env
, addr
);
1477 ret
= cpu_ldq_nucleus(env
, addr
);
1482 case 0x4a: /* UPA config */
1485 case 0x45: /* LSU */
1488 case 0x50: /* I-MMU regs */
1490 int reg
= (addr
>> 3) & 0xf;
1493 /* I-TSB Tag Target register */
1494 ret
= ultrasparc_tag_target(env
->immu
.tag_access
);
1496 ret
= env
->immuregs
[reg
];
1501 case 0x51: /* I-MMU 8k TSB pointer */
1503 /* env->immuregs[5] holds I-MMU TSB register value
1504 env->immuregs[6] holds I-MMU Tag Access register value */
1505 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
1509 case 0x52: /* I-MMU 64k TSB pointer */
1511 /* env->immuregs[5] holds I-MMU TSB register value
1512 env->immuregs[6] holds I-MMU Tag Access register value */
1513 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
1517 case 0x55: /* I-MMU data access */
1519 int reg
= (addr
>> 3) & 0x3f;
1521 ret
= env
->itlb
[reg
].tte
;
1524 case 0x56: /* I-MMU tag read */
1526 int reg
= (addr
>> 3) & 0x3f;
1528 ret
= env
->itlb
[reg
].tag
;
1531 case 0x58: /* D-MMU regs */
1533 int reg
= (addr
>> 3) & 0xf;
1536 /* D-TSB Tag Target register */
1537 ret
= ultrasparc_tag_target(env
->dmmu
.tag_access
);
1539 ret
= env
->dmmuregs
[reg
];
1543 case 0x59: /* D-MMU 8k TSB pointer */
1545 /* env->dmmuregs[5] holds D-MMU TSB register value
1546 env->dmmuregs[6] holds D-MMU Tag Access register value */
1547 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
1551 case 0x5a: /* D-MMU 64k TSB pointer */
1553 /* env->dmmuregs[5] holds D-MMU TSB register value
1554 env->dmmuregs[6] holds D-MMU Tag Access register value */
1555 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
1559 case 0x5d: /* D-MMU data access */
1561 int reg
= (addr
>> 3) & 0x3f;
1563 ret
= env
->dtlb
[reg
].tte
;
1566 case 0x5e: /* D-MMU tag read */
1568 int reg
= (addr
>> 3) & 0x3f;
1570 ret
= env
->dtlb
[reg
].tag
;
1573 case 0x48: /* Interrupt dispatch, RO */
1575 case 0x49: /* Interrupt data receive */
1576 ret
= env
->ivec_status
;
1578 case 0x7f: /* Incoming interrupt vector, RO */
1580 int reg
= (addr
>> 4) & 0x3;
1582 ret
= env
->ivec_data
[reg
];
1586 case 0x46: /* D-cache data */
1587 case 0x47: /* D-cache tag access */
1588 case 0x4b: /* E-cache error enable */
1589 case 0x4c: /* E-cache asynchronous fault status */
1590 case 0x4d: /* E-cache asynchronous fault address */
1591 case 0x4e: /* E-cache tag data */
1592 case 0x66: /* I-cache instruction access */
1593 case 0x67: /* I-cache tag access */
1594 case 0x6e: /* I-cache predecode */
1595 case 0x6f: /* I-cache LRU etc. */
1596 case 0x76: /* E-cache tag */
1597 case 0x7e: /* E-cache tag */
1599 case 0x5b: /* D-MMU data pointer */
1600 case 0x54: /* I-MMU data in, WO */
1601 case 0x57: /* I-MMU demap, WO */
1602 case 0x5c: /* D-MMU data in, WO */
1603 case 0x5f: /* D-MMU demap, WO */
1604 case 0x77: /* Interrupt vector, WO */
1606 cpu_unassigned_access(CPU(sparc_env_get_cpu(env
)),
1607 addr
, false, false, 1, size
);
1612 /* Convert from little endian */
1614 case 0x0c: /* Nucleus Little Endian (LE) */
1615 case 0x18: /* As if user primary LE */
1616 case 0x19: /* As if user secondary LE */
1617 case 0x1c: /* Bypass LE */
1618 case 0x1d: /* Bypass, non-cacheable LE */
1619 case 0x88: /* Primary LE */
1620 case 0x89: /* Secondary LE */
1638 /* Convert to signed number */
1645 ret
= (int16_t) ret
;
1648 ret
= (int32_t) ret
;
1655 dump_asi("read ", last_addr
, asi
, size
, ret
);
1660 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, target_ulong val
,
1663 CPUState
*cs
= ENV_GET_CPU(env
);
1665 dump_asi("write", addr
, asi
, size
, val
);
1670 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
1671 || (cpu_has_hypervisor(env
)
1672 && asi
>= 0x30 && asi
< 0x80
1673 && !(env
->hpstate
& HS_PRIV
))) {
1674 helper_raise_exception(env
, TT_PRIV_ACT
);
1677 helper_check_align(env
, addr
, size
- 1);
1678 addr
= asi_address_mask(env
, asi
, addr
);
1680 /* Convert to little endian */
1682 case 0x0c: /* Nucleus Little Endian (LE) */
1683 case 0x18: /* As if user primary LE */
1684 case 0x19: /* As if user secondary LE */
1685 case 0x1c: /* Bypass LE */
1686 case 0x1d: /* Bypass, non-cacheable LE */
1687 case 0x88: /* Primary LE */
1688 case 0x89: /* Secondary LE */
1707 case 0x10: /* As if user primary */
1708 case 0x11: /* As if user secondary */
1709 case 0x18: /* As if user primary LE */
1710 case 0x19: /* As if user secondary LE */
1711 case 0x80: /* Primary */
1712 case 0x81: /* Secondary */
1713 case 0x88: /* Primary LE */
1714 case 0x89: /* Secondary LE */
1715 case 0xe2: /* UA2007 Primary block init */
1716 case 0xe3: /* UA2007 Secondary block init */
1717 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
1718 if (cpu_hypervisor_mode(env
)) {
1721 cpu_stb_hypv(env
, addr
, val
);
1724 cpu_stw_hypv(env
, addr
, val
);
1727 cpu_stl_hypv(env
, addr
, val
);
1731 cpu_stq_hypv(env
, addr
, val
);
1735 /* secondary space access has lowest asi bit equal to 1 */
1739 cpu_stb_kernel_secondary(env
, addr
, val
);
1742 cpu_stw_kernel_secondary(env
, addr
, val
);
1745 cpu_stl_kernel_secondary(env
, addr
, val
);
1749 cpu_stq_kernel_secondary(env
, addr
, val
);
1755 cpu_stb_kernel(env
, addr
, val
);
1758 cpu_stw_kernel(env
, addr
, val
);
1761 cpu_stl_kernel(env
, addr
, val
);
1765 cpu_stq_kernel(env
, addr
, val
);
1771 /* secondary space access has lowest asi bit equal to 1 */
1775 cpu_stb_user_secondary(env
, addr
, val
);
1778 cpu_stw_user_secondary(env
, addr
, val
);
1781 cpu_stl_user_secondary(env
, addr
, val
);
1785 cpu_stq_user_secondary(env
, addr
, val
);
1791 cpu_stb_user(env
, addr
, val
);
1794 cpu_stw_user(env
, addr
, val
);
1797 cpu_stl_user(env
, addr
, val
);
1801 cpu_stq_user(env
, addr
, val
);
1807 case 0x14: /* Bypass */
1808 case 0x15: /* Bypass, non-cacheable */
1809 case 0x1c: /* Bypass LE */
1810 case 0x1d: /* Bypass, non-cacheable LE */
1814 stb_phys(cs
->as
, addr
, val
);
1817 stw_phys(cs
->as
, addr
, val
);
1820 stl_phys(cs
->as
, addr
, val
);
1824 stq_phys(cs
->as
, addr
, val
);
1829 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1830 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1831 Only ldda allowed */
1832 helper_raise_exception(env
, TT_ILL_INSN
);
1834 case 0x04: /* Nucleus */
1835 case 0x0c: /* Nucleus Little Endian (LE) */
1839 cpu_stb_nucleus(env
, addr
, val
);
1842 cpu_stw_nucleus(env
, addr
, val
);
1845 cpu_stl_nucleus(env
, addr
, val
);
1849 cpu_stq_nucleus(env
, addr
, val
);
1855 case 0x4a: /* UPA config */
1858 case 0x45: /* LSU */
1863 env
->lsu
= val
& (DMMU_E
| IMMU_E
);
1864 /* Mappings generated during D/I MMU disabled mode are
1865 invalid in normal mode */
1866 if (oldreg
!= env
->lsu
) {
1867 DPRINTF_MMU("LSU change: 0x%" PRIx64
" -> 0x%" PRIx64
"\n",
1870 dump_mmu(stdout
, fprintf
, env
);
1876 case 0x50: /* I-MMU regs */
1878 int reg
= (addr
>> 3) & 0xf;
1881 oldreg
= env
->immuregs
[reg
];
1885 case 1: /* Not in I-MMU */
1889 if ((val
& 1) == 0) {
1890 val
= 0; /* Clear SFSR */
1892 env
->immu
.sfsr
= val
;
1896 case 5: /* TSB access */
1897 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64
" -> 0x%016"
1898 PRIx64
"\n", env
->immu
.tsb
, val
);
1899 env
->immu
.tsb
= val
;
1901 case 6: /* Tag access */
1902 env
->immu
.tag_access
= val
;
1911 if (oldreg
!= env
->immuregs
[reg
]) {
1912 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
1913 PRIx64
"\n", reg
, oldreg
, env
->immuregs
[reg
]);
1916 dump_mmu(stdout
, fprintf
, env
);
1920 case 0x54: /* I-MMU data in */
1921 replace_tlb_1bit_lru(env
->itlb
, env
->immu
.tag_access
, val
, "immu", env
);
1923 case 0x55: /* I-MMU data access */
1925 /* TODO: auto demap */
1927 unsigned int i
= (addr
>> 3) & 0x3f;
1929 replace_tlb_entry(&env
->itlb
[i
], env
->immu
.tag_access
, val
, env
);
1932 DPRINTF_MMU("immu data access replaced entry [%i]\n", i
);
1933 dump_mmu(stdout
, fprintf
, env
);
1937 case 0x57: /* I-MMU demap */
1938 demap_tlb(env
->itlb
, addr
, "immu", env
);
1940 case 0x58: /* D-MMU regs */
1942 int reg
= (addr
>> 3) & 0xf;
1945 oldreg
= env
->dmmuregs
[reg
];
1951 if ((val
& 1) == 0) {
1952 val
= 0; /* Clear SFSR, Fault address */
1955 env
->dmmu
.sfsr
= val
;
1957 case 1: /* Primary context */
1958 env
->dmmu
.mmu_primary_context
= val
;
1959 /* can be optimized to only flush MMU_USER_IDX
1960 and MMU_KERNEL_IDX entries */
1963 case 2: /* Secondary context */
1964 env
->dmmu
.mmu_secondary_context
= val
;
1965 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1966 and MMU_KERNEL_SECONDARY_IDX entries */
1969 case 5: /* TSB access */
1970 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64
" -> 0x%016"
1971 PRIx64
"\n", env
->dmmu
.tsb
, val
);
1972 env
->dmmu
.tsb
= val
;
1974 case 6: /* Tag access */
1975 env
->dmmu
.tag_access
= val
;
1977 case 7: /* Virtual Watchpoint */
1978 case 8: /* Physical Watchpoint */
1980 env
->dmmuregs
[reg
] = val
;
1984 if (oldreg
!= env
->dmmuregs
[reg
]) {
1985 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
1986 PRIx64
"\n", reg
, oldreg
, env
->dmmuregs
[reg
]);
1989 dump_mmu(stdout
, fprintf
, env
);
1993 case 0x5c: /* D-MMU data in */
1994 replace_tlb_1bit_lru(env
->dtlb
, env
->dmmu
.tag_access
, val
, "dmmu", env
);
1996 case 0x5d: /* D-MMU data access */
1998 unsigned int i
= (addr
>> 3) & 0x3f;
2000 replace_tlb_entry(&env
->dtlb
[i
], env
->dmmu
.tag_access
, val
, env
);
2003 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i
);
2004 dump_mmu(stdout
, fprintf
, env
);
2008 case 0x5f: /* D-MMU demap */
2009 demap_tlb(env
->dtlb
, addr
, "dmmu", env
);
2011 case 0x49: /* Interrupt data receive */
2012 env
->ivec_status
= val
& 0x20;
2014 case 0x46: /* D-cache data */
2015 case 0x47: /* D-cache tag access */
2016 case 0x4b: /* E-cache error enable */
2017 case 0x4c: /* E-cache asynchronous fault status */
2018 case 0x4d: /* E-cache asynchronous fault address */
2019 case 0x4e: /* E-cache tag data */
2020 case 0x66: /* I-cache instruction access */
2021 case 0x67: /* I-cache tag access */
2022 case 0x6e: /* I-cache predecode */
2023 case 0x6f: /* I-cache LRU etc. */
2024 case 0x76: /* E-cache tag */
2025 case 0x7e: /* E-cache tag */
2027 case 0x51: /* I-MMU 8k TSB pointer, RO */
2028 case 0x52: /* I-MMU 64k TSB pointer, RO */
2029 case 0x56: /* I-MMU tag read, RO */
2030 case 0x59: /* D-MMU 8k TSB pointer, RO */
2031 case 0x5a: /* D-MMU 64k TSB pointer, RO */
2032 case 0x5b: /* D-MMU data pointer, RO */
2033 case 0x5e: /* D-MMU tag read, RO */
2034 case 0x48: /* Interrupt dispatch, RO */
2035 case 0x7f: /* Incoming interrupt vector, RO */
2036 case 0x82: /* Primary no-fault, RO */
2037 case 0x83: /* Secondary no-fault, RO */
2038 case 0x8a: /* Primary no-fault LE, RO */
2039 case 0x8b: /* Secondary no-fault LE, RO */
2041 cpu_unassigned_access(CPU(sparc_env_get_cpu(env
)),
2042 addr
, true, false, 1, size
);
2046 #endif /* CONFIG_USER_ONLY */
2048 void helper_ldda_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int rd
)
2050 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2051 || (cpu_has_hypervisor(env
)
2052 && asi
>= 0x30 && asi
< 0x80
2053 && !(env
->hpstate
& HS_PRIV
))) {
2054 helper_raise_exception(env
, TT_PRIV_ACT
);
2057 addr
= asi_address_mask(env
, asi
, addr
);
2060 #if !defined(CONFIG_USER_ONLY)
2061 case 0x24: /* Nucleus quad LDD 128 bit atomic */
2062 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE */
2063 helper_check_align(env
, addr
, 0xf);
2065 env
->gregs
[1] = cpu_ldq_nucleus(env
, addr
+ 8);
2067 bswap64s(&env
->gregs
[1]);
2069 } else if (rd
< 8) {
2070 env
->gregs
[rd
] = cpu_ldq_nucleus(env
, addr
);
2071 env
->gregs
[rd
+ 1] = cpu_ldq_nucleus(env
, addr
+ 8);
2073 bswap64s(&env
->gregs
[rd
]);
2074 bswap64s(&env
->gregs
[rd
+ 1]);
2077 env
->regwptr
[rd
] = cpu_ldq_nucleus(env
, addr
);
2078 env
->regwptr
[rd
+ 1] = cpu_ldq_nucleus(env
, addr
+ 8);
2080 bswap64s(&env
->regwptr
[rd
]);
2081 bswap64s(&env
->regwptr
[rd
+ 1]);
2087 helper_check_align(env
, addr
, 0x3);
2089 env
->gregs
[1] = helper_ld_asi(env
, addr
+ 4, asi
, 4, 0);
2090 } else if (rd
< 8) {
2091 env
->gregs
[rd
] = helper_ld_asi(env
, addr
, asi
, 4, 0);
2092 env
->gregs
[rd
+ 1] = helper_ld_asi(env
, addr
+ 4, asi
, 4, 0);
2094 env
->regwptr
[rd
] = helper_ld_asi(env
, addr
, asi
, 4, 0);
2095 env
->regwptr
[rd
+ 1] = helper_ld_asi(env
, addr
+ 4, asi
, 4, 0);
2101 void helper_ldf_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int size
,
2107 helper_check_align(env
, addr
, 3);
2108 addr
= asi_address_mask(env
, asi
, addr
);
2111 case 0xf0: /* UA2007/JPS1 Block load primary */
2112 case 0xf1: /* UA2007/JPS1 Block load secondary */
2113 case 0xf8: /* UA2007/JPS1 Block load primary LE */
2114 case 0xf9: /* UA2007/JPS1 Block load secondary LE */
2116 helper_raise_exception(env
, TT_ILL_INSN
);
2119 helper_check_align(env
, addr
, 0x3f);
2120 for (i
= 0; i
< 8; i
++, rd
+= 2, addr
+= 8) {
2121 env
->fpr
[rd
/ 2].ll
= helper_ld_asi(env
, addr
, asi
& 0x8f, 8, 0);
2125 case 0x16: /* UA2007 Block load primary, user privilege */
2126 case 0x17: /* UA2007 Block load secondary, user privilege */
2127 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2128 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2129 case 0x70: /* JPS1 Block load primary, user privilege */
2130 case 0x71: /* JPS1 Block load secondary, user privilege */
2131 case 0x78: /* JPS1 Block load primary LE, user privilege */
2132 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2134 helper_raise_exception(env
, TT_ILL_INSN
);
2137 helper_check_align(env
, addr
, 0x3f);
2138 for (i
= 0; i
< 8; i
++, rd
+= 2, addr
+= 8) {
2139 env
->fpr
[rd
/ 2].ll
= helper_ld_asi(env
, addr
, asi
& 0x19, 8, 0);
2150 val
= helper_ld_asi(env
, addr
, asi
, size
, 0);
2152 env
->fpr
[rd
/ 2].l
.lower
= val
;
2154 env
->fpr
[rd
/ 2].l
.upper
= val
;
2158 env
->fpr
[rd
/ 2].ll
= helper_ld_asi(env
, addr
, asi
, size
, 0);
2161 env
->fpr
[rd
/ 2].ll
= helper_ld_asi(env
, addr
, asi
, 8, 0);
2162 env
->fpr
[rd
/ 2 + 1].ll
= helper_ld_asi(env
, addr
+ 8, asi
, 8, 0);
2167 void helper_stf_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int size
,
2173 helper_check_align(env
, addr
, 3);
2174 addr
= asi_address_mask(env
, asi
, addr
);
2177 case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */
2178 case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */
2179 case 0xf0: /* UA2007/JPS1 Block store primary */
2180 case 0xf1: /* UA2007/JPS1 Block store secondary */
2181 case 0xf8: /* UA2007/JPS1 Block store primary LE */
2182 case 0xf9: /* UA2007/JPS1 Block store secondary LE */
2184 helper_raise_exception(env
, TT_ILL_INSN
);
2187 helper_check_align(env
, addr
, 0x3f);
2188 for (i
= 0; i
< 8; i
++, rd
+= 2, addr
+= 8) {
2189 helper_st_asi(env
, addr
, env
->fpr
[rd
/ 2].ll
, asi
& 0x8f, 8);
2193 case 0x16: /* UA2007 Block load primary, user privilege */
2194 case 0x17: /* UA2007 Block load secondary, user privilege */
2195 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2196 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2197 case 0x70: /* JPS1 Block store primary, user privilege */
2198 case 0x71: /* JPS1 Block store secondary, user privilege */
2199 case 0x78: /* JPS1 Block load primary LE, user privilege */
2200 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2202 helper_raise_exception(env
, TT_ILL_INSN
);
2205 helper_check_align(env
, addr
, 0x3f);
2206 for (i
= 0; i
< 8; i
++, rd
+= 2, addr
+= 8) {
2207 helper_st_asi(env
, addr
, env
->fpr
[rd
/ 2].ll
, asi
& 0x19, 8);
2219 val
= env
->fpr
[rd
/ 2].l
.lower
;
2221 val
= env
->fpr
[rd
/ 2].l
.upper
;
2223 helper_st_asi(env
, addr
, val
, asi
, size
);
2226 helper_st_asi(env
, addr
, env
->fpr
[rd
/ 2].ll
, asi
, size
);
2229 helper_st_asi(env
, addr
, env
->fpr
[rd
/ 2].ll
, asi
, 8);
2230 helper_st_asi(env
, addr
+ 8, env
->fpr
[rd
/ 2 + 1].ll
, asi
, 8);
2235 target_ulong
helper_cas_asi(CPUSPARCState
*env
, target_ulong addr
,
2236 target_ulong val1
, target_ulong val2
, uint32_t asi
)
2240 val2
&= 0xffffffffUL
;
2241 ret
= helper_ld_asi(env
, addr
, asi
, 4, 0);
2242 ret
&= 0xffffffffUL
;
2244 helper_st_asi(env
, addr
, val1
& 0xffffffffUL
, asi
, 4);
2249 target_ulong
helper_casx_asi(CPUSPARCState
*env
, target_ulong addr
,
2250 target_ulong val1
, target_ulong val2
,
2255 ret
= helper_ld_asi(env
, addr
, asi
, 8, 0);
2257 helper_st_asi(env
, addr
, val1
, asi
, 8);
2261 #endif /* TARGET_SPARC64 */
2263 void helper_ldqf(CPUSPARCState
*env
, target_ulong addr
, int mem_idx
)
2265 /* XXX add 128 bit load */
2268 helper_check_align(env
, addr
, 7);
2269 #if !defined(CONFIG_USER_ONLY)
2272 u
.ll
.upper
= cpu_ldq_user(env
, addr
);
2273 u
.ll
.lower
= cpu_ldq_user(env
, addr
+ 8);
2276 case MMU_KERNEL_IDX
:
2277 u
.ll
.upper
= cpu_ldq_kernel(env
, addr
);
2278 u
.ll
.lower
= cpu_ldq_kernel(env
, addr
+ 8);
2281 #ifdef TARGET_SPARC64
2283 u
.ll
.upper
= cpu_ldq_hypv(env
, addr
);
2284 u
.ll
.lower
= cpu_ldq_hypv(env
, addr
+ 8);
2289 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx
);
2293 u
.ll
.upper
= ldq_raw(address_mask(env
, addr
));
2294 u
.ll
.lower
= ldq_raw(address_mask(env
, addr
+ 8));
2299 void helper_stqf(CPUSPARCState
*env
, target_ulong addr
, int mem_idx
)
2301 /* XXX add 128 bit store */
2304 helper_check_align(env
, addr
, 7);
2305 #if !defined(CONFIG_USER_ONLY)
2309 cpu_stq_user(env
, addr
, u
.ll
.upper
);
2310 cpu_stq_user(env
, addr
+ 8, u
.ll
.lower
);
2312 case MMU_KERNEL_IDX
:
2314 cpu_stq_kernel(env
, addr
, u
.ll
.upper
);
2315 cpu_stq_kernel(env
, addr
+ 8, u
.ll
.lower
);
2317 #ifdef TARGET_SPARC64
2320 cpu_stq_hypv(env
, addr
, u
.ll
.upper
);
2321 cpu_stq_hypv(env
, addr
+ 8, u
.ll
.lower
);
2325 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx
);
2330 stq_raw(address_mask(env
, addr
), u
.ll
.upper
);
2331 stq_raw(address_mask(env
, addr
+ 8), u
.ll
.lower
);
2335 #if !defined(CONFIG_USER_ONLY)
2336 #ifndef TARGET_SPARC64
2337 void sparc_cpu_unassigned_access(CPUState
*cs
, hwaddr addr
,
2338 bool is_write
, bool is_exec
, int is_asi
,
2341 SPARCCPU
*cpu
= SPARC_CPU(cs
);
2342 CPUSPARCState
*env
= &cpu
->env
;
2345 #ifdef DEBUG_UNASSIGNED
2347 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2348 " asi 0x%02x from " TARGET_FMT_lx
"\n",
2349 is_exec
? "exec" : is_write
? "write" : "read", size
,
2350 size
== 1 ? "" : "s", addr
, is_asi
, env
->pc
);
2352 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2353 " from " TARGET_FMT_lx
"\n",
2354 is_exec
? "exec" : is_write
? "write" : "read", size
,
2355 size
== 1 ? "" : "s", addr
, env
->pc
);
2358 /* Don't overwrite translation and access faults */
2359 fault_type
= (env
->mmuregs
[3] & 0x1c) >> 2;
2360 if ((fault_type
> 4) || (fault_type
== 0)) {
2361 env
->mmuregs
[3] = 0; /* Fault status register */
2363 env
->mmuregs
[3] |= 1 << 16;
2366 env
->mmuregs
[3] |= 1 << 5;
2369 env
->mmuregs
[3] |= 1 << 6;
2372 env
->mmuregs
[3] |= 1 << 7;
2374 env
->mmuregs
[3] |= (5 << 2) | 2;
2375 /* SuperSPARC will never place instruction fault addresses in the FAR */
2377 env
->mmuregs
[4] = addr
; /* Fault address register */
2380 /* overflow (same type fault was not read before another fault) */
2381 if (fault_type
== ((env
->mmuregs
[3] & 0x1c)) >> 2) {
2382 env
->mmuregs
[3] |= 1;
2385 if ((env
->mmuregs
[0] & MMU_E
) && !(env
->mmuregs
[0] & MMU_NF
)) {
2387 helper_raise_exception(env
, TT_CODE_ACCESS
);
2389 helper_raise_exception(env
, TT_DATA_ACCESS
);
2393 /* flush neverland mappings created during no-fault mode,
2394 so the sequential MMU faults report proper fault types */
2395 if (env
->mmuregs
[0] & MMU_NF
) {
2400 void sparc_cpu_unassigned_access(CPUState
*cs
, hwaddr addr
,
2401 bool is_write
, bool is_exec
, int is_asi
,
2404 SPARCCPU
*cpu
= SPARC_CPU(cs
);
2405 CPUSPARCState
*env
= &cpu
->env
;
2407 #ifdef DEBUG_UNASSIGNED
2408 printf("Unassigned mem access to " TARGET_FMT_plx
" from " TARGET_FMT_lx
2409 "\n", addr
, env
->pc
);
2413 helper_raise_exception(env
, TT_CODE_ACCESS
);
2415 helper_raise_exception(env
, TT_DATA_ACCESS
);
2421 #if !defined(CONFIG_USER_ONLY)
2422 static void QEMU_NORETURN
do_unaligned_access(CPUSPARCState
*env
,
2423 target_ulong addr
, int is_write
,
2424 int is_user
, uintptr_t retaddr
)
2426 #ifdef DEBUG_UNALIGNED
2427 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
2428 "\n", addr
, env
->pc
);
2431 cpu_restore_state(env
, retaddr
);
2433 helper_raise_exception(env
, TT_UNALIGNED
);
2436 /* try to fill the TLB and return an exception if error. If retaddr is
2437 NULL, it means that the function was called in C code (i.e. not
2438 from generated code or from helper.c) */
2439 /* XXX: fix it to restore all registers */
2440 void tlb_fill(CPUSPARCState
*env
, target_ulong addr
, int is_write
, int mmu_idx
,
2445 ret
= cpu_sparc_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
);
2448 cpu_restore_state(env
, retaddr
);