]>
git.proxmox.com Git - mirror_qemu.git/blob - target-sparc/op_helper.c
2 #include "host-utils.h"
4 #if !defined(CONFIG_USER_ONLY)
5 #include "softmmu_exec.h"
6 #endif /* !defined(CONFIG_USER_ONLY) */
10 //#define DEBUG_UNALIGNED
11 //#define DEBUG_UNASSIGNED
15 #define DPRINTF_MMU(fmt, args...) \
16 do { printf("MMU: " fmt , ##args); } while (0)
18 #define DPRINTF_MMU(fmt, args...) do {} while (0)
22 #define DPRINTF_MXCC(fmt, args...) \
23 do { printf("MXCC: " fmt , ##args); } while (0)
25 #define DPRINTF_MXCC(fmt, args...) do {} while (0)
29 #define DPRINTF_ASI(fmt, args...) \
30 do { printf("ASI: " fmt , ##args); } while (0)
32 #define DPRINTF_ASI(fmt, args...) do {} while (0)
37 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
39 #define AM_CHECK(env1) (1)
43 static inline void address_mask(CPUState
*env1
, target_ulong
*addr
)
47 *addr
&= 0xffffffffULL
;
51 void raise_exception(int tt
)
53 env
->exception_index
= tt
;
57 void helper_trap(target_ulong nb_trap
)
59 env
->exception_index
= TT_TRAP
+ (nb_trap
& 0x7f);
63 void helper_trapcc(target_ulong nb_trap
, target_ulong do_trap
)
66 env
->exception_index
= TT_TRAP
+ (nb_trap
& 0x7f);
71 void helper_check_align(target_ulong addr
, uint32_t align
)
74 #ifdef DEBUG_UNALIGNED
75 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
78 raise_exception(TT_UNALIGNED
);
82 #define F_HELPER(name, p) void helper_f##name##p(void)
84 #define F_BINOP(name) \
87 FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \
91 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
95 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
104 void helper_fsmuld(void)
106 DT0
= float64_mul(float32_to_float64(FT0
, &env
->fp_status
),
107 float32_to_float64(FT1
, &env
->fp_status
),
111 void helper_fdmulq(void)
113 QT0
= float128_mul(float64_to_float128(DT0
, &env
->fp_status
),
114 float64_to_float128(DT1
, &env
->fp_status
),
120 FT0
= float32_chs(FT1
);
123 #ifdef TARGET_SPARC64
126 DT0
= float64_chs(DT1
);
131 QT0
= float128_chs(QT1
);
135 /* Integer to float conversion. */
138 FT0
= int32_to_float32(*((int32_t *)&FT1
), &env
->fp_status
);
143 DT0
= int32_to_float64(*((int32_t *)&FT1
), &env
->fp_status
);
148 QT0
= int32_to_float128(*((int32_t *)&FT1
), &env
->fp_status
);
151 #ifdef TARGET_SPARC64
154 FT0
= int64_to_float32(*((int64_t *)&DT1
), &env
->fp_status
);
159 DT0
= int64_to_float64(*((int64_t *)&DT1
), &env
->fp_status
);
164 QT0
= int64_to_float128(*((int64_t *)&DT1
), &env
->fp_status
);
169 /* floating point conversion */
170 void helper_fdtos(void)
172 FT0
= float64_to_float32(DT1
, &env
->fp_status
);
175 void helper_fstod(void)
177 DT0
= float32_to_float64(FT1
, &env
->fp_status
);
180 void helper_fqtos(void)
182 FT0
= float128_to_float32(QT1
, &env
->fp_status
);
185 void helper_fstoq(void)
187 QT0
= float32_to_float128(FT1
, &env
->fp_status
);
190 void helper_fqtod(void)
192 DT0
= float128_to_float64(QT1
, &env
->fp_status
);
195 void helper_fdtoq(void)
197 QT0
= float64_to_float128(DT1
, &env
->fp_status
);
200 /* Float to integer conversion. */
201 void helper_fstoi(void)
203 *((int32_t *)&FT0
) = float32_to_int32_round_to_zero(FT1
, &env
->fp_status
);
206 void helper_fdtoi(void)
208 *((int32_t *)&FT0
) = float64_to_int32_round_to_zero(DT1
, &env
->fp_status
);
211 void helper_fqtoi(void)
213 *((int32_t *)&FT0
) = float128_to_int32_round_to_zero(QT1
, &env
->fp_status
);
216 #ifdef TARGET_SPARC64
217 void helper_fstox(void)
219 *((int64_t *)&DT0
) = float32_to_int64_round_to_zero(FT1
, &env
->fp_status
);
222 void helper_fdtox(void)
224 *((int64_t *)&DT0
) = float64_to_int64_round_to_zero(DT1
, &env
->fp_status
);
227 void helper_fqtox(void)
229 *((int64_t *)&DT0
) = float128_to_int64_round_to_zero(QT1
, &env
->fp_status
);
232 void helper_faligndata(void)
236 tmp
= (*((uint64_t *)&DT0
)) << ((env
->gsr
& 7) * 8);
237 tmp
|= (*((uint64_t *)&DT1
)) >> (64 - (env
->gsr
& 7) * 8);
238 *((uint64_t *)&DT0
) = tmp
;
241 void helper_movl_FT0_0(void)
243 *((uint32_t *)&FT0
) = 0;
246 void helper_movl_DT0_0(void)
248 *((uint64_t *)&DT0
) = 0;
251 void helper_movl_FT0_1(void)
253 *((uint32_t *)&FT0
) = 0xffffffff;
256 void helper_movl_DT0_1(void)
258 *((uint64_t *)&DT0
) = 0xffffffffffffffffULL
;
261 void helper_fnot(void)
263 *(uint64_t *)&DT0
= ~*(uint64_t *)&DT1
;
266 void helper_fnots(void)
268 *(uint32_t *)&FT0
= ~*(uint32_t *)&FT1
;
271 void helper_fnor(void)
273 *(uint64_t *)&DT0
= ~(*(uint64_t *)&DT0
| *(uint64_t *)&DT1
);
276 void helper_fnors(void)
278 *(uint32_t *)&FT0
= ~(*(uint32_t *)&FT0
| *(uint32_t *)&FT1
);
281 void helper_for(void)
283 *(uint64_t *)&DT0
|= *(uint64_t *)&DT1
;
286 void helper_fors(void)
288 *(uint32_t *)&FT0
|= *(uint32_t *)&FT1
;
291 void helper_fxor(void)
293 *(uint64_t *)&DT0
^= *(uint64_t *)&DT1
;
296 void helper_fxors(void)
298 *(uint32_t *)&FT0
^= *(uint32_t *)&FT1
;
301 void helper_fand(void)
303 *(uint64_t *)&DT0
&= *(uint64_t *)&DT1
;
306 void helper_fands(void)
308 *(uint32_t *)&FT0
&= *(uint32_t *)&FT1
;
311 void helper_fornot(void)
313 *(uint64_t *)&DT0
= *(uint64_t *)&DT0
| ~*(uint64_t *)&DT1
;
316 void helper_fornots(void)
318 *(uint32_t *)&FT0
= *(uint32_t *)&FT0
| ~*(uint32_t *)&FT1
;
321 void helper_fandnot(void)
323 *(uint64_t *)&DT0
= *(uint64_t *)&DT0
& ~*(uint64_t *)&DT1
;
326 void helper_fandnots(void)
328 *(uint32_t *)&FT0
= *(uint32_t *)&FT0
& ~*(uint32_t *)&FT1
;
331 void helper_fnand(void)
333 *(uint64_t *)&DT0
= ~(*(uint64_t *)&DT0
& *(uint64_t *)&DT1
);
336 void helper_fnands(void)
338 *(uint32_t *)&FT0
= ~(*(uint32_t *)&FT0
& *(uint32_t *)&FT1
);
341 void helper_fxnor(void)
343 *(uint64_t *)&DT0
^= ~*(uint64_t *)&DT1
;
346 void helper_fxnors(void)
348 *(uint32_t *)&FT0
^= ~*(uint32_t *)&FT1
;
351 #ifdef WORDS_BIGENDIAN
352 #define VIS_B64(n) b[7 - (n)]
353 #define VIS_W64(n) w[3 - (n)]
354 #define VIS_SW64(n) sw[3 - (n)]
355 #define VIS_L64(n) l[1 - (n)]
356 #define VIS_B32(n) b[3 - (n)]
357 #define VIS_W32(n) w[1 - (n)]
359 #define VIS_B64(n) b[n]
360 #define VIS_W64(n) w[n]
361 #define VIS_SW64(n) sw[n]
362 #define VIS_L64(n) l[n]
363 #define VIS_B32(n) b[n]
364 #define VIS_W32(n) w[n]
382 void helper_fpmerge(void)
389 // Reverse calculation order to handle overlap
390 d
.VIS_B64(7) = s
.VIS_B64(3);
391 d
.VIS_B64(6) = d
.VIS_B64(3);
392 d
.VIS_B64(5) = s
.VIS_B64(2);
393 d
.VIS_B64(4) = d
.VIS_B64(2);
394 d
.VIS_B64(3) = s
.VIS_B64(1);
395 d
.VIS_B64(2) = d
.VIS_B64(1);
396 d
.VIS_B64(1) = s
.VIS_B64(0);
397 //d.VIS_B64(0) = d.VIS_B64(0);
402 void helper_fmul8x16(void)
411 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
412 if ((tmp & 0xff) > 0x7f) \
414 d.VIS_W64(r) = tmp >> 8;
425 void helper_fmul8x16al(void)
434 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
435 if ((tmp & 0xff) > 0x7f) \
437 d.VIS_W64(r) = tmp >> 8;
448 void helper_fmul8x16au(void)
457 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
458 if ((tmp & 0xff) > 0x7f) \
460 d.VIS_W64(r) = tmp >> 8;
471 void helper_fmul8sux16(void)
480 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
481 if ((tmp & 0xff) > 0x7f) \
483 d.VIS_W64(r) = tmp >> 8;
494 void helper_fmul8ulx16(void)
503 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
504 if ((tmp & 0xff) > 0x7f) \
506 d.VIS_W64(r) = tmp >> 8;
517 void helper_fmuld8sux16(void)
526 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
527 if ((tmp & 0xff) > 0x7f) \
531 // Reverse calculation order to handle overlap
539 void helper_fmuld8ulx16(void)
548 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
549 if ((tmp & 0xff) > 0x7f) \
553 // Reverse calculation order to handle overlap
561 void helper_fexpand(void)
566 s
.l
= (uint32_t)(*(uint64_t *)&DT0
& 0xffffffff);
568 d
.VIS_L64(0) = s
.VIS_W32(0) << 4;
569 d
.VIS_L64(1) = s
.VIS_W32(1) << 4;
570 d
.VIS_L64(2) = s
.VIS_W32(2) << 4;
571 d
.VIS_L64(3) = s
.VIS_W32(3) << 4;
576 #define VIS_HELPER(name, F) \
577 void name##16(void) \
584 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
585 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
586 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
587 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
592 void name##16s(void) \
599 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
600 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
605 void name##32(void) \
612 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
613 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
618 void name##32s(void) \
630 #define FADD(a, b) ((a) + (b))
631 #define FSUB(a, b) ((a) - (b))
632 VIS_HELPER(helper_fpadd
, FADD
)
633 VIS_HELPER(helper_fpsub
, FSUB
)
635 #define VIS_CMPHELPER(name, F) \
636 void name##16(void) \
643 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
644 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
645 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
646 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
651 void name##32(void) \
658 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
659 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
664 #define FCMPGT(a, b) ((a) > (b))
665 #define FCMPEQ(a, b) ((a) == (b))
666 #define FCMPLE(a, b) ((a) <= (b))
667 #define FCMPNE(a, b) ((a) != (b))
669 VIS_CMPHELPER(helper_fcmpgt
, FCMPGT
)
670 VIS_CMPHELPER(helper_fcmpeq
, FCMPEQ
)
671 VIS_CMPHELPER(helper_fcmple
, FCMPLE
)
672 VIS_CMPHELPER(helper_fcmpne
, FCMPNE
)
675 void helper_check_ieee_exceptions(void)
679 status
= get_float_exception_flags(&env
->fp_status
);
681 /* Copy IEEE 754 flags into FSR */
682 if (status
& float_flag_invalid
)
684 if (status
& float_flag_overflow
)
686 if (status
& float_flag_underflow
)
688 if (status
& float_flag_divbyzero
)
690 if (status
& float_flag_inexact
)
693 if ((env
->fsr
& FSR_CEXC_MASK
) & ((env
->fsr
& FSR_TEM_MASK
) >> 23)) {
694 /* Unmasked exception, generate a trap */
695 env
->fsr
|= FSR_FTT_IEEE_EXCP
;
696 raise_exception(TT_FP_EXCP
);
698 /* Accumulate exceptions */
699 env
->fsr
|= (env
->fsr
& FSR_CEXC_MASK
) << 5;
704 void helper_clear_float_exceptions(void)
706 set_float_exception_flags(0, &env
->fp_status
);
709 void helper_fabss(void)
711 FT0
= float32_abs(FT1
);
714 #ifdef TARGET_SPARC64
715 void helper_fabsd(void)
717 DT0
= float64_abs(DT1
);
720 void helper_fabsq(void)
722 QT0
= float128_abs(QT1
);
726 void helper_fsqrts(void)
728 FT0
= float32_sqrt(FT1
, &env
->fp_status
);
731 void helper_fsqrtd(void)
733 DT0
= float64_sqrt(DT1
, &env
->fp_status
);
736 void helper_fsqrtq(void)
738 QT0
= float128_sqrt(QT1
, &env
->fp_status
);
741 #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
742 void glue(helper_, name) (void) \
744 target_ulong new_fsr; \
746 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
747 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
748 case float_relation_unordered: \
749 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
750 if ((env->fsr & FSR_NVM) || TRAP) { \
751 env->fsr |= new_fsr; \
752 env->fsr |= FSR_NVC; \
753 env->fsr |= FSR_FTT_IEEE_EXCP; \
754 raise_exception(TT_FP_EXCP); \
756 env->fsr |= FSR_NVA; \
759 case float_relation_less: \
760 new_fsr = FSR_FCC0 << FS; \
762 case float_relation_greater: \
763 new_fsr = FSR_FCC1 << FS; \
769 env->fsr |= new_fsr; \
772 GEN_FCMP(fcmps
, float32
, FT0
, FT1
, 0, 0);
773 GEN_FCMP(fcmpd
, float64
, DT0
, DT1
, 0, 0);
775 GEN_FCMP(fcmpes
, float32
, FT0
, FT1
, 0, 1);
776 GEN_FCMP(fcmped
, float64
, DT0
, DT1
, 0, 1);
778 GEN_FCMP(fcmpq
, float128
, QT0
, QT1
, 0, 0);
779 GEN_FCMP(fcmpeq
, float128
, QT0
, QT1
, 0, 1);
781 #ifdef TARGET_SPARC64
782 GEN_FCMP(fcmps_fcc1
, float32
, FT0
, FT1
, 22, 0);
783 GEN_FCMP(fcmpd_fcc1
, float64
, DT0
, DT1
, 22, 0);
784 GEN_FCMP(fcmpq_fcc1
, float128
, QT0
, QT1
, 22, 0);
786 GEN_FCMP(fcmps_fcc2
, float32
, FT0
, FT1
, 24, 0);
787 GEN_FCMP(fcmpd_fcc2
, float64
, DT0
, DT1
, 24, 0);
788 GEN_FCMP(fcmpq_fcc2
, float128
, QT0
, QT1
, 24, 0);
790 GEN_FCMP(fcmps_fcc3
, float32
, FT0
, FT1
, 26, 0);
791 GEN_FCMP(fcmpd_fcc3
, float64
, DT0
, DT1
, 26, 0);
792 GEN_FCMP(fcmpq_fcc3
, float128
, QT0
, QT1
, 26, 0);
794 GEN_FCMP(fcmpes_fcc1
, float32
, FT0
, FT1
, 22, 1);
795 GEN_FCMP(fcmped_fcc1
, float64
, DT0
, DT1
, 22, 1);
796 GEN_FCMP(fcmpeq_fcc1
, float128
, QT0
, QT1
, 22, 1);
798 GEN_FCMP(fcmpes_fcc2
, float32
, FT0
, FT1
, 24, 1);
799 GEN_FCMP(fcmped_fcc2
, float64
, DT0
, DT1
, 24, 1);
800 GEN_FCMP(fcmpeq_fcc2
, float128
, QT0
, QT1
, 24, 1);
802 GEN_FCMP(fcmpes_fcc3
, float32
, FT0
, FT1
, 26, 1);
803 GEN_FCMP(fcmped_fcc3
, float64
, DT0
, DT1
, 26, 1);
804 GEN_FCMP(fcmpeq_fcc3
, float128
, QT0
, QT1
, 26, 1);
807 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
809 static void dump_mxcc(CPUState
*env
)
811 printf("mxccdata: %016llx %016llx %016llx %016llx\n",
812 env
->mxccdata
[0], env
->mxccdata
[1],
813 env
->mxccdata
[2], env
->mxccdata
[3]);
814 printf("mxccregs: %016llx %016llx %016llx %016llx\n"
815 " %016llx %016llx %016llx %016llx\n",
816 env
->mxccregs
[0], env
->mxccregs
[1],
817 env
->mxccregs
[2], env
->mxccregs
[3],
818 env
->mxccregs
[4], env
->mxccregs
[5],
819 env
->mxccregs
[6], env
->mxccregs
[7]);
823 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
824 && defined(DEBUG_ASI)
825 static void dump_asi(const char *txt
, target_ulong addr
, int asi
, int size
,
831 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %02" PRIx64
"\n", txt
,
832 addr
, asi
, r1
& 0xff);
835 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %04" PRIx64
"\n", txt
,
836 addr
, asi
, r1
& 0xffff);
839 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %08" PRIx64
"\n", txt
,
840 addr
, asi
, r1
& 0xffffffff);
843 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %016" PRIx64
"\n", txt
,
850 #ifndef TARGET_SPARC64
851 #ifndef CONFIG_USER_ONLY
852 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
855 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
856 uint32_t last_addr
= addr
;
859 helper_check_align(addr
, size
- 1);
861 case 2: /* SuperSparc MXCC registers */
863 case 0x01c00a00: /* MXCC control register */
865 ret
= env
->mxccregs
[3];
867 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
870 case 0x01c00a04: /* MXCC control register */
872 ret
= env
->mxccregs
[3];
874 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
877 case 0x01c00c00: /* Module reset register */
879 ret
= env
->mxccregs
[5];
880 // should we do something here?
882 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
885 case 0x01c00f00: /* MBus port address register */
887 ret
= env
->mxccregs
[7];
889 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
893 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
897 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
898 "addr = %08x -> ret = %08x,"
899 "addr = %08x\n", asi
, size
, sign
, last_addr
, ret
, addr
);
904 case 3: /* MMU probe */
908 mmulev
= (addr
>> 8) & 15;
912 ret
= mmu_probe(env
, addr
, mmulev
);
913 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64
"\n",
917 case 4: /* read MMU regs */
919 int reg
= (addr
>> 8) & 0x1f;
921 ret
= env
->mmuregs
[reg
];
922 if (reg
== 3) /* Fault status cleared on read */
924 else if (reg
== 0x13) /* Fault status read */
925 ret
= env
->mmuregs
[3];
926 else if (reg
== 0x14) /* Fault address read */
927 ret
= env
->mmuregs
[4];
928 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64
"\n", reg
, ret
);
931 case 5: // Turbosparc ITLB Diagnostic
932 case 6: // Turbosparc DTLB Diagnostic
933 case 7: // Turbosparc IOTLB Diagnostic
935 case 9: /* Supervisor code access */
938 ret
= ldub_code(addr
);
941 ret
= lduw_code(addr
);
945 ret
= ldl_code(addr
);
948 ret
= ldq_code(addr
);
952 case 0xa: /* User data access */
955 ret
= ldub_user(addr
);
958 ret
= lduw_user(addr
);
962 ret
= ldl_user(addr
);
965 ret
= ldq_user(addr
);
969 case 0xb: /* Supervisor data access */
972 ret
= ldub_kernel(addr
);
975 ret
= lduw_kernel(addr
);
979 ret
= ldl_kernel(addr
);
982 ret
= ldq_kernel(addr
);
986 case 0xc: /* I-cache tag */
987 case 0xd: /* I-cache data */
988 case 0xe: /* D-cache tag */
989 case 0xf: /* D-cache data */
991 case 0x20: /* MMU passthrough */
994 ret
= ldub_phys(addr
);
997 ret
= lduw_phys(addr
);
1001 ret
= ldl_phys(addr
);
1004 ret
= ldq_phys(addr
);
1008 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1011 ret
= ldub_phys((target_phys_addr_t
)addr
1012 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1015 ret
= lduw_phys((target_phys_addr_t
)addr
1016 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1020 ret
= ldl_phys((target_phys_addr_t
)addr
1021 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1024 ret
= ldq_phys((target_phys_addr_t
)addr
1025 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1029 case 0x30: // Turbosparc secondary cache diagnostic
1030 case 0x31: // Turbosparc RAM snoop
1031 case 0x32: // Turbosparc page table descriptor diagnostic
1032 case 0x39: /* data cache diagnostic register */
1035 case 8: /* User code access, XXX */
1037 do_unassigned_access(addr
, 0, 0, asi
);
1047 ret
= (int16_t) ret
;
1050 ret
= (int32_t) ret
;
1057 dump_asi("read ", last_addr
, asi
, size
, ret
);
1062 void helper_st_asi(target_ulong addr
, uint64_t val
, int asi
, int size
)
1064 helper_check_align(addr
, size
- 1);
1066 case 2: /* SuperSparc MXCC registers */
1068 case 0x01c00000: /* MXCC stream data register 0 */
1070 env
->mxccdata
[0] = val
;
1072 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1075 case 0x01c00008: /* MXCC stream data register 1 */
1077 env
->mxccdata
[1] = val
;
1079 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1082 case 0x01c00010: /* MXCC stream data register 2 */
1084 env
->mxccdata
[2] = val
;
1086 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1089 case 0x01c00018: /* MXCC stream data register 3 */
1091 env
->mxccdata
[3] = val
;
1093 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1096 case 0x01c00100: /* MXCC stream source */
1098 env
->mxccregs
[0] = val
;
1100 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1102 env
->mxccdata
[0] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1104 env
->mxccdata
[1] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1106 env
->mxccdata
[2] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1108 env
->mxccdata
[3] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1111 case 0x01c00200: /* MXCC stream destination */
1113 env
->mxccregs
[1] = val
;
1115 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1117 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 0,
1119 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 8,
1121 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 16,
1123 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 24,
1126 case 0x01c00a00: /* MXCC control register */
1128 env
->mxccregs
[3] = val
;
1130 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1133 case 0x01c00a04: /* MXCC control register */
1135 env
->mxccregs
[3] = (env
->mxccregs
[0xa] & 0xffffffff00000000ULL
)
1138 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1141 case 0x01c00e00: /* MXCC error register */
1142 // writing a 1 bit clears the error
1144 env
->mxccregs
[6] &= ~val
;
1146 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1149 case 0x01c00f00: /* MBus port address register */
1151 env
->mxccregs
[7] = val
;
1153 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1157 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
1161 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi
,
1167 case 3: /* MMU flush */
1171 mmulev
= (addr
>> 8) & 15;
1172 DPRINTF_MMU("mmu flush level %d\n", mmulev
);
1174 case 0: // flush page
1175 tlb_flush_page(env
, addr
& 0xfffff000);
1177 case 1: // flush segment (256k)
1178 case 2: // flush region (16M)
1179 case 3: // flush context (4G)
1180 case 4: // flush entire
1191 case 4: /* write MMU regs */
1193 int reg
= (addr
>> 8) & 0x1f;
1196 oldreg
= env
->mmuregs
[reg
];
1198 case 0: // Control Register
1199 env
->mmuregs
[reg
] = (env
->mmuregs
[reg
] & 0xff000000) |
1201 // Mappings generated during no-fault mode or MMU
1202 // disabled mode are invalid in normal mode
1203 if ((oldreg
& (MMU_E
| MMU_NF
| env
->mmu_bm
)) !=
1204 (env
->mmuregs
[reg
] & (MMU_E
| MMU_NF
| env
->mmu_bm
)))
1207 case 1: // Context Table Pointer Register
1208 env
->mmuregs
[reg
] = val
& env
->mmu_ctpr_mask
;
1210 case 2: // Context Register
1211 env
->mmuregs
[reg
] = val
& env
->mmu_cxr_mask
;
1212 if (oldreg
!= env
->mmuregs
[reg
]) {
1213 /* we flush when the MMU context changes because
1214 QEMU has no MMU context support */
1218 case 3: // Synchronous Fault Status Register with Clear
1219 case 4: // Synchronous Fault Address Register
1221 case 0x10: // TLB Replacement Control Register
1222 env
->mmuregs
[reg
] = val
& env
->mmu_trcr_mask
;
1224 case 0x13: // Synchronous Fault Status Register with Read and Clear
1225 env
->mmuregs
[3] = val
& env
->mmu_sfsr_mask
;
1227 case 0x14: // Synchronous Fault Address Register
1228 env
->mmuregs
[4] = val
;
1231 env
->mmuregs
[reg
] = val
;
1234 if (oldreg
!= env
->mmuregs
[reg
]) {
1235 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1236 reg
, oldreg
, env
->mmuregs
[reg
]);
1243 case 5: // Turbosparc ITLB Diagnostic
1244 case 6: // Turbosparc DTLB Diagnostic
1245 case 7: // Turbosparc IOTLB Diagnostic
1247 case 0xa: /* User data access */
1250 stb_user(addr
, val
);
1253 stw_user(addr
, val
);
1257 stl_user(addr
, val
);
1260 stq_user(addr
, val
);
1264 case 0xb: /* Supervisor data access */
1267 stb_kernel(addr
, val
);
1270 stw_kernel(addr
, val
);
1274 stl_kernel(addr
, val
);
1277 stq_kernel(addr
, val
);
1281 case 0xc: /* I-cache tag */
1282 case 0xd: /* I-cache data */
1283 case 0xe: /* D-cache tag */
1284 case 0xf: /* D-cache data */
1285 case 0x10: /* I/D-cache flush page */
1286 case 0x11: /* I/D-cache flush segment */
1287 case 0x12: /* I/D-cache flush region */
1288 case 0x13: /* I/D-cache flush context */
1289 case 0x14: /* I/D-cache flush user */
1291 case 0x17: /* Block copy, sta access */
1297 uint32_t src
= val
& ~3, dst
= addr
& ~3, temp
;
1299 for (i
= 0; i
< 32; i
+= 4, src
+= 4, dst
+= 4) {
1300 temp
= ldl_kernel(src
);
1301 stl_kernel(dst
, temp
);
1305 case 0x1f: /* Block fill, stda access */
1308 // fill 32 bytes with val
1310 uint32_t dst
= addr
& 7;
1312 for (i
= 0; i
< 32; i
+= 8, dst
+= 8)
1313 stq_kernel(dst
, val
);
1316 case 0x20: /* MMU passthrough */
1320 stb_phys(addr
, val
);
1323 stw_phys(addr
, val
);
1327 stl_phys(addr
, val
);
1330 stq_phys(addr
, val
);
1335 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1339 stb_phys((target_phys_addr_t
)addr
1340 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1343 stw_phys((target_phys_addr_t
)addr
1344 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1348 stl_phys((target_phys_addr_t
)addr
1349 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1352 stq_phys((target_phys_addr_t
)addr
1353 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1358 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
1359 case 0x31: // store buffer data, Ross RT620 I-cache flush or
1360 // Turbosparc snoop RAM
1361 case 0x32: // store buffer control or Turbosparc page table
1362 // descriptor diagnostic
1363 case 0x36: /* I-cache flash clear */
1364 case 0x37: /* D-cache flash clear */
1365 case 0x38: /* breakpoint diagnostics */
1366 case 0x4c: /* breakpoint action */
1368 case 8: /* User code access, XXX */
1369 case 9: /* Supervisor code access, XXX */
1371 do_unassigned_access(addr
, 1, 0, asi
);
1375 dump_asi("write", addr
, asi
, size
, val
);
1379 #endif /* CONFIG_USER_ONLY */
1380 #else /* TARGET_SPARC64 */
1382 #ifdef CONFIG_USER_ONLY
1383 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
1386 #if defined(DEBUG_ASI)
1387 target_ulong last_addr
= addr
;
1391 raise_exception(TT_PRIV_ACT
);
1393 helper_check_align(addr
, size
- 1);
1394 address_mask(env
, &addr
);
1397 case 0x80: // Primary
1398 case 0x82: // Primary no-fault
1399 case 0x88: // Primary LE
1400 case 0x8a: // Primary no-fault LE
1404 ret
= ldub_raw(addr
);
1407 ret
= lduw_raw(addr
);
1410 ret
= ldl_raw(addr
);
1414 ret
= ldq_raw(addr
);
1419 case 0x81: // Secondary
1420 case 0x83: // Secondary no-fault
1421 case 0x89: // Secondary LE
1422 case 0x8b: // Secondary no-fault LE
1429 /* Convert from little endian */
1431 case 0x88: // Primary LE
1432 case 0x89: // Secondary LE
1433 case 0x8a: // Primary no-fault LE
1434 case 0x8b: // Secondary no-fault LE
1452 /* Convert to signed number */
1459 ret
= (int16_t) ret
;
1462 ret
= (int32_t) ret
;
1469 dump_asi("read ", last_addr
, asi
, size
, ret
);
1474 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
1477 dump_asi("write", addr
, asi
, size
, val
);
1480 raise_exception(TT_PRIV_ACT
);
1482 helper_check_align(addr
, size
- 1);
1483 address_mask(env
, &addr
);
1485 /* Convert to little endian */
1487 case 0x88: // Primary LE
1488 case 0x89: // Secondary LE
1491 addr
= bswap16(addr
);
1494 addr
= bswap32(addr
);
1497 addr
= bswap64(addr
);
1507 case 0x80: // Primary
1508 case 0x88: // Primary LE
1527 case 0x81: // Secondary
1528 case 0x89: // Secondary LE
1532 case 0x82: // Primary no-fault, RO
1533 case 0x83: // Secondary no-fault, RO
1534 case 0x8a: // Primary no-fault LE, RO
1535 case 0x8b: // Secondary no-fault LE, RO
1537 do_unassigned_access(addr
, 1, 0, 1);
1542 #else /* CONFIG_USER_ONLY */
1544 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
1547 #if defined(DEBUG_ASI)
1548 target_ulong last_addr
= addr
;
1551 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
1552 || (asi
>= 0x30 && asi
< 0x80 && !(env
->hpstate
& HS_PRIV
)))
1553 raise_exception(TT_PRIV_ACT
);
1555 helper_check_align(addr
, size
- 1);
1557 case 0x10: // As if user primary
1558 case 0x18: // As if user primary LE
1559 case 0x80: // Primary
1560 case 0x82: // Primary no-fault
1561 case 0x88: // Primary LE
1562 case 0x8a: // Primary no-fault LE
1563 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
1564 if (env
->hpstate
& HS_PRIV
) {
1567 ret
= ldub_hypv(addr
);
1570 ret
= lduw_hypv(addr
);
1573 ret
= ldl_hypv(addr
);
1577 ret
= ldq_hypv(addr
);
1583 ret
= ldub_kernel(addr
);
1586 ret
= lduw_kernel(addr
);
1589 ret
= ldl_kernel(addr
);
1593 ret
= ldq_kernel(addr
);
1600 ret
= ldub_user(addr
);
1603 ret
= lduw_user(addr
);
1606 ret
= ldl_user(addr
);
1610 ret
= ldq_user(addr
);
1615 case 0x14: // Bypass
1616 case 0x15: // Bypass, non-cacheable
1617 case 0x1c: // Bypass LE
1618 case 0x1d: // Bypass, non-cacheable LE
1622 ret
= ldub_phys(addr
);
1625 ret
= lduw_phys(addr
);
1628 ret
= ldl_phys(addr
);
1632 ret
= ldq_phys(addr
);
1637 case 0x04: // Nucleus
1638 case 0x0c: // Nucleus Little Endian (LE)
1639 case 0x11: // As if user secondary
1640 case 0x19: // As if user secondary LE
1641 case 0x24: // Nucleus quad LDD 128 bit atomic
1642 case 0x2c: // Nucleus quad LDD 128 bit atomic
1643 case 0x4a: // UPA config
1644 case 0x81: // Secondary
1645 case 0x83: // Secondary no-fault
1646 case 0x89: // Secondary LE
1647 case 0x8b: // Secondary no-fault LE
1653 case 0x50: // I-MMU regs
1655 int reg
= (addr
>> 3) & 0xf;
1657 ret
= env
->immuregs
[reg
];
1660 case 0x51: // I-MMU 8k TSB pointer
1661 case 0x52: // I-MMU 64k TSB pointer
1664 case 0x55: // I-MMU data access
1666 int reg
= (addr
>> 3) & 0x3f;
1668 ret
= env
->itlb_tte
[reg
];
1671 case 0x56: // I-MMU tag read
1675 for (i
= 0; i
< 64; i
++) {
1676 // Valid, ctx match, vaddr match
1677 if ((env
->itlb_tte
[i
] & 0x8000000000000000ULL
) != 0) {
1680 switch ((env
->itlb_tte
[i
] >> 61) & 3) {
1683 mask
= 0xffffffffffffffff;
1686 mask
= 0xffffffffffff0fff;
1689 mask
= 0xfffffffffff80fff;
1692 mask
= 0xffffffffffc00fff;
1695 if ((env
->itlb_tag
[i
] & mask
) == (addr
& mask
)) {
1696 ret
= env
->itlb_tte
[i
];
1703 case 0x58: // D-MMU regs
1705 int reg
= (addr
>> 3) & 0xf;
1707 ret
= env
->dmmuregs
[reg
];
1710 case 0x5d: // D-MMU data access
1712 int reg
= (addr
>> 3) & 0x3f;
1714 ret
= env
->dtlb_tte
[reg
];
1717 case 0x5e: // D-MMU tag read
1721 for (i
= 0; i
< 64; i
++) {
1722 // Valid, ctx match, vaddr match
1723 if ((env
->dtlb_tte
[i
] & 0x8000000000000000ULL
) != 0) {
1726 switch ((env
->dtlb_tte
[i
] >> 61) & 3) {
1729 mask
= 0xffffffffffffffff;
1732 mask
= 0xffffffffffff0fff;
1735 mask
= 0xfffffffffff80fff;
1738 mask
= 0xffffffffffc00fff;
1741 if ((env
->dtlb_tag
[i
] & mask
) == (addr
& mask
)) {
1742 ret
= env
->dtlb_tte
[i
];
1749 case 0x46: // D-cache data
1750 case 0x47: // D-cache tag access
1751 case 0x4b: // E-cache error enable
1752 case 0x4c: // E-cache asynchronous fault status
1753 case 0x4d: // E-cache asynchronous fault address
1754 case 0x4e: // E-cache tag data
1755 case 0x66: // I-cache instruction access
1756 case 0x67: // I-cache tag access
1757 case 0x6e: // I-cache predecode
1758 case 0x6f: // I-cache LRU etc.
1759 case 0x76: // E-cache tag
1760 case 0x7e: // E-cache tag
1762 case 0x59: // D-MMU 8k TSB pointer
1763 case 0x5a: // D-MMU 64k TSB pointer
1764 case 0x5b: // D-MMU data pointer
1765 case 0x48: // Interrupt dispatch, RO
1766 case 0x49: // Interrupt data receive
1767 case 0x7f: // Incoming interrupt vector, RO
1770 case 0x54: // I-MMU data in, WO
1771 case 0x57: // I-MMU demap, WO
1772 case 0x5c: // D-MMU data in, WO
1773 case 0x5f: // D-MMU demap, WO
1774 case 0x77: // Interrupt vector, WO
1776 do_unassigned_access(addr
, 0, 0, 1);
1781 /* Convert from little endian */
1783 case 0x0c: // Nucleus Little Endian (LE)
1784 case 0x18: // As if user primary LE
1785 case 0x19: // As if user secondary LE
1786 case 0x1c: // Bypass LE
1787 case 0x1d: // Bypass, non-cacheable LE
1788 case 0x88: // Primary LE
1789 case 0x89: // Secondary LE
1790 case 0x8a: // Primary no-fault LE
1791 case 0x8b: // Secondary no-fault LE
1809 /* Convert to signed number */
1816 ret
= (int16_t) ret
;
1819 ret
= (int32_t) ret
;
1826 dump_asi("read ", last_addr
, asi
, size
, ret
);
1831 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
1834 dump_asi("write", addr
, asi
, size
, val
);
1836 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
1837 || (asi
>= 0x30 && asi
< 0x80 && !(env
->hpstate
& HS_PRIV
)))
1838 raise_exception(TT_PRIV_ACT
);
1840 helper_check_align(addr
, size
- 1);
1841 /* Convert to little endian */
1843 case 0x0c: // Nucleus Little Endian (LE)
1844 case 0x18: // As if user primary LE
1845 case 0x19: // As if user secondary LE
1846 case 0x1c: // Bypass LE
1847 case 0x1d: // Bypass, non-cacheable LE
1848 case 0x88: // Primary LE
1849 case 0x89: // Secondary LE
1852 addr
= bswap16(addr
);
1855 addr
= bswap32(addr
);
1858 addr
= bswap64(addr
);
1868 case 0x10: // As if user primary
1869 case 0x18: // As if user primary LE
1870 case 0x80: // Primary
1871 case 0x88: // Primary LE
1872 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
1873 if (env
->hpstate
& HS_PRIV
) {
1876 stb_hypv(addr
, val
);
1879 stw_hypv(addr
, val
);
1882 stl_hypv(addr
, val
);
1886 stq_hypv(addr
, val
);
1892 stb_kernel(addr
, val
);
1895 stw_kernel(addr
, val
);
1898 stl_kernel(addr
, val
);
1902 stq_kernel(addr
, val
);
1909 stb_user(addr
, val
);
1912 stw_user(addr
, val
);
1915 stl_user(addr
, val
);
1919 stq_user(addr
, val
);
1924 case 0x14: // Bypass
1925 case 0x15: // Bypass, non-cacheable
1926 case 0x1c: // Bypass LE
1927 case 0x1d: // Bypass, non-cacheable LE
1931 stb_phys(addr
, val
);
1934 stw_phys(addr
, val
);
1937 stl_phys(addr
, val
);
1941 stq_phys(addr
, val
);
1946 case 0x04: // Nucleus
1947 case 0x0c: // Nucleus Little Endian (LE)
1948 case 0x11: // As if user secondary
1949 case 0x19: // As if user secondary LE
1950 case 0x24: // Nucleus quad LDD 128 bit atomic
1951 case 0x2c: // Nucleus quad LDD 128 bit atomic
1952 case 0x4a: // UPA config
1953 case 0x81: // Secondary
1954 case 0x89: // Secondary LE
1962 env
->lsu
= val
& (DMMU_E
| IMMU_E
);
1963 // Mappings generated during D/I MMU disabled mode are
1964 // invalid in normal mode
1965 if (oldreg
!= env
->lsu
) {
1966 DPRINTF_MMU("LSU change: 0x%" PRIx64
" -> 0x%" PRIx64
"\n",
1975 case 0x50: // I-MMU regs
1977 int reg
= (addr
>> 3) & 0xf;
1980 oldreg
= env
->immuregs
[reg
];
1985 case 1: // Not in I-MMU
1992 val
= 0; // Clear SFSR
1994 case 5: // TSB access
1995 case 6: // Tag access
1999 env
->immuregs
[reg
] = val
;
2000 if (oldreg
!= env
->immuregs
[reg
]) {
2001 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64
" -> 0x%08"
2002 PRIx64
"\n", reg
, oldreg
, env
->immuregs
[reg
]);
2009 case 0x54: // I-MMU data in
2013 // Try finding an invalid entry
2014 for (i
= 0; i
< 64; i
++) {
2015 if ((env
->itlb_tte
[i
] & 0x8000000000000000ULL
) == 0) {
2016 env
->itlb_tag
[i
] = env
->immuregs
[6];
2017 env
->itlb_tte
[i
] = val
;
2021 // Try finding an unlocked entry
2022 for (i
= 0; i
< 64; i
++) {
2023 if ((env
->itlb_tte
[i
] & 0x40) == 0) {
2024 env
->itlb_tag
[i
] = env
->immuregs
[6];
2025 env
->itlb_tte
[i
] = val
;
2032 case 0x55: // I-MMU data access
2034 unsigned int i
= (addr
>> 3) & 0x3f;
2036 env
->itlb_tag
[i
] = env
->immuregs
[6];
2037 env
->itlb_tte
[i
] = val
;
2040 case 0x57: // I-MMU demap
2043 case 0x58: // D-MMU regs
2045 int reg
= (addr
>> 3) & 0xf;
2048 oldreg
= env
->dmmuregs
[reg
];
2054 if ((val
& 1) == 0) {
2055 val
= 0; // Clear SFSR, Fault address
2056 env
->dmmuregs
[4] = 0;
2058 env
->dmmuregs
[reg
] = val
;
2060 case 1: // Primary context
2061 case 2: // Secondary context
2062 case 5: // TSB access
2063 case 6: // Tag access
2064 case 7: // Virtual Watchpoint
2065 case 8: // Physical Watchpoint
2069 env
->dmmuregs
[reg
] = val
;
2070 if (oldreg
!= env
->dmmuregs
[reg
]) {
2071 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64
" -> 0x%08"
2072 PRIx64
"\n", reg
, oldreg
, env
->dmmuregs
[reg
]);
2079 case 0x5c: // D-MMU data in
2083 // Try finding an invalid entry
2084 for (i
= 0; i
< 64; i
++) {
2085 if ((env
->dtlb_tte
[i
] & 0x8000000000000000ULL
) == 0) {
2086 env
->dtlb_tag
[i
] = env
->dmmuregs
[6];
2087 env
->dtlb_tte
[i
] = val
;
2091 // Try finding an unlocked entry
2092 for (i
= 0; i
< 64; i
++) {
2093 if ((env
->dtlb_tte
[i
] & 0x40) == 0) {
2094 env
->dtlb_tag
[i
] = env
->dmmuregs
[6];
2095 env
->dtlb_tte
[i
] = val
;
2102 case 0x5d: // D-MMU data access
2104 unsigned int i
= (addr
>> 3) & 0x3f;
2106 env
->dtlb_tag
[i
] = env
->dmmuregs
[6];
2107 env
->dtlb_tte
[i
] = val
;
2110 case 0x5f: // D-MMU demap
2111 case 0x49: // Interrupt data receive
2114 case 0x46: // D-cache data
2115 case 0x47: // D-cache tag access
2116 case 0x4b: // E-cache error enable
2117 case 0x4c: // E-cache asynchronous fault status
2118 case 0x4d: // E-cache asynchronous fault address
2119 case 0x4e: // E-cache tag data
2120 case 0x66: // I-cache instruction access
2121 case 0x67: // I-cache tag access
2122 case 0x6e: // I-cache predecode
2123 case 0x6f: // I-cache LRU etc.
2124 case 0x76: // E-cache tag
2125 case 0x7e: // E-cache tag
2127 case 0x51: // I-MMU 8k TSB pointer, RO
2128 case 0x52: // I-MMU 64k TSB pointer, RO
2129 case 0x56: // I-MMU tag read, RO
2130 case 0x59: // D-MMU 8k TSB pointer, RO
2131 case 0x5a: // D-MMU 64k TSB pointer, RO
2132 case 0x5b: // D-MMU data pointer, RO
2133 case 0x5e: // D-MMU tag read, RO
2134 case 0x48: // Interrupt dispatch, RO
2135 case 0x7f: // Incoming interrupt vector, RO
2136 case 0x82: // Primary no-fault, RO
2137 case 0x83: // Secondary no-fault, RO
2138 case 0x8a: // Primary no-fault LE, RO
2139 case 0x8b: // Secondary no-fault LE, RO
2141 do_unassigned_access(addr
, 1, 0, 1);
2145 #endif /* CONFIG_USER_ONLY */
2147 void helper_ldf_asi(target_ulong addr
, int asi
, int size
, int rd
)
2152 helper_check_align(addr
, 3);
2154 case 0xf0: // Block load primary
2155 case 0xf1: // Block load secondary
2156 case 0xf8: // Block load primary LE
2157 case 0xf9: // Block load secondary LE
2159 raise_exception(TT_ILL_INSN
);
2162 helper_check_align(addr
, 0x3f);
2163 for (i
= 0; i
< 16; i
++) {
2164 *(uint32_t *)&env
->fpr
[rd
++] = helper_ld_asi(addr
, asi
& 0x8f, 4,
2174 val
= helper_ld_asi(addr
, asi
, size
, 0);
2178 *((uint32_t *)&FT0
) = val
;
2181 *((int64_t *)&DT0
) = val
;
2189 void helper_stf_asi(target_ulong addr
, int asi
, int size
, int rd
)
2192 target_ulong val
= 0;
2194 helper_check_align(addr
, 3);
2196 case 0xf0: // Block store primary
2197 case 0xf1: // Block store secondary
2198 case 0xf8: // Block store primary LE
2199 case 0xf9: // Block store secondary LE
2201 raise_exception(TT_ILL_INSN
);
2204 helper_check_align(addr
, 0x3f);
2205 for (i
= 0; i
< 16; i
++) {
2206 val
= *(uint32_t *)&env
->fpr
[rd
++];
2207 helper_st_asi(addr
, val
, asi
& 0x8f, 4);
2219 val
= *((uint32_t *)&FT0
);
2222 val
= *((int64_t *)&DT0
);
2228 helper_st_asi(addr
, val
, asi
, size
);
2231 target_ulong
helper_cas_asi(target_ulong addr
, target_ulong val1
,
2232 target_ulong val2
, uint32_t asi
)
2236 val1
&= 0xffffffffUL
;
2237 ret
= helper_ld_asi(addr
, asi
, 4, 0);
2238 ret
&= 0xffffffffUL
;
2240 helper_st_asi(addr
, val2
& 0xffffffffUL
, asi
, 4);
2244 target_ulong
helper_casx_asi(target_ulong addr
, target_ulong val1
,
2245 target_ulong val2
, uint32_t asi
)
2249 ret
= helper_ld_asi(addr
, asi
, 8, 0);
2251 helper_st_asi(addr
, val2
, asi
, 8);
2254 #endif /* TARGET_SPARC64 */
2256 #ifndef TARGET_SPARC64
2257 void helper_rett(void)
2261 if (env
->psret
== 1)
2262 raise_exception(TT_ILL_INSN
);
2265 cwp
= cpu_cwp_inc(env
, env
->cwp
+ 1) ;
2266 if (env
->wim
& (1 << cwp
)) {
2267 raise_exception(TT_WIN_UNF
);
2270 env
->psrs
= env
->psrps
;
2274 target_ulong
helper_udiv(target_ulong a
, target_ulong b
)
2279 x0
= a
| ((uint64_t) (env
->y
) << 32);
2283 raise_exception(TT_DIV_ZERO
);
2287 if (x0
> 0xffffffff) {
2296 target_ulong
helper_sdiv(target_ulong a
, target_ulong b
)
2301 x0
= a
| ((int64_t) (env
->y
) << 32);
2305 raise_exception(TT_DIV_ZERO
);
2309 if ((int32_t) x0
!= x0
) {
2311 return x0
< 0? 0x80000000: 0x7fffffff;
2318 uint64_t helper_pack64(target_ulong high
, target_ulong low
)
2320 return ((uint64_t)high
<< 32) | (uint64_t)(low
& 0xffffffff);
2323 void helper_stdf(target_ulong addr
, int mem_idx
)
2325 helper_check_align(addr
, 7);
2326 #if !defined(CONFIG_USER_ONLY)
2329 stfq_user(addr
, DT0
);
2332 stfq_kernel(addr
, DT0
);
2334 #ifdef TARGET_SPARC64
2336 stfq_hypv(addr
, DT0
);
2343 address_mask(env
, &addr
);
2344 stfq_raw(addr
, DT0
);
2348 void helper_lddf(target_ulong addr
, int mem_idx
)
2350 helper_check_align(addr
, 7);
2351 #if !defined(CONFIG_USER_ONLY)
2354 DT0
= ldfq_user(addr
);
2357 DT0
= ldfq_kernel(addr
);
2359 #ifdef TARGET_SPARC64
2361 DT0
= ldfq_hypv(addr
);
2368 address_mask(env
, &addr
);
2369 DT0
= ldfq_raw(addr
);
2373 void helper_ldqf(target_ulong addr
, int mem_idx
)
2375 // XXX add 128 bit load
2378 helper_check_align(addr
, 7);
2379 #if !defined(CONFIG_USER_ONLY)
2382 u
.ll
.upper
= ldq_user(addr
);
2383 u
.ll
.lower
= ldq_user(addr
+ 8);
2387 u
.ll
.upper
= ldq_kernel(addr
);
2388 u
.ll
.lower
= ldq_kernel(addr
+ 8);
2391 #ifdef TARGET_SPARC64
2393 u
.ll
.upper
= ldq_hypv(addr
);
2394 u
.ll
.lower
= ldq_hypv(addr
+ 8);
2402 address_mask(env
, &addr
);
2403 u
.ll
.upper
= ldq_raw(addr
);
2404 u
.ll
.lower
= ldq_raw((addr
+ 8) & 0xffffffffULL
);
2409 void helper_stqf(target_ulong addr
, int mem_idx
)
2411 // XXX add 128 bit store
2414 helper_check_align(addr
, 7);
2415 #if !defined(CONFIG_USER_ONLY)
2419 stq_user(addr
, u
.ll
.upper
);
2420 stq_user(addr
+ 8, u
.ll
.lower
);
2424 stq_kernel(addr
, u
.ll
.upper
);
2425 stq_kernel(addr
+ 8, u
.ll
.lower
);
2427 #ifdef TARGET_SPARC64
2430 stq_hypv(addr
, u
.ll
.upper
);
2431 stq_hypv(addr
+ 8, u
.ll
.lower
);
2439 address_mask(env
, &addr
);
2440 stq_raw(addr
, u
.ll
.upper
);
2441 stq_raw((addr
+ 8) & 0xffffffffULL
, u
.ll
.lower
);
2445 void helper_ldfsr(void)
2449 PUT_FSR32(env
, *((uint32_t *) &FT0
));
2450 switch (env
->fsr
& FSR_RD_MASK
) {
2451 case FSR_RD_NEAREST
:
2452 rnd_mode
= float_round_nearest_even
;
2456 rnd_mode
= float_round_to_zero
;
2459 rnd_mode
= float_round_up
;
2462 rnd_mode
= float_round_down
;
2465 set_float_rounding_mode(rnd_mode
, &env
->fp_status
);
2468 void helper_stfsr(void)
2470 *((uint32_t *) &FT0
) = GET_FSR32(env
);
2473 void helper_debug(void)
2475 env
->exception_index
= EXCP_DEBUG
;
2479 #ifndef TARGET_SPARC64
2480 /* XXX: use another pointer for %iN registers to avoid slow wrapping
2482 void helper_save(void)
2486 cwp
= cpu_cwp_dec(env
, env
->cwp
- 1);
2487 if (env
->wim
& (1 << cwp
)) {
2488 raise_exception(TT_WIN_OVF
);
2493 void helper_restore(void)
2497 cwp
= cpu_cwp_inc(env
, env
->cwp
+ 1);
2498 if (env
->wim
& (1 << cwp
)) {
2499 raise_exception(TT_WIN_UNF
);
2504 void helper_wrpsr(target_ulong new_psr
)
2506 if ((new_psr
& PSR_CWP
) >= env
->nwindows
)
2507 raise_exception(TT_ILL_INSN
);
2509 PUT_PSR(env
, new_psr
);
2512 target_ulong
helper_rdpsr(void)
2514 return GET_PSR(env
);
2518 /* XXX: use another pointer for %iN registers to avoid slow wrapping
2520 void helper_save(void)
2524 cwp
= cpu_cwp_dec(env
, env
->cwp
- 1);
2525 if (env
->cansave
== 0) {
2526 raise_exception(TT_SPILL
| (env
->otherwin
!= 0 ?
2527 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
2528 ((env
->wstate
& 0x7) << 2)));
2530 if (env
->cleanwin
- env
->canrestore
== 0) {
2531 // XXX Clean windows without trap
2532 raise_exception(TT_CLRWIN
);
2541 void helper_restore(void)
2545 cwp
= cpu_cwp_inc(env
, env
->cwp
+ 1);
2546 if (env
->canrestore
== 0) {
2547 raise_exception(TT_FILL
| (env
->otherwin
!= 0 ?
2548 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
2549 ((env
->wstate
& 0x7) << 2)));
2557 void helper_flushw(void)
2559 if (env
->cansave
!= env
->nwindows
- 2) {
2560 raise_exception(TT_SPILL
| (env
->otherwin
!= 0 ?
2561 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
2562 ((env
->wstate
& 0x7) << 2)));
2566 void helper_saved(void)
2569 if (env
->otherwin
== 0)
2575 void helper_restored(void)
2578 if (env
->cleanwin
< env
->nwindows
- 1)
2580 if (env
->otherwin
== 0)
2586 target_ulong
helper_rdccr(void)
2588 return GET_CCR(env
);
2591 void helper_wrccr(target_ulong new_ccr
)
2593 PUT_CCR(env
, new_ccr
);
2596 // CWP handling is reversed in V9, but we still use the V8 register
2598 target_ulong
helper_rdcwp(void)
2600 return GET_CWP64(env
);
2603 void helper_wrcwp(target_ulong new_cwp
)
2605 PUT_CWP64(env
, new_cwp
);
2608 // This function uses non-native bit order
2609 #define GET_FIELD(X, FROM, TO) \
2610 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
2612 // This function uses the order in the manuals, i.e. bit 0 is 2^0
2613 #define GET_FIELD_SP(X, FROM, TO) \
2614 GET_FIELD(X, 63 - (TO), 63 - (FROM))
2616 target_ulong
helper_array8(target_ulong pixel_addr
, target_ulong cubesize
)
2618 return (GET_FIELD_SP(pixel_addr
, 60, 63) << (17 + 2 * cubesize
)) |
2619 (GET_FIELD_SP(pixel_addr
, 39, 39 + cubesize
- 1) << (17 + cubesize
)) |
2620 (GET_FIELD_SP(pixel_addr
, 17 + cubesize
- 1, 17) << 17) |
2621 (GET_FIELD_SP(pixel_addr
, 56, 59) << 13) |
2622 (GET_FIELD_SP(pixel_addr
, 35, 38) << 9) |
2623 (GET_FIELD_SP(pixel_addr
, 13, 16) << 5) |
2624 (((pixel_addr
>> 55) & 1) << 4) |
2625 (GET_FIELD_SP(pixel_addr
, 33, 34) << 2) |
2626 GET_FIELD_SP(pixel_addr
, 11, 12);
2629 target_ulong
helper_alignaddr(target_ulong addr
, target_ulong offset
)
2633 tmp
= addr
+ offset
;
2635 env
->gsr
|= tmp
& 7ULL;
2639 target_ulong
helper_popc(target_ulong val
)
2641 return ctpop64(val
);
2644 static inline uint64_t *get_gregset(uint64_t pstate
)
2659 void change_pstate(uint64_t new_pstate
)
2661 uint64_t pstate_regs
, new_pstate_regs
;
2662 uint64_t *src
, *dst
;
2664 pstate_regs
= env
->pstate
& 0xc01;
2665 new_pstate_regs
= new_pstate
& 0xc01;
2666 if (new_pstate_regs
!= pstate_regs
) {
2667 // Switch global register bank
2668 src
= get_gregset(new_pstate_regs
);
2669 dst
= get_gregset(pstate_regs
);
2670 memcpy32(dst
, env
->gregs
);
2671 memcpy32(env
->gregs
, src
);
2673 env
->pstate
= new_pstate
;
2676 void helper_wrpstate(target_ulong new_state
)
2678 change_pstate(new_state
& 0xf3f);
2681 void helper_done(void)
2683 env
->pc
= env
->tsptr
->tpc
;
2684 env
->npc
= env
->tsptr
->tnpc
+ 4;
2685 PUT_CCR(env
, env
->tsptr
->tstate
>> 32);
2686 env
->asi
= (env
->tsptr
->tstate
>> 24) & 0xff;
2687 change_pstate((env
->tsptr
->tstate
>> 8) & 0xf3f);
2688 PUT_CWP64(env
, env
->tsptr
->tstate
& 0xff);
2690 env
->tsptr
= &env
->ts
[env
->tl
];
2693 void helper_retry(void)
2695 env
->pc
= env
->tsptr
->tpc
;
2696 env
->npc
= env
->tsptr
->tnpc
;
2697 PUT_CCR(env
, env
->tsptr
->tstate
>> 32);
2698 env
->asi
= (env
->tsptr
->tstate
>> 24) & 0xff;
2699 change_pstate((env
->tsptr
->tstate
>> 8) & 0xf3f);
2700 PUT_CWP64(env
, env
->tsptr
->tstate
& 0xff);
2702 env
->tsptr
= &env
->ts
[env
->tl
];
2706 void cpu_set_cwp(CPUState
*env1
, int new_cwp
)
2708 /* put the modified wrap registers at their proper location */
2709 if (env1
->cwp
== env1
->nwindows
- 1)
2710 memcpy32(env1
->regbase
, env1
->regbase
+ env1
->nwindows
* 16);
2711 env1
->cwp
= new_cwp
;
2712 /* put the wrap registers at their temporary location */
2713 if (new_cwp
== env1
->nwindows
- 1)
2714 memcpy32(env1
->regbase
+ env1
->nwindows
* 16, env1
->regbase
);
2715 env1
->regwptr
= env1
->regbase
+ (new_cwp
* 16);
2718 void set_cwp(int new_cwp
)
2720 cpu_set_cwp(env
, new_cwp
);
2723 void helper_flush(target_ulong addr
)
2726 tb_invalidate_page_range(addr
, addr
+ 8);
2729 #if !defined(CONFIG_USER_ONLY)
2731 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
2734 #define MMUSUFFIX _mmu
2735 #define ALIGNED_ONLY
2738 #include "softmmu_template.h"
2741 #include "softmmu_template.h"
2744 #include "softmmu_template.h"
2747 #include "softmmu_template.h"
2749 /* XXX: make it generic ? */
2750 static void cpu_restore_state2(void *retaddr
)
2752 TranslationBlock
*tb
;
2756 /* now we have a real cpu fault */
2757 pc
= (unsigned long)retaddr
;
2758 tb
= tb_find_pc(pc
);
2760 /* the PC is inside the translated code. It means that we have
2761 a virtual CPU fault */
2762 cpu_restore_state(tb
, env
, pc
, (void *)(long)env
->cond
);
2767 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
2770 #ifdef DEBUG_UNALIGNED
2771 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
2772 "\n", addr
, env
->pc
);
2774 cpu_restore_state2(retaddr
);
2775 raise_exception(TT_UNALIGNED
);
2778 /* try to fill the TLB and return an exception if error. If retaddr is
2779 NULL, it means that the function was called in C code (i.e. not
2780 from generated code or from helper.c) */
2781 /* XXX: fix it to restore all registers */
2782 void tlb_fill(target_ulong addr
, int is_write
, int mmu_idx
, void *retaddr
)
2785 CPUState
*saved_env
;
2787 /* XXX: hack to restore env in all cases, even if not called from
2790 env
= cpu_single_env
;
2792 ret
= cpu_sparc_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
, 1);
2794 cpu_restore_state2(retaddr
);
2802 #ifndef TARGET_SPARC64
2803 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
2806 CPUState
*saved_env
;
2808 /* XXX: hack to restore env in all cases, even if not called from
2811 env
= cpu_single_env
;
2812 #ifdef DEBUG_UNASSIGNED
2814 printf("Unassigned mem %s access to " TARGET_FMT_plx
2815 " asi 0x%02x from " TARGET_FMT_lx
"\n",
2816 is_exec
? "exec" : is_write
? "write" : "read", addr
, is_asi
,
2819 printf("Unassigned mem %s access to " TARGET_FMT_plx
" from "
2821 is_exec
? "exec" : is_write
? "write" : "read", addr
, env
->pc
);
2823 if (env
->mmuregs
[3]) /* Fault status register */
2824 env
->mmuregs
[3] = 1; /* overflow (not read before another fault) */
2826 env
->mmuregs
[3] |= 1 << 16;
2828 env
->mmuregs
[3] |= 1 << 5;
2830 env
->mmuregs
[3] |= 1 << 6;
2832 env
->mmuregs
[3] |= 1 << 7;
2833 env
->mmuregs
[3] |= (5 << 2) | 2;
2834 env
->mmuregs
[4] = addr
; /* Fault address register */
2835 if ((env
->mmuregs
[0] & MMU_E
) && !(env
->mmuregs
[0] & MMU_NF
)) {
2837 raise_exception(TT_CODE_ACCESS
);
2839 raise_exception(TT_DATA_ACCESS
);
2844 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
2847 #ifdef DEBUG_UNASSIGNED
2848 CPUState
*saved_env
;
2850 /* XXX: hack to restore env in all cases, even if not called from
2853 env
= cpu_single_env
;
2854 printf("Unassigned mem access to " TARGET_FMT_plx
" from " TARGET_FMT_lx
2855 "\n", addr
, env
->pc
);
2859 raise_exception(TT_CODE_ACCESS
);
2861 raise_exception(TT_DATA_ACCESS
);