]>
git.proxmox.com Git - mirror_qemu.git/blob - target-sparc/op_helper.c
2 #include "host-utils.h"
8 //#define DEBUG_UNALIGNED
9 //#define DEBUG_UNASSIGNED
12 //#define DEBUG_PSTATE
13 //#define DEBUG_CACHE_CONTROL
16 #define DPRINTF_MMU(fmt, ...) \
17 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
19 #define DPRINTF_MMU(fmt, ...) do {} while (0)
23 #define DPRINTF_MXCC(fmt, ...) \
24 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
26 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
30 #define DPRINTF_ASI(fmt, ...) \
31 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
35 #define DPRINTF_PSTATE(fmt, ...) \
36 do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
38 #define DPRINTF_PSTATE(fmt, ...) do {} while (0)
41 #ifdef DEBUG_CACHE_CONTROL
42 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
43 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
45 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
50 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
52 #define AM_CHECK(env1) (1)
56 #define DT0 (env->dt0)
57 #define DT1 (env->dt1)
58 #define QT0 (env->qt0)
59 #define QT1 (env->qt1)
61 /* Leon3 cache control */
63 /* Cache control: emulate the behavior of cache control registers but without
64 any effect on the emulated */
66 #define CACHE_STATE_MASK 0x3
67 #define CACHE_DISABLED 0x0
68 #define CACHE_FROZEN 0x1
69 #define CACHE_ENABLED 0x3
71 /* Cache Control register fields */
73 #define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */
74 #define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */
75 #define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */
76 #define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */
77 #define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */
78 #define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */
79 #define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */
80 #define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */
82 #if defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
83 static void do_unassigned_access(target_ulong addr
, int is_write
, int is_exec
,
84 int is_asi
, int size
);
87 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
88 // Calculates TSB pointer value for fault page size 8k or 64k
89 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register
,
90 uint64_t tag_access_register
,
93 uint64_t tsb_base
= tsb_register
& ~0x1fffULL
;
94 int tsb_split
= (tsb_register
& 0x1000ULL
) ? 1 : 0;
95 int tsb_size
= tsb_register
& 0xf;
97 // discard lower 13 bits which hold tag access context
98 uint64_t tag_access_va
= tag_access_register
& ~0x1fffULL
;
101 uint64_t tsb_base_mask
= ~0x1fffULL
;
102 uint64_t va
= tag_access_va
;
104 // move va bits to correct position
105 if (page_size
== 8*1024) {
107 } else if (page_size
== 64*1024) {
112 tsb_base_mask
<<= tsb_size
;
115 // calculate tsb_base mask and adjust va if split is in use
117 if (page_size
== 8*1024) {
118 va
&= ~(1ULL << (13 + tsb_size
));
119 } else if (page_size
== 64*1024) {
120 va
|= (1ULL << (13 + tsb_size
));
125 return ((tsb_base
& tsb_base_mask
) | (va
& ~tsb_base_mask
)) & ~0xfULL
;
128 // Calculates tag target register value by reordering bits
129 // in tag access register
130 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register
)
132 return ((tag_access_register
& 0x1fff) << 48) | (tag_access_register
>> 22);
135 static void replace_tlb_entry(SparcTLBEntry
*tlb
,
136 uint64_t tlb_tag
, uint64_t tlb_tte
,
139 target_ulong mask
, size
, va
, offset
;
141 // flush page range if translation is valid
142 if (TTE_IS_VALID(tlb
->tte
)) {
144 mask
= 0xffffffffffffe000ULL
;
145 mask
<<= 3 * ((tlb
->tte
>> 61) & 3);
148 va
= tlb
->tag
& mask
;
150 for (offset
= 0; offset
< size
; offset
+= TARGET_PAGE_SIZE
) {
151 tlb_flush_page(env1
, va
+ offset
);
159 static void demap_tlb(SparcTLBEntry
*tlb
, target_ulong demap_addr
,
160 const char* strmmu
, CPUState
*env1
)
166 int is_demap_context
= (demap_addr
>> 6) & 1;
169 switch ((demap_addr
>> 4) & 3) {
171 context
= env1
->dmmu
.mmu_primary_context
;
174 context
= env1
->dmmu
.mmu_secondary_context
;
184 for (i
= 0; i
< 64; i
++) {
185 if (TTE_IS_VALID(tlb
[i
].tte
)) {
187 if (is_demap_context
) {
188 // will remove non-global entries matching context value
189 if (TTE_IS_GLOBAL(tlb
[i
].tte
) ||
190 !tlb_compare_context(&tlb
[i
], context
)) {
195 // will remove any entry matching VA
196 mask
= 0xffffffffffffe000ULL
;
197 mask
<<= 3 * ((tlb
[i
].tte
>> 61) & 3);
199 if (!compare_masked(demap_addr
, tlb
[i
].tag
, mask
)) {
203 // entry should be global or matching context value
204 if (!TTE_IS_GLOBAL(tlb
[i
].tte
) &&
205 !tlb_compare_context(&tlb
[i
], context
)) {
210 replace_tlb_entry(&tlb
[i
], 0, 0, env1
);
212 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu
, i
);
213 dump_mmu(stdout
, fprintf
, env1
);
219 static void replace_tlb_1bit_lru(SparcTLBEntry
*tlb
,
220 uint64_t tlb_tag
, uint64_t tlb_tte
,
221 const char* strmmu
, CPUState
*env1
)
223 unsigned int i
, replace_used
;
225 // Try replacing invalid entry
226 for (i
= 0; i
< 64; i
++) {
227 if (!TTE_IS_VALID(tlb
[i
].tte
)) {
228 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
230 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu
, i
);
231 dump_mmu(stdout
, fprintf
, env1
);
237 // All entries are valid, try replacing unlocked entry
239 for (replace_used
= 0; replace_used
< 2; ++replace_used
) {
241 // Used entries are not replaced on first pass
243 for (i
= 0; i
< 64; i
++) {
244 if (!TTE_IS_LOCKED(tlb
[i
].tte
) && !TTE_IS_USED(tlb
[i
].tte
)) {
246 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
248 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
249 strmmu
, (replace_used
?"used":"unused"), i
);
250 dump_mmu(stdout
, fprintf
, env1
);
256 // Now reset used bit and search for unused entries again
258 for (i
= 0; i
< 64; i
++) {
259 TTE_SET_UNUSED(tlb
[i
].tte
);
264 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu
);
271 static inline target_ulong
address_mask(CPUState
*env1
, target_ulong addr
)
273 #ifdef TARGET_SPARC64
275 addr
&= 0xffffffffULL
;
280 /* returns true if access using this ASI is to have address translated by MMU
281 otherwise access is to raw physical address */
282 static inline int is_translating_asi(int asi
)
284 #ifdef TARGET_SPARC64
285 /* Ultrasparc IIi translating asi
286 - note this list is defined by cpu implementation
301 /* TODO: check sparc32 bits */
306 static inline target_ulong
asi_address_mask(CPUState
*env1
,
307 int asi
, target_ulong addr
)
309 if (is_translating_asi(asi
)) {
310 return address_mask(env
, addr
);
316 static void raise_exception(int tt
)
318 env
->exception_index
= tt
;
322 void HELPER(raise_exception
)(int tt
)
327 void helper_shutdown(void)
329 #if !defined(CONFIG_USER_ONLY)
330 qemu_system_shutdown_request();
334 void helper_check_align(target_ulong addr
, uint32_t align
)
337 #ifdef DEBUG_UNALIGNED
338 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
339 "\n", addr
, env
->pc
);
341 raise_exception(TT_UNALIGNED
);
345 #define F_HELPER(name, p) void helper_f##name##p(void)
347 #define F_BINOP(name) \
348 float32 helper_f ## name ## s (float32 src1, float32 src2) \
350 return float32_ ## name (src1, src2, &env->fp_status); \
354 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
358 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
367 void helper_fsmuld(float32 src1
, float32 src2
)
369 DT0
= float64_mul(float32_to_float64(src1
, &env
->fp_status
),
370 float32_to_float64(src2
, &env
->fp_status
),
374 void helper_fdmulq(void)
376 QT0
= float128_mul(float64_to_float128(DT0
, &env
->fp_status
),
377 float64_to_float128(DT1
, &env
->fp_status
),
381 float32
helper_fnegs(float32 src
)
383 return float32_chs(src
);
386 #ifdef TARGET_SPARC64
389 DT0
= float64_chs(DT1
);
394 QT0
= float128_chs(QT1
);
398 /* Integer to float conversion. */
399 float32
helper_fitos(int32_t src
)
401 return int32_to_float32(src
, &env
->fp_status
);
404 void helper_fitod(int32_t src
)
406 DT0
= int32_to_float64(src
, &env
->fp_status
);
409 void helper_fitoq(int32_t src
)
411 QT0
= int32_to_float128(src
, &env
->fp_status
);
414 #ifdef TARGET_SPARC64
415 float32
helper_fxtos(void)
417 return int64_to_float32(*((int64_t *)&DT1
), &env
->fp_status
);
422 DT0
= int64_to_float64(*((int64_t *)&DT1
), &env
->fp_status
);
427 QT0
= int64_to_float128(*((int64_t *)&DT1
), &env
->fp_status
);
432 /* floating point conversion */
433 float32
helper_fdtos(void)
435 return float64_to_float32(DT1
, &env
->fp_status
);
438 void helper_fstod(float32 src
)
440 DT0
= float32_to_float64(src
, &env
->fp_status
);
443 float32
helper_fqtos(void)
445 return float128_to_float32(QT1
, &env
->fp_status
);
448 void helper_fstoq(float32 src
)
450 QT0
= float32_to_float128(src
, &env
->fp_status
);
453 void helper_fqtod(void)
455 DT0
= float128_to_float64(QT1
, &env
->fp_status
);
458 void helper_fdtoq(void)
460 QT0
= float64_to_float128(DT1
, &env
->fp_status
);
463 /* Float to integer conversion. */
464 int32_t helper_fstoi(float32 src
)
466 return float32_to_int32_round_to_zero(src
, &env
->fp_status
);
469 int32_t helper_fdtoi(void)
471 return float64_to_int32_round_to_zero(DT1
, &env
->fp_status
);
474 int32_t helper_fqtoi(void)
476 return float128_to_int32_round_to_zero(QT1
, &env
->fp_status
);
479 #ifdef TARGET_SPARC64
480 void helper_fstox(float32 src
)
482 *((int64_t *)&DT0
) = float32_to_int64_round_to_zero(src
, &env
->fp_status
);
485 void helper_fdtox(void)
487 *((int64_t *)&DT0
) = float64_to_int64_round_to_zero(DT1
, &env
->fp_status
);
490 void helper_fqtox(void)
492 *((int64_t *)&DT0
) = float128_to_int64_round_to_zero(QT1
, &env
->fp_status
);
495 void helper_faligndata(void)
499 tmp
= (*((uint64_t *)&DT0
)) << ((env
->gsr
& 7) * 8);
500 /* on many architectures a shift of 64 does nothing */
501 if ((env
->gsr
& 7) != 0) {
502 tmp
|= (*((uint64_t *)&DT1
)) >> (64 - (env
->gsr
& 7) * 8);
504 *((uint64_t *)&DT0
) = tmp
;
507 #ifdef HOST_WORDS_BIGENDIAN
508 #define VIS_B64(n) b[7 - (n)]
509 #define VIS_W64(n) w[3 - (n)]
510 #define VIS_SW64(n) sw[3 - (n)]
511 #define VIS_L64(n) l[1 - (n)]
512 #define VIS_B32(n) b[3 - (n)]
513 #define VIS_W32(n) w[1 - (n)]
515 #define VIS_B64(n) b[n]
516 #define VIS_W64(n) w[n]
517 #define VIS_SW64(n) sw[n]
518 #define VIS_L64(n) l[n]
519 #define VIS_B32(n) b[n]
520 #define VIS_W32(n) w[n]
538 void helper_fpmerge(void)
545 // Reverse calculation order to handle overlap
546 d
.VIS_B64(7) = s
.VIS_B64(3);
547 d
.VIS_B64(6) = d
.VIS_B64(3);
548 d
.VIS_B64(5) = s
.VIS_B64(2);
549 d
.VIS_B64(4) = d
.VIS_B64(2);
550 d
.VIS_B64(3) = s
.VIS_B64(1);
551 d
.VIS_B64(2) = d
.VIS_B64(1);
552 d
.VIS_B64(1) = s
.VIS_B64(0);
553 //d.VIS_B64(0) = d.VIS_B64(0);
558 void helper_fmul8x16(void)
567 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
568 if ((tmp & 0xff) > 0x7f) \
570 d.VIS_W64(r) = tmp >> 8;
581 void helper_fmul8x16al(void)
590 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
591 if ((tmp & 0xff) > 0x7f) \
593 d.VIS_W64(r) = tmp >> 8;
604 void helper_fmul8x16au(void)
613 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
614 if ((tmp & 0xff) > 0x7f) \
616 d.VIS_W64(r) = tmp >> 8;
627 void helper_fmul8sux16(void)
636 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
637 if ((tmp & 0xff) > 0x7f) \
639 d.VIS_W64(r) = tmp >> 8;
650 void helper_fmul8ulx16(void)
659 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
660 if ((tmp & 0xff) > 0x7f) \
662 d.VIS_W64(r) = tmp >> 8;
673 void helper_fmuld8sux16(void)
682 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
683 if ((tmp & 0xff) > 0x7f) \
687 // Reverse calculation order to handle overlap
695 void helper_fmuld8ulx16(void)
704 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
705 if ((tmp & 0xff) > 0x7f) \
709 // Reverse calculation order to handle overlap
717 void helper_fexpand(void)
722 s
.l
= (uint32_t)(*(uint64_t *)&DT0
& 0xffffffff);
724 d
.VIS_W64(0) = s
.VIS_B32(0) << 4;
725 d
.VIS_W64(1) = s
.VIS_B32(1) << 4;
726 d
.VIS_W64(2) = s
.VIS_B32(2) << 4;
727 d
.VIS_W64(3) = s
.VIS_B32(3) << 4;
732 #define VIS_HELPER(name, F) \
733 void name##16(void) \
740 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
741 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
742 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
743 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
748 uint32_t name##16s(uint32_t src1, uint32_t src2) \
755 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
756 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
761 void name##32(void) \
768 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
769 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
774 uint32_t name##32s(uint32_t src1, uint32_t src2) \
786 #define FADD(a, b) ((a) + (b))
787 #define FSUB(a, b) ((a) - (b))
788 VIS_HELPER(helper_fpadd
, FADD
)
789 VIS_HELPER(helper_fpsub
, FSUB
)
791 #define VIS_CMPHELPER(name, F) \
792 void name##16(void) \
799 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
800 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
801 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
802 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
807 void name##32(void) \
814 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
815 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
820 #define FCMPGT(a, b) ((a) > (b))
821 #define FCMPEQ(a, b) ((a) == (b))
822 #define FCMPLE(a, b) ((a) <= (b))
823 #define FCMPNE(a, b) ((a) != (b))
825 VIS_CMPHELPER(helper_fcmpgt
, FCMPGT
)
826 VIS_CMPHELPER(helper_fcmpeq
, FCMPEQ
)
827 VIS_CMPHELPER(helper_fcmple
, FCMPLE
)
828 VIS_CMPHELPER(helper_fcmpne
, FCMPNE
)
831 void helper_check_ieee_exceptions(void)
835 status
= get_float_exception_flags(&env
->fp_status
);
837 /* Copy IEEE 754 flags into FSR */
838 if (status
& float_flag_invalid
)
840 if (status
& float_flag_overflow
)
842 if (status
& float_flag_underflow
)
844 if (status
& float_flag_divbyzero
)
846 if (status
& float_flag_inexact
)
849 if ((env
->fsr
& FSR_CEXC_MASK
) & ((env
->fsr
& FSR_TEM_MASK
) >> 23)) {
850 /* Unmasked exception, generate a trap */
851 env
->fsr
|= FSR_FTT_IEEE_EXCP
;
852 raise_exception(TT_FP_EXCP
);
854 /* Accumulate exceptions */
855 env
->fsr
|= (env
->fsr
& FSR_CEXC_MASK
) << 5;
860 void helper_clear_float_exceptions(void)
862 set_float_exception_flags(0, &env
->fp_status
);
865 float32
helper_fabss(float32 src
)
867 return float32_abs(src
);
870 #ifdef TARGET_SPARC64
871 void helper_fabsd(void)
873 DT0
= float64_abs(DT1
);
876 void helper_fabsq(void)
878 QT0
= float128_abs(QT1
);
882 float32
helper_fsqrts(float32 src
)
884 return float32_sqrt(src
, &env
->fp_status
);
887 void helper_fsqrtd(void)
889 DT0
= float64_sqrt(DT1
, &env
->fp_status
);
892 void helper_fsqrtq(void)
894 QT0
= float128_sqrt(QT1
, &env
->fp_status
);
897 #define GEN_FCMP(name, size, reg1, reg2, FS, E) \
898 void glue(helper_, name) (void) \
900 env->fsr &= FSR_FTT_NMASK; \
901 if (E && (glue(size, _is_any_nan)(reg1) || \
902 glue(size, _is_any_nan)(reg2)) && \
903 (env->fsr & FSR_NVM)) { \
904 env->fsr |= FSR_NVC; \
905 env->fsr |= FSR_FTT_IEEE_EXCP; \
906 raise_exception(TT_FP_EXCP); \
908 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
909 case float_relation_unordered: \
910 if ((env->fsr & FSR_NVM)) { \
911 env->fsr |= FSR_NVC; \
912 env->fsr |= FSR_FTT_IEEE_EXCP; \
913 raise_exception(TT_FP_EXCP); \
915 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
916 env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
917 env->fsr |= FSR_NVA; \
920 case float_relation_less: \
921 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
922 env->fsr |= FSR_FCC0 << FS; \
924 case float_relation_greater: \
925 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
926 env->fsr |= FSR_FCC1 << FS; \
929 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
933 #define GEN_FCMPS(name, size, FS, E) \
934 void glue(helper_, name)(float32 src1, float32 src2) \
936 env->fsr &= FSR_FTT_NMASK; \
937 if (E && (glue(size, _is_any_nan)(src1) || \
938 glue(size, _is_any_nan)(src2)) && \
939 (env->fsr & FSR_NVM)) { \
940 env->fsr |= FSR_NVC; \
941 env->fsr |= FSR_FTT_IEEE_EXCP; \
942 raise_exception(TT_FP_EXCP); \
944 switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
945 case float_relation_unordered: \
946 if ((env->fsr & FSR_NVM)) { \
947 env->fsr |= FSR_NVC; \
948 env->fsr |= FSR_FTT_IEEE_EXCP; \
949 raise_exception(TT_FP_EXCP); \
951 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
952 env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
953 env->fsr |= FSR_NVA; \
956 case float_relation_less: \
957 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
958 env->fsr |= FSR_FCC0 << FS; \
960 case float_relation_greater: \
961 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
962 env->fsr |= FSR_FCC1 << FS; \
965 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
970 GEN_FCMPS(fcmps
, float32
, 0, 0);
971 GEN_FCMP(fcmpd
, float64
, DT0
, DT1
, 0, 0);
973 GEN_FCMPS(fcmpes
, float32
, 0, 1);
974 GEN_FCMP(fcmped
, float64
, DT0
, DT1
, 0, 1);
976 GEN_FCMP(fcmpq
, float128
, QT0
, QT1
, 0, 0);
977 GEN_FCMP(fcmpeq
, float128
, QT0
, QT1
, 0, 1);
979 static uint32_t compute_all_flags(void)
981 return env
->psr
& PSR_ICC
;
984 static uint32_t compute_C_flags(void)
986 return env
->psr
& PSR_CARRY
;
989 static inline uint32_t get_NZ_icc(int32_t dst
)
995 } else if (dst
< 0) {
1001 #ifdef TARGET_SPARC64
1002 static uint32_t compute_all_flags_xcc(void)
1004 return env
->xcc
& PSR_ICC
;
1007 static uint32_t compute_C_flags_xcc(void)
1009 return env
->xcc
& PSR_CARRY
;
1012 static inline uint32_t get_NZ_xcc(target_long dst
)
1018 } else if (dst
< 0) {
1025 static inline uint32_t get_V_div_icc(target_ulong src2
)
1035 static uint32_t compute_all_div(void)
1039 ret
= get_NZ_icc(CC_DST
);
1040 ret
|= get_V_div_icc(CC_SRC2
);
1044 static uint32_t compute_C_div(void)
1049 static inline uint32_t get_C_add_icc(uint32_t dst
, uint32_t src1
)
1059 static inline uint32_t get_C_addx_icc(uint32_t dst
, uint32_t src1
,
1064 if (((src1
& src2
) | (~dst
& (src1
| src2
))) & (1U << 31)) {
1070 static inline uint32_t get_V_add_icc(uint32_t dst
, uint32_t src1
,
1075 if (((src1
^ src2
^ -1) & (src1
^ dst
)) & (1U << 31)) {
1081 #ifdef TARGET_SPARC64
1082 static inline uint32_t get_C_add_xcc(target_ulong dst
, target_ulong src1
)
1092 static inline uint32_t get_C_addx_xcc(target_ulong dst
, target_ulong src1
,
1097 if (((src1
& src2
) | (~dst
& (src1
| src2
))) & (1ULL << 63)) {
1103 static inline uint32_t get_V_add_xcc(target_ulong dst
, target_ulong src1
,
1108 if (((src1
^ src2
^ -1) & (src1
^ dst
)) & (1ULL << 63)) {
1114 static uint32_t compute_all_add_xcc(void)
1118 ret
= get_NZ_xcc(CC_DST
);
1119 ret
|= get_C_add_xcc(CC_DST
, CC_SRC
);
1120 ret
|= get_V_add_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1124 static uint32_t compute_C_add_xcc(void)
1126 return get_C_add_xcc(CC_DST
, CC_SRC
);
1130 static uint32_t compute_all_add(void)
1134 ret
= get_NZ_icc(CC_DST
);
1135 ret
|= get_C_add_icc(CC_DST
, CC_SRC
);
1136 ret
|= get_V_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1140 static uint32_t compute_C_add(void)
1142 return get_C_add_icc(CC_DST
, CC_SRC
);
1145 #ifdef TARGET_SPARC64
1146 static uint32_t compute_all_addx_xcc(void)
1150 ret
= get_NZ_xcc(CC_DST
);
1151 ret
|= get_C_addx_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1152 ret
|= get_V_add_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1156 static uint32_t compute_C_addx_xcc(void)
1160 ret
= get_C_addx_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1165 static uint32_t compute_all_addx(void)
1169 ret
= get_NZ_icc(CC_DST
);
1170 ret
|= get_C_addx_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1171 ret
|= get_V_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1175 static uint32_t compute_C_addx(void)
1179 ret
= get_C_addx_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1183 static inline uint32_t get_V_tag_icc(target_ulong src1
, target_ulong src2
)
1187 if ((src1
| src2
) & 0x3) {
1193 static uint32_t compute_all_tadd(void)
1197 ret
= get_NZ_icc(CC_DST
);
1198 ret
|= get_C_add_icc(CC_DST
, CC_SRC
);
1199 ret
|= get_V_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1200 ret
|= get_V_tag_icc(CC_SRC
, CC_SRC2
);
1204 static uint32_t compute_all_taddtv(void)
1208 ret
= get_NZ_icc(CC_DST
);
1209 ret
|= get_C_add_icc(CC_DST
, CC_SRC
);
1213 static inline uint32_t get_C_sub_icc(uint32_t src1
, uint32_t src2
)
1223 static inline uint32_t get_C_subx_icc(uint32_t dst
, uint32_t src1
,
1228 if (((~src1
& src2
) | (dst
& (~src1
| src2
))) & (1U << 31)) {
1234 static inline uint32_t get_V_sub_icc(uint32_t dst
, uint32_t src1
,
1239 if (((src1
^ src2
) & (src1
^ dst
)) & (1U << 31)) {
1246 #ifdef TARGET_SPARC64
1247 static inline uint32_t get_C_sub_xcc(target_ulong src1
, target_ulong src2
)
1257 static inline uint32_t get_C_subx_xcc(target_ulong dst
, target_ulong src1
,
1262 if (((~src1
& src2
) | (dst
& (~src1
| src2
))) & (1ULL << 63)) {
1268 static inline uint32_t get_V_sub_xcc(target_ulong dst
, target_ulong src1
,
1273 if (((src1
^ src2
) & (src1
^ dst
)) & (1ULL << 63)) {
1279 static uint32_t compute_all_sub_xcc(void)
1283 ret
= get_NZ_xcc(CC_DST
);
1284 ret
|= get_C_sub_xcc(CC_SRC
, CC_SRC2
);
1285 ret
|= get_V_sub_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1289 static uint32_t compute_C_sub_xcc(void)
1291 return get_C_sub_xcc(CC_SRC
, CC_SRC2
);
1295 static uint32_t compute_all_sub(void)
1299 ret
= get_NZ_icc(CC_DST
);
1300 ret
|= get_C_sub_icc(CC_SRC
, CC_SRC2
);
1301 ret
|= get_V_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1305 static uint32_t compute_C_sub(void)
1307 return get_C_sub_icc(CC_SRC
, CC_SRC2
);
1310 #ifdef TARGET_SPARC64
1311 static uint32_t compute_all_subx_xcc(void)
1315 ret
= get_NZ_xcc(CC_DST
);
1316 ret
|= get_C_subx_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1317 ret
|= get_V_sub_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1321 static uint32_t compute_C_subx_xcc(void)
1325 ret
= get_C_subx_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1330 static uint32_t compute_all_subx(void)
1334 ret
= get_NZ_icc(CC_DST
);
1335 ret
|= get_C_subx_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1336 ret
|= get_V_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1340 static uint32_t compute_C_subx(void)
1344 ret
= get_C_subx_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1348 static uint32_t compute_all_tsub(void)
1352 ret
= get_NZ_icc(CC_DST
);
1353 ret
|= get_C_sub_icc(CC_SRC
, CC_SRC2
);
1354 ret
|= get_V_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1355 ret
|= get_V_tag_icc(CC_SRC
, CC_SRC2
);
1359 static uint32_t compute_all_tsubtv(void)
1363 ret
= get_NZ_icc(CC_DST
);
1364 ret
|= get_C_sub_icc(CC_SRC
, CC_SRC2
);
1368 static uint32_t compute_all_logic(void)
1370 return get_NZ_icc(CC_DST
);
1373 static uint32_t compute_C_logic(void)
1378 #ifdef TARGET_SPARC64
1379 static uint32_t compute_all_logic_xcc(void)
1381 return get_NZ_xcc(CC_DST
);
1385 typedef struct CCTable
{
1386 uint32_t (*compute_all
)(void); /* return all the flags */
1387 uint32_t (*compute_c
)(void); /* return the C flag */
1390 static const CCTable icc_table
[CC_OP_NB
] = {
1391 /* CC_OP_DYNAMIC should never happen */
1392 [CC_OP_FLAGS
] = { compute_all_flags
, compute_C_flags
},
1393 [CC_OP_DIV
] = { compute_all_div
, compute_C_div
},
1394 [CC_OP_ADD
] = { compute_all_add
, compute_C_add
},
1395 [CC_OP_ADDX
] = { compute_all_addx
, compute_C_addx
},
1396 [CC_OP_TADD
] = { compute_all_tadd
, compute_C_add
},
1397 [CC_OP_TADDTV
] = { compute_all_taddtv
, compute_C_add
},
1398 [CC_OP_SUB
] = { compute_all_sub
, compute_C_sub
},
1399 [CC_OP_SUBX
] = { compute_all_subx
, compute_C_subx
},
1400 [CC_OP_TSUB
] = { compute_all_tsub
, compute_C_sub
},
1401 [CC_OP_TSUBTV
] = { compute_all_tsubtv
, compute_C_sub
},
1402 [CC_OP_LOGIC
] = { compute_all_logic
, compute_C_logic
},
1405 #ifdef TARGET_SPARC64
1406 static const CCTable xcc_table
[CC_OP_NB
] = {
1407 /* CC_OP_DYNAMIC should never happen */
1408 [CC_OP_FLAGS
] = { compute_all_flags_xcc
, compute_C_flags_xcc
},
1409 [CC_OP_DIV
] = { compute_all_logic_xcc
, compute_C_logic
},
1410 [CC_OP_ADD
] = { compute_all_add_xcc
, compute_C_add_xcc
},
1411 [CC_OP_ADDX
] = { compute_all_addx_xcc
, compute_C_addx_xcc
},
1412 [CC_OP_TADD
] = { compute_all_add_xcc
, compute_C_add_xcc
},
1413 [CC_OP_TADDTV
] = { compute_all_add_xcc
, compute_C_add_xcc
},
1414 [CC_OP_SUB
] = { compute_all_sub_xcc
, compute_C_sub_xcc
},
1415 [CC_OP_SUBX
] = { compute_all_subx_xcc
, compute_C_subx_xcc
},
1416 [CC_OP_TSUB
] = { compute_all_sub_xcc
, compute_C_sub_xcc
},
1417 [CC_OP_TSUBTV
] = { compute_all_sub_xcc
, compute_C_sub_xcc
},
1418 [CC_OP_LOGIC
] = { compute_all_logic_xcc
, compute_C_logic
},
1422 void helper_compute_psr(void)
1426 new_psr
= icc_table
[CC_OP
].compute_all();
1428 #ifdef TARGET_SPARC64
1429 new_psr
= xcc_table
[CC_OP
].compute_all();
1432 CC_OP
= CC_OP_FLAGS
;
1435 uint32_t helper_compute_C_icc(void)
1439 ret
= icc_table
[CC_OP
].compute_c() >> PSR_CARRY_SHIFT
;
1443 static inline void memcpy32(target_ulong
*dst
, const target_ulong
*src
)
1455 static void set_cwp(int new_cwp
)
1457 /* put the modified wrap registers at their proper location */
1458 if (env
->cwp
== env
->nwindows
- 1) {
1459 memcpy32(env
->regbase
, env
->regbase
+ env
->nwindows
* 16);
1463 /* put the wrap registers at their temporary location */
1464 if (new_cwp
== env
->nwindows
- 1) {
1465 memcpy32(env
->regbase
+ env
->nwindows
* 16, env
->regbase
);
1467 env
->regwptr
= env
->regbase
+ (new_cwp
* 16);
1470 void cpu_set_cwp(CPUState
*env1
, int new_cwp
)
1472 CPUState
*saved_env
;
1480 static target_ulong
get_psr(void)
1482 helper_compute_psr();
1484 #if !defined (TARGET_SPARC64)
1485 return env
->version
| (env
->psr
& PSR_ICC
) |
1486 (env
->psref
? PSR_EF
: 0) |
1487 (env
->psrpil
<< 8) |
1488 (env
->psrs
? PSR_S
: 0) |
1489 (env
->psrps
? PSR_PS
: 0) |
1490 (env
->psret
? PSR_ET
: 0) | env
->cwp
;
1492 return env
->psr
& PSR_ICC
;
1496 target_ulong
cpu_get_psr(CPUState
*env1
)
1498 CPUState
*saved_env
;
1508 static void put_psr(target_ulong val
)
1510 env
->psr
= val
& PSR_ICC
;
1511 #if !defined (TARGET_SPARC64)
1512 env
->psref
= (val
& PSR_EF
)? 1 : 0;
1513 env
->psrpil
= (val
& PSR_PIL
) >> 8;
1515 #if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
1516 cpu_check_irqs(env
);
1518 #if !defined (TARGET_SPARC64)
1519 env
->psrs
= (val
& PSR_S
)? 1 : 0;
1520 env
->psrps
= (val
& PSR_PS
)? 1 : 0;
1521 env
->psret
= (val
& PSR_ET
)? 1 : 0;
1522 set_cwp(val
& PSR_CWP
);
1524 env
->cc_op
= CC_OP_FLAGS
;
1527 void cpu_put_psr(CPUState
*env1
, target_ulong val
)
1529 CPUState
*saved_env
;
1537 static int cwp_inc(int cwp
)
1539 if (unlikely(cwp
>= env
->nwindows
)) {
1540 cwp
-= env
->nwindows
;
1545 int cpu_cwp_inc(CPUState
*env1
, int cwp
)
1547 CPUState
*saved_env
;
1557 static int cwp_dec(int cwp
)
1559 if (unlikely(cwp
< 0)) {
1560 cwp
+= env
->nwindows
;
1565 int cpu_cwp_dec(CPUState
*env1
, int cwp
)
1567 CPUState
*saved_env
;
1577 #ifdef TARGET_SPARC64
1578 GEN_FCMPS(fcmps_fcc1
, float32
, 22, 0);
1579 GEN_FCMP(fcmpd_fcc1
, float64
, DT0
, DT1
, 22, 0);
1580 GEN_FCMP(fcmpq_fcc1
, float128
, QT0
, QT1
, 22, 0);
1582 GEN_FCMPS(fcmps_fcc2
, float32
, 24, 0);
1583 GEN_FCMP(fcmpd_fcc2
, float64
, DT0
, DT1
, 24, 0);
1584 GEN_FCMP(fcmpq_fcc2
, float128
, QT0
, QT1
, 24, 0);
1586 GEN_FCMPS(fcmps_fcc3
, float32
, 26, 0);
1587 GEN_FCMP(fcmpd_fcc3
, float64
, DT0
, DT1
, 26, 0);
1588 GEN_FCMP(fcmpq_fcc3
, float128
, QT0
, QT1
, 26, 0);
1590 GEN_FCMPS(fcmpes_fcc1
, float32
, 22, 1);
1591 GEN_FCMP(fcmped_fcc1
, float64
, DT0
, DT1
, 22, 1);
1592 GEN_FCMP(fcmpeq_fcc1
, float128
, QT0
, QT1
, 22, 1);
1594 GEN_FCMPS(fcmpes_fcc2
, float32
, 24, 1);
1595 GEN_FCMP(fcmped_fcc2
, float64
, DT0
, DT1
, 24, 1);
1596 GEN_FCMP(fcmpeq_fcc2
, float128
, QT0
, QT1
, 24, 1);
1598 GEN_FCMPS(fcmpes_fcc3
, float32
, 26, 1);
1599 GEN_FCMP(fcmped_fcc3
, float64
, DT0
, DT1
, 26, 1);
1600 GEN_FCMP(fcmpeq_fcc3
, float128
, QT0
, QT1
, 26, 1);
1604 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
1606 static void dump_mxcc(CPUState
*env
)
1608 printf("mxccdata: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
1610 env
->mxccdata
[0], env
->mxccdata
[1],
1611 env
->mxccdata
[2], env
->mxccdata
[3]);
1612 printf("mxccregs: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
1614 " %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
1616 env
->mxccregs
[0], env
->mxccregs
[1],
1617 env
->mxccregs
[2], env
->mxccregs
[3],
1618 env
->mxccregs
[4], env
->mxccregs
[5],
1619 env
->mxccregs
[6], env
->mxccregs
[7]);
1623 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
1624 && defined(DEBUG_ASI)
1625 static void dump_asi(const char *txt
, target_ulong addr
, int asi
, int size
,
1631 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %02" PRIx64
"\n", txt
,
1632 addr
, asi
, r1
& 0xff);
1635 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %04" PRIx64
"\n", txt
,
1636 addr
, asi
, r1
& 0xffff);
1639 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %08" PRIx64
"\n", txt
,
1640 addr
, asi
, r1
& 0xffffffff);
1643 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %016" PRIx64
"\n", txt
,
1650 #ifndef TARGET_SPARC64
1651 #ifndef CONFIG_USER_ONLY
1654 /* Leon3 cache control */
1656 void leon3_cache_control_int(void)
1660 if (env
->cache_control
& CACHE_CTRL_IF
) {
1661 /* Instruction cache state */
1662 state
= env
->cache_control
& CACHE_STATE_MASK
;
1663 if (state
== CACHE_ENABLED
) {
1664 state
= CACHE_FROZEN
;
1665 DPRINTF_CACHE_CONTROL("Instruction cache: freeze\n");
1668 env
->cache_control
&= ~CACHE_STATE_MASK
;
1669 env
->cache_control
|= state
;
1672 if (env
->cache_control
& CACHE_CTRL_DF
) {
1673 /* Data cache state */
1674 state
= (env
->cache_control
>> 2) & CACHE_STATE_MASK
;
1675 if (state
== CACHE_ENABLED
) {
1676 state
= CACHE_FROZEN
;
1677 DPRINTF_CACHE_CONTROL("Data cache: freeze\n");
1680 env
->cache_control
&= ~(CACHE_STATE_MASK
<< 2);
1681 env
->cache_control
|= (state
<< 2);
1685 static void leon3_cache_control_st(target_ulong addr
, uint64_t val
, int size
)
1687 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64
", size:%d\n",
1691 DPRINTF_CACHE_CONTROL("32bits only\n");
1696 case 0x00: /* Cache control */
1698 /* These values must always be read as zeros */
1699 val
&= ~CACHE_CTRL_FD
;
1700 val
&= ~CACHE_CTRL_FI
;
1701 val
&= ~CACHE_CTRL_IB
;
1702 val
&= ~CACHE_CTRL_IP
;
1703 val
&= ~CACHE_CTRL_DP
;
1705 env
->cache_control
= val
;
1707 case 0x04: /* Instruction cache configuration */
1708 case 0x08: /* Data cache configuration */
1712 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr
);
1717 static uint64_t leon3_cache_control_ld(target_ulong addr
, int size
)
1722 DPRINTF_CACHE_CONTROL("32bits only\n");
1727 case 0x00: /* Cache control */
1728 ret
= env
->cache_control
;
1731 /* Configuration registers are read and only always keep those
1732 predefined values */
1734 case 0x04: /* Instruction cache configuration */
1737 case 0x08: /* Data cache configuration */
1741 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr
);
1744 DPRINTF_CACHE_CONTROL("st addr:%08x, ret:%" PRIx64
", size:%d\n",
1749 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
1752 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
1753 uint32_t last_addr
= addr
;
1756 helper_check_align(addr
, size
- 1);
1758 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
1760 case 0x00: /* Leon3 Cache Control */
1761 case 0x08: /* Leon3 Instruction Cache config */
1762 case 0x0C: /* Leon3 Date Cache config */
1763 ret
= leon3_cache_control_ld(addr
, size
);
1765 case 0x01c00a00: /* MXCC control register */
1767 ret
= env
->mxccregs
[3];
1769 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1772 case 0x01c00a04: /* MXCC control register */
1774 ret
= env
->mxccregs
[3];
1776 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1779 case 0x01c00c00: /* Module reset register */
1781 ret
= env
->mxccregs
[5];
1782 // should we do something here?
1784 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1787 case 0x01c00f00: /* MBus port address register */
1789 ret
= env
->mxccregs
[7];
1791 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1795 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
1799 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
1800 "addr = %08x -> ret = %" PRIx64
","
1801 "addr = %08x\n", asi
, size
, sign
, last_addr
, ret
, addr
);
1806 case 3: /* MMU probe */
1810 mmulev
= (addr
>> 8) & 15;
1814 ret
= mmu_probe(env
, addr
, mmulev
);
1815 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64
"\n",
1819 case 4: /* read MMU regs */
1821 int reg
= (addr
>> 8) & 0x1f;
1823 ret
= env
->mmuregs
[reg
];
1824 if (reg
== 3) /* Fault status cleared on read */
1825 env
->mmuregs
[3] = 0;
1826 else if (reg
== 0x13) /* Fault status read */
1827 ret
= env
->mmuregs
[3];
1828 else if (reg
== 0x14) /* Fault address read */
1829 ret
= env
->mmuregs
[4];
1830 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64
"\n", reg
, ret
);
1833 case 5: // Turbosparc ITLB Diagnostic
1834 case 6: // Turbosparc DTLB Diagnostic
1835 case 7: // Turbosparc IOTLB Diagnostic
1837 case 9: /* Supervisor code access */
1840 ret
= ldub_code(addr
);
1843 ret
= lduw_code(addr
);
1847 ret
= ldl_code(addr
);
1850 ret
= ldq_code(addr
);
1854 case 0xa: /* User data access */
1857 ret
= ldub_user(addr
);
1860 ret
= lduw_user(addr
);
1864 ret
= ldl_user(addr
);
1867 ret
= ldq_user(addr
);
1871 case 0xb: /* Supervisor data access */
1874 ret
= ldub_kernel(addr
);
1877 ret
= lduw_kernel(addr
);
1881 ret
= ldl_kernel(addr
);
1884 ret
= ldq_kernel(addr
);
1888 case 0xc: /* I-cache tag */
1889 case 0xd: /* I-cache data */
1890 case 0xe: /* D-cache tag */
1891 case 0xf: /* D-cache data */
1893 case 0x20: /* MMU passthrough */
1896 ret
= ldub_phys(addr
);
1899 ret
= lduw_phys(addr
);
1903 ret
= ldl_phys(addr
);
1906 ret
= ldq_phys(addr
);
1910 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1913 ret
= ldub_phys((target_phys_addr_t
)addr
1914 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1917 ret
= lduw_phys((target_phys_addr_t
)addr
1918 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1922 ret
= ldl_phys((target_phys_addr_t
)addr
1923 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1926 ret
= ldq_phys((target_phys_addr_t
)addr
1927 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1931 case 0x30: // Turbosparc secondary cache diagnostic
1932 case 0x31: // Turbosparc RAM snoop
1933 case 0x32: // Turbosparc page table descriptor diagnostic
1934 case 0x39: /* data cache diagnostic register */
1935 case 0x4c: /* SuperSPARC MMU Breakpoint Action register */
1938 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
1940 int reg
= (addr
>> 8) & 3;
1943 case 0: /* Breakpoint Value (Addr) */
1944 ret
= env
->mmubpregs
[reg
];
1946 case 1: /* Breakpoint Mask */
1947 ret
= env
->mmubpregs
[reg
];
1949 case 2: /* Breakpoint Control */
1950 ret
= env
->mmubpregs
[reg
];
1952 case 3: /* Breakpoint Status */
1953 ret
= env
->mmubpregs
[reg
];
1954 env
->mmubpregs
[reg
] = 0ULL;
1957 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64
"\n", reg
,
1961 case 8: /* User code access, XXX */
1963 do_unassigned_access(addr
, 0, 0, asi
, size
);
1973 ret
= (int16_t) ret
;
1976 ret
= (int32_t) ret
;
1983 dump_asi("read ", last_addr
, asi
, size
, ret
);
1988 void helper_st_asi(target_ulong addr
, uint64_t val
, int asi
, int size
)
1990 helper_check_align(addr
, size
- 1);
1992 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
1994 case 0x00: /* Leon3 Cache Control */
1995 case 0x08: /* Leon3 Instruction Cache config */
1996 case 0x0C: /* Leon3 Date Cache config */
1997 leon3_cache_control_st(addr
, val
, size
);
2000 case 0x01c00000: /* MXCC stream data register 0 */
2002 env
->mxccdata
[0] = val
;
2004 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
2007 case 0x01c00008: /* MXCC stream data register 1 */
2009 env
->mxccdata
[1] = val
;
2011 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
2014 case 0x01c00010: /* MXCC stream data register 2 */
2016 env
->mxccdata
[2] = val
;
2018 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
2021 case 0x01c00018: /* MXCC stream data register 3 */
2023 env
->mxccdata
[3] = val
;
2025 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
2028 case 0x01c00100: /* MXCC stream source */
2030 env
->mxccregs
[0] = val
;
2032 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
2034 env
->mxccdata
[0] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
2036 env
->mxccdata
[1] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
2038 env
->mxccdata
[2] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
2040 env
->mxccdata
[3] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
2043 case 0x01c00200: /* MXCC stream destination */
2045 env
->mxccregs
[1] = val
;
2047 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
2049 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 0,
2051 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 8,
2053 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 16,
2055 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 24,
2058 case 0x01c00a00: /* MXCC control register */
2060 env
->mxccregs
[3] = val
;
2062 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
2065 case 0x01c00a04: /* MXCC control register */
2067 env
->mxccregs
[3] = (env
->mxccregs
[3] & 0xffffffff00000000ULL
)
2070 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
2073 case 0x01c00e00: /* MXCC error register */
2074 // writing a 1 bit clears the error
2076 env
->mxccregs
[6] &= ~val
;
2078 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
2081 case 0x01c00f00: /* MBus port address register */
2083 env
->mxccregs
[7] = val
;
2085 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
2089 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
2093 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64
"\n",
2094 asi
, size
, addr
, val
);
2099 case 3: /* MMU flush */
2103 mmulev
= (addr
>> 8) & 15;
2104 DPRINTF_MMU("mmu flush level %d\n", mmulev
);
2106 case 0: // flush page
2107 tlb_flush_page(env
, addr
& 0xfffff000);
2109 case 1: // flush segment (256k)
2110 case 2: // flush region (16M)
2111 case 3: // flush context (4G)
2112 case 4: // flush entire
2119 dump_mmu(stdout
, fprintf
, env
);
2123 case 4: /* write MMU regs */
2125 int reg
= (addr
>> 8) & 0x1f;
2128 oldreg
= env
->mmuregs
[reg
];
2130 case 0: // Control Register
2131 env
->mmuregs
[reg
] = (env
->mmuregs
[reg
] & 0xff000000) |
2133 // Mappings generated during no-fault mode or MMU
2134 // disabled mode are invalid in normal mode
2135 if ((oldreg
& (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)) !=
2136 (env
->mmuregs
[reg
] & (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)))
2139 case 1: // Context Table Pointer Register
2140 env
->mmuregs
[reg
] = val
& env
->def
->mmu_ctpr_mask
;
2142 case 2: // Context Register
2143 env
->mmuregs
[reg
] = val
& env
->def
->mmu_cxr_mask
;
2144 if (oldreg
!= env
->mmuregs
[reg
]) {
2145 /* we flush when the MMU context changes because
2146 QEMU has no MMU context support */
2150 case 3: // Synchronous Fault Status Register with Clear
2151 case 4: // Synchronous Fault Address Register
2153 case 0x10: // TLB Replacement Control Register
2154 env
->mmuregs
[reg
] = val
& env
->def
->mmu_trcr_mask
;
2156 case 0x13: // Synchronous Fault Status Register with Read and Clear
2157 env
->mmuregs
[3] = val
& env
->def
->mmu_sfsr_mask
;
2159 case 0x14: // Synchronous Fault Address Register
2160 env
->mmuregs
[4] = val
;
2163 env
->mmuregs
[reg
] = val
;
2166 if (oldreg
!= env
->mmuregs
[reg
]) {
2167 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
2168 reg
, oldreg
, env
->mmuregs
[reg
]);
2171 dump_mmu(stdout
, fprintf
, env
);
2175 case 5: // Turbosparc ITLB Diagnostic
2176 case 6: // Turbosparc DTLB Diagnostic
2177 case 7: // Turbosparc IOTLB Diagnostic
2179 case 0xa: /* User data access */
2182 stb_user(addr
, val
);
2185 stw_user(addr
, val
);
2189 stl_user(addr
, val
);
2192 stq_user(addr
, val
);
2196 case 0xb: /* Supervisor data access */
2199 stb_kernel(addr
, val
);
2202 stw_kernel(addr
, val
);
2206 stl_kernel(addr
, val
);
2209 stq_kernel(addr
, val
);
2213 case 0xc: /* I-cache tag */
2214 case 0xd: /* I-cache data */
2215 case 0xe: /* D-cache tag */
2216 case 0xf: /* D-cache data */
2217 case 0x10: /* I/D-cache flush page */
2218 case 0x11: /* I/D-cache flush segment */
2219 case 0x12: /* I/D-cache flush region */
2220 case 0x13: /* I/D-cache flush context */
2221 case 0x14: /* I/D-cache flush user */
2223 case 0x17: /* Block copy, sta access */
2229 uint32_t src
= val
& ~3, dst
= addr
& ~3, temp
;
2231 for (i
= 0; i
< 32; i
+= 4, src
+= 4, dst
+= 4) {
2232 temp
= ldl_kernel(src
);
2233 stl_kernel(dst
, temp
);
2237 case 0x1f: /* Block fill, stda access */
2240 // fill 32 bytes with val
2242 uint32_t dst
= addr
& 7;
2244 for (i
= 0; i
< 32; i
+= 8, dst
+= 8)
2245 stq_kernel(dst
, val
);
2248 case 0x20: /* MMU passthrough */
2252 stb_phys(addr
, val
);
2255 stw_phys(addr
, val
);
2259 stl_phys(addr
, val
);
2262 stq_phys(addr
, val
);
2267 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
2271 stb_phys((target_phys_addr_t
)addr
2272 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
2275 stw_phys((target_phys_addr_t
)addr
2276 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
2280 stl_phys((target_phys_addr_t
)addr
2281 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
2284 stq_phys((target_phys_addr_t
)addr
2285 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
2290 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
2291 case 0x31: // store buffer data, Ross RT620 I-cache flush or
2292 // Turbosparc snoop RAM
2293 case 0x32: // store buffer control or Turbosparc page table
2294 // descriptor diagnostic
2295 case 0x36: /* I-cache flash clear */
2296 case 0x37: /* D-cache flash clear */
2297 case 0x4c: /* breakpoint action */
2299 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
2301 int reg
= (addr
>> 8) & 3;
2304 case 0: /* Breakpoint Value (Addr) */
2305 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
2307 case 1: /* Breakpoint Mask */
2308 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
2310 case 2: /* Breakpoint Control */
2311 env
->mmubpregs
[reg
] = (val
& 0x7fULL
);
2313 case 3: /* Breakpoint Status */
2314 env
->mmubpregs
[reg
] = (val
& 0xfULL
);
2317 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg
,
2321 case 8: /* User code access, XXX */
2322 case 9: /* Supervisor code access, XXX */
2324 do_unassigned_access(addr
, 1, 0, asi
, size
);
2328 dump_asi("write", addr
, asi
, size
, val
);
2332 #endif /* CONFIG_USER_ONLY */
2333 #else /* TARGET_SPARC64 */
2335 #ifdef CONFIG_USER_ONLY
2336 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
2339 #if defined(DEBUG_ASI)
2340 target_ulong last_addr
= addr
;
2344 raise_exception(TT_PRIV_ACT
);
2346 helper_check_align(addr
, size
- 1);
2347 addr
= asi_address_mask(env
, asi
, addr
);
2350 case 0x82: // Primary no-fault
2351 case 0x8a: // Primary no-fault LE
2352 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
2354 dump_asi("read ", last_addr
, asi
, size
, ret
);
2359 case 0x80: // Primary
2360 case 0x88: // Primary LE
2364 ret
= ldub_raw(addr
);
2367 ret
= lduw_raw(addr
);
2370 ret
= ldl_raw(addr
);
2374 ret
= ldq_raw(addr
);
2379 case 0x83: // Secondary no-fault
2380 case 0x8b: // Secondary no-fault LE
2381 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
2383 dump_asi("read ", last_addr
, asi
, size
, ret
);
2388 case 0x81: // Secondary
2389 case 0x89: // Secondary LE
2396 /* Convert from little endian */
2398 case 0x88: // Primary LE
2399 case 0x89: // Secondary LE
2400 case 0x8a: // Primary no-fault LE
2401 case 0x8b: // Secondary no-fault LE
2419 /* Convert to signed number */
2426 ret
= (int16_t) ret
;
2429 ret
= (int32_t) ret
;
2436 dump_asi("read ", last_addr
, asi
, size
, ret
);
2441 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
2444 dump_asi("write", addr
, asi
, size
, val
);
2447 raise_exception(TT_PRIV_ACT
);
2449 helper_check_align(addr
, size
- 1);
2450 addr
= asi_address_mask(env
, asi
, addr
);
2452 /* Convert to little endian */
2454 case 0x88: // Primary LE
2455 case 0x89: // Secondary LE
2474 case 0x80: // Primary
2475 case 0x88: // Primary LE
2494 case 0x81: // Secondary
2495 case 0x89: // Secondary LE
2499 case 0x82: // Primary no-fault, RO
2500 case 0x83: // Secondary no-fault, RO
2501 case 0x8a: // Primary no-fault LE, RO
2502 case 0x8b: // Secondary no-fault LE, RO
2504 do_unassigned_access(addr
, 1, 0, 1, size
);
2509 #else /* CONFIG_USER_ONLY */
2511 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
2514 #if defined(DEBUG_ASI)
2515 target_ulong last_addr
= addr
;
2520 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2521 || (cpu_has_hypervisor(env
)
2522 && asi
>= 0x30 && asi
< 0x80
2523 && !(env
->hpstate
& HS_PRIV
)))
2524 raise_exception(TT_PRIV_ACT
);
2526 helper_check_align(addr
, size
- 1);
2527 addr
= asi_address_mask(env
, asi
, addr
);
2530 case 0x82: // Primary no-fault
2531 case 0x8a: // Primary no-fault LE
2532 case 0x83: // Secondary no-fault
2533 case 0x8b: // Secondary no-fault LE
2535 /* secondary space access has lowest asi bit equal to 1 */
2536 int access_mmu_idx
= ( asi
& 1 ) ? MMU_KERNEL_IDX
2537 : MMU_KERNEL_SECONDARY_IDX
;
2539 if (cpu_get_phys_page_nofault(env
, addr
, access_mmu_idx
) == -1ULL) {
2541 dump_asi("read ", last_addr
, asi
, size
, ret
);
2547 case 0x10: // As if user primary
2548 case 0x11: // As if user secondary
2549 case 0x18: // As if user primary LE
2550 case 0x19: // As if user secondary LE
2551 case 0x80: // Primary
2552 case 0x81: // Secondary
2553 case 0x88: // Primary LE
2554 case 0x89: // Secondary LE
2555 case 0xe2: // UA2007 Primary block init
2556 case 0xe3: // UA2007 Secondary block init
2557 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
2558 if (cpu_hypervisor_mode(env
)) {
2561 ret
= ldub_hypv(addr
);
2564 ret
= lduw_hypv(addr
);
2567 ret
= ldl_hypv(addr
);
2571 ret
= ldq_hypv(addr
);
2575 /* secondary space access has lowest asi bit equal to 1 */
2579 ret
= ldub_kernel_secondary(addr
);
2582 ret
= lduw_kernel_secondary(addr
);
2585 ret
= ldl_kernel_secondary(addr
);
2589 ret
= ldq_kernel_secondary(addr
);
2595 ret
= ldub_kernel(addr
);
2598 ret
= lduw_kernel(addr
);
2601 ret
= ldl_kernel(addr
);
2605 ret
= ldq_kernel(addr
);
2611 /* secondary space access has lowest asi bit equal to 1 */
2615 ret
= ldub_user_secondary(addr
);
2618 ret
= lduw_user_secondary(addr
);
2621 ret
= ldl_user_secondary(addr
);
2625 ret
= ldq_user_secondary(addr
);
2631 ret
= ldub_user(addr
);
2634 ret
= lduw_user(addr
);
2637 ret
= ldl_user(addr
);
2641 ret
= ldq_user(addr
);
2647 case 0x14: // Bypass
2648 case 0x15: // Bypass, non-cacheable
2649 case 0x1c: // Bypass LE
2650 case 0x1d: // Bypass, non-cacheable LE
2654 ret
= ldub_phys(addr
);
2657 ret
= lduw_phys(addr
);
2660 ret
= ldl_phys(addr
);
2664 ret
= ldq_phys(addr
);
2669 case 0x24: // Nucleus quad LDD 128 bit atomic
2670 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2671 // Only ldda allowed
2672 raise_exception(TT_ILL_INSN
);
2674 case 0x04: // Nucleus
2675 case 0x0c: // Nucleus Little Endian (LE)
2679 ret
= ldub_nucleus(addr
);
2682 ret
= lduw_nucleus(addr
);
2685 ret
= ldl_nucleus(addr
);
2689 ret
= ldq_nucleus(addr
);
2694 case 0x4a: // UPA config
2700 case 0x50: // I-MMU regs
2702 int reg
= (addr
>> 3) & 0xf;
2705 // I-TSB Tag Target register
2706 ret
= ultrasparc_tag_target(env
->immu
.tag_access
);
2708 ret
= env
->immuregs
[reg
];
2713 case 0x51: // I-MMU 8k TSB pointer
2715 // env->immuregs[5] holds I-MMU TSB register value
2716 // env->immuregs[6] holds I-MMU Tag Access register value
2717 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
2721 case 0x52: // I-MMU 64k TSB pointer
2723 // env->immuregs[5] holds I-MMU TSB register value
2724 // env->immuregs[6] holds I-MMU Tag Access register value
2725 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
2729 case 0x55: // I-MMU data access
2731 int reg
= (addr
>> 3) & 0x3f;
2733 ret
= env
->itlb
[reg
].tte
;
2736 case 0x56: // I-MMU tag read
2738 int reg
= (addr
>> 3) & 0x3f;
2740 ret
= env
->itlb
[reg
].tag
;
2743 case 0x58: // D-MMU regs
2745 int reg
= (addr
>> 3) & 0xf;
2748 // D-TSB Tag Target register
2749 ret
= ultrasparc_tag_target(env
->dmmu
.tag_access
);
2751 ret
= env
->dmmuregs
[reg
];
2755 case 0x59: // D-MMU 8k TSB pointer
2757 // env->dmmuregs[5] holds D-MMU TSB register value
2758 // env->dmmuregs[6] holds D-MMU Tag Access register value
2759 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
2763 case 0x5a: // D-MMU 64k TSB pointer
2765 // env->dmmuregs[5] holds D-MMU TSB register value
2766 // env->dmmuregs[6] holds D-MMU Tag Access register value
2767 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
2771 case 0x5d: // D-MMU data access
2773 int reg
= (addr
>> 3) & 0x3f;
2775 ret
= env
->dtlb
[reg
].tte
;
2778 case 0x5e: // D-MMU tag read
2780 int reg
= (addr
>> 3) & 0x3f;
2782 ret
= env
->dtlb
[reg
].tag
;
2785 case 0x46: // D-cache data
2786 case 0x47: // D-cache tag access
2787 case 0x4b: // E-cache error enable
2788 case 0x4c: // E-cache asynchronous fault status
2789 case 0x4d: // E-cache asynchronous fault address
2790 case 0x4e: // E-cache tag data
2791 case 0x66: // I-cache instruction access
2792 case 0x67: // I-cache tag access
2793 case 0x6e: // I-cache predecode
2794 case 0x6f: // I-cache LRU etc.
2795 case 0x76: // E-cache tag
2796 case 0x7e: // E-cache tag
2798 case 0x5b: // D-MMU data pointer
2799 case 0x48: // Interrupt dispatch, RO
2800 case 0x49: // Interrupt data receive
2801 case 0x7f: // Incoming interrupt vector, RO
2804 case 0x54: // I-MMU data in, WO
2805 case 0x57: // I-MMU demap, WO
2806 case 0x5c: // D-MMU data in, WO
2807 case 0x5f: // D-MMU demap, WO
2808 case 0x77: // Interrupt vector, WO
2810 do_unassigned_access(addr
, 0, 0, 1, size
);
2815 /* Convert from little endian */
2817 case 0x0c: // Nucleus Little Endian (LE)
2818 case 0x18: // As if user primary LE
2819 case 0x19: // As if user secondary LE
2820 case 0x1c: // Bypass LE
2821 case 0x1d: // Bypass, non-cacheable LE
2822 case 0x88: // Primary LE
2823 case 0x89: // Secondary LE
2824 case 0x8a: // Primary no-fault LE
2825 case 0x8b: // Secondary no-fault LE
2843 /* Convert to signed number */
2850 ret
= (int16_t) ret
;
2853 ret
= (int32_t) ret
;
2860 dump_asi("read ", last_addr
, asi
, size
, ret
);
2865 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
2868 dump_asi("write", addr
, asi
, size
, val
);
2873 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2874 || (cpu_has_hypervisor(env
)
2875 && asi
>= 0x30 && asi
< 0x80
2876 && !(env
->hpstate
& HS_PRIV
)))
2877 raise_exception(TT_PRIV_ACT
);
2879 helper_check_align(addr
, size
- 1);
2880 addr
= asi_address_mask(env
, asi
, addr
);
2882 /* Convert to little endian */
2884 case 0x0c: // Nucleus Little Endian (LE)
2885 case 0x18: // As if user primary LE
2886 case 0x19: // As if user secondary LE
2887 case 0x1c: // Bypass LE
2888 case 0x1d: // Bypass, non-cacheable LE
2889 case 0x88: // Primary LE
2890 case 0x89: // Secondary LE
2909 case 0x10: // As if user primary
2910 case 0x11: // As if user secondary
2911 case 0x18: // As if user primary LE
2912 case 0x19: // As if user secondary LE
2913 case 0x80: // Primary
2914 case 0x81: // Secondary
2915 case 0x88: // Primary LE
2916 case 0x89: // Secondary LE
2917 case 0xe2: // UA2007 Primary block init
2918 case 0xe3: // UA2007 Secondary block init
2919 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
2920 if (cpu_hypervisor_mode(env
)) {
2923 stb_hypv(addr
, val
);
2926 stw_hypv(addr
, val
);
2929 stl_hypv(addr
, val
);
2933 stq_hypv(addr
, val
);
2937 /* secondary space access has lowest asi bit equal to 1 */
2941 stb_kernel_secondary(addr
, val
);
2944 stw_kernel_secondary(addr
, val
);
2947 stl_kernel_secondary(addr
, val
);
2951 stq_kernel_secondary(addr
, val
);
2957 stb_kernel(addr
, val
);
2960 stw_kernel(addr
, val
);
2963 stl_kernel(addr
, val
);
2967 stq_kernel(addr
, val
);
2973 /* secondary space access has lowest asi bit equal to 1 */
2977 stb_user_secondary(addr
, val
);
2980 stw_user_secondary(addr
, val
);
2983 stl_user_secondary(addr
, val
);
2987 stq_user_secondary(addr
, val
);
2993 stb_user(addr
, val
);
2996 stw_user(addr
, val
);
2999 stl_user(addr
, val
);
3003 stq_user(addr
, val
);
3009 case 0x14: // Bypass
3010 case 0x15: // Bypass, non-cacheable
3011 case 0x1c: // Bypass LE
3012 case 0x1d: // Bypass, non-cacheable LE
3016 stb_phys(addr
, val
);
3019 stw_phys(addr
, val
);
3022 stl_phys(addr
, val
);
3026 stq_phys(addr
, val
);
3031 case 0x24: // Nucleus quad LDD 128 bit atomic
3032 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
3033 // Only ldda allowed
3034 raise_exception(TT_ILL_INSN
);
3036 case 0x04: // Nucleus
3037 case 0x0c: // Nucleus Little Endian (LE)
3041 stb_nucleus(addr
, val
);
3044 stw_nucleus(addr
, val
);
3047 stl_nucleus(addr
, val
);
3051 stq_nucleus(addr
, val
);
3057 case 0x4a: // UPA config
3065 env
->lsu
= val
& (DMMU_E
| IMMU_E
);
3066 // Mappings generated during D/I MMU disabled mode are
3067 // invalid in normal mode
3068 if (oldreg
!= env
->lsu
) {
3069 DPRINTF_MMU("LSU change: 0x%" PRIx64
" -> 0x%" PRIx64
"\n",
3072 dump_mmu(stdout
, fprintf
, env1
);
3078 case 0x50: // I-MMU regs
3080 int reg
= (addr
>> 3) & 0xf;
3083 oldreg
= env
->immuregs
[reg
];
3087 case 1: // Not in I-MMU
3092 val
= 0; // Clear SFSR
3093 env
->immu
.sfsr
= val
;
3097 case 5: // TSB access
3098 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64
" -> 0x%016"
3099 PRIx64
"\n", env
->immu
.tsb
, val
);
3100 env
->immu
.tsb
= val
;
3102 case 6: // Tag access
3103 env
->immu
.tag_access
= val
;
3112 if (oldreg
!= env
->immuregs
[reg
]) {
3113 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
3114 PRIx64
"\n", reg
, oldreg
, env
->immuregs
[reg
]);
3117 dump_mmu(stdout
, fprintf
, env
);
3121 case 0x54: // I-MMU data in
3122 replace_tlb_1bit_lru(env
->itlb
, env
->immu
.tag_access
, val
, "immu", env
);
3124 case 0x55: // I-MMU data access
3128 unsigned int i
= (addr
>> 3) & 0x3f;
3130 replace_tlb_entry(&env
->itlb
[i
], env
->immu
.tag_access
, val
, env
);
3133 DPRINTF_MMU("immu data access replaced entry [%i]\n", i
);
3134 dump_mmu(stdout
, fprintf
, env
);
3138 case 0x57: // I-MMU demap
3139 demap_tlb(env
->itlb
, addr
, "immu", env
);
3141 case 0x58: // D-MMU regs
3143 int reg
= (addr
>> 3) & 0xf;
3146 oldreg
= env
->dmmuregs
[reg
];
3152 if ((val
& 1) == 0) {
3153 val
= 0; // Clear SFSR, Fault address
3156 env
->dmmu
.sfsr
= val
;
3158 case 1: // Primary context
3159 env
->dmmu
.mmu_primary_context
= val
;
3160 /* can be optimized to only flush MMU_USER_IDX
3161 and MMU_KERNEL_IDX entries */
3164 case 2: // Secondary context
3165 env
->dmmu
.mmu_secondary_context
= val
;
3166 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
3167 and MMU_KERNEL_SECONDARY_IDX entries */
3170 case 5: // TSB access
3171 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64
" -> 0x%016"
3172 PRIx64
"\n", env
->dmmu
.tsb
, val
);
3173 env
->dmmu
.tsb
= val
;
3175 case 6: // Tag access
3176 env
->dmmu
.tag_access
= val
;
3178 case 7: // Virtual Watchpoint
3179 case 8: // Physical Watchpoint
3181 env
->dmmuregs
[reg
] = val
;
3185 if (oldreg
!= env
->dmmuregs
[reg
]) {
3186 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
3187 PRIx64
"\n", reg
, oldreg
, env
->dmmuregs
[reg
]);
3190 dump_mmu(stdout
, fprintf
, env
);
3194 case 0x5c: // D-MMU data in
3195 replace_tlb_1bit_lru(env
->dtlb
, env
->dmmu
.tag_access
, val
, "dmmu", env
);
3197 case 0x5d: // D-MMU data access
3199 unsigned int i
= (addr
>> 3) & 0x3f;
3201 replace_tlb_entry(&env
->dtlb
[i
], env
->dmmu
.tag_access
, val
, env
);
3204 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i
);
3205 dump_mmu(stdout
, fprintf
, env
);
3209 case 0x5f: // D-MMU demap
3210 demap_tlb(env
->dtlb
, addr
, "dmmu", env
);
3212 case 0x49: // Interrupt data receive
3215 case 0x46: // D-cache data
3216 case 0x47: // D-cache tag access
3217 case 0x4b: // E-cache error enable
3218 case 0x4c: // E-cache asynchronous fault status
3219 case 0x4d: // E-cache asynchronous fault address
3220 case 0x4e: // E-cache tag data
3221 case 0x66: // I-cache instruction access
3222 case 0x67: // I-cache tag access
3223 case 0x6e: // I-cache predecode
3224 case 0x6f: // I-cache LRU etc.
3225 case 0x76: // E-cache tag
3226 case 0x7e: // E-cache tag
3228 case 0x51: // I-MMU 8k TSB pointer, RO
3229 case 0x52: // I-MMU 64k TSB pointer, RO
3230 case 0x56: // I-MMU tag read, RO
3231 case 0x59: // D-MMU 8k TSB pointer, RO
3232 case 0x5a: // D-MMU 64k TSB pointer, RO
3233 case 0x5b: // D-MMU data pointer, RO
3234 case 0x5e: // D-MMU tag read, RO
3235 case 0x48: // Interrupt dispatch, RO
3236 case 0x7f: // Incoming interrupt vector, RO
3237 case 0x82: // Primary no-fault, RO
3238 case 0x83: // Secondary no-fault, RO
3239 case 0x8a: // Primary no-fault LE, RO
3240 case 0x8b: // Secondary no-fault LE, RO
3242 do_unassigned_access(addr
, 1, 0, 1, size
);
3246 #endif /* CONFIG_USER_ONLY */
3248 void helper_ldda_asi(target_ulong addr
, int asi
, int rd
)
3250 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
3251 || (cpu_has_hypervisor(env
)
3252 && asi
>= 0x30 && asi
< 0x80
3253 && !(env
->hpstate
& HS_PRIV
)))
3254 raise_exception(TT_PRIV_ACT
);
3256 addr
= asi_address_mask(env
, asi
, addr
);
3259 #if !defined(CONFIG_USER_ONLY)
3260 case 0x24: // Nucleus quad LDD 128 bit atomic
3261 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
3262 helper_check_align(addr
, 0xf);
3264 env
->gregs
[1] = ldq_nucleus(addr
+ 8);
3266 bswap64s(&env
->gregs
[1]);
3267 } else if (rd
< 8) {
3268 env
->gregs
[rd
] = ldq_nucleus(addr
);
3269 env
->gregs
[rd
+ 1] = ldq_nucleus(addr
+ 8);
3271 bswap64s(&env
->gregs
[rd
]);
3272 bswap64s(&env
->gregs
[rd
+ 1]);
3275 env
->regwptr
[rd
] = ldq_nucleus(addr
);
3276 env
->regwptr
[rd
+ 1] = ldq_nucleus(addr
+ 8);
3278 bswap64s(&env
->regwptr
[rd
]);
3279 bswap64s(&env
->regwptr
[rd
+ 1]);
3285 helper_check_align(addr
, 0x3);
3287 env
->gregs
[1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
3289 env
->gregs
[rd
] = helper_ld_asi(addr
, asi
, 4, 0);
3290 env
->gregs
[rd
+ 1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
3292 env
->regwptr
[rd
] = helper_ld_asi(addr
, asi
, 4, 0);
3293 env
->regwptr
[rd
+ 1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
3299 void helper_ldf_asi(target_ulong addr
, int asi
, int size
, int rd
)
3304 helper_check_align(addr
, 3);
3305 addr
= asi_address_mask(env
, asi
, addr
);
3308 case 0xf0: // Block load primary
3309 case 0xf1: // Block load secondary
3310 case 0xf8: // Block load primary LE
3311 case 0xf9: // Block load secondary LE
3313 raise_exception(TT_ILL_INSN
);
3316 helper_check_align(addr
, 0x3f);
3317 for (i
= 0; i
< 16; i
++) {
3318 *(uint32_t *)&env
->fpr
[rd
++] = helper_ld_asi(addr
, asi
& 0x8f, 4,
3324 case 0x70: // Block load primary, user privilege
3325 case 0x71: // Block load secondary, user privilege
3327 raise_exception(TT_ILL_INSN
);
3330 helper_check_align(addr
, 0x3f);
3331 for (i
= 0; i
< 16; i
++) {
3332 *(uint32_t *)&env
->fpr
[rd
++] = helper_ld_asi(addr
, asi
& 0x1f, 4,
3342 val
= helper_ld_asi(addr
, asi
, size
, 0);
3346 *((uint32_t *)&env
->fpr
[rd
]) = val
;
3349 *((int64_t *)&DT0
) = val
;
3357 void helper_stf_asi(target_ulong addr
, int asi
, int size
, int rd
)
3360 target_ulong val
= 0;
3362 helper_check_align(addr
, 3);
3363 addr
= asi_address_mask(env
, asi
, addr
);
3366 case 0xe0: // UA2007 Block commit store primary (cache flush)
3367 case 0xe1: // UA2007 Block commit store secondary (cache flush)
3368 case 0xf0: // Block store primary
3369 case 0xf1: // Block store secondary
3370 case 0xf8: // Block store primary LE
3371 case 0xf9: // Block store secondary LE
3373 raise_exception(TT_ILL_INSN
);
3376 helper_check_align(addr
, 0x3f);
3377 for (i
= 0; i
< 16; i
++) {
3378 val
= *(uint32_t *)&env
->fpr
[rd
++];
3379 helper_st_asi(addr
, val
, asi
& 0x8f, 4);
3384 case 0x70: // Block store primary, user privilege
3385 case 0x71: // Block store secondary, user privilege
3387 raise_exception(TT_ILL_INSN
);
3390 helper_check_align(addr
, 0x3f);
3391 for (i
= 0; i
< 16; i
++) {
3392 val
= *(uint32_t *)&env
->fpr
[rd
++];
3393 helper_st_asi(addr
, val
, asi
& 0x1f, 4);
3405 val
= *((uint32_t *)&env
->fpr
[rd
]);
3408 val
= *((int64_t *)&DT0
);
3414 helper_st_asi(addr
, val
, asi
, size
);
3417 target_ulong
helper_cas_asi(target_ulong addr
, target_ulong val1
,
3418 target_ulong val2
, uint32_t asi
)
3422 val2
&= 0xffffffffUL
;
3423 ret
= helper_ld_asi(addr
, asi
, 4, 0);
3424 ret
&= 0xffffffffUL
;
3426 helper_st_asi(addr
, val1
& 0xffffffffUL
, asi
, 4);
3430 target_ulong
helper_casx_asi(target_ulong addr
, target_ulong val1
,
3431 target_ulong val2
, uint32_t asi
)
3435 ret
= helper_ld_asi(addr
, asi
, 8, 0);
3437 helper_st_asi(addr
, val1
, asi
, 8);
3440 #endif /* TARGET_SPARC64 */
3442 #ifndef TARGET_SPARC64
3443 void helper_rett(void)
3447 if (env
->psret
== 1)
3448 raise_exception(TT_ILL_INSN
);
3451 cwp
= cwp_inc(env
->cwp
+ 1) ;
3452 if (env
->wim
& (1 << cwp
)) {
3453 raise_exception(TT_WIN_UNF
);
3456 env
->psrs
= env
->psrps
;
3460 static target_ulong
helper_udiv_common(target_ulong a
, target_ulong b
, int cc
)
3466 x0
= (a
& 0xffffffff) | ((int64_t) (env
->y
) << 32);
3467 x1
= (b
& 0xffffffff);
3470 raise_exception(TT_DIV_ZERO
);
3474 if (x0
> 0xffffffff) {
3481 env
->cc_src2
= overflow
;
3482 env
->cc_op
= CC_OP_DIV
;
3487 target_ulong
helper_udiv(target_ulong a
, target_ulong b
)
3489 return helper_udiv_common(a
, b
, 0);
3492 target_ulong
helper_udiv_cc(target_ulong a
, target_ulong b
)
3494 return helper_udiv_common(a
, b
, 1);
3497 static target_ulong
helper_sdiv_common(target_ulong a
, target_ulong b
, int cc
)
3503 x0
= (a
& 0xffffffff) | ((int64_t) (env
->y
) << 32);
3504 x1
= (b
& 0xffffffff);
3507 raise_exception(TT_DIV_ZERO
);
3511 if ((int32_t) x0
!= x0
) {
3512 x0
= x0
< 0 ? 0x80000000: 0x7fffffff;
3518 env
->cc_src2
= overflow
;
3519 env
->cc_op
= CC_OP_DIV
;
3524 target_ulong
helper_sdiv(target_ulong a
, target_ulong b
)
3526 return helper_sdiv_common(a
, b
, 0);
3529 target_ulong
helper_sdiv_cc(target_ulong a
, target_ulong b
)
3531 return helper_sdiv_common(a
, b
, 1);
3534 void helper_stdf(target_ulong addr
, int mem_idx
)
3536 helper_check_align(addr
, 7);
3537 #if !defined(CONFIG_USER_ONLY)
3540 stfq_user(addr
, DT0
);
3542 case MMU_KERNEL_IDX
:
3543 stfq_kernel(addr
, DT0
);
3545 #ifdef TARGET_SPARC64
3547 stfq_hypv(addr
, DT0
);
3551 DPRINTF_MMU("helper_stdf: need to check MMU idx %d\n", mem_idx
);
3555 stfq_raw(address_mask(env
, addr
), DT0
);
3559 void helper_lddf(target_ulong addr
, int mem_idx
)
3561 helper_check_align(addr
, 7);
3562 #if !defined(CONFIG_USER_ONLY)
3565 DT0
= ldfq_user(addr
);
3567 case MMU_KERNEL_IDX
:
3568 DT0
= ldfq_kernel(addr
);
3570 #ifdef TARGET_SPARC64
3572 DT0
= ldfq_hypv(addr
);
3576 DPRINTF_MMU("helper_lddf: need to check MMU idx %d\n", mem_idx
);
3580 DT0
= ldfq_raw(address_mask(env
, addr
));
3584 void helper_ldqf(target_ulong addr
, int mem_idx
)
3586 // XXX add 128 bit load
3589 helper_check_align(addr
, 7);
3590 #if !defined(CONFIG_USER_ONLY)
3593 u
.ll
.upper
= ldq_user(addr
);
3594 u
.ll
.lower
= ldq_user(addr
+ 8);
3597 case MMU_KERNEL_IDX
:
3598 u
.ll
.upper
= ldq_kernel(addr
);
3599 u
.ll
.lower
= ldq_kernel(addr
+ 8);
3602 #ifdef TARGET_SPARC64
3604 u
.ll
.upper
= ldq_hypv(addr
);
3605 u
.ll
.lower
= ldq_hypv(addr
+ 8);
3610 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx
);
3614 u
.ll
.upper
= ldq_raw(address_mask(env
, addr
));
3615 u
.ll
.lower
= ldq_raw(address_mask(env
, addr
+ 8));
3620 void helper_stqf(target_ulong addr
, int mem_idx
)
3622 // XXX add 128 bit store
3625 helper_check_align(addr
, 7);
3626 #if !defined(CONFIG_USER_ONLY)
3630 stq_user(addr
, u
.ll
.upper
);
3631 stq_user(addr
+ 8, u
.ll
.lower
);
3633 case MMU_KERNEL_IDX
:
3635 stq_kernel(addr
, u
.ll
.upper
);
3636 stq_kernel(addr
+ 8, u
.ll
.lower
);
3638 #ifdef TARGET_SPARC64
3641 stq_hypv(addr
, u
.ll
.upper
);
3642 stq_hypv(addr
+ 8, u
.ll
.lower
);
3646 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx
);
3651 stq_raw(address_mask(env
, addr
), u
.ll
.upper
);
3652 stq_raw(address_mask(env
, addr
+ 8), u
.ll
.lower
);
3656 static inline void set_fsr(void)
3660 switch (env
->fsr
& FSR_RD_MASK
) {
3661 case FSR_RD_NEAREST
:
3662 rnd_mode
= float_round_nearest_even
;
3666 rnd_mode
= float_round_to_zero
;
3669 rnd_mode
= float_round_up
;
3672 rnd_mode
= float_round_down
;
3675 set_float_rounding_mode(rnd_mode
, &env
->fp_status
);
3678 void helper_ldfsr(uint32_t new_fsr
)
3680 env
->fsr
= (new_fsr
& FSR_LDFSR_MASK
) | (env
->fsr
& FSR_LDFSR_OLDMASK
);
3684 #ifdef TARGET_SPARC64
3685 void helper_ldxfsr(uint64_t new_fsr
)
3687 env
->fsr
= (new_fsr
& FSR_LDXFSR_MASK
) | (env
->fsr
& FSR_LDXFSR_OLDMASK
);
3692 void helper_debug(void)
3694 env
->exception_index
= EXCP_DEBUG
;
3698 #ifndef TARGET_SPARC64
3699 /* XXX: use another pointer for %iN registers to avoid slow wrapping
3701 void helper_save(void)
3705 cwp
= cwp_dec(env
->cwp
- 1);
3706 if (env
->wim
& (1 << cwp
)) {
3707 raise_exception(TT_WIN_OVF
);
3712 void helper_restore(void)
3716 cwp
= cwp_inc(env
->cwp
+ 1);
3717 if (env
->wim
& (1 << cwp
)) {
3718 raise_exception(TT_WIN_UNF
);
3723 void helper_wrpsr(target_ulong new_psr
)
3725 if ((new_psr
& PSR_CWP
) >= env
->nwindows
) {
3726 raise_exception(TT_ILL_INSN
);
3728 cpu_put_psr(env
, new_psr
);
3732 target_ulong
helper_rdpsr(void)
3738 /* XXX: use another pointer for %iN registers to avoid slow wrapping
3740 void helper_save(void)
3744 cwp
= cwp_dec(env
->cwp
- 1);
3745 if (env
->cansave
== 0) {
3746 raise_exception(TT_SPILL
| (env
->otherwin
!= 0 ?
3747 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
3748 ((env
->wstate
& 0x7) << 2)));
3750 if (env
->cleanwin
- env
->canrestore
== 0) {
3751 // XXX Clean windows without trap
3752 raise_exception(TT_CLRWIN
);
3761 void helper_restore(void)
3765 cwp
= cwp_inc(env
->cwp
+ 1);
3766 if (env
->canrestore
== 0) {
3767 raise_exception(TT_FILL
| (env
->otherwin
!= 0 ?
3768 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
3769 ((env
->wstate
& 0x7) << 2)));
3777 void helper_flushw(void)
3779 if (env
->cansave
!= env
->nwindows
- 2) {
3780 raise_exception(TT_SPILL
| (env
->otherwin
!= 0 ?
3781 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
3782 ((env
->wstate
& 0x7) << 2)));
3786 void helper_saved(void)
3789 if (env
->otherwin
== 0)
3795 void helper_restored(void)
3798 if (env
->cleanwin
< env
->nwindows
- 1)
3800 if (env
->otherwin
== 0)
3806 static target_ulong
get_ccr(void)
3812 return ((env
->xcc
>> 20) << 4) | ((psr
& PSR_ICC
) >> 20);
3815 target_ulong
cpu_get_ccr(CPUState
*env1
)
3817 CPUState
*saved_env
;
3827 static void put_ccr(target_ulong val
)
3829 target_ulong tmp
= val
;
3831 env
->xcc
= (tmp
>> 4) << 20;
3832 env
->psr
= (tmp
& 0xf) << 20;
3833 CC_OP
= CC_OP_FLAGS
;
3836 void cpu_put_ccr(CPUState
*env1
, target_ulong val
)
3838 CPUState
*saved_env
;
3846 static target_ulong
get_cwp64(void)
3848 return env
->nwindows
- 1 - env
->cwp
;
3851 target_ulong
cpu_get_cwp64(CPUState
*env1
)
3853 CPUState
*saved_env
;
3863 static void put_cwp64(int cwp
)
3865 if (unlikely(cwp
>= env
->nwindows
|| cwp
< 0)) {
3866 cwp
%= env
->nwindows
;
3868 set_cwp(env
->nwindows
- 1 - cwp
);
3871 void cpu_put_cwp64(CPUState
*env1
, int cwp
)
3873 CPUState
*saved_env
;
3881 target_ulong
helper_rdccr(void)
3886 void helper_wrccr(target_ulong new_ccr
)
3891 // CWP handling is reversed in V9, but we still use the V8 register
3893 target_ulong
helper_rdcwp(void)
3898 void helper_wrcwp(target_ulong new_cwp
)
3903 // This function uses non-native bit order
3904 #define GET_FIELD(X, FROM, TO) \
3905 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
3907 // This function uses the order in the manuals, i.e. bit 0 is 2^0
3908 #define GET_FIELD_SP(X, FROM, TO) \
3909 GET_FIELD(X, 63 - (TO), 63 - (FROM))
3911 target_ulong
helper_array8(target_ulong pixel_addr
, target_ulong cubesize
)
3913 return (GET_FIELD_SP(pixel_addr
, 60, 63) << (17 + 2 * cubesize
)) |
3914 (GET_FIELD_SP(pixel_addr
, 39, 39 + cubesize
- 1) << (17 + cubesize
)) |
3915 (GET_FIELD_SP(pixel_addr
, 17 + cubesize
- 1, 17) << 17) |
3916 (GET_FIELD_SP(pixel_addr
, 56, 59) << 13) |
3917 (GET_FIELD_SP(pixel_addr
, 35, 38) << 9) |
3918 (GET_FIELD_SP(pixel_addr
, 13, 16) << 5) |
3919 (((pixel_addr
>> 55) & 1) << 4) |
3920 (GET_FIELD_SP(pixel_addr
, 33, 34) << 2) |
3921 GET_FIELD_SP(pixel_addr
, 11, 12);
3924 target_ulong
helper_alignaddr(target_ulong addr
, target_ulong offset
)
3928 tmp
= addr
+ offset
;
3930 env
->gsr
|= tmp
& 7ULL;
3934 target_ulong
helper_popc(target_ulong val
)
3936 return ctpop64(val
);
3939 static inline uint64_t *get_gregset(uint32_t pstate
)
3943 DPRINTF_PSTATE("ERROR in get_gregset: active pstate bits=%x%s%s%s\n",
3945 (pstate
& PS_IG
) ? " IG" : "",
3946 (pstate
& PS_MG
) ? " MG" : "",
3947 (pstate
& PS_AG
) ? " AG" : "");
3948 /* pass through to normal set of global registers */
3960 static inline void change_pstate(uint32_t new_pstate
)
3962 uint32_t pstate_regs
, new_pstate_regs
;
3963 uint64_t *src
, *dst
;
3965 if (env
->def
->features
& CPU_FEATURE_GL
) {
3966 // PS_AG is not implemented in this case
3967 new_pstate
&= ~PS_AG
;
3970 pstate_regs
= env
->pstate
& 0xc01;
3971 new_pstate_regs
= new_pstate
& 0xc01;
3973 if (new_pstate_regs
!= pstate_regs
) {
3974 DPRINTF_PSTATE("change_pstate: switching regs old=%x new=%x\n",
3975 pstate_regs
, new_pstate_regs
);
3976 // Switch global register bank
3977 src
= get_gregset(new_pstate_regs
);
3978 dst
= get_gregset(pstate_regs
);
3979 memcpy32(dst
, env
->gregs
);
3980 memcpy32(env
->gregs
, src
);
3983 DPRINTF_PSTATE("change_pstate: regs new=%x (unchanged)\n",
3986 env
->pstate
= new_pstate
;
3989 void helper_wrpstate(target_ulong new_state
)
3991 change_pstate(new_state
& 0xf3f);
3993 #if !defined(CONFIG_USER_ONLY)
3994 if (cpu_interrupts_enabled(env
)) {
3995 cpu_check_irqs(env
);
4000 void helper_wrpil(target_ulong new_pil
)
4002 #if !defined(CONFIG_USER_ONLY)
4003 DPRINTF_PSTATE("helper_wrpil old=%x new=%x\n",
4004 env
->psrpil
, (uint32_t)new_pil
);
4006 env
->psrpil
= new_pil
;
4008 if (cpu_interrupts_enabled(env
)) {
4009 cpu_check_irqs(env
);
4014 void helper_done(void)
4016 trap_state
* tsptr
= cpu_tsptr(env
);
4018 env
->pc
= tsptr
->tnpc
;
4019 env
->npc
= tsptr
->tnpc
+ 4;
4020 put_ccr(tsptr
->tstate
>> 32);
4021 env
->asi
= (tsptr
->tstate
>> 24) & 0xff;
4022 change_pstate((tsptr
->tstate
>> 8) & 0xf3f);
4023 put_cwp64(tsptr
->tstate
& 0xff);
4026 DPRINTF_PSTATE("... helper_done tl=%d\n", env
->tl
);
4028 #if !defined(CONFIG_USER_ONLY)
4029 if (cpu_interrupts_enabled(env
)) {
4030 cpu_check_irqs(env
);
4035 void helper_retry(void)
4037 trap_state
* tsptr
= cpu_tsptr(env
);
4039 env
->pc
= tsptr
->tpc
;
4040 env
->npc
= tsptr
->tnpc
;
4041 put_ccr(tsptr
->tstate
>> 32);
4042 env
->asi
= (tsptr
->tstate
>> 24) & 0xff;
4043 change_pstate((tsptr
->tstate
>> 8) & 0xf3f);
4044 put_cwp64(tsptr
->tstate
& 0xff);
4047 DPRINTF_PSTATE("... helper_retry tl=%d\n", env
->tl
);
4049 #if !defined(CONFIG_USER_ONLY)
4050 if (cpu_interrupts_enabled(env
)) {
4051 cpu_check_irqs(env
);
4056 static void do_modify_softint(const char* operation
, uint32_t value
)
4058 if (env
->softint
!= value
) {
4059 env
->softint
= value
;
4060 DPRINTF_PSTATE(": %s new %08x\n", operation
, env
->softint
);
4061 #if !defined(CONFIG_USER_ONLY)
4062 if (cpu_interrupts_enabled(env
)) {
4063 cpu_check_irqs(env
);
4069 void helper_set_softint(uint64_t value
)
4071 do_modify_softint("helper_set_softint", env
->softint
| (uint32_t)value
);
4074 void helper_clear_softint(uint64_t value
)
4076 do_modify_softint("helper_clear_softint", env
->softint
& (uint32_t)~value
);
4079 void helper_write_softint(uint64_t value
)
4081 do_modify_softint("helper_write_softint", (uint32_t)value
);
4085 void helper_flush(target_ulong addr
)
4088 tb_invalidate_page_range(addr
, addr
+ 8);
4091 #ifdef TARGET_SPARC64
4093 static const char * const excp_names
[0x80] = {
4094 [TT_TFAULT
] = "Instruction Access Fault",
4095 [TT_TMISS
] = "Instruction Access MMU Miss",
4096 [TT_CODE_ACCESS
] = "Instruction Access Error",
4097 [TT_ILL_INSN
] = "Illegal Instruction",
4098 [TT_PRIV_INSN
] = "Privileged Instruction",
4099 [TT_NFPU_INSN
] = "FPU Disabled",
4100 [TT_FP_EXCP
] = "FPU Exception",
4101 [TT_TOVF
] = "Tag Overflow",
4102 [TT_CLRWIN
] = "Clean Windows",
4103 [TT_DIV_ZERO
] = "Division By Zero",
4104 [TT_DFAULT
] = "Data Access Fault",
4105 [TT_DMISS
] = "Data Access MMU Miss",
4106 [TT_DATA_ACCESS
] = "Data Access Error",
4107 [TT_DPROT
] = "Data Protection Error",
4108 [TT_UNALIGNED
] = "Unaligned Memory Access",
4109 [TT_PRIV_ACT
] = "Privileged Action",
4110 [TT_EXTINT
| 0x1] = "External Interrupt 1",
4111 [TT_EXTINT
| 0x2] = "External Interrupt 2",
4112 [TT_EXTINT
| 0x3] = "External Interrupt 3",
4113 [TT_EXTINT
| 0x4] = "External Interrupt 4",
4114 [TT_EXTINT
| 0x5] = "External Interrupt 5",
4115 [TT_EXTINT
| 0x6] = "External Interrupt 6",
4116 [TT_EXTINT
| 0x7] = "External Interrupt 7",
4117 [TT_EXTINT
| 0x8] = "External Interrupt 8",
4118 [TT_EXTINT
| 0x9] = "External Interrupt 9",
4119 [TT_EXTINT
| 0xa] = "External Interrupt 10",
4120 [TT_EXTINT
| 0xb] = "External Interrupt 11",
4121 [TT_EXTINT
| 0xc] = "External Interrupt 12",
4122 [TT_EXTINT
| 0xd] = "External Interrupt 13",
4123 [TT_EXTINT
| 0xe] = "External Interrupt 14",
4124 [TT_EXTINT
| 0xf] = "External Interrupt 15",
4128 trap_state
* cpu_tsptr(CPUState
* env
)
4130 return &env
->ts
[env
->tl
& MAXTL_MASK
];
4133 void do_interrupt(CPUState
*env
)
4135 int intno
= env
->exception_index
;
4139 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
4143 if (intno
< 0 || intno
>= 0x180)
4145 else if (intno
>= 0x100)
4146 name
= "Trap Instruction";
4147 else if (intno
>= 0xc0)
4148 name
= "Window Fill";
4149 else if (intno
>= 0x80)
4150 name
= "Window Spill";
4152 name
= excp_names
[intno
];
4157 qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64
" npc=%016" PRIx64
4158 " SP=%016" PRIx64
"\n",
4161 env
->npc
, env
->regwptr
[6]);
4162 log_cpu_state(env
, 0);
4169 ptr
= (uint8_t *)env
->pc
;
4170 for(i
= 0; i
< 16; i
++) {
4171 qemu_log(" %02x", ldub(ptr
+ i
));
4179 #if !defined(CONFIG_USER_ONLY)
4180 if (env
->tl
>= env
->maxtl
) {
4181 cpu_abort(env
, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
4182 " Error state", env
->exception_index
, env
->tl
, env
->maxtl
);
4186 if (env
->tl
< env
->maxtl
- 1) {
4189 env
->pstate
|= PS_RED
;
4190 if (env
->tl
< env
->maxtl
)
4193 tsptr
= cpu_tsptr(env
);
4195 tsptr
->tstate
= (get_ccr() << 32) |
4196 ((env
->asi
& 0xff) << 24) | ((env
->pstate
& 0xf3f) << 8) |
4198 tsptr
->tpc
= env
->pc
;
4199 tsptr
->tnpc
= env
->npc
;
4204 change_pstate(PS_PEF
| PS_PRIV
| PS_IG
);
4208 case TT_TMISS
... TT_TMISS
+ 3:
4209 case TT_DMISS
... TT_DMISS
+ 3:
4210 case TT_DPROT
... TT_DPROT
+ 3:
4211 change_pstate(PS_PEF
| PS_PRIV
| PS_MG
);
4214 change_pstate(PS_PEF
| PS_PRIV
| PS_AG
);
4218 if (intno
== TT_CLRWIN
) {
4219 set_cwp(cwp_dec(env
->cwp
- 1));
4220 } else if ((intno
& 0x1c0) == TT_SPILL
) {
4221 set_cwp(cwp_dec(env
->cwp
- env
->cansave
- 2));
4222 } else if ((intno
& 0x1c0) == TT_FILL
) {
4223 set_cwp(cwp_inc(env
->cwp
+ 1));
4225 env
->tbr
&= ~0x7fffULL
;
4226 env
->tbr
|= ((env
->tl
> 1) ? 1 << 14 : 0) | (intno
<< 5);
4228 env
->npc
= env
->pc
+ 4;
4229 env
->exception_index
= -1;
4233 static const char * const excp_names
[0x80] = {
4234 [TT_TFAULT
] = "Instruction Access Fault",
4235 [TT_ILL_INSN
] = "Illegal Instruction",
4236 [TT_PRIV_INSN
] = "Privileged Instruction",
4237 [TT_NFPU_INSN
] = "FPU Disabled",
4238 [TT_WIN_OVF
] = "Window Overflow",
4239 [TT_WIN_UNF
] = "Window Underflow",
4240 [TT_UNALIGNED
] = "Unaligned Memory Access",
4241 [TT_FP_EXCP
] = "FPU Exception",
4242 [TT_DFAULT
] = "Data Access Fault",
4243 [TT_TOVF
] = "Tag Overflow",
4244 [TT_EXTINT
| 0x1] = "External Interrupt 1",
4245 [TT_EXTINT
| 0x2] = "External Interrupt 2",
4246 [TT_EXTINT
| 0x3] = "External Interrupt 3",
4247 [TT_EXTINT
| 0x4] = "External Interrupt 4",
4248 [TT_EXTINT
| 0x5] = "External Interrupt 5",
4249 [TT_EXTINT
| 0x6] = "External Interrupt 6",
4250 [TT_EXTINT
| 0x7] = "External Interrupt 7",
4251 [TT_EXTINT
| 0x8] = "External Interrupt 8",
4252 [TT_EXTINT
| 0x9] = "External Interrupt 9",
4253 [TT_EXTINT
| 0xa] = "External Interrupt 10",
4254 [TT_EXTINT
| 0xb] = "External Interrupt 11",
4255 [TT_EXTINT
| 0xc] = "External Interrupt 12",
4256 [TT_EXTINT
| 0xd] = "External Interrupt 13",
4257 [TT_EXTINT
| 0xe] = "External Interrupt 14",
4258 [TT_EXTINT
| 0xf] = "External Interrupt 15",
4259 [TT_TOVF
] = "Tag Overflow",
4260 [TT_CODE_ACCESS
] = "Instruction Access Error",
4261 [TT_DATA_ACCESS
] = "Data Access Error",
4262 [TT_DIV_ZERO
] = "Division By Zero",
4263 [TT_NCP_INSN
] = "Coprocessor Disabled",
4267 void do_interrupt(CPUState
*env
)
4269 int cwp
, intno
= env
->exception_index
;
4272 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
4276 if (intno
< 0 || intno
>= 0x100)
4278 else if (intno
>= 0x80)
4279 name
= "Trap Instruction";
4281 name
= excp_names
[intno
];
4286 qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
4289 env
->npc
, env
->regwptr
[6]);
4290 log_cpu_state(env
, 0);
4297 ptr
= (uint8_t *)env
->pc
;
4298 for(i
= 0; i
< 16; i
++) {
4299 qemu_log(" %02x", ldub(ptr
+ i
));
4307 #if !defined(CONFIG_USER_ONLY)
4308 if (env
->psret
== 0) {
4309 cpu_abort(env
, "Trap 0x%02x while interrupts disabled, Error state",
4310 env
->exception_index
);
4315 cwp
= cwp_dec(env
->cwp
- 1);
4317 env
->regwptr
[9] = env
->pc
;
4318 env
->regwptr
[10] = env
->npc
;
4319 env
->psrps
= env
->psrs
;
4321 env
->tbr
= (env
->tbr
& TBR_BASE_MASK
) | (intno
<< 4);
4323 env
->npc
= env
->pc
+ 4;
4324 env
->exception_index
= -1;
4326 #if !defined(CONFIG_USER_ONLY)
4327 /* IRQ acknowledgment */
4328 if ((intno
& ~15) == TT_EXTINT
&& env
->qemu_irq_ack
!= NULL
) {
4329 env
->qemu_irq_ack(env
->irq_manager
, intno
);
4335 #if !defined(CONFIG_USER_ONLY)
4337 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
4340 #define MMUSUFFIX _mmu
4341 #define ALIGNED_ONLY
4344 #include "softmmu_template.h"
4347 #include "softmmu_template.h"
4350 #include "softmmu_template.h"
4353 #include "softmmu_template.h"
4355 /* XXX: make it generic ? */
4356 static void cpu_restore_state2(void *retaddr
)
4358 TranslationBlock
*tb
;
4362 /* now we have a real cpu fault */
4363 pc
= (unsigned long)retaddr
;
4364 tb
= tb_find_pc(pc
);
4366 /* the PC is inside the translated code. It means that we have
4367 a virtual CPU fault */
4368 cpu_restore_state(tb
, env
, pc
, (void *)(long)env
->cond
);
4373 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
4376 #ifdef DEBUG_UNALIGNED
4377 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
4378 "\n", addr
, env
->pc
);
4380 cpu_restore_state2(retaddr
);
4381 raise_exception(TT_UNALIGNED
);
4384 /* try to fill the TLB and return an exception if error. If retaddr is
4385 NULL, it means that the function was called in C code (i.e. not
4386 from generated code or from helper.c) */
4387 /* XXX: fix it to restore all registers */
4388 void tlb_fill(target_ulong addr
, int is_write
, int mmu_idx
, void *retaddr
)
4391 CPUState
*saved_env
;
4393 /* XXX: hack to restore env in all cases, even if not called from
4396 env
= cpu_single_env
;
4398 ret
= cpu_sparc_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
, 1);
4400 cpu_restore_state2(retaddr
);
4406 #endif /* !CONFIG_USER_ONLY */
4408 #ifndef TARGET_SPARC64
4409 #if !defined(CONFIG_USER_ONLY)
4410 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
4411 int is_asi
, int size
)
4413 CPUState
*saved_env
;
4416 /* XXX: hack to restore env in all cases, even if not called from
4419 env
= cpu_single_env
;
4420 #ifdef DEBUG_UNASSIGNED
4422 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
4423 " asi 0x%02x from " TARGET_FMT_lx
"\n",
4424 is_exec
? "exec" : is_write
? "write" : "read", size
,
4425 size
== 1 ? "" : "s", addr
, is_asi
, env
->pc
);
4427 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
4428 " from " TARGET_FMT_lx
"\n",
4429 is_exec
? "exec" : is_write
? "write" : "read", size
,
4430 size
== 1 ? "" : "s", addr
, env
->pc
);
4432 /* Don't overwrite translation and access faults */
4433 fault_type
= (env
->mmuregs
[3] & 0x1c) >> 2;
4434 if ((fault_type
> 4) || (fault_type
== 0)) {
4435 env
->mmuregs
[3] = 0; /* Fault status register */
4437 env
->mmuregs
[3] |= 1 << 16;
4439 env
->mmuregs
[3] |= 1 << 5;
4441 env
->mmuregs
[3] |= 1 << 6;
4443 env
->mmuregs
[3] |= 1 << 7;
4444 env
->mmuregs
[3] |= (5 << 2) | 2;
4445 /* SuperSPARC will never place instruction fault addresses in the FAR */
4447 env
->mmuregs
[4] = addr
; /* Fault address register */
4450 /* overflow (same type fault was not read before another fault) */
4451 if (fault_type
== ((env
->mmuregs
[3] & 0x1c)) >> 2) {
4452 env
->mmuregs
[3] |= 1;
4455 if ((env
->mmuregs
[0] & MMU_E
) && !(env
->mmuregs
[0] & MMU_NF
)) {
4457 raise_exception(TT_CODE_ACCESS
);
4459 raise_exception(TT_DATA_ACCESS
);
4462 /* flush neverland mappings created during no-fault mode,
4463 so the sequential MMU faults report proper fault types */
4464 if (env
->mmuregs
[0] & MMU_NF
) {
4472 #if defined(CONFIG_USER_ONLY)
4473 static void do_unassigned_access(target_ulong addr
, int is_write
, int is_exec
,
4474 int is_asi
, int size
)
4476 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
4477 int is_asi
, int size
)
4480 CPUState
*saved_env
;
4482 /* XXX: hack to restore env in all cases, even if not called from
4485 env
= cpu_single_env
;
4487 #ifdef DEBUG_UNASSIGNED
4488 printf("Unassigned mem access to " TARGET_FMT_plx
" from " TARGET_FMT_lx
4489 "\n", addr
, env
->pc
);
4493 raise_exception(TT_CODE_ACCESS
);
4495 raise_exception(TT_DATA_ACCESS
);
4502 #ifdef TARGET_SPARC64
4503 void helper_tick_set_count(void *opaque
, uint64_t count
)
4505 #if !defined(CONFIG_USER_ONLY)
4506 cpu_tick_set_count(opaque
, count
);
4510 uint64_t helper_tick_get_count(void *opaque
)
4512 #if !defined(CONFIG_USER_ONLY)
4513 return cpu_tick_get_count(opaque
);
4519 void helper_tick_set_limit(void *opaque
, uint64_t limit
)
4521 #if !defined(CONFIG_USER_ONLY)
4522 cpu_tick_set_limit(opaque
, limit
);